Thank you!
This information helps a lot !
On Fri, May 17, 2019 at 2:13 PM Gabe Black wrote:
> Hi Abhishek. You would probably want accesses to the MISCREG_* to go find
> the cache and ask it what value to reply with instead of the other way
> around. The system doesn't necessarily have caches or a particular number
> or topology of caches, so you'll likely need to set up some custom plumbing
> so the register code and the cache code can find each other in your setup.
>
> Gabe
>
> On Thu, May 16, 2019, 10:47 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Has anyone used Model Specific register in caches?
>> That is, to set single bit value in any of the MSR from caches?
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Wed, May 15, 2019 at 2:54 PM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hello Everyone and Gabe,
>>>
>>> I am having difficulty in finding a way to implment a new register in
>>> X86 ISA which is set one when an eviction occurs in dCache.
>>>
>>> Does anyone know which files, I should look into or any suggestions on
>>> how to achieve this implementation?
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
>>>
>>
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