[gem5-users] X86 CLFLUSH Flush Cache Line Instruction
Hello, I am aware that the above instruction has been implemented in the latest build of gem5, but wanted to know if we can make changes in Gem5 to only allow such instructions to run only in secure processes and with secure kernel privileges and not allowed to run in user application mode. Can we implement such changes in gem5, any ideas/suggestions for implementing it would be welcome.. Thanks in advance Bala ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction
Hey, You can do that, just go to the decoder code and make the secure flag high The code should be located at src/arch/x86/isa/ On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K wrote: > Hello, > > I am aware that the above instruction has been implemented in the latest > build of gem5, but wanted to know if we can make changes in Gem5 to only > allow such instructions to run only in secure processes and with secure > kernel privileges and not allowed to run in user application mode. > > Can we implement such changes in gem5, any ideas/suggestions for > implementing it would be welcome.. > > Thanks in advance > > Bala > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction
Abhishek, Thanks for the info, will try out the same. Bala On Mon, Nov 25, 2019 at 10:12 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hey, > You can do that, just go to the decoder code and make the secure flag high > > The code should be located at src/arch/x86/isa/ > > On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K > wrote: > >> Hello, >> >> I am aware that the above instruction has been implemented in the latest >> build of gem5, but wanted to know if we can make changes in Gem5 to only >> allow such instructions to run only in secure processes and with secure >> kernel privileges and not allowed to run in user application mode. >> >> Can we implement such changes in gem5, any ideas/suggestions for >> implementing it would be welcome.. >> >> Thanks in advance >> >> Bala >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction
Abhishek, In a similar query on secure bit/flag, Jason Lowe-Power had mentioned that the same (secure bit) is used only for ARM ISA in GEM5 and not for X86 ISA.. Am I missing something here? Bala On Mon, Nov 25, 2019 at 10:12 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hey, > You can do that, just go to the decoder code and make the secure flag high > > The code should be located at src/arch/x86/isa/ > > On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K > wrote: > >> Hello, >> >> I am aware that the above instruction has been implemented in the latest >> build of gem5, but wanted to know if we can make changes in Gem5 to only >> allow such instructions to run only in secure processes and with secure >> kernel privileges and not allowed to run in user application mode. >> >> Can we implement such changes in gem5, any ideas/suggestions for >> implementing it would be welcome.. >> >> Thanks in advance >> >> Bala >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction
Hi , I do not know about the secure bit implementation, if you want to implement something similar, what I would do is to follow what ARM does and try to replicate it in x86 On Wed, Nov 27, 2019 at 8:49 AM Muralidharan K wrote: > Abhishek, > > In a similar query on secure bit/flag, Jason Lowe-Power had mentioned that > the same (secure bit) is used only for ARM ISA in GEM5 and not for X86 > ISA.. Am I missing something here? > > Bala > > On Mon, Nov 25, 2019 at 10:12 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hey, >> You can do that, just go to the decoder code and make the secure flag >> high >> >> The code should be located at src/arch/x86/isa/ >> >> On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K < >> kmconsultant...@gmail.com> wrote: >> >>> Hello, >>> >>> I am aware that the above instruction has been implemented in the latest >>> build of gem5, but wanted to know if we can make changes in Gem5 to only >>> allow such instructions to run only in secure processes and with secure >>> kernel privileges and not allowed to run in user application mode. >>> >>> Can we implement such changes in gem5, any ideas/suggestions for >>> implementing it would be welcome.. >>> >>> Thanks in advance >>> >>> Bala >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
