Re: [gem5-users] (no subject)

[Nazish Shabbir]

Thank you so much. I'll try this.

On Sun, May 12, 2019 at 10:22 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Nazish,
>
> If you are using classic memory, edit src/mem/cache/base.cc file’s
> recvTimingReq function.
> You can access the old data through blk->data and the new data by
> pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
> mistake in writing correct name of the function).
>
> On Sun, May 12, 2019 at 2:52 AM Nazish Shabbir 
> wrote:
>
>>  Hello! I am relatively new to gem5 and trying to implement an encoding
>> scheme in it but not exactly sure what the best approach to implementing
>> this would be.
>>
>> The way i would like this to work is when there is a write access to the
>> last level cache, we need to read the old data in the last level cache.
>> Then we compare the new cache line with the old cache line to calculate the
>> HTs and STs.
>>
>> Where would you recommend i look to start implementing this? Which place
>> i need to start modifying?
>>
>> Thanks!
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Your logic sounds correct to me for single core.

For multi core, the last level cache is shared, and you can get block from
other core’s L1 dcache.
So you need to think through about what behavior you are expecting from
your design and make changes or keep things same.

On Mon, May 13, 2019 at 12:02 AM Muhammad Avais 
wrote:

> Dear Abhishek,
>
>  Many thanks for your reply. I will set the flag in response packet
> for L2 hit. This flag will be default reset, therefore, I think I will not
> need main memory flag in this case.
>  Please, let me know if you feel a problem in this logic.
>  For multicore simulation, what should be the difference?
>
> Many thanks for your response,
> Best regards,
> Avais
>
> On Sat, May 11, 2019 at 8:15 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> What you do, is create flags in src/mem/packet.hh for various cache
>> levels.
>> Whenever you hit in L2, you can set the L2flag in response pkt.
>> And if it is misses in L2, set main memory flag in response pkt, as you
>> are sure you will get data from main memory.
>> Here we are assuming it’s a single core simulation.
>>
>> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>
>>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
>>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
>>> cache)?
>>>
>>> Many thanks,
>>> Best Regards,
>>> Avais
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Re: [gem5-users] (no subject)

[Muhammad Avais]

Dear Abhishek,

 Many thanks for your reply. I will set the flag in response packet for
L2 hit. This flag will be default reset, therefore, I think I will not need
main memory flag in this case.
 Please, let me know if you feel a problem in this logic.
 For multicore simulation, what should be the difference?

Many thanks for your response,
Best regards,
Avais

On Sat, May 11, 2019 at 8:15 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> What you do, is create flags in src/mem/packet.hh for various cache levels.
> Whenever you hit in L2, you can set the L2flag in response pkt.
> And if it is misses in L2, set main memory flag in response pkt, as you
> are sure you will get data from main memory.
> Here we are assuming it’s a single core simulation.
>
> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>
>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
>> cache)?
>>
>> Many thanks,
>> Best Regards,
>> Avais
>> ___
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hello Nazish,

If you are using classic memory, edit src/mem/cache/base.cc file’s
recvTimingReq function.
You can access the old data through blk->data and the new data by
pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
mistake in writing correct name of the function).

On Sun, May 12, 2019 at 2:52 AM Nazish Shabbir 
wrote:

>  Hello! I am relatively new to gem5 and trying to implement an encoding
> scheme in it but not exactly sure what the best approach to implementing
> this would be.
>
> The way i would like this to work is when there is a write access to the
> last level cache, we need to read the old data in the last level cache.
> Then we compare the new cache line with the old cache line to calculate the
> HTs and STs.
>
> Where would you recommend i look to start implementing this? Which place
> i need to start modifying?
>
> Thanks!
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Re: [gem5-users] (no subject)

[Abhishek Singh]

What you do, is create flags in src/mem/packet.hh for various cache levels.
Whenever you hit in L2, you can set the L2flag in response pkt.
And if it is misses in L2, set main memory flag in response pkt, as you are
sure you will get data from main memory.
Here we are assuming it’s a single core simulation.

On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
wrote:

> Dear All,
>
> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
> cache)?
>
> Many thanks,
> Best Regards,
> Avais
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,

One way is to use the function "name()" in src/mem/cache/base.cc and
src/mem/cache/cache.cc file to implement cache specific function.
For e.g.,
for implementing things specifically  for dcache u can just write if
(name() == "system.cpu.dcache"){ }


Best regards,

Abhishek


On Fri, May 10, 2019 at 5:23 AM Muhammad Avais 
wrote:

>Dear All,
>
>   I have one question. For blocks loaded in the L1 cache, how can I
> distinguish that it was loaded into the L1 cache from L2 cache or main
> memory?
>
> Many thanks,
> Best regards,
> Avais
>
>
> On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Muhammad,
>>
>>
>> If you want on L2 hit, the block is invalidated from L2 cache and filled
>> in Dcache and the rest behavior same as you explained in the diagram, you
>> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
>> You may need to take care of "clean victim" from dcache which is not a
>> difficult modification.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>>> make it non-exclusive cache?
>>>
>>>   The non-exclusive cache is shown in Fig. below.
>>> [image: image.png]
>>>  Can anyone guide me?
>>>
>>> Many thanks,
>>> best regards,
>>> Avais
>>>
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>>
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Re: [gem5-users] (no subject)

[Muhammad Avais]

   Dear All,

  I have one question. For blocks loaded in the L1 cache, how can I
distinguish that it was loaded into the L1 cache from L2 cache or main
memory?

Many thanks,
Best regards,
Avais


On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Muhammad,
>
>
> If you want on L2 hit, the block is invalidated from L2 cache and filled
> in Dcache and the rest behavior same as you explained in the diagram, you
> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
> You may need to take care of "clean victim" from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>> make it non-exclusive cache?
>>
>>   The non-exclusive cache is shown in Fig. below.
>> [image: image.png]
>>  Can anyone guide me?
>>
>> Many thanks,
>> best regards,
>> Avais
>>
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Re: [gem5-users] (no subject)

[Muhammad Avais]

Dear Abhishek,

  Many thanks for the useful response, I will try to modify clean
victim eviction from "dcache".

Many thanks,
Best regards,
Avais

On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Muhammad,
>
>
> If you want on L2 hit, the block is invalidated from L2 cache and filled
> in Dcache and the rest behavior same as you explained in the diagram, you
> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
> You may need to take care of "clean victim" from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
> wrote:
>
>> Dear All,
>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>> make it non-exclusive cache?
>>
>>   The non-exclusive cache is shown in Fig. below.
>> [image: image.png]
>>  Can anyone guide me?
>>
>> Many thanks,
>> best regards,
>> Avais
>>
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,


If you want on L2 hit, the block is invalidated from L2 cache and filled in
Dcache and the rest behavior same as you explained in the diagram, you can
use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
You may need to take care of "clean victim" from dcache which is not a
difficult modification.

Best regards,

Abhishek


On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
wrote:

> Dear All,
>   Is 'mostly exclusive cache' supported in GEM5 classic model strictly
> non-exclusive cache? If it is not non-exclusive cache, how can I make it
> non-exclusive cache?
>
>   The non-exclusive cache is shown in Fig. below.
> [image: image.png]
>  Can anyone guide me?
>
> Many thanks,
> best regards,
> Avais
>
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Re: [gem5-users] (no subject)

[Krishna, Tushar]

http://www.gem5.org/Garnet2.0

It is woken up by both the coherence protocol buffers and the router to NI 
links connected to it.

Cheers,
Tushar

On Jun 26, 2018, 2:48 AM -0400, Nikhitha Josh , wrote:
Hi,
Which class calls the Network Interface wakeup() function?

Regards,
Nikhitha

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Re: [gem5-users] (no subject)

[SHARJEEL KHILJI]

Hello
yes if you are using ruby memory system you can select the type of protocol
(e.g., MESI Two level, MOESI CMP Directory etc).

regards,
Muhammad

On 11 October 2017 at 10:51, Muhammad Avais  wrote:

> Hi,
> Does GEM5 follows any specific cache coherence protocol?
>  If yes? then which one?
> Thanks
>
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Re: [gem5-users] (no subject)

[Matheus Alcântara Souza via gem5-users]

I've compiled Parsec v.2.1 for M5 following the instructions on
http://www.cs.utexas.edu/~cart/parsec_m5/. The code changes I needed were a
few, so I did not have much efforts.

You should aim this using the same instructions, reading the Tech Report
http://www.cs.utexas.edu/~parsec_m5/TR-09-32.pdf.

The crosscompiler is available in http://www.m5sim.org/Download. Pay
attention to the Kernel Version used to compile.

Best Regards.
Matheus

2014-09-28 11:51 GMT-03:00 babak aghaei via gem5-users gem5-users@gem5.org
:

 Hi
 Is anybody has run Parsec 3.0 on ALPHA ISA?
  plz help!
 ---

 *Babak Aghaei **Ph.D candidate* in *Computer*
 *Engineering (Hardware),Science and Research University*
 *Tehran, IRAN *
 *E-Mail: * b...@yahoo.com*B b.agh...@iaut.ac.ir b.agh...@iaut.ac.ir*
 b.agh...@iaut.ac.ir.agh...@iaut.ac.ir
 *E-Mail: **babak_agha...@yahoo.com* babak_agha...@yahoo.com
 *E-Mail: **babak.agha...@gmail.com* babak.agha...@gmail.com

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-- 

Atenciosamente,
Matheus Alcântara Souza
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Re: [gem5-users] (no subject)

[Amin Farmahini]

Tony,

I noticed the same thing as well and as you mentioned the perf penalty
could be really high.
http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html
I don't know what the reason could be, but I was able to fix this. If I
remember right, to prevent squashing, you need to mark those loads with a
flag or something and try to add them to instruction queue again.

Thanks,
Amin


On Thu, Sep 26, 2013 at 6:21 PM, Tony Nowatzki t...@cs.wisc.edu wrote:

 Hi All,

 Apologies in advance if this is a silly question, or a repeat.

 I recently noticed that the OoO core squashes itself and all younger
 instructions when a load is issued to the memory system, but the cache is
 blocked (say the MSHRs are full, or there are no targets left). Contrarily,
 when a write is issued to the memory system, the store will simply retry
 until the cache can handle the request.

 There is potentially some performance penalty in squashing these loads,
 and a large energy penalty as well (can be up to 2x for the core in some
 contrived cases, according to mcpat).  Given that these squashes can occur
 frequently in memory-bound programs, is there a reason this was chosen as
 the implementation?  Is there a reason why loads can't be stalled and
 retried on a cache block?

 Thanks!
 Tony
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Re: [gem5-users] (no subject)

[Mitch Hayenga]

Amin/Tony, there is a very big reason for why gem5 does this.  It's about
modeling what real processors do.

Modern out of orders are very deeply pipelined and instructions take
multiple cycles to execute from the time they are scheduled.  To enable
back-to-back execution of dependent instructions, the scheduler
speculatively schedules instructions multiple cycles ahead of time based on
the assumed execution cycle of the producer instructions.  If all
instructions take the expected latencies, dependent instructions catch
their operands via the bypass paths.  Loads throw a wrench into this
because they can have variable latencies (miss in the L1 cache, be blocked,
etc).  In a real pipeline, if a load misses or is blocked the speculative
schedule of instructions gets messed up.  The hard part is that some
portion of the scheduled instructions may have been independent of the
load, whereas other instructions fall in the load-dependent program slice.
 The amount of control logic to precisely determine mischeduled dependent
instructions is prohibitive, so squashing/replaying instructions is a
common technique.  There are various levels of preciseness that can be done
for replaying instructions.  If I remember right o3's was very
conservative/pessimistic.

Here is a good paper that discusses replay schemes and their impact.

Understanding Scheduling Replay Schemes
Ilhyun Kim and Mikko H. Lipasti
http://pharm.ece.wisc.edu/papers/hpca2004ikim.pdf

Whoever coded the o3 model decided that since stores do not produce
register operands, the replay is unnecessary there.



On Thu, Sep 26, 2013 at 6:35 PM, Amin Farmahini amin...@gmail.com wrote:

 Tony,

 I noticed the same thing as well and as you mentioned the perf penalty
 could be really high.
 http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html
 I don't know what the reason could be, but I was able to fix this. If I
 remember right, to prevent squashing, you need to mark those loads with a
 flag or something and try to add them to instruction queue again.

 Thanks,
 Amin


 On Thu, Sep 26, 2013 at 6:21 PM, Tony Nowatzki t...@cs.wisc.edu wrote:

 Hi All,

 Apologies in advance if this is a silly question, or a repeat.

 I recently noticed that the OoO core squashes itself and all younger
 instructions when a load is issued to the memory system, but the cache is
 blocked (say the MSHRs are full, or there are no targets left). Contrarily,
 when a write is issued to the memory system, the store will simply retry
 until the cache can handle the request.

 There is potentially some performance penalty in squashing these loads,
 and a large energy penalty as well (can be up to 2x for the core in some
 contrived cases, according to mcpat).  Given that these squashes can occur
 frequently in memory-bound programs, is there a reason this was chosen as
 the implementation?  Is there a reason why loads can't be stalled and
 retried on a cache block?

 Thanks!
 Tony
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Re: [gem5-users] (no subject)

[Amin Farmahini]

You should not add it there. O3CPU.py defines the variables (processor
parameters in this case) with their default values.
You should add it to your se.py or fe.py. After you instantiate your
processor, you can set this up. Something like:
system.cpu[?].numROBEntries = option.robsize

(Actually this is not the recommended way if you want to keep your code
clean, but it is the easier way. The better way is to make a separate
python file to take care of such things like what is done in CacheConfig.py)

Amin


On Wed, Jul 17, 2013 at 12:12 AM, Mahshid Sedghi
mahshid.sed...@gmail.comwrote:

 Thanks Tao and Amin. I am able to add options, but I am not able to assign
 it to numROBEntries. I mean when I use this in O3CPU.py:

 numROBEntries = options.robsize

 it doesn't work, since options module is not defined here. I tried
 importing options, but still didn't work. Can you elaborate on how to do
 this?

 Thanks.


 On Tue, Jul 16, 2013 at 9:32 PM, Zheng Wu z...@uwaterloo.ca wrote:

 Hi,

 I am also curious about how to create new options as well. The
 numRobEntries in O3CPU.py you mentioned has the following:

 numROBEntries = Param.Unsigned(192, Number of reorder buffer entries)

 How is this related to options.robsize as mentioned?


 In addition, what if I were to add another data member to a class and
 want to use python options to set the value, what additional steps or
 procedure do i need to perform? Do I need to do anything with SWIG or
 something?

 Thanks,
 Zheng Wu


 On 2013-07-16, at 8:23 PM, Amin Farmahini amin...@gmail.com wrote:

 The last thing that Tao forgot to mention is to use options.robsize to
 set the value of numROBEntries (numROBEntries is defined in
 src/cpu/o3/O3CPU.py).

 Amin


 On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang tao.zhang.0...@gmail.comwrote:

 Hi Mahshid,

 ** **

 You can use the “add_option” to add any desired options in the command
 line. To do this, you just add the line below (or something like it) at the
 beginning of your fs.py. 

 ** **

 parser.add_option(-rob, --robsize, type=int, default=128,
 help=”specify the rob size”);

 ** **

 Then, after all options (including the default options and personalized
 options) have been parsed (in other words, the variable ‘options’ is
 initialized), you can simply leverage the option below.

 ** **

 options.robsize

 ** **

 After this, you can use the option in the command line, like

 ** **

 gem5.opt configs/example/se.py --robsize=64 ……

 ** **

 Note that if your option includes dash “-”, it will be converted into
 underscore “_”. For example, “--rob-size” produces representative
 “options.rob_size”. 

 ** **

 Also, it is pretty helpful if you look at the Options.py to see how the
 default options are added into the system. The file is in configs/common/.
 

 ** **

 -Tao

 ** **

 ** **

 *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org]
 *On Behalf Of *Mahshid Sedghi
 *Sent:* Tuesday, July 16, 2013 4:35 PM
 *To:* gem5 users mailing list
 *Subject:* [gem5-users] (no subject)

 ** **

 Hello,

 ** **

 I want to introduce a new option to the simulation script to define the
 ROB size, since I am doing experiments with different ROB sizes and would
 like to skip the procedure of rebuilding the gem5 again and again for
 different ROB sizes. Basically, I need to do a similar thing as the thread
 below:

 ** **

 http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html

 ** **

 I am not still sure how to relate the option with the cpu parameters.
 I'd appreciate it if someone can give me some hints.

 ** **

 Thanks,

 Mahshid

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Re: [gem5-users] (no subject)

[Mahshid Sedghi]

Thanks a lot Amin. Now it's working. I actually had to insert the line in
Simulation.py rather than fs.py, since I switch cpus after restoring from
checkpoint and therefore, I had to assign the robsize to switch_cpus
rather than system.cpu.

Appreciate your help,
Mahshid


On Wed, Jul 17, 2013 at 2:32 AM, Amin Farmahini amin...@gmail.com wrote:

 You should not add it there. O3CPU.py defines the variables (processor
 parameters in this case) with their default values.
 You should add it to your se.py or fe.py. After you instantiate your
 processor, you can set this up. Something like:
 system.cpu[?].numROBEntries = option.robsize

 (Actually this is not the recommended way if you want to keep your code
 clean, but it is the easier way. The better way is to make a separate
 python file to take care of such things like what is done in CacheConfig.py)

 Amin


 On Wed, Jul 17, 2013 at 12:12 AM, Mahshid Sedghi mahshid.sed...@gmail.com
  wrote:

 Thanks Tao and Amin. I am able to add options, but I am not able to
 assign it to numROBEntries. I mean when I use this in O3CPU.py:

 numROBEntries = options.robsize

 it doesn't work, since options module is not defined here. I tried
 importing options, but still didn't work. Can you elaborate on how to do
 this?

 Thanks.


 On Tue, Jul 16, 2013 at 9:32 PM, Zheng Wu z...@uwaterloo.ca wrote:

 Hi,

 I am also curious about how to create new options as well. The
 numRobEntries in O3CPU.py you mentioned has the following:

 numROBEntries = Param.Unsigned(192, Number of reorder buffer entries)

 How is this related to options.robsize as mentioned?


 In addition, what if I were to add another data member to a class and
 want to use python options to set the value, what additional steps or
 procedure do i need to perform? Do I need to do anything with SWIG or
 something?

 Thanks,
 Zheng Wu


 On 2013-07-16, at 8:23 PM, Amin Farmahini amin...@gmail.com wrote:

 The last thing that Tao forgot to mention is to use options.robsize to
 set the value of numROBEntries (numROBEntries is defined in
 src/cpu/o3/O3CPU.py).

 Amin


 On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang tao.zhang.0...@gmail.comwrote:

 Hi Mahshid,

 ** **

 You can use the “add_option” to add any desired options in the command
 line. To do this, you just add the line below (or something like it) at the
 beginning of your fs.py. 

 ** **

 parser.add_option(-rob, --robsize, type=int, default=128,
 help=”specify the rob size”);

 ** **

 Then, after all options (including the default options and personalized
 options) have been parsed (in other words, the variable ‘options’ is
 initialized), you can simply leverage the option below.

 ** **

 options.robsize

 ** **

 After this, you can use the option in the command line, like

 ** **

 gem5.opt configs/example/se.py --robsize=64 ……

 ** **

 Note that if your option includes dash “-”, it will be converted into
 underscore “_”. For example, “--rob-size” produces representative
 “options.rob_size”. 

 ** **

 Also, it is pretty helpful if you look at the Options.py to see how the
 default options are added into the system. The file is in configs/common/.
 

 ** **

 -Tao

 ** **

 ** **

 *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org]
 *On Behalf Of *Mahshid Sedghi
 *Sent:* Tuesday, July 16, 2013 4:35 PM
 *To:* gem5 users mailing list
 *Subject:* [gem5-users] (no subject)

 ** **

 Hello,

 ** **

 I want to introduce a new option to the simulation script to define the
 ROB size, since I am doing experiments with different ROB sizes and would
 like to skip the procedure of rebuilding the gem5 again and again for
 different ROB sizes. Basically, I need to do a similar thing as the thread
 below:

 ** **

 http://www.mail-archive.com/gem5-users@gem5.org/msg00480.html

 ** **

 I am not still sure how to relate the option with the cpu parameters.
 I'd appreciate it if someone can give me some hints.

 ** **

 Thanks,

 Mahshid

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Re: [gem5-users] (no subject)

[SHARAN MORA (RIT Student)]

I want to specify gem5 which g++ compiler to use (in this case g++44), not
change default compiler of bash. In which file can I set the compiler path
Thanks


On Sat, Jan 26, 2013 at 9:50 PM, Fangfei Liu fangf...@princeton.edu wrote:

  Hi, you can add an environment variable CXX. For example, if you use
 bash, you can add a line in your .bashrc file:



 export CXX=g++44



 Hope it helps.
  --
 *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on
 behalf of SHARAN MORA (RIT Student) [sxm5...@rit.edu]
 *Sent:* Saturday, January 26, 2013 9:43 PM
 *To:* gem5-users@gem5.org
 *Subject:* [gem5-users] (no subject)

Hi Everyone,
  How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot
 directly upgrade my gcc version 4.1.2 as I use Centos 5.
  Thanks,

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Re: [gem5-users] (no subject)

[Andreas Hansson]

If you do the export in a shell it will only apply to that process. If you 
want, you can also have a gem5_env or similar that you source every time you 
do gem5 work. Lastly, you can add the CXX=g++44 and CC=gcc44 on the command 
line.

Hope that helps.

Andreas

From: SHARAN MORA (RIT Student) sxm5...@rit.edumailto:sxm5...@rit.edu
Reply-To: gem5 users mailing list 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Sunday, 27 January 2013 14:46
To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: Re: [gem5-users] (no subject)

I want to specify gem5 which g++ compiler to use (in this case g++44), not 
change default compiler of bash. In which file can I set the compiler path
Thanks


On Sat, Jan 26, 2013 at 9:50 PM, Fangfei Liu 
fangf...@princeton.edumailto:fangf...@princeton.edu wrote:

Hi, you can add an environment variable CXX. For example, if you use bash, you 
can add a line in your .bashrc file:



export CXX=g++44



Hope it helps.


From: gem5-users-boun...@gem5.orgmailto:gem5-users-boun...@gem5.org 
[gem5-users-boun...@gem5.orgmailto:gem5-users-boun...@gem5.org] on behalf of 
SHARAN MORA (RIT Student) [sxm5...@rit.edumailto:sxm5...@rit.edu]
Sent: Saturday, January 26, 2013 9:43 PM
To: gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] (no subject)

Hi Everyone,
How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot 
directly upgrade my gcc version 4.1.2 as I use Centos 5.
Thanks,

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Re: [gem5-users] (no subject)

[Fangfei Liu]

Hi, you can add an environment variable CXX. For example, if you use bash, you 
can add a line in your .bashrc file:



export CXX=g++44



Hope it helps.


From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of 
SHARAN MORA (RIT Student) [sxm5...@rit.edu]
Sent: Saturday, January 26, 2013 9:43 PM
To: gem5-users@gem5.org
Subject: [gem5-users] (no subject)

Hi Everyone,
How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot 
directly upgrade my gcc version 4.1.2 as I use Centos 5.
Thanks,
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Re: [gem5-users] (no subject)

[Tao Zhang]

this is correct. However, there should be more tag bits for the purpose 
of cache conherence and replacement (e.g., valid, dirty, LRU...)


-Tao

On 11/24/2012 01:23 AM, Nitin Chaturvedi wrote:

Dear sir
srry for wrong interpretation..please check again and correct 
me if i am wrong...


my understanding.
If..physical address space 1GB.size of 
physical address 30-bits...

Now,
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address interpretation will be as follows

-12bits for Tag8bits for 
index---4bits to select 
bank--6 bits for block offset



sir, please correct me if i am wrong..
 thanks

On Sat, Nov 24, 2012 at 11:28 AM, megha gupta megha122...@gmail.com 
mailto:megha122...@gmail.com wrote:


my understanding...physical address space
.means on chip L2 cache
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address is of 50 bits and its interpretation will be
as follows

-32bits for Tag8bits for
index---4bits to select
bank--6 bits for block offset


sir, please correct me if i am wrong..




--
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)


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Re: [gem5-users] (no subject)

[Nitin Chaturvedi]

Dear sir
srry for wrong interpretation..please check again and correct me if
i am wrong...

my understanding.
If..physical address space 1GB.size of physical
address 30-bits...
Now,
1. if size of on chip L2 cache is 4MB
2. block size.64byte
3. 16 banks and 16 way set associative

then physical address interpretation will be as follows

-12bits for Tag8bits for
index---4bits to select bank--6
bits for block offset


sir, please correct me if i am wrong..
 thanks

On Sat, Nov 24, 2012 at 11:28 AM, megha gupta megha122...@gmail.com wrote:

 my understanding...physical address space .means
 on chip L2 cache
 1. if size of on chip L2 cache is 4MB
 2. block size.64byte
 3. 16 banks and 16 way set associative

 then physical address is of 50 bits and its interpretation will be as
 follows

 -32bits for Tag8bits for
 index---4bits to select bank--6
 bits for block offset


 sir, please correct me if i am wrong..




-- 
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)
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Re: [gem5-users] (no subject)

[Mahesh Jethanandani]

Sunitha,

Have you installed the first software in this list?

http://www.gem5.org/Dependencies#External_tools_and_required_versions

On Jul 9, 2012, at 4:23 AM, sunitha p wrote:

 hi all..
 
 I am trying to install gem5
  am facing this error..have installed scons,swig,python..
 
 kindly help me out
 
 
 scons: Reading SConscript files ...
 Error Don't know what compiler options to use for your compiler.
compiler: None
version: COMMAND NOT FOUND!
If you're trying to use a compiler other than GCC, ICC, SunCC,
or clang, there appears to be something wrong with your
environment.

If you are trying to use a compiler other than those listed
above you will need to ease fix SConstruct and 
src/SConscript to support that compiler.
 
 -- 
 Thanks  Regards
 
 Sunitha.P
 8970314569
 
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Re: [gem5-users] (no subject)

[Gabriel Michael Black]

You should really put a subject on this so people who would be  
interested will see it when scanning through their mail.


This sounds like a bug in one of the simulation scripts. I vaguely  
remember a recent change where there was a redundant copy of the  
system parameter being used with one of the CPUs (maybe?) and that was  
taken out of the C++. It could be that it was left in some of the  
python scripts, and the now redundant system parameter is colliding  
with the real one.


Gabe

Quoting Meeran Mohideeen mee...@bsauniv.ac.in:


Hi...

I am trying to run an ALPHA CMP simulation with two cores with ruby memory
component When i try to run the simulation using
./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB
--l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing
--script=runcsript.rcS

i am getting the following warning.

warning: overwriting port orphan LinuxAlphaSystem.tsunami.ide.dma value
orphan LinuxAlphaSystem.dma_cntrl0.dma_sequencer.port[0] with orphan
LinuxAlphaSystem.dma_cntrl0.dma_sequencer.port[1]
warning: overwriting port orphan LinuxAlphaSystem.tsunami.ethernet.dma
value orphan LinuxAlphaSystem.dma_cntrl1.dma_sequencer.port[0] with
orphan LinuxAlphaSystem.dma_cntrl1.dma_sequencer.port[1]

Also... the simulation is halted with

[ srm_env: version 0.0.6 loaded successfully ] (i.e: knfsd installation
doesnt begins)  (from m5out/system.term)

But when i run the same simulation without ruby component (i.e:
./build/ALPHA/fs.py) the simulation runs fine. Whats wrong with
ruby Please help me..




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Re: [gem5-users] (no subject)

[Meeran Mohideeen]

I checked all the .py files within the src/mem/ruby folder... But i dont
see any flaw in them (upto my knowledege)... I will try checking the cc
files also...

[Thank you for mentioning my mistake... i actually forgot and will see to
it the subject is included always]

On Sat, Feb 18, 2012 at 3:30 AM, Gabriel Michael Black 
gbl...@eecs.umich.edu wrote:

 You should really put a subject on this so people who would be interested
 will see it when scanning through their mail.

 This sounds like a bug in one of the simulation scripts. I vaguely
 remember a recent change where there was a redundant copy of the system
 parameter being used with one of the CPUs (maybe?) and that was taken out
 of the C++. It could be that it was left in some of the python scripts, and
 the now redundant system parameter is colliding with the real one.

 Gabe


 Quoting Meeran Mohideeen mee...@bsauniv.ac.in:

  Hi...

 I am trying to run an ALPHA CMP simulation with two cores with ruby memory
 component When i try to run the simulation using
 ./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB
 --l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing
 --script=runcsript.rcS

 i am getting the following warning.

 warning: overwriting port orphan LinuxAlphaSystem.tsunami.ide.dma value
 orphan LinuxAlphaSystem.dma_cntrl0.dma_sequencer.port[0] with orphan
 LinuxAlphaSystem.dma_cntrl0.dma_sequencer.port[1]
 warning: overwriting port orphan LinuxAlphaSystem.tsunami.ethernet.dma
 value orphan LinuxAlphaSystem.dma_cntrl1.dma_sequencer.port[0] with
 orphan LinuxAlphaSystem.dma_cntrl1.dma_sequencer.port[1]

 Also... the simulation is halted with

 [ srm_env: version 0.0.6 loaded successfully ] (i.e: knfsd
 installation
 doesnt begins)  (from m5out/system.term)

 But when i run the same simulation without ruby component (i.e:
 ./build/ALPHA/fs.py) the simulation runs fine. Whats wrong with
 ruby Please help me..



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Re: [gem5-users] (no subject)

[Nilay Vaish]

Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


My name is Sudhanshu. I am using gem5 for simulations.?Can you please let 
me know if there is a document that specifies the architecture of gem5, in 
terms of module and its working model (document of detailed software 
architecture of gem5 and its work flow)? I need to understand the 
work-flow of gem5 to make changes to the model to support heterogeneous 
architectural parameters like frequency, cache size, etc instead of SMP 
model.


Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
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Re: [gem5-users] (no subject)

[sudhanshu jha]

Hello,

Thanks for the response.  I am looking for some detailed document like a 
full-fledged manual describing the whole simulation model (with block diagrams, 
etc). I hope you understand what i am trying to say. Please let me know if 
there is any document of this kind.

regards,
Sudhanshu.



 From: Nilay Vaish ni...@cs.wisc.edu
To: sudhanshu jha to_s...@yahoo.com; gem5 users mailing list 
gem5-users@gem5.org 
Sent: Monday, December 12, 2011 12:46 PM
Subject: Re: [gem5-users] (no subject)
 
Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:

 Hello,

My name is Sudhanshu. I am using gem5 for simulations. Can you please let me 
know if there is a document that specifies the architecture of gem5, in terms 
of module and its working model (document of detailed software architecture of 
gem5 and its work flow)? I need to understand the work-flow of gem5 to make 
changes to the model to support heterogeneous architectural parameters like 
frequency, cache size, etc instead of SMP model.

Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
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Re: [gem5-users] (no subject)

[Nilay Vaish]

You may want to take a look at our article in May 2011 issue of ACM 
SIGARCH Computer Architecture News. Here is the link --


http://dx.doi.org/10.1145/2024716.2024718

--
Nilay

On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


Thanks for the response. ?I am looking for some detailed document like a 
full-fledged manual describing the whole simulation model (with block 
diagrams, etc). I hope you understand what i am trying to say. Please let 
me know if there is any document of this kind.


regards,
Sudhanshu.



 From: Nilay Vaish ni...@cs.wisc.edu
To: sudhanshu jha to_s...@yahoo.com; gem5 users mailing list gem5-users@gem5.org 
Sent: Monday, December 12, 2011 12:46 PM

Subject: Re: [gem5-users] (no subject)

Sudhanshu, documentation on gem5 is available on our website www.gem5.org.

--
Nilay


On Mon, 12 Dec 2011, sudhanshu jha wrote:


Hello,


My name is Sudhanshu. I am using gem5 for simulations.?Can you please let me 
know if there is a document that specifies the architecture of gem5, in terms 
of module and its working model (document of detailed software architecture of 
gem5 and its work flow)? I need to understand the work-flow of gem5 to make 
changes to the model to support heterogeneous architectural parameters like 
frequency, cache size, etc instead of SMP model.

Can you please send me a copy of this document at your earliest?

Thanks in advance.

regards,
Sudhanshu.___
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