Re: Epoch Index

2024-06-11 Thread Paul Schuster
So, as of z/os 3.1, there does not seem to  be a way to test with dates beyond 
09/17/2042?  A “R 00,DATE=2042.260 “ works, but a “R 00,DATE=2042.261” 
generates a “IEE306I RPLY HAS INVALID NUMERICS” message.

Or am I missing something obvious?

Thank you.

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Re: Not getting IBM-MAIN Email

2024-04-10 Thread Paul Schuster
My digest also automagically showed up today.  Hopefully issue is resolved.

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Re: Is our LIST Active

2024-04-05 Thread Paul Schuster
I have not received my 'daily digest' email for a few weeks now.  Maybe 
something has changed?

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ATTACHX/STIMERM WAIT=YES

2023-11-13 Thread Paul Schuster
How to handle this situation: task ‘A’ attaches a subtask, task ‘B’.

The ‘B’ task issues a STIMERM WAIT=YES 

Task ‘A’ terminates, but gets the A03 abend since task ‘B’ still active.

How can task ‘A’ communicate to the subtask ‘B’ that it (task ‘B’) needs to 
terminate?  Task ‘B’ is in the STIMERM wait, so it can’t do anything.

I didn’t see this scenario documented in the Assembler Services Guide or the 
Assembler Services References.

Thank you.

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Re: Checkpoint/restart in COBOL applications?

2023-06-21 Thread Paul Schuster
There are a lot of documented restrictions with CHECKPOINT and NAME/TOKEN 
services.

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Re: Loss of access to z/VM USER DIRECT - Is there a Recovery path.

2023-06-07 Thread Paul Schuster
Perhaps using a directory management product such as VM SECURE or DIRMAINT 
would be helpful to prevent such a situation.

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SYS1.MACLIB(FXECNTRL)

2023-05-24 Thread Paul Schuster
Hello:

In the z/os 2.5 version of this macro, there is this statement:

"
Additional references and an overview of the Function Registry
for z/OS can be found in the z/OS MVS Diagnosis: Tools and
Service Aids book.
"

Looking in the z/os 2.5 version of this manual does not seem to contain any 
information about Function Registry.  Is this something that will be
added in a future edition of z/OS MVS Diagnosis: Tools and Service Aids?

Thank you.

Paul

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Re: Bytes in a 3390 track - reason for the question

2022-11-24 Thread Paul Schuster
TRKCALC knows everything.

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Re: Location of forms code in z/OS manuals

2022-10-27 Thread Paul Schuster
IBM provides an index when you download the entire pubs library zip file.
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D IPLINFO / IEE254I

2022-10-24 Thread Paul Schuster
Interesting after RSU2209 z/os 2.5 this now displays some VM info:

VM CPID = z/VMrelease
VM UUID IS NOT PROVIDED
VM NAME = vmuserid
VM EXT NAME IS NOT PROVIDED

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MODE trace entry

2022-07-28 Thread Paul Schuster
The manual z/OS: z/OS MVS Diagnosis: Tools and Service Aids GA32-0905-50 shows 
that a MODE trace entry will be generated for 
"a change into or out of 64-bit addressing mode".  Is a SAM64 instruction 
supposed to generate such a trace entry?  I am not seeing one when a SAM64 
instruction is executed.

Thank you.

Paul

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SYS1.LOGREC vs VERBX LOGDATA

2022-07-28 Thread Paul Schuster
Hello:

I clear the SYS1.LOGREC with a PGM=IFCEREP1 'ZERO=Y' parm.  But if I capture a 
SVC dump afer that, the VERBX LOGDATA will still show events that occurred 
before the SYS1.LOGREC was cleared.  Is there a way to force the z/os internal 
version of SYS1.LOGREC to be cleared at the same time the disk-resident version 
is cleared with a PGM=IFCEREP1 'ZERO=Y' ?

Thank you.

Paul 

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Re: TIMEUSED macro

2022-07-02 Thread Paul Schuster
Yes thank you 'LINKAGE=SYSTEM' works.  My apologies for not seeing that in the 
manual.

Paul

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TIMEUSED macro

2022-07-02 Thread Paul Schuster
There was a discussion from 2020 about 'Strange S0C4 on z15' where the 
instruction

L 15,X'B4C'(0,0)58F0 0B4C

would cause 0C4 accessing the SVT.

It seems that the TIMEUSED macro, even as of z/os 2.5 level (01* STATUS = 
HBB77C0 ) when coded

TIMEUSED STORADR=STIME  

generates the sequence

TIMEUSED STORADR=STIME 
MACDATE 04/06/2005  
LA1,STIMEAREA FOR RETURN OF TIME VALUE  
L 15,X'B4C'(0,0) SVT ADDRESS
L 15,X'88'(0,15) ADDRESS OF SERVICE ROUTINE 
BASSM 14,15 


which causes 0C4 on the   L 15,X'B4C'(0,0) instruction.

Does the TIMEUSED macro need updating to access the SVT the supported modern 
way?

Thank you.



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Question about z/os and VM ADJUNCT

2022-05-20 Thread Paul Schuster
I code an IF SLIP with ACTION=WAIT.  When it hits, I get the IEE844W message. I 
start the adjunct, and I want to display the storage at the locations pointed 
to by the registers.  I use the command 

CPU 0 CMD DISPLAY PRI regval.100

This works for a register that points to common storage, but for a register 
value that points to private storage I get 

CPU 0 CMD DISPLAY PRI 7F7FA2E8.100
00: V  0E R
00: V7F7FA2E8 to 7F7FA3E7  non-addressable storage - page translation exception

(At the time the SLIP hit, the register value is valid.)
Is there something else I need to specify on the DISPLAY command to get the 
register value correctly translated to the VM third level storage?  Or does the 
ACTION=WAIT destroy the capability of doing a translation?

Thank you. 

  

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Re: z/OS ISPF Panel to include System Name

2022-02-25 Thread Paul Schuster
If you have access to the ISPF Configuration Table (see ISPF Planning and 
Customizing) you can have ISPF default behavior display it:

DEFAULT_SYSTEM_NAME
Select to display the system name. The valid values are OFF or ON.
The default is OFF.

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IEARBUP/IEARBUPM

2021-10-08 Thread Paul Schuster
Hi:

In the z/os 2.4 MVS Programming: Authorized
Assembler Services Reference, Volume 2
(EDT-IXG) in the IEARBUP section, there is this sentence:

"Macro IEARBUPM provides equate symbols for the return and reason codes."

However, IEARBUPM doesn't seem to be in MACLIB or MODGEN.  

So 1) was it inadvertently not shipped in MACLIB or MODGEN, or 2) was it 
inadvertently documented in IEARBUP?

Just wondering.

Thank you.

Paul

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Re: Is there an IBM supplied DSECT that maps the linkage stack entry?

2020-02-11 Thread Paul Schuster
Do these comments still apply (15 years later)?:

"
No there is not.

And oh by the way even after you get all that you need from the Principles
of Operation, be aware that there are sections of a linkage stack within
which the entries are, and you cannot necessarily navigate from one section
to the next using architected-by-hardware structures.
"

Thank you.

Paul

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Re: ibm.com message (Yikes — we didn't catch all of that.)

2019-12-13 Thread Paul Schuster
"They should have a link that you select that fixes this. The problem is one of 
IBM’s own making. They generate a pie not a cookie. "
Yes unfortunately I get the same error 400 message Yikes — we didn't catch all 
of that.) when trying to access the link to report the problem to IBM.

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ibm.com message (Yikes — we didn't catch all of that.)

2019-12-13 Thread Paul Schuster
Does anyone get the dreaded 'Yikes — we didn't catch all of that.' message  
when trying to access something (like a  pmr) in IBM.com?  


How to avoid?


I tried their (IBM) suggested remedies of clearing browser cache and cookies 
but still no work.

Thank you.

Paul

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undocumented instruction?

2019-04-09 Thread Paul Schuster
Just curious.  Saw this in a JES2  abend:

$HASP088 FAILING INSTR WAS E3105004   

Could not find a 'E310' instruction in the Principles of Operation.  Is 'E310' 
IBM  only?  Or is the $HASP088 incorrect?

Thank you.

Paul

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VSAM ALTER ?

2019-03-21 Thread Paul Schuster
Hello:

Is it possible to alter the secondary space value in a catalog entry for a VSAM 
file?  Secondary space doesn’t show up in ALTER as a valid value to change, so 
I am wondering if it is possible to just issue a hand-written SVC 26 request to 
update this field.  Effectively I want to give the illusion that a cluster (or 
data component) has a secondary value when the cluster was originally defined 
with ‘0’ secondary.

Thank you.

Paul

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determining step completion code/status

2018-12-27 Thread Paul Schuster
How can you tell if a  step has completed normally or abnormally?

I have looked in the SCT and SCTX but don't see anything relevant.  Where else 
can this be stored?

Thank you.

Paul

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ESTAE retry vs percolate SDWACLUP bit

2018-11-30 Thread Paul Schuster
Hello:

The manual “MVS Programming: Assembler Services
Guide” Chapter 8. “Providing recovery” explains that an ESTAE that is called 
with the ‘SDWACLUP’ bit on can only ‘percolate’ (SETRP RC=0). It further 
explains that if you do attempt a ‘retry’ (SETRP RC=4) , the retry will be 
ignored.

I was testing with an ESTAE that gets control with the SDWACLUP’ bit on, and 
the routine does attempt a retry (SETRP RC=4) but it indeed was ignored, with 
no other apparent adverse impact.

So my question is this: aside from ‘completeness/code purity’, is there 
anything to worry about if an ESTAE attempts a ‘retry’ even though the 
‘SDWACLUP’ bit is on? I can envision that the recovery routine itself may have 
different logic based on whether the ‘SDWACLUP’ bit is on or off.

I did change my specific ESTAE to exit SETRP RC=0 when the ‘SDWACLUP’ bit is on.

Thank you for any insight you can provide.

Paul

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Re: Disable DYNALLOC?

2017-12-21 Thread Paul Schuster
IEFDB401 — Dynamic Allocation Input Validation
Routine Exit allows you to fail a request.

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ESTAE no SDWA ?

2017-05-23 Thread Paul Schuster
So when an SDWA is present in an ESTAE recovery routine, you
can do a SETRP REMREC=YES to have the ESTAE removed when you
do the retry.

When no SDWA is present, you cannot do the SETRP, so am I correct
in believing that the retry point must then do the ESTAE(X) 0 to
remove the ESTAE?

Thank you.

Paul

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Re: FRR Clarification One More Thing I forgot

2017-02-12 Thread Paul Schuster
if you have the ability to read look at

MVS Programming: Authorized Assembler
Services Guide

and

MVS Programming: Assembler
Services Guide


chapters on recovery

problem solved



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Re: diagnose 8 / interesting dilemma

2016-10-19 Thread Paul Schuster
Thank you for all of the responses and ideas.

I guess if your 'guest operating system' is something
like 'CMS' then it is quite easy to get consecutive pages of
real storage addresses.  But not quite so easy with z/os.

I guess if you really want to do 'query virtual dasd' under
z/os pre z/vm 6.4 you would need to do it via multiple calls to
diagnose 8 and doing a 'query virtual -' into the 4k
buffer and then
further parse out the DASD addresses. Or use Ed Jaffe's methodology.

Thank you.

Paul

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diagnose 8 / interesting dilemma

2016-10-17 Thread Paul Schuster
I am issuing DIAGNOSE 8 on my z/os image under VM (z/vm) to do a QUERY VIRTUAL 
DASD.  It works—up to a certain point:

The QUERY VIRTUAL DASD command returns (for me) 38617 (decimal) bytes, 
according to the CC=0 after the DIAGNOSE 8 command.  My buffer is large enough 
to accommodate this.  I have tried several different sub-pools of storage.  I 
PGSER FIX the buffer pages.  I do a SYSEVENT DONTSWAP.  I do a LRA of the 
virtual address of the start of the buffer.  The DIAGNOSE completes CC=0. But, 
in my buffer, I am only seeing the first page (4095) bytes of the output.  

My question: I don’t see any documented restriction in the VM manuals that 
limits the DIAGNOSE 8 output buffer to 4K (rather the limitation is the 
architecture limit depending on your amode.) The z/vm manuals say the buffer 
can cross page boundaries.  So is there a way to force the real storage 
addresses of the page-fixed pages to be consecutive?  According to the diagnose 
8 doc., the buffer needs to be in guest-real storage, hence the LRA.  And it is 
working for the first 4k page.

Thank you for any insight you can provide. 
Paul

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Re: Internals of Catalog

2016-09-13 Thread Paul Schuster
The IBM manual

z/OS
DFSMS Managing Catalogs

documents this very well.

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expiration date in a catalog entry

2016-08-18 Thread Paul Schuster
At what point in time does the 'expiration date' of a data set get written
to its catalog entry?

It seems you can allocate a data set with an EXPDT, but a subsequent LISTCAT
will show 'EXPIRATION--.000'.  There is a mention in 
'SYS1.MACLIB(IEFJFCBN)' that

"
NOTE: JFCBXPDT is not valid until the data set  
  is actually allocated."

I run an IEBDG to add a record to the data set, (which will cause it to 
be allocated), but a subsequent LISTCAT still shows the 
'EXPIRATION--.000'.

But I have seen catalog entries that have an expiration date other than 
.000,
so when does this get updated?

Thank you for any insight you can provide.

Paul

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Re: Highest address "below the bar"

2016-07-01 Thread Paul Schuster
Ed:

Can you elaborate on the reason(s) for your methodology:

"We routinely load base registers and "uninitialized" pointers to 
7000 (or sometimes 7BAD) rather than zero."

The one reason I can visualize is that instead of unintentionally
accessing something in low core you would experience a S0C4 instead.

Thank you.

Paul

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interesting SYSTRACE entries ?

2016-05-27 Thread Paul Schuster
Hello: I saw this in a z/os 1.13 dump:

00 01B2 008BA3E8  SVC  9 _0001A314   00040520 000400C0  
Delete  22:25:22.551801  32
 07741000 8000  
   
01 01B2 008BA1C8  SVC 78 _24F4135E  E601 1608 008789F8  
Freemain22:25:22.551810  28
 07841000 8000  
   
00 01B2 008BA3E8  SSRV78  8152C6B2  FF03 000C 008AB050  
Freemain22:25:22.551810  32
01B2
   
00 01B2 008BA3E8  SVCR 9 _0001A314   00040520 000400C0  
22:25:22.551812  32
 07741000 8000  
   
00 01B2 008BA3E8  SVC  9 _0001A314   00040530 000400C0  
Delete  22:25:22.551814  32
 07741000 8000  
   
01 01B2 008BA1C8  DSP_24F4135C   1608 008789F8  
0001  01B2 01B2 22:25:22.551815  28
 07841000 8000  
   
00 01B2 008BA3E8  SUSP8174CF08  00708A30 LOCL   
    22:25:22.551815  32

   
01 01B2 008BA1C8  SVC 78 _24F4135E  E601 1608 008789F8  
Freemain22:25:22.551816  28
 07841000 8000  
   
01 01B2 008BA1C8  SVCR78 _24F4135E   1608 008789F8  
22:25:22.551831  28
 07841000 8000

It looks like the first SVC 78 at 24F4135E  never completed and was later 
retried.  I have seen   intervening trace entries from other processors between 
the start and finish of a SVC 78, but have never seen the SVC 78 repeated like 
that.  It gives the illusion that there was a  double freemain, but I   would 
think if that was the case the second SVC 78 would have encountered some type 
of x78 abend.

I am just curious if anyone else has seen a SVC 78 trace entry like above.

Thank you.

Paul   



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SLIP and ESTAE

2016-01-15 Thread Paul Schuster
Hello:

As designed, an ESTAE routine can recover from a (for example) 0C4 abend.  The 
abend can happen, but the  ESTAE can be coded so no one is the wiser than an 
abend has happened.

However, if there is a SLIP set for (for example) C=0C4, it seems the SLIP and 
its action parms will take precedence over the ESTAE.  So the nicely coded 
ESTAE which masks any abends is ignored, and the actual cause of the abend is 
exposed.

I guess under certain circumstances this can be a good thing, but is there a 
way to have an ESTAE or some other recovery routine be immune to any SLIP 
processing?

Thank you for any insight you can provide.

Paul

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Re: 64 bit ICMxx ?

2015-07-17 Thread Paul Schuster
 Recently got into some real 64-bit coding. Noticed that there is no
 64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then 
a JZ.
 
 It seems for a 64 bit register, there is no ICMxx 
R1,B'',64bitfield 
 equivalent. I have to do a   LG R1,64bitfield and then a LTGR R1,R1 
 and then the JZ.
 
 I'm sure this was not overlooked by the engineers, so am I missing 
 something?  Or
 is this just a new paradigm going forward with 64 bit code?

 On z9 and later machines, there is LT/LTG.

Jim Mulder   z/OS System Test   IBM Corp.  Poughkeepsie,  NY

Yes thank you I see that now I was not looking at a high enough dash version of 
the POO.

Paul

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64 bit ICMxx ?

2015-07-17 Thread Paul Schuster
Recently got into some real 64-bit coding. Noticed that there is no
64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then a JZ.

It seems for a 64 bit register, there is no ICMxx R1,B'',64bitfield 
equivalent. I have to do a   LG R1,64bitfield and then a LTGR R1,R1 and then 
the JZ.

I'm sure this was not overlooked by the engineers, so am I missing something?  
Or
is this just a new paradigm going forward with 64 bit code?

Thank you.

Paul

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Re: abend code BB7 ?

2014-09-07 Thread Paul Schuster
Ok.  It is not clear to me from the IEC615I message that this is a 'user' abend.
Also, since I am the owner of the '(nameremoved)' module, I know that 
it does not issue any ABEND 2999,,,USER  macro.  But  I will research more.

Thank you.

Paul

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abend code BB7 ?

2014-09-05 Thread Paul Schuster
Abend code BB7 does not seem  to be documented in the System Codes manual, even 
at the z.os 2.1 level.  As in:

IEC615I ABEND=000BB7-1101 OCCURRED IN THE (nameremoved) EXIT MODULE FOR 
DYNAMIC EXIT IGGPRE00_EXIT

The IEC615I message only indicates that abend  000BB7-110 occured in exit 
routine (nameremoved) .

Is this not documented on purpose, or has the manual not caught up with Dynamic 
Exits?  Does anyone know what the BB7 abend is caused by? 

Thank you.

Paul

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dynamic unallocation / permanent attribute

2014-04-10 Thread Paul Schuster
[Reposting due to the email disruption.]

Hi:

I dynalloc a data set with the 'permanent' attribute.

Later, I do a dynamic unallocate DD name without specifying 
the DUNUNALC key.  The SVC 99 completes RC=0, but the
DD is not de-allocated.

Specifying the DUNUNALC key also gets RC=0 from SVC 99
and the DD is de-allocated.

Shouldn't the fact that the DD is not de-allocated when
not specifying the DUNUNALC key generate a RC=4 or at
least some kind of reason code in S99INFO since the 
DD is not de-allocated?

A RC=0 should mean that the DD -really- was de-allocated.

Thank you.

Paul

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Re: IEFUSI and SYS.PROCLIB(INIT)

2013-02-11 Thread Paul Schuster
Well, this is actually personally of interest to me.  But trying to understand 
your reply seems to indicate that 1) IEFUSI can't control INIT/IEFIIC and 2) 
there is not a GUPI/exit that will allow the INIT to be controlled?  Is that 
the correct understanding?

Thank you.

Paul

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IEFUSI and SYS.PROCLIB(INIT)

2013-02-10 Thread Paul Schuster
Can the IEFUSI exit be used to control the above-the-16mline-limit for the  
INIT address space?  Specifically, I have a IEFUSI exit coded that indeed does 
look for a REGION=0M and then correctly changes the above the line limit to 
x'7fff' (about 1.57gb).  However, when I code a REGION=0M in the INIT PROC 
(the one that does  EXEC   PGM=IEFIIC and restart the initiator, it still shows 
(as observed by a monitoring product) an above-the-line limit of 32M. I have 
verified that SMFPRMxx is correct, as other started tasks will correctly get 
changed by IEFUSI to the 1.57gb limit.  It seems it is only the INIT EXEC 
PGM=IEFIIC that doesn't get changed.  The documentation for SCHEDxx PPT says 
IEFIIC will honor IEFUSI requests.  Is there something I am overlooking here?

Thank you.

Paul

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Re: mvcl/mvcle padding byte

2012-08-23 Thread Paul Schuster
Actually I am interested to know if using the padding byte of x'B8' would be 
beneficial in clearing storage for a program's save area/local dynamic storage 
area since the program's save area would definitely be referenced.

Thank you.

Paul

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mvcl/mvcle padding byte

2012-08-14 Thread Paul Schuster
The Principles of Operation state that a padding  byte of x'b0' or x'b8' can be 
used to influence the use of cache.  How much impact does this actually have on 
an MVCL(e) instruction?

Further text gives an example of when the pad byte is not 'b1'which it 
wouldn't be if you are specifying 'b0' or 'b8'. So evidently 'b1' also has 
special meaning?

Thank you.

Paul

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JFCB field question

2012-07-10 Thread Paul Schuster
Hi:

Is the field JFCBEXTL ever non-zero?  The comments in the JFCB dsect say it is 
the 


LENGTH OF BLOCK OF EXTRA VOLUME SERIAL NUMBERS
(BEYOND FIVE) 
 

but it seems no matter how many volumes I code for a JCL or dynamica allocation 
disk data set the field is always zero.  

Thank you.

Paul

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