Re: BSAM Read 31 bit mode
They could of had had a exlst on the DCBE with xl5 ds x for the code and xl4 for the address -Original Message- From: IBM Mainframe Discussion List On Behalf Of Binyamin Dissen Sent: Sunday, February 19, 2023 10:38 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 08:37:39 -0600 Paul Gilmartin <042bfe9c879d-dmarc-requ...@listserv.ua.edu> wrote: :>On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: :> :>>The fact that your code is AMODE 31 does not mean that the access method MUST :>>be above the line. : :>>The actual expansion had an XR 15,15 before the ICM. : :>>Why do you think that there is an issue? BALR does not change the AMODE. : :>With one line more context: :>>:>ICM 15,B'0111',49(R6) :>>:> BALR 14,15 : :>THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it :>must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? The ICM does not touch 0-7. And it is the access method address, not the SYNAD :>It's dismaying that after almost 4 decades programmers must be concerned with :>24-bit limitations. Library macros should be sensitive to some option such as :>OPTABLE and generate code accordingly. The cost of downward compatibility. One could argue that IBM should supply GLUE routines, but instead they did the DCBE. One wonders how much effort it is worth to support legacy access methods from above the bar. :>31-bit is underreaching. Should be 64. Reasonable people can disagree. -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
Thanks. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Sunday, February 19, 2023 9:23 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode Shmuel I looked that up or browsed the macro there is no reference rmode/amode 31 in the macro. I did try sysstate amode64 generated the same code. -Original Message- From: IBM Mainframe Discussion List On Behalf Of Seymour J Metz Sent: Saturday, February 18, 2023 8:40 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode What is on your SYSSTATE? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Friday, February 17, 2023 3:35 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: BSAM Read 31 bit mode Hi I see this documentation from IBM Addressing mode: When you issue the READ macro in 24-bit mode, provide only 24-bit addresses unless you code SF64 or SF64P. When you issue the READ macro in 31-bit addressing mode, provide only 31-bit addresses unless documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, the data area can reside above the 2 GB bar but you cannot issue READ in 64-bit mode. And yet my read macro expands to ICM 15,B'0111',49(R6) BALR 14,15 Does the address mode paragraph then mean AMODE 31 RMODE 24 In Addition the synad exit Which has Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register Bits Meaning 8-31 Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB Does this mean The DECB has to be AMODE 24 Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
> The combination with a mask of B'0111' limits addressing to 24 bits. > It does work in AMODE 31 and 24, but not on a 360. In this case it doesn't matter, because IBM uses bits 0-7 of that word in the DCB for flags, so 24 bits is all that's left. > A colleague, working for MIPS/SGI had to steadfastly refuse requests from > software >developers not to validate upper bits of 64-bit addresses, prohibiting their >use for flags. Not my monkeys, not my circus, but how do you spell "Hell, no"? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Paul Gilmartin [042bfe9c879d-dmarc-requ...@listserv.ua.edu] Sent: Sunday, February 19, 2023 12:52 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 17:14:14 +, Seymour J Metz wrote: >> THe ICM clears bits 0-7 of the (SYNAD?) address. > >It's the XR that clears bits 0-7, not the ICM. > The combination with a mask of B'0111' limits addressing to 24 bits. It does work in AMODE 31 and 24, but not on a 360. >That's not what OPTABLE is for; many macros test the globals set by SYSSTATE, >which is why it's there. > Thanks. >> 31-bit is underreaching. Should be 64. > >Agreed, unless technology advances much more rapidly than I expect. But 24-bit >was also underreaching when S/360 came out, given what was already on the >market. > A colleague, working for MIPS/SGI had to steadfastly refuse requests from software developers not to validate upper bits of 64-bit addresses, prohibiting their use for flags. Assembler is the wrong language for upward compatibility. -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Sun, 19 Feb 2023 17:14:14 +, Seymour J Metz wrote: >> THe ICM clears bits 0-7 of the (SYNAD?) address. > >It's the XR that clears bits 0-7, not the ICM. > The combination with a mask of B'0111' limits addressing to 24 bits. It does work in AMODE 31 and 24, but not on a 360. >That's not what OPTABLE is for; many macros test the globals set by SYSSTATE, >which is why it's there. > Thanks. >> 31-bit is underreaching. Should be 64. > >Agreed, unless technology advances much more rapidly than I expect. But 24-bit >was also underreaching when S/360 came out, given what was already on the >market. > A colleague, working for MIPS/SGI had to steadfastly refuse requests from software developers not to validate upper bits of 64-bit addresses, prohibiting their use for flags. Assembler is the wrong language for upward compatibility. -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
> THe ICM clears bits 0-7 of the (SYNAD?) address. It's the XR that clears bits 0-7, not the ICM. > It's dismaying that after almost 4 decades programmers must be concerned with > 24-bit limitations. Library macros should be sensitive to some option such as > OPTABLE and generate code accordingly. That's not what OPTABLE is for; many macros test the globals set by SYSSTATE, which is why it's there. > 31-bit is underreaching. Should be 64. Agreed, unless technology advances much more rapidly than I expect. But 24-bit was also underreaching when S/360 came out, given what was already on the market. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Paul Gilmartin [042bfe9c879d-dmarc-requ...@listserv.ua.edu] Sent: Sunday, February 19, 2023 9:37 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: >The fact that your code is AMODE 31 does not mean that the access method MUST >be above the line. > >The actual expansion had an XR 15,15 before the ICM. > >Why do you think that there is an issue? BALR does not change the AMODE. > With one line more context: >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? It's dismaying that after almost 4 decades programmers must be concerned with 24-bit limitations. Library macros should be sensitive to some option such as OPTABLE and generate code accordingly. 31-bit is underreaching. Should be 64. >On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: > >:>I see this documentation from IBM >:> >:>Addressing mode: When you issue the READ macro in 24-bit mode, provide only >:>24-bit addresses unless you code SF64 or SF64P. When you issue the READ >:>macro in 31-bit addressing mode, provide only 31-bit addresses unless >:>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, >:>the data area can reside above the 2 GB bar but you cannot issue READ in >:>64-bit mode. >:> >:>And yet my read macro expands to >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 >:> >:>Does the address mode paragraph then mean AMODE 31 RMODE 24 >:> >:>In Addition the synad exit Which has >:> >:>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and >:>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's >:>address to provide the address of the first CCW (QSAM only). Value may be >:>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit >:>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents >:>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register >:>Bits Meaning >:> >:>8-31 Address of the associated data event control block for BDAM, BPAM, and >:>BSAM unless bit 2 of register 1 is on; address of the status indicators >:>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the >:>failure occurred in CNTRL, POINT, or BSP and this field contains the address >:>on an internal BSAM ECB >:> >:>Does this mean The DECB has to be AMODE 24 -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
Both BALR and BASR change all bits of the link register. ICM with a mask of 7, however, does not alter bits 0-7. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Sunday, February 19, 2023 9:38 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode My mistake was the BALR in AMODE 31 doesn't kill bits 1 - 7 thanks -Original Message- From: IBM Mainframe Discussion List On Behalf Of Binyamin Dissen Sent: Sunday, February 19, 2023 5:16 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode The fact that your code is AMODE 31 does not mean that the access method MUST be above the line. The actual expansion had an XR 15,15 before the ICM. Why do you think that there is an issue? BALR does not change the AMODE. On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: :>Hi :> :> :> :>I see this documentation from IBM :> :> :> :>Addressing mode: When you issue the READ macro in 24-bit mode, provide only :>24-bit addresses unless you code SF64 or SF64P. When you issue the READ :>macro in 31-bit addressing mode, provide only 31-bit addresses unless :>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, :>the data area can reside above the 2 GB bar but you cannot issue READ in :>64-bit mode. :> :> :> :> :> :>And yet my read macro expands to ICM 15,B'0111',49(R6) :> :> BALR 14,15 :> :> :> :>Does the address mode paragraph then mean AMODE 31 RMODE 24 :> :> :> :> :> :>In Addition the synad exit :> :> :> :>Which has :> :> :> :>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and :>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's :>address to provide the address of the first CCW (QSAM only). Value may be :>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit :>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents :>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register :>Bits Meaning :> :> :> :>8-31 Address of the associated data event control block for BDAM, BPAM, and :>BSAM unless bit 2 of register 1 is on; address of the status indicators :>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the :>failure occurred in CNTRL, POINT, or BSP and this field contains the address :>on an internal BSAM ECB :> :> :> :>Does this mean The DECB has to be AMODE 24 :> :> :> :>Thanks :> :> :>-- :>For IBM-MAIN subscribe / signoff / archive access instructions, :>send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- Binyamin Dissen http://secure-web.cisco.com/13hbCrLlhji1mE1QcrvOfhv220KW1Zbxc753wJYo9J6fI6SSH4j4xbkROG3VX4x1gpt7mCqN4G8oMrCFgaKuUI3BQnPlEKy_brLCZmDkRAXsa3hz1Vhie_a63QG5TuyjONJ6U2_r09JZ6I_piAF-_qr9v2ZFSc0xv6W-w_k8Pkoljr5mbtMhUg1XHb6HTqz4Hp6wsKPwpR-DkqDNB8O4CnjZTUc6d2fFrWlbjs6Ahl-7nhdDsumi8j0VoQIy9J6oJQ0V8lLeWdZrhxYIkaXei1H62qt8yuBJARAIuJ77F15muF8wbVFVaxtymYI7bpJ7J5zr_Omk_MSvbV_A9ZvLy0QaeUzFraZOxt8yYWi7wCb1ZcDVXI2Ub9gYV5g8kC_IIGS87GSTsfxQy25_8Aq0AaD7DhjGN-FKHGDD14odIDVqK8kGQmmC-wUEjI2VU9x8r/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
I've never believed that a faster assembly justifies making a program harder to debug, modify or read, not even on the 650, which was slower than your wrist watch. I'll admit to using "16" instead of "CVTPTR", but I attribute it to youthful folly and haven't done it in decades. Since the 1970s I've been urging the use of mapping macros rather than "magic numbers". -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Binyamin Dissen [bdis...@dissensoftware.com] Sent: Sunday, February 19, 2023 11:28 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 10:12:31 -0600 Paul Gilmartin <042bfe9c879d-dmarc-requ...@listserv.ua.edu> wrote: :>On Sun, 19 Feb 2023 17:37:46 +0200, Binyamin Dissen wrote: :>>: :>>:>With one line more context: :>>:>>:>ICM 15,B'0111',49(R6) :>>:>>:> BALR 14,15 :>>The ICM does not touch 0-7. : :>It doesn't preserve them. Of course it does. The bits in the register are unchanged. Refer to the POPS. :>>And it is the access method address, not the SYNAD :>(These things would be more legible if IBM relied on USING.) :>OK. Not exactly GUPI. Although I once stole it to supply a custom access method :>(RMODE 24). Which would have required a DCBD expansion and a slower assembly. The later macros do rely on the mapping macros. -- Binyamin Dissen http://secure-web.cisco.com/1Iu6t_VM2pP0PFuBEZyogndUWdd5B7xu3Wsn20MkWWtoMfQ8u47mZVoxCZjFwwSDFCkTKoZZqoRI9SoTnpyAkwKpORkuFmcEvDMSu3-NXtU_R9MN12duHlKQH63UNYzfnzTpHX0Buace_D3nsLFCosM3RyViKzJFEeaBIDfjFbtH-GILWRs-Jxdi4g5zhKYjmLZ5rSO0K7lh2vH4MEFNn8GvfvTCH4R6LjLX78OzaqBWyaQ6zG-TmNb1JQyNk_UDRmq2HYMxh4yigx0kVQqV8-fRPpaQ0omWc6vZgsWVWLICQloewqOiMq2ec58QmI4HSbKxiuVwTJcqyz8plO_7KpGlLM7-v7F-WgsBSncTW4nLJD6baHGTRWxr0rGmxlFxB8fca7nrWIOs_ioSi72yGFi9FQe6Q1TughB1rQdPKAM4/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Sun, 19 Feb 2023 10:12:31 -0600 Paul Gilmartin <042bfe9c879d-dmarc-requ...@listserv.ua.edu> wrote: :>On Sun, 19 Feb 2023 17:37:46 +0200, Binyamin Dissen wrote: :>>: :>>:>With one line more context: :>>:>>:>ICM 15,B'0111',49(R6) :>>:>>:> BALR 14,15 :>>The ICM does not touch 0-7. : :>It doesn't preserve them. Of course it does. The bits in the register are unchanged. Refer to the POPS. :>>And it is the access method address, not the SYNAD :>(These things would be more legible if IBM relied on USING.) :>OK. Not exactly GUPI. Although I once stole it to supply a custom access method :>(RMODE 24). Which would have required a DCBD expansion and a slower assembly. The later macros do rely on the mapping macros. -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Sun, 19 Feb 2023 17:37:46 +0200, Binyamin Dissen wrote: >: >:>With one line more context: >:>>:>ICM 15,B'0111',49(R6) >:>>:> BALR 14,15 > >The ICM does not touch 0-7. > It doesn't preserve them. >And it is the access method address, not the SYNAD > (These things would be more legible if IBM relied on USING.) OK. Not exactly GUPI. Although I once stole it to supply a custom access method (RMODE 24). -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Sun, 19 Feb 2023 08:37:39 -0600 Paul Gilmartin <042bfe9c879d-dmarc-requ...@listserv.ua.edu> wrote: :>On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: :> :>>The fact that your code is AMODE 31 does not mean that the access method MUST :>>be above the line. : :>>The actual expansion had an XR 15,15 before the ICM. : :>>Why do you think that there is an issue? BALR does not change the AMODE. : :>With one line more context: :>>:>ICM 15,B'0111',49(R6) :>>:> BALR 14,15 : :>THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it :>must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? The ICM does not touch 0-7. And it is the access method address, not the SYNAD :>It's dismaying that after almost 4 decades programmers must be concerned with :>24-bit limitations. Library macros should be sensitive to some option such as :>OPTABLE and generate code accordingly. The cost of downward compatibility. One could argue that IBM should supply GLUE routines, but instead they did the DCBE. One wonders how much effort it is worth to support legacy access methods from above the bar. :>31-bit is underreaching. Should be 64. Reasonable people can disagree. -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
I think SYNAD can be RMODE 31 it’s a parms on the DCBE The other like abend and open I think are RMODE 24 Think IBM should have been consistent. Here is the doc from the using datasets manual. The exits are discussed on chapter 31 in the using datasets manual. Programming Considerations For BSAM, BPAM, and QSAM your SYNAD routine is entered with the addressability (24- or 31-bit) of when you issued the macro that caused entry to SYNAD. This typically is a CHECK, GET, or PUT macro. DCB SYNAD identifies a routine that resides below the line (RMODE is 24). DCBE SYNAD identifies a routine that may reside above the line. If it resides above the line, then all macros that might detect an I/O error must be issued in 31-bit mode. If both the DCB and DCBE specify SYNAD, the DCBE routine will b says if SYNAD is coded on the DCBE is above the line the other exits open and abend I believe are below Just wonder if you code an estate if that will get control before open abend -Original Message- From: IBM Mainframe Discussion List On Behalf Of Paul Gilmartin Sent: Sunday, February 19, 2023 9:38 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: >The fact that your code is AMODE 31 does not mean that the access >method MUST be above the line. > >The actual expansion had an XR 15,15 before the ICM. > >Why do you think that there is an issue? BALR does not change the AMODE. > With one line more context: >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? It's dismaying that after almost 4 decades programmers must be concerned with 24-bit limitations. Library macros should be sensitive to some option such as OPTABLE and generate code accordingly. 31-bit is underreaching. Should be 64. >On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: > >:>I see this documentation from IBM >:> >:>Addressing mode: When you issue the READ macro in 24-bit mode, >provide only :>24-bit addresses unless you code SF64 or SF64P. When you >issue the READ :>macro in 31-bit addressing mode, provide only 31-bit >addresses unless :>documentation says otherwise or you code SF64 or >SF64P. With SF64 or SF64P, :>the data area can reside above the 2 GB >bar but you cannot issue READ in :>64-bit mode. >:> >:>And yet my read macro expands to >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 >:> >:>Does the address mode paragraph then mean AMODE 31 RMODE 24 :> :>In >Addition the synad exit Which has :> :>Table 58. Register contents on >entry to SYNAD routine-BDAM, BPAM, BSAM, and :>QSAM Register Bits >Meaning 0 0-7 Value to be added to the status indicator's :>address to >provide the address of the first CCW (QSAM only). Value may be :>zero, >meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit >:>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register >contents :>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM >(continued) Register :>Bits Meaning :> >:>8-31 Address of the associated data event control block for BDAM, >BPAM, and :>BSAM unless bit 2 of register 1 is on; address of the >status indicators :>shown in Figure 109 on page 491 for QSAM. If bit 2 >of register 1 is on, the :>failure occurred in CNTRL, POINT, or BSP and >this field contains the address :>on an internal BSAM ECB :> :>Does >this mean The DECB has to be AMODE 24 -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
My mistake was the BALR in AMODE 31 doesn't kill bits 1 - 7 thanks -Original Message- From: IBM Mainframe Discussion List On Behalf Of Binyamin Dissen Sent: Sunday, February 19, 2023 5:16 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode The fact that your code is AMODE 31 does not mean that the access method MUST be above the line. The actual expansion had an XR 15,15 before the ICM. Why do you think that there is an issue? BALR does not change the AMODE. On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: :>Hi :> :> :> :>I see this documentation from IBM :> :> :> :>Addressing mode: When you issue the READ macro in 24-bit mode, provide only :>24-bit addresses unless you code SF64 or SF64P. When you issue the READ :>macro in 31-bit addressing mode, provide only 31-bit addresses unless :>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, :>the data area can reside above the 2 GB bar but you cannot issue READ in :>64-bit mode. :> :> :> :> :> :>And yet my read macro expands to ICM 15,B'0111',49(R6) :> :> BALR 14,15 :> :> :> :>Does the address mode paragraph then mean AMODE 31 RMODE 24 :> :> :> :> :> :>In Addition the synad exit :> :> :> :>Which has :> :> :> :>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and :>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's :>address to provide the address of the first CCW (QSAM only). Value may be :>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit :>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents :>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register :>Bits Meaning :> :> :> :>8-31 Address of the associated data event control block for BDAM, BPAM, and :>BSAM unless bit 2 of register 1 is on; address of the status indicators :>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the :>failure occurred in CNTRL, POINT, or BSP and this field contains the address :>on an internal BSAM ECB :> :> :> :>Does this mean The DECB has to be AMODE 24 :> :> :> :>Thanks :> :> :>-- :>For IBM-MAIN subscribe / signoff / archive access instructions, :>send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: >The fact that your code is AMODE 31 does not mean that the access method MUST >be above the line. > >The actual expansion had an XR 15,15 before the ICM. > >Why do you think that there is an issue? BALR does not change the AMODE. > With one line more context: >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? It's dismaying that after almost 4 decades programmers must be concerned with 24-bit limitations. Library macros should be sensitive to some option such as OPTABLE and generate code accordingly. 31-bit is underreaching. Should be 64. >On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: > >:>I see this documentation from IBM >:> >:>Addressing mode: When you issue the READ macro in 24-bit mode, provide only >:>24-bit addresses unless you code SF64 or SF64P. When you issue the READ >:>macro in 31-bit addressing mode, provide only 31-bit addresses unless >:>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, >:>the data area can reside above the 2 GB bar but you cannot issue READ in >:>64-bit mode. >:> >:>And yet my read macro expands to >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 >:> >:>Does the address mode paragraph then mean AMODE 31 RMODE 24 >:> >:>In Addition the synad exit Which has >:> >:>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and >:>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's >:>address to provide the address of the first CCW (QSAM only). Value may be >:>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit >:>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents >:>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register >:>Bits Meaning >:> >:>8-31 Address of the associated data event control block for BDAM, BPAM, and >:>BSAM unless bit 2 of register 1 is on; address of the status indicators >:>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the >:>failure occurred in CNTRL, POINT, or BSP and this field contains the address >:>on an internal BSAM ECB >:> >:>Does this mean The DECB has to be AMODE 24 -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
Shmuel I looked that up or browsed the macro there is no reference rmode/amode 31 in the macro. I did try sysstate amode64 generated the same code. -Original Message- From: IBM Mainframe Discussion List On Behalf Of Seymour J Metz Sent: Saturday, February 18, 2023 8:40 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode What is on your SYSSTATE? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Friday, February 17, 2023 3:35 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: BSAM Read 31 bit mode Hi I see this documentation from IBM Addressing mode: When you issue the READ macro in 24-bit mode, provide only 24-bit addresses unless you code SF64 or SF64P. When you issue the READ macro in 31-bit addressing mode, provide only 31-bit addresses unless documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, the data area can reside above the 2 GB bar but you cannot issue READ in 64-bit mode. And yet my read macro expands to ICM 15,B'0111',49(R6) BALR 14,15 Does the address mode paragraph then mean AMODE 31 RMODE 24 In Addition the synad exit Which has Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register Bits Meaning 8-31 Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB Does this mean The DECB has to be AMODE 24 Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
The fact that your code is AMODE 31 does not mean that the access method MUST be above the line. The actual expansion had an XR 15,15 before the ICM. Why do you think that there is an issue? BALR does not change the AMODE. On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: :>Hi :> :> :> :>I see this documentation from IBM :> :> :> :>Addressing mode: When you issue the READ macro in 24-bit mode, provide only :>24-bit addresses unless you code SF64 or SF64P. When you issue the READ :>macro in 31-bit addressing mode, provide only 31-bit addresses unless :>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, :>the data area can reside above the 2 GB bar but you cannot issue READ in :>64-bit mode. :> :> :> :> :> :>And yet my read macro expands to ICM 15,B'0111',49(R6) :> :> BALR 14,15 :> :> :> :>Does the address mode paragraph then mean AMODE 31 RMODE 24 :> :> :> :> :> :>In Addition the synad exit :> :> :> :>Which has :> :> :> :>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and :>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's :>address to provide the address of the first CCW (QSAM only). Value may be :>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit :>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents :>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register :>Bits Meaning :> :> :> :>8-31 Address of the associated data event control block for BDAM, BPAM, and :>BSAM unless bit 2 of register 1 is on; address of the status indicators :>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the :>failure occurred in CNTRL, POINT, or BSP and this field contains the address :>on an internal BSAM ECB :> :> :> :>Does this mean The DECB has to be AMODE 24 :> :> :> :>Thanks :> :> :>-- :>For IBM-MAIN subscribe / signoff / archive access instructions, :>send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
What is on your SYSSTATE? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Friday, February 17, 2023 3:35 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: BSAM Read 31 bit mode Hi I see this documentation from IBM Addressing mode: When you issue the READ macro in 24-bit mode, provide only 24-bit addresses unless you code SF64 or SF64P. When you issue the READ macro in 31-bit addressing mode, provide only 31-bit addresses unless documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, the data area can reside above the 2 GB bar but you cannot issue READ in 64-bit mode. And yet my read macro expands to ICM 15,B'0111',49(R6) BALR 14,15 Does the address mode paragraph then mean AMODE 31 RMODE 24 In Addition the synad exit Which has Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register Bits Meaning 8-31 Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB Does this mean The DECB has to be AMODE 24 Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: BSAM Read 31 bit mode
On Fri, Feb 17, 2023 at 03:35:35PM -0500, Joseph Reichman wrote: > And yet my read macro expands to ICM 15,B'0111',49(R6) > > BALR 14,15 I can't see your read macro call, but if it's inline the macro is going to generate the DECB inline with the code. Since the DECB must be 24 bit addressable the code must be too. Perhaps the macro knows this and thus knows that the ICM will work... > Does this mean The DECB has to be AMODE 24 DFSMS Macro Instructions for Data Sets Version 2 Release 2 SC23-6852-03 see the section in Chapter 5. Non-VSAM macro descriptions Data above the 16MB line If the issuer of an access method macro executes in 31-bit addressing mode, the following must have valid 31-bit addresses but must reside below the 16 MB line: * DECB (BSAM). * DCB address on any macro (including the DECB) or in a register. * BSAM or BPAM buffers obtained by OPEN (BSAM). OPEN obtains BSAM or BPAM buffers only when you code BUFNO on the DCB macro or the DD statement. There's a lot more in this manual around this area. It appears the later manuals dropped this section... -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
BSAM Read 31 bit mode
Hi I see this documentation from IBM Addressing mode: When you issue the READ macro in 24-bit mode, provide only 24-bit addresses unless you code SF64 or SF64P. When you issue the READ macro in 31-bit addressing mode, provide only 31-bit addresses unless documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, the data area can reside above the 2 GB bar but you cannot issue READ in 64-bit mode. And yet my read macro expands to ICM 15,B'0111',49(R6) BALR 14,15 Does the address mode paragraph then mean AMODE 31 RMODE 24 In Addition the synad exit Which has Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register Bits Meaning 8-31 Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB Does this mean The DECB has to be AMODE 24 Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
