Re: 64 bit ICMxx ?
On 19 July 2015 at 11:27, John McKown john.archie.mck...@gmail.com wrote: Hum, just contemplating this. And wondering why IBM didn't do it. There are a lot of other instructions in the ISA which seem, to me, to have lesser utility. So I'm just posting some rambling thoughts. I am looking in the -10 POPS manual on the various instruction formats. I am not a hardware engineer. But I guess that such formats are standardized in order to group them into classes. Each of which has some sort of hardware support. There appear, to me, to be four classes of instructions which are what I think of as pertaining to a single register as a direct operand (as opposed to indirect such as use in a base or index). RX (two subclasses), RXY (two subclasses), RSY (two subclasses). [...] Actually, there is not _any_ currently defined class, as described on page 5-4 of the -10 POPS, into which such an IC instruction could fit. Now, the RXE format has 4 unused bits in it. So perhaps the engineers could make that into two subclasses A -a subclass which only uses 4 bits as at present, and a -b subclass which uses all 8 bit. That gets us an IC with base+12 bit displacement. Now we need to find where to put base+20 bit displacement and an immediate. For the immediate, they could use a new RIE variant (it already has 7) which has a 8 bit mask, similar to the -a variant which has a 4 bit mask. As best as I can see, this would require a new RSL subclass which has an 8 bit mask. I don't think for the likely uses for an ICMG that there is much call for a Y version. In most code I've seen, except where it is being used like LT, ICM is typically used with a zero or small displacement from a moving base register that is really a very local base for a data item. A more important constraint, or at least consideration, is that the mask field should be modifiable by an EXecute instruction, as it is with ICM[x]. This constrains the mask to being in bits 8-15 of the instruction, which could therefore be a single-byte opcode or a two-byte one where the second byte is not in bits 8-15. I don't think there are any instructions that, as you put it pertain[...] to a single register as a direct operand (as opposed to indirect such as use in a base or index) that have that target register not specified in bits 8-15. Another approach would be an instruction of RR[x] format, where the storage operand address is in a register, and the mask is in either a specified register or a hardcoded one (R0, perhaps). This might even allow for a mask of more than 8 bits (64, presumably), leading to a sort of ICMD scheme where the mask applies to more than one register. With the mask in a register, the ability to specify the mask via EXecute becomes unimportant. Well, small fantasies for a Monday morning. Presumably the compiler writers who seem to generate hardware design these days have found no use for such schemes. Tony H. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
In 7660897243938495.wa.pgs4ibmmainpacbell@listserv.ua.edu, on 07/17/2015 at 07:03 PM, Paul Schuster pgs4ibmm...@pacbell.net said: I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. LTG R1,64bitfield JZNULL I'm sure this was not overlooked by the engineers, Well, I'd like an ICMG with an 8-bit mask for more general use. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
On Sat, Jul 18, 2015 at 11:43 PM, Shmuel Metz (Seymour J.) shmuel+ibm-m...@patriot.net wrote: In 7660897243938495.wa.pgs4ibmmainpacbell@listserv.ua.edu, on 07/17/2015 at 07:03 PM, Paul Schuster pgs4ibmm...@pacbell.net said: I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. LTG R1,64bitfield JZNULL I'm sure this was not overlooked by the engineers, Well, I'd like an ICMG with an 8-bit mask for more general use. -- ​Hum, just contemplating this. And wondering why IBM didn't do it. There are a lot of other instructions in the ISA which seem, to me, to have lesser utility. So I'm just posting some rambling thoughts. There is the ICM and ICMH which, combined, could be use to emulate this. I am looking in the -10 POPS manual on the various instruction formats. I am not a hardware engineer. But I guess that such formats are standardized in order to group them into classes. Each of which has some sort of hardware support. There appear, to me, to be four classes of instructions which are what I think of as pertaining to a single register as a direct operand (as opposed to indirect such as use in a base or index). RX (two subclasses), RXY (two subclasses), RSY (two subclasses). The current Insert Character instructions are in the RX (subclass a), RXY (subclass a), RS (subclass b), and RSY (subclass b). All of these classes have all of their bits utilized. So there's no room in them for another 4 bits of mask. The only format in the -10 POPS which currently has 8 bits of masking is the VRR class, subclasses -b, -d, and -e. But that doesn't seem like a good class in which to put a IC type instruction. Just doesn't fit aesthetically. Actually, there is not _any_ currently defined class, as described on page 5-4 of the -10 POPS, into which such an IC instruction could fit. Now, the RXE format has 4 unused bits in it. So perhaps the engineers could make that into two subclasses A -a subclass which only uses 4 bits as at present, and a -b subclass which uses all 8 bit. That gets us an IC with base+12 bit displacement. Now we need to find where to put base+20 bit displacement and an immediate. For the immediate, they could use a new RIE variant (it already has 7) which has a 8 bit mask, similar to the -a variant which has a 4 bit mask. As best as I can see, this would require a new RSL subclass which has an 8 bit mask. I have _no_ idea how complicated it is to implement a new instruction format. But that is the first thing which would be required to implement an IC type instruction which does 8 bits. Seems a bit much for a single instruction. As an aside, if the CC is unimportant, then simply doing an ICM followed by an ICMH should suffice. If the CC is important, that is a bit more difficult. And today is Sunday and I'm not in the mood to try to figure out how to do it in a macro. But I'm sure that it's possible by using another register and SPM/IPM to maintain the condition code properly. Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- Schrodinger's backup: The condition of any backup is unknown until a restore is attempted. Yoda of Borg, we are. Futile, resistance is, yes. Assimilated, you will be. He's about as useful as a wax frying pan. 10 to the 12th power microphones = 1 Megaphone Maranatha! John McKown -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
Recently got into some real 64-bit coding. Noticed that there is no 64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then a JZ. It seems for a 64 bit register, there is no ICMxx R1,B'',64bitfield equivalent. I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. I'm sure this was not overlooked by the engineers, so am I missing something? Or is this just a new paradigm going forward with 64 bit code? On z9 and later machines, there is LT/LTG. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
Recently got into some real 64-bit coding. Noticed that there is no 64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then a JZ. It seems for a 64 bit register, there is no ICMxx R1,B'',64bitfield equivalent. I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. I'm sure this was not overlooked by the engineers, so am I missing something? Or is this just a new paradigm going forward with 64 bit code? On z9 and later machines, there is LT/LTG. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY Yes thank you I see that now I was not looking at a high enough dash version of the POO. Paul -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
Paul, Did you try ICMH (Insert Characters Under Mask High) ? Thanks, Kolusu IBM Mainframe Discussion List IBM-MAIN@LISTSERV.UA.EDU wrote on 07/17/2015 05:03:56 PM: From: Paul Schuster pgs4ibmm...@pacbell.net To: IBM-MAIN@LISTSERV.UA.EDU Date: 07/17/2015 05:04 PM Subject: 64 bit ICMxx ? Sent by: IBM Mainframe Discussion List IBM-MAIN@LISTSERV.UA.EDU Recently got into some real 64-bit coding. Noticed that there is no 64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then a JZ. It seems for a 64 bit register, there is no ICMxx R1,B'',64bitfield equivalent. I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. I'm sure this was not overlooked by the engineers, so am I missing something? Or is this just a new paradigm going forward with 64 bit code? Thank you. Paul -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: 64 bit ICMxx ?
Paul, There is an ICMH instruction, for which the mask bits indicate bit positions 0-7, 8-15, 16-23, and 24-31 of a 64-bit register. This instruction uses a 20-bit signed offset. There is also an ICMY instruction, which is equivalent to the ICM instruction except that this instruction uses a 20-bit signed offset. John P. Baker -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Paul Schuster Sent: Friday, July 17, 2015 8:04 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: 64 bit ICMxx ? Recently got into some real 64-bit coding. Noticed that there is no 64-bit version of ICM. I am used to doing ICM R1,B'',FIELD and then a JZ. It seems for a 64 bit register, there is no ICMxx R1,B'',64bitfield equivalent. I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then the JZ. I'm sure this was not overlooked by the engineers, so am I missing something? Or is this just a new paradigm going forward with 64 bit code? Thank you. Paul -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
