[Intel-gfx] [PATCH 1/2] drm/i915:merge ring_put/get_irq into bsd_ring_put/get_irq
This patch is a clean-up, since ring_put_irq/ring_get_irq are only used
by bsd_ring_put_irq and bsd_ring_get_irq.
This patch also serve the further fix about irq miss in bsd ring on g4x.
Interrupt control interfaces are different between g4x and ironlake,
they use different interrupt control reg addresses and interrupt flags.
Rather than handle the two differences in two put-get pairs, it's better
to merge them and put conditional judgment about dev version in one pair,
and handle them.
Remove ring_put_irq/ring_get_irq:drivers/gpu/drm/i915/intel_ringbuffer.c.
Expand the code in bsd_ring_put_irq/bsd_ring_get_irq.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 +++---
1 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9e6f71..06c921f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,7 +600,7 @@ ring_add_request(struct intel_ring_buffer *ring,
}
static bool
-ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
+gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
@@ -609,27 +609,33 @@ ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, flag);
+ if (ring-irq_refcount++ == 0) {
+ ring-irq_mask = ~rflag;
+ I915_WRITE_IMR(ring, ring-irq_mask);
+ ironlake_enable_irq(dev_priv, gflag);
+ }
spin_unlock(ring-irq_lock);
return true;
}
static void
-ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
+gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0)
- ironlake_disable_irq(dev_priv, flag);
+ if (--ring-irq_refcount == 0) {
+ ring-irq_mask |= rflag;
+ I915_WRITE_IMR(ring, ring-irq_mask);
+ ironlake_disable_irq(dev_priv, gflag);
+ }
spin_unlock(ring-irq_lock);
}
static bool
-gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
@@ -638,42 +644,24 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32
gflag, u32 rflag)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0) {
- ring-irq_mask = ~rflag;
- I915_WRITE_IMR(ring, ring-irq_mask);
- ironlake_enable_irq(dev_priv, gflag);
- }
+ if (ring-irq_refcount++ == 0)
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
spin_unlock(ring-irq_lock);
return true;
}
-
static void
-gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0) {
- ring-irq_mask |= rflag;
- I915_WRITE_IMR(ring, ring-irq_mask);
- ironlake_disable_irq(dev_priv, gflag);
- }
+ if (--ring-irq_refcount == 0)
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
spin_unlock(ring-irq_lock);
}
-static bool
-bsd_ring_get_irq(struct intel_ring_buffer *ring)
-{
- return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
-}
-static void
-bsd_ring_put_irq(struct intel_ring_buffer *ring)
-{
- ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
-}
-
static int
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32
length)
{
--
1.7.4.4
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[Intel-gfx] [PATCH 2/2] drm/i915:fix irq miss in bsd ring for g4x
This patch depends on patch drm/i915:merge ring_put/get_irq into
bsd_ring_put/get_irq
On g4x, user interrupt in bsd ring is missed.
g4x and ironlake share the same bsd_ring, but their interrupt control
interfaces are different, g4x use I915 while ironlake use GT.
The interrupt mask reg address on g4x should be IMR, user interrupt flag
in bsd ring on g4x is I915_BSD_USER_INTERRUPT
Add conditional judgment about dev version to find out which interrupt
control interface is to use.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 06c921f..48c21aa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -644,8 +644,12 @@ bsd_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ if (ring-irq_refcount++ == 0) {
+ if (IS_G4X(dev))
+ i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
spin_unlock(ring-irq_lock);
return true;
@@ -657,8 +661,12 @@ bsd_ring_put_irq(struct intel_ring_buffer *ring)
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0)
- ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ if (--ring-irq_refcount == 0) {
+ if (IS_G4X(dev))
+ i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
spin_unlock(ring-irq_lock);
}
--
1.7.4.4
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[Intel-gfx] g4x bsd user irq miss fix v2
We need this fix to enable h264 decoding on g4x platform. There are two patches to fix the problem. 1. merge ring irq put-get pair into bsd_ring irq put-get pair 2. add conditional judgment about dev version to use different interrupt control interfaces. As the patches show, g4x has a different interrupt control interface. So an if-else statement is needed. And make all differences in a put-get pair is reasonable, since the differences are neither so many to use another date structure nor so few to present by an argument. Thanks, Feng, Boqun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915:merge ring_put/get_irq into bsd_ring_put/get_irq v2
This patch is a clean-up, since ring_put_irq/ring_get_irq are only used
by bsd_ring_put_irq and bsd_ring_get_irq.
This patch also serve the further fix about irq miss in bsd ring on g4x.
Interrupt control interfaces are different between g4x and ironlake,
they use different interrupt control reg addresses and interrupt flags.
Rather than handle the two differences in two put-get pairs, it's better
to merge them and put conditional judgment about dev version in one pair,
and handle them.
Remove ring_put_irq/ring_get_irq:drivers/gpu/drm/i915/intel_ringbuffer.c.
Expand the code in bsd_ring_put_irq/bsd_ring_get_irq.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 +++---
1 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9e6f71..06c921f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,7 +600,7 @@ ring_add_request(struct intel_ring_buffer *ring,
}
static bool
-ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
+gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
@@ -609,27 +609,33 @@ ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, flag);
+ if (ring-irq_refcount++ == 0) {
+ ring-irq_mask = ~rflag;
+ I915_WRITE_IMR(ring, ring-irq_mask);
+ ironlake_enable_irq(dev_priv, gflag);
+ }
spin_unlock(ring-irq_lock);
return true;
}
static void
-ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
+gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0)
- ironlake_disable_irq(dev_priv, flag);
+ if (--ring-irq_refcount == 0) {
+ ring-irq_mask |= rflag;
+ I915_WRITE_IMR(ring, ring-irq_mask);
+ ironlake_disable_irq(dev_priv, gflag);
+ }
spin_unlock(ring-irq_lock);
}
static bool
-gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
@@ -638,42 +644,24 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32
gflag, u32 rflag)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0) {
- ring-irq_mask = ~rflag;
- I915_WRITE_IMR(ring, ring-irq_mask);
- ironlake_enable_irq(dev_priv, gflag);
- }
+ if (ring-irq_refcount++ == 0)
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
spin_unlock(ring-irq_lock);
return true;
}
-
static void
-gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
struct drm_device *dev = ring-dev;
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0) {
- ring-irq_mask |= rflag;
- I915_WRITE_IMR(ring, ring-irq_mask);
- ironlake_disable_irq(dev_priv, gflag);
- }
+ if (--ring-irq_refcount == 0)
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
spin_unlock(ring-irq_lock);
}
-static bool
-bsd_ring_get_irq(struct intel_ring_buffer *ring)
-{
- return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
-}
-static void
-bsd_ring_put_irq(struct intel_ring_buffer *ring)
-{
- ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
-}
-
static int
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32
length)
{
--
1.7.4.4
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[Intel-gfx] [PATCH 2/2] drm/i915:fix irq miss in bsd ring for g4x v2
This patch depends on patch drm/i915:merge ring_put/get_irq into
bsd_ring_put/get_irq
On g4x, user interrupt in bsd ring is missed.
g4x and ironlake share the same bsd_ring, but their interrupt control
interfaces are different, g4x use I915 while ironlake use GT.
The interrupt mask reg address on g4x should be IMR, user interrupt flag
in bsd ring on g4x is I915_BSD_USER_INTERRUPT
Add conditional judgment about dev version to find out which interrupt
control interface is to use.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 06c921f..48c21aa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -644,8 +644,12 @@ bsd_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ if (ring-irq_refcount++ == 0) {
+ if (IS_G4X(dev))
+ i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
spin_unlock(ring-irq_lock);
return true;
@@ -657,8 +661,12 @@ bsd_ring_put_irq(struct intel_ring_buffer *ring)
drm_i915_private_t *dev_priv = dev-dev_private;
spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0)
- ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ if (--ring-irq_refcount == 0) {
+ if (IS_G4X(dev))
+ i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
spin_unlock(ring-irq_lock);
}
--
1.7.4.4
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[Intel-gfx] [PATCH] drm/i915: Try to clarify the function and file naming
To the casual observer, our naming is a mess. However, we did have a plan for how our functions should be named, just we were lax and let cruft accrue. Explain how it was meant to look in the hope that someday it will all make sense. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/README | 76 +++ 1 files changed, 76 insertions(+), 0 deletions(-) create mode 100644 drivers/gpu/drm/i915/README diff --git a/drivers/gpu/drm/i915/README b/drivers/gpu/drm/i915/README new file mode 100644 index 000..4aef49b --- /dev/null +++ b/drivers/gpu/drm/i915/README @@ -0,0 +1,76 @@ +General notes on function naming + + +The goal is prefix the function names with the first chipset that work with. +So we have: + intel_ - general functions, used by all + i8xx_ - gen2 + i915_ - gen3 (915/945) + [NB: do not confuse with i915_gem which should be intel_gem by this logic!] + g33_, pineview_ - gen3 (blk/pnv) # perhaps just g33 as pnv = g33 + mobile? + i965_ - gen4 (brw/crl) + g4x_ - gen4 (egl/ctg) + ironlake_, sandybridge_, ivybridge_ - etc + +So ironlake can call a g4x function, but never vice versa. Note that different +generations share different components, but we may generalise and say +that: + +* sandybridge/ivybridge are roughly equivalent with a little overlap with +ironlake. + +* ironlake and g4x share a few common components. + +* g4x was a fairly distinct departure for the display engine from i965 +(though it shares almost the same render engine). + +* g33 included some of the same display engine reconfiguration as g4x, but +in its own unique fashion on top of i915. + +* i915 and i8xx are fairly independent, and each gen2 chipset subtly +different from each other. + +Also note that there is also a split between desktop versions of the +chipsets and their mobile variants. The differences are usually common +on all generations, but their implementation vary. + +General notes on file naming + + +File naming is a little more complex due to hysterical raisons that we +have not overcome yet. Originally the driver was a small interface for +DRI1, essentially to allow shared ringbuffer usage but all command +execution and memory management was done in userspace. + +This is the bulk of i915_dma.c, with the saving of state for suspend and +resume in i915_suspend.c. + +Then we introduced GEM and built a very solid buffer manager with an +entirely new interface for DRI2. + +These files live in i915_gem*.c, but they overlap somewhat with +i915_dma.c - a ceaseless source of unamusing bugs. When adding new +functionality, please do consider clearly segregating it and putting the +fundamental features into the core GEM namespace. + +* i915_gem.c is the core buffer management and domain tracking, +providing facilities for the rest of GEM + +* i915_gem_execbuffer.c is solely tasked with performing the relocations +on the incoming commands and submitting them to the ring. + +* i915_gem_evict.c contains the LRU fair-eviction policy. + +* i915_gem_gtt.c is the interface through which we program the GTT for +the translation of the buffer objects from the physical pages into the +GPU virtual addresses. + +* i915_gem_tiling.c is to centralise the complexity of device specific +programming and limitations of fences. + +Files prefixed with intel_* support (and abstract in some cases) common +features found across many generations, such as the ringbuffers for +command submission and the display engine. The core of the display +engine, the central driver for modesetting, is intel_display.c with +encoder specific functionality living in intel_dvo.c (i8xx-only digital +video out), intel_sdvo.c, intel_hdmi.c, intel_dp.c. -- 1.7.4.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915:fix irq miss in bsd ring for g4x v2
On Thu, 28 Apr 2011 15:22:05 +0800, Feng, Boqun boqun.f...@intel.com wrote: This patch depends on patch drm/i915:merge ring_put/get_irq into bsd_ring_put/get_irq I'm being a nuisance, but this is the wrong way around. This a bug fix and needs to apply cleanly on top of -fixes and marked for stable. The cleanup patch is something we can then do at our leisure and so goes in through next. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SandyBridge encoding code merged to libva master
On Wed, 2011-04-27 at 11:07 +0800, Zou, Nanhai wrote: Hi, We have merged HW accelerated SandyBridge encoding code to libva master branch. At this point we support I frame and P frame encoding for H.264 main profile. B frame support, frame rate control, performance tuning and quality improvement will come in next quarter. We will provide a simple test program soon to demonstrate how to use the encoding API. You can use the simple program 'avcenc' under libva dir/test/encode for testing. The usage is avcenc width height input file output file [qp] qp is optional. Thanks Haihao ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915:fix irq miss in bsd ring for g4x v2
I got it. Thanks -Boqun -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, April 28, 2011 4:03 PM To: Feng, Boqun; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915:fix irq miss in bsd ring for g4x v2 On Thu, 28 Apr 2011 15:22:05 +0800, Feng, Boqun boqun.f...@intel.com wrote: This patch depends on patch drm/i915:merge ring_put/get_irq into bsd_ring_put/get_irq I'm being a nuisance, but this is the wrong way around. This a bug fix and needs to apply cleanly on top of -fixes and marked for stable. The cleanup patch is something we can then do at our leisure and so goes in through next. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/ringbuffer: kill snb blt workaround
Bleh, I've fat-fingered the fdo address on the first submission, to which Eric replied. Pasting his response below: On Wed, 27 Apr 2011 22:33:35 +0200, Daniel Vetter daniel.vet...@ffwll.ch wrote: This was just to facilitate product enablement with pre-production hw. Allows us to kill quite a bit of cruft. Cc: Eric Anholt e...@anholt.net Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Reviewed-by: Eric Anholt e...@anholt.net -- Daniel Vetter daniel.vet...@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Try to clarify the function and file naming
On Thu, 28 Apr 2011 15:40:43 +0700, Magnus Kessler magnus.kess...@gmx.net wrote: On Thursday 28 April 2011 08:58:18 Chris Wilson wrote: +General notes on file naming + + +File naming is a little more complex due to hysterical raisons that we ^^ You probably mean historical Actually I meant hysterical *raisins*! ;) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] fix irq miss in bsd ring on g4x v3
Reverse the order of patches. There are two patches 1. fix user irq miss in BSD ring on g4x 2. clean up unused functions Feng, Boqun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: fix user irq miss in BSD ring on g4x
On g4x, user interrupt in BSD ring is missed.
g4x and ironlake share the same bsd_ring, but their interrupt control
interfaces are different. On g4x i915_enable_irq and i915_disable_irq
are used to enable/disable irq,and user interrupt flag in BSD ring on
g4x is I915_BSD_USER_INTERRUPT.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 29 +++--
1 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9e6f71..c4504a2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -666,12 +666,37 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32
gflag, u32 rflag)
static bool
bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
- return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
+ struct drm_device *dev = ring-dev;
+ drm_i915_private_t *dev_priv = dev-dev_private;
+
+ if (!dev-irq_enabled)
+ return false;
+
+ spin_lock(ring-irq_lock);
+ if (ring-irq_refcount++ == 0) {
+ if (IS_G4X(dev))
+ i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
+ spin_unlock(ring-irq_lock);
+
+ return true;
}
static void
bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
- ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
+ struct drm_device *dev = ring-dev;
+ drm_i915_private_t *dev_priv = dev-dev_private;
+
+ spin_lock(ring-irq_lock);
+ if (--ring-irq_refcount == 0) {
+ if (IS_G4X(dev))
+ i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
+ spin_unlock(ring-irq_lock);
}
static int
--
1.7.4.4
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[Intel-gfx] [PATCH 2/2] drm/i915: clean up unused ring_get_irq/ring_put_irq functions
This patch depends on patch drm/i915: fix user irq miss in BSD ring on
g4x.
Once the previous patch apply, ring_get_irq/ring_put_irq become unused.
So simply remove them.
Signed-off-by: Feng, Boqun boqun.f...@intel.com
Reviewed-by: Xiang, Haihao haihao.xi...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 29 -
1 files changed, 0 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c4504a2..ce9bf5f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,35 +600,6 @@ ring_add_request(struct intel_ring_buffer *ring,
}
static bool
-ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
-{
- struct drm_device *dev = ring-dev;
- drm_i915_private_t *dev_priv = dev-dev_private;
-
- if (!dev-irq_enabled)
- return false;
-
- spin_lock(ring-irq_lock);
- if (ring-irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, flag);
- spin_unlock(ring-irq_lock);
-
- return true;
-}
-
-static void
-ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
-{
- struct drm_device *dev = ring-dev;
- drm_i915_private_t *dev_priv = dev-dev_private;
-
- spin_lock(ring-irq_lock);
- if (--ring-irq_refcount == 0)
- ironlake_disable_irq(dev_priv, flag);
- spin_unlock(ring-irq_lock);
-}
-
-static bool
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring-dev;
--
1.7.4.4
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: re-enable rc6 for ironlake
On Wed, Apr 27, 2011 at 03:49:40PM -0700, Jesse Barnes wrote: On Wed, 27 Apr 2011 23:03:14 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: We should probably just enable fbc on the pipe connected to the internal panel (if any) and keep it disabled otherwise. On Arrandale, fbc is potentially a bigger win than rc6 - but is also a potential loss - right? No, I think rc6 is still a much bigger win even on Arrandale (iirc 1W for rc6, ~0.5W for fbc best case). And yeah, there is the potential for increased power consumption when fbc is enabled if a framebuffer that doesn't compress very well continues to get re-compressed over a long period of time. Jesse The last tests that I ran it seemed we needed to be really careful about when to turn on FBC on for Arrandale as noted in the bug that Chris assigned to me below :). I did some rc6 tests prior to the FBC tests and can't find my notes, but I actually recall it being closer to 2W. https://bugs.freedesktop.org/show_bug.cgi?id=31742 Ben ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c | 12 ++
drivers/gpu/drm/i915/i915_drv.h |6 +
drivers/gpu/drm/i915/i915_irq.c | 45 +-
3 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 3b69f38..2f653c2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,6 +1253,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_modeset_init(dev);
+ if (HAS_PCH_SPLIT(dev)) {
+ dev-driver-irq_handler = ironlake_irq_handler;
+ dev-driver-irq_preinstall = ironlake_irq_preinstall;
+ dev-driver-irq_postinstall = ironlake_irq_postinstall;
+ dev-driver-irq_uninstall = ironlake_irq_uninstall;
+ } else {
+ dev-driver-irq_preinstall = i915_driver_irq_preinstall;
+ dev-driver-irq_postinstall = i915_driver_irq_postinstall;
+ dev-driver-irq_uninstall = i915_driver_irq_uninstall;
+ dev-driver-irq_handler = i915_driver_irq_handler;
+ }
+
ret = drm_irq_install(dev);
if (ret)
goto cleanup_vga_switcheroo;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 05a6929..4841901 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1024,6 +1024,12 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
extern void i915_driver_irq_preinstall(struct drm_device * dev);
extern int i915_driver_irq_postinstall(struct drm_device *dev);
extern void i915_driver_irq_uninstall(struct drm_device * dev);
+
+extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
+extern void ironlake_irq_preinstall(struct drm_device *dev);
+extern int ironlake_irq_postinstall(struct drm_device *dev);
+extern void ironlake_irq_uninstall(struct drm_device *dev);
+
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c0466e..a58d477 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,8 +448,9 @@ static void pch_irq_handler(struct drm_device *dev)
DRM_DEBUG_DRIVER(PCH transcoder A underrun interrupt\n);
}
-static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
+irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
{
+ struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
int ret = IRQ_NONE;
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
@@ -457,6 +458,8 @@ static irqreturn_t ironlake_irq_handler(struct drm_device
*dev)
struct drm_i915_master_private *master_priv;
u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
+ atomic_inc(dev_priv-irq_received);
+
if (IS_GEN6(dev))
bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
@@ -1103,9 +1106,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
atomic_inc(dev_priv-irq_received);
- if (HAS_PCH_SPLIT(dev))
- return ironlake_irq_handler(dev);
-
iir = I915_READ(IIR);
if (INTEL_INFO(dev)-gen = 4)
@@ -1562,10 +1562,15 @@ repeat:
/* drm_dma.h hooks
*/
-static void ironlake_irq_preinstall(struct drm_device *dev)
+void ironlake_irq_preinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ atomic_set(dev_priv-irq_received, 0);
+
+ INIT_WORK(dev_priv-hotplug_work, i915_hotplug_work_func);
+ INIT_WORK(dev_priv-error_work, i915_error_work_func);
+
I915_WRITE(HWSTAM, 0xeffe);
/* XXX hotplug from PCH */
@@ -1585,7 +1590,7 @@ static void ironlake_irq_preinstall(struct drm_device
*dev)
POSTING_READ(SDEIER);
}
-static int ironlake_irq_postinstall(struct drm_device *dev)
+int ironlake_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
/* enable kind of interrupts always enabled */
@@ -1594,6 +1599,13 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
u32 render_irqs;
u32 hotplug_mask;
+ DRM_INIT_WAITQUEUE(dev_priv-ring[RCS].irq_queue);
+ if (HAS_BSD(dev))
+ DRM_INIT_WAITQUEUE(dev_priv-ring[VCS].irq_queue);
+ if (HAS_BLT(dev))
+ DRM_INIT_WAITQUEUE(dev_priv-ring[BCS].irq_queue);
+
+ dev_priv-vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
dev_priv-irq_mask
[Intel-gfx] [PATCH 01/19] drm/i915: make FDI training a display function
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_display.c |7 +++
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0296967..05a6929 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,7 +209,7 @@ struct drm_i915_display_funcs {
struct drm_display_mode *adjusted_mode,
int x, int y,
struct drm_framebuffer *old_fb);
-
+ void (*fdi_link_train)(struct drm_crtc *crtc);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 62f9e52..0dadc8e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2465,10 +2465,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
u32 reg, temp;
/* For PCH output, training FDI link */
- if (IS_GEN6(dev))
- gen6_fdi_link_train(crtc);
- else
- ironlake_fdi_link_train(crtc);
+ dev_priv-display.fdi_link_train(crtc);
intel_enable_pch_pll(dev_priv, pipe);
@@ -7290,6 +7287,7 @@ static void intel_init_display(struct drm_device *dev)
Disable CxSR\n);
dev_priv-display.update_wm = NULL;
}
+ dev_priv-display.fdi_link_train =
ironlake_fdi_link_train;
} else if (IS_GEN6(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv-display.update_wm =
sandybridge_update_wm;
@@ -7298,6 +7296,7 @@ static void intel_init_display(struct drm_device *dev)
Disable CxSR\n);
dev_priv-display.update_wm = NULL;
}
+ dev_priv-display.fdi_link_train = gen6_fdi_link_train;
} else
dev_priv-display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
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[Intel-gfx] [RFC] Ivy Bridge supprt v2
Updated with review comments, just need to check and make sure all the rebasing didn't mess anything up, and of course testing is always needed. Thanks, Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions
This makes the Ironlake+ code trivial and generally simplifies things.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c |4 +++
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/i915_irq.c | 42 --
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2f653c2..d124f0e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1258,11 +1258,15 @@ static int i915_load_modeset_init(struct drm_device
*dev)
dev-driver-irq_preinstall = ironlake_irq_preinstall;
dev-driver-irq_postinstall = ironlake_irq_postinstall;
dev-driver-irq_uninstall = ironlake_irq_uninstall;
+ dev-driver-enable_vblank = ironlake_enable_vblank;
+ dev-driver-disable_vblank = ironlake_disable_vblank;
} else {
dev-driver-irq_preinstall = i915_driver_irq_preinstall;
dev-driver-irq_postinstall = i915_driver_irq_postinstall;
dev-driver-irq_uninstall = i915_driver_irq_uninstall;
dev-driver-irq_handler = i915_driver_irq_handler;
+ dev-driver-enable_vblank = i915_enable_vblank;
+ dev-driver-disable_vblank = i915_disable_vblank;
}
ret = drm_irq_install(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4841901..4dfe3fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1036,6 +1036,8 @@ extern int i915_vblank_pipe_get(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
extern int i915_enable_vblank(struct drm_device *dev, int crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
+extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
+extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a58d477..d5dcb8f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1344,10 +1344,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(dev_priv-irq_lock, irqflags);
- if (HAS_PCH_SPLIT(dev))
- ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
- DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else if (INTEL_INFO(dev)-gen = 4)
+ if (INTEL_INFO(dev)-gen = 4)
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
else
@@ -1362,6 +1359,22 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
return 0;
}
+int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ unsigned long irqflags;
+
+ if (!i915_pipe_enabled(dev, pipe))
+ return -EINVAL;
+
+ spin_lock_irqsave(dev_priv-irq_lock, irqflags);
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
+
+ return 0;
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -1375,13 +1388,20 @@ void i915_disable_vblank(struct drm_device *dev, int
pipe)
I915_WRITE(INSTPM,
INSTPM_AGPBUSY_DIS 16 | INSTPM_AGPBUSY_DIS);
- if (HAS_PCH_SPLIT(dev))
- ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
-DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else
- i915_disable_pipestat(dev_priv, pipe,
- PIPE_VBLANK_INTERRUPT_ENABLE |
- PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ i915_disable_pipestat(dev_priv, pipe,
+ PIPE_VBLANK_INTERRUPT_ENABLE |
+ PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
+}
+
+void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(dev_priv-irq_lock, irqflags);
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
}
--
1.7.4.1
[Intel-gfx] [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
Note: IS_GEN* are for render related checks. Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dfe3fa..93ac632 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -931,11 +931,18 @@ enum intel_chip_family {
#define IS_IRONLAKE_M(dev) ((dev)-pci_device == 0x0046)
#define IS_MOBILE(dev) (INTEL_INFO(dev)-is_mobile)
+/*
+ * The genX designation typically refers to the render engine, so render
+ * capability related checks should use IS_GEN, while display and other checks
+ * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
+ * chips, etc.).
+ */
#define IS_GEN2(dev) (INTEL_INFO(dev)-gen == 2)
#define IS_GEN3(dev) (INTEL_INFO(dev)-gen == 3)
#define IS_GEN4(dev) (INTEL_INFO(dev)-gen == 4)
#define IS_GEN5(dev) (INTEL_INFO(dev)-gen == 5)
#define IS_GEN6(dev) (INTEL_INFO(dev)-gen == 6)
+#define IS_GEN7(dev) (INTEL_INFO(dev)-gen == 7)
#define HAS_BSD(dev)(INTEL_INFO(dev)-has_bsd_ring)
#define HAS_BLT(dev)(INTEL_INFO(dev)-has_blt_ring)
--
1.7.4.1
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[Intel-gfx] [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93ac632..3a23de6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -230,6 +230,7 @@ struct intel_device_info {
u8 is_pineview : 1;
u8 is_broadwater : 1;
u8 is_crestline : 1;
+ u8 is_ivybridge : 1;
u8 has_fbc : 1;
u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1;
@@ -929,6 +930,7 @@ enum intel_chip_family {
#define IS_G33(dev)(INTEL_INFO(dev)-is_g33)
#define IS_IRONLAKE_D(dev) ((dev)-pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)-pci_device == 0x0046)
+#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)-is_ivybridge)
#define IS_MOBILE(dev) (INTEL_INFO(dev)-is_mobile)
/*
--
1.7.4.1
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[Intel-gfx] [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
A0 stepping chips need to use manual training, but the bits have all
moved. So fix things up so we can at least train FDI for VGA links.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++
drivers/gpu/drm/i915/intel_display.c | 128 +-
2 files changed, 135 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8848411..aba3fe5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3105,7 +3105,15 @@
#define FDI_TX_ENHANCE_FRAME_ENABLE(118)
/* Ironlake: hardwired to 1 */
#define FDI_TX_PLL_ENABLE (114)
+
+/* Ivybridge has different bits for lolz */
+#define FDI_LINK_TRAIN_PATTERN_1_IVB (08)
+#define FDI_LINK_TRAIN_PATTERN_2_IVB (18)
+#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB(28)
+#define FDI_LINK_TRAIN_NONE_IVB(38)
+
/* both Tx and Rx */
+#define FDI_LINK_TRAIN_AUTO (110)
#define FDI_SCRAMBLING_ENABLE (07)
#define FDI_SCRAMBLING_DISABLE (17)
@@ -3115,6 +3123,8 @@
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
#define FDI_RX_ENABLE (131)
/* train, dp width same as FDI_TX */
+#define FDI_FS_ERRC_ENABLE(127)
+#define FDI_FE_ERRC_ENABLE(126)
#define FDI_DP_PORT_WIDTH_X8 (719)
#define FDI_8BPC (016)
#define FDI_10BPC (116)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0dadc8e..ab840a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2047,8 +2047,13 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- temp = ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ if (IS_GEN6(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ } else if (IS_IVYBRIDGE(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+ }
I915_WRITE(reg, temp);
reg = FDI_RX_CTL(pipe);
@@ -2065,6 +2070,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* wait one idle pattern time */
POSTING_READ(reg);
udelay(1000);
+
+ /* IVB wants error correction enabled */
+ if (IS_IVYBRIDGE(dev))
+ I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
+ FDI_FE_ERRC_ENABLE);
}
/* The FDI link training functions for ILK/Ibexpeak. */
@@ -2292,7 +2302,116 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
DRM_DEBUG_KMS(FDI train done.\n);
}
-static void ironlake_fdi_enable(struct drm_crtc *crtc)
+/* Manual link training for Ivy Bridge A0 parts */
+static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 reg, temp, i;
+
+ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+ for train result */
+ reg = FDI_RX_IMR(pipe);
+ temp = I915_READ(reg);
+ temp = ~FDI_RX_SYMBOL_LOCK;
+ temp = ~FDI_RX_BIT_LOCK;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ /* enable CPU FDI TX and PCH FDI RX */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp = ~(7 19);
+ temp |= (intel_crtc-fdi_lanes - 1) 19;
+ temp = ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
+ temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
+ temp = ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp = ~FDI_LINK_TRAIN_AUTO;
+ temp = ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ for (i = 0; i 4; i++ ) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp = ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(500);
+
+ reg = FDI_RX_IIR(pipe);
+ temp = I915_READ(reg);
+ DRM_DEBUG_KMS(FDI_RX_IIR 0x%x\n, temp);
+
+ if (temp FDI_RX_BIT_LOCK ||
+ (I915_READ(reg) FDI_RX_BIT_LOCK)) {
+
[Intel-gfx] [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
Treat it like Ironlake and Sandy Bridge.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_gem_tiling.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index dfb682b..418015f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
--
1.7.4.1
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control
Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a23de6..4c06eb1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -971,8 +971,8 @@ enum intel_chip_family {
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)-has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)-has_fbc)
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
-#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)-gen = 5)
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private
*)(dev)-dev_private)-pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
--
1.7.4.1
___
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[Intel-gfx] [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
Ivy Bridge supports auto-training on the CPU side, so add a separate
training function to handle it.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |2 +
drivers/gpu/drm/i915/intel_display.c | 82 +++--
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aba3fe5..03c99ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3116,6 +3116,8 @@
#define FDI_LINK_TRAIN_AUTO (110)
#define FDI_SCRAMBLING_ENABLE (07)
#define FDI_SCRAMBLING_DISABLE (17)
+/* Ivybridge */
+#define FDI_AUTO_TRAIN_DONE (11)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
#define _FDI_RXA_CTL 0xf000c
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ab840a6..3396043 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2411,6 +2411,75 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
DRM_DEBUG_KMS(FDI train done.\n);
}
+/* On Ivybridge we can use auto training */
+static void ivb_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ unsigned long start = jiffies_to_msecs(jiffies);
+ int pipe = intel_crtc-pipe;
+ u32 reg, temp, i, j;
+
+ /* Can't pair IVB Ibex Peak */
+ BUG_ON(HAS_PCH_IBX(dev));
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp = ~(7 19);
+ temp |= (intel_crtc-fdi_lanes - 1) 19;
+ temp = ~FDI_LINK_TRAIN_NONE;
+ I915_WRITE(reg, temp);
+
+ /* Enable auto training on TX and RX */
+ for (i = 0; i ARRAY_SIZE(snb_b_fdi_train_param); i++) {
+ /* Try each vswing/pre-emphasis pair twice */
+ for (j = 0; j 2; j++) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_AUTO_TRAINING;
+ temp = ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+ POSTING_READ(reg);
+
+ udelay(5);
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ if ((temp FDI_AUTO_TRAIN_DONE) ||
+ (I915_READ(reg) FDI_AUTO_TRAIN_DONE)) {
+ DRM_DEBUG_KMS(FDI auto train complete in %d
ms\n,
+ jiffies_to_msecs(jiffies) -
start);
+ goto done;
+ }
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp ~FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp ~FDI_RX_ENABLE);
+ POSTING_READ(reg);
+ udelay(31); /* wait idle time before retrying */
+ }
+ }
+ DRM_ERROR(FDI auto train failed\n);
+ return;
+
+done:
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
+ I915_WRITE(reg, temp);
+ POSTING_READ(reg);
+}
+
static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -2452,7 +2521,7 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
}
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -2674,9 +2743,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
is_pch_port = intel_crtc_driving_pch(crtc);
if (is_pch_port)
- ironlake_fdi_enable(crtc);
+ ironlake_fdi_pll_enable(crtc);
else
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
/* Enable panel fitting for LVDS */
if (dev_priv-pch_pf_size
@@ -2729,7 +2798,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
I915_WRITE(PF_CTL(pipe), 0);
I915_WRITE(PF_WIN_SZ(pipe), 0);
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
/* This is a horrible layering violation; we should be doing this in
Re: [Intel-gfx] [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
On Thu, 28 Apr 2011 15:12:55 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
Ivy Bridge supports auto-training on the CPU side, so add a separate
training function to handle it.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |2 +
drivers/gpu/drm/i915/intel_display.c | 82 +++--
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aba3fe5..03c99ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3116,6 +3116,8 @@
#define FDI_LINK_TRAIN_AUTO (110)
#define FDI_SCRAMBLING_ENABLE (07)
#define FDI_SCRAMBLING_DISABLE (17)
+/* Ivybridge */
+#define FDI_AUTO_TRAIN_DONE (11)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
#define _FDI_RXA_CTL 0xf000c
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ab840a6..3396043 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2411,6 +2411,75 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
DRM_DEBUG_KMS(FDI train done.\n);
}
+/* On Ivybridge we can use auto training */
+static void ivb_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ unsigned long start = jiffies_to_msecs(jiffies);
+ int pipe = intel_crtc-pipe;
+ u32 reg, temp, i, j;
+
+ /* Can't pair IVB Ibex Peak */
+ BUG_ON(HAS_PCH_IBX(dev));
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp = ~(7 19);
+ temp |= (intel_crtc-fdi_lanes - 1) 19;
+ temp = ~FDI_LINK_TRAIN_NONE;
+ I915_WRITE(reg, temp);
+
+ /* Enable auto training on TX and RX */
+ for (i = 0; i ARRAY_SIZE(snb_b_fdi_train_param); i++) {
+ /* Try each vswing/pre-emphasis pair twice */
+ for (j = 0; j 2; j++) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_AUTO_TRAINING;
+ temp = ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+ POSTING_READ(reg);
+
+ udelay(5);
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ if ((temp FDI_AUTO_TRAIN_DONE) ||
+ (I915_READ(reg) FDI_AUTO_TRAIN_DONE)) {
+ DRM_DEBUG_KMS(FDI auto train complete in %d
ms\n,
+ jiffies_to_msecs(jiffies) -
start);
+ goto done;
+ }
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp ~FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp ~FDI_RX_ENABLE);
+ POSTING_READ(reg);
+ udelay(31); /* wait idle time before retrying */
+ }
+ }
+ DRM_ERROR(FDI auto train failed\n);
+ return;
+
+done:
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
+ I915_WRITE(reg, temp);
+ POSTING_READ(reg);
+}
+
static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -2452,7 +2521,7 @@ static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc)
}
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -2674,9 +2743,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
is_pch_port = intel_crtc_driving_pch(crtc);
if (is_pch_port)
- ironlake_fdi_enable(crtc);
+ ironlake_fdi_pll_enable(crtc);
else
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
/* Enable panel fitting for LVDS */
if (dev_priv-pch_pf_size
@@ -2729,7 +2798,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
I915_WRITE(PF_CTL(pipe), 0);
I915_WRITE(PF_WIN_SZ(pipe), 0);
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
arg,
[Intel-gfx] [PATCH 18/19] drm/i915: set IBX pch type explicitly
This is a little less confusing than relying on the implicit zeroing of
the dev_priv.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 14b9c6f..9290abd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -254,6 +254,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
#endif
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
+#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
@@ -274,7 +275,10 @@ void intel_detect_pch (struct drm_device *dev)
int id;
id = pch-device INTEL_PCH_DEVICE_ID_MASK;
- if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
+ if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
+ dev_priv-pch_type = PCH_IBX;
+ DRM_DEBUG_KMS(Found Ibex Peak PCH\n);
+ } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv-pch_type = PCH_CPT;
DRM_DEBUG_KMS(Found CougarPoint PCH\n);
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
--
1.7.4.1
___
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[Intel-gfx] [PATCH 11/19] drm/i915: interrupt vblank support for Ivy Bridge
Add new interrupt handling functions for Ivy Bridge.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c | 12 +++-
drivers/gpu/drm/i915/i915_drv.h |7 ++
drivers/gpu/drm/i915/i915_irq.c | 156 +++
drivers/gpu/drm/i915/i915_reg.h | 13 +++
4 files changed, 186 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d124f0e..8e27bc4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,7 +1253,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_modeset_init(dev);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_IVYBRIDGE(dev)) {
+ /* Share pre uninstall handlers with ILK/SNB */
+ dev-driver-irq_handler = ivybridge_irq_handler;
+ dev-driver-irq_preinstall = ironlake_irq_preinstall;
+ dev-driver-irq_postinstall = ivybridge_irq_postinstall;
+ dev-driver-irq_uninstall = ironlake_irq_uninstall;
+ dev-driver-enable_vblank = ivybridge_enable_vblank;
+ dev-driver-disable_vblank = ivybridge_disable_vblank;
+ } else if (HAS_PCH_SPLIT(dev)) {
dev-driver-irq_handler = ironlake_irq_handler;
dev-driver-irq_preinstall = ironlake_irq_preinstall;
dev-driver-irq_postinstall = ironlake_irq_postinstall;
@@ -1998,7 +2006,7 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
dev-driver-get_vblank_counter = i915_get_vblank_counter;
dev-max_vblank_count = 0xff; /* only 24 bits of frame count */
- if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
dev-max_vblank_count = 0x; /* full 32 bit counter */
dev-driver-get_vblank_counter = gm45_get_vblank_counter;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4c06eb1..5f906f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1039,6 +1039,11 @@ extern void ironlake_irq_preinstall(struct drm_device
*dev);
extern int ironlake_irq_postinstall(struct drm_device *dev);
extern void ironlake_irq_uninstall(struct drm_device *dev);
+extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
+extern void ivybridge_irq_preinstall(struct drm_device *dev);
+extern int ivybridge_irq_postinstall(struct drm_device *dev);
+extern void ivybridge_irq_uninstall(struct drm_device *dev);
+
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
@@ -1047,6 +1052,8 @@ extern int i915_enable_vblank(struct drm_device *dev, int
crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
+extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
+extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d5dcb8f..a025002 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,6 +448,85 @@ static void pch_irq_handler(struct drm_device *dev)
DRM_DEBUG_DRIVER(PCH transcoder A underrun interrupt\n);
}
+irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
+{
+ struct drm_device *dev = (struct drm_device *) arg;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ int ret = IRQ_NONE;
+ u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
+ struct drm_i915_master_private *master_priv;
+
+ atomic_inc(dev_priv-irq_received);
+
+ /* disable master interrupt before clearing iir */
+ de_ier = I915_READ(DEIER);
+ I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
+ POSTING_READ(DEIER);
+
+ de_iir = I915_READ(DEIIR);
+ gt_iir = I915_READ(GTIIR);
+ pch_iir = I915_READ(SDEIIR);
+ pm_iir = I915_READ(GEN6_PMIIR);
+
+ if (de_iir == 0 gt_iir == 0 pch_iir == 0 pm_iir == 0)
+ goto done;
+
+ ret = IRQ_HANDLED;
+
+ if (dev-primary-master) {
+ master_priv = dev-primary-master-driver_priv;
+ if (master_priv-sarea_priv)
+ master_priv-sarea_priv-last_dispatch =
+ READ_BREADCRUMB(dev_priv);
+ }
+
+ if (gt_iir (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+
[Intel-gfx] [PATCH 15/19] agp/intel: add Ivy Bridge support
Just use the Sandy Bridge routines.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/char/agp/intel-agp.c |3 +++
drivers/char/agp/intel-agp.h |8
drivers/char/agp/intel-gtt.c | 10 ++
3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index b0a0dcc..b427711 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -903,6 +903,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
{ }
};
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5feebe2..999803c 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -225,6 +225,14 @@
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
int intel_gmch_probe(struct pci_dev *pdev,
struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0d09b53..8515101 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1420,6 +1420,16 @@ static const struct intel_gtt_driver_description {
Sandybridge, sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
Sandybridge, sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
+ Ivybridge, sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
+ Ivybridge, sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
+ Ivybridge, sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
+ Ivybridge, sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
+ Ivybridge, sandybridge_gtt_driver },
{ 0, NULL, NULL }
};
--
1.7.4.1
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[Intel-gfx] [PATCH 19/19] drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_suspend.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 337 +++---
3 files changed, 195 insertions(+), 146 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5f906f1..c4628d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -210,12 +210,12 @@ struct drm_i915_display_funcs {
int x, int y,
struct drm_framebuffer *old_fb);
void (*fdi_link_train)(struct drm_crtc *crtc);
+ void (*init_clock_gating)(struct drm_device *dev);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
- /* clock gating init */
};
struct intel_device_info {
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index da47415..6cb27ff 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -864,7 +864,7 @@ int i915_restore_state(struct drm_device *dev)
}
/* Clock gating state */
- intel_enable_clock_gating(dev);
+ dev_priv-display.init_clock_gating(dev);
if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5ce54fe..77a32fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7142,161 +7142,194 @@ void gen6_enable_rps(struct drm_i915_private
*dev_priv)
__gen6_gt_force_wake_put(dev_priv);
}
-void intel_enable_clock_gating(struct drm_device *dev)
+static void ironlake_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+ /* Required for FBC */
+ dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
+ DPFCRUNIT_CLOCK_GATE_DISABLE |
+ DPFDUNIT_CLOCK_GATE_DISABLE;
+ /* Required for CxSR */
+ dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+
+ I915_WRITE(PCH_3DCGDIS0,
+ MARIUNIT_CLOCK_GATE_DISABLE |
+ SVSMUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(PCH_3DCGDIS1,
+ VFMUNIT_CLOCK_GATE_DISABLE);
+
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+ /*
+* On Ibex Peak and Cougar Point, we need to disable clock
+* gating for the panel power sequencer or it will fail to
+* start up when no ports are active.
+*/
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+ /*
+* According to the spec the following bits should be set in
+* order to enable memory self-refresh
+* The bit 22/21 of 0x42004
+* The bit 5 of 0x42020
+* The bit 15 of 0x45000
+*/
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ (I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL));
+ I915_WRITE(ILK_DSPCLK_GATE,
+ (I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPARB_CLK_GATE));
+ I915_WRITE(DISP_ARB_CTL,
+ (I915_READ(DISP_ARB_CTL) |
+ DISP_FBC_WM_DIS));
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
+
+ /*
+* Based on the document from hardware guys the following bits
+* should be set unconditionally in order to enable FBC.
+* The bit 22 of 0x42000
+* The bit 22 of 0x42004
+* The bit 7,8,9 of 0x42020.
+*/
+ if (IS_IRONLAKE_M(dev)) {
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS);
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_DIS1 |
+ ILK_DPFC_DIS2 |
+ ILK_CLK_FBC);
+ }
+
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_ELPIN_409_SELECT);
+ I915_WRITE(_3D_CHICKEN2,
+ _3D_CHICKEN2_WM_READ_PIPELINED 16 |
+ _3D_CHICKEN2_WM_READ_PIPELINED);
+}
+
+static void gen6_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int pipe;
+ uint32_t dspclk_gate =
[Intel-gfx] [PATCH 16/19] drm/i915: add PantherPoint PCH ID
We can treat PantherPoint as CougarPoint as far as display goes.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5d0d28c..09d2b78 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -236,6 +236,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
void intel_detect_pch (struct drm_device *dev)
{
@@ -257,6 +258,10 @@ void intel_detect_pch (struct drm_device *dev)
if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv-pch_type = PCH_CPT;
DRM_DEBUG_KMS(Found CougarPoint PCH\n);
+ } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
+ /* PantherPoint is CPT compatible */
+ dev_priv-pch_type = PCH_CPT;
+ DRM_DEBUG_KMS(Found PatherPoint PCH\n);
}
}
pci_dev_put(pch);
--
1.7.4.1
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[Intel-gfx] [PATCH 12/19] drm/i915: page flip support for Ivy Bridge
Treat Ivy Bridge like previous chips as far as flip submission is concerned. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fbb7a6b..5ce54fe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6362,6 +6362,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, break; case 6: + case 7: OUT_RING(MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc-plane)); OUT_RING(fb-pitch | obj-tiling_mode); -- 1.7.4.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/19] drm/i915: ring support for Ivy Bridge
Use Sandy Bridge paths in a few places.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_ringbuffer.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f15d80f..9bcfb9b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -287,7 +287,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
if (INTEL_INFO(dev)-gen 3) {
int mode = VS_TIMER_DISPATCH 16 | VS_TIMER_DISPATCH;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
mode |= MI_FLUSH_ENABLE 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
}
@@ -553,7 +553,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
drm_i915_private_t *dev_priv = ring-dev-dev_private;
- u32 mmio = IS_GEN6(ring-dev) ?
+ u32 mmio = (IS_GEN6(ring-dev) || IS_GEN7(ring-dev)) ?
RING_HWS_PGA_GEN6(ring-mmio_base) :
RING_HWS_PGA(ring-mmio_base);
I915_WRITE(mmio, (u32)ring-status_page.gfx_addr);
@@ -1335,7 +1335,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
drm_i915_private_t *dev_priv = dev-dev_private;
struct intel_ring_buffer *ring = dev_priv-ring[VCS];
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
*ring = gen6_bsd_ring;
else
*ring = bsd_ring;
--
1.7.4.1
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[Intel-gfx] [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
Treat it like Sandy Bridge in a few places.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0daefca..1d0eccd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = intel_hrawclk(dev) / 2;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
precharge = 3;
else
precharge = 5;
@@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (;;) {
/* Use intel_dp-train_set[0] to set the voltage and pre
emphasis values */
uint32_tsignal_levels;
- if (IS_GEN6(dev) is_edp(intel_dp)) {
+ if ((IS_GEN6(dev) || IS_GEN7(dev)) is_edp(intel_dp)) {
signal_levels =
intel_gen6_edp_signal_levels(intel_dp-train_set[0]);
DP = (DP ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) |
signal_levels;
} else {
@@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN6(dev) is_edp(intel_dp)) {
+ if ((IS_GEN6(dev) || IS_GEN7(dev)) is_edp(intel_dp)) {
signal_levels =
intel_gen6_edp_signal_levels(intel_dp-train_set[0]);
DP = (DP ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) |
signal_levels;
} else {
--
1.7.4.1
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[Intel-gfx] [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
Not fully tested.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3396043..fbb7a6b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7229,7 +7229,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
_3D_CHICKEN2_WM_READ_PIPELINED);
}
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
I915_WRITE(WM3_LP_ILK, 0);
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
@@ -7491,6 +7491,13 @@ static void intel_init_display(struct drm_device *dev)
dev_priv-display.fdi_link_train =
ivb_fdi_link_train;
else
dev_priv-display.fdi_link_train =
ivb_manual_fdi_link_train;
+ if (SNB_READ_WM0_LATENCY()) {
+ dev_priv-display.update_wm =
sandybridge_update_wm;
+ } else {
+ DRM_DEBUG_KMS(Failed to read display plane
latency.
+ Disable CxSR\n);
+ dev_priv-display.update_wm = NULL;
+ }
} else
dev_priv-display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
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[Intel-gfx] [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs
There are several variants, set feature bits appropriately for both
mobile and desktop parts.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 09d2b78..14b9c6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,6 +188,20 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
.has_blt_ring = 1,
};
+static const struct intel_device_info intel_ivybridge_d_info = {
+ .is_ivybridge = 1, .gen = 7,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_info = {
+ .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x3577, intel_i830_info), /* I830_M */
INTEL_VGA_DEVICE(0x2562, intel_845g_info), /* 845_G */
@@ -227,6 +241,11 @@ static const struct pci_device_id pciidlist[] = {
/* aka */
INTEL_VGA_DEVICE(0x0116, intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x0126, intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x010A, intel_sandybridge_d_info),
+ INTEL_VGA_DEVICE(0x0156, intel_ivybridge_m_info), /* GT1 mobile */
+ INTEL_VGA_DEVICE(0x0166, intel_ivybridge_m_info), /* GT2 mobile */
+ INTEL_VGA_DEVICE(0x0152, intel_ivybridge_d_info), /* GT1 desktop */
+ INTEL_VGA_DEVICE(0x0162, intel_ivybridge_d_info), /* GT2 desktop */
+ INTEL_VGA_DEVICE(0x015a, intel_ivybridge_d_info), /* GT1 server */
{0, 0, 0}
};
--
1.7.4.1
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Re: [Intel-gfx] [PATCH 01/19] drm/i915: make FDI training a display function
On Thu, 28 Apr 2011 15:12:47 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Rather than branching in ironlake_pch_enable, add a new train_fdi function to the display function pointer struct and use it instead. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgpkV3NopGSL6.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
On Thu, 28 Apr 2011 15:12:48 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Set the IRQ handling functions in driver load so they'll just be used directly, rather than branching over most of the code in the chipset functions. Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgp2AbBeCyLbw.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions
On Thu, 28 Apr 2011 15:12:49 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: This makes the Ironlake+ code trivial and generally simplifies things. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgpmUuBtFRc86.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
On Thu, 28 Apr 2011 15:12:50 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Note: IS_GEN* are for render related checks. Display and other checks should use IS_MOBILE, IS_$CHIPSET or test for specific features. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgpsB6S4fLOTt.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks
On Thu, 28 Apr 2011 15:12:51 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: I don't see a patch in this series that sets this value from the PCI ids. Is that still pending? -- keith.pack...@intel.com pgpfAzxA46ANr.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control
On Thu, 28 Apr 2011 15:12:52 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Ivy Bridge has a similar split display controller to Sandy Bridge, so use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so use HAS_PIPE_CONTROL as well. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgp0rmuIHa20e.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
On Thu, 28 Apr 2011 15:12:53 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Treat it like Ironlake and Sandy Bridge. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Should use gen = 5? -- keith.pack...@intel.com pgptprXAz4FhS.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
On Thu, 28 Apr 2011 15:12:54 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
+ if (IS_GEN6(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ } else if (IS_IVYBRIDGE(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+ }
This seems inconsistent using IS_GEN6 for SNB and IS_IVYBRIDGE for IVB?
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Re: [Intel-gfx] [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
On Thu, 28 Apr 2011 15:12:55 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Ivy Bridge supports auto-training on the CPU side, so add a separate training function to handle it. Let's leave this out of the kernel until we have hardware that actually uses it. -- keith.pack...@intel.com pgpBSTIApdDAP.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please.
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Re: [Intel-gfx] [PATCH 11/19] drm/i915: interrupt vblank support for Ivy Bridge
On Thu, 28 Apr 2011 15:12:57 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
- if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
IS_G4X || gen = 5 ?
Otherwise, this looks good (seems like it's just bit shuffling from SNB, right?)
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Re: [Intel-gfx] [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Treat it like Sandy Bridge in a few places. gen = 6? -- keith.pack...@intel.com pgpqFHB2q8tev.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 14/19] drm/i915: ring support for Ivy Bridge
On Thu, 28 Apr 2011 15:13:00 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Use Sandy Bridge paths in a few places. gen = 6 ? -- keith.pack...@intel.com pgp6Bmd9mjsyL.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs
On Thu, 28 Apr 2011 15:13:03 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: There are several variants, set feature bits appropriately for both mobile and desktop parts. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgpgD7gICZi93.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/19] drm/i915: set IBX pch type explicitly
On Thu, 28 Apr 2011 15:13:04 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: This is a little less confusing than relying on the implicit zeroing of the dev_priv. Thanks. Reviewed-by: Keith Packard kei...@keithp.com -- keith.pack...@intel.com pgpFuOeuyyxOq.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
On Thu, 28 Apr 2011 15:43:10 -0700
Keith Packard kei...@keithp.com wrote:
On Thu, 28 Apr 2011 15:12:54 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
+ if (IS_GEN6(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ } else if (IS_IVYBRIDGE(dev)) {
+ temp = ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+ }
This seems inconsistent using IS_GEN6 for SNB and IS_IVYBRIDGE for IVB?
Yes, there are several IS_GEN checks that I'd argue are wrong, I can
clean them up in a subsequent.
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Re: [Intel-gfx] [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
On Thu, 28 Apr 2011 15:42:13 -0700 Keith Packard kei...@keithp.com wrote: On Thu, 28 Apr 2011 15:12:53 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Treat it like Ironlake and Sandy Bridge. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Should use gen = 5? Yeah, probably better. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
On Thu, 28 Apr 2011 15:46:06 -0700
Keith Packard kei...@keithp.com wrote:
On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please.
See earlier mail; GEN6 is the wrong one to use here imo.
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