[Intel-gfx] assertion on intel_disable_transcoder
Hi Daniel/Paulo, It's easy to see such WARNING in dmesg, the DDI port is not disabled prior to disable transcoder. I am not sure it will impact the Pipe/transcoder/DDI-port configurations, anyway after some times WARNING, I could not make HDMI audio work anymore. With intel_audio_dump I could see the related configurations was totally disabled. DDI_BUF_CTL_A 0x0080 DDI Buffer Controler A DDI_BUF_CTL_B 0x DDI Buffer Controler B DDI_BUF_CTL_C 0x0080 DDI Buffer Controler C DDI_BUF_CTL_D 0x DDI Buffer Controler D DDI_BUF_CTL_E 0x8002 DDI Buffer Controler E PIPE_CONF_A 0x PIPE Configuration A PIPE_CONF_B 0x PIPE Configuration B PIPE_CONF_C 0x PIPE Configuration C PIPE_CONF_EDP 0x PIPE Configuration EDP PIPE_DDI_FUNC_CTL_A 0xc4034002 PIPE DDI Function Control A PIPE_DDI_FUNC_CTL_B 0xa0035000 PIPE DDI Function Control B PIPE_DDI_FUNC_CTL_C 0x0003 PIPE DDI Function Control C PIPE_DDI_FUNC_CTL_EDP 0x0003 PIPE DDI Function Control EDP TRANS_CONF0x Transcoder Configuration Thanks --xingchao [ 16.835658] [ cut here ] [ 16.835690] WARNING: at drivers/gpu/drm/i915/intel_display.c:1118 assert_fdi_tx+0x87/0x90 [i915]() [ 16.835691] Hardware name: Shark Bay Client platform [ 16.835692] FDI TX state assertion failure (expected off, current on) [ 16.835706] Modules linked in: snd_seq_midi_event i915(+) snd_seq snd_timer drm_kms_helper snd_seq _device ghash_clmulni_intel drm aesni_intel snd cryptd mcs7830 usbnet joydev aes_x86_64 soundcore psm ouse snd_page_alloc hid_generic i2c_algo_bit serio_raw video mac_hid microcode lpc_ich lp parport e10 00e usbhid hid [ 16.835708] Pid: 470, comm: modprobe Not tainted 3.5.0-rc46patches+ #12 [ 16.835709] Call Trace: [ 16.835715] [8105278f] warn_slowpath_common+0x7f/0xc0 [ 16.835718] [81052886] warn_slowpath_fmt+0x46/0x50 [ 16.835728] [a01cc847] assert_fdi_tx+0x87/0x90 [i915] [ 16.835739] [a01d5cf5] ironlake_crtc_disable+0x185/0x820 [i915] [ 16.835748] [a01d641e] ironlake_crtc_dpms+0x8e/0xa0 [i915] [ 16.835756] [a01cdbd8] intel_crtc_dpms+0x48/0x140 [i915] [ 16.835768] [a01d49d5] intel_crtc_disable+0x35/0xb0 [i915] [ 16.835772] [a012d6a5] drm_helper_disable_unused_functions+0x115/0x190 [drm_kms_helper] [ 16.835785] [a01d849d] intel_modeset_init+0x8ad/0xf90 [i915] [ 16.835796] [a01aebba] i915_driver_load+0xa8a/0xb90 [i915] [ 16.835812] [a016fa7b] ? drm_get_minor+0x26b/0x310 [drm] [ 16.835819] [a0171e71] drm_get_pci_dev+0x191/0x2b0 [drm] [ 16.835834] [a01fc01b] i915_pci_probe+0x4f/0x57 [i915] [ 16.835837] [8134230c] local_pci_probe+0x5c/0xd0 [ 16.835840] [81343c49] pci_device_probe+0x109/0x130 [ 16.835843] [814065ee] driver_probe_device+0x7e/0x220 [ 16.835845] [8140683b] __driver_attach+0xab/0xb0 [ 16.835848] [81406790] ? driver_probe_device+0x220/0x220 [ 16.835850] [81404a26] bus_for_each_dev+0x56/0x90 [ 16.835852] [8140610e] driver_attach+0x1e/0x20 [ 16.835854] [81405cc0] bus_add_driver+0x1a0/0x270 [ 16.835856] [81406d96] driver_register+0x76/0x130 [ 16.835859] [81343916] __pci_register_driver+0x56/0xd0 [ 16.835862] [8166949d] ? notifier_call_chain+0x4d/0x70 [ 16.835869] [a01720aa] drm_pci_init+0x11a/0x130 [drm] [ 16.835871] [a023] ? 0xa022 [ 16.835880] [a0230066] i915_init+0x66/0x68 [i915] [ 16.835884] [8100203f] do_one_initcall+0x3f/0x170 [ 16.835887] [810b581e] sys_init_module+0xbe/0x230 [ 16.835890] [8166d769] system_call_fastpath+0x16/0x1b [ 16.835891] ---[ end trace bd9532eaee4e4542 ]--- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: correctly order the ring init sequence
We may only start to set up the new register values after having confirmed that the ring is truely off. Otherwise the hw might lose the newly written register values. This is caught later on in the init sequence, when we check whether the register writes have stuck. Cc: sta...@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 Tested-by: Yang Guang guang.a.y...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_ringbuffer.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bf0195a..5b19917 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) I915_WRITE_HEAD(ring, 0); ring-write_tail(ring, 0); - /* Initialize the ring. */ - I915_WRITE_START(ring, obj-gtt_offset); head = I915_READ_HEAD(ring) HEAD_ADDR; /* G45 ring initialization fails to reset head to zero */ @@ -316,6 +314,10 @@ static int init_ring_common(struct intel_ring_buffer *ring) } } + /* Initialize the ring. This must happen _after_ we have confirmed that +* the ring is off (with the above head == 0 check), otherwise the hw +* might lose the new ring register values. */ + I915_WRITE_START(ring, obj-gtt_offset); I915_WRITE_CTL(ring, ((ring-size - PAGE_SIZE) RING_NR_PAGES) | RING_VALID); -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Fwd: Re: Macbook Pro Retina display problems
Daniel,
nope, the hack didn't succeed. No apparent change.
Francois
On Tue 07 Aug 2012 05:31:25 EST, Daniel Vetter wrote:
On Mon, Aug 06, 2012 at 11:40:36PM +1000, Francois Rigaut wrote:
Daniel,
On Mon, Aug 6, 2012 at 7:17 PM, Daniel Vetter dan...@ffwll.ch
mailto:dan...@ffwll.ch wrote:
On Mon, Aug 6, 2012 at 10:59 AM, Francois Rigaut frig...@gmail.com
mailto:frig...@gmail.com wrote:
Daniel,
my bad for the dmesg. It's there:
http://maumae.net/retina/intel_corrupted_drm_debug/dmesg_intel_corrupted_drm_debug
I took pictures with a camera, and uploaded them at
Small 800x600 versions:
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_right_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_whole_screen_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
full resolution versions:
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_right.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_whole_screen.jpg
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
Otherwise, the display works and behave normally (it's not
static, doesn't
flicker). I can interact normally with the GUI element, display
stuff, it's
accelerated (I run compiz and window wiggle normally, I can play
videos, I
have control of backlight, etc).
Wow, that's a pretty impressive light-show ;-) Are the wrong colors
always wrong in this manner, or does it change from boot to boot?
everything (color and sync) are always wrong in the same manner.
the last git version of intel_reg_dumper gives me:
with i915 loaded:
http://maumae.net/retina/intel_corrupted_drm_debug/ird_i915_loaded
with i915.die=1:
http://maumae.net/retina/intel_corrupted_drm_debug/ird_i915_not_loaded
Can you please try the below quick hack. If that doesn't cut it, I need to
improve the reg_dumper tool first, the efi firmware sets things up on pipe
C, which we currently don't dump.
-Daniel
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a56b9a..d7462da 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -920,9 +920,9 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
if (is_cpu_edp(intel_dp) IS_GEN7(dev)) {
- if (adjusted_mode-flags DRM_MODE_FLAG_PHSYNC)
+ //if (adjusted_mode-flags DRM_MODE_FLAG_PHSYNC)
intel_dp-DP |= DP_SYNC_HS_HIGH;
- if (adjusted_mode-flags DRM_MODE_FLAG_PVSYNC)
+ //if (adjusted_mode-flags DRM_MODE_FLAG_PVSYNC)
intel_dp-DP |= DP_SYNC_VS_HIGH;
intel_dp-DP |= DP_LINK_TRAIN_OFF_CPT;
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[Intel-gfx] [PATCH 0/2] Haswell intel_audio_dump support
This patch enabled intel_audio_dump to support Haswell platform. Haswell has some registers differences comprared with previous platforms. Changes since V1: - fix compile warnings - remove HBR bits show, it doesnot exist under Haswell Wang Xingchao (2): intel_audio_dump: fix wrong port definition intel_audio_dump: add Haswell audio dump support tools/intel_audio_dump.c | 588 +- 1 file changed, 585 insertions(+), 3 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V2 1/2] intel_audio_dump: fix wrong port definition
There're three Ports B/C/D used for selection by each transcoder A/B/C.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
tools/intel_audio_dump.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index 077e096..8a0f6ee 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -126,9 +126,9 @@ static const char *video_dip_trans[] = {
static const char *trans_to_port_sel[] = {
[0] = no port,
[1] = Digital Port B,
- [2] = Digital Port B,
- [3] = Digital Port B,
- [4] = Digital Port B,
+ [2] = Digital Port C,
+ [3] = Digital Port D,
+ [4] = reserved,
[5] = reserved,
[6] = reserved,
[7] = reserved,
--
1.7.9.5
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[Intel-gfx] [PATCH V2 2/2] intel_audio_dump: add Haswell audio dump support
Add Haswell audio registers definition and dump support.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
tools/intel_audio_dump.c | 582 ++
1 file changed, 582 insertions(+)
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index 8a0f6ee..5ee9372 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -94,6 +94,11 @@ static const char *dip_port[] = {
[3] = Digital Port D,
};
+static const char *dip_type[] = {
+[0] = Audio DIP Disabled,
+[1] = Audio DIP Enabled,
+};
+
static const char *dip_index[] = {
[0] = Audio DIP,
[1] = ACP DIP,
@@ -134,6 +139,17 @@ static const char *trans_to_port_sel[] = {
[7] = reserved,
};
+static const char *ddi_mode[] = {
+ [0] = HDMI mode,
+ [1] = DVI mode,
+ [2] = DP SST mode,
+ [3] = DP MST mode,
+ [4] = DP FDI mode,
+ [5] = reserved,
+ [6] = reserved,
+ [7] = reserved,
+};
+
static const char *transcoder_select[] = {
[0] = Transcoder A,
[1] = Transcoder B,
@@ -1354,6 +1370,567 @@ static void dump_cpt(void)
}
+#undef AUD_CONFIG_A
+#undef AUD_MISC_CTRL_A
+#undef AUD_VID_DID
+#undef AUD_RID
+#undef AUD_CTS_ENABLE_A
+#undef AUD_PWRST
+#undef AUD_HDMIW_HDMIEDID_A
+#undef AUD_HDMIW_INFOFR_A
+#undef AUD_PORT_EN_HD_CFG
+#undef AUD_OUT_DIG_CNVT_A
+#undef AUD_OUT_STR_DESC_A
+#undef AUD_OUT_CH_STR
+#undef AUD_PINW_CONNLNG_LIST
+#undef AUD_CNTL_ST_A
+#undef AUD_HDMIW_STATUS
+#undef AUD_CONFIG_B
+#undef AUD_MISC_CTRL_B
+#undef AUD_CTS_ENABLE_B
+#undef AUD_HDMIW_HDMIEDID_B
+#undef AUD_HDMIW_INFOFR_B
+#undef AUD_OUT_DIG_CNVT_B
+#undef AUD_OUT_STR_DESC_B
+#undef AUD_CNTL_ST_B
+#undef AUD_CONFIG_C
+#undef AUD_MISC_CTRL_C
+#undef AUD_CTS_ENABLE_C
+#undef AUD_HDMIW_HDMIEDID_C
+#undef AUD_HDMIW_INFOFR_C
+#undef AUD_OUT_DIG_CNVT_C
+#undef AUD_OUT_STR_DESC_C
+
+#undef VIDEO_DIP_CTL_A
+#undef VIDEO_DIP_CTL_B
+#undef VIDEO_DIP_CTL_C
+#undef VIDEO_DIP_CTL_D
+#undef VIDEO_DIP_DATA
+
+/*Haswell registers*/
+
+/*DisplayPort Transport Control*/
+#define DP_TP_CTL_A0x64040
+#define DP_TP_CTL_B0x64140
+#define DP_TP_CTL_C0x64240
+#define DP_TP_CTL_D0x64340
+#define DP_TP_CTL_E0x64440
+
+/*DisplayPort Transport Status*/
+#define DP_TP_ST_A 0x64044
+#define DP_TP_ST_B 0x64144
+#define DP_TP_ST_C 0x64244
+#define DP_TP_ST_D 0x64344
+#define DP_TP_ST_E 0x6
+
+/*Transcoder configuration*/
+#define TRANS_CONF_A 0xF0008
+#define TRANS_CONF_B 0xF1008
+#define TRANS_CONF_C 0xF2008
+
+/*DDI Buffer Control*/
+#define DDI_BUF_CTL_A0x64000
+#define DDI_BUF_CTL_B0x64100
+#define DDI_BUF_CTL_C0x64200
+#define DDI_BUF_CTL_D0x64300
+#define DDI_BUF_CTL_E0x64400
+
+/*DDI Buffer Translation*/
+#define DDI_BUF_TRANS_A0x64e00
+#define DDI_BUF_TRANS_B0x64e60
+#define DDI_BUF_TRANS_C0x64ec0
+#define DDI_BUF_TRANS_D0x64f20
+#define DDI_BUF_TRANS_E0x64f80
+
+/*DDI Aux Channel*/
+#define DDI_AUX_CHANNEL_CTRL 0x64010
+#define DDI_AUX_DATA 0x64014
+#define DDI_AUX_TST0x64028
+
+/*DDI CRC Control*/
+#define DDI_CRC_CTL_A 0x64050
+#define DDI_CRC_CTL_B 0x64150
+#define DDI_CRC_CTL_C 0x64250
+#define DDI_CRC_CTL_D 0x64350
+#define DDI_CRC_CTL_E 0x64450
+
+/*Pipe DDI Function Control*/
+#define PIPE_DDI_FUNC_CTL_A 0x60400
+#define PIPE_DDI_FUNC_CTL_B 0x61400
+#define PIPE_DDI_FUNC_CTL_C 0x62400
+#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
+
+/*Pipe Configuration*/
+#define PIPE_CONF_A0x70008
+#define PIPE_CONF_B0x71008
+#define PIPE_CONF_C0x72008
+#define PIPE_CONF_EDP 0x7F008
+
+/*Audio registers*/
+#define AUD_CONFIG_A 0x65000
+#define AUD_MISC_CTRL_A 0x65010
+#define AUD_VID_DID 0x65020
+#define AUD_RID 0x65024
+#define AUD_CTS_ENABLE_A 0x65028
+#define AUD_PWRST 0x6504C
+#define AUD_HDMIW_HDMIEDID_A 0x65050
+#define AUD_HDMIW_INFOFR_A0x65054
+#define AUD_PORT_EN_HD_CFG0x6507C
+#define AUD_OUT_DIG_CNVT_A0x65080
+#define AUD_OUT_STR_DESC_A0x65084
+#define AUD_OUT_CHAN_MAP 0x65088
+#define AUD_PINW_CONNLNG_LIST_A 0x650A8
+#define AUD_PINW_CONNLNG_LIST_B 0x651A8
+#define AUD_PINW_CONNLNG_LIST_C 0x652A8
+#define AUD_PIPE_CONN_SEL_CTRL 0x650AC
+#define AUD_PIN_ELD_CP_VLD0x650C0
+#define AUD_HDMIW_STATUS 0x650D4
+#define AUD_CONFIG_B 0x65100
+#define AUD_MISC_CTRL_B 0x65110
+#define AUD_CTS_ENABLE_B 0x65128
+#define AUD_HDMIW_HDMIEDID_B 0x65150
+#define AUD_HDMIW_INFOFR_B0x65154
+#define AUD_OUT_DIG_CNVT_B0x65180
+#define AUD_OUT_STR_DESC_B0x65184
+#define AUD_CONFIG_C 0x65200
+#define AUD_MISC_CTRL_C 0x65210
+#define AUD_CTS_ENABLE_C 0x65228
+#define
Re: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs
On Mon, 6 Aug 2012 19:20:29 -0300, Rodrigo Vivi rodrigo.v...@gmail.com wrote: Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com Thanks for the patch and the careful review, pushed. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: correctly order the ring init sequence
On Tue, 07 Aug 2012, Daniel Vetter daniel.vet...@ffwll.ch wrote: We may only start to set up the new register values after having confirmed that the ring is truely off. Otherwise the hw might lose the newly written register values. This is caught later on in the init sequence, when we check whether the register writes have stuck. With or without (up to you) the comment clarification discussed in IRC, Reviewed-by: Jani Nikula jani.nik...@intel.com Cc: sta...@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 Tested-by: Yang Guang guang.a.y...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_ringbuffer.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bf0195a..5b19917 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) I915_WRITE_HEAD(ring, 0); ring-write_tail(ring, 0); - /* Initialize the ring. */ - I915_WRITE_START(ring, obj-gtt_offset); head = I915_READ_HEAD(ring) HEAD_ADDR; /* G45 ring initialization fails to reset head to zero */ @@ -316,6 +314,10 @@ static int init_ring_common(struct intel_ring_buffer *ring) } } + /* Initialize the ring. This must happen _after_ we have confirmed that + * the ring is off (with the above head == 0 check), otherwise the hw + * might lose the new ring register values. */ + I915_WRITE_START(ring, obj-gtt_offset); I915_WRITE_CTL(ring, ((ring-size - PAGE_SIZE) RING_NR_PAGES) | RING_VALID); -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: correctly order the ring init sequence
On Tue, Aug 07, 2012 at 03:32:42PM +0300, Jani Nikula wrote: On Tue, 07 Aug 2012, Daniel Vetter daniel.vet...@ffwll.ch wrote: We may only start to set up the new register values after having confirmed that the ring is truely off. Otherwise the hw might lose the newly written register values. This is caught later on in the init sequence, when we check whether the register writes have stuck. With or without (up to you) the comment clarification discussed in IRC, Reviewed-by: Jani Nikula jani.nik...@intel.com I'll fixup the comment when applying, but for reference the new proposal is: Initialize the ring. This must happen _after_ we've cleared the ring registers with the above sequence (the readback of the HEAD registers also enforces ordering), otherwise the hw might lose the new ring register values. Thanks for the review. -Daniel Cc: sta...@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 Tested-by: Yang Guang guang.a.y...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bf0195a..5b19917 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) I915_WRITE_HEAD(ring, 0); ring-write_tail(ring, 0); - /* Initialize the ring. */ -I915_WRITE_START(ring, obj-gtt_offset); head = I915_READ_HEAD(ring) HEAD_ADDR; /* G45 ring initialization fails to reset head to zero */ @@ -316,6 +314,10 @@ static int init_ring_common(struct intel_ring_buffer *ring) } } + /* Initialize the ring. This must happen _after_ we have confirmed that + * the ring is off (with the above head == 0 check), otherwise the hw + * might lose the new ring register values. */ + I915_WRITE_START(ring, obj-gtt_offset); I915_WRITE_CTL(ring, ((ring-size - PAGE_SIZE) RING_NR_PAGES) | RING_VALID); -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: correctly order the ring init sequence
On Tue, 07 Aug 2012, Jani Nikula jani.nik...@linux.intel.com wrote: On Tue, 07 Aug 2012, Daniel Vetter daniel.vet...@ffwll.ch wrote: We may only start to set up the new register values after having confirmed that the ring is truely off. Otherwise the hw might lose the newly written register values. This is caught later on in the init sequence, when we check whether the register writes have stuck. With or without (up to you) the comment clarification discussed in IRC, For the record, 15:14 danvet This must happen _after_ we've cleared the ring registers with the above sequence (the readback of the HEAD registers also enforces ordering), otherwise the hw might lose the new ring register values. Reviewed-by: Jani Nikula jani.nik...@intel.com Cc: sta...@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 Tested-by: Yang Guang guang.a.y...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_ringbuffer.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bf0195a..5b19917 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) I915_WRITE_HEAD(ring, 0); ring-write_tail(ring, 0); -/* Initialize the ring. */ -I915_WRITE_START(ring, obj-gtt_offset); head = I915_READ_HEAD(ring) HEAD_ADDR; /* G45 ring initialization fails to reset head to zero */ @@ -316,6 +314,10 @@ static int init_ring_common(struct intel_ring_buffer *ring) } } +/* Initialize the ring. This must happen _after_ we have confirmed that + * the ring is off (with the above head == 0 check), otherwise the hw + * might lose the new ring register values. */ +I915_WRITE_START(ring, obj-gtt_offset); I915_WRITE_CTL(ring, ((ring-size - PAGE_SIZE) RING_NR_PAGES) | RING_VALID); -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] intel_ddi.c
2012/8/6 ron minnich rminn...@gmail.com: As I read this new (to me) file I get the impression that it really applies to haswell and not the earlier parts, is that correct? Yes :) If you're running code from this file on older gens, please report the problem. thanks ron ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Fwd: Re: Macbook Pro Retina display problems
On Tue, Aug 07, 2012 at 06:08:51PM +1000, Francois Rigaut wrote: Daniel, nope, the hack didn't succeed. No apparent change. Ok, I've updated the reg_dumper to also dump the registers for pipe C. Can you please update your intel-gpu-tools checkout and then grab a new register dump for both i915 loaded and not loaded? To make comparing easier, please switch the panel to pipe C when i915 is loaded with $ xrandr --output eDP1 --auto --crtc 2 that way the register dumps are much easier to compare. Thanks, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: Haswell HDMI audio enable
Hi
2012/8/6 Wang Xingchao xingchao.w...@intel.com:
Configure the related HDMI audio register to generate an unsolicited
response to the audio controller driver to indicate that the controller
sequence should start.
Use pipe way to get correct register definitions for IBX/CPT/HSW.
Please split this patch in 2: one that just converts the IBX/CPT into
the PIPE macro, and another that adds the HSW regs.
Thanks,
Paulo
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 32 +++--
drivers/gpu/drm/i915/intel_display.c | 52
+++---
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed87de9..9588dd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4247,7 +4247,15 @@
#define G4X_HDMIW_HDMIEDID 0x6210C
#define IBX_HDMIW_HDMIEDID_A 0xE2050
+#define IBX_HDMIW_HDMIEDID_B 0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+ IBX_HDMIW_HDMIEDID_A, \
+ IBX_HDMIW_HDMIEDID_B)
#define IBX_AUD_CNTL_ST_A 0xE20B4
+#define IBX_AUD_CNTL_ST_B 0xE21B4
+#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+ IBX_AUD_CNTL_ST_A, \
+ IBX_AUD_CNTL_ST_B)
#define IBX_ELD_BUFFER_SIZE(0x1f 10)
#define IBX_ELD_ADDRESS(0x1f 5)
#define IBX_ELD_ACK(1 4)
@@ -4256,7 +4264,15 @@
#define IBX_CP_READYB (1 1)
#define CPT_HDMIW_HDMIEDID_A 0xE5050
+#define CPT_HDMIW_HDMIEDID_B 0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+ CPT_HDMIW_HDMIEDID_A, \
+ CPT_HDMIW_HDMIEDID_B)
#define CPT_AUD_CNTL_ST_A 0xE50B4
+#define CPT_AUD_CNTL_ST_B 0xE51B4
+#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+ CPT_AUD_CNTL_ST_A, \
+ CPT_AUD_CNTL_ST_B)
#define CPT_AUD_CNTRL_ST2 0xE50C0
/* These are the 4 32-bit write offset registers for each stream
@@ -4266,7 +4282,15 @@
#define GEN7_SO_WRITE_OFFSET(n)(0x5280 + (n) * 4)
#define IBX_AUD_CONFIG_A 0xe2000
+#define IBX_AUD_CONFIG_B 0xe2100
+#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
+ IBX_AUD_CONFIG_A, \
+ IBX_AUD_CONFIG_B)
#define CPT_AUD_CONFIG_A 0xe5000
+#define CPT_AUD_CONFIG_B 0xe5100
+#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
+ CPT_AUD_CONFIG_A, \
+ CPT_AUD_CONFIG_B)
#define AUD_CONFIG_N_VALUE_INDEX (1 29)
#define AUD_CONFIG_N_PROG_ENABLE (1 28)
#define AUD_CONFIG_UPPER_N_SHIFT 20
@@ -4296,7 +4320,7 @@
HSW_AUD_DIP_ELD_CTRL_ST_B)
#define HSW_AUD_PIPE_CONV_CFG0x6507c /*Audio pipe and
converter configs*/
-#define HSW_AUD_PIN_ELD_CP_VL0x650c0 /*Audio ELD and CP
Ready Status*/
+#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /*Audio ELD and CP Ready
Status*/
#define AUDIO_INACTIVE_C (111)
#define AUDIO_INACTIVE_B (17)
#define AUDIO_INACTIVE_A (13)
@@ -4317,7 +4341,11 @@
HSW_AUD_DIG_CNVT_1, \
HSW_AUD_DIG_CNVT_2)
-#define HSW_AUD_EDID_DATA0x65050
+#define HSW_AUD_EDID_DATA_A 0x65050
+#define HSW_AUD_EDID_DATA_B 0x65150
+#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
+ HSW_AUD_EDID_DATA_A, \
+ HSW_AUD_EDID_DATA_B)
#define TRANS_CONF_A 0xf0008
#define AUD_PB_UNSL_DEV_CP 0x65fb0
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 17020cd..103de56 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5071,6 +5071,7 @@ static void ironlake_write_eld(struct drm_connector
*connector,
struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = connector-dev-dev_private;
+ struct drm_device *dev = crtc-dev;
uint8_t *eld = connector-eld;
uint32_t eldv;
uint32_t i;
@@ -5079,23 +5080,52 @@ static void ironlake_write_eld(struct drm_connector
*connector,
int aud_config;
int aud_cntl_st;
int
Re: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs
Why using xxx_SDV_xxx in the macros ? Is there an official
Name for those chips ?Besides, what does CRW stands
For ?
Thanks,
-minskey
-Original Message-
From: intel-gfx-bounces+chaohong.guo=intel@lists.freedesktop.org
[mailto:intel-gfx-bounces+chaohong.guo=intel@lists.freedesktop.org] On
Behalf Of Paulo Zanoni
Sent: Tuesday, August 07, 2012 5:48 AM
To: intel-gfx@lists.freedesktop.org
Cc: Zanoni, Paulo R
Subject: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
src/intel_driver.h | 37 +++ src/intel_module.c | 73
++
2 files changed, 110 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h index 882d889..ac02cc7
100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -192,6 +192,43 @@
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
+#define PCI_CHIP_HASWELL_D_GT1 0x0402
+#define PCI_CHIP_HASWELL_D_GT2 0x0412
+#define PCI_CHIP_HASWELL_D_GT2_PLUS0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS0x042A
+#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
+#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS0x0C2A
+#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
+#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS0x0A2A
+#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS0x0D3A
+
#endif
#define I85X_CAPID 0x44
diff --git a/src/intel_module.c b/src/intel_module.c index ae19f75..c0403ca
100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT2, Ivybridge Desktop (GT2) },
{PCI_CHIP_IVYBRIDGE_S_GT1, Ivybridge Server },
{PCI_CHIP_IVYBRIDGE_S_GT2, Ivybridge Server (GT2) },
+ {PCI_CHIP_HASWELL_D_GT1,Haswell Desktop (GT1) },
+ {PCI_CHIP_HASWELL_D_GT2,Haswell Desktop (GT2) },
+ {PCI_CHIP_HASWELL_D_GT2_PLUS, Haswell Desktop (GT2+) },
+ {PCI_CHIP_HASWELL_M_GT1,Haswell Mobile (GT1) },
+ {PCI_CHIP_HASWELL_M_GT2,Haswell Mobile (GT2) },
+ {PCI_CHIP_HASWELL_M_GT2_PLUS, Haswell Mobile (GT2+) },
+ {PCI_CHIP_HASWELL_S_GT1,Haswell Server (GT1) },
+ {PCI_CHIP_HASWELL_S_GT2,Haswell Server (GT2) },
+ {PCI_CHIP_HASWELL_S_GT2_PLUS, Haswell Server (GT2+) },
+ {PCI_CHIP_HASWELL_SDV_D_GT1,Haswell SDV Desktop (GT1) },
+ {PCI_CHIP_HASWELL_SDV_D_GT2,Haswell SDV Desktop (GT2) },
+ {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, Haswell SDV Desktop (GT2+) },
+ {PCI_CHIP_HASWELL_SDV_M_GT1,Haswell SDV Mobile (GT1) },
+ {PCI_CHIP_HASWELL_SDV_M_GT2,Haswell SDV Mobile (GT2) },
+ {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, Haswell SDV Mobile (GT2+) },
+ {PCI_CHIP_HASWELL_SDV_S_GT1,Haswell SDV Server (GT1) },
+ {PCI_CHIP_HASWELL_SDV_S_GT2,Haswell SDV Server (GT2) },
+ {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, Haswell SDV Server (GT2+) },
+ {PCI_CHIP_HASWELL_ULT_D_GT1,Haswell ULT Desktop (GT1) },
+ {PCI_CHIP_HASWELL_ULT_D_GT2,Haswell ULT Desktop (GT2) },
+ {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, Haswell ULT Desktop (GT2+) },
+ {PCI_CHIP_HASWELL_ULT_M_GT1,Haswell ULT Mobile (GT1) },
+ {PCI_CHIP_HASWELL_ULT_M_GT2,Haswell ULT Mobile (GT2) },
+
Re: [Intel-gfx] [Mesa-dev] [PATCH mesa] i965: add more Haswell PCI IDs
2012/8/6 Kenneth Graunke kenn...@whitecape.org: On 08/06/2012 02:50 PM, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com Reviewed-by: Kenneth Graunke kenn...@whitecape.org Do you have push access? If not, I can commit this for you. I just discovered I have. Patch committed, thanks. -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] HD audio not working
Ref. to filed bug https://bugs.freedesktop.org/show_bug.cgi?id=49055: DTS-HD and Dolby TrueHD audio is not working in Intel Sandy Bridge. This must have been well known for quite some time now, and I consider this to be a serious error in the Intel driver. Due to this error it is not possible to play DTS-HD or Dolby-TrueHD on Linux. I have waited patiently several months for a fix, as I was confident that Intel knew about the problem and surely would fix this in the next driver release. I also have the understanding that quite many people are waiting for this fix. Seeing as the bug is filed, and someone has actually looked at it and identified the problem, is there a plan for further progress on this? Regards, -- Oyvind Kvalsvoll (+47) 41306243 NO-6008 Alesund, Norway ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/4] Haswell HDMI/DP audio enable
This patch series enable HDMI audio on Haswell platform, not DP audio. The DP enablement will come after the DP patches are upstream. I tested this patch on Sharkbay machine and i could hear clear sound from HDMI port. V2 patches fixed one warning and some type errors. V3 patches changes: - change some registers definitions - use macro for IBX/CPT/HSW to get registers - remove some unused variable intended to use in TODO list. v4 patches changes: - remove alsa related hack patch v5 patches changes: - change comments stype - split IBX/CTP registers patch into seperate one - remove unused register definition Here're some notes useful for you to test the patches on Sharkbay machine: I please make sure your branch include below three commits in Takashi's sound tree, othersiwe there's no proper Haswell ID and HDMI ID. For the upstream tree, please refer to sound git tree git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git You can just pull for-linus branch. The all commits above are found in 3.6-rc1. e926f2c850c472f813f9bab486c68a3fe0b03ae4 1c76684d2752b3a24bb7da183cc18e5d126dbcc9 bdbe34dece4942f4d8df9865dba7785bb813366a II No sound from HDMI/DP. we found it's not stable in current stage, sometimes you may not heard sound from HDMI or DP port, but most of the time you can heard clear sound. After some investigation, we suspect the HDA verb didnot really make codec change,and we regard the GPU register as the right one. (see III explanation) the easy way is to use intel_audio_dump to compare related registers, and make sure the port is enabled and unmute, otherwise there's no sound. intel_audio_tools has no support on Haswell yet, i wrote patches to make that happen, if you need the patches, please feel free to let me know. Here's part of the snapshot about port enable and mute status from intel_audio_dump: AUD_PORT_EN_HD_CFG Port_B_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_C_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_D_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status 1 AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status 0 AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status 1 you can see from above message, the Port C is enabled and unmute, that's what we expect. III HDA Codec dependency. When you found there's no sound from HDMI, please use intel_audio_dump to check Port enable/mute status in II and also check related Pipe/Transcoder/DDI port status. Sometimes the pipe and transcoder was disabled in dpms and will not work anymore, that results in the HDMI port no sound. HDA codec's three converters are somehow hardwired to audio Pipes and if you choose the pipe, that means the regarding Codec converter should be enabled too, and only one digital Pin's HDA verbs could work, that depends on whehter your Pin select the converter as input. Here's one example about the Pipe/Transcoder/DDI port(Pipe B, DDI Port C): DDI_BUF_CTL_A 0x0080 DDI Buffer Controler A DDI_BUF_CTL_B 0x DDI Buffer Controler B DDI_BUF_CTL_C 0x8000 DDI Buffer Controler C DDI_BUF_CTL_D 0x DDI Buffer Controler D DDI_BUF_CTL_E 0x8002 DDI Buffer Controler E PIPE_CONF_A 0xc000 PIPE Configuration A PIPE_CONF_B 0xc000 PIPE Configuration B PIPE_CONF_C 0x PIPE Configuration C PIPE_CONF_EDP 0x PIPE Configuration EDP PIPE_DDI_FUNC_CTL_A 0xc4034002 PIPE DDI Function Control A PIPE_DDI_FUNC_CTL_B 0xa0035000 PIPE DDI Function Control B PIPE_DDI_FUNC_CTL_C 0x0003 PIPE DDI Function Control C PIPE_DDI_FUNC_CTL_EDP 0x0003 PIPE DDI Function Control EDP Wang Xingchao (3): Wang Xingchao (4): drm/i915: HSW audio registers definition drm/i915: write eld info for HDMI audio drm/i915: Haswell HDMI audio enable drm/i915: use _PIPE macro for IBX/CPT register definition drivers/gpu/drm/i915/i915_reg.h | 71 ++ drivers/gpu/drm/i915/intel_ddi.c |6 ++- drivers/gpu/drm/i915/intel_display.c | 52 - 3 files changed, 118 insertions(+), 11 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/4] Haswell HDMI/DP audio enable
This patch series enable HDMI audio on Haswell platform, not DP audio. The DP enablement will come after the DP patches are upstream. I tested this patch on Sharkbay machine and i could hear clear sound from HDMI port. V2 patches fixed one warning and some type errors. V3 patches changes: - change some registers definitions - use macro for IBX/CPT/HSW to get registers - remove some unused variable intended to use in TODO list. v4 patches changes: - remove alsa related hack patch v5 patches changes: - change comments stype - split IBX/CTP registers patch into seperate one - remove unused register definition Here're some notes useful for you to test the patches on Sharkbay machine: I please make sure your branch include below three patches in Takashi's sound tree, othersiwe there's no proper Haswell ID and HDMI ID. http://git.alsa-project.org/?p=alsa-kmirror.git;a=commitdiff;h=79fc901301d6115b11457e8240ed6abc4b3f5c65 http://git.alsa-project.org/?p=alsa-kmirror.git;a=commitdiff;h=e269cee227a2b2297b79bfc71094c709b9387061 http://git.alsa-project.org/?p=alsa-kmirror.git;a=commitdiff;h=cb192625233496ac3d96cce667ebf4e322dab678 II No sound from HDMI/DP. we found it's not stable in current stage, sometimes you may not heard sound from HDMI or DP port, but most of the time you can heard clear sound. After some investigation, we suspect the HDA verb didnot really make codec change,and we regard the GPU register as the right one. (see III explanation) the easy way is to use intel_audio_dump to compare related registers, and make sure the port is enabled and unmute, otherwise there's no sound. intel_audio_tools has no support on Haswell yet, i wrote patches to make that happen, if you need the patches, please feel free to let me know. Here's part of the snapshot about port enable and mute status from intel_audio_dump: AUD_PORT_EN_HD_CFG Port_B_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_C_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_D_Out_Enable 1 AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status 1 AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status 0 AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status 1 you can see from above message, the Port C is enabled and unmute, that's what we expect. III HDA Codec dependency. When you found there's no sound from HDMI, please use intel_audio_dump to check Port enable/mute status in II and also check related Pipe/Transcoder/DDI port status. Sometimes the pipe and transcoder was disabled in dpms and will not work anymore, that results in the HDMI port no sound. HDA codec's three converters are somehow hardwired to audio Pipes and if you choose the pipe, that means the regarding Codec converter should be enabled too, and only one digital Pin's HDA verbs could work, that depends on whehter your Pin select the converter as input. Here's one example about the Pipe/Transcoder/DDI port(Pipe B, DDI Port C): DDI_BUF_CTL_A 0x0080 DDI Buffer Controler A DDI_BUF_CTL_B 0x DDI Buffer Controler B DDI_BUF_CTL_C 0x8000 DDI Buffer Controler C DDI_BUF_CTL_D 0x DDI Buffer Controler D DDI_BUF_CTL_E 0x8002 DDI Buffer Controler E PIPE_CONF_A 0xc000 PIPE Configuration A PIPE_CONF_B 0xc000 PIPE Configuration B PIPE_CONF_C 0x PIPE Configuration C PIPE_CONF_EDP 0x PIPE Configuration EDP PIPE_DDI_FUNC_CTL_A 0xc4034002 PIPE DDI Function Control A PIPE_DDI_FUNC_CTL_B 0xa0035000 PIPE DDI Function Control B PIPE_DDI_FUNC_CTL_C 0x0003 PIPE DDI Function Control C PIPE_DDI_FUNC_CTL_EDP 0x0003 PIPE DDI Function Control EDP Wang Xingchao (3): Wang Xingchao (4): drm/i915: HSW audio registers definition drm/i915: write eld info for HDMI audio drm/i915: Haswell HDMI audio enable drm/i915: use _PIPE macro for IBX/CPT register definition drivers/gpu/drm/i915/i915_reg.h | 71 ++ drivers/gpu/drm/i915/intel_ddi.c |6 ++- drivers/gpu/drm/i915/intel_display.c | 52 - 3 files changed, 118 insertions(+), 11 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/4] drm/i915: write eld info for HDMI audio
HDMI audio related registers will be configured in write_eld callback. Signed-off-by: Wang Xingchao xingchao.w...@intel.com --- drivers/gpu/drm/i915/intel_ddi.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 32604ac..4c12371 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -718,8 +718,12 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, /* Proper support for digital audio needs a new logic and a new set * of registers, so we leave it for future patch bombing. */ - DRM_DEBUG_DRIVER(HDMI audio on pipe %c not yet supported on DDI\n, + DRM_DEBUG_DRIVER(HDMI audio on pipe %c on DDI\n, pipe_name(intel_crtc-pipe)); + + /* write eld */ + DRM_DEBUG_DRIVER(HDMI audio: write eld information\n); + intel_write_eld(encoder, adjusted_mode); } /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 3/4] drm/i915: Haswell HDMI audio enable
Initialize Haswell HDMI audio registers to generate an unsolicited
response to the audio controller driver to indicate that the controller
sequence should start.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 17020cd..b635bf6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5071,6 +5071,7 @@ static void ironlake_write_eld(struct drm_connector
*connector,
struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = connector-dev-dev_private;
+ struct drm_device *dev = crtc-dev;
uint8_t *eld = connector-eld;
uint32_t eldv;
uint32_t i;
@@ -5079,12 +5080,18 @@ static void ironlake_write_eld(struct drm_connector
*connector,
int aud_config;
int aud_cntl_st;
int aud_cntrl_st2;
+ int pipe = to_intel_crtc(crtc)-pipe;
if (HAS_PCH_IBX(connector-dev)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
aud_config = IBX_AUD_CONFIG_A;
aud_cntl_st = IBX_AUD_CNTL_ST_A;
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+ } else if (IS_HASWELL(dev)) {
+ hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
+ aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
+ aud_config = HSW_AUD_CFG(pipe);
+ aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
} else {
hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
aud_config = CPT_AUD_CONFIG_A;
@@ -5092,6 +5099,34 @@ static void ironlake_write_eld(struct drm_connector
*connector,
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
}
+ if (IS_HASWELL(dev)) {
+ int tmp;
+ int aud_vld = HSW_AUD_PIN_ELD_CP_VLD;
+
+ DRM_DEBUG_DRIVER(HDMI: Haswell Audio initialize\n);
+
+ /* Audio output enable */
+ DRM_DEBUG_DRIVER(HDMI audio: enable codec\n);
+ tmp = I915_READ(aud_vld);
+ tmp |= (AUDIO_OUTPUT_ENABLE_A | AUDIO_OUTPUT_ENABLE_B |
AUDIO_OUTPUT_ENABLE_C);
+ I915_WRITE(aud_vld, tmp);
+
+ /* Set ELD valid state */
+ tmp = I915_READ(aud_vld);
+ DRM_DEBUG_DRIVER(HDMI audio: pin eld vld status=0x%8x\n, tmp);
+ tmp |= (AUDIO_ELD_VALID_A | AUDIO_ELD_VALID_B |
AUDIO_ELD_VALID_C);
+ I915_WRITE(aud_vld, tmp);
+ tmp = I915_READ(aud_vld);
+ DRM_DEBUG_DRIVER(HDMI audio: eld vld status=0x%8x\n, tmp);
+
+ /* Enable HDMI mode */
+ tmp = I915_READ(aud_config);
+ DRM_DEBUG_DRIVER(HDMI audio: audio conf: 0x%8x\n, tmp);
+ /* clear N_programing_enable and N_value_index */
+ tmp = ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
+ I915_WRITE(aud_config, tmp);
+ }
+
i = to_intel_crtc(crtc)-pipe;
hdmiw_hdmiedid += i * 0x100;
aud_cntl_st += i * 0x100;
@@ -5135,6 +5170,8 @@ static void ironlake_write_eld(struct drm_connector
*connector,
i = I915_READ(aud_cntl_st);
i = ~IBX_ELD_ADDRESS;
I915_WRITE(aud_cntl_st, i);
+ i = (i 29) 0x3;/* DIP_Port_Select, 0x1 = PortB */
+ DRM_DEBUG_DRIVER(port num:%d\n, i);
len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
DRM_DEBUG_DRIVER(ELD size %d\n, len);
--
1.7.9.5
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[Intel-gfx] [PATCH v5 4/4] drm/i915: use _PIPE macro for IBX/CPT register definition
Use _PIPE macro to get correct register definition for IBX/CPT, discard
old variable i way.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 24
drivers/gpu/drm/i915/intel_display.c | 17 ++---
2 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cf09ad..3d7a6a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4247,7 +4247,15 @@
#define G4X_HDMIW_HDMIEDID 0x6210C
#define IBX_HDMIW_HDMIEDID_A 0xE2050
+#define IBX_HDMIW_HDMIEDID_B 0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+ IBX_HDMIW_HDMIEDID_A, \
+ IBX_HDMIW_HDMIEDID_B)
#define IBX_AUD_CNTL_ST_A 0xE20B4
+#define IBX_AUD_CNTL_ST_B 0xE21B4
+#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+ IBX_AUD_CNTL_ST_A, \
+ IBX_AUD_CNTL_ST_B)
#define IBX_ELD_BUFFER_SIZE(0x1f 10)
#define IBX_ELD_ADDRESS(0x1f 5)
#define IBX_ELD_ACK(1 4)
@@ -4256,7 +4264,15 @@
#define IBX_CP_READYB (1 1)
#define CPT_HDMIW_HDMIEDID_A 0xE5050
+#define CPT_HDMIW_HDMIEDID_B 0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+ CPT_HDMIW_HDMIEDID_A, \
+ CPT_HDMIW_HDMIEDID_B)
#define CPT_AUD_CNTL_ST_A 0xE50B4
+#define CPT_AUD_CNTL_ST_B 0xE51B4
+#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+ CPT_AUD_CNTL_ST_A, \
+ CPT_AUD_CNTL_ST_B)
#define CPT_AUD_CNTRL_ST2 0xE50C0
/* These are the 4 32-bit write offset registers for each stream
@@ -4266,7 +4282,15 @@
#define GEN7_SO_WRITE_OFFSET(n)(0x5280 + (n) * 4)
#define IBX_AUD_CONFIG_A 0xe2000
+#define IBX_AUD_CONFIG_B 0xe2100
+#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
+ IBX_AUD_CONFIG_A, \
+ IBX_AUD_CONFIG_B)
#define CPT_AUD_CONFIG_A 0xe5000
+#define CPT_AUD_CONFIG_B 0xe5100
+#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
+ CPT_AUD_CONFIG_A, \
+ CPT_AUD_CONFIG_B)
#define AUD_CONFIG_N_VALUE_INDEX (1 29)
#define AUD_CONFIG_N_PROG_ENABLE (1 28)
#define AUD_CONFIG_UPPER_N_SHIFT 20
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b635bf6..103de56 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5083,9 +5083,9 @@ static void ironlake_write_eld(struct drm_connector
*connector,
int pipe = to_intel_crtc(crtc)-pipe;
if (HAS_PCH_IBX(connector-dev)) {
- hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
- aud_config = IBX_AUD_CONFIG_A;
- aud_cntl_st = IBX_AUD_CNTL_ST_A;
+ hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+ aud_config = IBX_AUD_CFG(pipe);
+ aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
} else if (IS_HASWELL(dev)) {
hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
@@ -5093,9 +5093,9 @@ static void ironlake_write_eld(struct drm_connector
*connector,
aud_config = HSW_AUD_CFG(pipe);
aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
} else {
- hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
- aud_config = CPT_AUD_CONFIG_A;
- aud_cntl_st = CPT_AUD_CNTL_ST_A;
+ hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+ aud_config = CPT_AUD_CFG(pipe);
+ aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
}
@@ -5127,11 +5127,6 @@ static void ironlake_write_eld(struct drm_connector
*connector,
I915_WRITE(aud_config, tmp);
}
- i = to_intel_crtc(crtc)-pipe;
- hdmiw_hdmiedid += i * 0x100;
- aud_cntl_st += i * 0x100;
- aud_config += i * 0x100;
-
DRM_DEBUG_DRIVER(ELD on pipe %c\n, pipe_name(i));
i = I915_READ(aud_cntl_st);
--
1.7.9.5
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