[Intel-gfx] [QA 10/19] Testing report for `drm-intel-testing` (was: Updated -next)
Summary We finished a new round of kernel testing. Generally, in this circle, one bug are re-opened, 12 bugs are still open. Test Environment Kernel: (drm-intel-testing)6760818aad5622d7f20d7f1c45d75a8165aeaf24 Some additional commit info: Merge: 39bc66c be3cd5e Author: Daniel Vetter Date: Fri Oct 12 12:24:12 2012 +0200 Hardware We covered the platform: IvyBridge, SandyBridge, IronLake Findings Reopened Bug: Bug 44309 - [IVB eDP] 3 pipe doesn't work with eDP monitor Open Bugs: Bug 41976 - [IVB] screen turn to be black while switching between console and x-window with 3-pipe active Bug 42194 - [IVB/SNB] coldplug new monitors for fbcon on lastclose() Bug 45729 - [bisected regression] Incorrect Mode Timing on DP Display, with 3.3-rc (due to interlaced CEA modes) Bug 50569 - [ILK] System reboot after S4 Bug 51975 - [IVB]can't find the HDMI audio device Bug 52424 - [Bisected SNB Regression] glxgears causes GPU hung Bug 54111 - [IVB]I-G-T/module_reload fail with *ERROR* "Memory manager not clean. Delaying takedown" Bug 54253 - [SNB]eDP can't work while booting with miniVGA Bug 55268 - [SNB] eDP can't light up after reboot with micro HDMI Bug 55276 - [SNB regression]some dp display modes can't light up Bug 54764 - [ILK regression] DP display some mode not able to light up Blocked Bug: Bug 55271 - [ILK regression] DP fail to light up after S4 with X and glxgears(blocked by 50569) Thanks --Sun, Yi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/14] drm/i915: convert pipe timing definitions to transcoder
On Thu, Oct 18, 2012 at 06:21:38PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Signed-off-by: Paulo Zanoni
Again, I think we can drop the hunks for the load detect code and the pch
stuff for now. For the pch stuff I think we'll better do that once we give
vga a good look.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 ++---
> drivers/gpu/drm/i915/i915_reg.h | 14 +-
> drivers/gpu/drm/i915/intel_crt.c | 6 ++---
> drivers/gpu/drm/i915/intel_display.c | 52
> +++-
> 4 files changed, 41 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c9b186d..31b266b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device
> *dev, int pipe,
> int vbl_start, vbl_end, htotal, vtotal;
> bool in_vbl = true;
> int ret = 0;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> if (!i915_pipe_enabled(dev, pipe)) {
> DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
> @@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device
> *dev, int pipe,
> }
>
> /* Get vtotal. */
> - vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
> + vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* No obvious pixelcount register. Only query vertical
> @@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device
> *dev, int pipe,
>*/
> position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK)
> >> PIPE_PIXEL_SHIFT;
>
> - htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
> + htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) &
> 0x1fff);
> *vpos = position / htotal;
> *hpos = position - (*vpos * htotal);
> }
>
> /* Query vblank area. */
> - vbl = I915_READ(VBLANK(pipe));
> + vbl = I915_READ(VBLANK(cpu_transcoder));
>
> /* Test position against vblank region. */
> vbl_start = vbl & 0x1fff;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b4f608..f22059e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1565,14 +1565,14 @@
> #define _VSYNCSHIFT_B0x61028
>
>
> -#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
> -#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
> -#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
> -#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
> -#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
> -#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
> +#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
> +#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> +#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
> +#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
> +#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
> +#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
> -#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
> +#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>
> /* VGA port control */
> #define ADPA 0x61100
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 2a2c976..6e96ba6 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -488,9 +488,9 @@ intel_crt_load_detect(struct intel_crt *crt)
> DRM_DEBUG_KMS("starting load-detect on CRT\n");
>
> bclrpat_reg = BCLRPAT(pipe);
> - vtotal_reg = VTOTAL(pipe);
> - vblank_reg = VBLANK(pipe);
> - vsync_reg = VSYNC(pipe);
> + vtotal_reg = VTOTAL(cpu_transcoder);
> + vblank_reg = VBLANK(cpu_transcoder);
> + vsync_reg = VSYNC(cpu_transcoder);
> pipeconf_reg = PIPECONF(cpu_transcoder);
> pipe_dsl_reg = PIPEDSL(pipe);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 95a4a5f..9202cb6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3019,14 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* set transcoder timing, panel must allow it */
> assert_panel_unlocked(dev_priv, pipe);
> - I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
> - I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
> - I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
> + I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(cpu_transcoder)));
> + I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(cpu_transcoder)))
Re: [Intel-gfx] [PATCH 07/14] drm/i915: convert CPU M/N timings to transcoder
On Thu, Oct 18, 2012 at 06:21:37PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Same thing as the previous commits. Not renaming this one since it
> exists since way before Haswell.
>
> Signed-off-by: Paulo Zanoni
Again I think we can drop the fdi hunks here. We better keep the set_m_n
hunks (I think we only need the dp one though), since that part of the
code is a convoluted mess and needs a cleanup. I have plans for pre-hsw
pch platforms ;-)
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16
> drivers/gpu/drm/i915/intel_display.c | 12 ++--
> drivers/gpu/drm/i915/intel_dp.c | 10 ++
> 3 files changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9eab732..5b4f608 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3304,14 +3304,14 @@
> #define _PIPEB_LINK_M2 0x61048
> #define _PIPEB_LINK_N2 0x6104c
>
> -#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> -#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> -#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> -#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> -#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> -#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> -#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> -#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
> +#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> +#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> +#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> +#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> +#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> +#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> +#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> +#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
>
> /* CPU panel fitter */
> /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index dc93c39..95a4a5f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2689,7 +2689,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc
> *intel_crtc)
>
> /* Write the TU size bits so error detection works */
> I915_WRITE(FDI_RX_TUSIZE1(pipe),
> -I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
>
> /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
> reg = FDI_RX_CTL(pipe);
> @@ -4847,7 +4847,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> struct intel_encoder *intel_encoder, *edp_encoder = NULL;
> struct fdi_m_n m_n = {0};
> int target_clock, pixel_multiplier, lane, link_bw;
> @@ -4910,10 +4910,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
> ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
>&m_n);
>
> - I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> - I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> - I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> - I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> + I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
> + I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
> + I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
> + I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
> }
>
> static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 697b176..244cb6a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -791,6 +791,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
> drm_display_mode *mode,
> int lane_count = 4;
> struct intel_dp_m_n m_n;
> int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>
> /*
>* Find the lane count in the intel_encoder private
> @@ -815,10 +816,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
> drm_display_mode *mode,
>mode->clock, adjusted_mode->clock, &m_n);
>
>
Re: [Intel-gfx] [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe
On Thu, Oct 18, 2012 at 06:21:35PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Because the PIPECONF register is actually part of the CPU transcoder,
> not the CPU pipe.
>
> Ideally we would also rename PIPECONF to TRANSCONF to remind people
> that they should use the transcoder instead of the pipe, but let's
> keep it like this for now since most Gens still name it PIPECONF.
>
> Signed-off-by: Paulo Zanoni
I think as a general rule it makes sense to not convert codepaths that are
never run on haswell to cpu_transcoder, since that thing really doesn't
exist that much on earlier platforms. Also, it makes the patch smaller ;-)
Below some comments about which hunks I think we can drop.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 ++-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 6 ++--
> drivers/gpu/drm/i915/intel_display.c | 61
> ++--
> drivers/gpu/drm/i915/intel_sprite.c | 3 +-
> drivers/gpu/drm/i915/intel_tv.c | 4 +--
> 6 files changed, 49 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d07c787..c9b186d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -123,7 +123,9 @@ static int
> i915_pipe_enabled(struct drm_device *dev, int pipe)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> - return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
> +
> + return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
> }
Oh, how I hate our vblank code and it's insistency to deal with pipes
instead of crtc numbers.
>
> /* Called from drm generic code, passed a 'crtc', which
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 72a61b5..9fecd3b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2714,7 +2714,7 @@
> #define PIPE_12BPC (3 << 5)
>
> #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
> -#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
> +#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
> #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
> #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
> #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 53f3e87..2a2c976 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -467,7 +467,9 @@ intel_crt_load_detect(struct intel_crt *crt)
> {
> struct drm_device *dev = crt->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crt->base.base.crtc);
> + enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t save_bclrpat;
> uint32_t save_vtotal;
> uint32_t vtotal, vactive;
> @@ -489,7 +491,7 @@ intel_crt_load_detect(struct intel_crt *crt)
> vtotal_reg = VTOTAL(pipe);
> vblank_reg = VBLANK(pipe);
> vsync_reg = VSYNC(pipe);
> - pipeconf_reg = PIPECONF(pipe);
> + pipeconf_reg = PIPECONF(cpu_transcoder);
> pipe_dsl_reg = PIPEDSL(pipe);
>
> save_bclrpat = I915_READ(bclrpat_reg);
Load detect is only used by gen2/3 vga connectors and by the tv out
connector, nothing else. So I think we can just leave this as-is.
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 827c5ba..dc93c39 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1008,9 +1008,10 @@ void intel_wait_for_vblank(struct drm_device *dev, int
> pipe)
> void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> - int reg = PIPECONF(pipe);
> + int reg = PIPECONF(cpu_transcoder);
>
> /* Wait for the Pipe State to go off */
> if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
> @@ -1222,12 +1223,13 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> int reg;
> u32 val;
> bool cur_state;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> /* if we need the pipe A quirk it must be always on */
> if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
> state = true;
>
> - reg = PIPECONF(pipe);
> + reg = PIPECONF(cpu_transcoder
Re: [Intel-gfx] [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
On Thu, Oct 18, 2012 at 06:21:34PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We need to check if any of the pipes is using TRANSCODER_EDP.
>
> Signed-off-by: Paulo Zanoni
I wonder whether it doesn't make more sense for haswell to return the
transcoder in the encoder->get_hw_state function, and then map that to the
crtc with the intel_pipe_to_cpu_transcoder. That way we don't need to add
a special-case for eDP.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 73ce007..827c5ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8551,6 +8551,31 @@ void intel_modeset_setup_hw_state(struct drm_device
> *dev)
> struct intel_encoder *encoder;
> struct intel_connector *connector;
>
> + if (IS_HASWELL(dev)) {
> + tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
> +
> + if (tmp & TRANS_DDI_FUNC_ENABLE) {
> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + case TRANS_DDI_EDP_INPUT_A_ONOFF:
> + pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + pipe = PIPE_C;
> + break;
> + }
> +
> + crtc =
> to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> + crtc->cpu_transcoder = TRANSCODER_EDP;
> +
> + DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
> + pipe_name(pipe));
> + }
> + }
> +
> for_each_pipe(pipe) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>
> --
> 1.7.11.4
>
> ___
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 01/14] drm/i915: add TRANSCODER_EDP
On Thu, Oct 18, 2012 at 06:21:31PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Before Haswell we used to have the CPU pipes and the PCH transcoders.
> We had the same amount of pipes and transcoders, and there was a 1:1
> mapping between them. After Haswell what we used to call CPU pipe was
> split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
> B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
> (only used for VGA).
>
> For all the outputs except for EDP we have an 1:1 mapping on the CPU
> pipes and CPU transcoders, so if you're using CPU pipe A you have to
> use CPU transcoder A. When have an eDP output you have to use
> transcoder EDP and you can attach this CPU transcoder to any of the 3
> CPU pipes. When using VGA you need to select a pair of matching CPU
> pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
> PCH transcoder.
>
> For now we're just creating the cpu_transcoder definitions and setting
> cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
> registers was ported to use transcoder instead of pipe. The goal is to
> keep the code backwards-compatible since on all cases except when
> using eDP we must have pipe == cpu_transcoder.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 18 ++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4728d30..922ab8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -58,6 +58,14 @@ enum pipe {
> };
> #define pipe_name(p) ((p) + 'A')
>
> +enum transcoder {
> + TRANSCODER_A = 0,
> + TRANSCODER_B,
> + TRANSCODER_C,
> + TRANSCODER_EDP = 0xF,
> +};
> +#define transcoder_name(t) ((t) + 'A')
> +
> enum plane {
> PLANE_A = 0,
> PLANE_B,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c31ee5b..c3fd536 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
> +#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
>
> #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c2c219b..6bf5ea8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit,
> struct drm_crtc *crtc,
> return true;
> }
>
> +enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> +enum pipe pipe)
> +{
> + struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + return intel_crtc->cpu_transcoder;
> +}
We need int intel_ prefix on this to avoid polluting the global namespace.
-Daniel
> +
> static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
>
> static void haswell_crtc_off(struct drm_crtc *crtc)
> {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + intel_crtc->cpu_transcoder = intel_crtc->pipe;
> intel_ddi_put_crtc_pll(crtc);
> }
>
> @@ -5212,6 +5224,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> num_connectors++;
> }
>
> + if (is_cpu_edp)
> + intel_crtc->cpu_transcoder = TRANSCODER_EDP;
> + else
> + intel_crtc->cpu_transcoder = pipe;
> +
> /* We are not sure yet this won't happen. */
> WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
>INTEL_PCH_TYPE(dev));
> @@ -7770,6 +7787,7 @@ static void intel_crtc_init(struct drm_device *dev, int
> pipe)
> /* Swap pipes & planes for FBC on pre-965 */
> intel_crtc->pipe = pipe;
> intel_crtc->plane = pipe;
> + intel_crtc->cpu_transcoder = pipe;
> if (IS_MOBILE(dev) && IS_GEN3(dev)) {
> DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
> intel_crtc->plane = !pipe;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 95cbd67..8f6eee5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -185,6 +185,7 @@ struct intel_crtc {
> struct drm_crtc base;
> enum pipe pipe;
> enum plane plane;
> + enum transcoder cpu_transcoder;
> u8 lut_r[256], lut_g[256], lut_b[256];
> /*
>* Whether the crtc and the connected output pipeline is active. Implies
>
[Intel-gfx] [PATCH 14/14] drm/i915: enable DDI eDP
From: Paulo Zanoni
Now that all the eDP enablement bits are there, we can actually try to
use the eDP.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 91f126b..4890f67 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -242,8 +242,8 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
switch(port){
case PORT_A:
- /* We don't handle eDP and DP yet */
DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
+ intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A);
break;
/* Assume that the ports B, C and D are working in HDMI mode for now */
case PORT_B:
--
1.7.11.4
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[Intel-gfx] [PATCH 13/14] drm/i915: turn the eDP DDI panel on/off
From: Paulo Zanoni
It's an important step :)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 18 --
drivers/gpu/drm/i915/intel_dp.c | 11 ---
drivers/gpu/drm/i915/intel_drv.h | 4
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 48eb125..91f126b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1162,12 +1162,19 @@ void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
- WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ ironlake_edp_panel_vdd_on(intel_dp);
+ ironlake_edp_panel_on(intel_dp);
+ ironlake_edp_panel_vdd_off(intel_dp, true);
+ }
+ WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
- if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -1195,6 +1202,7 @@ void intel_ddi_post_disable(struct intel_encoder
*intel_encoder)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
uint32_t val;
bool wait = false;
@@ -1213,6 +1221,12 @@ void intel_ddi_post_disable(struct intel_encoder
*intel_encoder)
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ ironlake_edp_panel_vdd_on(intel_dp);
+ ironlake_edp_panel_off(intel_dp);
+ }
+
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f241f49..14921a8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -667,9 +667,6 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
return -EREMOTEIO;
}
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-
static int
intel_dp_i2c_init(struct intel_dp *intel_dp,
struct intel_connector *intel_connector, const char *name)
@@ -1018,7 +1015,7 @@ static u32 ironlake_get_pp_control(struct
drm_i915_private *dev_priv)
return control;
}
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1088,7 +1085,7 @@ static void ironlake_panel_vdd_work(struct work_struct
*__work)
mutex_unlock(&dev->mode_config.mutex);
}
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
if (!is_edp(intel_dp))
return;
@@ -,7 +1108,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp, bool sync)
}
}
-static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1153,7 +1150,7 @@ static void ironlake_edp_panel_on(struct intel_dp
*intel_dp)
}
}
-static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
+void ironlake_edp_panel_off(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7247950..b9eb888 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -430,6 +430,10 @@ extern void intel_dp_sink_dpms(struct intel_dp *intel_dp,
int mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
+extern void ironlak
[Intel-gfx] [PATCH 12/14] drm/i915: set/unset the DDI eDP backlight
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 15 +--
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 6 --
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5e21bc1..48eb125 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1230,12 +1230,23 @@ void intel_enable_ddi(struct intel_encoder
*intel_encoder)
* enabling the port.
*/
I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
+ } else if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ ironlake_edp_backlight_on(intel_dp);
}
}
-void intel_disable_ddi(struct intel_encoder *encoder)
+void intel_disable_ddi(struct intel_encoder *intel_encoder)
{
- /* This will be needed in the future, so leave it here for now */
+ struct drm_encoder *encoder = &intel_encoder->base;
+ int type = intel_encoder->type;
+
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ ironlake_edp_backlight_off(intel_dp);
+ }
}
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9486f11..f241f49 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1178,7 +1178,7 @@ static void ironlake_edp_panel_off(struct intel_dp
*intel_dp)
ironlake_wait_panel_off(intel_dp);
}
-static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1201,7 +1201,7 @@ static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp)
POSTING_READ(PCH_PP_CONTROL);
}
-static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed436d0..7247950 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -428,6 +428,8 @@ extern void intel_dp_start_link_train(struct intel_dp
*intel_dp);
extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
+extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
struct drm_display_mode *mode);
@@ -586,8 +588,8 @@ extern void intel_disable_gt_powersave(struct drm_device
*dev);
extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
extern void ironlake_teardown_rc6(struct drm_device *dev);
-extern void intel_enable_ddi(struct intel_encoder *encoder);
-extern void intel_disable_ddi(struct intel_encoder *encoder);
+extern void intel_enable_ddi(struct intel_encoder *intel_encoder);
+extern void intel_disable_ddi(struct intel_encoder *intel_encoder);
extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe);
extern void intel_ddi_mode_set(struct drm_encoder *encoder,
--
1.7.11.4
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[Intel-gfx] [PATCH 11/14] drm/i915: set the correct eDP aux channel clock divider on DDI
From: Paulo Zanoni
The cdclk frequency is not always the same, so the value here should
be adjusted to match it.
Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 08881f1..5e21bc1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1238,7 +1238,7 @@ void intel_disable_ddi(struct intel_encoder *encoder)
/* This will be needed in the future, so leave it here for now */
}
-static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
+int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
return 450;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 244cb6a..9486f11 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -386,7 +386,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_cpu_edp(intel_dp)) {
- if (IS_VALLEYVIEW(dev))
+ if (IS_HASWELL(dev))
+ aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv)
>> 1;
+ else if (IS_VALLEYVIEW(dev))
aux_clock_divider = 100;
else if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock
at 400Mhz */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5bc1ddd..ed436d0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -593,6 +593,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
extern void intel_ddi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
+extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
extern void intel_ddi_pll_init(struct drm_device *dev);
extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
extern void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv,
--
1.7.11.4
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[Intel-gfx] [PATCH 10/14] drm/i915: select the correct pipe when using TRANSCODER_EDP
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c30cb14..08881f1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -954,6 +954,23 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DDI_PHSYNC;
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ switch (pipe) {
+ case PIPE_A:
+ temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
+ break;
+ case PIPE_B:
+ temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+ break;
+ case PIPE_C:
+ temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ }
+
if (type == INTEL_OUTPUT_HDMI) {
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
--
1.7.11.4
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[Intel-gfx] [PATCH 09/14] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP
From: Paulo Zanoni
See the documentation for the DDI_FUNC_CTL register, EDP Input Select
bits: when the EDP input selection is B, the VTOTAL_B must be
programmed with the VTOTAL_EDP value, same thing for selection C.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9202cb6..cc859b3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4376,6 +4376,17 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
+ /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
+* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
+* documented on the DDI_FUNC_CTL register description, EDP Input Select
+* bits. */
+ if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+ (pipe == PIPE_B || pipe == PIPE_C)) {
+ I915_WRITE(VTOTAL(pipe),
+ (adjusted_mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ }
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
--
1.7.11.4
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[Intel-gfx] [PATCH 08/14] drm/i915: convert pipe timing definitions to transcoder
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 7 ++---
drivers/gpu/drm/i915/i915_reg.h | 14 +-
drivers/gpu/drm/i915/intel_crt.c | 6 ++---
drivers/gpu/drm/i915/intel_display.c | 52 +++-
4 files changed, 41 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c9b186d..31b266b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev,
int pipe,
int vbl_start, vbl_end, htotal, vtotal;
bool in_vbl = true;
int ret = 0;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
if (!i915_pipe_enabled(dev, pipe)) {
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev,
int pipe,
}
/* Get vtotal. */
- vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+ vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
if (INTEL_INFO(dev)->gen >= 4) {
/* No obvious pixelcount register. Only query vertical
@@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device
*dev, int pipe,
*/
position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK)
>> PIPE_PIXEL_SHIFT;
- htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+ htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) &
0x1fff);
*vpos = position / htotal;
*hpos = position - (*vpos * htotal);
}
/* Query vblank area. */
- vbl = I915_READ(VBLANK(pipe));
+ vbl = I915_READ(VBLANK(cpu_transcoder));
/* Test position against vblank region. */
vbl_start = vbl & 0x1fff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b4f608..f22059e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1565,14 +1565,14 @@
#define _VSYNCSHIFT_B 0x61028
-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
/* VGA port control */
#define ADPA 0x61100
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 2a2c976..6e96ba6 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -488,9 +488,9 @@ intel_crt_load_detect(struct intel_crt *crt)
DRM_DEBUG_KMS("starting load-detect on CRT\n");
bclrpat_reg = BCLRPAT(pipe);
- vtotal_reg = VTOTAL(pipe);
- vblank_reg = VBLANK(pipe);
- vsync_reg = VSYNC(pipe);
+ vtotal_reg = VTOTAL(cpu_transcoder);
+ vblank_reg = VBLANK(cpu_transcoder);
+ vsync_reg = VSYNC(cpu_transcoder);
pipeconf_reg = PIPECONF(cpu_transcoder);
pipe_dsl_reg = PIPEDSL(pipe);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 95a4a5f..9202cb6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3019,14 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
- I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
- I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
- I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
+ I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(cpu_transcoder)));
+ I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(cpu_transcoder)));
+ I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(cpu_transcoder)));
- I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
- I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
- I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
- I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
+ I915_WRITE(TRANS_VTOTAL(pipe),
[Intel-gfx] [PATCH 07/14] drm/i915: convert CPU M/N timings to transcoder
From: Paulo Zanoni
Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 16
drivers/gpu/drm/i915/intel_display.c | 12 ++--
drivers/gpu/drm/i915/intel_dp.c | 10 ++
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9eab732..5b4f608 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3304,14 +3304,14 @@
#define _PIPEB_LINK_M2 0x61048
#define _PIPEB_LINK_N2 0x6104c
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dc93c39..95a4a5f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2689,7 +2689,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc)
/* Write the TU size bits so error detection works */
I915_WRITE(FDI_RX_TUSIZE1(pipe),
- I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+ I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
reg = FDI_RX_CTL(pipe);
@@ -4847,7 +4847,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct intel_encoder *intel_encoder, *edp_encoder = NULL;
struct fdi_m_n m_n = {0};
int target_clock, pixel_multiplier, lane, link_bw;
@@ -4910,10 +4910,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
&m_n);
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
}
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 697b176..244cb6a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,6 +791,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
drm_display_mode *mode,
int lane_count = 4;
struct intel_dp_m_n m_n;
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
/*
* Find the lane count in the intel_encoder private
@@ -815,10 +816,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
drm_display_mode *mode,
mode->clock, adjusted_mode->clock, &m_n);
if (IS_HASWELL(dev)) {
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
+ TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_D
[Intel-gfx] [PATCH 06/14] drm/i915: convert PIPE_MSA_MISC to transcoder
From: Paulo Zanoni
Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 19 ++-
drivers/gpu/drm/i915/intel_ddi.c | 18 +-
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fecd3b..9eab732 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4552,15 +4552,16 @@
#define TRANS_CLK_SEL_DISABLED(0x0<<29)
#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
-#define _PIPEA_MSA_MISC0x60410
-#define _PIPEB_MSA_MISC0x61410
-#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
-#define PIPE_MSA_SYNC_CLK (1<<0)
-#define PIPE_MSA_6_BPC(0<<5)
-#define PIPE_MSA_8_BPC(1<<5)
-#define PIPE_MSA_10_BPC (2<<5)
-#define PIPE_MSA_12_BPC (3<<5)
-#define PIPE_MSA_16_BPC (4<<5)
+#define _TRANSA_MSA_MISC 0x60410
+#define _TRANSB_MSA_MISC 0x61410
+#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
+ _TRANSB_MSA_MISC)
+#define TRANS_MSA_SYNC_CLK(1<<0)
+#define TRANS_MSA_6_BPC (0<<5)
+#define TRANS_MSA_8_BPC (1<<5)
+#define TRANS_MSA_10_BPC (2<<5)
+#define TRANS_MSA_12_BPC (3<<5)
+#define TRANS_MSA_16_BPC (4<<5)
/* LCPLL Control */
#define LCPLL_CTL 0x130040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8d3ce3a..c30cb14 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
- temp = PIPE_MSA_SYNC_CLK;
+ temp = TRANS_MSA_SYNC_CLK;
switch (intel_crtc->bpp) {
case 18:
- temp |= PIPE_MSA_6_BPC;
+ temp |= TRANS_MSA_6_BPC;
break;
case 24:
- temp |= PIPE_MSA_8_BPC;
+ temp |= TRANS_MSA_8_BPC;
break;
case 30:
- temp |= PIPE_MSA_10_BPC;
+ temp |= TRANS_MSA_10_BPC;
break;
case 36:
- temp |= PIPE_MSA_12_BPC;
+ temp |= TRANS_MSA_12_BPC;
break;
default:
- temp |= PIPE_MSA_8_BPC;
- WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ temp |= TRANS_MSA_8_BPC;
+ WARN(1, "%d bpp unsupported by DDI function\n",
intel_crtc->bpp);
}
- I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+ I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
}
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe
From: Paulo Zanoni
Because the PIPECONF register is actually part of the CPU transcoder,
not the CPU pipe.
Ideally we would also rename PIPECONF to TRANSCONF to remind people
that they should use the transcoder instead of the pipe, but let's
keep it like this for now since most Gens still name it PIPECONF.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 6 ++--
drivers/gpu/drm/i915/intel_display.c | 61 ++--
drivers/gpu/drm/i915/intel_sprite.c | 3 +-
drivers/gpu/drm/i915/intel_tv.c | 4 +--
6 files changed, 49 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d07c787..c9b186d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -123,7 +123,9 @@ static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
- return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
+
+ return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
}
/* Called from drm generic code, passed a 'crtc', which
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72a61b5..9fecd3b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2714,7 +2714,7 @@
#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
-#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
+#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 53f3e87..2a2c976 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -467,7 +467,9 @@ intel_crt_load_detect(struct intel_crt *crt)
{
struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crt->base.base.crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t save_bclrpat;
uint32_t save_vtotal;
uint32_t vtotal, vactive;
@@ -489,7 +491,7 @@ intel_crt_load_detect(struct intel_crt *crt)
vtotal_reg = VTOTAL(pipe);
vblank_reg = VBLANK(pipe);
vsync_reg = VSYNC(pipe);
- pipeconf_reg = PIPECONF(pipe);
+ pipeconf_reg = PIPECONF(cpu_transcoder);
pipe_dsl_reg = PIPEDSL(pipe);
save_bclrpat = I915_READ(bclrpat_reg);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 827c5ba..dc93c39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1008,9 +1008,10 @@ void intel_wait_for_vblank(struct drm_device *dev, int
pipe)
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
if (INTEL_INFO(dev)->gen >= 4) {
- int reg = PIPECONF(pipe);
+ int reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
@@ -1222,12 +1223,13 @@ void assert_pipe(struct drm_i915_private *dev_priv,
int reg;
u32 val;
bool cur_state;
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
/* if we need the pipe A quirk it must be always on */
if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
state = true;
- reg = PIPECONF(pipe);
+ reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg);
cur_state = !!(val & PIPECONF_ENABLE);
WARN(cur_state != state,
@@ -1661,6 +1663,7 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
int reg;
u32 val, pipeconf_val;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
@@ -1680,7 +1683,7 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
}
reg = TRANSCONF(pipe);
val = I915_READ(reg);
- pipeconf_val = I915_READ(PIPECONF(pipe));
+ pipeconf
[Intel-gfx] [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
From: Paulo Zanoni
We need to check if any of the pipes is using TRANSCODER_EDP.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 73ce007..827c5ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8551,6 +8551,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
struct intel_encoder *encoder;
struct intel_connector *connector;
+ if (IS_HASWELL(dev)) {
+ tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
+
+ if (tmp & TRANS_DDI_FUNC_ENABLE) {
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ case TRANS_DDI_EDP_INPUT_A_ONOFF:
+ pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ pipe = PIPE_C;
+ break;
+ }
+
+ crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ crtc->cpu_transcoder = TRANSCODER_EDP;
+
+ DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
+ pipe_name(pipe));
+ }
+ }
+
for_each_pipe(pipe) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
--
1.7.11.4
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[Intel-gfx] [PATCH 03/14] drm/i915: convert DDI_FUNC_CTL to transcoder
From: Paulo Zanoni Because there's one instance of the register per CPU transcoder and not per CPU pipe. This is another register that appeared for the first time on Haswell, and even though its Haswell name is PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's just use the new naming scheme before it confuses more people. Notice that there's a big improvement on intel_ddi_get_hw_state due to the new TRANSCODER_EDP. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 59 +++-- drivers/gpu/drm/i915/intel_ddi.c | 100 ++- drivers/gpu/drm/i915/intel_display.c | 8 +-- drivers/gpu/drm/i915/intel_drv.h | 4 +- 4 files changed, 102 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 32cad88..72a61b5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4395,34 +4395,39 @@ #define HSW_PWR_WELL_CTL6 0x45414 /* Per-pipe DDI Function Control */ -#define PIPE_DDI_FUNC_CTL_A0x60400 -#define PIPE_DDI_FUNC_CTL_B0x61400 -#define PIPE_DDI_FUNC_CTL_C0x62400 -#define PIPE_DDI_FUNC_CTL_EDP 0x6F400 -#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \ - PIPE_DDI_FUNC_CTL_B) -#define PIPE_DDI_FUNC_ENABLE (1<<31) +#define TRANS_DDI_FUNC_CTL_A 0x60400 +#define TRANS_DDI_FUNC_CTL_B 0x61400 +#define TRANS_DDI_FUNC_CTL_C 0x62400 +#define TRANS_DDI_FUNC_CTL_EDP 0x6F400 +#define DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ +TRANS_DDI_FUNC_CTL_B) +#define TRANS_DDI_FUNC_ENABLE (1<<31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ -#define PIPE_DDI_PORT_MASK(7<<28) -#define PIPE_DDI_SELECT_PORT(x) ((x)<<28) -#define PIPE_DDI_PORT_NONE(0<<28) -#define PIPE_DDI_MODE_SELECT_MASK (7<<24) -#define PIPE_DDI_MODE_SELECT_HDMI (0<<24) -#define PIPE_DDI_MODE_SELECT_DVI (1<<24) -#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) -#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) -#define PIPE_DDI_MODE_SELECT_FDI (4<<24) -#define PIPE_DDI_BPC_MASK (7<<20) -#define PIPE_DDI_BPC_8(0<<20) -#define PIPE_DDI_BPC_10 (1<<20) -#define PIPE_DDI_BPC_6(2<<20) -#define PIPE_DDI_BPC_12 (3<<20) -#define PIPE_DDI_PVSYNC (1<<17) -#define PIPE_DDI_PHSYNC (1<<16) -#define PIPE_DDI_BFI_ENABLE (1<<4) -#define PIPE_DDI_PORT_WIDTH_X1(0<<1) -#define PIPE_DDI_PORT_WIDTH_X2(1<<1) -#define PIPE_DDI_PORT_WIDTH_X4(3<<1) +#define TRANS_DDI_PORT_MASK (7<<28) +#define TRANS_DDI_SELECT_PORT(x) ((x)<<28) +#define TRANS_DDI_PORT_NONE (0<<28) +#define TRANS_DDI_MODE_SELECT_MASK(7<<24) +#define TRANS_DDI_MODE_SELECT_HDMI(0<<24) +#define TRANS_DDI_MODE_SELECT_DVI (1<<24) +#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) +#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) +#define TRANS_DDI_MODE_SELECT_FDI (4<<24) +#define TRANS_DDI_BPC_MASK(7<<20) +#define TRANS_DDI_BPC_8 (0<<20) +#define TRANS_DDI_BPC_10 (1<<20) +#define TRANS_DDI_BPC_6 (2<<20) +#define TRANS_DDI_BPC_12 (3<<20) +#define TRANS_DDI_PVSYNC (1<<17) +#define TRANS_DDI_PHSYNC (1<<16) +#define TRANS_DDI_EDP_INPUT_MASK (7<<12) +#define TRANS_DDI_EDP_INPUT_A_ON (0<<12) +#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) +#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) +#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) +#define TRANS_DDI_BFI_ENABLE (1<<4) +#define TRANS_DDI_PORT_WIDTH_X1 (0<<1) +#define TRANS_DDI_PORT_WIDTH_X2 (1<<1) +#define TRANS_DDI_PORT_WIDTH_X4 (3<<1) /* DisplayPort Transport Control */ #define DP_TP_CTL_A0x64040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f568862..8d3ce3a 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -924,68 +924,69 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) struct drm_encoder *encoder = &intel_encoder->base; struct drm_i915_private *dev_priv = crtc->dev->dev_private; enum pipe pipe = intel_crtc->pipe; + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; int type = intel_encoder->type; uint32_t temp; - /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */ - temp = PIPE_DDI_FUNC_ENABLE; + /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ + temp = TRANS_DDI_FUNC_ENABLE; switch (intel_crtc->b
[Intel-gfx] [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder
From: Paulo Zanoni
This register appeared in Haswell. It does not have an EDP version
because the EDP transcoder is always tied to the DDIA clock. Notice
that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder
is TRANSCODER_EDP we might introduce a bug, that's why this is a
transcoder register even though it does not have an EDP version.
Even though Haswell names this register PIPE_CLK_SEL, it will be
renamed to TRANS_CLK_SEL in the future, so let's just start using the
real name that makes more sense and avoids misusage.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++---
drivers/gpu/drm/i915/intel_ddi.c | 10 --
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3fd536..32cad88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4539,13 +4539,13 @@
#define PORT_CLK_SEL_WRPLL2 (5<<29)
#define PORT_CLK_SEL_NONE (7<<29)
-/* Pipe clock selection */
-#define PIPE_CLK_SEL_A 0x46140
-#define PIPE_CLK_SEL_B 0x46144
-#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
-/* For each pipe, we need to select the corresponding port clock */
-#define PIPE_CLK_SEL_DISABLED (0x0<<29)
-#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
+/* Transcoder clock selection */
+#define TRANS_CLK_SEL_A0x46140
+#define TRANS_CLK_SEL_B0x46144
+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
+/* For each transcoder, we need to select the corresponding port clock */
+#define TRANS_CLK_SEL_DISABLED(0x0<<29)
+#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
#define _PIPEA_MSA_MISC0x60410
#define _PIPEB_MSA_MISC0x61410
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 81cca48..f568862 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1095,15 +1095,21 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
- I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
}
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
- I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
}
void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
--
1.7.11.4
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[Intel-gfx] [PATCH 01/14] drm/i915: add TRANSCODER_EDP
From: Paulo Zanoni
Before Haswell we used to have the CPU pipes and the PCH transcoders.
We had the same amount of pipes and transcoders, and there was a 1:1
mapping between them. After Haswell what we used to call CPU pipe was
split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
(only used for VGA).
For all the outputs except for EDP we have an 1:1 mapping on the CPU
pipes and CPU transcoders, so if you're using CPU pipe A you have to
use CPU transcoder A. When have an eDP output you have to use
transcoder EDP and you can attach this CPU transcoder to any of the 3
CPU pipes. When using VGA you need to select a pair of matching CPU
pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
PCH transcoder.
For now we're just creating the cpu_transcoder definitions and setting
cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe. The goal is to
keep the code backwards-compatible since on all cases except when
using eDP we must have pipe == cpu_transcoder.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 18 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4728d30..922ab8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
};
#define pipe_name(p) ((p) + 'A')
+enum transcoder {
+ TRANSCODER_A = 0,
+ TRANSCODER_B,
+ TRANSCODER_C,
+ TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
enum plane {
PLANE_A = 0,
PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c31ee5b..c3fd536 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c2c219b..6bf5ea8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct
drm_crtc *crtc,
return true;
}
+enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ return intel_crtc->cpu_transcoder;
+}
+
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
static void haswell_crtc_off(struct drm_crtc *crtc)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ intel_crtc->cpu_transcoder = intel_crtc->pipe;
intel_ddi_put_crtc_pll(crtc);
}
@@ -5212,6 +5224,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
+ if (is_cpu_edp)
+ intel_crtc->cpu_transcoder = TRANSCODER_EDP;
+ else
+ intel_crtc->cpu_transcoder = pipe;
+
/* We are not sure yet this won't happen. */
WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
INTEL_PCH_TYPE(dev));
@@ -7770,6 +7787,7 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
+ intel_crtc->cpu_transcoder = pipe;
if (IS_MOBILE(dev) && IS_GEN3(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 95cbd67..8f6eee5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -185,6 +185,7 @@ struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
enum plane plane;
+ enum transcoder cpu_transcoder;
u8 lut_r[256], lut_g[256], lut_b[256];
/*
* Whether the crtc and the connected output pipeline is active. Implies
@@ -491,6 +492,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct
drm_device *dev,
struct drm_crtc *crtc);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+extern enum transcoder pip
[Intel-gfx] [PATCH 00/14] Haswell eDP enablement
From: Paulo Zanoni Hi Now that DP is merged, time for eDP :) Most of the patches here exist because on Haswell what we used to call "CPU pipe" was split into "CPU pipe" and "CPU transcoder" (and we still have the "PCH transcoder") and now we have 3 CPU pipes (A, B and C) and 4 CPU transcoders (A, B, C and EDP). Read the description of patch 01 to understand the changes. In addition to the CPU transcoder changes we just have a few patches to add the eDP-specific bits to the Haswell mode set sequence. I'm not reusing some code from intel_dp.c because I really want our mode set sequence to follow the spec. After this series eDP should light up and work. Paulo Zanoni (14): drm/i915: add TRANSCODER_EDP drm/i915: convert PIPE_CLK_SEL to transcoder drm/i915: convert DDI_FUNC_CTL to transcoder drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state drm/i915: convert PIPECONF to use transcoder instead of pipe drm/i915: convert PIPE_MSA_MISC to transcoder drm/i915: convert CPU M/N timings to transcoder drm/i915: convert pipe timing definitions to transcoder drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP drm/i915: select the correct pipe when using TRANSCODER_EDP drm/i915: set the correct eDP aux channel clock divider on DDI drm/i915: set/unset the DDI eDP backlight drm/i915: turn the eDP DDI panel on/off drm/i915: enable DDI eDP drivers/gpu/drm/i915/i915_drv.h | 8 ++ drivers/gpu/drm/i915/i915_irq.c | 11 ++- drivers/gpu/drm/i915/i915_reg.h | 127 +--- drivers/gpu/drm/i915/intel_crt.c | 12 ++- drivers/gpu/drm/i915/intel_ddi.c | 182 -- drivers/gpu/drm/i915/intel_display.c | 187 --- drivers/gpu/drm/i915/intel_dp.c | 29 +++--- drivers/gpu/drm/i915/intel_drv.h | 18 +++- drivers/gpu/drm/i915/intel_sprite.c | 3 +- drivers/gpu/drm/i915/intel_tv.c | 4 +- 10 files changed, 379 insertions(+), 202 deletions(-) -- 1.7.11.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add no-lvds quirk for Supermicro X7SPA-H
Reported-and-tested-by: Francois Tigeot
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55375
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lvds.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 40d72bd..224ae5f 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -778,6 +778,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
},
},
+ {
+ .callback = intel_no_lvds_dmi_callback,
+ .ident = "Supermicro X7SPA-H",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
+ },
+ },
{ } /* terminating entry */
};
--
1.7.10.4
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Re: [Intel-gfx] [PATCH] drm/i915: implement hsw WaDisableVFUnitClockGating
On Thu, Oct 18, 2012 at 02:06:28PM -0300, Paulo Zanoni wrote: > Hi > > 2012/10/17 Daniel Vetter : > > Found while strolling for ilk workarounds since this one is listed > > there, too. I think that's a mistake though, since the w/a isn't > > listed for snb/ivb, and the relevant register doesn't seem to exist on > > ilk. > > > > Signed-off-by: Daniel Vetter > > Tested-by: Paulo Zanoni > > This needs a comment saying that it's just for pre-production > hardware, needs to be removed later. With that: > Reviewed-by: Paulo Zanoni Meh, I've missed that totally. In that case I think I'll drop this patch here. Thanks anyway for review&testing. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
On Thu, Oct 18, 2012 at 02:14:52PM -0300, Paulo Zanoni wrote: > Hi > > 2012/10/17 Daniel Vetter : > > On Tue, Oct 16, 2012 at 02:49:58PM +0300, Jani Nikula wrote: > >> On Mon, 15 Oct 2012, Paulo Zanoni wrote: > >> > From: Paulo Zanoni > >> > > >> > Much simpler and looks more like the M/N code inside intel_display.c. > >> > >> Reviewed-by: Jani Nikula > > > > Merged up to this patch, thanks. > > No. Actually I think we're missing patches 4 and 5. Patch 4 has a R-B, > but 5 doesn't. Yeah, I've made a bit a mess ;-) Should be all merged now, thanks for patches and review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function
So we can write them properly.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6f03b26..39c53ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1130,8 +1130,17 @@ static bool IS_DISPLAYREG(u32 reg)
return false;
switch (reg) {
+ case _3D_CHICKEN3:
+ case IVB_CHICKEN3:
+ case GEN7_COMMON_SLICE_CHICKEN1:
+ case GEN7_L3CNTLREG1:
+ case GEN7_L3_CHICKEN_MODE_REGISTER:
case GEN7_ROW_CHICKEN2:
+ case GEN7_L3SQCREG4:
+ case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
case GEN7_HALF_SLICE_CHICKEN1:
+ case GEN6_MBCTL:
+ case GEN6_UCGCTL2:
return false;
default:
break;
--
1.7.9.5
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[Intel-gfx] [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op
So store into the scratch space of the HWS to make sure the invalidate occurs. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |6 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++ drivers/gpu/drm/i915/intel_ringbuffer.h |1 + 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34067b5..c6f63a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -241,8 +241,10 @@ */ #define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DWMI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB(1<<18) -#define MI_INVALIDATE_BSD(1<<7) +#define MI_FLUSH_DW_STORE_INDEX (1<<21) +#define MI_INVALIDATE_TLB(1<<18) +#define MI_FLUSH_DW_OP_STOREDW (1<<14) +#define MI_INVALIDATE_BSD(1<<7) #define MI_BATCH_BUFFERMI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6c6f95a..e7daa90 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1396,10 +1396,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* +* Bspec vol 1c.5 - video engine command streamer: +* "If ENABLED, all TLBs will be invalidated once the flush +* operation is complete. This bit is only valid when the +* Post-Sync Operation field is a value of 1h or 3h." +*/ if (invalidate & I915_GEM_GPU_DOMAINS) - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << 3); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); @@ -1461,10 +1468,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* +* Bspec vol 1c.3 - blitter engine command streamer: +* "If ENABLED, all TLBs will be invalidated once the flush +* operation is complete. This bit is only valid when the +* Post-Sync Operation field is a value of 1h or 3h." +*/ if (invalidate & I915_GEM_DOMAIN_RENDER) - cmd |= MI_INVALIDATE_TLB; + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | + MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << 3); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3745d1d..d089520 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -183,6 +183,7 @@ intel_read_status_page(struct intel_ring_buffer *ring, * The area from dword 0x20 to 0x3ff is available for driver usage. */ #define I915_GEM_HWS_INDEX 0x20 +#define I915_GEM_HWS_SCRATCH_INDEX 0x28 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ringbuffer.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e7daa90..1e09c62 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -246,7 +246,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, /* * TLB invalidate requires a post-sync write. */ - flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; } ret = intel_ring_begin(ring, 4); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |2 ++ drivers/gpu/drm/i915/intel_pm.c |7 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b07d309..ecb28be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -552,6 +552,8 @@ #define IIR0x020a4 #define IMR0x020a8 #define ISR0x020ac +#define VLV_GUNIT_CLOCK_GATE 0x182060 +#define GCFG_DIS (1<<8) #define VLV_IIR_RW 0x182084 #define VLV_IER0x1820a0 #define VLV_IIR0x1820a4 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 969687f..4c86549 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3691,6 +3691,13 @@ static void valleyview_init_clock_gating(struct drm_device *dev) PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | PLANEA_FLIPDONE_INT_EN); + + /* +* WaDisableVLVClockGating_VBIIssue +* Disable clock gating on th GCFG unit to prevent a delay +* in the reporting of vblank events. +*/ + I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } static void g4x_init_clock_gating(struct drm_device *dev) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915: implement WaForceL3Serialization on VLV and IVB
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Reviewed-by: Ben Widawsky Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 15328a3..969687f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3631,6 +3631,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + /* WaForceL3Serialization */ + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & + ~L3SQ_URB_READ_CAM_MATCH_DISABLE); + /* This is required by WaCatErrorRejectionIssue */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
Workaround for dual port PS dispatch on GT1.
v2: pull in register definition & offset handling
v3: use IVB GT1 macro to get the right regs (Ben)
v4: add for VLV too (Ben)
v5: don't read the reg, it's masked so we'll only enable the one extra bit
(Chris)
v6: use a _GT2 suffix for the second reg (Chris)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |1 +
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/intel_pm.c | 11 +++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 39282a4..6f03b26 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,7 @@ static bool IS_DISPLAYREG(u32 reg)
switch (reg) {
case GEN7_ROW_CHICKEN2:
+ case GEN7_HALF_SLICE_CHICKEN1:
return false;
default:
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ecb28be..34067b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4268,6 +4268,11 @@
#define GEN7_L3LOG_BASE0xB070
#define GEN7_L3LOG_SIZE0x80
+#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
+#define GEN7_MAX_PS_THREAD_DEP (8<<12)
+#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
+
#define GEN7_ROW_CHICKEN2 0xe4f4
#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
#define DOP_CLOCK_GATING_DISABLE (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c86549..0c1b270 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3527,6 +3527,14 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ /* WaDisablePSDDualDispatchEnable */
+ if (IS_IVB_GT1(dev))
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+ else
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
+
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
@@ -3615,6 +3623,9 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+ _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
--
1.7.9.5
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[Intel-gfx] [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV
Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Note this removes the IVB workaround value from VLV and uses the default value, just adding in the L3 cache aging disable bit, since the IVB value is wrong for VLV. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c31ee5b..876ef96 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3449,6 +3449,7 @@ #define GEN7_L3CNTLREG10xB01C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C +#define GEN7_L3AGDIS (1<<19) #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 #define GEN7_WA_L3_CHICKEN_MODE 0x2000 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b3cddf..049c7e2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3613,7 +3613,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ - I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); + I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); /* WaForceL3Serialization */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB
v2: use correct register
v3: remove extra hunks, pull in register definitions & offset check directly
v4: add GT1 vs GT2 distinction for IVB portion (Ben)
References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
Reviewed-by: Ben Widawsky
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |7 +++
drivers/gpu/drm/i915/i915_drv.h |3 +++
drivers/gpu/drm/i915/i915_reg.h |4
drivers/gpu/drm/i915/intel_pm.c | 13 -
4 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e7e647..39282a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1129,6 +1129,13 @@ static bool IS_DISPLAYREG(u32 reg)
if (reg == GEN6_GDRST)
return false;
+ switch (reg) {
+ case GEN7_ROW_CHICKEN2:
+ return false;
+ default:
+ break;
+ }
+
return true;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4728d30..beef67f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,6 +1128,9 @@ struct drm_i915_file_private {
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVB_GT1(dev)((dev)->pci_device == 0x0156 || \
+(dev)->pci_device == 0x0152 || \
+(dev)->pci_device == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_HASWELL(dev)(INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 876ef96..b07d309 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4266,6 +4266,10 @@
#define GEN7_L3LOG_BASE0xB070
#define GEN7_L3LOG_SIZE0x80
+#define GEN7_ROW_CHICKEN2 0xe4f4
+#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
+#define DOP_CLOCK_GATING_DISABLE (1<<0)
+
#define G4X_AUD_VID_DID0x62020
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 049c7e2..15328a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3535,7 +3535,14 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN7_L3CNTLREG1,
GEN7_WA_FOR_GEN7_L3_CONTROL);
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
- GEN7_WA_L3_CHICKEN_MODE);
+ GEN7_WA_L3_CHICKEN_MODE);
+ if (IS_IVB_GT1(dev))
+ I915_WRITE(GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ else
+ I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
/* WaForceL3Serialization */
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
@@ -3620,6 +3627,10 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+ /* WaDisableDopClockGating */
+ I915_WRITE(GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
/* This is required by WaCatErrorRejectionIssue */
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 05/14] drm/i915: add DP support to intel_ddi_mode_set
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > This is the final remaining piece of Haswell DP enablement. After this > patch, just calling intel_dp_init on any port will make DP work. We > still do not do this because we're currently initializing HDMI on all > the ports, so if we replace intel_hdmi_init with intel_dp_init, we > will break HDMI, and we can't call both because they share the same > registers. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/14] drm/i915: implement Haswell DP link train sequence
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Previous patch "drm/i915: add basic Haswell DP link train bits" > implemented the basic structure to set the voltage levels and training > patterns. This patch adds the higher-level bits that are part of the > mode set sequence and hot plug. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
Hi 2012/10/17 Daniel Vetter : > On Tue, Oct 16, 2012 at 02:49:58PM +0300, Jani Nikula wrote: >> On Mon, 15 Oct 2012, Paulo Zanoni wrote: >> > From: Paulo Zanoni >> > >> > Much simpler and looks more like the M/N code inside intel_display.c. >> >> Reviewed-by: Jani Nikula > > Merged up to this patch, thanks. No. Actually I think we're missing patches 4 and 5. Patch 4 has a R-B, but 5 doesn't. After this, we still need 9 (just resent), then 13 and 14. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: implement hsw WaDisableVFUnitClockGating
Hi 2012/10/17 Daniel Vetter : > Found while strolling for ilk workarounds since this one is listed > there, too. I think that's a mistake though, since the w/a isn't > listed for snb/ivb, and the relevant register doesn't seem to exist on > ilk. > > Signed-off-by: Daniel Vetter Tested-by: Paulo Zanoni This needs a comment saying that it's just for pre-production hardware, needs to be removed later. With that: Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_reg.h |1 + > drivers/gpu/drm/i915/intel_pm.c |7 +-- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a4162dd..555a90f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4126,6 +4126,7 @@ > # define GEN6_CSUNIT_CLOCK_GATE_DISABLE(1 << 7) > > #define GEN6_UCGCTL2 0x9404 > +# define GEN7_VFUNIT_CLOCK_GATE_DISABLE(1<<31) > # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) > # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) > # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 72f41aa..48bbcc1 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3507,8 +3507,11 @@ static void haswell_init_clock_gating(struct > drm_device *dev) > > /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. > * This implements the WaDisableRCZUnitClockGating workaround. > -*/ > - I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > +* New w/a on hsw: bit 31 must be set, too. This implements for > +* WaDisableVFUnitClockGating */ > + I915_WRITE(GEN6_UCGCTL2, > + GEN6_RCZUNIT_CLOCK_GATE_DISABLE | > + GEN7_VFUNIT_CLOCK_GATE_DISABLE); > > I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); > > -- > 1.7.10.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function
So we can write them properly.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6f03b26..39c53ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1130,8 +1130,17 @@ static bool IS_DISPLAYREG(u32 reg)
return false;
switch (reg) {
+ case _3D_CHICKEN3:
+ case IVB_CHICKEN3:
+ case GEN7_COMMON_SLICE_CHICKEN1:
+ case GEN7_L3CNTLREG1:
+ case GEN7_L3_CHICKEN_MODE_REGISTER:
case GEN7_ROW_CHICKEN2:
+ case GEN7_L3SQCREG4:
+ case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
case GEN7_HALF_SLICE_CHICKEN1:
+ case GEN6_MBCTL:
+ case GEN6_UCGCTL2:
return false;
default:
break;
--
1.7.9.5
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[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ringbuffer.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e7daa90..1e09c62 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -246,7 +246,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, /* * TLB invalidate requires a post-sync write. */ - flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; } ret = intel_ring_begin(ring, 4); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
Workaround for dual port PS dispatch on GT1.
v2: pull in register definition & offset handling
v3: use IVB GT1 macro to get the right regs (Ben)
v4: add for VLV too (Ben)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |1 +
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/intel_pm.c | 14 ++
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 39282a4..6f03b26 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,7 @@ static bool IS_DISPLAYREG(u32 reg)
switch (reg) {
case GEN7_ROW_CHICKEN2:
+ case GEN7_HALF_SLICE_CHICKEN1:
return false;
default:
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ecb28be..12816bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4268,6 +4268,11 @@
#define GEN7_L3LOG_BASE0xB070
#define GEN7_L3LOG_SIZE0x80
+#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100
+#define GEN7_MAX_PS_THREAD_DEP (8<<12)
+#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
+
#define GEN7_ROW_CHICKEN2 0xe4f4
#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
#define DOP_CLOCK_GATING_DISABLE (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c86549..7864da3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3527,6 +3527,16 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ /* WaDisablePSDDualDispatchEnable */
+ if (IS_IVB_GT1(dev))
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+ I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+ else
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
+ I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
@@ -3615,6 +3625,10 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+ I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+ _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
--
1.7.9.5
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[Intel-gfx] [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op
So store into the scratch space of the HWS to make sure the invalidate occurs. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |6 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++ drivers/gpu/drm/i915/intel_ringbuffer.h |1 + 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 12816bb..9d7e4f5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -241,8 +241,10 @@ */ #define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DWMI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB(1<<18) -#define MI_INVALIDATE_BSD(1<<7) +#define MI_FLUSH_DW_STORE_INDEX (1<<21) +#define MI_INVALIDATE_TLB(1<<18) +#define MI_FLUSH_DW_OP_STOREDW (1<<14) +#define MI_INVALIDATE_BSD(1<<7) #define MI_BATCH_BUFFERMI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6c6f95a..e7daa90 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1396,10 +1396,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* +* Bspec vol 1c.5 - video engine command streamer: +* "If ENABLED, all TLBs will be invalidated once the flush +* operation is complete. This bit is only valid when the +* Post-Sync Operation field is a value of 1h or 3h." +*/ if (invalidate & I915_GEM_GPU_DOMAINS) - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << 3); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); @@ -1461,10 +1468,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* +* Bspec vol 1c.3 - blitter engine command streamer: +* "If ENABLED, all TLBs will be invalidated once the flush +* operation is complete. This bit is only valid when the +* Post-Sync Operation field is a value of 1h or 3h." +*/ if (invalidate & I915_GEM_DOMAIN_RENDER) - cmd |= MI_INVALIDATE_TLB; + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | + MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << 3); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3745d1d..d089520 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -183,6 +183,7 @@ intel_read_status_page(struct intel_ring_buffer *ring, * The area from dword 0x20 to 0x3ff is available for driver usage. */ #define I915_GEM_HWS_INDEX 0x20 +#define I915_GEM_HWS_SCRATCH_INDEX 0x28 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |2 ++ drivers/gpu/drm/i915/intel_pm.c |7 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b07d309..ecb28be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -552,6 +552,8 @@ #define IIR0x020a4 #define IMR0x020a8 #define ISR0x020ac +#define VLV_GUNIT_CLOCK_GATE 0x182060 +#define GCFG_DIS (1<<8) #define VLV_IIR_RW 0x182084 #define VLV_IER0x1820a0 #define VLV_IIR0x1820a4 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 969687f..4c86549 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3691,6 +3691,13 @@ static void valleyview_init_clock_gating(struct drm_device *dev) PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | PLANEA_FLIPDONE_INT_EN); + + /* +* WaDisableVLVClockGating_VBIIssue +* Disable clock gating on th GCFG unit to prevent a delay +* in the reporting of vblank events. +*/ + I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } static void g4x_init_clock_gating(struct drm_device *dev) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915: implement WaForceL3Serialization on VLV and IVB
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Reviewed-by: Ben Widawsky Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 15328a3..969687f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3631,6 +3631,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + /* WaForceL3Serialization */ + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & + ~L3SQ_URB_READ_CAM_MATCH_DISABLE); + /* This is required by WaCatErrorRejectionIssue */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB
v2: use correct register
v3: remove extra hunks, pull in register definitions & offset check directly
v4: add GT1 vs GT2 distinction for IVB portion (Ben)
References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
Reviewed-by: Ben Widawsky
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |7 +++
drivers/gpu/drm/i915/i915_drv.h |3 +++
drivers/gpu/drm/i915/i915_reg.h |4
drivers/gpu/drm/i915/intel_pm.c | 13 -
4 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e7e647..39282a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1129,6 +1129,13 @@ static bool IS_DISPLAYREG(u32 reg)
if (reg == GEN6_GDRST)
return false;
+ switch (reg) {
+ case GEN7_ROW_CHICKEN2:
+ return false;
+ default:
+ break;
+ }
+
return true;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4728d30..beef67f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,6 +1128,9 @@ struct drm_i915_file_private {
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVB_GT1(dev)((dev)->pci_device == 0x0156 || \
+(dev)->pci_device == 0x0152 || \
+(dev)->pci_device == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_HASWELL(dev)(INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 876ef96..b07d309 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4266,6 +4266,10 @@
#define GEN7_L3LOG_BASE0xB070
#define GEN7_L3LOG_SIZE0x80
+#define GEN7_ROW_CHICKEN2 0xe4f4
+#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
+#define DOP_CLOCK_GATING_DISABLE (1<<0)
+
#define G4X_AUD_VID_DID0x62020
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 049c7e2..15328a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3535,7 +3535,14 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN7_L3CNTLREG1,
GEN7_WA_FOR_GEN7_L3_CONTROL);
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
- GEN7_WA_L3_CHICKEN_MODE);
+ GEN7_WA_L3_CHICKEN_MODE);
+ if (IS_IVB_GT1(dev))
+ I915_WRITE(GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ else
+ I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
/* WaForceL3Serialization */
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
@@ -3620,6 +3627,10 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+ /* WaDisableDopClockGating */
+ I915_WRITE(GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
/* This is required by WaCatErrorRejectionIssue */
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
--
1.7.9.5
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[Intel-gfx] [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV
Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c31ee5b..876ef96 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3449,6 +3449,7 @@ #define GEN7_L3CNTLREG10xB01C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C +#define GEN7_L3AGDIS (1<<19) #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 #define GEN7_WA_L3_CHICKEN_MODE 0x2000 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b3cddf..049c7e2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3613,7 +3613,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ - I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); + I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); /* WaForceL3Serialization */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/83] drm/i915: fix Haswell DP M/N registers
From: Paulo Zanoni
We have to write the correct values inside intel_dp_set_m_n and then
prevent these values from being overwritten later.
V2: Unconfuse double negation.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
drivers/gpu/drm/i915/intel_dp.c | 7 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f48986b9..ba40aa7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
- ironlake_set_m_n(crtc, mode, adjusted_mode);
+ if (!is_dp || is_cpu_edp)
+ ironlake_set_m_n(crtc, mode, adjusted_mode);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
if (is_cpu_edp)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52b5453..22702df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -793,7 +793,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
drm_display_mode *mode,
intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
mode->clock, adjusted_mode->clock, &m_n);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ } else if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
--
1.7.11.4
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Don't program DSPCLK_GATE_D twice on IVB and VLV
Hi
2012/10/17 Damien Lespiau :
> From: Damien Lespiau
>
> We were programming register 0x42020 twice on those platforms. Once
> should be enough.
>
> Signed-off-by: Damien Lespiau
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c |6 --
> 1 files changed, 0 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index be42b2c..724ca4b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3506,11 +3506,8 @@ static void ivybridge_init_clock_gating(struct
> drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> - uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> uint32_t snpcr;
>
> - I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
> @@ -3588,9 +3585,6 @@ static void valleyview_init_clock_gating(struct
> drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> - uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> - I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> --
> 1.7.7.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Program DSPCLK_GATE_D only once on Ironlake
2012/10/17 Damien Lespiau :
> From: Damien Lespiau
>
> With the consolidated registers, it appears that we're setting the same
> bis several times. Let's just collect the bit we want to set and program
s/bis/bits/
> it once.
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_pm.c | 15 ---
> 1 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 76e10c0..be42b2c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3316,8 +3316,6 @@ static void ironlake_init_clock_gating(struct
> drm_device *dev)
> I915_WRITE(PCH_3DCGDIS1,
>VFMUNIT_CLOCK_GATE_DISABLE);
>
> - I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> /*
> * According to the spec the following bits should be set in
> * order to enable memory self-refresh
> @@ -3328,9 +3326,7 @@ static void ironlake_init_clock_gating(struct
> drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
>(I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> - I915_WRITE(ILK_DSPCLK_GATE_D,
> - (I915_READ(ILK_DSPCLK_GATE_D) |
> - ILK_DPARBUNIT_CLOCK_GATE_DISABLE));
> + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_DISABLE;
We are still doing "dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_DISABLE;"
twice: here and also at the beginning of the function.
If you look at the function after this patch it looks like this:
ironlake_init_clock_gating {
/* Required for FBC */
dspclk_gate |= XXX;
/* Required for CxSR */
dspclk_gate |= YYY;
/* According to the spec, required by CxSR, big comment */
dspclk_gate |= YYY;
/* Based on document, required by FBC, big comment */
(no "dpslclk_gate |= XXX" setting here since it is already above)
}
I was told that CxSR is the same as memory self-refresh, so I guess we
could clean up the function by de-duplicating even the comments since
they're talking about the same things. My suggestion would be to
eliminate the first comments/code, leaving just the multi-line
comments and setting dspclk_gate after each of these (also taking care
to set the FBC bits not only for mobile).
> I915_WRITE(DISP_ARB_CTL,
>(I915_READ(DISP_ARB_CTL) |
> DISP_FBC_WM_DIS));
> @@ -3343,7 +3339,7 @@ static void ironlake_init_clock_gating(struct
> drm_device *dev)
> * should be set unconditionally in order to enable FBC.
> * The bit 22 of 0x42000
> * The bit 22 of 0x42004
> -* The bit 7,8,9 of 0x42020.
> +* The bit 7,8,9 of 0x42020 (dspclk_gate is set above)
> */
> if (IS_IRONLAKE_M(dev)) {
> I915_WRITE(ILK_DISPLAY_CHICKEN1,
> @@ -3352,13 +3348,10 @@ static void ironlake_init_clock_gating(struct
> drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
>I915_READ(ILK_DISPLAY_CHICKEN2) |
>ILK_DPARB_GATE);
> - I915_WRITE(ILK_DSPCLK_GATE_D,
> - I915_READ(ILK_DSPCLK_GATE_D) |
> - ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_DISABLE);
> }
>
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> +
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
>I915_READ(ILK_DISPLAY_CHICKEN2) |
>ILK_ELPIN_409_SELECT);
> --
> 1.7.7.5
>
> ___
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___
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Re: [Intel-gfx] [PATCH 12/14] drm/i915: add DP support to intel_enable_ddi
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > We should only write the DDI_BUF_CTL at this point for HDMI/DVI. For > DP we need to do this earlier, and the values written to the register > are also different. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATE
Hi
2012/10/17 Damien Lespiau :
> From: Damien Lespiau
>
> Register 0x42020 was defined twice under the names PCH_DSPCLK_GATE_D and
> ILK_DSPCLK_GATE. This patch consolidate the 2 sets of defines in one.
>
> The transforms done are:
>
> PCH_DSPCLK_GATE_D-> ILK_DSPCLK_GATE_D
> ILK_DSPCLK_GATE -> ILK_DSPCLK_GATE_D
>
> DPARBUNIT_CLOCK_GATE_DISABLE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
> ILK_DPARB_CLK_GATE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
>
> DPFDUNIT_CLOCK_GATE_DISABLE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
> ILK_DPFD_CLK_GATE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
> ILK_CLK_FBC -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
>
> DPFCRUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
> ILK_DPFC_DIS1-> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
>
> DPFCUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
> ILK_DPFC_DIS2 -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
>
> We have a VHRUNIT_CLOCK_GATE_DISABLE define for the pre-ILK DSPCLK_GATE_D.
> Even if the same bit is used in ILK_DSPCLK_GATE_D, other bits in the
> register change, so I went with re-defining it, well more precisely rename
> IVB_VRHUNIT_CLK_GATE, which is not specific to IVB+. So:
>
> IVB_VRHUNIT_CLK_GATE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE
> VHRUNIT_CLOCK_GATE_DISABLE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE (ILK+ code)
>
> This commit is only a renaming commit, further commits will clean up the
> logic.
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 +---
> drivers/gpu/drm/i915/intel_pm.c | 52 +++---
> 2 files changed, 33 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8200c31..ac09d66 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3245,12 +3245,6 @@
> #define DISPLAY_PORT_PLL_BIOS_1 0x46010
> #define DISPLAY_PORT_PLL_BIOS_2 0x46014
>
> -#define PCH_DSPCLK_GATE_D 0x42020
> -# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> -# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
> -# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
> -# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
> -
> #define PCH_3DCGDIS0 0x46020
> # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
> # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
> @@ -3422,15 +3416,13 @@
> #define ILK_HDCP_DISABLE (1<<25)
> #define ILK_eDP_A_DISABLE (1<<24)
> #define ILK_DESKTOP (1<<23)
> -#define ILK_DSPCLK_GATE0x42020
> -#define IVB_VRHUNIT_CLK_GATE (1<<28)
> -#define ILK_DPARB_CLK_GATE(1<<5)
> -#define ILK_DPFD_CLK_GATE (1<<7)
> -
> -/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
> -#define ILK_CLK_FBC (1<<7)
> -#define ILK_DPFC_DIS1(1<<8)
> -#define ILK_DPFC_DIS2(1<<9)
> +
> +#define ILK_DSPCLK_GATE_D 0x42020
> +#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
> +#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> +#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
> +#define ILK_DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
> +#define ILK_DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Setting bits 7 and 5 to "1" actually means "enable", even though the
bit name is "dxxxunit clock gating disable". So my suggestion would
be:
+#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
+#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
The other bits are fine, since setting them to 1 actually means "disable".
With that fixed:
Reviewed-by: Paulo Zanoni
>
> #define IVB_CHICKEN3 0x4200c
> # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 07da990..76e10c0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3301,14 +3301,14 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> static void ironlake_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> + uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> /* Required for FBC */
> - dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
> - DPFCRUNIT_CLOCK_GATE_DISABLE |
> - DPFDUNIT_CLOCK_GATE_DISABLE;
> + dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_DISABLE;
> /* Required for CxSR */
> - dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
> + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_DISABLE;
>
> I915_WRITE(PCH_3DCGDIS0,
>MARIUNIT_CLOCK_GATE_DISABLE |
> @@ -3316,7 +3316,7 @@ static void
Re: [Intel-gfx] [PATCH 11/14] drm/i915: add DP support to intel_ddi_get_hw_state
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/10] extract dp helper functions
On Thu, Oct 18, 2012 at 3:48 PM, Alex Deucher wrote: > On Thu, Oct 18, 2012 at 4:15 AM, Daniel Vetter wrote: >> Hi all, >> >> I've frustrated myself the last few days yelling at our link training code. >> Comparing the i915 code to radeon and nouveau I've noticed the lack of a nice >> set of dp helper functions. So I've started to extract a few. >> >> There's lots more that we can do I think (link configuration selection, the >> i2c >> over aux retry stuff which diverges already between i915 and radeon, maybe >> more >> higher level parts of the training sequence). But there the drivers diverge >> quite a bit (e.g. the link configuration is driver by different things in >> each >> driver: coded link bw from the dp spec, link clock or required bw vs >> avialable >> bw), so that's more work and probably best done when reworking these >> functions >> for other reasons. > > In theory we could provide a helper function to do the entire link > training in common code. We'd just need a a couple of function > callbacks: > > dp_aux_read() > dp_aux_write() > dp_link_train_init() > dp_set_src_training_pattern() > dp_link_train_fini() > > Obviously some drivers may want to do their own thing, so it would > just be a helper. Still for DP 1.2, it would be nice to have the > option of sharing more code. Yeah, that's one of the ideas. Although I think we should start with a few smaller things like e.g. the bandwidth stuff or the dp aux i2c logic. Those need a subset of the above interfaces only and are less intrusive. And since the link training in i915 seems to be still rather broken and it in decent flux due to hsw enabling in general, I want to wait and see a bit first until we have the corner cases nailed. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/14] drm/i915: add DP support to intel_ddi_get_encoder_port
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > The old rule that the AUX registers are just an offset (+4 and +10) > from output_reg is not true anymore, since output_reg in on the CPU > and some AUX regs are on the PCH. Right, dp.output_reg is now DDI_BUF_CTL(port), note that _DATA is still _AUX_CH_CTL + 4, so could keep that logic and just have switch for DP_AUX_CH_CTL. > +#define PCH_DPB_AUX_CH_CTL 0xe4110 > +#define PCH_DPC_AUX_CH_CTL 0xe4210 > +#define PCH_DPD_AUX_CH_CTL 0xe4310 > + > +#define PCH_DPB_AUX_CH_DATA0xe4114 > +#define PCH_DPC_AUX_CH_DATA0xe4214 > +#define PCH_DPD_AUX_CH_DATA0xe4314 Those defines are already there AFAICS: http://cgit.freedesktop.org/~danvet/drm-intel/tree/drivers/gpu/drm/i915/i915_reg.h#n4017 -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/10] extract dp helper functions
On Thu, Oct 18, 2012 at 4:15 AM, Daniel Vetter wrote: > Hi all, > > I've frustrated myself the last few days yelling at our link training code. > Comparing the i915 code to radeon and nouveau I've noticed the lack of a nice > set of dp helper functions. So I've started to extract a few. > > There's lots more that we can do I think (link configuration selection, the > i2c > over aux retry stuff which diverges already between i915 and radeon, maybe > more > higher level parts of the training sequence). But there the drivers diverge > quite a bit (e.g. the link configuration is driver by different things in each > driver: coded link bw from the dp spec, link clock or required bw vs avialable > bw), so that's more work and probably best done when reworking these functions > for other reasons. In theory we could provide a helper function to do the entire link training in common code. We'd just need a a couple of function callbacks: dp_aux_read() dp_aux_write() dp_link_train_init() dp_set_src_training_pattern() dp_link_train_fini() Obviously some drivers may want to do their own thing, so it would just be a helper. Still for DP 1.2, it would be nice to have the option of sharing more code. > > I've also tried to put the new helpers a bit to use in nouveau, but due to > lack > of hw that part is untested. > > Comments and testing highly welcome. > > Yours, Daniel > > Daniel Vetter (10): > drm: rename drm_dp_i2c_helper.c to drm_dp_helper.c > drm: dp helper: extract drm_dp_channel_eq_ok > drm: dp helper: extract drm_dp_clock_recovery_ok > drm/nouveau: use the cr_ok/chanel_eq_ok helpers > drm: extract helpers to compute new training values from sink request > drm/nouveau: use dp link train request helper > drm: extract dp link train delay functions from radeon > drm/i915: use the new dp train delay helpers > drm: extract dp link bw helpers > drm: extract drm_dp_max_lane_count helper > > drivers/gpu/drm/Makefile | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 328 > +++ > drivers/gpu/drm/drm_dp_i2c_helper.c | 208 -- > drivers/gpu/drm/i915/intel_dp.c | 98 ++- > drivers/gpu/drm/nouveau/nouveau_dp.c | 35 +--- > drivers/gpu/drm/radeon/atombios_dp.c | 147 ++-- > drivers/gpu/drm/radeon/radeon_mode.h | 2 +- > include/drm/drm_dp_helper.h | 31 > 8 files changed, 400 insertions(+), 451 deletions(-) > create mode 100644 drivers/gpu/drm/drm_dp_helper.c > delete mode 100644 drivers/gpu/drm/drm_dp_i2c_helper.c > > -- > 1.7.11.4 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: extract dp link train delay functions from radeon
This requires a few changes since that dpcd value is above the
range currently cached by radeon. I've check the dp specs, and
above 0xf there's a big gap and nothing that looks like we should
cache it while a given device is plugged in. It's also the same value
that i915.ko uses.
Hence extend the various dpcd arrays in the radeon driver, use
proper symbolic constants where applicable (one place overallocated
the dpcd array to 25 bytes). Then also drop the rd_interval cache -
radeon_dp_link_train_init re-reads the dpcd block, so the values we'll
consume in train_cr and train_ce will always be fresh.
To avoid needless diff-churn, #define the old size of dpcd as the new
one and keep it around.
v2: Alex Deucher noticed one place where I've forgotten to replace 8
with DP_RECEIVER_CAP_SIZE.
Reviewed-by: Alex Deucher
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_helper.c | 15 +++
drivers/gpu/drm/i915/intel_dp.c | 1 -
drivers/gpu/drm/radeon/atombios_dp.c | 27 ++-
drivers/gpu/drm/radeon/radeon_mode.h | 2 +-
include/drm/drm_dp_helper.h | 5 +
5 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index d1a196f..e43ddde 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -283,3 +283,18 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8
link_status[DP_LINK_STATUS_SIZE],
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+ if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ udelay(100);
+ else
+ mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+}
+EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
+
+void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+ if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ udelay(400);
+ else
+ mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+}
+EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4cd957a..aa1a28c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -37,7 +37,6 @@
#include "i915_drm.h"
#include "i915_drv.h"
-#define DP_RECEIVER_CAP_SIZE 0xf
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
/**
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 5479832..1e9e490 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -34,7 +34,7 @@
/* move these to drm_dp_helper.c/h */
#define DP_LINK_CONFIGURATION_SIZE 9
-#define DP_DPCD_SIZE 8
+#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
static char *voltage_names[] = {
"0.4V", "0.6V", "0.8V", "1.2V"
@@ -478,14 +478,15 @@ static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector)
bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
{
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
- u8 msg[25];
+ u8 msg[DP_DPCD_SIZE];
int ret, i;
- ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8,
0);
+ ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
+ DP_DPCD_SIZE, 0);
if (ret > 0) {
- memcpy(dig_connector->dpcd, msg, 8);
+ memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
DRM_DEBUG_KMS("DPCD: ");
- for (i = 0; i < 8; i++)
+ for (i = 0; i < DP_DPCD_SIZE; i++)
DRM_DEBUG_KMS("%02x ", msg[i]);
DRM_DEBUG_KMS("\n");
@@ -604,9 +605,8 @@ struct radeon_dp_link_train_info {
int enc_id;
int dp_clock;
int dp_lane_count;
- int rd_interval;
bool tp3_supported;
- u8 dpcd[8];
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 train_set[4];
u8 link_status[DP_LINK_STATUS_SIZE];
u8 tries;
@@ -748,10 +748,7 @@ static int radeon_dp_link_train_cr(struct
radeon_dp_link_train_info *dp_info)
dp_info->tries = 0;
voltage = 0xff;
while (1) {
- if (dp_info->rd_interval == 0)
- udelay(100);
- else
- mdelay(dp_info->rd_interval * 4);
+ drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
if (!radeon_dp_get_link_status(dp_info->radeon_connector,
dp_info->link_status)) {
DRM_ERROR("displayport link status failed\n");
@@ -813,10 +810,7 @@ static int radeon_dp_link_train_ce(struct
radeon_dp_link_train_info *dp_info)
dp_info->tries = 0;
channel_eq = false;
while (1) {
- if (dp_info->rd_interval == 0)
- udelay(400);
-
Re: [Intel-gfx] [PATCH 00/10] extract dp helper functions
On Thu, Oct 18, 2012 at 4:15 AM, Daniel Vetter wrote: > Hi all, > > I've frustrated myself the last few days yelling at our link training code. > Comparing the i915 code to radeon and nouveau I've noticed the lack of a nice > set of dp helper functions. So I've started to extract a few. > > There's lots more that we can do I think (link configuration selection, the > i2c > over aux retry stuff which diverges already between i915 and radeon, maybe > more > higher level parts of the training sequence). But there the drivers diverge > quite a bit (e.g. the link configuration is driver by different things in each > driver: coded link bw from the dp spec, link clock or required bw vs avialable > bw), so that's more work and probably best done when reworking these functions > for other reasons. > > I've also tried to put the new helpers a bit to use in nouveau, but due to > lack > of hw that part is untested. > > Comments and testing highly welcome. Looks good to me. Other than the minor change required in patch7, this series is: Reviewed-by: Alex Deucher > > Yours, Daniel > > Daniel Vetter (10): > drm: rename drm_dp_i2c_helper.c to drm_dp_helper.c > drm: dp helper: extract drm_dp_channel_eq_ok > drm: dp helper: extract drm_dp_clock_recovery_ok > drm/nouveau: use the cr_ok/chanel_eq_ok helpers > drm: extract helpers to compute new training values from sink request > drm/nouveau: use dp link train request helper > drm: extract dp link train delay functions from radeon > drm/i915: use the new dp train delay helpers > drm: extract dp link bw helpers > drm: extract drm_dp_max_lane_count helper > > drivers/gpu/drm/Makefile | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 328 > +++ > drivers/gpu/drm/drm_dp_i2c_helper.c | 208 -- > drivers/gpu/drm/i915/intel_dp.c | 98 ++- > drivers/gpu/drm/nouveau/nouveau_dp.c | 35 +--- > drivers/gpu/drm/radeon/atombios_dp.c | 147 ++-- > drivers/gpu/drm/radeon/radeon_mode.h | 2 +- > include/drm/drm_dp_helper.h | 31 > 8 files changed, 400 insertions(+), 451 deletions(-) > create mode 100644 drivers/gpu/drm/drm_dp_helper.c > delete mode 100644 drivers/gpu/drm/drm_dp_i2c_helper.c > > -- > 1.7.11.4 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/10] drm: extract dp link train delay functions from radeon
On Thu, Oct 18, 2012 at 4:15 AM, Daniel Vetter wrote:
> This requires a few changes since that dpcd value is above the
> range currently cached by radeon. I've check the dp specs, and
> above 0xf there's a big gap and nothing that looks like we should
> cache it while a given device is plugged in. It's also the same value
> that i915.ko uses.
>
> Hence extend the various dpcd arrays in the radeon driver, use
> proper symbolic constants where applicable (one place overallocated
> the dpcd array to 25 bytes). Then also drop the rd_interval cache -
> radeon_dp_link_train_init re-reads the dpcd block, so the values we'll
> consume in train_cr and train_ce will always be fresh.
>
> To avoid needless diff-churn, #define the old size of dpcd as the new
> one and keep it around.
Looks good to me. Just one minor fix below.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_dp_helper.c | 15 +++
> drivers/gpu/drm/i915/intel_dp.c | 1 -
> drivers/gpu/drm/radeon/atombios_dp.c | 25 +
> drivers/gpu/drm/radeon/radeon_mode.h | 2 +-
> include/drm/drm_dp_helper.h | 5 +
> 5 files changed, 30 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index d1a196f..e43ddde 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -283,3 +283,18 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8
> link_status[DP_LINK_STATUS_SIZE],
> }
> EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>
> +void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> + if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> + udelay(100);
> + else
> + mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> +}
> +EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
> +
> +void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> + if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> + udelay(400);
> + else
> + mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> +}
> +EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4cd957a..aa1a28c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -37,7 +37,6 @@
> #include "i915_drm.h"
> #include "i915_drv.h"
>
> -#define DP_RECEIVER_CAP_SIZE 0xf
> #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
>
> /**
> diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
> b/drivers/gpu/drm/radeon/atombios_dp.c
> index 5479832..4551ea5 100644
> --- a/drivers/gpu/drm/radeon/atombios_dp.c
> +++ b/drivers/gpu/drm/radeon/atombios_dp.c
> @@ -34,7 +34,7 @@
>
> /* move these to drm_dp_helper.c/h */
> #define DP_LINK_CONFIGURATION_SIZE 9
> -#define DP_DPCD_SIZE 8
> +#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
>
> static char *voltage_names[] = {
> "0.4V", "0.6V", "0.8V", "1.2V"
> @@ -478,14 +478,15 @@ static void radeon_dp_probe_oui(struct radeon_connector
> *radeon_connector)
> bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
> {
> struct radeon_connector_atom_dig *dig_connector =
> radeon_connector->con_priv;
> - u8 msg[25];
> + u8 msg[DP_DPCD_SIZE];
> int ret, i;
>
> - ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
> 8, 0);
> + ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
> + DP_DPCD_SIZE, 0);
> if (ret > 0) {
> - memcpy(dig_connector->dpcd, msg, 8);
> + memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
> DRM_DEBUG_KMS("DPCD: ");
> - for (i = 0; i < 8; i++)
> + for (i = 0; i < DP_DPCD_SIZE; i++)
> DRM_DEBUG_KMS("%02x ", msg[i]);
> DRM_DEBUG_KMS("\n");
>
> @@ -604,9 +605,8 @@ struct radeon_dp_link_train_info {
> int enc_id;
> int dp_clock;
> int dp_lane_count;
> - int rd_interval;
> bool tp3_supported;
> - u8 dpcd[8];
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> u8 train_set[4];
> u8 link_status[DP_LINK_STATUS_SIZE];
> u8 tries;
> @@ -748,10 +748,7 @@ static int radeon_dp_link_train_cr(struct
> radeon_dp_link_train_info *dp_info)
> dp_info->tries = 0;
> voltage = 0xff;
> while (1) {
> - if (dp_info->rd_interval == 0)
> - udelay(100);
> - else
> - mdelay(dp_info->rd_interval * 4);
> + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
>
> if (!radeon_dp_get_link_status(dp_info->radeon_connector,
> dp_info->link_status)) {
> DRM_ERROR("displayport link status failed\n");
> @@ -813,10 +810,7 @@ static int radeon_dp_link_train_ce(struct
> radeon
[Intel-gfx] [PATCH] drm/i915: unconditionally use mt forcewake on hsw/ivb
Single-threaded forcewake was only used on some early pre-production
ivybridge machines, all the latest ones should use mt forcewake. And
we already assume this in other places of the code (e.g. DERRMR
support in the ddx, or the latest intel_gt_reset patch to reset any
lingering forcewake references left behind by the bios), so don't
bother here, too.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_pm.c | 31 ---
1 file changed, 4 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b3cddf..568c98d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4146,35 +4146,12 @@ void intel_gt_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev)) {
dev_priv->gt.force_wake_get = vlv_force_wake_get;
dev_priv->gt.force_wake_put = vlv_force_wake_put;
- } else if (INTEL_INFO(dev)->gen >= 6) {
+ } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+ dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
+ dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
+ } else if (IS_GEN6(dev)) {
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
-
- /* IVB configs may use multi-threaded forcewake */
- if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
- u32 ecobus;
-
- /* A small trick here - if the bios hasn't configured
-* MT forcewake, and if the device is in RC6, then
-* force_wake_mt_get will not wake the device and the
-* ECOBUS read will return zero. Which will be
-* (correctly) interpreted by the test below as MT
-* forcewake being disabled.
-*/
- mutex_lock(&dev->struct_mutex);
- __gen6_gt_force_wake_mt_get(dev_priv);
- ecobus = I915_READ_NOTRACE(ECOBUS);
- __gen6_gt_force_wake_mt_put(dev_priv);
- mutex_unlock(&dev->struct_mutex);
-
- if (ecobus & FORCEWAKE_MT_ENABLE) {
- DRM_DEBUG_KMS("Using MT version of
forcewake\n");
- dev_priv->gt.force_wake_get =
- __gen6_gt_force_wake_mt_get;
- dev_priv->gt.force_wake_put =
- __gen6_gt_force_wake_mt_put;
- }
- }
}
}
--
1.7.10.4
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: don't save/restor ADPA for kms
On Wed, Oct 17, 2012 at 06:49:00PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2012/10/11 Daniel Vetter :
> > We now no longer rely on this.
> >
> > This is step 1 on a long journey to rid us of the save/restore
> > madness, which tends to lightly paper over many issues, and cause
> > tons of bad things itself ...
> >
> > Signed-off-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/i915/i915_suspend.c | 26 +-
> > 1 file changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_suspend.c
> > b/drivers/gpu/drm/i915/i915_suspend.c
> > index 4776ccf..6e398a8 100644
> > --- a/drivers/gpu/drm/i915/i915_suspend.c
> > +++ b/drivers/gpu/drm/i915/i915_suspend.c
> > @@ -395,6 +395,13 @@ static void i915_save_modeset_reg(struct drm_device
> > *dev)
> > break;
> > }
> >
> > + /* CRT state */
> > + if (HAS_PCH_SPLIT(dev)) {
> > + dev_priv->saveADPA = I915_READ(PCH_ADPA);
> > + } else {
> > + dev_priv->saveADPA = I915_READ(ADPA);
> > + }
> > +
>
> My OCD is telling me to ask you to remove '}' and '{' here (yes, I
> know, they're here because of copy/paste).
OCD is satisfied, patches merged, thanks for the review.
-Daniel
--
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[Intel-gfx] [PATCH] drm/i915: WaInsertNoopAfterBatchEndCommand
Comment says that this applies to earlier gens, too. Since two more
MI_NOOP's can't hurt that much, I've figured I'll apply this w/a down
to gen2.
v2: Correct the ringbuffer dword count for gen3, spotted by Chris
Wilson.
v3: Fixup the comments.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 984a0c5..90db51d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -969,7 +969,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length)
{
int ret;
- ret = intel_ring_begin(ring, 2);
+ ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
@@ -978,6 +978,10 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length)
MI_BATCH_GTT |
MI_BATCH_NON_SECURE_I965);
intel_ring_emit(ring, offset);
+ /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after
+* the batchbuffer start command. */
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
@@ -996,7 +1000,10 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
intel_ring_emit(ring, MI_BATCH_BUFFER);
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
intel_ring_emit(ring, offset + len - 8);
- intel_ring_emit(ring, 0);
+ /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after
+* the batchbuffer start command. Unclear whether really required on
+* gen2, but better safe than sorry. */
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
@@ -1008,12 +1015,17 @@ i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
{
int ret;
- ret = intel_ring_begin(ring, 2);
+ ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
+ /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after
+* the batchbuffer start command. Unclear whether really required on
+* gen3, but better safe than sorry. */
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
--
1.7.10.4
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[Intel-gfx] [PATCH] drm/i915: implement WaIssueDummyWriteToWakeupFromRC6
Or at least our best understanding of it.
v2: Fixup commit message and put the wa name into the comment block.
And actually update the commit, too.
Reviewed-by: Chris Wilson
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7837e5..fb6b633 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,9 +1131,20 @@ static bool IS_DISPLAYREG(u32 reg)
return true;
}
+static void
+ilk_dummy_write(struct drm_i915_private *dev_priv)
+{
+ /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
+* chip from rc6 before touching it for real. MI_MODE is masked, hence
+* harmless to write 0 into. */
+ I915_WRITE_NOTRACE(MI_MODE, 0);
+}
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
unsigned long irqflags; \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
@@ -1165,6 +1176,8 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32
reg, u##x val) { \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
write##y(val, dev_priv->regs + reg + 0x18); \
} else {\
--
1.7.10.4
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[Intel-gfx] [PATCH] drm/i915: implement WaIssueDummyWriteToWakeupFromRC6
Or at least our best understanding of it.
Reviewed-by: Chris Wilson
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7837e5..c3f4f04 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,9 +1131,20 @@ static bool IS_DISPLAYREG(u32 reg)
return true;
}
+static void
+ilk_dummy_write(struct drm_i915_private *dev_priv)
+{
+ /* Ilk w/a: Issue a dummy write to wake up the chip from rc6 before
+* touching it for real. MI_MODE is masked, hence harmless to write 0
+* into. */
+ I915_WRITE_NOTRACE(MI_MODE, 0);
+}
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
unsigned long irqflags; \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
@@ -1165,6 +1176,8 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32
reg, u##x val) { \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
write##y(val, dev_priv->regs + reg + 0x18); \
} else {\
--
1.7.10.4
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: implement WaDisableSpriteDestColorKey
On Thu, 18 Oct 2012 11:49:53 +0200, Daniel Vetter wrote: > Unfortunately this requires a bit of book-keeping to return the > right values for get_colorkey and to set things up correctly > when re-enabling the plane. Needs to worry about per-pipe values and ilk_get_colorkey(). Maybe the code would be simpler if we unconditionally shadowed DVSCNTR[I915_NUM_PIPES]. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6
On Thu, Oct 18, 2012 at 10:49 AM, Daniel Vetter wrote:
> +static void
> +ilk_dummy_write(struct drm_i915_private *dev_priv)
> +{
> + /* Ilk w/a: Issue a dummy write to wake up the chip from rc6 before
> +* touching it for real. MI_MODE is masked, hence harmless to write 0
> +* into. */
I'd document the wa implemented here.
The summary line is missing an 'e' in Wake, it makes it harder to look for it.
--
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: WaInsertNoopAfterBatchEndCommand
On Thu, 18 Oct 2012 11:49:52 +0200, Daniel Vetter wrote: > Comment says that this applies to earlier gens, too. Since two more > MI_NOOP's can't hurt that much, I've figured I'll apply this w/a down > to gen2. > > v2: Correct the ringbuffer dword count for gen3, spotted by Chris > Wilson. > > Signed-off-by: Daniel Vetter I'm just not sold on this one, surely we would have spotted a need before now? 12 extra cycles after every batch! :-p Can you please fix up the cut'n'paste comments to not refer to generations that never call the function? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush
On Thu, 18 Oct 2012 11:49:51 +0200, Daniel Vetter wrote: > Comment says for eaglelake/cantiga, but it's listed in the ilk table, > too. So apply it to both. > > Signed-off-by: Daniel Vetter Looks harmless due to the massive number of other p/c errata and that pipelined render cache flushes have never been relied upon. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6
On Thu, Oct 18, 2012 at 1:17 PM, Chris Wilson wrote:
> On Thu, 18 Oct 2012 11:49:50 +0200, Daniel Vetter
> wrote:
>> #define __i915_read(x, y) \
>> u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>> u##x val = 0; \
>> + if (IS_GEN5(dev_priv->dev)) \
>> + ilk_dummy_write(dev_priv); \
>
> IS_GEN5(dev_priv->dev) just makes me want to puke. At some point we must
> go through and add an __INTEL_INFO(dev_priv) and so
> #define __IS_GEN5(dev_priv__) ((dev_priv__)->info->->gen == 5)
> #define IS_GEN5(dev) __IS_GEN5(to_drm_i915_private(dev))
We could also teach the drm setup and teardown code manners and embed
struct drm_device into our own device struct and call it a day. Would
kill all that pointless circular pointer chasing. Been on my todo
since ages, will probably stay there for a while ...
-Daniel
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6
On Thu, 18 Oct 2012 11:49:50 +0200, Daniel Vetter
wrote:
> #define __i915_read(x, y) \
> u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
> u##x val = 0; \
> + if (IS_GEN5(dev_priv->dev)) \
> + ilk_dummy_write(dev_priv); \
IS_GEN5(dev_priv->dev) just makes me want to puke. At some point we must
go through and add an __INTEL_INFO(dev_priv) and so
#define __IS_GEN5(dev_priv__) ((dev_priv__)->info->->gen == 5)
#define IS_GEN5(dev) __IS_GEN5(to_drm_i915_private(dev))
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6
On Thu, 18 Oct 2012 11:49:50 +0200, Daniel Vetter wrote: > Or at least our best understanding of it. > > Signed-off-by: Daniel Vetter Looks legit. Just a minor alteration to include the w/a name inside ilk_dummy_write() as well. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [pull] drm-intel-fixes
Hi Dave, The big thing is the disabling of the hsw support by default, cc: stable. We've aimed for basic hsw support in 3.6, but due to a few bad happenstances we've screwed up and only 3.8 will have better modeset support than vesa. To avoid yet another round of fallout from such a gaffle on for the next platform we've added a module option to disable early hw support by default. That should also give us more flexibility in bring-up. Otherwise just small fixes: - 3 fixes from Egbert for sdvo corner cases - invert-brightness quirk entry from Egbert - revert a dp link training change, it regresses some setups - and shut up a spurious WARN in our gem fault handler. Yours, Daniel The following changes since commit be3cd5e37716bcf1579f63bdd919345a1f9692b9: drm/i915: fix non-DP-D eDP backlight cleanup and module reload (2012-10-12 10:59:12 +0200) are available in the git repository at: git://people.freedesktop.org/~danvet/drm-intel drm-intel-fixes for you to fetch changes up to 0a3af268644e0217ea22d6899a76187f930e9590: drm/i915: Insert i915_preliminary_hw_support variable. (2012-10-17 21:21:45 +0200) Daniel Vetter (2): Revert "drm/i915: Try harder to complete DP training pattern 1" drm/i915: shut up spurious WARN in the gtt fault handler Egbert Eich (4): DRM/i915: Don't delete DPLL Multiplier during DAC init. DRM/i915: Add QUIRK_INVERT_BRIGHTNESS for NCR machines. DRM/i915: Don't clone SDVO LVDS with analog. DRM/i915: Restore sdvo_flags after dtd->mode->dtd Roundrtrip. Rodrigo Vivi (1): drm/i915: Insert i915_preliminary_hw_support variable. drivers/gpu/drm/i915/i915_drv.c | 13 + drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_gem.c |4 +++- drivers/gpu/drm/i915/intel_crt.c | 15 +-- drivers/gpu/drm/i915/intel_display.c | 32 drivers/gpu/drm/i915/intel_dp.c | 15 ++- drivers/gpu/drm/i915/intel_sdvo.c| 14 ++ 7 files changed, 70 insertions(+), 24 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Clear FORCEWAKE when taking over from BIOS
Some BIOSes may forcibly suspend RC6 during their operation which
trigger a warning as we find the hardware in a perplexing state upon
first use. So far that appears to be the worst symptom as fortuituously
we use the same values as the BIOS for programming the FORCEWAKE register.
Reported-by:
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 705b2e1..ea2b718 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -526,6 +526,8 @@ static int i915_drm_thaw(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int error = 0;
+ intel_gt_reset(dev);
+
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
mutex_lock(&dev->struct_mutex);
i915_gem_restore_gtt_mappings(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b7f07b..3a0c102 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1300,6 +1300,7 @@ void i915_handle_error(struct drm_device *dev, bool
wedged);
extern void intel_irq_init(struct drm_device *dev);
extern void intel_gt_init(struct drm_device *dev);
+extern void intel_gt_reset(struct drm_device *dev);
void i915_error_state_free(struct kref *error_ref);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 423ee69..fbdb104 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3999,6 +3999,12 @@ static void __gen6_gt_wait_for_thread_c0(struct
drm_i915_private *dev_priv)
DRM_ERROR("GT thread status wait timed out\n");
}
+static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE_NOTRACE(FORCEWAKE, 0);
+ POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE
*/
+}
+
static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
u32 forcewake_ack;
@@ -4022,6 +4028,12 @@ static void __gen6_gt_force_wake_get(struct
drm_i915_private *dev_priv)
__gen6_gt_wait_for_thread_c0(dev_priv);
}
+static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
+ POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE
*/
+}
+
static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
{
u32 forcewake_ack;
@@ -4117,6 +4129,11 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv)
return ret;
}
+static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0x));
+}
+
static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
{
if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
@@ -4139,12 +4156,27 @@ static void vlv_force_wake_put(struct drm_i915_private
*dev_priv)
gen6_gt_check_fifodbg(dev_priv);
}
+void intel_gt_reset(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (IS_VALLEYVIEW(dev)) {
+ vlv_force_wake_reset(dev_priv);
+ } else if (INTEL_INFO(dev)->gen >= 6) {
+ __gen6_gt_force_wake_reset(dev_priv);
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+ __gen6_gt_force_wake_mt_reset(dev_priv);
+ }
+}
+
void intel_gt_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
spin_lock_init(&dev_priv->gt_lock);
+ intel_gt_reset(dev);
+
if (IS_VALLEYVIEW(dev)) {
dev_priv->gt.force_wake_get = vlv_force_wake_get;
dev_priv->gt.force_wake_put = vlv_force_wake_put;
--
1.7.10.4
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Re: [Intel-gfx] Lockup when switching displays using xrandr since kernel 3.5.x
Am Donnerstag, den 18.10.2012, 09:10 +0200 schrieb Thilo-Alexander Ginkel: > On Wed, Oct 17, 2012 at 1:26 AM, Thilo-Alexander Ginkel wrote: > > since upgrading from kernel 3.4.10 to 3.5.x or 3.6.2 (on Kubuntu > > 12.04) I am getting sporadic (but frequent) lockups when switching > > displays using xrandr: > > [...] > > BTW, the lockups also happen with i915.i915_enable_rc6=1 (instead of > the original i915.i915_enable_rc6=3). Please follow the instructions on the page »How to file a good bug report« [1]. Thanks, Paul [1] http://intellinuxgraphics.org/how_to_report_bug.html signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Lockup when switching displays using xrandr since kernel 3.5.x
On Thu, Oct 18, 2012 at 9:10 AM, Thilo-Alexander Ginkel wrote: > On Wed, Oct 17, 2012 at 1:26 AM, Thilo-Alexander Ginkel > wrote: >> since upgrading from kernel 3.4.10 to 3.5.x or 3.6.2 (on Kubuntu >> 12.04) I am getting sporadic (but frequent) lockups when switching >> displays using xrandr: >> [...] > > BTW, the lockups also happen with i915.i915_enable_rc6=1 (instead of > the original i915.i915_enable_rc6=3). Have you upgrade to the very latest xf86-video-intel version already? We've fixed a few bugs related to modeset changes and hanging the gpu. Otherwise, make sure that your kernel contains: commit 5bb61643f6a70d48de9cfe91ad0fee0d618b6816 Author: Chris Wilson Date: Thu Sep 27 21:25:58 2012 +0100 drm/i915: Flush the pending flips on the CRTC before modification Yours, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: document a few more already implemented ilk w/as
Found while strolling docs. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aa77639..45ffb2c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3342,6 +3342,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) /* Required for CxSR */ dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; + /* WaDisableSVSMUnitClockGating */ I915_WRITE(PCH_3DCGDIS0, MARIUNIT_CLOCK_GATE_DISABLE | SVSMUNIT_CLOCK_GATE_DISABLE); @@ -3353,7 +3354,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) /* * According to the spec the following bits should be set in * order to enable memory self-refresh -* The bit 22/21 of 0x42004 +* The bit 22/21 of 0x42004 (WaDisableDisplayFetchStrideStreching) * The bit 5 of 0x42020 * The bit 15 of 0x45000 */ -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: WaInsertNoopAfterBatchEndCommand
Comment says that this applies to earlier gens, too. Since two more
MI_NOOP's can't hurt that much, I've figured I'll apply this w/a down
to gen2.
v2: Correct the ringbuffer dword count for gen3, spotted by Chris
Wilson.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 984a0c5..38092dc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -969,7 +969,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length)
{
int ret;
- ret = intel_ring_begin(ring, 2);
+ ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
@@ -978,6 +978,11 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length)
MI_BATCH_GTT |
MI_BATCH_NON_SECURE_I965);
intel_ring_emit(ring, offset);
+ /* WaInsertNoopAfterBatchEndCommand: Command says to do the same after
+* the batchbuffer start command. Unclear whether really required on
+* gen3, but better safe than sorry. */
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
@@ -996,7 +1001,10 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
intel_ring_emit(ring, MI_BATCH_BUFFER);
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
intel_ring_emit(ring, offset + len - 8);
- intel_ring_emit(ring, 0);
+ /* WaInsertNoopAfterBatchEndCommand: Command says to do the same after
+* the batchbuffer start command. Unclear whether really required on
+* gen2, but better safe than sorry. */
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
@@ -1008,12 +1016,16 @@ i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
{
int ret;
- ret = intel_ring_begin(ring, 2);
+ ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
+ /* WaInsertNoopAfterBatchEndCommand: Command says to do the same after
+* the batchbuffer start command. */
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
--
1.7.10.4
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[Intel-gfx] [PATCH 4/5] drm/i915: implement WaDisableSpriteDestColorKey
Unfortunately this requires a bit of book-keeping to return the
right values for get_colorkey and to set things up correctly
when re-enabling the plane.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_drv.h|2 ++
drivers/gpu/drm/i915/intel_sprite.c | 27 +++
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 79f8ed6..e935e75 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -220,6 +220,8 @@ struct intel_plane {
struct drm_i915_gem_object *obj;
int max_downscale;
u32 lut_r[1024], lut_g[1024], lut_b[1024];
+ bool restore_ilk_dest_key; /* for a w/a */
+
void (*update_plane)(struct drm_plane *plane,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 7644f31..8bcacd5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -230,6 +230,13 @@ ilk_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
dvscntr = I915_READ(DVSCNTR(pipe));
+ WARN_ON(!(dvscntr & DVS_ENABLE) && (dvscntr && DVS_DEST_KEY));
+
+ if (intel_plane->restore_ilk_dest_key) {
+ dvscntr |= DVS_DEST_KEY;
+ intel_plane->restore_ilk_dest_key = false;
+ }
+
/* Mask out pixel format bits in case we change it */
dvscntr &= ~DVS_PIXFORMAT_MASK;
dvscntr &= ~DVS_RGB_ORDER_XBGR;
@@ -311,8 +318,16 @@ ilk_disable_plane(struct drm_plane *plane)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
int pipe = intel_plane->pipe;
+ uint32_t tmp;
- I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
+ /* WaDisableSpriteDestColorKey: We need to disable the dest key when
+* disabling the sprite. */
+ tmp = I915_READ(DVSCNTR(pipe));
+ if (IS_GEN5(dev) &&(tmp & DVS_DEST_KEY))
+ intel_plane->restore_ilk_dest_key = true;
+ tmp &= ~(DVS_ENABLE | DVS_DEST_KEY);
+
+ I915_WRITE(DVSCNTR(pipe), tmp);
/* Disable the scaler */
I915_WRITE(DVSSCALE(pipe), 0);
/* Flush double buffered register updates */
@@ -365,6 +380,7 @@ ilk_update_colorkey(struct drm_plane *plane,
int ret = 0;
intel_plane = to_intel_plane(plane);
+ intel_plane->restore_ilk_dest_key = false;
I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
@@ -372,9 +388,12 @@ ilk_update_colorkey(struct drm_plane *plane,
dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
- if (key->flags & I915_SET_COLORKEY_DESTINATION)
- dvscntr |= DVS_DEST_KEY;
- else if (key->flags & I915_SET_COLORKEY_SOURCE)
+ if (key->flags & I915_SET_COLORKEY_DESTINATION) {
+ if ((dvscntr & DVS_ENABLE) || !IS_GEN5(dev))
+ dvscntr |= DVS_DEST_KEY;
+ else
+ intel_plane->restore_ilk_dest_key = true;
+ } else if (key->flags & I915_SET_COLORKEY_SOURCE)
dvscntr |= DVS_SOURCE_KEY;
I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
--
1.7.10.4
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[Intel-gfx] [PATCH 2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush
Comment says for eaglelake/cantiga, but it's listed in the ilk table, too. So apply it to both. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |8 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a4162dd..1970c54 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -661,6 +661,7 @@ #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0)/* display B > display A */ #define CACHE_MODE_0 0x02120 /* 915+ only */ +#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) #define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 72f41aa..aa77639 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3397,6 +3397,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED << 16 | _3D_CHICKEN2_WM_READ_PIPELINED); + + /* WaDisableRenderCachePipelinedFlush */ + I915_WRITE(CACHE_MODE_0, + _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); } static void gen6_init_clock_gating(struct drm_device *dev) @@ -3728,6 +3732,10 @@ static void g4x_init_clock_gating(struct drm_device *dev) if (IS_GM45(dev)) dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; I915_WRITE(DSPCLK_GATE_D, dspclk_gate); + + /* WaDisableRenderCachePipelinedFlush */ + I915_WRITE(CACHE_MODE_0, + _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); } static void crestline_init_clock_gating(struct drm_device *dev) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6
Or at least our best understanding of it.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7837e5..c3f4f04 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,9 +1131,20 @@ static bool IS_DISPLAYREG(u32 reg)
return true;
}
+static void
+ilk_dummy_write(struct drm_i915_private *dev_priv)
+{
+ /* Ilk w/a: Issue a dummy write to wake up the chip from rc6 before
+* touching it for real. MI_MODE is masked, hence harmless to write 0
+* into. */
+ I915_WRITE_NOTRACE(MI_MODE, 0);
+}
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
unsigned long irqflags; \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
@@ -1165,6 +1176,8 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32
reg, u##x val) { \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
+ if (IS_GEN5(dev_priv->dev)) \
+ ilk_dummy_write(dev_priv); \
if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
write##y(val, dev_priv->regs + reg + 0x18); \
} else {\
--
1.7.10.4
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[Intel-gfx] [PATCH 0/5] pile of ilk related workarounds
Hi all, Dave reported a gpu hang regression on his ilk, likely due to the re-enabled rc6 support (but not confirmed). So I've scrounged through the w/a database and found a few bits. Preliminary verdict is that this seems to prevent the hangs. If that stands for a few more days, I'd like to merge patches 1-3 to -fixes, the last two for dinq. Please review. Thanks, Daniel Daniel Vetter (5): drm/i915: implement WaIssueDummyWriteToWakupFromRC6 drm/i915: implement WaDisableRenderCachePipelinedFlush drm/i915: WaInsertNoopAfterBatchEndCommand drm/i915: implement WaDisableSpriteDestColorKey drm/i915: document a few more already implemented ilk w/as drivers/gpu/drm/i915/i915_drv.c | 13 + drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_drv.h|2 ++ drivers/gpu/drm/i915/intel_pm.c | 11 ++- drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++--- drivers/gpu/drm/i915/intel_sprite.c | 27 +++ 6 files changed, 64 insertions(+), 8 deletions(-) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/10] drm: extract drm_dp_max_lane_count helper
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_dp.c | 17 ++---
drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +-
drivers/gpu/drm/radeon/atombios_dp.c | 7 +--
include/drm/drm_dp_helper.h | 7 +++
4 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fea768d..72fbd6c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -127,19 +127,6 @@ intel_edp_target_clock(struct intel_encoder *intel_encoder,
}
static int
-intel_dp_max_lane_count(struct intel_dp *intel_dp)
-{
- int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
- switch (max_lane_count) {
- case 1: case 2: case 4:
- break;
- default:
- max_lane_count = 4;
- }
- return max_lane_count;
-}
-
-static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
@@ -199,7 +186,7 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp,
bool adjust_mode)
{
int max_link_clock =
intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
- int max_lanes = intel_dp_max_lane_count(intel_dp);
+ int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
int max_rate, mode_rate;
mode_rate = intel_dp_link_required(mode->clock, 24);
@@ -675,7 +662,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
struct drm_device *dev = encoder->dev;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
int lane_count, clock;
- int max_lane_count = intel_dp_max_lane_count(intel_dp);
+ int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 :
0;
int bpp, mode_rate;
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c
b/drivers/gpu/drm/nouveau/nouveau_dp.c
index d46a8ff..2786594 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -528,7 +528,7 @@ nouveau_dp_detect(struct drm_encoder *encoder)
return false;
nv_encoder->dp.link_bw = 27000 * dpcd[1];
- nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
+ nv_encoder->dp.link_nr = drm_dp_max_lane_count(dpcd);
NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index aebd4d3..d808cb4 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -347,11 +347,6 @@ static int dp_get_max_dp_pix_clock(int link_rate,
return (link_rate * lane_num * 8) / bpp;
}
-static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
-{
- return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
-}
-
/* radeon specific DP functions */
/* First get the min lane# when low rate is used according to pixel clock
@@ -364,7 +359,7 @@ static int radeon_dp_get_dp_lane_number(struct
drm_connector *connector,
{
int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
int max_link_rate = drm_dp_max_link_rate(dpcd);
- int max_lane_num = dp_get_max_lane_number(dpcd);
+ int max_lane_num = drm_dp_max_lane_count(dpcd);
int lane_num;
int max_dp_pix_clock;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 455f8e0..c09d367 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -346,4 +346,11 @@ drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
}
+
+static inline u8
+drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+}
+
#endif /* _DRM_DP_HELPER_H_ */
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/10] drm: extract dp link bw helpers
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_helper.c | 28
drivers/gpu/drm/i915/intel_dp.c | 5 +
drivers/gpu/drm/radeon/atombios_dp.c | 32 +++-
include/drm/drm_dp_helper.h | 8
4 files changed, 40 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index e43ddde..d8a4189 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -298,3 +298,31 @@ void drm_dp_link_train_channel_eq_delay(u8
dpcd[DP_RECEIVER_CAP_SIZE]) {
mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+
+u8 drm_dp_link_rate_to_bw_code(int link_rate)
+{
+ switch (link_rate) {
+ case 162000:
+ default:
+ return DP_LINK_BW_1_62;
+ case 27:
+ return DP_LINK_BW_2_7;
+ case 54:
+ return DP_LINK_BW_5_4;
+ }
+}
+EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
+
+int drm_dp_bw_code_to_link_rate(u8 link_bw)
+{
+ switch (link_bw) {
+ case DP_LINK_BW_1_62:
+ default:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 27;
+ case DP_LINK_BW_5_4:
+ return 54;
+ }
+}
+EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 865f7f3..fea768d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -111,10 +111,7 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
struct intel_dp *intel_dp = container_of(intel_encoder, struct
intel_dp, base);
*lane_num = intel_dp->lane_count;
- if (intel_dp->link_bw == DP_LINK_BW_1_62)
- *link_bw = 162000;
- else if (intel_dp->link_bw == DP_LINK_BW_2_7)
- *link_bw = 27;
+ *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
}
int
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 4551ea5..aebd4d3 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -347,37 +347,11 @@ static int dp_get_max_dp_pix_clock(int link_rate,
return (link_rate * lane_num * 8) / bpp;
}
-static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
-{
- switch (dpcd[DP_MAX_LINK_RATE]) {
- case DP_LINK_BW_1_62:
- default:
- return 162000;
- case DP_LINK_BW_2_7:
- return 27;
- case DP_LINK_BW_5_4:
- return 54;
- }
-}
-
static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
{
return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
}
-static u8 dp_get_dp_link_rate_coded(int link_rate)
-{
- switch (link_rate) {
- case 162000:
- default:
- return DP_LINK_BW_1_62;
- case 27:
- return DP_LINK_BW_2_7;
- case 54:
- return DP_LINK_BW_5_4;
- }
-}
-
/* radeon specific DP functions */
/* First get the min lane# when low rate is used according to pixel clock
@@ -389,7 +363,7 @@ static int radeon_dp_get_dp_lane_number(struct
drm_connector *connector,
int pix_clock)
{
int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
- int max_link_rate = dp_get_max_link_rate(dpcd);
+ int max_link_rate = drm_dp_max_link_rate(dpcd);
int max_lane_num = dp_get_max_lane_number(dpcd);
int lane_num;
int max_dp_pix_clock;
@@ -427,7 +401,7 @@ static int radeon_dp_get_dp_link_clock(struct drm_connector
*connector,
return 54;
}
- return dp_get_max_link_rate(dpcd);
+ return drm_dp_max_link_rate(dpcd);
}
static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
@@ -692,7 +666,7 @@ static int radeon_dp_link_train_init(struct
radeon_dp_link_train_info *dp_info)
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET,
tmp);
/* set the link rate on the sink */
- tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
+ tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
/* start training on the source */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 60bd8d3..455f8e0 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -338,4 +338,12 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8
link_status[DP_LINK_STATUS_SIZE],
void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+u8 drm_dp_link_rate_to_bw_code(int link_rate);
+int drm_dp_bw_code_to_link_rate(u8 link_bw);
+
+static inli
[Intel-gfx] [PATCH 08/10] drm/i915: use the new dp train delay helpers
Only really required for dp 1.2. I've hoped this would help with some
link training woes I'm fighting, but alas those are only dp 1.1
devices.
Also move a comment that went misplaced in the recent refactorings to
the right spot again.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aa1a28c..865f7f3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1806,13 +1806,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
signal_levels);
+ /* Set training pattern 1 */
if (!intel_dp_set_link_train(intel_dp, DP,
DP_TRAINING_PATTERN_1 |
DP_LINK_SCRAMBLING_DISABLE))
break;
- /* Set training pattern 1 */
- udelay(100);
+ drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
break;
@@ -1900,7 +1900,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
DP_LINK_SCRAMBLING_DISABLE))
break;
- udelay(400);
+ drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
if (!intel_dp_get_link_status(intel_dp, link_status))
break;
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm: extract dp link train delay functions from radeon
This requires a few changes since that dpcd value is above the
range currently cached by radeon. I've check the dp specs, and
above 0xf there's a big gap and nothing that looks like we should
cache it while a given device is plugged in. It's also the same value
that i915.ko uses.
Hence extend the various dpcd arrays in the radeon driver, use
proper symbolic constants where applicable (one place overallocated
the dpcd array to 25 bytes). Then also drop the rd_interval cache -
radeon_dp_link_train_init re-reads the dpcd block, so the values we'll
consume in train_cr and train_ce will always be fresh.
To avoid needless diff-churn, #define the old size of dpcd as the new
one and keep it around.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_helper.c | 15 +++
drivers/gpu/drm/i915/intel_dp.c | 1 -
drivers/gpu/drm/radeon/atombios_dp.c | 25 +
drivers/gpu/drm/radeon/radeon_mode.h | 2 +-
include/drm/drm_dp_helper.h | 5 +
5 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index d1a196f..e43ddde 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -283,3 +283,18 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8
link_status[DP_LINK_STATUS_SIZE],
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+ if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ udelay(100);
+ else
+ mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+}
+EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
+
+void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+ if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ udelay(400);
+ else
+ mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+}
+EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4cd957a..aa1a28c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -37,7 +37,6 @@
#include "i915_drm.h"
#include "i915_drv.h"
-#define DP_RECEIVER_CAP_SIZE 0xf
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
/**
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 5479832..4551ea5 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -34,7 +34,7 @@
/* move these to drm_dp_helper.c/h */
#define DP_LINK_CONFIGURATION_SIZE 9
-#define DP_DPCD_SIZE 8
+#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
static char *voltage_names[] = {
"0.4V", "0.6V", "0.8V", "1.2V"
@@ -478,14 +478,15 @@ static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector)
bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
{
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
- u8 msg[25];
+ u8 msg[DP_DPCD_SIZE];
int ret, i;
- ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8,
0);
+ ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
+ DP_DPCD_SIZE, 0);
if (ret > 0) {
- memcpy(dig_connector->dpcd, msg, 8);
+ memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
DRM_DEBUG_KMS("DPCD: ");
- for (i = 0; i < 8; i++)
+ for (i = 0; i < DP_DPCD_SIZE; i++)
DRM_DEBUG_KMS("%02x ", msg[i]);
DRM_DEBUG_KMS("\n");
@@ -604,9 +605,8 @@ struct radeon_dp_link_train_info {
int enc_id;
int dp_clock;
int dp_lane_count;
- int rd_interval;
bool tp3_supported;
- u8 dpcd[8];
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 train_set[4];
u8 link_status[DP_LINK_STATUS_SIZE];
u8 tries;
@@ -748,10 +748,7 @@ static int radeon_dp_link_train_cr(struct
radeon_dp_link_train_info *dp_info)
dp_info->tries = 0;
voltage = 0xff;
while (1) {
- if (dp_info->rd_interval == 0)
- udelay(100);
- else
- mdelay(dp_info->rd_interval * 4);
+ drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
if (!radeon_dp_get_link_status(dp_info->radeon_connector,
dp_info->link_status)) {
DRM_ERROR("displayport link status failed\n");
@@ -813,10 +810,7 @@ static int radeon_dp_link_train_ce(struct
radeon_dp_link_train_info *dp_info)
dp_info->tries = 0;
channel_eq = false;
while (1) {
- if (dp_info->rd_interval == 0)
- udelay(400);
- else
- mdelay(dp_info->rd_interval * 4);
+ drm_dp_link_train_channel_eq_delay(dp_info->d
[Intel-gfx] [PATCH 06/10] drm/nouveau: use dp link train request helper
nouveau again score with an impressive density of magic numbers.
Again only compile-tested due to lack of hw, but should be equivalent
code.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/nouveau/nouveau_dp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c
b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 60d561e..d46a8ff 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -261,11 +261,10 @@ dp_link_train_commit(struct drm_device *dev, struct
dp_state *dp)
int i;
for (i = 0; i < dp->link_nr; i++) {
- u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
- u8 lpre = (lane & 0x0c) >> 2;
- u8 lvsw = (lane & 0x03) >> 0;
+ u8 lpre = drm_dp_get_adjust_request_pre_emphasis(dp->stat, i);
+ u8 lvsw = drm_dp_get_adjust_request_voltage(dp->stat, i);
- dp->conf[i] = (lpre << 3) | lvsw;
+ dp->conf[i] = lpre | lvsw;
if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/10] drm: extract helpers to compute new training values from sink request
Safe for the minor difference that the intel versions get an offset
into the link_status as an argument, both are the same again.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_helper.c | 27 +++
drivers/gpu/drm/i915/intel_dp.c | 30 ++
drivers/gpu/drm/radeon/atombios_dp.c | 34 ++
include/drm/drm_dp_helper.h | 4
4 files changed, 35 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9dde04a..d1a196f 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -256,3 +256,30 @@ bool drm_dp_clock_recovery_ok(u8
link_status[DP_LINK_STATUS_SIZE],
return true;
}
EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
+
+u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
+int lane)
+{
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
+DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
+ u8 l = dp_link_status(link_status, i);
+
+ return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
+}
+EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
+
+u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+{
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
+DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
+ u8 l = dp_link_status(link_status, i);
+
+ return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+}
+EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5a9ab3a..4cd957a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1399,31 +1399,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp,
uint8_t link_status[DP_LINK_
DP_LINK_STATUS_SIZE);
}
-static uint8_t
-intel_get_adjust_request_voltage(uint8_t adjust_request[2],
-int lane)
-{
- int s = ((lane & 1) ?
-DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
-DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
- uint8_t l = adjust_request[lane>>1];
-
- return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
-}
-
-static uint8_t
-intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
- int lane)
-{
- int s = ((lane & 1) ?
-DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
-DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
- uint8_t l = adjust_request[lane>>1];
-
- return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
-}
-
-
#if 0
static char*voltage_names[] = {
"0.4V", "0.6V", "0.8V", "1.2V"
@@ -1502,13 +1477,12 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
uint8_t link_status[DP_LINK_ST
uint8_t v = 0;
uint8_t p = 0;
int lane;
- uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 -
DP_LANE0_1_STATUS);
uint8_t voltage_max;
uint8_t preemph_max;
for (lane = 0; lane < intel_dp->lane_count; lane++) {
- uint8_t this_v =
intel_get_adjust_request_voltage(adjust_request, lane);
- uint8_t this_p =
intel_get_adjust_request_pre_emphasis(adjust_request, lane);
+ uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
+ uint8_t this_p =
drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
if (this_v > v)
v = this_v;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 75fdf34..5479832 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -289,36 +289,6 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int
mode,
/* general DP utility functions */
-static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
-{
- return link_status[r - DP_LANE0_1_STATUS];
-}
-
-static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
- int lane)
-
-{
- int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
- int s = ((lane & 1) ?
-DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
-DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
- u8 l = dp_link_status(link_status, i);
-
- return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
-}
-
-static u8 dp_get_adjust_request_pre_emphasis(u8
link_status[DP_LINK_STATUS_SIZE],
-int lane)
-{
- int i = DP_ADJUST_R
[Intel-gfx] [PATCH 04/10] drm/nouveau: use the cr_ok/chanel_eq_ok helpers
Only compile-tested, due to a lack of nouveau dp hw. Should be
equivalent code though.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/nouveau/nouveau_dp.c | 26 +-
1 file changed, 5 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c
b/drivers/gpu/drm/nouveau/nouveau_dp.c
index e754aa3..60d561e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -298,7 +298,7 @@ dp_link_train_cr(struct drm_device *dev, struct dp_state
*dp)
{
bool cr_done = false, abort = false;
int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
- int tries = 0, i;
+ int tries = 0;
dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
@@ -307,16 +307,7 @@ dp_link_train_cr(struct drm_device *dev, struct dp_state
*dp)
dp_link_train_update(dev, dp, 100))
break;
- cr_done = true;
- for (i = 0; i < dp->link_nr; i++) {
- u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
- if (!(lane & DP_LANE_CR_DONE)) {
- cr_done = false;
- if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
- abort = true;
- break;
- }
- }
+ cr_done = drm_dp_clock_recovery_ok(dp->stat, dp->link_nr);
if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
@@ -331,7 +322,7 @@ static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
bool eq_done, cr_done = true;
- int tries = 0, i;
+ int tries = 0;
dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
@@ -339,15 +330,8 @@ dp_link_train_eq(struct drm_device *dev, struct dp_state
*dp)
if (dp_link_train_update(dev, dp, 400))
break;
- eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
- for (i = 0; i < dp->link_nr && eq_done; i++) {
- u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
- if (!(lane & DP_LANE_CR_DONE))
- cr_done = false;
- if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
- !(lane & DP_LANE_SYMBOL_LOCKED))
- eq_done = false;
- }
+ eq_done = drm_dp_channel_eq_ok(dp->stat, dp->link_nr);
+ cr_done = drm_dp_clock_recovery_ok(dp->stat, dp->link_nr);
if (dp_link_train_commit(dev, dp))
break;
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] drm: dp helper: extract drm_dp_clock_recovery_ok
radeon and intel use the exact same definition.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
drivers/gpu/drm/radeon/atombios_dp.c | 25 +
include/drm/drm_dp_helper.h | 2 ++
3 files changed, 5 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d3f4db0..5a9ab3a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1845,7 +1845,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
break;
}
- if (intel_clock_recovery_ok(link_status, intel_dp->lane_count))
{
+ if (drm_dp_clock_recovery_ok(link_status,
intel_dp->lane_count)) {
DRM_DEBUG_KMS("clock recovery OK\n");
clock_recovery = true;
break;
@@ -1932,7 +1932,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
/* Make sure clock is still ok */
- if (!intel_clock_recovery_ok(link_status,
intel_dp->lane_count)) {
+ if (!drm_dp_clock_recovery_ok(link_status,
intel_dp->lane_count)) {
intel_dp_start_link_train(intel_dp);
cr_tries++;
continue;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index 8aa8187..75fdf34 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -294,29 +294,6 @@ static u8 dp_link_status(u8
link_status[DP_LINK_STATUS_SIZE], int r)
return link_status[r - DP_LANE0_1_STATUS];
}
-static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
-int lane)
-{
- int i = DP_LANE0_1_STATUS + (lane >> 1);
- int s = (lane & 1) * 4;
- u8 l = dp_link_status(link_status, i);
- return (l >> s) & 0xf;
-}
-
-static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
-int lane_count)
-{
- int lane;
- u8 lane_status;
-
- for (lane = 0; lane < lane_count; lane++) {
- lane_status = dp_get_lane_status(link_status, lane);
- if ((lane_status & DP_LANE_CR_DONE) == 0)
- return false;
- }
- return true;
-}
-
static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
int lane)
@@ -811,7 +788,7 @@ static int radeon_dp_link_train_cr(struct
radeon_dp_link_train_info *dp_info)
break;
}
- if (dp_clock_recovery_ok(dp_info->link_status,
dp_info->dp_lane_count)) {
+ if (drm_dp_clock_recovery_ok(dp_info->link_status,
dp_info->dp_lane_count)) {
clock_recovery = true;
break;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 9e10420..89e92c9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -326,5 +326,7 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
#define DP_LINK_STATUS_SIZE 6
bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
+bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane_count);
#endif /* _DRM_DP_HELPER_H_ */
--
1.7.11.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/10] drm: dp helper: extract drm_dp_channel_eq_ok
radeon and intel use the exact same definition.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_helper.c | 50
drivers/gpu/drm/i915/intel_dp.c | 35 ++---
drivers/gpu/drm/radeon/atombios_dp.c | 24 ++---
include/drm/drm_dp_helper.h | 5
4 files changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f7eba0a..9dde04a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -206,3 +206,53 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
return error;
}
EXPORT_SYMBOL(i2c_dp_aux_add_bus);
+
+/* Helpers for DP link training */
+static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
+{
+ return link_status[r - DP_LANE0_1_STATUS];
+}
+
+static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
+int lane)
+{
+ int i = DP_LANE0_1_STATUS + (lane >> 1);
+ int s = (lane & 1) * 4;
+ u8 l = dp_link_status(link_status, i);
+ return (l >> s) & 0xf;
+}
+
+bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane_count)
+{
+ u8 lane_align;
+ u8 lane_status;
+ int lane;
+
+ lane_align = dp_link_status(link_status,
+ DP_LANE_ALIGN_STATUS_UPDATED);
+ if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
+ return false;
+ for (lane = 0; lane < lane_count; lane++) {
+ lane_status = dp_get_lane_status(link_status, lane);
+ if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
+ return false;
+ }
+ return true;
+}
+EXPORT_SYMBOL(drm_dp_channel_eq_ok);
+
+bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane_count)
+{
+ int lane;
+ u8 lane_status;
+
+ for (lane = 0; lane < lane_count; lane++) {
+ lane_status = dp_get_lane_status(link_status, lane);
+ if ((lane_status & DP_LANE_CR_DONE) == 0)
+ return false;
+ }
+ return true;
+}
+EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f2c9ea6..d3f4db0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,7 +38,6 @@
#include "i915_drv.h"
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_LINK_STATUS_SIZE6
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
/**
@@ -1401,13 +1400,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp,
uint8_t link_status[DP_LINK_
}
static uint8_t
-intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
-int r)
-{
- return link_status[r - DP_LANE0_1_STATUS];
-}
-
-static uint8_t
intel_get_adjust_request_voltage(uint8_t adjust_request[2],
int lane)
{
@@ -1692,29 +1684,6 @@ intel_clock_recovery_ok(uint8_t
link_status[DP_LINK_STATUS_SIZE], int lane_count
return true;
}
-/* Check to see if channel eq is done on all channels */
-#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
-DP_LANE_CHANNEL_EQ_DONE|\
-DP_LANE_SYMBOL_LOCKED)
-static bool
-intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t
link_status[DP_LINK_STATUS_SIZE])
-{
- uint8_t lane_align;
- uint8_t lane_status;
- int lane;
-
- lane_align = intel_dp_link_status(link_status,
- DP_LANE_ALIGN_STATUS_UPDATED);
- if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
- return false;
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
- lane_status = intel_get_lane_status(link_status, lane);
- if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
- return false;
- }
- return true;
-}
-
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
uint32_t dp_reg_value,
@@ -1969,7 +1938,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
continue;
}
- if (intel_channel_eq_ok(intel_dp, link_status)) {
+ if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
channel_eq = true;
break;
}
@@ -2170,7 +2139,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
- if (!intel_channel_eq_ok(intel_dp, link_status)) {
+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
drm_get_encoder_name(&intel_dp->base.base));
intel
[Intel-gfx] [PATCH 01/10] drm: rename drm_dp_i2c_helper.c to drm_dp_helper.c
I want to move some dp link training helpers into this place, so in
the future this won't be just about i2c any longer.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/drm_dp_helper.c | 208
drivers/gpu/drm/drm_dp_i2c_helper.c | 208
3 files changed, 209 insertions(+), 209 deletions(-)
create mode 100644 drivers/gpu/drm/drm_dp_helper.c
delete mode 100644 drivers/gpu/drm/drm_dp_i2c_helper.c
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2ff5cef..dc4e88f 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -19,7 +19,7 @@ drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
drm-usb-y := drm_usb.o
-drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o drm_dp_i2c_helper.o
+drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o drm_dp_helper.o
drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
new file mode 100644
index 000..f7eba0a
--- /dev/null
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright © 2009 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm_dp_helper.h"
+#include "drmP.h"
+
+/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
+static int
+i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
+ uint8_t write_byte, uint8_t *read_byte)
+{
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ int ret;
+
+ ret = (*algo_data->aux_ch)(adapter, mode,
+ write_byte, read_byte);
+ return ret;
+}
+
+/*
+ * I2C over AUX CH
+ */
+
+/*
+ * Send the address. If the I2C link is running, this 'restarts'
+ * the connection with the new address, this is used for doing
+ * a write followed by a read (as needed for DDC)
+ */
+static int
+i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
+{
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ int mode = MODE_I2C_START;
+ int ret;
+
+ if (reading)
+ mode |= MODE_I2C_READ;
+ else
+ mode |= MODE_I2C_WRITE;
+ algo_data->address = address;
+ algo_data->running = true;
+ ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+ return ret;
+}
+
+/*
+ * Stop the I2C transaction. This closes out the link, sending
+ * a bare address packet with the MOT bit turned off
+ */
+static void
+i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
+{
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ int mode = MODE_I2C_STOP;
+
+ if (reading)
+ mode |= MODE_I2C_READ;
+ else
+ mode |= MODE_I2C_WRITE;
+ if (algo_data->running) {
+ (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+ algo_data->running = false;
+ }
+}
+
+/*
+ * Write a single byte to the current I2C address, the
+ * the I2C link must be running or this returns -EIO
+ */
+static int
+i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
+{
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ int ret;
+
+ if (!algo_data->running)
+ return -EIO;
+
+ ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
+ return ret;
+}
+
+/*
+ * Read a single byte from the current I2C address, the
+ * I2C link must be running or this returns -EIO
+ */
+static int
+i2c_algo_dp_aux_get_byte(struct i2c_adapter
[Intel-gfx] [PATCH 00/10] extract dp helper functions
Hi all, I've frustrated myself the last few days yelling at our link training code. Comparing the i915 code to radeon and nouveau I've noticed the lack of a nice set of dp helper functions. So I've started to extract a few. There's lots more that we can do I think (link configuration selection, the i2c over aux retry stuff which diverges already between i915 and radeon, maybe more higher level parts of the training sequence). But there the drivers diverge quite a bit (e.g. the link configuration is driver by different things in each driver: coded link bw from the dp spec, link clock or required bw vs avialable bw), so that's more work and probably best done when reworking these functions for other reasons. I've also tried to put the new helpers a bit to use in nouveau, but due to lack of hw that part is untested. Comments and testing highly welcome. Yours, Daniel Daniel Vetter (10): drm: rename drm_dp_i2c_helper.c to drm_dp_helper.c drm: dp helper: extract drm_dp_channel_eq_ok drm: dp helper: extract drm_dp_clock_recovery_ok drm/nouveau: use the cr_ok/chanel_eq_ok helpers drm: extract helpers to compute new training values from sink request drm/nouveau: use dp link train request helper drm: extract dp link train delay functions from radeon drm/i915: use the new dp train delay helpers drm: extract dp link bw helpers drm: extract drm_dp_max_lane_count helper drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_dp_helper.c | 328 +++ drivers/gpu/drm/drm_dp_i2c_helper.c | 208 -- drivers/gpu/drm/i915/intel_dp.c | 98 ++- drivers/gpu/drm/nouveau/nouveau_dp.c | 35 +--- drivers/gpu/drm/radeon/atombios_dp.c | 147 ++-- drivers/gpu/drm/radeon/radeon_mode.h | 2 +- include/drm/drm_dp_helper.h | 31 8 files changed, 400 insertions(+), 451 deletions(-) create mode 100644 drivers/gpu/drm/drm_dp_helper.c delete mode 100644 drivers/gpu/drm/drm_dp_i2c_helper.c -- 1.7.11.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Insert i915_preliminary_hw_support variable.
On Wed, 17 Oct 2012 21:55:10 -0300, Rodrigo Vivi wrote: > On Wed, Oct 17, 2012 at 4:22 PM, Daniel Vetter wrote: > > > On Mon, Oct 15, 2012 at 05:16:23PM -0300, Rodrigo Vivi wrote: > > > On the worst scenario, users with new hardwares and old kernel from > > enabling times can get black screens. > > > So, now on, this i915_perliminary_hw_support variable shall be used by > > all upcoming platforms that are still under enabling. > > > > > > Although it is uncomfortable for developers use this extra variable it > > brings more stability for end users. > > > > > > Signed-off-by: Rodrigo Vivi > > > > Merged, with the linewrap in the commit message fixed and the module param > > shrunk by the redudant i915_ prefix. > > > > Thanks! > To be honest I don't like any of those i915_... all redundants i195.i915_ There weren't meant to be there, they were just cut'n'pasting the variable name into the wrong field and then enshrined as a public interface. > > > > > > > Thanks, Daniel > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br Non-text part: text/html > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: disable cpu relocs on ilk and earlier
On Mon, Oct 15, 2012 at 5:11 PM, Greg KH wrote: > On Mon, Oct 15, 2012 at 10:11:22AM +0200, Daniel Vetter wrote: >> Hi Greg&stable-team, >> >> The below patch papers over a graphics corruption issue in 3.5/3.6. The >> regression happened due to pwrite tunings in 3.5, which made cpu relocations >> much more likely. >> >> The issue seems to have disappeared in 3.7-rc1, but it takes a few days to >> test >> a patch, so we haven't figured out what exactly fixed things. Now users are >> taking out their pitchforks already, so instead of wasting more days (maybe >> weeks?) to fully understand the bug before backporting the fix, we've opted >> for >> the below disable patch, which should have minimal impact (at most it undoes >> the >> tuning improvements in 3.5). >> >> Patch is tested by reporters & acked by all relevant ppl, please apply to >> 3.5/3.6 series kernels. > > No, I'd really like to wait until you figure out what is happening in > 3.7-rc1 right now before applying the patch. We have the rule, "it must > be in Linus's tree first" for a very good reason :) Ok, the verdict is in (thanks a lot Dave for testing all these different patches) and it seems like commit 504c7267a1e84b157cbd7e9c1b805e1bc0c2c846 Author: Chris Wilson Date: Thu Aug 23 13:12:52 2012 +0100 drm/i915: Use cpu relocations if the object is in the GTT but not mappable from upstream nicely papers over the issues. Please apply to 3.5/3.6 stable series (earlier kernels don't exhibit the problem). Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=852210 Tested-by: Dave Airlie Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Lockup when switching displays using xrandr since kernel 3.5.x
On Wed, Oct 17, 2012 at 1:26 AM, Thilo-Alexander Ginkel wrote: > since upgrading from kernel 3.4.10 to 3.5.x or 3.6.2 (on Kubuntu > 12.04) I am getting sporadic (but frequent) lockups when switching > displays using xrandr: > [...] BTW, the lockups also happen with i915.i915_enable_rc6=1 (instead of the original i915.i915_enable_rc6=3). Regards, Thilo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Insert i915_preliminary_hw_support variable.
On Thu, Oct 18, 2012 at 2:55 AM, Rodrigo Vivi wrote: > To be honest I don't like any of those i915_... all redundants i195.i915_ Yeah, unfortunately we can't kill them because tons of people set random options they've found while googling (i915.rc6=7 anyone?) and if we rename them, the module won't load any more :( -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
