Re: [Intel-gfx] [PATCH 0/2] drm/i915: Page flip vs. GPU reset fixes
On Mon, Feb 18, 2013 at 07:08:47PM +0200, ville.syrj...@linux.intel.com wrote: Here are the (hopefully) final versions of the page flip vs. GPU reset fixes. They survive the i-g-t kms_flip flip-vs-modeset-vs-hang and flip-vs-panning-vs-hang tests, as well as stopping the rings while a fullscreen GL application is running under X. Now that we finish the page flips explicitly, the patches should also work on Gen2-Gen4 hardware, assuming we have otherwise working GPU reset support for them. Both Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: clarify logging about reasons for disabling FBC
On Tue, Feb 19, 2013 at 09:18:20AM +0200, Jani Nikula wrote:
Previously FBC disabling due to per-chip default was logged as being
disabled per module parameter. Distinguish between the two.
v2: Don't even squawk in the debug log if FBC is explicitly disabled (Chris
Wilson).
I'm still not entirely happy, as I still get to see the repeated message
many time a second, but it is an improvement over the current message.
I would be happiest if just the state changes were logged. Something
like in out_disable:
if (reason != dev_priv-no_fbc_reason) {
DEBUG(disabling fbc: %s\n, reason);
dev_priv-no_fbc_reason = reason;
}
and move the enum-string conversion from debugfs and just store the
(static) string.
-Chris
--
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Re: [Intel-gfx] [PATCH] drm/i915: Vanish some unused 3d commands
On Mon, Feb 18, 2013 at 09:18:31PM -0800, Ben Widawsky wrote: i915_reg.h is messy enough without the extra stuff. Signed-off-by: Ben Widawsky b...@bwidawsk.net Would be nice if we could just discard the rest. Since we can't (damn you GEM/DRI1) can we just move them to i915_cmd.h? I would also keep the BLT commands, but since no one else cares to kill off intelfb entirely, I can always reinstate them on that fateful day. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
On Mon, Feb 18, 2013 at 07:00:22PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, if the BIOS did anything wrong, our first I915_{WRITE,READ}
will give us unclaimed register messages.
V2: Even earlier.
Call it intel_early_sanitize_regs() as it seems like a function that
will only grow with time as more warts are discovered.
-Chris
--
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Re: [Intel-gfx] [PATCH 0/2] drm/i915: Page flip vs. GPU reset fixes
On Tue, Feb 19, 2013 at 09:07:21AM +, Chris Wilson wrote: On Mon, Feb 18, 2013 at 07:08:47PM +0200, ville.syrj...@linux.intel.com wrote: Here are the (hopefully) final versions of the page flip vs. GPU reset fixes. They survive the i-g-t kms_flip flip-vs-modeset-vs-hang and flip-vs-panning-vs-hang tests, as well as stopping the rings while a fullscreen GL application is running under X. Now that we finish the page flips explicitly, the patches should also work on Gen2-Gen4 hardware, assuming we have otherwise working GPU reset support for them. Both Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk Both queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: add \n to the end of sysfs attributes
On Thu, 14 Feb 2013, Ben Widawsky b...@bwidawsk.net wrote: On Thu, Feb 14, 2013 at 10:42:11AM +0200, Jani Nikula wrote: It is customary to end sysfs attributes with a newline. As best I can tell, you are correct. Have you tested powertop with this change? If not, can you? Good point. Tested, and eyeballed the powertop sysfs reading code. This should be all right. BR, Jani. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Blog regarding i915 changes in kernel 3.9
On Tue, Feb 19, 2013 at 7:29 AM, William Brown will...@firstyear.id.au wrote: I recently read your blog article at : http://blog.ffwll.ch/2013/02/neat-drmi915-stuff-for-39.html If you don't mind I have two questions regarding these changes. Do any of these fixes correct the black screen on dual gpu laptops when switching to the i915? There are billions of ways you can end up with a black screen, so can't tell. Do these changes affect the issue where on a dual gpu laptop both the i915 and discrete gpu are powered on at boot? If these issues are new to you, Would you mind sending me some hints on how to track them down and potentially correct them? Please file a bug report against DRI - DRM(Intel) on bugs.freedesktop.org with a clear description of how things fail and all the usual details about your hw. Also, please _always_ cc and appropriate mailing list when poking your maintainer, he might be lazy, busy, drunken or on vacation ;-) Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC][PATCH] drm/i915: Fix races in gen4 page flip interrupt handling
On Mon, Feb 18, 2013 at 05:16:06PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Use the gen3 logic for handling page flip interrupts on gen4. We're just missing the other piece of the puzzle: =0 cantiga:~/git/linux (master)$ git diff | cat diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c844790..15218bf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2544,6 +2544,8 @@ static int i965_irq_postinstall(struct drm_device *dev) I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); enable_mask = ~dev_priv-irq_mask; + enable_mask = ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | +I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); enable_mask |= I915_USER_INTERRUPT; if (IS_G4X(dev)) With that, Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk Tested-by: Chris Wilson ch...@chris-wilson.co.uk Unfortuantely this kills the stall_check since that looks like it can easily trigger too early. With the current logic the stall check would kick in on the first vblank after the flip has been submitted to the ring. If the CS takes longer than that to process the commands in the ring, the stall check will cause the page flip to be complete too early. That doesn't sound like a very good idea. Something better should be deviced if we still need the stall check. Indeed. I hope that we've fixed up the races that necessiated the stall check! But if we can think of a similarly cheap sanity check, that would be a useful addition in future. But for now we have to do something before Ben complains about us breaking his vim debugging, so mark it unused. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: remove obsolete obj assignment in page flip
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com --- drivers/gpu/drm/i915/intel_display.c |3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6eb3882..2b9ea56 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6925,7 +6925,6 @@ static void do_intel_finish_page_flip(struct drm_device *dev, drm_i915_private_t *dev_priv = dev-dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_unpin_work *work; - struct drm_i915_gem_object *obj; unsigned long flags; /* Ignore early vblank irqs */ @@ -6955,8 +6954,6 @@ static void do_intel_finish_page_flip(struct drm_device *dev, spin_unlock_irqrestore(dev-event_lock, flags); - obj = work-old_fb_obj; - wake_up_all(dev_priv-pending_flip_queue); queue_work(dev_priv-wq, work-work); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: add \n to the end of sysfs attributes
On Tue, Feb 19, 2013 at 12:33:14PM +0200, Jani Nikula wrote: On Thu, 14 Feb 2013, Ben Widawsky b...@bwidawsk.net wrote: On Thu, Feb 14, 2013 at 10:42:11AM +0200, Jani Nikula wrote: It is customary to end sysfs attributes with a newline. As best I can tell, you are correct. Have you tested powertop with this change? If not, can you? Good point. Tested, and eyeballed the powertop sysfs reading code. This should be all right. Patche queued for next, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: remove obsolete obj assignment in page flip
On Tue, Feb 19, 2013 at 12:50:09PM +0200, Mika Kuoppala wrote: Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: clarify confusion between SDVO and HDMI registers
On Mon, Feb 18, 2013 at 07:00:27PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Some HDMI registers can be used for SDVO, so saying HDMIB should be
the same as saying SDVOB for a given HW generation. This was not
true and led to confusions and even a regression.
Previously we had:
- SDVO{B,C} defined as the Gen3+ registers
- HDMI{B,C,D} and PCH_SDVOB defined as the PCH registers
But now:
- SDVO{B,C} became GEN3_SDVO{B,C} on SDVO code
- SDVO{B,C} became GEN4_HDMI{B,C} on HDMI code
- HDMI{B,C,D} became PCH_HDMI{B,C,D}
- PCH_SDVOB is still the same thing
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
I think we still have a bit of ugly left in here, especially that the
register bit definitions are splattered all over irks me a bit. What about
moving the HDMI stuff up to the SDVO definitions and giving the HDMI bits
consisten HDMI_ prefixes? Imo there's no point in adding duplicate
#defines for all the SDVO_ bits we use in intel_hdmi.c ...
-Daniel
---
drivers/gpu/drm/i915/i915_reg.h | 19 ---
drivers/gpu/drm/i915/intel_display.c | 42
++
drivers/gpu/drm/i915/intel_sdvo.c| 22 +-
3 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e5844b..cd31af2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1680,8 +1680,9 @@
#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 6)
/* SDVO port control */
-#define SDVOB0x61140
-#define SDVOC0x61160
+#define GEN3_SDVOB 0x61140
+#define GEN3_SDVOC 0x61160
+#define PCH_SDVOB0xe1140
#define SDVO_ENABLE(1 31)
#define SDVO_PIPE_B_SELECT (1 30)
#define SDVO_STALL_SELECT (1 29)
@@ -3979,8 +3980,12 @@
#define FDI_PLL_CTL_1 0xfe000
#define FDI_PLL_CTL_2 0xfe004
-/* or SDVOB */
-#define HDMIB 0xe1140
+/* The same register may be used for SDVO or HDMI */
+#define GEN4_HDMIB GEN3_SDVOB
+#define GEN4_HDMIC GEN3_SDVOC
+#define PCH_HDMIBPCH_SDVOB
+#define PCH_HDMIC0xe1150
+#define PCH_HDMID0xe1160
#define PORT_ENABLE(1 31)
#define TRANSCODER(pipe) ((pipe) 30)
#define TRANSCODER_CPT(pipe) ((pipe) 29)
@@ -4001,12 +4006,6 @@
#define HSYNC_ACTIVE_HIGH (1 3)
#define PORT_DETECTED (1 2)
-/* PCH SDVOB multiplex with HDMIB */
-#define PCH_SDVOBHDMIB
-
-#define HDMIC 0xe1150
-#define HDMID 0xe1160
-
#define PCH_LVDS 0xe1180
#define LVDS_DETECTED (1 1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6eb3882..744db70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1419,9 +1419,9 @@ static void assert_pch_ports_disabled(struct
drm_i915_private *dev_priv,
PCH LVDS enabled on transcoder %c, should be disabled\n,
pipe_name(pipe));
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}
/**
@@ -8323,20 +8323,20 @@ static void intel_setup_outputs(struct drm_device
*dev)
if (has_edp_a(dev))
intel_dp_init(dev, DP_A, PORT_A);
- if (I915_READ(HDMIB) PORT_DETECTED) {
+ if (I915_READ(PCH_HDMIB) PORT_DETECTED) {
/* PCH SDVOB multiplex with HDMIB */
found = intel_sdvo_init(dev, PCH_SDVOB, true);
if (!found)
- intel_hdmi_init(dev, HDMIB, PORT_B);
+ intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
if (!found (I915_READ(PCH_DP_B) DP_DETECTED))
intel_dp_init(dev, PCH_DP_B, PORT_B);
}
- if (I915_READ(HDMIC) PORT_DETECTED)
- intel_hdmi_init(dev, HDMIC, PORT_C);
+ if (I915_READ(PCH_HDMIC) PORT_DETECTED)
+ intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
- if (!dpd_is_edp I915_READ(HDMID) PORT_DETECTED)
- intel_hdmi_init(dev, HDMID, PORT_D);
+ if (!dpd_is_edp I915_READ(PCH_HDMID) PORT_DETECTED)
+ intel_hdmi_init(dev, PCH_HDMID, PORT_D);
if (I915_READ(PCH_DP_C) DP_DETECTED)
intel_dp_init(dev, PCH_DP_C, PORT_C);
@@ -8348,24 +8348,26 @@ static void intel_setup_outputs(struct drm_device
[Intel-gfx] [PATCH] drm/i915: Revert hdmp HDP pin checks
This reverts
commit 8ec22b214d76773c9d89f4040505ce10f677ed9a
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Fri May 11 18:01:34 2012 +0100
drm/i915/hdmi: Query the live connector status bit for G4x
and
commit b0ea7d37a8f63eeec5ae80b4a6403cfba01da02f
Author: Damien Lespiau damien.lesp...@intel.com
Date: Thu Dec 13 16:09:00 2012 +
drm/i915/hdmi: Read the HPD status before trying to read the EDID
They reliably cause HDMI to not be detected on some systems (like my
ivb or the bug reporters gm45). To fix up the very slow unplug issues
we might want to fire up a 2nd detect cycle a few hundred ms after
each hotplug. But for now at least make displays work again.
I somewhat suspect that this is confined to HDMI connectors, since all
the machines I have with DP+ outputs work correctly.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52361
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Jani Nikula jani.nik...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_hdmi.c | 29 -
1 file changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 599a27e..67ad17b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -827,28 +827,6 @@ bool intel_hdmi_compute_config(struct intel_encoder
*encoder,
return true;
}
-static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
-{
- struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_digital_port *intel_dig_port =
hdmi_to_dig_port(intel_hdmi);
- uint32_t bit;
-
- switch (intel_dig_port-port) {
- case PORT_B:
- bit = PORTB_HOTPLUG_LIVE_STATUS;
- break;
- case PORT_C:
- bit = PORTC_HOTPLUG_LIVE_STATUS;
- break;
- default:
- bit = 0;
- break;
- }
-
- return I915_READ(PORT_HOTPLUG_STAT) bit;
-}
-
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
@@ -861,13 +839,6 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
struct edid *edid;
enum drm_connector_status status = connector_status_disconnected;
-
- if (IS_G4X(dev) !g4x_hdmi_connected(intel_hdmi))
- return status;
- else if (HAS_PCH_SPLIT(dev)
-!ibx_digital_port_connected(dev_priv, intel_dig_port))
-return status;
-
intel_hdmi-has_hdmi_sink = false;
intel_hdmi-has_audio = false;
intel_hdmi-rgb_quant_range_selectable = false;
--
1.7.11.4
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Re: [Intel-gfx] [PATCH] drm/i915: Revert hdmp HDP pin checks
On Tue, Feb 19, 2013 at 01:30:40PM +0100, Daniel Vetter wrote: They reliably cause HDMI to not be detected on some systems (like my ivb or the bug reporters gm45). To fix up the very slow unplug issues we might want to fire up a 2nd detect cycle a few hundred ms after each hotplug. But for now at least make displays work again. If the status bit is not being set, how is the hotplug event being generated? Is it ever set? Before we throw it away, I'd just like to have a little more evidence that it is unsalvageable. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 2/2] intel_chipset: Add multiple inclusion guards into intel_chipset.h
On Mon, Feb 18, 2013 at 09:41:10PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Applied the two i-g-t patches. -Daniel --- lib/intel_chipset.h | 5 + 1 file changed, 5 insertions(+) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 6b4fab3..f703239 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -25,6 +25,9 @@ * */ +#ifndef _INTEL_CHIPSET_H +#define _INTEL_CHIPSET_H + #define PCI_CHIP_I8100x7121 #define PCI_CHIP_I810_DC100 0x7123 #define PCI_CHIP_I810_E 0x7125 @@ -274,3 +277,5 @@ #define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \ (devid) == PCI_CHIP_I965_GME) + +#endif /* _INTEL_CHIPSET_H */ -- 1.7.12.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be completed too soon.
To eliminate this race, check the live pending flip status from the ISR
register before finishing the page flip.
v2: Added a comment explaining the logic (by Chris Wilson)
v3: Fix a typo in the comment
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Tested-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9fde49a..6488249 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2284,8 +2284,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 0)) {
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 0);
- intel_finish_page_flip(dev, 0);
- flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 0);
+ flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2293,8 +2296,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 1)) {
if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 1);
- intel_finish_page_flip(dev, 1);
- flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 1);
+ flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2491,8 +2497,17 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, pipe)) {
if (iir flip[plane]) {
intel_prepare_page_flip(dev, plane);
- intel_finish_page_flip(dev, pipe);
- flip_mask = ~flip[plane];
+
+ /* We detect FlipDone by looking for
the change in PendingFlip from '1'
+* to '0' on the following vblank, i.e.
IIR has the Pendingflip
+* asserted following the
MI_DISPLAY_FLIP, but ISR is deasserted, hence
+* the flip is completed (no longer
pending). Since this doesn't raise an
+* interrupt per se, we watch for the
change at vblank.
+*/
+ if ((I915_READ(ISR) flip[plane]) ==
0) {
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[plane];
+ }
}
}
--
1.7.12.4
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[Intel-gfx] [PATCH v2 2/2] drm/i915: Fix races in gen4 page flip interrupt handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the gen3 logic for handling page flip interrupts on gen4.
Unfortuantely this kills the stall_check since that looks like it can
easily trigger too early. With the current logic the stall check would
kick in on the first vblank after the flip has been submitted to the
ring. If the CS takes longer than that to process the commands in the
ring, the stall check will cause the page flip to be complete too
early. That doesn't sound like a very good idea. Something better
should be deviced if we still need the stall check. For now, mark
i915_pageflip_stall_check() as unused.
v2: Fix irq enable_mask and add __always_unused (Chris Wilson)
References:
https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1116587
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Tested-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6488249..18de788 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1547,7 +1547,7 @@ void i915_handle_error(struct drm_device *dev, bool
wedged)
queue_work(dev_priv-wq, dev_priv-gpu_error.work);
}
-static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
+static void __always_unused i915_pageflip_stall_check(struct drm_device *dev,
int pipe)
{
drm_i915_private_t *dev_priv = dev-dev_private;
struct drm_crtc *crtc = dev_priv-pipe_to_crtc_mapping[pipe];
@@ -2598,6 +2598,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
enable_mask = ~dev_priv-irq_mask;
+ enable_mask = ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
+I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
enable_mask |= I915_USER_INTERRUPT;
if (IS_G4X(dev))
@@ -2684,6 +2686,13 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
unsigned long irqflags;
int irq_received;
int ret = IRQ_NONE, pipe;
+ u32 flip[2] = {
+ I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
+ I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
+ };
+ u32 flip_mask =
+ I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
+ I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
atomic_inc(dev_priv-irq_received);
@@ -2692,7 +2701,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
for (;;) {
bool blc_event = false;
- irq_received = iir != 0;
+ irq_received = (iir ~flip_mask) != 0;
/* Can't rely on pipestat interrupt bit in iir as it might
* have been cleared after the pipestat interrupt was received.
@@ -2739,7 +2748,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
I915_READ(PORT_HOTPLUG_STAT);
}
- I915_WRITE(IIR, iir);
+ I915_WRITE(IIR, iir ~flip_mask);
new_iir = I915_READ(IIR); /* Flush posted writes */
if (iir I915_USER_INTERRUPT)
@@ -2747,17 +2756,17 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (iir I915_BSD_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[VCS]);
- if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
- intel_prepare_page_flip(dev, 0);
-
- if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
- intel_prepare_page_flip(dev, 1);
-
for_each_pipe(pipe) {
if (pipe_stats[pipe]
PIPE_START_VBLANK_INTERRUPT_STATUS
drm_handle_vblank(dev, pipe)) {
- i915_pageflip_stall_check(dev, pipe);
- intel_finish_page_flip(dev, pipe);
+ if (iir flip[pipe]) {
+ intel_prepare_page_flip(dev, pipe);
+
+ if ((I915_READ(ISR) flip[pipe]) == 0)
{
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[pipe];
+ }
+ }
}
if (pipe_stats[pipe] PIPE_LEGACY_BLC_EVENT_STATUS)
--
1.7.12.4
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Re: [Intel-gfx] [PATCH] drm: Don't set the plane-fb to NULL on successfull set_plane
On Fri, Feb 15, 2013 at 09:21:37PM +0100, Daniel Vetter wrote:
We need to clear the local variable to get the refcounting right
(since the reference drm_mode_setplane holds is transferred to the
plane-fb pointer). But should be done _after_ we update the pointer.
Breakage introduced in
commit 6c2a75325c800de286166c693e0cd33c3a1c5ec8
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Tue Dec 11 00:59:24 2012 +0100
drm: refcounting for sprite framebuffers
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Rob Clark r...@ti.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/drm_crtc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 826a5ca..1960418 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1982,9 +1982,9 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
plane_req-src_w, plane_req-src_h);
if (!ret) {
old_fb = plane-fb;
- fb = NULL;
plane-crtc = crtc;
plane-fb = fb;
+ fb = NULL;
}
drm_modeset_unlock_all(dev);
Ugh... and again I sent the same patch because I didn't look properly
and missed yours.
Reviewed-by: Thierry Reding thierry.red...@avionic-design.de
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Re: [Intel-gfx] Blog regarding i915 changes in kernel 3.9
On Tue, 2013-02-19 at 11:35 +0100, Daniel Vetter wrote: On Tue, Feb 19, 2013 at 7:29 AM, William Brown will...@firstyear.id.au wrote: I recently read your blog article at : http://blog.ffwll.ch/2013/02/neat-drmi915-stuff-for-39.html If you don't mind I have two questions regarding these changes. Do any of these fixes correct the black screen on dual gpu laptops when switching to the i915? There are billions of ways you can end up with a black screen, so can't tell. Do these changes affect the issue where on a dual gpu laptop both the i915 and discrete gpu are powered on at boot? If these issues are new to you, Would you mind sending me some hints on how to track them down and potentially correct them? Please file a bug report against DRI - DRM(Intel) on bugs.freedesktop.org with a clear description of how things fail and all the usual details about your hw. Also, please _always_ cc and appropriate mailing list when poking your maintainer, he might be lazy, busy, drunken or on vacation ;-) Cheers, Daniel Thanks. I didn't know what the correct mailing list was, nor the right bug tracker. I have as such, made two bugs on that bugzilla describing the issues. Of course, I'm happy to provide more information and time debugging and solving it. -- Sincerely, William Brown pgp.mit.edu http://pgp.mit.edu:11371/pks/lookup?op=vindexsearch=0x3C0AC6DAB2F928A2 signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] VT switchless v3
On Mon, 18 Feb 2013 16:03:20 +0100 Daniel Vetter dan...@ffwll.ch wrote: On Fri, Feb 15, 2013 at 01:23:08PM -0800, Jesse Barnes wrote: A few more fixes from Daniel. So one thing that crossed my mind which we should at least quickly discuss: How is userspace supposed to notice the resume? On a lot of desktops (and even Androids) the normal thing seems to be to draw the screensave/lock after resume, which means that we'll show the desktop for a frame or so. Which is not too nice. Is userspace simply supposed to draw the screen lock before sleep, or does it need a helping hand from the kernel to fix this issue? Userspace initiates the suspend, so GNOME or whatever is supposed to lock things at that point. I've heard talk of a uevent or dbus thing to broadcast it as well, but I'm not sure of the status of that. IIRC Android already has a hack like this; they don't want the fbcon to ever be visible during usage... -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] VT switchless v3
On Mon, 18 Feb 2013 19:58:26 -0500 Kristian Høgsberg k...@bitplanet.net wrote: On Mon, Feb 18, 2013 at 10:03 AM, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Feb 15, 2013 at 01:23:08PM -0800, Jesse Barnes wrote: A few more fixes from Daniel. So one thing that crossed my mind which we should at least quickly discuss: How is userspace supposed to notice the resume? On a lot of desktops (and even Androids) the normal thing seems to be to draw the screensave/lock after resume, which means that we'll show the desktop for a frame or so. Which is not too nice. Is userspace simply supposed to draw the screen lock before sleep, or does it need a helping hand from the kernel to fix this issue? Yup, I second that and I've mentioned it to Jesse before. VTs in KD_GRAPHICS mode are already responsible for re-setting their mode when you switch back to them after having switched away. Surely they should have the option to handle setting mode and potentially present a lockscreen when coming back from resume. In case of weston, we have the option to handle this very well, since the compositor can launch prepare a lock screen (potentailly launching a helper client to do that) and just not set a mode or dpms on until the UI is ready. Rob Bradford mentioned that GNOME had a bug here where on suspend the lock screen daemon would be notified, but the suspend would happen too quickly for it to actually receive the notification and take action. So when you resumed, you'd see your desktop until the daemon was re-run and then the lock screen would appear. That's been fixed apparently, but it illustrates that you don't want to do things on resume, you want to do them on suspend like Kristian points out. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/6] drm/i915: add sprite restore function v2
On Mon, 18 Feb 2013 19:19:55 +0200
Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Fri, Feb 15, 2013 at 01:23:10PM -0800, Jesse Barnes wrote:
To be used to restore sprite state on resume.
v2: move sprite tracking bits up so we don't track modified sprite state
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_drv.h|5 +
drivers/gpu/drm/i915/intel_sprite.c | 23 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 005a91f..1b548e0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -247,6 +247,10 @@ struct intel_plane {
bool can_scale;
int max_downscale;
u32 lut_r[1024], lut_g[1024], lut_b[1024];
+ int crtc_x, crtc_y;
+ unsigned int crtc_w, crtc_h;
+ uint32_t x, y;
Can we call just them src_x/src_y instead?
+ uint32_t src_w, src_h;
void (*update_plane)(struct drm_plane *plane,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
@@ -532,6 +536,7 @@ extern bool intel_encoder_check_is_cloned(struct
intel_encoder *encoder);
extern void intel_connector_dpms(struct drm_connector *, int mode);
extern bool intel_connector_get_hw_state(struct intel_connector
*connector);
extern void intel_modeset_check_state(struct drm_device *dev);
+extern void intel_plane_restore(struct drm_plane *plane);
static inline struct intel_encoder *intel_attached_encoder(struct
drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 03cfd62..ca171af 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -438,6 +438,15 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
old_obj = intel_plane-obj;
+ intel_plane-crtc_x = crtc_x;
+ intel_plane-crtc_y = crtc_y;
+ intel_plane-crtc_w = crtc_w;
+ intel_plane-crtc_h = crtc_h;
+ intel_plane-x = x;
+ intel_plane-y = y;
x and y are not fixed point numbers. They just contain the integer parts
of src_x and src_y. So you need to use src_x and src_y here instead.
Oops, thanks. Will fix and use the suggested terminology to avoid
future confusion.
--
Jesse Barnes, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: clarify confusion between SDVO and HDMI registers
Hi
2013/2/19 Daniel Vetter dan...@ffwll.ch:
On Mon, Feb 18, 2013 at 07:00:27PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Some HDMI registers can be used for SDVO, so saying HDMIB should be
the same as saying SDVOB for a given HW generation. This was not
true and led to confusions and even a regression.
Previously we had:
- SDVO{B,C} defined as the Gen3+ registers
- HDMI{B,C,D} and PCH_SDVOB defined as the PCH registers
But now:
- SDVO{B,C} became GEN3_SDVO{B,C} on SDVO code
- SDVO{B,C} became GEN4_HDMI{B,C} on HDMI code
- HDMI{B,C,D} became PCH_HDMI{B,C,D}
- PCH_SDVOB is still the same thing
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
I think we still have a bit of ugly left in here, especially that the
register bit definitions are splattered all over irks me a bit. What about
moving the HDMI stuff up to the SDVO definitions and giving the HDMI bits
consisten HDMI_ prefixes? Imo there's no point in adding duplicate
#defines for all the SDVO_ bits we use in intel_hdmi.c ...
I agree, there's more to clean up. I thought about amending your
suggestions to this patch, but I don't think this will be a good idea,
so I will send 3 additional patches on top of this one. Feel free to
merge them as a single patch if you want.
-Daniel
---
drivers/gpu/drm/i915/i915_reg.h | 19 ---
drivers/gpu/drm/i915/intel_display.c | 42
++
drivers/gpu/drm/i915/intel_sdvo.c| 22 +-
3 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 9e5844b..cd31af2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1680,8 +1680,9 @@
#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 6)
/* SDVO port control */
-#define SDVOB0x61140
-#define SDVOC0x61160
+#define GEN3_SDVOB 0x61140
+#define GEN3_SDVOC 0x61160
+#define PCH_SDVOB0xe1140
#define SDVO_ENABLE(1 31)
#define SDVO_PIPE_B_SELECT (1 30)
#define SDVO_STALL_SELECT (1 29)
@@ -3979,8 +3980,12 @@
#define FDI_PLL_CTL_1 0xfe000
#define FDI_PLL_CTL_2 0xfe004
-/* or SDVOB */
-#define HDMIB 0xe1140
+/* The same register may be used for SDVO or HDMI */
+#define GEN4_HDMIB GEN3_SDVOB
+#define GEN4_HDMIC GEN3_SDVOC
+#define PCH_HDMIBPCH_SDVOB
+#define PCH_HDMIC0xe1150
+#define PCH_HDMID0xe1160
#define PORT_ENABLE(1 31)
#define TRANSCODER(pipe) ((pipe) 30)
#define TRANSCODER_CPT(pipe) ((pipe) 29)
@@ -4001,12 +4006,6 @@
#define HSYNC_ACTIVE_HIGH (1 3)
#define PORT_DETECTED (1 2)
-/* PCH SDVOB multiplex with HDMIB */
-#define PCH_SDVOBHDMIB
-
-#define HDMIC 0xe1150
-#define HDMID 0xe1160
-
#define PCH_LVDS 0xe1180
#define LVDS_DETECTED (1 1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6eb3882..744db70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1419,9 +1419,9 @@ static void assert_pch_ports_disabled(struct
drm_i915_private *dev_priv,
PCH LVDS enabled on transcoder %c, should be disabled\n,
pipe_name(pipe));
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}
/**
@@ -8323,20 +8323,20 @@ static void intel_setup_outputs(struct drm_device
*dev)
if (has_edp_a(dev))
intel_dp_init(dev, DP_A, PORT_A);
- if (I915_READ(HDMIB) PORT_DETECTED) {
+ if (I915_READ(PCH_HDMIB) PORT_DETECTED) {
/* PCH SDVOB multiplex with HDMIB */
found = intel_sdvo_init(dev, PCH_SDVOB, true);
if (!found)
- intel_hdmi_init(dev, HDMIB, PORT_B);
+ intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
if (!found (I915_READ(PCH_DP_B) DP_DETECTED))
intel_dp_init(dev, PCH_DP_B, PORT_B);
}
- if (I915_READ(HDMIC) PORT_DETECTED)
- intel_hdmi_init(dev, HDMIC, PORT_C);
+ if (I915_READ(PCH_HDMIC) PORT_DETECTED)
+ intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
- if (!dpd_is_edp I915_READ(HDMID) PORT_DETECTED)
- intel_hdmi_init(dev, HDMID, PORT_D);
+ if (!dpd_is_edp
[Intel-gfx] [PATCH 9/8] drm/i915: unify the definitions of the HDMI/SDVO register
From: Paulo Zanoni paulo.r.zan...@intel.com Since they're all the same register, leave all the #defines at the same place, organized by Gen and also specify which bits are used by only a specific port or encoding. Also remove a few unused duplicates and adjust indentation. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 111 +++ 1 file changed, 55 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cd31af2..f35b28c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1679,43 +1679,68 @@ #define SDVOC_HOTPLUG_INT_STATUS_I915(1 7) #define SDVOB_HOTPLUG_INT_STATUS_I915(1 6) -/* SDVO port control */ -#define GEN3_SDVOB 0x61140 -#define GEN3_SDVOC 0x61160 -#define PCH_SDVOB 0xe1140 -#define SDVO_ENABLE (1 31) -#define SDVO_PIPE_B_SELECT (1 30) -#define SDVO_STALL_SELECT(1 29) -#define SDVO_INTERRUPT_ENABLE(1 26) +/* SDVO and HDMI port control. + * The same register may be used for SDVO or HDMI */ +#define GEN3_SDVOB 0x61140 +#define GEN3_SDVOC 0x61160 +#define GEN4_HDMIB GEN3_SDVOB +#define GEN4_HDMIC GEN3_SDVOC +#define PCH_SDVOB 0xe1140 +#define PCH_HDMIB PCH_SDVOB +#define PCH_HDMIC 0xe1150 +#define PCH_HDMID 0xe1160 + +/* Gen 3 SDVO bits: */ +#define SDVO_ENABLE (1 31) +#define SDVO_PIPE_B_SELECT (1 30) +#define SDVO_STALL_SELECT(1 29) +#define SDVO_INTERRUPT_ENABLE(1 26) /** * 915G/GM SDVO pixel multiplier. - * * Programmed value is multiplier - 1, up to 5x. - * * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ -#define SDVO_PORT_MULTIPLY_MASK (7 23) +#define SDVO_PORT_MULTIPLY_MASK (7 23) #define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 19) -#define SDVO_PHASE_SELECT_DEFAULT(6 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 18) -#define SDVOC_GANG_MODE (1 16) -#define SDVO_ENCODING_SDVO (0x0 10) -#define SDVO_ENCODING_HDMI (0x2 10) -/** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 9) -#define SDVO_COLOR_RANGE_16_235 (1 8) -#define SDVO_BORDER_ENABLE (1 7) -#define SDVO_AUDIO_ENABLE(1 6) -/** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 4) -/** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 3) -#define SDVOB_PCIE_CONCURRENCY (1 3) -#define SDVO_DETECTED(1 2) +#define SDVO_PHASE_SELECT_MASK (15 19) +#define SDVO_PHASE_SELECT_DEFAULT(6 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 18) +#define SDVOC_GANG_MODE (1 16) /* Port C only */ +#define SDVO_BORDER_ENABLE (1 7) /* SDVO only */ +#define SDVOB_PCIE_CONCURRENCY (1 3) /* Port B only */ +#define SDVO_DETECTED(1 2) /* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 17) | (1 16) | (1 14) | (1 26)) -#define SDVOC_PRESERVE_MASK ((1 17) | (1 26)) +#define SDVOB_PRESERVE_MASK ((1 17) | (1 16) | (1 14) | \ + SDVO_INTERRUPT_ENABLE) +#define SDVOC_PRESERVE_MASK ((1 17) | SDVO_INTERRUPT_ENABLE) + +/* Gen 4 SDVO/HDMI bits: */ +#define COLOR_FORMAT_8bpc(0 26) +#define SDVO_ENCODING_SDVO (0 10) +#define SDVO_ENCODING_HDMI (2 10) +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 9) /* HDMI only */ +#define SDVO_COLOR_RANGE_16_235 (1 8) /* HDMI only */ +#define SDVO_AUDIO_ENABLE(1 6) +/* VSYNC/HSYNC bits new with 965, default is to be set */ +#define SDVO_VSYNC_ACTIVE_HIGH (1 4) +#define SDVO_HSYNC_ACTIVE_HIGH (1 3) + +/* Gen 5 (IBX) SDVO/HDMI bits: */ +#define COLOR_FORMAT_12bpc (3 26) /* HDMI only */ +#define SDVOB_HOTPLUG_ENABLE (1 23) /* SDVO only */ + +/* Gen 6 (CPT) SDVO/HDMI bits: */ +#define TRANSCODER_CPT(pipe) ((pipe) 29) +#define TRANSCODER_MASK_CPT (3 29) + +/* Repeated but still used bits: */ +#define PORT_ENABLE (1 31) +#define TRANSCODER(pipe) ((pipe) 30) +#define TRANSCODER_MASK (1 30) +#define HDMI_MODE_SELECT (1 9) +#define DVI_MODE_SELECT (0 9) +#define PORT_DETECTED(1 2) + /* DVO port control */ #define DVOA 0x61120 @@ -3980,32 +4005,6 @@ #define
[Intel-gfx] [PATCH 10/8] drm/i915: remove duplicated SDVO/HDMI bit definitions
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 17 ++---
drivers/gpu/drm/i915/intel_display.c | 18 +-
drivers/gpu/drm/i915/intel_hdmi.c| 23 +--
drivers/gpu/drm/i915/intel_sdvo.c| 16 +---
4 files changed, 29 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f35b28c..aad8eee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1692,6 +1692,8 @@
/* Gen 3 SDVO bits: */
#define SDVO_ENABLE (1 31)
+#define SDVO_PIPE_SEL(pipe) ((pipe) 30)
+#define SDVO_PIPE_SEL_MASK (1 30)
#define SDVO_PIPE_B_SELECT (1 30)
#define SDVO_STALL_SELECT(1 29)
#define SDVO_INTERRUPT_ENABLE(1 26)
@@ -1718,7 +1720,8 @@
#define COLOR_FORMAT_8bpc(0 26)
#define SDVO_ENCODING_SDVO (0 10)
#define SDVO_ENCODING_HDMI (2 10)
-#define SDVO_NULL_PACKETS_DURING_VSYNC (1 9) /* HDMI only */
+#define HDMI_MODE_SELECT_HDMI(1 9) /* HDMI only */
+#define HDMI_MODE_SELECT_DVI (0 9) /* HDMI only */
#define SDVO_COLOR_RANGE_16_235 (1 8) /* HDMI only */
#define SDVO_AUDIO_ENABLE(1 6)
/* VSYNC/HSYNC bits new with 965, default is to be set */
@@ -1730,16 +1733,8 @@
#define SDVOB_HOTPLUG_ENABLE (1 23) /* SDVO only */
/* Gen 6 (CPT) SDVO/HDMI bits: */
-#define TRANSCODER_CPT(pipe) ((pipe) 29)
-#define TRANSCODER_MASK_CPT (3 29)
-
-/* Repeated but still used bits: */
-#define PORT_ENABLE (1 31)
-#define TRANSCODER(pipe) ((pipe) 30)
-#define TRANSCODER_MASK (1 30)
-#define HDMI_MODE_SELECT (1 9)
-#define DVI_MODE_SELECT (0 9)
-#define PORT_DETECTED(1 2)
+#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) 29)
+#define SDVO_PIPE_SEL_MASK_CPT (3 29)
/* DVO port control */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d32ac72..b381fcd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1327,14 +1327,14 @@ static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv,
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
enum pipe pipe, u32 val)
{
- if ((val PORT_ENABLE) == 0)
+ if ((val SDVO_ENABLE) == 0)
return false;
if (HAS_PCH_CPT(dev_priv-dev)) {
- if ((val PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
+ if ((val SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
return false;
} else {
- if ((val TRANSCODER_MASK) != TRANSCODER(pipe))
+ if ((val SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
return false;
}
return true;
@@ -1392,7 +1392,7 @@ static void assert_pch_hdmi_disabled(struct
drm_i915_private *dev_priv,
PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n,
reg, pipe_name(pipe));
- WARN(HAS_PCH_IBX(dev_priv-dev) (val PORT_ENABLE) == 0
+ WARN(HAS_PCH_IBX(dev_priv-dev) (val SDVO_ENABLE) == 0
(val SDVO_PIPE_B_SELECT),
IBX PCH hdmi port still using transcoder B\n);
}
@@ -8357,7 +8357,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (has_edp_a(dev))
intel_dp_init(dev, DP_A, PORT_A);
- if (I915_READ(PCH_HDMIB) PORT_DETECTED) {
+ if (I915_READ(PCH_HDMIB) SDVO_DETECTED) {
/* PCH SDVOB multiplex with HDMIB */
found = intel_sdvo_init(dev, PCH_SDVOB, true);
if (!found)
@@ -8366,10 +8366,10 @@ static void intel_setup_outputs(struct drm_device *dev)
intel_dp_init(dev, PCH_DP_B, PORT_B);
}
- if (I915_READ(PCH_HDMIC) PORT_DETECTED)
+ if (I915_READ(PCH_HDMIC) SDVO_DETECTED)
intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
- if (!dpd_is_edp I915_READ(PCH_HDMID) PORT_DETECTED)
+ if (!dpd_is_edp I915_READ(PCH_HDMID) SDVO_DETECTED)
intel_hdmi_init(dev, PCH_HDMID, PORT_D);
if (I915_READ(PCH_DP_C) DP_DETECTED)
@@ -8382,14 +8382,14 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(VLV_DISPLAY_BASE + DP_C)
Re: [Intel-gfx] [PATCH 3/7] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
On Tue, Feb 19, 2013 at 04:13:35PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, if the BIOS did anything wrong, our first I915_{WRITE,READ}
will give us unclaimed register messages.
V2: Even earlier.
V3: Move it to intel_early_sanitize_regs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58897
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Slurped in the first 3 patches of this series, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [PATCH 1/6] drm/i915: don't restore LVDS enable state blindly v2
We still rely on a few LVDS bits, but restoring the enable bit can cause
trouble at this point, so don't.
v2: use the right mask to prevent restore (Daniel)
conditionalize on KMS support (Denial)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_suspend.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 2135f21..c1e02b0 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -255,6 +255,7 @@ static void i915_save_display(struct drm_device *dev)
static void i915_restore_display(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 mask = 0x;
/* Display arbitration */
if (INTEL_INFO(dev)-gen = 4)
@@ -267,10 +268,13 @@ static void i915_restore_display(struct drm_device *dev)
if (INTEL_INFO(dev)-gen = 4 !HAS_PCH_SPLIT(dev))
I915_WRITE(BLC_PWM_CTL2, dev_priv-regfile.saveBLC_PWM_CTL2);
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ mask = ~LVDS_PORT_EN;
+
if (HAS_PCH_SPLIT(dev)) {
- I915_WRITE(PCH_LVDS, dev_priv-regfile.saveLVDS);
+ I915_WRITE(PCH_LVDS, dev_priv-regfile.saveLVDS mask);
} else if (IS_MOBILE(dev) !IS_I830(dev))
- I915_WRITE(LVDS, dev_priv-regfile.saveLVDS);
+ I915_WRITE(LVDS, dev_priv-regfile.saveLVDS mask);
if (!IS_I830(dev) !IS_845G(dev) !HAS_PCH_SPLIT(dev))
I915_WRITE(PFIT_CONTROL, dev_priv-regfile.savePFIT_CONTROL);
--
1.7.9.5
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[Intel-gfx] [PATCH 5/6] drm/i915: emit a hotplug event on resume
This will poke userspace into probing for configuration changes that may
have occurred across suspend/resume.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e76b038..1b37eec 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -551,6 +551,24 @@ void intel_console_resume(struct work_struct *work)
console_unlock();
}
+static void intel_resume_hotplug(struct drm_device *dev)
+{
+ struct drm_mode_config *mode_config = dev-mode_config;
+ struct intel_encoder *encoder;
+
+ mutex_lock(mode_config-mutex);
+ DRM_DEBUG_KMS(running encoder hotplug functions\n);
+
+ list_for_each_entry(encoder, mode_config-encoder_list, base.head)
+ if (encoder-hot_plug)
+ encoder-hot_plug(encoder);
+
+ mutex_unlock(mode_config-mutex);
+
+ /* Just fire off a uevent and let userspace tell us what to do */
+ drm_helper_hpd_irq_event(dev);
+}
+
static int __i915_drm_thaw(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -578,6 +596,8 @@ static int __i915_drm_thaw(struct drm_device *dev)
drm_modeset_lock_all(dev);
intel_modeset_setup_hw_state(dev, true);
drm_modeset_unlock_all(dev);
+
+ intel_resume_hotplug(dev);
}
intel_opregion_init(dev);
--
1.7.9.5
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[Intel-gfx] [PATCH 3/6] drm/i915: restore cursor and sprite state when forcing a config restore
Needed for VT switchless resume.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3e6dadf..2bf076e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8985,6 +8985,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev-dev_private;
enum pipe pipe;
u32 tmp;
+ struct drm_plane *plane;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
struct intel_connector *connector;
@@ -9081,8 +9082,20 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
if (force_restore) {
for_each_pipe(pipe) {
-
intel_crtc_restore_mode(dev_priv-pipe_to_crtc_mapping[pipe]);
+ struct drm_crtc *crtc =
+ dev_priv-pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ intel_crtc_restore_mode(crtc);
+ if (intel_crtc-cursor_visible) {
+ /* Force update for previously enabled cursor */
+ intel_crtc-cursor_visible = false;
+ intel_crtc_update_cursor(intel_crtc-base,
+true);
+ }
}
+ list_for_each_entry(plane, dev-mode_config.plane_list, head)
+ intel_plane_restore(plane);
i915_redisable_vga(dev);
} else {
--
1.7.9.5
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[Intel-gfx] [PATCH 4/6] drm/i915: enable VT switchless resume v2
With the other bits in place, we can do this safely. v2: disable backlight on suspend to prevent premature enablement on resume Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/i915_drv.c | 12 +--- drivers/gpu/drm/i915/intel_fb.c |3 +++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c5b8c81..e76b038 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -492,9 +492,10 @@ static int i915_drm_freeze(struct drm_device *dev) cancel_delayed_work_sync(dev_priv-rps.delayed_resume_work); - intel_modeset_disable(dev); - drm_irq_uninstall(dev); + + if (dev_priv-backlight) + intel_panel_disable_backlight(dev); } i915_save_state(dev); @@ -569,9 +570,14 @@ static int __i915_drm_thaw(struct drm_device *dev) mutex_unlock(dev-struct_mutex); intel_modeset_init_hw(dev); - intel_modeset_setup_hw_state(dev, false); + drm_irq_install(dev); intel_hpd_init(dev); + + /* Resume the modeset for every activated CRTC */ + drm_modeset_lock_all(dev); + intel_modeset_setup_hw_state(dev, true); + drm_modeset_unlock_all(dev); } intel_opregion_init(dev); diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 1c510da..987bc33 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -149,6 +149,9 @@ static int intelfb_create(struct intel_fbdev *ifbdev, } info-screen_size = size; + /* This driver doesn't need a VT switch to restore the mode on resume */ + info-skip_vt_switch = true; + // memset(info-screen_base, 0, size); drm_fb_helper_fill_fix(info, fb-pitches[0], fb-depth); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/6] drm/i915: remove disabled memset of framebuffer from intel_fb
Commented out and unneeded. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_fb.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 987bc33..f4e0b88 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -152,8 +152,6 @@ static int intelfb_create(struct intel_fbdev *ifbdev, /* This driver doesn't need a VT switch to restore the mode on resume */ info-skip_vt_switch = true; -// memset(info-screen_base, 0, size); - drm_fb_helper_fill_fix(info, fb-pitches[0], fb-depth); drm_fb_helper_fill_var(info, ifbdev-helper, sizes-fb_width, sizes-fb_height); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] VT switchless suspend/resume
Updated with the fix from Ville. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915: don't restore LVDS enable state blindly v2
Hi
2013/2/19 Jesse Barnes jbar...@virtuousgeek.org:
We still rely on a few LVDS bits, but restoring the enable bit can cause
trouble at this point, so don't.
v2: use the right mask to prevent restore (Daniel)
conditionalize on KMS support (Denial)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Briefly tested on SNB, and it still works.
---
drivers/gpu/drm/i915/i915_suspend.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 2135f21..c1e02b0 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -255,6 +255,7 @@ static void i915_save_display(struct drm_device *dev)
static void i915_restore_display(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 mask = 0x;
/* Display arbitration */
if (INTEL_INFO(dev)-gen = 4)
@@ -267,10 +268,13 @@ static void i915_restore_display(struct drm_device *dev)
if (INTEL_INFO(dev)-gen = 4 !HAS_PCH_SPLIT(dev))
I915_WRITE(BLC_PWM_CTL2, dev_priv-regfile.saveBLC_PWM_CTL2);
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ mask = ~LVDS_PORT_EN;
+
if (HAS_PCH_SPLIT(dev)) {
- I915_WRITE(PCH_LVDS, dev_priv-regfile.saveLVDS);
+ I915_WRITE(PCH_LVDS, dev_priv-regfile.saveLVDS mask);
} else if (IS_MOBILE(dev) !IS_I830(dev))
- I915_WRITE(LVDS, dev_priv-regfile.saveLVDS);
+ I915_WRITE(LVDS, dev_priv-regfile.saveLVDS mask);
if (!IS_I830(dev) !IS_845G(dev) !HAS_PCH_SPLIT(dev))
I915_WRITE(PFIT_CONTROL, dev_priv-regfile.savePFIT_CONTROL);
--
1.7.9.5
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--
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Re: [Intel-gfx] VT switchless suspend/resume
2013/2/19 Jesse Barnes jbar...@virtuousgeek.org: Updated with the fix from Ville. Very briefly tested on SNB (LVDS) and HSW (eDP + DP). Suspend-to-ram + resume still work. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/13] drm/i915: Introduce i915_gem_object_create_stolen_for_preallocated
From: Chris Wilson ch...@chris-wilson.co.uk
Wrap a preallocated region of stolen memory within an ordinary GEM
object, for example the BIOS framebuffer.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h|5 +++
drivers/gpu/drm/i915/i915_gem_stolen.c | 65
2 files changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e95337c..9b5478f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1717,6 +1717,11 @@ void i915_gem_stolen_cleanup_compression(struct
drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
+ u32 stolen_offset,
+ u32 gtt_offset,
+ u32 size);
void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
/* i915_gem_tiling.c */
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 9f01332..7f1735c 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -309,6 +309,71 @@ i915_gem_object_create_stolen(struct drm_device *dev, u32
size)
return NULL;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
+ u32 stolen_offset,
+ u32 gtt_offset,
+ u32 size)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_i915_gem_object *obj;
+ struct drm_mm_node *stolen;
+
+ if (dev_priv-mm.stolen_base == 0)
+ return NULL;
+
+ DRM_DEBUG_KMS(creating preallocated stolen object: stolen_offset=%x,
gtt_offset=%x, size=%x\n,
+ stolen_offset, gtt_offset, size);
+
+ /* KISS and expect everything to be page-aligned */
+ BUG_ON(stolen_offset 4095);
+ BUG_ON(gtt_offset 4095);
+ BUG_ON(size 4095);
+
+ if (WARN_ON(size == 0))
+ return NULL;
+
+ stolen = drm_mm_create_block(dev_priv-mm.stolen,
+stolen_offset, size,
+false);
+ if (stolen == NULL) {
+ DRM_DEBUG_KMS(failed to allocate stolen space\n);
+ return NULL;
+ }
+
+ obj = _i915_gem_object_create_stolen(dev, stolen);
+ if (obj == NULL) {
+ DRM_DEBUG_KMS(failed to allocate stolen object\n);
+ drm_mm_put_block(stolen);
+ return NULL;
+ }
+
+ /* To simplify the initialisation sequence between KMS and GTT,
+* we allow construction of the stolen object prior to
+* setting up the GTT space. The actual reservation will occur
+* later.
+*/
+ if (drm_mm_initialized(dev_priv-mm.gtt_space)) {
+ obj-gtt_space = drm_mm_create_block(dev_priv-mm.gtt_space,
+gtt_offset, size,
+false);
+ if (obj-gtt_space == NULL) {
+ DRM_DEBUG_KMS(failed to allocate stolen GTT space\n);
+ drm_gem_object_unreference(obj-base);
+ return NULL;
+ }
+ } else
+ obj-gtt_space = I915_GTT_RESERVED;
+
+ obj-gtt_offset = gtt_offset;
+ obj-has_global_gtt_mapping = 1;
+
+ list_add_tail(obj-gtt_list, dev_priv-mm.bound_list);
+ list_add_tail(obj-mm_list, dev_priv-mm.inactive_list);
+
+ return obj;
+}
+
void
i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
{
--
1.7.9.5
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[Intel-gfx] [PATCH 07/13] drm/i915: Only preserve the BIOS modes if they are the preferred ones
From: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c |9 +
drivers/gpu/drm/i915/intel_dp.c |1 +
drivers/gpu/drm/i915/intel_drv.h |8
drivers/gpu/drm/i915/intel_fb.c |9 +
drivers/gpu/drm/i915/intel_lvds.c|1 +
drivers/gpu/drm/i915/intel_panel.c | 10 ++
6 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e19b637..8ca47e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9270,6 +9270,15 @@ void intel_connector_attach_encoder(struct
intel_connector *connector,
encoder-base);
}
+bool intel_connector_get_preferred_mode(struct intel_connector *connector,
+ struct drm_display_mode *mode)
+{
+ if (!connector-get_preferred_mode)
+ return false;
+
+ return connector-get_preferred_mode(connector, mode);
+}
+
/*
* set vga decode state - true == enable VGA decode
*/
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e84d4dd..edd29d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2941,6 +2941,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
}
if (is_edp(intel_dp)) {
+ intel_connector-get_preferred_mode =
intel_connector_get_panel_fixed_mode;
intel_panel_init(intel_connector-panel, fixed_mode);
intel_panel_setup_backlight(connector);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index de8928b..5487285 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -204,6 +204,9 @@ struct intel_connector {
* and active (i.e. dpms ON state). */
bool (*get_hw_state)(struct intel_connector *);
+ bool (*get_preferred_mode)(struct intel_connector *,
+ struct drm_display_mode *);
+
/* Panel info for eDP and LVDS */
struct intel_panel panel;
@@ -509,6 +512,9 @@ extern int intel_panel_init(struct intel_panel *panel,
struct drm_display_mode *fixed_mode);
extern void intel_panel_fini(struct intel_panel *panel);
+extern bool intel_connector_get_panel_fixed_mode(struct intel_connector
*connector,
+struct drm_display_mode *mode);
+
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
extern void intel_pch_panel_fitting(struct drm_device *dev,
@@ -580,6 +586,8 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
struct intel_digital_port *port);
+extern bool intel_connector_get_preferred_mode(struct intel_connector
*connector,
+ struct drm_display_mode *mode);
extern void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 4ca2ee4..b60f277 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -237,6 +237,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
for (i = 0; i fb_helper-connector_count; i++) {
struct drm_connector *connector;
struct drm_encoder *encoder;
+ struct drm_display_mode mode;
connector = fb_helper-connector_info[i]-connector;
if (!enabled[i]) {
@@ -266,6 +267,14 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
return false;
}
+ if
(intel_connector_get_preferred_mode(to_intel_connector(connector), mode)
+ !drm_mode_equal(mode, encoder-crtc-mode)) {
+ DRM_DEBUG_KMS(connector %s on crtc %d has an
non-native mode, aborting\n,
+ drm_get_connector_name(connector),
+ encoder-crtc-base.id);
+ return false;
+ }
+
modes[i] = encoder-crtc-mode;
crtcs[i] = intel_fb_helper_crtc(fb_helper, encoder-crtc);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 400afa4..fa3a543 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1127,6 +1127,7 @@ bool intel_lvds_init(struct drm_device *dev)
[Intel-gfx] [PATCH 08/13] drm/i915: Validate that the framebuffer accommodates the current mode
From: Chris Wilson ch...@chris-wilson.co.uk
As we retrieve the mode from the BIOS it may be constructed using
different assumptions for its configuration, such as utilizing the panel
fitter in a conflicting manner. As such the associated framebuffer may be
insufficient for our setup, and so we need to reject the current mode
and install our own.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 38 +-
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8ca47e5..0a2279e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6450,27 +6450,40 @@ intel_framebuffer_create_for_mode(struct drm_device
*dev,
return intel_framebuffer_create(dev, mode_cmd, obj);
}
+static bool
+mode_fits_in_fb(struct drm_display_mode *mode,
+ struct drm_framebuffer *fb)
+{
+ struct drm_i915_gem_object *obj;
+ int min_pitch;
+
+ min_pitch = intel_framebuffer_pitch_for_width(mode-hdisplay,
+ fb-bits_per_pixel);
+ if (fb-pitches[0] min_pitch)
+ return false;
+
+ obj = to_intel_framebuffer(fb)-obj;
+ if (obj == NULL)
+ return false;
+
+ if (obj-base.size mode-vdisplay * fb-pitches[0])
+ return false;
+
+ return true;
+}
+
static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct drm_i915_gem_object *obj;
struct drm_framebuffer *fb;
if (dev_priv-fbdev == NULL)
return NULL;
- obj = dev_priv-fbdev-ifb.obj;
- if (obj == NULL)
- return NULL;
-
fb = dev_priv-fbdev-ifb.base;
- if (fb-pitches[0] intel_framebuffer_pitch_for_width(mode-hdisplay,
-
fb-bits_per_pixel))
- return NULL;
-
- if (obj-base.size mode-vdisplay * fb-pitches[0])
+ if (!mode_fits_in_fb(mode, fb))
return NULL;
return fb;
@@ -9127,6 +9140,11 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
if (crtc-base.enabled)
crtc-mode_valid = intel_crtc_get_mode(crtc-base,
crtc-base.mode);
+
+ if (crtc-base.fb
+ !mode_fits_in_fb(crtc-base.mode, crtc-base.fb))
+ crtc-mode_valid = false;
+
if (crtc-mode_valid) {
DRM_DEBUG_KMS(found active mode: );
drm_mode_debug_printmodeline(crtc-base.mode);
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/13] drm/i915: Split the framebuffer_info creation into a separate routine
From: Chris Wilson ch...@chris-wilson.co.uk
This will be shared with wrapping the BIOS framebuffer into the fbdev
later. In the meantime, we can tidy the code slightly and improve the
error path handling.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c |7 --
drivers/gpu/drm/i915/intel_drv.h |7 ++
drivers/gpu/drm/i915/intel_fb.c | 154 ++
3 files changed, 91 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f20555e..dc58b01 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6422,13 +6422,6 @@ intel_framebuffer_create(struct drm_device *dev,
}
static u32
-intel_framebuffer_pitch_for_width(int width, int bpp)
-{
- u32 pitch = DIV_ROUND_UP(width * bpp, 8);
- return ALIGN(pitch, 64);
-}
-
-static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
u32 pitch = intel_framebuffer_pitch_for_width(mode-hdisplay, bpp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 005a91f..f93653d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -134,6 +134,13 @@ struct intel_framebuffer {
struct drm_i915_gem_object *obj;
};
+inline static u32
+intel_framebuffer_pitch_for_width(int width, int bpp)
+{
+ u32 pitch = DIV_ROUND_UP(width * bpp, 8);
+ return ALIGN(pitch, 64);
+}
+
struct intel_fbdev {
struct drm_fb_helper helper;
struct intel_framebuffer ifb;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 1c510da..5afc31b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -57,29 +57,96 @@ static struct fb_ops intelfb_ops = {
.fb_debug_leave = drm_fb_helper_debug_leave,
};
+static struct fb_info *intelfb_create_info(struct intel_fbdev *ifbdev)
+{
+ struct drm_framebuffer *fb = ifbdev-ifb.base;
+ struct drm_device *dev = fb-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct fb_info *info;
+ u32 gtt_offset, size;
+ int ret;
+
+ info = framebuffer_alloc(0, dev-pdev-dev);
+ if (!info)
+ return NULL;
+
+ info-par = ifbdev;
+ ifbdev-helper.fb = fb;
+ ifbdev-helper.fbdev = info;
+
+ strcpy(info-fix.id, inteldrmfb);
+
+ info-flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
+ info-fbops = intelfb_ops;
+
+ ret = fb_alloc_cmap(info-cmap, 256, 0);
+ if (ret)
+ goto err_info;
+
+ /* setup aperture base/size for vesafb takeover */
+ info-apertures = alloc_apertures(1);
+ if (!info-apertures)
+ goto err_cmap;
+
+ info-apertures-ranges[0].base = dev-mode_config.fb_base;
+ info-apertures-ranges[0].size = dev_priv-gtt.mappable_end;
+
+ gtt_offset = ifbdev-ifb.obj-gtt_offset;
+ size = ifbdev-ifb.obj-base.size;
+
+ info-fix.smem_start = dev-mode_config.fb_base + gtt_offset;
+ info-fix.smem_len = size;
+
+ info-screen_size = size;
+ info-screen_base = ioremap_wc(dev_priv-gtt.mappable_base + gtt_offset,
+ size);
+ if (!info-screen_base)
+ goto err_cmap;
+
+ /* If the object is shmemfs backed, it will have given us zeroed pages.
+* If the object is stolen however, it will be full of whatever
+* garbage was left in there.
+*/
+ if (ifbdev-ifb.obj-stolen)
+ memset_io(info-screen_base, 0, info-screen_size);
+
+ /* Use default scratch pixmap (info-pixmap.flags = FB_PIXMAP_SYSTEM) */
+
+ drm_fb_helper_fill_fix(info, fb-pitches[0], fb-depth);
+ drm_fb_helper_fill_var(info, ifbdev-helper, fb-width, fb-height);
+
+ return info;
+
+err_cmap:
+ if (info-cmap.len)
+ fb_dealloc_cmap(info-cmap);
+err_info:
+ framebuffer_release(info);
+ return NULL;
+}
+
static int intelfb_create(struct intel_fbdev *ifbdev,
struct drm_fb_helper_surface_size *sizes)
{
struct drm_device *dev = ifbdev-helper.dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct fb_info *info;
- struct drm_framebuffer *fb;
- struct drm_mode_fb_cmd2 mode_cmd = {};
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_i915_gem_object *obj;
- struct device *device = dev-pdev-dev;
+ struct fb_info *info;
int size, ret;
/* we don't do packed 24bpp */
if (sizes-surface_bpp == 24)
sizes-surface_bpp = 32;
- mode_cmd.width = sizes-surface_width;
+ mode_cmd.width = sizes-surface_width;
mode_cmd.height = sizes-surface_height;
- mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((sizes-surface_bpp + 7) /
-
[Intel-gfx] [PATCH 01/13] drm/i915: Skip modifying PCH DREF if not changing clock sources
From: Chris Wilson ch...@chris-wilson.co.uk
Modifying the clock sources (via the DREF control on the PCH) is a slow
multi-stage process as we need to let the clocks stabilise between each
stage. If we are not actually changing the clock sources, then we can
return early.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 83 +-
1 file changed, 61 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3e6dadf..f20555e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4758,7 +4758,7 @@ static void ironlake_init_pch_refclk(struct drm_device
*dev)
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_mode_config *mode_config = dev-mode_config;
struct intel_encoder *encoder;
- u32 temp;
+ u32 val, final;
bool has_lvds = false;
bool has_cpu_edp = false;
bool has_pch_edp = false;
@@ -4801,70 +4801,109 @@ static void ironlake_init_pch_refclk(struct drm_device
*dev)
* PCH B stepping, previous chipset stepping should be
* ignoring this setting.
*/
- temp = I915_READ(PCH_DREF_CONTROL);
+ val = I915_READ(PCH_DREF_CONTROL);
+
+ /* As we must carefully and slowly disable/enable each source in turn,
+* compute the final state we want first and check if we need to
+* make any changes at all.
+*/
+ final = val;
+ final = ~DREF_NONSPREAD_SOURCE_MASK;
+ if (has_ck505)
+ final |= DREF_NONSPREAD_CK505_ENABLE;
+ else
+ final |= DREF_NONSPREAD_SOURCE_ENABLE;
+
+ final = ~DREF_SSC_SOURCE_MASK;
+ final = ~DREF_CPU_SOURCE_OUTPUT_MASK;
+ final = ~DREF_SSC1_ENABLE;
+
+ if (has_panel) {
+ final |= DREF_SSC_SOURCE_ENABLE;
+
+ if (intel_panel_use_ssc(dev_priv) can_ssc)
+ final |= DREF_SSC1_ENABLE;
+
+ if (has_cpu_edp) {
+ if (intel_panel_use_ssc(dev_priv) can_ssc)
+ final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ else
+ final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ } else
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ } else {
+ final |= DREF_SSC_SOURCE_DISABLE;
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ }
+
+ if (final == val)
+ return;
+
/* Always enable nonspread source */
- temp = ~DREF_NONSPREAD_SOURCE_MASK;
+ val = ~DREF_NONSPREAD_SOURCE_MASK;
if (has_ck505)
- temp |= DREF_NONSPREAD_CK505_ENABLE;
+ val |= DREF_NONSPREAD_CK505_ENABLE;
else
- temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+ val |= DREF_NONSPREAD_SOURCE_ENABLE;
if (has_panel) {
- temp = ~DREF_SSC_SOURCE_MASK;
- temp |= DREF_SSC_SOURCE_ENABLE;
+ val = ~DREF_SSC_SOURCE_MASK;
+ val |= DREF_SSC_SOURCE_ENABLE;
/* SSC must be turned on before enabling the CPU output */
if (intel_panel_use_ssc(dev_priv) can_ssc) {
DRM_DEBUG_KMS(Using SSC on panel\n);
- temp |= DREF_SSC1_ENABLE;
+ val |= DREF_SSC1_ENABLE;
} else
- temp = ~DREF_SSC1_ENABLE;
+ val = ~DREF_SSC1_ENABLE;
/* Get SSC going before enabling the outputs */
- I915_WRITE(PCH_DREF_CONTROL, temp);
+ I915_WRITE(PCH_DREF_CONTROL, val);
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
- temp = ~DREF_CPU_SOURCE_OUTPUT_MASK;
+ val = ~DREF_CPU_SOURCE_OUTPUT_MASK;
/* Enable CPU source on CPU attached eDP */
if (has_cpu_edp) {
if (intel_panel_use_ssc(dev_priv) can_ssc) {
DRM_DEBUG_KMS(Using SSC on eDP\n);
- temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
}
else
- temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
} else
- temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
- I915_WRITE(PCH_DREF_CONTROL, temp);
+ I915_WRITE(PCH_DREF_CONTROL, val);
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
} else {
DRM_DEBUG_KMS(Disabling SSC entirely\n);
-
[Intel-gfx] [PATCH 06/13] drm/i915: Retrieve the current mode upon KMS takeover
From: Chris Wilson ch...@chris-wilson.co.uk
Read the current hardware state to retrieve the active mode and populate
our CRTC config if that mode matches our presumptions.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_crt.c | 27 +++-
drivers/gpu/drm/i915/intel_display.c | 119 ++
drivers/gpu/drm/i915/intel_dp.c | 22 +++
drivers/gpu/drm/i915/intel_drv.h |7 +-
drivers/gpu/drm/i915/intel_dvo.c | 36 ++
drivers/gpu/drm/i915/intel_hdmi.c| 22 +++
drivers/gpu/drm/i915/intel_lvds.c| 27 +++-
drivers/gpu/drm/i915/intel_sdvo.c| 23 +++
9 files changed, 242 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30cf7e6..8473db4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -283,6 +283,8 @@ struct drm_i915_display_funcs {
void (*update_linetime_wm)(struct drm_device *dev, int pipe,
struct drm_display_mode *mode);
void (*modeset_global_resources)(struct drm_device *dev);
+ bool (*crtc_get_mode)(struct drm_crtc *crtc,
+struct drm_display_mode *mode);
int (*crtc_mode_set)(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index cfc9687..f1d68e8 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -81,6 +81,27 @@ static bool intel_crt_get_hw_state(struct intel_encoder
*encoder,
return true;
}
+static unsigned intel_crt_get_mode_flags(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder-base.dev-dev_private;
+ struct intel_crt *crt = intel_encoder_to_crt(encoder);
+ u32 tmp, flags = 0;
+
+ tmp = I915_READ(crt-adpa_reg);
+
+ if (tmp ADPA_HSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
+
+ if (tmp ADPA_VSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+
+ return flags;
+}
+
static void intel_disable_crt(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder-base.dev-dev_private;
@@ -777,10 +798,12 @@ void intel_crt_init(struct drm_device *dev)
crt-base.disable = intel_disable_crt;
crt-base.enable = intel_enable_crt;
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev)) {
crt-base.get_hw_state = intel_ddi_get_hw_state;
- else
+ } else {
crt-base.get_hw_state = intel_crt_get_hw_state;
+ crt-base.get_mode_flags = intel_crt_get_mode_flags;
+ }
intel_connector-get_hw_state = intel_connector_get_hw_state;
drm_encoder_helper_add(crt-base.base, crt_encoder_funcs);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9793e66..e19b637 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6618,11 +6618,12 @@ void intel_release_load_detect_pipe(struct
drm_connector *connector,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+static int i9xx_crtc_clock_get(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc-pipe;
+ enum pipe pipe = intel_crtc-pipe;
u32 dpll = I915_READ(DPLL(pipe));
u32 fp;
intel_clock_t clock;
@@ -6705,35 +6706,84 @@ static int intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc)
}
/** Returns the currently programmed mode of the given pipe. */
-struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-struct drm_crtc *crtc)
+static bool i9xx_crtc_get_mode(struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
- struct drm_display_mode *mode;
- int htot = I915_READ(HTOTAL(cpu_transcoder));
- int hsync = I915_READ(HSYNC(cpu_transcoder));
- int vtot = I915_READ(VTOTAL(cpu_transcoder));
- int vsync = I915_READ(VSYNC(cpu_transcoder));
+ u32 tmp;
- mode =
[Intel-gfx] [PATCH 05/13] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon
From: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c |8 +-
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_drv.h |4 +
drivers/gpu/drm/i915/intel_fb.c | 305 +++---
5 files changed, 306 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4fa6beb..f2b7db7 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1273,6 +1273,7 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
static int i915_load_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ bool was_vga_enabled;
int ret;
ret = intel_parse_bios(dev);
@@ -1309,7 +1310,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
/* Important: The output setup functions called by modeset_init need
* working irqs for e.g. gmbus and dp aux transfers. */
- intel_modeset_init(dev);
+ intel_modeset_init(dev, was_vga_enabled);
+
+ /* Wrap existing BIOS mode configuration prior to GEM takeover */
+ if (!was_vga_enabled)
+ intel_fbdev_init_bios(dev);
ret = i915_gem_init(dev);
if (ret)
@@ -1323,6 +1328,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev-vblank_disable_allowed = 1;
+ /* Install a default KMS/GEM fbcon if we failed to wrap the BIOS fb */
ret = intel_fbdev_init(dev);
if (ret)
goto cleanup_gem;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b5478f..30cf7e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1811,7 +1811,7 @@ static inline void intel_unregister_dsm_handler(void) {
return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
-extern void intel_modeset_init(struct drm_device *dev);
+extern void intel_modeset_init(struct drm_device *dev, bool *was_vga_enabled);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dc58b01..9793e66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8735,12 +8735,17 @@ static void intel_init_quirks(struct drm_device *dev)
}
/* Disable the VGA plane that we never use */
-static void i915_disable_vga(struct drm_device *dev)
+static bool i915_disable_vga(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ bool was_enabled;
u8 sr1;
u32 vga_reg = i915_vgacntrl_reg(dev);
+ was_enabled = !(I915_READ(vga_reg) VGA_DISP_DISABLE);
+ DRM_DEBUG_KMS(VGA output is currently %s\n,
+ was_enabled ? enabled : disabled);
+
vga_get_uninterruptible(dev-pdev, VGA_RSRC_LEGACY_IO);
outb(SR01, VGA_SR_INDEX);
sr1 = inb(VGA_SR_DATA);
@@ -8750,6 +8755,8 @@ static void i915_disable_vga(struct drm_device *dev)
I915_WRITE(vga_reg, VGA_DISP_DISABLE);
POSTING_READ(vga_reg);
+
+ return was_enabled;
}
void intel_modeset_init_hw(struct drm_device *dev)
@@ -8765,7 +8772,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(dev-struct_mutex);
}
-void intel_modeset_init(struct drm_device *dev)
+void intel_modeset_init(struct drm_device *dev,
+ bool *was_vga_enabled)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int i, ret;
@@ -8812,7 +8820,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_pch_pll_init(dev);
/* Just disable it once at startup */
- i915_disable_vga(dev);
+ *was_vga_enabled = i915_disable_vga(dev);
intel_setup_outputs(dev);
/* Just in case the BIOS is doing something questionable. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f93653d..9cf794f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -146,6 +146,8 @@ struct intel_fbdev {
struct intel_framebuffer ifb;
struct list_head fbdev_list;
struct drm_display_mode *our_mode;
+ bool stolen;
+ int preferred_bpp;
};
struct intel_encoder {
@@ -212,6 +214,7 @@ struct intel_crtc {
enum plane plane;
enum transcoder cpu_transcoder;
u8 lut_r[256], lut_g[256], lut_b[256];
+ bool mode_valid;
/*
* Whether the crtc and the
Re: [Intel-gfx] [PATCH 1/6] drm/i915: don't restore LVDS enable state blindly v2
On Tue, Feb 19, 2013 at 05:39:49PM -0300, Paulo Zanoni wrote: Hi 2013/2/19 Jesse Barnes jbar...@virtuousgeek.org: We still rely on a few LVDS bits, but restoring the enable bit can cause trouble at this point, so don't. v2: use the right mask to prevent restore (Daniel) conditionalize on KMS support (Denial) Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com Briefly tested on SNB, and it still works. Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/13] drm/i915: treat no fb - fb as simple flip instead of full mode set
In case we don't get an fb from the BIOS, we may still be able to re-use
existing state and flip a new buffer.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 861af1a..b04d8b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7993,10 +7993,8 @@ intel_set_config_compute_mode_changes(struct
drm_mode_set *set,
/* We should be able to check here if the fb has the same properties
* and then just flip_or_move it */
if (set-crtc-fb != set-fb) {
- /* If we have no fb then treat it as a full mode set */
if (set-crtc-fb == NULL) {
- DRM_DEBUG_KMS(crtc has no fb, full mode set\n);
- config-mode_changed = true;
+ config-fb_changed = true;
} else if (set-fb == NULL) {
config-mode_changed = true;
} else if (set-fb-depth != set-crtc-fb-depth) {
--
1.7.9.5
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[Intel-gfx] [PATCH 13/13] drm/i915: check for non-native modes when inheriting a BIOS fb
If the mode is non-native using the panel fitter, don't try to re-use
the fb the BIOS allocated for it.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_fb.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index b60f277..9ff12aa 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -438,6 +438,18 @@ void intel_fbdev_init_bios(struct drm_device *dev)
width = ((val 16) 0xfff) + 1;
height = ((val 0) 0xfff) + 1;
+ /* Don't bother inheriting panel fitted modes */
+ val = I915_READ(HTOTAL(pipe));
+ if (((val 0x) + 1) != width) {
+ DRM_ERROR(BIOS fb not native width (%d vs %d),
skipping\n, width, (val 0x) + 1);
+ continue;
+ }
+ val = I915_READ(VTOTAL(pipe));
+ if (((val 0x) + 1) != height) {
+ DRM_ERROR(BIOS fb not native width (%d vs %d),
skipping\n, height, (val 0x) + 1);
+ continue;
+ }
+
DRM_DEBUG_KMS(Found active pipe [%d/%d]: size=%dx%d@%d,
offset=%x\n,
pipe, plane, width, height, bpp, offset);
--
1.7.9.5
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[Intel-gfx] [PATCH 10/13] drm/i915: check panel fit status at update_plane time
We may need to disable the panel when flipping to a new buffer, so check
the state here and zero it out if needed, otherwise leave it alone.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 595590c..91660b1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2304,6 +2304,25 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
if (crtc-fb)
intel_finish_fb(crtc-fb);
+ I915_WRITE(PIPESRC(intel_crtc-pipe),
+ ((crtc-mode.hdisplay - 1) 16) |
+ (crtc-mode.vdisplay - 1));
+ if (!dev_priv-pch_pf_size
+ (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
+intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
+ /* Force use of hard-coded filter coefficients
+* as some pre-programmed values are broken,
+* e.g. x201.
+*/
+ if (IS_IVYBRIDGE(dev))
+ I915_WRITE(PF_CTL(intel_crtc-pipe), 0);
+ else
+ I915_WRITE(PF_CTL(intel_crtc-pipe), 0);
+ I915_WRITE(PF_WIN_POS(intel_crtc-pipe), 0);
+ I915_WRITE(PF_WIN_SZ(intel_crtc-pipe), 0);
+ }
+
+
ret = dev_priv-display.update_plane(crtc, fb, x, y);
if (ret) {
intel_unpin_fb_obj(to_intel_framebuffer(fb)-obj);
--
1.7.9.5
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[Intel-gfx] [PATCH 11/13] drm/i915: add clock_get for ironlake+
Turns out it's easy to get the clock, though it may correspond to a
potential pfit mode. In that case, we may still be able to flip if
we can get the native mode params somehow.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91660b1..861af1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6771,6 +6771,27 @@ static bool i9xx_crtc_get_mode(struct drm_crtc *crtc,
return true;
}
+static int ironlake_crtc_clock_get(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc-dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ int clock;
+ u32 link_m;
+
+ /*
+* PCH platforms make this easy: we can just use the LINK_M1 reg.
+* Note: this may be the pixel clock for a fitted mode, in which
+* case it won't match the native mode clock. That means we won't be
+* able to do a simple flip in the fastboot case.
+*/
+ link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
+
+ clock = link_m;
+
+ return clock;
+}
+
static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode)
{
@@ -6797,12 +6818,11 @@ static bool ironlake_crtc_get_mode(struct drm_crtc
*crtc,
mode-vsync_start = (tmp 0x) + 1;
mode-vsync_end = ((tmp 0x) 16) + 1;
- //mode-clock = i9xx_crtc_clock_get(crtc);
- //mode-clock = 69300;
+ mode-clock = ironlake_crtc_clock_get(crtc);
drm_mode_set_name(mode);
- return false; /* XXX mode-clock unset */
+ return true;
}
static __maybe_unused bool no_crtc_get_mode(struct drm_crtc *crtc,
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915: Read the Base of Stolen Memory for 915gm
On Sun, Feb 10, 2013 at 01:37:52PM -0800, Ben Widawsky wrote:
On Sun, Feb 10, 2013 at 07:38:13PM +, Chris Wilson wrote:
Reading the cspec pays dividends once again, as I found the 'Base of
Stolen Memory' config register so that we can skip the fragile
computation from Top of Usable Draw and use the real value provided by
the BIOS.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Don't really want to dig out the doc, but I so prefer this to the
old way.
Acked-by: Ben Widawsky b...@bwidawsk.net
Hm, sloppy me didn't send out the patch merged spam. Anyway:
stolen + phys_object = kaboom
Dropped the patcha again.
-Daniel
---
drivers/gpu/drm/i915/i915_gem_stolen.c |9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 130d1db..7f1735c 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -72,13 +72,10 @@ static unsigned long i915_stolen_to_physical(struct
drm_device *dev)
} else if (INTEL_INFO(dev)-gen 3 || IS_G33(dev)) {
/* Read Graphics Base of Stolen Memory directly */
pci_read_config_dword(pdev, 0xA4, base);
-#if 0
} else if (IS_GEN3(dev)) {
- u8 val;
- /* Stolen is immediately below Top of Low Usable DRAM */
- pci_read_config_byte(pdev, 0x9c, val);
- base = val 3 27;
- base -= dev_priv-mm.gtt-stolen_size;
+ /* Read D2:F0 Base of Stolen Memory directly */
+ pci_read_config_dword(dev-pdev, 0x5c, base);
+#if 0
} else {
/* Stolen is immediately above Top of Memory */
base = max_low_pfn_mapped PAGE_SHIFT;
--
1.7.10.4
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--
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Increase the RC6p threshold.
On Tue, Jan 29, 2013 at 7:41 PM, Stéphane Marchesin marc...@chromium.orgwrote: This increases GEN6_RC6p_THRESHOLD from 10 to 15. For some reason this avoids the gen6_gt_check_fifodbg.isra warnings and associated GPU lockups, which makes my ivy bridge machine stable. Ping? Signed-off-by: Stéphane Marchesin marc...@chromium.org --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3280cff..dde0ded 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP, 0); I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); I915_WRITE(GEN6_RC6_THRESHOLD, 5); - I915_WRITE(GEN6_RC6p_THRESHOLD, 10); + I915_WRITE(GEN6_RC6p_THRESHOLD, 15); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ /* Check if we are enabling RC6 */ -- 1.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote: On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com The bit controlling whether PIPE_CONTROL DW/QW write targets the global GTT or PPGTT moved moved from DW 2 bit 2 to DW 1 bit 24 on IVB. I verified on IVB that the fix is in fact effective. Without the fix none of the scratch writes actually landed in the pipe control page. With the fix the writes show up correctly. v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Reviewed-by: Ben Widawsky b...@bwidawsk.net [snip] Reading the bspec again... do we want to set bit 21? -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Read the Base of Stolen Memory for 915gm
On Wed, Feb 20, 2013 at 12:28:00AM +0100, Daniel Vetter wrote: Hm, sloppy me didn't send out the patch merged spam. Anyway: stolen + phys_object = kaboom Nice reminder that the phys objects need to be upgraded to stolen. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Increase the RC6p threshold.
On Tue, 19 Feb 2013 15:53:56 -0800 Stéphane Marchesin marc...@chromium.org wrote: On Tue, Jan 29, 2013 at 7:41 PM, Stéphane Marchesin marc...@chromium.orgwrote: This increases GEN6_RC6p_THRESHOLD from 10 to 15. For some reason this avoids the gen6_gt_check_fifodbg.isra warnings and associated GPU lockups, which makes my ivy bridge machine stable. Ping? Seems ok to me. Ouping, can you measure any power difference between the two values? Thanks, -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
