[Intel-gfx] [PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT
On DevCPT, the control register for Transcoder DP Sync Polarity is
TRANS_DP_CTL, not DP_CTL.
Without this patch, Many OOP occur on CPT machine with DP monitor.The OOP
is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/intel_dp.c | 57 ---
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8708a0c..16c5803 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1324,20 +1324,57 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
struct intel_crtc_config *pipe_config)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
u32 tmp, flags = 0;
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum port port = dp_to_dig_port(intel_dp)->port;
- tmp = I915_READ(intel_dp->output_reg);
+ if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
+ tmp = I915_READ(intel_dp->output_reg);
+ if (tmp & DP_SYNC_HS_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
- if (tmp & DP_SYNC_HS_HIGH)
- flags |= DRM_MODE_FLAG_PHSYNC;
- else
- flags |= DRM_MODE_FLAG_NHSYNC;
+ if (tmp & DP_SYNC_VS_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+ } else {
+ u32 trans_sel = 0;
+ int i;
- if (tmp & DP_SYNC_VS_HIGH)
- flags |= DRM_MODE_FLAG_PVSYNC;
- else
- flags |= DRM_MODE_FLAG_NVSYNC;
+ switch (intel_dp->output_reg) {
+ case PCH_DP_B:
+ trans_sel = TRANS_DP_PORT_SEL_B;
+ break;
+ case PCH_DP_C:
+ trans_sel = TRANS_DP_PORT_SEL_C;
+ break;
+ case PCH_DP_D:
+ trans_sel = TRANS_DP_PORT_SEL_D;
+ break;
+ default:
+ break;
+ }
+
+ for_each_pipe(i) {
+ tmp = I915_READ(TRANS_DP_CTL(i));
+ if ((tmp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
+ if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
+
+ if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+
+ break;
+ }
+ }
+ }
pipe_config->adjusted_mode.flags |= flags;
}
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Adding global I915_PARAM for PSR ENABLED.
This global value allows userspace know when PSR is enabled.
This will allow userspace emit more busy_ioctl when doing directly copy_area
operations through scanout allowing forced psr exit.
v2: Check for PSR enabled instead of active. (by Chris Wilson)
Cc: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_dma.c | 4
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index adb319b..f924388 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1000,6 +1000,10 @@ static int i915_getparam(struct drm_device *dev, void
*data,
case I915_PARAM_HAS_EXEC_HANDLE_LUT:
value = 1;
break;
+ case I915_PARAM_PSR_ENABLED:
+ value = IS_HASWELL(dev) &&
+ I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 923ed7f..a5db73b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -310,6 +310,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_PINNED_BATCHES 24
#define I915_PARAM_HAS_EXEC_NO_RELOC25
#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
+#define I915_PARAM_PSR_ENABLED 27
typedef struct drm_i915_getparam {
int param;
--
1.8.1.4
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Re: [Intel-gfx] [PATCH 07/24] drm/i915: fold the no-irq check into intel_hpd_irq_handler
2013/6/12 Egbert Eich : > Daniel Vetter writes: > > The usual pattern for our sub-function irq_handlers is that they check > > for the no-irq case themselves. This results in more streamlined code > > in the upper irq handlers. > > > > Cc: Egbert Eich > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/i915_irq.c | 33 + > > 1 file changed, 17 insertions(+), 16 deletions(-) > > > > [reviewed code deleted] > > Reviewed-by: Egbert Eich Patches 4, 5, 6 and 7 (all reviewed by Egbert) are also Reviewed-by: Paulo Zanoni But I do have to notice they don't apply anymore due to s/hpd_status_i965/hpd_status_i915/ > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/11] drm/i915: Adding global I915_PARAM for PSR ACTIVE.
On Wed, Jun 26, 2013 at 06:55:20PM -0300, Rodrigo Vivi wrote: > This global value allows userspace know when PSR is enabled and active, > i.e. in SRD entry state. > This will allow userspace emit more busy_ioctl when doing directly copy_area > operations through scanout allowing forced psr exit. I don't want PSR_ACTIVE, but PSR_ENABLED. I'd rather check once after updating the mode configuration instead of everytime the ddx is about to sleep. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Linux 3.10-rc7
> > Can you please send me the log part when this starts? > > > > Thanks > > > > It rolled over and I don't have prior messages. I tried reproducing twice and > didn't see it again. I will try a few more times and see if I can get it to > happen > again. > > This is what I could save before dmesg rolled over: > > [ 78.709014] mei_me :00:16.0: reset: wrong host start response > [ 78.709016] mei_me :00:16.0: unexpected reset: dev_state = > RESETTING > [ 78.709029] mei_me :00:16.0: reset: unexpected enumeration > response hbm. > [ 78.709031] mei_me :00:16.0: unexpected reset: dev_state = > RESETTING > [ 78.709069] mei_me :00:16.0: reset: wrong host start response > So far I was able to positively reproduce it with 3.10-rc5 but not with 3.10-rc7 and above. There are 3 patches that went in to fix this issue 42f132f mei: me: clear interrupts on the resume path 2753ff5 mei: nfc: fix nfc device freeing 5e85b36 mei: init: Flush scheduled work before resetting the device Are you sure you have these 3 in? Thanks Tomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Initialize drm_crtc gamma ramp
As we initialize our own gamma LUT to sane values during initialisation,
we should also update the user visible gamma ramp to match our settings.
And before touching the storage for the user visible gamma ramp, we also
need to check for an allocation failure.
v2: set_gamma_size() returns an error code, not success/fail. Also
expand the 8bit LUT value to 16bit using bit replication.
v3: Just log the error and disable gamma user functionality if we fail
to allocate the ramp during initialisation.
Signed-off-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/intel_display.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5988bda..22bdf16 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8983,11 +8983,18 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
- drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
+ if (drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256))
+ DRM_ERROR("failed to allocate ramp for gamma, changing gamma
tables will be unavailable on CRTC:%d (pipe %d)\n", intel_crtc->base.base.id,
pipe);
+
for (i = 0; i < 256; i++) {
intel_crtc->lut_r[i] = i;
intel_crtc->lut_g[i] = i;
intel_crtc->lut_b[i] = i;
+ if (intel_crtc->base.gamma_size) {
+ intel_crtc->base.gamma_store[i + 0*256] = i << 8 | i;
+ intel_crtc->base.gamma_store[i + 1*256] = i << 8 | i;
+ intel_crtc->base.gamma_store[i + 2*256] = i << 8 | i;
+ }
}
/* Swap pipes & planes for FBC on pre-965 */
--
1.8.3.1
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[Intel-gfx] [PATCH 11/11] drm/i915: Hook PSR functionality
PSR must be enabled after transcoder and port are running.
And it is only available for HSW.
v2: move enable/disable to intel_ddi
v3: The spec suggests PSR should be disabled even before backlight (by pzanoni)
v4: also disabling and enabling whenever panel is disabled/enabled.
v5: make it last patch to avoid breaking whenever bisecting. So calling for
update and force exit came to this patch along with enable/disable calls.
CC: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 ++
4 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c68b90f..f2e135b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3786,6 +3786,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
goto unlock;
}
+ intel_edp_psr_force_exit(dev);
+
/* Count all active objects as busy, even if they are currently not used
* by the gpu. Users of this interface expect objects to eventually
* become non-busy without any further actions, therefore emit any
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 324211a..4211925 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1117,6 +1117,7 @@ static void intel_enable_ddi(struct intel_encoder
*intel_encoder)
intel_dp_stop_link_train(intel_dp);
ironlake_edp_backlight_on(intel_dp);
+ intel_edp_psr_enable(intel_dp);
}
if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
@@ -1147,6 +1148,7 @@ static void intel_disable_ddi(struct intel_encoder
*intel_encoder)
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_psr_disable(intel_dp);
ironlake_edp_backlight_off(intel_dp);
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6fafa43..5bbfed0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2236,6 +2236,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
intel_update_fbc(dev);
+ intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
intel_crtc_update_sarea_pos(crtc, x, y);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9986484..019b1ff 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1668,6 +1668,7 @@ static void intel_disable_dp(struct intel_encoder
*encoder)
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
ironlake_edp_panel_vdd_on(intel_dp);
+ intel_edp_psr_disable(intel_dp);
ironlake_edp_backlight_off(intel_dp);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
ironlake_edp_panel_off(intel_dp);
@@ -1708,6 +1709,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
intel_dp_complete_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
ironlake_edp_backlight_on(intel_dp);
+ intel_edp_psr_enable(intel_dp);
if (IS_VALLEYVIEW(dev)) {
struct intel_digital_port *dport =
--
1.8.1.4
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[Intel-gfx] [PATCH 03/11] drm/i915: split aux_clock_divider logic in a separated function for reuse.
Prep patch for reuse aux_clock_divider with EDP_PSR_AUX_CTL setup.
Reviewed-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 58 +++--
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 709e9d9..5cd276b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -271,29 +271,12 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool
has_aux_irq)
return status;
}
-static int
-intel_dp_aux_ch(struct intel_dp *intel_dp,
- uint8_t *send, int send_bytes,
- uint8_t *recv, int recv_size)
+static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
- uint32_t ch_data = ch_ctl + 4;
- int i, ret, recv_bytes;
- uint32_t status;
- uint32_t aux_clock_divider;
- int try, precharge;
- bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
- /* dp aux is extremely sensitive to irq latency, hence request the
-* lowest possible wakeup latency and so prevent the cpu from going into
-* deep sleep states.
-*/
- pm_qos_update_request(&dev_priv->pm_qos, 0);
-
- intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk,
* and would like to run at 2MHz. So, take the
* hrawclk value and divide by 2 and use that
@@ -302,23 +285,48 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (IS_VALLEYVIEW(dev)) {
- aux_clock_divider = 100;
+ return 100;
} else if (intel_dig_port->port == PORT_A) {
if (HAS_DDI(dev))
- aux_clock_divider = DIV_ROUND_CLOSEST(
+ return DIV_ROUND_CLOSEST(
intel_ddi_get_cdclk_freq(dev_priv), 2000);
else if (IS_GEN6(dev) || IS_GEN7(dev))
- aux_clock_divider = 200; /* SNB & IVB eDP input clock
at 400Mhz */
+ return 200; /* SNB & IVB eDP input clock at 400Mhz */
else
- aux_clock_divider = 225; /* eDP input clock at 450Mhz */
+ return 225; /* eDP input clock at 450Mhz */
} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
/* Workaround for non-ULT HSW */
- aux_clock_divider = 74;
+ return 74;
} else if (HAS_PCH_SPLIT(dev)) {
- aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+ return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
} else {
- aux_clock_divider = intel_hrawclk(dev) / 2;
+ return intel_hrawclk(dev) / 2;
}
+}
+
+static int
+intel_dp_aux_ch(struct intel_dp *intel_dp,
+ uint8_t *send, int send_bytes,
+ uint8_t *recv, int recv_size)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
+ uint32_t ch_data = ch_ctl + 4;
+ int i, ret, recv_bytes;
+ uint32_t status;
+ uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
+ int try, precharge;
+ bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
+
+ /* dp aux is extremely sensitive to irq latency, hence request the
+* lowest possible wakeup latency and so prevent the cpu from going into
+* deep sleep states.
+*/
+ pm_qos_update_request(&dev_priv->pm_qos, 0);
+
+ intel_dp_check_edp(intel_dp);
if (IS_GEN6(dev))
precharge = 3;
--
1.8.1.4
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[Intel-gfx] [PATCH 10/11] drm/i915: Add functions to force psr exit
PSR tracking engine in HSW doesn't detect automagically some directly copy area
operations through scanout so we will have to kick it manually and
reschedule it to come back to normal operation as soon as possible.
v2: Before PSR Hook. Don't force it when busy yet.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 59
drivers/gpu/drm/i915/intel_drv.h | 4 +++
3 files changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab5d597..cea646b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1838,6 +1838,7 @@
#define EDP_PSR_PERF_CNT_MASK0xff
#define EDP_PSR_DEBUG_CTL 0x64860
+#define EDP_PSR_DEBUG_FORCE_EXIT (3<<30)
#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91d3bd6..9986484 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1366,6 +1366,48 @@ static bool intel_edp_is_psr_enabled(struct drm_device
*dev)
return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
}
+static void intel_edp_psr_delayed_normal_work(struct work_struct *__work)
+{
+ struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
+struct intel_dp,
+edp_psr_delayed_normal_work);
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ mutex_lock(&intel_dp->psr_exit_mutex);
+ I915_WRITE(EDP_PSR_DEBUG_CTL, I915_READ(EDP_PSR_DEBUG_CTL) &
+ ~EDP_PSR_DEBUG_FORCE_EXIT);
+ mutex_unlock(&intel_dp->psr_exit_mutex);
+}
+
+void intel_edp_psr_force_exit(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+
+ if (!intel_edp_is_psr_enabled(dev))
+ return;
+
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
+ if (encoder->type == INTEL_OUTPUT_EDP)
+ intel_dp = enc_to_intel_dp(&encoder->base);
+
+ if (!intel_dp)
+ return;
+
+ if (WARN_ON(!intel_dp->psr_setup_done))
+ return;
+
+ mutex_lock(&intel_dp->psr_exit_mutex);
+ I915_WRITE(EDP_PSR_DEBUG_CTL, I915_READ(EDP_PSR_DEBUG_CTL) |
+ EDP_PSR_DEBUG_FORCE_EXIT);
+ mutex_unlock(&intel_dp->psr_exit_mutex);
+
+ schedule_delayed_work(&intel_dp->edp_psr_delayed_normal_work,
+ msecs_to_jiffies(100));
+}
+
void intel_edp_psr_write_vsc(struct intel_dp* intel_dp,
struct edp_vsc_psr *vsc_psr)
{
@@ -1400,6 +1442,18 @@ void intel_edp_psr_write_vsc(struct intel_dp* intel_dp,
POSTING_READ(ctl_reg);
}
+static void intel_edp_psr_setup(struct intel_dp *intel_dp)
+{
+ if (intel_dp->psr_setup_done)
+ return;
+
+ INIT_DELAYED_WORK(&intel_dp->edp_psr_delayed_normal_work,
+ intel_edp_psr_delayed_normal_work);
+ mutex_init(&intel_dp->psr_exit_mutex);
+
+ intel_dp->psr_setup_done = true;
+}
+
static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -1544,6 +1598,9 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
void intel_edp_psr_do_enable(struct intel_dp* intel_dp)
{
+ /* Setup PSR once */
+ intel_edp_psr_setup(intel_dp);
+
/* Enable PSR on the panel */
intel_edp_psr_enable_sink(intel_dp);
@@ -3413,6 +3470,8 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
error, port_name(port));
+ intel_dp->psr_setup_done = false;
+
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
i2c_del_adapter(&intel_dp->adapter);
if (is_edp(intel_dp)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 69224d2..b3d5a97 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -497,6 +497,9 @@ struct intel_dp {
int backlight_on_delay;
int backlight_off_delay;
struct delayed_work panel_vdd_work;
+ struct delayed_work edp_psr_delayed_normal_work;
+ struct mutex psr_exit_mutex;
+ bool psr_setup_done;
bool want_panel_vdd;
struct intel_connector *attached_connector;
};
@@ -843,5 +846,6 @@ extern bool intel_set_pch_fifo_underrun_reporting(struct
drm_device *dev,
extern
[Intel-gfx] [PATCH 09/11] drm/i915: Adding global I915_PARAM for PSR ACTIVE.
This global value allows userspace know when PSR is enabled and active,
i.e. in SRD entry state.
This will allow userspace emit more busy_ioctl when doing directly copy_area
operations through scanout allowing forced psr exit.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index adb319b..de20c4a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1000,6 +1000,9 @@ static int i915_getparam(struct drm_device *dev, void
*data,
case I915_PARAM_HAS_EXEC_HANDLE_LUT:
value = 1;
break;
+ case I915_PARAM_PSR_ACTIVE:
+ value = I915_READ(EDP_PSR_STATUS_CTL) &
EDP_PSR_STATUS_STATE_SRDENT;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 923ed7f..191a7fc 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -310,6 +310,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_PINNED_BATCHES 24
#define I915_PARAM_HAS_EXEC_NO_RELOC25
#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
+#define I915_PARAM_PSR_ACTIVE 27
typedef struct drm_i915_getparam {
int param;
--
1.8.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/11] drm/intel: add enable_psr module option
PSR is enabled by default but can be disabled.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 6 ++
4 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 85b7dd2..8b235c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1895,6 +1895,9 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
case PSR_NO_SINK:
seq_printf(m, "not supported by panel");
break;
+ case PSR_MODULE_PARAM:
+ seq_printf(m, "disabled by flag");
+ break;
case PSR_CRTC_NOT_ACTIVE:
seq_printf(m, "crtc not active");
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 062cbda..7920c6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -118,6 +118,10 @@ module_param_named(i915_enable_ppgtt, i915_enable_ppgtt,
int, 0600);
MODULE_PARM_DESC(i915_enable_ppgtt,
"Enable PPGTT (default: true)");
+int i915_enable_psr __read_mostly = 1;
+module_param_named(enable_psr, i915_enable_psr, int, 0600);
+MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
+
unsigned int i915_preliminary_hw_support __read_mostly = 0;
module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int,
0600);
MODULE_PARM_DESC(preliminary_hw_support,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f08c1d9..dda992a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -546,6 +546,7 @@ enum no_fbc_reason {
enum no_psr_reason {
PSR_NO_SOURCE, /* Not supported on platform */
PSR_NO_SINK, /* Not supported by panel */
+ PSR_MODULE_PARAM,
PSR_CRTC_NOT_ACTIVE,
PSR_PWR_WELL_ENABLED,
PSR_NOT_TILED,
@@ -1555,6 +1556,7 @@ extern int i915_enable_rc6 __read_mostly;
extern int i915_enable_fbc __read_mostly;
extern bool i915_enable_hangcheck __read_mostly;
extern int i915_enable_ppgtt __read_mostly;
+extern int i915_enable_psr __read_mostly;
extern unsigned int i915_preliminary_hw_support __read_mostly;
extern int i915_disable_power_well __read_mostly;
extern int i915_enable_ips __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ba018..91d3bd6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1500,6 +1500,12 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return false;
}
+ if (!i915_enable_psr) {
+ DRM_DEBUG_KMS("PSR disable by flag\n");
+ dev_priv->no_psr_reason = PSR_MODULE_PARAM;
+ return false;
+ }
+
if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
DRM_DEBUG_KMS("crtc not active for PSR\n");
dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
--
1.8.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/11] drm/i915: add update function to disable/enable-back PSR
Required function to disable PSR when going to console mode.
But also can be used whenever PSR mode entry conditions changed.
v2: Add it before PSR Hook. Update function not really been called yet.
---
drivers/gpu/drm/i915/intel_dp.c | 37 ++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 13b0155..91ba018 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1536,14 +1536,8 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return true;
}
-void intel_edp_psr_enable(struct intel_dp* intel_dp)
+void intel_edp_psr_do_enable(struct intel_dp* intel_dp)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
-
- if (!intel_edp_psr_match_conditions(intel_dp) ||
- intel_edp_is_psr_enabled(dev))
- return;
-
/* Enable PSR on the panel */
intel_edp_psr_enable_sink(intel_dp);
@@ -1551,6 +1545,15 @@ void intel_edp_psr_enable(struct intel_dp* intel_dp)
intel_edp_psr_enable_source(intel_dp);
}
+void intel_edp_psr_enable(struct intel_dp* intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+
+ if (intel_edp_psr_match_conditions(intel_dp) &&
+ !intel_edp_is_psr_enabled(dev))
+ intel_edp_psr_do_enable(intel_dp);
+}
+
void intel_edp_psr_disable(struct intel_dp* intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -1573,6 +1576,26 @@ void intel_edp_psr_disable(struct intel_dp* intel_dp)
intel_wait_for_vblank(dev, intel_crtc->pipe);
}
+void intel_edp_psr_update(struct drm_device *dev)
+{
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ intel_dp = enc_to_intel_dp(&encoder->base);
+
+ if (!is_edp_psr(intel_dp))
+ return;
+
+ if (!intel_edp_psr_match_conditions(intel_dp))
+ intel_edp_psr_disable(intel_dp);
+ else
+ if (!intel_edp_is_psr_enabled(dev))
+ intel_edp_psr_do_enable(intel_dp);
+ }
+}
+
static void intel_disable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f86d9c5..69224d2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -842,5 +842,6 @@ extern bool intel_set_pch_fifo_underrun_reporting(struct
drm_device *dev,
extern void intel_edp_psr_enable(struct intel_dp* intel_dp);
extern void intel_edp_psr_disable(struct intel_dp* intel_dp);
+extern void intel_edp_psr_update(struct drm_device *dev);
#endif /* __INTEL_DRV_H__ */
--
1.8.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/11] drm/i915: Match all PSR mode entry conditions before enabling it.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 39 ++---
drivers/gpu/drm/i915/i915_drv.h | 12 +++
drivers/gpu/drm/i915/intel_dp.c | 68 -
3 files changed, 114 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b81adf7..85b7dd2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1882,11 +1882,42 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 psrctl, psrstat, psrperf;
+ u32 psrstat, psrperf;
- psrctl = I915_READ(EDP_PSR_CTL);
- seq_printf(m, "PSR Enabled: %s\n",
- yesno(psrctl & EDP_PSR_ENABLE));
+ if (I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
+ seq_printf(m, "PSR enabled\n");
+ } else {
+ seq_printf(m, "PSR disabled: ");
+ switch (dev_priv->no_psr_reason) {
+ case PSR_NO_SOURCE:
+ seq_printf(m, "not supported on this platform");
+ break;
+ case PSR_NO_SINK:
+ seq_printf(m, "not supported by panel");
+ break;
+ case PSR_CRTC_NOT_ACTIVE:
+ seq_printf(m, "crtc not active");
+ break;
+ case PSR_PWR_WELL_ENABLED:
+ seq_printf(m, "power well enabled");
+ break;
+ case PSR_NOT_TILED:
+ seq_printf(m, "not tiled");
+ break;
+ case PSR_SPRITE_ENABLED:
+ seq_printf(m, "sprite enabled");
+ break;
+ case PSR_INTERLACED_ENABLED:
+ seq_printf(m, "interlaced enabled");
+ break;
+ case PSR_HSW_NOT_DDIA:
+ seq_printf(m, "HSW ties PSR to DDI A (eDP)");
+ break;
+ default:
+ seq_printf(m, "unknown reason");
+ }
+ seq_printf(m, "\n");
+ }
psrstat = I915_READ(EDP_PSR_STATUS_CTL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56bd82b..f08c1d9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -543,6 +543,17 @@ enum no_fbc_reason {
FBC_CHIP_DEFAULT, /* disabled by default on this chip */
};
+enum no_psr_reason {
+ PSR_NO_SOURCE, /* Not supported on platform */
+ PSR_NO_SINK, /* Not supported by panel */
+ PSR_CRTC_NOT_ACTIVE,
+ PSR_PWR_WELL_ENABLED,
+ PSR_NOT_TILED,
+ PSR_SPRITE_ENABLED,
+ PSR_INTERLACED_ENABLED,
+ PSR_HSW_NOT_DDIA,
+};
+
enum intel_pch {
PCH_NONE = 0, /* No PCH present */
PCH_IBX,/* Ibexpeak PCH */
@@ -1146,6 +1157,7 @@ typedef struct drm_i915_private {
struct i915_power_well power_well;
enum no_fbc_reason no_fbc_reason;
+ enum no_psr_reason no_psr_reason;
struct drm_mm_node *compressed_fb;
struct drm_mm_node *compressed_llb;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 144f216..13b0155 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1471,11 +1471,77 @@ static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp)
EDP_PSR_ENABLE);
}
+static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_crtc *crtc = dig_port->base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+
+ if (!IS_HASWELL(dev)) {
+ DRM_DEBUG_KMS("PSR not supported on this platform\n");
+ dev_priv->no_psr_reason = PSR_NO_SOURCE;
+ return false;
+ }
+
+ if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
+ (enc_to_dig_port(&intel_encoder->base)->port != PORT_A)) {
+ DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
+ dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
+ return false;
+ }
+
+ if (!is_edp_psr(intel_dp)) {
+ DRM_DEBUG_KMS("PSR not supported by this panel\n");
+ dev_priv->no_psr_reason = PSR_NO_SINK;
+ return false;
+ }
+
+ if (!intel_crtc->active || !cr
[Intel-gfx] [PATCH 05/11] drm/i915: Added debugfs support for PSR Status
Adding support for PSR Status, PSR entry counter and performance counters.
Heavily based on initial work from Shobhit.
v2: Fix PSR Status Link bits by Paulo Zanoni.
CC: Paulo Zanoni
Credits-by: Shobhit Kumar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 90 +
drivers/gpu/drm/i915/i915_reg.h | 24 ++
2 files changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a188624..b81adf7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1877,6 +1877,95 @@ static int i915_dpio_info(struct seq_file *m, void *data)
return 0;
}
+static int i915_edp_psr_status(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 psrctl, psrstat, psrperf;
+
+ psrctl = I915_READ(EDP_PSR_CTL);
+ seq_printf(m, "PSR Enabled: %s\n",
+ yesno(psrctl & EDP_PSR_ENABLE));
+
+ psrstat = I915_READ(EDP_PSR_STATUS_CTL);
+
+ seq_printf(m, "PSR Current State: ");
+ switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
+ case EDP_PSR_STATUS_STATE_IDLE:
+ seq_printf(m, "Reset state\n");
+ break;
+ case EDP_PSR_STATUS_STATE_SRDONACK:
+ seq_printf(m, "Wait for TG/Stream to send on frame of data
after SRD conditions are met\n");
+ break;
+ case EDP_PSR_STATUS_STATE_SRDENT:
+ seq_printf(m, "SRD entry\n");
+ break;
+ case EDP_PSR_STATUS_STATE_BUFOFF:
+ seq_printf(m, "Wait for buffer turn off\n");
+ break;
+ case EDP_PSR_STATUS_STATE_BUFON:
+ seq_printf(m, "Wait for buffer turn on\n");
+ break;
+ case EDP_PSR_STATUS_STATE_AUXACK:
+ seq_printf(m, "Wait for AUX to acknowledge on SRD
exit\n");
+ break;
+ case EDP_PSR_STATUS_STATE_SRDOFFACK:
+ seq_printf(m, "Wait for TG/Stream to acknowledge the
SRD VDM exit\n");
+ break;
+ default:
+ seq_printf(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "Link Status: ");
+ switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
+ case EDP_PSR_STATUS_LINK_FULL_OFF:
+ seq_printf(m, "Link is fully off\n");
+ break;
+ case EDP_PSR_STATUS_LINK_FULL_ON:
+ seq_printf(m, "Link is fully on\n");
+ break;
+ case EDP_PSR_STATUS_LINK_STANDBY:
+ seq_printf(m, "Link is in standby\n");
+ break;
+ default:
+ seq_printf(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "PSR Entry Count: %u\n",
+ psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
+ EDP_PSR_STATUS_COUNT_MASK);
+
+ seq_printf(m, "Max Sleep Timer Counter: %u\n",
+ psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
+ EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
+
+ seq_printf(m, "Had AUX error: %s\n",
+ yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
+
+ seq_printf(m, "Sending AUX: %s\n",
+ yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
+
+ seq_printf(m, "Sending Idle: %s\n",
+ yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
+
+ seq_printf(m, "Sending TP2 TP3: %s\n",
+ yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
+
+ seq_printf(m, "Sending TP1: %s\n",
+ yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
+
+ seq_printf(m, "Idle Count: %u\n",
+ psrstat & EDP_PSR_STATUS_IDLE_MASK);
+
+ psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
+ seq_printf(m, "Performance Counter: %u\n", psrperf);
+
+ return 0;
+}
+
static int
i915_wedged_get(void *data, u64 *val)
{
@@ -2306,6 +2395,7 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_swizzle_info", i915_swizzle_info, 0},
{"i915_ppgtt_info", i915_ppgtt_info, 0},
{"i915_dpio", i915_dpio_info, 0},
+ {"i915_edp_psr_status", i915_edp_psr_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index caf57d8..ab5d597 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1812,6 +1812,30 @@
#define EDP_PSR_STATUS_CTL 0x64840
#define EDP_PSR_STATUS_STATE_MASK(7<<29)
+#define EDP_PSR_STATUS_STATE_IDLE(0<<29)
+#define EDP_PSR_STATUS_STATE_SRDONACK(1<<29)
+#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
+#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29
[Intel-gfx] [PATCH 04/11] drm/i915: Enable/Disable PSR
Adding Enable and Disable PSR functionalities. This includes setting the
PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
enabling PSR in the sink via DPCD register and finally enabling PSR on
the host.
This patch is based on initial PSR code by Sateesh Kavuri and Kumar Shobhit
but in a different implementation.
v2: * moved functions around and changed its names.
* removed VSC DIP unset from disable.
* remove FBC wa.
* don't mask LSPS anymore.
* incorporate new crtc usage after a rebase.
v3: Make a clear separation between Sink (Panel) and Source (HW) enabling.
Credits-by: Sateesh Kavuri
Credits-by: Shobhit Kumar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 42 +++
drivers/gpu/drm/i915/intel_dp.c | 151 +++
drivers/gpu/drm/i915/intel_drv.h | 3 +
3 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 137be4c..caf57d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1777,6 +1777,47 @@
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+/* HSW eDP PSR registers */
+#define EDP_PSR_CTL0x64800
+#define EDP_PSR_ENABLE (1<<31)
+#define EDP_PSR_LINK_DISABLE (0<<27)
+#define EDP_PSR_LINK_STANDBY (1<<27)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
+#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
+#define EDP_PSR_SKIP_AUX_EXIT(1<<12)
+#define EDP_PSR_TP1_TP2_SEL (0<<11)
+#define EDP_PSR_TP1_TP3_SEL (1<<11)
+#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
+#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
+#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
+#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define EDP_PSR_TP1_TIME_500us (0<<4)
+#define EDP_PSR_TP1_TIME_100us (1<<4)
+#define EDP_PSR_TP1_TIME_2500us (2<<4)
+#define EDP_PSR_TP1_TIME_0us (3<<4)
+#define EDP_PSR_IDLE_FRAME_SHIFT 0
+
+#define EDP_PSR_AUX_CTL0x64810
+#define EDP_PSR_AUX_DATA1 0x64814
+#define EDP_PSR_DPCD_COMMAND 0x8006
+#define EDP_PSR_AUX_DATA2 0x64818
+#define EDP_PSR_DPCD_NORMAL_OPERATION(1<<24)
+#define EDP_PSR_AUX_DATA3 0x6481c
+#define EDP_PSR_AUX_DATA4 0x64820
+#define EDP_PSR_AUX_DATA5 0x64824
+
+#define EDP_PSR_STATUS_CTL 0x64840
+#define EDP_PSR_STATUS_STATE_MASK(7<<29)
+
+#define EDP_PSR_DEBUG_CTL 0x64860
+#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
+#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
+#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
+
/* VGA port control */
#define ADPA 0x61100
#define PCH_ADPA0xe1100
@@ -2046,6 +2087,7 @@
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each
byte
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
+#define VIDEO_DIP_VSC_DATA_SIZE 36
#define VIDEO_DIP_CTL 0x61170
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5cd276b..144f216 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1356,6 +1356,157 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
(intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED));
}
+static bool intel_edp_is_psr_enabled(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (!IS_HASWELL(dev))
+ return false;
+
+ return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
+}
+
+void intel_edp_psr_write_vsc(struct intel_dp* intel_dp,
+struct edp_vsc_psr *vsc_psr)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+
+ u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
+ u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
+ uint32_t *data = (uint32_t *) vsc_psr;
+ unsigned int i;
+ u32 val = I915_READ(ctl_reg);
+
+ /* As per eDP spec, wait for vblank to send SDP VSC packet */
+ intel_wait_for_vblank(
[Intel-gfx] [PATCH 02/11] drm/i915: Read the EDP DPCD and PSR Capability
From: Shobhit Kumar
v2: reuse of just created is_edp_psr and put it at right place.
v3: move is_edp_psr above intel_edp_disable
Reviewed-by: Paulo Zanoni
Reviewed-by: Jani Nikula
Signed-off-by: Shobhit Kumar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 13 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 24a44ed..709e9d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1342,6 +1342,12 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
pipe_config->adjusted_mode.flags |= flags;
}
+static bool is_edp_psr(struct intel_dp *intel_dp)
+{
+ return (is_edp(intel_dp) &&
+ (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED));
+}
+
static void intel_disable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2255,6 +2261,13 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
return false; /* DPCD not present */
+ /* Check if the panel supports PSR */
+ memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
+ intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
+ intel_dp->psr_dpcd,
+ sizeof(intel_dp->psr_dpcd));
+ if (is_edp_psr(intel_dp))
+ DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_PRESENT))
return true; /* native DP sink */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c5b463c..9b264ee 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -486,6 +486,7 @@ struct intel_dp {
uint8_t link_bw;
uint8_t lane_count;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
+ uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
struct i2c_adapter adapter;
struct i2c_algo_dp_aux_data algo;
--
1.8.1.4
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[Intel-gfx] [PATCH 01/11] drm: Added SDP and VSC structures for handling PSR for eDP
From: Shobhit Kumar
SDP header and SDP VSC header as per eDP 1.3 spec, section 3.5,
chapter "PSR Secondary Data Package Support".
v2: Modified and corrected the structures to be more in line for
kernel coding guidelines and rebased the code on Paulo's DP patchset
v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE
v4: moving them to include/drm/drm_dp_helper.h and also already
icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed
for PSR at once at drm_dp_helper.h
v5: Fix SDP VSC header and identation by (Paulo Zanoni) and
remove i915 from title (Daniel Vetter)
v6: Fix spec version and move comments from code to commit message
since numbers might change in the future (by Paulo Zanoni).
CC: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Sateesh Kavuri
Signed-off-by: Shobhit Kumar
Signed-off-by: Rodrigo Vivi
---
include/drm/drm_dp_helper.h | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index e8e1417..ae8dbfb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -342,13 +342,42 @@ u8 drm_dp_get_adjust_request_voltage(u8
link_status[DP_LINK_STATUS_SIZE],
u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
-#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_RECEIVER_CAP_SIZE 0xf
+#define EDP_PSR_RECEIVER_CAP_SIZE 2
+
void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
u8 drm_dp_link_rate_to_bw_code(int link_rate);
int drm_dp_bw_code_to_link_rate(u8 link_bw);
+struct edp_sdp_header {
+ u8 HB0; /* Secondary Data Packet ID */
+ u8 HB1; /* Secondary Data Packet Type */
+ u8 HB2; /* 7:5 reserved, 4:0 revision number */
+ u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
+} __packed;
+
+#define EDP_SDP_HEADER_REVISION_MASK 0x1F
+#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+
+struct edp_vsc_psr {
+ struct edp_sdp_header sdp_header;
+ u8 DB0; /* Stereo Interface */
+ u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+ u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+ u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+ u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+ u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+ u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+ u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+ u8 DB8_31[24]; /* Reserved */
+} __packed;
+
+#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
+#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
+#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+
static inline int
drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
--
1.8.1.4
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[Intel-gfx] [PATCH 01/11] drm: Added SDP and VSC structures for handling PSR for eDP
From: Shobhit Kumar
SDP header and SDP VSC header as per eDP 1.3 spec, section 3.5,
chapter "PSR Secondary Data Package Support".
v2: Modified and corrected the structures to be more in line for
kernel coding guidelines and rebased the code on Paulo's DP patchset
v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE
v4: moving them to include/drm/drm_dp_helper.h and also already
icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed
for PSR at once at drm_dp_helper.h
v5: Fix SDP VSC header and identation by (Paulo Zanoni) and
remove i915 from title (Daniel Vetter)
v6: Fix spec version and move comments from code to commit message
since numbers might change in the future (by Paulo Zanoni).
CC: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Sateesh Kavuri
Signed-off-by: Shobhit Kumar
Signed-off-by: Rodrigo Vivi
---
include/drm/drm_dp_helper.h | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index e8e1417..ae8dbfb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -342,13 +342,42 @@ u8 drm_dp_get_adjust_request_voltage(u8
link_status[DP_LINK_STATUS_SIZE],
u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
-#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_RECEIVER_CAP_SIZE 0xf
+#define EDP_PSR_RECEIVER_CAP_SIZE 2
+
void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
u8 drm_dp_link_rate_to_bw_code(int link_rate);
int drm_dp_bw_code_to_link_rate(u8 link_bw);
+struct edp_sdp_header {
+ u8 HB0; /* Secondary Data Packet ID */
+ u8 HB1; /* Secondary Data Packet Type */
+ u8 HB2; /* 7:5 reserved, 4:0 revision number */
+ u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
+} __packed;
+
+#define EDP_SDP_HEADER_REVISION_MASK 0x1F
+#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+
+struct edp_vsc_psr {
+ struct edp_sdp_header sdp_header;
+ u8 DB0; /* Stereo Interface */
+ u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+ u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+ u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+ u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+ u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+ u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+ u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+ u8 DB8_31[24]; /* Reserved */
+} __packed;
+
+#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
+#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
+#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+
static inline int
drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
--
1.8.1.4
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[Intel-gfx] [PATCH] drm/i915: Initialize drm_crtc gamma ramp
As we initialize our own gamma LUT to sane values during initialisation,
we should also update the user visible gamma ramp to match our settings.
And before touching the storage for the user visible gamma ramp, we also
need to check for an allocation failure.
Signed-off-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/intel_display.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5988bda..041e07a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8983,11 +8983,18 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
- drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
+ if (!drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256)) {
+ drm_crtc_cleanup(&intel_crtc->base);
+ kfree(intel_crtc);
+ return;
+ }
for (i = 0; i < 256; i++) {
intel_crtc->lut_r[i] = i;
intel_crtc->lut_g[i] = i;
intel_crtc->lut_b[i] = i;
+ intel_crtc->base.gamma_store[i + 0*256] = i << 8;
+ intel_crtc->base.gamma_store[i + 1*256] = i << 8;
+ intel_crtc->base.gamma_store[i + 2*256] = i << 8;
}
/* Swap pipes & planes for FBC on pre-965 */
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 03/24] drm/i915: assert_spin_locked for pipestat interrupt enable/disable
2013/6/12 Daniel Vetter :
> Just to keep the paranoia equal also sprinkle locking asserts over the
> pipestat interrupt enable/disable functions.
>
> Again this results in false positives in the interrupt setup. Add
> bogo-locking for these and a big comment explaining why it's there and
> that it's indeed unnecessary.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_irq.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 969da20..c0b6c85 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -329,6 +329,8 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int
> pipe, u32 mask)
> u32 reg = PIPESTAT(pipe);
> u32 pipestat = I915_READ(reg) & 0x7fff;
>
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> if ((pipestat & mask) == mask)
> return;
>
> @@ -344,6 +346,8 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int
> pipe, u32 mask)
> u32 reg = PIPESTAT(pipe);
> u32 pipestat = I915_READ(reg) & 0x7fff;
>
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> if ((pipestat & mask) == 0)
> return;
>
> @@ -2681,7 +2685,7 @@ static int ironlake_irq_postinstall(struct drm_device
> *dev)
> ibx_irq_postinstall(dev);
>
> if (IS_IRONLAKE_M(dev)) {
> - /* Clear & enable PCU event interrupts
> + /* Enable PCU event interrupts
Oh, here's the "updated comment" I was looking for in the previous
patch! Looks like it missed the train.
> *
> * spinlocking not required here for correctness since
> interrupt
> * setup is guaranteed to run in single-threaded context. But
> we
> @@ -2758,6 +2762,7 @@ static int valleyview_irq_postinstall(struct drm_device
> *dev)
> u32 gt_irqs;
> u32 enable_mask;
> u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> + unsigned long irqflags;
>
> enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> @@ -2783,9 +2788,13 @@ static int valleyview_irq_postinstall(struct
> drm_device *dev)
> I915_WRITE(PIPESTAT(1), 0x);
> POSTING_READ(VLV_IER);
>
> + /* Interrup setup is already guaranteed to be single-threaded, this is
> +* just to make the assert_spin_locked check happy. */
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
I guess the same question about irqsave from patch 1 applies here and below.
> i915_enable_pipestat(dev_priv, 0, pipestat_enable);
> i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> i915_enable_pipestat(dev_priv, 1, pipestat_enable);
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> I915_WRITE(VLV_IIR, 0x);
> I915_WRITE(VLV_IIR, 0x);
> @@ -3267,6 +3276,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
> drm_i915_private_t *dev_priv = (drm_i915_private_t *)
> dev->dev_private;
> u32 enable_mask;
> u32 error_mask;
> + unsigned long irqflags;
>
> /* Unmask the interrupts that we always want on. */
> dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
> @@ -3285,7 +3295,11 @@ static int i965_irq_postinstall(struct drm_device *dev)
> if (IS_G4X(dev))
> enable_mask |= I915_BSD_USER_INTERRUPT;
>
> + /* Interrup setup is already guaranteed to be single-threaded, this is
> +* just to make the assert_spin_locked check happy. */
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> /*
> * Enable some error detection, note the instruction error mask
> --
> 1.8.1.4
>
> ___
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--
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[Intel-gfx] [PATCH] drm/i915: get mode clock when reading the pipe config v9
We need this for comparing modes between configuration changes.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
v3: drop get_clock now that the pixel_multiply has been moved into
get_pipe_config
v4: re-add get_clock; we need to get the pixel multiplier in the
encoder, so need to calculate the clock value after the encoder's
get_config is called
v5: drop hsw clock_get, still needs to be written
v6: add fuzzy clock check (Daniel)
v7: wrap fuzzy clock check under !IS_HASWELL
use port_clock field rather than a new CPU eDP clock field in crtc_config
v8: remove stale pixel_multiplier sets (Daniel)
multiply by pixel_multiplier in 9xx clock get too (Daniel)
v9: make sure we set pixel_multiplier before calling clock_get from mode_get
for LVDS (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c | 120 +++---
drivers/gpu/drm/i915/intel_dp.c |7 ++
drivers/gpu/drm/i915/intel_sdvo.c|5 ++
4 files changed, 123 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4bbff22..a9886a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,7 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
+ void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8f746d9..be85800 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -45,6 +45,11 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
+static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config);
+static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config);
+
typedef struct {
int min, max;
} intel_range_t;
@@ -6877,11 +6882,12 @@ void intel_release_load_detect_pipe(struct
drm_connector *connector,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
{
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ int pipe = pipe_config->cpu_transcoder;
u32 dpll = I915_READ(DPLL(pipe));
u32 fp;
intel_clock_t clock;
@@ -6920,7 +6926,8 @@ static int intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc)
default:
DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
"mode\n", (int)(dpll & DPLL_MODE_MASK));
- return 0;
+ pipe_config->adjusted_mode.clock = 0;
+ return;
}
if (IS_PINEVIEW(dev))
@@ -6957,12 +6964,55 @@ static int intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc)
}
}
- /* XXX: It would be nice to validate the clocks, but we can't reuse
-* i830PllIsValid() because it relies on the xf86_config connector
-* configuration being accurate, which it isn't necessarily.
+ pipe_config->adjusted_mode.clock = clock.dot *
+ pipe_config->pixel_multiplier;
+}
+
+static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ int link_freq, repeat;
+ u64 clock;
+ u32 link_m, link_n;
+
+ repeat = pipe_config->pixel_multiplier;
+
+ /*
+* The calculation for the data clock is:
+* pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
+* But we want to avoid losing precison if possible, so:
+* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
+*
+* and the link c
Re: [Intel-gfx] [PATCH 02/24] drm/i915: close tiny race in the ilk pcu even interrupt setup
2013/6/12 Daniel Vetter :
> By the time we write DEIER in the postinstall hook the interrupt
> handler could run any time. And it does modify DEIER to handle
> interrupts.
>
> Hence the DEIER read-modify-write cycle for enabling the PCU event
> source is racy. Close this races the same way we handle vblank
> interrupts: Unconditionally enable the interrupt in the IER register,
> but conditionally mask it in IMR. The later poses no such race since
> the interrupt handler does not touch DEIMR.
>
> Also update the comment, the clearing has already happened
> unconditionally above.
I don't see an "updated comment". I guess you wanted to s/Clear &
enable/Enable/ ? Anyway:
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_irq.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 567945f..969da20 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2658,7 +2658,8 @@ static int ironlake_irq_postinstall(struct drm_device
> *dev)
> /* should always can generate irq */
> I915_WRITE(DEIIR, I915_READ(DEIIR));
> I915_WRITE(DEIMR, dev_priv->irq_mask);
> - I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
> + I915_WRITE(DEIER, display_mask |
> + DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
> POSTING_READ(DEIER);
>
> dev_priv->gt_irq_mask = ~0;
> @@ -2680,11 +2681,9 @@ static int ironlake_irq_postinstall(struct drm_device
> *dev)
> ibx_irq_postinstall(dev);
>
> if (IS_IRONLAKE_M(dev)) {
> - /* Clear & enable PCU event interrupts */
> - I915_WRITE(DEIIR, DE_PCU_EVENT);
> - I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
> -
> - /* spinlocking not required here for correctness since
> interrupt
> + /* Clear & enable PCU event interrupts
> +*
> +* spinlocking not required here for correctness since
> interrupt
> * setup is guaranteed to run in single-threaded context. But
> we
> * need it to make the assert_spin_locked happy. */
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> --
> 1.8.1.4
>
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915: fix locking around ironlake_enable|disable_display_irq
2013/6/25 Daniel Vetter :
> The haswell unclaimed register handling code forgot to take the
> spinlock. Since this is in the context of the non-rentrant interupt
> handler and we only have one interrupt handler it is sufficient to
> just grab the spinlock - we do not need to exclude any other
> interrupts from running on the same cpu.
>
> To prevent such gaffles in the future sprinkle assert_spin_locked over
> these functions. Unfornately this requires us to hold the spinlock in
> the ironlake postinstall hook where it is not strictly required:
> Currently that is run in single-threaded context and with userspace
> exlcuded from running concurrent ioctls. Add a comment explaining
> this.
>
> v2: ivb_can_enable_err_int also needs to be protected by the spinlock.
> To ensure this won't happen in the future again also sprinkle a
> spinlock assert in there.
Why does ivb_can_enable_err_int need it? Maybe we should add a comment
inside the function explaining why it needs it.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_irq.c | 27 ---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c482e8a..ff1fed4 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -95,6 +95,8 @@ static void i915_hpd_irq_setup(struct drm_device *dev);
> static void
> ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
> {
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> if ((dev_priv->irq_mask & mask) != 0) {
> dev_priv->irq_mask &= ~mask;
> I915_WRITE(DEIMR, dev_priv->irq_mask);
> @@ -105,6 +107,8 @@ ironlake_enable_display_irq(drm_i915_private_t *dev_priv,
> u32 mask)
> static void
> ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
> {
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> if ((dev_priv->irq_mask & mask) != mask) {
> dev_priv->irq_mask |= mask;
> I915_WRITE(DEIMR, dev_priv->irq_mask);
> @@ -118,6 +122,8 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
> struct intel_crtc *crtc;
> enum pipe pipe;
>
> + assert_spin_locked(&dev_priv->irq_lock);
> +
> for_each_pipe(pipe) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>
> @@ -1218,8 +1224,11 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
> *arg)
> /* On Haswell, also mask ERR_INT because we don't want to risk
> * generating "unclaimed register" interrupts from inside the
> interrupt
> * handler. */
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev)) {
> + spin_lock(&dev_priv->irq_lock);
> ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
> + spin_unlock(&dev_priv->irq_lock);
> + }
>
> gt_iir = I915_READ(GTIIR);
> if (gt_iir) {
> @@ -1272,8 +1281,12 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
> *arg)
> ret = IRQ_HANDLED;
> }
>
> - if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
> - ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
> + if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev)) {
> + spin_lock(&dev_priv->irq_lock);
> + if (ivb_can_enable_err_int(dev))
You're calling ivb_can_enable_err_int twice here.
> + ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
> + spin_unlock(&dev_priv->irq_lock);
> + }
>
> I915_WRITE(DEIER, de_ier);
> POSTING_READ(DEIER);
> @@ -2633,6 +2646,8 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>
> static int ironlake_irq_postinstall(struct drm_device *dev)
> {
> + unsigned long irqflags;
> +
> drm_i915_private_t *dev_priv = (drm_i915_private_t *)
> dev->dev_private;
> /* enable kind of interrupts always enabled */
> u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
> @@ -2671,7 +2686,13 @@ static int ironlake_irq_postinstall(struct drm_device
> *dev)
> /* Clear & enable PCU event interrupts */
> I915_WRITE(DEIIR, DE_PCU_EVENT);
> I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
> +
> + /* spinlocking not required here for correctness since
> interrupt
> +* setup is guaranteed to run in single-threaded context. But
> we
> +* need it to make the assert_spin_locked happy. */
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
If spinlocking is not even required, why take the irqsave one instead
of just spin_lock()?
> ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> return 0;
> --
> 1.8.1.4
>
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix VLV sprite register offsets
On Wed, Jun 26, 2013 at 08:44:54PM +0200, Daniel Vetter wrote: > On Tue, Jun 25, 2013 at 02:16:35PM +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > We forgot to add VLV_DISPLAY_BASE to the VLV sprite registers, which > > caused the sprites to not work at all. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/i915_reg.h | 50 > > - > > 1 file changed, 25 insertions(+), 25 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 2c3bba5..10ac3d5 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3492,7 +3492,7 @@ > > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) > > #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > > > -#define _SPACNTR 0x72180 > > +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) > > #define SP_ENABLE(1<<31) > > #define SP_GEAMMA_ENABLE (1<<30) > > #define SP_PIXFORMAT_MASK(0xf<<26) > > @@ -3511,30 +3511,30 @@ > > #define SP_YUV_ORDER_YVYU(2<<16) > > #define SP_YUV_ORDER_VYUY(3<<16) > > #define SP_TILED (1<<10) > > -#define _SPALINOFF 0x72184 > > -#define _SPASTRIDE 0x72188 > > -#define _SPAPOS0x7218c > > -#define _SPASIZE 0x72190 > > -#define _SPAKEYMINVAL 0x72194 > > -#define _SPAKEYMSK 0x72198 > > -#define _SPASURF 0x7219c > > -#define _SPAKEYMAXVAL 0x721a0 > > -#define _SPATILEOFF0x721a4 > > -#define _SPACONSTALPHA 0x721a8 > > -#define _SPAGAMC 0x721f4 > > - > > -#define _SPBCNTR 0x72280 > > -#define _SPBLINOFF 0x72284 > > -#define _SPBSTRIDE 0x72288 > > -#define _SPBPOS0x7228c > > -#define _SPBSIZE 0x72290 > > -#define _SPBKEYMINVAL 0x72294 > > -#define _SPBKEYMSK 0x72298 > > -#define _SPBSURF 0x7229c > > -#define _SPBKEYMAXVAL 0x722a0 > > -#define _SPBTILEOFF0x722a4 > > -#define _SPBCONSTALPHA 0x722a8 > > -#define _SPBGAMC 0x722f4 > > +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) > > +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) > > +#define _SPAPOS(VLV_DISPLAY_BASE + 0x7218c) > > +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) > > +#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) > > +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) > > +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) > > +#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) > > +#define _SPATILEOFF(VLV_DISPLAY_BASE + 0x721a4) > > +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) > > +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) > > + > > +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) > > +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) > > +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) > > +#define _SPBPOS(VLV_DISPLAY_BASE + 0x7228c) > > +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) > > +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) > > +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) > > +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) > > +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) > > +#define _SPBTILEOFF(VLV_DISPLAY_BASE + 0x722a4) > > +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) > > +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) > > Do we anticipate any unification of these registers anytime soon? I wonder > whether we should switch to a per-sprite mmio offset just in case. That's been on my TODO list since the dawn of time, but never got around to coding a solution I was happy with. > Anyway since this doesn't make it messier I've merged this patch for now. For now I'm happy to just get the damn sprites on the screen :) > -Daniel > > > > > #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) > > #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, > > _SPBLINOFF) > > -- > > 1.8.1.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Mask out hardware status bits from VLV DPLL register
On Wed, Jun 26, 2013 at 09:25:33AM -0700, Jesse Barnes wrote:
> On Wed, 26 Jun 2013 17:44:15 +0300
> ville.syrj...@linux.intel.com wrote:
>
> > From: Ville Syrjälä
> >
> > The DPLL lock bit, and the DPIO phy status bits are read-only and
> > controlled by the hardware, so they will never be set by the driver.
> > Mask them out when reading the hw state, so that the state
> > comparison won't fail.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 259ea4b..d67a9f5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4958,6 +4958,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc
> > *crtc,
> > if (!IS_VALLEYVIEW(dev)) {
> > pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
> > pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
> > + } else {
> > + pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
> > +DPLL_PORTC_READY_MASK |
> > +DPLL_PORTB_READY_MASK);
> > }
> >
> > return true;
>
> As a rule I'd like to see comments explaining this too, so we don't
> have to dig through the changelog to figure it out. But that's no
> biggie here, so:
Very much agreed on the need for a comment here, so I've added a
one-liner.
> Reviewed-by: Jesse Barnes
Queued for -next, thanks for the patch.
-Daniel
--
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Software Engineer, Intel Corporation
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Re: [Intel-gfx] [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers
On Wed, Jun 26, 2013 at 08:57:34PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Add the names of all VLV DPIO registers. > > v2: Use the third element to signal DPIO registers, and split > the code changes to a separate patch > > Signed-off-by: Ville Syrjälä > Series is: Reviewed-by: Ben Widawsky -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix VLV sprite register offsets
On Tue, Jun 25, 2013 at 02:16:35PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We forgot to add VLV_DISPLAY_BASE to the VLV sprite registers, which > caused the sprites to not work at all. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 50 > - > 1 file changed, 25 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2c3bba5..10ac3d5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3492,7 +3492,7 @@ > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) > #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > -#define _SPACNTR 0x72180 > +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) > #define SP_ENABLE (1<<31) > #define SP_GEAMMA_ENABLE (1<<30) > #define SP_PIXFORMAT_MASK (0xf<<26) > @@ -3511,30 +3511,30 @@ > #define SP_YUV_ORDER_YVYU (2<<16) > #define SP_YUV_ORDER_VYUY (3<<16) > #define SP_TILED (1<<10) > -#define _SPALINOFF 0x72184 > -#define _SPASTRIDE 0x72188 > -#define _SPAPOS 0x7218c > -#define _SPASIZE 0x72190 > -#define _SPAKEYMINVAL0x72194 > -#define _SPAKEYMSK 0x72198 > -#define _SPASURF 0x7219c > -#define _SPAKEYMAXVAL0x721a0 > -#define _SPATILEOFF 0x721a4 > -#define _SPACONSTALPHA 0x721a8 > -#define _SPAGAMC 0x721f4 > - > -#define _SPBCNTR 0x72280 > -#define _SPBLINOFF 0x72284 > -#define _SPBSTRIDE 0x72288 > -#define _SPBPOS 0x7228c > -#define _SPBSIZE 0x72290 > -#define _SPBKEYMINVAL0x72294 > -#define _SPBKEYMSK 0x72298 > -#define _SPBSURF 0x7229c > -#define _SPBKEYMAXVAL0x722a0 > -#define _SPBTILEOFF 0x722a4 > -#define _SPBCONSTALPHA 0x722a8 > -#define _SPBGAMC 0x722f4 > +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) > +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) > +#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) > +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) > +#define _SPAKEYMINVAL(VLV_DISPLAY_BASE + 0x72194) > +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) > +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) > +#define _SPAKEYMAXVAL(VLV_DISPLAY_BASE + 0x721a0) > +#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) > +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) > +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) > + > +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) > +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) > +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) > +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) > +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) > +#define _SPBKEYMINVAL(VLV_DISPLAY_BASE + 0x72294) > +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) > +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) > +#define _SPBKEYMAXVAL(VLV_DISPLAY_BASE + 0x722a0) > +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) > +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) > +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) Do we anticipate any unification of these registers anytime soon? I wonder whether we should switch to a per-sprite mmio offset just in case. Anyway since this doesn't make it messier I've merged this patch for now. -Daniel > > #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) > #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) > -- > 1.8.1.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915: Don't use the HDMI port color range bit on Valleyview"
On Wed, Jun 26, 2013 at 07:53:31AM -0700, Jesse Barnes wrote: > On Tue, 25 Jun 2013 14:16:34 +0300 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > The PIPECONF color range bit doesn't appear to be effective, on HDMI > > outputs at least. The color range bit in the port register works though, > > so let's use it. > > > > I have not yet verified whether the PIPECONF bit works on DP outputs. > > > > This reverts commit 83a2af88f80ebf8104c9e083b786668b00f5b9ce. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > > b/drivers/gpu/drm/i915/intel_hdmi.c > > index bc12518..98df2a0 100644 > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder > > *encoder, > > u32 hdmi_val; > > > > hdmi_val = SDVO_ENCODING_HDMI; > > - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) > > + if (!HAS_PCH_SPLIT(dev)) > > hdmi_val |= intel_hdmi->color_range; > > if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) > > hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; > > Reviewed-by: Jesse Barnes Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: s/LFP/LPF in DPIO PLL register names
On Wed, Jun 26, 2013 at 07:55:26AM -0700, Jesse Barnes wrote: > On Fri, 14 Jun 2013 14:02:53 +0300 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > LPF is short for "low pass filter". > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 8 > > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- > > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > > 3 files changed, 9 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > b/drivers/gpu/drm/i915/i915_debugfs.c > > index d4e78b6..cc20637 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -1862,10 +1862,10 @@ static int i915_dpio_info(struct seq_file *m, void > > *data) > > seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", > >vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); > > > > - seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", > > - vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); > > - seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", > > - vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); > > + seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", > > + vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); > > + seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", > > + vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); > > > > seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", > >vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 9cb6236..828a6ed 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -448,9 +448,9 @@ > > #define _DPIO_PLL_CML_B0x806c > > #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) > > > > -#define _DPIO_LFP_COEFF_A 0x8048 > > -#define _DPIO_LFP_COEFF_B 0x8068 > > -#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, > > _DPIO_LFP_COEFF_B) > > +#define _DPIO_LPF_COEFF_A 0x8048 > > +#define _DPIO_LPF_COEFF_B 0x8068 > > +#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, > > _DPIO_LPF_COEFF_B) > > > > #define DPIO_CALIBRATION 0x80ac > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 465d6bc..f6eaba2 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4407,10 +4407,10 @@ static void vlv_update_pll(struct intel_crtc *crtc) > > if (crtc->config.port_clock == 162000 || > > intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || > > intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) > > - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), > > + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), > > 0x005f0021); > > else > > - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), > > + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), > > 0x00df); > > > > if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || > > Reviewed-by: Jesse Barnes Both patches merged to dinq, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/3] quick_dump: Document the register definition format
From: Ville Syrjälä
Add a small comment about what the elements in the register
tuple mean.
Signed-off-by: Ville Syrjälä
---
tools/quick_dump/quick_dump.py | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 390cafa..8fdd169 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -1,5 +1,12 @@
#!/usr/bin/env python3
+# register definition format:
+# ('register name', 'register offset', 'register type')
+#
+# register types:
+# '' - normal register
+# 'DPIO' - DPIO register
+
import argparse
import os
import sys
--
1.8.1.5
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[Intel-gfx] [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers
From: Ville Syrjälä
Add the names of all VLV DPIO registers.
v2: Use the third element to signal DPIO registers, and split
the code changes to a separate patch
Signed-off-by: Ville Syrjälä
---
tools/quick_dump/Makefile.am | 2 +-
tools/quick_dump/valleyview | 1 +
tools/quick_dump/vlv_dpio.txt | 53 +++
3 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 tools/quick_dump/vlv_dpio.txt
diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am
index afd6814..cc19987 100644
--- a/tools/quick_dump/Makefile.am
+++ b/tools/quick_dump/Makefile.am
@@ -25,7 +25,7 @@ EXTRA_DIST = \
base_display.txt base_interrupt.txt base_other.txt base_power.txt
base_rings.txt \
gen6_other.txt sandybridge \
gen7_other.txt ivybridge \
- vlv_display.txt valleyview \
+ vlv_display.txt vlv_dpio.txt valleyview \
quick_dump.py \
reg_access.py \
chipset.i chipset.py
diff --git a/tools/quick_dump/valleyview b/tools/quick_dump/valleyview
index 4d7dee1..6b6e16c 100644
--- a/tools/quick_dump/valleyview
+++ b/tools/quick_dump/valleyview
@@ -5,3 +5,4 @@ base_other.txt
base_power.txt
base_rings.txt
gen7_other.txt
+vlv_dpio.txt
diff --git a/tools/quick_dump/vlv_dpio.txt b/tools/quick_dump/vlv_dpio.txt
new file mode 100644
index 000..8359149
--- /dev/null
+++ b/tools/quick_dump/vlv_dpio.txt
@@ -0,0 +1,53 @@
+('DPIO_TX3_SWING_CTL4_A', '0x690', 'DPIO')
+('DPIO_TX3_SWING_CTL4_B', '0x2a90', 'DPIO')
+('DPIO_DIV_A', '0x800c', 'DPIO')
+('DPIO_DIV_B', '0x802c', 'DPIO')
+('DPIO_REFSFR_A', '0x8014', 'DPIO')
+('DPIO_REFSFR_B', '0x8034', 'DPIO')
+('DPIO_CORE_CLK_A', '0x801c', 'DPIO')
+('DPIO_CORE_CLK_B', '0x803c', 'DPIO')
+('DPIO_IREF_CTL_A', '0x8040', 'DPIO')
+('DPIO_IREF_CTL_B', '0x8060', 'DPIO')
+('DPIO_IREF_BCAST', '0xc044', 'DPIO')
+('DPIO_IREF_A', '0x8044', 'DPIO')
+('DPIO_IREF_B', '0x8064', 'DPIO')
+('DPIO_PLL_CML_A', '0x804c', 'DPIO')
+('DPIO_PLL_CML_B', '0x806c', 'DPIO')
+('DPIO_LPF_COEFF_A', '0x8048', 'DPIO')
+('DPIO_LPF_COEFF_B', '0x8068', 'DPIO')
+('DPIO_CALIBRATION', '0x80ac', 'DPIO')
+('DPIO_FASTCLK_DISABLE', '0x8100', 'DPIO')
+('DPIO_PCS_TX_0', '0x8200', 'DPIO')
+('DPIO_PCS_TX_1', '0x8400', 'DPIO')
+('DPIO_PCS_CLK_0', '0x8204', 'DPIO')
+('DPIO_PCS_CLK_1', '0x8404', 'DPIO')
+('DPIO_PCS_CTL_OVR1_A', '0x8224', 'DPIO')
+('DPIO_PCS_CTL_OVR1_B', '0x8424', 'DPIO')
+('DPIO_PCS_STAGGER0_A', '0x822c', 'DPIO')
+('DPIO_PCS_STAGGER0_B', '0x842c', 'DPIO')
+('DPIO_PCS_STAGGER1_A', '0x8230', 'DPIO')
+('DPIO_PCS_STAGGER1_B', '0x8430', 'DPIO')
+('DPIO_PCS_CLOCKBUF0_A', '0x8238', 'DPIO')
+('DPIO_PCS_CLOCKBUF0_B', '0x8438', 'DPIO')
+('DPIO_PCS_CLOCKBUF8_A', '0x825c', 'DPIO')
+('DPIO_PCS_CLOCKBUF8_B', '0x845c', 'DPIO')
+('DPIO_TX_SWING_CTL2_A', '0x8288', 'DPIO')
+('DPIO_TX_SWING_CTL2_B', '0x8488', 'DPIO')
+('DPIO_TX_SWING_CTL3_A', '0x828c', 'DPIO')
+('DPIO_TX_SWING_CTL3_B', '0x848c', 'DPIO')
+('DPIO_TX_SWING_CTL4_A', '0x8290', 'DPIO')
+('DPIO_TX_SWING_CTL4_B', '0x8490', 'DPIO')
+('DPIO_TX_OCALINIT_0', '0x8294', 'DPIO')
+('DPIO_TX_OCALINIT_1', '0x8494', 'DPIO')
+('DPIO_TX_CTL_0', '0x82ac', 'DPIO')
+('DPIO_TX_CTL_1', '0x84ac', 'DPIO')
+('DPIO_TX_LANE_0', '0x82b8', 'DPIO')
+('DPIO_TX_LANE_1', '0x84b8', 'DPIO')
+('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
+('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
+('DPIO_PORT0_PCS0', '0x0220', 'DPIO')
+('DPIO_PORT0_PCS1', '0x0420', 'DPIO')
+('DPIO_PORT1_PCS2', '0x2620', 'DPIO')
+('DPIO_PORT1_PCS3', '0x2820', 'DPIO')
+('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
+('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
--
1.8.1.5
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[Intel-gfx] [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support
From: Ville Syrjälä
Repurpose the (currently unused) third element in the register
definition tuple to indicate the type of the register. 'DPIO'
is the only special register type for now.
Signed-off-by: Ville Syrjälä
---
tools/quick_dump/quick_dump.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 6111b5d..390cafa 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -13,7 +13,10 @@ def parse_file(file):
print('-' * 54)
for line in file:
register = ast.literal_eval(line)
- val = reg.read(register[1])
+ if register[2] == 'DPIO':
+ val = reg.dpio_read(register[1])
+ else:
+ val = reg.read(register[1])
intreg = int(register[1], 16)
print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg,
register[0], val))
print('')
--
1.8.1.5
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: s/LFP/LPF in DPIO PLL register names
On Fri, 14 Jun 2013 14:02:53 +0300 ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > LPF is short for "low pass filter". > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_debugfs.c | 8 > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 3 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index d4e78b6..cc20637 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1862,10 +1862,10 @@ static int i915_dpio_info(struct seq_file *m, void > *data) > seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", > vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); > > - seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", > -vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); > - seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", > -vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); > + seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", > +vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); > + seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", > +vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); > > seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", > vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9cb6236..828a6ed 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -448,9 +448,9 @@ > #define _DPIO_PLL_CML_B 0x806c > #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) > > -#define _DPIO_LFP_COEFF_A0x8048 > -#define _DPIO_LFP_COEFF_B0x8068 > -#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, > _DPIO_LFP_COEFF_B) > +#define _DPIO_LPF_COEFF_A0x8048 > +#define _DPIO_LPF_COEFF_B0x8068 > +#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, > _DPIO_LPF_COEFF_B) > > #define DPIO_CALIBRATION 0x80ac > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 465d6bc..f6eaba2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4407,10 +4407,10 @@ static void vlv_update_pll(struct intel_crtc *crtc) > if (crtc->config.port_clock == 162000 || > intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || > intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) > - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), > + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), >0x005f0021); > else > - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), > + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), >0x00df); > > if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915: Don't use the HDMI port color range bit on Valleyview"
On Tue, 25 Jun 2013 14:16:34 +0300 ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The PIPECONF color range bit doesn't appear to be effective, on HDMI > outputs at least. The color range bit in the port register works though, > so let's use it. > > I have not yet verified whether the PIPECONF bit works on DP outputs. > > This reverts commit 83a2af88f80ebf8104c9e083b786668b00f5b9ce. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index bc12518..98df2a0 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder > *encoder, > u32 hdmi_val; > > hdmi_val = SDVO_ENCODING_HDMI; > - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) > + if (!HAS_PCH_SPLIT(dev)) > hdmi_val |= intel_hdmi->color_range; > if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) > hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] 'Timed out waiting for forcewake old ack to clear' and hangup on IvyBridge system
On Wed, Jun 26, 2013 at 09:24:07AM -0700, Jesse Barnes wrote: > On Sat, 22 Jun 2013 13:04:09 -0700 > Guenter Roeck wrote: > > > On Sat, Jun 22, 2013 at 12:16:46PM -0700, Jesse Barnes wrote: > > > On Fri, 21 Jun 2013 23:58:08 -0700 > > > Guenter Roeck wrote: > > > > > > > Hi all, > > > > > > > > after upgrading one of my servers to 3.8, then 3.9.7 and 3.10-rc6, I > > > > started to > > > > see lots of "Timed out waiting for forcewake old ack to clear" error > > > > messages, > > > > including hang-ups especially if the system was highly loaded. With > > > > 3.5.24 > > > > everything was fine. > > > > > > > > After backing out commit 36ec8f877 (drm/i915: unconditionally use mt > > > > forcewake > > > > on hsw/ivb), everything is back to normal. The log message is still > > > > there, but > > > > only once during boot, and the system runs stable. > > > > > > > > CPU is "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz", mainboard is > > > > Supermicro > > > > C7H61, BIOS version 2.00 dated 11/02/2012. Configuration file is > > > > whatever > > > > comes with Ubuntu; I'll be happy to provide a copy if anyone thinks it > > > > might > > > > help. > > > > > > > > Any idea what else I can do besides using a special kernel with the > > > > backed out > > > > commit ? Is it possible that others have the same problem ? > > > > > > Ouch, so a BIOS that uses the other forcewake mechanism seems to have > > > escaped. Is there a newer one available for your system? I'm hoping > > > it'll fix the issue, otherwise we may have to introduce both methods > > > for IVB again... > > > > > I installed the latest BIOS version (2.00b), but it did not fix the problem. > > > > Is there some info (such as an Intel document describing what needs to be > > done) > > which I could pass on to Supermicro ? > > > > I think it would be helpful if the condition was detected and reported, if > > that > > is possible. I spent two days so far tracking this down. It would be nice > > if others would not have to go through the same experience. > > I don't think there's anything public to share, but it's not a big deal > to simply revert the patch in question. That seems like the right > thing to do anyway since we'd like stuff to work "out of the box" as > much as possible. > Agreed. Kind of unlikely that I can get Supermicro to listen to me anyway :(. Who can initiate the revert ? Thanks, Guenter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use wait_for() to wait for Punit to change GPU freq on VLV
On Wed, 26 Jun 2013 17:43:24 +0300
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Use wait_for() instead of the open coded loop to avoid spreading the
> same old timeout related bugs.
>
> This changes the loop to use msleep(1) instead of udelay(10) when the
> Punit had not yet completed the frequency change. In practice that
> doesn't seem to hurt performance as the Punit appears to be ready pretty
> much always.
>
> Also give the status bit a name, instead of using the magic number 1.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 11 ++-
> 2 files changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10ac3d5..d5199a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -363,6 +363,7 @@
> #define PUNIT_REG_GPU_LFM0xd3
> #define PUNIT_REG_GPU_FREQ_REQ 0xd4
> #define PUNIT_REG_GPU_FREQ_STS 0xd8
> +#define GENFREQSTATUS (1<<0)
> #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
>
> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index aa48fc6..bff5709 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3074,19 +3074,12 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
> */
> static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
> {
> - unsigned long timeout = jiffies + msecs_to_jiffies(10);
> u32 pval;
>
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>
> - do {
> - pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> - if (time_after(jiffies, timeout)) {
> - DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
> - break;
> - }
> - udelay(10);
> - } while (pval & 1);
> + if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
> & GENFREQSTATUS) == 0, 10))
> + DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
>
> pval >>= 8;
>
Reviewed-by: Jesse Barnes
--
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Re: [Intel-gfx] [PATCH] drm/i915: Mask out hardware status bits from VLV DPLL register
On Wed, 26 Jun 2013 17:44:15 +0300
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The DPLL lock bit, and the DPIO phy status bits are read-only and
> controlled by the hardware, so they will never be set by the driver.
> Mask them out when reading the hw state, so that the state
> comparison won't fail.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 259ea4b..d67a9f5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4958,6 +4958,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc
> *crtc,
> if (!IS_VALLEYVIEW(dev)) {
> pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
> pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
> + } else {
> + pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
> + DPLL_PORTC_READY_MASK |
> + DPLL_PORTB_READY_MASK);
> }
>
> return true;
As a rule I'd like to see comments explaining this too, so we don't
have to dig through the changelog to figure it out. But that's no
biggie here, so:
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Re: [Intel-gfx] 'Timed out waiting for forcewake old ack to clear' and hangup on IvyBridge system
On Sat, 22 Jun 2013 13:04:09 -0700 Guenter Roeck wrote: > On Sat, Jun 22, 2013 at 12:16:46PM -0700, Jesse Barnes wrote: > > On Fri, 21 Jun 2013 23:58:08 -0700 > > Guenter Roeck wrote: > > > > > Hi all, > > > > > > after upgrading one of my servers to 3.8, then 3.9.7 and 3.10-rc6, I > > > started to > > > see lots of "Timed out waiting for forcewake old ack to clear" error > > > messages, > > > including hang-ups especially if the system was highly loaded. With 3.5.24 > > > everything was fine. > > > > > > After backing out commit 36ec8f877 (drm/i915: unconditionally use mt > > > forcewake > > > on hsw/ivb), everything is back to normal. The log message is still > > > there, but > > > only once during boot, and the system runs stable. > > > > > > CPU is "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz", mainboard is Supermicro > > > C7H61, BIOS version 2.00 dated 11/02/2012. Configuration file is whatever > > > comes with Ubuntu; I'll be happy to provide a copy if anyone thinks it > > > might > > > help. > > > > > > Any idea what else I can do besides using a special kernel with the > > > backed out > > > commit ? Is it possible that others have the same problem ? > > > > Ouch, so a BIOS that uses the other forcewake mechanism seems to have > > escaped. Is there a newer one available for your system? I'm hoping > > it'll fix the issue, otherwise we may have to introduce both methods > > for IVB again... > > > I installed the latest BIOS version (2.00b), but it did not fix the problem. > > Is there some info (such as an Intel document describing what needs to be > done) > which I could pass on to Supermicro ? > > I think it would be helpful if the condition was detected and reported, if > that > is possible. I spent two days so far tracking this down. It would be nice > if others would not have to go through the same experience. I don't think there's anything public to share, but it's not a big deal to simply revert the patch in question. That seems like the right thing to do anyway since we'd like stuff to work "out of the box" as much as possible. Daniel? -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: copy fetched mode state into crtc at setup_hw time v5
We already fetch and track other state into the main CRTC and encoder
structs, and for fastboot we need to do the same with the mode and clock
data we read out.
v2: fix debug print
v3: use fastboot param around state copy
v4: set clock and flags for crtc here instead of in setup_hw_state
v5: rename function to intel_crtc_mode_from_pipe_config for consistency (Chris)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1fb44fd..33faa36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4731,6 +4731,27 @@ static void intel_get_pipe_timings(struct intel_crtc
*crtc,
pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0x) + 1;
}
+static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
+struct intel_crtc_config
*pipe_config)
+{
+ struct drm_crtc *crtc = &intel_crtc->base;
+
+ crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
+ crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
+ crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
+ crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
+
+ crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
+ crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
+ crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
+ crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
+
+ crtc->mode.flags = pipe_config->adjusted_mode.flags;
+
+ crtc->mode.clock = pipe_config->adjusted_mode.clock;
+ crtc->mode.flags |= pipe_config->adjusted_mode.flags;
+}
+
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -9942,6 +9963,22 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
intel_modeset_readout_hw_state(dev);
+ /*
+* Now that we have the config, copy it to each CRTC struct
+* Note that this could go away if we move to using crtc_config
+* checking everywhere.
+*/
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+ base.head) {
+ if (crtc->active && i915_fastboot) {
+ intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
+
+ DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
+ crtc->base.base.id);
+ drm_mode_debug_printmodeline(&crtc->base.mode);
+ }
+ }
+
/* HW state is read out, now we need to sanitize this mess. */
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
base.head) {
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: get mode clock when reading the pipe config v8
We need this for comparing modes between configuration changes.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
v3: drop get_clock now that the pixel_multiply has been moved into
get_pipe_config
v4: re-add get_clock; we need to get the pixel multiplier in the
encoder, so need to calculate the clock value after the encoder's
get_config is called
v5: drop hsw clock_get, still needs to be written
v6: add fuzzy clock check (Daniel)
v7: wrap fuzzy clock check under !IS_HASWELL
use port_clock field rather than a new CPU eDP clock field in crtc_config
v8: remove stale pixel_multiplier sets (Daniel)
multiply by pixel_multiplier in 9xx clock get too (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c | 112 +++---
drivers/gpu/drm/i915/intel_dp.c |7 +++
drivers/gpu/drm/i915/intel_sdvo.c|5 ++
4 files changed, 115 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4bbff22..a9886a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,7 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
+ void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8f746d9..1fb44fd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -45,6 +45,11 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
+static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config);
+static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config);
+
typedef struct {
int min, max;
} intel_range_t;
@@ -6877,11 +6882,12 @@ void intel_release_load_detect_pipe(struct
drm_connector *connector,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
{
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ int pipe = pipe_config->cpu_transcoder;
u32 dpll = I915_READ(DPLL(pipe));
u32 fp;
intel_clock_t clock;
@@ -6920,7 +6926,8 @@ static int intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc)
default:
DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
"mode\n", (int)(dpll & DPLL_MODE_MASK));
- return 0;
+ pipe_config->adjusted_mode.clock = 0;
+ return;
}
if (IS_PINEVIEW(dev))
@@ -6957,12 +6964,55 @@ static int intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc)
}
}
- /* XXX: It would be nice to validate the clocks, but we can't reuse
-* i830PllIsValid() because it relies on the xf86_config connector
-* configuration being accurate, which it isn't necessarily.
+ pipe_config->adjusted_mode.clock = clock.dot *
+ pipe_config->pixel_multiplier;
+}
+
+static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ int link_freq, repeat;
+ u64 clock;
+ u32 link_m, link_n;
+
+ repeat = pipe_config->pixel_multiplier;
+
+ /*
+* The calculation for the data clock is:
+* pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
+* But we want to avoid losing precison if possible, so:
+* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
+*
+* and the link clock is simpler:
+* link_clock = (m * link_clock * repeat) / n
+*/
+
+ /*
+
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Fix VLV PLL LPF coefficients for DAC
On Fri, 14 Jun 2013 14:02:52 +0300 ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The current PLL settings produce a rather unstable picture when > I hook up a VLV to my HP ZR24w display via a VGA cable. > > According to VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_9, we should > use the the same LPF coefficients for DAC as we do for HDMI and RBR DP. > And indeed that seems to cure the shivers. > > v2: Add the name of the relevant document to the commit message > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_display.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 29f2c0d..465d6bc 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4405,6 +4405,7 @@ static void vlv_update_pll(struct intel_crtc *crtc) > > /* Set HBR and RBR LPF coefficients */ > if (crtc->config.port_clock == 162000 || > + intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || > intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) > vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), >0x005f0021); Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Mask out hardware status bits from VLV DPLL register
From: Ville Syrjälä
The DPLL lock bit, and the DPIO phy status bits are read-only and
controlled by the hardware, so they will never be set by the driver.
Mask them out when reading the hw state, so that the state
comparison won't fail.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 259ea4b..d67a9f5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4958,6 +4958,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (!IS_VALLEYVIEW(dev)) {
pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
+ } else {
+ pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
+DPLL_PORTC_READY_MASK |
+DPLL_PORTB_READY_MASK);
}
return true;
--
1.8.1.5
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[Intel-gfx] [PATCH] drm/i915: Use wait_for() to wait for Punit to change GPU freq on VLV
From: Ville Syrjälä
Use wait_for() instead of the open coded loop to avoid spreading the
same old timeout related bugs.
This changes the loop to use msleep(1) instead of udelay(10) when the
Punit had not yet completed the frequency change. In practice that
doesn't seem to hurt performance as the Punit appears to be ready pretty
much always.
Also give the status bit a name, instead of using the magic number 1.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10ac3d5..d5199a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -363,6 +363,7 @@
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define GENFREQSTATUS(1<<0)
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa48fc6..bff5709 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3074,19 +3074,12 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
{
- unsigned long timeout = jiffies + msecs_to_jiffies(10);
u32 pval;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
- do {
- pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- if (time_after(jiffies, timeout)) {
- DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
- break;
- }
- udelay(10);
- } while (pval & 1);
+ if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
& GENFREQSTATUS) == 0, 10))
+ DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
pval >>= 8;
--
1.8.1.5
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix VLV sprite register offsets
On Tue, 25 Jun 2013 14:16:35 +0300 ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We forgot to add VLV_DISPLAY_BASE to the VLV sprite registers, which > caused the sprites to not work at all. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 50 > - > 1 file changed, 25 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2c3bba5..10ac3d5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3492,7 +3492,7 @@ > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) > #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > -#define _SPACNTR 0x72180 > +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) > #define SP_ENABLE (1<<31) > #define SP_GEAMMA_ENABLE (1<<30) > #define SP_PIXFORMAT_MASK (0xf<<26) > @@ -3511,30 +3511,30 @@ > #define SP_YUV_ORDER_YVYU (2<<16) > #define SP_YUV_ORDER_VYUY (3<<16) > #define SP_TILED (1<<10) > -#define _SPALINOFF 0x72184 > -#define _SPASTRIDE 0x72188 > -#define _SPAPOS 0x7218c > -#define _SPASIZE 0x72190 > -#define _SPAKEYMINVAL0x72194 > -#define _SPAKEYMSK 0x72198 > -#define _SPASURF 0x7219c > -#define _SPAKEYMAXVAL0x721a0 > -#define _SPATILEOFF 0x721a4 > -#define _SPACONSTALPHA 0x721a8 > -#define _SPAGAMC 0x721f4 > - > -#define _SPBCNTR 0x72280 > -#define _SPBLINOFF 0x72284 > -#define _SPBSTRIDE 0x72288 > -#define _SPBPOS 0x7228c > -#define _SPBSIZE 0x72290 > -#define _SPBKEYMINVAL0x72294 > -#define _SPBKEYMSK 0x72298 > -#define _SPBSURF 0x7229c > -#define _SPBKEYMAXVAL0x722a0 > -#define _SPBTILEOFF 0x722a4 > -#define _SPBCONSTALPHA 0x722a8 > -#define _SPBGAMC 0x722f4 > +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) > +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) > +#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) > +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) > +#define _SPAKEYMINVAL(VLV_DISPLAY_BASE + 0x72194) > +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) > +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) > +#define _SPAKEYMAXVAL(VLV_DISPLAY_BASE + 0x721a0) > +#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) > +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) > +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) > + > +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) > +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) > +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) > +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) > +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) > +#define _SPBKEYMINVAL(VLV_DISPLAY_BASE + 0x72294) > +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) > +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) > +#define _SPBKEYMAXVAL(VLV_DISPLAY_BASE + 0x722a0) > +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) > +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) > +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) > > #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) > #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) QA needs to get their VLV system set up to catch stuff like this... Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: copy fetched mode state into crtc at setup_hw time v4
On Wed, Jun 26, 2013 at 01:38:17AM +0300, Jesse Barnes wrote: > We already fetch and track other state into the main CRTC and encoder > structs, and for fastboot we need to do the same with the mode and clock > data we read out. > > v2: fix debug print > v3: use fastboot param around state copy > v4: set clock and flags for crtc here instead of in setup_hw_state to_mode (or to_crtc_mode for extra verbosity) makes more sense, and given the ordering of the parameters: intel_crtc_mode_from_pipe_config(). -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: get mode clock when reading the pipe config v7
On Wed, Jun 26, 2013 at 01:38:16AM +0300, Jesse Barnes wrote:
> We need this for comparing modes between configuration changes.
>
> v2: try harder to calulate non-simple pixel clocks (Daniel)
> call get_clock after getting the encoder config, needed for pixel multiply
> (Jesse)
> v3: drop get_clock now that the pixel_multiply has been moved into
> get_pipe_config
> v4: re-add get_clock; we need to get the pixel multiplier in the
> encoder, so need to calculate the clock value after the encoder's
> get_config is called
> v5: drop hsw clock_get, still needs to be written
> v6: add fuzzy clock check (Daniel)
> v7: wrap fuzzy clock check under !IS_HASWELL
> use port_clock field rather than a new CPU eDP clock field in crtc_config
>
> Signed-off-by: Jesse Barnes
You have some random pixel_multiplier = 1 assignments lingering around,
those should all go away on top of latest dinq. And with the patch I've
just posted we'll even have correct pixel multiplier read-out support on
pch-split platforms.
Second issue is that the pixel multiplier for the i9xx dotclock
reconstruction code looks wrong, it doesn't seem to take it into account
at all.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h |1 +
> drivers/gpu/drm/i915/intel_crt.c |1 +
> drivers/gpu/drm/i915/intel_display.c | 109
> +++---
> drivers/gpu/drm/i915/intel_dp.c |8 +++
> drivers/gpu/drm/i915/intel_dvo.c |1 +
> drivers/gpu/drm/i915/intel_hdmi.c|1 +
> drivers/gpu/drm/i915/intel_lvds.c|1 +
> drivers/gpu/drm/i915/intel_sdvo.c|5 ++
> 8 files changed, 120 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4bbff22..a9886a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -364,6 +364,7 @@ struct drm_i915_display_funcs {
>* fills out the pipe-config with the hw state. */
> bool (*get_pipe_config)(struct intel_crtc *,
> struct intel_crtc_config *);
> + void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
> int (*crtc_mode_set)(struct drm_crtc *crtc,
>int x, int y,
>struct drm_framebuffer *old_fb);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 3acec8c..765a224 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -104,6 +104,7 @@ static void intel_crt_get_config(struct intel_encoder
> *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> pipe_config->adjusted_mode.flags |= flags;
> + pipe_config->pixel_multiplier = 1;
> }
>
> /* Note: The caller is required to filter out dpms modes not supported by the
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8f746d9..e75ce2f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -45,6 +45,11 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
> static void intel_increase_pllclock(struct drm_crtc *crtc);
> static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
>
> +static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config);
> +static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config);
> +
> typedef struct {
> int min, max;
> } intel_range_t;
> @@ -6877,11 +6882,12 @@ void intel_release_load_detect_pipe(struct
> drm_connector *connector,
> }
>
> /* Returns the clock of the currently programmed mode of the given pipe. */
> -static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc
> *crtc)
> +static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> {
> + struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + int pipe = pipe_config->cpu_transcoder;
> u32 dpll = I915_READ(DPLL(pipe));
> u32 fp;
> intel_clock_t clock;
> @@ -6920,7 +6926,8 @@ static int intel_crtc_clock_get(struct drm_device *dev,
> struct drm_crtc *crtc)
> default:
> DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
> "mode\n", (int)(dpll & DPLL_MODE_MASK));
> - return 0;
> + pipe_config->adjusted_mode.clock = 0;
> + return;
> }
>
> if (IS_PINEVIEW(dev))
> @@ -6961,8 +6968,54 @@ static int intel_crtc_clock_get(struct drm_device
> *dev, struct drm_crtc *crtc)
>* i830PllIsValid() bec
Re: [Intel-gfx] [RFC][PATCH 2/2] drm/i915: Jump to at least RPe on VLV when increasing the GPU frequency
On Tue, Jun 25, 2013 at 11:54:39AM -0700, Jesse Barnes wrote:
> On Tue, 25 Jun 2013 21:38:11 +0300
> ville.syrj...@linux.intel.com wrote:
>
> > From: Ville Syrjälä
> >
> > If the current GPU frquency is below RPe, and we're asked to increase
> > it, just go directly to RPe. This should provide better performance
> > faster than letting the frequency trickle up in response to the up
> > threshold interrupts.
> >
> > For now just do it for VLV, since that matches quite closely how VLV
> > used to operate when the rps delayed timer kept things at RPe always.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 12 ++--
> > 1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 62f8b2d..d6bd0d7 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -699,9 +699,17 @@ static void gen6_pm_rps_work(struct work_struct *work)
> >
> > mutex_lock(&dev_priv->rps.hw_lock);
> >
> > - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
> > + if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
> > new_delay = dev_priv->rps.cur_delay + 1;
> > - else
> > +
> > + /*
> > +* For better performance, jump directly
> > +* to RPe if we're below it.
> > +*/
> > + if (IS_VALLEYVIEW(dev_priv->dev) &&
> > + dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
> > + new_delay = dev_priv->rps.rpe_delay;
> > + } else
> > new_delay = dev_priv->rps.cur_delay - 1;
> >
> > /* sysfs frequency interfaces may have snuck in while servicing the
>
> Yeah, seems reasonable. Going to RP1 on other platforms might be a
> good approximation of this.
>
> Reviewed-by: Jesse Barnes
Queued for -next, thanks for the patch.
-Daniel
--
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Software Engineer, Intel Corporation
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Re: [Intel-gfx] [RFC][PATCH 1/2] drm/i915: Don't increase the GPU frequency from the delayed VLV rps timer
On Tue, Jun 25, 2013 at 11:53:28AM -0700, Jesse Barnes wrote: > On Tue, 25 Jun 2013 21:38:10 +0300 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > There's little point in increasing the GPU frequency from the delayed > > rps work on VLV. Now when the GPU is idle, the GPU frequency actually > > keeps dropping gradually until it hits the minimum, whereas previously > > it just ping-ponged constantly between RPe and RPe-1. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 96cfb3e..eaf0fa2 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3464,7 +3464,8 @@ static void vlv_rps_timer_work(struct work_struct > > *work) > > * min freq available. > > */ > > mutex_lock(&dev_priv->rps.hw_lock); > > - valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > > + if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) > > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > > mutex_unlock(&dev_priv->rps.hw_lock); > > } > > > > Hm that's not what I saw here; I stopped getting the timer interrupts > when the GPU went idle. But that could be explained by punit fw > differences. > > So this change looks ok to me. > > Reviewed-by: Jesse Barnes Queued for -next, thanks for the patch. In case you noodle around in here some more, I'd also vote for a s/timer_work/delayed_work/ color change: The execution enviroment of a time is _much_ different than from a work, so sticking to consistent naming helps in reading code. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/6] drm/i915: GEN6_RP_INTERRUPT_LIMITS doesn't seem to exist on VLV
On Tue, Jun 25, 2013 at 12:06:47PM -0700, Jesse Barnes wrote:
> On Tue, 25 Jun 2013 19:21:06 +0300
> ville.syrj...@linux.intel.com wrote:
>
> > From: Ville Syrjälä
> >
> > I can't find GEN6_RP_INTERRUPT_LIMITS (0xA014) anywhere in VLV docs.
> > Reading it always returns zero from what I can tell, and eliminating
> > it doesn't seem to make any difference to the behaviour of the system.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 8 ++--
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8b7475e..96cfb3e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3107,7 +3107,8 @@ static void vlv_update_rps_cur_delay(struct
> > drm_i915_private *dev_priv)
> > void valleyview_set_rps(struct drm_device *dev, u8 val)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > - u32 limits = gen6_rps_limits(dev_priv, &val);
> > +
> > + gen6_rps_limits(dev_priv, &val);
> >
> > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > WARN_ON(val > dev_priv->rps.max_delay);
> > @@ -3126,11 +3127,6 @@ void valleyview_set_rps(struct drm_device *dev, u8
> > val)
> >
> > vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> >
> > - /* Make sure we continue to get interrupts
> > -* until we hit the minimum or maximum frequencies.
> > -*/
> > - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
> > -
> > dev_priv->rps.cur_delay = val;
> >
> > trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
>
> I don't see it anymore either... so Reviewed-by: Jesse Barnes
>
Thanks for patches and review, all but 4&5 merged to dinq. Like mentioned
in my other mail I'd vote to replace the logic in patches 4&5 with a
simple wait_for if it doesn't hurt performance.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Optimize the VLV Punit wait a bit
On Tue, Jun 25, 2013 at 07:21:03PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Don't do needless udelay() calls if the Punit already completed
> the frequency change.
>
> Also double check things after the timeout to make sure the timeout
> wasn't just caused by some scheduling delays.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6dbcad7..6b98d45 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3078,14 +3078,20 @@ static void vlv_update_rps_cur_delay(struct
> drm_i915_private *dev_priv)
>
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>
> - do {
> - pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +
> + while (pval & 1) {
> if (time_after(jiffies, timeout)) {
> - DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
> + pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> break;
> }
> +
> udelay(10);
> - } while (pval & 1);
> + pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + }
> +
> + if (pval & 1)
> + DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
Since we notoriously get these suckers wrong and this check isn't really
in the critical path any more (the punit should have complete the last
change already) and furthermore in a work item: Can we just use one of our
bog-standard wait_for macros here now?
-Daniel
--
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Software Engineer, Intel Corporation
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Re: [Intel-gfx] [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port enable function
On Sat, Jun 15, 2013 at 11:32:51AM +0300, Imre Deak wrote: > On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote: > > i9xx doesn't use pre_enable at all, so we can fold this in now. > > > > Signed-off-by: Daniel Vetter > > I managed to review 23-28 for now, so on those apart from the two > nitpicks: > > Reviewed-by: Imre Deak Merged up to patch 28, thanks for the review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
