Re: [Intel-gfx] [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8
On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote: Hello All- I'm trying to determine if the ChromeOS-only patches being carried by Google still make sense and are the right way to do things in the 3.11+ world, and Jesse asked me to forward the patches to the list for evaluation and potential upstreaming. I've quickly read through the pile here and there's a few things we need to look at. But one thing which makes assessing the patches here a bit a pain is that often there's a fixup later on again. E.g. rc6 is tuned in about 5-6 different patches. There's also a bunch of patches to fix up warnings introduced in earlier ones So can you please go through this and squash in the fixups into the relevant original patches and resubmit? Please keep the commit messages around in case there's interesting stuff in there like when a tuning value changes again. Thanks, Daniel Thanks! -James [PATCH] drm/i915: Only apply the adaptive backlight modulation when [PATCH] drm/i915: Add a try limit to avoid infinite loops [PATCH] drm/i915: Add a timeout to a potentially infinite loop [PATCH] i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7 [PATCH] drm/i915: Make intel_dp_aux_native_read timeout [PATCH] drm/i915: Honor i915_min_freq post resume [PATCH] Wake up DP sinks for DPCD read-based detection. [PATCH] Restrict DP sink wake up to non-EDP. [PATCH] Fix display underruns on Pineview with 2048x1280 VGA display. [PATCH] CHROMIUM: drivers: i915: select non-alternate SSC frequency [PATCH] CHROMIUM: drivers: i915: Default backlight PWM frequency [PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by [PATCH] CHROMIUM: drm/i915: Enable LVDS downclocking [PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores [PATCH] CHROMIUM: drm/i915: Adjust the down threshold. [PATCH] CHROMIUM: drm/i915: Adjust the RPS thresholds [PATCH] CHROMIUM: drm/i915: Move the backlight accessor functions in [PATCH] CHROMIUM: drm/i915: Add backlight support for Link [PATCH] CHROMIUM: drm/i915: set enable_rc6 to per-chip default. [PATCH] CHROMIUM: gpu: i915: optimize vblank timeout [PATCH] CHROMIUM: i915: Allow 0 level when turning on backlight. [PATCH] CHROMIUM: drm/i915: Check the current edp backlight state [PATCH] CHROMIUM: drm/i915: Workaround disappearing AVI Infoframe on [PATCH] CHROMIUM: Partial revert of [PATCH] CHROMIUM: drm/i915: bounds check execbuffer relocations [PATCH] CHROMIUM: drm/i915: Improve RC6p stability [PATCH] CHROMIUM: drm/i915/intel_i2c: enable 400kHz GMBUS for [PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for cyapa [PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for atmel mxt bl [PATCH] CHROMIUM: drm/i915: fix resume [PATCH] CHROMIUM: drm/i915: Fix warning [PATCH] CHROMIUM: drm/i915: Initialize the backlight when reported [PATCH] CHROMIUM: drm/i915: Don't evict bound object in the shrinker [PATCH] CHROMIUM: drm/i915/intel_drv: reduce wait_for polling time [PATCH] CHROMIUM: drm/i915: tune the RC6 timeout for stability [PATCH] CHROMIUM: drm/i915: repin bound framebuffers on resume [PATCH] CHROMIUM: i915: fix max backlight in normal mode [PATCH] CHROMIUM: drm/i915: Tune the rc6 value again [PATCH] CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays [PATCH] CHROMIUM: drm/i915: set lower RC6_THRESHOLD for HSW [PATCH] CHROMIUM: drm/i915: set linetime WM based on target_clock [PATCH] CHROMIUM: drivers: i915: intel_hdmi deleted unused variable [PATCH] CHROMIUM: drm/i915: Increase the wakeup up delay for PPT [PATCH] CHROMIUM: drm/i915: Don't load boot context at init time on ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Dump the contents of the GTT
On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: I've just pushed a (cairo-based!) tool to intel-gpu-tools, intel_framebuffer_dump, that should also confirm everything we've found so far - i.e. that we read and write consistently through the GTT into stolen memory. Which just leaves the step between memory and the display. Thanks. This still forces me to upgrade to a higher cairo version, not sure which to which more depends this will lead. So, the root-cause for my issue is not intel-gfx related? BIOS? Quirk needed? Other areas? ( I have seen some mm/soft-dirty fixes in mainline... Is CONFIG_MEM_SOFT_DIRTY=y an option to play with? Or how to interpret this snooped/LLC dirty outputs I had sent? ) - Sedat - P.S.: Commits in recent mainline: mm: save soft-dirty bits on file pages mm: save soft-dirty bits on swapped pages ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Invalidate TLBs for the rings after a reset
On Tue, Aug 06, 2013 at 07:01:14PM +0100, Chris Wilson wrote: After any soft gfx reset we must manually invalidate the TLBs associated with each ring. Empirically, it seems that a suspend/resume or D3-D0 cycle count as a soft reset. The symptom is that the hardware would fail to note the new address for its status page, and so it would continue to write the shadow registers and breadcrumbs into the old physical address (now used by something completely different, scary). Whereas the driver would read the new status page and never see any progress, it would appear that the GPU hung immediately upon resume. Based on a patch by naresh kumar kachhi naresh.kumar.kac...@intel.com Reported-by: Thiago Macieira thi...@kde.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64725 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Thiago reports that early testing indicates success. Anyone fancy acking this and sending this onto to stable@? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Dump the contents of the GTT
On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote: On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: I've just pushed a (cairo-based!) tool to intel-gpu-tools, intel_framebuffer_dump, that should also confirm everything we've found so far - i.e. that we read and write consistently through the GTT into stolen memory. Which just leaves the step between memory and the display. Thanks. This still forces me to upgrade to a higher cairo version, not sure which to which more depends this will lead. So, the root-cause for my issue is not intel-gfx related? BIOS? Quirk needed? Other areas? No, I am pretty sure it is our evil hardware tormenting us. Daniel made one suggestion to remove the rmw from DISPBASE i.e. revert commit 446f254566ea8911c9e19c7bc8a162fc0e53cf31 Author: Armin Reese armin.c.re...@intel.com Date: Fri Mar 30 16:20:16 2012 -0700 drm/i915: Mask reserved bits in display/sprite address registers diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2690ec..56ac7df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3370,8 +3370,7 @@ #define DISP_BASEADDR_MASK (0xf000) #define I915_LO_DISPBASE(val) (val ~DISP_BASEADDR_MASK) #define I915_HI_DISPBASE(val) (val DISP_BASEADDR_MASK) -#define I915_MODIFY_DISPBASE(reg, gfx_addr) \ - (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg +#define I915_MODIFY_DISPBASE(reg, gfx_addr) I915_WRITE((reg), (gfx_addr)) /* VBIOS flags */ #define SWF00 (dev_priv-info-display_mmio_offset + 0x71410) which avoids invoking suspiciously racy behaviour. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by default.
On Thu, Aug 15, 2013 at 05:30:37PM -0700, james.aus...@intel.com wrote: From: Todd Broch tbr...@chromium.org BUG=chrome-os-partner:6768 TEST=manual, - boot kernel 1. cat /sys/module/i915/parameters/i915_enable_rc6 - should equal 1 2. start powertop, goto 'Idle Stats' tab - make sure that the Package c-states (C6, C7) are entered at some non-trivial percentage when system is idle Signed-off-by: Todd Broch tbr...@chromium.org Change-Id: Ib557a14e3cf20b55a6670808e681ef21b1e0ed1b Reviewed-on: https://gerrit.chromium.org/gerrit/12280 Reviewed-by: Stéphane Marchesin marc...@chromium.org Drop this patch. This is incorrect against upstream. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] CHROMIUM: drm/i915: Adjust the down threshold.
On Thu, Aug 15, 2013 at 05:30:40PM -0700, james.aus...@intel.com wrote: From: Stéphane Marchesin marc...@chromium.org The thresholds for GPU reclocking are highly asymetrical. This creates an interesting phenomenon on Chrome startup where the clock ramps up very quickly, and then the blinking cursor is enough to keep it up. Obviously having the max GPU clock on the login screen is very bad for thermals. With this change, the clock goes back to its minimum frequency after a couple of seconds. You can drop the RPS changes as Stéphane has been feeding these back once he found (semi?) stable values. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Wake up DP sinks for DPCD read-based detection.
On Thu, Aug 15, 2013 at 05:30:32PM -0700, james.aus...@intel.com wrote:
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
@@ -2330,6 +2336,12 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
intel_dp-has_audio = false;
+ /* Ensure the sink is awake for DPCD/EDID reads. */
I would try using the force parameter to return the last known status to
avoid the extra busy work.
+ if (connector-dpms != DRM_MODE_DPMS_ON) {
+ /* Bypass DPCD check, since we obtain it during detection. */
+ intel_dp_do_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ }
+
if (HAS_PCH_SPLIT(dev))
status = ironlake_dp_detect(intel_dp);
else
@@ -2339,8 +2351,11 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
DRM_DEBUG_KMS(DPCD: %s\n, dpcd_hex_dump);
- if (status != connector_status_connected)
+ if (status != connector_status_connected) {
+ if (connector-dpms != DRM_MODE_DPMS_ON)
+ intel_dp_do_sink_dpms(intel_dp, connector-dpms);
return status;
+ }
intel_dp_probe_oui(intel_dp);
@@ -2356,6 +2371,11 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
if (intel_encoder-type != INTEL_OUTPUT_EDP)
intel_encoder-type = INTEL_OUTPUT_DISPLAYPORT;
+
+ /* Restore the sink state */
+ if (connector-dpms != DRM_MODE_DPMS_ON)
+ intel_dp_do_sink_dpms(intel_dp, connector-dpms);
+
return connector_status_connected;
}
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores for kernel 3.2
On Thu, Aug 15, 2013 at 05:30:39PM -0700, james.aus...@intel.com wrote: From: Simon Que s...@chromium.org marcheu added these changes in kernel 3.0: https://gerrit.chromium.org/gerrit/12367 https://gerrit.chromium.org/gerrit/12368 They were undone in kernel 3.2. This patch restores them. They were disabled with good reason. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add a try limit to avoid infinite loops
On Thu, Aug 15, 2013 at 05:30:27PM -0700, james.aus...@intel.com wrote:
From: Chris Wolfe cwo...@chromium.org
Unfortunately some combinations of hardware seem to generate successful
communications on the aux channel, which always report deferred. As a
result native_write can wind up in an infinite loop.
This hack adds a large (~10ms) retry limit to avoid a kernel panic,
while hopefully minimizing the impact on working hardware.
Signed-off-by: cwo...@chromium.org
BUG=chromium-os:34840
TEST=Manually connect DP to VGA adapter to problem system. Added display
powers up and works normally, rather than black screen and reboot.
Change-Id: Ib1b0001ca8004e65c9c5e353dbdb5e252fd88438
Reviewed-on: https://gerrit.chromium.org/gerrit/34203
Commit-Ready: Chris Wolfe cwo...@chromium.org
Reviewed-by: Chris Wolfe cwo...@chromium.org
Tested-by: Chris Wolfe cwo...@chromium.org
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e5d16bc..ac7d610 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -491,6 +491,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
uint8_t msg[20];
int msg_bytes;
uint8_t ack;
+ int try;
intel_dp_check_edp(intel_dp);
if (send_bytes 16)
@@ -501,7 +502,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
msg[3] = send_bytes - 1;
memcpy(msg[4], send, send_bytes);
msg_bytes = send_bytes + 4;
- for (;;) {
+ for (try = 0; try 100; try++) {
ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, ack, 1);
if (ret 0)
return ret;
@@ -512,6 +513,10 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
else
return -EIO;
}
+ if (try == 100) {
+ DRM_ERROR(too many retries, giving up\n);
+ return -EREMOTEIO;
+ }
If we break out here, we need to reset the hw somewhere as it will still
have the last command in the out queue.
-Chris
--
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Re: [Intel-gfx] [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8
On Fri, 16 Aug 2013, Daniel Vetter dan...@ffwll.ch wrote: On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote: Hello All- I'm trying to determine if the ChromeOS-only patches being carried by Google still make sense and are the right way to do things in the 3.11+ world, and Jesse asked me to forward the patches to the list for evaluation and potential upstreaming. I've quickly read through the pile here and there's a few things we need to look at. Ditto, and agreed. But one thing which makes assessing the patches here a bit a pain is that often there's a fixup later on again. Another pain is that sometimes the fixup is first, i.e. the series does not seem to be in the right order. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Dump the contents of the GTT
On Fri, Aug 16, 2013 at 9:39 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote: On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: I've just pushed a (cairo-based!) tool to intel-gpu-tools, intel_framebuffer_dump, that should also confirm everything we've found so far - i.e. that we read and write consistently through the GTT into stolen memory. Which just leaves the step between memory and the display. Thanks. This still forces me to upgrade to a higher cairo version, not sure which to which more depends this will lead. So, the root-cause for my issue is not intel-gfx related? BIOS? Quirk needed? Other areas? No, I am pretty sure it is our evil hardware tormenting us. Daniel made one suggestion to remove the rmw from DISPBASE i.e. revert commit 446f254566ea8911c9e19c7bc8a162fc0e53cf31 Author: Armin Reese armin.c.re...@intel.com Date: Fri Mar 30 16:20:16 2012 -0700 drm/i915: Mask reserved bits in display/sprite address registers diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2690ec..56ac7df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3370,8 +3370,7 @@ #define DISP_BASEADDR_MASK (0xf000) #define I915_LO_DISPBASE(val) (val ~DISP_BASEADDR_MASK) #define I915_HI_DISPBASE(val) (val DISP_BASEADDR_MASK) -#define I915_MODIFY_DISPBASE(reg, gfx_addr) \ - (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg +#define I915_MODIFY_DISPBASE(reg, gfx_addr) I915_WRITE((reg), (gfx_addr)) /* VBIOS flags */ #define SWF00 (dev_priv-info-display_mmio_offset + 0x71410) which avoids invoking suspiciously racy behaviour. Only that line or the complete commit? The complete commit cannot be cleanly reverted. - Sedat - ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Dump the contents of the GTT
On Fri, Aug 16, 2013 at 10:34 AM, Sedat Dilek sedat.di...@gmail.com wrote: On Fri, Aug 16, 2013 at 9:39 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote: On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: I've just pushed a (cairo-based!) tool to intel-gpu-tools, intel_framebuffer_dump, that should also confirm everything we've found so far - i.e. that we read and write consistently through the GTT into stolen memory. Which just leaves the step between memory and the display. Thanks. This still forces me to upgrade to a higher cairo version, not sure which to which more depends this will lead. So, the root-cause for my issue is not intel-gfx related? BIOS? Quirk needed? Other areas? No, I am pretty sure it is our evil hardware tormenting us. Daniel made one suggestion to remove the rmw from DISPBASE i.e. revert commit 446f254566ea8911c9e19c7bc8a162fc0e53cf31 Author: Armin Reese armin.c.re...@intel.com Date: Fri Mar 30 16:20:16 2012 -0700 drm/i915: Mask reserved bits in display/sprite address registers diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2690ec..56ac7df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3370,8 +3370,7 @@ #define DISP_BASEADDR_MASK (0xf000) #define I915_LO_DISPBASE(val) (val ~DISP_BASEADDR_MASK) #define I915_HI_DISPBASE(val) (val DISP_BASEADDR_MASK) -#define I915_MODIFY_DISPBASE(reg, gfx_addr) \ - (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg +#define I915_MODIFY_DISPBASE(reg, gfx_addr) I915_WRITE((reg), (gfx_addr)) /* VBIOS flags */ #define SWF00 (dev_priv-info-display_mmio_offset + 0x71410) which avoids invoking suspiciously racy behaviour. Only that line or the complete commit? The complete commit cannot be cleanly reverted. I have tested... 1. Linux v3.11-rc as base 2. d-i-n (up to commit 89296cd1af88b0c8cec6a4806db6db236729decc, on top of 1) 3. with the attached patch (on top of 2) NO, this did not help here. - Sedat - 0001-drm-i915-Partly-revert-446f254566ea8911c9e19c7bc8a16.patch Description: Binary data ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915: Update VGA arbiter support for newer devices
On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote: On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote: On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson alex.william...@redhat.com wrote: This is intended to add VGA arbiter support for Intel HD graphics on Core processors. The old GMCH registers no longer exist, so even though it appears that i915 participates in VGA arbitration, it doesn't work. On Intel HD graphics we already attempt to disable VGA regions of the device. This makes registering as a VGA client unnecessary since we don't intend to operate differently depending on how many VGA devices are present. We can disable VGA memory regions by clearing a memory enable bit in the VGA MSR. That only leaves VGA IO, which we update the VGA arbiter to know that we don't participate in VGA memory arbitration. We also add a hook on unload to re-enable memory and reinstate VGA memory arbitration. I would think there is still a VGA disable bit on the Intel device somewhere, we'd just need Intel to look in the docs and find it. A bit that can nuke both i/o and cmd regs. The only bit available is in the GGC and is a keyed/locked register that not only disables VGA memory and I/O, but also modifies the class code of the device. Early Core processors didn't lock this, but it's untouchable in newer ones AFAICT. Thanks, I've not found anything else in the docs. And also we _need_ VGA I/O access to make i915_disable_vga() work. It's not 100% clear whether we really need to poke at the sequencer register in modern hardware, but the docs do still list it as a mandatory step. So even if we were to have a global disable VGA I/O and mem bit we'd need to make sure we already disabled VGA eg. after resume when the BIOS had a chance to turn the VGA display back on. I think there were also some BIOSen that turned VGA display back on when closing/opening the laptop lid. Not sure what would even happen with those if totally disabled VGA I/O access. I'm not sure they actually frob with the VGA regs though. Could be they just turn on the VGA display bit in the VGA_CONTROL register. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [QA] Testing report for `drm-intel-testing` (was: Updated -next) on ww33
Summary We covered the platform: Haswell mobile, HSW desktop, HSW ULT, IvyBridge, SandyBridge, IronLake. in this circle, 13 new bugs are filed, 26 bugs are still opened, no WONTFIX bugs, 1 NOTABUG bugs,4 NOTOURBUG bugs, 3 Duplicated bugs,1 REOPENED bugs, 17 bugs are closed. Test Environment Kernel: (drm-intel-testing)93825ce151e8e2e3d6c564d50246dfd41c50aa05 Some additional commit info: Merge: bc42ac1 e91abf8 Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Fri Aug 9 20:28:36 2013 +0200 Finding New Bugs:13 bugs Bug 68171https://bugs.freedesktop.org/show_bug.cgi?id=68171 - [IVB/HSW ULT]system hang when run nightly testing Bug 68170https://bugs.freedesktop.org/show_bug.cgi?id=68170 - [ILK]igt/gem_dummy_reloc_loop/mixed causes [drm:i915_hangcheck_elapsed] *ERROR* stuck on bsd ring Bug 68166https://bugs.freedesktop.org/show_bug.cgi?id=68166 - igt/prime_nv_api/i915_nv_double_export aborted Bug 68165https://bugs.freedesktop.org/show_bug.cgi?id=68165 - [SNB IVB HSW eDP bisected]I-G-T/testdisplay -f causes eDP black Bug 68134https://bugs.freedesktop.org/show_bug.cgi?id=68134 - [SNB]igt/gem_suspend/fence-restore-untiled randomly causes call trace and *ERROR* stuck on bsd ring Bug 68004https://bugs.freedesktop.org/show_bug.cgi?id=68004 - igt/prime_self_import/with_one_bo_two_files aborted Bug 67891https://bugs.freedesktop.org/show_bug.cgi?id=67891 - igt/prime_self_import/export-vs-gem_close-race fail and causes call trace Bug 67889https://bugs.freedesktop.org/show_bug.cgi?id=67889 - [Baytrail-M] Blackscreen occurred after running xrandr setting twice Bug 67813https://bugs.freedesktop.org/show_bug.cgi?id=67813 - [HSW bisected]igt/module_reload causes [drm:hsw_unclaimed_reg_check] *ERROR* Unclaimed write to 44004 and system hang with headless, with power well disabled Bug 67734https://bugs.freedesktop.org/show_bug.cgi?id=67734 - [Baytrail-M] gt_RP0_freq_mhz value is equal to 0 Bug 67733https://bugs.freedesktop.org/show_bug.cgi?id=67733 - [Baytrail-M] VGA can't hotplug Bug 67732https://bugs.freedesktop.org/show_bug.cgi?id=67732 - [Baytrail-M] eDP and VGA can't light up simultaneously Bug 67731https://bugs.freedesktop.org/show_bug.cgi?id=67731 - [Baytrail-M] system can't resume from S3/S4 Opened Bugs: 26 bugs Bug 67520https://bugs.freedesktop.org/show_bug.cgi?id=67520 - [HSW ULT] System boots with *ERROR* conflict detected with stolen region: [0xada0 - 0xafa0] Bug 67462https://bugs.freedesktop.org/show_bug.cgi?id=67462 - [SNB] Call trace appears after system boots with DP Bug 67345https://bugs.freedesktop.org/show_bug.cgi?id=67345 - [BayTrail-M] [drm:intel_pipe_config_compare] *ERROR* mismatch in clock (expected 146250, found 0) Bug 67287https://bugs.freedesktop.org/show_bug.cgi?id=67287 - igt/gem_flink_race fails Bug 67243https://bugs.freedesktop.org/show_bug.cgi?id=67243 - [ILK]igt/kms_render/gpu-blit randomly causes system hang Bug 67030https://bugs.freedesktop.org/show_bug.cgi?id=67030 - [HSW] no modes bigger than 1080p in the parsed EDID for 4k TV on both HDMI/VGA Bug 67027https://bugs.freedesktop.org/show_bug.cgi?id=67027 - [HSW] some modes oversan, on a 4K HDMI TV Bug 66844https://bugs.freedesktop.org/show_bug.cgi?id=66844 - [SNB Regression]*ERROR* conflict detected with stolen region: [0xcba0 - 0xcfa0] Bug 66726https://bugs.freedesktop.org/show_bug.cgi?id=66726 - [PNV Regression]*ERROR* conflict detected with stolen region: [0x7f80 - 0x8000] Bug 66301https://bugs.freedesktop.org/show_bug.cgi?id=66301 - [HSW mobile] resume from s4 sporadically causes call trace and machine is reachable Bug 65995https://bugs.freedesktop.org/show_bug.cgi?id=65995 - [HSW mobile] eDP can't light up when boot up Bug 65927https://bugs.freedesktop.org/show_bug.cgi?id=65927 - [HSW] crash when vga output set to mirror mode Bug 65700https://bugs.freedesktop.org/show_bug.cgi?id=65700 - [SNB]3[drm:ironlake_disable_pch_transcoder] *ERROR* failed to disable transcoder 0 Bug 65496https://bugs.freedesktop.org/show_bug.cgi?id=65496 - [HSW] Probabilistic resume from s4 causes call trace and system hang, with warm boot Bug 64415https://bugs.freedesktop.org/show_bug.cgi?id=64415 - [ILK] Some modes unable to light up on DP display Bug 64379https://bugs.freedesktop.org/show_bug.cgi?id=64379 - [HSW desktop bisected] ddi pll tracking botch-up due to vt-switchless resume Bug 63981https://bugs.freedesktop.org/show_bug.cgi?id=63981 - MacBook Pro retina 13 inch early 2013 jittery display Bug 61041https://bugs.freedesktop.org/show_bug.cgi?id=61041 - [Pineview]I-G-T/testdisplay VGA 1600x1200 65Hz messing the screen Bug 60002https://bugs.freedesktop.org/show_bug.cgi?id=60002 - [PNV]I-G-T/kms_flip subtest：'blocking-absolute-wf_vblank' fail Bug 5https://bugs.freedesktop.org/show_bug.cgi?id=5 - [ILK,IVB]kms_flip error: inter-flip ts jitter Bug 59836https://bugs.freedesktop.org/show_bug.cgi?id=59836 -
[Intel-gfx] [QA] Testing report for `drm-intel-testing` (was: Updated -next) on ww33
Summary We covered the platform: Haswell mobile, HSW desktop, HSW ULT, IvyBridge, SandyBridge, IronLake. in this circle, 13 new bugs are filed, 26 bugs are still opened, no WONTFIX bugs, 1 NOTABUG bugs,4 NOTOURBUG bugs, 3 Duplicated bugs,1 REOPENED bugs, 17 bugs are closed. Test Environment Kernel: (drm-intel-testing)93825ce151e8e2e3d6c564d50246dfd41c50aa05 Some additional commit info: Merge: bc42ac1 e91abf8 Author: Daniel Vetter daniel.vet...@ffwll.chmailto:daniel.vet...@ffwll.ch Date: Fri Aug 9 20:28:36 2013 +0200 Finding New Bugs:13 bugs Bug 68171https://bugs.freedesktop.org/show_bug.cgi?id=68171 - [IVB/HSW ULT]system hang when run nightly testing Bug 68170https://bugs.freedesktop.org/show_bug.cgi?id=68170 - [ILK]igt/gem_dummy_reloc_loop/mixed causes [drm:i915_hangcheck_elapsed] *ERROR* stuck on bsd ring Bug 68166https://bugs.freedesktop.org/show_bug.cgi?id=68166 - igt/prime_nv_api/i915_nv_double_export aborted Bug 68165https://bugs.freedesktop.org/show_bug.cgi?id=68165 - [SNB IVB HSW eDP bisected]I-G-T/testdisplay -f causes eDP black Bug 68134https://bugs.freedesktop.org/show_bug.cgi?id=68134 - [SNB]igt/gem_suspend/fence-restore-untiled randomly causes call trace and *ERROR* stuck on bsd ring Bug 68004https://bugs.freedesktop.org/show_bug.cgi?id=68004 - igt/prime_self_import/with_one_bo_two_files aborted Bug 67891https://bugs.freedesktop.org/show_bug.cgi?id=67891 - igt/prime_self_import/export-vs-gem_close-race fail and causes call trace Bug 67889https://bugs.freedesktop.org/show_bug.cgi?id=67889 - [Baytrail-M] Blackscreen occurred after running xrandr setting twice Bug 67813https://bugs.freedesktop.org/show_bug.cgi?id=67813 - [HSW bisected]igt/module_reload causes [drm:hsw_unclaimed_reg_check] *ERROR* Unclaimed write to 44004 and system hang with headless, with power well disabled Bug 67734https://bugs.freedesktop.org/show_bug.cgi?id=67734 - [Baytrail-M] gt_RP0_freq_mhz value is equal to 0 Bug 67733https://bugs.freedesktop.org/show_bug.cgi?id=67733 - [Baytrail-M] VGA can't hotplug Bug 67732https://bugs.freedesktop.org/show_bug.cgi?id=67732 - [Baytrail-M] eDP and VGA can't light up simultaneously Bug 67731https://bugs.freedesktop.org/show_bug.cgi?id=67731 - [Baytrail-M] system can't resume from S3/S4 Opened Bugs: 26 bugs Bug 67520https://bugs.freedesktop.org/show_bug.cgi?id=67520 - [HSW ULT] System boots with *ERROR* conflict detected with stolen region: [0xada0 - 0xafa0] Bug 67462https://bugs.freedesktop.org/show_bug.cgi?id=67462 - [SNB] Call trace appears after system boots with DP Bug 67345https://bugs.freedesktop.org/show_bug.cgi?id=67345 - [BayTrail-M] [drm:intel_pipe_config_compare] *ERROR* mismatch in clock (expected 146250, found 0) Bug 67287https://bugs.freedesktop.org/show_bug.cgi?id=67287 - igt/gem_flink_race fails Bug 67243https://bugs.freedesktop.org/show_bug.cgi?id=67243 - [ILK]igt/kms_render/gpu-blit randomly causes system hang Bug 67030https://bugs.freedesktop.org/show_bug.cgi?id=67030 - [HSW] no modes bigger than 1080p in the parsed EDID for 4k TV on both HDMI/VGA Bug 67027https://bugs.freedesktop.org/show_bug.cgi?id=67027 - [HSW] some modes oversan, on a 4K HDMI TV Bug 66844https://bugs.freedesktop.org/show_bug.cgi?id=66844 - [SNB Regression]*ERROR* conflict detected with stolen region: [0xcba0 - 0xcfa0] Bug 66726https://bugs.freedesktop.org/show_bug.cgi?id=66726 - [PNV Regression]*ERROR* conflict detected with stolen region: [0x7f80 - 0x8000] Bug 66301https://bugs.freedesktop.org/show_bug.cgi?id=66301 - [HSW mobile] resume from s4 sporadically causes call trace and machine is reachable Bug 65995https://bugs.freedesktop.org/show_bug.cgi?id=65995 - [HSW mobile] eDP can't light up when boot up Bug 65927https://bugs.freedesktop.org/show_bug.cgi?id=65927 - [HSW] crash when vga output set to mirror mode Bug 65700https://bugs.freedesktop.org/show_bug.cgi?id=65700 - [SNB]3[drm:ironlake_disable_pch_transcoder] *ERROR* failed to disable transcoder 0 Bug 65496https://bugs.freedesktop.org/show_bug.cgi?id=65496 - [HSW] Probabilistic resume from s4 causes call trace and system hang, with warm boot Bug 64415https://bugs.freedesktop.org/show_bug.cgi?id=64415 - [ILK] Some modes unable to light up on DP display Bug 64379https://bugs.freedesktop.org/show_bug.cgi?id=64379 - [HSW desktop bisected] ddi pll tracking botch-up due to vt-switchless resume Bug 63981https://bugs.freedesktop.org/show_bug.cgi?id=63981 - MacBook Pro retina 13 inch early 2013 jittery display Bug 61041https://bugs.freedesktop.org/show_bug.cgi?id=61041 - [Pineview]I-G-T/testdisplay VGA 1600x1200 65Hz messing the screen Bug 60002https://bugs.freedesktop.org/show_bug.cgi?id=60002 - [PNV]I-G-T/kms_flip subtest：'blocking-absolute-wf_vblank' fail Bug 5https://bugs.freedesktop.org/show_bug.cgi?id=5 - [ILK,IVB]kms_flip error: inter-flip ts jitter Bug 59836https://bugs.freedesktop.org/show_bug.cgi?id=59836
Re: [Intel-gfx] [igt PATCH 3/4] lib: add subtest extra command line option handling
On Tue, 2013-08-06 at 11:09 +0200, Daniel Vetter wrote:
On Mon, Aug 05, 2013 at 02:45:25PM +0300, Imre Deak wrote:
At the moment any command line option handling done by tests will
interfere with the option handling of the subtest interface. To fix this
add a new version of the subtest_init function accepting optional short
and long command line options. Merge these together with the subtest
interface's own long options and handle both together in the same
getopt_long call.
Signed-off-by: Imre Deak imre.d...@intel.com
Hm, I've thought that getopt would filter the passed-in argv/argc arrays
and we could run a second getopt afterwards without too much interfence
(maybe we need to reset a few global getop state variables). But I'm not
sure since I've never tried it out. Am I wrong?
Afaics getopt itself can't handle the long options (which we already
have for subtests), it'll try to parse each character of the long option
as a short one.
We could still do the scanning twice by always using getopt_long, but
there I don't like the fact that we would have to set opterr=0 and
silently ignore invalid options. Also I thought that later we could add
a check for clashing test case/subtest options and that's not possible
by scanning twice.
--Imre
-Daniel
---
lib/drmtest.c | 85
---
lib/drmtest.h | 6 +
2 files changed, 81 insertions(+), 10 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index afbaa35..7a68091 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -657,7 +657,21 @@ void drmtest_stop_signal_helper(void)
static bool list_subtests = false;
static char *run_single_subtest = NULL;
-void drmtest_subtest_init(int argc, char **argv)
+static void print_usage(const char *command_str, const char *help_str,
+ bool output_on_stderr)
+{
+ FILE *f = output_on_stderr ? stderr : stdout;
+
+ fprintf(f, Usage: %s [OPTIONS]\n
+--list-subtests\n
+--run-subtest pattern\n
+ %s\n, command_str, help_str);
+}
+
+int drmtest_subtest_init_parse_opts(int argc, char **argv, const char
*opts,
+ struct option *long_opts,
+ const char *help_str,
+ drmtest_opt_handler_t opt_handler)
{
int c, option_index = 0;
static struct option long_options[] = {
@@ -665,24 +679,75 @@ void drmtest_subtest_init(int argc, char **argv)
{run-subtest, 1, 0, 'r'},
{NULL, 0, 0, 0,}
};
+ struct option help_opt =
+ {help, 0, 0, 'h'};
+ const char *command_str;
+ char *short_opts;
+ struct option *combined_opts;
+ int extra_opts;
+ int all_opts;
+ int ret = 0;
+
+ command_str = argv[0];
+ if (strrchr(command_str, '/'))
+ command_str = strrchr(command_str, '/') + 1;
+
+ all_opts = 0;
+ while (long_opts long_opts[all_opts].name)
+ all_opts++;
+ extra_opts = all_opts;
+ if (help_str)
+ all_opts++;
+ all_opts += ARRAY_SIZE(long_options);
+
+ combined_opts = malloc(all_opts * sizeof(*combined_opts));
+ memcpy(combined_opts, long_opts, extra_opts * sizeof(*combined_opts));
+ if (help_str) {
+ combined_opts[extra_opts] = help_opt;
+ extra_opts++;
+ }
+ memcpy(combined_opts[extra_opts], long_options,
+ ARRAY_SIZE(long_options) * sizeof(*combined_opts));
- /* supress getopt errors about unknown options */
- opterr = 0;
- /* restrict the option parsing to long option names to avoid collisions
-* with options the test declares */
- while((c = getopt_long(argc, argv, ,
- long_options, option_index)) != -1) {
+ ret = asprintf(short_opts, %s%s,
+ opts ? opts : , help_str ? h : );
+ assert(ret = 0);
+
+ while ((c = getopt_long(argc, argv, short_opts, combined_opts,
+ option_index)) != -1) {
switch(c) {
case 'l':
- list_subtests = true;
- goto out;
+ if (!run_single_subtest)
+ list_subtests = true;
+ break;
case 'r':
- run_single_subtest = strdup(optarg);
+ if (!list_subtests)
+ run_single_subtest = strdup(optarg);
+ break;
+ case '?':
+ case 'h':
+ print_usage(command_str, help_str, c == '?');
+ ret = c == '?' ? -2 : -1;
goto out;
+ default:
+ ret = opt_handler(c, option_index);
+ if (ret)
+ goto out;
}
}
out:
[Intel-gfx] [PATCH] Add second DRI driver name (DRI2DriverVDPAU)
libvdpau uses second DRI driver name to determine which VDPAU driver
to use. This patch will allow libvdpau choose libvdpau_i965.so on systems
with Intel GPUs, libvdpau_nvidia.so on those with nVidia ones, and so on.
I'm experimenting now with generic vdpau driver using OpenGL/VA-API,
it would be convenient to have this driver selection working without manual
driver selection.
Signed-off-by: Rinat ibragimovri...@mail.ru
---
src/sna/sna_dri.c |5 +++--
src/uxa/intel_dri.c |5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index 1569251..0ba373d 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -2299,7 +2299,7 @@ bool sna_dri_open(struct sna *sna, ScreenPtr screen)
DRI2InfoRec info;
int major = 1, minor = 0;
#if DRI2INFOREC_VERSION = 4
- const char *driverNames[1];
+ const char *driverNames[2];
#endif
DBG((%s()\n, __FUNCTION__));
@@ -2336,9 +2336,10 @@ bool sna_dri_open(struct sna *sna, ScreenPtr screen)
info.ScheduleSwap = sna_dri_schedule_swap;
info.GetMSC = sna_dri_get_msc;
info.ScheduleWaitMSC = sna_dri_schedule_wait_msc;
- info.numDrivers = 1;
+ info.numDrivers = 2;
info.driverNames = driverNames;
driverNames[0] = info.driverName;
+ driverNames[1] = info.driverName;
#endif
#if DRI2INFOREC_VERSION = 6
diff --git a/src/uxa/intel_dri.c b/src/uxa/intel_dri.c
index 0370034..2d33380 100644
--- a/src/uxa/intel_dri.c
+++ b/src/uxa/intel_dri.c
@@ -1553,7 +1553,7 @@ Bool I830DRI2ScreenInit(ScreenPtr screen)
int dri2_major = 1;
int dri2_minor = 0;
#if DRI2INFOREC_VERSION = 4
- const char *driverNames[1];
+ const char *driverNames[2];
#endif
if (intel-force_fallback) {
@@ -1620,9 +1620,10 @@ Bool I830DRI2ScreenInit(ScreenPtr screen)
info.ScheduleSwap = I830DRI2ScheduleSwap;
info.GetMSC = I830DRI2GetMSC;
info.ScheduleWaitMSC = I830DRI2ScheduleWaitMSC;
- info.numDrivers = 1;
+ info.numDrivers = 2;
info.driverNames = driverNames;
driverNames[0] = info.driverName;
+ driverNames[1] = info.driverName;
#endif
return DRI2ScreenInit(screen, info);
--
1.7.10.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt PATCH 3/4] lib: add subtest extra command line option handling
On Fri, Aug 16, 2013 at 02:07:07PM +0300, Imre Deak wrote: On Tue, 2013-08-06 at 11:09 +0200, Daniel Vetter wrote: On Mon, Aug 05, 2013 at 02:45:25PM +0300, Imre Deak wrote: At the moment any command line option handling done by tests will interfere with the option handling of the subtest interface. To fix this add a new version of the subtest_init function accepting optional short and long command line options. Merge these together with the subtest interface's own long options and handle both together in the same getopt_long call. Signed-off-by: Imre Deak imre.d...@intel.com Hm, I've thought that getopt would filter the passed-in argv/argc arrays and we could run a second getopt afterwards without too much interfence (maybe we need to reset a few global getop state variables). But I'm not sure since I've never tried it out. Am I wrong? Afaics getopt itself can't handle the long options (which we already have for subtests), it'll try to parse each character of the long option as a short one. We could still do the scanning twice by always using getopt_long, but there I don't like the fact that we would have to set opterr=0 and silently ignore invalid options. Also I thought that later we could add a check for clashing test case/subtest options and that's not possible by scanning twice. Hm, just scanning with getopt_long twice was actually my idea. It's a bit ugly that we then can't check for unknown options. But since you have all already solved I think we could just move ahead with your patch here. So please push. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Lower threshold for pixel doubling.
On Fri, Aug 16, 2013 at 09:20:49AM +0100, Chris Wilson wrote: On Mon, May 20, 2013 at 11:15:08AM -0700, Stuart Abercrombie wrote: 90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get pixel doubling on Pineview, which it needs to avoid underruns, so lower this to 85%. Signed-off-by: Stuart Abercrombie sabercrom...@chromium.org I've not found any rationale in the gen3 bspec describing what the upper limit on usuable bw is. Nothing to support the old value nor the new, so Acked-by: Chris Wilson ch...@chris-wilson.co.uk And quick before Daniel converts the double-wide tracking to pipe_config... Erhm, we've already fixed this for real in commit 257a7ffcfaf68718c963db6e9978d1f4f647986b Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Fri Jul 26 08:35:42 2013 +0200 drm/i915: fix pnv display core clock readout out and the fact that the above mentioned mode with a pixelclock of 167MHz is right at the display core clock of 166MHz (per spec) suggests that even the 10% margin we currently have is massive overkill. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Invalidate TLBs for the rings after a reset
On Fri, Aug 16, 2013 at 08:31:35AM +0100, Chris Wilson wrote: On Tue, Aug 06, 2013 at 07:01:14PM +0100, Chris Wilson wrote: After any soft gfx reset we must manually invalidate the TLBs associated with each ring. Empirically, it seems that a suspend/resume or D3-D0 cycle count as a soft reset. The symptom is that the hardware would fail to note the new address for its status page, and so it would continue to write the shadow registers and breadcrumbs into the old physical address (now used by something completely different, scary). Whereas the driver would read the new status page and never see any progress, it would appear that the GPU hung immediately upon resume. Based on a patch by naresh kumar kachhi naresh.kumar.kac...@intel.com Reported-by: Thiago Macieira thi...@kde.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64725 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Thiago reports that early testing indicates success. Anyone fancy acking this and sending this onto to stable@? Picked up for -fixes, thanks for the patch. I'll let it hang there a bit though before forwarding, so I don't plan to update the -fixes pull request I've just recently sent out. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 00/15] drm/i915: Baytrail MIPI DSI support
Hi all, v2 of http://mid.gmane.org/cover.1376397804.git.jani.nik...@intel.com Patch 10/15 is new, fixing PLL assertions for DSI PLL. BR, Jani. Jani Nikula (10): drm/i915: add more VLV IOSF sideband ports accessors drm/i915: add VLV pipeconf bit definition for DSI PLL lock drm/i915: add MIPI DSI register definitions drm/i915: add MIPI DSI output type and subtypes drm/i915: add structs for MIPI DSI output drm/i915: add MIPI DSI command sending routines drm/i915: add basic MIPI DSI output support drm/i915: fix PLL assertions for DSI PLL drm/i915: don't enable DPLL for DSI drm/i915: initialize DSI output on VLV Shobhit Kumar (4): drm: add MIPI DSI encoder and connector types drm/i915: Band Gap WA drm/i915: Parse the MIPI related VBT Block and store relevant info drm/i915: add AUO MIPI DSI display sub-encoder ymohanma (1): drm/i915: add VLV DSI PLL Calculations drivers/gpu/drm/drm_crtc.c |2 + drivers/gpu/drm/i915/Makefile |4 + drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++ drivers/gpu/drm/i915/i915_drv.h| 13 + drivers/gpu/drm/i915/i915_reg.h| 425 +++ drivers/gpu/drm/i915/intel_bios.c | 16 + drivers/gpu/drm/i915/intel_bios.h | 41 +++ drivers/gpu/drm/i915/intel_display.c | 94 +++-- drivers/gpu/drm/i915/intel_drv.h |7 +- drivers/gpu/drm/i915/intel_dsi.c | 594 drivers/gpu/drm/i915/intel_dsi.h | 105 ++ drivers/gpu/drm/i915/intel_dsi_cmd.c | 442 drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 ++ drivers/gpu/drm/i915/intel_dsi_pll.c | 310 + drivers/gpu/drm/i915/intel_sideband.c | 56 +++ include/uapi/drm/drm_mode.h|2 + 16 files changed, 2374 insertions(+), 28 deletions(-) create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/15] drm: add MIPI DSI encoder and connector types
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/drm_crtc.c |2 ++
include/uapi/drm/drm_mode.h |2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index fc83bb9..8768c5f 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -209,6 +209,7 @@ static struct drm_conn_prop_enum_list
drm_connector_enum_list[] =
{ DRM_MODE_CONNECTOR_TV, TV, 0 },
{ DRM_MODE_CONNECTOR_eDP, eDP, 0 },
{ DRM_MODE_CONNECTOR_VIRTUAL, Virtual, 0},
+ { DRM_MODE_CONNECTOR_DSI, DSI, 0},
};
static const struct drm_prop_enum_list drm_encoder_enum_list[] =
@@ -218,6 +219,7 @@ static const struct drm_prop_enum_list
drm_encoder_enum_list[] =
{ DRM_MODE_ENCODER_LVDS, LVDS },
{ DRM_MODE_ENCODER_TVDAC, TV },
{ DRM_MODE_ENCODER_VIRTUAL, Virtual },
+ { DRM_MODE_ENCODER_DSI, DSI },
};
const char *drm_get_encoder_name(const struct drm_encoder *encoder)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 53db7ce..589114e 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -165,6 +165,7 @@ struct drm_mode_get_plane_res {
#define DRM_MODE_ENCODER_LVDS 3
#define DRM_MODE_ENCODER_TVDAC 4
#define DRM_MODE_ENCODER_VIRTUAL 5
+#define DRM_MODE_ENCODER_DSI 6
struct drm_mode_get_encoder {
__u32 encoder_id;
@@ -203,6 +204,7 @@ struct drm_mode_get_encoder {
#define DRM_MODE_CONNECTOR_TV 13
#define DRM_MODE_CONNECTOR_eDP 14
#define DRM_MODE_CONNECTOR_VIRTUAL 15
+#define DRM_MODE_CONNECTOR_DSI 16
struct drm_mode_get_connector {
--
1.7.9.5
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/15] drm/i915: add VLV pipeconf bit definition for DSI PLL lock
Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/i915_reg.h |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b417a8c..2f8e341 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2972,6 +2972,7 @@ #define PIPECONF_DISABLE 0 #define PIPECONF_DOUBLE_WIDE (130) #define I965_PIPECONF_ACTIVE (130) +#define PIPECONF_DSI_PLL_LOCKED (129) /* vlv only */ #define PIPECONF_FRAME_START_DELAY_MASK (327) #define PIPECONF_SINGLE_WIDE 0 #define PIPECONF_PIPE_UNLOCKED 0 -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/15] drm/i915: add MIPI DSI register definitions
Add definitions for VLV MIPI DSI registers. v2: Small fixes per Ville's review comments. Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 410 +++ 1 file changed, 410 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f8e341..9879619 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5104,4 +5104,414 @@ #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) +/* VLV MIPI registers */ + +#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) +#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) +#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL) +#define DPI_ENABLE(1 31) /* A + B */ +#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 +#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf 27) +#define DUAL_LINK_MODE_MASK (1 26) +#define DUAL_LINK_MODE_FRONT_BACK (0 26) +#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 26) +#define DITHERING_ENABLE (1 25) /* A + B */ +#define FLOPPED_HSTX (1 23) +#define DE_INVERT (1 19) /* XXX */ +#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 +#define MIPIA_FLISDSI_DELAY_COUNT_MASK(0xf 18) +#define AFE_LATCHOUT (1 17) +#define LP_OUTPUT_HOLD(1 16) +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 15) +#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 +#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf 11) +#define CSB_SHIFT 9 +#define CSB_MASK (3 9) +#define CSB_20MHZ (0 9) +#define CSB_10MHZ (1 9) +#define CSB_40MHZ (2 9) +#define BANDGAP_MASK (1 8) +#define BANDGAP_PNW_CIRCUIT (0 8) +#define BANDGAP_LNC_CIRCUIT (1 8) +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK(7 5) +#define TEARING_EFFECT_DELAY (1 4) /* A + B */ +#define TEARING_EFFECT_SHIFT 2 /* A + B */ +#define TEARING_EFFECT_MASK (3 2) +#define TEARING_EFFECT_OFF(0 2) +#define TEARING_EFFECT_DSI(1 2) +#define TEARING_EFFECT_GPIO (2 2) +#define LANE_CONFIGURATION_SHIFT 0 +#define LANE_CONFIGURATION_MASK (3 0) +#define LANE_CONFIGURATION_4LANE (0 0) +#define LANE_CONFIGURATION_DUAL_LINK_A(1 0) +#define LANE_CONFIGURATION_DUAL_LINK_B(2 0) + +#define _MIPIA_TEARING_CTRL(VLV_DISPLAY_BASE + 0x61194) +#define _MIPIB_TEARING_CTRL(VLV_DISPLAY_BASE + 0x61704) +#define MIPI_TEARING_CTRL(pipe)_PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) +#define TEARING_EFFECT_DELAY_SHIFT0 +#define TEARING_EFFECT_DELAY_MASK (0x 0) + +/* XXX: all bits reserved */ +#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) + +/* MIPI DSI Controller and D-PHY registers */ + +#define _MIPIA_DEVICE_READY(VLV_DISPLAY_BASE + 0xb000) +#define _MIPIB_DEVICE_READY(VLV_DISPLAY_BASE + 0xb800) +#define MIPI_DEVICE_READY(pipe)_PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) +#define BUS_POSSESSION(1 3) /* set to give bus to receiver */ +#define ULPS_STATE_MASK (3 1) +#define ULPS_STATE_ENTER (2 1) +#define ULPS_STATE_EXIT (1 1) +#define ULPS_STATE_NORMAL_OPERATION (0 1) +#define DEVICE_READY (1 0) + +#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) +#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) +#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT) +#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008) +#define _MIPIB_INTR_EN
[Intel-gfx] [PATCH v2 07/15] drm/i915: add MIPI DSI command sending routines
v2: Rebase due to register bit definition change.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/intel_dsi_cmd.c | 442 ++
drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 +
3 files changed, 552 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c
create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b8449a8..8bffd29 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_display.o \
intel_crt.o \
intel_lvds.o \
+ intel_dsi_cmd.o \
intel_bios.o \
intel_ddi.o \
intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
new file mode 100644
index 000..aca41c9
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula jani.nik...@intel.com
+ */
+
+#include linux/export.h
+#include drm/drmP.h
+#include drm/drm_crtc.h
+#include video/mipi_display.h
+#include i915_drv.h
+#include intel_drv.h
+#include intel_dsi.h
+#include intel_dsi_cmd.h
+
+/*
+ * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
+ * MIPI_COMMAND_ADDRESS registers.
+ *
+ * Apparently these registers provide a MIPI adapter level way to send (lots
of)
+ * commands and data to the receiver, without having to write the commands and
+ * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
+ *
+ * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
+ * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
+ * framebuffer in command mode displays) these are just an optimization that
can
+ * come later.
+ *
+ * For memory writes, these should probably be used for performance.
+ */
+
+static void print_stat(struct intel_dsi *intel_dsi)
+{
+ struct drm_encoder *encoder = intel_dsi-base.base;
+ struct drm_device *dev = encoder-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder-crtc);
+ enum pipe pipe = intel_crtc-pipe;
+ u32 val;
+
+ val = I915_READ(MIPI_INTR_STAT(pipe));
+
+#define STAT_BIT(val, bit) (val) (bit) ? #bit :
+ DRM_DEBUG_KMS(MIPI_INTR_STAT(%d) = %08x
+
%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s
+ \n, pipe, val,
+ STAT_BIT(val, TEARING_EFFECT),
+ STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
+ STAT_BIT(val, GEN_READ_DATA_AVAIL),
+ STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
+ STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
+ STAT_BIT(val, RX_PROT_VIOLATION),
+ STAT_BIT(val, RX_INVALID_TX_LENGTH),
+ STAT_BIT(val, ACK_WITH_NO_ERROR),
+ STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
+ STAT_BIT(val, LP_RX_TIMEOUT),
+ STAT_BIT(val, HS_TX_TIMEOUT),
+ STAT_BIT(val, DPI_FIFO_UNDERRUN),
+ STAT_BIT(val, LOW_CONTENTION),
+ STAT_BIT(val, HIGH_CONTENTION),
+ STAT_BIT(val, TXDSI_VC_ID_INVALID),
+ STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
+ STAT_BIT(val, TXCHECKSUM_ERROR),
+ STAT_BIT(val, TXECC_MULTIBIT_ERROR),
+ STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
+ STAT_BIT(val, TXFALSE_CONTROL_ERROR),
+ STAT_BIT(val, RXDSI_VC_ID_INVALID),
[Intel-gfx] [PATCH v2 09/15] drm/i915: add VLV DSI PLL Calculations
From: ymohanma yogesh.mohan.marimu...@intel.com
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
Signed-off-by: ymohanma yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/i915_reg.h | 10 ++
drivers/gpu/drm/i915/intel_dsi.c |7 +
drivers/gpu/drm/i915/intel_dsi.h |3 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 310 ++
5 files changed, 331 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5864c5b..65e60d2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_lvds.o \
intel_dsi.o \
intel_dsi_cmd.o \
+ intel_dsi_pll.o \
intel_bios.o \
intel_ddi.o \
intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9879619..5feed04 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -390,6 +390,16 @@
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
+/* vlv2 north clock has */
+#define CCK_REG_DSI_PLL_FUSE 0x44
+#define CCK_REG_DSI_PLL_CONTROL0x48
+#define DSI_PLL_VCO_EN(1 31)
+#define DSI_PLL_LDO_GATE (1 30)
+#define DSI_PLL_P1_POST_DIV_SHIFT 17
+#define DSI_PLL_P1_POST_DIV_MASK (0x1ff 17)
+#define DSI_PLL_LOCK (1 0)
+#define CCK_REG_DSI_PLL_DIVIDER0x4c
+
/*
* DPIO - a special bus for various display related registers to hide behind
*
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d7eddbd..352ff46 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder
*encoder,
static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
{
DRM_DEBUG_KMS(\n);
+
+ vlv_enable_dsi_pll(encoder);
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -161,6 +163,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
static void intel_dsi_post_disable(struct intel_encoder *encoder)
{
DRM_DEBUG_KMS(\n);
+
+ vlv_disable_dsi_pll(encoder);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -284,6 +288,9 @@ static void intel_dsi_mode_set(struct intel_encoder
*intel_encoder)
DRM_DEBUG_KMS(pipe %d\n, pipe);
+ /* Update the DSI PLL */
+ vlv_enable_dsi_pll(intel_encoder);
+
/* escape clock divider, 20MHz, shared for A and C. device ready must be
* off when doing this! txclkesc? */
tmp = I915_READ(MIPI_CTRL(0));
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f308269..c7765f3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -96,4 +96,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
+extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
+
#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
new file mode 100644
index 000..c50a90e
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ *
[Intel-gfx] [PATCH v2 10/15] drm/i915: fix PLL assertions for DSI PLL
For DSI, we need to be asserting DSI PLL, not DPLL.
This is a somewhat stopgap implementation. It's slightly ugly to have to
pass the dsi parameter to intel_enable_pipe().
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 44 +++---
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 00114a5..2264a13 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -929,6 +929,24 @@ void assert_pll(struct drm_i915_private *dev_priv,
state_string(state), state_string(cur_state));
}
+/* XXX: the dsi pll is shared between MIPI DSI ports */
+static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
+{
+ u32 val;
+ bool cur_state;
+
+ mutex_lock(dev_priv-dpio_lock);
+ val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+ mutex_unlock(dev_priv-dpio_lock);
+
+ cur_state = val DSI_PLL_VCO_EN;
+ WARN(cur_state != state,
+DSI PLL state assertion failure (expected %s, current %s)\n,
+state_string(state), state_string(cur_state));
+}
+#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
+#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
+
struct intel_shared_dpll *
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
{
@@ -1661,7 +1679,7 @@ static void lpt_disable_pch_transcoder(struct
drm_i915_private *dev_priv)
* returning.
*/
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe
pipe,
- bool pch_port)
+ bool pch_port, bool dsi)
{
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
@@ -1683,7 +1701,10 @@ static void intel_enable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe,
* need the check.
*/
if (!HAS_PCH_SPLIT(dev_priv-dev))
- assert_pll_enabled(dev_priv, pipe);
+ if (dsi)
+ assert_dsi_pll_enabled(dev_priv);
+ else
+ assert_pll_enabled(dev_priv, pipe);
else {
if (pch_port) {
/* if driving the PCH, we need FDI enabled */
@@ -3280,7 +3301,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
intel_enable_pipe(dev_priv, pipe,
- intel_crtc-config.has_pch_encoder);
+ intel_crtc-config.has_pch_encoder, false);
intel_enable_plane(dev_priv, plane, pipe);
intel_enable_planes(crtc);
intel_crtc_update_cursor(crtc, true);
@@ -3388,7 +3409,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_ddi_enable_transcoder_func(crtc);
intel_enable_pipe(dev_priv, pipe,
- intel_crtc-config.has_pch_encoder);
+ intel_crtc-config.has_pch_encoder, false);
intel_enable_plane(dev_priv, plane, pipe);
intel_enable_planes(crtc);
intel_crtc_update_cursor(crtc, true);
@@ -3646,6 +3667,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc-pipe;
int plane = intel_crtc-plane;
+ bool is_dsi;
WARN_ON(!crtc-enabled);
@@ -3659,6 +3681,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder-pre_pll_enable)
encoder-pre_pll_enable(encoder);
+ is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
vlv_enable_pll(intel_crtc);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3669,7 +3693,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
- intel_enable_pipe(dev_priv, pipe, false);
+ intel_enable_pipe(dev_priv, pipe, false, is_dsi);
intel_enable_plane(dev_priv, plane, pipe);
intel_enable_planes(crtc);
intel_crtc_update_cursor(crtc, true);
@@ -3707,7 +3731,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
- intel_enable_pipe(dev_priv, pipe, false);
+ intel_enable_pipe(dev_priv, pipe, false, false);
intel_enable_plane(dev_priv, plane, pipe);
intel_enable_planes(crtc);
/* The fixup needs to happen before cursor is enabled */
@@ -6494,8 +6518,12 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
if (!crtc-enabled || !intel_crtc-active)
return;
- if (!HAS_PCH_SPLIT(dev_priv-dev))
- assert_pll_enabled(dev_priv, pipe);
+ if (!HAS_PCH_SPLIT(dev_priv-dev)) {
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+ assert_dsi_pll_enabled(dev_priv);
[Intel-gfx] [PATCH v2 11/15] drm/i915: don't enable DPLL for DSI
DPLL is not needed for DSI
v2: Rebase due to added DSI PLL assertion patch.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 48 --
1 file changed, 29 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2264a13..336bee4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3683,7 +3683,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
- vlv_enable_pll(intel_crtc);
+ if (!is_dsi)
+ vlv_enable_pll(intel_crtc);
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder-pre_enable)
@@ -3798,7 +3799,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
if (encoder-post_disable)
encoder-post_disable(encoder);
- i9xx_disable_pll(dev_priv, pipe);
+ if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+ i9xx_disable_pll(dev_priv, pipe);
intel_crtc-active = false;
intel_update_fbc(dev);
@@ -4866,7 +4868,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
intel_clock_t clock, reduced_clock;
u32 dspcntr;
bool ok, has_reduced_clock = false;
- bool is_lvds = false;
+ bool is_lvds = false, is_dsi = false;
struct intel_encoder *encoder;
const intel_limit_t *limit;
int ret;
@@ -4876,6 +4878,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
case INTEL_OUTPUT_LVDS:
is_lvds = true;
break;
+ case INTEL_OUTPUT_DSI:
+ is_dsi = true;
+ break;
}
num_connectors++;
@@ -4883,18 +4888,21 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
refclk = i9xx_get_refclk(crtc, num_connectors);
- /*
-* Returns a set of divisors for the desired target clock with the given
-* refclk, or FALSE. The returned values represent the clock equation:
-* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
-*/
- limit = intel_limit(crtc, refclk);
- ok = dev_priv-display.find_dpll(limit, crtc,
-intel_crtc-config.port_clock,
-refclk, NULL, clock);
- if (!ok !intel_crtc-config.clock_set) {
- DRM_ERROR(Couldn't find PLL settings for mode!\n);
- return -EINVAL;
+ if (!is_dsi) {
+ /*
+* Returns a set of divisors for the desired target clock with
+* the given refclk, or FALSE. The returned values represent
+* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
+* 2) / p1 / p2.
+*/
+ limit = intel_limit(crtc, refclk);
+ ok = dev_priv-display.find_dpll(limit, crtc,
+intel_crtc-config.port_clock,
+refclk, NULL, clock);
+ if (!ok !intel_crtc-config.clock_set) {
+ DRM_ERROR(Couldn't find PLL settings for mode!\n);
+ return -EINVAL;
+ }
}
/* Ensure that the cursor is valid for the new mode before changing...
*/
@@ -4922,16 +4930,18 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
intel_crtc-config.dpll.p2 = clock.p2;
}
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev)) {
i8xx_update_pll(intel_crtc,
has_reduced_clock ? reduced_clock : NULL,
num_connectors);
- else if (IS_VALLEYVIEW(dev))
- vlv_update_pll(intel_crtc);
- else
+ } else if (IS_VALLEYVIEW(dev)) {
+ if (!is_dsi)
+ vlv_update_pll(intel_crtc);
+ } else {
i9xx_update_pll(intel_crtc,
has_reduced_clock ? reduced_clock : NULL,
num_connectors);
+ }
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
--
1.7.9.5
___
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[Intel-gfx] [PATCH v2 12/15] drm/i915: Band Gap WA
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: ymohanma yogesh.mohan.marimu...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 352ff46..676b310 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -37,6 +37,51 @@
static const struct intel_dsi_device intel_dsi_devices[] = {
};
+
+static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
+ u32 mask)
+{
+ u32 tmp = vlv_cck_read(dev_priv, reg);
+ tmp = ~mask;
+ tmp |= val;
+ vlv_cck_write(dev_priv, reg, tmp);
+}
+
+static void band_gap_wa(struct drm_i915_private *dev_priv)
+{
+ mutex_lock(dev_priv-dpio_lock);
+
+ /* Enable bandgap fix in GOP driver */
+ vlv_cck_modify(dev_priv, 0x6D, 0x0001, 0x0003);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6E, 0x0001, 0x0003);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6F, 0x0001, 0x0003);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x00, 0x8000, 0x8000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x00, 0x, 0x8000);
+ msleep(20);
+
+ /* Turn Display Trunk on */
+ vlv_cck_modify(dev_priv, 0x6B, 0x0002, 0x0003);
+ msleep(20);
+
+ vlv_cck_modify(dev_priv, 0x6C, 0x0002, 0x0003);
+ msleep(20);
+
+ vlv_cck_modify(dev_priv, 0x6D, 0x0002, 0x0003);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6E, 0x0002, 0x0003);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6F, 0x0002, 0x0003);
+
+ mutex_unlock(dev_priv-dpio_lock);
+
+ /* Need huge delay, otherwise clock is not stable */
+ msleep(100);
+}
+
static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
{
return container_of(intel_attached_encoder(connector),
@@ -291,6 +336,9 @@ static void intel_dsi_mode_set(struct intel_encoder
*intel_encoder)
/* Update the DSI PLL */
vlv_enable_dsi_pll(intel_encoder);
+ /* XXX: Location of the call */
+ band_gap_wa(dev_priv);
+
/* escape clock divider, 20MHz, shared for A and C. device ready must be
* off when doing this! txclkesc? */
tmp = I915_READ(MIPI_CTRL(0));
--
1.7.9.5
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[Intel-gfx] [PATCH v2 15/15] drm/i915: add AUO MIPI DSI display sub-encoder
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/auo_dsi_display.c | 182
drivers/gpu/drm/i915/intel_dsi.c |5 +
drivers/gpu/drm/i915/intel_dsi.h |3 +
4 files changed, 191 insertions(+)
create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 65e60d2..18bf236 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -42,6 +42,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_opregion.o \
intel_sideband.o \
intel_uncore.o \
+ auo_dsi_display.o \
dvo_ch7xxx.o \
dvo_ch7017.o \
dvo_ivch.o \
diff --git a/drivers/gpu/drm/i915/auo_dsi_display.c
b/drivers/gpu/drm/i915/auo_dsi_display.c
new file mode 100644
index 000..771a725
--- /dev/null
+++ b/drivers/gpu/drm/i915/auo_dsi_display.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula jani.nik...@intel.com
+ *Shobhit Kumar shobhit.ku...@intel.com
+ */
+
+#include drm/drmP.h
+#include drm/drm_crtc.h
+#include drm/drm_edid.h
+#include drm/i915_drm.h
+#include linux/slab.h
+#include video/mipi_display.h
+#include i915_drv.h
+#include intel_drv.h
+#include intel_dsi.h
+#include intel_dsi_cmd.h
+
+#if 0 /* XXX */
+static void auo_vid_get_panel_info(int pipe, struct drm_connector *connector)
+{
+ DRM_DEBUG_KMS(\n);
+ if (!connector)
+ return;
+
+ if (pipe == 0) {
+ connector-display_info.width_mm = 216;
+ connector-display_info.height_mm = 135;
+ }
+
+ return;
+}
+#endif
+
+static bool auo_init(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS(\n);
+
+ intel_dsi-eot_disable = 0;
+ intel_dsi-pixel_format = VID_MODE_FORMAT_RGB888;
+ intel_dsi-video_mode_format = VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
+ intel_dsi-lane_count = 4;
+
+ return true;
+}
+
+static void auo_enable(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS(\n);
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE);
+
+ dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00);
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON);
+ dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55);
+}
+
+static void auo_disable(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS(\n);
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF);
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE);
+}
+
+static int auo_mode_valid(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static bool auo_mode_fixup(struct intel_dsi_device *dsi,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void auo_mode_set(struct intel_dsi_device *dsi,
+struct drm_display_mode *mode,
+struct drm_display_mode *adjusted_mode)
+{
+}
+
+static enum drm_connector_status auo_detect(struct intel_dsi_device *dsi)
+{
+ return connector_status_connected;
+}
+
+static bool auo_get_hw_state(struct intel_dsi_device *dev)
+{
+ return true;
+}
+
+static struct drm_display_mode *auo_get_modes(struct intel_dsi_device *dsi)
+{
+ struct
[Intel-gfx] [PATCH v2 13/15] drm/i915: Parse the MIPI related VBT Block and store relevant info
From: Shobhit Kumar shobhit.ku...@intel.com
Initial parsing of the VBT MIPI block. For now, just store the panel id
if found.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |5 +
drivers/gpu/drm/i915/intel_bios.c | 16 +++
drivers/gpu/drm/i915/intel_bios.h | 41 +
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96c875b..ea80133 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1064,6 +1064,11 @@ struct intel_vbt_data {
int edp_bpp;
struct edp_power_seq edp_pps;
+ /* MIPI DSI */
+ struct {
+ u16 panel_id;
+ } dsi;
+
int crt_ddc_pin;
int child_dev_num;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 53f2bed..6668873 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -569,6 +569,21 @@ parse_edp(struct drm_i915_private *dev_priv, struct
bdb_header *bdb)
}
static void
+parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+ struct bdb_mipi *mipi;
+
+ mipi = find_section(bdb, BDB_MIPI);
+ if (!mipi) {
+ DRM_DEBUG_KMS(No MIPI BDB found);
+ return;
+ }
+
+ /* XXX: add more info */
+ dev_priv-vbt.dsi.panel_id = mipi-panel_id;
+}
+
+static void
parse_device_mapping(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
@@ -745,6 +760,7 @@ intel_parse_bios(struct drm_device *dev)
parse_device_mapping(dev_priv, bdb);
parse_driver_features(dev_priv, bdb);
parse_edp(dev_priv, bdb);
+ parse_mipi(dev_priv, bdb);
if (bios)
pci_unmap_rom(pdev, bios);
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index e088d6f..6e9250e 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -104,6 +104,7 @@ struct vbios_data {
#define BDB_LVDS_LFP_DATA 42
#define BDB_LVDS_BACKLIGHT 43
#define BDB_LVDS_POWER 44
+#define BDB_MIPI50
#define BDB_SKIP 254 /* VBIOS private block, ignore */
struct bdb_general_features {
@@ -618,4 +619,44 @@ int intel_parse_bios(struct drm_device *dev);
#definePORT_IDPC 8
#definePORT_IDPD 9
+/* MIPI DSI panel info */
+struct bdb_mipi {
+ u16 panel_id;
+ u16 bridge_revision;
+
+ /* General params */
+ u32 dithering:1;
+ u32 bpp_pixel_format:1;
+ u32 rsvd1:1;
+ u32 dphy_valid:1;
+ u32 resvd2:28;
+
+ u16 port_info;
+ u16 rsvd3:2;
+ u16 num_lanes:2;
+ u16 rsvd4:12;
+
+ /* DSI config */
+ u16 virt_ch_num:2;
+ u16 vtm:2;
+ u16 rsvd5:12;
+
+ u32 dsi_clock;
+ u32 bridge_ref_clk;
+ u16 rsvd_pwr;
+
+ /* Dphy Params */
+ u32 prepare_cnt:5;
+ u32 rsvd6:3;
+ u32 clk_zero_cnt:8;
+ u32 trail_cnt:5;
+ u32 rsvd7:3;
+ u32 exit_zero_cnt:6;
+ u32 rsvd8:2;
+
+ u32 hl_switch_cnt;
+ u32 lp_byte_clk;
+ u32 clk_lane_switch_cnt;
+} __attribute__((packed));
+
#endif /* _I830_BIOS_H_ */
--
1.7.9.5
___
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[Intel-gfx] [PATCH v2 14/15] drm/i915: initialize DSI output on VLV
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 336bee4..2f00c98 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9386,6 +9386,8 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(VLV_DISPLAY_BASE + DP_B) DP_DETECTED)
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B,
PORT_B);
}
+
+ intel_dsi_init(dev);
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
--
1.7.9.5
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[Intel-gfx] [PATCH v2 06/15] drm/i915: add structs for MIPI DSI output
The sub-encoder model is copied from DVO.
v2: Add attached_connector to struct intel_dsi.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.h | 99 ++
1 file changed, 99 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.h
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
new file mode 100644
index 000..f308269
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _INTEL_DSI_H
+#define _INTEL_DSI_H
+
+#include drm/drmP.h
+#include drm/drm_crtc.h
+#include intel_drv.h
+
+struct intel_dsi_device {
+ unsigned int panel_id;
+ const char *name;
+ int type;
+ const struct intel_dsi_dev_ops *dev_ops;
+ void *dev_priv;
+};
+
+struct intel_dsi_dev_ops {
+ bool (*init)(struct intel_dsi_device *dsi);
+
+ /* This callback must be able to assume DSI commands can be sent */
+ void (*enable)(struct intel_dsi_device *dsi);
+
+ /* This callback must be able to assume DSI commands can be sent */
+ void (*disable)(struct intel_dsi_device *dsi);
+
+ int (*mode_valid)(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode);
+
+ bool (*mode_fixup)(struct intel_dsi_device *dsi,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+
+ void (*mode_set)(struct intel_dsi_device *dsi,
+struct drm_display_mode *mode,
+struct drm_display_mode *adjusted_mode);
+
+ enum drm_connector_status (*detect)(struct intel_dsi_device *dsi);
+
+ bool (*get_hw_state)(struct intel_dsi_device *dev);
+
+ struct drm_display_mode *(*get_modes)(struct intel_dsi_device *dsi);
+
+ void (*destroy) (struct intel_dsi_device *dsi);
+};
+
+struct intel_dsi {
+ struct intel_encoder base;
+
+ struct intel_dsi_device dev;
+
+ struct intel_connector *attached_connector;
+
+ /* if true, use HS mode, otherwise LP */
+ bool hs;
+
+ /* virtual channel */
+ int channel;
+
+ /* number of DSI lanes */
+ unsigned int lane_count;
+
+ /* video mode pixel format for MIPI_DSI_FUNC_PRG register */
+ u32 pixel_format;
+
+ /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
+ u32 video_mode_format;
+
+ /* eot for MIPI_EOT_DISABLE register */
+ u32 eot_disable;
+};
+
+static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct intel_dsi, base.base);
+}
+
+#endif /* _INTEL_DSI_H */
--
1.7.9.5
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[Intel-gfx] [PATCH v2 08/15] drm/i915: add basic MIPI DSI output support
This does not include any panel specific sub-encoders yet.
v2: Fix fixed mode handling (Daniel)
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_dsi.c | 534 ++
3 files changed, 536 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8bffd29..5864c5b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_display.o \
intel_crt.o \
intel_lvds.o \
+ intel_dsi.o \
intel_dsi_cmd.o \
intel_bios.o \
intel_ddi.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a31abc6..cbe3df1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -525,6 +525,7 @@ extern void intel_mark_fb_busy(struct drm_i915_gem_object
*obj,
struct intel_ring_buffer *ring);
extern void intel_mark_idle(struct drm_device *dev);
extern void intel_lvds_init(struct drm_device *dev);
+extern bool intel_dsi_init(struct drm_device *dev);
extern bool intel_is_dual_link_lvds(struct drm_device *dev);
extern void intel_dp_init(struct drm_device *dev, int output_reg,
enum port port);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
new file mode 100644
index 000..d7eddbd
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -0,0 +1,534 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula jani.nik...@intel.com
+ */
+
+#include drm/drmP.h
+#include drm/drm_crtc.h
+#include drm/drm_edid.h
+#include drm/i915_drm.h
+#include linux/slab.h
+#include i915_drv.h
+#include intel_drv.h
+#include intel_dsi.h
+#include intel_dsi_cmd.h
+
+/* the sub-encoders aka panel drivers */
+static const struct intel_dsi_device intel_dsi_devices[] = {
+};
+
+static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
+{
+ return container_of(intel_attached_encoder(connector),
+ struct intel_dsi, base);
+}
+
+static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi-dev.type == INTEL_DSI_VIDEO_MODE;
+}
+
+static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi-dev.type == INTEL_DSI_COMMAND_MODE;
+}
+
+static void intel_dsi_hot_plug(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS(\n);
+}
+
+static bool intel_dsi_compute_config(struct intel_encoder *encoder,
+struct intel_crtc_config *config)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ struct intel_connector *intel_connector = intel_dsi-attached_connector;
+ struct drm_display_mode *fixed_mode = intel_connector-panel.fixed_mode;
+ struct drm_display_mode *adjusted_mode = config-adjusted_mode;
+ struct drm_display_mode *mode = config-requested_mode;
+
+ DRM_DEBUG_KMS(\n);
+
+ if (fixed_mode)
+ intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+
+ if (intel_dsi-dev.dev_ops-mode_fixup)
+ return intel_dsi-dev.dev_ops-mode_fixup(intel_dsi-dev,
+ mode, adjusted_mode);
+
+ return true;
+}
+
+static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS(\n);
+}
+
+static void intel_dsi_pre_enable(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS(\n);
+}
+
+static void
[Intel-gfx] [PATCH v2 05/15] drm/i915: add MIPI DSI output type and subtypes
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 01455aa..a31abc6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -93,13 +93,17 @@
#define INTEL_OUTPUT_HDMI 6
#define INTEL_OUTPUT_DISPLAYPORT 7
#define INTEL_OUTPUT_EDP 8
-#define INTEL_OUTPUT_UNKNOWN 9
+#define INTEL_OUTPUT_DSI 9
+#define INTEL_OUTPUT_UNKNOWN 10
#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4
+#define INTEL_DSI_COMMAND_MODE 0
+#define INTEL_DSI_VIDEO_MODE 1
+
struct intel_framebuffer {
struct drm_framebuffer base;
struct drm_i915_gem_object *obj;
--
1.7.9.5
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[Intel-gfx] [PATCH v2 02/15] drm/i915: add more VLV IOSF sideband ports accessors
For GPIO NC, CCK, CCU, and GPS CORE.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |8 +
drivers/gpu/drm/i915/i915_reg.h |4 +++
drivers/gpu/drm/i915/intel_sideband.c | 56 +
3 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1eb4d98..96c875b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2171,6 +2171,14 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a543c4e..b417a8c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -360,6 +360,10 @@
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
+#define IOSF_PORT_GPIO_NC0x13
+#define IOSF_PORT_CCK0x14
+#define IOSF_PORT_CCU0xA9
+#define IOSF_PORT_GPS_CORE 0x48
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 9a0e6c5..0a41670 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -101,6 +101,62 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
return val;
}
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+ PUNIT_OPCODE_REG_READ, reg, val);
+ return val;
+}
+
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+ PUNIT_OPCODE_REG_WRITE, reg, val);
+}
+
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+ PUNIT_OPCODE_REG_READ, reg, val);
+ return val;
+}
+
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+ PUNIT_OPCODE_REG_WRITE, reg, val);
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+ PUNIT_OPCODE_REG_READ, reg, val);
+ return val;
+}
+
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+ PUNIT_OPCODE_REG_WRITE, reg, val);
+}
+
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+ PUNIT_OPCODE_REG_READ, reg, val);
+ return val;
+}
+
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+ PUNIT_OPCODE_REG_WRITE, reg, val);
+}
+
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
u32 val = 0;
--
1.7.9.5
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Re: [Intel-gfx] [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8
On Fri, Aug 16, 2013 at 1:15 AM, Jani Nikula jani.nik...@linux.intel.com wrote: On Fri, 16 Aug 2013, Daniel Vetter dan...@ffwll.ch wrote: On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote: Hello All- I'm trying to determine if the ChromeOS-only patches being carried by Google still make sense and are the right way to do things in the 3.11+ world, and Jesse asked me to forward the patches to the list for evaluation and potential upstreaming. I've quickly read through the pile here and there's a few things we need to look at. Ditto, and agreed. But one thing which makes assessing the patches here a bit a pain is that often there's a fixup later on again. Another pain is that sometimes the fixup is first, i.e. the series does not seem to be in the right order. One of the issues is that it's not truly a series, but rather individual patches dating back through 2011 - I thought I had gotten git-send-email to push them out in chronological order, but maybe I was less successful than I thought. :) I'll see what I can do in regards to squishing some of these down - I have fairly limited knowledge when it comes to the i915 driver, so it may not end up perfect, but I'll give it a go. :) Thanks! -James BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/vma: Correct use after free in eviction
The vma will [possibly] be destroyed during unbind in eviction. Immediately after this, we try to delete the list entry. Chris and Ville did the debug on this before I woke up, I just get to take credit for the fix :p Reported-by: Mika Kuoppala mika.kuopp...@intel.com Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_gem_evict.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index 0cbaad4..db90261 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/i915_gem_evict.c @@ -139,10 +139,11 @@ found: vma = list_first_entry(eviction_list, struct i915_vma, exec_list); + + list_del_init(vma-exec_list); if (ret == 0) ret = i915_vma_unbind(vma); - list_del_init(vma-exec_list); drm_gem_object_unreference(vma-obj-base); } -- 1.8.3.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915: Update VGA arbiter support for newer devices
On Fri, 2013-08-16 at 13:20 +0300, Ville Syrjälä wrote: On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote: On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote: On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson alex.william...@redhat.com wrote: This is intended to add VGA arbiter support for Intel HD graphics on Core processors. The old GMCH registers no longer exist, so even though it appears that i915 participates in VGA arbitration, it doesn't work. On Intel HD graphics we already attempt to disable VGA regions of the device. This makes registering as a VGA client unnecessary since we don't intend to operate differently depending on how many VGA devices are present. We can disable VGA memory regions by clearing a memory enable bit in the VGA MSR. That only leaves VGA IO, which we update the VGA arbiter to know that we don't participate in VGA memory arbitration. We also add a hook on unload to re-enable memory and reinstate VGA memory arbitration. I would think there is still a VGA disable bit on the Intel device somewhere, we'd just need Intel to look in the docs and find it. A bit that can nuke both i/o and cmd regs. The only bit available is in the GGC and is a keyed/locked register that not only disables VGA memory and I/O, but also modifies the class code of the device. Early Core processors didn't lock this, but it's untouchable in newer ones AFAICT. Thanks, I've not found anything else in the docs. And also we _need_ VGA I/O access to make i915_disable_vga() work. It's not 100% clear whether we really need to poke at the sequencer register in modern hardware, but the docs do still list it as a mandatory step. So even if we were to have a global disable VGA I/O and mem bit we'd need to make sure we already disabled VGA eg. after resume when the BIOS had a chance to turn the VGA display back on. I think there were also some BIOSen that turned VGA display back on when closing/opening the laptop lid. Not sure what would even happen with those if totally disabled VGA I/O access. I'm not sure they actually frob with the VGA regs though. Could be they just turn on the VGA display bit in the VGA_CONTROL register. Hmm, it appears the MSR write isn't fully disabling VGA memory space. When the VBIOS for the PEG graphics is run in the guest, I get some corruption of the IGD frame buffer. If I manually disable PCI memory in the command register, this doesn't happen. I also get some strange artifacts on the PEG display that don't happen when PCI memory is disabled. Should that MSR bit give us the whole a_-b_ range? Thanks, Alex ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] intel: Update i915_drm.h and correct misspelled caching
On 08/14/2013 01:19 AM, Sedat Dilek wrote:
AFAICS, there are more updates needed to be in sync with recent kernel-drm.
I fell over the misspelling when digging into an issue in Linux-next.
The spelling should be consistent in kernel-drm, libdrm, intel-ddx, etc.
Here, I had a look especially at the defined macros (defines).
Signed-off-by: Sedat Dilek sedat.di...@gmail.com
This should get Chris's ok before committing, but
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
include/drm/i915_drm.h | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index aa983f3..61a8407 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -195,8 +195,8 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_WAIT 0x2c
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
-#define DRM_I915_GEM_SET_CACHEING 0x2f
-#define DRM_I915_GEM_GET_CACHEING 0x30
+#define DRM_I915_GEM_SET_CACHING 0x2f
+#define DRM_I915_GEM_GET_CACHING 0x30
#define DRM_I915_REG_READ 0x31
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
@@ -222,8 +222,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_PINDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
-#define DRM_IOCTL_I915_GEM_SET_CACHEING
DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct
drm_i915_gem_cacheing)
-#define DRM_IOCTL_I915_GEM_GET_CACHEING
DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct
drm_i915_gem_cacheing)
+#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
+#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_GEM_THROTTLE)
#define DRM_IOCTL_I915_GEM_ENTERVTDRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVTDRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
@@ -706,21 +706,22 @@ struct drm_i915_gem_busy {
__u32 busy;
};
-#define I915_CACHEING_NONE 0
-#define I915_CACHEING_CACHED 1
+#define I915_CACHING_NONE 0
+#define I915_CACHING_CACHED1
+#define I915_CACHING_DISPLAY 2
-struct drm_i915_gem_cacheing {
+struct drm_i915_gem_caching {
/**
-* Handle of the buffer to set/get the cacheing level of. */
+* Handle of the buffer to set/get the caching level of. */
__u32 handle;
/**
* Cacheing level to apply or return value
*
-* bits0-15 are for generic cacheing control (i.e. the above defined
+* bits0-15 are for generic caching control (i.e. the above defined
* values). bits16-31 are reserved for platform-specific variations
* (e.g. l3$ caching on gen7). */
- __u32 cacheing;
+ __u32 caching;
};
#define I915_TILING_NONE 0
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[Intel-gfx] [PATCH] [v2] drm/i915/vma: Correct use after free in eviction
The vma will [possibly] be destroyed during unbind in eviction.
Immediately after this, we try to delete the list entry.
Chris and Ville did the debug on this before I woke up, I just get to
take credit for the fix :p
v2: Missed the drm_object_unreference use after free (Ville)
Reported-by: Mika Kuoppala mika.kuopp...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_evict.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 0cbaad4..3b7b74e 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -136,14 +136,17 @@ found:
/* Unbinding will emit any required flushes */
while (!list_empty(eviction_list)) {
+ struct drm_gem_object *obj;
vma = list_first_entry(eviction_list,
struct i915_vma,
exec_list);
+
+ obj = vma-obj-base;
+ list_del_init(vma-exec_list);
if (ret == 0)
ret = i915_vma_unbind(vma);
- list_del_init(vma-exec_list);
- drm_gem_object_unreference(vma-obj-base);
+ drm_gem_object_unreference(obj);
}
return ret;
--
1.8.3.4
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