Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build
Reviewed-by: Oscar Mateo (sorry, I forgot about this one) > -Original Message- > From: intel-gfx-boun...@lists.freedesktop.org [mailto:intel-gfx- > boun...@lists.freedesktop.org] On Behalf Of joao.san...@intel.com > Sent: Thursday, January 23, 2014 6:30 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build > > From: Joao Santos > > Changed TOP to ANDROID_BUILD_TOP to allow package to be compiled as part > of a top build; LIBDRM_PATH changed to PATH_LIBDRM because otherwise it > cannot be written to when in a top build (must be getting used in some other > makefile). > > Issue: VIZ-3495 > Signed-off-by: Joao Santos > > diff --git a/tests/Android.mk b/tests/Android.mk index abccb7f..82b28cd > 100644 > --- a/tests/Android.mk > +++ b/tests/Android.mk > @@ -2,17 +2,17 @@ include $(LOCAL_PATH)/tests/Makefile.sources > include $(LOCAL_PATH)/lib/Makefile.sources > > LIBPCIACCESS_PATH := $(firstword $(wildcard \ > - $(TOP)/external/PRIVATE/libpciaccess \ > - $(TOP)/hardware/intel/libpciaccess\ > - $(TOP)/external/libpciaccess)) > + $(ANDROID_BUILD_TOP)/external/PRIVATE/libpciaccess \ > + $(ANDROID_BUILD_TOP)/hardware/intel/libpciaccess\ > + $(ANDROID_BUILD_TOP)/external/libpciaccess)) > ifeq ($(LIBPCIACCESS_PATH),) > $(error "Unable to find libpciaccess!") endif > > -LIBDRM_PATH := $(firstword $(wildcard \ > - $(TOP)/external/PRIVATE/drm \ > - $(TOP)/external/drm)) > -ifeq ($(LIBDRM_PATH),) > +PATH_LIBDRM = $(firstword $(wildcard \ > + $(ANDROID_BUILD_TOP)/external/PRIVATE/drm \ > + $(ANDROID_BUILD_TOP)/external/drm)) > +ifeq ($(PATH_LIBDRM),) > $(error "Unable to find libdrm!") > endif > > @@ -66,8 +66,8 @@ define add_test > > LOCAL_C_INCLUDES += \ > $(LOCAL_PATH)/lib \ > - $(LIBDRM_PATH)/include/drm\ > - $(LIBDRM_PATH)/intel \ > + $(PATH_LIBDRM)/include/drm\ > + $(PATH_LIBDRM)/intel \ > $(LIBPCIACCESS_PATH)/include > > LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM > -- > 1.7.9.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable
On Tue, Jan 28, 2014 at 10:06:05AM -0200, Rodrigo Vivi wrote:
> I agree that spec is strange, but following the spec correctly result
> for this and next patch would be only this:
>
> if (IS_IVB_GT1(dev))
> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - else
> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> }
That would match what the w/a database says. But bspec says otherwise.
But anyway Chris confirmed on his GT1 that GEN7_HALF_SLICE_CHICKEN1_GT2
doesn't exist there, so I think these patches are correct.
>
> On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrjälä
> wrote:
> > On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
> >> Your patch itself makes sense, but the registers values there are at
> >> i915_reg.h
> >> differs from what I see at BSpec:
> >>
> >> #define GEN7_ROW_CHICKEN2 0xe4f4
> >> #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
> >>
> >> against
> >> Address: 0E4F0h
> >> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
> >> Address: 0F4F0h
> >> Valid Projects: [DevIVB:GT2]
> >
> > ROW_CHICKEN vs. ROW_CHICKEN2
> >
> >>
> >> Also, I couldn't see the wa description at wa_database...
> >> description was empty for me..
> >
> > Which one? WaDisableDopClockGating? It's not in the list for IVB,
> > so in order to see it you need to pick another platform which
> > includes this w/a.
> >
> >>
> >> On Wed, Jan 22, 2014 at 5:32 PM, wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > IVB GT2 has two registers for these things, and both must be written.
> >> >
> >> > To add a bit more confusion both Bspec and the W/A database state that
> >> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
> >> > database also says to write even the second GT2 only register. So I
> >> > don't really know what the right thing here is.
> >> >
> >> > Signed-off-by: Ville Syrjälä
> >> > ---
> >> > drivers/gpu/drm/i915/intel_pm.c | 13 ++---
> >> > 1 file changed, 10 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> > b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 6a1d98a..b268a55 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct
> >> > drm_device *dev)
> >> > if (IS_IVB_GT1(dev))
> >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >> >
> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> > - else
> >> > + else {
> >> > + /* must write both registers */
> >> > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >> > +
> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> >> >
> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> > + }
> >> >
> >> > /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb
> >> > workaround. */
> >> > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> >> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct
> >> > drm_device *dev)
> >> > if (IS_IVB_GT1(dev))
> >> > I915_WRITE(GEN7_ROW_CHICKEN2,
> >> >_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> > - else
> >> > + else {
> >> > + /* must write both registers */
> >> > + I915_WRITE(GEN7_ROW_CHICKEN2,
> >> > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> > I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> >> >_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> > -
> >> > + }
> >> >
> >> > /* WaForceL3Serialization:ivb */
> >> > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> >> > --
> >> > 1.8.3.2
> >> >
> >> > ___
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >>
> >>
> >> --
> >> Rodrigo Vivi
> >> Blog: http://blog.vivi.eng.br
> >
> > --
> > Ville Syrjälä
> > Intel OTC
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Increase OpRegion timeout
I have a machine here which hits this (a g33):
[ 13.368536] excessive driver sleep timeout (DSPL) 1024
Apparently people love pot numbers, and one second isn't that
unreasonable (for a bios writer at least) I guess.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_opregion.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 3da259e280ba..3c7e38c7ed87 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -261,10 +261,10 @@ static int swsci(struct drm_device *dev, u32 function,
u32 parm, u32 *parm_out)
/* The spec says 2ms should be the default, but it's too small
* for some machines. */
dslp = 50;
- } else if (dslp > 500) {
+ } else if (dslp > 1500) {
/* Hey bios, trust must be earned. */
WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
dslp);
- dslp = 500;
+ dslp = 1500;
}
/* The spec tells us to do this, but we are the only user... */
--
1.8.3.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build
> -Original Message- > From: intel-gfx-boun...@lists.freedesktop.org [mailto:intel-gfx- > boun...@lists.freedesktop.org] On Behalf Of Mateo Lozano, Oscar > Sent: Friday, January 31, 2014 9:03 AM > To: Santos, Joao; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build > > Reviewed-by: Oscar Mateo > > (sorry, I forgot about this one) > > > -Original Message- > > From: intel-gfx-boun...@lists.freedesktop.org [mailto:intel-gfx- > > boun...@lists.freedesktop.org] On Behalf Of joao.san...@intel.com > > Sent: Thursday, January 23, 2014 6:30 PM > > To: intel-gfx@lists.freedesktop.org > > Subject: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build > > > > From: Joao Santos > > > > Changed TOP to ANDROID_BUILD_TOP to allow package to be compiled as > > part of a top build; LIBDRM_PATH changed to PATH_LIBDRM because > > otherwise it cannot be written to when in a top build (must be getting > > used in some other makefile). > > > > Issue: VIZ-3495 > > Signed-off-by: Joao Santos > > > > diff --git a/tests/Android.mk b/tests/Android.mk index > > abccb7f..82b28cd > > 100644 > > --- a/tests/Android.mk > > +++ b/tests/Android.mk > > @@ -2,17 +2,17 @@ include $(LOCAL_PATH)/tests/Makefile.sources > > include $(LOCAL_PATH)/lib/Makefile.sources > > > > LIBPCIACCESS_PATH := $(firstword $(wildcard \ > > - $(TOP)/external/PRIVATE/libpciaccess \ > > - $(TOP)/hardware/intel/libpciaccess\ > > - $(TOP)/external/libpciaccess)) > > + $(ANDROID_BUILD_TOP)/external/PRIVATE/libpciaccess \ > > + $(ANDROID_BUILD_TOP)/hardware/intel/libpciaccess\ > > + $(ANDROID_BUILD_TOP)/external/libpciaccess)) > > ifeq ($(LIBPCIACCESS_PATH),) > > $(error "Unable to find libpciaccess!") endif The patch is incomplete. If you change these macros in the tests directory then why does it not need to be changed in the tools directory also? I have a patch that refactors these macros into a third file, I'll send it up for review later once I fix another issue I have in the patch series. Thanks, Raf > > > > -LIBDRM_PATH := $(firstword $(wildcard \ > > - $(TOP)/external/PRIVATE/drm \ > > - $(TOP)/external/drm)) > > -ifeq ($(LIBDRM_PATH),) > > +PATH_LIBDRM = $(firstword $(wildcard \ > > + $(ANDROID_BUILD_TOP)/external/PRIVATE/drm \ > > + $(ANDROID_BUILD_TOP)/external/drm)) > > +ifeq ($(PATH_LIBDRM),) > > $(error "Unable to find libdrm!") > > endif > > > > @@ -66,8 +66,8 @@ define add_test > > > > LOCAL_C_INCLUDES += \ > > $(LOCAL_PATH)/lib \ > > - $(LIBDRM_PATH)/include/drm\ > > - $(LIBDRM_PATH)/intel \ > > + $(PATH_LIBDRM)/include/drm\ > > + $(PATH_LIBDRM)/intel \ > > $(LIBPCIACCESS_PATH)/include > > > > LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM > > -- > > 1.7.9.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Increase OpRegion timeout
On Fri, Jan 31, 2014 at 10:31:16AM +0100, Daniel Vetter wrote: > I have a machine here which hits this (a g33): > > [ 13.368536] excessive driver sleep timeout (DSPL) 1024 > > Apparently people love pot numbers, and one second isn't that > unreasonable (for a bios writer at least) I guess. Reference https://bugs.freedesktop.org/show_bug.cgi?id=74266 excessive driver sleep timeout (DSPL) 1280 Quirks are DRM_INFO not full blown oops! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build
On Fri, Jan 31, 2014 at 09:36:25AM +, Barbalho, Rafael wrote: > The patch is incomplete. If you change these macros in the tests > directory then why does it not need to be changed in the tools > directory also? > > I have a patch that refactors these macros into a third file, I'll > send it up for review later once I fix another issue I have in the > patch series. Holding the horses then! -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: dma_buf_vunmap is presumed not to fail, don't let it
Since dma_buf_vunmap() procedes blithely on ignorant of whether the
driver failed to actually unmap the backing storage for the dma-buf, we
need to make a best-effort to do so. This involves not allowing
ourselves to be susceptible to signals causing us to leak the storage.
This should have been detectable with the current i-g-t as a misplaced
signal should have left the pages pinned upon freeing the object where
we have a warning in place.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 9bb533e0d762..321102a8374b 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -161,12 +161,8 @@ static void i915_gem_dmabuf_vunmap(struct dma_buf
*dma_buf, void *vaddr)
{
struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
struct drm_device *dev = obj->base.dev;
- int ret;
-
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- return;
+ mutex_lock(&dev->struct_mutex);
if (--obj->vmapping_count == 0) {
vunmap(obj->dma_buf_vmapping);
obj->dma_buf_vmapping = NULL;
--
1.9.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Improve the comment on ring_sync after seqno wrap
There are quite alot of nasty things happening inside the
seemingly bening intel_ring_begin() if seqno wrap happens.
Warn the reader about it.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d897a19..f99e2ae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -727,7 +727,13 @@ gen6_ring_sync(struct intel_ring_buffer *waiter,
if (ret)
return ret;
- /* If seqno wrap happened, omit the wait with no-ops */
+ /* Seqno allocation is inside intel_ring_begin() so the seqno
+* wrap (re init of driver seqno counter) might have happened.
+* This means that the seqno we are syncing to, just became
+* irrelevant in this brand new seqno universe. And as it does
+* not exists anymore, waiting for it to happen is unwise.
+* If this is the case, emit no-ops instead.
+*/
if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
intel_ring_emit(waiter,
dw1 |
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Improve the comment on ring_sync after seqno wrap
On Fri, Jan 31, 2014 at 01:04:21PM +0200, Mika Kuoppala wrote: > There are quite alot of nasty things happening inside the > seemingly bening intel_ring_begin() if seqno wrap happens. > Warn the reader about it. > > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_ringbuffer.c |8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index d897a19..f99e2ae 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -727,7 +727,13 @@ gen6_ring_sync(struct intel_ring_buffer *waiter, > if (ret) > return ret; > > - /* If seqno wrap happened, omit the wait with no-ops */ /* If the seqno have wrapped and so reset, omit the wait with no-ops. */ -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Convert EFAULT into a silent SIGBUS
EFAULT will be a possible return code where backing storage is transient, such after it is purged by madvise. As such it is to be expected and so should not trigger a WARN inside i915_gem_fault() but be converted silently to SIGBUS. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d58f777903c0..f2ef2c8518ba 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1574,6 +1574,7 @@ out: ret = VM_FAULT_OOM; break; case -ENOSPC: + case -EFAULT: ret = VM_FAULT_SIGBUS; break; default: -- 1.9.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Treat using a purged buffer as a source of EFAULT
Since a purged buffer is one without any associated pages, attempting to
use it should generate EFAULT rather than EINVAL, as it is not strictly
an invalid parameter.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f2ef2c8518ba..1c91a6718e89 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1733,7 +1733,7 @@ i915_gem_mmap_gtt(struct drm_file *file,
if (obj->madv != I915_MADV_WILLNEED) {
DRM_ERROR("Attempting to mmap a purgeable buffer\n");
- ret = -EINVAL;
+ ret = -EFAULT;
goto out;
}
@@ -2087,7 +2087,7 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
if (obj->madv != I915_MADV_WILLNEED) {
DRM_ERROR("Attempting to obtain a purgeable object\n");
- return -EINVAL;
+ return -EFAULT;
}
BUG_ON(obj->pages_pin_count);
@@ -4091,7 +4091,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
if (obj->madv != I915_MADV_WILLNEED) {
DRM_ERROR("Attempting to pin a purgeable buffer\n");
- ret = -EINVAL;
+ ret = -EFAULT;
goto out;
}
--
1.9.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
The WARN is a bit too verbose, make it a DRM_INFO that gets printed
once.
While at it, fix the typo in DSLP.
Suggested-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 46d288055345..0fae017c4c7b 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32 function, u32
parm, u32 *parm_out)
dslp = 50;
} else if (dslp > 1500) {
/* Hey bios, trust must be earned. */
- WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
dslp);
+ static bool warned;
+ if (!warned) {
+ DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
dslp);
+ warned = true;
+ }
dslp = 1500;
}
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Increase OpRegion timeout
On Fri, 31 Jan 2014, Daniel Vetter wrote:
> I have a machine here which hits this (a g33):
>
> [ 13.368536] excessive driver sleep timeout (DSPL) 1024
>
> Apparently people love pot numbers, and one second isn't that
> unreasonable (for a bios writer at least) I guess.
Reviewed-by: Jani Nikula
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> b/drivers/gpu/drm/i915/intel_opregion.c
> index 3da259e280ba..3c7e38c7ed87 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -261,10 +261,10 @@ static int swsci(struct drm_device *dev, u32 function,
> u32 parm, u32 *parm_out)
> /* The spec says 2ms should be the default, but it's too small
>* for some machines. */
> dslp = 50;
> - } else if (dslp > 500) {
> + } else if (dslp > 1500) {
> /* Hey bios, trust must be earned. */
> WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
> dslp);
> - dslp = 500;
> + dslp = 1500;
> }
>
> /* The spec tells us to do this, but we are the only user... */
> --
> 1.8.3.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
> once.
>
> While at it, fix the typo in DSLP.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_opregion.c |6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> b/drivers/gpu/drm/i915/intel_opregion.c
> index 46d288055345..0fae017c4c7b 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32 function,
> u32 parm, u32 *parm_out)
> dslp = 50;
> } else if (dslp > 1500) {
> /* Hey bios, trust must be earned. */
> - WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
> dslp);
> + static bool warned;
> + if (!warned) {
> + DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
> dslp);
> + warned = true;
> + }
This is the second "print once" thing I've seen in a few days. Seems
like we should add DRM_INFO_ONCE() & co. to hide the ugliness a bit.
> dslp = 1500;
> }
>
> --
> 1.7.9.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable
Both registers must be programmed for the Mode bit to be valid. DevIVB:GT2 ...
So I also agree ;)
Maybe you should improve the commit message now that we are sure, but anyway:
Reviewed-by: Rodrigo Vivi
On Fri, Jan 31, 2014 at 4:28 AM, Ville Syrjälä
wrote:
> On Tue, Jan 28, 2014 at 10:06:05AM -0200, Rodrigo Vivi wrote:
>> I agree that spec is strange, but following the spec correctly result
>> for this and next patch would be only this:
>>
>> if (IS_IVB_GT1(dev))
>> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> - else
>> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> }
>
> That would match what the w/a database says. But bspec says otherwise.
>
> But anyway Chris confirmed on his GT1 that GEN7_HALF_SLICE_CHICKEN1_GT2
> doesn't exist there, so I think these patches are correct.
>
>>
>> On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrjälä
>> wrote:
>> > On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
>> >> Your patch itself makes sense, but the registers values there are at
>> >> i915_reg.h
>> >> differs from what I see at BSpec:
>> >>
>> >> #define GEN7_ROW_CHICKEN2 0xe4f4
>> >> #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
>> >>
>> >> against
>> >> Address: 0E4F0h
>> >> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
>> >> Address: 0F4F0h
>> >> Valid Projects: [DevIVB:GT2]
>> >
>> > ROW_CHICKEN vs. ROW_CHICKEN2
>> >
>> >>
>> >> Also, I couldn't see the wa description at wa_database...
>> >> description was empty for me..
>> >
>> > Which one? WaDisableDopClockGating? It's not in the list for IVB,
>> > so in order to see it you need to pick another platform which
>> > includes this w/a.
>> >
>> >>
>> >> On Wed, Jan 22, 2014 at 5:32 PM, wrote:
>> >> > From: Ville Syrjälä
>> >> >
>> >> > IVB GT2 has two registers for these things, and both must be written.
>> >> >
>> >> > To add a bit more confusion both Bspec and the W/A database state that
>> >> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
>> >> > database also says to write even the second GT2 only register. So I
>> >> > don't really know what the right thing here is.
>> >> >
>> >> > Signed-off-by: Ville Syrjälä
>> >> > ---
>> >> > drivers/gpu/drm/i915/intel_pm.c | 13 ++---
>> >> > 1 file changed, 10 insertions(+), 3 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> >> > b/drivers/gpu/drm/i915/intel_pm.c
>> >> > index 6a1d98a..b268a55 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> >> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct
>> >> > drm_device *dev)
>> >> > if (IS_IVB_GT1(dev))
>> >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> >> >
>> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> > - else
>> >> > + else {
>> >> > + /* must write both registers */
>> >> > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> >> > +
>> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>> >> >
>> >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> > + }
>> >> >
>> >> > /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb
>> >> > workaround. */
>> >> > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>> >> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct
>> >> > drm_device *dev)
>> >> > if (IS_IVB_GT1(dev))
>> >> > I915_WRITE(GEN7_ROW_CHICKEN2,
>> >> >
>> >> > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> > - else
>> >> > + else {
>> >> > + /* must write both registers */
>> >> > + I915_WRITE(GEN7_ROW_CHICKEN2,
>> >> > +
>> >> > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> > I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
>> >> >
>> >> > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> > -
>> >> > + }
>> >> >
>> >> > /* WaForceL3Serialization:ivb */
>> >> > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>> >> > --
>> >> > 1.8.3.2
>> >> >
>> >> > ___
>> >> > Intel-gfx mailing list
>> >> > Intel-gfx@lists.freedesktop.org
>> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>
>> >>
>> >>
>> >> --
>> >> Rodrigo Vivi
>> >> Blog: http://blog.vivi.eng.br
>> >
>> > --
>> > Ville Syrjälä
>> > Intel OTC
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesk
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, Jan 31, 2014 at 01:55:47PM +0200, Jani Nikula wrote:
> On Fri, 31 Jan 2014, Chris Wilson wrote:
> > On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
> >> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
> >> once.
> >>
> >> While at it, fix the typo in DSLP.
> >>
> >> Suggested-by: Chris Wilson
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/intel_opregion.c |6 +-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> >> b/drivers/gpu/drm/i915/intel_opregion.c
> >> index 46d288055345..0fae017c4c7b 100644
> >> --- a/drivers/gpu/drm/i915/intel_opregion.c
> >> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> >> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32
> >> function, u32 parm, u32 *parm_out)
> >>dslp = 50;
> >>} else if (dslp > 1500) {
> >>/* Hey bios, trust must be earned. */
> >> - WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
> >> dslp);
> >> + static bool warned;
> >> + if (!warned) {
> >> + DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
> >> dslp);
> >
> > DRM_INFO("ACPI BIOS requests an excessive sleep of %d ms, using %d
> > instead\n", dslp, MAX_DSLP);
>
> You're just saying that because I didn't dare to write the new value
> back to opregion! :p
I'm just trying to clarify that it is not our fault we want to sleep for
several seconds during startup, but the manufacturer...
But yes, you are a coward. ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, 31 Jan 2014, Ville Syrjälä wrote:
> On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
>> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
>> once.
>>
>> While at it, fix the typo in DSLP.
>>
>> Suggested-by: Chris Wilson
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_opregion.c |6 +-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>> b/drivers/gpu/drm/i915/intel_opregion.c
>> index 46d288055345..0fae017c4c7b 100644
>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32 function,
>> u32 parm, u32 *parm_out)
>> dslp = 50;
>> } else if (dslp > 1500) {
>> /* Hey bios, trust must be earned. */
>> -WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
>> dslp);
>> +static bool warned;
>> +if (!warned) {
>> +DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
>> dslp);
>> +warned = true;
>> +}
>
> This is the second "print once" thing I've seen in a few days. Seems
> like we should add DRM_INFO_ONCE() & co. to hide the ugliness a bit.
I'm adding DRM_INFO_ONCE() in the next version, but if you're referring
to
commit 53a4c6b26ddef1f2969f8bc17178bcda4782d18d
Author: Chris Wilson
Date: Thu Jan 30 14:38:15 2014 +
drm/i915: Only print information for filing bug reports once
it's probably better to keep that as it is.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: release mutex in i915_gem_init()'s error path
Found with smatch.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 08331e1..feedef9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4536,8 +4536,10 @@ int i915_gem_init(struct drm_device *dev)
i915_gem_init_global_gtt(dev);
ret = i915_gem_context_init(dev);
- if (ret)
+ if (ret) {
+ mutex_unlock(&dev->struct_mutex);
return ret;
+ }
ret = i915_gem_init_hw(dev);
mutex_unlock(&dev->struct_mutex);
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: check for oom when allocating private_default_ctx
Found with smatch Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_context.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 985c1ed..19fd362 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -489,6 +489,10 @@ int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) /* Cheat for hang stats */ file_priv->private_default_ctx = kzalloc(sizeof(struct i915_hw_context), GFP_KERNEL); + + if (file_priv->private_default_ctx == NULL) + return -ENOMEM; + file_priv->private_default_ctx->vm = &dev_priv->gtt.base; return 0; } -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, 31 Jan 2014, Chris Wilson wrote:
> On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
>> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
>> once.
>>
>> While at it, fix the typo in DSLP.
>>
>> Suggested-by: Chris Wilson
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_opregion.c |6 +-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>> b/drivers/gpu/drm/i915/intel_opregion.c
>> index 46d288055345..0fae017c4c7b 100644
>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32 function,
>> u32 parm, u32 *parm_out)
>> dslp = 50;
>> } else if (dslp > 1500) {
>> /* Hey bios, trust must be earned. */
>> -WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
>> dslp);
>> +static bool warned;
>> +if (!warned) {
>> +DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
>> dslp);
>
> DRM_INFO("ACPI BIOS requests an excessive sleep of %d ms, using %d
> instead\n", dslp, MAX_DSLP);
You're just saying that because I didn't dare to write the new value
back to opregion! :p
>
>> +warned = true;
>> +}
>> dslp = 1500;
>> }
>>
>> --
>> 1.7.9.5
>>
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, Jan 31, 2014 at 03:21:27PM +0200, Jani Nikula wrote:
> On Fri, 31 Jan 2014, Ville Syrjälä wrote:
> > On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
> >> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
> >> once.
> >>
> >> While at it, fix the typo in DSLP.
> >>
> >> Suggested-by: Chris Wilson
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/intel_opregion.c |6 +-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> >> b/drivers/gpu/drm/i915/intel_opregion.c
> >> index 46d288055345..0fae017c4c7b 100644
> >> --- a/drivers/gpu/drm/i915/intel_opregion.c
> >> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> >> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32
> >> function, u32 parm, u32 *parm_out)
> >>dslp = 50;
> >>} else if (dslp > 1500) {
> >>/* Hey bios, trust must be earned. */
> >> - WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
> >> dslp);
> >> + static bool warned;
> >> + if (!warned) {
> >> + DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
> >> dslp);
> >> + warned = true;
> >> + }
> >
> > This is the second "print once" thing I've seen in a few days. Seems
> > like we should add DRM_INFO_ONCE() & co. to hide the ugliness a bit.
>
> I'm adding DRM_INFO_ONCE() in the next version, but if you're referring
> to
>
> commit 53a4c6b26ddef1f2969f8bc17178bcda4782d18d
> Author: Chris Wilson
> Date: Thu Jan 30 14:38:15 2014 +
>
> drm/i915: Only print information for filing bug reports once
>
> it's probably better to keep that as it is.
Oh right that's multiple DRM_INFO()s. Can't it be done with one
DRM_INFO(), or would that exceed some limit?
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] android: Add makefile for the lib directory
From: Rafael Barbalho The lib directory should really be compiled as a static library on its own and be re-used by any tests or tools that require it. Signed-off-by: Rafael Barbalho --- lib/Android.mk | 31 +++ 1 file changed, 31 insertions(+) create mode 100644 lib/Android.mk diff --git a/lib/Android.mk b/lib/Android.mk new file mode 100644 index 000..23c7d42 --- /dev/null +++ b/lib/Android.mk @@ -0,0 +1,31 @@ +LOCAL_PATH := $(call my-dir) + +include $(LOCAL_PATH)/Makefile.sources + +skip_lib_list := \ +igt_kms.c \ +igt_kms.h + +lib_list := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) + +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(lib_list) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_EXPORT_C_INCLUDE_DIRS += $(LOCAL_PATH) + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES +LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM +LOCAL_CFLAGS += -DANDROID +LOCAL_CFLAGS += -std=c99 +LOCAL_MODULE:= libintel_gpu_tools + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm\ + libdrm_intel + +include $(BUILD_STATIC_LIBRARY) + -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] pm_rps: Add variable load support to load helper
From: Jeff McGee
The load helper can be set to HIGH or LOW. HIGH is the original mode
of sending continuous dword store commands. LOW adds a pause between
each command to reduce throughput.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 9277196..05b859c 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -146,6 +146,11 @@ static void dumpit(const int *freqs)
#define dump(x) if (verbose) dumpit(x)
#define log(...) if (verbose) printf(__VA_ARGS__)
+enum load {
+ LOW,
+ HIGH
+};
+
static struct load_helper {
int devid;
int has_ppgtt;
@@ -153,13 +158,17 @@ static struct load_helper {
struct intel_batchbuffer *batch;
drm_intel_bo *target_buffer;
bool ready;
+ enum load load;
bool exit;
struct igt_helper_process igt_proc;
} lh;
static void load_helper_signal_handler(int sig)
{
- lh.exit = true;
+ if (sig == SIGUSR2)
+ lh.load = lh.load == LOW ? HIGH : LOW;
+ else
+ lh.exit = true;
}
static void emit_store_dword_imm(uint32_t val)
@@ -190,21 +199,30 @@ static void emit_store_dword_imm(uint32_t val)
}
}
-static void load_helper_run(void)
+#define LOAD_HELPER_PAUSE_USEC 500
+static void load_helper_run(enum load load)
{
assert(!lh.igt_proc.running);
igt_require(lh.ready == true);
+ lh.load = load;
+
igt_fork_helper(&lh.igt_proc) {
uint32_t val = 0;
signal(SIGUSR1, load_helper_signal_handler);
+ signal(SIGUSR2, load_helper_signal_handler);
while (!lh.exit) {
emit_store_dword_imm(val);
intel_batchbuffer_flush_on_ring(lh.batch, 0);
val++;
+
+ /* Lower the load by pausing after every submitted
+* write. */
+ if (lh.load == LOW)
+ usleep(LOAD_HELPER_PAUSE_USEC);
}
/* Map buffer to stall for write completion */
@@ -215,6 +233,17 @@ static void load_helper_run(void)
}
}
+static void load_helper_set_load(enum load load)
+{
+ assert(lh.igt_proc.running);
+
+ if (lh.load == load)
+ return;
+
+ lh.load = load;
+ kill(lh.igt_proc.pid, SIGUSR2);
+}
+
static void load_helper_stop(void)
{
assert(lh.igt_proc.running);
@@ -521,7 +550,7 @@ int main(int argc, char **argv)
min_max_config(idle_check);
igt_subtest("min-max-config-loaded") {
- load_helper_run();
+ load_helper_run(HIGH);
min_max_config(loaded_check);
load_helper_stop();
}
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] Android build system clean-up
From: Rafael Barbalho IGT in android still had some hang-ups from the initial porting, we were re-compiling the lib directory every time for each tool or test binary. It also could get its include paths confused due to overloaded make variable names. It also wasn't possible to do the typical android thing of issuing the "mm" command inside either the tests or tools directory to only rebuild & install the binaries that you modified. The patch series tries to clean all this up by using the new include path mechanism introduced in recent versions of android and making the lib directory as a static library in the same way that is it done in the autotools version. Rafael Barbalho (5): android: Handle the case when android doesn't have mmap64 android: Clean-up common makefile directives android: Add makefile for the lib directory android: Add the generation of vesion.h & config.h to lib android: Change tests & tools directory to use the lib directory Android.mk| 5 +--- lib/Android.mk| 64 +++ lib/intel_gpu_tools.h | 11 tests/Android.mk | 69 --- tools/Android.mk | 37 --- 5 files changed, 86 insertions(+), 100 deletions(-) create mode 100644 lib/Android.mk -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] pm_rps: New subtest for gpu reset
From: Jeff McGee
Test that RPS functions as expected after a gpu reset.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 05b859c..846abe6 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -133,6 +133,16 @@ static void checkit(const int *freqs)
igt_assert(freqs[RP1] != 0);
}
+static void matchit(const int *freqs1, const int *freqs2)
+{
+ igt_assert(freqs1[CUR] == freqs2[CUR]);
+ igt_assert(freqs1[MIN] == freqs2[MIN]);
+ igt_assert(freqs1[MAX] == freqs2[MAX]);
+ igt_assert(freqs1[RP0] == freqs2[RP0]);
+ igt_assert(freqs1[RP1] == freqs2[RP1]);
+ igt_assert(freqs1[RPn] == freqs2[RPn]);
+}
+
static void dumpit(const int *freqs)
{
int i;
@@ -462,6 +472,55 @@ static void loaded_check(void)
log("Required %d msec to reach cur=max\n", wait);
}
+#define STABILIZE_WAIT_TIMESTEP_MSEC 100
+#define STABILIZE_WAIT_TIMEOUT_MSEC 2000
+static void stabilize_check(int *freqs)
+{
+ int wait = 0;
+
+ do {
+ read_freqs(freqs);
+ dump(freqs);
+ usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
+ wait += STABILIZE_WAIT_TIMESTEP_MSEC;
+ } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
+
+ log("Waited %d msec to stabilize cur\n", wait);
+}
+
+static void reset(void)
+{
+ int pre_freqs[NUMFREQ];
+ int post_freqs[NUMFREQ];
+
+ log("Apply low load...\n");
+ load_helper_run(LOW);
+ stabilize_check(pre_freqs);
+
+ log("Stop rings...\n");
+ stop_rings();
+ while (rings_stopped())
+ usleep(1000 * 100);
+ log("Ring stop cleared\n");
+
+ log("Apply high load...\n");
+ load_helper_set_load(HIGH);
+ loaded_check();
+
+ log("Apply low load...\n");
+ load_helper_set_load(LOW);
+ stabilize_check(post_freqs);
+ matchit(pre_freqs, post_freqs);
+
+ log("Apply high load...\n");
+ load_helper_set_load(HIGH);
+ loaded_check();
+
+ log("Removing load...\n");
+ load_helper_stop();
+ idle_check();
+}
+
static void pm_rps_exit_handler(int sig)
{
if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
@@ -555,5 +614,8 @@ int main(int argc, char **argv)
load_helper_stop();
}
+ igt_subtest("reset")
+ reset();
+
igt_exit();
}
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/11] drm: Set property to return invalid for unsupported arguments for bitmask property
From: Sagar Kamble
DRM will not propagate the set_property call for bitmask drm
properties if they are not supported by underlying driver.
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_crtc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 4f5e408..4c92741 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3420,6 +3420,8 @@ int drm_mode_obj_set_property_ioctl(struct drm_device
*dev, void *data,
struct drm_mode_object *arg_obj;
struct drm_mode_object *prop_obj;
struct drm_property *property;
+ struct drm_property_enum *prop_enum;
+ bool supported_val = false;
int ret = -EINVAL;
int i;
@@ -3451,6 +3453,22 @@ int drm_mode_obj_set_property_ioctl(struct drm_device
*dev, void *data,
}
property = obj_to_property(prop_obj);
+ if (property->flags | DRM_MODE_PROP_BITMASK) {
+ if (!list_empty(&property->enum_blob_list)) {
+ list_for_each_entry(prop_enum,
+ &property->enum_blob_list, head) {
+ if (BIT(prop_enum->value) == arg->value) {
+ supported_val = true;
+ break;
+ }
+ }
+ }
+ if (!supported_val) {
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
if (!drm_property_change_is_valid(property, arg->value))
goto out;
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Add reset subtest to pm_rps
From: Jeff McGee This patch set is dependent on set "Add two new subtests to pm_rps". Jeff McGee (4): pm_rps: Add stop rings injection utility pm_rps: Load helper should stall for last write pm_rps: Add variable load support to load helper pm_rps: New subtest for gpu reset tests/pm_rps.c | 138 +++-- 1 file changed, 135 insertions(+), 3 deletions(-) -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] android: Handle the case when android doesn't have mmap64
From: Rafael Barbalho
Not all versions of Android have the mmap64 call, thus a suitable alternative
must be called.
Signed-off-by: Rafael Barbalho
---
lib/intel_gpu_tools.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index b242243..1ae1bab 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -35,6 +35,17 @@
#include "intel_chipset.h"
#include "intel_reg.h"
+#ifdef ANDROID
+#ifndef HAVE_MMAP64
+extern void* __mmap2(void *, size_t, int, int, int, off_t);
+static inline void *mmap64(void *addr, size_t length, int prot, int flags,
+int fd, off64_t offset)
+{
+return __mmap2(addr, length, prot, flags, fd, offset >> 12);
+}
+#endif
+#endif
+
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
extern void *mmio;
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO
On Fri, Jan 31, 2014 at 01:41:08PM +0200, Jani Nikula wrote:
> The WARN is a bit too verbose, make it a DRM_INFO that gets printed
> once.
>
> While at it, fix the typo in DSLP.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_opregion.c |6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> b/drivers/gpu/drm/i915/intel_opregion.c
> index 46d288055345..0fae017c4c7b 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -263,7 +263,11 @@ static int swsci(struct drm_device *dev, u32 function,
> u32 parm, u32 *parm_out)
> dslp = 50;
> } else if (dslp > 1500) {
> /* Hey bios, trust must be earned. */
> - WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
> dslp);
> + static bool warned;
> + if (!warned) {
> + DRM_INFO("excessive driver sleep timeout (DSLP) %u\n",
> dslp);
DRM_INFO("ACPI BIOS requests an excessive sleep of %d ms, using %d instead\n",
dslp, MAX_DSLP);
> + warned = true;
> + }
> dslp = 1500;
> }
>
> --
> 1.7.9.5
>
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/11] drm/omap: Switch omapdrm over to drm_mode_create_rotation_property()
From: Sagar Kamble
Use the new drm_mode_create_rotation_property() in omapdrm.
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/omapdrm/omap_plane.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c
b/drivers/gpu/drm/omapdrm/omap_plane.c
index 046d5e6..fee8f35 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -300,16 +300,13 @@ void omap_plane_install_properties(struct drm_plane
*plane,
if (priv->has_dmm) {
prop = priv->rotation_prop;
if (!prop) {
- const struct drm_prop_enum_list props[] = {
- { DRM_ROTATE_0, "rotate-0" },
- { DRM_ROTATE_90, "rotate-90" },
- { DRM_ROTATE_180, "rotate-180" },
- { DRM_ROTATE_270, "rotate-270" },
- { DRM_REFLECT_X, "reflect-x" },
- { DRM_REFLECT_Y, "reflect-y" },
- };
- prop = drm_property_create_bitmask(dev, 0, "rotation",
- props, ARRAY_SIZE(props));
+ prop = drm_mode_create_rotation_property(dev,
+
BIT(DRM_ROTATE_0) |
+
BIT(DRM_ROTATE_90) |
+
BIT(DRM_ROTATE_180) |
+
BIT(DRM_ROTATE_270) |
+
BIT(DRM_REFLECT_X) |
+
BIT(DRM_REFLECT_Y));
if (prop == NULL)
return;
priv->rotation_prop = prop;
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/11] drm/i915: Make intel_plane_restore() return an error
From: Sagar Kamble
Propagate the error from intel_update_plane() up through
intel_plane_restore() to the caller. This will be used for
rollback purposes when setting properties fails.
Signed-off-by: Ville Syrjala
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_drv.h| 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 14 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 85864fc..7a79b8e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -897,7 +897,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t
sdvo_reg, bool is_sdvob);
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane);
-void intel_plane_restore(struct drm_plane *plane);
+int intel_plane_restore(struct drm_plane *plane);
void intel_plane_disable(struct drm_plane *plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index f9c8c41..11560a6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1044,18 +1044,18 @@ out_unlock:
return ret;
}
-void intel_plane_restore(struct drm_plane *plane)
+int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
if (!plane->crtc || !plane->fb)
- return;
+ return 0;
- intel_update_plane(plane, plane->crtc, plane->fb,
- intel_plane->crtc_x, intel_plane->crtc_y,
- intel_plane->crtc_w, intel_plane->crtc_h,
- intel_plane->src_x, intel_plane->src_y,
- intel_plane->src_w, intel_plane->src_h);
+ return intel_update_plane(plane, plane->crtc, plane->fb,
+ intel_plane->crtc_x, intel_plane->crtc_y,
+ intel_plane->crtc_w, intel_plane->crtc_h,
+ intel_plane->src_x, intel_plane->src_y,
+ intel_plane->src_w, intel_plane->src_h);
}
void intel_plane_disable(struct drm_plane *plane)
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
From: Sagar Kamble
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
Signed-off-by: Uma Shankar
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 54 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57906c5..d3000c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3553,6 +3553,7 @@
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
+#define DISPPLANE_ROTATE_180 (1<<15)
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
#define DISPPLANE_TILED (1<<10)
#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..483de59 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
unsigned long linear_offset;
u32 dspcntr;
u32 reg;
+ int pixel_size;
switch (plane) {
case 0:
@@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
return -EINVAL;
}
+ pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
intel_fb = to_intel_framebuffer(fb);
obj = intel_fb->obj;
@@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
dspcntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+ dspcntr &= ~DISPPLANE_ROTATE_180;
+
switch (fb->pixel_format) {
case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
@@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- I915_WRITE(reg, dspcntr);
-
linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
if (INTEL_INFO(dev)->gen >= 4) {
@@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
intel_crtc->dspaddr_offset = linear_offset;
}
+ if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) {
+ dspcntr |= DISPPLANE_ROTATE_180;
+
+ x += (fb->width - 1);
+ y += (fb->height - 1);
+ linear_offset += (fb->height - 1) * fb->pitches[0] +
+ fb->width * pixel_size;
+ }
+
+ I915_WRITE(reg, dspcntr);
+
DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
fb->pitches[0]);
@@ -8748,6 +8761,31 @@ free_work:
return ret;
}
+static int intel_crtc_set_property(struct drm_crtc *crtc,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == dev_priv->rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val & 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_crtc->rotation;
+ intel_crtc->rotation = val;
+ ret = dev_priv->display.update_plane(crtc, crtc->fb, 0, 0);
+ if (ret)
+ intel_crtc->rotation = old_val;
+ }
+
+ return ret;
+}
+
static struct drm_crtc_helper_funcs intel_helper_funcs = {
.mode_set_base_atomic = intel_pipe_set_base_atomic,
.load_lut = intel_crtc_load_lut,
@@ -10160,6 +10198,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.set_config = intel_crtc_set_config,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
+ .set_property = intel_crtc_set_property
};
static void intel_cpu_pll_init(struct drm_device *dev)
@@ -10288,6 +10327,7 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
*/
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
+ intel_crtc->rotation = BIT(DRM_ROTATE_0);
if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Re: [Intel-gfx] [PATCH v6] drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
On Thu, Jan 30, 2014 at 11:08:16PM +0530, deepa...@intel.com wrote: > From: Deepak S > > When we enter RC6 and GFX Clocks are off, the voltage remains higher > than Vmin. When we try to set the freq to RPn, it might fail since the > Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up > and set the freq to RPn then move GFx down. > > v2: remove vlv_update_rps_cur_delay function. Update commit message (Daniel) > > v3: Fix the timeout during wait for gfx clock (Jesse) > > v4: addressed comments on set freq and punit wait (Ville) > > v5: use wait_for while waiting for GFX clk to be up. (Daniel) > update cur_delay before requesting min_delay. (Ville) > > v6: use wait_for while waiting for punit. (Ville) > > Signed-off-by: Deepak S > Reviewed-by: Ville Syrjä ^^ Stuff missing from my name. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/11] drm: Add drm_rotation_simplify()
From: Sagar Kamble
drm_rotation_simplify() can be used to eliminate unsupported rotation
flags. It will check if any unsupported flags are present, and if so
it will modify the rotation to an alternate form by adding 180 degrees
to rotation angle, and flipping the reflect x and y bits. The hope is
that this identity transform will eliminate the unsupported flags.
Of course that might not result in any more supported rotation, so
the caller is still responsible for checking the result afterwards.
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/drm_crtc.c | 30 ++
include/drm/drm_crtc.h | 3 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 87744d6..b0a2889 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4002,6 +4002,36 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_rotation_simplify() - Try to simplify the rotation
+ * @rotation: Rotation to be simplified
+ * @supported_rotations: Supported rotations
+ *
+ * Attempt to simplify the rotation to a form that is supported.
+ * Eg. if the hardware supports everything except DRM_REFLECT_X
+ * one could call this function like this:
+ *
+ * drm_rotation_simplify(rotation, BIT(DRM_ROTATE_0) |
+ * BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) |
+ * BIT(DRM_ROTATE_270) | BIT(DRM_REFLECT_Y));
+ *
+ * to eliminate the DRM_ROTATE_X flag. Depending on what kind of
+ * transforms the hardware supports, this function may not
+ * be able to produce a supported transform, so the caller should
+ * check the result afterwards.
+ */
+unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations)
+{
+ if (rotation & ~supported_rotations) {
+ rotation ^= BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y);
+ rotation = (rotation & ~0xf) | BIT((ffs(rotation & 0xf) + 1) %
4);
+ }
+
+ return rotation;
+}
+EXPORT_SYMBOL(drm_rotation_simplify);
+
+/**
* drm_mode_config_init - initialize DRM mode_configuration structure
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b7d0f3c..5a6c345 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1184,6 +1184,9 @@ extern int drm_format_vert_chroma_subsampling(uint32_t
format);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
unsigned int
supported_rotations);
+extern unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations);
+
/* Helpers */
static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] android: Clean-up common makefile directives
From: Rafael Barbalho All the Android.mk files had the same directives to find the path of libdrm & libpciaccess. These are no longer required as the android system now allows the libraries being used to export include paths to dependant modules & programs. Signed-off-by: Rafael Barbalho --- tests/Android.mk | 20 +--- tools/Android.mk | 20 +--- 2 files changed, 2 insertions(+), 38 deletions(-) diff --git a/tests/Android.mk b/tests/Android.mk index abccb7f..0e292a9 100644 --- a/tests/Android.mk +++ b/tests/Android.mk @@ -1,21 +1,6 @@ include $(LOCAL_PATH)/tests/Makefile.sources include $(LOCAL_PATH)/lib/Makefile.sources -LIBPCIACCESS_PATH := $(firstword $(wildcard \ - $(TOP)/external/PRIVATE/libpciaccess \ - $(TOP)/hardware/intel/libpciaccess\ - $(TOP)/external/libpciaccess)) -ifeq ($(LIBPCIACCESS_PATH),) - $(error "Unable to find libpciaccess!") -endif - -LIBDRM_PATH := $(firstword $(wildcard \ - $(TOP)/external/PRIVATE/drm \ - $(TOP)/external/drm)) -ifeq ($(LIBDRM_PATH),) - $(error "Unable to find libdrm!") -endif - skip_lib_list := \ igt_kms.c \ igt_kms.h @@ -65,10 +50,7 @@ define add_test $(LOCAL_PATH)/config.h LOCAL_C_INCLUDES += \ - $(LOCAL_PATH)/lib \ - $(LIBDRM_PATH)/include/drm\ - $(LIBDRM_PATH)/intel \ - $(LIBPCIACCESS_PATH)/include + $(LOCAL_PATH)/lib LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM LOCAL_CFLAGS += -DANDROID -UNDEBUG -include "check-ndebug.h" diff --git a/tools/Android.mk b/tools/Android.mk index 99c39b7..7227c89 100644 --- a/tools/Android.mk +++ b/tools/Android.mk @@ -1,21 +1,6 @@ include $(LOCAL_PATH)/tools/Makefile.sources include $(LOCAL_PATH)/lib/Makefile.sources -LIBPCIACCESS_PATH := $(firstword $(wildcard \ - $(TOP)/external/PRIVATE/libpciaccess \ - $(TOP)/hardware/intel/libpciaccess\ - $(TOP)/external/libpciaccess)) -ifeq ($(LIBPCIACCESS_PATH),) - $(error "Unable to find libpciaccess!") -endif - -LIBDRM_PATH := $(firstword $(wildcard \ - $(TOP)/external/PRIVATE/drm \ - $(TOP)/external/drm)) -ifeq ($(LIBDRM_PATH),) - $(error "Unable to find libdrm!") -endif - skip_lib_list := \ igt_kms.c \ igt_kms.h @@ -33,10 +18,7 @@ define add_tool $(LIB_SOURCES) LOCAL_C_INCLUDES += \ - $(LOCAL_PATH)/lib \ - $(LIBDRM_PATH)/include/drm\ - $(LIBDRM_PATH)/intel \ - $(LIBPCIACCESS_PATH)/include + $(LOCAL_PATH)/lib LOCAL_CFLAGS += -DHAVE_TERMIOS_H LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/11] drm/i915: Add 180 degree sprite rotation support
From: Sagar Kamble
The sprite planes (in fact all display planes starting from gen4)
support 180 degree rotation. Add the relevant low level bits to the
sprite code to make use of that feature.
The upper layers are not yet plugged in.
Signed-off-by: Ville Syrjala
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_sprite.c | 34 ++
3 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd18cd..57906c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3637,6 +3637,7 @@
#define DVS_YUV_ORDER_UYVY (1<<16)
#define DVS_YUV_ORDER_YVYU (2<<16)
#define DVS_YUV_ORDER_VYUY (3<<16)
+#define DVS_ROTATE_180 (1<<15)
#define DVS_DEST_KEY (1<<2)
#define DVS_TRICKLE_FEED_DISABLE (1<<14)
#define DVS_TILED(1<<10)
@@ -3707,6 +3708,7 @@
#define SPRITE_YUV_ORDER_UYVY(1<<16)
#define SPRITE_YUV_ORDER_YVYU(2<<16)
#define SPRITE_YUV_ORDER_VYUY(3<<16)
+#define SPRITE_ROTATE_180(1<<15)
#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
#define SPRITE_INT_GAMMA_ENABLE (1<<13)
#define SPRITE_TILED (1<<10)
@@ -3780,6 +3782,7 @@
#define SP_YUV_ORDER_UYVY(1<<16)
#define SP_YUV_ORDER_YVYU(2<<16)
#define SP_YUV_ORDER_VYUY(3<<16)
+#define SP_ROTATE_180(1<<15)
#define SP_TILED (1<<10)
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44067bc..85864fc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -397,6 +397,7 @@ struct intel_plane {
unsigned int crtc_w, crtc_h;
uint32_t src_x, src_y;
uint32_t src_w, src_h;
+ unsigned int rotation;
/* Since we need to change the watermarks before/after
* enabling/disabling the planes, we need to store the parameters here
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 336ae6c..f9c8c41 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -60,6 +60,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
sprctl &= ~SP_PIXFORMAT_MASK;
sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
sprctl &= ~SP_TILED;
+ sprctl &= ~SP_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_YUYV:
@@ -131,6 +132,14 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SP_ROTATE_180;
+
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+ }
+
I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
@@ -238,6 +247,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
sprctl &= ~SPRITE_RGB_ORDER_RGBX;
sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl &= ~SPRITE_TILED;
+ sprctl &= ~SPRITE_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
@@ -299,6 +309,14 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
pixel_size, fb->pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SPRITE_ROTATE_180;
+
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+ }
+
I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
@@ -422,6 +440,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
dvscntr &= ~DVS_RGB_ORDER_XBGR;
dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
dvscntr &= ~DVS_TILED;
+ dvscntr &= ~DVS_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
@@ -478,6 +497,14 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
pixel_size, fb->pitches[0]);
linear_offset -= dvssurf_offset;
+ if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+ dvscntr |= DVS_ROTATE_180;
+
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+
[Intel-gfx] [PATCH 01/11] drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h
From: Sagar Kamble
The rotation property stuff should be standardized among all drivers.
Move the bits to drm_crtc.h from omap_drv.h.
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/omapdrm/omap_drv.h | 7 ---
include/drm/drm_crtc.h | 8
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h
b/drivers/gpu/drm/omapdrm/omap_drv.h
index 428b2981..aac8e10 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -119,13 +119,6 @@ struct omap_drm_private {
struct omap_drm_irq error_handler;
};
-/* this should probably be in drm-core to standardize amongst drivers */
-#define DRM_ROTATE_0 0
-#define DRM_ROTATE_90 1
-#define DRM_ROTATE_180 2
-#define DRM_ROTATE_270 3
-#define DRM_REFLECT_X 4
-#define DRM_REFLECT_Y 5
#ifdef CONFIG_DEBUG_FS
int omap_debugfs_init(struct drm_minor *minor);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 71727b6..d5c46c1 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -65,6 +65,14 @@ struct drm_object_properties {
uint64_t values[DRM_OBJECT_MAX_PROPERTY];
};
+/* rotation property bits */
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+
/*
* Note on terminology: here, for brevity and convenience, we refer to
connector
* control chips as 'CRTCs'. They can control any type of connector, VGA,
LVDS,
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] pm_rps: Load helper should stall for last write
From: Jeff McGee
This ensures that gpu is quiescent when load helper exits.
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index a6807d2..9277196 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -207,6 +207,10 @@ static void load_helper_run(void)
val++;
}
+ /* Map buffer to stall for write completion */
+ drm_intel_bo_map(lh.target_buffer, 0);
+ drm_intel_bo_unmap(lh.target_buffer);
+
log("load helper sent %u dword writes\n", val);
}
}
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6] drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
On 1/31/2014 10:40 PM, Ville Syrjälä wrote: On Thu, Jan 30, 2014 at 11:08:16PM +0530, deepa...@intel.com wrote: From: Deepak S When we enter RC6 and GFX Clocks are off, the voltage remains higher than Vmin. When we try to set the freq to RPn, it might fail since the Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up and set the freq to RPn then move GFx down. v2: remove vlv_update_rps_cur_delay function. Update commit message (Daniel) v3: Fix the timeout during wait for gfx clock (Jesse) v4: addressed comments on set freq and punit wait (Ville) v5: use wait_for while waiting for GFX clk to be up. (Daniel) update cur_delay before requesting min_delay. (Ville) v6: use wait_for while waiting for punit. (Ville) Signed-off-by: Deepak S Reviewed-by: Ville Syrjä ^^ Stuff missing from my name. Sorry Something got missed while uploading the patch :( ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/11] drm: Add drm_rect rotation functions
From: Sagar Kamble
Add some helper functions to move drm_rects between different rotated
coordinate spaces. One function does the forward transform and
another does the inverse.
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/drm_rect.c | 140 +
include/drm/drm_rect.h | 6 ++
2 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c
index 7047ca0..631f5af 100644
--- a/drivers/gpu/drm/drm_rect.c
+++ b/drivers/gpu/drm/drm_rect.c
@@ -293,3 +293,143 @@ void drm_rect_debug_print(const struct drm_rect *r, bool
fixed_point)
DRM_DEBUG_KMS("%dx%d%+d%+d\n", w, h, r->x1, r->y1);
}
EXPORT_SYMBOL(drm_rect_debug_print);
+
+/**
+ * drm_rect_rotate - Rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation to be applied
+ *
+ * Apply @rotation to the coordinates of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the untransformed coordinate
+ * space.
+ */
+void drm_rect_rotate(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation & BIT(DRM_REFLECT_X)) {
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ }
+
+ if (rotation & BIT(DRM_REFLECT_Y)) {
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ }
+ }
+
+ switch (rotation & 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r->x1 = tmp.y1;
+ r->x2 = tmp.y2;
+ r->y1 = width - tmp.x2;
+ r->y2 = width - tmp.x1;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r->x1 = height - tmp.y2;
+ r->x2 = height - tmp.y1;
+ r->y1 = tmp.x1;
+ r->y2 = tmp.x2;
+ break;
+ default:
+ break;
+ }
+}
+EXPORT_SYMBOL(drm_rect_rotate);
+
+/**
+ * drm_rect_rotate_inv - Inverse rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation whose inverse is to be applied
+ *
+ * Apply the inverse of @rotation to the coordinates
+ * of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the original untransformed
+ * coordinate space, so that you never have to flip
+ * them when doing a rotatation and its inverse.
+ * That is, if you do:
+ *
+ * drm_rotate(&r, width, height, rotation);
+ * drm_rotate_inv(&r, width, height, rotation);
+ *
+ * you will always get back the original rectangle.
+ */
+void drm_rect_rotate_inv(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ switch (rotation & 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r->x1 = width - tmp.y2;
+ r->x2 = width - tmp.y1;
+ r->y1 = tmp.x1;
+ r->y2 = tmp.x2;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r->x1 = tmp.y1;
+ r->x2 = tmp.y2;
+ r->y1 = height - tmp.x2;
+ r->y2 = height - tmp.x1;
+ break;
+ default:
+ break;
+ }
+
+ if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation & BIT(DRM_REFLECT_X)) {
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ }
+
+ if (rotation & BIT(DRM_REFLECT_Y)) {
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ }
+ }
+}
+EX
Re: [Intel-gfx] [PATCH 09/28] drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2
Reviewed-by: Rodrigo Vivi
I think this was the last wa patch to be reviewed yet. Please let me
know if I' m still missing any.
On Wed, Jan 22, 2014 at 2:32 PM, wrote:
> From: Ville Syrjälä
>
> Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
> is only needed for IVB GT1.
>
> The only real confusion here is that the the W/A database also says to
> write to the GT2 only register as well, which is strange if the W/A is
> only for GT1.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b268a55..6781845 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4828,13 +4828,6 @@ static void ivybridge_init_clock_gating(struct
> drm_device *dev)
> if (IS_IVB_GT1(dev))
> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - else {
> - /* must write both registers */
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> -
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> -
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - }
>
> /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> --
> 1.8.3.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] demos: Add intel_plane_rotate test to verify rotation of planes and crtc
From: Sagar Kamble
This test will verify the 180 degree rotation of sprite and crtc planes.
It will allow user to control rotation separately for crtc and sprite
planes.
Signed-off-by: Sagar Kamble
---
demos/Makefile.am | 1 +
demos/intel_plane_rotate.c | 929 +
2 files changed, 930 insertions(+)
create mode 100644 demos/intel_plane_rotate.c
diff --git a/demos/Makefile.am b/demos/Makefile.am
index 49804d7..1cee2b6 100644
--- a/demos/Makefile.am
+++ b/demos/Makefile.am
@@ -1,5 +1,6 @@
bin_PROGRAMS = \
intel_sprite_on \
+ intel_plane_rotate \
$(NULL)
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
diff --git a/demos/intel_plane_rotate.c b/demos/intel_plane_rotate.c
new file mode 100644
index 000..b203d75
--- /dev/null
+++ b/demos/intel_plane_rotate.c
@@ -0,0 +1,929 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ *
+ * Author:
+ * Sagar Kamble
+ */
+
+/*
+ * Most of the functions are reused from intel_sprite_on test by Armeen Reese
+ *
+ * This program is intended for testing CRTC and plane rotation functionality.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "igt_kms.h"
+
+#if defined(DRM_IOCTL_MODE_ADDFB2) && defined(DRM_I915_SET_SPRITE_COLORKEY)
+#define TEST_PLANES 1
+#include "drm_fourcc.h"
+#endif
+
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+
+#define BIT(x) (1 << x)
+
+/*
+ * Mode setting with the kernel interfaces is a bit of a chore.
+ * First you have to find the connector in question and make sure the
+ * requested mode is available.
+ * Then you need to find the encoder attached to that connector so you
+ * can bind it with a free crtc.
+ */
+struct connector {
+ uint32_tid;
+ int mode_valid;
+ drmModeModeInfo mode;
+ drmModeEncoder *encoder;
+ drmModeConnector*connector;
+ int crtc;
+ int pipe;
+};
+
+static void dump_mode(drmModeModeInfo *mode)
+{
+ printf(" %s %d %d %d %d %d %d %d %d %d 0x%x 0x%x %d\n",
+ mode->name,
+ mode->vrefresh,
+ mode->hdisplay,
+ mode->hsync_start,
+ mode->hsync_end,
+ mode->htotal,
+ mode->vdisplay,
+ mode->vsync_start,
+ mode->vsync_end,
+ mode->vtotal,
+ mode->flags,
+ mode->type,
+ mode->clock);
+}
+
+static void dump_connectors(int gfx_fd, drmModeRes *resources)
+{
+ int i, j;
+
+ printf("Connectors:\n");
+ printf("id\tencoder\tstatus\t\ttype\tsize (mm)\tmodes\n");
+ for (i = 0; i < resources->count_connectors; i++) {
+ drmModeConnector *connector;
+
+ connector = drmModeGetConnector(gfx_fd,
resources->connectors[i]);
+ if (!connector) {
+ printf("could not get connector %i: %s\n",
+ resources->connectors[i],
strerror(errno));
+ continue;
+ }
+
+ printf("%d\t%d\t%s\t%s\t%dx%d\t\t%d\n",
+ connector->connector_id,
+ connector->encoder_id,
+ kmstest_connector_status_str(connector->connection),
+ kmstest_connector_type_str(connector->connector_type),
+ connector->mmWidth, connector->mmHeight,
+ connector->count_modes);
+
Re: [Intel-gfx] [PATCH 2/2] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO_ONCE
On Fri, Jan 31, 2014 at 03:49:08PM +0200, Jani Nikula wrote: > The WARN_ONCE is a bit too verbose, make it a DRM_INFO_ONCE. > > While at it, add a #define for MAX_DSLP and make the message a bit more > informative. > > v2: use DRM_INFO_ONCE, add MAX_DSLP, pimp the message. > > Suggested-by: Chris Wilson > Signed-off-by: Jani Nikula Both Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/11] drm: Add support_bits parameter to drm_property_create_bitmask()
From: Sagar Kamble
Make drm_property_create_bitmask() a bit more generic by allowing the
caller to specify which bits are in fact supported. This allows multiple
callers to use the same enum list, but still create different versions
of the same property with different list of supported bits.
Signed-off-by: Ville Syrjala
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_crtc.c | 6 +-
include/drm/drm_crtc.h | 3 ++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index b0a2889..4f5e408 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2906,7 +2906,8 @@ EXPORT_SYMBOL(drm_property_create_enum);
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values)
+int num_values,
+unsigned int supported_bits)
{
struct drm_property *property;
int i, ret;
@@ -2918,6 +2919,9 @@ struct drm_property *drm_property_create_bitmask(struct
drm_device *dev,
return NULL;
for (i = 0; i < num_values; i++) {
+ if (!(supported_bits & (1 << i)))
+ continue;
+
ret = drm_property_add_enum(property, i,
props[i].type,
props[i].name);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5a6c345..e227e85 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1070,7 +1070,8 @@ extern struct drm_property
*drm_property_create_enum(struct drm_device *dev, int
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values);
+int num_values,
+unsigned int supported_bits);
struct drm_property *drm_property_create_range(struct drm_device *dev, int
flags,
const char *name,
uint64_t min, uint64_t max);
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm: add DRM_INFO_ONCE() to print a one-time DRM_INFO() message
Just like DRM_INFO(), but only do it once. Signed-off-by: Jani Nikula --- include/drm/drmP.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 04086c5be930..04a7f31301f8 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -199,6 +199,9 @@ int drm_err(const char *func, const char *format, ...); #define DRM_INFO(fmt, ...) \ printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__) +#define DRM_INFO_ONCE(fmt, ...)\ + printk_once(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__) + /** * Debug output. * -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7] drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
From: Deepak S
When we enter RC6 and GFX Clocks are off, the voltage remains higher
than Vmin. When we try to set the freq to RPn, it might fail since the
Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up
and set the freq to RPn then move GFx down.
v2: remove vlv_update_rps_cur_delay function. Update commit message (Daniel)
v3: Fix the timeout during wait for gfx clock (Jesse)
v4: addressed comments on set freq and punit wait (Ville)
v5: use wait_for while waiting for GFX clk to be up. (Daniel)
update cur_delay before requesting min_delay. (Ville)
v6: use wait_for while waiting for punit. (Ville)
v7: Correct reviewer's name (Ville)
Signed-off-by: Deepak S
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 55 -
4 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac5cd7e..6f9108d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1961,6 +1961,8 @@ extern void intel_console_resume(struct work_struct
*work);
void i915_queue_hangcheck(struct drm_device *dev);
void i915_handle_error(struct drm_device *dev, bool wedged);
+void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
+ int new_delay);
extern void intel_irq_init(struct drm_device *dev);
extern void intel_hpd_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b226ae6..acbee73 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -986,7 +986,7 @@ static void notify_ring(struct drm_device *dev,
i915_queue_hangcheck(dev);
}
-static void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
+void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
u32 pm_iir, int new_delay)
{
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbbaf26..00d2f2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4949,6 +4949,10 @@
GEN6_PM_RP_DOWN_THRESHOLD | \
GEN6_PM_RP_DOWN_TIMEOUT)
+#define VLV_GTLC_SURVIVABILITY_REG 0x130098
+#define VLV_GFX_CLK_STATUS_BIT (1<<3)
+#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
+
#define GEN6_GT_GFX_RC6_LOCKED 0x138104
#define VLV_COUNTER_CONTROL0x138104
#define VLV_COUNT_RANGE_HIGH (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4876ba5..3b5a1b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3038,6 +3038,58 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
+/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
+ *
+ * * If Gfx is Idle, then
+ * 1. Mask Turbo interrupts
+ * 2. Bring up Gfx clock
+ * 3. Change the freq to Rpn and wait till P-Unit updates freq
+ * 4. Clear the Force GFX CLK ON bit so that Gfx can down
+ * 5. Unmask Turbo interrupts
+*/
+static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
+{
+ /*
+* When we are idle. Drop to min voltage state.
+*/
+
+ if (dev_priv->rps.cur_delay <= dev_priv->rps.min_delay)
+ return;
+
+ /* Mask turbo interrupt so that they will not come in between */
+ I915_WRITE(GEN6_PMINTRMSK, 0x);
+
+ /* Bring up the Gfx clock */
+ I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
+ I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
+ VLV_GFX_CLK_FORCE_ON_BIT);
+
+ if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
+ I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
+ DRM_ERROR("GFX_CLK_ON request timed out\n");
+ return;
+ }
+
+ dev_priv->rps.cur_delay = dev_priv->rps.min_delay;
+
+ vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
+ dev_priv->rps.min_delay);
+
+ if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
+ & GENFREQSTATUS) == 0, 5))
+ DRM_ERROR("timed out waiting for Punit\n");
+
+ /* Release the Gfx clock */
+ I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
+ I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
+ ~VLV_GFX_CLK_FORCE_ON_BIT);
+
+ /* Unmask Up interrupts */
+ dev_priv->rps.rp_up_masked = true;
+ gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD,
+
[Intel-gfx] [PATCH 4/5] android: Add the generation of vesion.h & config.h to lib
From: Rafael Barbalho The lib directory is used by all the tests & tools so it should really be the place where the generate files are created. Signed-off-by: Rafael Barbalho --- lib/Android.mk | 33 + 1 file changed, 33 insertions(+) diff --git a/lib/Android.mk b/lib/Android.mk index 23c7d42..724d884 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -1,5 +1,34 @@ LOCAL_PATH := $(call my-dir) +GPU_TOOLS_PATH := $(LOCAL_PATH)/.. + +.PHONY: version.h.tmp + +$(GPU_TOOLS_PATH)/version.h.tmp: + @touch $@ + @if test -d ../.git; then \ + if which git > /dev/null; then git log -n 1 --oneline | \ + sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' \ + >> $@ ; \ + fi \ + else \ + echo '#define IGT_GIT_SHA1 "NOT-GIT"' >> $@ ; \ + fi + +$(GPU_TOOLS_PATH)/version.h: $(GPU_TOOLS_PATH)/version.h.tmp + @echo "updating version.h" + @if ! cmp -s $(GPU_TOOLS_PATH)/version.h.tmp $(GPU_TOOLS_PATH)/version.h; then \ + mv $(GPU_TOOLS_PATH)/version.h.tmp $(GPU_TOOLS_PATH)/version.h ; \ + else \ + rm $(GPU_TOOLS_PATH)/version.h.tmp ; \ + fi + +# FIXME: autogenerate this info # +$(GPU_TOOLS_PATH)/config.h: + @echo "updating config.h" + @echo '#define PACKAGE_VERSION "1.5"' >> $@ ; \ + echo '#define TARGET_CPU_PLATFORM "android-ia"' >> $@ ; + include $(LOCAL_PATH)/Makefile.sources skip_lib_list := \ @@ -12,6 +41,10 @@ include $(CLEAR_VARS) LOCAL_SRC_FILES := $(lib_list) +LOCAL_GENERATED_SOURCES := \ + $(GPU_TOOLS_PATH)/version.h \ + $(GPU_TOOLS_PATH)/config.h + LOCAL_C_INCLUDES += \ $(LOCAL_PATH)/.. -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: demote opregion excessive timeout WARN_ONCE to DRM_INFO_ONCE
The WARN_ONCE is a bit too verbose, make it a DRM_INFO_ONCE.
While at it, add a #define for MAX_DSLP and make the message a bit more
informative.
v2: use DRM_INFO_ONCE, add MAX_DSLP, pimp the message.
Suggested-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 46d288055345..68459605bd12 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -227,6 +227,8 @@ struct opregion_asle {
#define ACPI_DIGITAL_OUTPUT (3<<8)
#define ACPI_LVDS_OUTPUT (4<<8)
+#define MAX_DSLP 1500
+
#ifdef CONFIG_ACPI
static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out)
{
@@ -261,10 +263,11 @@ static int swsci(struct drm_device *dev, u32 function,
u32 parm, u32 *parm_out)
/* The spec says 2ms should be the default, but it's too small
* for some machines. */
dslp = 50;
- } else if (dslp > 1500) {
+ } else if (dslp > MAX_DSLP) {
/* Hey bios, trust must be earned. */
- WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n",
dslp);
- dslp = 1500;
+ DRM_INFO_ONCE("ACPI BIOS requests an excessive sleep of %u ms, "
+ "using %u ms instead\n", dslp, MAX_DSLP);
+ dslp = MAX_DSLP;
}
/* The spec tells us to do this, but we are the only user... */
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/11] Enabling 180 degree rotation for sprite and crtc planes
From: Sagar Kamble With these patches 180 degree rotation for crtc and sprite planes will be exposed through drm rotation properties implemented by Ville few days back. I have added CRTC rotation support on top of Ville's 9 patches that includes sprite rotation. Omapdrm changes, rotation_simplify, drm_rect functions are also included in this list. Functionality has been tested with i-g-t test "intel_plane_rotate". Sagar Kamble (11): drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h drm: Add drm_mode_create_rotation_property() drm/omap: Switch omapdrm over to drm_mode_create_rotation_property() drm: Add drm_rotation_simplify() drm/i915: Add 180 degree sprite rotation support drm/i915: Make intel_plane_restore() return an error drm/i915: Add rotation property for sprites drm: Add support_bits parameter to drm_property_create_bitmask() drm: Add drm_rect rotation functions drm/i915: Add 180 degree primary plane rotation support drm: Set property to return invalid for unsupported arguments for bitmask property drivers/gpu/drm/drm_crtc.c | 72 +- drivers/gpu/drm/drm_rect.c | 140 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_display.c | 54 +- drivers/gpu/drm/i915/intel_drv.h | 5 +- drivers/gpu/drm/i915/intel_sprite.c | 90 -- drivers/gpu/drm/omapdrm/omap_drv.h | 7 -- drivers/gpu/drm/omapdrm/omap_plane.c | 17 ++--- include/drm/drm_crtc.h | 16 +++- include/drm/drm_rect.h | 6 ++ 11 files changed, 382 insertions(+), 30 deletions(-) -- 1.8.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] android: Change tests & tools directory to use the lib directory
From: Rafael Barbalho Instead of recompiling the lib directory for every tool or tests we can just re-use the static library. This also has the nice side effect of fixing the android "mm" command to allow android users to only rebuild the local changes in either the test or tools directory. Signed-off-by: Rafael Barbalho --- Android.mk | 5 + lib/Android.mk | 2 +- tests/Android.mk | 51 +-- tools/Android.mk | 19 +-- 4 files changed, 12 insertions(+), 65 deletions(-) diff --git a/Android.mk b/Android.mk index 7b42d10..8aeb2d4 100644 --- a/Android.mk +++ b/Android.mk @@ -1,5 +1,2 @@ -LOCAL_PATH := $(call my-dir) - -include $(LOCAL_PATH)/tests/Android.mk -include $(LOCAL_PATH)/tools/Android.mk +include $(call all-named-subdir-makefiles, lib tests tools) diff --git a/lib/Android.mk b/lib/Android.mk index 724d884..6735255 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -48,7 +48,7 @@ LOCAL_GENERATED_SOURCES := \ LOCAL_C_INCLUDES += \ $(LOCAL_PATH)/.. -LOCAL_EXPORT_C_INCLUDE_DIRS += $(LOCAL_PATH) +LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_PATH) LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM diff --git a/tests/Android.mk b/tests/Android.mk index 0e292a9..30be4a6 100644 --- a/tests/Android.mk +++ b/tests/Android.mk @@ -1,56 +1,13 @@ -include $(LOCAL_PATH)/tests/Makefile.sources -include $(LOCAL_PATH)/lib/Makefile.sources +LOCAL_PATH := $(call my-dir) -skip_lib_list := \ -igt_kms.c \ -igt_kms.h - -lib_list := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) -LIB_SOURCES := $(addprefix lib/,$(lib_list)) -GPU_TOOLS_PATH := $(LOCAL_PATH) - -.PHONY: version.h.tmp - -$(LOCAL_PATH)/version.h.tmp: - @touch $@ - @if test -d .git; then \ - if which git > /dev/null; then git log -n 1 --oneline | \ - sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' \ - >> $@ ; \ - fi \ - else \ - echo '#define IGT_GIT_SHA1 "NOT-GIT"' >> $@ ; \ - fi - -$(LOCAL_PATH)/version.h: $(LOCAL_PATH)/version.h.tmp - @echo "updating version.h" - @if ! cmp -s $(GPU_TOOLS_PATH)/version.h.tmp $(GPU_TOOLS_PATH)/version.h; then \ - mv $(GPU_TOOLS_PATH)/version.h.tmp $(GPU_TOOLS_PATH)/version.h ; \ - else \ - rm $(GPU_TOOLS_PATH)/version.h.tmp ; \ - fi - -# FIXME: autogenerate this info # -$(LOCAL_PATH)/config.h: - @echo "updating config.h" - echo '#define PACKAGE_VERSION "1.5"' >> $@ ; \ - echo '#define TARGET_CPU_PLATFORM "android-ia"' >> $@ ; +include $(LOCAL_PATH)/Makefile.sources ## define add_test include $(CLEAR_VARS) -LOCAL_SRC_FILES := \ - tests/$1.c \ - $(LIB_SOURCES) - -LOCAL_GENERATED_SOURCES := \ - $(LOCAL_PATH)/version.h \ - $(LOCAL_PATH)/config.h - -LOCAL_C_INCLUDES += \ - $(LOCAL_PATH)/lib +LOCAL_SRC_FILES := $1.c LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM LOCAL_CFLAGS += -DANDROID -UNDEBUG -include "check-ndebug.h" @@ -63,6 +20,8 @@ define add_test LOCAL_MODULE := $1 LOCAL_MODULE_TAGS := optional +LOCAL_STATIC_LIBRARIES := libintel_gpu_tools + LOCAL_SHARED_LIBRARIES := libpciaccess \ libdrm\ libdrm_intel diff --git a/tools/Android.mk b/tools/Android.mk index 7227c89..a957ec1 100644 --- a/tools/Android.mk +++ b/tools/Android.mk @@ -1,24 +1,13 @@ -include $(LOCAL_PATH)/tools/Makefile.sources -include $(LOCAL_PATH)/lib/Makefile.sources +LOCAL_PATH := $(call my-dir) -skip_lib_list := \ -igt_kms.c \ -igt_kms.h - -lib_list := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) -LIB_SOURCES := $(addprefix lib/,$(lib_list)) +include $(LOCAL_PATH)/Makefile.sources ## define add_tool include $(CLEAR_VARS) -LOCAL_SRC_FILES := \ - tools/$1.c \ - $(LIB_SOURCES) - -LOCAL_C_INCLUDES += \ - $(LOCAL_PATH)/lib +LOCAL_SRC_FILES := $1.c LOCAL_CFLAGS += -DHAVE_TERMIOS_H LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM @@ -32,6 +21,8 @@ define add_tool LOCAL_MODULE := $1 LOCAL_MODULE_TAGS := optional +LOCAL_STATIC_LIBRARIES := libintel_gpu_tools + LOCAL_SHARED_LIBRARIES := libpciaccess \ libdrm\ libdrm_intel -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/11] drm: Add drm_mode_create_rotation_property()
From: Sagar Kamble
Add a function to create a standards compliant rotation property.
Signed-off-by: Ville Syrjala
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_crtc.c | 18 ++
include/drm/drm_crtc.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3b7d32d..87744d6 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4114,3 +4114,21 @@ void drm_mode_config_cleanup(struct drm_device *dev)
idr_destroy(&dev->mode_config.crtc_idr);
}
EXPORT_SYMBOL(drm_mode_config_cleanup);
+
+struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
+ unsigned int
supported_rotations)
+{
+ static const struct drm_prop_enum_list props[] = {
+ { DRM_ROTATE_0, "rotate-0" },
+ { DRM_ROTATE_90, "rotate-90" },
+ { DRM_ROTATE_180, "rotate-180" },
+ { DRM_ROTATE_270, "rotate-270" },
+ { DRM_REFLECT_X, "reflect-x" },
+ { DRM_REFLECT_Y, "reflect-y" },
+ };
+
+ return drm_property_create_bitmask(dev, 0, "rotation",
+ props, ARRAY_SIZE(props),
+ supported_rotations);
+}
+EXPORT_SYMBOL(drm_mode_create_rotation_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index d5c46c1..b7d0f3c 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1182,6 +1182,8 @@ extern int drm_format_plane_cpp(uint32_t format, int
plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
extern const char *drm_get_format_name(uint32_t format);
+extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
+ unsigned int
supported_rotations);
/* Helpers */
static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/11] drm/i915: Add rotation property for sprites
From: Sagar Kamble
Sprite planes support 180 degree rotation. The lower layers are now in
place, so hook in the standard rotation property to expose the feature
to the users.
Signed-off-by: Ville Syrjala
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 42 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa37dfd..ea2efc3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1548,6 +1548,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *rotation_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 11560a6..d84f2fb 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1044,6 +1044,30 @@ out_unlock:
return ret;
}
+static int intel_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_i915_private *dev_priv = plane->dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == dev_priv->rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val & 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane->rotation;
+ intel_plane->rotation = val;
+ ret = intel_plane_restore(plane);
+ if (ret)
+ intel_plane->rotation = old_val;
+ }
+
+ return ret;
+}
+
int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -1070,6 +1094,7 @@ static const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = intel_update_plane,
.disable_plane = intel_disable_plane,
.destroy = intel_destroy_plane,
+ .set_property = intel_plane_set_property,
};
static uint32_t ilk_plane_formats[] = {
@@ -1106,6 +1131,7 @@ static uint32_t vlv_plane_formats[] = {
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
const uint32_t *plane_formats;
@@ -1180,8 +1206,22 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
&intel_plane_funcs,
plane_formats, num_plane_formats,
false);
- if (ret)
+ if (ret) {
kfree(intel_plane);
+ goto out;
+ }
+
+ if (!dev_priv->rotation_property)
+ dev_priv->rotation_property =
+ drm_mode_create_rotation_property(dev,
+ BIT(DRM_ROTATE_0) |
+ BIT(DRM_ROTATE_180));
+
+ if (dev_priv->rotation_property)
+ drm_object_attach_property(&intel_plane->base.base,
+ dev_priv->rotation_property,
+ intel_plane->rotation);
+ out:
return ret;
}
--
1.8.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] pm_rps: Add stop rings injection utility
From: Jeff McGee
Signed-off-by: Jeff McGee
---
tests/pm_rps.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 709e341..a6807d2 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -32,10 +32,12 @@
#include
#include
#include
+#include
#include "drmtest.h"
#include "intel_gpu_tools.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
+#include "igt_debugfs.h"
static bool verbose = false;
@@ -62,6 +64,8 @@ struct junk {
{ "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, {
"RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL,
NULL }
};
+static igt_debugfs_t dfs;
+
static int readval(FILE *filp)
{
int val;
@@ -267,6 +271,37 @@ static void load_helper_deinit(void)
drm_intel_bufmgr_destroy(lh.bufmgr);
}
+static void stop_rings(void)
+{
+ int fd;
+ static const char data[] = "0xf";
+
+ fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_WRONLY);
+ igt_assert(fd >= 0);
+
+ log("injecting ring stop\n");
+ igt_assert(write(fd, data, sizeof(data)) == sizeof(data));
+
+ close(fd);
+}
+
+static bool rings_stopped(void)
+{
+ int fd;
+ static char buf[128];
+ unsigned long long val;
+
+ fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_RDONLY);
+ igt_assert(fd >= 0);
+
+ igt_assert(read(fd, buf, sizeof(buf)) > 0);
+ close(fd);
+
+ sscanf(buf, "%llx", &val);
+
+ return (bool)val;
+}
+
static void min_max_config(void (*check)(void))
{
int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
@@ -471,6 +506,8 @@ int main(int argc, char **argv)
igt_install_exit_handler(pm_rps_exit_handler);
load_helper_init();
+
+ igt_debugfs_init(&dfs);
}
igt_subtest("basic-api")
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/11] Enabling 180 degree rotation for sprite and crtc planes
On Sat, Feb 01, 2014 at 12:40:36AM +0530, sagar.a.kam...@intel.com wrote: > From: Sagar Kamble > > With these patches 180 degree rotation for crtc and sprite planes will be > exposed through drm rotation properties implemented by Ville few days back. > I have added CRTC rotation support on top of Ville's 9 patches that includes > sprite rotation. Omapdrm changes, rotation_simplify, drm_rect functions are > also included in this list. Functionality has been tested with i-g-t test > "intel_plane_rotate". > > > Sagar Kamble (11): Somehow you've managed to change the authorship information of most of the patches. Please don't do that. > drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h > drm: Add drm_mode_create_rotation_property() > drm/omap: Switch omapdrm over to drm_mode_create_rotation_property() > drm: Add drm_rotation_simplify() > drm/i915: Add 180 degree sprite rotation support > drm/i915: Make intel_plane_restore() return an error > drm/i915: Add rotation property for sprites > drm: Add support_bits parameter to drm_property_create_bitmask() > drm: Add drm_rect rotation functions > drm/i915: Add 180 degree primary plane rotation support > drm: Set property to return invalid for unsupported arguments for > bitmask property > > drivers/gpu/drm/drm_crtc.c | 72 +- > drivers/gpu/drm/drm_rect.c | 140 > +++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 4 + > drivers/gpu/drm/i915/intel_display.c | 54 +- > drivers/gpu/drm/i915/intel_drv.h | 5 +- > drivers/gpu/drm/i915/intel_sprite.c | 90 -- > drivers/gpu/drm/omapdrm/omap_drv.h | 7 -- > drivers/gpu/drm/omapdrm/omap_plane.c | 17 ++--- > include/drm/drm_crtc.h | 16 +++- > include/drm/drm_rect.h | 6 ++ > 11 files changed, 382 insertions(+), 30 deletions(-) > > -- > 1.8.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/11] drm/i915: Add 180 degree sprite rotation support
On Sat, Feb 01, 2014 at 12:40:41AM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> The sprite planes (in fact all display planes starting from gen4)
> support 180 degree rotation. Add the relevant low level bits to the
> sprite code to make use of that feature.
>
> The upper layers are not yet plugged in.
>
> Signed-off-by: Ville Syrjala
> Tested-by: Sagar Kamble
I actually posted a v2 of this patch, which fixes HSW. But I guess now
we really need a v3 which extends that fix for BDW. Assuming BDW is like
HSW here.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_drv.h| 1 +
> drivers/gpu/drm/i915/intel_sprite.c | 34 ++
> 3 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd18cd..57906c5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3637,6 +3637,7 @@
> #define DVS_YUV_ORDER_UYVY (1<<16)
> #define DVS_YUV_ORDER_YVYU (2<<16)
> #define DVS_YUV_ORDER_VYUY (3<<16)
> +#define DVS_ROTATE_180 (1<<15)
> #define DVS_DEST_KEY (1<<2)
> #define DVS_TRICKLE_FEED_DISABLE (1<<14)
> #define DVS_TILED (1<<10)
> @@ -3707,6 +3708,7 @@
> #define SPRITE_YUV_ORDER_UYVY (1<<16)
> #define SPRITE_YUV_ORDER_YVYU (2<<16)
> #define SPRITE_YUV_ORDER_VYUY (3<<16)
> +#define SPRITE_ROTATE_180 (1<<15)
> #define SPRITE_TRICKLE_FEED_DISABLE(1<<14)
> #define SPRITE_INT_GAMMA_ENABLE(1<<13)
> #define SPRITE_TILED (1<<10)
> @@ -3780,6 +3782,7 @@
> #define SP_YUV_ORDER_UYVY (1<<16)
> #define SP_YUV_ORDER_YVYU (2<<16)
> #define SP_YUV_ORDER_VYUY (3<<16)
> +#define SP_ROTATE_180 (1<<15)
> #define SP_TILED (1<<10)
> #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 44067bc..85864fc 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -397,6 +397,7 @@ struct intel_plane {
> unsigned int crtc_w, crtc_h;
> uint32_t src_x, src_y;
> uint32_t src_w, src_h;
> + unsigned int rotation;
>
> /* Since we need to change the watermarks before/after
>* enabling/disabling the planes, we need to store the parameters here
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 336ae6c..f9c8c41 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -60,6 +60,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
> *crtc,
> sprctl &= ~SP_PIXFORMAT_MASK;
> sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
> sprctl &= ~SP_TILED;
> + sprctl &= ~SP_ROTATE_180;
>
> switch (fb->pixel_format) {
> case DRM_FORMAT_YUYV:
> @@ -131,6 +132,14 @@ vlv_update_plane(struct drm_plane *dplane, struct
> drm_crtc *crtc,
> fb->pitches[0]);
> linear_offset -= sprsurf_offset;
>
> + if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
> + sprctl |= SP_ROTATE_180;
> +
> + x += src_w;
> + y += src_h;
> + linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
> + }
> +
> I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
>
> @@ -238,6 +247,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
> *crtc,
> sprctl &= ~SPRITE_RGB_ORDER_RGBX;
> sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
> sprctl &= ~SPRITE_TILED;
> + sprctl &= ~SPRITE_ROTATE_180;
>
> switch (fb->pixel_format) {
> case DRM_FORMAT_XBGR:
> @@ -299,6 +309,14 @@ ivb_update_plane(struct drm_plane *plane, struct
> drm_crtc *crtc,
> pixel_size, fb->pitches[0]);
> linear_offset -= sprsurf_offset;
>
> + if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
> + sprctl |= SPRITE_ROTATE_180;
> +
> + x += src_w;
> + y += src_h;
> + linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
> + }
> +
> I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
> I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
>
> @@ -422,6 +440,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
> *crtc,
> dvscntr &= ~DVS_RGB_ORDER_XBGR;
> dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
> dvscntr &= ~DVS_TILED;
> + dvscntr &= ~DVS_ROTATE_180;
>
> switch (fb->pixel_format) {
> case DRM_FORMAT_XBGR:
> @@ -478,6 +497,14 @@ ilk_update_plane(struct drm_plane *plane, struct
> drm_crtc
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Add 180 degree primary plane rotation support
On Sat, Feb 01, 2014 at 12:40:46AM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> Primary planes support 180 degree rotation. Expose the feature
> through rotation drm property.
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Sagar Kamble
> Tested-by: Sagar Kamble
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 54
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 57906c5..d3000c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3553,6 +3553,7 @@
> #define DISPPLANE_NO_LINE_DOUBLE 0
> #define DISPPLANE_STEREO_POLARITY_FIRST0
> #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
> +#define DISPPLANE_ROTATE_180 (1<<15)
> #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
> #define DISPPLANE_TILED(1<<10)
> #define _DSPAADDR(dev_priv->info->display_mmio_offset + 0x70184)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4d4a0d9..483de59 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> unsigned long linear_offset;
> u32 dspcntr;
> u32 reg;
> + int pixel_size;
>
> switch (plane) {
> case 0:
> @@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> return -EINVAL;
> }
>
> + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> intel_fb = to_intel_framebuffer(fb);
> obj = intel_fb->obj;
>
> @@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> dspcntr = I915_READ(reg);
> /* Mask out pixel format bits in case we change it */
> dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
> + dspcntr &= ~DISPPLANE_ROTATE_180;
> +
> switch (fb->pixel_format) {
> case DRM_FORMAT_C8:
> dspcntr |= DISPPLANE_8BPP;
> @@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> if (IS_G4X(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - I915_WRITE(reg, dspcntr);
> -
> linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> @@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> intel_crtc->dspaddr_offset = linear_offset;
> }
>
> + if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) {
> + dspcntr |= DISPPLANE_ROTATE_180;
> +
> + x += (fb->width - 1);
> + y += (fb->height - 1);
> + linear_offset += (fb->height - 1) * fb->pitches[0] +
> + fb->width * pixel_size;
> + }
This isn't quite right. We need something like:
x += pipe_src_w - 1;
y += pipe_src_h - 1;
That suggests your tests don't check if panning works correctly when
rotated.
I was also going to say we need to do this before stashing the result
into intel_crtc->dspaddr_offset on gen2/3, but it actually looks like
rotation is a gen4+ feature, so this place looks OK for this code.
You've also forgotten to add the rotation bits to
ironlake_update_plane(). That one will need additional HSW/BDW checks
I think.
> +
> + I915_WRITE(reg, dspcntr);
> +
> DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
> i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
> fb->pitches[0]);
> @@ -8748,6 +8761,31 @@ free_work:
> return ret;
> }
>
> +static int intel_crtc_set_property(struct drm_crtc *crtc,
> + struct drm_property *prop,
> + uint64_t val)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + uint64_t old_val;
> + int ret = -ENOENT;
> +
> + if (prop == dev_priv->rotation_property) {
> + /* exactly one rotation angle please */
> + if (hweight32(val & 0xf) != 1)
> + return -EINVAL;
> +
> + old_val = intel_crtc->rotation;
> + intel_crtc->rotation = val;
> + ret = dev_priv->display.update_plane(crtc, crtc->fb, 0, 0);
> + if (ret)
> + intel_crtc->rotation = old_val;
> + }
> +
> + return ret;
> +}
> +
> static struct drm_crtc_helper_funcs intel_helper_funcs = {
> .mode_set_base_atomic = intel_pipe_set_base
[Intel-gfx] [PATCH 1/5] drm/i915: Add RPS debugfs manual mode
From: Jeff McGee
RPS manual mode disables/ignores load-based inputs and allows render
performance state to be controlled externally. The enabling of manual
mode and setting of desired frequency is done through debugfs.
i915_rps_manual:
'0' - RPS controlled normally using load metrics.
'1' - RPS controlled manually via i915_cur_freq writes.
i915_cur_freq:
u64 - Value is the current gpu frequency request in MHz. Writes
accepted only if i915_rps_manual = 1.
Supports Gen6+ except Valleyview and Broadwell.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_debugfs.c | 111
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 42 --
4 files changed, 156 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc8707f..c6d4da0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3322,6 +3322,115 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
i915_min_freq_get, i915_min_freq_set,
"%llu\n");
+static int i915_cur_freq_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ *val = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
+
+ return 0;
+}
+
+static int i915_cur_freq_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u64 freq = val;
+ int ret;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
+ if (ret)
+ return ret;
+
+ /* Must be in manual mode to guarantee setting will persist. */
+ if (!dev_priv->rps.manual_mode) {
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return -EINVAL;
+ }
+
+ do_div(val, GT_FREQUENCY_MULTIPLIER);
+
+ if (val < dev_priv->rps.min_delay || val > dev_priv->rps.max_delay) {
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return -EINVAL;
+ }
+
+ DRM_DEBUG_DRIVER("Setting current freq to %llu\n", freq);
+
+ gen6_set_rps(dev, val);
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_cur_freq_fops,
+ i915_cur_freq_get, i915_cur_freq_set,
+ "%llu\n");
+
+static int i915_rps_manual_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ *val = dev_priv->rps.manual_mode;
+
+ return 0;
+}
+
+static int i915_rps_manual_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ DRM_DEBUG_DRIVER("Setting RPS mode to %s\n",
+val ? "manual" : "normal");
+
+ ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
+ if (ret)
+ return ret;
+
+ gen6_set_rps_mode(dev, val);
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_rps_manual_fops,
+ i915_rps_manual_get, i915_rps_manual_set,
+ "%llu\n");
+
static int
i915_cache_sharing_get(void *data, u64 *val)
{
@@ -3496,6 +3605,8 @@ static const struct i915_debugfs_files {
{"i915_wedged", &i915_wedged_fops},
{"i915_max_freq", &i915_max_freq_fops},
{"i915_min_freq", &i915_min_freq_fops},
+ {"i915_cur_freq", &i915_cur_freq_fops},
+ {"i915_rps_manual", &i915_rps_manual_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa37dfd..73fd646 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -968,6 +968,7 @@ struct intel_gen6_power_mgmt {
i
[Intel-gfx] [PATCH 5/5] drm/i915: Add CxSR debugfs disabling
From: Jeff McGee
i915_sr_disable:
'0' - CxSR enabled normally per device and settings.
'1' - CxSR explicitly disabled.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_debugfs.c | 43 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 47 +
3 files changed, 72 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 92f6213..cccb1bf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1523,6 +1523,8 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
else if (IS_PINEVIEW(dev))
sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+ else if (IS_VALLEYVIEW(dev))
+ sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
seq_printf(m, "self-refresh: %s\n",
sr_enabled ? "enabled" : "disabled");
@@ -1530,6 +1532,46 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_sr_disable_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ *val = dev_priv->sr_disable;
+
+ return 0;
+}
+
+static int i915_sr_disable_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+
+ if (dev_priv->sr_disable == (bool)val)
+ return 0;
+
+ drm_modeset_lock_all(dev);
+
+ DRM_DEBUG_DRIVER("Setting CxSR disable %s\n",
+val ? "true" : "false");
+
+ dev_priv->sr_disable = (bool)val;
+
+ /* Reset enabled crtc to force CxSR state update */
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ if (crtc->enabled)
+ intel_crtc_restore_mode(crtc);
+
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_sr_disable_fops,
+ i915_sr_disable_get, i915_sr_disable_set,
+ "%llu\n");
+
static int i915_emon_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3753,6 +3795,7 @@ static const struct i915_debugfs_files {
{"i915_rc6_disable", &i915_rc6_disable_fops},
{"i915_ips_disable", &i915_ips_disable_fops},
{"i915_fbc_disable", &i915_fbc_disable_fops},
+ {"i915_sr_disable", &i915_sr_disable_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18b2849..6d7dae2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1537,6 +1537,8 @@ typedef struct drm_i915_private {
bool ips_disable;
+ bool sr_disable;
+
struct i915_power_domains power_domains;
struct i915_psr psr;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a8605fc..93e1c60 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1041,7 +1041,7 @@ static void pineview_update_wm(struct drm_crtc
*unused_crtc)
}
crtc = single_enabled_crtc(dev);
- if (crtc) {
+ if (crtc && !dev_priv->sr_disable) {
const struct drm_display_mode *adjusted_mode;
int pixel_size = crtc->fb->bits_per_pixel / 8;
int clock;
@@ -1335,6 +1335,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
enabled |= 1 << PIPE_B;
if (single_plane_enabled(enabled) &&
+ !dev_priv->sr_disable &&
g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns,
&valleyview_wm_info,
@@ -1392,6 +1393,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
enabled |= 1 << PIPE_B;
if (single_plane_enabled(enabled) &&
+ !dev_priv->sr_disable &&
g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns,
&g4x_wm_info,
@@ -1433,7 +1435,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
/* Calc sr entries for one plane configs */
crtc = single_enabled_crtc(dev);
- if (crtc) {
+ if (crtc && !dev_priv->sr_disable) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
const struct drm_display_mode *adjusted_mode =
@@ -1603,7 +1605,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
I915_WRITE(FW_BLC2, fwate
[Intel-gfx] [PATCH 4/5] drm/i915: Add FBC debugfs disabling
From: Jeff McGee
i915_fbc_disable:
'0' - FBC enabled normally per device and settings.
'1' - FBC explicitly disabled.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_debugfs.c | 50 +
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 5
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 949c6a4..92f6213 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1386,6 +1386,9 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
case FBC_CHIP_DEFAULT:
seq_puts(m, "disabled per chip default");
break;
+ case FBC_DEBUG_FS:
+ seq_puts(m, "disabled per debugfs");
+ break;
default:
seq_puts(m, "unknown reason");
}
@@ -1394,6 +1397,52 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_fbc_disable_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if (!HAS_FBC(dev))
+ return -ENODEV;
+
+ *val = dev_priv->fbc.disable;
+
+ return 0;
+}
+
+static int i915_fbc_disable_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+
+ if (!HAS_FBC(dev))
+ return -ENODEV;
+
+ if (dev_priv->fbc.disable == (bool)val)
+ return 0;
+
+ drm_modeset_lock_all(dev);
+
+ DRM_DEBUG_DRIVER("Setting FBC disable %s\n",
+val ? "true" : "false");
+
+ dev_priv->fbc.disable = (bool)val;
+
+ /* Reset enabled crtc to force FBC state update */
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ if (crtc->enabled)
+ intel_crtc_restore_mode(crtc);
+
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_disable_fops,
+ i915_fbc_disable_get, i915_fbc_disable_set,
+ "%llu\n");
+
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3703,6 +3752,7 @@ static const struct i915_debugfs_files {
{"i915_rps_manual", &i915_rps_manual_fops},
{"i915_rc6_disable", &i915_rc6_disable_fops},
{"i915_ips_disable", &i915_ips_disable_fops},
+ {"i915_fbc_disable", &i915_fbc_disable_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93e1547..18b2849 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -763,7 +763,10 @@ struct i915_fbc {
FBC_MULTIPLE_PIPES, /* more than one pipe active */
FBC_MODULE_PARAM,
FBC_CHIP_DEFAULT, /* disabled by default on this chip */
+ FBC_DEBUG_FS, /* user requests disabling through debugfs */
} no_fbc_reason;
+
+ bool disable;
};
struct i915_psr {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6478116..a8605fc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -519,6 +519,11 @@ void intel_update_fbc(struct drm_device *dev)
DRM_DEBUG_KMS("fbc disabled per module param\n");
goto out_disable;
}
+ if (dev_priv->fbc.disable) {
+ if (set_no_fbc_reason(dev_priv, FBC_DEBUG_FS))
+ DRM_DEBUG_KMS("fbc disabled per debugfs\n");
+ goto out_disable;
+ }
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
(adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Add IPS debugfs disabling
From: Jeff McGee
i915_ips_disable:
'0' - IPS enabled normally per device and settings.
'1' - IPS explicitly disabled.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_debugfs.c | 47
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 4 +++
3 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a51c357..949c6a4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1413,6 +1413,52 @@ static int i915_ips_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_ips_disable_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if (!HAS_IPS(dev))
+ return -ENODEV;
+
+ *val = dev_priv->ips_disable;
+
+ return 0;
+}
+
+static int i915_ips_disable_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+
+ if (!HAS_IPS(dev))
+ return -ENODEV;
+
+ if (dev_priv->ips_disable == (bool)val)
+ return 0;
+
+ drm_modeset_lock_all(dev);
+
+ DRM_DEBUG_DRIVER("Setting IPS disable %s\n",
+val ? "true" : "false");
+
+ dev_priv->ips_disable = (bool)val;
+
+ /* Reset enabled crtc to force IPS state update */
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ if (crtc->enabled)
+ intel_crtc_restore_mode(crtc);
+
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_ips_disable_fops,
+ i915_ips_disable_get, i915_ips_disable_set,
+ "%llu\n");
+
static int i915_sr_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3656,6 +3702,7 @@ static const struct i915_debugfs_files {
{"i915_cur_freq", &i915_cur_freq_fops},
{"i915_rps_manual", &i915_rps_manual_fops},
{"i915_rc6_disable", &i915_rc6_disable_fops},
+ {"i915_ips_disable", &i915_ips_disable_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9893451..93e1547 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1532,6 +1532,8 @@ typedef struct drm_i915_private {
* mchdev_lock in intel_pm.c */
struct intel_ilk_power_mgmt ips;
+ bool ips_disable;
+
struct i915_power_domains power_domains;
struct i915_psr psr;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..5af41ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4580,7 +4580,11 @@ retry:
static void hsw_compute_ips_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
pipe_config->ips_enabled = i915.enable_ips &&
+ !dev_priv->ips_disable &&
hsw_crtc_supports_ips(crtc) &&
pipe_config->pipe_bpp <= 24;
}
--
1.8.5.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] Add power feature debugfs disabling
From: Jeff McGee This series has recently been accepted into the Haswell Android kernel and helps with debugging and profiling these power features. I would like it to be considered for upstream incorporation. The patches here have been rebased (minimal changes required) and compile-tested only. Broad device support is provided, accept for RPS and RC6 with Broadwell and Valleyview. Both of these were somewhat of a moving target and I didn't have devices to work with. Support can of course be added with help from appropriate folks. The hooks introduce some amount of overhead as an additional check is often needed to determine whether the feature is on or off - similar to the module parameters that already exist. I felt that the overhead was minimal enough and didn't want to ugly up the code with CONFIG_DEBUG_FS compile conditionals. But I'm open to the list's thoughts on this. IGT tests of these new interfaces can certainly be added. I wanted to make sure there was sufficient interest in having these interfaces before starting on the tests. So please provide feedback. Thanks, Jeff Jeff McGee (5): drm/i915: Add RPS debugfs manual mode drm/i915: Add RC6 debugfs disabling drm/i915: Add IPS debugfs disabling drm/i915: Add FBC debugfs disabling drm/i915: Add CxSR debugfs disabling drivers/gpu/drm/i915/i915_debugfs.c | 300 +++ drivers/gpu/drm/i915/i915_drv.h | 14 ++ drivers/gpu/drm/i915/i915_irq.c | 6 + drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_pm.c | 125 +++ 5 files changed, 420 insertions(+), 29 deletions(-) -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Add RC6 debugfs disabling
From: Jeff McGee
i915_rc6_disable:
'0' - RC6 states used normally per device and settings.
'1' - RC6 states explicitly disabled.
Supports Gen6+ except Valleyview and Broadwell.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +
drivers/gpu/drm/i915/i915_drv.h | 5
drivers/gpu/drm/i915/intel_pm.c | 31 ---
3 files changed, 81 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c6d4da0..a51c357 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3431,6 +3431,54 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_rps_manual_fops,
i915_rps_manual_get, i915_rps_manual_set,
"%llu\n");
+static int i915_rc6_disable_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ *val = dev_priv->rps.rc6_disable;
+
+ return 0;
+}
+
+static int i915_rc6_disable_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ DRM_DEBUG_DRIVER("Setting RC6 disable %s\n",
+val ? "true" : "false");
+
+ ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
+ if (ret)
+ return ret;
+
+ gen6_set_rc6_mode(dev, val);
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_rc6_disable_fops,
+ i915_rc6_disable_get, i915_rc6_disable_set,
+ "%llu\n");
+
static int
i915_cache_sharing_get(void *data, u64 *val)
{
@@ -3607,6 +3655,7 @@ static const struct i915_debugfs_files {
{"i915_min_freq", &i915_min_freq_fops},
{"i915_cur_freq", &i915_cur_freq_fops},
{"i915_rps_manual", &i915_rps_manual_fops},
+ {"i915_rc6_disable", &i915_rc6_disable_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 73fd646..9893451 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -970,6 +970,10 @@ struct intel_gen6_power_mgmt {
bool manual_mode;
bool enabled;
+
+ u32 rc6_mask;
+ bool rc6_disable;
+
struct delayed_work delayed_resume_work;
/*
@@ -2537,6 +2541,7 @@ extern bool intel_fbc_enabled(struct drm_device *dev);
extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
+extern void gen6_set_rc6_mode(struct drm_device *dev, bool disable);
extern void gen6_set_rps_mode(struct drm_device *dev, bool manual);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfdf5f0..6478116 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3071,6 +3071,30 @@ void gen6_set_rps_mode(struct drm_device *dev, bool
manual)
gen6_set_rps(dev, delay);
}
+void gen6_set_rc6_mode(struct drm_device *dev, bool disable)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+IS_VALLEYVIEW(dev) ||
+IS_BROADWELL(dev)) {
+ DRM_DEBUG_DRIVER("RC6 disable not supported\n");
+ return;
+ }
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ dev_priv->rps.rc6_disable = disable;
+
+ if (disable)
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+ else
+ I915_WRITE(GEN6_RC_CONTROL,
+ dev_priv->rps.rc6_mask |
+ GEN6_RC_CTL_EI_MODE(1) |
+ GEN6_RC_CTL_HW_ENABLE);
+}
+
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -3376,10 +3400,9 @@ static void gen6_enable_rps(struct drm_device *dev)
intel_print_rc6_info(dev, rc6_mask);
- I915_WRITE(GEN6_RC_CONTROL,
- rc6_mask |
- GEN6_RC_CTL_EI_MODE(1) |
- GEN6_RC_CTL_HW_ENABLE);
+ dev_priv->rps.rc6_ma
