[Intel-gfx] [PATCH 3/4] drm/i915: MIPI PPS delays added
Added as generic parameters which will be initialized in the panel
driver and are specific to panels.
Backlight delays have also kept as placeholders and will be used used
once we have MIPI backlight enabling support
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 7 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 09b9318..0d4dd54 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -185,6 +185,8 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
/* put device in ready state */
intel_dsi_device_ready(encoder);
+ msleep(intel_dsi->panel_on_delay);
+
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
@@ -301,6 +303,9 @@ static void intel_dsi_post_disable(struct intel_encoder
*encoder)
if (intel_dsi->dev.dev_ops->disable_panel_power)
intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
+
+ msleep(intel_dsi->panel_off_delay);
+ msleep(intel_dsi->panel_pwr_cycle_delay);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index be132c5..e3f4e91 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -116,6 +116,13 @@ struct intel_dsi {
u16 clk_hs_to_lp_count;
u16 init_count;
+
+ /* all delays in ms */
+ u16 backlight_off_delay;
+ u16 backlight_on_delay;
+ u16 panel_on_delay;
+ u16 panel_off_delay;
+ u16 panel_pwr_cycle_delay;
};
static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
--
1.8.3.2
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[Intel-gfx] [PATCH 0/4] Generic MIPI Panel driver
Hi, This series enabled generic MIPI panel driver support, the ground for which has been built up from the patches - http://lists.freedesktop.org/archives/intel-gfx/2014-February/040764.html http://lists.freedesktop.org/archives/intel-gfx/2014-April/043646.html With a version of these patches Asus T100A was found to be working by Arjan who has a device. I do not have the device to test directly. Will be getting one and verifying on that. But ideally should work. I have verified these patches on couple of internal panels. Also some minor changes in intel_dsi.c to support the generic panel driver are done. Regards Shobhit Shobhit Kumar (4): drm/i915: Correct MIPI operation mode as per expected values from VBT drm/i915: MIPI init count programming as generic parameter drm/i915: MIPI PPS delays added drm/i915: Add support for Generic MIPI panel driver drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/dsi_mod_vbt_generic.c | 598 + drivers/gpu/drm/i915/intel_drv.h | 4 +- drivers/gpu/drm/i915/intel_dsi.c | 17 +- drivers/gpu/drm/i915/intel_dsi.h | 15 +- 5 files changed, 630 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/dsi_mod_vbt_generic.c -- 1.8.3.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Add support for Generic MIPI panel driver
This driver makes use of the generic panel information from the VBT.
Panel information is classified into two - panel configuration and panel
power sequence which is unique to each panel. The generic driver uses the
panel configuration and sequence parsed from VBT block #52 and #53
v2: Address review comments by Jani
- Move all of the things in driver c file from header
- Make all functions static
- Make use of video/mipi_display.c instead of redefining
- Null checks during sequence execution
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/dsi_mod_vbt_generic.c | 598 +
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 2 +
4 files changed, 606 insertions(+)
create mode 100644 drivers/gpu/drm/i915/dsi_mod_vbt_generic.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b1445b7..756a7a4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -55,6 +55,7 @@ i915-y += dvo_ch7017.o \
intel_dsi_cmd.o \
intel_dsi.o \
intel_dsi_pll.o \
+ dsi_mod_vbt_generic.o \
intel_dvo.o \
intel_hdmi.o \
intel_i2c.o \
diff --git a/drivers/gpu/drm/i915/dsi_mod_vbt_generic.c
b/drivers/gpu/drm/i915/dsi_mod_vbt_generic.c
new file mode 100644
index 000..0c12ce8
--- /dev/null
+++ b/drivers/gpu/drm/i915/dsi_mod_vbt_generic.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Shobhit Kumar
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+#define MIPI_TRANSFER_MODE_SHIFT 0
+#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
+#define MIPI_PORT_SHIFT3
+
+#define PREPARE_CNT_MAX0x3F
+#define EXIT_ZERO_CNT_MAX 0x3F
+#define CLK_ZERO_CNT_MAX 0xFF
+#define TRAIL_CNT_MAX 0x1F
+
+#define NS_MHZ_RATIO 100
+
+/* This macro divides two integers and rounds fractional values up
+ * to the nearest integer value. */
+#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
+
+#define GPI0_NC_0_HV_DDI0_HPD 0x4130
+#define GPIO_NC_0_HV_DDI0_PAD 0x4138
+#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
+#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
+#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
+#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
+#define GPIO_NC_3_PANEL0_VDDEN 0x4140
+#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
+#define GPIO_NC_4_PANEL0_BLKEN 0x4150
+#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
+#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
+#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
+#define GPIO_NC_6_PCONF00x4180
+#define GPIO_NC_6_PAD 0x4188
+#define GPIO_NC_7_PCONF00x4190
+#define GPIO_NC_7_PAD 0x4198
+#define GPIO_NC_8_PCONF00x4170
+#define GPIO_NC_8_PAD 0x4178
+#define GPIO_NC_9_PCONF00x4100
+#define GPIO_NC_9_PAD 0x4108
+#define GPIO_NC_10_PCONF0 0x40E0
+#define GPIO_NC_10_PAD 0x40E8
+#define GPIO_NC_11_PCONF0 0x40F0
+#define GPIO_NC_11_PAD 0x40F8
+
+struct gpio_table {
+ u16 function_reg;
+ u16 pad_reg;
+ u8 init;
+};
+
+static struct gpio_table gtable[] = {
+ { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
+ { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
+ { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
+ { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
+ { GPIO_NC_4_PAN
[Intel-gfx] [PATCH 2/4] drm/i915: MIPI init count programming as generic parameter
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2795782..09b9318 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -525,6 +525,9 @@ static void intel_dsi_mode_set(struct intel_encoder
*intel_encoder)
/* recovery disables */
I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
+ /* in terms of low power clock */
+ I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
+
/* in terms of txbyteclkhs. actual high to low switch +
* MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
*
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 1649422..be132c5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -114,6 +114,8 @@ struct intel_dsi {
u16 hs_to_lp_count;
u16 clk_lp_to_hs_count;
u16 clk_hs_to_lp_count;
+
+ u16 init_count;
};
static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
--
1.8.3.2
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[Intel-gfx] [PATCH 1/4] drm/i915: Correct MIPI operation mode as per expected values from VBT
In VBT fields operation mode is 0 for Video mode and 1 for command mode.
This field will be directly used as is in generic panel driver. So
adjust accordingly.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_dsi.c | 4 ++--
drivers/gpu/drm/i915/intel_dsi.h | 4 +++-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c551472..fca11f3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -106,8 +106,8 @@
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4
-#define INTEL_DSI_COMMAND_MODE 0
-#define INTEL_DSI_VIDEO_MODE 1
+#define INTEL_DSI_VIDEO_MODE 0
+#define INTEL_DSI_COMMAND_MODE 1
struct intel_framebuffer {
struct drm_framebuffer base;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e271c7..2795782 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -59,12 +59,12 @@ static struct intel_dsi *intel_attached_dsi(struct
drm_connector *connector)
static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
{
- return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
+ return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
}
static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
{
- return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
+ return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
}
static void intel_dsi_hot_plug(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 550714c..1649422 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -31,7 +31,6 @@
struct intel_dsi_device {
unsigned int panel_id;
const char *name;
- int type;
const struct intel_dsi_dev_ops *dev_ops;
void *dev_priv;
};
@@ -85,6 +84,9 @@ struct intel_dsi {
/* virtual channel */
int channel;
+ /* Video mode or command mode */
+ u16 operation_mode;
+
/* number of DSI lanes */
unsigned int lane_count;
--
1.8.3.2
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[Intel-gfx] [PATCH v3] drm/i915: Add parsing support for new MIPI blocks in VBT
The parser extracts the config block(#52) and sequence(#53) data
and store in private data structures.
v2: Address review comments by Jani
- adjust code for the structure changes for bdb_mipi_config
- add boundry and buffer overflow checks as suggested
- use kmemdup instead of kmalloc and memcpy
v3: More strict check while parsing VBT
- Ensure that at anytime we do not go beyond sequence block
while parsing
- On unknown element fail the whole parsing
v4: Style changes and spell check mostly as suggested by Jani
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 204 +-
drivers/gpu/drm/i915/intel_bios.h | 31 ++
3 files changed, 236 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85e362f..1b763aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1170,6 +1170,12 @@ struct intel_vbt_data {
/* MIPI DSI */
struct {
u16 panel_id;
+ struct mipi_config *config;
+ struct mipi_pps_data *pps;
+ u8 seq_version;
+ u32 size;
+ u8 *data;
+ u8 *sequence[MIPI_SEQ_MAX];
} dsi;
int crt_ddc_pin;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 862ca04..917f5bb 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -636,19 +636,213 @@ parse_edp(struct drm_i915_private *dev_priv, struct
bdb_header *bdb)
}
}
+static u8 *goto_next_sequence(u8 *data, int *size)
+{
+ u16 len;
+ int tmp = *size;
+
+ if (--tmp < 0)
+ return NULL;
+
+ /* goto first element */
+ data++;
+ while (1) {
+ switch (*data) {
+ case MIPI_SEQ_ELEM_SEND_PKT:
+ /*
+* skip by this element payload size
+* skip elem id, command flag and data type
+*/
+ if ((tmp = tmp - 5) < 0)
+ return NULL;
+
+ data += 3;
+ len = *((u16 *)data);
+
+ if ((tmp = tmp - len) < 0)
+ return NULL;
+
+ /* skip by len */
+ data = data + 2 + len;
+ break;
+ case MIPI_SEQ_ELEM_DELAY:
+ /* skip by elem id, and delay is 4 bytes */
+ if ((tmp = tmp - 5) < 0)
+ return NULL;
+
+ data += 5;
+ break;
+ case MIPI_SEQ_ELEM_GPIO:
+ if ((tmp = tmp - 3) < 0)
+ return NULL;
+
+ data += 3;
+ break;
+ default:
+ DRM_ERROR("Unknown element\n");
+ return NULL;
+ }
+
+ /* end of sequence ? */
+ if (*data == 0)
+ break;
+ }
+
+ /* goto next sequence or end of block byte */
+ if (--tmp < 0)
+ return NULL;
+
+ data++;
+
+ /* update amount of data left for the sequence block to be parsed */
+ *size = tmp;
+ return data;
+}
+
static void
parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
{
- struct bdb_mipi *mipi;
+ struct bdb_mipi_config *start;
+ struct bdb_mipi_sequence *sequence;
+ struct mipi_config *config;
+ struct mipi_pps_data *pps;
+ u8 *data, *seq_data;
+ int i, panel_id, seq_size;
+ u16 block_size;
+
+ /* Initialize this to undefined indicating no generic MIPI support */
+ dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
+
+ /* Block #40 is already parsed and panel_fixed_mode is
+* stored in dev_priv->lfp_lvds_vbt_mode
+* resuse this when needed
+*/
- mipi = find_section(bdb, BDB_MIPI_CONFIG);
- if (!mipi) {
- DRM_DEBUG_KMS("No MIPI BDB found");
+ /* Parse #52 for panel index used from panel_type already
+* parsed
+*/
+ start = find_section(bdb, BDB_MIPI_CONFIG);
+ if (!start) {
+ DRM_DEBUG_KMS("No MIPI config BDB found");
return;
}
- /* XXX: add more info */
+ DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
+ panel_type);
+
+ /*
+* get hold of the correct configuration block and pps data as per
+* the panel_type as index
+*/
+ config = &start->config[panel_type];
+ pps = &start->pps[p
[Intel-gfx] [PATCH V2 6/6] drm/i915:Use the coarse ping-pong mechanism based on drm fd to dispatch the BSD command on BDW GT3
V1->V2: Follow Daniel's comment and use the simple ping-pong mechanism.
This is only to add the support of dual BSD rings on BDW GT3 machine.
The further optimization will be considered in another patch set.
The BDW GT3 has two independent BSD rings, which can be used to process the
video commands. To be simpler, it is transparent to user-space driver/middle.
Instead the kernel driver will decide which ring is to dispatch the BSD video
command.
As every BSD ring is powerful, it is enough to dispatch the BSD video command
based on the drm fd. In such case it can play back video stream while encoding
another video stream. The coarse ping-pong mechanism is used to determine
which BSD ring is used to dispatch the BSD video command.
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_dma.c|3 +++
drivers/gpu/drm/i915/i915_drv.h|3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 37 +++-
3 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0b38f88..4d27cf4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1572,6 +1572,7 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
spin_lock_init(&dev_priv->backlight_lock);
spin_lock_init(&dev_priv->uncore.lock);
spin_lock_init(&dev_priv->mm.object_stat_lock);
+ atomic_set(&dev_priv->bsd_cmd_counter, 0);
mutex_init(&dev_priv->dpio_lock);
mutex_init(&dev_priv->modeset_restore_lock);
@@ -1929,6 +1930,8 @@ void i915_driver_postclose(struct drm_device *dev, struct
drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
+ if (file_priv && file_priv->bsd_ring)
+ file_priv->bsd_ring = NULL;
kfree(file_priv);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac5598c3..68e8166 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1466,6 +1466,8 @@ struct drm_i915_private {
struct i915_dri1_state dri1;
/* Old ums support infrastructure, same warning applies. */
struct i915_ums_state ums;
+ /* the lock for dispatch video commands on two BSD rings */
+ atomic_t bsd_cmd_counter;
};
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
@@ -1673,6 +1675,7 @@ struct drm_i915_file_private {
struct i915_hw_context *private_default_ctx;
atomic_t rps_wait_boost;
+ struct intel_ring_buffer *bsd_ring;
};
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 341ec68..720ef17 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -999,6 +999,34 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
return 0;
}
+/**
+ * Find one BSD ring to dispatch the corresponding BSD command.
+ * The Ring ID is returned.
+ */
+static int gen8_dispatch_bsd_ring(struct drm_device *dev,
+ struct drm_file *file)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+
+ /* Check whether the file_priv is using one ring */
+ if (file_priv->bsd_ring)
+ return file_priv->bsd_ring->id;
+ else {
+ /* If no, use the ping-pong mechanism to select one ring */
+ int counter, ring_id;
+ smp_mb__before_atomic_inc();
+ counter = atomic_inc_return(&dev_priv->bsd_cmd_counter);
+ if (counter % 2 == 0)
+ ring_id = VCS;
+ else
+ ring_id = VCS2;
+
+ file_priv->bsd_ring = &dev_priv->ring[ring_id];
+ return ring_id;
+ }
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file,
@@ -1043,7 +1071,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void
*data,
if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
ring = &dev_priv->ring[RCS];
- else
+ else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
+ if (HAS_BSD2(dev)) {
+ int ring_id;
+ ring_id = gen8_dispatch_bsd_ring(dev, file);
+ ring = &dev_priv->ring[ring_id];
+ } else
+ ring = &dev_priv->ring[VCS];
+ } else
ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
if (!intel_ring_initialized(ring)) {
--
1.7.10.1
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[Intel-gfx] [PATCH V2 0/6] drm/i915: Add the support of dual BSD rings on BDW GT3
V1->V2: Follow Daniel's comment to do the following update: a. consider the stolen check for BDW in kernel/early-quirks.c in patch 01 b. update the comment in Patch 04 c. use the simple ping-pong mechanism to add the support of dual BSD rings. The further optimization will be considered in another patch set. This is the patch set that tries to add the support of dual BSD rings on BDW GT3. Based on hardware spec, the BDW GT3 has two independent BSD rings, which can be used to process the video commands. To be simpler, it is transparent to user-space driver/middleware. In such case the kernel driver will decide which ring is to dispatch the BSD video command. As every BSD ring is powerful, it is enough to dispatch the BSD video command based on the drm fd. In such case the different BSD ring is used for video playing back and encoding. Zhao Yakui (6): drm/i915: Split the BDW device definition to prepare for dual BSD rings on BDW GT3 drm/i915:Initialize the second BSD ring on BDW GT3 machine drm/i915:Handle the irq interrupt for the second BSD ring drm/i915:Add the VCS2 switch in Intel_ring_setup_status_page for Gen7 to remove the switch check warning drm/i915:Update the restrict check to filter out wrong Ring ID passed by user-space drm/i915:Use the coarse ping-pong mechanism based on drm fd to dispatch the BSD command on BDW GT3 drivers/gpu/drm/i915/i915_dma.c|3 ++ drivers/gpu/drm/i915/i915_drv.c| 26 +++- drivers/gpu/drm/i915/i915_drv.h|5 +++ drivers/gpu/drm/i915/i915_gem.c|9 - drivers/gpu/drm/i915/i915_gem_execbuffer.c | 39 +- drivers/gpu/drm/i915/i915_gpu_error.c |1 + drivers/gpu/drm/i915/i915_irq.c|5 ++- drivers/gpu/drm/i915/i915_reg.h|1 + drivers/gpu/drm/i915/intel_ringbuffer.c| 59 drivers/gpu/drm/i915/intel_ringbuffer.h|5 ++- include/drm/i915_pciids.h | 22 --- 11 files changed, 163 insertions(+), 12 deletions(-) -- 1.7.10.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V2 5/6] drm/i915: Update the restrict check to filter out wrong Ring ID passed by user-space
One extra ring is added in the kernel driver but it is transparent to the
user-space application/middleware. In such case the number of the rings
in kernel driver is bigger than that exported to the user-space. So
it needs to filter out the wrong Ring ID passed by user-space.
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h|1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 3491402..341ec68 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1035,7 +1035,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (args->flags & I915_EXEC_IS_PINNED)
flags |= I915_DISPATCH_PINNED;
- if ((args->flags & I915_EXEC_RING_MASK) > I915_NUM_RINGS) {
+ if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
DRM_DEBUG("execbuf with unknown ring: %d\n",
(int)(args->flags & I915_EXEC_RING_MASK));
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8ca4285..59f4cdd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -64,6 +64,7 @@ struct intel_ring_buffer {
VCS2,
} id;
#define I915_NUM_RINGS 5
+#define LAST_USER_RING (VECS + 1)
u32 mmio_base;
void__iomem *virtual_start;
struct drm_device *dev;
--
1.7.10.1
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[Intel-gfx] [PATCH V2 3/6] drm/i915:Handle the irq interrupt for the second BSD ring
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_irq.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a4d3ae..63bd5de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1347,13 +1347,16 @@ static irqreturn_t gen8_gt_irq_handler(struct
drm_device *dev,
DRM_ERROR("The master control interrupt lied (GT0)!\n");
}
- if (master_ctl & GEN8_GT_VCS1_IRQ) {
+ if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
tmp = I915_READ(GEN8_GT_IIR(1));
if (tmp) {
ret = IRQ_HANDLED;
vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
if (vcs & GT_RENDER_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[VCS]);
+ vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
+ if (vcs & GT_RENDER_USER_INTERRUPT)
+ notify_ring(dev, &dev_priv->ring[VCS2]);
I915_WRITE(GEN8_GT_IIR(1), tmp);
} else
DRM_ERROR("The master control interrupt lied (GT1)!\n");
--
1.7.10.1
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[Intel-gfx] [PATCH V2 2/6] drm/i915:Initialize the second BSD ring on BDW GT3 machine
Based on the hardware spec, the BDW GT3 machine has two independent
BSD ring that can be used to dispatch the video commands.
So just initialize it.
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_drv.c |4 +--
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c |9 +-
drivers/gpu/drm/i915/i915_gpu_error.c |1 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 54 +++
drivers/gpu/drm/i915/intel_ringbuffer.h |4 ++-
7 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 17fbbe5..2a7842b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -282,7 +282,7 @@ static const struct intel_device_info
intel_broadwell_m_info = {
static const struct intel_device_info intel_broadwell_gt3d_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
.has_fbc = 1,
@@ -292,7 +292,7 @@ static const struct intel_device_info
intel_broadwell_gt3d_info = {
static const struct intel_device_info intel_broadwell_gt3m_info = {
.gen = 8, .is_mobile = 1, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
.has_fbc = 1,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 761fc53..ac5598c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1827,7 +1827,9 @@ struct drm_i915_cmd_table {
#define BSD_RING (1ring_mask & BSD2_RING)
#define HAS_BLT(dev)(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)(INTEL_INFO(dev)->has_llc)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 85c9cf0..b4dcf2a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4374,13 +4374,20 @@ static int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_blt_ring;
}
+ if (HAS_BSD2(dev)) {
+ ret = intel_init_bsd2_ring_buffer(dev);
+ if (ret)
+ goto cleanup_vebox_ring;
+ }
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
- goto cleanup_vebox_ring;
+ goto cleanup_ring;
return 0;
+cleanup_ring:
+ intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
cleanup_vebox_ring:
intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
cleanup_blt_ring:
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4865ade..3cab7f9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -42,6 +42,7 @@ static const char *ring_str(int ring)
case VCS: return "bsd";
case BCS: return "blt";
case VECS: return "vebox";
+ case VCS2: return "second bsd";
default: return "";
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f84555..0b88508 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -760,6 +760,7 @@ enum punit_power_well {
#define RENDER_RING_BASE 0x02000
#define BSD_RING_BASE 0x04000
#define GEN6_BSD_RING_BASE 0x12000
+#define GEN8_BSD2_RING_BASE0x1c000
#define VEBOX_RING_BASE0x1a000
#define BLT_RING_BASE 0x22000
#define RING_TAIL(base)((base)+0x30)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eb3dd26..8b9b89080 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1924,10 +1924,12 @@ int intel_init_render_ring_buffer(struct drm_device
*dev)
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
+ ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
ring->signal_mbox[RCS] = GEN6_NOSYNC;
ring->signal_mbox[VCS] = GEN6_VRSYNC;
ring->signal_mbox[BCS] = GEN6_BRSYNC;
ring->signal_mbox[VECS] = GEN6_VERSYNC;
+ ring->signal_mbox[VCS2] = GEN6_NOSYNC;
} else i
[Intel-gfx] [PATCH V2 4/6] drm/i915: Add the VCS2 switch in Intel_ring_setup_status_page for Gen7 to remove the switch check warning
V1->V2: Follow Daniel's comment to update the comment The Gen7 doesn't have the second BSD ring. But it will complain the switch check warning message during compilation. So just add it to remove the switch check warning. Signed-off-by: Zhao Yakui --- drivers/gpu/drm/i915/intel_ringbuffer.c |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8b9b89080..2c89525 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -988,6 +988,11 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) case BCS: mmio = BLT_HWS_PGA_GEN7; break; + /* +* VCS2 actually doesn't exist on Gen7. Only shut up +* gcc switch check warning +*/ + case VCS2: case VCS: mmio = BSD_HWS_PGA_GEN7; break; -- 1.7.10.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V2 1/6] drm/i915: Split the BDW device definition to prepare for dual BSD rings on BDW GT3
V1->V2: Follow Daniel's comment to consider the stolen check for BDW in
kernel/early-quirks.c
Based on the hardware spec, the BDW GT3 has the different configuration
with the BDW GT1/GT2. So split the BDW device info definition.
This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine.
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_drv.c | 26 --
include/drm/i915_pciids.h | 22 +-
2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5d8250f..17fbbe5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -279,6 +279,26 @@ static const struct intel_device_info
intel_broadwell_m_info = {
GEN_DEFAULT_PIPEOFFSETS,
};
+static const struct intel_device_info intel_broadwell_gt3d_info = {
+ .gen = 8, .num_pipes = 3,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .has_llc = 1,
+ .has_ddi = 1,
+ .has_fbc = 1,
+ GEN_DEFAULT_PIPEOFFSETS,
+};
+
+static const struct intel_device_info intel_broadwell_gt3m_info = {
+ .gen = 8, .is_mobile = 1, .num_pipes = 3,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .has_llc = 1,
+ .has_ddi = 1,
+ .has_fbc = 1,
+ GEN_DEFAULT_PIPEOFFSETS,
+};
+
/*
* Make sure any device matches here are from most specific to most
* general. For example, since the Quanta match is based on the subsystem
@@ -311,8 +331,10 @@ static const struct intel_device_info
intel_broadwell_m_info = {
INTEL_HSW_M_IDS(&intel_haswell_m_info), \
INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
- INTEL_BDW_M_IDS(&intel_broadwell_m_info), \
- INTEL_BDW_D_IDS(&intel_broadwell_d_info)
+ INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
+ INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
+ INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
+ INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info)
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4..24f3cad 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -223,14 +223,26 @@
_INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
_INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
-#define INTEL_BDW_M_IDS(info) \
+#define INTEL_BDW_GT12M_IDS(info) \
_INTEL_BDW_M_IDS(1, info), \
- _INTEL_BDW_M_IDS(2, info), \
- _INTEL_BDW_M_IDS(3, info)
+ _INTEL_BDW_M_IDS(2, info)
-#define INTEL_BDW_D_IDS(info) \
+#define INTEL_BDW_GT12D_IDS(info) \
_INTEL_BDW_D_IDS(1, info), \
- _INTEL_BDW_D_IDS(2, info), \
+ _INTEL_BDW_D_IDS(2, info)
+
+#define INTEL_BDW_GT3M_IDS(info) \
+ _INTEL_BDW_M_IDS(3, info)
+
+#define INTEL_BDW_GT3D_IDS(info) \
_INTEL_BDW_D_IDS(3, info)
+#define INTEL_BDW_M_IDS(info) \
+ INTEL_BDW_GT12M_IDS(info), \
+ INTEL_BDW_GT3M_IDS(info)
+
+#define INTEL_BDW_D_IDS(info) \
+ INTEL_BDW_GT12D_IDS(info), \
+ INTEL_BDW_GT3D_IDS(info)
+
#endif /* _I915_PCIIDS_H */
--
1.7.10.1
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[Intel-gfx] [PATCH I-g-t 2/2] tests: Add dummy_reloc test case based on multi drm_fd to test CPU<->GPU sync under multi BSD rings
The Broadwell GT3 machine has two independent BSD rings in kernel driver while
it is transparent to the user-space driver. In such case it needs to check
the CPU<->GPU sync for the second BSD ring. Multi drm_fd can assure that the
second BSD ring has the opportunity to dispatch the GPU command.
Signed-off-by: Zhao Yakui
---
tests/Makefile.sources|1 +
tests/gem_dummy_reloc_multi_bsd.c | 258 +
2 files changed, 259 insertions(+)
create mode 100644 tests/gem_dummy_reloc_multi_bsd.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 254a5c5..98f277f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs = \
gem_ring_sync_copy \
gem_ring_sync_loop \
gem_multi_bsd_sync_loop \
+ gem_dummy_reloc_multi_bsd \
gem_seqno_wrap \
gem_set_tiling_vs_gtt \
gem_set_tiling_vs_pwrite \
diff --git a/tests/gem_dummy_reloc_multi_bsd.c
b/tests/gem_dummy_reloc_multi_bsd.c
new file mode 100644
index 000..ef8213e
--- /dev/null
+++ b/tests/gem_dummy_reloc_multi_bsd.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Daniel Vetter (based on gem_dummy_reloc_loop*.c)
+ *Zhao Yakui
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm.h"
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_io.h"
+#include "i830_reg.h"
+#include "intel_chipset.h"
+
+#define LOCAL_I915_EXEC_VEBOX (4<<0)
+
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+static drm_intel_bo *target_buffer;
+
+#define NUM_FD 50
+
+static int mfd[NUM_FD];
+static drm_intel_bufmgr *mbufmgr[NUM_FD];
+static struct intel_batchbuffer *mbatch[NUM_FD];
+static drm_intel_bo *mbuffer[NUM_FD];
+
+
+/*
+ * Testcase: Basic check of ring<->cpu sync using a dummy reloc under multi-fd
+ *
+ * The last test (that randomly switches the ring) seems to be pretty effective
+ * at hitting the missed irq bug that's worked around with the HWSTAM irq
write.
+ */
+
+
+#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
+#define MI_DO_COMPARE (1<<21)
+static void
+dummy_reloc_loop(int ring)
+{
+ int i;
+ srandom(0xdeadbeef);
+
+ for (i = 0; i < 0x10; i++) {
+ int mindex = random() % NUM_FD;
+
+ batch = mbatch[mindex];
+ if (ring == I915_EXEC_RENDER) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
+ OUT_BATCH(0x); /* compare dword */
+ OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(MI_NOOP);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_FLUSH_DW | 1);
+ OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(0); /* reserved */
+ OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
+ ADVANCE_BATCH();
+ }
+ intel_batchbuffer_flush_on_ring(batch, ring);
+
+ drm_intel_bo_map(target_buffer, 0);
+ // map to force completion
+ drm_intel_bo_unmap(target_buffer);
+ }
+}
+
+static void
+dummy_reloc_loop_random_ring(int num_rings)
+{
+ int i;
+
+ srandom(0xdeadbeef);
+
+ for (i = 0; i < 0x10; i++) {
+ int mindex;
+ int ring = random() % num_rings + 1;
+
+ m
[Intel-gfx] [PATCH I-g-t 1/2] tests: Add one ring sync case based on multi drm_fd to test ring semaphore sync
The Broadwell GT3 machine has two independent BSD rings in kernel driver while
it is transparent to the user-space driver. In such case it needs to check
the ring sync between the two BSD rings. At the same time it also needs to
check the sync among the second BSD ring and the other rings. Multi drm_fd can
assure that the second BSD ring has the opportunity to dispatch the GPU
command.
Signed-off-by: Zhao Yakui
---
tests/Makefile.sources |1 +
tests/gem_multi_bsd_sync_loop.c | 172 +++
2 files changed, 173 insertions(+)
create mode 100644 tests/gem_multi_bsd_sync_loop.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bf02a48..254a5c5 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -104,6 +104,7 @@ TESTS_progs = \
gem_render_tiled_blits \
gem_ring_sync_copy \
gem_ring_sync_loop \
+ gem_multi_bsd_sync_loop \
gem_seqno_wrap \
gem_set_tiling_vs_gtt \
gem_set_tiling_vs_pwrite \
diff --git a/tests/gem_multi_bsd_sync_loop.c b/tests/gem_multi_bsd_sync_loop.c
new file mode 100644
index 000..7f5b832
--- /dev/null
+++ b/tests/gem_multi_bsd_sync_loop.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Daniel Vetter (based on gem_ring_sync_loop_*.c)
+ *Zhao Yakui
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm.h"
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_io.h"
+#include "i830_reg.h"
+#include "intel_chipset.h"
+
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+static drm_intel_bo *target_buffer;
+
+#define NUM_FD 50
+
+static int mfd[NUM_FD];
+static drm_intel_bufmgr *mbufmgr[NUM_FD];
+static struct intel_batchbuffer *mbatch[NUM_FD];
+static drm_intel_bo *mbuffer[NUM_FD];
+
+
+/*
+ * Testcase: Basic check of ring<->ring sync using a dummy reloc
+ *
+ * Extremely efficient at catching missed irqs with semaphores=0 ...
+ */
+
+#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
+#define MI_DO_COMPARE (1<<21)
+
+static void
+store_dword_loop(int fd)
+{
+ int i;
+ int num_rings = gem_get_num_rings(fd);
+
+ srandom(0xdeadbeef);
+
+ for (i = 0; i < SLOW_QUICK(0x10, 10); i++) {
+ int ring, mindex;
+ ring = random() % num_rings + 1;
+ mindex = random() % NUM_FD;
+ batch = mbatch[mindex];
+ if (ring == I915_EXEC_RENDER) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
+ OUT_BATCH(0x); /* compare dword */
+ OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(MI_NOOP);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_FLUSH_DW | 1);
+ OUT_BATCH(0); /* reserved */
+ OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
+ ADVANCE_BATCH();
+ }
+ intel_batchbuffer_flush_on_ring(batch, ring);
+ }
+
+ drm_intel_bo_map(target_buffer, 0);
+ // map to force waiting on rendering
+ drm_intel_bo_unmap(target_buffer);
+}
+
+igt_simple_main
+{
+ int fd;
+ int devid;
+ int i;
+
+ fd = drm_open_any();
+ devid = intel_get_drm_devid(fd);
+ gem_require_ring(fd, I915_EXEC_BLT);
+
+
+
[Intel-gfx] [PATCH I-g-t 0/2] Tests: Add two test cases based on multi drm_fd to test sync
This follows Daniel's advice to add the two test cases based on multi drm_fd to test the ring sync and CPU<->GPU sync. The Broadwell GT3 machine has two independent BSD rings that can be used to process the video commands. This is implemented in kernel driver and transparent to the user-space. But we still need to check the ring sync and CPU<->GPU sync for the second BSD ring. Two tests are created based on the multi drm_fds to test the sync. Multi drm_fd can assure that the second BSD ring has the opportunity to dispatch the GPU command. Zhao Yakui (2): tests: Add one ring sync case based on multi drm_fd to test ring semaphore sync under multi BSD rings tests: Add dummy_reloc test case based on multi drm_fd to test CPU<->GPU sync under multi BSD rings tests/Makefile.sources|2 + tests/gem_dummy_reloc_multi_bsd.c | 258 + tests/gem_multi_bsd_sync_loop.c | 172 + 3 files changed, 432 insertions(+) create mode 100644 tests/gem_dummy_reloc_multi_bsd.c create mode 100644 tests/gem_multi_bsd_sync_loop.c -- 1.7.10.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/5] drm/i915: Add the support of dual BSD rings on BDW GT3
On Fri, 2014-04-11 at 02:57 -0600, Daniel Vetter wrote: > On Fri, Apr 11, 2014 at 08:56:28AM +0800, Zhao Yakui wrote: > > On Thu, 2014-04-10 at 03:04 -0600, Daniel Vetter wrote: > > > On Thu, Apr 10, 2014 at 04:28:34PM +0800, Zhao Yakui wrote: > > > > BTW: Does it need to check all the flags defined in i915_drm.h or the > > > > exported flag returned by i915_get_parameter? > > > > > > I don't have i915_get_parameter anywhere in my sources, so no idea what > > > you mean ... > > > > Sorry that the function should be i915_getparam. It is called by the > > I915_GETPARAM ioctl to query the flag supported by the driver. > > Ah, now I understand. The idea is to test all fields of the structure > exhaustively (so also rsvd to make sure it's 0). Well except for the > buffer count field since we have tests for that already. > > For the reasons see my two blog posts on the topic: > > http://blog.ffwll.ch/2013/11/testing-requirements-for-drmi915.html > > http://blog.ffwll.ch/2013/11/botching-up-ioctls.html OK. It seems that the case needs to check more fields than the exported flag. I will take a look at your blog and understand how to write the test case. Thanks. Yakui > > Cheers, Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] oops on ILK with piglit
I just ran drm-next on my ILK box and ran piglit inside gnome-shell and got this oops ernel: BUG: unable to handle kernel NULL pointer dereference at 0030 ernel: IP: [] i915_gem_free_request+0x58/0xa0 [i915] ernel: PGD 19152067 PUD 50ef4067 PMD 0 ernel: Oops: [#1] SMP ernel: Modules linked in: nls_utf8 udf ccm arc4 iwldvm mac80211 fuse xt_CHECKSUM iptable_mangle tun bridge stp llc ebtable_nat ebtables bnep ernel: drm i2c_core video ernel: CPU: 1 PID: 648 Comm: shader_runner Not tainted 3.14.0+ #5 ernel: Hardware name: Hewlett-Packard HP EliteBook 2540p/7008, BIOS 68CSU Ver. F.08 11/24/2010 ernel: task: 880105ad6100 ti: 880104aa8000 task.ti: 880104aa8000 ernel: RIP: 0010:[] [] i915_gem_free_request+0x58/0xa0 [i915] ernel: RSP: 0018:880104aa9cf8 EFLAGS: 00010286 ernel: RAX: RBX: 88000388fd20 RCX: dead00200200 ernel: RDX: 880108613090 RSI: 88012f523898 RDI: 88000388f840 ernel: RBP: 880104aa9d08 R08: 88000388fd50 R09: 00018015000b ernel: R10: a00a8f34 R11: ea0002112f80 R12: ernel: R13: 88000388fd50 R14: 0004c488 R15: 880037bb1868 ernel: FS: 7f389ae70880() GS:880137c4() knlGS: ernel: CS: 0010 DS: ES: CR0: 80050033 ernel: CR2: 0030 CR3: 1910c000 CR4: 07e0 ernel: Stack: ernel: 880131f39828 0004c487 880104aa9d50 a00a3a7e ernel: 880131f39928 88000388fd20 880084841800 ernel: 880131f39828 880037bb1868 880104aa9d90 ernel: Call Trace: ernel: [] i915_gem_retire_requests_ring+0xae/0x130 [i915] ernel: [] i915_gem_object_wait_rendering__nonblocking+0xdc/0x110 [i915] ernel: [] i915_gem_set_domain_ioctl+0x91/0x140 [i915] ernel: [] ? __vma_link_rb+0x71/0xe0 ernel: [] drm_ioctl+0x1e0/0x5e0 [drm] ernel: [] ? mmap_region+0x199/0x5a0 ernel: [] ? i915_gem_object_set_to_gtt_domain+0x200/0x200 [i915] ernel: [] do_vfs_ioctl+0x2d8/0x4b0 ernel: [] SyS_ioctl+0x81/0xa0 ernel: [] tracesys+0xdd/0xe2 Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/crtc-helper: gc usless connectro loop in disable_unused_functions
I've forgotten to clean this all up correctly in
commit e3d6ddb35f6221859b6054879d186e13a3af351e
Author: Daniel Vetter
Date: Tue Apr 1 22:15:00 2014 +0200
drm/crtc-helper: don't disable disconnected outputs
Reported-by: Russell King - ARM Linux
Cc: Russell King - ARM Linux
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_crtc_helper.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc_helper.c
b/drivers/gpu/drm/drm_crtc_helper.c
index 1fbe8427c70e..163971fdee58 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -281,16 +281,10 @@ drm_encoder_disable(struct drm_encoder *encoder)
static void __drm_helper_disable_unused_functions(struct drm_device *dev)
{
struct drm_encoder *encoder;
- struct drm_connector *connector;
struct drm_crtc *crtc;
drm_warn_on_modeset_not_all_locked(dev);
- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- if (!connector->encoder)
- continue;
- }
-
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
if (!drm_helper_encoder_in_use(encoder)) {
drm_encoder_disable(encoder);
--
1.9.2
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Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: New drm crtc property for varying the size of borders
On Sun, Apr 13, 2014 at 2:28 PM, Akash Goel wrote: > Yes, the 'Center' Panel fitting mode of "scaling mode" property is not > working on VLV (for HDMI/EDP panels). That sounds like a really good reason for a stab at a CRC based testcase for all this - we've blown up the different upscaling modes way too often already. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] lib/kmstest: Fix up tiled buffer creation
When extracting a raw __gem_set_tiling helper I've fumbled this in
commit 590f6101402b51bca54f69c002380bda967484ea
Author: Daniel Vetter
Date: Wed Oct 9 20:50:50 2013 +0200
lib/drmtest: extract rawer __gem_set_tiling
Fix things up so that we properly propaget the error again.
Now to make this all properly work we also need to make kms_flip a
notch more robust against such failures ...
This only blows up on gen2/3 with the pan tests which want a too wide
framebuffer for tiling.
Signed-off-by: Daniel Vetter
---
lib/igt_fb.c | 6 +++---
lib/igt_kms.c| 1 -
tests/kms_flip.c | 9 ++---
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index ef486f970f03..29a12c6cc640 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -79,7 +79,7 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
unsigned *size_ret, unsigned *stride_ret)
{
uint32_t gem_handle;
- int size;
+ int size, ret = 0;
unsigned stride;
if (tiled) {
@@ -109,13 +109,13 @@ static int create_bo_for_fb(int fd, int width, int
height, int bpp,
gem_handle = gem_create(fd, size);
if (tiled)
- gem_set_tiling(fd, gem_handle, I915_TILING_X, stride);
+ ret = __gem_set_tiling(fd, gem_handle, I915_TILING_X, stride);
*stride_ret = stride;
*size_ret = size;
*gem_handle_ret = gem_handle;
- return 0;
+ return ret;
}
/**
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 9dee855c8053..fffad9f60671 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -56,7 +56,6 @@
* Note that this library's header pulls in the [i-g-t
framebuffer](intel-gpu-tools-i-g-t-framebuffer.html)
* library as a dependency.
*/
-
const char *kmstest_pipe_str(int pipe)
{
const char *str[] = { "A", "B", "C" };
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 24bbc0ba5336..c2f0d2ee9c67 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -1277,11 +1277,13 @@ static void run_test_on_crtc_set(struct test_output *o,
int *crtc_idxs,
true, &o->fb_info[2]);
igt_assert(o->fb_ids[0]);
igt_assert(o->fb_ids[1]);
- igt_assert(o->fb_ids[2]);
+ if (o->flags & TEST_FB_BAD_TILING)
+ igt_require(o->fb_ids[2]);
paint_flip_mode(&o->fb_info[0], false);
paint_flip_mode(&o->fb_info[1], true);
- paint_flip_mode(&o->fb_info[2], true);
+ if (o->fb_ids[2])
+ paint_flip_mode(&o->fb_info[2], true);
if (o->flags & TEST_FB_BAD_TILING)
set_y_tiling(o, 2);
@@ -1329,7 +1331,8 @@ static void run_test_on_crtc_set(struct test_output *o,
int *crtc_idxs,
igt_info("\n%s: PASSED\n\n", test_name);
out:
- igt_remove_fb(drm_fd, &o->fb_info[2]);
+ if (o->fb_ids[2])
+ igt_remove_fb(drm_fd, &o->fb_info[2]);
igt_remove_fb(drm_fd, &o->fb_info[1]);
igt_remove_fb(drm_fd, &o->fb_info[0]);
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.
On Thursday 10 April 2014 04:03 AM, Ben Widawsky wrote:
On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote:
On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrj...@linux.intel.com wrote:
+static void gen8_enable_rps_interrupts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Clear out any stale interrupts first */
+ spin_lock_irq(&dev_priv->irq_lock);
+ WARN_ON(dev_priv->rps.pm_iir);
+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+ dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
+ I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
+ /* only unmask PM interrupts we need. Mask all others. */
+ I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
PMINTRMSK handling is now a part of set_rps (and so this line is
redundant).
-Chris
Thanks Chris. I will make the changes based on the current nightly code
I think my patch kept up with this, but I too am not sure. In either
case feel free to reuse, copy, or review that one.
I don't think I've mailed out the very latest version, but I am pretty
sure I mailed out after the last painful rebase (and it's tested on
BDW).
http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6&id=80fbe001fc4ba38c41db3cec177c9157b2613c3c
Thanks Ben. I will reuse the patches submitted by you
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Re: [Intel-gfx] [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
Thanks for the feedback. I will address all the comments
and I will post cherryview rc6/turbo updated patches within couple of days.
I think the patches need little bit of cleanup.
Thanks
Deepak
On Thursday 10 April 2014 10:36 PM, Ville Syrjälä wrote:
On Thu, Apr 10, 2014 at 07:51:03PM +0300, Jani Nikula wrote:
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
From: Deepak S
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 101 ++--
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0889af7..909cc0a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ if (dev_priv->vlv_pctx) {
+ drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
+ dev_priv->vlv_pctx = NULL;
+ }
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv)
return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
}
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = &dev_priv->gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if (pcbr >> 12 == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size -
pctx_size);
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3595,6 +3630,61 @@ out:
dev_priv->vlv_pctx = pctx;
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
Please no assignment within if; this one's easy to split.
There's a bunch of other checkpatch issues in the series; I don't
personally care about most of them but you might want to run it and see
if you want to do something about it.
Looks like it's a straight up copy-paste from the gen6 and vlv code. So
someone might want to clean those out as well.
And maybe we should just drop this check for CHV since the GT wake FIFO
isn't used anymore. But I'm not sure if the register still hold something
sensible or not.
BR,
Jani.
+ DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_setup_pctx(dev);
+
+ /* 1a & 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* Todo: If BIOS has not configured PCBR
+* then allocate in BIOS Reserved */
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
+
+ /* 3: Enable RC6 */
+ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
+
Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: New drm crtc property for varying the size of borders
On Fri, 2014-04-11 at 14:42 +0300, Ville Syrjälä wrote:
> On Fri, Apr 11, 2014 at 08:34:08AM +0530, Akash Goel wrote:
> > On Thu, 2014-04-10 at 14:34 +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 10, 2014 at 01:13:56PM +0530, Akash Goel wrote:
> > > > On Tue, 2014-04-08 at 19:28 +0300, Ville Syrjälä wrote:
> > > > > On Wed, Mar 26, 2014 at 09:25:12AM +0530, akash.g...@intel.com wrote:
> > > > > > From: Akash Goel
> > > > > >
> > > > > > This patch adds a new drm crtc property for varying the size of
> > > > > > the horizontal & vertical borers of the output/display window.
> > > > > > This will control the output of Panel fitter.
> > > > > >
> > > > > > v2: Added a new check for the invalid border size input
> > > > > >
> > > > > > v3: Fixed bugs in output window calculation
> > > > > > Removed superfluous checks
> > > > > >
> > > > > > v4: Added the capability to forecfully enable the Panel fitter.
> > > > > > The property value is of 64 bits, first 32 bits are used for
> > > > > > border dimensions. The 33rd bit can be used to forcefully
> > > > > > enable the panel fitter. This is useful for Panels which
> > > > > > do not override the User specified Pipe timings.
> > > > > >
> > > > > > Testcase: igt/kms_panel_fitter_test
> > > > > >
> > > > > > Signed-off-by: Akash Goel
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 7 ++
> > > > > > drivers/gpu/drm/i915/intel_display.c | 39 +++-
> > > > > > drivers/gpu/drm/i915/intel_drv.h | 5 +
> > > > > > drivers/gpu/drm/i915/intel_panel.c | 176
> > > > > > ---
> > > > > > 4 files changed, 211 insertions(+), 16 deletions(-)
> > > > > >
> > >
> > > > > > @@ -42,6 +57,60 @@ intel_fixed_panel_mode(const struct
> > > > > > drm_display_mode *fixed_mode,
> > > > > > drm_mode_set_crtcinfo(adjusted_mode, 0);
> > > > > > }
> > > > > >
> > > > > > +void
> > > > > > +intel_pch_manual_panel_fitting(struct intel_crtc *intel_crtc,
> > > > > > + struct intel_crtc_config *pipe_config)
> > > > > > +{
> > > > > > + struct drm_display_mode *adjusted_mode;
> > > > > > + int x, y;
> > > > > > + u32 pf_horizontal_ratio, pf_vertical_ratio;
> > > > > > + u32 tot_width, tot_height;
> > > > > > + u32 src_width, src_height; /* pipesrc.x, pipesrc.y */
> > > > > > + u32 dst_width, dst_height;
> > > > > > +
> > > > > > + adjusted_mode = &pipe_config->adjusted_mode;
> > > > > > +
> > > > > > + src_width = pipe_config->pipe_src_w;
> > > > > > + src_height = pipe_config->pipe_src_h;
> > > > > > +
> > > > > > + tot_width = adjusted_mode->hdisplay;
> > > > > > + tot_height = adjusted_mode->vdisplay;
> > > > > > +
> > > > > > + /*
> > > > > > +* Having non zero borders will reduce the size of
> > > > > > 'HACTIVE/VACTIVE'
> > > > > > +* region. So (HACTIVE - Left border - Right Border) *
> > > > > > +* (VACTIVE - Top Border - Bottom border) will effectively be
> > > > > > the
> > > > > > +* output rectangle on screen
> > > > > > +*/
> > > > > > + dst_width = tot_width -
> > > > > > + (((intel_crtc->border_size >> 16) & 0x) *
> > > > > > 2);
> > > > > > + dst_height = tot_height -
> > > > > > + ((intel_crtc->border_size & 0x) * 2);
> > > > >
> > > > > I'm thinking that we should allow the user to specify each border
> > > > > width
> > > > > individually rather than just assume left==right and top==bottom.
> > > > >
> > > >
> > > > Sorry I thought that the Top/Bottom & left/Right borders would be
> > > > symmetric only.
> > >
> > > I don't see a reason to limit ourselves here.
> > >
> >
> > Fine, will extend this property to set each border separately.
> > Can I use the 12 bits for each border value, as that shall be
> > sufficient.
>
> Maybe just add separate properties for each border value. We already
> have similar properties for TV outputs.
>
ok so should define 4 new properties like "left margin", "right margin",
"top margin", "bottom margin" already defined for TV.
> >
> > > > Tried setting the borders on EDP & HDMI panels by manipulating the Pipe
> > > > timings (through the logic used in 'centre_horizontally' &
> > > > 'centre_vertically' functions), but it didn't work.
> > > > Is this logic effective for the LVDS panel only ?
> > >
> > > Could be. Certainly the border enable bit is there only for LVDS. The
> > > gmch panel fitter isn't very flexible so it's possible we can't
> > > actually make it do many of the things the pch pfit can do.
> > >
> >
> > Yes the GMCH panel fitter function is not equally capable as the PCH
> > counterpart. Here except the LVDS panel, it seems that borders cannot be
> > realized on any other panel, just via the manipulation of Pipe timings
> > (the way it can be done in PCH one).
> > For the same reason the 'Center' Panel fitting mode of "scaling mode"
> > property is not working on VLV (at least for HDMI/EDP panels).
> >
> > > What happens i
[Intel-gfx] [PATCH] drm/i915: Don't check gmch state on inherited configs
... our current modeset code isn't good enough yet to handle this. The
scenario is:
1. BIOS sets up a cloned config with lvds+external screen on the same
pipe, e.g. pipe B.
2. We read out that state for pipe B and assign the gmch_pfit state to
it.
3. The initial modeset switches the lvds to pipe A but due to lack of
atomic modeset we don't recompute the config of pipe B.
-> both pipes now claim (in the sw pipe config structure) to use the
gmch_pfit, which just won't work.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74081
Cc: Alan Stern
Cc: sta...@vger.kernel.org
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 23 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1390ab5e00dc..7b7987dc65ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9655,11 +9655,22 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(pipe_src_w);
PIPE_CONF_CHECK_I(pipe_src_h);
- PIPE_CONF_CHECK_I(gmch_pfit.control);
- /* pfit ratios are autocomputed by the hw on gen4+ */
- if (INTEL_INFO(dev)->gen < 4)
- PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
- PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
+ /*
+* FIXME: BIOS likes to set up a cloned config with lvds+external
+* screen. Since we don't yet re-compute the pipe config when moving
+* just the lvds port away to another pipe the sw tracking won't match.
+*
+* Proper atomic modesets with recomputed global state will fix this.
+* Until then just don't check gmch state for inherited modes.
+*/
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
+ PIPE_CONF_CHECK_I(gmch_pfit.control);
+ /* pfit ratios are autocomputed by the hw on gen4+ */
+ if (INTEL_INFO(dev)->gen < 4)
+ PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
+ PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
+ }
+
PIPE_CONF_CHECK_I(pch_pfit.enabled);
if (current_config->pch_pfit.enabled) {
PIPE_CONF_CHECK_I(pch_pfit.pos);
@@ -11618,6 +11629,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
base.head) {
memset(&crtc->config, 0, sizeof(crtc->config));
+ crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
+
crtc->active = dev_priv->display.get_pipe_config(crtc,
&crtc->config);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c551472b892e..b885df150910 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -236,7 +236,8 @@ struct intel_crtc_config {
* tracked with quirk flags so that fastboot and state checker can act
* accordingly.
*/
-#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags
*/
+#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync
mode.flags */
+#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from
firmware */
unsigned long quirks;
/* User requested mode, only valid as a starting point to
--
1.8.4.rc3
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling
On Mon, Jan 27, 2014 at 10:00:30AM +0100, Daniel Vetter wrote:
> Apparently we really only need this when the pfit is enabled, at least
> I couldn't dicern any difference here. Furthermore the hacks we have
> to reconstruct this bit is a bit glaring, and probably only works
> because we can't move the lvds port to any other pipe than pipe B on
> gen2/3.
>
> So let's just rip this out.
>
> Signed-off-by: Daniel Vetter
I've just written this exact patch again, so figured I might as well merge
it. r-b still appreciated ...
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lvds.c | 7 ---
> drivers/gpu/drm/i915/intel_panel.c | 8
> 2 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 8bcb93a2a9f6..8a3ebe940a74 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -111,13 +111,6 @@ static void intel_lvds_get_config(struct intel_encoder
> *encoder,
>
> pipe_config->adjusted_mode.flags |= flags;
>
> - /* gen2/3 store dither state in pfit control, needs to match */
> - if (INTEL_INFO(dev)->gen < 4) {
> - tmp = I915_READ(PFIT_CONTROL);
> -
> - pipe_config->gmch_pfit.control |= tmp &
> PANEL_8TO6_DITHER_ENABLE;
> - }
> -
> dotclock = pipe_config->port_clock;
>
> if (HAS_PCH_SPLIT(dev_priv->dev))
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 9f83ab06fb5e..41116753f1c0 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -308,16 +308,16 @@ void intel_gmch_panel_fitting(struct intel_crtc
> *intel_crtc,
> pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
>PFIT_FILTER_FUZZY);
>
> + /* Make sure pre-965 set dither correctly for 18bpp panels. */
> + if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
> + pfit_control |= PANEL_8TO6_DITHER_ENABLE;
> +
> out:
> if ((pfit_control & PFIT_ENABLE) == 0) {
> pfit_control = 0;
> pfit_pgm_ratios = 0;
> }
>
> - /* Make sure pre-965 set dither correctly for 18bpp panels. */
> - if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
> - pfit_control |= PANEL_8TO6_DITHER_ENABLE;
> -
> pipe_config->gmch_pfit.control = pfit_control;
> pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
> pipe_config->gmch_pfit.lvds_border_bits = border;
> --
> 1.8.4.rc3
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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