[Intel-gfx] [PATCH v3] drm/i915: New offset for reading frequencies on CHV.
From: Deepak S
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
v3: add break in switch conditions (Ville)
Signed-off-by: Deepak S
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_pm.c | 54 +++--
2 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9692f9..2dcb1b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -605,6 +605,15 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
+#define FB_GFX_FREQ_FUSE_MASK 0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2..b73d601 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4338,11 +4338,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp0;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+ switch (INTEL_INFO(dev)->eu_total) {
+ case 8:
+ /* (2 * 4) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
+ break;
+ case 12:
+ /* (2 * 6) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
+ break;
+ case 16:
+ /* (2 * 8) config */
+ default:
+ /* Setting (2 * 8) Min RP0 for any other
combination */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
+ break;
+ }
+ rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+ }
return rp0;
}
@@ -4358,20 +4382,36 @@ static int cherryview_rps_rpe_freq(struct
drm_i915_private *dev_priv)
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp1;
- val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+ rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK);
+ }
return rp1;
}
static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rpn;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
+ rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
+ FB_GFX_FREQ_FUSE_MASK);
+ } else { /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
+ }
+
return rpn;
}
--
1.9.1
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: New offset for reading frequencies on CHV.
On Friday 16 January 2015 10:39 PM, Ville Syrjälä wrote:
On Fri, Jan 16, 2015 at 08:42:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_pm.c | 53 ++---
2 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9692f9..2dcb1b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -605,6 +605,15 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
+#define FB_GFX_FREQ_FUSE_MASK 0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2..c010d5c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4338,11 +4338,32 @@ void gen6_update_ring_freq(struct drm_device *dev)
static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp0;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+
+ switch (INTEL_INFO(dev)->eu_total) {
+ case 8:
+ /* (2 * 4) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
break;
+ case 12:
+ /* (2 * 6) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
break;
+ case 16:
+ /* (2 * 8) config */
+ default:
+ /* Setting (2 * 8) Min RP0 for any other
combination */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
Maybe break; here too if you feel like it :)
:) Thanks for the review
Hmm. Now that I started to think about it, might we be expecting EUs to
be fused off in some other configurations? In that case the switch
statement might be not be the best idea, or we'd need to use the gnu
case range extension. But we can maybe worry about that later since it
might require more investigative work, or I might be totally off base here
anyway, and we should get this patch in ASAP.
So if you add the missing break statements this patch can have:
Reviewed-by: Ville Syrjälä
+ }
+ rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+ }
return rp0;
}
@@ -4358,20 +4379,36 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp1;
- val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+ rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK);
+ }
return rp1;
}
static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rpn;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
PUNIT_GPU_STATUS_GFX_MIN_FREQ_M
Re: [Intel-gfx] [PATCH] drm/i915: Don't cleanup plane state in intel_plane_destroy()
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5594 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 353/353 352/353 ILK 200/200 200/200 SNB 400/422 400/422 IVB 487/487 487/487 BYT 296/296 296/296 HSW -1 487/508 486/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gen3_render_linear_blits PASS(3, M25M23) CRASH(1, M23) HSW igt_kms_flip_event_leak NSPT(5, M19)PASS(1, M19) NSPT(1, M19) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] intel: Use I915_EXEC_NO_RELOC when available
On Fri, Jan 16, 2015 at 05:46:00PM -0800, Kristian Høgsberg wrote:
> The I915_EXEC_NO_RELOC flag lets us tell the kernel that the offset we
> provide in the validate list entry is what we've used in all relocations
> to the bo in question. If the bo hasn't moved, the kernel can skip
> relocations completely.
>
> Signed-off-by: Kristian Høgsberg
> ---
> intel/intel_bufmgr_gem.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 8a51cea..a657a4d 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -131,6 +131,7 @@ typedef struct _drm_intel_bufmgr_gem {
> unsigned int no_exec : 1;
> unsigned int has_vebox : 1;
> unsigned int has_handle_lut : 1;
> + unsigned int has_no_reloc : 1;
> bool fenced_relocs;
>
> char *aub_filename;
> @@ -504,7 +505,15 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int
> need_fence)
> bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
> bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
> bufmgr_gem->exec2_objects[index].alignment = 0;
> - bufmgr_gem->exec2_objects[index].offset = 0;
> +
> + /* If the kernel supports I915_EXEC_NO_RELOC, it will compare
> + * offset in struct drm_i915_gem_exec_object2 against the bos
> + * current offset and if all bos haven't moved it will skip
> + * relocation processing alltogether. If I915_EXEC_NO_RELOC
> + * is not supported, the kernel ignores the incoming value of
> + * offset so we can set it either way.
> + */
> + bufmgr_gem->exec2_objects[index].offset = bo->offset64;
> bufmgr_gem->exec_bos[index] = bo;
> bufmgr_gem->exec2_objects[index].flags = 0;
> bufmgr_gem->exec2_objects[index].rsvd1 = 0;
> @@ -2471,6 +2480,8 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context
> *ctx,
>
> if (bufmgr_gem->has_handle_lut)
> execbuf.flags |= I915_EXEC_HANDLE_LUT;
> + if (bufmgr_gem->has_no_reloc)
> + execbuf.flags |= I915_EXEC_NO_RELOC;
You need some opt-in flag to not break existing userspace: Iirc both UXA
and libva retain reloc trees partially, which means that we might have
different presumed offsets for the same bo in different relocs.
This is only safe when you throw away and rebuild the reloc tree with all
buffers completely each time around (like current mesa does afaik).
-Daniel
>
> ret = drmIoctl(bufmgr_gem->fd,
> DRM_IOCTL_I915_GEM_EXECBUFFER2,
> @@ -3598,6 +3609,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
> ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
> bufmgr_gem->has_handle_lut = ret == 0;
>
> + gp.param = I915_PARAM_HAS_EXEC_NO_RELOC;
> + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
> + bufmgr_gem->has_no_reloc = ret == 0;
> +
> /* Let's go with one relocation per every 2 dwords (but round down a bit
> * since a power of two will mean an extra page allocation for the reloc
> * buffer).
> --
> 2.2.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Enabling PSR on Skylake
On Fri, Jan 16, 2015 at 02:07:26PM +0530, Sonika Jindal wrote:
> Mainly taking care of some register offsets, otherwise things are similar to
> hsw. Also, programming ddi aux to use hardcoded values for psr data select.
>
> v2: introduce EDP_PSR_AUX_BASE macro (Chris)
> v3: Moving to HW tracking for SKL+ platforms, so activating source psr during
> psr_enabling and then avoiding psr entries and exits for each frontbuffer
> updates.
>
> Signed-off-by: Sonika Jindal
> ---
> drivers/gpu/drm/i915/i915_drv.h |3 ++-
> drivers/gpu/drm/i915/i915_reg.h | 19 +--
> drivers/gpu/drm/i915/intel_frontbuffer.c |7 +--
> drivers/gpu/drm/i915/intel_psr.c | 18 +-
> 4 files changed, 37 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 42c69ca..ee5cd3b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2355,7 +2355,8 @@ struct drm_i915_cmd_table {
> #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
> - IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
> + IS_SKYLAKE(dev))
> #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
> IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
> #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a828cf5..068c8da 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2619,12 +2619,14 @@ enum skl_disp_power_wells {
> #define EDP_PSR_TP1_TIME_0us (3<<4)
> #define EDP_PSR_IDLE_FRAME_SHIFT 0
>
> -#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
> -#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
> -#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
> -#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
> -#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
> +#define EDP_PSR_AUX_BASE(dev) (INTEL_INFO(dev)->gen >= 9 ? \
> + 0x64000 : EDP_PSR_BASE(dev))
> +#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_AUX_BASE(dev) + 0x10)
> +#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_AUX_BASE(dev) + 0x14)
> +#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_AUX_BASE(dev) + 0x18)
> +#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_AUX_BASE(dev) + 0x1c)
> +#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_AUX_BASE(dev) + 0x20)
> +#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_AUX_BASE(dev) + 0x24)
>
> #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> @@ -3771,6 +3773,11 @@ enum skl_disp_power_wells {
> #define DP_AUX_CH_CTL_PRECHARGE_TEST(1 << 11)
> #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK(0x7ff)
> #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
> +#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
> +#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
> +#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
> +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
> +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c
> b/drivers/gpu/drm/i915/intel_frontbuffer.c
> index 79f6d72..010d550 100644
> --- a/drivers/gpu/drm/i915/intel_frontbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
> @@ -156,7 +156,9 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object
> *obj,
>
> intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
>
> - intel_psr_invalidate(dev, obj->frontbuffer_bits);
> +
> + if (INTEL_INFO(dev)->gen < 9)
> + intel_psr_invalidate(dev, obj->frontbuffer_bits);
> }
>
> /**
> @@ -182,7 +184,8 @@ void intel_frontbuffer_flush(struct drm_device *dev,
>
> intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
>
> - intel_psr_flush(dev, frontbuffer_bits);
> + if (INTEL_INFO(dev)->gen < 9)
> + intel_psr_flush(dev, frontbuffer_bits);
I'm pretty sure the hw isn't good enough yet to detect everything,
unfortunately the testcase is also not quite ready yet. In any case these
changes should be moved into the inel_psr_* functions and in a separate
patch.
Also someone needs to re-review the psr igt testcase to make sure it
covers everything. Ville could do that too since he's done the fbc
testcase.
-Daniel
>
> /*
> * FIXME: Unconditional fbc flushing here is a rather gross hack and
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index dd0e6e0..6d2cdb8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -173,11 +173,24 @@ static void hsw_psr_enable_sink(struct intel_dp
> *intel_dp)
> I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
> intel_dp_pack_aux(&aux_msg[i], sizeof(a
Re: [Intel-gfx] [PATCH] drm/i915: Do not invalidate obj->pages under mempressure
On Thu, Jan 15, 2015 at 08:44:00PM +, Chris Wilson wrote: > On Thu, Jan 15, 2015 at 08:36:15PM +0100, Daniel Vetter wrote: > > On Wed, Jan 14, 2015 at 9:34 PM, Chris Wilson > > wrote: > > > This (partially) reverts > > > > > > commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd > > > Author: Chris Wilson > > > Date: Tue Mar 25 13:23:06 2014 + > > > > > > drm/i915: Invalidate our pages under memory pressure > > > > Shouldn't we also revert the hunk in i915_gem_free_objects? Without > > the truncate vs. invalidate disdinction it seems to have lost it's > > reason for existence ... > > No, setting MADV_DONTNEED has other nice properties during put_pages() - > I think it is useful in its own right, for example that is where my page > stealing code goes... Well right now I can't make sense of this bit any more (tbh I didn't with the other code either, but overlooked that while reviewing). When it's just there for future work but atm dead code I prefer for it to get removed. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
On Thu, Jan 15, 2015 at 01:25:02PM +0200, Jani Nikula wrote:
> On Wed, 14 Jan 2015, "Singh, Gaurav K" wrote:
> > On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
> >>
> >> On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
> >>> For CHT changes are required for calculating the correct m,n & p with
> >>> minimal error +/- for the required DSI clock, so that the correct
> >>> dividor
> >>> & ctrl values are written in cck regs for DSI. This patch has been
> >>> tested
> >>> on CHT RVP with 1200 x 1920 panel.
> >>>
> >>> Signed-off-by: Gaurav K Singh
> >>> ---
> >>> drivers/gpu/drm/i915/intel_dsi_pll.c | 43
> >>> ++
> >>> 1 file changed, 33 insertions(+), 10 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> index 8957f10..9236b66 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int
> >>> pixel_format, int lane_count)
> >>> #endif
> >>> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> >>> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
> >>> +u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> >>> {
> >>> u32 m, n, p;
> >>> u32 ref_clk;
> >>> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> u32 calc_m;
> >>> u32 calc_p;
> >>> u32 m_seed;
> >>> +u32 m_start;
> >>> +u32 m_limit;
> >>> +u32 n_limit;
> >>> +u32 p_limit;
> >>> /* dsi_clk is expected in KHZ */
> >>> if (dsi_clk < 30 || dsi_clk > 115) {
> >>> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> return -ECHRNG;
> >>> }
> >>> -ref_clk = 25000;
> >>> +if (IS_CHERRYVIEW(dev_priv->dev)) {
> >>> +ref_clk = 10;
> >>> +m_start = 70;
> >>> +m_limit = 96;
> >>> +n_limit = 4;
> >>> +p_limit = 6;
> >>> +} else if (IS_VALLEYVIEW(dev_priv->dev)) {
> >>> +ref_clk = 25000;
> >>> +m_start = 62;
> >>> +m_limit = 92;
> >>> +n_limit = 1;
> >>> +p_limit = 6;
> >>> +} else {
> >>> +DRM_ERROR("Unsupported device\n");
> >>> +return -ENODEV;
> >>> +}
> >>> target_dsi_clk = dsi_clk;
> >>> error = 0x;
> >>> tmp_error = 0x;
> >>> calc_m = 0;
> >>> calc_p = 0;
> >>> -for (m = 62; m <= 92; m++) {
> >>> -for (p = 2; p <= 6; p++) {
> >>> +for (m = m_start; m <= m_limit; m++) {
> >>> +for (p = 2; p <= p_limit; p++) {
> >>> /* Find the optimal m and p divisors
> >>> with minimal error +/- the required clock */
> >>> -calc_dsi_clk = (m * ref_clk) / p;
> >>> +calc_dsi_clk = (m * ref_clk) / (p * n_limit);
> >>> if (calc_dsi_clk == target_dsi_clk) {
> >>> calc_m = m;
> >>> calc_p = p;
> >>> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> }
> >>> m_seed = lfsr_converts[calc_m - 62];
> >>> -n = 1;
> >>> +n = n_limit;
> >>> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT +
> >>> calc_p - 2);
> >>> -dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> >>> -m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> -
> >>> +if (IS_CHERRYVIEW(dev_priv->dev))
> >>> +dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
> >>> +m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> +else
> >>> +dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> >>> +m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> return 0;
> >>> }
> >>> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct
> >>> intel_encoder *encoder)
> >>> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
> >>> intel_dsi->pixel_format,
> >>> intel_dsi->lane_count);
> >>> -ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
> >>> +ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
> >>> if (ret) {
> >>> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> >>> return;
> >> Hi Jani,
> >>
> >> Could you please review this patch?
> >>
> >> With regards,
> >> Gaurav
> >>
> > Hi Jani,
> >
> > Could you please review this patch?
>
> I did, almost a month ago!
> 87h9ws2dbz.fsf@intel.com">http://mid.mail-archive.com/87h9ws2dbz.fsf@intel.com
>
> Daniel, please pick it up.
Well, review said "Otherwise r-b: Jani" which I interpreted as "please
apply my suggestions, with that's it's good for a review tag. And since
Gaurav didn't reply I've figured that a revised version is in the works
...
Gaurav, can you please apply the bit of polish plus Jani's r-b tag an
resend?
Thanks, Daniel
>
> Gaurav, please let us know if there are any more pending patches that
> we've faile
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Fix mutex->owner inspection race under DEBUG_MUTEXES"
On Thu, Jan 15, 2015 at 09:13:02AM +0200, Jani Nikula wrote: > On Wed, 14 Jan 2015, Chris Wilson wrote: > > The core fix was applied in > > > > commit a63b03e2d2477586440741677ecac45bcf28d7b1 > > Author: Chris Wilson > > Date: Tue Jan 6 10:29:35 2015 + > > > > mutex: Always clear owner field upon mutex_unlock() > > > > (note the absence of stable@ tag) > > > > so we can now revert our band-aid commit 226e5ae9e5f910 for -next. > > Daniel, this one is for dinq, not fixes. I tried to apply it, then noticed that I don't even have the original patch in there yet. It's sitting in your latest -fixes pull (which means that patch is not really needed since the real fix in the mutex code landed). Imo better if we don't ship a kernel with this. -Daniel > > BR, > Jani. > > > > > Signed-off-by: Chris Wilson > > Cc: Daniel Vetter > > Cc: Jani Nikula > > --- > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > b/drivers/gpu/drm/i915/i915_gem.c > > index b06f051a73de..31219af4b7a5 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -5082,7 +5082,7 @@ static bool mutex_is_locked_by(struct mutex *mutex, > > struct task_struct *task) > > if (!mutex_is_locked(mutex)) > > return false; > > > > -#if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES) > > +#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) > > return mutex->owner == task; > > #else > > /* Since UP may be pre-empted, we cannot assume that we own the lock */ > > -- > > 2.1.4 > > > > -- > Jani Nikula, Intel Open Source Technology Center -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] intel: Use I915_EXEC_HANDLE_LUT when available
In userspace we can track which buffer a relocation refers to in
constant time. However, the kernel has to look up the per-fd gem
handle for each relocation. Using the I915_EXEC_HANDLE_LUT flag lets
us use the the bos validation list index instead of the gem handle in
the relocation entries. This allows the kernel to look up the bo for
a reloc in constant time.
Signed-off-by: Kristian Høgsberg
---
intel/intel_bufmgr_gem.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index cf85bb8..8a51cea 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -130,6 +130,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
unsigned int has_vebox : 1;
+ unsigned int has_handle_lut : 1;
bool fenced_relocs;
char *aub_filename;
@@ -399,11 +400,12 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem
*bufmgr_gem)
(drm_intel_bo_gem *) target_bo;
DBG("%2d: %d (%s)@0x%08llx -> "
- "%d (%s)@0x%08lx + 0x%08x\n",
+ "%d (#%d) (%s)@0x%08lx + 0x%08x\n",
i,
bo_gem->gem_handle, bo_gem->name,
(unsigned long long)bo_gem->relocs[j].offset,
target_gem->gem_handle,
+ bo_gem->relocs[j].target_handle,
target_gem->name,
target_bo->offset64,
bo_gem->relocs[j].delta);
@@ -470,7 +472,7 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int
need_fence)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
- int index;
+ int i, index;
if (bo_gem->validate_index != -1) {
if (need_fence)
@@ -512,6 +514,26 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int
need_fence)
EXEC_OBJECT_NEEDS_FENCE;
}
bufmgr_gem->exec_count++;
+
+ if (bufmgr_gem->has_handle_lut) {
+ /* If the kernel supports I915_EXEC_HANDLE_LUT, we can
+* use validate_index instead of the gem handle in
+* target_handle in the reloc entry. This allows the
+* kernel to do a simple constant time lookup instead
+* of looking up the gem handle for each reloc.
+*
+* We have to fix up the relocs here, since the bo_gem
+* needs to have a valid validate_index in case there
+* are self-relocs in the reloc list.
+*/
+ for (i = 0; i < bo_gem->reloc_count; i++) {
+ drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)
+ bo_gem->reloc_target_info[i].bo;
+
+ bo_gem->relocs[i].target_handle =
+ target_bo_gem->validate_index;
+ }
+ }
}
#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
@@ -2447,6 +2469,9 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context
*ctx,
if (bufmgr_gem->no_exec)
goto skip_execution;
+ if (bufmgr_gem->has_handle_lut)
+ execbuf.flags |= I915_EXEC_HANDLE_LUT;
+
ret = drmIoctl(bufmgr_gem->fd,
DRM_IOCTL_I915_GEM_EXECBUFFER2,
&execbuf);
@@ -3569,6 +3594,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
}
}
+ gp.param = I915_PARAM_HAS_EXEC_HANDLE_LUT;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_handle_lut = ret == 0;
+
/* Let's go with one relocation per every 2 dwords (but round down a bit
* since a power of two will mean an extra page allocation for the reloc
* buffer).
--
2.2.1
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[Intel-gfx] [PATCH 2/2] intel: Use I915_EXEC_NO_RELOC when available
The I915_EXEC_NO_RELOC flag lets us tell the kernel that the offset we
provide in the validate list entry is what we've used in all relocations
to the bo in question. If the bo hasn't moved, the kernel can skip
relocations completely.
Signed-off-by: Kristian Høgsberg
---
intel/intel_bufmgr_gem.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 8a51cea..a657a4d 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -131,6 +131,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int no_exec : 1;
unsigned int has_vebox : 1;
unsigned int has_handle_lut : 1;
+ unsigned int has_no_reloc : 1;
bool fenced_relocs;
char *aub_filename;
@@ -504,7 +505,15 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int
need_fence)
bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->exec2_objects[index].alignment = 0;
- bufmgr_gem->exec2_objects[index].offset = 0;
+
+ /* If the kernel supports I915_EXEC_NO_RELOC, it will compare
+* offset in struct drm_i915_gem_exec_object2 against the bos
+* current offset and if all bos haven't moved it will skip
+* relocation processing alltogether. If I915_EXEC_NO_RELOC
+* is not supported, the kernel ignores the incoming value of
+* offset so we can set it either way.
+*/
+ bufmgr_gem->exec2_objects[index].offset = bo->offset64;
bufmgr_gem->exec_bos[index] = bo;
bufmgr_gem->exec2_objects[index].flags = 0;
bufmgr_gem->exec2_objects[index].rsvd1 = 0;
@@ -2471,6 +2480,8 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context
*ctx,
if (bufmgr_gem->has_handle_lut)
execbuf.flags |= I915_EXEC_HANDLE_LUT;
+ if (bufmgr_gem->has_no_reloc)
+ execbuf.flags |= I915_EXEC_NO_RELOC;
ret = drmIoctl(bufmgr_gem->fd,
DRM_IOCTL_I915_GEM_EXECBUFFER2,
@@ -3598,6 +3609,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
bufmgr_gem->has_handle_lut = ret == 0;
+ gp.param = I915_PARAM_HAS_EXEC_NO_RELOC;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_no_reloc = ret == 0;
+
/* Let's go with one relocation per every 2 dwords (but round down a bit
* since a power of two will mean an extra page allocation for the reloc
* buffer).
--
2.2.1
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Re: [Intel-gfx] [PATCH 6/7] drm/i915: Improve how the memory for crtc state is allocated
On Thu, Jan 15, 2015 at 02:55:26PM +0200, Ander Conselvan de Oliveira wrote:
> The previous patch changed the config field in intel_crtc to a pointer,
> but to keep the mechanical changes (done with spatch) separate from the
> new code, the pointer was made to point to a new _config field with type
> struct intel_crtc_state added to that struct. This patch improves that
> code by getting rid of that field, allocating a state struct in
> intel_crtc_init() a keeping it properly updated when a mode set
> happens.
>
> v2: Manual changes split from previous patch. (Matt)
> Don't leak the current state when the crtc is destroyed (Matt)
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_display.c | 20
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index acdaed2..002e5a9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8926,6 +8926,13 @@ out:
> intel_runtime_pm_put(dev_priv);
> }
>
> +static void intel_crtc_set_state(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state)
> +{
> + kfree(crtc->config);
> + crtc->config = crtc_state;
> +}
> +
> static void intel_crtc_destroy(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -8944,6 +8951,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
>
> drm_crtc_cleanup(crtc);
>
> + intel_crtc_set_state(intel_crtc, NULL);
Actually I just looked at this again and I think this is going to cause
a non-fatal warning on unload. Given your update of the base state in
patch 7, the drm_crtc_cleanup() here is going to see crtc->state as non-NULL and
try to clean it up itself. But since you haven't implemented
crtc->funcs->atomic_destroy_state(), it will just throw a warning and
continue on.
So I think you want to do one of the following:
* Move the intel_crtc_set_state() call above drm_crtc_cleanup() so that
the core won't see a non-NULL state and think it needs to clean up.
* Completely drop the intel_crtc_set_state() call and instead implement
crtc->funcs->atomic_destroy_state() so that the core can handle the
cleanup for us.
Matt
> kfree(intel_crtc);
> }
>
> @@ -10995,8 +11003,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> crtc->mode = *mode;
> /* mode_set/enable/disable functions rely on a correct pipe
>* config. */
> - (*(to_intel_crtc(crtc)->config)) = *pipe_config;
> - to_intel_crtc(crtc)->new_config = to_intel_crtc(crtc)->config;
> + intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
>
> /*
>* Calculate and store various constants which
> @@ -11040,7 +11047,6 @@ done:
> if (ret && crtc->enabled)
> crtc->mode = *saved_mode;
>
> - kfree(pipe_config);
> kfree(saved_mode);
> return ret;
> }
> @@ -12187,6 +12193,7 @@ static void intel_crtc_init(struct drm_device *dev,
> int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state = NULL;
> struct drm_plane *primary = NULL;
> struct drm_plane *cursor = NULL;
> int i, ret;
> @@ -12195,6 +12202,11 @@ static void intel_crtc_init(struct drm_device *dev,
> int pipe)
> if (intel_crtc == NULL)
> return;
>
> + crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
> + if (!crtc_state)
> + goto fail;
> + intel_crtc_set_state(intel_crtc, crtc_state);
> +
> primary = intel_primary_plane_create(dev, pipe);
> if (!primary)
> goto fail;
> @@ -12240,7 +12252,6 @@ static void intel_crtc_init(struct drm_device *dev,
> int pipe)
> drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
>
> WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
> - intel_crtc->config = &intel_crtc->_config;
> return;
>
> fail:
> @@ -12248,6 +12259,7 @@ fail:
> drm_plane_cleanup(primary);
> if (cursor)
> drm_plane_cleanup(cursor);
> + kfree(crtc_state);
> kfree(intel_crtc);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 0b59a93..c8c0b7f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -469,7 +469,6 @@ struct intel_crtc {
> uint32_t cursor_base;
>
> struct intel_plane_config plane_config;
> - struct intel_crtc_state _config;
> struct intel_crtc_state *config;
> struct intel_crtc_state *new_config;
> bool new_enabled;
> --
> 1.9.1
>
> ___
> Intel-
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Rename i915_gen6_forcewake_count_info
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5592 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 353/353 352/353 ILK 200/200 200/200 SNB 400/422 400/422 IVB 487/487 487/487 BYT 296/296 296/296 HSW -1 487/508 486/508 BDW -2 401/402 399/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_fence_thrash_bo-write-verify-threaded-none PASS(2, M25M7) CRASH(1, M7) HSW igt_kms_flip_event_leak NSPT(4, M19)PASS(1, M19) NSPT(1, M19) *BDW igt_gem_pwrite_pread_display-pwrite-blt-gtt_mmap-performance PASS(2, M30M28) DMESG_WARN(1, M28) *BDW igt_gem_pwrite_pread_uncached-pwrite-blt-gtt_mmap-performance PASS(2, M30M28) DMESG_WARN(1, M28) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v2] tools/intel_gpu_frequency: remove use of getsubopt
On Fri, Jan 16, 2015 at 09:12:15AM +, tim.g...@intel.com wrote: > From: Tim Gore > > getsubopt is not available in android. The "get" option > doesn't really need sub-options, just display all the > current frequency settings (as per discussion with > Ben Widawsky) > > Signed-off-by: Tim Gore Sorry, I forgot you probably don't have push access. I would have fixed it myself if I remembered that. You missed the -geff example in the comments, but I fixed that and pushed. Thank you. [snip] ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] SKL turbo part 1
The turbo work is not quite complete with those patches, but it's a big step forward. The missing bit is that the granularity of frequency the GPU supports has changed. For this reason, I left in the code disabling gen6_rps_irq_handler() for gen9+ in until we have a proper implementation. -- Damien Akash Goel (1): drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau (1): drm/i915/skl: Retrieve the frequency limits Jesse Barnes (1): drm/i915/skl: add turbo support Zhe Wang (1): drm/i915/skl: Gen9 coarse power gating drivers/gpu/drm/i915/i915_debugfs.c | 44 +++-- drivers/gpu/drm/i915/i915_reg.h | 6 + drivers/gpu/drm/i915/intel_pm.c | 40 + 3 files changed, 88 insertions(+), 2 deletions(-) -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits
v2: Use the new function, gen6_init_rps_frequencies() (Damien) Reviewed-by: Mika Kuoppala (v1) Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3a0aec0..f40b8f2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4032,6 +4032,8 @@ static void gen9_enable_rps(struct drm_device *dev) gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + gen6_init_rps_frequencies(dev); + I915_WRITE(GEN6_RPNSWREQ, 0xc80); I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc80); -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9
From: Akash Goel
Updated the i915_drpc_info & i915_gen6_forcewake_count debugfs interface
v2: Change all IS_GEN9() by gen >= 9 (Damien)
Change-Id: Ibed2fb71b233a369e69278bc96298df82d032a47
Signed-off-by: Akash Goel
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index aac6126..b0a142d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1347,8 +1347,10 @@ static int gen6_drpc_info(struct seq_file *m)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+ u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
unsigned forcewake_count;
int count = 0, ret;
+ u32 fw_rendercount = 0, fw_mediacount = 0, fw_blittercount = 0;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
@@ -1374,6 +1376,10 @@ static int gen6_drpc_info(struct seq_file *m)
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
+ if (INTEL_INFO(dev)->gen >= 9) {
+ gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
+ gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
+ }
mutex_unlock(&dev->struct_mutex);
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -1392,6 +1398,12 @@ static int gen6_drpc_info(struct seq_file *m)
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & 0x1));
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & 0x2));
+ }
seq_printf(m, "Deep RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
seq_printf(m, "Deepest RC6 Enabled: %s\n",
@@ -1420,6 +1432,14 @@ static int gen6_drpc_info(struct seq_file *m)
seq_printf(m, "Core Power Down: %s\n",
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Power Well: %s\n",
+ (gen9_powergate_status &
+GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+ seq_printf(m, "Media Power Well: %s\n",
+ (gen9_powergate_status &
+GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ }
/* Not exactly sure what this is */
seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
@@ -1437,6 +1457,20 @@ static int gen6_drpc_info(struct seq_file *m)
GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
seq_printf(m, "RC6++ voltage: %dmV\n",
GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
+
+ if (INTEL_INFO(dev)->gen >= 9) {
+ spin_lock_irq(&dev_priv->uncore.lock);
+ fw_rendercount = dev_priv->uncore.fw_rendercount;
+ fw_mediacount = dev_priv->uncore.fw_mediacount;
+ fw_blittercount = dev_priv->uncore.fw_blittercount;
+ spin_unlock_irq(&dev_priv->uncore.lock);
+
+ seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
+ seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
+ seq_printf(m, "Forcewake Blitter Count = %u\n",
+ fw_blittercount);
+ }
+
return 0;
}
@@ -1990,18 +2024,24 @@ static int i915_gen6_forcewake_count_info(struct
seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
+ unsigned fw_blittercount = 0;
spin_lock_irq(&dev_priv->uncore.lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
fw_rendercount = dev_priv->uncore.fw_rendercount;
fw_mediacount = dev_priv->uncore.fw_mediacount;
+ if (INTEL_INFO(dev)->gen >= 9)
+ fw_blittercount = dev_priv->uncore.fw_blittercount;
} else
forcewake_count = dev_priv->uncore.forcewake_count;
+
spin_unlock_irq(&dev_priv->uncore.lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
[Intel-gfx] [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating
From: Zhe Wang
Enable coarse power gating for Gen9. This feature allows render and
media engine to enter RC6 independently. Policies are configured
together with RC6. This feature will only be enabled when RC6 is
enabled.
Signed-off-by: Zhe Wang
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb96041..3d08f9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,9 @@ enum skl_disp_power_wells {
#define GEN6_PMINTRMSK 0xA168
#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
#define VLV_PWRDWNUPCTL0xA294
+#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
+#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
+#define GEN9_PG_ENABLE 0xA210
#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
#define PIXEL_OVERLAP_CNT_MASK(3 << 30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f40b8f2..71bf4f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3892,6 +3892,7 @@ static void gen9_disable_rps(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(GEN6_RC_CONTROL, 0);
+ I915_WRITE(GEN9_PG_ENABLE, 0);
}
static void gen6_disable_rps(struct drm_device *dev)
@@ -4081,6 +4082,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
I915_WRITE(GEN6_RC_SLEEP, 0);
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ /* 2c: Program Coarse Power Gating Policies. */
+ I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
+ I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
+
/* 3a: Enable RC6 */
if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -4090,6 +4095,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
+ /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.8.3.1
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[Intel-gfx] [PATCH 1/4] drm/i915/skl: add turbo support
From: Jesse Barnes
Per latest PM programming guide.
v2: the wrong flavour of the function updating the ring frequency was
called, leading to dead locks (Tvrtko)
v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien)
Signed-off-by: Jesse Barnes
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2..3a0aec0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4025,9 +4025,37 @@ static void gen6_init_rps_frequencies(struct drm_device
*dev)
}
}
+/* See the Gen9_GT_PM_Programming_Guide doc for the below */
static void gen9_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ I915_WRITE(GEN6_RPNSWREQ, 0xc80);
+ I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc80);
+
+ I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x1206);
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
+ I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
+ I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
+ I915_WRITE(GEN6_PMINTRMSK, 0x6);
+ I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_AVG);
+
+ gen6_enable_rps_interrupts(dev);
+
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void gen9_enable_rc6(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
uint32_t rc6_mask = 0;
int unused;
@@ -5527,7 +,9 @@ static void intel_gen6_powersave_work(struct work_struct
*work)
} else if (IS_VALLEYVIEW(dev)) {
valleyview_enable_rps(dev);
} else if (INTEL_INFO(dev)->gen >= 9) {
+ gen9_enable_rc6(dev);
gen9_enable_rps(dev);
+ __gen6_update_ring_freq(dev);
} else if (IS_BROADWELL(dev)) {
gen8_enable_rps(dev);
__gen6_update_ring_freq(dev);
--
1.8.3.1
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Starting with Cherryview, devices may have a varying number of EU for
> a given ID due to creative fusing. Punit support different frequency for
> different fuse data. We use this patch to help get total eu enabled and
> read the right offset to get RP0
>
> Based upon a patch from Jeff, but reworked to only store eu_total and
> avoid sending info to userspace
>
> v2: Format register definitions (Jani)
>
> Signed-off-by: Deepak S
> Signed-off-by: Jeff McGee
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_dma.c | 11 +++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 2447de3..b868e9d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct
> drm_device *dev)
> info->num_pipes = 0;
> }
> }
> +
> + if (IS_CHERRYVIEW(dev)) {
> + u32 fuse, mask_eu;
> +
> + fuse = I915_READ(CHV_FUSE_GT);
> + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> + CHV_FGT_EU_DIS_SS0_R1_MASK |
> + CHV_FGT_EU_DIS_SS1_R0_MASK |
> + CHV_FGT_EU_DIS_SS1_R1_MASK);
> + info->eu_total = 16 - hweight32(mask_eu);
> + }
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 66f0c60..ab1fa9e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -653,6 +653,7 @@ struct intel_device_info {
> int trans_offsets[I915_MAX_TRANSCODERS];
> int palette_offsets[I915_MAX_PIPES];
> int cursor_offsets[I915_MAX_PIPES];
> + unsigned int eu_total;
> };
>
> #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a39bb03..d9692f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1471,6 +1471,17 @@ enum punit_power_well {
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
>
> +/* Fuse readout registers for GT */
> +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
> +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT16
> +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
> +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT20
> +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
> +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT24
> +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
> +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT28
> +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
> +
> #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> --
> 1.9.1
--
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Increase the range of sideband address.
On Fri, Jan 16, 2015 at 08:42:17PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Looks like latest BSW/CHV production system has sideband address > 128.
> Use u32 data types to cover new offset/address range :)
>
> Signed-off-by: Deepak S
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ab1fa9e..272088c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3130,8 +3130,8 @@ int sandybridge_pcode_read(struct drm_i915_private
> *dev_priv, u32 mbox, u32 *val
> int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32
> val);
>
> /* intel_sideband.c */
> -u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
> -void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
> +u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> +void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index 01d841e..3c42eef 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private
> *dev_priv, u32 devfn,
> return 0;
> }
>
> -u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
> +u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
> {
> u32 val = 0;
>
> @@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8
> addr)
> return val;
> }
>
> -void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
> +void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
> {
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>
> --
> 1.9.1
--
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: New offset for reading frequencies on CHV.
On Fri, Jan 16, 2015 at 08:42:18PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Use new Sideband offset to read max/min/gaur freq based on the SKU it
> is running on. Based on the Number of EU, we read different bits to
> identify the max frequencies at which system can run.
>
> v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
>
> Signed-off-by: Deepak S
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++
> drivers/gpu/drm/i915/intel_pm.c | 53
> ++---
> 2 files changed, 54 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9692f9..2dcb1b3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -605,6 +605,15 @@ enum punit_power_well {
> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>
> +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
> +#define FB_GFX_FREQ_FUSE_MASK0xff
> +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT24
> +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT16
> +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT8
> +
> +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
> +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
> +
> #define PUNIT_GPU_STATUS_REG 0xdb
> #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 03fc7f2..c010d5c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4338,11 +4338,32 @@ void gen6_update_ring_freq(struct drm_device *dev)
>
> static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> {
> + struct drm_device *dev = dev_priv->dev;
> u32 val, rp0;
>
> - val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> - rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> -
> + if (dev->pdev->revision >= 0x20) {
> + val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> +
> + switch (INTEL_INFO(dev)->eu_total) {
> + case 8:
> + /* (2 * 4) config */
> + rp0 = (val >>
> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
break;
> + case 12:
> + /* (2 * 6) config */
> + rp0 = (val >>
> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
break;
> + case 16:
> + /* (2 * 8) config */
> + default:
> + /* Setting (2 * 8) Min RP0 for any other
> combination */
> + rp0 = (val >>
> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
Maybe break; here too if you feel like it :)
Hmm. Now that I started to think about it, might we be expecting EUs to
be fused off in some other configurations? In that case the switch
statement might be not be the best idea, or we'd need to use the gnu
case range extension. But we can maybe worry about that later since it
might require more investigative work, or I might be totally off base here
anyway, and we should get this patch in ASAP.
So if you add the missing break statements this patch can have:
Reviewed-by: Ville Syrjälä
> + }
> + rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> + } else {
> + /* For pre-production hardware */
> + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> + rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> +PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> + }
> return rp0;
> }
>
> @@ -4358,20 +4379,36 @@ static int cherryview_rps_rpe_freq(struct
> drm_i915_private *dev_priv)
>
> static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> {
> + struct drm_device *dev = dev_priv->dev;
> u32 val, rp1;
>
> - val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> - rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> -
> + if (dev->pdev->revision >= 0x20) {
> + val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> + rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> + } else {
> + /* For pre-production hardware */
> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> +PUNIT_GPU_STATUS_MAX_FREQ_MASK);
> + }
> return rp1;
> }
>
> static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> {
> + struct drm_device *dev = dev_priv->dev;
> u32 val, rpn;
>
> - val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> - rpn = (val >> PUNIT_GPU
Re: [Intel-gfx] [PATCH] drm/i915: Don't cleanup plane state in intel_plane_destroy()
On Fri, 16 Jan 2015, Matt Roper wrote:
> When we transitioned to the atomic plane helpers in commit:
>
> commit ea2c67bb4affa84080c616920f3899f123786e56
> Author: Matt Roper
> Date: Tue Dec 23 10:41:52 2014 -0800
>
> drm/i915: Move to atomic plane helpers (v9)
>
> one of the changes was to call intel_plane_destroy_state() while tearing
> down a plane to prevent leaks when unloading the driver. That made
> sense when the patches were first written, but before they were merged,
>
> commit 3009c0377f25c29852b218a6933a969d02cbdc5d
> Author: Thierry Reding
> Date: Tue Nov 25 12:09:49 2014 +0100
>
> drm: Free atomic state during cleanup
>
> had already landed, which made this the responsibility of the DRM core.
> The result was that we were kfree()'ing the state twice, and also
> possibly double-unref'ing a framebuffer, leading to memory corruption
> when the driver was unloaded.
>
> The fix is to simply not try to cleanup the state in the i915 teardown
> code now that the core handles this for us.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88433
> Testcase: igt/drv_module_reload
> Root-cause-analysis-by: Ander Conselvan de Oliveira
Thanked-by-and-good-weekend-wished-by-and-
Reviewed-by: Jani Nikula
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_display.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 91d8ada..cc3b9d8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11937,7 +11937,6 @@ static void intel_finish_crtc_commit(struct drm_crtc
> *crtc)
> void intel_plane_destroy(struct drm_plane *plane)
> {
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - intel_plane_destroy_state(plane, plane->state);
> drm_plane_cleanup(plane);
> kfree(intel_plane);
> }
> --
> 1.8.5.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 0/2] Power well support for SKL
Those two patches implement power support for SKL. Patch 1 is already reviewed. For the moment we don't do anything fancy with the AUX power domain, so the series has no real impact on current hardware to ease its inclusion in 3.20. -- Damien Satheeshakrishna M (2): drm/i915/skl: Adding power domains for AUX controllers drm/i915/skl: Implementation of SKL display power well support drivers/gpu/drm/i915/i915_debugfs.c | 8 ++ drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_reg.h | 20 +++ drivers/gpu/drm/i915/intel_runtime_pm.c | 245 4 files changed, 277 insertions(+) -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/skl: Adding power domains for AUX controllers
From: Satheeshakrishna M
Adding new power doamins for AUX controllers
v2: Added new power domains in power_domain_str per Imre's comment
v3: Added AUX power domains to older platforms
v4: Rebase on top of POWER_DOMAIN_PLLS.
v5: Modified to address review comments from Imre
Reviewed-by: Imre Deak
Signed-off-by: Satheeshakrishna M
Signed-off-by: Damien Lespiau (v3)
Signed-off-by: Daniel Vetter
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_debugfs.c | 8
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_runtime_pm.c | 15 +++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e515aad..aac6126 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2397,6 +2397,14 @@ static const char *power_domain_str(enum
intel_display_power_domain domain)
return "AUDIO";
case POWER_DOMAIN_PLLS:
return "PLLS";
+ case POWER_DOMAIN_AUX_A:
+ return "AUX_A";
+ case POWER_DOMAIN_AUX_B:
+ return "AUX_B";
+ case POWER_DOMAIN_AUX_C:
+ return "AUX_C";
+ case POWER_DOMAIN_AUX_D:
+ return "AUX_D";
case POWER_DOMAIN_INIT:
return "INIT";
default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66f0c60..a4d026d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -184,6 +184,10 @@ enum intel_display_power_domain {
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
POWER_DOMAIN_PLLS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_AUX_D,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8bf7bb4..49695d7 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -703,6 +703,10 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) |\
BIT(POWER_DOMAIN_PLLS) |\
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
+ BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
#define HSW_DISPLAY_POWER_DOMAINS (\
(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |\
@@ -724,24 +728,30 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) |\
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_PIPE_A_POWER_DOMAINS ( \
@@ -761,20 +771,25 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER
[Intel-gfx] [PATCH 2/2] drm/i915/skl: Implementation of SKL display power well support
From: Satheeshakrishna M
This patch implements core logic of SKL display power well.
v2: Addressed Imre's comments
- Added respective DDIs under power well #1 and #2
- Simplified repetitive code in power well programming
v3: Implemented Imre's comments
- Further simplified power well programming
- Made sure that PW 1 is enabled prior to PW 2
v4: Fix minor conflict with the the cherryview support (Damien)
v5: Add the PLL power domain to the always on power well (Damien)
v6: Disable BIOS power well (Imre)
Use power well data for comparison (Imre)
Put the PLL power domain into PW1 as its needed for CDCLK (Satheesh,
Damien)
v7: Addressed Imre's comments
- Lowered the time out to 1ms
- Added parantheses in macro
- Moved debug message and fixed wait_for interval
v8:
- Add a WARN() when swiching on an unknown power well (Imre, done by Damien)
- Whitespace fixes (spaces instead of tabs) (Damien)
v9: (Imre, done by Damien)
- Merge the register definitions with this patch
- Merge the MISC IO power well in this patch
Signed-off-by: Satheeshakrishna M (v3,v6,v7)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_reg.h | 20 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 230
2 files changed, 250 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a39bb03..cb96041 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -586,6 +586,19 @@ enum punit_power_well {
PUNIT_POWER_WELL_NUM,
};
+enum skl_disp_power_wells {
+ SKL_DISP_PW_MISC_IO,
+ SKL_DISP_PW_DDI_A_E,
+ SKL_DISP_PW_DDI_B,
+ SKL_DISP_PW_DDI_C,
+ SKL_DISP_PW_DDI_D,
+ SKL_DISP_PW_1 = 14,
+ SKL_DISP_PW_2,
+};
+
+#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
+#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
+
#define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
@@ -6323,6 +6336,13 @@ enum punit_power_well {
#define HSW_PWR_WELL_FORCE_ON(1<<19)
#define HSW_PWR_WELL_CTL6 0x45414
+/* SKL Fuse Status */
+#define SKL_FUSE_STATUS0x42000
+#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
+#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
+#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
+#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
+
/* Per-pipe DDI Function Control */
#define TRANS_DDI_FUNC_CTL_A 0x60400
#define TRANS_DDI_FUNC_CTL_B 0x61400
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 49695d7..d72ec13 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -230,6 +230,146 @@ static void hsw_set_power_well(struct drm_i915_private
*dev_priv,
}
}
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (\
+ BIT(POWER_DOMAIN_PIPE_B) | \
+ BIT(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT(POWER_DOMAIN_PIPE_C) | \
+ BIT(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
+ BIT(POWER_DOMAIN_AUX_D) | \
+ BIT(POWER_DOMAIN_AUDIO) | \
+ BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (\
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_PLLS) |\
+ BIT(POWER_DOMAIN_PIPE_A) | \
+ BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
+ BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (\
+ BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_D
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Starting with Cherryview, devices may have a varying number of EU for
> a given ID due to creative fusing. Punit support different frequency for
> different fuse data. We use this patch to help get total eu enabled and
> read the right offset to get RP0
>
> Based upon a patch from Jeff, but reworked to only store eu_total and
> avoid sending info to userspace
>
> v2: Format register definitions (Jani)
>
> Signed-off-by: Deepak S
> Signed-off-by: Jeff McGee
> ---
> drivers/gpu/drm/i915/i915_dma.c | 11 +++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 2447de3..b868e9d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct
> drm_device *dev)
> info->num_pipes = 0;
> }
> }
> +
> + if (IS_CHERRYVIEW(dev)) {
> + u32 fuse, mask_eu;
> +
> + fuse = I915_READ(CHV_FUSE_GT);
> + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> + CHV_FGT_EU_DIS_SS0_R1_MASK |
> + CHV_FGT_EU_DIS_SS1_R0_MASK |
> + CHV_FGT_EU_DIS_SS1_R1_MASK);
> + info->eu_total = 16 - hweight32(mask_eu);
> + }
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 66f0c60..ab1fa9e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -653,6 +653,7 @@ struct intel_device_info {
> int trans_offsets[I915_MAX_TRANSCODERS];
> int palette_offsets[I915_MAX_PIPES];
> int cursor_offsets[I915_MAX_PIPES];
> + unsigned int eu_total;
> };
>
> #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a39bb03..d9692f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1471,6 +1471,17 @@ enum punit_power_well {
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
>
> +/* Fuse readout registers for GT */
> +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
> +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT16
> +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
> +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT20
> +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
> +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT24
> +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
> +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT28
> +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
> +
> #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> --
> 1.9.1
>
Looks good to me. I'm trying to get the full version of this upstreamed,
but this version is likely to be accepted first. I'll rebase the user
space export portions on it if needed.
-Jeff
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[Intel-gfx] [PATCH] drm/i915: Don't cleanup plane state in intel_plane_destroy()
When we transitioned to the atomic plane helpers in commit:
commit ea2c67bb4affa84080c616920f3899f123786e56
Author: Matt Roper
Date: Tue Dec 23 10:41:52 2014 -0800
drm/i915: Move to atomic plane helpers (v9)
one of the changes was to call intel_plane_destroy_state() while tearing
down a plane to prevent leaks when unloading the driver. That made
sense when the patches were first written, but before they were merged,
commit 3009c0377f25c29852b218a6933a969d02cbdc5d
Author: Thierry Reding
Date: Tue Nov 25 12:09:49 2014 +0100
drm: Free atomic state during cleanup
had already landed, which made this the responsibility of the DRM core.
The result was that we were kfree()'ing the state twice, and also
possibly double-unref'ing a framebuffer, leading to memory corruption
when the driver was unloaded.
The fix is to simply not try to cleanup the state in the i915 teardown
code now that the core handles this for us.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88433
Testcase: igt/drv_module_reload
Root-cause-analysis-by: Ander Conselvan de Oliveira
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91d8ada..cc3b9d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11937,7 +11937,6 @@ static void intel_finish_crtc_commit(struct drm_crtc
*crtc)
void intel_plane_destroy(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
- intel_plane_destroy_state(plane, plane->state);
drm_plane_cleanup(plane);
kfree(intel_plane);
}
--
1.8.5.1
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[Intel-gfx] [PATCH v2 2/3] drm/i915: Increase the range of sideband address.
From: Deepak S
Looks like latest BSW/CHV production system has sideband address > 128.
Use u32 data types to cover new offset/address range :)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ab1fa9e..272088c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3130,8 +3130,8 @@ int sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u32 mbox, u32 *val
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32
val);
/* intel_sideband.c */
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
-void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
+void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 01d841e..3c42eef 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv,
u32 devfn,
return 0;
}
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
{
u32 val = 0;
@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
return val;
}
-void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
{
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
--
1.9.1
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[Intel-gfx] [PATCH v2 3/3] drm/i915: New offset for reading frequencies on CHV.
From: Deepak S
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_pm.c | 53 ++---
2 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9692f9..2dcb1b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -605,6 +605,15 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
+#define FB_GFX_FREQ_FUSE_MASK 0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2..c010d5c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4338,11 +4338,32 @@ void gen6_update_ring_freq(struct drm_device *dev)
static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp0;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+
+ switch (INTEL_INFO(dev)->eu_total) {
+ case 8:
+ /* (2 * 4) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
+ case 12:
+ /* (2 * 6) config */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
+ case 16:
+ /* (2 * 8) config */
+ default:
+ /* Setting (2 * 8) Min RP0 for any other
combination */
+ rp0 = (val >>
FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
+ }
+ rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+ }
return rp0;
}
@@ -4358,20 +4379,36 @@ static int cherryview_rps_rpe_freq(struct
drm_i915_private *dev_priv)
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rp1;
- val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+ rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
+ } else {
+ /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_MAX_FREQ_MASK);
+ }
return rp1;
}
static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv->dev;
u32 val, rpn;
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+ if (dev->pdev->revision >= 0x20) {
+ val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
+ rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
+ FB_GFX_FREQ_FUSE_MASK);
+ } else { /* For pre-production hardware */
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
+ PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
+ }
+
return rpn;
}
--
1.9.1
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[Intel-gfx] [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
From: Deepak S
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store eu_total and
avoid sending info to userspace
v2: Format register definitions (Jani)
Signed-off-by: Deepak S
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_dma.c | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 11 +++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2447de3..b868e9d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
info->num_pipes = 0;
}
}
+
+ if (IS_CHERRYVIEW(dev)) {
+ u32 fuse, mask_eu;
+
+ fuse = I915_READ(CHV_FUSE_GT);
+ mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK |
+ CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+ info->eu_total = 16 - hweight32(mask_eu);
+ }
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66f0c60..ab1fa9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -653,6 +653,7 @@ struct intel_device_info {
int trans_offsets[I915_MAX_TRANSCODERS];
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
+ unsigned int eu_total;
};
#undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a39bb03..d9692f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1471,6 +1471,17 @@ enum punit_power_well {
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12)
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
+/* Fuse readout registers for GT */
+#define CHV_FUSE_GT(VLV_DISPLAY_BASE + 0x2168)
+#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
+#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
+#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
+#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
+#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
+#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
+#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
+#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL0x12050
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
--
1.9.1
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[Intel-gfx] [PATCH v2 0/3] Use new turbo offset for chv production system
From: Deepak S CHV/BSW production system has new turbo offset to read different freq. This series adds the support. Deepak S (3): drm/i915/chv: Populate total EU count on Cherryview drm/i915: Increase the range of sideband address. drm/i915: New offset for reading frequencies on CHV. drivers/gpu/drm/i915/i915_dma.c | 11 drivers/gpu/drm/i915/i915_drv.h | 5 ++-- drivers/gpu/drm/i915/i915_reg.h | 20 + drivers/gpu/drm/i915/intel_pm.c | 53 +-- drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 5 files changed, 81 insertions(+), 12 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Enabling PSR on Skylake
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5591 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 353/353 352/353 ILK 353/353 353/353 SNB 400/422 400/422 IVB 487/487 487/487 BYT 296/296 296/296 HSW +20-8 487/508 499/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gen3_render_linear_blits PASS(2, M25M23) CRASH(1, M23) *HSW igt_kms_cursor_crc_cursor-size-change NSPT(1, M19)TIMEOUT(1, M40)PASS(1, M20) PASS(1, M40) *HSW igt_kms_fence_pin_leak NSPT(1, M19)DMESG_WARN(1, M40)PASS(1, M20) PASS(1, M40) HSW igt_kms_flip_dpms-vs-vblank-race DMESG_WARN(2, M20M40)PASS(1, M19) DMESG_WARN(1, M40) HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset DMESG_WARN(1, M40)PASS(2, M19M20) DMESG_WARN(1, M40) *HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M19)TIMEOUT(1, M40)PASS(1, M20) PASS(1, M40) *HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M19)TIMEOUT(1, M40)PASS(1, M20) FAIL(1, M40) *HSW igt_kms_plane_plane-panning-top-left-pipe-B-plane-1 TIMEOUT(1, M40)PASS(1, M19) DMESG_FAIL(1, M40) HSW igt_kms_plane_plane-panning-top-left-pipe-C-plane-1 TIMEOUT(1, M40)PASS(1, M19) TIMEOUT(1, M40) *HSW igt_pm_lpsp_non-edp NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_cursor NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_cursor-dpms NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_dpms-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_drm-resources-equal NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_fences NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_fences-dpms NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_gem-execbuf NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_gem-mmap-cpu NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_gem-mmap-gtt NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_gem-pread NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_i2c NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_modeset-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_pci-d3-state NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_pm_rpm_rte NSPT(1, M19)PASS(1, M20) PASS(1, M40) *HSW igt_kms_flip_absolute-wf_vblank-interruptible PASS(1, M19) DMESG_WARN(1, M40) *HSW igt_kms_flip_blocking-absolute-wf_vblank PASS(1, M19) DMESG_WARN(1, M40) *HSW igt_kms_flip_plain-flip-fb-recreate PASS(1, M19) DMESG_WARN(1, M40) *HSW igt_kms_flip_plain-flip-ts-check-interruptible PASS(1, M19) DMESG_WARN(1, M40) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 11/12] drm/i915/dsi: move dpi_send_cmd() to intel_dsi.c and make it static
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 39 ++--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 34 ---
drivers/gpu/drm/i915/intel_dsi_cmd.h | 5 -
3 files changed, 37 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5cfa3431785a..791d90b4c047 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -202,6 +202,41 @@ static struct intel_dsi_host *intel_dsi_host_init(struct
intel_dsi *intel_dsi,
return host;
}
+/*
+ * send a video mode command
+ *
+ * XXX: commands with data in MIPI_DPI_DATA?
+ */
+static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
+ enum port port)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 mask;
+
+ /* XXX: pipe, hs */
+ if (hs)
+ cmd &= ~DPI_LP_MODE;
+ else
+ cmd |= DPI_LP_MODE;
+
+ /* clear bit */
+ I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+
+ /* XXX: old code skips write if control unchanged */
+ if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
+ DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+
+ I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
+
+ mask = SPL_PKT_SENT_INTERRUPT;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
+ DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+
+ return 0;
+}
+
static void band_gap_reset(struct drm_i915_private *dev_priv)
{
mutex_lock(&dev_priv->dpio_lock);
@@ -357,7 +392,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
else {
msleep(20); /* XXX */
for_each_dsi_port(port, intel_dsi->ports)
- dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port);
+ dpi_send_cmd(intel_dsi, TURN_ON, false, port);
msleep(100);
drm_panel_enable(intel_dsi->panel);
@@ -430,7 +465,7 @@ static void intel_dsi_pre_disable(struct intel_encoder
*encoder)
if (is_vid_mode(intel_dsi)) {
/* Send Shutdown command to the panel in LP mode */
for_each_dsi_port(port, intel_dsi->ports)
- dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port);
+ dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
msleep(10);
}
}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 6baaa374fc89..acdc5da7b46f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -115,37 +115,3 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool
enable,
intel_dsi->hs = enable;
}
-
-/*
- * send a video mode command
- *
- * XXX: commands with data in MIPI_DPI_DATA?
- */
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port)
-{
- struct drm_encoder *encoder = &intel_dsi->base.base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- u32 mask;
-
- /* XXX: pipe, hs */
- if (hs)
- cmd &= ~DPI_LP_MODE;
- else
- cmd |= DPI_LP_MODE;
-
- /* clear bit */
- I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
-
- /* XXX: old code skips write if control unchanged */
- if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
- DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
-
- I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
-
- mask = SPL_PKT_SENT_INTERRUPT;
- if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
- DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
-
- return 0;
-}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h
b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 9a28ff58a92b..886779030f1a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -33,12 +33,7 @@
#include "intel_drv.h"
#include "intel_dsi.h"
-#define DPI_LP_MODE_EN false
-#define DPI_HS_MODE_EN true
-
void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
enum port port);
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port
port);
-
#endif /* _INTEL_DSI_DSI_H */
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 12/12] drm/i915/dsi: remove intel_dsi_cmd.c and the unused functions therein
The removed functions can be resurrected in intel_dsi.c as need arises.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/intel_dsi.c | 1 -
drivers/gpu/drm/i915/intel_dsi_cmd.c | 117 -
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 1 -
4 files changed, 120 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 16e3dc350274..63afe63bf0e4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -71,7 +71,6 @@ i915-y += dvo_ch7017.o \
intel_ddi.o \
intel_dp.o \
intel_dp_mst.o \
- intel_dsi_cmd.o \
intel_dsi.o \
intel_dsi_pll.o \
intel_dsi_panel_vbt.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 791d90b4c047..02ae5e583b27 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -33,7 +33,6 @@
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
-#include "intel_dsi_cmd.h"
static const struct {
u16 panel_id;
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
deleted file mode 100644
index acdc5da7b46f..
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright © 2013 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Author: Jani Nikula
- */
-
-#include
-#include
-#include
-#include
-#include "i915_drv.h"
-#include "intel_drv.h"
-#include "intel_dsi.h"
-#include "intel_dsi_cmd.h"
-
-/*
- * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
- * MIPI_COMMAND_ADDRESS registers.
- *
- * Apparently these registers provide a MIPI adapter level way to send (lots
of)
- * commands and data to the receiver, without having to write the commands and
- * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
- *
- * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
- * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
- * framebuffer in command mode displays) these are just an optimization that
can
- * come later.
- *
- * For memory writes, these should probably be used for performance.
- */
-
-static void print_stat(struct intel_dsi *intel_dsi, enum port port)
-{
- struct drm_encoder *encoder = &intel_dsi->base.base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- u32 val;
-
- val = I915_READ(MIPI_INTR_STAT(port));
-
-#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
- DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x"
-
"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
- "\n", port_name(port), val,
- STAT_BIT(val, TEARING_EFFECT),
- STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
- STAT_BIT(val, GEN_READ_DATA_AVAIL),
- STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
- STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
- STAT_BIT(val, RX_PROT_VIOLATION),
- STAT_BIT(val, RX_INVALID_TX_LENGTH),
- STAT_BIT(val, ACK_WITH_NO_ERROR),
- STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
- STAT_BIT(val, LP_RX_TIMEOUT),
- STAT_BIT(val, HS_TX_TIMEOUT),
- STAT_BIT(val, DPI_FIFO_UNDERRUN),
- STAT_BIT(val, LOW_CONTENTION),
- STAT_BIT(val, HIGH_CONTENTION),
- STAT_BIT(val, TXDSI_VC_ID_INVALID),
- STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
- STAT_BIT(val, TXCHECKSUM_ERROR),
[Intel-gfx] [RFC PATCH 09/12] drm/i915/dsi: make the vbt panel driver use mipi_dsi_device for transfers
Use the drm core interfaces in preparation of removing our homebrew.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 52 +++---
1 file changed, 34 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index e363c26a2b05..0b09e66f7e29 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -113,14 +113,18 @@ static inline enum port intel_dsi_seq_port_to_port(u8
port)
static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
const u8 *data)
{
- u8 type, byte, mode, vc, seq_port;
+ struct mipi_dsi_device *dsi_device;
+ u8 type, flags, seq_port;
u16 len;
enum port port;
- byte = *data++;
- mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
- vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
- seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
+ flags = *data++;
+ type = *data++;
+
+ len = *((u16 *) data);
+ data += 2;
+
+ seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
/* For DSI single link on Port A & C, the seq_port value which is
* parsed from Sequence Block#53 of VBT has been set to 0
@@ -131,24 +135,29 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi
*intel_dsi,
port = PORT_C;
else
port = intel_dsi_seq_port_to_port(seq_port);
- /* LP or HS mode */
- intel_dsi->hs = mode;
- /* get packet type and increment the pointer */
- type = *data++;
+ dsi_device = intel_dsi->dsi_hosts[port]->device;
+ if (!dsi_device) {
+ DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
+ goto out;
+ }
- len = *((u16 *) data);
- data += 2;
+ if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
+ dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
+ else
+ dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
+
+ dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
switch (type) {
case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
- dsi_vc_generic_write_0(intel_dsi, vc, port);
+ mipi_dsi_generic_write(dsi_device, NULL, 0);
break;
case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
- dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
+ mipi_dsi_generic_write(dsi_device, data, 1);
break;
case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
- dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
+ mipi_dsi_generic_write(dsi_device, data, 2);
break;
case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
@@ -156,22 +165,23 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi
*intel_dsi,
DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
break;
case MIPI_DSI_GENERIC_LONG_WRITE:
- dsi_vc_generic_write(intel_dsi, vc, data, len, port);
+ mipi_dsi_generic_write(dsi_device, data, len);
break;
case MIPI_DSI_DCS_SHORT_WRITE:
- dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
+ mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
break;
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
- dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
+ mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
break;
case MIPI_DSI_DCS_READ:
DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
break;
case MIPI_DSI_DCS_LONG_WRITE:
- dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
+ mipi_dsi_dcs_write_buffer(dsi_device, data, len);
break;
}
+out:
data += len;
return data;
@@ -389,6 +399,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
*intel_dsi, u16 panel_id)
u32 lp_to_hs_switch, hs_to_lp_switch;
u32 pclk, computed_ddr;
u16 burst_mode_ratio;
+ enum port port;
DRM_DEBUG_KMS("\n");
@@ -661,5 +672,10 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
*intel_dsi, u16 panel_id)
vbt_panel->panel.funcs = &vbt_panel_funcs;
drm_panel_add(&vbt_panel->panel);
+ /* a regular driver would get the device in probe */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
+ }
+
return &vbt_panel->panel;
}
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 08/12] drm/i915/dsi: add drm mipi dsi host support
Add basic support for using the drm mipi dsi framework for DSI. We don't
use device tree which is pretty much required by mipi_dsi_host_register
and friends, and we don't have the kind of device model the functions
expect either. So we cheat and use it as a library to abstract what we
need: a nice, clean interface for DSI transfers. This means we will have
to be careful with what functions we call, as the driver model devices
in mipi_dsi_host and mipi_dsi_device will *not* be initialized.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 162 -
drivers/gpu/drm/i915/intel_dsi.h | 18
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 3 -
4 files changed, 180 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index da196cd07263..74acca9bcd9d 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -12,6 +12,7 @@ config DRM_I915
select TMPFS
select DRM_KMS_HELPER
select DRM_PANEL
+ select DRM_MIPI_DSI
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
select BACKLIGHT_LCD_SUPPORT if ACPI
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 19a9955eab0e..5cfa3431785a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include "i915_drv.h"
#include "intel_drv.h"
@@ -58,6 +59,149 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi, enum port port)
DRM_ERROR("DPI FIFOs are not empty\n");
}
+static void write_data(struct drm_i915_private *dev_priv, u32 reg,
+ const u8 *data, u32 len)
+{
+ u32 i, j;
+
+ for (i = 0; i < len; i += 4) {
+ u32 val = 0;
+
+ for (j = 0; j < min_t(u32, len - i, 4); j++)
+ val |= *data++ << 8 * j;
+
+ I915_WRITE(reg, val);
+ }
+}
+
+static void read_data(struct drm_i915_private *dev_priv, u32 reg,
+ u8 *data, u32 len)
+{
+ u32 i, j;
+
+ for (i = 0; i < len; i += 4) {
+ u32 val = I915_READ(reg);
+
+ for (j = 0; j < min_t(u32, len - i, 4); j++)
+ *data++ = val >> 8 * j;
+ }
+}
+
+static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
+ const struct mipi_dsi_msg *msg)
+{
+ struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+ struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum port port = intel_dsi_host->port;
+ struct mipi_dsi_packet packet;
+ ssize_t ret;
+ const u8 *header, *data;
+ u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
+
+ ret = mipi_dsi_create_packet(&packet, msg);
+ if (ret < 0)
+ return ret;
+
+ header = packet.header;
+ data = packet.payload;
+
+ if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
+ data_reg = MIPI_LP_GEN_DATA(port);
+ data_mask = LP_DATA_FIFO_FULL;
+ ctrl_reg = MIPI_LP_GEN_CTRL(port);
+ ctrl_mask = LP_CTRL_FIFO_FULL;
+ } else {
+ data_reg = MIPI_HS_GEN_DATA(port);
+ data_mask = HS_DATA_FIFO_FULL;
+ ctrl_reg = MIPI_HS_GEN_CTRL(port);
+ ctrl_mask = HS_CTRL_FIFO_FULL;
+ }
+
+ /* note: this is never true for reads */
+ if (packet.payload_length) {
+
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask)
== 0, 50))
+ DRM_ERROR("Timeout waiting for HS/LP DATA FIFO
!full\n");
+
+ write_data(dev_priv, data_reg, packet.payload,
+ packet.payload_length);
+ }
+
+ if (msg->rx_len) {
+ I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
+ }
+
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0,
50)) {
+ DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
+ }
+
+ I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
+
+ /* ->rx_len is set only for reads */
+ if (msg->rx_len) {
+ data_mask = GEN_READ_DATA_AVAIL;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) ==
data_mask, 50))
+ DRM_ERROR("Timeout waiting for read data.\n");
+
+ read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
+ }
+
+ /* XXX: fix for reads and writes */
+ return 4 + packet.payload_length;
+}
+
+static int intel_dsi_host_attach(struct mipi_dsi_host *host,
+
[Intel-gfx] [RFC PATCH 05/12] drm/i915/dsi: remove unnecessary dsi device callbacks
Remove all the trivial and/or dummy callbacks from intel dsi device
ops. Merge send_otp_cmds into panel_reset as they're called back to
back.
This will be helpful for switching to use drm_panel for the
callbacks. If we ever need the additional callbacks, we should add them
to drm_panel funcs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 32 ++---
drivers/gpu/drm/i915/intel_dsi.h | 20 -
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++
3 files changed, 5 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9b0eaa9db845..fc218b7754b3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -70,12 +70,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->dpio_lock);
}
-static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
-{
- return container_of(intel_attached_encoder(connector),
- struct intel_dsi, base);
-}
-
static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
{
return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
@@ -99,7 +93,6 @@ static bool intel_dsi_compute_config(struct intel_encoder
*encoder,
struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
- struct drm_display_mode *mode = &config->requested_mode;
DRM_DEBUG_KMS("\n");
@@ -109,10 +102,6 @@ static bool intel_dsi_compute_config(struct intel_encoder
*encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI
*/
adjusted_mode->flags = 0;
- if (intel_dsi->dev.dev_ops->mode_fixup)
- return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
- mode, adjusted_mode);
-
return true;
}
@@ -269,9 +258,6 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
- if (intel_dsi->dev.dev_ops->send_otp_cmds)
- intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
-
for_each_dsi_port(port, intel_dsi->ports)
wait_for_dsi_fifo_empty(intel_dsi, port);
@@ -484,7 +470,6 @@ intel_dsi_mode_valid(struct drm_connector *connector,
{
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
DRM_DEBUG_KMS("\n");
@@ -500,7 +485,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
return MODE_PANEL;
}
- return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
+ return MODE_OK;
}
/* return txclkesc cycles in terms of divider and duration in us */
@@ -749,20 +734,7 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder)
static enum drm_connector_status
intel_dsi_detect(struct drm_connector *connector, bool force)
{
- struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
- struct intel_encoder *intel_encoder = &intel_dsi->base;
- enum intel_display_power_domain power_domain;
- enum drm_connector_status connector_status;
- struct drm_i915_private *dev_priv =
intel_encoder->base.dev->dev_private;
-
- DRM_DEBUG_KMS("\n");
- power_domain = intel_display_port_power_domain(intel_encoder);
-
- intel_display_power_get(dev_priv, power_domain);
- connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
- intel_display_power_put(dev_priv, power_domain);
-
- return connector_status;
+ return connector_status_connected;
}
static int intel_dsi_get_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2bb8c46c7889..22f87036a256 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -47,33 +47,13 @@ struct intel_dsi_dev_ops {
void (*disable_panel_power)(struct intel_dsi_device *dsi);
- /* one time programmable commands if needed */
- void (*send_otp_cmds)(struct intel_dsi_device *dsi);
-
/* This callback must be able to assume DSI commands can be sent */
void (*enable)(struct intel_dsi_device *dsi);
/* This callback must be able to assume DSI commands can be sent */
void (*disable)(struct intel_dsi_device *dsi);
- int (*mode_valid)(struct intel_dsi_device *dsi,
- struct drm_display_mode *mode);
-
- bool (*mode_fixup)(stru
[Intel-gfx] [RFC PATCH 07/12] drm/i915/dsi: switch to drm_panel interface
Replace intel_dsi_device and intel_dsi_dev_ops with drm_panel and
drm_panel_funcs. They are adequate for what we have now, and if we end
up needing more than this we should improve drm_panel. This will keep us
better aligned with the drm core infrastructure.
The panel driver initialization changes a bit. It still remains hideous,
but fixing that is beyond the scope here.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 68 +++
drivers/gpu/drm/i915/intel_dsi.h | 27 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 179 ++---
4 files changed, 156 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 4e39ab34eb1c..da196cd07263 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -11,6 +11,7 @@ config DRM_I915
select SHMEM
select TMPFS
select DRM_KMS_HELPER
+ select DRM_PANEL
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
select BACKLIGHT_LCD_SUPPORT if ACPI
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fc218b7754b3..19a9955eab0e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -27,18 +27,20 @@
#include
#include
#include
+#include
#include
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
#include "intel_dsi_cmd.h"
-/* the sub-encoders aka panel drivers */
-static const struct intel_dsi_device intel_dsi_devices[] = {
+static const struct {
+ u16 panel_id;
+ struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
+} intel_dsi_drivers[] = {
{
.panel_id = MIPI_DSI_GENERIC_PANEL_ID,
- .name = "vbt-generic-dsi-vid-mode-display",
- .dev_ops = &vbt_generic_dsi_display_ops,
+ .init = vbt_panel_init,
},
};
@@ -214,8 +216,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port);
msleep(100);
- if (intel_dsi->dev.dev_ops->enable)
- intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
+ drm_panel_enable(intel_dsi->panel);
for_each_dsi_port(port, intel_dsi->ports)
wait_for_dsi_fifo_empty(intel_dsi, port);
@@ -255,8 +256,7 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
msleep(intel_dsi->panel_on_delay);
- if (intel_dsi->dev.dev_ops->panel_reset)
- intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
+ drm_panel_prepare(intel_dsi->panel);
for_each_dsi_port(port, intel_dsi->ports)
wait_for_dsi_fifo_empty(intel_dsi, port);
@@ -329,8 +329,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
}
/* if disable packets are sent before sending shutdown packet then in
* some next enable sequence send turn on packet error is observed */
- if (intel_dsi->dev.dev_ops->disable)
- intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
+ drm_panel_disable(intel_dsi->panel);
for_each_dsi_port(port, intel_dsi->ports)
wait_for_dsi_fifo_empty(intel_dsi, port);
@@ -395,8 +394,7 @@ static void intel_dsi_post_disable(struct intel_encoder
*encoder)
val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, val);
- if (intel_dsi->dev.dev_ops->disable_panel_power)
- intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
+ drm_panel_unprepare(intel_dsi->panel);
msleep(intel_dsi->panel_off_delay);
msleep(intel_dsi->panel_pwr_cycle_delay);
@@ -760,7 +758,7 @@ static int intel_dsi_get_modes(struct drm_connector
*connector)
return 1;
}
-static void intel_dsi_destroy(struct drm_connector *connector)
+static void intel_dsi_connector_destroy(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -770,8 +768,20 @@ static void intel_dsi_destroy(struct drm_connector
*connector)
kfree(connector);
}
+static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+
+ if (intel_dsi->panel) {
+ drm_panel_detach(intel_dsi->panel);
+ /* XXX: Logically this call belongs in the panel driver. */
+ drm_panel_remove(intel_dsi->panel);
+ }
+ intel_encoder_destroy(encoder);
+}
+
static const struct drm_encoder_funcs intel_dsi_funcs = {
- .destroy = intel_encoder_destroy,
+ .destroy = intel_dsi_encoder_destroy,
};
static const struct drm_connector_helper_funcs
i
[Intel-gfx] [RFC PATCH 10/12] drm/i915/dsi: remove old read/write functions in favor of new stuff
All of these are replaced by the drm core mipi dsi functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 259 ---
drivers/gpu/drm/i915/intel_dsi_cmd.h | 72 --
2 files changed, 331 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 17b892a365ee..6baaa374fc89 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -96,11 +96,6 @@ static void print_stat(struct intel_dsi *intel_dsi, enum
port port)
#undef STAT_BIT
}
-enum dsi_type {
- DSI_DCS,
- DSI_GENERIC,
-};
-
/* enable or disable command mode hs transmissions */
void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
enum port port)
@@ -121,260 +116,6 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool
enable,
intel_dsi->hs = enable;
}
-static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
-u8 data_type, u16 data, enum port port)
-{
- struct drm_encoder *encoder = &intel_dsi->base.base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- u32 ctrl_reg;
- u32 ctrl;
- u32 mask;
-
- DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
- channel, data_type, data);
-
- if (intel_dsi->hs) {
- ctrl_reg = MIPI_HS_GEN_CTRL(port);
- mask = HS_CTRL_FIFO_FULL;
- } else {
- ctrl_reg = MIPI_LP_GEN_CTRL(port);
- mask = LP_CTRL_FIFO_FULL;
- }
-
- if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
- DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
- print_stat(intel_dsi, port);
- }
-
- /*
-* Note: This function is also used for long packets, with length passed
-* as data, since SHORT_PACKET_PARAM_SHIFT ==
-* LONG_PACKET_WORD_COUNT_SHIFT.
-*/
- ctrl = data << SHORT_PACKET_PARAM_SHIFT |
- channel << VIRTUAL_CHANNEL_SHIFT |
- data_type << DATA_TYPE_SHIFT;
-
- I915_WRITE(ctrl_reg, ctrl);
-
- return 0;
-}
-
-static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
- u8 data_type, const u8 *data, int len, enum port port)
-{
- struct drm_encoder *encoder = &intel_dsi->base.base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- u32 data_reg;
- int i, j, n;
- u32 mask;
-
- DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
- channel, data_type, len);
-
- if (intel_dsi->hs) {
- data_reg = MIPI_HS_GEN_DATA(port);
- mask = HS_DATA_FIFO_FULL;
- } else {
- data_reg = MIPI_LP_GEN_DATA(port);
- mask = LP_DATA_FIFO_FULL;
- }
-
- if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50))
- DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
-
- for (i = 0; i < len; i += n) {
- u32 val = 0;
- n = min_t(int, len - i, 4);
-
- for (j = 0; j < n; j++)
- val |= *data++ << 8 * j;
-
- I915_WRITE(data_reg, val);
- /* XXX: check for data fifo full, once that is set, write 4
-* dwords, then wait for not set, then continue. */
- }
-
- return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
-}
-
-static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
- int channel, const u8 *data, int len,
- enum dsi_type type, enum port port)
-{
- int ret;
-
- if (len == 0) {
- BUG_ON(type == DSI_GENERIC);
- ret = dsi_vc_send_short(intel_dsi, channel,
- MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
- 0, port);
- } else if (len == 1) {
- ret = dsi_vc_send_short(intel_dsi, channel,
- type == DSI_GENERIC ?
- MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
- MIPI_DSI_DCS_SHORT_WRITE, data[0],
- port);
- } else if (len == 2) {
- ret = dsi_vc_send_short(intel_dsi, channel,
- type == DSI_GENERIC ?
- MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
- MIPI_DSI_DCS_SHORT_WRITE_PARAM,
- (data[1] << 8) | data[0], port);
- } else {
- ret = dsi_vc_send_long(intel_dsi, channel,
-
[Intel-gfx] [RFC PATCH 06/12] drm/i915/dsi: add some constness to vbt panel driver
Const is good for you. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index b0e7327a485f..561ec2981dfd 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -99,7 +99,8 @@ static inline enum port intel_dsi_seq_port_to_port(u8 port)
return port ? PORT_C : PORT_A;
}
-static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
+static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
+ const u8 *data)
{
u8 type, byte, mode, vc, seq_port;
u16 len;
@@ -165,9 +166,9 @@ static u8 *mipi_exec_send_packet(struct intel_dsi
*intel_dsi, u8 *data)
return data;
}
-static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
+static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
{
- u32 delay = *((u32 *) data);
+ u32 delay = *((const u32 *) data);
usleep_range(delay, delay + 10);
data += 4;
@@ -175,7 +176,7 @@ static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8
*data)
return data;
}
-static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
+static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
u8 gpio, action;
u16 function, pad;
@@ -208,7 +209,8 @@ static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8
*data)
return data;
}
-typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
+typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
+ const u8 *data);
static const fn_mipi_elem_exec exec_elem[] = {
NULL, /* reserved */
mipi_exec_send_packet,
@@ -232,13 +234,12 @@ static const char * const seq_name[] = {
"MIPI_SEQ_DEASSERT_RESET"
};
-static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
+static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
{
- u8 *data = sequence;
fn_mipi_elem_exec mipi_elem_exec;
int index;
- if (!sequence)
+ if (!data)
return;
DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 02/12] drm/i915/dsi: set max return packet size for each dsi port
This seems like the right thing to do. This also gets rid of a call to
intel_dsi_pipe_to_port() which we want to remove eventually.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 36b19c7e87b9..49e186bc080f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -197,14 +197,14 @@ static void intel_dsi_enable(struct intel_encoder
*encoder)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+ enum port port;
DRM_DEBUG_KMS("\n");
if (is_cmd_mode(intel_dsi))
- I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
+ for_each_dsi_port(port, intel_dsi->ports)
+ I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
else {
msleep(20); /* XXX */
for_each_dsi_port(port, intel_dsi->ports)
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 03/12] drm/i915/dsi: move wait_for_dsi_fifo_empty to intel_dsi.c
wait_for_dsi_fifo_empty can be static in intel_dsi.c. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 16
drivers/gpu/drm/i915/intel_dsi_cmd.c | 16
drivers/gpu/drm/i915/intel_dsi_cmd.h | 1 -
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 49e186bc080f..e82cf5f65c9a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -42,6 +42,22 @@ static const struct intel_dsi_device intel_dsi_devices[] = {
},
};
+static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
+ u32 mask;
+
+ mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
+ LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
+
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
+ DRM_ERROR("DPI FIFOs are not empty\n");
+}
+
static void band_gap_reset(struct drm_i915_private *dev_priv)
{
mutex_lock(&dev_priv->dpio_lock);
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 5f63c807acea..17b892a365ee 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -408,19 +408,3 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd,
bool hs, enum port port)
return 0;
}
-
-void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
-{
- struct drm_encoder *encoder = &intel_dsi->base.base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
- u32 mask;
-
- mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
- LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
-
- if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
- DRM_ERROR("DPI FIFOs are not empty\n");
-}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h
b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 1d1a716e473a..70f24666a1f9 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -52,7 +52,6 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int
channel,
u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port
port);
-void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
/* XXX: questionable write helpers */
static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 04/12] drm/i915/dsi: call wait_for_dsi_fifo_empty() for each dsi port
Add port parameter to wait_for_dsi_fifo_empty, and call it for each dsi
port.
We can now remove the transitional intel_dsi_pipe_to_port() function.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 17 ++---
drivers/gpu/drm/i915/intel_dsi.h | 12
2 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e82cf5f65c9a..9b0eaa9db845 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -42,13 +42,11 @@ static const struct intel_dsi_device intel_dsi_devices[] = {
},
};
-static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
+static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port
port)
{
struct drm_encoder *encoder = &intel_dsi->base.base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
u32 mask;
mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
@@ -230,7 +228,8 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
if (intel_dsi->dev.dev_ops->enable)
intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
- wait_for_dsi_fifo_empty(intel_dsi);
+ for_each_dsi_port(port, intel_dsi->ports)
+ wait_for_dsi_fifo_empty(intel_dsi, port);
intel_dsi_port_enable(encoder);
}
@@ -243,6 +242,7 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
enum pipe pipe = intel_crtc->pipe;
+ enum port port;
u32 tmp;
DRM_DEBUG_KMS("\n");
@@ -272,7 +272,8 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
if (intel_dsi->dev.dev_ops->send_otp_cmds)
intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
- wait_for_dsi_fifo_empty(intel_dsi);
+ for_each_dsi_port(port, intel_dsi->ports)
+ wait_for_dsi_fifo_empty(intel_dsi, port);
/* Enable port in pre-enable phase itself because as per hw team
* recommendation, port should be enabled befor plane & pipe */
@@ -315,7 +316,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
if (is_vid_mode(intel_dsi)) {
- wait_for_dsi_fifo_empty(intel_dsi);
+ for_each_dsi_port(port, intel_dsi->ports)
+ wait_for_dsi_fifo_empty(intel_dsi, port);
intel_dsi_port_disable(encoder);
msleep(2);
@@ -344,7 +346,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
if (intel_dsi->dev.dev_ops->disable)
intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
- wait_for_dsi_fifo_empty(intel_dsi);
+ for_each_dsi_port(port, intel_dsi->ports)
+ wait_for_dsi_fifo_empty(intel_dsi, port);
}
static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 8fe2064dd804..2bb8c46c7889 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -137,18 +137,6 @@ struct intel_dsi {
u16 panel_pwr_cycle_delay;
};
-/* XXX: Transitional before dual port configuration */
-static inline enum port intel_dsi_pipe_to_port(enum pipe pipe)
-{
- if (pipe == PIPE_A)
- return PORT_A;
- else if (pipe == PIPE_B)
- return PORT_C;
-
- WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe));
- return PORT_C;
-}
-
#define for_each_dsi_port(__port, __ports_mask) \
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
if ((__ports_mask) & (1 << (__port)))
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 01/12] drm/i915/dsi: call dpi_send_cmd() for each dsi port at a higher level
Instead of having the for each dsi port loop within dpi_send_cmd(), add
a port parameter to the function and call it for each port instead.
This is a rewrite of
commit 4510cd779e5897eeb8691aecbd639bb62ec27d55
Author: Gaurav K Singh
Date: Thu Dec 4 10:58:51 2014 +0530
drm/i915: Dual link needs Shutdown and Turn on packet for both ports
to add more flexibility in using dpi_send_cmd() for just one port as
necessary. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 7 +--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 26 ++
drivers/gpu/drm/i915/intel_dsi_cmd.h | 2 +-
3 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 42b6d6f5cecc..36b19c7e87b9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -207,7 +207,8 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
else {
msleep(20); /* XXX */
- dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
+ for_each_dsi_port(port, intel_dsi->ports)
+ dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port);
msleep(100);
if (intel_dsi->dev.dev_ops->enable)
@@ -275,12 +276,14 @@ static void intel_dsi_enable_nop(struct intel_encoder
*encoder)
static void intel_dsi_pre_disable(struct intel_encoder *encoder)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
DRM_DEBUG_KMS("\n");
if (is_vid_mode(intel_dsi)) {
/* Send Shutdown command to the panel in LP mode */
- dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
+ for_each_dsi_port(port, intel_dsi->ports)
+ dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port);
msleep(10);
}
}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 562811c1a9d2..5f63c807acea 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -380,12 +380,11 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int
channel,
*
* XXX: commands with data in MIPI_DPI_DATA?
*/
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port)
{
struct drm_encoder *encoder = &intel_dsi->base.base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum port port;
u32 mask;
/* XXX: pipe, hs */
@@ -394,23 +393,18 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd,
bool hs)
else
cmd |= DPI_LP_MODE;
- for_each_dsi_port(port, intel_dsi->ports) {
- /* clear bit */
- I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+ /* clear bit */
+ I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
- /* XXX: old code skips write if control unchanged */
- if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
- DRM_ERROR("Same special packet %02x twice in a row.\n",
- cmd);
+ /* XXX: old code skips write if control unchanged */
+ if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
+ DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
- I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
+ I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
- mask = SPL_PKT_SENT_INTERRUPT;
- if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
- 100))
- DRM_ERROR("Video mode command 0x%08x send failed.\n",
- cmd);
- }
+ mask = SPL_PKT_SENT_INTERRUPT;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
+ DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h
b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 326a5ac55561..1d1a716e473a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -51,7 +51,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel,
u8 dcs_cmd,
int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port
port);
void wait_for_dsi_fifo_empty(struct intel_dsi *i
[Intel-gfx] [RFC PATCH 00/12] drm/i915: port dsi over to drm panel/dsi frameworks
This series ports our DSI code over to the drm_panel and mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the end of the series, see commit message for patch 8 for details. Patches 1-6 are prep work, fairly independent Patch 7 ports the driver over to drm_panel Patches 8-10 port the driver over to mipi_dsi_host/device Patches 11-12 do some additional cleanup BR, Jani. Jani Nikula (12): drm/i915/dsi: call dpi_send_cmd() for each dsi port at a higher level drm/i915/dsi: set max return packet size for each dsi port drm/i915/dsi: move wait_for_dsi_fifo_empty to intel_dsi.c drm/i915/dsi: call wait_for_dsi_fifo_empty() for each dsi port drm/i915/dsi: remove unnecessary dsi device callbacks drm/i915/dsi: add some constness to vbt panel driver drm/i915/dsi: switch to drm_panel interface drm/i915/dsi: add drm mipi dsi host support drm/i915/dsi: make the vbt panel driver use mipi_dsi_device for transfers drm/i915/dsi: remove old read/write functions in favor of new stuff drm/i915/dsi: move dpi_send_cmd() to intel_dsi.c and make it static drm/i915/dsi: remove intel_dsi_cmd.c and the unused functions therein drivers/gpu/drm/i915/Kconfig | 2 + drivers/gpu/drm/i915/Makefile | 1 - drivers/gpu/drm/i915/intel_dsi.c | 336 +- drivers/gpu/drm/i915/intel_dsi.h | 69 ++--- drivers/gpu/drm/i915/intel_dsi_cmd.c | 432 - drivers/gpu/drm/i915/intel_dsi_cmd.h | 78 -- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 289 ++- 7 files changed, 441 insertions(+), 766 deletions(-) delete mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v2 1/4] drm: Add support to find drm_panel by name
On Tue, Jan 13, 2015 at 12:08:11AM +0100, Daniel Vetter wrote: > On Fri, Jan 9, 2015 at 1:50 PM, Jani Nikula wrote: > > I have a slightly uneasy feeling about handing out drm_panel pointers > > (both from here and of_drm_find_panel) without refcounting. If the panel > > driver gets removed, whoever called the find functions will have a > > dangling pointer. I supposed this will be discussed on drm-devel. > > There's been some discussion already about exactly this problem (but > with drm bridges) with Thierry and some other people. Cc'ed them all > hopefully. Especially when the panel/bridge is a separate driver > there's imo indeed an issue. I posted patches some time ago to create a generic registry to do the actual ref-counting[0]. It didn't seem to be very well received by Greg for the core, so perhaps we could test-drive it in DRM first for panels and bridges and once it's matured a bit it could still be promoted to the driver core, or maybe lib/. The difficult part about it is that while reference counting gives you the benefit of keeping a valid pointer around, you may still want to have a method of getting notified of the panel going away. I've thought a bit about that and I think we could probably integrate that into the registry, since that will notice anyway. Thierry [0]: http://www.spinics.net/linux/lists/kernel/msg1859333.html pgpt2u9WBzrMC.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: Ensure the HiZ RAW Stall Optimization is on for Cherryview.
On Tue, Jan 13, 2015 at 12:46:53PM -0800, Kenneth Graunke wrote: > This is an important optimization for avoiding read-after-write (RAW) > stalls in the HiZ buffer. Certain workloads would run very slowly with > HiZ enabled, but run much faster with the "hiz=false" driconf option. > With this patch, they run at full speed even with HiZ. > > Increases performance in OglVSInstancing by about 2.7x on Braswell. > > Signed-off-by: Kenneth Graunke Reviewed-by: Ville Syrjälä also for the remaining two patches. > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 + > 1 file changed, 5 insertions(+) > > Split, as requested by Ben. > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 0df15a4..23020d6 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs > *ring) > HDC_FORCE_NON_COHERENT | > HDC_DONOT_FETCH_MEM_WHEN_MASKED); > > + /* According to the CACHE_MODE_0 default value documentation, some > + * CHV platforms disable this optimization by default. Turn it on. > + */ > + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > + > /* Improve HiZ throughput on CHV. */ > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); > > -- > 2.2.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915
On Tue, Jan 13, 2015 at 12:48:47AM +0100, Daniel Vetter wrote: > On Fri, Jan 09, 2015 at 02:21:15PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > 915 doens't support hotplug at all, so we shouldn't try to pretend > > otherwise in the SDVO code. > > It actually has a hpd pin, but since it's just one for all ports we > haven't ever used it. You learn something new every day. > Probably would't work well when facing an irq storm. irq storm handling is already pretty hosed for DP++ ports for the same reason. > > I'll augment the commit message jus to clarify. > -Daniel > > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_sdvo.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c > > b/drivers/gpu/drm/i915/intel_sdvo.c > > index 6d7a277..4e3d362 100644 > > --- a/drivers/gpu/drm/i915/intel_sdvo.c > > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > > @@ -1617,6 +1617,9 @@ static uint16_t intel_sdvo_get_hotplug_support(struct > > intel_sdvo *intel_sdvo) > > struct drm_device *dev = intel_sdvo->base.base.dev; > > uint16_t hotplug; > > > > + if (!I915_HAS_HOTPLUG(dev)) > > + return 0; > > + > > /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise > > * on the line. */ > > if (IS_I945G(dev) || IS_I945GM(dev)) > > -- > > 2.0.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915: reuse %ph to dump small buffers
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5588 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 353/353 353/353 SNB -1 400/422 399/422 IVB 487/487 487/487 BYT 296/296 296/296 HSW +21-2 487/508 506/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *SNB igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset PASS(2, M35M22) NSPT(1, M22) HSW igt_kms_cursor_crc_cursor-size-change NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_kms_fence_pin_leak NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_kms_flip_dpms-vs-vblank-race DMESG_WARN(1, M20)PASS(1, M19) DMESG_WARN(1, M20) *HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset PASS(2, M19M20) DMESG_WARN(1, M20) HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_lpsp_non-edp NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_cursor NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_cursor-dpms NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_dpms-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_drm-resources-equal NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_fences NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_fences-dpms NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_gem-execbuf NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_gem-mmap-cpu NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_gem-mmap-gtt NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_gem-pread NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_i2c NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_modeset-non-lpsp NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_pci-d3-state NSPT(1, M19)PASS(1, M20) PASS(1, M20) HSW igt_pm_rpm_rte NSPT(1, M19)PASS(1, M20) PASS(1, M20) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] drm/i915: Untangle execlist tracking
> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Nick Hoath > Sent: Thursday, January 15, 2015 1:11 PM > To: intel-gfx@lists.freedesktop.org > Cc: daniel.vet...@ffwll.ch > Subject: [Intel-gfx] [PATCH 0/4] drm/i915: Untangle execlist tracking > > This patchset merges execlist queue items in to gem requests. It does this by > using the reference count added by the "Replace seqno values with request > structures" patchset to ensure that the gem request is available for the > whole execlist submission lifespan. > > v2: merge intel_ctx_submit_request and drm_i915_gem_request, rebase > changes & >add cover letter > > v3: Rebase over upstreamed "Replace seqno values with request structures" > and add overzealous freeing fix. > > v4: Removed re-addition of cleanup work queue (found by Daniel Vetter) > v5: Fixed non-building individual patch (0002). Separated out the tail pointer > from the postfix pointer (found by Thomas Daniel) > v6: Actual removal of intel_ctx_submit_request. Update both tail and postfix > pointer in __i915_add_request (found by Thomas Daniel) > v7: Removed unrelated changes Well, I'm happy with v7 of this patchset now. Reviewed-by: Thomas Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/9] drm/i915: Reduce duplicated forcewake logic
From: Chris Wilson
Introduce a structure to track the individual forcewake domains and use
that to eliminate duplicate logic.
v2: - Rebase on latest dinq (Mika)
- for_each_fw_domain macro (Mika)
- Handle reset atomically, keeping the timer running (Mika)
- for_each_fw_domain parameter ordering (Chris)
- defer timer on new register access (Mika)
v3: - Fix forcewake_reset/get race by waiting pending timers
v4: - cond_resched and verbose warning on timer deletion (Chris)
- need to run pending timers manually on reset
Signed-off-by: Chris Wilson (v1)
Signed-off-by: Mika Kuoppala
Acked-by: Deepak S (v2)
---
drivers/gpu/drm/i915/i915_debugfs.c | 65 +++---
drivers/gpu/drm/i915/i915_drv.h | 54 +++--
drivers/gpu/drm/i915/intel_uncore.c | 445 +++-
3 files changed, 246 insertions(+), 318 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8bb34a9..65adb62 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1288,14 +1288,36 @@ static int ironlake_drpc_info(struct seq_file *m)
return 0;
}
-static int vlv_drpc_info(struct seq_file *m)
+static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_uncore_forcewake_domain *fw_domain;
+ const char *domain_names[] = {
+ "render",
+ "blitter",
+ "media",
+ };
+ int i;
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ for_each_fw_domain(fw_domain, dev_priv, i) {
+ seq_printf(m, "%s.wake_count = %u\n",
+ domain_names[i],
+ fw_domain->wake_count);
+ }
+ spin_unlock_irq(&dev_priv->uncore.lock);
+ return 0;
+}
+
+static int vlv_drpc_info(struct seq_file *m)
+{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, rcctl1, pw_status;
- unsigned fw_rendercount = 0, fw_mediacount = 0;
intel_runtime_pm_get(dev_priv);
@@ -1327,22 +1349,11 @@ static int vlv_drpc_info(struct seq_file *m)
seq_printf(m, "Media RC6 residency since boot: %u\n",
I915_READ(VLV_GT_MEDIA_RC6));
- spin_lock_irq(&dev_priv->uncore.lock);
- fw_rendercount = dev_priv->uncore.fw_rendercount;
- fw_mediacount = dev_priv->uncore.fw_mediacount;
- spin_unlock_irq(&dev_priv->uncore.lock);
-
- seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
- seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
-
-
- return 0;
+ return i915_gen6_forcewake_count_info(m, NULL);
}
-
static int gen6_drpc_info(struct seq_file *m)
{
-
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1356,7 +1367,7 @@ static int gen6_drpc_info(struct seq_file *m)
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->uncore.lock);
- forcewake_count = dev_priv->uncore.forcewake_count;
+ forcewake_count =
dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
spin_unlock_irq(&dev_priv->uncore.lock);
if (forcewake_count) {
@@ -1984,30 +1995,6 @@ static int i915_execlists(struct seq_file *m, void *data)
return 0;
}
-static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
-{
- struct drm_info_node *node = m->private;
- struct drm_device *dev = node->minor->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
-
- spin_lock_irq(&dev_priv->uncore.lock);
- if (IS_VALLEYVIEW(dev)) {
- fw_rendercount = dev_priv->uncore.fw_rendercount;
- fw_mediacount = dev_priv->uncore.fw_mediacount;
- } else
- forcewake_count = dev_priv->uncore.forcewake_count;
- spin_unlock_irq(&dev_priv->uncore.lock);
-
- if (IS_VALLEYVIEW(dev)) {
- seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
- seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
- } else
- seq_printf(m, "forcewake count = %u\n", forcewake_count);
-
- return 0;
-}
-
static const char *swizzle_string(unsigned swizzle)
{
switch (swizzle) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66f0c60..2615927 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -595,20 +595,45 @@ struct intel_uncore_funcs {
uint64_t val, bool trac
[Intel-gfx] [PATCH 2/9] drm/i915: Assert that runtime pm is active on user fw access
From: Chris Wilson
On user forcewake access, assert that runtime pm reference is held.
Fix and cleanup the callsites accordingly.
v2: Remove intel_runtime_pm_get() rebasehap (Deepak)
v3: use drivers own runtime state tracking as pm_runtime_active()
will return wrong results when we are in resume callchain (Mika)
Signed-off-by: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S (v2)
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +
drivers/gpu/drm/i915/intel_display.c | 19 +
drivers/gpu/drm/i915/intel_lrc.c | 53 ++---
drivers/gpu/drm/i915/intel_uncore.c | 76 +++-
4 files changed, 30 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e515aad..8bb34a9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4335,6 +4335,7 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
if (INTEL_INFO(dev)->gen < 6)
return 0;
+ intel_runtime_pm_get(dev_priv);
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
return 0;
@@ -4349,6 +4350,7 @@ static int i915_forcewake_release(struct inode *inode,
struct file *file)
return 0;
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+ intel_runtime_pm_put(dev_priv);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ece397b..043b7a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7862,19 +7862,8 @@ static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv)
/*
* Make sure we're not on PC8 state before disabling PC8, otherwise
* we'll hang the machine. To prevent PC8 state, just enable force_wake.
-*
-* The other problem is that hsw_restore_lcpll() is called as part of
-* the runtime PM resume sequence, so we can't just call
-* gen6_gt_force_wake_get() because that function calls
-* intel_runtime_pm_get(), and we can't change the runtime PM refcount
-* while we are on the resume sequence. So to solve this problem we have
-* to call special forcewake code that doesn't touch runtime PM and
-* doesn't enable the forcewake delayed work.
*/
- spin_lock_irq(&dev_priv->uncore.lock);
- if (dev_priv->uncore.forcewake_count++ == 0)
- dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
if (val & LCPLL_POWER_DOWN_ALLOW) {
val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -7904,11 +7893,7 @@ static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv)
DRM_ERROR("Switching back to LCPLL failed\n");
}
- /* See the big comment above. */
- spin_lock_irq(&dev_priv->uncore.lock);
- if (--dev_priv->uncore.forcewake_count == 0)
- dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e405b61..ce338e6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -283,7 +283,6 @@ static void execlists_elsp_write(struct intel_engine_cs
*ring,
struct drm_i915_private *dev_priv = dev->dev_private;
uint64_t temp = 0;
uint32_t desc[4];
- unsigned long flags;
/* XXX: You must always write both descriptors in the order below. */
if (ctx_obj1)
@@ -297,63 +296,17 @@ static void execlists_elsp_write(struct intel_engine_cs
*ring,
desc[3] = (u32)(temp >> 32);
desc[2] = (u32)temp;
- /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
-* are in progress.
-*
-* The other problem is that we can't just call gen6_gt_force_wake_get()
-* because that function calls intel_runtime_pm_get(), which might
sleep.
-* Instead, we do the runtime_pm_get/put when creating/destroying
requests.
-*/
- spin_lock_irqsave(&dev_priv->uncore.lock, flags);
- if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
- if (dev_priv->uncore.fw_rendercount++ == 0)
- dev_priv->uncore.funcs.force_wake_get(dev_priv,
- FORCEWAKE_RENDER);
- if (dev_priv->uncore.fw_mediacount++ == 0)
- dev_priv->uncore.funcs.force_wake_get(dev_priv,
- FORCEWAKE_MEDIA);
- if (INTEL_INFO(dev)->gen >= 9) {
- if (dev_priv->unc
[Intel-gfx] [PATCH 6/9] drm/i915: Make vlv and chv forcewake put generic.
From: Mika Kuoppala
These two were using a fw dance logic where posting read was done
after both domain bit were set. When in other gens, the posting
read is done immediately after setting the forcewake bit for each
domain.
Now bring these in line with other gens.
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S
---
drivers/gpu/drm/i915/intel_uncore.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 529dcbc..b97f3c5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -232,16 +232,6 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv)
return ret;
}
-static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
-int fw_engine)
-{
- fw_domains_put(dev_priv, fw_engine);
- fw_domains_posting_read(dev_priv);
-
- if (!IS_CHERRYVIEW(dev_priv->dev))
- gen6_gt_check_fifodbg(dev_priv);
-}
-
static void gen6_force_wake_timer(unsigned long arg)
{
struct intel_uncore_forcewake_domain *domain = (void *)arg;
@@ -996,7 +986,11 @@ void intel_uncore_init(struct drm_device *dev)
FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
- dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
+ if (!IS_CHERRYVIEW(dev))
+ dev_priv->uncore.funcs.force_wake_put =
+ fw_domains_put_with_fifo;
+ else
+ dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
--
1.9.1
___
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[Intel-gfx] [PATCH 7/9] drm/i915: Rename the forcewake get/put functions
From: Mika Kuoppala
We have multiple forcewake domains now on recent gens. Change the
function naming to reflect this.
v2: More verbose names (Chris)
v3: Rebase
v4: Rebase
v5: Add documentation for forcewake_get/put
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S (v2)
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 15 ---
drivers/gpu/drm/i915/intel_display.c| 4 +--
drivers/gpu/drm/i915/intel_fbc.c| 4 +--
drivers/gpu/drm/i915/intel_lrc.c| 4 +--
drivers/gpu/drm/i915/intel_pm.c | 25 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +--
drivers/gpu/drm/i915/intel_uncore.c | 44 +
9 files changed, 58 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1f8e444..c9dbf58 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1105,7 +1105,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
if (ret)
goto out;
- gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
reqf = I915_READ(GEN6_RPNSWREQ);
reqf &= ~GEN6_TURBO_DISABLE;
@@ -1132,7 +1132,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
cagf *= GT_FREQUENCY_MULTIPLIER;
- gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev->struct_mutex);
if (IS_GEN6(dev) || IS_GEN7(dev)) {
@@ -4318,7 +4318,7 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
return 0;
intel_runtime_pm_get(dev_priv);
- gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
return 0;
}
@@ -4331,7 +4331,7 @@ static int i915_forcewake_release(struct inode *inode,
struct file *file)
if (INTEL_INFO(dev)->gen < 6)
return 0;
- gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 55a3fef..6484229 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1431,7 +1431,7 @@ static int intel_runtime_suspend(struct device *device)
intel_opregion_notify_adapter(dev, PCI_D3hot);
}
- assert_force_wake_inactive(dev_priv);
+ assert_forcewakes_inactive(dev_priv);
DRM_DEBUG_KMS("Device suspended\n");
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3262b3f..8f9b43d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2518,6 +2518,11 @@ extern void intel_uncore_check_errors(struct drm_device
*dev);
extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
+void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+ unsigned fw_domains);
+void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+ unsigned fw_domains);
+void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
@@ -3149,16 +3154,6 @@ extern void intel_display_print_error_state(struct
drm_i915_error_state_buf *e,
struct drm_device *dev,
struct intel_display_error_state
*error);
-/* On SNB platform, before reading ring registers forcewake bit
- * must be set to prevent GT core from power down and stale values being
- * returned.
- */
-void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
- unsigned fw_domains);
-void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
- unsigned fw_domains);
-void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
-
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32
*val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32
val);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 043b7a6..887d22a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7863,7 +7
[Intel-gfx] [PATCH 9/9] drm/i915: Rename i915_gen6_forcewake_count_info
From: Mika Kuoppala
There are multiple forcewake domains in newer architectures.
Rename 'i915_gen6_forcewake_count_info' debugfs entry to
'i915_forcewake_domains' to reflect this.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c9dbf58..269425b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1288,7 +1288,7 @@ static int ironlake_drpc_info(struct seq_file *m)
return 0;
}
-static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
+static int i915_forcewake_domains(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
@@ -1344,7 +1344,7 @@ static int vlv_drpc_info(struct seq_file *m)
seq_printf(m, "Media RC6 residency since boot: %u\n",
I915_READ(VLV_GT_MEDIA_RC6));
- return i915_gen6_forcewake_count_info(m, NULL);
+ return i915_forcewake_domains(m, NULL);
}
static int gen6_drpc_info(struct seq_file *m)
@@ -4406,7 +4406,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_context_status", i915_context_status, 0},
{"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_execlists", i915_execlists, 0},
- {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
+ {"i915_forcewake_domains", i915_forcewake_domains, 0},
{"i915_swizzle_info", i915_swizzle_info, 0},
{"i915_ppgtt_info", i915_ppgtt_info, 0},
{"i915_llc", i915_llc, 0},
--
1.9.1
___
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[Intel-gfx] [PATCH 3/9] drm/i915: Skip uncore lock on earlier gens
From: Chris Wilson
With gen < 6 we don't need to take uncore lock as we
don't have anything to protect from concurrent access.
v2: rebase and account for gen9 changes
Signed-off-by: Chris Wilson (v1)
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S
---
drivers/gpu/drm/i915/intel_uncore.c | 158 +---
1 file changed, 91 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 974881e..3d1ffac 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -702,38 +702,61 @@ hsw_unclaimed_reg_detect(struct drm_i915_private
*dev_priv)
}
}
-#define REG_READ_HEADER(x) \
- unsigned long irqflags; \
+#define GEN2_READ_HEADER(x) \
u##x val = 0; \
- assert_device_not_suspended(dev_priv); \
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+ assert_device_not_suspended(dev_priv);
-#define REG_READ_FOOTER \
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+#define GEN2_READ_FOOTER \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
-#define __gen4_read(x) \
+#define __gen2_read(x) \
static u##x \
-gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
- REG_READ_HEADER(x); \
+gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ GEN2_READ_HEADER(x); \
val = __raw_i915_read##x(dev_priv, reg); \
- REG_READ_FOOTER; \
+ GEN2_READ_FOOTER; \
}
#define __gen5_read(x) \
static u##x \
gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
- REG_READ_HEADER(x); \
+ GEN2_READ_HEADER(x); \
ilk_dummy_write(dev_priv); \
val = __raw_i915_read##x(dev_priv, reg); \
- REG_READ_FOOTER; \
+ GEN2_READ_FOOTER; \
}
+__gen5_read(8)
+__gen5_read(16)
+__gen5_read(32)
+__gen5_read(64)
+__gen2_read(8)
+__gen2_read(16)
+__gen2_read(32)
+__gen2_read(64)
+
+#undef __gen5_read
+#undef __gen2_read
+
+#undef GEN2_READ_FOOTER
+#undef GEN2_READ_HEADER
+
+#define GEN6_READ_HEADER(x) \
+ unsigned long irqflags; \
+ u##x val = 0; \
+ assert_device_not_suspended(dev_priv); \
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+
+#define GEN6_READ_FOOTER \
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+ trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
+ return val
+
#define __gen6_read(x) \
static u##x \
gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
- REG_READ_HEADER(x); \
+ GEN6_READ_HEADER(x); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
if (dev_priv->uncore.forcewake_count == 0 && \
NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
@@ -745,14 +768,14 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t
reg, bool trace) { \
} \
val = __raw_i915_read##x(dev_priv, reg); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
- REG_READ_FOOTER; \
+ GEN6_READ_FOOTER; \
}
#define __vlv_read(x) \
static u##x \
vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
- REG_READ_HEADER(x); \
+ GEN6_READ_HEADER(x); \
if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
if (dev_priv->uncore.fw_rendercount == 0) \
fwengine = FORCEWAKE_RENDER; \
@@ -765,14 +788,14 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
val = __raw_i915_read##x(dev_priv, reg); \
if (fwengine) \
dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
- REG_READ_FOOTER; \
+ GEN6_READ_FOOTER; \
}
#define __chv_read(x) \
static u##x \
chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
- REG_READ_HEADER(x); \
+ GEN6_READ_HEADER(x); \
if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
if (dev_priv->uncore.fw_rendercount == 0) \
fwengine = FORCEWAKE_RENDER; \
@@ -790,7 +813,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
val = __raw_i915_read##x(dev_priv, reg); \
if (fwengine) \
dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
- REG_READ_FOOTER; \
+ GEN6_READ_FOOTER; \
}
#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)\
@@ -799,7 +822,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
#define __gen9_read(x) \
static u##x \
gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
- REG_READ_HEADER(x); \
+ GEN6_READ_HEADER(x); \
if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
val = __raw_i915_read##x(dev_priv, reg); \
} else { \
@@ -825,7 +848,7 @@ g
[Intel-gfx] [PATCH 8/9] drm/i915: Enum forcewake domains and domain identifiers
From: Mika Kuoppala
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
v2: s/fw_domain/forcewake_domain (Jani)
v3: rebase
Suggested-by: Daniel Vetter
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S (v1)
---
drivers/gpu/drm/i915/i915_drv.h | 45 ++-
drivers/gpu/drm/i915/intel_uncore.c | 47 -
2 files changed, 49 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f9b43d..b3e36ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -574,11 +574,28 @@ struct drm_i915_display_funcs {
void (*enable_backlight)(struct intel_connector *connector);
};
+enum forcewake_domain_id {
+ FW_DOMAIN_ID_RENDER = 0,
+ FW_DOMAIN_ID_BLITTER,
+ FW_DOMAIN_ID_MEDIA,
+
+ FW_DOMAIN_ID_COUNT
+};
+
+enum forcewake_domains {
+ FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
+ FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
+ FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
+ FORCEWAKE_ALL = (FORCEWAKE_RENDER |
+FORCEWAKE_BLITTER |
+FORCEWAKE_MEDIA)
+};
+
struct intel_uncore_funcs {
void (*force_wake_get)(struct drm_i915_private *dev_priv,
- int fw_engine);
+ enum forcewake_domains
domains);
void (*force_wake_put)(struct drm_i915_private *dev_priv,
- int fw_engine);
+ enum forcewake_domains
domains);
uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset,
bool trace);
uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset,
bool trace);
@@ -595,25 +612,17 @@ struct intel_uncore_funcs {
uint64_t val, bool trace);
};
-enum {
- FW_DOMAIN_ID_RENDER = 0,
- FW_DOMAIN_ID_BLITTER,
- FW_DOMAIN_ID_MEDIA,
-
- FW_DOMAIN_ID_COUNT
-};
-
struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
struct intel_uncore_funcs funcs;
unsigned fifo_count;
- unsigned fw_domains;
+ enum forcewake_domains fw_domains;
struct intel_uncore_forcewake_domain {
struct drm_i915_private *i915;
- int id;
+ enum forcewake_domain_id id;
unsigned wake_count;
struct timer_list timer;
u32 reg_set;
@@ -623,12 +632,6 @@ struct intel_uncore {
u32 reg_post;
u32 val_reset;
} fw_domain[FW_DOMAIN_ID_COUNT];
-#define FORCEWAKE_RENDER (1 << FW_DOMAIN_ID_RENDER)
-#define FORCEWAKE_BLITTER (1 << FW_DOMAIN_ID_BLITTER)
-#define FORCEWAKE_MEDIA(1 << FW_DOMAIN_ID_MEDIA)
-#define FORCEWAKE_ALL (FORCEWAKE_RENDER | \
-FORCEWAKE_BLITTER | \
-FORCEWAKE_MEDIA)
};
/* Iterate over initialised fw domains */
@@ -2517,11 +2520,11 @@ extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
-const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
+const char *intel_uncore_forcewake_domain_to_str(const enum
forcewake_domain_id id);
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
- unsigned fw_domains);
+ enum forcewake_domains domains);
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
- unsigned fw_domains);
+ enum forcewake_domains domains);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
void
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 886ff6d..12da502 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -49,7 +49,7 @@ static const char * const forcewake_domain_names[] = {
};
const char *
-intel_uncore_forcewake_domain_to_str(const int id)
+intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
{
BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
FW_DOMAIN_ID_COUNT);
@@ -122,10 +122,10 @@ fw_domain_posting_read(const struct
intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
-
[Intel-gfx] [PATCH 5/9] drm/i915: Consolidate forcewake code
From: Mika Kuoppala
As we now have forcewake domains, take advantage of it
by putting the differences in gen fw handling in data rather
than in code.
In past we have opencoded this quite extensively as the fw handling
is in the fast path. There has also been a lot of cargo-culted
copy'n'pasting from older gens to newer ones.
Now when the releasing of the forcewake is done by deferred timer,
it gives chance to consolidate more. Due to the frequency of actual hw
access being significantly less.
Take advantage of this and generalize the fw handling code
as much as possible. But we still aim to keep the forcewake sequence
particularities for each gen intact. So the access pattern
to fw engines should remain the same.
v2: - s/old_ack/clear_ack (Chris)
- s/post_read/posting_read (Chris)
- less polite commit msg (Chris)
v3: - rebase
- check and clear wake_count in init
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S (v2)
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/intel_uncore.c | 469
3 files changed, 213 insertions(+), 270 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 65adb62..1f8e444 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1294,17 +1294,12 @@ static int i915_gen6_forcewake_count_info(struct
seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_uncore_forcewake_domain *fw_domain;
- const char *domain_names[] = {
- "render",
- "blitter",
- "media",
- };
int i;
spin_lock_irq(&dev_priv->uncore.lock);
for_each_fw_domain(fw_domain, dev_priv, i) {
seq_printf(m, "%s.wake_count = %u\n",
- domain_names[i],
+ intel_uncore_forcewake_domain_to_str(i),
fw_domain->wake_count);
}
spin_unlock_irq(&dev_priv->uncore.lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2615927..3262b3f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -616,6 +616,12 @@ struct intel_uncore {
int id;
unsigned wake_count;
struct timer_list timer;
+ u32 reg_set;
+ u32 val_set;
+ u32 val_clear;
+ u32 reg_ack;
+ u32 reg_post;
+ u32 val_reset;
} fw_domain[FW_DOMAIN_ID_COUNT];
#define FORCEWAKE_RENDER (1 << FW_DOMAIN_ID_RENDER)
#define FORCEWAKE_BLITTER (1 << FW_DOMAIN_ID_BLITTER)
@@ -2511,6 +2517,7 @@ extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
+const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index b35f3a9..529dcbc 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -42,6 +42,26 @@
#define __raw_posting_read(dev_priv__, reg__)
(void)__raw_i915_read32(dev_priv__, reg__)
+static const char * const forcewake_domain_names[] = {
+ "render",
+ "blitter",
+ "media",
+};
+
+const char *
+intel_uncore_forcewake_domain_to_str(const int id)
+{
+ BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
+FW_DOMAIN_ID_COUNT);
+
+ if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
+ return forcewake_domain_names[id];
+
+ WARN_ON(id);
+
+ return "unknown";
+}
+
static void
assert_device_not_suspended(struct drm_i915_private *dev_priv)
{
@@ -49,73 +69,123 @@ assert_device_not_suspended(struct drm_i915_private
*dev_priv)
"Device suspended\n");
}
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
+static inline void
+fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
{
- /* w/a for a sporadic read returning 0 by waiting for the GT
-* thread to wake up.
-*/
- if (wait_for_atomic_us((__raw_i915_read32(dev_priv,
GEN6_GT_THREAD_STATUS_REG) &
- GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
- DRM_ERROR("GT thread status wait timed out\n");
+ __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
}
-static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
+static inline void
+fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
{
-
[Intel-gfx] [PATCH 1/9] drm/i915: Rebalance runtime pm vs forcewake
From: Chris Wilson
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack
commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
Author: Paulo Zanoni
Date: Tue Apr 1 14:55:07 2014 -0300
drm/i915: don't schedule force_wake_timer at gen6_read
and apply the single line corrective instead.
v2: assert forcewake is off after the forcewake_reset (Paulo)
References: https://bugs.freedesktop.org/show_bug.cgi?id=80913
Cc: Paulo Zanoni
Cc: Daniel Vetter
Signed-off-by: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Deepak S (v1)
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++--
drivers/gpu/drm/i915/intel_uncore.c | 18 ++
2 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 308774f..55a3fef 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1365,8 +1365,6 @@ static int intel_runtime_suspend(struct device *device)
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
return -ENODEV;
- assert_force_wake_inactive(dev_priv);
-
DRM_DEBUG_KMS("Suspending device\n");
/*
@@ -1405,6 +1403,7 @@ static int intel_runtime_suspend(struct device *device)
}
del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
+ intel_uncore_forcewake_reset(dev, false);
dev_priv->pm.suspended = true;
/*
@@ -1432,6 +1431,8 @@ static int intel_runtime_suspend(struct device *device)
intel_opregion_notify_adapter(dev, PCI_D3hot);
}
+ assert_force_wake_inactive(dev_priv);
+
DRM_DEBUG_KMS("Device suspended\n");
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e9561de..b39ed79 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -449,8 +449,6 @@ static void gen6_force_wake_timer(unsigned long arg)
if (--dev_priv->uncore.forcewake_count == 0)
dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-
- intel_runtime_pm_put(dev_priv);
}
void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
@@ -586,7 +584,6 @@ void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv, int fw_engine)
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
{
unsigned long irqflags;
- bool delayed = false;
if (!dev_priv->uncore.funcs.force_wake_put)
return;
@@ -603,21 +600,19 @@ void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv, int fw_engine)
goto out;
}
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
WARN_ON(!dev_priv->uncore.forcewake_count);
if (--dev_priv->uncore.forcewake_count == 0) {
dev_priv->uncore.forcewake_count++;
- delayed = true;
mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
jiffies + 1);
}
+
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
out:
- if (!delayed)
- intel_runtime_pm_put(dev_priv);
+ intel_runtime_pm_put(dev_priv);
}
void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
@@ -774,12 +769,11 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t
reg, bool trace) { \
NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
dev_priv->uncore.funcs.force_wake_get(dev_priv, \
FORCEWAKE_ALL); \
- val = __raw_i915_read##x(dev_priv, reg); \
- dev_priv->uncore.funcs.force_wake_put(dev_priv, \
- FORCEWAKE_ALL); \
- } else { \
- val = __raw_i915_read##x(dev_priv, reg); \
+ dev_priv->uncore.forcewake_count++; \
+ mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
+jiffies + 1); \
} \
+ val = __raw_i915_read##x(dev_priv, reg); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
REG_READ_FOOTER; \
}
--
1.9.1
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] tools/intel_gpu_frequency: remove use of getsubopt
From: Tim Gore
getsubopt is not available in android. The "get" option
doesn't really need sub-options, just display all the
current frequency settings (as per discussion with
Ben Widawsky)
Signed-off-by: Tim Gore
---
man/intel_gpu_frequency.man | 6 +++---
tools/intel_gpu_frequency.c | 29 +
2 files changed, 8 insertions(+), 27 deletions(-)
diff --git a/man/intel_gpu_frequency.man b/man/intel_gpu_frequency.man
index 60e4e0c..7144848 100644
--- a/man/intel_gpu_frequency.man
+++ b/man/intel_gpu_frequency.man
@@ -3,7 +3,7 @@
intel_gpu_frequency: \- manual page for intel_gpu_frequency
.SH SYNOPSIS
.B intel_gpu_frequency
-[\fI\,-e\/\fR] [\fI\,--min | --max\/\fR] [\fI\,-g (min|max|efficient)\/\fR]
[\fI\,-s frequency_mhz\/\fR]
+[\fI\,-e\/\fR] [\fI\,--min | --max\/\fR] [\fI\,-g\/\fR] [\fI\,-s
frequency_mhz\/\fR]
.SH DESCRIPTION
\&A program to manipulate Intel GPU frequencies. Intel GPUs
will automatically throttle the frequencies based on system demands, up when
@@ -19,8 +19,8 @@ safe bet.
\fB\-e\fR
Lock frequency to the most efficient frequency
.TP
-\fB\-g\fR, \fB\-\-get=\fR
-Get the frequency comma separated list of ("cur"|"min"|"max"|"eff")
+\fB\-g\fR, \fB\-\-get\fR
+Get all the current frequency settings
.TP
\fB\-s\fR, \fB\-\-set\fR
Lock frequency to an absolute value (MHz)
diff --git a/tools/intel_gpu_frequency.c b/tools/intel_gpu_frequency.c
index aedceb4..7144461 100644
--- a/tools/intel_gpu_frequency.c
+++ b/tools/intel_gpu_frequency.c
@@ -22,7 +22,7 @@
*
* Example:
* Get all frequencies:
- * intel_gpu_frequency --get=cur,min,max,eff
+ * intel_gpu_frequency --get
*
* Same as above:
* intel_gpu_frequency -g
@@ -152,7 +152,7 @@ usage(const char *prog)
printf("Usage: %s [-e] [--min | --max] [-g (min|max|efficient)] [-s
frequency_mhz]\n\n", prog);
printf("Options: \n");
printf(" -eLock frequency to the most efficient
frequency\n");
- printf(" -g, --get=Get the frequency (optional arg:
\"cur\"|\"min\"|\"max\"|\"eff\")\n");
+ printf(" -g, --get Get all the frequency settings\n");
printf(" -s, --set Lock frequency to an absolute value (MHz)\n");
printf(" -c, --custom Set a min, or max frequency \"min=X |
max=Y\"\n");
printf(" -m --max Lock frequency to max frequency\n");
@@ -184,13 +184,6 @@ parse(int argc, char *argv[], bool *act_upon, size_t
act_upon_n, int *new_freq)
int c, tmp;
bool write = false;
- char *token[] = {
- (char *)info[CUR].name,
- (char *)info[MIN].name,
- (char *)"eff",
- (char *)info[MAX].name
- };
-
/* No args means -g" */
if (argc == 1) {
for (c = 0; c < act_upon_n; c++)
@@ -200,7 +193,7 @@ parse(int argc, char *argv[], bool *act_upon, size_t
act_upon_n, int *new_freq)
while (1) {
int option_index = 0;
static struct option long_options[] = {
- { "get", optional_argument, NULL, 'g' },
+ { "get", no_argument, NULL, 'g' },
{ "set", required_argument, NULL, 's' },
{ "custom", required_argument, NULL, 'c'},
{ "min", no_argument, NULL, 'i' },
@@ -211,7 +204,7 @@ parse(int argc, char *argv[], bool *act_upon, size_t
act_upon_n, int *new_freq)
{ NULL, 0, NULL, 0}
};
- c = getopt_long(argc, argv, "eg::s:c:midh", long_options,
&option_index);
+ c = getopt_long(argc, argv, "egs:c:midh", long_options,
&option_index);
if (c == -1)
break;
@@ -219,19 +212,7 @@ parse(int argc, char *argv[], bool *act_upon, size_t
act_upon_n, int *new_freq)
case 'g':
if (write == true)
fprintf(stderr, "Read and write operations not
support simultaneously.\n");
-
- if (optarg) {
- char *value, *subopts = optarg;
- int x;
- while (*subopts != '\0') {
- x = getsubopt(&subopts, token, &value);
- if (x == -1) {
- fprintf(stderr, "Unrecognized
option (%s)\n", value);
- break;
- } else
- act_upon[x] = true;
- }
- } else {
+ {
int i;
for (i = 0; i < act_upon_n; i++)
act_upon[i] = true;
--
2.2.1
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Re: [Intel-gfx] [PATCH 6/7] drm/i915: Improve how the memory for crtc state is allocated
On 01/15/2015 08:50 PM, Matt Roper wrote:
On Thu, Jan 15, 2015 at 02:55:26PM +0200, Ander Conselvan de Oliveira wrote:
The previous patch changed the config field in intel_crtc to a pointer,
but to keep the mechanical changes (done with spatch) separate from the
new code, the pointer was made to point to a new _config field with type
struct intel_crtc_state added to that struct. This patch improves that
code by getting rid of that field, allocating a state struct in
intel_crtc_init() a keeping it properly updated when a mode set
happens.
v2: Manual changes split from previous patch. (Matt)
Don't leak the current state when the crtc is destroyed (Matt)
Signed-off-by: Ander Conselvan de Oliveira
I don't see a need to keep patch #7 separate from the changes you're
making here; I'd go ahead and just squash it into this patch since it's
a trivial change.
Although 6+7 look okay, I do question whether we really want to keep
intel_crtc->config now that our intel crtc state is a subclass of the
DRM state object and can always be accessed through our base pointer.
For planes, we just grab the base state through the
object's base pointer, then cast that to the i915-specific state object;
i.e.,
foo = to_intel_plane_state(intel_plane->base.state);
My inclination would be to handle crtc's the same way for consistency
and so that we don't have two pointers per object (one base, one
i915-specific) that are essentially pointing at the same thing and have
to be kept in sync.
Daniel was anticipating we would still need ->config and ->new_config.
For async updates, we would commit drm_crtc->state before it is written
to the hardware. In that case, the hardware current state would still be
in intel_crtc->config and drm_crtc->state would actually match
->new_config. We'll have to sort this out later, so I just avoided doing
too many changes.
Ander
Anyway, you can consider this entire series
Reviewed-by: Matt Roper
whether or not you decide to make further updates to 6+7. The use of
Coccinelle to auto-generate most of these patches was great and made the
series very easy to review.
Matt
---
drivers/gpu/drm/i915/intel_display.c | 20
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index acdaed2..002e5a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8926,6 +8926,13 @@ out:
intel_runtime_pm_put(dev_priv);
}
+static void intel_crtc_set_state(struct intel_crtc *crtc,
+struct intel_crtc_state *crtc_state)
+{
+ kfree(crtc->config);
+ crtc->config = crtc_state;
+}
+
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -8944,6 +8951,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
+ intel_crtc_set_state(intel_crtc, NULL);
kfree(intel_crtc);
}
@@ -10995,8 +11003,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
crtc->mode = *mode;
/* mode_set/enable/disable functions rely on a correct pipe
* config. */
- (*(to_intel_crtc(crtc)->config)) = *pipe_config;
- to_intel_crtc(crtc)->new_config = to_intel_crtc(crtc)->config;
+ intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
/*
* Calculate and store various constants which
@@ -11040,7 +11047,6 @@ done:
if (ret && crtc->enabled)
crtc->mode = *saved_mode;
- kfree(pipe_config);
kfree(saved_mode);
return ret;
}
@@ -12187,6 +12193,7 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state = NULL;
struct drm_plane *primary = NULL;
struct drm_plane *cursor = NULL;
int i, ret;
@@ -12195,6 +12202,11 @@ static void intel_crtc_init(struct drm_device *dev,
int pipe)
if (intel_crtc == NULL)
return;
+ crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+ if (!crtc_state)
+ goto fail;
+ intel_crtc_set_state(intel_crtc, crtc_state);
+
primary = intel_primary_plane_create(dev, pipe);
if (!primary)
goto fail;
@@ -12240,7 +12252,6 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
- intel_crtc->config = &intel_crtc->_config;
return;
fail:
@@ -12248,6 +12259,7 @@ fail:
drm_plane_cleanup(primary);
if (cursor)
dr
[Intel-gfx] [PATCH] drm/i915/skl: Enabling PSR on Skylake
Mainly taking care of some register offsets, otherwise things are similar to
hsw. Also, programming ddi aux to use hardcoded values for psr data select.
v2: introduce EDP_PSR_AUX_BASE macro (Chris)
v3: Moving to HW tracking for SKL+ platforms, so activating source psr during
psr_enabling and then avoiding psr entries and exits for each frontbuffer
updates.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/i915_drv.h |3 ++-
drivers/gpu/drm/i915/i915_reg.h | 19 +--
drivers/gpu/drm/i915/intel_frontbuffer.c |7 +--
drivers/gpu/drm/i915/intel_psr.c | 18 +-
4 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 42c69ca..ee5cd3b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2355,7 +2355,8 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
-IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
+IS_SKYLAKE(dev))
#define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828cf5..068c8da 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2619,12 +2619,14 @@ enum skl_disp_power_wells {
#define EDP_PSR_TP1_TIME_0us (3<<4)
#define EDP_PSR_IDLE_FRAME_SHIFT 0
-#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_BASE(dev) (INTEL_INFO(dev)->gen >= 9 ? \
+ 0x64000 : EDP_PSR_BASE(dev))
+#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_AUX_BASE(dev) + 0x10)
+#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_AUX_BASE(dev) + 0x14)
+#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_AUX_BASE(dev) + 0x18)
+#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_AUX_BASE(dev) + 0x1c)
+#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_AUX_BASE(dev) + 0x20)
+#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_AUX_BASE(dev) + 0x24)
#define EDP_PSR_STATUS_CTL(dev)(EDP_PSR_BASE(dev) +
0x40)
#define EDP_PSR_STATUS_STATE_MASK(7<<29)
@@ -3771,6 +3773,11 @@ enum skl_disp_power_wells {
#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK(0x7ff)
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
+#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
+#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL(1 << 13)
+#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
+#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
+#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
/*
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c
b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 79f6d72..010d550 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -156,7 +156,9 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj,
intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
- intel_psr_invalidate(dev, obj->frontbuffer_bits);
+
+ if (INTEL_INFO(dev)->gen < 9)
+ intel_psr_invalidate(dev, obj->frontbuffer_bits);
}
/**
@@ -182,7 +184,8 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
- intel_psr_flush(dev, frontbuffer_bits);
+ if (INTEL_INFO(dev)->gen < 9)
+ intel_psr_flush(dev, frontbuffer_bits);
/*
* FIXME: Unconditional fbc flushing here is a rather gross hack and
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index dd0e6e0..6d2cdb8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -173,11 +173,24 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
- I915_WRITE(EDP_PSR_AUX_CTL(dev),
+ if (INTEL_INF
