Re: [Intel-gfx] [PATCH v3 5/5] drm/i915: Setup static bias for GPU
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6085 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 270/270 269/270 ILK 303/303 303/303 SNB 304/304 304/304 IVB 337/337 337/337 BYT 287/287 287/287 HSW 361/361 361/361 BDW 309/309 309/309 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt@gem_tiled_pread_pwrite PASS(2) FAIL(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reject the colorkey ioctls for primary and cursor planes
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6083 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 270/270 269/270 ILK 303/303 303/303 SNB -1 304/304 303/304 IVB 337/337 337/337 BYT 287/287 287/287 HSW 361/361 361/361 BDW 309/309 309/309 -Detailed- Platform Testdrm-intel-nightly Series Applied PNV igt@gem_userptr_blits@coherency-sync CRASH(1)PASS(1) CRASH(1)PASS(1) *SNB igt@kms_rotation_crc@sprite-rotation PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*failed_to_enable_link_training@failed to enable link training drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_start_channel_equalization@failed to start channel equalization drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Enable dithering on intel VCH DVO chips on 18bpp panels
Hi folks,
this is a patch against drm-intel-nightly that enables an apparently
undocumented feature of the intel VCH DVO chips. Bit 4 of the VR01
register controls an automatic dithering for 18bpp outputs which greatly
improves the visual image quality for 24bpp display buffers.
The bios of my IBM R31 automatically enables this feature, it is
disabled again by the ivchr driver. The following patch checks whether
the display is connected with a 18bpp connection and if so, re-enables
dithering.
This feature has been tested to work fine on 16bpp images and with the
scaler on and off. There are no ill side effects.
Please let me know whether this patch is acceptable.
Thanks and greetings,
Thomas
Signed-off-by: Thomas Richter t...@math.tu-berlin.de
---
drivers/gpu/drm/i915/dvo_ivch.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c
b/drivers/gpu/drm/i915/dvo_ivch.c
index 0f2587f..89b08a8 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -23,6 +23,9 @@
* Authors:
*Eric Anholt e...@anholt.net
*
+ * Minor modifications (Dithering enable):
+ *Thomas Richter t...@math.tu-berlin.de
+ *
*/
#include dvo.h
@@ -59,6 +62,8 @@
# define VR01_DVO_BYPASS_ENABLE(1 1)
/** Enables the DVO clock */
# define VR01_DVO_ENABLE (1 0)
+/** Enable dithering for 18bpp panels. Not documented. */
+# define VR01_DITHER_ENABLE (1 4)
/*
* LCD Interface Format
@@ -74,6 +79,8 @@
# define VR10_INTERFACE_2X18 (2 2)
/** Enables 2x24-bit LVDS output */
# define VR10_INTERFACE_2X24 (3 2)
+/** Mask that defines the depth of the pipeline */
+# define VR10_INTERFACE_DEPTH_MASK (3 2)
/*
* VR20 LCD Horizontal Display Size
@@ -342,9 +349,15 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
struct drm_display_mode *adjusted_mode)
{
uint16_t vr40 = 0;
- uint16_t vr01;
+ uint16_t vr01 = 0;
+ uint16_t vr10;
+
+ ivch_read(dvo, VR10, vr10);
+ /* Enable dithering for 18 bpp pipelines */
+ vr10 = VR10_INTERFACE_DEPTH_MASK;
+ if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
+ vr01 = VR01_DITHER_ENABLE;
- vr01 = 0;
vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
VR40_HORIZONTAL_INTERP_ENABLE);
@@ -353,7 +366,7 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
uint16_t x_ratio, y_ratio;
vr01 |= VR01_PANEL_FIT_ENABLE;
- vr40 |= VR40_CLOCK_GATING_ENABLE;
+ vr40 |= VR40_CLOCK_GATING_ENABLE |
VR40_ENHANCED_PANEL_FITTING;
x_ratio = (((mode-hdisplay - 1) 16) /
(adjusted_mode-hdisplay - 1)) 2;
y_ratio = (((mode-vdisplay - 1) 16) /
@@ -380,6 +393,8 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
DRM_DEBUG_KMS(VR00: 0x%04x\n, val);
ivch_read(dvo, VR01, val);
DRM_DEBUG_KMS(VR01: 0x%04x\n, val);
+ ivch_read(dvo, VR10, val);
+ DRM_DEBUG_KMS(VR10: 0x%04x\n, val);
ivch_read(dvo, VR30, val);
DRM_DEBUG_KMS(VR30: 0x%04x\n, val);
ivch_read(dvo, VR40, val);
--
1.7.10.4
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Re: [Intel-gfx] [PATCH 49/49] drm/i915: Cache last cmd descriptor when parsing
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6074 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4 270/270 266/270 ILK -1 303/303 302/303 SNB 304/304 304/304 IVB -26 337/337 311/337 BYT -21 287/287 266/287 HSW -28 361/361 333/361 BDW -5 309/309 304/309 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt@gem_fence_thrash@bo-write-verify-threaded-none PASS(1) FAIL(1)PASS(1) *PNV igt@gem_fence_thrash@bo-write-verify-x PASS(1) FAIL(1)PASS(1) *PNV igt@gem_fence_thrash@bo-write-verify-y PASS(1) FAIL(1)PASS(1) *PNV igt@gem_tiled_pread_pwrite PASS(1) FAIL(1)PASS(1) *ILK igt@kms_flip@blocking-absolute-wf_vblank-interruptible PASS(1) DMESG_WARN(1)PASS(1) *IVB igt@gem_reloc_overflow@single-overflow PASS(1) FAIL(2) *IVB igt@gem_exec_bad_domains@conflicting-write-domain PASS(1) FAIL(2) *IVB igt@drm_import_export@prime PASS(1) DMESG_WARN(2) (dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/i915_cmd_parser.c:#i915_parse_cmds[i915]()@WARNING:.* at .* i915_parse_cmds+0x *IVB igt@gem_reloc_overflow@batch-end-unaligned PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@invalid-address PASS(1) FAIL(2) *IVB igt@prime_self_import@reimport-vs-gem_close-race PASS(1) FAIL(2) *IVB igt@gem_write_read_ring_switch@blt2bsd-interruptible PASS(1) FAIL(2) *IVB igt@gem_write_read_ring_switch@blt2bsd PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@batch-start-unaligned PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@source-offset-end-reloc-cpu PASS(1) FAIL(2) *IVB igt@gem_write_read_ring_switch@blt2render PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@buffercount-overflow PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@source-offset-big-reloc-gtt PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@source-offset-negative-reloc-gtt PASS(1) FAIL(2) *IVB igt@gem_reloc_overflow@source-offset-unaligned-reloc-cpu PASS(1) FAIL(2) *IVB igt@drm_import_export@flink PASS(1) DMESG_WARN(1) (dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/i915_cmd_parser.c:#i915_parse_cmds[i915]()@WARNING:.* at .* i915_parse_cmds+0x *IVB igt@gem_ctx_exec@basic PASS(1) FAIL(1) *IVB igt@gem_reloc_overflow@wrapped-overflow PASS(1) FAIL(1) *IVB igt@gem_reloc_overflow@source-offset-negative-reloc-cpu PASS(1) FAIL(1) *IVB igt@gem_reloc_overflow@source-offset-unaligned-reloc-gtt PASS(1) FAIL(1) *IVB igt@gem_reloc_overflow@source-offset-end-reloc-gtt PASS(1) FAIL(1) *IVB igt@gem_exec_parse@oacontrol-tracking PASS(1) FAIL(1) *IVB igt@gem_reloc_overflow@source-offset-big-reloc-cpu PASS(1) FAIL(1) *IVB igt@gem_exec_parse@cmd-crossing-page PASS(1) FAIL(1) *IVB igt@gem_write_read_ring_switch@blt2render-interruptible PASS(1) FAIL(1) *IVB igt@gem_flink_race@flink_close PASS(1) FAIL(1) *BYT igt@gem_reloc_overflow@single-overflow PASS(1) FAIL(2) *BYT igt@gem_exec_bad_domains@conflicting-write-domain PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@batch-end-unaligned PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@invalid-address PASS(1) FAIL(2) *BYT igt@prime_self_import@reimport-vs-gem_close-race PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@batch-start-unaligned PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-end-reloc-cpu PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@buffercount-overflow PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-big-reloc-gtt PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-negative-reloc-gtt PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-unaligned-reloc-cpu PASS(1) FAIL(2) *BYT igt@gem_ctx_exec@basic PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@wrapped-overflow PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-negative-reloc-cpu PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-unaligned-reloc-gtt PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-end-reloc-gtt PASS(1) FAIL(2) *BYT igt@gem_exec_parse@oacontrol-tracking PASS(1) FAIL(2) *BYT igt@gem_reloc_overflow@source-offset-big-reloc-cpu PASS(1)
[Intel-gfx] [PATCH v3 5/5] drm/i915: Setup static bias for GPU
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..ea708ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -670,6 +670,11 @@ enum skl_disp_power_wells {
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
+#define VLV_IOSFB_RPS_OVERRIDE 0x04
+#define VLV_OVERRIDE_RPS_MASK 1
+#define VLV_ENABLE_BIAS_SHARE (1 1)
+#define VLV_BIAS_VAL (6 2)
+
#define VLV_CZ_CLOCK_TO_MILLI_SEC 10
#define VLV_RP_UP_EI_THRESHOLD 90
#define VLV_RP_DOWN_EI_THRESHOLD 70
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e71a3..673612b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5015,6 +5015,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+ vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
@@ -5099,6 +5105,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+ vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
--
1.9.1
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[Intel-gfx] [PATCH v3 4/5] drm/i915/chv: Remove unused rps min function
From: Deepak S deepa...@linux.intel.com
On CHV, since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2f7d2e0..88e71a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4665,24 +4665,6 @@ static int cherryview_rps_guar_freq(struct
drm_i915_private *dev_priv)
return rp1;
}
-static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = dev_priv-dev;
- u32 val, rpn;
-
- if (dev-pdev-revision = 0x20) {
- val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
- rpn = ((val FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT)
- FB_GFX_FREQ_FUSE_MASK);
- } else { /* For pre-production hardware */
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = ((val PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT)
- PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
- }
-
- return rpn;
-}
-
static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp1;
--
1.9.1
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[Intel-gfx] [PATCH v3 0/5] CHV PM fix Improvements
From: Deepak S deepa...@linux.intel.com Adding few of PM fixes and Improvements for CHV/VLV. Addressed few comments. Deepak S (5): drm/i915/chv: Remove Wait for a previous gfx force-off drm/i915: Re-adjusting rc6 promotional timer for chv drm/i915/chv: Set min freq to efficient frequency on chv drm/i915/chv: Remove unused rps min function drm/i915: Setup static bias for GPU drivers/gpu/drm/i915/i915_drv.c | 6 -- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 37 - 3 files changed, 25 insertions(+), 23 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/5] drm/i915/chv: Remove Wait for a previous gfx force-off
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 82f8be4..182d6a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1194,11 +1194,13 @@ int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv, bool force_on)
int err;
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
- WARN_ON(!!(val VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) VLV_GFX_CLK_STATUS_BIT)
/* Wait for a previous force-off to settle */
- if (force_on) {
+ if (force_on !IS_CHERRYVIEW(dev_priv-dev)) {
+ /* WARN_ON only for the Valleyview */
+ WARN_ON(!!(val VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
+
err = wait_for(!COND, 20);
if (err) {
DRM_ERROR(timeout waiting for GFX clock force-off
(%08x)\n,
--
1.9.1
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[Intel-gfx] [PATCH v3 3/5] drm/i915/chv: Set min freq to efficient frequency on chv
From: Deepak S deepa...@linux.intel.com After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe Rp0. If we drop the frequency to RPn, punit is failing to change the input voltage to minimum :( v2: Change commit message v3: set min_freq before idle_freq (chris) Signed-off-by: Deepak S deepa...@linux.intel.com Acked-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 44428e4..2f7d2e0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4934,7 +4934,8 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) intel_gpu_freq(dev_priv, dev_priv-rps.rp1_freq), dev_priv-rps.rp1_freq); - dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv); + /* PUnit validated range is only [RPe, RP0] */ + dev_priv-rps.min_freq = dev_priv-rps.efficient_freq; DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n, intel_gpu_freq(dev_priv, dev_priv-rps.min_freq), dev_priv-rps.min_freq); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/5] drm/i915: Re-adjusting rc6 promotional timer for chv
From: Deepak S deepa...@linux.intel.com After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance. Signed-off-by: Deepak S deepa...@linux.intel.com Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fa4ccb3..44428e4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4996,8 +4996,8 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ - I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); + /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); /* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
