Re: [Intel-gfx] [PATCH] drm/i915: Remove wait for for punit to updates freq.
On Wed, Apr 29, 2015 at 08:20:20AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index e710b43..2e1ed07 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3894,7 +3894,7 @@ static void valleyview_set_rps(struct drm_device
*dev, u8 val)
* * If Gfx is Idle, then
* 1. Mask Turbo interrupts
* 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
+ * 3. Request the freq to Rpn.
* 4. Clear the Force GFX CLK ON bit so that Gfx can down
* 5. Unmask Turbo interrupts
*/
@@ -3902,8 +3902,8 @@ static void vlv_set_rps_idle(struct
drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
- /* CHV and latest VLV don't need to force the gfx clock */
- if (IS_CHERRYVIEW(dev) || dev-pdev-revision = 0xd) {
+ /* CHV don't need to force the gfx clock */
+ if (IS_CHERRYVIEW(dev)) {
valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
return;
}
@@ -3920,20 +3920,8 @@ static void vlv_set_rps_idle(struct
drm_i915_private *dev_priv)
gen6_sanitize_rps_pm_mask(dev_priv, ~0));
vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
- dev_priv-rps.min_freq_softlimit);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
- GENFREQSTATUS) == 0, 100))
- DRM_ERROR(timed out waiting for Punit\n);
-
+ valleyview_set_rps(dev_priv-dev, dev_priv-rps.min_freq_softlimit);
vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK,
-gen6_rps_pm_mask(dev_priv, dev_priv-rps.cur_freq));
}
void gen6_rps_idle(struct drm_i915_private *dev_priv)
Yeah I think this is fine (may need a rebase though, you can keep my r-b
if you do that in case Jani doesn't want to deal with the merge conflicts).
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
The removal of the stepping check is still confusing me even if the
rest would be OK.
Stepping check was added latest BYT release. On older BYT stepping, We used
to wait for punit to grant the freq in GT Idle case, (most of the cases punit
is timing out :( )
We now make the gfx clock force apply to all VLV and then request the freq to
RPn this should be good enough to get voltage to Vnn.
But we shouldn't need the gfx clock force for the latest VLV
stepping(s), and we certainly didn't do it before. So why do
it now?
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Add support for getting size of the stolen region
On Wed, Apr 29, 2015 at 03:01:59PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch extends the get_aperture_ioctl to add support
for getting total size of the stolen region and available
size of the stolen region.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_gem.c | 15 ++-
include/uapi/drm/i915_drm.h | 6 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a568cd1..a40b44f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3277,4 +3277,10 @@ inline static bool i915_gem_obj_is_prw_allowed(struct
drm_i915_gem_object *obj)
return !obj-userptr.mm;
}
+inline static bool i915_gem_obj_is_stolen_used(struct drm_i915_gem_object
*obj)
+{
+ return obj-stolen (i915_gem_obj_is_pinned(obj)
+|| obj-madv == I915_MADV_WILLNEED);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3491bd3..ee93508 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -150,17 +150,30 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev,
void *data,
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_gem_get_aperture *args = data;
struct drm_i915_gem_object *obj;
- size_t pinned;
+ size_t pinned, pinned_stolen;
pinned = 0;
+ pinned_stolen = 0;
mutex_lock(dev-struct_mutex);
list_for_each_entry(obj, dev_priv-mm.bound_list, global_list)
if (i915_gem_obj_is_pinned(obj))
pinned += i915_gem_obj_ggtt_size(obj);
+
+ /* Calculating available stolen size */
+ list_for_each_entry(obj, dev_priv-mm.bound_list, global_list)
+ if (i915_gem_obj_is_stolen_used(obj))
+ pinned_stolen += i915_gem_obj_ggtt_size(obj);
+
+ list_for_each_entry(obj, dev_priv-mm.unbound_list, global_list)
+ if (i915_gem_obj_is_stolen_used(obj))
+ pinned_stolen += i915_gem_obj_ggtt_size(obj);
Ah, here you will want to iterate over the stolen drm_mm range manager
to get an accurate count.
Could you respin this on top of
id:1422276205-8532-5-git-send-email-rodrigo.v...@intel.com ?
-Chris
--
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Re: [Intel-gfx] [PATCH 04/11] drm/i915: Extend GET_APERTURE ioctl to report available map space
On Wed, Jan 28, 2015 at 10:59:28AM +0100, Daniel Vetter wrote: Do we have the libdrm patch for this too? Imo there's not much use in this if mesa remains broken, especially since this is for gen2/3 ... most DE use gl nowadays. On the other hand, there is a bug report open for mesa being broken in how it determines the aperture size that is causing an X crash. So maybe I should fix it up anyway. Hard to do without such a patch. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Avoid GPU hang when coming out of S3 or S4
On Wed, Apr 29, 2015 at 02:07:19PM +0300, David Weinehall wrote: On Tue, Apr 28, 2015 at 03:46:46PM +0100, Chris Wilson wrote: On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote: So is the plan to push these patches and have follow-on work to cover the other paths? As this fixes the Bugzilla issue that has been raised. You've identified an issue, but I think your patch is incomplete. I've tried my best to go through the remaining similar-looking code, but the rest seems fine (I might've missed something though). The only thing I reacted on was that in intel_runtime_resume() the call to intel_init_pch_refclk() is conditional on IS_GEN6(), but none of the other invocations of intel_init_pch_refclk() are. The commit message doesn't seem to provide a sufficient explanation for why this is so. The explanation for moving init_hw() was that it setups clock_gating. If any in that path are required for enabling the rings, those should be move to init_render_ring() or the init_context. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt/gem_create_stolen: Verifying extended gem_create ioctl
On Wed, Apr 29, 2015 at 03:02:20PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be specified, i.e. either
shmem or stolen memory.
These testcases include functional tests and interface tests for
testing the gem_create ioctl call for stolen memory placement
v2: Testing pread/pwrite functionality for stolen backed objects,
added local struct for extended gem_create and gem_get_aperture,
until headers catch up (Chris)
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
lib/ioctl_wrappers.c | 88 +++
lib/ioctl_wrappers.h | 28
tests/Makefile.sources| 1 +
tests/gem_create_stolen.c | 392
++
tests/gem_pread.c | 43 +
tests/gem_pwrite.c| 42 +
6 files changed, 594 insertions(+)
create mode 100644 tests/gem_create_stolen.c
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index ff78ef1..5980067 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -379,6 +379,57 @@ void gem_sync(int fd, uint32_t handle)
gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
}
+bool gem_create__has_stolen_support(int fd)
+{
+ static int has_stolen_support = -1;
+ struct drm_i915_getparam gp;
+ int val = -1;
+
+ if (has_stolen_support 0) {
+ memset(gp, 0, sizeof(gp));
+ gp.param = 35; /* CREATE_VERSION */
+ gp.value = val;
+
+ /* Do we have the extended gem_create_ioctl? */
+ ioctl(fd, DRM_IOCTL_I915_GETPARAM, gp);
+ has_stolen_support = val = 1;
+ }
+
+ return has_stolen_support;
+}
+
+#define LOCAL_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct local_i915_gem_create_v2)
+/**
+ * gem_create_stolen:
+ * @fd: open i915 drm file descriptor
+ * @size: desired size of the buffer
+ * @flags: desired placement i.e. stolen or shmem
+ *
+ * This wraps the new GEM_CREATE ioctl, which allocates a
+ * new gem buffer object of @size and placement based on @flags.
+ *
+ * Returns: The file-private handle of the created buffer object
+ */
+
+uint32_t gem_create_stolen(int fd, int size, uint32_t flags)
+{
+ struct local_i915_gem_create_v2 create;
+ int ret;
With a name like gem_create_stolen() I expect it to only create a stolen
obj i.e. always set create.flags = I915_GEM_CREATE_STOLEN.
+ memset(create, 0, sizeof(create));
+ create.handle = 0;
+ create.size = size;
+ create.flags = flags;
+ ret = drmIoctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, create);
The default behaviour is for gem_create() to die if it fails (and so
cause a FAIL, we do explicit checks to skip the test if we don't have
kernel support beforehand). That saves all the various igt_assert()
noise you have in your test cases.
+
+ if (ret 0)
+ return 0;
+
+ errno = 0;
+ return create.handle;
+}
uint32_t __gem_create(int fd, int size)
{
struct drm_i915_gem_create create;
@@ -1016,6 +1067,43 @@ uint64_t gem_mappable_aperture_size(void)
return pci_dev-regions[bar].size;
}
+#define LOCAL_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_APERTURE, struct local_i915_gem_get_aperture_v2)
+/**
+ * gem_stolen_size:
+ *
+ * Feature test macro to query the total size of the stolen region
+ *
+ * Returns: The total size of the stolen region
+ */
+uint64_t gem_stolen_size(fd)
+{
+ struct local_i915_gem_get_aperture_v2 aperture;
+
+ memset(aperture, 0, sizeof(aperture));
+ aperture.aper_size = 256*1024*1024;
Ah, there's no point initializing aperture.aper_size since we don't
return it in case of ioctl failure anyway.
+ do_ioctl(fd, LOCAL_IOCTL_I915_GEM_GET_APERTURE, aperture);
+
+ return aperture.stolen_size;
+}
+
+/**
+ * gem_available_stolen_size:
+ *
+ * Feature test macro to query the available size in the stolen region
+ *
+ * Returns: The available size in the stolen region
+ */
+uint64_t gem_available_stolen_size(fd)
+{
+ struct local_i915_gem_get_aperture_v2 aperture;
+
+ memset(aperture, 0, sizeof(aperture));
+ aperture.aper_size = 256*1024*1024;
Ditto.
+ do_ioctl(fd, LOCAL_IOCTL_I915_GEM_GET_APERTURE, aperture);
+
+ return aperture.stolen_available_size;
+}
+
/**
* gem_require_caching:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ced7ef3..af76af0 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -56,6 +56,16 @@ void gem_read(int fd, uint32_t handle, uint32_t offset,
void *buf, uint32_t leng
void gem_set_domain(int fd, uint32_t handle,
[Intel-gfx] [PATCH] drm/i915/hdmi: fix vlv infoframe port check
Due to missing shifting, the vlv infoframe port check only works for port A. Fix it. Broken since introduction in commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Author: Jesse Barnes jbar...@virtuousgeek.org Date: Wed Apr 15 16:52:29 2015 -0700 drm/i915/vlv: check port in infoframe_enabled v2 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90059 Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e63f0b9260e9..7774ca2b9bdf 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -327,9 +327,8 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder) struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = VLV_TVIDEO_DIP_CTL(intel_crtc-pipe); u32 val = I915_READ(reg); - u32 port = intel_dig_port-port; - if (port == (val VIDEO_DIP_PORT_MASK)) + if (VIDEO_DIP_PORT(intel_dig_port-port) == (val VIDEO_DIP_PORT_MASK)) return val VIDEO_DIP_ENABLE; return false; -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Support for pread/pwrite from/to non shmem backed objects
On Wed, Apr 29, 2015 at 11:19:18AM +0100, Chris Wilson wrote:
On Wed, Apr 29, 2015 at 03:01:58PM +0530, ankitprasad.r.sha...@intel.com
wrote:
+ while (remain 0) {
+ /* Operation in this page
+*
+* page_base = page offset within aperture
+* page_offset = offset within page
+* page_length = bytes to copy for this page
+*/
+ page_base = offset PAGE_MASK;
+ page_offset = offset_in_page(offset);
+ page_length = remain;
+ if ((page_offset + remain) PAGE_SIZE)
+ page_length = PAGE_SIZE - page_offset;
+
+ /* This is a slow read/write as it tries to read from
+* and write to user memory which may result into page
+* faults
+*/
Hmm, I am in the process of rewriting this function (GTT pwrite) to reduce
aperture pressure (which will also be important here). However for your
use case, we do need to drop the locks around slow_user_access() so that
we can use non-atomic copy functions and *pagefault*. We do need the full
level of complexity like i915_gem_shmem_pread()
It would be a good exercise to try and reproduce the fautling failure condition
with igt/gem_stolen.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Avoid GPU hang when coming out of S3 or S4
On Tue, Apr 28, 2015 at 03:46:46PM +0100, Chris Wilson wrote: On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote: So is the plan to push these patches and have follow-on work to cover the other paths? As this fixes the Bugzilla issue that has been raised. You've identified an issue, but I think your patch is incomplete. I've tried my best to go through the remaining similar-looking code, but the rest seems fine (I might've missed something though). The only thing I reacted on was that in intel_runtime_resume() the call to intel_init_pch_refclk() is conditional on IS_GEN6(), but none of the other invocations of intel_init_pch_refclk() are. The commit message doesn't seem to provide a sufficient explanation for why this is so. Regards, David ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Silence compiler warning in dvo
On Mon, 27 Apr 2015, Dave Gordon david.s.gor...@intel.com wrote: On 27/04/15 16:32, Chris Wilson wrote: drivers/gpu/drm/i915/intel_dvo.c: In function ‘intel_dvo_init’: drivers/gpu/drm/i915/intel_dvo.c:531:8: warning: array subscript is above array bounds [-Warray-bounds] I found this one too, so: Reviewed-by: Dave Gordon david.s.gor...@intel.com Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Ville Syrjälä ville.syrj...@linux.intel.com Pushed to drm-intel-next-queued, thanks for the patch and review. BR, Jani. --- drivers/gpu/drm/i915/intel_dvo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 7c9f85285aea..ece5bd754f85 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -496,7 +496,7 @@ void intel_dvo_init(struct drm_device *dev) int gpio; bool dvoinit; enum pipe pipe; -uint32_t dpll[2]; +uint32_t dpll[I915_MAX_PIPES]; /* Allow the I2C driver info to specify the GPIO to be used in * special cases, but otherwise default to what's defined ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] backlight: Do not hang forever if helper pid is -1
On Wed, Apr 29, 2015 at 11:19:47AM +0200, Olivier Fourdan wrote: Backlight helper PID is set to -1 by default, if for some reason it's not set, we may end up with waitpid(-1, ...) which will hang forever. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90230 Signed-off-by: Olivier Fourdan ofour...@redhat.com Nice catch. Pushed with thanks, 1a67dac..e7016d3 master - master -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] atom D525 trouble
On Tue, Apr 28, 2015 at 11:46:59AM +0100, Patrick Welche wrote: In ancient pre-KMS times, I was able to get a particular pineview-based (Atom D525) desktop computer monitor to run at decent resolutions. Recently, I have tried the 2.99.917 snapshot, and the best I can manage is 1024x768. Bad parts of the system are: - the monitor's EDID is invalid - it presents a - low resolution LVDS connected to a DVI socket(!) - a high resolution VGA connector It used to be sufficient simply to Section Monitor Identifier VGA Option Ignore false EndSection Section Monitor Identifier LVDS Option Ignore true EndSection Section Monitor Identifier LVDS-1 Option Ignore true EndSection in xorg.conf. How is the connector / resolution meant to be selected (what are the rules)? If we cannot inherit a config, one is chosen such that a similar pixel size is presented across all outputs - a cloned config. Any hints on where to look / how to improve the situation? First try kernel cmdline video=LVDS-1:d to disable the spurious LVDS-DVI connection (I am sorry it will never work with the current code without some hacks as we stongly expect a LVDS connection to be a laptop panel). To fixup the missing EDID, either find a genuine one for your panel (or fake one) and use drm_kms_helper.edid_firmware=VGA-1:my-edid.bin or provide sufficent Modelines in either your xorg.conf or through xrandr. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Setup static bias for GPU
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Matches the spec. Whether the chosen bias is really the best, I can't
really say. But favoring the GPU does seem like a sensible idea if we
want to keep the UI stuff fluid enough while there's some CPU heavy
tasks running at the same time.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36805b6..048987e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -670,6 +670,12 @@ enum skl_disp_power_wells {
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf800
+#define VLV_TURBO_SOC_OVERRIDE 0x04
+#define VLV_OVERRIDE_EN 1
+#define VLV_SOC_TDP_EN (1 1)
+#define VLV_BIAS_CPU_125_SOC_875 (6 2)
+#define CHV_BIAS_CPU_50_SOC_50 (3 2)
+
#define VLV_CZ_CLOCK_TO_MILLI_SEC10
/* vlv2 north clock has */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78c89ff..3689d0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device
*dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_EN |
+ VLV_SOC_TDP_EN |
+ CHV_BIAS_CPU_50_SOC_50;
+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
@@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device
*dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_EN |
+ VLV_SOC_TDP_EN |
+ VLV_BIAS_CPU_125_SOC_875;
+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
--
1.9.1
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: Support for pread/pwrite from/to non shmem backed objects
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr objects it is still forbidden.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 125 +---
2 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21a2b1f..a568cd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3270,4 +3270,11 @@ static inline void i915_trace_irq_get(struct
intel_engine_cs *ring,
i915_gem_request_assign(ring-trace_irq_req, req);
}
+/* Checking if pread/pwrite is allowed for the object */
+inline static bool i915_gem_obj_is_prw_allowed(struct drm_i915_gem_object *obj)
+{
+ /* pread/pwrite is forbidden for userptrs */
+ return !obj-userptr.mm;
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 81c5381..3491bd3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -631,6 +631,96 @@ shmem_pread_slow(struct page *page, int shmem_page_offset,
int page_length,
return ret ? - EFAULT : 0;
}
+static inline int
+slow_user_access(struct io_mapping *mapping,
+loff_t page_base, int page_offset,
+char __user *user_data,
+int length, bool write)
+{
+ void __iomem *vaddr_inatomic;
+ void *vaddr;
+ unsigned long unwritten;
+
+ vaddr_inatomic = io_mapping_map_wc(mapping, page_base);
+ /* We can use the cpu mem copy function because this is X86. */
+ vaddr = (void __force *)vaddr_inatomic + page_offset;
+ if (write)
+ unwritten = __copy_from_user(vaddr, user_data, length);
+ else
+ unwritten = __copy_to_user(user_data, vaddr, length);
+
+ io_mapping_unmap(vaddr_inatomic);
+ return unwritten;
+}
+
+static int
+i915_gem_gtt_pread_pwrite(struct drm_device *dev,
+ struct drm_i915_gem_object *obj, uint64_t size,
+ uint64_t data_offset, uint64_t data_ptr, bool write)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ char __user *user_data;
+ ssize_t remain;
+ loff_t offset, page_base;
+ int page_offset, page_length, ret = 0;
+
+ ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
+ if (ret)
+ goto out;
+
+ ret = i915_gem_object_set_to_gtt_domain(obj, write);
+ if (ret)
+ goto out_unpin;
+
+ ret = i915_gem_object_put_fence(obj);
+ if (ret)
+ goto out_unpin;
+
+ user_data = to_user_ptr(data_ptr);
+ remain = size;
+
+ offset = i915_gem_obj_ggtt_offset(obj) + data_offset;
+
+ if (write)
+ intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
+
+ while (remain 0) {
+ /* Operation in this page
+*
+* page_base = page offset within aperture
+* page_offset = offset within page
+* page_length = bytes to copy for this page
+*/
+ page_base = offset PAGE_MASK;
+ page_offset = offset_in_page(offset);
+ page_length = remain;
+ if ((page_offset + remain) PAGE_SIZE)
+ page_length = PAGE_SIZE - page_offset;
+
+ /* This is a slow read/write as it tries to read from
+* and write to user memory which may result into page
+* faults
+*/
+ ret = slow_user_access(dev_priv-gtt.mappable, page_base,
+ page_offset, user_data,
+ page_length, write);
+
+ if (ret) {
+ ret = -EINVAL;
+ break;
+ }
+
+ remain -= page_length;
+ user_data += page_length;
+ offset += page_length;
+ }
+
+out_unpin:
+ i915_gem_object_ggtt_unpin(obj);
+out:
+ return ret;
+}
+
static int
i915_gem_shmem_pread(struct drm_device *dev,
struct drm_i915_gem_object *obj,
@@ -754,17 +844,24 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
goto out;
}
- /* prime objects have no backing filp to GEM pread/pwrite
-* pages from.
-*/
- if (!obj-base.filp) {
+ if (!i915_gem_obj_is_prw_allowed(obj)) {
ret = -EINVAL;
goto out;
}
trace_i915_gem_object_pread(obj, args-offset,
[Intel-gfx] [PATCH 1/5] drm/i915: Clearing buffer objects via blitter engine
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
v2: Add support for using execlists PPGTT
v3: Fix issues in legacy ringbuffer submission mode
testcase: igt/gem_create_stolen
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_gem_exec.c | 197 +++
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.h | 2 +
5 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_exec.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a69002e..711a87d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,6 +25,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_debug.o \
i915_gem_dmabuf.o \
i915_gem_evict.o \
+ i915_gem_exec.o \
i915_gem_execbuffer.o \
i915_gem_gtt.o \
i915_gem.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eb38cd1..21a2b1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2927,6 +2927,10 @@ int __must_check i915_gem_evict_something(struct
drm_device *dev,
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
int i915_gem_evict_everything(struct drm_device *dev);
+/* i915_gem_exec.c */
+int i915_gem_exec_clear_object(struct drm_i915_gem_object *obj,
+ struct drm_i915_file_private *file_priv);
+
/* belongs in i915_gem_gtt.h */
static inline void i915_gem_chipset_flush(struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_exec.c
b/drivers/gpu/drm/i915/i915_gem_exec.c
new file mode 100644
index 000..224bd5f
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_exec.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Chris Wilson chris at chris-wilson.co.uk
+ *
+ */
+
+#include drm/drmP.h
+#include drm/i915_drm.h
+#include i915_drv.h
+
+#define GEN8_COLOR_BLT_CMD (229 | 0x5022)
+
+#define BPP_8 0
+#define BPP_16 (124)
+#define BPP_32 (125 | 124)
+
+#define ROP_FILL_COPY (0xf0 16)
+
+static int i915_gem_exec_flush_object(struct drm_i915_gem_object *obj,
+ struct intel_engine_cs *ring,
+ struct intel_context *ctx)
+{
+ int ret;
+ struct intel_ringbuffer *ringbuf = ctx-engine[ring-id].ringbuf;
+
+ ret = i915_gem_object_sync(obj, ring);
+ if (ret)
+ return ret;
+
+ if (obj-base.write_domain I915_GEM_DOMAIN_CPU) {
+ if (i915_gem_clflush_object(obj, false))
+ i915_gem_chipset_flush(obj-base.dev);
+ obj-base.write_domain = ~I915_GEM_DOMAIN_CPU;
+ }
+ if (obj-base.write_domain I915_GEM_DOMAIN_GTT) {
+ wmb();
+ obj-base.write_domain = ~I915_GEM_DOMAIN_GTT;
+ }
+
+
+ return i915.enable_execlists ?
+ logical_ring_invalidate_all_caches(ringbuf, ctx) :
+ intel_ring_invalidate_all_caches(ring);
+}
+
+static void i915_gem_exec_dirty_object(struct drm_i915_gem_object *obj,
+ struct intel_engine_cs *ring,
+ struct i915_address_space *vm)
+{
+ struct drm_i915_gem_request *req;
+ req = intel_ring_get_request(ring);
+
+ i915_gem_request_assign(obj-last_write_req, req);
+
[Intel-gfx] [PATCH] igt/gem_create_stolen: Verifying extended gem_create ioctl
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be specified, i.e. either
shmem or stolen memory.
These testcases include functional tests and interface tests for
testing the gem_create ioctl call for stolen memory placement
v2: Testing pread/pwrite functionality for stolen backed objects,
added local struct for extended gem_create and gem_get_aperture,
until headers catch up (Chris)
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
lib/ioctl_wrappers.c | 88 +++
lib/ioctl_wrappers.h | 28
tests/Makefile.sources| 1 +
tests/gem_create_stolen.c | 392 ++
tests/gem_pread.c | 43 +
tests/gem_pwrite.c| 42 +
6 files changed, 594 insertions(+)
create mode 100644 tests/gem_create_stolen.c
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index ff78ef1..5980067 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -379,6 +379,57 @@ void gem_sync(int fd, uint32_t handle)
gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
}
+bool gem_create__has_stolen_support(int fd)
+{
+ static int has_stolen_support = -1;
+ struct drm_i915_getparam gp;
+ int val = -1;
+
+ if (has_stolen_support 0) {
+ memset(gp, 0, sizeof(gp));
+ gp.param = 35; /* CREATE_VERSION */
+ gp.value = val;
+
+ /* Do we have the extended gem_create_ioctl? */
+ ioctl(fd, DRM_IOCTL_I915_GETPARAM, gp);
+ has_stolen_support = val = 1;
+ }
+
+ return has_stolen_support;
+}
+
+#define LOCAL_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct local_i915_gem_create_v2)
+/**
+ * gem_create_stolen:
+ * @fd: open i915 drm file descriptor
+ * @size: desired size of the buffer
+ * @flags: desired placement i.e. stolen or shmem
+ *
+ * This wraps the new GEM_CREATE ioctl, which allocates a
+ * new gem buffer object of @size and placement based on @flags.
+ *
+ * Returns: The file-private handle of the created buffer object
+ */
+
+uint32_t gem_create_stolen(int fd, int size, uint32_t flags)
+{
+ struct local_i915_gem_create_v2 create;
+ int ret;
+
+ memset(create, 0, sizeof(create));
+ create.handle = 0;
+ create.size = size;
+ create.flags = flags;
+ ret = drmIoctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, create);
+
+ if (ret 0)
+ return 0;
+
+ errno = 0;
+ return create.handle;
+}
+
+
uint32_t __gem_create(int fd, int size)
{
struct drm_i915_gem_create create;
@@ -1016,6 +1067,43 @@ uint64_t gem_mappable_aperture_size(void)
return pci_dev-regions[bar].size;
}
+#define LOCAL_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_APERTURE, struct local_i915_gem_get_aperture_v2)
+/**
+ * gem_stolen_size:
+ *
+ * Feature test macro to query the total size of the stolen region
+ *
+ * Returns: The total size of the stolen region
+ */
+uint64_t gem_stolen_size(fd)
+{
+ struct local_i915_gem_get_aperture_v2 aperture;
+
+ memset(aperture, 0, sizeof(aperture));
+ aperture.aper_size = 256*1024*1024;
+ do_ioctl(fd, LOCAL_IOCTL_I915_GEM_GET_APERTURE, aperture);
+
+ return aperture.stolen_size;
+}
+
+/**
+ * gem_available_stolen_size:
+ *
+ * Feature test macro to query the available size in the stolen region
+ *
+ * Returns: The available size in the stolen region
+ */
+uint64_t gem_available_stolen_size(fd)
+{
+ struct local_i915_gem_get_aperture_v2 aperture;
+
+ memset(aperture, 0, sizeof(aperture));
+ aperture.aper_size = 256*1024*1024;
+ do_ioctl(fd, LOCAL_IOCTL_I915_GEM_GET_APERTURE, aperture);
+
+ return aperture.stolen_available_size;
+}
+
/**
* gem_require_caching:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ced7ef3..af76af0 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -56,6 +56,16 @@ void gem_read(int fd, uint32_t handle, uint32_t offset, void
*buf, uint32_t leng
void gem_set_domain(int fd, uint32_t handle,
uint32_t read_domains, uint32_t write_domain);
void gem_sync(int fd, uint32_t handle);
+
+struct local_i915_gem_create_v2 {
+ uint64_t size;
+ uint32_t handle;
+ uint32_t pad;
+#define I915_CREATE_PLACEMENT_STOLEN (10)
+ uint32_t flags;
+};
+bool gem_create__has_stolen_support(int fd);
+uint32_t gem_create_stolen(int fd, int size, uint32_t flags);
uint32_t __gem_create(int fd, int size);
uint32_t gem_create(int fd, int size);
void gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
@@ -67,6 +77,15 @@ bool gem_mmap__has_wc(int fd);
void *gem_mmap__wc(int fd, uint32_t handle, int
[Intel-gfx] [PATCH 3/5] drm/i915: Add support for stealing purgable stolen pages
From: Chris Wilson ch...@chris-wilson.co.uk
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when binding
a new object - and you will be forgiven for thinking that the code looks
very similar.
At the moment, we do not allow userspace to allocate objects in stolen,
so there is neither the memory pressure to trigger stolen eviction nor
any purgeable objects inside the stolen arena. However, this will change
in the near future, and so better management and defragmentation of
stolen memory will become a real issue.
v2: Remember to remove the drm_mm_node.
testcase: igt/gem_create_stolen
Signed-off-by: Chris Wilson c...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 121 ++---
1 file changed, 110 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f8da716..0a38d71 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -430,18 +430,29 @@ cleanup:
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_device *dev, u32 size)
+static bool mark_free(struct drm_i915_gem_object *obj, struct list_head
*unwind)
+{
+ if (obj-stolen == NULL)
+ return false;
+
+ if (obj-madv != I915_MADV_DONTNEED)
+ return false;
+
+ if (i915_gem_obj_is_pinned(obj))
+ return false;
+
+ list_add(obj-obj_exec_link, unwind);
+ return drm_mm_scan_add_block(obj-stolen);
+}
+
+static struct drm_mm_node *
+stolen_alloc(struct drm_i915_private *dev_priv, u32 size)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
+ struct drm_i915_gem_object *obj;
+ struct list_head unwind, evict;
int ret;
- if (!drm_mm_initialized(dev_priv-mm.stolen))
- return NULL;
-
- DRM_DEBUG_KMS(creating stolen object: size=%x\n, size);
if (size == 0)
return NULL;
@@ -451,11 +462,99 @@ i915_gem_object_create_stolen(struct drm_device *dev, u32
size)
ret = drm_mm_insert_node(dev_priv-mm.stolen, stolen, size,
4096, DRM_MM_SEARCH_DEFAULT);
- if (ret) {
- kfree(stolen);
- return NULL;
+ if (ret == 0)
+ return stolen;
+
+ /* No more stolen memory available, or too fragmented.
+* Try evicting purgeable objects and search again.
+*/
+
+ drm_mm_init_scan(dev_priv-mm.stolen, size, 4096, 0);
+ INIT_LIST_HEAD(unwind);
+
+ list_for_each_entry(obj, dev_priv-mm.unbound_list, global_list)
+ if (mark_free(obj, unwind))
+ goto found;
+
+ list_for_each_entry(obj, dev_priv-mm.bound_list, global_list)
+ if (mark_free(obj, unwind))
+ goto found;
+
+found:
+ INIT_LIST_HEAD(evict);
+ while (!list_empty(unwind)) {
+ obj = list_first_entry(unwind,
+ struct drm_i915_gem_object,
+ obj_exec_link);
+ list_del_init(obj-obj_exec_link);
+
+ if (drm_mm_scan_remove_block(obj-stolen)) {
+ list_add(obj-obj_exec_link, evict);
+ drm_gem_object_reference(obj-base);
+ }
}
+ ret = 0;
+ while (!list_empty(evict)) {
+ obj = list_first_entry(evict,
+ struct drm_i915_gem_object,
+ obj_exec_link);
+ list_del_init(obj-obj_exec_link);
+
+ if (ret == 0) {
+ struct i915_vma *vma, *vma_next;
+
+ list_for_each_entry_safe(vma, vma_next,
+obj-vma_list,
+vma_link)
+ if (i915_vma_unbind(vma))
+ break;
+
+ /* Stolen pins its pages to prevent the
+* normal shrinker from processing stolen
+* objects.
+*/
+ i915_gem_object_unpin_pages(obj);
+
+ ret = i915_gem_object_put_pages(obj);
+ if (ret == 0) {
+ i915_gem_object_release_stolen(obj);
+ obj-madv = __I915_MADV_PURGED;
+ } else
+ i915_gem_object_pin_pages(obj);
+ }
+
+
[Intel-gfx] [PATCH 2/5] drm/i915: Support for creating Stolen memory backed objects
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be made to allocate
the object from stolen memory subject to the availability of
free space in the stolen region.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 31 +++
include/uapi/drm/i915_drm.h | 15 +++
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d49ed68..491c91f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -163,6 +163,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
if (!value)
return -ENODEV;
break;
+ case I915_PARAM_CREATE_VERSION:
+ value = 1;
+ break;
default:
DRM_DEBUG(Unknown parameter %d\n, param-param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 84e2a23..81c5381 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -391,7 +391,8 @@ static int
i915_gem_create(struct drm_file *file,
struct drm_device *dev,
uint64_t size,
- uint32_t *handle_p)
+ uint32_t *handle_p,
+ uint32_t flags)
{
struct drm_i915_gem_object *obj;
int ret;
@@ -401,8 +402,29 @@ i915_gem_create(struct drm_file *file,
if (size == 0)
return -EINVAL;
+ if (flags ~(I915_CREATE_PLACEMENT_STOLEN))
+ return -EINVAL;
+
/* Allocate the new object */
- obj = i915_gem_alloc_object(dev, size);
+ if (flags I915_CREATE_PLACEMENT_STOLEN) {
+ mutex_lock(dev-struct_mutex);
+ obj = i915_gem_object_create_stolen(dev, size);
+ if (!obj) {
+ mutex_unlock(dev-struct_mutex);
+ return -ENOMEM;
+ }
+
+ ret = i915_gem_exec_clear_object(obj, file-driver_priv);
+ if (ret) {
+ i915_gem_object_free(obj);
+ mutex_unlock(dev-struct_mutex);
+ return ret;
+ }
+
+ mutex_unlock(dev-struct_mutex);
+ } else
+ obj = i915_gem_alloc_object(dev, size);
+
if (obj == NULL)
return -ENOMEM;
@@ -425,7 +447,7 @@ i915_gem_dumb_create(struct drm_file *file,
args-pitch = ALIGN(args-width * DIV_ROUND_UP(args-bpp, 8), 64);
args-size = args-pitch * args-height;
return i915_gem_create(file, dev,
- args-size, args-handle);
+ args-size, args-handle, 0);
}
/**
@@ -438,7 +460,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_create *args = data;
return i915_gem_create(file, dev,
- args-size, args-handle);
+ args-size, args-handle,
+ args-flags);
}
static inline int
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 8d1be90..ab4f3a9 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -350,6 +350,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_REVISION 32
#define I915_PARAM_SUBSLICE_TOTAL 33
#define I915_PARAM_EU_TOTAL 34
+#define I915_PARAM_CREATE_VERSION 35
typedef struct drm_i915_getparam {
int param;
@@ -445,6 +446,20 @@ struct drm_i915_gem_create {
*/
__u32 handle;
__u32 pad;
+ /**
+* Requested flags (currently used for placement
+* (which memory domain))
+*
+* You can request that the object be created from special memory
+* rather than regular system pages using this parameter. Such
+* irregular objects may have certain restrictions (such as CPU
+* access to a stolen object is verboten).
+*
+* This can be used in the future for other purposes too
+* e.g. specifying tiling/caching/madvise
+*/
+ __u32 flags;
+#define I915_CREATE_PLACEMENT_STOLEN (10) /* Cannot use CPU mmaps or
pread/pwrite */
};
struct drm_i915_gem_pread {
--
1.9.1
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[Intel-gfx] [PATCH 5/5] drm/i915: Add support for getting size of the stolen region
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch extends the get_aperture_ioctl to add support
for getting total size of the stolen region and available
size of the stolen region.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_gem.c | 15 ++-
include/uapi/drm/i915_drm.h | 6 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a568cd1..a40b44f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3277,4 +3277,10 @@ inline static bool i915_gem_obj_is_prw_allowed(struct
drm_i915_gem_object *obj)
return !obj-userptr.mm;
}
+inline static bool i915_gem_obj_is_stolen_used(struct drm_i915_gem_object *obj)
+{
+ return obj-stolen (i915_gem_obj_is_pinned(obj)
+ || obj-madv == I915_MADV_WILLNEED);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3491bd3..ee93508 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -150,17 +150,30 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_gem_get_aperture *args = data;
struct drm_i915_gem_object *obj;
- size_t pinned;
+ size_t pinned, pinned_stolen;
pinned = 0;
+ pinned_stolen = 0;
mutex_lock(dev-struct_mutex);
list_for_each_entry(obj, dev_priv-mm.bound_list, global_list)
if (i915_gem_obj_is_pinned(obj))
pinned += i915_gem_obj_ggtt_size(obj);
+
+ /* Calculating available stolen size */
+ list_for_each_entry(obj, dev_priv-mm.bound_list, global_list)
+ if (i915_gem_obj_is_stolen_used(obj))
+ pinned_stolen += i915_gem_obj_ggtt_size(obj);
+
+ list_for_each_entry(obj, dev_priv-mm.unbound_list, global_list)
+ if (i915_gem_obj_is_stolen_used(obj))
+ pinned_stolen += i915_gem_obj_ggtt_size(obj);
+
mutex_unlock(dev-struct_mutex);
args-aper_size = dev_priv-gtt.base.total;
args-aper_available_size = args-aper_size - pinned;
+ args-stolen_size = dev_priv-gtt.stolen_size;
+ args-stolen_available_size = args-stolen_size - pinned_stolen;
return 0;
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ab4f3a9..49766b8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -932,6 +932,12 @@ struct drm_i915_gem_get_aperture {
* bytes
*/
__u64 aper_available_size;
+
+ /** Total size of the stolen region, in bytes */
+ __u64 stolen_size;
+
+ /* Available space in the stolen region, in bytes */
+ __u64 stolen_available_size;
};
struct drm_i915_get_pipe_from_crtc_id {
--
1.9.1
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[Intel-gfx] [PATCH v2 0/5] Support for creating/using Stolen memory backed objects
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com This patch series adds support for creating/using Stolen memory backed objects. Despite being a unified memory architecture (UMA) some bits of memory are more equal than others. In particular we have the thorny issue of stolen memory, memory stolen from the system by the BIOS and reserved for igfx use. Stolen memory is required for some functions of the GPU and display engine, but in general it goes wasted. Whilst we cannot return it back to the system, we need to find some other method for utilising it. As we do not support direct access to the physical address in the stolen region, it behaves like a different class of memory, closer in kin to local GPU memory. This strongly suggests that we need a placement model like TTM if we are to fully utilize these discrete chunks of differing memory. To add support for creating Stolen memory backed objects, we extend the drm_i915_gem_create structure, by adding a new flag through which user can specify the preference to allocate the object from stolen memory, which if set, an attempt will be made to allocate the object from stolen memory subject to the availability of free space in the stolen region. This patch series adds support for clearing buffer objects via blitter engines. This is particularly useful for clearing out the memory from stolen region, but can also be used for other shmem allocated objects. Also adding support for stealing purgable stolen pages, if we run out of stolen memory when trying to allocate an object. This also adds support for read/write from/to objects not backed by shmem using the pread/pwrite interface. Series also extends the current get_aperture ioctl to retrieve the total and available size of the stolen region This can be verified using IGT tests: igt/gem_create_stolen Ankitprasad Sharma (4): drm/i915: Clearing buffer objects via blitter engine drm/i915: Support for creating Stolen memory backed objects drm/i915: Support for pread/pwrite from/to non shmem backed objects drm/i915: Add support for getting size of the stolen region Chris Wilson (1): drm/i915: Add support for stealing purgable stolen pages drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_dma.c| 3 + drivers/gpu/drm/i915/i915_drv.h| 17 +++ drivers/gpu/drm/i915/i915_gem.c| 171 +--- drivers/gpu/drm/i915/i915_gem_exec.c | 197 + drivers/gpu/drm/i915/i915_gem_stolen.c | 121 ++-- drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_lrc.h | 2 + include/uapi/drm/i915_drm.h| 21 9 files changed, 509 insertions(+), 26 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_exec.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] backlight: Do not hang forever if helper pid is -1
Backlight helper PID is set to -1 by default, if for some reason it's
not set, we may end up with waitpid(-1, ...) which will hang forever.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90230
Signed-off-by: Olivier Fourdan ofour...@redhat.com
---
src/backlight.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/backlight.c b/src/backlight.c
index 84d8f76..c65e466 100644
--- a/src/backlight.c
+++ b/src/backlight.c
@@ -523,7 +523,7 @@ void backlight_disable(struct backlight *b)
void backlight_close(struct backlight *b)
{
backlight_disable(b);
- if (b-pid)
+ if (b-pid 0)
waitpid(b-pid, NULL, 0);
}
--
2.3.6
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[Intel-gfx] [PATCH-V3 2/2] ALSA:hda - reset display codec when power on
From: Lu, Han han...@intel.com
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells,
so it's necessary to reset display audio codecs when power well on, otherwise
display audio codecs will disappear when resume from low power state.
Reset steps when power on:
enable codec wakeup - azx_init_chip() - disable codec wakeup
The callback for codec wakeup enable/disable is in drivers/gpu/drm/i915/.
Signed-off-by: Lu, Han han...@intel.com
diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c
index 3052a2b..fe4f979a 100644
--- a/sound/pci/hda/hda_i915.c
+++ b/sound/pci/hda/hda_i915.c
@@ -33,6 +33,27 @@
#define AZX_REG_EM40x100c
#define AZX_REG_EM50x1010
+int hda_set_codec_wakeup(struct hda_intel *hda, bool enable)
+{
+ struct i915_audio_component *acomp = hda-audio_component;
+
+ if (!acomp-ops)
+ return -ENODEV;
+
+ if (!acomp-ops-codec_wake_override) {
+ dev_warn(hda-chip.pci-dev,
+ Invalid codec wake callback\n);
+ return 0;
+ }
+
+ dev_dbg(hda-chip.pci-dev, %s codec wakeup\n,
+ enable ? enable : disable);
+
+ acomp-ops-codec_wake_override(acomp-dev, enable);
+
+ return 0;
+}
+
int hda_display_power(struct hda_intel *hda, bool enable)
{
struct i915_audio_component *acomp = hda-audio_component;
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 34040d2..f4ed12d 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -491,6 +491,17 @@ static void azx_init_pci(struct azx *chip)
}
}
+static void hda_intel_init_chip(struct azx *chip, bool full_reset)
+{
+ struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
+
+ if (chip-driver_caps AZX_DCAPS_I915_POWERWELL)
+ hda_set_codec_wakeup(hda, true);
+ azx_init_chip(chip, full_reset);
+ if (chip-driver_caps AZX_DCAPS_I915_POWERWELL)
+ hda_set_codec_wakeup(hda, false);
+}
+
/* calculate runtime delay from LPIB */
static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
unsigned int pos)
@@ -827,7 +838,7 @@ static int azx_resume(struct device *dev)
return -EIO;
azx_init_pci(chip);
- azx_init_chip(chip, true);
+ hda_intel_init_chip(chip, true);
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
return 0;
@@ -888,13 +899,16 @@ static int azx_runtime_resume(struct device *dev)
if (chip-driver_caps AZX_DCAPS_I915_POWERWELL) {
hda_display_power(hda, true);
haswell_set_bclk(hda);
+ /* toggle codec wakeup bit for STATESTS read */
+ hda_set_codec_wakeup(hda, true);
+ hda_set_codec_wakeup(hda, false);
}
/* Read STATESTS before controller reset */
status = azx_readw(chip, STATESTS);
azx_init_pci(chip);
- azx_init_chip(chip, true);
+ hda_intel_init_chip(chip, true);
bus = chip-bus;
if (status bus) {
@@ -1588,7 +1602,7 @@ static int azx_first_init(struct azx *chip)
haswell_set_bclk(hda);
}
- azx_init_chip(chip, (probe_only[dev] 2) == 0);
+ hda_intel_init_chip(chip, (probe_only[dev] 2) == 0);
/* codec detection */
if (!chip-codec_mask) {
diff --git a/sound/pci/hda/hda_intel.h b/sound/pci/hda/hda_intel.h
index d5231f7..5d2bb07 100644
--- a/sound/pci/hda/hda_intel.h
+++ b/sound/pci/hda/hda_intel.h
@@ -48,11 +48,16 @@ struct hda_intel {
};
#ifdef CONFIG_SND_HDA_I915
+int hda_set_codec_wakeup(struct hda_intel *hda, bool enable);
int hda_display_power(struct hda_intel *hda, bool enable);
void haswell_set_bclk(struct hda_intel *hda);
int hda_i915_init(struct hda_intel *hda);
int hda_i915_exit(struct hda_intel *hda);
#else
+static inline int hda_set_codec_wakeup(struct hda_intel *hda, bool enable)
+{
+ return 0;
+}
static inline int hda_display_power(struct hda_intel *hda, bool enable)
{
return 0;
--
1.9.1
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[Intel-gfx] [PATCH-V3 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback
From: Lu, Han han...@intel.com
Add support for enabling codec wakeup override signal to allow
re-enumeration of the controller on SKL after resume from low power state.
v3 by Jani: Simplify to only support toggling the appropriate chicken bit.
Signed-off-by: Lu, Han han...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36805b6..435c372 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
#define AUDIO_CP_READY(trans)((1 1) ((trans) * 4))
#define AUDIO_ELD_VALID(trans) ((1 0) ((trans) * 4))
+#define HSW_AUD_CHICKENBIT 0x65f10
+#define SKL_AUD_CODEC_WAKE_SIGNAL(1 15)
+
/* HSW Power Wells */
#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
#define HSW_PWR_WELL_DRIVER0x45404 /* CTL2 */
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index f72e93a..ceb2328 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -474,6 +474,32 @@ static void i915_audio_component_put_power(struct device
*dev)
intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
}
+static void i915_audio_component_codec_wake_override(struct device *dev,
+bool enable)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ u32 tmp;
+
+ if (!IS_SKYLAKE(dev_priv))
+ return;
+
+ /*
+* Enable/disable generating the codec wake signal, overriding the
+* internal logic to generate the codec wake to controller.
+*/
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp = ~SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+
+ if (enable) {
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+ }
+}
+
/* Get CDCLK in kHz */
static int i915_audio_component_get_cdclk_freq(struct device *dev)
{
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops
i915_audio_component_ops = {
.owner = THIS_MODULE,
.get_power = i915_audio_component_get_power,
.put_power = i915_audio_component_put_power,
+ .codec_wake_override = i915_audio_component_codec_wake_override,
.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 3e2f22e..c9a8b64 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -31,6 +31,7 @@ struct i915_audio_component {
struct module *owner;
void (*get_power)(struct device *);
void (*put_power)(struct device *);
+ void (*codec_wake_override)(struct device *, bool enable);
int (*get_cdclk_freq)(struct device *);
} *ops;
};
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915/gtt: Allocate va range only if vma is not bound
On Wed, Apr 29, 2015 at 09:49:30AM +0300, Mika Kuoppala wrote: When we have bound vma into an address space, the layout of page table structures is immutable. So we can be absolutely certain that if vma is already bound, there is no need to (re)allocate a virtual address range for it. v2: - add sanity checks and remove superfluous GLOBAL_BIND set - we might do update for an unbound vma (Chris) v3: s/u32/unsigned (Chris) Go back to v2. Sorry, seems like u32 is being used throughout this callchain and so needs to be fixed all together. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH-V2 1/2] drm/i915: add callback to enable/disable codec wakeup
Hi Jani,
Sorry I didn't find method to access chicken bit registers or any other 0x65000
based registers
through audio mmio bar in ALSA side. It looks like the only way to access i915
registers from audio
side is through i915 callback (please correct me if I was wrong). So I apply
your patch and it works
well. Thanks a lot!
(and yes, in my case, neither refcounting nor locking is must in ALSA side, so
I will not add them this
time.)
BR,
Han Lu
-Original Message-
From: Nikula, Jani
Sent: Tuesday, April 28, 2015 10:22 PM
To: Lu, Han; Vetter, Daniel; ti...@suse.de; Yang, Libin; Lin, Mengdong; intel-
g...@lists.freedesktop.org
Cc: Lu, Han; Deak, Imre
Subject: Re: [PATCH-V2 1/2] drm/i915: add callback to enable/disable codec
wakeup
On Tue, 28 Apr 2015, han...@intel.com wrote:
From: Lu, Han han...@intel.com
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different
power wells, so it's necessary to reset display audio codecs when
power well on, otherwise display audio codecs will disappear when
resume from low power state.
The reset step when power on is:
enable codec wakeup - azx_init_chip() - disable codec wakeup
The callback is defined in drivers/gpu/drm/i915/.
The caller is in sound/pci/hda/.
Han Lu, two more things:
First, is there any chance the chicken bit register is mirrored in the audio
device mmio bar? If yes, you could use it directly in the audio driver, and we
could drop patch 1/2...
Second, looking at the audio driver code for the usage of this callback in
patch
2/2, I don't think the locking and refcounting add any value. Especially since
you ignore the refcounting for disable. You're the only user, and anything
beyond that would be broken anyway, with or without refcounting or locking.
In fact, I'd like to push back the locking and refcounting to audio driver
side,
where you may realize they are not needed at all. Thus, I propose this as
patch 1/2:
From b06bf55b94cdbfad8ec35923b2b657674472cce5 Mon Sep 17 00:00:00
2001
From: Lu, Han han...@intel.com
Date: Tue, 28 Apr 2015 17:03:08 +0300
Subject: [PATCH] drm/i915/audio: add codec wakeup override
enabled/disable callback
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160
Espoo
Cc: Jani Nikula jani.nik...@intel.com
Add support for enabling codec wakeup override signal to allow re-
enumeration of the controller on SKL after resume from low power state.
v3 by Jani: Simplify to only support toggling the appropriate chicken bit.
Signed-off-by: Lu, Han han...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_audio.c | 27 +++
include/drm/i915_component.h | 1 +
3 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h index 36805b64036b..435c372d001e
100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
#define AUDIO_CP_READY(trans) ((1 1) ((trans) * 4))
#define AUDIO_ELD_VALID(trans) ((1 0) ((trans) * 4))
+#define HSW_AUD_CHICKENBIT 0x65f10
+#define SKL_AUD_CODEC_WAKE_SIGNAL (1 15)
+
/* HSW Power Wells */
#define HSW_PWR_WELL_BIOS0x45400 /* CTL1 */
#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index f72e93a45e11..ceb232870d5a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -474,6 +474,32 @@ static void
i915_audio_component_put_power(struct device *dev)
intel_display_power_put(dev_to_i915(dev),
POWER_DOMAIN_AUDIO); }
+static void i915_audio_component_codec_wake_override(struct device
*dev,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ u32 tmp;
+
+ if (!IS_SKYLAKE(dev_priv))
+ return;
+
+ /*
+ * Enable/disable generating the codec wake signal, overriding the
+ * internal logic to generate the codec wake to controller.
+ */
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp = ~SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+
+ if (enable) {
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+ }
+}
+
/* Get CDCLK in kHz */
static int i915_audio_component_get_cdclk_freq(struct device *dev) { @@
-495,6 +521,7 @@ static const struct i915_audio_component_ops
i915_audio_component_ops = {
.owner = THIS_MODULE,
.get_power =
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: DP link training optimization
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is required or not
(based on Sivakumar's comment)
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e0b35cb..bb1a8d0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
intel_dp-DP = DP;
if (channel_eq) {
- intel_dp-train_set_valid = is_edp(intel_dp);
+ intel_dp-train_set_valid = true;
DRM_DEBUG_KMS(Channel EQ done. DP Training successful\n);
}
}
@@ -4843,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
intel_display_power_get(dev_priv, power_domain);
if (long_hpd) {
+ /* indicate that we need to restart link training */
+ intel_dp-train_set_valid = false;
if (HAS_PCH_SPLIT(dev)) {
if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
--
regards,
Sivakumar
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[Intel-gfx] [PATCH] drm/i915/gtt: Allocate va range only if vma is not bound
When we have bound vma into an address space, the layout
of page table structures is immutable. So we can be absolutely
certain that if vma is already bound, there is no need to
(re)allocate a virtual address range for it.
v2: - add sanity checks and remove superfluous GLOBAL_BIND set
- we might do update for an unbound vma (Chris)
v3: s/u32/unsigned (Chris)
Testcase: igt/gem_exec_big #bdw
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Michel Thierry michel.thie...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6fae6bd..85f27d6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1928,8 +1928,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
vma-vm-insert_entries(vma-vm, pages,
vma-node.start,
cache_level, pte_flags);
-
- vma-bound |= GLOBAL_BIND;
}
if (dev_priv-mm.aliasing_ppgtt flags LOCAL_BIND) {
@@ -2804,21 +2802,13 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
u32 flags)
{
- int ret = 0;
- u32 bind_flags = 0;
-
- if (vma-vm-allocate_va_range) {
- trace_i915_va_alloc(vma-vm, vma-node.start,
- vma-node.size,
- VM_TO_TRACE_NAME(vma-vm));
+ int ret;
+ unsigned bind_flags;
- ret = vma-vm-allocate_va_range(vma-vm,
-vma-node.start,
-vma-node.size);
- if (ret)
- return ret;
- }
+ if (WARN_ON(flags == 0))
+ return -EINVAL;
+ bind_flags = 0;
if (flags PIN_GLOBAL)
bind_flags |= GLOBAL_BIND;
if (flags PIN_USER)
@@ -2829,8 +2819,23 @@ int i915_vma_bind(struct i915_vma *vma, enum
i915_cache_level cache_level,
else
bind_flags = ~vma-bound;
- if (bind_flags)
- ret = vma-vm-bind_vma(vma, cache_level, bind_flags);
+ if (bind_flags == 0)
+ return 0;
+
+ if (vma-bound == 0 vma-vm-allocate_va_range) {
+ trace_i915_va_alloc(vma-vm,
+ vma-node.start,
+ vma-node.size,
+ VM_TO_TRACE_NAME(vma-vm));
+
+ ret = vma-vm-allocate_va_range(vma-vm,
+vma-node.start,
+vma-node.size);
+ if (ret)
+ return ret;
+ }
+
+ ret = vma-vm-bind_vma(vma, cache_level, bind_flags);
if (ret)
return ret;
--
1.9.1
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Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: DP link training optimization
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
V2:
- flag that indicates if DP link is trained and valid
renamed from 'link_trained' to 'train_set_valid'
- removed routine 'intel_dp_reuse_link_train'
V3:
- rebased against the latest drm-intel-nightly
V4:
- removed HPD long pulse handling for eDP case to clear the
flag that indicates to reuse the current link training
parameters. (based on Sivakumar's comment)
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 27 ---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 937ba31..e0b35cb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,7 +3547,8 @@ static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
uint8_t dp_train_pat)
{
- memset(intel_dp-train_set, 0, sizeof(intel_dp-train_set));
+ if (!intel_dp-train_set_valid)
+ memset(intel_dp-train_set, 0, sizeof(intel_dp-train_set));
intel_dp_set_signal_levels(intel_dp, DP);
return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}
@@ -3660,6 +3661,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
break;
}
+ /*
+* if we used previously trained voltage and pre-emphasis values
+* and we don't get clock recovery, reset link training values
+*/
+ if (intel_dp-train_set_valid) {
+ DRM_DEBUG_KMS(clock recovery not ok, reset);
+ /* clear the flag as we are not reusing train set */
+ intel_dp-train_set_valid = false;
+ if (!intel_dp_reset_link_train(intel_dp, DP,
+ DP_TRAINING_PATTERN_1 |
+
DP_LINK_SCRAMBLING_DISABLE)) {
+ DRM_ERROR(failed to enable link training\n);
+ return;
+ }
+ continue;
+ }
+
/* Check to see if we've tried the max voltage */
for (i = 0; i intel_dp-lane_count; i++)
if ((intel_dp-train_set[i]
DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -3737,6 +3755,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* Make sure clock is still ok */
if (!drm_dp_clock_recovery_ok(link_status,
intel_dp-lane_count)) {
+ intel_dp-train_set_valid = false;
intel_dp_start_link_train(intel_dp);
intel_dp_set_link_train(intel_dp, DP,
training_pattern |
@@ -3752,6 +3771,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* Try 5 times, then try clock recovery if that fails */
if (tries 5) {
+ intel_dp-train_set_valid = false;
intel_dp_start_link_train(intel_dp);
intel_dp_set_link_train(intel_dp, DP,
training_pattern |
@@ -3773,9 +3793,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
intel_dp-DP = DP;
- if (channel_eq)
+ if (channel_eq) {
+ intel_dp-train_set_valid = is_edp(intel_dp);
DRM_DEBUG_KMS(Channel EQ done. DP Training successful\n);
-
+ }
}
void intel_dp_stop_link_train(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 43fe003..94197bd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -736,6 +736,7 @@ struct intel_dp {
bool has_aux_irq,
int send_bytes,
uint32_t aux_clock_divider);
+ bool train_set_valid;
/* Displayport compliance testing */
unsigned long compliance_test_type;
--
regards,
Sivakumar
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[Intel-gfx] [PATCH v4 2/2] drm/i915: DP link training optimization
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is required or not
(based on Sivakumar's comment)
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e0b35cb..bb1a8d0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
intel_dp-DP = DP;
if (channel_eq) {
- intel_dp-train_set_valid = is_edp(intel_dp);
+ intel_dp-train_set_valid = true;
DRM_DEBUG_KMS(Channel EQ done. DP Training successful\n);
}
}
@@ -4843,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
intel_display_power_get(dev_priv, power_domain);
if (long_hpd) {
+ /* indicate that we need to restart link training */
+ intel_dp-train_set_valid = false;
if (HAS_PCH_SPLIT(dev)) {
if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
--
1.9.1
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[Intel-gfx] [PATCH v4 1/2] drm/i915: DP link training optimization
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
V2:
- flag that indicates if DP link is trained and valid
renamed from 'link_trained' to 'train_set_valid'
- removed routine 'intel_dp_reuse_link_train'
V3:
- rebased against the latest drm-intel-nightly
V4:
- removed HPD long pulse handling for eDP case to clear the
flag that indicates to reuse the current link training
parameters. (based on Sivakumar's comment)
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 27 ---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 937ba31..e0b35cb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,7 +3547,8 @@ static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
uint8_t dp_train_pat)
{
- memset(intel_dp-train_set, 0, sizeof(intel_dp-train_set));
+ if (!intel_dp-train_set_valid)
+ memset(intel_dp-train_set, 0, sizeof(intel_dp-train_set));
intel_dp_set_signal_levels(intel_dp, DP);
return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}
@@ -3660,6 +3661,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
break;
}
+ /*
+* if we used previously trained voltage and pre-emphasis values
+* and we don't get clock recovery, reset link training values
+*/
+ if (intel_dp-train_set_valid) {
+ DRM_DEBUG_KMS(clock recovery not ok, reset);
+ /* clear the flag as we are not reusing train set */
+ intel_dp-train_set_valid = false;
+ if (!intel_dp_reset_link_train(intel_dp, DP,
+ DP_TRAINING_PATTERN_1 |
+
DP_LINK_SCRAMBLING_DISABLE)) {
+ DRM_ERROR(failed to enable link training\n);
+ return;
+ }
+ continue;
+ }
+
/* Check to see if we've tried the max voltage */
for (i = 0; i intel_dp-lane_count; i++)
if ((intel_dp-train_set[i]
DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -3737,6 +3755,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* Make sure clock is still ok */
if (!drm_dp_clock_recovery_ok(link_status,
intel_dp-lane_count)) {
+ intel_dp-train_set_valid = false;
intel_dp_start_link_train(intel_dp);
intel_dp_set_link_train(intel_dp, DP,
training_pattern |
@@ -3752,6 +3771,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* Try 5 times, then try clock recovery if that fails */
if (tries 5) {
+ intel_dp-train_set_valid = false;
intel_dp_start_link_train(intel_dp);
intel_dp_set_link_train(intel_dp, DP,
training_pattern |
@@ -3773,9 +3793,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
intel_dp-DP = DP;
- if (channel_eq)
+ if (channel_eq) {
+ intel_dp-train_set_valid = is_edp(intel_dp);
DRM_DEBUG_KMS(Channel EQ done. DP Training successful\n);
-
+ }
}
void intel_dp_stop_link_train(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 43fe003..94197bd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -736,6 +736,7 @@ struct intel_dp {
bool has_aux_irq,
int send_bytes,
uint32_t aux_clock_divider);
+ bool train_set_valid;
/* Displayport compliance testing */
unsigned long compliance_test_type;
--
1.9.1
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[Intel-gfx] [PATCH v4 0/2] drm/i915: DP link training optimization
This is patch series optimizes DP link training by reusing the link parameter settings if DP link has bee previously trained. In case we are not able to train the link by reusing the known values, the link training parameters are set to zero and training is restarted. The first patch is for eDP only where we reuse the previously trained link training values from cache i.e. voltage swing and pre-emphasis levels. The second patch is a generalization to cover DP case. Mika Kahola (2): drm/i915: DP link training optimization drm/i915: DP link training optimization drivers/gpu/drm/i915/intel_dp.c | 29 ++--- drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 27 insertions(+), 3 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] kms_flip_tiling: New tiling tests, including Y/Yf
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
New subtests to excercise flips from tiled to tiled and from
linear to tiled frame buffers.
These will catch display programming issues like not preserving the
tiling mode in page flips or not re-programming the watermarks.
v2: Cleanup crc object after failing subtests.
v3:
* Wait for page flip completion instead of vblank. (Chris Wilson)
* Added linear-tiled flip tests to catch watermark programming issues.
v4:
* Refactored for less code.
* Check crc after page flip to ensure it happened. (Chris Wilson)
* Skip rather than fail when flip fails. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/kms_flip_tiling.c | 230 ++--
1 file changed, 184 insertions(+), 46 deletions(-)
diff --git a/tests/kms_flip_tiling.c b/tests/kms_flip_tiling.c
index 8345505..c7fd4de 100644
--- a/tests/kms_flip_tiling.c
+++ b/tests/kms_flip_tiling.c
@@ -35,8 +35,7 @@
#include ioctl_wrappers.h
#include intel_chipset.h
-IGT_TEST_DESCRIPTION(Test that a page flip from a tiled buffer to a linear
- one works correctly.);
+IGT_TEST_DESCRIPTION(Test page flips and tiling scenarios);
typedef struct {
int drm_fd;
@@ -44,16 +43,8 @@ typedef struct {
int gen;
} data_t;
-/*
- * Test that a page flip from a tiled buffer to a linear one works
- * correctly. First, it sets the crtc with the linear buffer and generate
- * a reference crc for the pipe. Then, the crtc is set with the tiled one
- * and page flip to the linear one issued. A new crc is generated and
- * compared to the rerence one.
- */
-
static void
-fill_linear_fb(struct igt_fb *fb, data_t *data, drmModeModeInfo *mode)
+fill_fb(struct igt_fb *fb, data_t *data, drmModeModeInfo *mode)
{
cairo_t *cr;
@@ -62,67 +53,124 @@ fill_linear_fb(struct igt_fb *fb, data_t *data,
drmModeModeInfo *mode)
cairo_destroy(cr);
}
+static igt_pipe_crc_t *_pipe_crc;
+
+static igt_pipe_crc_t *pipe_crc_new(int pipe)
+{
+ if (_pipe_crc) {
+ igt_pipe_crc_free(_pipe_crc);
+ _pipe_crc = NULL;
+ }
+
+ _pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+ igt_assert(_pipe_crc);
+
+ return _pipe_crc;
+}
+
+static void pipe_crc_free(void)
+{
+ if (_pipe_crc) {
+ igt_pipe_crc_free(_pipe_crc);
+ _pipe_crc = NULL;
+ }
+}
+
+static void wait_for_pageflip(int fd)
+{
+ drmEventContext evctx = { .version = DRM_EVENT_CONTEXT_VERSION };
+ struct timeval timeout = { .tv_sec = 0, .tv_usec = 32000 };
+ fd_set fds;
+ int ret;
+
+ /* Wait for pageflip completion, then consume event on fd */
+ FD_ZERO(fds);
+ FD_SET(fd, fds);
+ do {
+ ret = select(fd + 1, fds, NULL, NULL, timeout);
+ } while (ret 0 errno == EINTR);
+ igt_assert_eq(ret, 1);
+ igt_assert(drmHandleEvent(fd, evctx) == 0);
+}
+
static void
-test_flip_changes_tiling(data_t *data, igt_output_t *output, uint64_t tiling)
+test_flip_tiling(data_t *data, igt_output_t *output, uint64_t tiling[2])
{
- struct igt_fb linear, tiled;
drmModeModeInfo *mode;
igt_plane_t *primary;
+ struct igt_fb fb[2];
igt_pipe_crc_t *pipe_crc;
igt_crc_t reference_crc, crc;
int fb_id, pipe, ret, width;
pipe = output-config.pipe;
- pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+ pipe_crc = pipe_crc_new(pipe);
igt_output_set_pipe(output, pipe);
mode = igt_output_get_mode(output);
primary = igt_output_get_plane(output, 0);
- /* Allocate a linear buffer. Since a page flip to a buffer with
-* different stride doesn't work, choose width so that the stride of
-* both buffers is the same. */
- width = 512;
- while (width mode-hdisplay)
- width *= 2;
+ width = mode-hdisplay;
+
+ if (tiling[0] != tiling[1]
+ (tiling[0] != LOCAL_DRM_FORMAT_MOD_NONE ||
+tiling[1] != LOCAL_DRM_FORMAT_MOD_NONE)) {
+ /*
+* Since a page flip to a buffer with different stride
+* doesn't work, choose width so that the stride of both
+* buffers is the same.
+*/
+ width = 512;
+ while (width mode-hdisplay)
+ width *= 2;
+ }
+
fb_id = igt_create_fb(data-drm_fd, width, mode-vdisplay,
- DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE,
- linear);
+ DRM_FORMAT_XRGB, tiling[0],
+ fb[0]);
+ igt_assert(fb_id);
+
+ /* Second fb has different background so CRC does not match. */
+ fb_id =
[Intel-gfx] [PATCH i-g-t 1/2] igt_fb: Transfer existing content to Cairo surface for Y/Yf frame buffers
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Rendering into Y and Yf tiled frame buffers with Cairo was losing the
previous content ie. was starting from black. This is different than the
behaviour with linear and X tiled so make it the same by blitting the
initial content when creating the rendering context.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_fb.c | 56
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 6dc22bb..fe0c63f 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -650,11 +650,27 @@ struct fb_blit_upload {
} linear;
};
+static unsigned int fb_mod_to_obj_tiling(uint64_t fb_mod)
+{
+ switch (fb_mod) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ return I915_TILING_NONE;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ return I915_TILING_X;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ return I915_TILING_Y;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ return I915_TILING_Yf;
+ default:
+ igt_assert(0);
+ }
+}
+
static void destroy_cairo_surface__blit(void *arg)
{
struct fb_blit_upload *blit = arg;
struct igt_fb *fb = blit-fb;
- unsigned int obj_tiling = I915_TILING_NONE;
+ unsigned int obj_tiling = fb_mod_to_obj_tiling(fb-tiling);
munmap(blit-linear.map, blit-linear.size);
fb-cairo_surface = NULL;
@@ -662,18 +678,6 @@ static void destroy_cairo_surface__blit(void *arg)
gem_set_domain(blit-fd, blit-linear.handle,
I915_GEM_DOMAIN_GTT, 0);
- switch (fb-tiling) {
- case LOCAL_I915_FORMAT_MOD_X_TILED:
- obj_tiling = I915_TILING_X;
- break;
- case LOCAL_I915_FORMAT_MOD_Y_TILED:
- obj_tiling = I915_TILING_Y;
- break;
- case LOCAL_I915_FORMAT_MOD_Yf_TILED:
- obj_tiling = I915_TILING_Yf;
- break;
- }
-
igt_blitter_fast_copy__raw(blit-fd,
blit-linear.handle,
blit-linear.stride,
@@ -695,6 +699,7 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
{
struct fb_blit_upload *blit;
cairo_format_t cairo_format;
+ unsigned int obj_tiling = fb_mod_to_obj_tiling(fb-tiling);
int bpp, ret;
blit = malloc(sizeof(*blit));
@@ -716,6 +721,28 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
blit-fd = fd;
blit-fb = fb;
+
+ /* Copy fb content to linear BO */
+ gem_set_domain(fd, blit-linear.handle,
+ I915_GEM_DOMAIN_GTT, 0);
+
+ igt_blitter_fast_copy__raw(fd,
+ fb-gem_handle,
+ fb-stride,
+ obj_tiling,
+ 0, 0, /* src_x, src_y */
+ fb-width, fb-height,
+ blit-linear.handle,
+ blit-linear.stride,
+ I915_TILING_NONE,
+ 0, 0 /* dst_x, dst_y */);
+
+ gem_sync(fd, blit-linear.handle);
+
+ gem_set_domain(fd, blit-linear.handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ /* Setup cairo context */
blit-linear.map = gem_mmap__cpu(fd,
blit-linear.handle,
0,
@@ -723,9 +750,6 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
PROT_READ | PROT_WRITE);
igt_assert(blit-linear.map);
- gem_set_domain(fd, blit-linear.handle,
- I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
-
cairo_format = drm_format_to_cairo(fb-drm_format);
fb-cairo_surface =
cairo_image_surface_create_for_data(blit-linear.map,
--
2.3.5
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 883e11f..5aad253 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1038,8 +1038,15 @@ static int skl_init_workarounds(struct intel_engine_cs
*ring)
static int bxt_init_workarounds(struct intel_engine_cs *ring)
{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
gen9_init_workarounds(ring);
+ /* WaDisableThreadStallDopClockGating:bxt */
+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ STALL_DOP_GATING_DISABLE);
+
return 0;
}
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 91eef06..d34432b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6318,6 +6318,7 @@ enum skl_disp_power_wells {
#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
#define GEN7_MAX_PS_THREAD_DEP (812)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE(110)
+#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE(14)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (13)
#define GEN9_HALF_SLICE_CHICKEN5 0xe188
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5aad253..eebee73 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs
*ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
+ /* WaDisableSbeCacheDispatchPortSharing:bxt */
+ if (INTEL_REVID(dev) = BXT_REVID_B0) {
+ WA_SET_BIT_MASKED(
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ }
+
This looks ok, but according to the WA DB it should also be added for
SKL (=F0) in gen9_init_workarounds.
return 0;
}
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[Intel-gfx] [PATCH] drm/i915/hdmi: check port in ibx_infoframe_enabled
Add port check for ibx similar to vlv in commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Author: Jesse Barnes jbar...@virtuousgeek.org Date: Wed Apr 15 16:52:29 2015 -0700 drm/i915/vlv: check port in infoframe_enabled v2 Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 7774ca2b9bdf..65bc3867dda2 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -223,10 +223,14 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder-dev; struct drm_i915_private *dev_priv = dev-dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder-crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = TVIDEO_DIP_CTL(intel_crtc-pipe); u32 val = I915_READ(reg); - return val VIDEO_DIP_ENABLE; + if (VIDEO_DIP_PORT(intel_dig_port-port) == (val VIDEO_DIP_PORT_MASK)) + return val VIDEO_DIP_ENABLE; + + return false; } static void cpt_write_infoframe(struct drm_encoder *encoder, -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling using shared scalers
On Mon, 27 Apr 2015, Chandra Konduru chandra.kond...@intel.com wrote:
This patch enables skylake primary plane scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt)
-use values in plane_state-src as regular integers (me)
v4:
-changes to align with updated scaler structures (Matt, me)
-keep plane src rect in 16.16 format (Matt, Daniel)
v5:
-Rebased on top of 90/270 rotation changes (me)
-Fixed an issue introduced by 90/270 changes where plane programming
is using drm_plane-state rect instead of intel_plane-state rect.
This change also required for scaling to work properly. (me)
-With 90/270, updated limits to cover both portrait and landscape usages (me)
-Refactored skylake_update_primary_plane to reduce its size (Daniel)
Added helper functions for refactoring are comprehended enough to be
used for skylake_update_plane (for sprite) too. One stop towards
having single function for all planes.
v6:
-Added fixme note when checking plane_state-src width in update_plane
(Daniel)
-Release lock when failing to colorkey request with active scaler (Daniel)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Reviewed-by: matthew.d.ro...@intel.com
Matt, I never saw an explicit r-b from you for this patch, and there
were also plenty of recent changes. Does your r-b still hold?
Chandra, an earlier version of the patch has Testcase: kms_plane_scaling
but this one doesn't. Does that test now do what Daniel requested in
[1]?
BR,
Jani.
[1] http://mid.gmane.org/20150413181245.GC6092@phenom.ffwll.local
Reviewed-by: sonika.jin...@intel.com (v5)
---
drivers/gpu/drm/i915/intel_atomic.c |5 +-
drivers/gpu/drm/i915/intel_display.c | 266
+-
drivers/gpu/drm/i915/intel_drv.h |8 +-
drivers/gpu/drm/i915/intel_sprite.c | 10 ++
4 files changed, 219 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 3c4b7cd..cb6d5f2 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -169,7 +169,7 @@ int intel_atomic_commit(struct drm_device *dev,
plane-state-state = NULL;
}
- /* swap crtc_state */
+ /* swap crtc_scaler_state */
for (i = 0; i dev-mode_config.num_crtc; i++) {
struct drm_crtc *crtc = state-crtcs[i];
if (!crtc) {
@@ -178,6 +178,9 @@ int intel_atomic_commit(struct drm_device *dev,
to_intel_crtc(crtc)-config-scaler_state =
to_intel_crtc_state(state-crtc_states[i])-scaler_state;
+
+ if (INTEL_INFO(dev)-gen = 9)
+ skl_detach_scalers(to_intel_crtc(crtc));
}
drm_atomic_helper_commit_planes(dev, state);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5f7a40f..22799fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2960,126 +2960,204 @@ void skl_detach_scalers(struct intel_crtc
*intel_crtc)
}
}
-static void skylake_update_primary_plane(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- int x, int y)
+u32 skl_plane_ctl_format(uint32_t pixel_format)
{
- struct drm_device *dev = crtc-dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_i915_gem_object *obj;
- int pipe = intel_crtc-pipe;
- u32 plane_ctl, stride_div, stride;
- u32 tile_height, plane_offset, plane_size;
- unsigned int rotation;
- int x_offset, y_offset;
- unsigned long surf_addr;
- struct drm_plane *plane;
-
- if (!intel_crtc-primary_enabled) {
- I915_WRITE(PLANE_CTL(pipe, 0), 0);
- I915_WRITE(PLANE_SURF(pipe, 0), 0);
- POSTING_READ(PLANE_CTL(pipe, 0));
- return;
- }
-
- plane_ctl = PLANE_CTL_ENABLE |
- PLANE_CTL_PIPE_GAMMA_ENABLE |
- PLANE_CTL_PIPE_CSC_ENABLE;
-
- switch (fb-pixel_format) {
+ u32 plane_ctl_format = 0;
+ switch (pixel_format) {
case DRM_FORMAT_RGB565:
- plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
- break;
- case DRM_FORMAT_XRGB:
- plane_ctl |= PLANE_CTL_FORMAT_XRGB_;
- break;
- case DRM_FORMAT_ARGB:
- plane_ctl |= PLANE_CTL_FORMAT_XRGB_;
- plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+ plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
break;
case DRM_FORMAT_XBGR:
- plane_ctl |= PLANE_CTL_ORDER_RGBX;
- plane_ctl |= PLANE_CTL_FORMAT_XRGB_;
+ plane_ctl_format =
Re: [Intel-gfx] [RFC v6 1/8] drivers/gpio/gpiolib: Add support for removing registered consumer lookup table
On Fri, 24 Apr 2015, Shobhit Kumar shobhit.ku...@intel.com wrote:
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing maintainers
Shobhit, please resend to linux-g...@vger.kernel.org and
linux-ker...@vger.kernel.org in addition to the maintainers, with
Alexandre's r-b added.
BR,
Jani.
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpio/gpiolib.c | 13 +
include/linux/gpio/machine.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 59eaa23..2420af9 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1658,6 +1658,19 @@ void gpiod_add_lookup_table(struct gpiod_lookup_table
*table)
mutex_unlock(gpio_lookup_lock);
}
+/**
+ * gpiod_remove_lookup_table() - unregister GPIO device consumers
+ * @table: table of consumers to unregister
+ */
+void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
+{
+ mutex_lock(gpio_lookup_lock);
+
+ list_del(table-list);
+
+ mutex_unlock(gpio_lookup_lock);
+}
+
static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
unsigned int idx,
enum gpio_lookup_flags *flags)
diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h
index e270614..c0d712d 100644
--- a/include/linux/gpio/machine.h
+++ b/include/linux/gpio/machine.h
@@ -57,5 +57,6 @@ struct gpiod_lookup_table {
}
void gpiod_add_lookup_table(struct gpiod_lookup_table *table);
+void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
#endif /* __LINUX_GPIO_MACHINE_H */
--
2.1.0
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: Signed-off-by: Nick Hoath nicholas.ho...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eebee73..cc62e5c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } + /* WaForceContextSaveRestoreNonCoherent:bxt */ + WA_SET_BIT_MASKED(HDC_CHICKEN0, + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + Looks ok, but again it needs to be added for SKL (all steppings) in gen9_init_workarounds. return 0; } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Support for pread/pwrite from/to non shmem backed objects
On Wed, Apr 29, 2015 at 03:01:58PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr objects it is still forbidden.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 125
+---
2 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21a2b1f..a568cd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3270,4 +3270,11 @@ static inline void i915_trace_irq_get(struct
intel_engine_cs *ring,
i915_gem_request_assign(ring-trace_irq_req, req);
}
+/* Checking if pread/pwrite is allowed for the object */
+inline static bool i915_gem_obj_is_prw_allowed(struct drm_i915_gem_object
*obj)
+{
+ /* pread/pwrite is forbidden for userptrs */
+ return !obj-userptr.mm;
+}
Not quite. Just wasn't implemented (as there wasn't much point since we
couldn't provide other CPU access) but there is no reason to arbitrary
limit the API - especially as you are in the process of removing that
arbitrary limitation!
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 81c5381..3491bd3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -631,6 +631,96 @@ shmem_pread_slow(struct page *page, int
shmem_page_offset, int page_length,
return ret ? - EFAULT : 0;
}
+static inline int
+slow_user_access(struct io_mapping *mapping,
+ loff_t page_base, int page_offset,
+ char __user *user_data,
+ int length, bool write)
+{
+ void __iomem *vaddr_inatomic;
+ void *vaddr;
+ unsigned long unwritten;
+
+ vaddr_inatomic = io_mapping_map_wc(mapping, page_base);
+ /* We can use the cpu mem copy function because this is X86. */
+ vaddr = (void __force *)vaddr_inatomic + page_offset;
+ if (write)
+ unwritten = __copy_from_user(vaddr, user_data, length);
+ else
+ unwritten = __copy_to_user(user_data, vaddr, length);
+
+ io_mapping_unmap(vaddr_inatomic);
+ return unwritten;
+}
+
+static int
+i915_gem_gtt_pread_pwrite(struct drm_device *dev,
+ struct drm_i915_gem_object *obj, uint64_t size,
+ uint64_t data_offset, uint64_t data_ptr, bool write)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ char __user *user_data;
+ ssize_t remain;
+ loff_t offset, page_base;
+ int page_offset, page_length, ret = 0;
+
+ ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
+ if (ret)
+ goto out;
+
+ ret = i915_gem_object_set_to_gtt_domain(obj, write);
+ if (ret)
+ goto out_unpin;
+
+ ret = i915_gem_object_put_fence(obj);
+ if (ret)
+ goto out_unpin;
+
+ user_data = to_user_ptr(data_ptr);
+ remain = size;
+
+ offset = i915_gem_obj_ggtt_offset(obj) + data_offset;
+
+ if (write)
+ intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
+
+ while (remain 0) {
+ /* Operation in this page
+ *
+ * page_base = page offset within aperture
+ * page_offset = offset within page
+ * page_length = bytes to copy for this page
+ */
+ page_base = offset PAGE_MASK;
+ page_offset = offset_in_page(offset);
+ page_length = remain;
+ if ((page_offset + remain) PAGE_SIZE)
+ page_length = PAGE_SIZE - page_offset;
+
+ /* This is a slow read/write as it tries to read from
+ * and write to user memory which may result into page
+ * faults
+ */
Hmm, I am in the process of rewriting this function (GTT pwrite) to reduce
aperture pressure (which will also be important here). However for your
use case, we do need to drop the locks around slow_user_access() so that
we can use non-atomic copy functions and *pagefault*. We do need the full
level of complexity like i915_gem_shmem_pread()
-Chris
--
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Re: [Intel-gfx] [PATCH 04/11] drm/i915: Extend GET_APERTURE ioctl to report available map space
On Wed, Jan 28, 2015 at 10:59:28AM +0100, Daniel Vetter wrote: On Mon, Jan 26, 2015 at 04:43:18AM -0800, Rodrigo Vivi wrote: When constructing a batchbuffer, it is sometimes crucial to know the largest hole into which we can fit a fenceable buffer (for example when handling very large objects on gen2 and gen3). This depends on the fragmentation of pinned buffers inside the aperture, a question only the kernel can easily answer. This patch extends the current DRM_I915_GEM_GET_APERTURE ioctl to include a couple of new fields in its reply to userspace - the total amount of space available in the mappable region of the aperture and also the single largest block available. This is not quite what userspace wants to answer the question of whether this batch will fit as fences are also required to meet severe alignment constraints within the batch. For this purpose, a third conservative estimate of largest fence available is also provided. For when userspace needs more than one batch, we also provide the culmulative space available for fences such that it has some additional guidance to how much space it could allocate to fences. Conservatism still wins. The patch also adds a debugfs file for convenient testing and reporting. v2: The first object cannot end at offset 0, so we can use last==0 to detect the empty list. v3: Expand all values to 64bit, just in case. Report total mappable aperture size for userspace that cannot easily determine it by inspecting the PCI device. v4: (Rodrigo) Fixed rebase conflicts. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com Do we have the libdrm patch for this too? Imo there's not much use in this if mesa remains broken, especially since this is for gen2/3 ... most DE use gl nowadays. Mesa on gen2/3 is broken full stop as it cannot handle the full desktop size anyway. Just like Broadwell. There was a user ready to go and waiting. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/16] drm/i915: Only remove objects pinned to the display from the available aperture
On Wed, Apr 29, 2015 at 04:05:40PM +0100, Tvrtko Ursulin wrote: On 04/27/2015 01:41 PM, Chris Wilson wrote: With the removal of the pin_ioctl, we need only consider obj-pin_display when looking at available aperture space. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index afdb604e4005..ec9e36e9ec78 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -157,7 +157,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, pinned = 0; mutex_lock(dev-struct_mutex); list_for_each_entry(obj, dev_priv-mm.bound_list, global_list) -if (i915_gem_obj_is_pinned(obj)) +if (obj-pin_display) pinned += i915_gem_obj_ggtt_size(obj); mutex_unlock(dev-struct_mutex); The only thing I can think of are transients from execbuf, pre-ppgtt, but I suppose we don't care about that a lot? Or I misunderstand how something works? They are only pinned whilst we process reservations for the batch. The only things that are permenantly pinned are the display objects, which hardware is pointed at. Hmm, I guess they are actually a few others we do care about such as overlay regs and legacy ringbuffer objs, default contects and status pages and the like. On the other hand perma-pinning into the GGTT is now quite rare, so perhaps it is time to start tracking it again. I guess I am going to have to revisit this patch (my goal is try and clarify what i915_gem_obj_is_pinned() means by eliminating it ;-) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/hdmi: check port in ibx_infoframe_enabled
On 04/29/2015 05:30 AM, Jani Nikula wrote: Add port check for ibx similar to vlv in commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Author: Jesse Barnes jbar...@virtuousgeek.org Date: Wed Apr 15 16:52:29 2015 -0700 drm/i915/vlv: check port in infoframe_enabled v2 Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 7774ca2b9bdf..65bc3867dda2 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -223,10 +223,14 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder-dev; struct drm_i915_private *dev_priv = dev-dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder-crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = TVIDEO_DIP_CTL(intel_crtc-pipe); u32 val = I915_READ(reg); - return val VIDEO_DIP_ENABLE; + if (VIDEO_DIP_PORT(intel_dig_port-port) == (val VIDEO_DIP_PORT_MASK)) + return val VIDEO_DIP_ENABLE; + + return false; } static void cpt_write_infoframe(struct drm_encoder *encoder, Ah great, thanks Jani. R-b for both. Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling using shared scalers
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Wednesday, April 29, 2015 5:13 AM
To: Konduru, Chandra; intel-gfx@lists.freedesktop.org; Roper, Matthew D
Cc: Vetter, Daniel; Conselvan De Oliveira, Ander
Subject: Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling
using shared scalers
On Mon, 27 Apr 2015, Chandra Konduru chandra.kond...@intel.com wrote:
This patch enables skylake primary plane scaling using shared scalers
atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt) -use values in
plane_state-src as regular integers (me)
v4:
-changes to align with updated scaler structures (Matt, me) -keep
plane src rect in 16.16 format (Matt, Daniel)
v5:
-Rebased on top of 90/270 rotation changes (me) -Fixed an issue
introduced by 90/270 changes where plane programming is using
drm_plane-state rect instead of intel_plane-state rect.
This change also required for scaling to work properly. (me) -With
90/270, updated limits to cover both portrait and landscape usages
(me) -Refactored skylake_update_primary_plane to reduce its size
(Daniel) Added helper functions for refactoring are comprehended
enough to be used for skylake_update_plane (for sprite) too. One stop
towards having single function for all planes.
v6:
-Added fixme note when checking plane_state-src width in update_plane
(Daniel) -Release lock when failing to colorkey request with active
scaler (Daniel)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Reviewed-by: matthew.d.ro...@intel.com
Matt, I never saw an explicit r-b from you for this patch, and there were also
plenty of recent changes. Does your r-b still hold?
Chandra, an earlier version of the patch has Testcase: kms_plane_scaling but
this one doesn't. Does that test now do what Daniel requested in [1]?
Hi Jani,
Yes, same kms_plane_scaling is applicable. In patch creation, missed to add
back the line:
Testcase: kms_plane_scaling
Regarding review, Matt reviewed until v4.
For v5: changes are related to rebasing for 90/270, and Matt's suggestion was
to get it reviewed from 90/270 owner (Sonika). Got R-b for v5 changes from her.
For v6- it is adding a comment and addressing lock issue; nothing new added.
I have sent a patch to update kms_plane_scaling but need some minor updates
to address review feedback. I think, that shouldn't block merge of remaining
scaler
patches.
BR,
Jani.
[1] http://mid.gmane.org/20150413181245.GC6092@phenom.ffwll.local
Reviewed-by: sonika.jin...@intel.com (v5)
---
drivers/gpu/drm/i915/intel_atomic.c |5 +-
drivers/gpu/drm/i915/intel_display.c | 266 +
-
drivers/gpu/drm/i915/intel_drv.h |8 +-
drivers/gpu/drm/i915/intel_sprite.c | 10 ++
4 files changed, 219 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 3c4b7cd..cb6d5f2 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -169,7 +169,7 @@ int intel_atomic_commit(struct drm_device *dev,
plane-state-state = NULL;
}
- /* swap crtc_state */
+ /* swap crtc_scaler_state */
for (i = 0; i dev-mode_config.num_crtc; i++) {
struct drm_crtc *crtc = state-crtcs[i];
if (!crtc) {
@@ -178,6 +178,9 @@ int intel_atomic_commit(struct drm_device *dev,
to_intel_crtc(crtc)-config-scaler_state =
to_intel_crtc_state(state-crtc_states[i])-scaler_state;
+
+ if (INTEL_INFO(dev)-gen = 9)
+ skl_detach_scalers(to_intel_crtc(crtc));
}
drm_atomic_helper_commit_planes(dev, state); diff --git
a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5f7a40f..22799fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2960,126 +2960,204 @@ void skl_detach_scalers(struct intel_crtc
*intel_crtc)
}
}
-static void skylake_update_primary_plane(struct drm_crtc *crtc,
-struct drm_framebuffer *fb,
-int x, int y)
+u32 skl_plane_ctl_format(uint32_t pixel_format)
{
- struct drm_device *dev = crtc-dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_i915_gem_object *obj;
- int pipe = intel_crtc-pipe;
- u32 plane_ctl, stride_div, stride;
- u32 tile_height, plane_offset, plane_size;
- unsigned int rotation;
- int x_offset, y_offset;
- unsigned long surf_addr;
- struct drm_plane *plane;
-
- if (!intel_crtc-primary_enabled) {
- I915_WRITE(PLANE_CTL(pipe, 0), 0);
-
[Intel-gfx] [PATCH v5 1/8] drm/i915/skl: Add support to load SKL CSR firmware.
From: A.Sunil Kamath sunil.kam...@intel.com Display Context Save and Restore support is needed for various SKL Display C states like DC5, DC6. This implementation is added based on first version of DMC CSR program that we received from h/w team. Here we are using request_firmware based design. Finally this firmware should end up in linux-firmware tree. For SKL platform its mandatory to ensure that we load this csr program before enabling DC states like DC5/DC6. As CSR program gets reset on various conditions, we should ensure to load it during boot and in future change to be added to load this system resume sequence too. v1: Initial relese as RFC patch v2: Design change as per Daniel, Damien and Shobit's review comments request firmware method followed. v3: Some optimization and functional changes. Pulled register defines into drivers/gpu/drm/i915/i915_reg.h Used kmemdup to allocate and duplicate firmware content. Ensured to free allocated buffer. v4: Modified as per review comments from Satheesh and Daniel Removed temporary buffer. Optimized number of writes by replacing I915_WRITE with I915_WRITE64. v5: Modified as per review comemnts from Damien. - Changed name for functions and firmware. - Introduced HAS_CSR. - Reverted back previous change and used csr_buf with u8 size. - Using cpu_to_be64 for endianness change. Modified as per review comments from Imre. - Modified registers and macro names to be a bit closer to bspec terminology and the existing register naming in the driver. - Early return for non SKL platforms in intel_load_csr_program function. - Added locking around CSR program load function as it may be called concurrently during system/runtime resume. - Releasing the fw before loading the program for consistency - Handled error path during f/w load. v6: Modified as per review comments from Imre. - Corrected out_freecsr sequence. v7: Modified as per review comments from Imre. Fail loading fw if fw-size%8!=0. v8: Rebase to latest. v9: Rebase on top of -nightly (Damien) v10: Enabled support for dmc firmware ver 1.0. According to ver 1.0 in a single binary package all the firmware's that are required for different stepping's of the product will be stored. The package contains the css header, followed by the package header and the actual dmc firmwares. Package header contains the firmware/stepping mapping table and the corresponding firmware offsets to the individual binaries, within the package. Each individual program binary contains the header and the payload sections whose size is specified in the header section. This changes are done to extract the specific firmaware from the package. (Animesh) v11: Modified as per review comemnts from Imre. - Added code comment from bpec for header structure elements. - Added __packed to avoid structure padding. - Added helper functions for stepping and substepping info. - Added code comment for CSR_MAX_FW_SIZE. - Disabled BXT firmware loading, will be enabled with dmc 1.0 support. - Changed skl_stepping_info based on bspec, earlier used from config DB. - Removed duplicate call of cpu_to_be* from intel_csr_load_program function. - Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned. - Added sanity check for header length. - Added sanity check for mmio address got from firmware binary. - kmalloc done separately for dmc header and dmc firmware. (Animesh) v12: Modified as per review comemnts from Imre. - Corrected the typo error in skl stepping info structure. - Added out-of-bound access for skl_stepping_info. - Sanity check for mmio address modified. - Sanity check added for stepping and substeppig. - Modified the intel_dmc_info structure, cache only the required header info. (Animesh) v13: clarify firmware load error message. The reason for a firmware loading failure can be obscure if the driver is built-in. Provide an explanation to the user about the likely reason for the failure and how to resolve it. (Imre) v14: Suggested by Jani. - fix s/I915/CONFIG_DRM_I915/ typo - add fw_path to the firmware object instead of using a static ptr (Jani) v15: 1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link with same name will help not to build kernel again. 2) Changes done as per review comments from Imre. - Error check removed for intel_csr_ucode_init. - Moved csr-specific data structure to intel_csr.h and optimization done on structure definition. - fw-data used directly for parsing the header info memory allocation only done separately for payload. (Animesh) v16: - No need for out_regs label in i915_driver_load(), so removed it. - Changed the firmware name as skl_dmc_ver1.bin, followed naming convention platform_dmc_api-version.bin (Animesh) Issue: VIZ-2569 Signed-off-by: A.Sunil Kamath sunil.kam...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Animesh Manna animesh.ma...@intel.com Signed-off-by: Imre Deak imre.d...@intel.com ---
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Allocate va range only if vma is not bound
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6279 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 264/264 264/264 BYT -3 227/227 224/227 BDW 318/318 318/318 -Detailed- Platform Testdrm-intel-nightly Series Applied BYT igt@drm_vma_limiter_cached FAIL(3)PASS(3) FAIL(2) *BYT igt@gem_exec_params@rsvd2-dirt FAIL(1)PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(2)PASS(3) TIMEOUT(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv
On Wed, Apr 29, 2015 at 06:31:56PM +0300, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
So far I can't reproduce this problem on my BSW. In fact what I see
that the voltage at RPn is lower than the voltage at RPe, even while
we're in rc6.
without forcewake:
RPn - 0x66
RPe - 0x67
RP0 - 0x69
with forcewake:
RPn - 0x66
RPe - 0x76
RP0 - 0x9d
Also asking Punit to change the frequency after the GPU has gone to
rc6 does absolutely nothing (remind anyone of VLV?). I think I need to
retest my VLV C0 to see if my earlier observations there were accurate.
The shared Vnn rail does make it harder to observe this stuff on
VLV though.
I went back to my VLVs (had a B3 and C0 actually). And I'm seeing the
exact same behaviour on both, ie. requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if I let it enter rc6 with a
high frequency Vnn also remains high. Previously I had thought that C0
fixed this, but now it definitely shows the same problem here. I must
have had some accidental forcewake somewhere when I originally tested
it,
So based on that, your other patch to remove the stepping check from
vlv_set_rps_idle() is in fact correct.
The question remains however what should we do with CHV. According to my
testing to get the minimum voltage we should keep RPn around, and we
should also do the vlv_set_rps_idle() workaround on CHV.
Oh and I also observed something else on VLV. Normally when entering rc6
the GPLL ref clock gets trunk gated at CCK (by Punit I assume). However
when using the vlv_gfx_clock_force() that doesn't happen. So I'm not
entirely sure the GPLL gets turned off properly in that case. Maybe we
should just use forcewake instead? Oh and BTW, CHV doesn't do the trunk
gating in either case. I'm not sure where to check if the GPLL is
actually running or not.
So based on my tests this patch feels a bit wrong.
Since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
v2: Change commit message
v3: set min_freq before idle_freq (chris)
v4: Squash 'Remove unused rps min function' patch
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index a7516ed..78c89ff 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4715,24 +4715,6 @@ static int cherryview_rps_guar_freq(struct
drm_i915_private *dev_priv)
return rp1;
}
-static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = dev_priv-dev;
- u32 val, rpn;
-
- if (dev-pdev-revision = 0x20) {
- val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
- rpn = ((val FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT)
- FB_GFX_FREQ_FUSE_MASK);
- } else { /* For pre-production hardware */
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = ((val PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT)
- PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
- }
-
- return rpn;
-}
-
static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp1;
@@ -4984,7 +4966,8 @@ static void cherryview_init_gt_powersave(struct
drm_device *dev)
intel_gpu_freq(dev_priv, dev_priv-rps.rp1_freq),
dev_priv-rps.rp1_freq);
- dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ /* PUnit validated range is only [RPe, RP0] */
+ dev_priv-rps.min_freq = dev_priv-rps.efficient_freq;
DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
intel_gpu_freq(dev_priv, dev_priv-rps.min_freq),
dev_priv-rps.min_freq);
--
1.9.1
--
Ville Syrjälä
Intel OTC
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH v6 13/14] drm/i915: Enable GuC firmware log
From: Alex Dai yu@intel.com
Allocate a gem obj to hold GuC log data. Also a debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 5 +++
drivers/gpu/drm/i915/intel_guc.h| 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 64 -
5 files changed, 104 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f12bbee..f47714c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2332,14 +2332,14 @@ static int i915_guc_load_status_info(struct seq_file
*m, void *data)
tmp = I915_READ(GUC_STATUS);
- seq_puts(m, \nResponse from GuC:\n);
+ seq_printf(m, \nGuC status 0x%08x:\n, tmp);
seq_printf(m, \tBootrom status = 0x%x\n,
(tmp GS_BOOTROM_MASK) GS_BOOTROM_SHIFT);
seq_printf(m, \tuKernel status = 0x%x\n,
(tmp GS_UKERNEL_MASK) GS_UKERNEL_SHIFT);
seq_printf(m, \tMIA Core status = 0x%x\n,
(tmp GS_MIA_MASK) GS_MIA_SHIFT);
- seq_puts(m, Scratch registers value:\n);
+ seq_puts(m, \nScratch registers value:\n);
for (i = 0; i 16; i++)
seq_printf(m, \t%2d: \t0x%x\n, i, I915_READ(SOFT_SCRATCH(i)));
@@ -2352,13 +2352,11 @@ static int i915_guc_info(struct seq_file *m, void *data)
struct drm_device *dev = node-minor-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_guc guc;
- struct i915_guc_client client;
+ struct i915_guc_client client = { 0 };
- if (!i915.enable_guc_scheduling)
+ if (!HAS_GUC_SCHED(dev_priv-dev))
return 0;
- memset(client, 0, sizeof(struct i915_guc_client));
-
/* Take a local copy of the GuC data, so we can dump it at leisure */
spin_lock(dev_priv-guc.host2guc_lock);
guc = dev_priv-guc;
@@ -2376,7 +2374,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
seq_printf(m, GuC action failure count: %u\n, guc.action_fail);
seq_printf(m, GuC last action error code: %d\n, guc.action_err);
- seq_printf(m, GuC execbuf client @ %p:\n, guc.execbuf_client);
+ seq_printf(m, \nGuC execbuf client @ %p:\n, guc.execbuf_client);
seq_printf(m, \tTotal submissions: %llu\n, client.submissions);
seq_printf(m, \tFailed to queue: %u\n, client.q_fail);
seq_printf(m, \tFailed doorbell: %u\n, client.b_fail);
@@ -2387,6 +2385,34 @@ static int i915_guc_info(struct seq_file *m, void *data)
return 0;
}
+static int i915_guc_log_dump(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m-private;
+ struct drm_device *dev = node-minor-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_i915_gem_object *log_obj = dev_priv-guc.log_obj;
+ u32 *log;
+ int i = 0, pg;
+
+ if (!log_obj)
+ return 0;
+
+ for (pg = 0; pg log_obj-base.size / PAGE_SIZE; pg++) {
+ log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
+
+ for (i = 0; i PAGE_SIZE / sizeof(u32); i += 4)
+ seq_printf(m, 0x%08x 0x%08x 0x%08x 0x%08x\n,
+ *(log + i), *(log + i + 1),
+ *(log + i + 2), *(log + i + 3));
+
+ kunmap_atomic(log);
+ }
+
+ seq_putc(m, '\n');
+
+ return 0;
+}
+
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_info_node *node = m-private;
@@ -4855,6 +4881,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_gem_batch_pool, i915_gem_batch_pool_info, 0},
{i915_guc_info, i915_guc_info, 0},
{i915_guc_load_status, i915_guc_load_status_info, 0},
+ {i915_guc_log_dump, i915_guc_log_dump, 0},
{i915_frequency_info, i915_frequency_info, 0},
{i915_hangcheck_info, i915_hangcheck_info, 0},
{i915_drpc_info, i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d60119..aa3d81b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2505,6 +2505,7 @@ struct i915_params {
bool disable_display;
bool disable_vtd_wa;
bool enable_guc_scheduling;
+ unsigned int guc_log_level;
int use_mmio_flip;
int mmio_debug;
bool verbose_state_checks;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 9ad2e27..95e4eb7 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -54,6 +54,7 @@ struct i915_params i915 __read_mostly = {
[Intel-gfx] [PATCH v6 05/14] drm/i915: Add guc firmware interface headers
From: Alex Dai yu@intel.com These are the subset of GuC interface that we are going to use to enable command submission through GuC. The definition of these struct and bit setting need to match those in firmware. Issue: VIZ-4884 Signed-off-by: Alex Dai yu@intel.com --- drivers/gpu/drm/i915/intel_guc_api.h | 217 +++ 1 file changed, 217 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_guc_api.h diff --git a/drivers/gpu/drm/i915/intel_guc_api.h b/drivers/gpu/drm/i915/intel_guc_api.h new file mode 100644 index 000..3d4f74a --- /dev/null +++ b/drivers/gpu/drm/i915/intel_guc_api.h @@ -0,0 +1,217 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ +#ifndef _INTEL_GUC_API_H +#define _INTEL_GUC_API_H + +#define GFXCORE_FAMILY_GEN811 +#define GFXCORE_FAMILY_GEN912 +#define GFXCORE_FAMILY_FORCE_ULONG 0x7fff + +#define GUC_CTX_PRIORITY_CRITICAL 0 +#define GUC_CTX_PRIORITY_HIGH 1 +#define GUC_CTX_PRIORITY_NORMAL2 +#define GUC_CTX_PRIORITY_LOW 3 + +#define MAX_GUC_GPU_CONTEXTS 1024 + +/* Work queue item header definitions */ +#define WQ_STATUS_ACTIVE 1 +#define WQ_STATUS_SUSPENDED2 +#define WQ_STATUS_CMD_ERROR3 +#define WQ_STATUS_ENGINE_ID_NOT_USED 4 +#define WQ_STATUS_SUSPENDED_FROM_RESET 5 +#define WQ_TYPE_SHIFT 0 +#define WQ_TYPE_BATCH_BUF(0x1 WQ_TYPE_SHIFT) +#define WQ_TYPE_PSEUDO (0x2 WQ_TYPE_SHIFT) +#define WQ_TYPE_INORDER (0x3 WQ_TYPE_SHIFT) +#define WQ_TARGET_SHIFT10 +#define WQ_LEN_SHIFT 16 +#define WQ_NO_WCFLUSH_WAIT (1 27) +#define WQ_PRESENT_WORKLOAD(1 28) + +#define WQ_RING_TAIL_SHIFT 20 +#define WQ_RING_TAIL_MASK (0x7FF WQ_RING_TAIL_SHIFT) + +#define GUC_DOORBELL_ENABLED 1 +#define GUC_DOORBELL_DISABLED 0 + +#define GUC_CTX_DESC_ATTR_ACTIVE (1 0) +#define GUC_CTX_DESC_ATTR_PENDING_DB (1 1) +#define GUC_CTX_DESC_ATTR_KERNEL (1 2) +#define GUC_CTX_DESC_ATTR_PREEMPT (1 3) +#define GUC_CTX_DESC_ATTR_RESET(1 4) +#define GUC_CTX_DESC_ATTR_WQLOCKED (1 5) +#define GUC_CTX_DESC_ATTR_PCH (1 6) + +/* The guc control data is 10 DWORDs */ +#define GUC_CTL_CTXINFO0 +#define GUC_CTL_CTXNUM_IN16_SHIFT0 +#define GUC_CTL_BASE_ADDR_SHIFT 12 +#define GUC_CTL_ARAT_HIGH 1 +#define GUC_CTL_ARAT_LOW 2 +#define GUC_CTL_DEVICE_INFO3 +#define GUC_CTL_GTTYPE_SHIFT 0 +#define GUC_CTL_COREFAMILY_SHIFT 7 +#define GUC_CTL_LOG_PARAMS 4 +#define GUC_LOG_VALID(1 0) +#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 1) +#define GUC_LOG_ALLOC_IN_MEGABYTE(1 3) +#define GUC_LOG_CRASH_SHIFT 4 +#define GUC_LOG_DPC_SHIFT6 +#define GUC_LOG_ISR_SHIFT9 +#define GUC_LOG_BUF_ADDR_SHIFT 12 +#define GUC_CTL_PAGE_FAULT_CONTROL 5 +#define GUC_CTL_WA 6 +#define GUC_CTL_WA_UK_BY_DRIVER (1 3) +#define GUC_CTL_FEATURE7 +#define GUC_CTL_VCS2_ENABLED (1 0) +#define GUC_CTL_KERNEL_SUBMISSIONS (1 1) +#define GUC_CTL_FEATURE2 (1 2) +#define GUC_CTL_POWER_GATING (1 3) +#define GUC_CTL_DISABLE_SCHEDULER(1 4) +#define GUC_CTL_PREEMPTION_LOG (1 5) +#define GUC_CTL_DEBUG 8 +#define GUC_LOG_VERBOSITY_SHIFT 0 +#define GUC_LOG_VERBOSITY_LOW(0 GUC_LOG_VERBOSITY_SHIFT) +#define GUC_LOG_VERBOSITY_MED(1 GUC_LOG_VERBOSITY_SHIFT) +#define GUC_LOG_VERBOSITY_HIGH (2 GUC_LOG_VERBOSITY_SHIFT) +#define
[Intel-gfx] [PATCH v6 06/14] drm/i915: GuC firmware loader
From: Alex Dai yu@intel.com
Add GuC firmware loader. It uses the unified firmware loader to
fetch firmware blob first, then load to hw in driver main thread.
This patch is derived from GuC loading work originally done by
Vinit Azad and Ben Widawsky. It has been reconstructed to accord
with the unified firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_dma.c | 4 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_gem.c | 7 +
drivers/gpu/drm/i915/i915_gem_context.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_guc.h| 106 +
drivers/gpu/drm/i915/intel_guc_loader.c | 368
8 files changed, 500 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc.h
create mode 100644 drivers/gpu/drm/i915/intel_guc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1b027c7..6188302 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -40,7 +40,8 @@ i915-y += i915_cmd_parser.o \
intel_uncore.o
# ancilliary microcontroller support
-i915-y += intel_uc_loader.o
+i915-y += intel_uc_loader.o \
+ intel_guc_loader.o
# autogenerated null render state
i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e44116f..92f19e5 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -465,6 +465,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
cleanup_gem:
mutex_lock(dev-struct_mutex);
+ intel_guc_ucode_fini(dev);
i915_gem_cleanup_ringbuffer(dev);
i915_gem_context_fini(dev);
mutex_unlock(dev-struct_mutex);
@@ -861,6 +862,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long
flags)
intel_uncore_init(dev);
+ intel_guc_ucode_init(dev);
+
ret = i915_gem_gtt_init(dev);
if (ret)
goto out_regs;
@@ -1108,6 +,7 @@ int i915_driver_unload(struct drm_device *dev)
flush_workqueue(dev_priv-wq);
mutex_lock(dev-struct_mutex);
+ intel_guc_ucode_fini(dev);
i915_gem_cleanup_ringbuffer(dev);
i915_gem_context_fini(dev);
mutex_unlock(dev-struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5068cb..b0b901d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -50,6 +50,7 @@
#include linux/intel-iommu.h
#include linux/kref.h
#include linux/pm_qos.h
+#include intel_guc.h
/* General customization:
*/
@@ -1581,6 +1582,8 @@ struct drm_i915_private {
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
+ struct intel_guc guc;
+
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
* controller on different i2c buses. */
struct mutex gmbus_mutex;
@@ -2432,6 +2435,9 @@ struct drm_i915_cmd_table {
#define HAS_RC6(dev) (INTEL_INFO(dev)-gen = 6)
#define HAS_RC6p(dev) (INTEL_INFO(dev)-gen == 6 || IS_IVYBRIDGE(dev))
+#define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
+#define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
+
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fabe8de..4001a90 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4864,6 +4864,13 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_cleanup_ringbuffer(dev);
}
+ /* We can't enable contexts until all firmware is loaded */
+ ret = intel_guc_ucode_load(dev, false);
+ if (ret == -EAGAIN) {
+ ret = 0;/* too early */
+ goto out;
+ }
+
ret = i915_gem_context_enable(dev_priv);
if (ret == 0) {
dev_priv-contexts_ready = true;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0edae87..81159b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -453,6 +453,10 @@ static int i915_gem_context_first_open(struct drm_device
*dev)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
+ /* We can't enable contexts until all firmware is loaded */
+ ret = intel_guc_ucode_load(dev, true);
+ WARN_ON(ret == -EAGAIN);
+
ret = i915_gem_context_enable(dev_priv);
if (ret == 0)
dev_priv-contexts_ready = true;
diff --git a/drivers/gpu/drm/i915/i915_reg.h
[Intel-gfx] [PATCH v6 12/14] drm/i915: debugfs of GuC status
From: Alex Dai yu@intel.com
Now print out Bootrom, uKernel and MIA Core status. The scratch reg
0 15 are used for communication between driver and firmware. Their
status is also printed out.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 79 +
drivers/gpu/drm/i915/intel_guc.h| 13 ++
drivers/gpu/drm/i915/intel_guc_client.c | 33 +++---
3 files changed, 118 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9c2b9e4..f12bbee 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2310,6 +2310,83 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
+static void i915_uc_load_status_info(struct seq_file *m, struct intel_uc_fw
*uc_fw)
+{
+ seq_printf(m, %s firmware status:\n\tpath: %s\n\tfetch: %d\n\tload:
%d\n,
+ uc_fw-uc_name,
+ uc_fw-uc_fw_path,
+ uc_fw-uc_fw_fetch_status,
+ uc_fw-uc_fw_load_status);
+}
+
+static int i915_guc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m-private;
+ struct drm_i915_private *dev_priv = node-minor-dev-dev_private;
+ u32 tmp, i;
+
+ if (!HAS_GUC_UCODE(dev_priv-dev))
+ return 0;
+
+ i915_uc_load_status_info(m, dev_priv-guc.guc_fw);
+
+ tmp = I915_READ(GUC_STATUS);
+
+ seq_puts(m, \nResponse from GuC:\n);
+ seq_printf(m, \tBootrom status = 0x%x\n,
+ (tmp GS_BOOTROM_MASK) GS_BOOTROM_SHIFT);
+ seq_printf(m, \tuKernel status = 0x%x\n,
+ (tmp GS_UKERNEL_MASK) GS_UKERNEL_SHIFT);
+ seq_printf(m, \tMIA Core status = 0x%x\n,
+ (tmp GS_MIA_MASK) GS_MIA_SHIFT);
+ seq_puts(m, Scratch registers value:\n);
+ for (i = 0; i 16; i++)
+ seq_printf(m, \t%2d: \t0x%x\n, i, I915_READ(SOFT_SCRATCH(i)));
+
+ return 0;
+}
+
+static int i915_guc_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m-private;
+ struct drm_device *dev = node-minor-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_guc guc;
+ struct i915_guc_client client;
+
+ if (!i915.enable_guc_scheduling)
+ return 0;
+
+ memset(client, 0, sizeof(struct i915_guc_client));
+
+ /* Take a local copy of the GuC data, so we can dump it at leisure */
+ spin_lock(dev_priv-guc.host2guc_lock);
+ guc = dev_priv-guc;
+ if (guc.execbuf_client) {
+ spin_lock(guc.execbuf_client-wq_lock);
+ client = *guc.execbuf_client;
+ spin_unlock(guc.execbuf_client-wq_lock);
+ }
+ spin_unlock(dev_priv-guc.host2guc_lock);
+
+ seq_printf(m, GuC total action count: %llu\n, guc.action_count);
+ seq_printf(m, GuC last action command: 0x%x\n, guc.action_cmd);
+ seq_printf(m, GuC last action status: 0x%x\n, guc.action_status);
+
+ seq_printf(m, GuC action failure count: %u\n, guc.action_fail);
+ seq_printf(m, GuC last action error code: %d\n, guc.action_err);
+
+ seq_printf(m, GuC execbuf client @ %p:\n, guc.execbuf_client);
+ seq_printf(m, \tTotal submissions: %llu\n, client.submissions);
+ seq_printf(m, \tFailed to queue: %u\n, client.q_fail);
+ seq_printf(m, \tFailed doorbell: %u\n, client.b_fail);
+ seq_printf(m, \tLast submission result: %d\n, client.retcode);
+
+ /* Add more as required ... */
+
+ return 0;
+}
+
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_info_node *node = m-private;
@@ -4776,6 +4853,8 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_gem_hws_bsd, i915_hws_info, 0, (void *)VCS},
{i915_gem_hws_vebox, i915_hws_info, 0, (void *)VECS},
{i915_gem_batch_pool, i915_gem_batch_pool_info, 0},
+ {i915_guc_info, i915_guc_info, 0},
+ {i915_guc_load_status, i915_guc_load_status_info, 0},
{i915_frequency_info, i915_frequency_info, 0},
{i915_hangcheck_info, i915_hangcheck_info, 0},
{i915_drpc_info, i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f8065cf..b096d1a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -42,6 +42,12 @@ struct i915_guc_client {
uint32_t wq_size;
uint32_t wq_tail;
uint32_t cookie;
+
+ /* GuC submission statistics status */
+ uint64_t submissions;
+ uint32_t q_fail;
+ uint32_t b_fail;
+ int retcode;
};
#define I915_MAX_DOORBELLS 256
@@ -66,6 +72,13 @@ struct intel_guc {
struct ida ctx_ids;
int db_cacheline;
DECLARE_BITMAP(doorbell_bitmap, I915_MAX_DOORBELLS);
+
+
[Intel-gfx] [PATCH v6 09/14] drm/i915: Integration of GuC client
From: Alex Dai yu@intel.com
Implementation of GuC client. A GuC client has its own doorbell
and workqueue. It maintains the doorbell cache line, process
description object and work queue item.
A default guc_client is created to do the in-order legacy execlist
submission.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h| 5 +
drivers/gpu/drm/i915/intel_guc.h | 46 +++
drivers/gpu/drm/i915/intel_guc_client.c| 430 +
drivers/gpu/drm/i915/intel_guc_loader.c| 7 +
drivers/gpu/drm/i915/intel_guc_scheduler.c | 29 +-
6 files changed, 517 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_client.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 50b2057..0407720 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -42,7 +42,8 @@ i915-y += i915_cmd_parser.o \
# ancilliary microcontroller support
i915-y += intel_uc_loader.o \
- intel_guc_loader.o
+ intel_guc_loader.o \
+ intel_guc_client.o
# autogenerated null render state
i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 248..0d60119 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1850,6 +1850,11 @@ static inline struct drm_i915_private
*dev_to_i915(struct device *dev)
return to_i915(dev_get_drvdata(dev));
}
+static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
+{
+ return container_of(guc, struct drm_i915_private, guc);
+}
+
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
for ((i__) = 0; (i__) I915_NUM_RINGS; (i__)++) \
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index bf80f32..fd6f394 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,25 @@
#include intel_guc_api.h
#include intel_uc_loader.h
+#define GUC_DB_SIZEPAGE_SIZE
+#define GUC_WQ_SIZE(PAGE_SIZE * 2)
+
+struct i915_guc_client {
+ struct drm_i915_gem_object *client_obj;
+ u32 priority;
+ off_t doorbell_offset;
+ off_t proc_desc_offset;
+ off_t wq_offset;
+ uint16_t doorbell_id;
+ uint32_t ctx_index;
+ uint32_t wq_size;
+};
+
+#define I915_MAX_DOORBELLS 256
+#define INVALID_DOORBELL_IDI915_MAX_DOORBELLS
+
+#define INVALID_CTX_ID (MAX_GUC_GPU_CONTEXTS+1)
+
struct intel_guc {
/* Generic uC firmware management */
struct intel_uc_fw guc_fw;
@@ -35,7 +54,15 @@ struct intel_guc {
uint32_t fw_ver_major;
uint32_t fw_ver_minor;
+ spinlock_t host2guc_lock;
+
struct drm_i915_gem_object *ctx_pool_obj;
+
+ struct i915_guc_client *execbuf_client;
+
+ struct ida ctx_ids;
+ int db_cacheline;
+ DECLARE_BITMAP(doorbell_bitmap, I915_MAX_DOORBELLS);
};
#define GUC_STATUS 0xc000
@@ -100,6 +127,16 @@ struct intel_guc {
GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA)
+#define HOST2GUC_INTERRUPT 0xc4c8
+#define HOST2GUC_TRIGGER (10)
+
+#define DRBMISC1 0x1984
+#define DOORBELL_ENABLE (10)
+
+#define GEN8_DRBREGL(x) (0x1000 + (x) * 8)
+#define GEN8_DRB_VALID (10)
+#define GEN8_DRBREGU(x) (0x1000 + (x) * 8 + 4)
+
/* intel_guc_loader.c */
extern int intel_guc_ucode_load(struct drm_device *dev, bool wait);
extern void intel_guc_ucode_fini(struct drm_device *dev);
@@ -114,4 +151,13 @@ void guc_scheduler_fini(struct drm_device *dev);
int guc_scheduler_enable(struct drm_device *dev);
void guc_scheduler_disable(struct drm_device *dev);
+/* intel_guc_client.c */
+struct i915_guc_client*
+i915_guc_client_alloc(struct drm_device *dev, u32 priority);
+void i915_guc_client_free(struct drm_device *dev,
+ struct i915_guc_client *client);
+int i915_guc_client_submit(struct i915_guc_client *client,
+ struct intel_context *ctx,
+ struct intel_engine_cs *ring);
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_client.c
b/drivers/gpu/drm/i915/intel_guc_client.c
new file mode 100644
index 000..7922427
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_client.c
@@ -0,0 +1,430 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ *
[Intel-gfx] [PATCH v6 01/14] drm/i915: Defer default hardware context initialisation until first open
From: Dave Gordon david.s.gor...@intel.com
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which may not be possible during
driver load, because the filesystem(s) containing the firmware may not
be mounted until later.
Therefore, we now allow the first call to the firmware-loading code to
return -EAGAIN to indicate that it's not yet ready, and that it should
be retried when the device is first opened from user code, by which
time we expect that all required filesystems will have been mounted.
The late-retry code will then re-attempt to load the firmware if the
early attempt failed.
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 4 +++-
drivers/gpu/drm/i915/i915_gem_context.c | 31 ++-
3 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f3c77ca..31e13e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1757,6 +1757,7 @@ struct drm_i915_private {
/* hda/i915 audio component */
bool audio_component_registered;
+ bool contexts_ready;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e8f6f4c..db59821 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4865,7 +4865,9 @@ i915_gem_init_hw(struct drm_device *dev)
}
ret = i915_gem_context_enable(dev_priv);
- if (ret ret != -EIO) {
+ if (ret == 0) {
+ dev_priv-contexts_ready = true;
+ } else if (ret ret != -EIO) {
DRM_ERROR(Context enable failed %d\n, ret);
i915_gem_cleanup_ringbuffer(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5a47eb5..0edae87 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -447,23 +447,44 @@ static int context_idr_cleanup(int id, void *p, void
*data)
return 0;
}
+/* Complete any late initialisation here */
+static int i915_gem_context_first_open(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int ret;
+
+ ret = i915_gem_context_enable(dev_priv);
+ if (ret == 0)
+ dev_priv-contexts_ready = true;
+ return ret;
+}
+
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_file_private *file_priv = file-driver_priv;
struct intel_context *ctx;
+ int ret = 0;
idr_init(file_priv-context_idr);
mutex_lock(dev-struct_mutex);
- ctx = i915_gem_create_context(dev, file_priv);
+
+ if (!dev_priv-contexts_ready)
+ ret = i915_gem_context_first_open(dev);
+
+ if (ret == 0) {
+ ctx = i915_gem_create_context(dev, file_priv);
+ if (IS_ERR(ctx))
+ ret = PTR_ERR(ctx);
+ }
+
mutex_unlock(dev-struct_mutex);
- if (IS_ERR(ctx)) {
+ if (ret)
idr_destroy(file_priv-context_idr);
- return PTR_ERR(ctx);
- }
- return 0;
+ return ret;
}
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 14/14] Documentation/drm: kerneldoc for GuC
From: Alex Dai yu@intel.com Add overview design of GuC, plus some key points related to the implementation. Signed-off-by: Alex Dai yu@intel.com --- Documentation/DocBook/drm.tmpl | 19 +++ 1 file changed, 19 insertions(+) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7c68ecc..c3da928 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -4206,6 +4206,25 @@ int num_ioctls;/synopsis /sect1 sect1 + titleGuC Scheduler/title + sect2 +titleMicrocontroller (uC) firmware loading support/title +!Pdrivers/gpu/drm/i915/intel_uc_loader.c Microcontroller (uC) firmware loading support +!Idrivers/gpu/drm/i915/intel_uc_loader.c + /sect2 + sect2 +titleGuC/title +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC +!Idrivers/gpu/drm/i915/intel_guc_loader.c + /sect2 + sect2 +titleGuC Client/title +!Pdrivers/gpu/drm/i915/intel_guc_client.c GuC Client +!Idrivers/gpu/drm/i915/intel_guc_client.c + /sect2 +/sect1 + +sect1 title Tracing /title para This sections covers all things related to the tracepoints implemented in -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 07/14] drm/i915: Add functions to allocate / release gem obj for GuC
From: Alex Dai yu@intel.com
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/intel_guc.h| 3 ++
drivers/gpu/drm/i915/intel_guc_loader.c | 55 +
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c6886d1..3082a3e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -102,5 +102,8 @@ struct intel_guc {
extern int intel_guc_ucode_load(struct drm_device *dev, bool wait);
extern void intel_guc_ucode_fini(struct drm_device *dev);
extern void intel_guc_ucode_init(struct drm_device *dev);
+struct drm_i915_gem_object *
+intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size);
+void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 0f13620..49f3730 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -45,6 +45,12 @@
* The firmware installation package will install (symbolic link) proper
version
* of firmware.
*
+ * GuC address space:
+ * GuC does not allow any gfx GGTT address that falls into range [0,
WOPCM_TOP),
+ * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address
is
+ * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
+ * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ *
*/
#define I915_SKL_GUC_UCODE i915/skl_guc_ver1.bin
@@ -52,6 +58,55 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
#define I915_BXT_GUC_UCODE i915/bxt_guc_ver1.bin
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
+/**
+ * intel_guc_allocate_gem_obj() - Allocate gem object for GuC usage
+ * @dev: drm device
+ * @size: size of object
+ *
+ * This is a wrapper to create a gem obj. In order to use it inside GuC, the
+ * object needs to be pinned lifetime. Also we must pin it to gtt space other
+ * than [0, GUC_WOPCM_SIZE] because this range is reserved inside GuC.
+ *
+ * Return: A drm_i915_gem_object if successful, otherwise NULL.
+ */
+struct drm_i915_gem_object *
+intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_alloc_object(dev, size);
+ if (!obj)
+ return NULL;
+
+ if (i915_gem_object_get_pages(obj)) {
+ drm_gem_object_unreference(obj-base);
+ return NULL;
+ }
+
+ if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
+ PIN_OFFSET_BIAS | GUC_WOPCM_SIZE_VALUE)) {
+ drm_gem_object_unreference(obj-base);
+ return NULL;
+ }
+
+ return obj;
+}
+
+/**
+ * intel_guc_release_gem_obj() - Release gem object allocated for GuC usage
+ * @obj: gem obj to be released
+ */
+void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj)
+{
+ if (!obj)
+ return;
+
+ if (i915_gem_obj_is_pinned(obj))
+ i915_gem_object_ggtt_unpin(obj);
+
+ drm_gem_object_unreference(obj-base);
+}
+
/* Read GuC status register (GUC_STATUS)
* Return true if get a success code from normal boot or RC6 boot
*/
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/14] drm/i915: Move execlists defines from .c to .h
From: Michael H. Nguyen michael.h.ngu...@intel.com
Move defines from intel_lrc.c to i915_reg.h so they are
accessible by the guc files
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen michael.h.ngu...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 77
drivers/gpu/drm/i915/intel_lrc.c | 76 ---
2 files changed, 77 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e35d7f2..64beedb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7749,4 +7749,81 @@ enum skl_disp_power_wells {
#define _PALETTE_A (dev_priv-info.display_mmio_offset + 0xa000)
#define _PALETTE_B (dev_priv-info.display_mmio_offset + 0xa800)
+/* Exec Lists */
+#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
+#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
+
+#define RING_EXECLIST_QFULL(1 0x2)
+#define RING_EXECLIST1_VALID (1 0x3)
+#define RING_EXECLIST0_VALID (1 0x4)
+#define RING_EXECLIST_ACTIVE_STATUS(3 0xE)
+#define RING_EXECLIST1_ACTIVE (1 0x11)
+#define RING_EXECLIST0_ACTIVE (1 0x12)
+
+#define GEN8_CTX_STATUS_IDLE_ACTIVE(1 0)
+#define GEN8_CTX_STATUS_PREEMPTED (1 1)
+#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 2)
+#define GEN8_CTX_STATUS_ACTIVE_IDLE(1 3)
+#define GEN8_CTX_STATUS_COMPLETE (1 4)
+#define GEN8_CTX_STATUS_LITE_RESTORE (1 15)
+
+#define CTX_LRI_HEADER_0 0x01
+#define CTX_CONTEXT_CONTROL0x02
+#define CTX_RING_HEAD 0x04
+#define CTX_RING_TAIL 0x06
+#define CTX_RING_BUFFER_START 0x08
+#define CTX_RING_BUFFER_CONTROL0x0a
+#define CTX_BB_HEAD_U 0x0c
+#define CTX_BB_HEAD_L 0x0e
+#define CTX_BB_STATE 0x10
+#define CTX_SECOND_BB_HEAD_U 0x12
+#define CTX_SECOND_BB_HEAD_L 0x14
+#define CTX_SECOND_BB_STATE0x16
+#define CTX_BB_PER_CTX_PTR 0x18
+#define CTX_RCS_INDIRECT_CTX 0x1a
+#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
+#define CTX_LRI_HEADER_1 0x21
+#define CTX_CTX_TIMESTAMP 0x22
+#define CTX_PDP3_UDW 0x24
+#define CTX_PDP3_LDW 0x26
+#define CTX_PDP2_UDW 0x28
+#define CTX_PDP2_LDW 0x2a
+#define CTX_PDP1_UDW 0x2c
+#define CTX_PDP1_LDW 0x2e
+#define CTX_PDP0_UDW 0x30
+#define CTX_PDP0_LDW 0x32
+#define CTX_LRI_HEADER_2 0x41
+#define CTX_R_PWR_CLK_STATE0x42
+#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+
+#define GEN8_CTX_VALID (10)
+#define GEN8_CTX_FORCE_PD_RESTORE (11)
+#define GEN8_CTX_FORCE_RESTORE (12)
+#define GEN8_CTX_L3LLC_COHERENT (15)
+#define GEN8_CTX_PRIVILEGE (18)
+
+#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
+ const u64 _addr = test_bit(n, ppgtt-pdp.used_pdpes) ? \
+ ppgtt-pdp.page_directory[n]-daddr : \
+ ppgtt-scratch_pd-daddr; \
+ reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
+ reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
+}
+
+enum {
+ ADVANCED_CONTEXT = 0,
+ LEGACY_CONTEXT,
+ ADVANCED_AD_CONTEXT,
+ LEGACY_64B_CONTEXT
+};
+#define GEN8_CTX_MODE_SHIFT 3
+enum {
+ FAULT_AND_HANG = 0,
+ FAULT_AND_HALT, /* Debug only */
+ FAULT_AND_STREAM,
+ FAULT_AND_CONTINUE /* Unsupported */
+};
+#define GEN8_CTX_ID_SHIFT 32
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 732fd63..da58da2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,82 +136,6 @@
#include drm/i915_drm.h
#include i915_drv.h
-#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
-#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
-#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
-
-#define RING_EXECLIST_QFULL(1 0x2)
-#define RING_EXECLIST1_VALID (1 0x3)
-#define RING_EXECLIST0_VALID (1 0x4)
-#define RING_EXECLIST_ACTIVE_STATUS(3 0xE)
-#define RING_EXECLIST1_ACTIVE (1 0x11)
-#define RING_EXECLIST0_ACTIVE (1 0x12)
-
-#define GEN8_CTX_STATUS_IDLE_ACTIVE(1 0)
-#define GEN8_CTX_STATUS_PREEMPTED (1 1)
-#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 2)
-#define GEN8_CTX_STATUS_ACTIVE_IDLE(1 3)
-#define GEN8_CTX_STATUS_COMPLETE (1 4)
-#define GEN8_CTX_STATUS_LITE_RESTORE (1 15)
-
-#define CTX_LRI_HEADER_0 0x01
-#define CTX_CONTEXT_CONTROL0x02
-#define CTX_RING_HEAD 0x04
-#define CTX_RING_TAIL 0x06
-#define CTX_RING_BUFFER_START 0x08
[Intel-gfx] [PATCH v6 10/14] drm/i915: Interrupt routing for GuC scheduler
From: Alex Dai yu@intel.com
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 11 --
drivers/gpu/drm/i915/intel_guc.h | 7
drivers/gpu/drm/i915/intel_guc_scheduler.c | 55 +-
3 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d56546d..c298163 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1610,12 +1610,18 @@ enum skl_disp_power_wells {
#define GFX_MODE_GEN7 0x0229c
#define RING_MODE_GEN7(ring) ((ring)-mmio_base+0x29c)
#define GFX_RUN_LIST_ENABLE (115)
+#define GFX_INTERRUPT_STEERING (114)
#define GFX_TLB_INVALIDATE_EXPLICIT (113)
#define GFX_SURFACE_FAULT_ENABLE (112)
#define GFX_REPLAY_MODE (111)
#define GFX_PSMI_GRANULARITY (110)
#define GFX_PPGTT_ENABLE (19)
+#define GFX_FORWARD_VBLANK_MASK (35)
+#define GFX_FORWARD_VBLANK_NEVER (05)
+#define GFX_FORWARD_VBLANK_ALWAYS(15)
+#define GFX_FORWARD_VBLANK_COND (25)
+
#define VLV_DISPLAY_BASE 0x18
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
@@ -5566,11 +5572,12 @@ enum skl_disp_power_wells {
#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
-#define GEN8_BCS_IRQ_SHIFT 16
#define GEN8_RCS_IRQ_SHIFT 0
-#define GEN8_VCS2_IRQ_SHIFT 16
+#define GEN8_BCS_IRQ_SHIFT 16
#define GEN8_VCS1_IRQ_SHIFT 0
+#define GEN8_VCS2_IRQ_SHIFT 16
#define GEN8_VECS_IRQ_SHIFT 0
+#define GEN8_WD_IRQ_SHIFT 16
#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index fd6f394..892f974 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -137,6 +137,13 @@ struct intel_guc {
#define GEN8_DRB_VALID (10)
#define GEN8_DRBREGU(x) (0x1000 + (x) * 8 + 4)
+#define DE_GUCRMR 0x44054
+
+#define GUC_BCS_RCS_IER0xC550
+#define GUC_VCS2_VCS1_IER 0xC554
+#define GUC_WD_VECS_IER0xC558
+#define GUC_PM_P24C_IER0xC55C
+
/* intel_guc_loader.c */
extern int intel_guc_ucode_load(struct drm_device *dev, bool wait);
extern void intel_guc_ucode_fini(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_scheduler.c
b/drivers/gpu/drm/i915/intel_guc_scheduler.c
index 962443c..669d066 100644
--- a/drivers/gpu/drm/i915/intel_guc_scheduler.c
+++ b/drivers/gpu/drm/i915/intel_guc_scheduler.c
@@ -25,6 +25,53 @@
#include i915_drv.h
#include intel_guc.h
+static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *ring;
+ int i, irqs;
+
+ /* tell all command streamers to forward interrupts and vblank to GuC */
+ irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK,
GFX_FORWARD_VBLANK_ALWAYS);
+ irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MODE_GEN7(ring), irqs);
+
+ /* tell DE to send (all) flip_done to GuC */
+ irqs = DERRMR_PIPEA_PRI_FLIP_DONE | DERRMR_PIPEA_SPR_FLIP_DONE |
+ DERRMR_PIPEB_PRI_FLIP_DONE | DERRMR_PIPEB_SPR_FLIP_DONE |
+ DERRMR_PIPEC_PRI_FLIP_DONE | DERRMR_PIPEC_SPR_FLIP_DONE;
+ /* Unmasked bits will cause GuC response message to be sent */
+ I915_WRITE(DE_GUCRMR, ~irqs);
+
+ /* route USER_INTERRUPT to Host, all others are sent to GuC. */
+ irqs = GT_RENDER_USER_INTERRUPT GEN8_RCS_IRQ_SHIFT |
+ GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT;
+ /* These three registers have the same bit definitions */
+ I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
+ I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
+ I915_WRITE(GUC_WD_VECS_IER, ~irqs);
+}
+
+static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *ring;
+ int i, irqs;
+
+ /* tell all command streamers NOT to forward interrupts and vblank to
GuC */
+ irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
+ irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MODE_GEN7(ring), irqs);
+
+ /* tell DE to send nothing to GuC */
+ I915_WRITE(DE_GUCRMR, ~0);
+
+ /* route all GT interrupts to the host */
+ I915_WRITE(GUC_BCS_RCS_IER, 0);
+ I915_WRITE(GUC_VCS2_VCS1_IER, 0);
+ I915_WRITE(GUC_WD_VECS_IER, 0);
+}
+
void guc_scheduler_fini(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -77,8 +124,10 @@ int
[Intel-gfx] [PATCH v6 02/14] drm/i915: Add i915_gem_object_write() to i915_gem.c
From: Michael H. Nguyen michael.h.ngu...@intel.com
i915_gem_object_write() is a generic function to copy data from
user memory to gem object.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 28
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 31e13e9..f5068cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2646,6 +2646,8 @@ void i915_init_vm(struct drm_i915_private *dev_priv,
struct i915_address_space *vm);
void i915_gem_free_object(struct drm_gem_object *obj);
void i915_gem_vma_destroy(struct i915_vma *vma);
+int i915_gem_object_write(struct drm_i915_gem_object *obj,
+ const void *data, const size_t size);
/* Flags used by pin/bindfriends. */
#define PIN_MAPPABLE (10)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index db59821..fabe8de 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5238,3 +5238,31 @@ bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj)
return false;
}
+/* Fill the @obj with the @size amount of @data */
+int i915_gem_object_write(struct drm_i915_gem_object *obj,
+ const void *data, const size_t size)
+{
+ struct sg_table *sg;
+ size_t bytes;
+ int ret;
+
+ ret = i915_gem_object_get_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_pin_pages(obj);
+
+ sg = obj-pages;
+
+ bytes = sg_copy_from_buffer(sg-sgl, sg-nents, (void *)data, size);
+
+ i915_gem_object_unpin_pages(obj);
+
+ if (WARN_ON(bytes != size)) {
+ DRM_ERROR(Uncompleted copy, wrote %zu of %zu, bytes, size);
+ i915_gem_object_put_pages(obj);
+ return -EIO;
+ }
+
+ return 0;
+}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 11/14] drm/i915: Enable commands submission via GuC
From: Alex Dai yu@intel.com
Add functions to submit work queue item and ring the door bell.
GuC TLB needs to be invalided if LRC context changes.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/intel_guc.h| 3 +
drivers/gpu/drm/i915/intel_guc_client.c | 198 +++-
drivers/gpu/drm/i915/intel_lrc.c| 34 +-
drivers/gpu/drm/i915/intel_lrc.h| 2 +
4 files changed, 230 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 892f974..f8065cf 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
#define GUC_WQ_SIZE(PAGE_SIZE * 2)
struct i915_guc_client {
+ spinlock_t wq_lock;
struct drm_i915_gem_object *client_obj;
u32 priority;
off_t doorbell_offset;
@@ -39,6 +40,8 @@ struct i915_guc_client {
uint16_t doorbell_id;
uint32_t ctx_index;
uint32_t wq_size;
+ uint32_t wq_tail;
+ uint32_t cookie;
};
#define I915_MAX_DOORBELLS 256
diff --git a/drivers/gpu/drm/i915/intel_guc_client.c
b/drivers/gpu/drm/i915/intel_guc_client.c
index 7922427..31934a3 100644
--- a/drivers/gpu/drm/i915/intel_guc_client.c
+++ b/drivers/gpu/drm/i915/intel_guc_client.c
@@ -22,6 +22,7 @@
*
*/
#include linux/firmware.h
+#include linux/circ_buf.h
#include i915_drv.h
#include intel_guc.h
@@ -52,6 +53,14 @@
* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
* mapped into process space.
*
+ * Work Items:
+ * There are several types of work items that the host may place into a
+ * workqueue, each with its own requirements and limitations. Currently only
+ * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
+ * represents in-order queue. The kernel driver packs ring tail pointer and an
+ * ELSP context descriptor dword into Work Item.
+ * See add_workqueue_item()
+ *
*/
/*
@@ -395,6 +404,8 @@ i915_guc_client_alloc(struct drm_device *dev, u32 priority)
/* XXX: evict a doorbell instead */
goto err;
+ spin_lock_init(client-wq_lock);
+
init_ctx_desc(guc, client);
init_proc_desc(guc, client);
init_doorbell(guc, client);
@@ -414,6 +425,183 @@ err:
return NULL;
}
+/* Get valid workqueue item and return it back to offset */
+static int get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
+{
+ struct guc_process_desc *desc;
+ void *base;
+ u32 size = sizeof(struct guc_wq_item);
+ int ret = 0, timeout_counter = 200;
+ unsigned long flags;
+
+ base = kmap_atomic(i915_gem_object_get_page(gc-client_obj, 0));
+ desc = base + gc-proc_desc_offset;
+
+ while (timeout_counter-- 0) {
+ spin_lock_irqsave(gc-wq_lock, flags);
+
+ ret = wait_for_atomic(CIRC_SPACE(gc-wq_tail, desc-head,
+ gc-wq_size) = size, 1);
+
+ if (!ret) {
+ *offset = gc-wq_tail;
+
+ /* advance the tail for next workqueue item */
+ gc-wq_tail += size;
+ gc-wq_tail = gc-wq_size - 1;
+
+ /* this will break the loop */
+ timeout_counter = 0;
+ }
+
+ spin_unlock_irqrestore(gc-wq_lock, flags);
+ };
+
+ kunmap_atomic(base);
+
+ return ret;
+}
+
+static void guc_update_context(struct intel_context *ctx,
+ struct intel_engine_cs *ring)
+{
+ struct intel_ringbuffer *ringbuf = ctx-engine[ring-id].ringbuf;
+ struct drm_i915_gem_object *ctx_obj = ctx-engine[ring-id].state;
+ struct page *page;
+ uint32_t *reg_state;
+
+ page = i915_gem_object_get_page(ctx_obj, 1);
+ reg_state = kmap_atomic(page);
+
+ reg_state[CTX_RING_BUFFER_START + 1] =
+ i915_gem_obj_ggtt_offset(ringbuf-obj);
+
+ /* True PPGTT with dynamic page allocation: update PDP registers and
+* point the unallocated PDPs to the scratch page
+*/
+ if (ctx-ppgtt) {
+ ASSIGN_CTX_PDP(ctx-ppgtt, reg_state, 3);
+ ASSIGN_CTX_PDP(ctx-ppgtt, reg_state, 2);
+ ASSIGN_CTX_PDP(ctx-ppgtt, reg_state, 1);
+ ASSIGN_CTX_PDP(ctx-ppgtt, reg_state, 0);
+ }
+
+ kunmap_atomic(reg_state);
+}
+
+static int add_workqueue_item(struct i915_guc_client *gc,
+ struct intel_context *ctx,
+ struct intel_engine_cs *ring)
+{
+ struct intel_ringbuffer *ringbuf = ctx-engine[ring-id].ringbuf;
+ struct drm_i915_gem_object *ctx_obj;
+ struct guc_wq_item *wqi;
+ void *base;
+ u32 wq_off = 0, tail = ringbuf-tail, wq_len;
+ int ret;
+
+ ctx_obj = ctx-engine[ring-id].state;
+
+ /*
[Intel-gfx] [PATCH v6 03/14] drm/i915: Unified firmware loading mechanism
From: Dave Gordon david.s.gor...@intel.com
Factor out the common code of loading firmware into a new file,
leaving only the uC-specific parts in the GuC loaders.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/intel_uc_loader.c | 310 +
drivers/gpu/drm/i915/intel_uc_loader.h | 82 +
3 files changed, 395 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_uc_loader.c
create mode 100644 drivers/gpu/drm/i915/intel_uc_loader.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a69002e..1b027c7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -39,6 +39,9 @@ i915-y += i915_cmd_parser.o \
intel_ringbuffer.o \
intel_uncore.o
+# ancilliary microcontroller support
+i915-y += intel_uc_loader.o
+
# autogenerated null render state
i915-y += intel_renderstate_gen6.o \
intel_renderstate_gen7.o \
diff --git a/drivers/gpu/drm/i915/intel_uc_loader.c
b/drivers/gpu/drm/i915/intel_uc_loader.c
new file mode 100644
index 000..75dc17d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_uc_loader.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Dave Gordon david.s.gor...@intel.com
+ */
+#include linux/firmware.h
+#include i915_drv.h
+#include intel_uc_loader.h
+
+/**
+ * DOC: Generic embedded microcontroller (uC) firmware loading support
+ *
+ * The functions in this file provide a generic way to load the firmware that
+ * may be required by an embedded microcontroller (uC).
+ *
+ * The function intel_uc_fw_init() should be called early, and will initiate
+ * an asynchronous request to fetch the firmware image (aka binary blob).
+ * When the image has been fetched into memory, the kernel will call back to
+ * uc_fw_fetch_callback() whose function is simply to record the completion
+ * status, and stash the firmware blob for later.
+ *
+ * At some convenient point after GEM initialisation, the driver should call
+ * intel_uc_fw_check(); this will check whether the asynchronous thread has
+ * completed and wait for it if not, check whether the image was successfully
+ * fetched; and then allow the callback() function (if provided) to validate
+ * the image and/or save the data in a GEM object.
+ *
+ * Thereafter the uC-specific code can transfer the data in the GEM object
+ * to the uC's memory (in some uC-specific way, not handled here).
+ *
+ * During driver shutdown, or if driver load is aborted, intel_uc_fw_fini()
+ * should be called to release any remaining resources.
+ */
+
+
+/*
+ * Called once per uC, late in driver initialisation. GEM is now ready, and so
+ * we can now create a GEM object to hold the uC firmware. But first, we must
+ * synchronise with the firmware-fetching thread that was initiated during
+ * early driver load, in intel_uc_fw_init(), and see whether it successfully
+ * fetched the firmware blob.
+ */
+static void
+uc_fw_fetch_wait(struct intel_uc_fw *uc_fw, bool callback(struct intel_uc_fw
*))
+{
+ struct drm_device *dev = uc_fw-uc_dev;
+ struct drm_i915_gem_object *obj;
+ const struct firmware *fw;
+
+ DRM_DEBUG_DRIVER(before waiting: %s fw fetch status %d, fw %p\n,
+ uc_fw-uc_name, uc_fw-uc_fw_fetch_status, uc_fw-uc_fw_blob);
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+ WARN_ON(uc_fw-uc_fw_fetch_status != INTEL_UC_FIRMWARE_PENDING);
+
+ wait_for_completion(uc_fw-uc_fw_fetched);
+
+ DRM_DEBUG_DRIVER(after waiting: %s fw fetch status %d, fw %p\n,
+ uc_fw-uc_name, uc_fw-uc_fw_fetch_status, uc_fw-uc_fw_blob);
+
+ fw = uc_fw-uc_fw_blob;
+ if (!fw) {
+ /* no firmware found; try
[Intel-gfx] [PATCH v6 08/14] drm/i915: Functions to support command submission via GuC
From: Alex Dai yu@intel.com
To enable GuC command submission / scheduling, we need to setup
firmware initializaion properly. i915.enable_guc_scheduling is
introduced to enable / disable GuC submission.
GuC firmware uses the one page after Ring Context as shared data.
However, GuC uses same offset to address this page for all rings.
So we have to allocate same size of lrc context for all rings.
Also, reduce ring buffer size to 4 pages. In GuC, work queue tail is
referenced by 11 bits (WQ_RING_TAIL_MASK). It is in QW, so total 14
bits (4 pages).
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_params.c | 4 ++
drivers/gpu/drm/i915/intel_guc.h | 8 +++
drivers/gpu/drm/i915/intel_guc_loader.c| 52
drivers/gpu/drm/i915/intel_guc_scheduler.c | 78 ++
drivers/gpu/drm/i915/intel_lrc.c | 23 +++--
7 files changed, 153 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_scheduler.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6188302..50b2057 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -37,7 +37,8 @@ i915-y += i915_cmd_parser.o \
i915_trace_points.o \
intel_lrc.o \
intel_ringbuffer.o \
- intel_uncore.o
+ intel_uncore.o \
+ intel_guc_scheduler.o
# ancilliary microcontroller support
i915-y += intel_uc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b0b901d..248 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2499,6 +2499,7 @@ struct i915_params {
bool reset;
bool disable_display;
bool disable_vtd_wa;
+ bool enable_guc_scheduling;
int use_mmio_flip;
int mmio_debug;
bool verbose_state_checks;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index bb64415..9ad2e27 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -53,6 +53,7 @@ struct i915_params i915 __read_mostly = {
.mmio_debug = 0,
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
+ .enable_guc_scheduling = false,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -184,3 +185,6 @@ MODULE_PARM_DESC(verbose_state_checks,
module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0600);
MODULE_PARM_DESC(nuclear_pageflip,
Force atomic modeset functionality; only planes work for now
(default: false).);
+
+module_param_named(enable_guc_scheduling, i915.enable_guc_scheduling, bool,
0400);
+MODULE_PARM_DESC(enable_guc_scheduling, Enable GuC scheduling
(default:false));
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3082a3e..bf80f32 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -34,6 +34,8 @@ struct intel_guc {
/* GuC-specific additions */
uint32_t fw_ver_major;
uint32_t fw_ver_minor;
+
+ struct drm_i915_gem_object *ctx_pool_obj;
};
#define GUC_STATUS 0xc000
@@ -106,4 +108,10 @@ struct drm_i915_gem_object *
intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size);
void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj);
+/* intel_guc_scheduler.c */
+int guc_scheduler_init(struct drm_device *dev);
+void guc_scheduler_fini(struct drm_device *dev);
+int guc_scheduler_enable(struct drm_device *dev);
+void guc_scheduler_disable(struct drm_device *dev);
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 49f3730..5e021db 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -229,6 +229,36 @@ static void set_guc_init_params(struct drm_i915_private
*dev_priv)
/* XXX: Set up log buffer */
+ /* If GuC scheduling is enabled, setup params here. */
+ if (i915.enable_guc_scheduling) {
+ u32 pgs = i915_gem_obj_ggtt_offset(dev_priv-guc.ctx_pool_obj);
+ u32 ctx_in_16 = MAX_GUC_GPU_CONTEXTS / 16;
+
+ pgs = PAGE_SHIFT;
+ params[GUC_CTL_CTXINFO] = (pgs GUC_CTL_BASE_ADDR_SHIFT) |
+ (ctx_in_16 GUC_CTL_CTXNUM_IN16_SHIFT);
+
+ /* The shared data is one page following the Ring Context.
+* So the offset is the page number of LRC */
+ pgs = IS_GEN9(dev_priv-dev) ? GEN9_LR_CONTEXT_RENDER_SIZE :
+ GEN8_LR_CONTEXT_RENDER_SIZE;
+ pgs = PAGE_SHIFT;
+ params[GUC_CTL_OFFSET] |= pgs GUC_CTL_SHARED_DATA_SHIFT;
+
+ /* This must be non-zero for scheduler to
[Intel-gfx] [PATCH v6 00/14] Command submission via GuC for SKL
From: Alex Dai yu@intel.com This series of patch is to enable ExecList submission via GuC. It is verified by some basic IGT tests on HAS and SKL HW. Here are some key points related to this series, not in particular order. v6: - Changed the firmware name to skl_guc_ver1.bin, followed naming convention platform_guc_major-version.bin - Fixed one issue pointed out by Chris W. Should not touch legacy ringbuf size. - The uc loader is slightly modified by Dave G. v5: - Firmware loading mechnism is changed - More verbose GuC info to debugfs - Code has be re-organized v4: - Use PIN_OFFSET_BIAS to pin gfx object into gtt space out of WPOCM mm range - Fix issues in interrupts routing that causes VBlank timeout - Change the way how to wait DMA complete after load firmware - Address more issues from review v3: - Completely new rewritten GuC interface header file - Address some issues found from review v2: - Address some coding issues, especially in firmware interface header files - Clean up some paches and remove a couple ones not really needed - Fix a GuC loading issue when HuC is loaded first. Need to dirty GuC TLB cache before loading GuC. The fix is ammended to patch 'add MMIO WA settings'. *** i915_guc_client *** We use the term client to avoid confusion with contexts. A i915_guc_client is equivalent to GuC object guc_context_desc. This context descriptor is allocated from a pool of 1024 entries. Kernel driver will allocate doorbell and workqueue for it. Also the process descriptor (guc_process_desc), which is mapped to client space. So the client can write Work Item then ring the doorbell. To simplify the implementation, we allocate one gem object that contains all pages for doorbell, process descriptor and workqueue. *** intel_guc *** Top level structure of guc. It handles firmware loading and manages client pool and doorbells. intel_guc owns a i915_guc_client to do the legacy submission. ** The Scratch registers *** There are 16 MMIO-based registers start from 0xC180. The kernel driver writes a value to the action register (SOFT_SCRATCH_0) along with any data. It then triggers an interrupt on the GuC via another register write (0xC4C8). Firmware writes a success/fail code back to the action register after processes the request. The kernel driver polls waiting for this update and then proceeds. Details in intel_guc_action() *** Work Items *** There are several types of work items that the host may place into a workqueue, each with its own requirements and limitations. Currently only WQ_TYPE_INORDER is used to support legacy submission via GuC, which represents in-order queue. The kernel driver packs ring tail pointer and an ELSP context descriptor dword into Work Item. Details in add_workqueue_item() *** Doorbells *** Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) mapped into process space. Details in ring_doorbell() *** Firmware versioning *** The firmware build process will generate a version header file with major and minor version defined. The versions are built into CSS header of firmware too. i915 kernel driver set the minimal firmware version required by each platform. The firmware installation package will install (symbolic link) proper version of firmware. *** Firmware log *** Firmware log is enabled by setting i915.guc_log_level to non-negative level. Log data is printed out via reading debugfs i915_guc_log_dump. Reading from i915_guc_load_status will print out firmware loading status and scratch registers value. TODO: the buffer works like a ring. To not missing any data, driver should handle a GuC2Host interrupt (triggered when log buffer is half full) from GuC. *** Ring buffer size *** It is up to 16K (4 pages) per LRC. Not HW limitation but firmware is setup in this way. *** GuC address space *** GuC is not expecting any gfx GGTT address that falls into range [0, WOPCM_TOP), which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is 512K in order to fit in big HuC firmware. In order to exclude 0-512K address space from GGTT, all gfx objects used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. Alex Dai (10): drm/i915: Add guc firmware interface headers drm/i915: GuC firmware loader drm/i915: Add functions to allocate / release gem obj for GuC drm/i915: Functions to support command submission via GuC drm/i915: Integration of GuC client drm/i915: Interrupt routing for GuC scheduler drm/i915: Enable commands submission via GuC drm/i915: debugfs of GuC status drm/i915: Enable GuC firmware log Documentation/drm: kerneldoc for GuC Dave Gordon (2): drm/i915: Defer default hardware context initialisation until first open drm/i915: Unified firmware loading mechanism Michael H. Nguyen (2): drm/i915: Add i915_gem_object_write() to i915_gem.c drm/i915: Move execlists defines from .c to .h Documentation/DocBook/drm.tmpl | 19 + drivers/gpu/drm/i915/Makefile
Re: [Intel-gfx] [PATCH v2] drm/i915: Setup static bias for GPU
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6281 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK -1 302/302 301/302 SNB 316/316 316/316 IVB 264/264 264/264 BYT -3 227/227 224/227 BDW 318/318 318/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *ILK igt@gem_caching@reads PASS(2) NO_RESULT(1)PASS(1) *BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(5) TIMEOUT(1)PASS(1) *BYT igt@gem_exec_parse@bitmasks FAIL(1)PASS(4) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(3)PASS(3) TIMEOUT(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/16] drm/i915: Implement inter-engine read-read optimisations
On 04/27/2015 01:41 PM, Chris Wilson wrote: Currently, we only track the last request globally across all engines. This prevents us from issuing concurrent read requests on e.g. the RCS and BCS engines (or more likely the render and media engines). Without semaphores, we incur costly stalls as we synchronise between rings - greatly impacting the current performance of Broadwell versus Haswell in certain workloads (like video decode). With the introduction of reference counted requests, it is much easier to track the last request per ring, as well as the last global write request so that we can optimise inter-engine read read requests (as well as better optimise certain CPU waits). v2: Fix inverted readonly condition for nonblocking waits. v3: Handle non-continguous engine array after waits v4: Rebase, tidy, rewrite ring list debugging v5: Use obj-active as a bitfield, it looks cool v6: Micro-optimise, mostly involving moving code around v7: Fix retire-requests-upto for execlists (and multiple rq-ringbuf) v8: Rebase v9: Refactor i915_gem_object_sync() to allow the compiler to better optimise it. Looks OK, you can upgrade my r-b to v9. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] igt_fb: Transfer existing content to Cairo surface for Y/Yf frame buffers
On Wed, Apr 29, 2015 at 01:24:34PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Rendering into Y and Yf tiled frame buffers with Cairo was losing the
previous content ie. was starting from black. This is different than the
behaviour with linear and X tiled so make it the same by blitting the
initial content when creating the rendering context.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
This looks fine to me, pushed.
--
Damien
---
lib/igt_fb.c | 56
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 6dc22bb..fe0c63f 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -650,11 +650,27 @@ struct fb_blit_upload {
} linear;
};
+static unsigned int fb_mod_to_obj_tiling(uint64_t fb_mod)
+{
+ switch (fb_mod) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ return I915_TILING_NONE;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ return I915_TILING_X;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ return I915_TILING_Y;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ return I915_TILING_Yf;
+ default:
+ igt_assert(0);
+ }
+}
+
static void destroy_cairo_surface__blit(void *arg)
{
struct fb_blit_upload *blit = arg;
struct igt_fb *fb = blit-fb;
- unsigned int obj_tiling = I915_TILING_NONE;
+ unsigned int obj_tiling = fb_mod_to_obj_tiling(fb-tiling);
munmap(blit-linear.map, blit-linear.size);
fb-cairo_surface = NULL;
@@ -662,18 +678,6 @@ static void destroy_cairo_surface__blit(void *arg)
gem_set_domain(blit-fd, blit-linear.handle,
I915_GEM_DOMAIN_GTT, 0);
- switch (fb-tiling) {
- case LOCAL_I915_FORMAT_MOD_X_TILED:
- obj_tiling = I915_TILING_X;
- break;
- case LOCAL_I915_FORMAT_MOD_Y_TILED:
- obj_tiling = I915_TILING_Y;
- break;
- case LOCAL_I915_FORMAT_MOD_Yf_TILED:
- obj_tiling = I915_TILING_Yf;
- break;
- }
-
igt_blitter_fast_copy__raw(blit-fd,
blit-linear.handle,
blit-linear.stride,
@@ -695,6 +699,7 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
{
struct fb_blit_upload *blit;
cairo_format_t cairo_format;
+ unsigned int obj_tiling = fb_mod_to_obj_tiling(fb-tiling);
int bpp, ret;
blit = malloc(sizeof(*blit));
@@ -716,6 +721,28 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
blit-fd = fd;
blit-fb = fb;
+
+ /* Copy fb content to linear BO */
+ gem_set_domain(fd, blit-linear.handle,
+ I915_GEM_DOMAIN_GTT, 0);
+
+ igt_blitter_fast_copy__raw(fd,
+fb-gem_handle,
+fb-stride,
+obj_tiling,
+0, 0, /* src_x, src_y */
+fb-width, fb-height,
+blit-linear.handle,
+blit-linear.stride,
+I915_TILING_NONE,
+0, 0 /* dst_x, dst_y */);
+
+ gem_sync(fd, blit-linear.handle);
+
+ gem_set_domain(fd, blit-linear.handle,
+I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ /* Setup cairo context */
blit-linear.map = gem_mmap__cpu(fd,
blit-linear.handle,
0,
@@ -723,9 +750,6 @@ static void create_cairo_surface__blit(int fd, struct
igt_fb *fb)
PROT_READ | PROT_WRITE);
igt_assert(blit-linear.map);
- gem_set_domain(fd, blit-linear.handle,
-I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
-
cairo_format = drm_format_to_cairo(fb-drm_format);
fb-cairo_surface =
cairo_image_surface_create_for_data(blit-linear.map,
--
2.3.5
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Re: [Intel-gfx] [PATCH 07/16] drm/i915: Inline check required for object syncing prior to execbuf
Hi,
On 04/27/2015 01:41 PM, Chris Wilson wrote:
This trims a little overhead from the common case of not needing to
synchronize between rings.
v2: execlists is special and likes to duplicate code.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++---
drivers/gpu/drm/i915/intel_lrc.c | 9 ++---
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 45d74da7f6c4..4fe09568089b 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -889,6 +889,7 @@ static int
i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
struct list_head *vmas)
{
+ const unsigned other_rings = ~intel_ring_flag(ring);
struct i915_vma *vma;
uint32_t flush_domains = 0;
bool flush_chipset = false;
@@ -896,9 +897,12 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
- ret = i915_gem_object_sync(obj, ring);
- if (ret)
- return ret;
+
+ if (obj-active other_rings) {
+ ret = i915_gem_object_sync(obj, ring);
+ if (ret)
+ return ret;
+ }
Just to avoid bailing out near the top of i915_gem_object_sync?
Anyway,
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Regards,
Tvrtko
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[Intel-gfx] [PATCH 7/8] drm/i915: Use the CRC gpio for panel enable/disable
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use the newer gpiod interface(Alexandre)
v3: Remove the redundant checks and unused code (Ville)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 32 ++--
drivers/gpu/drm/i915/intel_dsi.h | 6 ++
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5196642..be55ffa 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -31,6 +31,7 @@
#include drm/drm_panel.h
#include drm/drm_mipi_dsi.h
#include linux/slab.h
+#include linux/gpio/consumer.h
#include i915_drv.h
#include intel_drv.h
#include intel_dsi.h
@@ -415,6 +416,12 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
DRM_DEBUG_KMS(\n);
+ /* Panel Enable over CRC PMIC */
+ if (intel_dsi-gpio_panel)
+ gpiod_set_value_cansleep(intel_dsi-gpio_panel, 1);
+
+ msleep(intel_dsi-panel_on_delay);
+
/* Disable DPOunit clock gating, can stall pipe
* and we need DPLL REFA always enabled */
tmp = I915_READ(DPLL(pipe));
@@ -432,8 +439,6 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
/* put device in ready state */
intel_dsi_device_ready(encoder);
- msleep(intel_dsi-panel_on_delay);
-
drm_panel_prepare(intel_dsi-panel);
for_each_dsi_port(port, intel_dsi-ports)
@@ -576,6 +581,10 @@ static void intel_dsi_post_disable(struct intel_encoder
*encoder)
msleep(intel_dsi-panel_off_delay);
msleep(intel_dsi-panel_pwr_cycle_delay);
+
+ /* Panel Disable over CRC PMIC */
+ if (intel_dsi-gpio_panel)
+ gpiod_set_value_cansleep(intel_dsi-gpio_panel, 0);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -955,6 +964,11 @@ static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder)
/* XXX: Logically this call belongs in the panel driver. */
drm_panel_remove(intel_dsi-panel);
}
+
+ /* dispose of the gpios */
+ if (intel_dsi-gpio_panel)
+ gpiod_put(intel_dsi-gpio_panel);
+
intel_encoder_destroy(encoder);
}
@@ -1071,6 +1085,20 @@ void intel_dsi_init(struct drm_device *dev)
goto err;
}
+ /*
+* In case of BYT with CRC PMIC, we need to use GPIO for
+* Panel control.
+*/
+ if (dev_priv-vbt.dsi.config-pwm_blc == PPS_BLC_PMIC) {
+ intel_dsi-gpio_panel =
+ gpiod_get(dev-dev, panel, GPIOD_OUT_HIGH);
+
+ if (IS_ERR(intel_dsi-gpio_panel)) {
+ DRM_ERROR(Failed to own gpio for panel control\n);
+ intel_dsi-gpio_panel = NULL;
+ }
+ }
+
intel_encoder-type = INTEL_OUTPUT_DSI;
intel_encoder-cloneable = 0;
drm_connector_init(dev, connector, intel_dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..bf1bade 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -29,6 +29,9 @@
#include drm/drm_mipi_dsi.h
#include intel_drv.h
+#define PPS_BLC_PMIC 0
+#define PPS_BLC_SOC1
+
/* Dual Link support */
#define DSI_DUAL_LINK_NONE 0
#define DSI_DUAL_LINK_FRONT_BACK 1
@@ -42,6 +45,9 @@ struct intel_dsi {
struct drm_panel *panel;
struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
+ /* GPIO Desc for CRC based Panel control */
+ struct gpio_desc *gpio_panel;
+
struct intel_connector *attached_connector;
/* bit mask of ports being driven */
--
2.1.0
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[Intel-gfx] [PATCH 8/8] drm/i915: Backlight control using CRC PMIC based PWM driver
Use the CRC PWM device in intel_panel.c and add new MIPI backlight
specififc callbacks
v2: Modify to use pwm_config callback
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 5 +++
drivers/gpu/drm/i915/intel_dsi.c | 6 +++
drivers/gpu/drm/i915/intel_panel.c | 92 +++---
3 files changed, 98 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 897f17d..b4ebe3b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -182,7 +182,12 @@ struct intel_panel {
bool enabled;
bool combination_mode; /* gen 2/4 only */
bool active_low_pwm;
+
+ /* PWM chip */
+ struct pwm_device *pwm;
+
struct backlight_device *device;
+
} backlight;
void (*backlight_power)(struct intel_connector *, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index be55ffa..83c4540 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -402,6 +402,8 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
intel_dsi_port_enable(encoder);
}
+
+ intel_panel_enable_backlight(intel_dsi-attached_connector);
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -466,6 +468,8 @@ static void intel_dsi_pre_disable(struct intel_encoder
*encoder)
DRM_DEBUG_KMS(\n);
+ intel_panel_disable_backlight(intel_dsi-attached_connector);
+
if (is_vid_mode(intel_dsi)) {
/* Send Shutdown command to the panel in LP mode */
for_each_dsi_port(port, intel_dsi-ports)
@@ -1132,6 +1136,8 @@ void intel_dsi_init(struct drm_device *dev)
}
intel_panel_init(intel_connector-panel, fixed_mode, NULL);
+ intel_panel_setup_backlight(connector,
+ (intel_encoder-crtc_mask = (1 PIPE_A)) ? PIPE_A: PIPE_B);
return;
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 08532d4..5700f6f 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,8 +32,12 @@
#include linux/kernel.h
#include linux/moduleparam.h
+#include linux/pwm.h
#include intel_drv.h
+#define CRC_PMIC_PWM_PERIOD_NS 21333
+#define CRC_PMIC_PWM_STEPS 255
+
void
intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -536,6 +540,15 @@ static u32 vlv_get_backlight(struct intel_connector
*connector)
return _vlv_get_backlight(dev, pipe);
}
+static u32 vlv_get_mipi_backlight(struct intel_connector *connector)
+{
+ struct intel_panel *panel = connector-panel;
+ int duty_ns;
+
+ duty_ns = pwm_get_duty_cycle(panel-backlight.pwm);
+ return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS);
+}
+
static u32 intel_panel_get_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector-base.dev;
@@ -616,6 +629,14 @@ static void vlv_set_backlight(struct intel_connector
*connector, u32 level)
I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
}
+static void vlv_set_mipi_backlight(struct intel_connector *connector, u32
level)
+{
+ struct intel_panel *panel = connector-panel;
+ int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100);
+
+ pwm_config(panel-backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS);
+}
+
static void
intel_panel_actually_set_backlight(struct intel_connector *connector, u32
level)
{
@@ -741,6 +762,16 @@ static void vlv_disable_backlight(struct intel_connector
*connector)
I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp ~BLM_PWM_ENABLE);
}
+static void vlv_disable_mipi_backlight(struct intel_connector *connector)
+{
+ struct intel_panel *panel = connector-panel;
+
+ /* Disable the backlight */
+ pwm_config(panel-backlight.pwm, 0, CRC_PMIC_PWM_PERIOD_NS);
+ usleep_range(2000, 3000);
+ pwm_disable(panel-backlight.pwm);
+}
+
void intel_panel_disable_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector-base.dev;
@@ -947,6 +978,16 @@ static void vlv_enable_backlight(struct intel_connector
*connector)
I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
}
+static void vlv_enable_mipi_backlight(struct intel_connector *connector)
+{
+ struct intel_panel *panel = connector-panel;
+ int duty_ns = DIV_ROUND_UP(
+ panel-backlight.level * CRC_PMIC_PWM_PERIOD_NS, 100);
+
+ pwm_enable(panel-backlight.pwm);
+ pwm_config(panel-backlight.pwm, duty_ns,
Re: [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer
On Wed, Apr 29, 2015 at 01:28:19PM +, Daniel, Thomas wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of
Chris Wilson
Sent: Friday, March 6, 2015 9:44 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer
Userspace can pass in an offset that it presumes the object is located
at. The kernel will then do its utmost to fit the object into that
location. The assumption is that userspace is handling its own object
locations (for example along with full-ppgtt) and that the kernel will
rarely have to make space for the user's requests.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 5 +++
drivers/gpu/drm/i915/i915_gem.c| 53
++
drivers/gpu/drm/i915/i915_gem_evict.c | 52
+
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 -
include/uapi/drm/i915_drm.h| 3 +-
5 files changed, 106 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 9d0df4d85693..b266b31690e4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3592,22 +3592,43 @@ i915_gem_object_bind_to_vm(struct
drm_i915_gem_object *obj,
if (IS_ERR(vma))
goto err_unpin;
+ if (flags PIN_OFFSET_FIXED) {
+ uint64_t offset = flags PIN_OFFSET_MASK;
+ if (offset (alignment - 1)) {
+ vma = ERR_PTR(-EINVAL);
+ goto err_free_vma;
+ }
+ vma-node.start = offset;
+ vma-node.size = size;
+ vma-node.color = obj-cache_level;
+ ret = drm_mm_reserve_node(vm-mm, vma-node);
+ if (ret) {
+ ret = i915_gem_evict_range(dev, vm, start, end);
Did you mean i915_gem_evict_range(dev, vm, offset, offset+size) ?
Whoops. I guess i915_gem_evict_vma() would be a better interface.
+int
+i915_gem_evict_range(struct drm_device *dev, struct i915_address_space
*vm,
+unsigned long start, unsigned long end)
+{
+ struct drm_mm_node *node;
+ struct list_head eviction_list;
+ int ret = 0;
+
+ INIT_LIST_HEAD(eviction_list);
+ drm_mm_for_each_node(node, vm-mm) {
+ struct i915_vma *vma;
+
+ if (node-start + node-size = start)
+ continue;
+ if (node-start = end)
+ break;
+
+ vma = container_of(node, typeof(*vma), node);
+ if (vma-pin_count) {
+ ret = -EBUSY;
+ break;
+ }
+
+ if (WARN_ON(!list_empty(vma-exec_list))) {
So if an execbuffer uses both EXEC_OBJECT_PINNED and ordinary buffers in its
exec_list then the ordinary buffers cannot be relocated if they are in the
range of the pinned buffer. Was this your intention?
The desired behaviour should be to restart the reservation process with
bind the fixed objects first, then bind the rest.
The reservation logic is design around not moving objects, with the
expectation that we can reuse the layout from the last batch and
optimised for that. We should return ENOSPC here which causes the
reservation logic to unpin everything, evict and try again. It will be
easy enough to place the fixed objects at the head of the second pass.
I choose EINVAL initially thinking it should catch the condition of two
overlapping fixed objects without consider evicting ordinary bo (I was
caught thinking of userspace doing an all or nothing approach).
+ ret = -EINVAL;
+ break;
+ }
+
+ drm_gem_object_reference(vma-obj-base);
+ list_add(vma-exec_list, eviction_list);
I guess we need another list_head if we want to support both types of object
in the same execbuffer call and allow relocation.
Actually, here since we are walking the drm_mm rather than using the
scanner, we can switch over to list_for_each_entry_safe() and do the
unbinding inline.
Reduces to
int
i915_gem_evict_for_vma(struct i915_vma *target)
{
struct drm_mm_node *node, *next;
int ret;
list_for_each_entry_safe(node, next,
target-vm-mm.head_node.node_list,
node_list) {
struct i915_vma *vma;
if (node-start + node-size = target-node.start)
continue;
if (node-start = target-node.start + target-node.size)
break;
vma = container_of(node, typeof(*vma), node);
if (vma-exec_entry
vma-exec_entry-flags EXEC_OBJECT_PINNED)
/* Overlapping fixed
[Intel-gfx] [PATCH 4/8] drivers/mfd: Add PWM cell device for Crystalcove PMIC
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_crc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index 4cc1b32..8839e25 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -109,6 +109,9 @@ static struct mfd_cell crystal_cove_dev[] = {
{
.name = crystal_cove_pmic,
},
+ {
+ .name = crystal_cove_pwm,
+ },
};
static const struct regmap_config crystal_cove_regmap_config = {
--
2.1.0
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[Intel-gfx] [PATCH 6/8] drivers/pwm: Add Crystalcove (CRC) PWM driver
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
v2: Use the existing config callback with duty_ns and period_ns(Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/pwm/Kconfig | 7 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-crc.c | 171 ++
3 files changed, 179 insertions(+)
create mode 100644 drivers/pwm/pwm-crc.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index b1541f4..954da3e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -183,6 +183,13 @@ config PWM_LPC32XX
To compile this driver as a module, choose M here: the module
will be called pwm-lpc32xx.
+config PWM_CRC
+ bool Intel Crystalcove (CRC) PWM support
+ depends on X86 INTEL_SOC_PMIC
+ help
+ Generic PWM framework driver for Crystalcove (CRC) PMIC based PWM
+ control.
+
config PWM_LPSS
tristate Intel LPSS PWM support
depends on X86
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index ec50eb5..3d38fed 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o
obj-$(CONFIG_PWM_TWL) += pwm-twl.o
obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o
obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o
+obj-$(CONFIG_PWM_CRC) += pwm-crc.o
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
new file mode 100644
index 000..987f3b4
--- /dev/null
+++ b/drivers/pwm/pwm-crc.c
@@ -0,0 +1,171 @@
+/*
+ * pwm-crc.c - Intel Crystal Cove PWM Driver
+ *
+ * Copyright (C) 2015 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Author: Shobhit Kumar shobhit.ku...@intel.com
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/mfd/intel_soc_pmic.h
+#include linux/pwm.h
+
+#define PWM0_CLK_DIV 0x4B
+#define PWM_OUTPUT_ENABLE (17)
+#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
+#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
+#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
+
+#define PWM0_DUTY_CYCLE0x4E
+#define BACKLIGHT_EN 0x51
+
+#define PWM_MAX_LEVEL 0xFF
+
+#define PWM_BASE_CLK 6000/* 6 MHz */
+#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */
+
+/**
+ * struct crystalcove_pwm - Crystal Cove PWM controller
+ * @chip: the abstract pwm_chip structure.
+ * @regmap: the regmap from the parent device.
+ */
+struct crystalcove_pwm {
+ struct pwm_chip chip;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+};
+
+static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
+{
+ return container_of(pc, struct crystalcove_pwm, chip);
+}
+
+static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
+
+ regmap_write(crc_pwm-regmap, BACKLIGHT_EN, 1);
+
+ return 0;
+}
+
+static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
+
+ regmap_write(crc_pwm-regmap, BACKLIGHT_EN, 0);
+}
+
+static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
+ struct device *dev = crc_pwm-pdev-dev;
+ int level, percent;
+
+ if (period_ns PWM_MAX_PERIOD_NS) {
+ dev_err(dev, un-supported period_ns\n);
+ return -1;
+ }
+
+ if (pwm-period != period_ns) {
+ int clk_div;
+
+ /* changing the clk divisor, need to disable fisrt */
+ crc_pwm_disable(c, pwm);
+ clk_div = PWM_BASE_CLK * period_ns / 100;
+
+ regmap_write(crc_pwm-regmap, PWM0_CLK_DIV,
+ clk_div | PWM_OUTPUT_ENABLE);
+
+ /* enable back */
+ crc_pwm_enable(c, pwm);
+ }
+
+ if (duty_ns period_ns) {
+ dev_err(dev, duty cycle cannot be greater than cycle
period\n);
+ return -1;
+ }
+
+ /*
[Intel-gfx] [PATCH 0/8] Crystalcove (CRC) PMIC based panel and pwm control
Hi All, On some of the BYT devices, for DSI panels, the panel enable/disable signals and backlight control are done using the Crystalcove PMIC. This series provides support for the same and has been reviewed earlier on - http://lists.freedesktop.org/archives/intel-gfx/2015-March/061908.html This series addresses the review comments with two of the patches already merged in linux-next as - http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=e189ca56d91bbf1d3fe2f88ab6858bf919d42adf http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=c264f1110d27185f8531602f5fce400a6bbce946 Basically following are implemented - 1. GPIO control for panel enable/disable with GFX device as consumer 2. New PWM chip driver added for CRC PMIC based backlight control 3. i915 is modified to use the CRC gpio chip and the CRC PWM chip to do backlight control. This is now added in the generic panel backlight control infrastructure All these patches have been tested on AsusT100 and working fine using /sys/class/backlight/intel_backlight interface. Patches are also verified on android-x86 tree for AsusT100. Regards Shobhit Shobhit Kumar (8): drivers/gpio/gpiolib: Add support for removing registered consumer lookup table drivers/pwm/core: Add support to remove registered consumer lookup tables drivers/mfd: Add lookup table for Panel Control as GPIO signal drivers/mfd: Add PWM cell device for Crystalcove PMIC drivers/mfd: ADD PWM lookup table for CRC PMIC based PWM drivers/pwm: Add Crystalcove (CRC) PWM driver drm/i915: Use the CRC gpio for panel enable/disable drm/i915: Backlight control using CRC PMIC based PWM driver drivers/gpio/gpiolib.c | 13 +++ drivers/gpu/drm/i915/intel_drv.h | 5 ++ drivers/gpu/drm/i915/intel_dsi.c | 38 - drivers/gpu/drm/i915/intel_dsi.h | 6 ++ drivers/gpu/drm/i915/intel_panel.c | 92 ++-- drivers/mfd/intel_soc_pmic_core.c | 29 +++ drivers/mfd/intel_soc_pmic_crc.c | 3 + drivers/pwm/Kconfig| 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/core.c | 17 drivers/pwm/pwm-crc.c | 171 + include/linux/gpio/machine.h | 1 + include/linux/pwm.h| 5 ++ 13 files changed, 381 insertions(+), 7 deletions(-) create mode 100644 drivers/pwm/pwm-crc.c -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drivers/mfd: Add lookup table for Panel Control as GPIO signal
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the lookup table during driver remove (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_core.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_core.c
b/drivers/mfd/intel_soc_pmic_core.c
index 7b50b6b..f3d918e 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -24,8 +24,19 @@
#include linux/acpi.h
#include linux/regmap.h
#include linux/mfd/intel_soc_pmic.h
+#include linux/gpio/machine.h
#include intel_soc_pmic_core.h
+/* Lookup table for the Panel Enable/Disable line as GPIO signals */
+static struct gpiod_lookup_table panel_gpio_table = {
+ /* Intel GFX is consumer */
+ .dev_id = :00:02.0,
+ .table = {
+ /* Panel EN/DISABLE */
+ GPIO_LOOKUP(gpio_crystalcove, 94, panel, GPIO_ACTIVE_HIGH),
+ },
+};
+
static int intel_soc_pmic_find_gpio_irq(struct device *dev)
{
struct gpio_desc *desc;
@@ -85,6 +96,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
if (ret)
dev_warn(dev, Can't enable IRQ as wake source: %d\n, ret);
+ /* Add lookup table binding for Panel Control to the GPIO Chip */
+ gpiod_add_lookup_table(panel_gpio_table);
+
ret = mfd_add_devices(dev, -1, config-cell_dev,
config-n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic-irq_chip_data));
@@ -104,6 +118,9 @@ static int intel_soc_pmic_i2c_remove(struct i2c_client *i2c)
regmap_del_irq_chip(pmic-irq, pmic-irq_chip_data);
+ /* Remove lookup table for Panel Control from the GPIO Chip */
+ gpiod_remove_lookup_table(panel_gpio_table);
+
mfd_remove_devices(i2c-dev);
return 0;
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drivers/gpio/gpiolib: Add support for removing registered consumer lookup table
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing maintainers
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Reviewed-by: Alexandre Courbot acour...@nvidia.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpio/gpiolib.c | 13 +
include/linux/gpio/machine.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 59eaa23..2420af9 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1658,6 +1658,19 @@ void gpiod_add_lookup_table(struct gpiod_lookup_table
*table)
mutex_unlock(gpio_lookup_lock);
}
+/**
+ * gpiod_remove_lookup_table() - unregister GPIO device consumers
+ * @table: table of consumers to unregister
+ */
+void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
+{
+ mutex_lock(gpio_lookup_lock);
+
+ list_del(table-list);
+
+ mutex_unlock(gpio_lookup_lock);
+}
+
static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
unsigned int idx,
enum gpio_lookup_flags *flags)
diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h
index e270614..c0d712d 100644
--- a/include/linux/gpio/machine.h
+++ b/include/linux/gpio/machine.h
@@ -57,5 +57,6 @@ struct gpiod_lookup_table {
}
void gpiod_add_lookup_table(struct gpiod_lookup_table *table);
+void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
#endif /* __LINUX_GPIO_MACHINE_H */
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drivers/mfd: ADD PWM lookup table for CRC PMIC based PWM
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
v2: Remove the lookup table on driver unload (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_core.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_core.c
b/drivers/mfd/intel_soc_pmic_core.c
index f3d918e..a00ddd9 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -25,6 +25,7 @@
#include linux/regmap.h
#include linux/mfd/intel_soc_pmic.h
#include linux/gpio/machine.h
+#include linux/pwm.h
#include intel_soc_pmic_core.h
/* Lookup table for the Panel Enable/Disable line as GPIO signals */
@@ -37,6 +38,11 @@ static struct gpiod_lookup_table panel_gpio_table = {
},
};
+/* PWM consumed by the Intel GFX */
+static struct pwm_lookup crc_pwm_lookup[] = {
+ PWM_LOOKUP(crystal_cove_pwm, 0, :00:02.0, pwm_backlight, 0,
PWM_POLARITY_NORMAL),
+};
+
static int intel_soc_pmic_find_gpio_irq(struct device *dev)
{
struct gpio_desc *desc;
@@ -99,6 +105,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
/* Add lookup table binding for Panel Control to the GPIO Chip */
gpiod_add_lookup_table(panel_gpio_table);
+ /* Add lookup table for crc-pwm */
+ pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
+
ret = mfd_add_devices(dev, -1, config-cell_dev,
config-n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic-irq_chip_data));
@@ -121,6 +130,9 @@ static int intel_soc_pmic_i2c_remove(struct i2c_client *i2c)
/* Remove lookup table for Panel Control from the GPIO Chip */
gpiod_remove_lookup_table(panel_gpio_table);
+ /* remove crc-pwm lookup table */
+ pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
+
mfd_remove_devices(i2c-dev);
return 0;
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drivers/pwm/core: Add support to remove registered consumer lookup tables
In case some drivers are unloading, they can remove lookup tables which
they would have registered during their load time to avoid redundant
entries if loaded again
v2: Ccing maintainers
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/pwm/core.c | 17 +
include/linux/pwm.h | 5 +
2 files changed, 22 insertions(+)
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index ba34c7d..d2fe7c8d 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -586,6 +586,23 @@ void pwm_add_table(struct pwm_lookup *table, size_t num)
}
/**
+ * pwm_remove_table() - un-register PWM device consumers
+ * @table: array of consumers to un-register
+ * @num: number of consumers in table
+ */
+void pwm_remove_table(struct pwm_lookup *table, size_t num)
+{
+ mutex_lock(pwm_lookup_lock);
+
+ while (num--) {
+ list_del(table-list);
+ table++;
+ }
+
+ mutex_unlock(pwm_lookup_lock);
+}
+
+/**
* pwm_get() - look up and request a PWM device
* @dev: device for PWM consumer
* @con_id: consumer name
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index e90628c..cfe2d8d 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -290,10 +290,15 @@ struct pwm_lookup {
#if IS_ENABLED(CONFIG_PWM)
void pwm_add_table(struct pwm_lookup *table, size_t num);
+void pwm_remove_table(struct pwm_lookup *table, size_t num);
#else
static inline void pwm_add_table(struct pwm_lookup *table, size_t num)
{
}
+
+static inline void pwm_remove_table(struct pwm_lookup *table, size_t num)
+{
+}
#endif
#ifdef CONFIG_PWM_SYSFS
--
2.1.0
___
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Re: [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chris Wilson
Sent: Friday, March 6, 2015 9:44 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer
Userspace can pass in an offset that it presumes the object is located
at. The kernel will then do its utmost to fit the object into that
location. The assumption is that userspace is handling its own object
locations (for example along with full-ppgtt) and that the kernel will
rarely have to make space for the user's requests.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 5 +++
drivers/gpu/drm/i915/i915_gem.c| 53
++
drivers/gpu/drm/i915/i915_gem_evict.c | 52
+
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 -
include/uapi/drm/i915_drm.h| 3 +-
5 files changed, 106 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 9d0df4d85693..b266b31690e4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3592,22 +3592,43 @@ i915_gem_object_bind_to_vm(struct
drm_i915_gem_object *obj,
if (IS_ERR(vma))
goto err_unpin;
+ if (flags PIN_OFFSET_FIXED) {
+ uint64_t offset = flags PIN_OFFSET_MASK;
+ if (offset (alignment - 1)) {
+ vma = ERR_PTR(-EINVAL);
+ goto err_free_vma;
+ }
+ vma-node.start = offset;
+ vma-node.size = size;
+ vma-node.color = obj-cache_level;
+ ret = drm_mm_reserve_node(vm-mm, vma-node);
+ if (ret) {
+ ret = i915_gem_evict_range(dev, vm, start, end);
Did you mean i915_gem_evict_range(dev, vm, offset, offset+size) ?
+ if (ret == 0)
+ ret = drm_mm_reserve_node(vm-mm,
vma-node);
+ }
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err_free_vma;
+ }
+ } else {
search_free:
- ret = drm_mm_insert_node_in_range_generic(vm-mm, vma-node,
- size, alignment,
- obj-cache_level,
- start, end,
-
DRM_MM_SEARCH_DEFAULT,
-
DRM_MM_CREATE_DEFAULT);
- if (ret) {
- ret = i915_gem_evict_something(dev, vm, size, alignment,
-obj-cache_level,
-start, end,
-flags);
- if (ret == 0)
- goto search_free;
+ ret = drm_mm_insert_node_in_range_generic(vm-mm,
vma-node,
+ size, alignment,
+ obj-cache_level,
+ start, end,
+
DRM_MM_SEARCH_DEFAULT,
+
DRM_MM_CREATE_DEFAULT);
+ if (ret) {
+ ret = i915_gem_evict_something(dev, vm, size,
alignment,
+obj-cache_level,
+start, end,
+flags);
+ if (ret == 0)
+ goto search_free;
- goto err_free_vma;
+ goto err_free_vma;
+ }
}
if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj-cache_level))) {
ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index e3a49d94da3a..c4b2ead0d805 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -195,6 +195,58 @@ found:
return ret;
}
+int
+i915_gem_evict_range(struct drm_device *dev, struct i915_address_space
*vm,
+ unsigned long start, unsigned long end)
+{
+ struct drm_mm_node *node;
+ struct list_head eviction_list;
+ int ret = 0;
+
+ INIT_LIST_HEAD(eviction_list);
+ drm_mm_for_each_node(node, vm-mm) {
+ struct i915_vma *vma;
+
+ if (node-start + node-size = start)
+ continue;
+ if (node-start = end)
+ break;
+
+ vma = container_of(node, typeof(*vma), node);
+ if (vma-pin_count) {
+ ret = -EBUSY;
+ break;
+ }
+
+ if (WARN_ON(!list_empty(vma-exec_list))) {
So if an execbuffer uses both EXEC_OBJECT_PINNED and ordinary buffers in its
Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable existing gen9 harware workarounds for Broxton
On ti, 2015-04-07 at 11:45 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 53
+++--
3 files changed, 41 insertions(+), 22 deletions(-)
The patch needs to be rebased on the latest -nightly and your
[PATCH 0/3] drm/i915/bxt: add workarounds patchset. It'd be best to
resend it as part of that patchset.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e1a0fd9..91eef06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5339,6 +5339,7 @@ enum skl_disp_power_wells {
#define GEN8_L3SQCREG4 0xb118
#define GEN8_LQSC_RO_PERF_DIS (127)
+#define GEN8_PIPELINE_FLUSH_COHERENT_LINES (121)
/* GEN8 chicken */
#define HDC_CHICKEN0 0x7300
@@ -7324,4 +7325,11 @@ enum skl_disp_power_wells {
#define _PALETTE_A (dev_priv-info.display_mmio_offset + 0xa000)
#define _PALETTE_B (dev_priv-info.display_mmio_offset + 0xa800)
+/*
+ * Chicken Registers for LLC/eLLC Hot Spotting Avoidance Mode for
+ * 3D/Media Compressed Resources
+ */
+#define GEN9_CHICKEN_MISC1_REG 0x42080
+#define GEN9_CHICKEN_MISC1_NEW_HASH_ENABLE (115)
Please move this next to CHICKEN_PAR1_1 and use the standard two space
indent before the flag name. Also no need for the comment, it doesn't
fully describe the register and we don't have similar comments for other
registers either.
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c3c473d..bbb5d64 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -96,6 +96,8 @@ static void skl_init_clock_gating(struct drm_device *dev)
static void bxt_init_clock_gating(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
gen9_init_clock_gating(dev);
/* WaVSRefCountFullforceMissDisable:bxt */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 44c7b99..741bdfa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -916,7 +916,7 @@ static int gen9_init_workarounds(struct intel_engine_cs
*ring)
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- /* WaDisablePartialInstShootdown:skl */
+ /* WaDisablePartialInstShootdown:skl,bxt */
It would be better to split out all the parts that only update the WA
comments into one separate patch.
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
@@ -924,45 +924,43 @@ static int gen9_init_workarounds(struct intel_engine_cs
*ring)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- if (INTEL_REVID(dev) == SKL_REVID_A0 ||
- INTEL_REVID(dev) == SKL_REVID_B0) {
- /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
+ if (
+ (IS_SKYLAKE(dev) (INTEL_REVID(dev) == SKL_REVID_A0 ||
+ INTEL_REVID(dev) == SKL_REVID_B0)) ||
+ (IS_BROXTON(dev) INTEL_REVID(dev) == BXT_REVID_A0)
+ ) {
To align with the coding style please remove the whitespace after the
opening '(' and before the closing ')'.
I assume we should use the GT/Display device stepping, not the SOC
stepping. Accordingly the above check should be ' BXT_REVID_B0', since
steppings 0,1,2 all map to A0 GT/Display device stepping.
Please split out the enabling for each workaround into a separate patch.
+ /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
}
- if (IS_SKYLAKE(dev) INTEL_REVID(dev) = SKL_REVID_B0) {
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
+ if (
+ (IS_SKYLAKE(dev) INTEL_REVID(dev) = SKL_REVID_B0) ||
+ (IS_BROXTON(dev) INTEL_REVID(dev) == BXT_REVID_A0)
As above ' BXT_REVID_B0'
+) {
+ /*
WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
DISABLE_PIXEL_MASK_CAMMING);
}
- if (INTEL_REVID(dev) = SKL_REVID_C0) {
- /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
+ if (
+ (IS_SKYLAKE(dev) INTEL_REVID(dev) = SKL_REVID_C0) ||
+ (IS_BROXTON(dev))
+) {
+ /*
Re: [Intel-gfx] [PATCH] drm/i915: Add missing MacBook Pro models with dual channel LVDS
On Sun, 12 Apr 2015, Lukas Wunner lu...@wunner.de wrote:
Single channel LVDS maxes out at 112 MHz. All 17 models with i915
graphics had a resolution of 1920x1200 (193 MHz), necessitating dual
channel LVDS. The 15 pre-retina models had either 1440x900 (106 MHz)
or 1680x1050 (119 MHz), both versions used dual channel LVDS even
though the smaller one would have fit into a single channel.
Signed-off-by: Lukas Wunner lu...@wunner.de
Tested-by: Lukas Wunner lu...@wunner.de
Acked-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_lvds.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 071b96d..417ccab 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -812,12 +812,28 @@ static int intel_dual_link_lvds_callback(const struct
dmi_system_id *id)
static const struct dmi_system_id intel_dual_link_lvds[] = {
{
.callback = intel_dual_link_lvds_callback,
- .ident = Apple MacBook Pro (Core i5/i7 Series),
+ .ident = Apple MacBook Pro 15\ (2010),
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, Apple Inc.),
+ DMI_MATCH(DMI_PRODUCT_NAME, MacBookPro6,2),
+ },
+ },
+ {
+ .callback = intel_dual_link_lvds_callback,
+ .ident = Apple MacBook Pro 15\ (2011),
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, Apple Inc.),
DMI_MATCH(DMI_PRODUCT_NAME, MacBookPro8,2),
},
},
+ {
+ .callback = intel_dual_link_lvds_callback,
+ .ident = Apple MacBook Pro 15\ (2012),
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, Apple Inc.),
+ DMI_MATCH(DMI_PRODUCT_NAME, MacBookPro9,1),
+ },
+ },
{ } /* terminating entry */
};
@@ -847,6 +863,11 @@ static bool compute_is_dual_link_lvds(struct
intel_lvds_encoder *lvds_encoder)
if (i915.lvds_channel_mode 0)
return i915.lvds_channel_mode == 2;
+ /* single channel LVDS is limited to 112 kHz */
+ if (lvds_encoder-attached_connector-base.panel.fixed_mode-clock
+ 112999)
+ return true;
+
if (dmi_check_system(intel_dual_link_lvds))
return true;
@@ -1104,6 +1125,8 @@ void intel_lvds_init(struct drm_device *dev)
out:
mutex_unlock(dev-mode_config.mutex);
+ intel_panel_init(intel_connector-panel, fixed_mode, downclock_mode);
+
lvds_encoder-is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
DRM_DEBUG_KMS(detected %s-link lvds configuration\n,
lvds_encoder-is_dual_link ? dual : single);
@@ -1118,7 +1141,6 @@ out:
}
drm_connector_register(connector);
- intel_panel_init(intel_connector-panel, fixed_mode, downclock_mode);
intel_panel_setup_backlight(connector, INVALID_PIPE);
return;
--
1.8.5.2 (Apple Git-48)
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--
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Re: [Intel-gfx] [PATCH 07/16] drm/i915: Inline check required for object syncing prior to execbuf
On Wed, Apr 29, 2015 at 03:03:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 04/27/2015 01:41 PM, Chris Wilson wrote:
This trims a little overhead from the common case of not needing to
synchronize between rings.
v2: execlists is special and likes to duplicate code.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++---
drivers/gpu/drm/i915/intel_lrc.c | 9 ++---
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 45d74da7f6c4..4fe09568089b 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -889,6 +889,7 @@ static int
i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
struct list_head *vmas)
{
+const unsigned other_rings = ~intel_ring_flag(ring);
struct i915_vma *vma;
uint32_t flush_domains = 0;
bool flush_chipset = false;
@@ -896,9 +897,12 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
-ret = i915_gem_object_sync(obj, ring);
-if (ret)
-return ret;
+
+if (obj-active other_rings) {
+ret = i915_gem_object_sync(obj, ring);
+if (ret)
+return ret;
+}
Just to avoid bailing out near the top of i915_gem_object_sync?
Yes. Every function where we spend more time in the push/pop preamble
than in the body is a function I don't want to call :)
-Chris
--
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Re: [Intel-gfx] [PATCH libdrm] intel: Leak the userptr test bo
On Fri, Apr 17, 2015 at 12:22:00PM +0100, Chris Wilson wrote: On Fri, Apr 17, 2015 at 11:57:28AM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin tvrtko.ursu...@intel.com In order to use userptr, the kernel tracks the owner's mm with a mmu_notifier. Setting that is very expensive - it involves taking all mm_locks and a stop_machine(). This tracking lives only for as long as the client is using userptr objects - so if the client allocates then frees a userptr in a loop, we will be executing that heavyweight setup everytime. To ammoritize this cost, just leak the test bo and the single backing page we use for detecting userptr. v2: Free the object and memory when bufmgr is destroyed. Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com Cc: Chris Wilson ch...@chris-wilson.co.uk Reveiwed-by: Chris Wilson ch...@chris-wilson.co.uk s/vei/vie/ and merged. Thanks for the patch and review (could it be time to ask for push access?) -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i195/bxt: Add A1 stepping for Broxton
On pe, 2015-03-20 at 09:29 +, Nick Hoath wrote:
This stepping isn't listed separately in the specs, so needs confirmation.
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eec271a..68fb41a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
#define SKL_REVID_E0 (0x4)
#define BXT_REVID_A0 (0x0)
+#define BXT_REVID_A1 (0x1)
The above mapping is for the SOC RevID, but I think for all our purposes
(WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
mapping to A0.
#define BXT_REVID_B0 (0x3)
#define BXT_REVID_C0 (0x6)
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Re: [Intel-gfx] [PATCH 01/16] drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level
On 04/27/2015 01:41 PM, Chris Wilson wrote:
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj-pin_display. So we can safely replace i915_gem_object_is_pinned()
here with a plain obj-pin_display check. During rebinding, we will check
sanity checks in case vma-pin_count is erroneously set.
At the same time, we can micro-optimise GTT mmap() behaviour since we
only need to relinquish the mmaps before Sandybridge.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f0a6d03e9ba5..afdb604e4005 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3768,31 +3768,34 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
{
struct drm_device *dev = obj-base.dev;
struct i915_vma *vma, *next;
+ bool bound = false;
int ret;
if (obj-cache_level == cache_level)
return 0;
- if (i915_gem_obj_is_pinned(obj)) {
+ if (obj-pin_display) {
DRM_DEBUG(can not change the cache level of pinned objects\n);
return -EBUSY;
}
list_for_each_entry_safe(vma, next, obj-vma_list, vma_link) {
+ if (!drm_mm_node_allocated(vma-node))
+ continue;
+
Another micro-optimisation?
Side note - this was puzzling and then I realized
i915_gem_valid_gtt_space says true when node is not allocated. It seems
to be only concerned by node colouring - so is that one badly name
function or I am missing something?
if (!i915_gem_valid_gtt_space(vma, cache_level)) {
ret = i915_vma_unbind(vma);
if (ret)
return ret;
- }
+ } else
+ bound = true;
}
- if (i915_gem_obj_bound_any(obj)) {
+ if (bound) {
ret = i915_gem_object_finish_gpu(obj);
if (ret)
return ret;
- i915_gem_object_finish_gtt(obj);
-
/* Before SandyBridge, you could not use tiling or fence
* registers with snooped memory, so relinquish any fences
* currently pointing to our region in the aperture.
@@ -3801,15 +3804,21 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
ret = i915_gem_object_put_fence(obj);
if (ret)
return ret;
+
+ i915_gem_release_mmap(obj);
}
If only gen6 we need to drop the mmap, what happens with the domain
tracking - who removes the GTT bit from there now?
- list_for_each_entry(vma, obj-vma_list, vma_link)
- if (drm_mm_node_allocated(vma-node)) {
- ret = i915_vma_bind(vma, cache_level,
- PIN_UPDATE);
- if (ret)
- return ret;
- }
+ list_for_each_entry(vma, obj-vma_list, vma_link) {
+ if (!drm_mm_node_allocated(vma-node))
+ continue;
+
+ if (vma-pin_count)
+ return -EBUSY;
Preserve DRM_DEBUG as it was before?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6282 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB -1 264/264 263/264 BYT -4 227/227 223/227 BDW -1 318/318 317/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *IVB igt@gem_storedw_batches_loop@normal PASS(2) FAIL(1)PASS(1) *BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(6) TIMEOUT(1)PASS(1) *BYT igt@gem_exec_parse@bitmasks FAIL(1)PASS(4) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(4)PASS(3) TIMEOUT(2) *BYT igt@gem_tiled_pread FAIL(1)PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x *BDW igt@gem_userptr_blits@forked-sync-swapping-multifd-mempressure-normal PASS(2) NO_RESULT(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
So far I can't reproduce this problem on my BSW. In fact what I see
that the voltage at RPn is lower than the voltage at RPe, even while
we're in rc6.
without forcewake:
RPn - 0x66
RPe - 0x67
RP0 - 0x69
with forcewake:
RPn - 0x66
RPe - 0x76
RP0 - 0x9d
Also asking Punit to change the frequency after the GPU has gone to
rc6 does absolutely nothing (remind anyone of VLV?). I think I need to
retest my VLV C0 to see if my earlier observations there were accurate.
The shared Vnn rail does make it harder to observe this stuff on
VLV though.
So based on my tests this patch feels a bit wrong.
Since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
v2: Change commit message
v3: set min_freq before idle_freq (chris)
v4: Squash 'Remove unused rps min function' patch
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a7516ed..78c89ff 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4715,24 +4715,6 @@ static int cherryview_rps_guar_freq(struct
drm_i915_private *dev_priv)
return rp1;
}
-static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = dev_priv-dev;
- u32 val, rpn;
-
- if (dev-pdev-revision = 0x20) {
- val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
- rpn = ((val FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT)
-FB_GFX_FREQ_FUSE_MASK);
- } else { /* For pre-production hardware */
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = ((val PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT)
-PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
- }
-
- return rpn;
-}
-
static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp1;
@@ -4984,7 +4966,8 @@ static void cherryview_init_gt_powersave(struct
drm_device *dev)
intel_gpu_freq(dev_priv, dev_priv-rps.rp1_freq),
dev_priv-rps.rp1_freq);
- dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ /* PUnit validated range is only [RPe, RP0] */
+ dev_priv-rps.min_freq = dev_priv-rps.efficient_freq;
DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
intel_gpu_freq(dev_priv, dev_priv-rps.min_freq),
dev_priv-rps.min_freq);
--
1.9.1
--
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Re: [Intel-gfx] [Beignet] Haswell issues
Andi, Thanks for your comments and that makes sense for me, just check kernel version is not an ideal method for those unofficial kernels with back porting patches. Then we have the following open questions in my mind: How do we check whether the i915 KMD support secure batch buffer execution if the batch buffer pass the cmd parser check under full-ppgtt mode in UMD? How do we check whether the i915 KMD support secure batch buffer execution with aliasing ppgtt after the merging of the patch drm/i915: Arm cmd parser with aliasing ppgtt only in UMD? CC to Daniel, do you have any suggestion here? Thanks, Zhigang Gong. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Andi Kleen Sent: Thursday, April 30, 2015 12:19 PM To: beig...@lists.freedesktop.org Cc: zhigang.g...@linux.intel.com Subject: Re: [Beignet] Haswell issues Zhigang Gong zhigang.g...@linux.intel.com writes: but I don't have the hardware to try it. We will do some testing on this. And once we get the exact version, I will submit a new patch to give some warn if the user is using an unsupported kernel. As now we have better solution than patch kernel manually, I will change the document to suggest user to upgrade to a supported kernel rather than patch kernel manually. It would be better to add something to the kernel interface that can be probed without relying on the kernel version. The problem with checking versions is that it'll break if someone backports the fixes to older kernels, which is not uncommon. -Andi -- a...@linux.intel.com -- Speaking for myself only ___ Beignet mailing list beig...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Preallocate request before access of the ring
From: Alex Dai yu@intel.com This is to avoid bad IO access caused by writing NOOP to wrap the ring buffer whilst ring is unpinned. Signed-off-by: Alex Dai yu@intel.com --- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 732fd63..3e8fcfd 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -803,12 +803,12 @@ static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, if (ret) return ret; - ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); + /* Preallocate the olr before touching the ring */ + ret = i915_gem_request_alloc(ring, ctx); if (ret) return ret; - /* Preallocate the olr before touching the ring */ - ret = i915_gem_request_alloc(ring, ctx); + ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); if (ret) return ret; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/16] drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level
On Wed, Apr 29, 2015 at 03:50:13PM +0100, Tvrtko Ursulin wrote:
On 04/27/2015 01:41 PM, Chris Wilson wrote:
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj-pin_display. So we can safely replace i915_gem_object_is_pinned()
here with a plain obj-pin_display check. During rebinding, we will check
sanity checks in case vma-pin_count is erroneously set.
At the same time, we can micro-optimise GTT mmap() behaviour since we
only need to relinquish the mmaps before Sandybridge.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index f0a6d03e9ba5..afdb604e4005 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3768,31 +3768,34 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
{
struct drm_device *dev = obj-base.dev;
struct i915_vma *vma, *next;
+bool bound = false;
int ret;
if (obj-cache_level == cache_level)
return 0;
-if (i915_gem_obj_is_pinned(obj)) {
+if (obj-pin_display) {
DRM_DEBUG(can not change the cache level of pinned objects\n);
return -EBUSY;
}
list_for_each_entry_safe(vma, next, obj-vma_list, vma_link) {
+if (!drm_mm_node_allocated(vma-node))
+continue;
+
Another micro-optimisation?
Side note - this was puzzling and then I realized
i915_gem_valid_gtt_space says true when node is not allocated. It
seems to be only concerned by node colouring - so is that one badly
name function or I am missing something?
It's only concerned with colouring, yes. I felt like moving the two
checks together but it also acts as a sanity check in i915_vma_insert.
So it's not a micro-optimisation as such, except that I had two
conflicting uses and this was the easiest path to take.
if (!i915_gem_valid_gtt_space(vma, cache_level)) {
ret = i915_vma_unbind(vma);
if (ret)
return ret;
-}
+} else
+bound = true;
}
-if (i915_gem_obj_bound_any(obj)) {
+if (bound) {
ret = i915_gem_object_finish_gpu(obj);
if (ret)
return ret;
-i915_gem_object_finish_gtt(obj);
-
/* Before SandyBridge, you could not use tiling or fence
* registers with snooped memory, so relinquish any fences
* currently pointing to our region in the aperture.
@@ -3801,15 +3804,21 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
ret = i915_gem_object_put_fence(obj);
if (ret)
return ret;
+
+i915_gem_release_mmap(obj);
}
If only gen6 we need to drop the mmap, what happens with the
domain tracking - who removes the GTT bit from there now?
We don't care. The GTT domain bits remains valid. Access through the GTT
will remain consistent as we change the caching bits - except that on
snooped architectures access may suddenly become verboten and in those
cases we should throwaway the mmap and force the client to fault them
back in (so we can do the sanity checks in i915_gem_fault() and throw
SIGBUS to protect ourself).
To be pendantic we should split this into:
if (gen 6)
i915_gem_put_fence();
if (!HAS_LLC cache_level != I915_CACHE_NONE)
i915_gem_release_mmap(obj);
-list_for_each_entry(vma, obj-vma_list, vma_link)
-if (drm_mm_node_allocated(vma-node)) {
-ret = i915_vma_bind(vma, cache_level,
-PIN_UPDATE);
-if (ret)
-return ret;
-}
+list_for_each_entry(vma, obj-vma_list, vma_link) {
+if (!drm_mm_node_allocated(vma-node))
+continue;
+
+if (vma-pin_count)
+return -EBUSY;
Preserve DRM_DEBUG as it was before?
Oh, that can actually die. of be if (WARN_ON()) since the preposition is
that I have already checked for the only vma that can be legally pinned
at this point.
Bah, this entire patch is bogus - because of how set_cache_level is used
by pin_to_display(). Whoops. time to thow it out and start again.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 3/8] drivers/mfd: Add lookup table for Panel Control as GPIO signal
By the way, your subject lines are messed up.
They should adhere to the conventions laid down by the Maintainers.
`git log --oneline -- drivers/subsystem`
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the lookup table during driver remove (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_core.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_core.c
b/drivers/mfd/intel_soc_pmic_core.c
index 7b50b6b..f3d918e 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -24,8 +24,19 @@
#include linux/acpi.h
#include linux/regmap.h
#include linux/mfd/intel_soc_pmic.h
+#include linux/gpio/machine.h
#include intel_soc_pmic_core.h
+/* Lookup table for the Panel Enable/Disable line as GPIO signals */
+static struct gpiod_lookup_table panel_gpio_table = {
+ /* Intel GFX is consumer */
+ .dev_id = :00:02.0,
+ .table = {
+ /* Panel EN/DISABLE */
+ GPIO_LOOKUP(gpio_crystalcove, 94, panel, GPIO_ACTIVE_HIGH),
+ },
+};
+
static int intel_soc_pmic_find_gpio_irq(struct device *dev)
{
struct gpio_desc *desc;
@@ -85,6 +96,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
if (ret)
dev_warn(dev, Can't enable IRQ as wake source: %d\n, ret);
+ /* Add lookup table binding for Panel Control to the GPIO Chip */
+ gpiod_add_lookup_table(panel_gpio_table);
+
ret = mfd_add_devices(dev, -1, config-cell_dev,
config-n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic-irq_chip_data));
@@ -104,6 +118,9 @@ static int intel_soc_pmic_i2c_remove(struct i2c_client
*i2c)
regmap_del_irq_chip(pmic-irq, pmic-irq_chip_data);
+ /* Remove lookup table for Panel Control from the GPIO Chip */
+ gpiod_remove_lookup_table(panel_gpio_table);
+
mfd_remove_devices(i2c-dev);
return 0;
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [Intel-gfx] [PATCH 5/8] drivers/mfd: ADD PWM lookup table for CRC PMIC based PWM
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
v2: Remove the lookup table on driver unload (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_core.c | 12
1 file changed, 12 insertions(+)
How do you expect this set to be managed?
Acked-by: Lee Jones lee.jo...@linaro.org
diff --git a/drivers/mfd/intel_soc_pmic_core.c
b/drivers/mfd/intel_soc_pmic_core.c
index f3d918e..a00ddd9 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -25,6 +25,7 @@
#include linux/regmap.h
#include linux/mfd/intel_soc_pmic.h
#include linux/gpio/machine.h
+#include linux/pwm.h
#include intel_soc_pmic_core.h
/* Lookup table for the Panel Enable/Disable line as GPIO signals */
@@ -37,6 +38,11 @@ static struct gpiod_lookup_table panel_gpio_table = {
},
};
+/* PWM consumed by the Intel GFX */
+static struct pwm_lookup crc_pwm_lookup[] = {
+ PWM_LOOKUP(crystal_cove_pwm, 0, :00:02.0, pwm_backlight, 0,
PWM_POLARITY_NORMAL),
+};
+
static int intel_soc_pmic_find_gpio_irq(struct device *dev)
{
struct gpio_desc *desc;
@@ -99,6 +105,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
/* Add lookup table binding for Panel Control to the GPIO Chip */
gpiod_add_lookup_table(panel_gpio_table);
+ /* Add lookup table for crc-pwm */
+ pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
+
ret = mfd_add_devices(dev, -1, config-cell_dev,
config-n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic-irq_chip_data));
@@ -121,6 +130,9 @@ static int intel_soc_pmic_i2c_remove(struct i2c_client
*i2c)
/* Remove lookup table for Panel Control from the GPIO Chip */
gpiod_remove_lookup_table(panel_gpio_table);
+ /* remove crc-pwm lookup table */
+ pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
+
mfd_remove_devices(i2c-dev);
return 0;
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [Intel-gfx] [PATCH 4/8] drivers/mfd: Add PWM cell device for Crystalcove PMIC
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_crc.c | 3 +++
1 file changed, 3 insertions(+)
For my own reference:
Acked-by: Lee Jones lee.jo...@linaro.org
diff --git a/drivers/mfd/intel_soc_pmic_crc.c
b/drivers/mfd/intel_soc_pmic_crc.c
index 4cc1b32..8839e25 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -109,6 +109,9 @@ static struct mfd_cell crystal_cove_dev[] = {
{
.name = crystal_cove_pmic,
},
+ {
+ .name = crystal_cove_pwm,
+ },
};
static const struct regmap_config crystal_cove_regmap_config = {
--
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Re: [Intel-gfx] [PATCH 3/8] drivers/mfd: Add lookup table for Panel Control as GPIO signal
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the lookup table during driver remove (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_core.c | 17 +
1 file changed, 17 insertions(+)
I have no idea what this stuff is, but it looks plausible.
For my own reference:
Acked-by: Lee Jones lee.jo...@linaro.org
diff --git a/drivers/mfd/intel_soc_pmic_core.c
b/drivers/mfd/intel_soc_pmic_core.c
index 7b50b6b..f3d918e 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -24,8 +24,19 @@
#include linux/acpi.h
#include linux/regmap.h
#include linux/mfd/intel_soc_pmic.h
+#include linux/gpio/machine.h
#include intel_soc_pmic_core.h
+/* Lookup table for the Panel Enable/Disable line as GPIO signals */
+static struct gpiod_lookup_table panel_gpio_table = {
+ /* Intel GFX is consumer */
+ .dev_id = :00:02.0,
+ .table = {
+ /* Panel EN/DISABLE */
+ GPIO_LOOKUP(gpio_crystalcove, 94, panel, GPIO_ACTIVE_HIGH),
+ },
+};
+
static int intel_soc_pmic_find_gpio_irq(struct device *dev)
{
struct gpio_desc *desc;
@@ -85,6 +96,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
if (ret)
dev_warn(dev, Can't enable IRQ as wake source: %d\n, ret);
+ /* Add lookup table binding for Panel Control to the GPIO Chip */
+ gpiod_add_lookup_table(panel_gpio_table);
+
ret = mfd_add_devices(dev, -1, config-cell_dev,
config-n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic-irq_chip_data));
@@ -104,6 +118,9 @@ static int intel_soc_pmic_i2c_remove(struct i2c_client
*i2c)
regmap_del_irq_chip(pmic-irq, pmic-irq_chip_data);
+ /* Remove lookup table for Panel Control from the GPIO Chip */
+ gpiod_remove_lookup_table(panel_gpio_table);
+
mfd_remove_devices(i2c-dev);
return 0;
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [Intel-gfx] [PATCH 02/16] drm/i915: Only remove objects pinned to the display from the available aperture
On 04/27/2015 01:41 PM, Chris Wilson wrote: With the removal of the pin_ioctl, we need only consider obj-pin_display when looking at available aperture space. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index afdb604e4005..ec9e36e9ec78 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -157,7 +157,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, pinned = 0; mutex_lock(dev-struct_mutex); list_for_each_entry(obj, dev_priv-mm.bound_list, global_list) - if (i915_gem_obj_is_pinned(obj)) + if (obj-pin_display) pinned += i915_gem_obj_ggtt_size(obj); mutex_unlock(dev-struct_mutex); The only thing I can think of are transients from execbuf, pre-ppgtt, but I suppose we don't care about that a lot? Or I misunderstand how something works? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Remove unnecessary null check in execlists_context_unqueue
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6268 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 264/264 264/264 BYT -3 227/227 224/227 BDW 318/318 318/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(3) TIMEOUT(1)PASS(1) BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(2)PASS(2) TIMEOUT(2) *BYT igt@gem_threaded_access_tiled FAIL(1)PASS(2) DMESG_WARN(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
