Re: [Intel-gfx] drm/atomic: Reject events for inactive crtc's.

[Maarten Lankhorst]

Op 27-08-15 om 17:22 schreef Daniel Vetter:
> On Thu, Aug 27, 2015 at 03:36:09PM +0100, Daniel Stone wrote:
>> Hi,
>>
>> On 6 August 2015 at 13:49, Daniel Vetter  wrote:
>>> On Thu, Aug 06, 2015 at 01:19:35PM +0200, Maarten Lankhorst wrote:
 Op 06-08-15 om 11:47 schreef Daniel Stone:
> On 30 July 2015 at 08:03, Maarten Lankhorst
>  wrote:
>> +   if (!state->active && state->event) {
>> +   DRM_DEBUG_ATOMIC("[CRTC:%d] requesting event and not 
>> active\n",
>> +crtc->base.id);
>> +   return -EINVAL;
>> +   }
> Hmm, even if disabling? Maybe (!crtc->state->active && !state->active)
> && state->event.
 How do you want to send a vblank event after disabling?
>>> The event would be when we stop scanning out, but yeah that's a bit a
>>> tricky one. I guess for now (until we have someone who needs this) we
>>> could just merge Maarten's patch as the easier thing to do right now?
>>> Maybe with a small code comment that this is intentional?
>> Exactly that. Surely this (when the CRTC actually goes dark) is
>> something we already know? Assuming you don't have atomic_disable /
>> instant-scanout-stop, and have to wait until the next vblank to kill
>> it, then how does this work?
>>   - create FB
>>   - assign FB to plane on CRTC
>>   - unreference FB such that plane holds the last remaining reference
>>   - set plane->fb == NULL + crtc->active = 0, i.e. SetCrtc(NULL, 0, 0,
>> 0, 0, ...)
>>
>> You can't immediately unpin/destroy the FB since you might still be
>> mid-scanout. So you already need to defer this, and that would be the
>> point at which you stop scanout. In a lot of hardware, this is just
>> another latched register which takes effect on the next vblank, for
>> which you still catch an IRQ - at which point you send the event. If
>> you actually have atomic_disable hardware that stops scanout
>> immediately, you can just send the event immediately.
>>
>> What am I missing?
> The userspace which actually wants this and the testcases which makes sure
> it works. Until we have that I'd really prefer to just close that
> undefined behaviour gap in the atomic api, similar to how we just merged a
> patch to disallow switching live planes.
>
> We can always extend this later on easily, there's lots of little features
> like this that people suggested for atomic.
> -Daniel
Or in this case it's really solved in the kernel. Old fb's don't get unpinned 
until the update, so why should userspace care about any of it, assuming kernel 
refcount is correct?

~Maarten
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[Intel-gfx] [PATCH] i915: Set ddi_pll_sel in DP MST path

[Ander Conselvan de Oliveira]

The DP MST encoder config function never sets ddi_pll_sel, even though
its value is programmed in its ->pre_enable() hook. That used to work
because a new pipe_config was kzalloc'ed at every modeset, and the value
of zero selects the highest clock for the PLL. Starting with the commit
below, the value of ddi_pll_sel is preserved through modesets, and since
the correct value wasn't properly setup by the MST code, it could lead
to warnings and blank screens.

commit 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93
Author: Ander Conselvan de Oliveira 
Date:   Fri May 15 11:51:50 2015 +0300

drm/i915: Preserve ddi_pll_sel when allocating new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628
Cc: sta...@vger.kernel.org
Cc: Timo Aaltonen 
Cc: Luciano Coelho 
Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_dp.c | 2 +-
 drivers/gpu/drm/i915/intel_dp_mst.c | 5 +
 drivers/gpu/drm/i915/intel_drv.h| 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9e90a2b..393aed0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1190,7 +1190,7 @@ skl_edp_set_pll_config(struct intel_crtc_state 
*pipe_config)
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
 }
 
-static void
+void
 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
 {
memset(&pipe_config->dpll_hw_state, 0,
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index ebf2054..677d70e 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -33,6 +33,7 @@
 static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
 {
+   struct drm_device *dev = encoder->base.dev;
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
@@ -88,6 +89,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
   &pipe_config->dp_m_n);
 
pipe_config->dp_m_n.tu = slots;
+
+   if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+   hsw_dp_set_ddi_pll_sel(pipe_config);
+
return true;
 
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c61ba47..458f56c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1209,6 +1209,7 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp);
 void intel_edp_drrs_invalidate(struct drm_device *dev,
unsigned frontbuffer_bits);
 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
+void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int 
conn_id);
-- 
2.4.3

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[Intel-gfx] [PATCH] drm/i915/bxt: Fix irq_port for eDP

[Sonika Jindal]

From: Durgadoss R 

Currently, HDMI hotplug with eDP as local panel is failing
because the HDMI hpd is detected as a long hpd for eDP; and is
thus rightfully ignored. But, it should really be handled as
an interrupt on port B for HDMI (due to BXT A1 platform having
HPD pins A and B swapped). This patch sets the irq_port[PORT_A]
to NULL in case eDP is on port A so that irq handler does not
treat it as a 'dig_port' interrupt.

v2 (Sonika): Moving the setting of irq_port for BXT WA outside so that this
can be set for both hdmi or dp ports. For HDMI this is required
because we get interrupts for portB on the hpd line of portA for
BXT A0/A1.
This issue occurred because hpd on edp was not disabled
which was done as part of "drm/i915: Dont enable hpd for eDP" from
the series:
http://lists.freedesktop.org/archives/intel-gfx/2015-August/073266.html

This patch can be squashed to :
commit cf1d58833f07afbb4534b15caa3fd48baa313b2c
Author: Sonika Jindal 
Date:   Mon Aug 10 10:35:36 2015 +0530

drm/i915/bxt: WA for swapped HPD pins in A stepping

Signed-off-by: Durgadoss R 
Signed-off-by: Sonika Jindal 
---
 drivers/gpu/drm/i915/intel_ddi.c |   21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 56d778f..bba0cb6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3242,15 +3242,7 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
goto err;
 
intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
-   /*
-* On BXT A0/A1, sw needs to activate DDIA HPD logic and
-* interrupts to check the external panel connection.
-*/
-   if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
-&& port == PORT_B)
-   dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
-   else
-   dev_priv->hotplug.irq_port[port] = intel_dig_port;
+   dev_priv->hotplug.irq_port[port] = intel_dig_port;
}
 
/* In theory we don't need the encoder->type check, but leave it just in
@@ -3259,6 +3251,17 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
if (!intel_ddi_init_hdmi_connector(intel_dig_port))
goto err;
}
+   /*
+* On BXT A0/A1, sw needs to activate DDIA HPD logic and
+* interrupts to check the external panel connection.
+*/
+   if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
+   if (port == PORT_B) {
+   dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
+   intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
+   } else if (intel_encoder->type == INTEL_OUTPUT_EDP)
+   dev_priv->hotplug.irq_port[port] = NULL;
+   }
 
return;
 
-- 
1.7.10.4

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Re: [Intel-gfx] [PATCH] drm/atomic: Make sure lock is held in trylock contexts.

[shuang . he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 7273
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
ILK  302/302  302/302
SNB  315/315  315/315
IVB  336/336  336/336
BYT -2  283/283  281/283
HSW  378/378  378/378
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*BYT  igt@gem_partial_pwrite_pread@reads-uncached  PASS(1)  FAIL(1)
*BYT  igt@gem_tiled_partial_pwrite_pread@reads  PASS(1)  FAIL(1)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH] intel-gpu-tools: Fixes-compiler-warnings-about-wrong-function-type

[Stefan Dirsch]

On Wed, Aug 26, 2015 at 11:42:23AM +0100, Thomas Wood wrote:
> On 24 August 2015 at 10:59, Stefan Dirsch  wrote:
> > Hi
> >
> > Find a simple buildfix against current intel-gpu-tools git sources attached.
> 
> I assume the compiler warning is about uninitialised values and unused
> variables? It looks like the Makefile is not using the debug cflags so
> these warning do not appear by default.

Warnings/error were:

W: intel-gpu-tools uninitialized-variable intel_renderstate_gen9.c:476
E: intel-gpu-tools no-return-in-nonvoid-function intel_renderstate_gen8.c:441

> intel_null_state_gen.c appears to assume the
> gen*_setup_null_render_state functions have return values in the
> extern declarations, so this could do with fixing too.

Indeed your patches fixes these warnings/errors. So no need any longer to
include/review my patch as long as your patch gets integrated. ;-)

Thanks,
Stefan

Public Key available
--
Stefan Dirsch (Res. & Dev.)   SUSE LINUX GmbH
Tel: 0911-740 53 0Maxfeldstraße 5
FAX: 0911-740 53 479  D-90409 Nürnberg
http://www.suse.deGermany 
---
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham
Norton, HRB 21284 (AG Nürnberg)
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[Intel-gfx] [PATCH] drm/atomic: Fix bookkeeping with TEST_ONLY, v3.

[Maarten Lankhorst]

Commit ec9f932ed41622d120de52a5b525e4d77b9ef17e
"drm/atomic: Cleanup on error properly in the atomic ioctl."
cleaned up some error paths, but didn't fix the TEST_ONLY path.
In the check only case plane->fb shouldn't be updated, and
the vblank events should be cleared as on failure.

Changes since v1:
- Fix -EDEADLK handling of vblank events too.
- Free state last with CHECK_ONLY.
Changes since v2:
- Add comment about freeing crtc_state->event with TEST_ONLY.
  (Daniel Stone)

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Daniel Stone 
---
 drivers/gpu/drm/drm_atomic.c | 39 +++
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index e515261d0a7f..940f80bbf192 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1540,7 +1540,8 @@ retry:
copied_props++;
}
 
-   if (obj->type == DRM_MODE_OBJECT_PLANE && count_props) {
+   if (obj->type == DRM_MODE_OBJECT_PLANE && count_props &&
+   !(arg->flags & DRM_MODE_ATOMIC_TEST_ONLY)) {
plane = obj_to_plane(obj);
plane_mask |= (1 << drm_plane_index(plane));
plane->old_fb = plane->fb;
@@ -1562,10 +1563,11 @@ retry:
}
 
if (arg->flags & DRM_MODE_ATOMIC_TEST_ONLY) {
+   /*
+* Unlike commit, check_only does not clean up state.
+* Below we call drm_atomic_state_free for it.
+*/
ret = drm_atomic_check_only(state);
-   /* _check_only() does not free state, unlike _commit() */
-   if (!ret)
-   drm_atomic_state_free(state);
} else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
ret = drm_atomic_async_commit(state);
} else {
@@ -1592,25 +1594,30 @@ out:
plane->old_fb = NULL;
}
 
+   if (ret && arg->flags & DRM_MODE_PAGE_FLIP_EVENT) {
+   /*
+* TEST_ONLY and PAGE_FLIP_EVENT are mutually exclusive,
+* if they weren't, this code should be called on success
+* for TEST_ONLY too.
+*/
+
+   for_each_crtc_in_state(state, crtc, crtc_state, i) {
+   if (!crtc_state->event)
+   continue;
+
+   destroy_vblank_event(dev, file_priv,
+crtc_state->event);
+   }
+   }
+
if (ret == -EDEADLK) {
drm_atomic_state_clear(state);
drm_modeset_backoff(&ctx);
goto retry;
}
 
-   if (ret) {
-   if (arg->flags & DRM_MODE_PAGE_FLIP_EVENT) {
-   for_each_crtc_in_state(state, crtc, crtc_state, i) {
-   if (!crtc_state->event)
-   continue;
-
-   destroy_vblank_event(dev, file_priv,
-crtc_state->event);
-   }
-   }
-
+   if (ret || arg->flags & DRM_MODE_ATOMIC_TEST_ONLY)
drm_atomic_state_free(state);
-   }
 
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
-- 
2.1.0

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Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add some CHV DPIO lane power state asserts

[Deepak]

On 08/27/2015 04:32 PM, Ville Syrjälä wrote:

On Thu, Aug 27, 2015 at 10:06:09AM +0530, Deepak wrote:


On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä 

Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides.

The hardware only provides two bits per channel indicating whether all
or some of the lanes are powered down, so we can't do an exact check.

Additionally, CL2 powering down before we can check it adds another
twist. To work around this we simply check for the 0 value of the
CL2 register (which is what we get when it's powered down) and
adjust our expectations.

Signed-off-by: Ville Syrjälä 
---
   drivers/gpu/drm/i915/i915_reg.h |  8 +
   drivers/gpu/drm/i915/intel_runtime_pm.c | 54 
+
   2 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 395f556..586a0f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1089,6 +1089,12 @@ enum skl_disp_power_wells {
   #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE  1 /* 1: coarse & 0 : 
fine  */
   #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
   
+#define _CHV_CMN_DW0_CH0   0x8100

+#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0   19
+#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0   18
+#define   DPIO_ALLDL_POWERDOWN (1 << 1)
+#define   DPIO_ANYDL_POWERDOWN (1 << 0)
+
   #define _CHV_CMN_DW5_CH0   0x8114
   #define   CHV_BUFRIGHTENA1_DISABLE   (0 << 20)
   #define   CHV_BUFRIGHTENA1_NORMAL(1 << 20)
@@ -1125,6 +1131,8 @@ enum skl_disp_power_wells {
   
   #define _CHV_CMN_DW19_CH0		0x814c

   #define _CHV_CMN_DW6_CH1 0x8098
+#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1   30 /* CL2 DW6 only */
+#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1   29 /* CL2 DW6 only */
   #define   DPIO_DYNPWRDOWNEN_CH1  (1 << 28) /* CL2 DW6 only */
   #define   CHV_CMN_USEDCLKCHANNEL (1 << 13)
   
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c

index 002b78f..a1d9676 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1026,6 +1026,58 @@ static void chv_dpio_cmn_power_well_disable(struct 
drm_i915_private *dev_priv,
  phy, dev_priv->chv_phy_control);
   }
   
+static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,

+enum dpio_channel ch, bool override, 
unsigned int mask)
+{
+   enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;

Why not PIPE B? I think PIPE B can also be used to drive using PHY0?

Here we only pass 'pipe' to vlv_dpio_read() and it will just use
'DPIO_PHY(pipe)' to turn it back into an enum dpio_phy :) Since pipe A
and B are hooked up the same phy we don't need pipe B here.

I've been meaning to change vlv_dpio_read/write() to take enum dpio_phy
instead of enum pipe to get rid of this kind of sillyness, but haven't
gotten around to it yet. There may also be a few other functions that
could use the same treatment.


Thanks for the clarification
Reviewed-by: Deepak S 

+   u32 reg, val, expected, actual;
+
+   if (ch == DPIO_CH0)
+   reg = _CHV_CMN_DW0_CH0;
+   else
+   reg = _CHV_CMN_DW6_CH1;
+
+   mutex_lock(&dev_priv->sb_lock);
+   val = vlv_dpio_read(dev_priv, pipe, reg);
+   mutex_unlock(&dev_priv->sb_lock);
+
+   /*
+* This assumes !override is only used when the port is disabled.
+* All lanes should power down even without the override when
+* the port is disabled.
+*/
+   if (!override || mask == 0xf) {
+   expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+   /*
+* If CH1 common lane is not active anymore
+* (eg. for pipe B DPLL) the entire channel will
+* shut down, which causes the common lane registers
+* to read as 0. That means we can't actually check
+* the lane power down status bits, but as the entire
+* register reads as 0 it's a good indication that the
+* channel is indeed entirely powered down.
+*/
+   if (ch == DPIO_CH1 && val == 0)
+   expected = 0;
+   } else if (mask != 0x0) {
+   expected = DPIO_ANYDL_POWERDOWN;
+   } else {
+   expected = 0;
+   }
+
+   if (ch == DPIO_CH0)
+   actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
+   else
+   actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
+   actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+
+   WARN(actual != expected,
+"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any 
%d. (0x%

[Intel-gfx] [PATCH 1/2] drm/i915: Remove start frame argument to pipe_update_begin/end.

[Maarten Lankhorst]

There's already a per crtc member that can be used for it.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c |  9 -
 drivers/gpu/drm/i915/intel_drv.h |  5 ++---
 drivers/gpu/drm/i915/intel_sprite.c  | 15 ---
 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b5dc2fab98d1..86586642b5f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11098,11 +11098,10 @@ static void ilk_do_mmio_flip(struct intel_crtc 
*intel_crtc)
 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
struct drm_device *dev = intel_crtc->base.dev;
-   u32 start_vbl_count;
 
intel_mark_page_flip_active(intel_crtc);
 
-   intel_pipe_update_start(intel_crtc, &start_vbl_count);
+   intel_pipe_update_start(intel_crtc);
 
if (INTEL_INFO(dev)->gen >= 9)
skl_do_mmio_flip(intel_crtc);
@@ -0,7 +11109,7 @@ static void intel_do_mmio_flip(struct intel_crtc 
*intel_crtc)
/* use_mmio_flip() retricts MMIO flips to ilk+ */
ilk_do_mmio_flip(intel_crtc);
 
-   intel_pipe_update_end(intel_crtc, start_vbl_count);
+   intel_pipe_update_end(intel_crtc);
 }
 
 static void intel_mmio_flip_work_func(struct work_struct *work)
@@ -13441,7 +13440,7 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
 
/* Perform vblank evasion around commit operation */
if (crtc->state->active)
-   intel_pipe_update_start(intel_crtc, 
&intel_crtc->start_vbl_count);
+   intel_pipe_update_start(intel_crtc);
 
if (modeset)
return;
@@ -13458,7 +13457,7 @@ static void intel_finish_crtc_commit(struct drm_crtc 
*crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
if (crtc->state->active)
-   intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
+   intel_pipe_update_end(intel_crtc);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2e02bed0d3c1..172c10ac92ae 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1414,9 +1414,8 @@ struct drm_plane *intel_plane_init(struct drm_device 
*dev, enum pipe pipe,
   int plane, enum drm_plane_type plane_type);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  struct drm_file *file_priv);
-void intel_pipe_update_start(struct intel_crtc *crtc,
-uint32_t *start_vbl_count);
-void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+void intel_pipe_update_start(struct intel_crtc *crtc);
+void intel_pipe_update_end(struct intel_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 596fa4319681..63fba42be2cf 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -76,7 +76,7 @@ static int usecs_to_scanlines(const struct drm_display_mode 
*mode, int usecs)
  * avoid random delays. The value written to @start_vbl_count should be
  * supplied to intel_pipe_update_end() for error checking.
  */
-void intel_pipe_update_start(struct intel_crtc *crtc, uint32_t 
*start_vbl_count)
+void intel_pipe_update_start(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
@@ -95,7 +95,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc, 
uint32_t *start_vbl_count)
max = vblank_start - 1;
 
local_irq_disable();
-   *start_vbl_count = 0;
+   crtc->start_vbl_count = 0;
 
if (min <= 0 || max <= 0)
return;
@@ -134,9 +134,10 @@ void intel_pipe_update_start(struct intel_crtc *crtc, 
uint32_t *start_vbl_count)
 
drm_crtc_vblank_put(&crtc->base);
 
-   *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
+   crtc->start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 
-   trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
+   trace_i915_pipe_update_vblank_evaded(crtc, min, max,
+crtc->start_vbl_count);
 }
 
 /**
@@ -148,7 +149,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc, 
uint32_t *start_vbl_count)
  * re-enables interrupts and verifies the update was actually completed
  * before a vblank using the value of @start_vbl_count.
  */
-void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
+void intel_pipe_update_end(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
enum pipe pipe = crtc->pipe;
@@ -158,9 +159,9 @@ void intel_pipe_update_end(struct intel_crtc *crtc, u32 
start_vb

[Intel-gfx] [PATCH 2/2] drm/i915: Also record time difference if vblank evasion fails.

[Maarten Lankhorst]

This makes the error message slightly more useful.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_drv.h| 2 ++
 drivers/gpu/drm/i915/intel_sprite.c | 6 --
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 172c10ac92ae..513981751e92 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -565,6 +565,8 @@ struct intel_crtc {
int scanline_offset;
 
unsigned start_vbl_count;
+   ktime_t start_vbl_time;
+
struct intel_crtc_atomic_commit atomic;
 
/* scalers available on this crtc */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 63fba42be2cf..cc0eb3915f1c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -134,6 +134,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
 
drm_crtc_vblank_put(&crtc->base);
 
+   crtc->start_vbl_time = ktime_get();
crtc->start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 
trace_i915_pipe_update_vblank_evaded(crtc, min, max,
@@ -160,8 +161,9 @@ void intel_pipe_update_end(struct intel_crtc *crtc)
local_irq_enable();
 
if (crtc->start_vbl_count && crtc->start_vbl_count != end_vbl_count)
-   DRM_ERROR("Atomic update failure on pipe %c (start=%u 
end=%u)\n",
- pipe_name(pipe), crtc->start_vbl_count, 
end_vbl_count);
+   DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) 
time %lld us\n",
+ pipe_name(pipe), crtc->start_vbl_count, end_vbl_count,
+ ktime_us_delta(ktime_get(), crtc->start_vbl_time));
 }
 
 static void
-- 
2.1.0

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Re: [Intel-gfx] [PATCH] i915: Set ddi_pll_sel in DP MST path

[Ville Syrjälä]

On Mon, Aug 31, 2015 at 11:23:28AM +0300, Ander Conselvan de Oliveira wrote:
> The DP MST encoder config function never sets ddi_pll_sel, even though
> its value is programmed in its ->pre_enable() hook. That used to work
> because a new pipe_config was kzalloc'ed at every modeset, and the value
> of zero selects the highest clock for the PLL. Starting with the commit
> below, the value of ddi_pll_sel is preserved through modesets, and since
> the correct value wasn't properly setup by the MST code, it could lead
> to warnings and blank screens.

The ddi pll handling is still quite a mess. Every platform does things
just a bit different to the next guy.

But yeah, looks like HSW/BDW handle the PLL selection for DP from
the encoder .compute_config() so MST should do the same since it
(re)computes the main link config for each stream. And SKL and BXT
handle DP via the .crtc_compute_clock() path, so nothing needed for
them I suppose.

Reviewed-by: Ville Syrjälä 

> 
> commit 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93
> Author: Ander Conselvan de Oliveira 
> Date:   Fri May 15 11:51:50 2015 +0300
> 
> drm/i915: Preserve ddi_pll_sel when allocating new pipe_config
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628
> Cc: sta...@vger.kernel.org
> Cc: Timo Aaltonen 
> Cc: Luciano Coelho 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 2 +-
>  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +
>  drivers/gpu/drm/i915/intel_drv.h| 1 +
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9e90a2b..393aed0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1190,7 +1190,7 @@ skl_edp_set_pll_config(struct intel_crtc_state 
> *pipe_config)
>   pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>  }
>  
> -static void
> +void
>  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
>  {
>   memset(&pipe_config->dpll_hw_state, 0,
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index ebf2054..677d70e 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -33,6 +33,7 @@
>  static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>   struct intel_crtc_state *pipe_config)
>  {
> + struct drm_device *dev = encoder->base.dev;
>   struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
>   struct intel_digital_port *intel_dig_port = intel_mst->primary;
>   struct intel_dp *intel_dp = &intel_dig_port->dp;
> @@ -88,6 +89,10 @@ static bool intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
>  &pipe_config->dp_m_n);
>  
>   pipe_config->dp_m_n.tu = slots;
> +
> + if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + hsw_dp_set_ddi_pll_sel(pipe_config);
> +
>   return true;
>  
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index c61ba47..458f56c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1209,6 +1209,7 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp);
>  void intel_edp_drrs_invalidate(struct drm_device *dev,
>   unsigned frontbuffer_bits);
>  void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
> +void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
>  
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int 
> conn_id);
> -- 
> 2.4.3
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Enabling RC6 immediately during init/resume

[Salonie, Namrta]

Hi Chris, Daniel.

Thanks for your inputs.
I agree that we need to amend the patch. Will do following changes.
1.	RPM ref count is not needed with immediate enabling of RC6, I will 
remove that.

2.  I will extend this to other GEN as well.

This was one of the set of optimization we implemented for BYT Android. 
All of these
gave improvement of ~5mW for 30minutes for Active Idle WLAN KPI. And 
about ~5mW for other airplane, wifi, radio suspend scenarios.


The other optimizations included :-
1.	Reduction of autosuspend delay to 500ms from 10ms (On BYT, display D3 
should happen in suspend as Punit initiates S0iX flow only considering 
Display D3). Because of this reduction Display D3 will happen 
immediately: This can be controlled by user mode in android. However 
shall we bring this value for Linux as well?


2.	Deferring RC6 disabling from early_resume callback to resume callback 
to reduce the delay for which the wells had to stay ON – We verified the 
HDMI case and it worked without issues.
3.	During resume, perform modeset based on the DPMS state, so that 
Display remains Off for the intermediate wake ups where no DPMS ON/OFF 
happens.


Also, can we port the optimizations 2 & 3 to the upstream kernel?

Thanks,
Namrta

On 8/25/2015 8:02 PM, Daniel Vetter wrote:

On Fri, Aug 21, 2015 at 01:41:26PM +0100, Chris Wilson wrote:

On Sat, Aug 22, 2015 at 02:19:48AM +0530, Namrta Salonie wrote:

Since RC6 enabling does not involve PCU communication overhead,
it can be enabled immediately during the resume time.
This will help save additional power & meet power requirements
for active Idle KPI where power is evaluated over
number of transitions of suspend/resume.

Signed-off-by: Namrta Salonie 
Signed-off-by: Sagar Arun Kamble 


You can pull out gen9 rc6 as well, and apply a similar transformation to
gen6-8. So instead of putting the if-chain in
intel_enable_gt_powersave(), add intel_enable_rc6() and start placing
the ready functions there.

Reviewing the comments we only need the rpm lock until after rc6
enabling and as you keep that wakelock, you are not getting the full
improvement you seek. If you keep refactoring the remaining two rc6
functions, you can then drop the wakelock.


Since this seems to not have much of a benefit due to the missing removal
of the wakelock I wonder how this was tested ... Next patch should have
(relative, we're not allowed to publish absolute) performance data
attached, e.g. "Over 100 suspend/resume cycles with 5s of idle time in
between each suspend/resume time this reduce in a reduction of $number
$unit."

Without this this patch is just unjustified tuning and I won't take it.
-Daniel


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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Also record time difference if vblank evasion fails.

[Ville Syrjälä]

On Mon, Aug 31, 2015 at 01:04:26PM +0200, Maarten Lankhorst wrote:
> This makes the error message slightly more useful.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
>  drivers/gpu/drm/i915/intel_sprite.c | 6 --
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 172c10ac92ae..513981751e92 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -565,6 +565,8 @@ struct intel_crtc {
>   int scanline_offset;
>  
>   unsigned start_vbl_count;
> + ktime_t start_vbl_time;
> +
>   struct intel_crtc_atomic_commit atomic;
>  
>   /* scalers available on this crtc */
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 63fba42be2cf..cc0eb3915f1c 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -134,6 +134,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>  
>   drm_crtc_vblank_put(&crtc->base);
>  
> + crtc->start_vbl_time = ktime_get();
>   crtc->start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
>  
>   trace_i915_pipe_update_vblank_evaded(crtc, min, max,
> @@ -160,8 +161,9 @@ void intel_pipe_update_end(struct intel_crtc *crtc)
>   local_irq_enable();
>  
>   if (crtc->start_vbl_count && crtc->start_vbl_count != end_vbl_count)
> - DRM_ERROR("Atomic update failure on pipe %c (start=%u 
> end=%u)\n",
> -   pipe_name(pipe), crtc->start_vbl_count, 
> end_vbl_count);
> + DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) 
> time %lld us\n",
> +   pipe_name(pipe), crtc->start_vbl_count, end_vbl_count,
> +   ktime_us_delta(ktime_get(), crtc->start_vbl_time));

Should really do the ktime_get() before local_irq_enable().

With that fixed this series is
Reviewed-by: Ville Syrjälä 

>  }
>  
>  static void
> -- 
> 2.1.0
> 
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Re: [Intel-gfx] [PATCH v4 2/5] drm: Add private data field to trace control block

[Patrik Jakobsson]

On Wed, Aug 26, 2015 at 03:26:08PM +0200, Patrik Jakobsson wrote:
> On Tue, Aug 25, 2015 at 11:12 PM, Mike Frysinger  wrote:
> > On 24 Aug 2015 14:42, Patrik Jakobsson wrote:
> >> We need to be able to store private data in the tcb across it's
> >> lifetime. To ensure proper destruction of the data a free_priv_data
> >> callback must be provided if an allocation is stored in priv_data. The
> >> callback is executed automatically when the life of the tcb ends.
> >>
> >> * defs.h: Add extern declaration of free_tcb_priv_data.
> >>  (struct tcb): Add priv_data and free_priv_data.
> >> * strace.c (free_tcb_priv_data): New function
> >> (drop_tcb): Execute free_tcb_priv_data callback
> >> * syscall.c (trace_syscall_exiting): Execute free_tcb_priv_data callback
> >>
> >> Signed-off-by: Patrik Jakobsson 
> >> ---
> >>  defs.h|  6 ++
> >>  strace.c  | 14 ++
> >>  syscall.c |  1 +
> >>  3 files changed, 21 insertions(+)
> >>
> >> diff --git a/defs.h b/defs.h
> >> index 9059026..bc3bd83 100644
> >> --- a/defs.h
> >> +++ b/defs.h
> >> @@ -266,6 +266,10 @@ struct tcb {
> >>   int u_error;/* Error code */
> >>   long scno;  /* System call number */
> >>   long u_arg[MAX_ARGS];   /* System call arguments */
> >> +
> >> + void *priv_data;/* Private data for syscall decoding 
> >> functions */
> >> + void (*free_priv_data)(void *); /* Callback for freeing priv_data */
> >
> > should we name these _priv_data and _free_priv_data and provides accessor
> > functions ?  i worry that code paths might stomp on each other by accident
> > and we don't end up noticing.
> >
> > static void set_tcb_priv_data(struct tcb *tcp, void *data, void 
> > (*free_data)(void *))
> > {
> > assert(tcp->_priv_data == NULL && tcp->_free_priv_data == NULL);
> > ...
> > }
> > -mike
> 
> Yes, that's a good idea. My use case is pretty simple but usage can easliy 
> grow.
> 
> I'll resend this patch and take it out of the drm/i915 series.
> 
> -Patrik

Here's my take on it (I assume it needs some discussion):

int
set_tcb_priv_data(struct tcb *tcp, void *priv_data)
{
/* A free callback is required before setting private data and private
 * data must be set back to NULL before being set again.
 */
if (tcp->_free_priv_data == NULL ||
(tcp->_priv_data && priv_data != NULL))
return -1;

tcp->_priv_data = priv_data;
return 0;
}

void *
get_tcb_priv_data(struct tcb *tcp)
{
return tcp->_priv_data;
}

int
set_tcb_free_priv_data(struct tcb *tcp, void (*free_priv_data)(void *))
{
/* _free_priv_data must be set back to NULL before being set again. */
if (tcp->_free_priv_data && free_priv_data != NULL)
return -1;

tcp->_free_priv_data = free_priv_data;
return 0;
}

void
free_tcb_priv_data(struct tcb *tcp)
{
if (tcp->_priv_data) {
if (tcp->_free_priv_data) {
tcp->_free_priv_data(tcp->_priv_data);
tcp->_free_priv_data = NULL;
}
tcp->_priv_data = NULL;
}
}

Cheers
Patrik
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Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: guest i915 notification for Intel GVT-g

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> When i915 drivers run inside a VM with Intel GVT-g, some explicit
> notifications are needed from guest to host device model through PV
> INFO page write. The notifications include:
> 
>   PPGTT create
>   PPGTT destroy
> 
> They are used for the shadow implementation of PPGTT. Intel GVT-g
> needs to write-protect the guest pages of PPGTT, and clear the write
> protection when they end their life cycle.
> 
> v2:
> - Use lower_32_bits()/upper_32_bits() for qword operations;
> - Remove the notification of guest context creation/destroy;
> 
> Signed-off-by: Zhiyuan Lv 
> Signed-off-by: Zhi Wang 
> 

Again, as there's really no formal spec of what the hypervisor expects
to see, that part is hard to comment on, so apart from that:

Reviewed-by: Joonas Lahtinen 

PS. Adding people who previously commented on the patch as CC, makes
the reviewing go much smoother (new revisions get picked up faster).

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 41
> +
>  1 file changed, 41 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 56cc8e8..df60227 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -899,6 +899,41 @@ static int gen8_init_scratch(struct
> i915_address_space *vm)
>   return 0;
>  }
>  
> +static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool
> create)
> +{
> + enum vgt_g2v_type msg;
> + struct drm_device *dev = ppgtt->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int offset = vgtif_reg(pdp0_lo);
> + int i;
> +
> + if (USES_FULL_48BIT_PPGTT(dev)) {
> + u64 daddr = px_dma(&ppgtt->pml4);
> +
> + I915_WRITE(offset, lower_32_bits(daddr));
> + I915_WRITE(offset + 4, upper_32_bits(daddr));
> +
> + msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
> + VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY)
> ;
> + } else {
> + for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
> + u64 daddr = i915_page_dir_dma_addr(ppgtt,
> i);
> +
> + I915_WRITE(offset, lower_32_bits(daddr));
> + I915_WRITE(offset + 4,
> upper_32_bits(daddr));
> +
> + offset += 8;
> + }
> +
> + msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
> + VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY)
> ;
> + }
> +
> + I915_WRITE(vgtif_reg(g2v_notify), msg);
> +
> + return 0;
> +}
> +
>  static void gen8_free_scratch(struct i915_address_space *vm)
>  {
>   struct drm_device *dev = vm->dev;
> @@ -945,6 +980,9 @@ static void gen8_ppgtt_cleanup(struct
> i915_address_space *vm)
>   struct i915_hw_ppgtt *ppgtt =
>   container_of(vm, struct i915_hw_ppgtt, base);
>  
> + if (intel_vgpu_active(vm->dev))
> + gen8_ppgtt_notify_vgt(ppgtt, false);
> +
>   if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
>   gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt
> ->pdp);
>   else
> @@ -1519,6 +1557,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt
> *ppgtt)
>   }
>   }
>  
> + if (intel_vgpu_active(ppgtt->base.dev))
> + gen8_ppgtt_notify_vgt(ppgtt, true);
> +
>   return 0;
>  
>  free_scratch:
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Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Always enable execlists on BDW for vgpu

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> Broadwell hardware supports both ring buffer mode and execlist mode.
> When i915 runs inside a VM with Intel GVT-g, we allow execlist mode
> only.
> 
> The main reason of EXECLIST only is that GVT-g does not support the
> dynamic mode switch between ring buffer mode and execlist mode when
> running multiple virtual machines.
> 
> v2:
> - Adjust the position of vgpu check in sanitize function (Joonas)
> - Add vgpu error check in context initialization. (Joonas, Daniel)
> 
> Signed-off-by: Zhiyuan Lv 
> Signed-off-by: Zhi Wang 

Reviewed-by: Joonas Lahtinen 

> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 7 +++
>  drivers/gpu/drm/i915/intel_lrc.c| 6 ++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 8e893b3..74aa0c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -332,6 +332,13 @@ int i915_gem_context_init(struct drm_device
> *dev)
>   if (WARN_ON(dev_priv->ring[RCS].default_context))
>   return 0;
>  
> + if (intel_vgpu_active(dev) &&
> HAS_LOGICAL_RING_CONTEXTS(dev)) {
> + if (!i915.enable_execlists) {
> + DRM_INFO("Only EXECLIST mode is supported in
> vgpu.\n");
> + return -EINVAL;
> + }
> + }
> +
>   if (i915.enable_execlists) {
>   /* NB: intentionally left blank. We will allocate
> our own
>* backing objects as we need them, thank you very
> much */
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 258af9b..e9520af 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -236,6 +236,12 @@ int intel_sanitize_enable_execlists(struct
> drm_device *dev, int enable_execlists
>  {
>   WARN_ON(i915.enable_ppgtt == -1);
>  
> + /* On platforms with execlist available, vGPU will only
> +  * support execlist mode, no ring buffer mode.
> +  */
> + if (HAS_LOGICAL_RING_CONTEXTS(dev) &&
> intel_vgpu_active(dev))
> + return 1;
> +
>   if (INTEL_INFO(dev)->gen >= 9)
>   return 1;
>  
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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Enable full ppgtt for vgpu on Broadwell

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> The full ppgtt is supported now in Intel GVT-g device model.
> Broadwell
> is allowed to use it in virtual machines.
> 
> v2:
> - Keep backward compatibility on HSW with old device model (daniel)
> 
> Signed-off-by: Zhiyuan Lv 
> Signed-off-by: Zhi Wang 
> Reviewed-by: Joonas Lahtinen 

It's a good idea to add the version reviewed after Reviewed-by, when
adding a new revision. This is not to make it look like the new
revision had already been reviewed too.

I this case:

Reviewed-by: Joonas Lahtinen  (v1)

Would have been appropriate.

But you can now leave it as it is, as this patch seems fine, too. Maybe
could still add a comment in the code what makes Haswell special.

Regards, Joonas

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ed10e77..56cc8e8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -108,8 +108,8 @@ static int sanitize_enable_ppgtt(struct
> drm_device *dev, int enable_ppgtt)
>   has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
>   has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
>  
> - if (intel_vgpu_active(dev))
> - has_full_ppgtt = false; /* emulation is too hard */
> + if (intel_vgpu_active(dev) && (IS_HASWELL(dev)))
> + has_full_ppgtt = false;
>  
>   /*
>* We don't allow disabling PPGTT for gen9+ as it's a
> requirement for
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Re: [Intel-gfx] [PATCH v2] drm/atomic: Fix bookkeeping with TEST_ONLY, v2.

[shuang . he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 7274
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
ILK -1  283/283  282/283
SNB  315/315  315/315
IVB  336/336  336/336
BYT  283/283  283/283
HSW  378/378  378/378
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt@kms_flip@flip-vs-dpms-interruptible  PASS(1)  DMESG_WARN(1)
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH] drm/i915: Always mark the object as dirty when used by the GPU

[Chris Wilson]

There have been many hard to track down bugs whereby userspace forgot to
flag a write buffer and then cause graphics corruption or a hung GPU
when that buffer was later purged under memory pressure (as the buffer
appeared clean, its pages would have been evicted rather than preserved
and any changes more recent than in the backing storage would be lost).
In retrospect this is a rare optimisation against memory pressure,
already the slow path. If we always mark the buffer as dirty when
accessed by the GPU, anything not used can still be evicted cheaply
(ideal behaviour for mark-and-sweep eviction) but we do not run the risk
of corruption. For correct read serialisation, userspace still has to
notify when the GPU writes to an object. However, there are certain
situations under which userspace may wish to tell white lies to the
kernel...

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Kristian Høgsberg 
Cc: Jesse Barnes 
Cc: "Goel, Akash" 
Cc: Michał Winiarski 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 923a3c4bf0b7..a953d4975b8c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1032,6 +1032,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
u32 old_read = obj->base.read_domains;
u32 old_write = obj->base.write_domain;
 
+   obj->dirty = 1; /* be paranoid  */
obj->base.write_domain = obj->base.pending_write_domain;
if (obj->base.write_domain == 0)
obj->base.pending_read_domains |= 
obj->base.read_domains;
@@ -1039,7 +1040,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
 
i915_vma_move_to_active(vma, req);
if (obj->base.write_domain) {
-   obj->dirty = 1;
i915_gem_request_assign(&obj->last_write_req, req);
 
intel_fb_obj_invalidate(obj, ORIGIN_CS);
-- 
2.5.1

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Re: [Intel-gfx] [PATCH 2/3] drm/i915: add yesno utility function

[Jani Nikula]

On Thu, 27 Aug 2015, Jani Nikula  wrote:
> On Thu, 27 Aug 2015, Chris Wilson  wrote:
>> On Thu, Aug 27, 2015 at 04:23:30PM +0300, Jani Nikula wrote:
>>> Add a common function to return "yes" or "no" string based on the
>>> argument, and drop the local versions of it.
>>
>> Purely out of curiosity, gcc is able to amalgamate the constant strings
>> (I remember reading that it is intelligent enough to do so), right? i.e.
>> size i915.ko doesn't change (at least .data, we may see .text
>> differences for gcc having different ideas about inlines)?
>
> I admit to giving GCC the benefit of the doubt. I may be naïve that way,
> trusting the tools to do what seems like the obviously right thing to
> do.
>
> If GCC lets us down, we could try something like the yesno version in
> drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c. GCC not doing the
> right thing with that would be violating the standard.

AFAICT GCC does the right thing with the patch.

BR,
Jani.


>
> BR,
> Jani.
>
>> -Chris
>>
>> -- 
>> Chris Wilson, Intel Open Source Technology Centre
>
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: add yesno utility function

[Chris Wilson]

On Mon, Aug 31, 2015 at 05:23:27PM +0300, Jani Nikula wrote:
> On Thu, 27 Aug 2015, Jani Nikula  wrote:
> > On Thu, 27 Aug 2015, Chris Wilson  wrote:
> >> On Thu, Aug 27, 2015 at 04:23:30PM +0300, Jani Nikula wrote:
> >>> Add a common function to return "yes" or "no" string based on the
> >>> argument, and drop the local versions of it.
> >>
> >> Purely out of curiosity, gcc is able to amalgamate the constant strings
> >> (I remember reading that it is intelligent enough to do so), right? i.e.
> >> size i915.ko doesn't change (at least .data, we may see .text
> >> differences for gcc having different ideas about inlines)?
> >
> > I admit to giving GCC the benefit of the doubt. I may be naïve that way,
> > trusting the tools to do what seems like the obviously right thing to
> > do.
> >
> > If GCC lets us down, we could try something like the yesno version in
> > drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c. GCC not doing the
> > right thing with that would be violating the standard.
> 
> AFAICT GCC does the right thing with the patch.

Fwiw, I didn't see any harm in the series, so
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 11/13] drm/i915: Add two-stage ILK-style watermark programming (v3)

[Ander Conselvan De Oliveira]

On Thu, 2015-08-20 at 18:12 -0700, Matt Roper wrote:
> In addition to calculating final watermarks, let's also pre-calculate a
> set of intermediate watermark values at atomic check time.  These
> intermediate watermarks are a combination of the watermarks for the old
> state and the new state; they should satisfy the requirements of both
> states which means they can be programmed immediately when we commit the
> atomic state (without waiting for a vblank).  Once the vblank does
> happen, we can then re-program watermarks to the more optimal final
> value.
> 
> v2: Significant rebasing/rewriting.
> 
> v3:
>  - Move 'need_postvbl_update' flag to CRTC state (Daniel)
>  - Don't forget to check intermediate watermark values for validity
>(Maarten)
>  - Don't due async watermark optimization; just do it at the end of the
>atomic transaction, after waiting for vblanks.  We do want it to be
>async eventually, but adding that now will cause more trouble for
>Maarten's in-progress work.  (Maarten)
>  - Don't allocate space in crtc_state for intermediate watermarks on
>platforms that don't need it (gen9+).
>  - Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
>now that ilk_update_wm is gone.
> 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |   5 ++
>  drivers/gpu/drm/i915/intel_display.c |  77 ++-
>  drivers/gpu/drm/i915/intel_drv.h |  33 ++--
>  drivers/gpu/drm/i915/intel_pm.c  | 144 
> ---
>  4 files changed, 208 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ac13cd7..be42dd8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -622,6 +622,11 @@ struct drm_i915_display_funcs {
> struct dpll *best_clock);
>   int (*compute_pipe_wm)(struct drm_crtc *crtc,
>  struct drm_atomic_state *state);
> + int (*compute_intermediate_wm)(struct drm_device *dev,
> +struct intel_crtc_state *newstate,
> +const struct intel_crtc_state *oldstate);
> + void (*program_watermarks)(struct drm_i915_private *dev_priv);
> + void (*optimize_watermarks)(struct intel_crtc_state *cstate);
>   void (*update_wm)(struct drm_crtc *crtc);
>   int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
>   void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 8e9d87a..f929676 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11634,6 +11634,11 @@ int intel_plane_atomic_calc_changes(struct 
> drm_crtc_state *crtc_state,
>   }
>   } else if (intel_wm_need_update(plane, plane_state)) {
>   intel_crtc->atomic.update_wm_pre = true;
> +
> + /* Pre-gen9 platforms need two-step watermark updates */
> + if (INTEL_INFO(dev)->gen < 9 &&
> + dev_priv->display.program_watermarks)
> + cstate->wm.need_postvbl_update = true;
>   }
>  
>   if (visible)
> @@ -11769,6 +11774,8 @@ static int intel_crtc_atomic_check(struct drm_crtc 
> *crtc,
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   struct intel_crtc_state *pipe_config =
>   to_intel_crtc_state(crtc_state);
> + struct intel_crtc_state *old_pipe_config =
> + to_intel_crtc_state(crtc->state);
>   struct drm_atomic_state *state = crtc_state->state;
>   int ret;
>   bool mode_changed = needs_modeset(crtc_state);
> @@ -11793,8 +11800,28 @@ static int intel_crtc_atomic_check(struct drm_crtc 
> *crtc,
>   ret = 0;
>   if (dev_priv->display.compute_pipe_wm) {
>   ret = dev_priv->display.compute_pipe_wm(crtc, state);
> - if (ret)
> + if (ret) {
> + DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
> + return ret;
> + }
> + }
> +
> + if (dev_priv->display.compute_intermediate_wm) {
> + if (WARN_ON(!dev_priv->display.compute_pipe_wm))
> + return 0;
> +
> + /*
> +  * Calculate 'intermediate' watermarks that satisfy both the
> +  * old state and the new state.  We can program these
> +  * immediately.
> +  */
> + ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
> + pipe_config,
> + 
> old_pipe_config);
> + if (ret) {
> + DRM_DEBUG_KMS("No valid intermediate pipe watermarks 
> are possible\n");
>   return ret;
> + }
>   

Re: [Intel-gfx] [PATCH 6/6] drm/radeon: Send out the full AUX address

[Alex Deucher]

On Thu, Aug 27, 2015 at 10:23 AM,   wrote:
> From: Ville Syrjälä 
>
> AUX addresses are 20 bits long. Send out the entire address instead of
> just the low 16 bits.
>
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Signed-off-by: Ville Syrjälä 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/atombios_dp.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_dp.c 
> b/drivers/gpu/drm/radeon/atombios_dp.c
> index ca372c5..bd73b40 100644
> --- a/drivers/gpu/drm/radeon/atombios_dp.c
> +++ b/drivers/gpu/drm/radeon/atombios_dp.c
> @@ -171,8 +171,9 @@ radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, 
> struct drm_dp_aux_msg *msg)
> return -E2BIG;
>
> tx_buf[0] = msg->address & 0xff;
> -   tx_buf[1] = msg->address >> 8;
> -   tx_buf[2] = msg->request << 4;
> +   tx_buf[1] = (msg->address >> 8) & 0xff;
> +   tx_buf[2] = (msg->request << 4) |
> +   ((msg->address >> 16) & 0xf);
> tx_buf[3] = msg->size ? (msg->size - 1) : 0;
>
> switch (msg->request & ~DP_AUX_I2C_MOT) {
> --
> 2.4.6
>
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: eDP can be present on DDI-E

[Jani Nikula]

On Thu, 06 Aug 2015, Xiong Zhang  wrote:
> From: Rodrigo Vivi 
>
> On Skylake we have eDP-to-VGA using DDI-E and another aux.
> So let's identify it properly.
>
> Also let's remove duplicated definitions to avoid later
> confusion.
>
> Signed-off-by: Rodrigo Vivi 

Pushed to drm-intel-next-fixes with commit message rectified.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_bios.h | 5 -
>  drivers/gpu/drm/i915/intel_dp.c   | 9 +
>  2 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.h 
> b/drivers/gpu/drm/i915/intel_bios.h
> index 02255d8..a2ef0df 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -747,11 +747,6 @@ int intel_parse_bios(struct drm_device *dev);
>  #define  DVO_C   2
>  #define  DVO_D   3
>  
> -/* define the PORT for DP output type */
> -#define  PORT_IDPB   7
> -#define  PORT_IDPC   8
> -#define  PORT_IDPD   9
> -
>  /* Possible values for the "DVO Port" field for versions >= 155: */
>  #define DVO_PORT_HDMIA   0
>  #define DVO_PORT_HDMIB   1
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7cd47bc..0643a91 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4978,16 +4978,17 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
>   return -1;
>  }
>  
> -/* check the VBT to see whether the eDP is on DP-D port */
> +/* check the VBT to see whether the eDP is on another port */
>  bool intel_dp_is_edp(struct drm_device *dev, enum port port)
>  {
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   union child_device_config *p_child;
>   int i;
>   static const short port_mapping[] = {
> - [PORT_B] = PORT_IDPB,
> - [PORT_C] = PORT_IDPC,
> - [PORT_D] = PORT_IDPD,
> + [PORT_B] = DVO_PORT_DPB,
> + [PORT_C] = DVO_PORT_DPC,
> + [PORT_D] = DVO_PORT_DPD,
> + [PORT_E] = DVO_PORT_DPE,
>   };
>  
>   if (port == PORT_A)
> -- 
> 2.1.4
>
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Re: [Intel-gfx] [PATCH 6/6 v3] drm/i915: Enable HDMI on DDI-E

[Jani Nikula]

On Mon, 17 Aug 2015, Xiong Zhang  wrote:
> DDI-E doesn't have the correspondent GMBUS pin.
>
> We rely on VBT to tell us which one it being used instead.
>
> The DVI/HDMI on shared port couldn't exist.
>
> This patch isn't tested without hardware wchich has HDMI
> on DDI-E.
>
> v2: fix trailing whitespace
> v3: MISSING_CASE take place of BUG()
>
> Signed-off-by: Xiong Zhang 
> Reviewed-by: Rodrigo Vivi 

Pushed to drm-intel-next-fixes.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  5 +
>  drivers/gpu/drm/i915/intel_bios.c | 25 +
>  drivers/gpu/drm/i915/intel_hdmi.c | 21 +
>  3 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 35192d2..22e8bf0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1418,6 +1418,10 @@ enum modeset_restore {
>  #define DP_AUX_C 0x20
>  #define DP_AUX_D 0x30
>  
> +#define DDC_PIN_B  0x05
> +#define DDC_PIN_C  0x04
> +#define DDC_PIN_D  0x06
> +
>  struct ddi_vbt_port_info {
>   /*
>* This is an index in the HDMI/DVI DDI buffer translation table.
> @@ -1432,6 +1436,7 @@ struct ddi_vbt_port_info {
>   uint8_t supports_dp:1;
>  
>   uint8_t alternate_aux_channel;
> + uint8_t alternate_ddc_pin;
>  
>   uint8_t dp_boost_level;
>   uint8_t hdmi_boost_level;
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index 8e46149..a2ee347 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -905,7 +905,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv, enum port port,
>   uint8_t hdmi_level_shift;
>   int i, j;
>   bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
> - uint8_t aux_channel;
> + uint8_t aux_channel, ddc_pin;
>   /* Each DDI port can have more than one value on the "DVO Port" field,
>* so look for all the possible values for each port and abort if more
>* than one is found. */
> @@ -939,6 +939,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv, enum port port,
>   return;
>  
>   aux_channel = child->raw[25];
> + ddc_pin = child->common.ddc_pin;
>  
>   is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
>   is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
> @@ -970,11 +971,27 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv, enum port port,
>   DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
>  
>   if (is_dvi) {
> - if (child->common.ddc_pin == 0x05 && port != PORT_B)
> + if (port == PORT_E) {
> + info->alternate_ddc_pin = ddc_pin;
> + /* if DDIE share ddc pin with other port, then
> +  * dvi/hdmi couldn't exist on the shared port.
> +  * Otherwise they share the same ddc bin and system
> +  * couldn't communicate with them seperately. */
> + if (ddc_pin == DDC_PIN_B) {
> + 
> dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0;
> + 
> dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0;
> + } else if (ddc_pin == DDC_PIN_C) {
> + 
> dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0;
> + 
> dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0;
> + } else if (ddc_pin == DDC_PIN_D) {
> + 
> dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0;
> + 
> dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0;
> + }
> + } else if (ddc_pin == DDC_PIN_B && port != PORT_B)
>   DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
> - if (child->common.ddc_pin == 0x04 && port != PORT_C)
> + else if (ddc_pin == DDC_PIN_C && port != PORT_C)
>   DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
> - if (child->common.ddc_pin == 0x06 && port != PORT_D)
> + else if (ddc_pin == DDC_PIN_D && port != PORT_D)
>   DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
>   }
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 7185062..d1a7f7b 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1956,6 +1956,7 @@ void intel_hdmi_init_connector(struct 
> intel_digital_port *intel_dig_port,
>   struct drm_device *dev = intel_encoder->base.dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   enum port port = intel_dig_port->port;
> + uint8_t alternate_ddc_pin;
>  
>   drm_connector_init(dev, connector, &intel_hdmi_connector_

Re: [Intel-gfx] [PATCH 8/6] drm/i915/skl: Enable DDI-E

[Jani Nikula]

On Sat, 08 Aug 2015, Rodrigo Vivi  wrote:
> There are OEMs using DDI-E out there,
> so let's enable it.
>
> Unfortunately there is no detection bit for DDI-E
> So we need to rely on VBT for that.
>
> I also need to give credits to Xiong since before seing
> his approach to check info->support_* I was creating an ugly
> vbt->ddie_sfuse_strap in order to propagate the ddi presence info
>
> v2: Rebased as last patch in the series. since all other patches
> in this series are needed for anything working propperly on DDI-E.
>
> Credits-to: "Zhang, Xiong Y" 
> Cc: "Zhang, Xiong Y" 
> Signed-off-by: Rodrigo Vivi 

Pushed to drm-intel-next-fixes.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_bios.c| 14 +++---
>  drivers/gpu/drm/i915/intel_bios.h|  2 ++
>  drivers/gpu/drm/i915/intel_display.c |  9 +
>  3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index c417973..c5b5a59b 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -898,19 +898,19 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv, enum port port,
>   /* Each DDI port can have more than one value on the "DVO Port" field,
>* so look for all the possible values for each port and abort if more
>* than one is found. */
> - int dvo_ports[][2] = {
> - {DVO_PORT_HDMIA, DVO_PORT_DPA},
> - {DVO_PORT_HDMIB, DVO_PORT_DPB},
> - {DVO_PORT_HDMIC, DVO_PORT_DPC},
> - {DVO_PORT_HDMID, DVO_PORT_DPD},
> - {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ },
> + int dvo_ports[][3] = {
> + {DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
> + {DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
> + {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> + {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> + {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
>   };
>  
>   /* Find the child device to use, abort if more than one found. */
>   for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
>   it = dev_priv->vbt.child_dev + i;
>  
> - for (j = 0; j < 2; j++) {
> + for (j = 0; j < 3; j++) {
>   if (dvo_ports[port][j] == -1)
>   break;
>  
> diff --git a/drivers/gpu/drm/i915/intel_bios.h 
> b/drivers/gpu/drm/i915/intel_bios.h
> index 77bf1dd..a2ef0df 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -759,6 +759,8 @@ int intel_parse_bios(struct drm_device *dev);
>  #define DVO_PORT_DPC 8
>  #define DVO_PORT_DPD 9
>  #define DVO_PORT_DPA 10
> +#define DVO_PORT_DPE 11
> +#define DVO_PORT_HDMIE   12
>  #define DVO_PORT_MIPIA   21
>  #define DVO_PORT_MIPIB   22
>  #define DVO_PORT_MIPIC   23
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index fcf1230..7bf6209 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13961,6 +13961,15 @@ static void intel_setup_outputs(struct drm_device 
> *dev)
>   intel_ddi_init(dev, PORT_C);
>   if (found & SFUSE_STRAP_DDID_DETECTED)
>   intel_ddi_init(dev, PORT_D);
> + /*
> +  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
> +  */
> + if (IS_SKYLAKE(dev) &&
> + (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
> +  dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
> +  dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
> + intel_ddi_init(dev, PORT_E);
> +
>   } else if (HAS_PCH_SPLIT(dev)) {
>   int found;
>   dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
> -- 
> 2.4.3
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Adding DDI_E power well domain

[Jani Nikula]

On Thu, 13 Aug 2015, Xiong Zhang  wrote:
> From B spec, DDI_E port belong to PowerWell 2, but
> DDI_E share the powerwell_req/staus register bit with
> DDI_A which belong to DDI_A_E_POWER_WELL.
>
> In order to communicate with the connector on DDI-E, both
> DDI_A_E_POWER_WELL and POWER_WELL_2 must be enabled.
>
> Currently intel_dp_power_get(DDI_E) only enable
> DDI_A_E_POWER_WELL, this patch will not only enable
> DDI_a_E_POWER_WELL but also enable POWER_WELL_2.
>
> This patch also fix the DDI-E hotplug function.
>
> Signed-off-by: Xiong Zhang 

Pushed to drm-intel-next-fixes.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  drivers/gpu/drm/i915/intel_display.c| 3 ++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
>  4 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 86734be..5523b6e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2564,6 +2564,8 @@ static const char *power_domain_str(enum 
> intel_display_power_domain domain)
>   return "PORT_DDI_D_2_LANES";
>   case POWER_DOMAIN_PORT_DDI_D_4_LANES:
>   return "PORT_DDI_D_4_LANES";
> + case POWER_DOMAIN_PORT_DDI_E_2_LANES:
> + return "PORT_DDI_E_2_LANES";
>   case POWER_DOMAIN_PORT_DSI:
>   return "PORT_DSI";
>   case POWER_DOMAIN_PORT_CRT:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b157865..ee71f90 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -182,6 +182,7 @@ enum intel_display_power_domain {
>   POWER_DOMAIN_PORT_DDI_C_4_LANES,
>   POWER_DOMAIN_PORT_DDI_D_2_LANES,
>   POWER_DOMAIN_PORT_DDI_D_4_LANES,
> + POWER_DOMAIN_PORT_DDI_E_2_LANES,
>   POWER_DOMAIN_PORT_DSI,
>   POWER_DOMAIN_PORT_CRT,
>   POWER_DOMAIN_PORT_OTHER,
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 801187c..ccd3f0b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5150,7 +5150,6 @@ static enum intel_display_power_domain 
> port_to_power_domain(enum port port)
>  {
>   switch (port) {
>   case PORT_A:
> - case PORT_E:
>   return POWER_DOMAIN_PORT_DDI_A_4_LANES;
>   case PORT_B:
>   return POWER_DOMAIN_PORT_DDI_B_4_LANES;
> @@ -5158,6 +5157,8 @@ static enum intel_display_power_domain 
> port_to_power_domain(enum port port)
>   return POWER_DOMAIN_PORT_DDI_C_4_LANES;
>   case PORT_D:
>   return POWER_DOMAIN_PORT_DDI_D_4_LANES;
> + case PORT_E:
> + return POWER_DOMAIN_PORT_DDI_E_2_LANES;
>   default:
>   WARN_ON_ONCE(1);
>   return POWER_DOMAIN_PORT_OTHER;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 821644d..af7fdb3 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -297,6 +297,7 @@ static void hsw_set_power_well(struct drm_i915_private 
> *dev_priv,
>   BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
>   BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
>   BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
> + BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |  \
>   BIT(POWER_DOMAIN_AUX_B) |   \
>   BIT(POWER_DOMAIN_AUX_C) |   \
>   BIT(POWER_DOMAIN_AUX_D) |   \
> @@ -316,6 +317,7 @@ static void hsw_set_power_well(struct drm_i915_private 
> *dev_priv,
>  #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (  \
>   BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |  \
>   BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |  \
> + BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |  \
>   BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (\
>   BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
> -- 
> 2.1.4
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH] drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6

[Jani Nikula]

On Sat, 29 Aug 2015, Mikko Rapeli  wrote:
> Please, please merge this patch already. Without it hibernation poweroff
> is broken for several users. There were some doubts raised over the
> approach on lkml review but Imre as maintainer thinks this is the right
> thing to do and users like me need this patch.
>
> Tested again with Thinkpad T60 and kernel version 4.1.6.
>
> Tested-by: Mikko Rapeli 

Pushed to drm-intel-next-fixes.

BR,
Jani.

>
> -Mikko
>
> On Tue, Jun 30, 2015 at 05:06:47PM +0300, Imre Deak wrote:
>> commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
>> Author: Imre Deak 
>> Date:   Thu Oct 23 19:23:26 2014 +0300
>> 
>> drm/i915: add poweroff_late handler
>> 
>> introduced a regression on old platforms during hibernation. A workaround was
>> added in
>> 
>> commit ab3be73fa7b43f4c3648ce29b5fd649ea54d3adb
>> Author: Imre Deak 
>> Date:   Mon Mar 2 13:04:41 2015 +0200
>> 
>> drm/i915: gen4: work around hang during hibernation
>> 
>> using an explicit blacklist for the GENs/BIOS vendors where the issue was
>> reported. Later there we had reports of the same failure on platforms not on
>> this list.
>> 
>> To my best knowledge the correct thing to do is still to put the device to 
>> PCI
>> D3 state during hibernation, see [1] and [2] for the reasons. This also 
>> aligns
>> with our future plans to unify more the runtime and system suspend/resume
>> paths. Since an exact blacklist seems to be impractical (multiple GENs and
>> BIOS vendors are affected) apply the workaround on everything pre GEN6.
>> 
>> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-February/060710.html
>> [2] https://lkml.org/lkml/2015/6/22/274
>> 
>> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=95061
>> Reported-by: Ilya Tumaykin 
>> Reported-by: Dirk Griesbach 
>> Reported-by: Pavel Machek 
>> Reported-by: Mikko Rapeli 
>> Reported-by: Paul Bolle 
>> CC: sta...@vger.kernel.org
>> Signed-off-by: Imre Deak 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c | 15 +--
>>  1 file changed, 9 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index e44dc0d..1e675ff 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -664,15 +664,18 @@ static int i915_drm_suspend_late(struct drm_device 
>> *drm_dev, bool hibernation)
>>  
>>  pci_disable_device(drm_dev->pdev);
>>  /*
>> - * During hibernation on some GEN4 platforms the BIOS may try to access
>> + * During hibernation on some platforms the BIOS may try to access
>>   * the device even though it's already in D3 and hang the machine. So
>>   * leave the device in D0 on those platforms and hope the BIOS will
>> - * power down the device properly. Platforms where this was seen:
>> - * Lenovo Thinkpad X301, X61s
>> + * power down the device properly. The issue was seen on multiple old
>> + * GENs with different BIOS vendors, so having an explicit blacklist
>> + * is inpractical; apply the workaround on everything pre GEN6. The
>> + * platforms where the issue was seen:
>> + * Lenovo Thinkpad X301, X61s, X60, T60, X41
>> + * Fujitsu FSC S7110
>> + * Acer Aspire 1830T
>>   */
>> -if (!(hibernation &&
>> -  drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
>> -  INTEL_INFO(dev_priv)->gen == 4))
>> +if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
>>  pci_set_power_state(drm_dev->pdev, PCI_D3hot);
>>  
>>  return 0;
>> -- 
>> 2.1.4
>> 

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Check DP link status on long hpd too

[Jani Nikula]

On Thu, 20 Aug 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
>
> We are no longer checkling the DP link status on long hpd. We used to do
> that from the .hot_plug() handler, but it was removed when MST got
> introduced.
>
> If there's no userspace we now fail to retrain the link if the sink
> power is toggled (or cable yanked and replugged), meaning the user is
> left staring at a blank screen. With the retraining put back that should
> be fixed.
>
> Also remove the leftover comment that referred to the old retraining
> from .hot_plug().
>
> Fixes a regression introduced in:
> commit 0e32b39ceed665bfa4a77a4bc307b6652b991632
> Author: Dave Airlie 
> Date:   Fri May 2 14:02:48 2014 +1000
>
> drm/i915: add DP 1.2 MST support (v0.7)
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89453
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91407
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89461
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89594
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85641
> Cc: Dave Airlie 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä 

Pushed to drm-intel-next-fixes.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 +--
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d32ce48..b014158 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5024,9 +5024,12 @@ intel_dp_hpd_pulse(struct intel_digital_port 
> *intel_dig_port, bool long_hpd)
>  
>   intel_dp_probe_oui(intel_dp);
>  
> - if (!intel_dp_probe_mst(intel_dp))
> + if (!intel_dp_probe_mst(intel_dp)) {
> + drm_modeset_lock(&dev->mode_config.connection_mutex, 
> NULL);
> + intel_dp_check_link_status(intel_dp);
> + drm_modeset_unlock(&dev->mode_config.connection_mutex);
>   goto mst_fail;
> -
> + }
>   } else {
>   if (intel_dp->is_mst) {
>   if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
> @@ -5034,10 +5037,6 @@ intel_dp_hpd_pulse(struct intel_digital_port 
> *intel_dig_port, bool long_hpd)
>   }
>  
>   if (!intel_dp->is_mst) {
> - /*
> -  * we'll check the link status via the normal hot plug 
> path later -
> -  * but for short hpds we should check it now
> -  */
>   drm_modeset_lock(&dev->mode_config.connection_mutex, 
> NULL);
>   intel_dp_check_link_status(intel_dp);
>   drm_modeset_unlock(&dev->mode_config.connection_mutex);
> -- 
> 2.4.6
>
> ___
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[Intel-gfx] [PATCH] drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmaps

[Michał Winiarski]

On each call to gen8_alloc_va_range_3lvl we're allocating temporary
bitmaps needed for error handling. Unfortunately, when we increase
address space size (48b ppgtt) we do additional (512 - 4) calls to
kcalloc, increasing latency between exec and actual start of execution
on the GPU. Let's just do a single kcalloc and setup proper offsets in
an array, we can also drop the size from free_gen8_temp_bitmaps since
it's no longer needed.

Cc: Mika Kuoppala 
Cc: Michel Thierry 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++
 1 file changed, 15 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4a76807..fd5545a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1126,13 +1126,9 @@ unwind_out:
 }
 
 static void
-free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
-  uint32_t pdpes)
+free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 {
-   int i;
-
-   for (i = 0; i < pdpes; i++)
-   kfree(new_pts[i]);
+   kfree(*new_pts);
kfree(new_pts);
kfree(new_pds);
 }
@@ -1154,17 +1150,16 @@ int __must_check alloc_gen8_temp_bitmaps(unsigned long 
**new_pds,
return -ENOMEM;
 
pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
-   if (!pts) {
-   kfree(pds);
-   return -ENOMEM;
-   }
+   if (!pts)
+   goto err_out;
 
-   for (i = 0; i < pdpes; i++) {
-   pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
-sizeof(unsigned long), GFP_KERNEL);
-   if (!pts[i])
-   goto err_out;
-   }
+   *pts = kcalloc(pdpes * BITS_TO_LONGS(I915_PDES),
+   sizeof(unsigned long), GFP_KERNEL);
+   if (!*pts)
+   goto err_out;
+
+   for (i = 0; i < pdpes; i++)
+   pts[i] = *pts + i * BITS_TO_LONGS(I915_PDES);
 
*new_pds = pds;
*new_pts = pts;
@@ -1172,7 +1167,7 @@ int __must_check alloc_gen8_temp_bitmaps(unsigned long 
**new_pds,
return 0;
 
 err_out:
-   free_gen8_temp_bitmaps(pds, pts, pdpes);
+   free_gen8_temp_bitmaps(pds, pts);
return -ENOMEM;
 }
 
@@ -1220,7 +1215,7 @@ static int gen8_alloc_va_range_3lvl(struct 
i915_address_space *vm,
ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
new_page_dirs);
if (ret) {
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
return ret;
}
 
@@ -1278,7 +1273,7 @@ static int gen8_alloc_va_range_3lvl(struct 
i915_address_space *vm,
gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
}
 
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
mark_tlbs_dirty(ppgtt);
return 0;
 
@@ -1291,7 +1286,7 @@ err_out:
for_each_set_bit(pdpe, new_page_dirs, pdpes)
free_pd(dev, pdp->page_directory[pdpe]);
 
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
mark_tlbs_dirty(ppgtt);
return ret;
 }
-- 
2.4.3

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Re: [Intel-gfx] [PATCH] drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmaps

[Chris Wilson]

On Mon, Aug 31, 2015 at 06:27:40PM +0200, Michał Winiarski wrote:
> On each call to gen8_alloc_va_range_3lvl we're allocating temporary
> bitmaps needed for error handling. Unfortunately, when we increase
> address space size (48b ppgtt) we do additional (512 - 4) calls to
> kcalloc, increasing latency between exec and actual start of execution
> on the GPU. Let's just do a single kcalloc and setup proper offsets in
> an array, we can also drop the size from free_gen8_temp_bitmaps since
> it's no longer needed.
> 
> Cc: Mika Kuoppala 
> Cc: Michel Thierry 
> Signed-off-by: Michał Winiarski 

Whilst you are here, mind using GFP_TEMPORARY as well?
-Chris

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[Intel-gfx] [PATCH v2] drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmaps

[Michał Winiarski]

On each call to gen8_alloc_va_range_3lvl we're allocating temporary
bitmaps needed for error handling. Unfortunately, when we increase
address space size (48b ppgtt) we do additional (512 - 4) calls to
kcalloc, increasing latency between exec and actual start of execution
on the GPU. Let's just do a single kcalloc and setup proper offsets in
an array, we can also drop the size from free_gen8_temp_bitmaps since
it's no longer needed.

v2: Use GFP_TEMPORARY to make the allocations reclaimable.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 39 -
 1 file changed, 17 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4a76807..9270c47 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1126,13 +1126,9 @@ unwind_out:
 }
 
 static void
-free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
-  uint32_t pdpes)
+free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 {
-   int i;
-
-   for (i = 0; i < pdpes; i++)
-   kfree(new_pts[i]);
+   kfree(*new_pts);
kfree(new_pts);
kfree(new_pds);
 }
@@ -1149,22 +1145,21 @@ int __must_check alloc_gen8_temp_bitmaps(unsigned long 
**new_pds,
unsigned long *pds;
unsigned long **pts;
 
-   pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
+   pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), 
GFP_TEMPORARY);
if (!pds)
return -ENOMEM;
 
-   pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
-   if (!pts) {
-   kfree(pds);
-   return -ENOMEM;
-   }
+   pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_TEMPORARY);
+   if (!pts)
+   goto err_out;
 
-   for (i = 0; i < pdpes; i++) {
-   pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
-sizeof(unsigned long), GFP_KERNEL);
-   if (!pts[i])
-   goto err_out;
-   }
+   *pts = kcalloc(pdpes * BITS_TO_LONGS(I915_PDES),
+   sizeof(unsigned long), GFP_TEMPORARY);
+   if (!*pts)
+   goto err_out;
+
+   for (i = 0; i < pdpes; i++)
+   pts[i] = *pts + i * BITS_TO_LONGS(I915_PDES);
 
*new_pds = pds;
*new_pts = pts;
@@ -1172,7 +1167,7 @@ int __must_check alloc_gen8_temp_bitmaps(unsigned long 
**new_pds,
return 0;
 
 err_out:
-   free_gen8_temp_bitmaps(pds, pts, pdpes);
+   free_gen8_temp_bitmaps(pds, pts);
return -ENOMEM;
 }
 
@@ -1220,7 +1215,7 @@ static int gen8_alloc_va_range_3lvl(struct 
i915_address_space *vm,
ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
new_page_dirs);
if (ret) {
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
return ret;
}
 
@@ -1278,7 +1273,7 @@ static int gen8_alloc_va_range_3lvl(struct 
i915_address_space *vm,
gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
}
 
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
mark_tlbs_dirty(ppgtt);
return 0;
 
@@ -1291,7 +1286,7 @@ err_out:
for_each_set_bit(pdpe, new_page_dirs, pdpes)
free_pd(dev, pdp->page_directory[pdpe]);
 
-   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+   free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
mark_tlbs_dirty(ppgtt);
return ret;
 }
-- 
2.4.3

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[Intel-gfx] [PATCH libdrm v2] intel: resolve shadowing warnings

[Emil Velikov]

v2: keep the bo_gem declaration in exec2() within the loop (Chris)

Cc: Chris Wilson 
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 intel/intel_bufmgr_fake.c | 2 +-
 intel/intel_bufmgr_gem.c  | 7 +++
 intel/intel_decode.c  | 7 ++-
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c
index 75387b7..551e05d 100644
--- a/intel/intel_bufmgr_fake.c
+++ b/intel/intel_bufmgr_fake.c
@@ -1460,7 +1460,7 @@ restart:
assert(ret == 0);
 
if (bufmgr_fake->exec != NULL) {
-   int ret = bufmgr_fake->exec(bo, used, bufmgr_fake->exec_priv);
+   ret = bufmgr_fake->exec(bo, used, bufmgr_fake->exec_priv);
if (ret != 0) {
pthread_mutex_unlock(&bufmgr_fake->lock);
return ret;
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 2723e21..7303903 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2165,8 +2165,7 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
drm_intel_gem_dump_validation_list(bufmgr_gem);
 
for (i = 0; i < bufmgr_gem->exec_count; i++) {
-   drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
-   drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+   bo_gem = (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
 
bo_gem->idle = false;
 
@@ -2260,8 +2259,8 @@ skip_execution:
drm_intel_gem_dump_validation_list(bufmgr_gem);
 
for (i = 0; i < bufmgr_gem->exec_count; i++) {
-   drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
-   drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
+   drm_intel_bo_gem *bo_gem =
+   (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
 
bo_gem->idle = false;
 
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2b902a3..345d457 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3630,7 +3630,6 @@ decode_3d_965(struct drm_intel_decode *ctx)
 
case 0x7a00:
if (IS_GEN6(devid) || IS_GEN7(devid)) {
-   unsigned int i;
if (len != 4 && len != 5)
fprintf(out, "Bad count in PIPE_CONTROL\n");
 
@@ -3732,8 +3731,6 @@ decode_3d_965(struct drm_intel_decode *ctx)
if (opcode_3d->func) {
return opcode_3d->func(ctx);
} else {
-   unsigned int i;
-
instr_out(ctx, 0, "%s\n", opcode_3d->name);
 
for (i = 1; i < len; i++) {
@@ -3883,9 +3880,9 @@ drm_intel_decode_set_head_tail(struct drm_intel_decode 
*ctx,
 
 void
 drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
-FILE *out)
+FILE *output)
 {
-   ctx->out = out;
+   ctx->out = output;
 }
 
 /**
-- 
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[Intel-gfx] [PATCH libdrm v2] intel: error out on has_error in exec2

[Emil Velikov]

Just like we do for the original exec()

v2: move bo_gem declaration to the top of the function.

Cc: Chris Wilson 
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 intel/intel_bufmgr_gem.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 7303903..5287419 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2185,10 +2185,14 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context 
*ctx,
 unsigned int flags)
 {
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
+   drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
struct drm_i915_gem_execbuffer2 execbuf;
int ret = 0;
int i;
 
+   if (bo_gem->has_error)
+   return -ENOMEM;
+
switch (flags & 0x7) {
default:
return -EINVAL;
@@ -2259,8 +2263,7 @@ skip_execution:
drm_intel_gem_dump_validation_list(bufmgr_gem);
 
for (i = 0; i < bufmgr_gem->exec_count; i++) {
-   drm_intel_bo_gem *bo_gem =
-   (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
+   bo_gem = (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
 
bo_gem->idle = false;
 
-- 
2.5.0

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Re: [Intel-gfx] [PATCH libdrm v2] intel: resolve shadowing warnings

[Chris Wilson]

On Mon, Aug 31, 2015 at 07:13:12PM +0100, Emil Velikov wrote:
> v2: keep the bo_gem declaration in exec2() within the loop (Chris)
> 
> Cc: Chris Wilson 
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Emil Velikov 
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH libdrm v2] intel: error out on has_error in exec2

[Chris Wilson]

On Mon, Aug 31, 2015 at 07:14:12PM +0100, Emil Velikov wrote:
> Just like we do for the original exec()
> 
> v2: move bo_gem declaration to the top of the function.
> 
> Cc: Chris Wilson 
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Emil Velikov 
> ---
>  intel/intel_bufmgr_gem.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 7303903..5287419 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -2185,10 +2185,14 @@ do_exec2(drm_intel_bo *bo, int used, 
> drm_intel_context *ctx,
>unsigned int flags)
>  {
>   drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
> + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
>   struct drm_i915_gem_execbuffer2 execbuf;
>   int ret = 0;
>   int i;
>  
> + if (bo_gem->has_error)
> + return -ENOMEM;
> +
>   switch (flags & 0x7) {
>   default:
>   return -EINVAL;
> @@ -2259,8 +2263,7 @@ skip_execution:
>   drm_intel_gem_dump_validation_list(bufmgr_gem);
>  
>   for (i = 0; i < bufmgr_gem->exec_count; i++) {
> - drm_intel_bo_gem *bo_gem =
> - (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
> + bo_gem = (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];

Reusing bo_gem here is a little worrying as it would be very easy for
someone to add code to the end of the function thinking that bo_gem
still was the batch.

If we had

static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
{
return (drm_intel_bo_gem *)bo;
}

then we can start doing one offs like

if (to_bo_gem(bo)->has_error) return -ENOMEM;

and of course
for (i = 0; i < bufmgr_gem->exec_count; i++) {
drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
-Chris

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Re: [Intel-gfx] [PATCH v2] drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmaps

[Chris Wilson]

On Mon, Aug 31, 2015 at 06:59:40PM +0200, Michał Winiarski wrote:
> On each call to gen8_alloc_va_range_3lvl we're allocating temporary
> bitmaps needed for error handling. Unfortunately, when we increase
> address space size (48b ppgtt) we do additional (512 - 4) calls to
> kcalloc, increasing latency between exec and actual start of execution
> on the GPU. Let's just do a single kcalloc and setup proper offsets in
> an array, we can also drop the size from free_gen8_temp_bitmaps since
> it's no longer needed.
> 
> v2: Use GFP_TEMPORARY to make the allocations reclaimable.
> 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michel Thierry 
> Signed-off-by: Michał Winiarski 

Is there any reason why it remains a 2D array though? Looks like it can
be reduced to a single block. And why do we allocate a bitmap for the
whole address space rather than just the range being allocated?

While you may just answer the questions posed, this looks clumsy:

> + *pts = kcalloc(pdpes * BITS_TO_LONGS(I915_PDES),
> + sizeof(unsigned long), GFP_TEMPORARY);
> + if (!*pts)
> + goto err_out;
> +
> + for (i = 0; i < pdpes; i++)
> + pts[i] = *pts + i * BITS_TO_LONGS(I915_PDES);

i..e

for (i = 1; i < pdpes; i++)
pts[i] = pts[0] + i* BITS_TO_LONGS(I915_PDES);

raises fewer questions.
-Chris

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Re: [Intel-gfx] [PATCH libdrm v2] intel: error out on has_error in exec2

[Emil Velikov]

On 31 August 2015 at 19:26, Chris Wilson  wrote:
> On Mon, Aug 31, 2015 at 07:14:12PM +0100, Emil Velikov wrote:
>> Just like we do for the original exec()
>>
>> v2: move bo_gem declaration to the top of the function.
>>
>> Cc: Chris Wilson 
>> Cc: intel-gfx@lists.freedesktop.org
>> Signed-off-by: Emil Velikov 
>> ---
>>  intel/intel_bufmgr_gem.c | 7 +--
>>  1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
>> index 7303903..5287419 100644
>> --- a/intel/intel_bufmgr_gem.c
>> +++ b/intel/intel_bufmgr_gem.c
>> @@ -2185,10 +2185,14 @@ do_exec2(drm_intel_bo *bo, int used, 
>> drm_intel_context *ctx,
>>unsigned int flags)
>>  {
>>   drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
>> + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
>>   struct drm_i915_gem_execbuffer2 execbuf;
>>   int ret = 0;
>>   int i;
>>
>> + if (bo_gem->has_error)
>> + return -ENOMEM;
>> +
>>   switch (flags & 0x7) {
>>   default:
>>   return -EINVAL;
>> @@ -2259,8 +2263,7 @@ skip_execution:
>>   drm_intel_gem_dump_validation_list(bufmgr_gem);
>>
>>   for (i = 0; i < bufmgr_gem->exec_count; i++) {
>> - drm_intel_bo_gem *bo_gem =
>> - (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
>> + bo_gem = (drm_intel_bo_gem *) bufmgr_gem->exec_bos[i];
>
> Reusing bo_gem here is a little worrying as it would be very easy for
> someone to add code to the end of the function thinking that bo_gem
> still was the batch.
>
Doesn't this concert apply to drm_intel_gem_bo_exec() as well ?

> If we had
>
> static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
> {
> return (drm_intel_bo_gem *)bo;
> }
>
> then we can start doing one offs like
>
> if (to_bo_gem(bo)->has_error) return -ENOMEM;
>
> and of course
> for (i = 0; i < bufmgr_gem->exec_count; i++) {
> drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);

How about we do this as a follow up patch (4.1/17) that covers both functions ?

Thanks again,
Emil
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Re: [Intel-gfx] [PATCH libdrm v2] intel: error out on has_error in exec2

[Chris Wilson]

On Mon, Aug 31, 2015 at 08:01:21PM +0100, Emil Velikov wrote:
> > Reusing bo_gem here is a little worrying as it would be very easy for
> > someone to add code to the end of the function thinking that bo_gem
> > still was the batch.
> >
> Doesn't this concert apply to drm_intel_gem_bo_exec() as well ?

Probably. Haven't looked at that in years. :p

> > If we had
> >
> > static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
> > {
> > return (drm_intel_bo_gem *)bo;
> > }
> >
> > then we can start doing one offs like
> >
> > if (to_bo_gem(bo)->has_error) return -ENOMEM;
> >
> > and of course
> > for (i = 0; i < bufmgr_gem->exec_count; i++) {
> > drm_intel_bo_gem *bo_gem = 
> > to_bo_gem(bufmgr_gem->exec_bos[i]);
> 
> How about we do this as a follow up patch (4.1/17) that covers both functions 
> ?

If you are quick...
-Chris

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Re: [Intel-gfx] [PATCH v2 00/22] Enable gpu switching on the MacBook Pro

[Jani Nikula]

On Sat, 29 Aug 2015, Lukas Wunner  wrote:
> Hi Daniel, Hi Jani,
>
> the patch set I've posted August 12 included 3 commits which fix bugs
> in i915. These bugs should be fixed independently of MacBook Pro GPU
> switching, please consider merging them:
>
> drm/i915: Preserve SSC earlier
> http://patchwork.freedesktop.org/patch/56921/
>
> drm/i915: Fix failure paths around initial fbdev allocation
> http://patchwork.freedesktop.org/patch/53673/
> drm/i915: On fb alloc failure, unref gem object where it gets refed
> http://patchwork.freedesktop.org/patch/53674/
>
> The latter two commits relate to a bug Jani was tracking before his
> holidays which has unfortunately fallen by the wayside.

Sorry about that. Unfortunately the target is moving fast, and they no
longer apply. Please resend on top of current nightly.

BR,
Jani.


>
> Thanks,
>
> Lukas

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Re: [Intel-gfx] [PATCH v2 12/22] drm/i915: Preserve SSC earlier

[Jesse Barnes]

On 07/15/2015 04:57 AM, Lukas Wunner wrote:
> Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
> added code to intel_modeset_gem_init to override the SSC status read
> from VBT with the SSC status set by BIOS.
> 
> However, intel_modeset_gem_init is invoked *after* intel_modeset_init,
> which calls intel_setup_outputs, which *modifies* SSC status by way of
> intel_init_pch_refclk. So unlike advertised, intel_modeset_gem_init
> doesn't preserve the SSC status set by BIOS but whatever
> intel_init_pch_refclk decided on.
> 
> This is a problem on dual gpu laptops such as the MacBook Pro which
> require either a handler to switch DDC lines, or the discrete gpu
> to proxy DDC/AUX communication: Both the handler and the discrete
> gpu may initialize after the i915 driver, and consequently, an LVDS
> connector may initially seem disconnected and the SSC therefore
> is disabled by intel_init_pch_refclk, but on reprobe the connector
> may turn out to be connected and the SSC must then be enabled.
> 
> Due to 92122789b2d6 however, the SSC is not enabled on reprobe since
> it is assumed BIOS disabled it while in fact it was disabled by
> intel_init_pch_refclk.
> 
> Also, because the SSC status is preserved so late, the preserved value
> only ever gets used on resume but not on panel initialization:
> intel_modeset_init calls intel_init_display which indirectly calls
> intel_panel_use_ssc via multiple subroutines, *before* the BIOS value
> overrides the VBT value in intel_modeset_gem_init (intel_panel_use_ssc
> is the sole user of dev_priv->vbt.lvds_use_ssc).
> 
> Fix this by moving the code introduced by 92122789b2d6 from
> intel_modeset_gem_init to intel_modeset_init before the invocation
> of intel_setup_outputs and intel_init_display.
> 
> Add a DRM_DEBUG_KMS as suggested way back by Jani:
> http://lists.freedesktop.org/archives/intel-gfx/2014-June/04.html
> 
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=88861
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61115
> Tested-by: Paul Hordiienko 
> [MBP  6,2 2010  intel ILK + nvidia GT216  pre-retina]
> Tested-by: William Brown 
> [MBP  8,2 2011  intel SNB + amd turks pre-retina]
> Tested-by: Lukas Wunner 
> [MBP  9,1 2012  intel IVB + nvidia GK107  pre-retina]
> Tested-by: Bruno Bierbaumer 
> [MBP 11,3 2013  intel HSW + nvidia GK107  retina -- work in progress]
> 
> Fixes: 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
> Signed-off-by: Lukas Wunner 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 29 ++---
>  1 file changed, 18 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index af0bcfe..6335883 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14893,6 +14893,24 @@ void intel_modeset_init(struct drm_device *dev)
>   if (INTEL_INFO(dev)->num_pipes == 0)
>   return;
>  
> + /*
> +  * There may be no VBT; and if the BIOS enabled SSC we can
> +  * just keep using it to avoid unnecessary flicker.  Whereas if the
> +  * BIOS isn't using it, don't assume it will work even if the VBT
> +  * indicates as much.
> +  */
> + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> + bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
> + DREF_SSC1_ENABLE);
> +
> + if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
> + DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT 
> which says %sabled\n",
> +  bios_lvds_use_ssc ? "en" : "dis",
> +  dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
> + dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
> + }
> + }
> +
>   intel_init_display(dev);
>   intel_init_audio(dev);
>  
> @@ -15446,7 +15464,6 @@ err:
>  
>  void intel_modeset_gem_init(struct drm_device *dev)
>  {
> - struct drm_i915_private *dev_priv = dev->dev_private;
>   struct drm_crtc *c;
>   struct drm_i915_gem_object *obj;
>   int ret;
> @@ -15455,16 +15472,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
>   intel_init_gt_powersave(dev);
>   mutex_unlock(&dev->struct_mutex);
>  
> - /*
> -  * There may be no VBT; and if the BIOS enabled SSC we can
> -  * just keep using it to avoid unnecessary flicker.  Whereas if the
> -  * BIOS isn't using it, don't assume it will work even if the VBT
> -  * indicates as much.
> -  */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> - dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
> - DREF_SSC1_ENABLE);
> -
>   intel_modeset_init_hw(dev);
>  
>   intel_setup_overlay(dev);
> 

Yeah looks good (and I'm having deja vu here; I thought I ran into the same 
o

[Intel-gfx] [PATCH 2/2] drm/i915/skl+: Enable pipe CSC on cursor planes. (v2)

[Bob Paauwe]

Extend this to SKL and BXT as it's needed for these platforms as well.

v2: Change if condition to HAS_DDI() instead of listing each platform
Signed-off-by: Bob Paauwe 
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 88f9764..ba180f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10001,7 +10001,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, 
u32 base)
}
cntl |= pipe << 28; /* Connect to correct pipe */
 
-   if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+   if (HAS_DDI(dev))
cntl |= CURSOR_PIPE_CSC_ENABLE;
}
 
-- 
2.1.0

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Re: [Intel-gfx] [PATCH] drm/i915: Fix module initialisation, v2.

[Matt Roper]

On Thu, Aug 27, 2015 at 03:15:15PM +0200, Maarten Lankhorst wrote:
> Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
> Remove the legacy suspend/resume, to fix a warning introduced by:
> 
> "drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers"
> 
> and removing the .get_vblank_timestamp reset to NULL. It's a noop without UMS.
> 
> Signed-off-by: Maarten Lankhorst 

Reviewed-by: Matt Roper 

> ---
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 097d4ba0421c..f0eaa6f8826b 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -364,12 +364,12 @@ static void i915_switcheroo_set_state(struct pci_dev 
> *pdev, enum vga_switcheroo_
>   dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>   /* i915 resume handler doesn't set to D0 */
>   pci_set_power_state(dev->pdev, PCI_D0);
> - i915_resume_legacy(dev);
> + i915_resume_switcheroo(dev);
>   dev->switch_power_state = DRM_SWITCH_POWER_ON;
>   } else {
>   pr_err("switched off\n");
>   dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
> - i915_suspend_legacy(dev, pmm);
> + i915_suspend_switcheroo(dev, pmm);
>   dev->switch_power_state = DRM_SWITCH_POWER_OFF;
>   }
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ce3bd0c713b9..4646fe1a0499 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -679,7 +679,7 @@ static int i915_drm_suspend_late(struct drm_device 
> *drm_dev, bool hibernation)
>   return 0;
>  }
>  
> -int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
> +int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
>  {
>   int error;
>  
> @@ -812,7 +812,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>   return ret;
>  }
>  
> -int i915_resume_legacy(struct drm_device *dev)
> +int i915_resume_switcheroo(struct drm_device *dev)
>  {
>   int ret;
>  
> @@ -1649,7 +1649,7 @@ static struct drm_driver driver = {
>*/
>   .driver_features =
>   DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
> - DRIVER_RENDER,
> + DRIVER_RENDER | DRIVER_MODESET,
>   .load = i915_driver_load,
>   .unload = i915_driver_unload,
>   .open = i915_driver_open,
> @@ -1658,10 +1658,6 @@ static struct drm_driver driver = {
>   .postclose = i915_driver_postclose,
>   .set_busid = drm_pci_set_busid,
>  
> - /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
> - .suspend = i915_suspend_legacy,
> - .resume = i915_resume_legacy,
> -
>  #if defined(CONFIG_DEBUG_FS)
>   .debugfs_init = i915_debugfs_init,
>   .debugfs_cleanup = i915_debugfs_cleanup,
> @@ -1704,7 +1700,6 @@ static int __init i915_init(void)
>* either the i915.modeset prarameter or by the
>* vga_text_mode_force boot option.
>*/
> - driver.driver_features |= DRIVER_MODESET;
>  
>   if (i915.modeset == 0)
>   driver.driver_features &= ~DRIVER_MODESET;
> @@ -1715,17 +1710,11 @@ static int __init i915_init(void)
>  #endif
>  
>   if (!(driver.driver_features & DRIVER_MODESET)) {
> - driver.get_vblank_timestamp = NULL;
>   /* Silently fail loading to not upset userspace. */
>   DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
>   return 0;
>   }
>  
> - /*
> -  * FIXME: Note that we're lying to the DRM core here so that we can get 
> access
> -  * to the atomic ioctl and the atomic properties.  Only plane 
> operations on
> -  * a single CRTC will actually work.
> -  */
>   if (i915.nuclear_pageflip)
>   driver.driver_features |= DRIVER_ATOMIC;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8c938451a05e..5c2541ddf212 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2607,8 +2607,8 @@ struct drm_i915_cmd_table {
>  extern const struct drm_ioctl_desc i915_ioctls[];
>  extern int i915_max_ioctl;
>  
> -extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
> -extern int i915_resume_legacy(struct drm_device *dev);
> +extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t 
> state);
> +extern int i915_resume_switcheroo(struct drm_device *dev);
>  
>  /* i915_params.c */
>  struct i915_params {
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 00/16] drm/i915: Adding NV12 for skylake display

[Chandra Konduru]

This patch series is adding initial NV12 support for Skylake display
after rebasing on latest drm-intel-nightly. Earlier I had two patch
series one for 0/180 and another for 90/270. Some of the patches
were already merged. This is combined series to support 0/90/180/270
and removing the ones that are already merged.

Feature is tested with igt/kms_nv12 testcases.
Feature is unit tested for linear/X/Y formats in 0, 90, 180, 270
orientations with combinations of 1 or 2 planes enabled along with
scaling. Also negatively tested for enabling NV12 on unsupported
plane.

The last patch in this series depends on Tvrtko's GEM remapping
for NV12 format patch series.

First two patches fixing couple things in dbuf logic to allocate
correct min number of dbuf blocks and use correct source width
and height in 90/270 rotation cases.

Update from last rev:
 Resolved Daniel's review feedback
 - Did one WA per commit
 - Moved get stepping functions better place
 - Added comments

Chandra Konduru (16):
  drm/i915: Allocate min dbuf blocks per bspec
  drm/i915: In DBUF/WM calcs for 90/270, swap w & h
  drm/i915: Add register definitions for NV12 support
  drm/i915: Set scaler mode for NV12
  drm/i915: Stage scaler request for NV12 as src format
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12.
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init
  drm/i915: Add NV12 to primary plane programming.
  drm/i915: Add NV12 to sprite plane programming.
  drm/i915: Set initial phase & trip for NV12 scaler
  drm/i915: skl nv12 wa - disable streamer fix
  drm/i915: skl nv12 wa - NV12 to RGB switch
  drm/i915: Add 90/270 rotation for NV12 format.

 drivers/gpu/drm/i915/i915_reg.h  |   47 +++
 drivers/gpu/drm/i915/intel_atomic.c  |5 +-
 drivers/gpu/drm/i915/intel_csr.c |   29 -
 drivers/gpu/drm/i915/intel_display.c |  226 --
 drivers/gpu/drm/i915/intel_drv.h |6 +-
 drivers/gpu/drm/i915/intel_pm.c  |   71 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  125 +++
 7 files changed, 439 insertions(+), 70 deletions(-)

-- 
1.7.9.5

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[Intel-gfx] [PATCH 02/16] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Chandra Konduru]

This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_pm.c |   32 
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index da3046f..c455946 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3193,6 +3193,8 @@ static void skl_compute_wm_pipe_parameters(struct 
drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
struct drm_plane *plane;
struct drm_framebuffer *fb;
+   struct intel_plane_state *plane_state;
+   int src_w, src_h;
int i = 1; /* Index for sprite planes start */
 
p->active = intel_crtc->active;
@@ -3201,6 +3203,7 @@ static void skl_compute_wm_pipe_parameters(struct 
drm_crtc *crtc,
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
 
fb = crtc->primary->state->fb;
+   plane_state = to_intel_plane_state(crtc->primary->state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p->plane[0].enabled = true;
@@ -3215,8 +3218,22 @@ static void skl_compute_wm_pipe_parameters(struct 
drm_crtc *crtc,
p->plane[0].y_bytes_per_pixel = 0;
p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
-   p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
-   p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+   if (drm_rect_width(&plane_state->src)) {
+   src_w = drm_rect_width(&plane_state->src) >> 16;
+   src_h = drm_rect_height(&plane_state->src) >> 16;
+   } else {
+   src_w = intel_crtc->config->pipe_src_w;
+   src_h = intel_crtc->config->pipe_src_h;
+   }
+
+   if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+   p->plane[0].horiz_pixels = src_h;
+   p->plane[0].vert_pixels = src_w;
+   } else {
+   p->plane[0].horiz_pixels = src_w;
+   p->plane[0].vert_pixels = src_h;
+   }
p->plane[0].rotation = crtc->primary->state->rotation;
 
fb = crtc->cursor->state->fb;
@@ -3750,8 +3767,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct 
drm_crtc *crtc,
 
intel_plane->wm.enabled = enabled;
intel_plane->wm.scaled = scaled;
-   intel_plane->wm.horiz_pixels = sprite_width;
-   intel_plane->wm.vert_pixels = sprite_height;
+
+   if (intel_rotation_90_or_270(plane->state->rotation)) {
+   intel_plane->wm.horiz_pixels = sprite_height;
+   intel_plane->wm.vert_pixels = sprite_width;
+   } else {
+   intel_plane->wm.horiz_pixels = sprite_width;
+   intel_plane->wm.vert_pixels = sprite_height;
+   }
+
intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
 
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
-- 
1.7.9.5

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[Intel-gfx] [PATCH 01/16] drm/i915: Allocate min dbuf blocks per bspec

[Chandra Konduru]

Properly allocate min blocks per hw requirements.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_pm.c |   39 +--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..da3046f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2959,6 +2959,41 @@ skl_get_total_relative_data_rate(struct intel_crtc 
*intel_crtc,
return total_data_rate;
 }
 
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+   uint16_t min_alloc;
+
+   /* For packed formats, no y-plane, return 0 */
+   if (y_plane && !p->y_bytes_per_pixel)
+   return 0;
+
+
+   if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+   p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+   uint32_t min_scanlines = 8;
+   uint8_t bytes_per_pixel =
+   y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+   switch (bytes_per_pixel) {
+   case 1:
+   min_scanlines = 32;
+   break;
+   case 2:
+   min_scanlines = 16;
+   break;
+   case 8:
+   WARN(1, "Unsupported pixel depth for rotation");
+   }
+   min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2) 
*
+   bytes_per_pixel), 512) * min_scanlines/4 + 3;
+   } else {
+   min_alloc = 8;
+   }
+
+   return min_alloc;
+}
+
 static void
 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
  const struct intel_wm_config *config,
@@ -2999,9 +3034,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p->enabled)
continue;
 
-   minimum[plane] = 8;
+   minimum[plane] = skl_dbuf_min_alloc(p, 0);/* 
uv-plane/packed */
alloc_size -= minimum[plane];
-   y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+   y_minimum[plane] = skl_dbuf_min_alloc(p, 1);  /* y-plane */
alloc_size -= y_minimum[plane];
}
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 05/16] drm/i915: Stage scaler request for NV12 as src format

[Chandra Konduru]

This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.

v2:
-Added helper function for need_scaling (Ville)

v3:
-Rebased to current kernel version 4.2.0.rc4 (me)

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_display.c |   30 --
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3ee1c17..411b211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4341,10 +4341,27 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
}
 }
 
+static int skl_need_scaling(int src_w, int dst_w, int src_h, int dst_h,
+   int rotation, uint32_t pixel_format)
+{
+   /* scaling is required when src dst sizes doesn't match or format is 
NV12 */
+   if (src_w != dst_w || src_h != dst_h)
+   return 1;
+
+   if (intel_rotation_90_or_270(rotation) &&
+   (src_h != dst_w || src_w != dst_h))
+   return 1;
+
+   if (pixel_format == DRM_FORMAT_NV12)
+   return 1;
+
+   return 0;
+}
+
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t 
pixel_format)
 {
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -4352,9 +4369,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
to_intel_crtc(crtc_state->base.crtc);
int need_scaling;
 
-   need_scaling = intel_rotation_90_or_270(rotation) ?
-   (src_h != dst_w || src_w != dst_h):
-   (src_w != dst_w || src_h != dst_h);
+   need_scaling = skl_need_scaling(src_w, dst_w, src_h, dst_h, rotation,
+   pixel_format);
 
/*
 * if plane is being disabled or scaler is no more required or force 
detach
@@ -4423,7 +4439,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
&state->scaler_state.scaler_id, DRM_ROTATE_0,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->hdisplay, adjusted_mode->vdisplay);
+   adjusted_mode->hdisplay, adjusted_mode->vdisplay, 0);
 }
 
 /**
@@ -4459,7 +4475,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(&plane_state->src) >> 16,
drm_rect_height(&plane_state->src) >> 16,
drm_rect_width(&plane_state->dst),
-   drm_rect_height(&plane_state->dst));
+   drm_rect_height(&plane_state->dst),
+   fb ? fb->pixel_format : 0);
 
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4484,6 +4501,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 
0x%x\n",
-- 
1.7.9.5

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[Intel-gfx] [PATCH 06/16] drm/i915: Update format_is_yuv() to include NV12

[Chandra Konduru]

This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_drv.h|1 +
 drivers/gpu/drm/i915/intel_sprite.c |9 +
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f44941b..18632a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, 
void *data,
 void intel_pipe_update_start(struct intel_crtc *crtc,
 uint32_t *start_vbl_count);
 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+bool intel_format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index c13c529..8b73bb8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,14 +39,15 @@
 #include 
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool
+intel_format_is_yuv(uint32_t format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -293,7 +294,7 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t 
format)
int plane = intel_plane->plane;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
 
/*
@@ -857,7 +858,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
 
-   if (format_is_yuv(fb->pixel_format)) {
+   if (intel_format_is_yuv(fb->pixel_format)) {
src_x &= ~1;
src_w &= ~1;
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 07/16] drm/i915: Upscale scaler max scale for NV12.

[Chandra Konduru]

This patch updates max supported scaler limits for NV12.

v2:
-Rebased to current kernel version 4.2.0.rc4 (me)

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_display.c |   13 +
 drivers/gpu/drm/i915/intel_drv.h |3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |2 +-
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 411b211..b1d9edf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13421,7 +13421,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+   struct intel_crtc_state *crtc_state,
+   uint32_t pixel_format)
 {
int max_scale;
struct drm_device *dev;
@@ -13441,11 +13443,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct 
intel_crtc_state *crtc_state
 
/*
 * skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+*  -1 is for that purpose
 *or
 *cdclk/crtc_clock
 */
-   max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / 
crtc_clock));
+   max_scale = min((1 << 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) - 
1,
+   (1 << 8) * ((cdclk << 8) / crtc_clock));
 
return max_scale;
 }
@@ -13465,7 +13469,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(plane->dev)->gen >= 9 &&
state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
-   max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+   max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state,
+   fb ? fb->pixel_format : 0);
can_position = true;
}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18632a4..d50b8cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1140,7 +1140,8 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc 
*crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state 
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+   uint32_t pixel_format);
 
 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
 struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b73bb8..66d60ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -780,7 +780,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
-   max_scale = skl_max_scale(intel_crtc, crtc_state);
+   max_scale = skl_max_scale(intel_crtc, crtc_state, 
fb->pixel_format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
-- 
1.7.9.5

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[Intel-gfx] [PATCH 14/16] drm/i915: skl nv12 wa - disable streamer fix

[Chandra Konduru]

When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1

v2:
-one wa per commit with comments, and function headers (Daniel)

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/i915_reg.h  |   12 
 drivers/gpu/drm/i915/intel_csr.c |   29 --
 drivers/gpu/drm/i915/intel_display.c |   54 ++
 drivers/gpu/drm/i915/intel_drv.h |2 ++
 drivers/gpu/drm/i915/intel_sprite.c  |   11 +++
 5 files changed, 79 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4d732f..84c5db6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,18 @@ enum skl_disp_power_wells {
 #define PLANE_NV12_BUF_CFG(pipe, plane)\
_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
 
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A  0x420B0
+#define _CHICKEN_PIPESL_B  0x420B4
+#define _CHICKEN_PIPESL_C  0x420B8
+#define  DISABLE_STREAMER_FIX  (1 << 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1 0x46430
+#define IDLE_WAKEMEM_MASK  (1 << 13)
+
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A 0x7017c
 #define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..9577727 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -170,35 +170,6 @@ struct intel_dmc_header {
uint32_t reserved1[2];
 } __packed;
 
-struct stepping_info {
-   char stepping;
-   char substepping;
-};
-
-static const struct stepping_info skl_stepping_info[] = {
-   {'A', '0'}, {'B', '0'}, {'C', '0'},
-   {'D', '0'}, {'E', '0'}, {'F', '0'},
-   {'G', '0'}, {'H', '0'}, {'I', '0'}
-};
-
-static char intel_get_stepping(struct drm_device *dev)
-{
-   if (IS_SKYLAKE(dev) && (dev->pdev->revision <
-   ARRAY_SIZE(skl_stepping_info)))
-   return skl_stepping_info[dev->pdev->revision].stepping;
-   else
-   return -ENODATA;
-}
-
-static char intel_get_substepping(struct drm_device *dev)
-{
-   if (IS_SKYLAKE(dev) && (dev->pdev->revision <
-   ARRAY_SIZE(skl_stepping_info)))
-   return skl_stepping_info[dev->pdev->revision].substepping;
-   else
-   return -ENODATA;
-}
-
 /**
  * intel_csr_load_status_get() - to get firmware loading status.
  * @dev_priv: i915 device.
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 419660d..35e9f89 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -92,6 +92,19 @@ static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
 };
 
+/* stepping info */
+struct stepping_info {
+   char stepping;
+   char substepping;
+};
+
+/* skl stepping info */
+static const struct stepping_info skl_stepping_info[] = {
+   {'A', '0'}, {'B', '0'}, {'C', '0'},
+   {'D', '0'}, {'E', '0'}, {'F', '0'},
+   {'G', '0'}, {'H', '0'}, {'I', '0'},
+};
+
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
@@ -138,6 +151,36 @@ struct intel_limit {
intel_p2_t  p2;
 };
 
+/**
+ * intel_get_stepping() - get stepping info
+ * @dev: drm device.
+ *
+ * Returns stepping id 'A', 'B', 'C', etc.
+ */
+char intel_get_stepping(struct drm_device *dev)
+{
+   if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+   ARRAY_SIZE(skl_stepping_info)))
+   return skl_stepping_info[dev->pdev->revision].stepping;
+   else
+   return -ENODATA;
+}
+
+/**
+ * intel_get_substepping() - get substepping info
+ * @dev: drm device.
+ *
+ * Returns substepping id '0', '1', '2', etc.
+ */
+char intel_get_substepping(struct drm_device *dev)
+{
+   if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+   ARRAY_SIZE(skl_stepping_info)))
+   return skl_stepping_info[dev->pdev->revision].substepping;
+   else
+   return -ENODATA;
+}
+
 int
 intel_pch_rawclk(struct drm_device *dev)
 {
@@ -3196,6 +3239,17 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | 
aux_x_offset);
 
+   /*
+* Per bspec, for SKL C and BXT A steppings, when the plane source pixel
+* format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1
+*/
+   if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') ||
+   (IS_BROXTON(dev) && intel_get_steppin

[Intel-gfx] [PATCH 03/16] drm/i915: Add register definitions for NV12 support

[Chandra Konduru]

This patch adds register definitions for skylake
display NV12 support.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/i915_reg.h |   27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa0554..c4d732f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) ((plane + 1) << 25)
 #define PS_FILTER_MASK (3 << 23)
@@ -5601,6 +5602,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
 
+
+/*
+ * Skylake  NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+   _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A   0x701c4
+#define PLANE_AUX_OFFSET_2_A   0x702c4
+#define PLANE_AUX_OFFSET_1_B   0x711c4
+#define PLANE_AUX_OFFSET_2_B   0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe)  \
+   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe)  \
+   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane)  \
+   _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
 /* legacy palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
-- 
1.7.9.5

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[Intel-gfx] [PATCH 12/16] drm/i915: Add NV12 to sprite plane programming.

[Chandra Konduru]

This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.

For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_sprite.c |   31 +--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 4e8c020..a1384a7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,6 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
int scaler_id;
+   u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+   u32 tile_row_adjustment = 0;
 
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -234,24 +236,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
plane_size = (src_w << 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+   /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
plane_size = (src_h << 16) | src_w;
x_offset = x;
y_offset = y;
+   tile_height = PAGE_SIZE / stride_div;
+
+   if (fb->pixel_format == DRM_FORMAT_NV12) {
+   int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+   /*
+* If UV starts from middle of a page, then UV start 
should
+* be programmed to beginning of that page. And offset 
into that
+* page to be programmed into y-offset
+*/
+   tile_row_adjustment = height_in_mem % tile_height;
+   aux_dist = fb->pitches[0] * (height_in_mem - 
tile_row_adjustment);
+   aux_x_offset = DIV_ROUND_UP(x, 2);
+   aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+   /* For tile-Yf, uv-subplane tile width is 2x of 
Y-subplane */
+   aux_stride = fb->modifier[0] == 
I915_FORMAT_MOD_Yf_TILED ?
+   stride / 2 : stride;
+   }
}
plane_offset = y_offset << 16 | x_offset;
 
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+   I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+   I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 | 
aux_x_offset);
 
/* program plane scaler */
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
 
-   DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
-   PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -262,6 +288,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
 
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+   WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
}
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 04/16] drm/i915: Set scaler mode for NV12

[Chandra Konduru]

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_atomic.c |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 9336e80..fd3972c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
 
/* set scaler mode */
-   if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
+   if (plane_state && plane_state->base.fb &&
+   plane_state->base.fb->pixel_format == DRM_FORMAT_NV12) {
+   scaler_state->scalers[*scaler_id].mode = 
PS_SCALER_MODE_NV12;
+   } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
 * when only 1 scaler is in use on either pipe A or B,
 * scaler 0 operates in high quality (HQ) mode.
-- 
1.7.9.5

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[Intel-gfx] [PATCH 09/16] drm/i915: Add NV12 as supported format for sprite plane

[Chandra Konduru]

This patch adds NV12 to list of supported formats for
sprite plane.

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_sprite.c |   23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 66d60ae..4e8c020 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1041,6 +1041,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
 };
 
+static uint32_t skl_plane_formats_with_nv12[] = {
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_YUYV,
+   DRM_FORMAT_YVYU,
+   DRM_FORMAT_UYVY,
+   DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
+};
+
 int
 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 {
@@ -1112,8 +1125,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, 
int plane)
intel_plane->disable_plane = skl_disable_plane;
state->scaler_id = -1;
 
-   plane_formats = skl_plane_formats;
-   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+   if ((pipe == PIPE_A || pipe == PIPE_B) && (plane == 0)) {
+   plane_formats = skl_plane_formats_with_nv12;
+   num_plane_formats = 
ARRAY_SIZE(skl_plane_formats_with_nv12);
+   } else {
+   plane_formats = skl_plane_formats;
+   num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+   }
+
break;
default:
kfree(intel_plane);
-- 
1.7.9.5

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[Intel-gfx] [PATCH 16/16] drm/i915: Add 90/270 rotation for NV12 format.

[Chandra Konduru]

Adding NV12 90/270 rotation support for primary and sprite planes.

v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)

v3:
-Rebased (me)

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   28 +++--
 drivers/gpu/drm/i915/intel_sprite.c  |   56 ++
 2 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e8fb15b..8602432 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3139,7 +3139,8 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
-   u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+   unsigned long aux_dist = 0;
+   u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
 
@@ -3198,12 +3199,16 @@ static void skylake_update_primary_plane(struct 
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
-   /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+   if (fb->pixel_format == DRM_FORMAT_NV12) {
+   u32 uv_tile_height = intel_tile_height(dev, 
fb->pixel_format,
+   fb->modifier[0], 1);
+   aux_stride = DIV_ROUND_UP(fb->height / 2, 
uv_tile_height);
+   aux_dist = 
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+   surf_addr;
+   aux_x_offset = aux_stride * uv_tile_height - y / 2 - 
fb->height / 2;
+   aux_y_offset = x / 2;
+   }
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
@@ -11745,8 +11750,13 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
 
/* Adjust (macro)pixel boundary */
if (fb && intel_format_is_yuv(fb->pixel_format)) {
-   to_intel_plane_state(plane_state)->src.x1 &= ~0x1;
-   to_intel_plane_state(plane_state)->src.x2 &= ~0x1;
+   if (intel_rotation_90_or_270(plane_state->rotation)) {
+   to_intel_plane_state(plane_state)->src.y1 &= ~0x1;
+   to_intel_plane_state(plane_state)->src.y2 &= ~0x1;
+   } else {
+   to_intel_plane_state(plane_state)->src.x1 &= ~0x1;
+   to_intel_plane_state(plane_state)->src.x2 &= ~0x1;
+   }
}
 
if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index b2346b0..7602be0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
int scaler_id;
-   u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+   unsigned long aux_dist = 0;
+   u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
 
@@ -238,12 +239,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
 
-   /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+   if (fb->pixel_format == DRM_FORMAT_NV12) {
+   u32 uv_tile_height = intel_tile_height(dev, 
fb->pixel_format,
+   fb->modifier[0], 1);
+   aux_stride = DIV_ROUND_UP(fb->height / 2, 
uv_tile_height);
+   aux_dist = intel_plane_obj_offset(intel_plane, obj, 1) 
- surf_addr;
+   aux_x_offset = aux_stride * uv_tile_height - y / 2 - 
fb->height / 2;
+   aux_y_offset = x / 2;
+   }
} else {
stride =

[Intel-gfx] [PATCH 13/16] drm/i915: Set initial phase & trip for NV12 scaler

[Chandra Konduru]

This patch sets default initial phase and trip to scale NV12
content. In future, if needed these can be set via properties
or other means depending on incoming stream request. Until then
defaults are fine.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/intel_display.c |7 +++
 drivers/gpu/drm/i915/intel_sprite.c  |7 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 329651e..419660d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
int scaler_id = -1;
u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
+   u32 hphase = 0, vphase = 0;
 
plane_state = to_intel_plane_state(plane->state);
 
@@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
/* For tile-Yf, uv-subplane tile width is 2x of 
Y-subplane */
aux_stride = fb->modifier[0] == 
I915_FORMAT_MOD_Yf_TILED ?
stride / 2 : stride;
+
+   hphase = 0x00010001;  /* use trip for both Y and UV */
+   vphase = 0x00012000;  /* use trip for Y and phase 0.5 
for UV */
}
}
plane_offset = y_offset << 16 | x_offset;
@@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
 
+   I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase);
+   I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase);
+
I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
 
POSTING_READ(PLANE_SURF(pipe, 0));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index a1384a7..0ea9273 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
int scaler_id;
u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
+   u32 hphase = 0, vphase = 0;
 
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
/* For tile-Yf, uv-subplane tile width is 2x of 
Y-subplane */
aux_stride = fb->modifier[0] == 
I915_FORMAT_MOD_Yf_TILED ?
stride / 2 : stride;
+
+   hphase = 0x00010001;  /* use trip for both Y and UV */
+   vphase = 0x00012000;  /* use trip for Y and phase 0.5 
for UV */
}
}
plane_offset = y_offset << 16 | x_offset;
@@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct 
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
}
 
+   I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase);
+   I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase);
+
I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
POSTING_READ(PLANE_SURF(pipe, plane));
-- 
1.7.9.5

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[Intel-gfx] [PATCH 08/16] drm/i915: Add NV12 as supported format for primary plane

[Chandra Konduru]

This patch adds NV12 to list of supported formats for
primary plane.

v2:
-Rebased (me)

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b1d9edf..e4a6a91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -74,6 +74,19 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
 };
 
+/* Primary plane formats for gen >= 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+   DRM_FORMAT_C8,
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_XRGB2101010,
+   DRM_FORMAT_XBGR2101010,
+   DRM_FORMAT_NV12,
+};
+
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13606,8 +13619,13 @@ static struct drm_plane 
*intel_primary_plane_create(struct drm_device *dev,
primary->plane = !pipe;
 
if (INTEL_INFO(dev)->gen >= 9) {
-   intel_primary_formats = skl_primary_formats;
-   num_formats = ARRAY_SIZE(skl_primary_formats);
+   if (pipe == PIPE_A || pipe == PIPE_B) {
+   intel_primary_formats = skl_primary_formats_with_nv12;
+   num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+   } else {
+   intel_primary_formats = skl_primary_formats;
+   num_formats = ARRAY_SIZE(skl_primary_formats);
+   }
} else if (INTEL_INFO(dev)->gen >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
-- 
1.7.9.5

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[Intel-gfx] [PATCH 11/16] drm/i915: Add NV12 to primary plane programming.

[Chandra Konduru]

This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.

For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.

v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)

v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)

v4:
-Rebased to current kernel version 4.2.0.rc4 (me)

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   37 ++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 4df4d77..329651e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+   u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+   u32 tile_row_adjustment = 0;
 
plane_state = to_intel_plane_state(plane->state);
 
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct 
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
+   /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) << 16 | (src_w - 1);
+   tile_height = PAGE_SIZE / stride_div;
+
+   if (fb->pixel_format == DRM_FORMAT_NV12) {
+   int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+   /*
+* If UV starts from middle of a page, then UV start 
should
+* be programmed to beginning of that page. And offset 
into that
+* page to be programmed into y-offset
+*/
+   tile_row_adjustment = height_in_mem % tile_height;
+   aux_dist = fb->pitches[0] * (height_in_mem - 
tile_row_adjustment);
+   aux_x_offset = DIV_ROUND_UP(x, 2);
+   aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+   /* For tile-Yf, uv-subplane tile width is 2x of 
Y-subplane */
+   aux_stride = fb->modifier[0] == 
I915_FORMAT_MOD_Yf_TILED ?
+   stride / 2 : stride;
+   }
}
plane_offset = y_offset << 16 | x_offset;
 
@@ -3162,11 +3189,14 @@ static void skylake_update_primary_plane(struct 
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+   I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+   I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | 
aux_x_offset);
 
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
 
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3175,6 +3205,7 @@ static void skylake_update_primary_plane(struct drm_crtc 
*crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | 
dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+   WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
 
@@ -11626,6 +11657,12 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
bool turn_off, turn_on, visible, was_visible;
struct drm_framebuffer *fb = plane_state->fb;
 
+   /* Adjust (macro)pixel boundary */
+

[Intel-gfx] [PATCH 15/16] drm/i915: skl nv12 wa - NV12 to RGB switch

[Chandra Konduru]

Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.

Signed-off-by: Chandra Konduru 
---
 drivers/gpu/drm/i915/i915_reg.h  |8 
 drivers/gpu/drm/i915/intel_display.c |   25 +
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c5db6..3192837 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@ enum skl_disp_power_wells {
 #define CHICKEN_DCPR_1 0x46430
 #define IDLE_WAKEMEM_MASK  (1 << 13)
 
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 << 15)
+#define DUPS2_GATING_DIS (1 << 19)
+#define DUPS3_GATING_DIS (1 << 23)
+#define CLKGATE_DIS_PSL(pipe)  _PIPE(pipe, CLKGATE_DIS_PSL_A, 
CLKGATE_DIS_PSL_B)
+
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A 0x7017c
 #define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 35e9f89..e8fb15b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5058,6 +5058,25 @@ static bool hsw_crtc_supports_ips(struct intel_crtc 
*crtc)
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
 
+/*
+ * Switching format from NV12 to RGB can result in display underrun
+ * and corruption. Workaround is to set bits 15 & 19 to 1 in
+ * CLKGATE_DIS_PSL register.
+ */
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+   int pipe, int enable)
+{
+   if (pipe == PIPE_A || pipe == PIPE_B) {
+   if (enable)
+   I915_WRITE(CLKGATE_DIS_PSL(pipe),
+   DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+   else
+   I915_WRITE(CLKGATE_DIS_PSL(pipe),
+   I915_READ(CLKGATE_DIS_PSL(pipe) &
+   ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+   }
+}
+
 static void haswell_crtc_enable(struct drm_crtc *crtc)
 {
struct drm_device *dev = crtc->dev;
@@ -5148,6 +5167,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
+
+   /* workaround for NV12 */
+   skl_wa_clkgate(dev_priv, pipe, 1);
 }
 
 static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5265,6 +5287,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
intel_crtc->active = false;
intel_update_watermarks(crtc);
+
+   /* workaround for NV12 */
+   skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
 }
 
 static void i9xx_pfit_enable(struct intel_crtc *crtc)
-- 
1.7.9.5

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[Intel-gfx] [PATCH 10/16] drm/i915: Add NV12 support to intel_framebuffer_init

[Chandra Konduru]

This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (me)

Signed-off-by: Chandra Konduru 
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e4a6a91..4df4d77 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14343,6 +14343,34 @@ static int intel_framebuffer_init(struct drm_device 
*dev,
return -EINVAL;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_INFO(dev)->gen < 9) {
+   DRM_DEBUG("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format));
+   return -EINVAL;
+   }
+   if (!mode_cmd->offsets[1]) {
+   DRM_DEBUG("uv start offset not set\n");
+   return -EINVAL;
+   }
+   if (mode_cmd->pitches[0] != mode_cmd->pitches[1] ||
+   mode_cmd->handles[0] != mode_cmd->handles[1]) {
+   DRM_DEBUG("y and uv subplanes have different 
parameters\n");
+   return -EINVAL;
+   }
+   if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
+   (mode_cmd->offsets[1] & 0xFFF)) {
+   DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new 
tile-row\n",
+   mode_cmd->offsets[1]);
+   return -EINVAL;
+   }
+   if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
+   ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) {
+   DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line 
aligned\n",
+   mode_cmd->offsets[1]);
+   return -EINVAL;
+   }
+   break;
default:
DRM_DEBUG("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format));
-- 
1.7.9.5

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Re: [Intel-gfx] [RFC 1/3] drm/i915: Roll intel_crtc->atomic into intel_crtc_state

[Maarten Lankhorst]

Op 29-08-15 om 01:57 schreef Matt Roper:
> Way back at the beginning of i915's atomic conversion I added
> intel_crtc->atomic as a temporary dumping ground for "stuff to do
> outside vblank evasion" flags since CRTC states weren't properly wired
> up and tracked at that time.  We've had proper CRTC state tracking for a
> while now, so there's really no reason for this hack to continue to
> exist.  Moving forward we want to store intermediate crtc/plane state
> data for modesets in addition to the final state, so moving these fields
> into the proper state object allows us to properly compute them for both
> the intermediate and final state.
>
> Signed-off-by: Matt Roper 
> ---
Can I shoot this patch down? It's better to add a field 'wm_changed' to the 
crtc_state,
which gets reset to false for each crtc_state duplication. It's needed for 
checking if a cs pageflip
can be done for atomic. It would remove the duplication of some checks there.

The other atomic state members will die soon. I already have some patches to 
achieve that. :)

I'm not sure if an intermediate state is a good idea. Any code that disables a 
crtc should only be
looking at the old state. pre_plane_update runs all stuff in preparation for 
disabling planes,
while post_plane_update runs everything needed for enabling planes. So no need 
to split it up
I think, maybe put in some intermediate watermarks in intel_atomic_state, but 
no need for a full
crtc_state.

After a modeset disable you should be able to put in any wm value in 
.crtc_enable because no plane
will be active.
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Re: [Intel-gfx] [PATCH 10/13] drm/i915: Calculate watermark configuration during atomic check

[Maarten Lankhorst]

Op 28-08-15 om 15:42 schreef Ander Conselvan De Oliveira:
> On Thu, 2015-08-20 at 18:12 -0700, Matt Roper wrote:
>> Signed-off-by: Matt Roper 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h  | 10 ++
>>  drivers/gpu/drm/i915/intel_display.c | 51 ++--
>>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>>  drivers/gpu/drm/i915/intel_pm.c  | 66 
>> +++-
>>  4 files changed, 71 insertions(+), 57 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index c91bab9..ac13cd7 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1686,6 +1686,13 @@ struct i915_execbuffer_params {
>>  struct drm_i915_gem_request *request;
>>  };
>>  
>> +/* used in computing the new watermarks state */
>> +struct intel_wm_config {
>> +unsigned int num_pipes_active;
>> +bool sprites_enabled;
>> +bool sprites_scaled;
>> +};
>> +
>>  struct drm_i915_private {
>>  struct drm_device *dev;
>>  struct kmem_cache *objects;
>> @@ -1903,6 +1910,9 @@ struct drm_i915_private {
>>   */
>>  uint16_t skl_latency[8];
>>  
>> +/* Committed wm config */
>> +struct intel_wm_config config;
>> +
>>  /*
>>   * The skl_wm_values structure is a bit too big for stack
>>   * allocation, so we keep the staging struct where we store
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index c40f025..8e9d87a 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -13005,6 +13005,44 @@ static int intel_modeset_checks(struct 
>> drm_atomic_state *state)
>>  return 0;
>>  }
>>  
>> +/*
>> + * Handle calculation of various watermark data at the end of the atomic 
>> check
>> + * phase.  The code here should be run after the per-crtc and per-plane 
>> 'check'
>> + * handlers to ensure that all derived state has been updated.
>> + */
>> +static void calc_watermark_data(struct drm_atomic_state *state)
>> +{
>> +struct drm_device *dev = state->dev;
>> +struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>> +struct drm_crtc *crtc;
>> +struct drm_crtc_state *cstate;
>> +struct drm_plane *plane;
>> +struct drm_plane_state *pstate;
>> +
>> +/*
>> + * Calculate watermark configuration details now that derived
>> + * plane/crtc state is all properly updated.
>> + */
>> +drm_for_each_crtc(crtc, dev) {
>> +cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
>> +crtc->state;
>> +
> Did you intend to check crtc->active here?
>
>> +intel_state->wm_config.num_pipes_active++;
>> +}
>> +drm_for_each_legacy_plane(plane, dev) {
>> +pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
>> +plane->state;
>> +
>> +if (!to_intel_plane_state(pstate)->visible)
>> +continue;
> If I understand correctly, it is possible for a plane on an inactive crtc to 
> have visible = true. In
> that case, the result here would be different than the function this 
> replaces, which counts only
> planes on active crtcs.
>
Now that i915's atomic visibility is updated correctly in almost all cases 
except initial readout perhaps. :-)

~Maarten
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Re: [Intel-gfx] [PATCH v2 12/22] drm/i915: Preserve SSC earlier

[Jani Nikula]

On Mon, 31 Aug 2015, Jesse Barnes  wrote:
> On 07/15/2015 04:57 AM, Lukas Wunner wrote:
>> Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
>> added code to intel_modeset_gem_init to override the SSC status read
>> from VBT with the SSC status set by BIOS.
>> 
>> However, intel_modeset_gem_init is invoked *after* intel_modeset_init,
>> which calls intel_setup_outputs, which *modifies* SSC status by way of
>> intel_init_pch_refclk. So unlike advertised, intel_modeset_gem_init
>> doesn't preserve the SSC status set by BIOS but whatever
>> intel_init_pch_refclk decided on.
>> 
>> This is a problem on dual gpu laptops such as the MacBook Pro which
>> require either a handler to switch DDC lines, or the discrete gpu
>> to proxy DDC/AUX communication: Both the handler and the discrete
>> gpu may initialize after the i915 driver, and consequently, an LVDS
>> connector may initially seem disconnected and the SSC therefore
>> is disabled by intel_init_pch_refclk, but on reprobe the connector
>> may turn out to be connected and the SSC must then be enabled.
>> 
>> Due to 92122789b2d6 however, the SSC is not enabled on reprobe since
>> it is assumed BIOS disabled it while in fact it was disabled by
>> intel_init_pch_refclk.
>> 
>> Also, because the SSC status is preserved so late, the preserved value
>> only ever gets used on resume but not on panel initialization:
>> intel_modeset_init calls intel_init_display which indirectly calls
>> intel_panel_use_ssc via multiple subroutines, *before* the BIOS value
>> overrides the VBT value in intel_modeset_gem_init (intel_panel_use_ssc
>> is the sole user of dev_priv->vbt.lvds_use_ssc).
>> 
>> Fix this by moving the code introduced by 92122789b2d6 from
>> intel_modeset_gem_init to intel_modeset_init before the invocation
>> of intel_setup_outputs and intel_init_display.
>> 
>> Add a DRM_DEBUG_KMS as suggested way back by Jani:
>> http://lists.freedesktop.org/archives/intel-gfx/2014-June/04.html
>> 
>> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=88861
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61115
>> Tested-by: Paul Hordiienko 
>> [MBP  6,2 2010  intel ILK + nvidia GT216  pre-retina]
>> Tested-by: William Brown 
>> [MBP  8,2 2011  intel SNB + amd turks pre-retina]
>> Tested-by: Lukas Wunner 
>> [MBP  9,1 2012  intel IVB + nvidia GK107  pre-retina]
>> Tested-by: Bruno Bierbaumer 
>> [MBP 11,3 2013  intel HSW + nvidia GK107  retina -- work in progress]
>> 
>> Fixes: 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
>> Signed-off-by: Lukas Wunner 
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 29 ++---
>>  1 file changed, 18 insertions(+), 11 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index af0bcfe..6335883 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -14893,6 +14893,24 @@ void intel_modeset_init(struct drm_device *dev)
>>  if (INTEL_INFO(dev)->num_pipes == 0)
>>  return;
>>  
>> +/*
>> + * There may be no VBT; and if the BIOS enabled SSC we can
>> + * just keep using it to avoid unnecessary flicker.  Whereas if the
>> + * BIOS isn't using it, don't assume it will work even if the VBT
>> + * indicates as much.
>> + */
>> +if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
>> +bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
>> +DREF_SSC1_ENABLE);
>> +
>> +if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
>> +DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT 
>> which says %sabled\n",
>> + bios_lvds_use_ssc ? "en" : "dis",
>> + dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
>> +dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
>> +}
>> +}
>> +
>>  intel_init_display(dev);
>>  intel_init_audio(dev);
>>  
>> @@ -15446,7 +15464,6 @@ err:
>>  
>>  void intel_modeset_gem_init(struct drm_device *dev)
>>  {
>> -struct drm_i915_private *dev_priv = dev->dev_private;
>>  struct drm_crtc *c;
>>  struct drm_i915_gem_object *obj;
>>  int ret;
>> @@ -15455,16 +15472,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
>>  intel_init_gt_powersave(dev);
>>  mutex_unlock(&dev->struct_mutex);
>>  
>> -/*
>> - * There may be no VBT; and if the BIOS enabled SSC we can
>> - * just keep using it to avoid unnecessary flicker.  Whereas if the
>> - * BIOS isn't using it, don't assume it will work even if the VBT
>> - * indicates as much.
>> - */
>> -if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>> -dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
>> -DREF_SSC1_ENABLE);
>> -
>>  intel_modeset_init_hw(dev);
>>  

Re: [Intel-gfx] [PATCH v2 00/22] Enable gpu switching on the MacBook Pro

[Jani Nikula]

On Mon, 31 Aug 2015, Jani Nikula  wrote:
> On Sat, 29 Aug 2015, Lukas Wunner  wrote:
>> Hi Daniel, Hi Jani,
>>
>> the patch set I've posted August 12 included 3 commits which fix bugs
>> in i915. These bugs should be fixed independently of MacBook Pro GPU
>> switching, please consider merging them:
>>
>> drm/i915: Preserve SSC earlier
>> http://patchwork.freedesktop.org/patch/56921/

Pushed this one.

Jani.

>>
>> drm/i915: Fix failure paths around initial fbdev allocation
>> http://patchwork.freedesktop.org/patch/53673/
>> drm/i915: On fb alloc failure, unref gem object where it gets refed
>> http://patchwork.freedesktop.org/patch/53674/
>>
>> The latter two commits relate to a bug Jani was tracking before his
>> holidays which has unfortunately fallen by the wayside.
>
> Sorry about that. Unfortunately the target is moving fast, and they no
> longer apply. Please resend on top of current nightly.
>
> BR,
> Jani.
>
>
>>
>> Thanks,
>>
>> Lukas
>
> -- 
> Jani Nikula, Intel Open Source Technology Center

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Re: [Intel-gfx] Request Linux Graphic Driver for Intel GMA 3150

[Jani Nikula]

On Sat, 22 Aug 2015, David Ho  wrote:
> REQUEST
>
> May I please request support for driver of Intel GMA 3150 for Ubuntu 14.04.3
> 32 bit (Trusty Tahr)?
>
> I installed "Intel Graphic Installer for Linux" from 01.org, but it stops at
> the very first step saying "Distribution not supported".

Rodrigo (Cc'd) knows this stuff better, but I don't think it's likely
old (from upstream POV) distros will be supported. In that regard,
you're probably better off asking help from your distro vendor.

> BACKGROUND
>
> After fresh install of 14.04, the mouse pointer is not showing up and the
> display change (when scrolling, moving between windows, etc) is very slow
> (even only for regular application, never tried to watch video yet). I
> concluded that this is the driver issue.

Does it work on a newer Ubuntu install? Or can you try a new kernel? If
you can reproduce this on a new kernel, please file a bug at [1].

BR,
Jani.



[1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel


>
> I must install it for around 20 PCs.
>
> Please help me to get the correct driver.
>
>  
>
> Thank you.
>
>  
>
> Regards,
>
> David Ho
>
>  
>
>  
>
> -Original Message-
> From: Chacn Limn, DanielX [mailto:danielx.chacn.l...@intel.com] 
> Sent: 21 Agustus 2015 22:05
> To: hupernikao...@gmail.com
> Cc: Becerra Ruiz, Lilia; Flores Perez, Jimena; Diaz, Victor H
> Subject: RE: [Contact] Intel GMA 3150 for Ubuntu 14.04.3Trusty Tahr 32bit
>
>  
>
> Hi David,
>
> Thank you for contacting us.
>
>  
>
> For help or more information about Linux Graphics drivers please contact the
> Team in charge through their mailing list:
>
>   intel-gfx@lists.freedesktop.org
>
>  
>
> Regards,
>
> Daniel.
>
>  
>
> [.MESSAGES TRUNCATED]
>
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