[Intel-gfx] [Regression report] Weekly regression report WW2
WW2 Regression Report Last week regressions +---+---+++ | BugId | Summary | Created on | Bisect | +---+---+++ | 93608 | bisected: i915 SNB modeset crash in ac9b82365 | 2016-01-06 | Yes| | 93640 | [BAT SKL regression] Fifo underruns since CI_ | 2016-01-08 | No | +---+---+++ Previous Regressions +---+---+++ | BugId | Summary | Created on | Bisect | +---+---+++ | 72782 | [945GM bisected] screen blank on S3 resume on | 2013-12-17 | Yes| | 81537 | [snb dp regression] dp retry forever due to s | 2014-07-19 | No | | 84855 | [ILK regression]igt kms_rotation_crc/sprite-r | 2014-10-10 | No | | 84974 | [VLV eDP-LVDS bisected] powerdomains: Screen | 2014-10-14 | Yes| | 87131 | [PNV regression] igt/gem_exec_lut_handle take | 2014-12-09 | No | | 87662 | [ALL 3.18 Bisected] DVI --rotation inverted c | 2014-12-24 | Yes| | 87725 | [BDW Bisected] OglBatch7 performance reduced | 2014-12-26 | Yes| | 87726 | [BDW Bisected] OglDrvCtx performance reduced | 2014-12-26 | Yes| | 88124 | i915: regression: after DP connected monitor | 2015-01-06 | No | | 88439 | [BDW Bisected]igt/gem_reloc_vs_gpu/forked-fau | 2015-01-15 | Yes| | 89334 | [945 regression] 4.0-rc1 kernel GPU hang: ec | 2015-02-26 | No | | 89629 | [i965 regression]igt/kms_rotation_crc/sprite- | 2015-03-18 | No | | 89632 | [i965 regression]igt/kms_universal_plane/univ | 2015-03-18 | No | | 89728 | [HSW/BDW/BSW/BYT bisected] igt / pm_rps / res | 2015-03-23 | Yes| | 89872 | [ HSW Bisected ] VGA was white screen when re | 2015-04-02 | Yes| | 90112 | [BSW bisected] OglGSCloth/Lightsmark/CS/ Port | 2015-04-20 | Yes| | 90134 | [BSW Bisected]GFXBench3_gl_driver/GFXBench3_g | 2015-04-22 | Yes| | 90368 | [SNB BSW SKL] bisected igt/kms_3d has hardcod | 2015-05-08 | Yes| | 90732 | [BDW/BSW Bisected]igt/gem_reloc_vs_gpu/forked | 2015-05-29 | Yes| | 90808 | [BDW Bisected]igt/gem_ctx_param_basic/invalid | 2015-06-02 | Yes| | 90994 | [BDW regression] pm_rpm subtests fail and giv | 2015-06-16 | No | | 91378 | [hsw dp regression] 06ea66b6 (5.4GHz link clo | 2015-07-17 | No | | 91592 | [pnv regression] OOPS on boot | 2015-08-09 | No | | 91844 | [HSW Regression] intel_do_flush_locked failed | 2015-09-02 | No | | 91952 | [Bisected Regression] Blank screen from boot | 2015-09-10 | Yes| | 91959 | [865g 3.19 regression] Desktop image is disto | 2015-09-10 | No | | 91974 | [bisected] unrecoverable black screen after k | 2015-09-11 | Yes| | 92050 | [regression]/bug introduced by commit [0e572f | 2015-09-19 | No | | 92083 | [regression] [git pull] drm for 4.3 | 2015-09-23 | No | | 92096 | regression/bug introduced by commit [0e572fe7 | 2015-09-24 | No | | 92174 | PROBLEM: Intel VGA output busticated on 4.3-r | 2015-09-29 | No | | 92237 | Horrible noise (audio) via DisplayPort [regre | 2015-10-02 | No | | 92355 | [SKL Regression] igt/kms_fbc_crc cause DUT cr | 2015-10-09 | No | | 92414 | [Intel-gfx] As of kernel 4.3-rc1 system will | 2015-10-10 | Yes| | 92502 | [SKL] [Regression] igt/kms_flip/2x-flip-vs-ex | 2015-10-16 | No | | 92575 | [4.2 regression] Massive graphics corruption | 2015-10-21 | No | | 92655 | [i915] LVDS screen half garbled. unable to bi | 2015-10-23 | Yes| | 92718 | [REGRESSION] 4.3.0-rc7 - Multiple identical k | 2015-10-29 | No | | 92972 | Black screen on Intel NUC hardware (i915) pos | 2015-11-16 | No | | 93120 | [SNB BAT IGT regression] WARN_ON(was_visible) | 2015-11-26 | No | | 93122 | [SNB BAT IGT regression] pm_rpm started skipp | 2015-11-26 | No | | 93263 | 945GM regression since 4.3| 2015-12-05 | No | | 93393 | Regression for Skylake modesetting in kernel | 2015-12-16 | No | | 93509 | [SNB] [4.4 regression] vblank wait timed out | 2015-12-26 | No | +---+---+++ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Intel graphics on Thinkpad T540p is most unsuable now :( (Intel(R) HD Graphics 4600)
On Fri, Jan 08, 2016 at 09:42:24AM -0800, Marc MERLIN wrote: > On Sun, Jan 03, 2016 at 08:04:27AM -0800, Marc MERLIN wrote: > > My hunch at this point is that google-chrome-beta is taxing the GPU and > > causing the driver to misbehave. I'm now back to > > 2:2.99.917+git20151217-1~exp1 and 4.3.3 and will run google-chrome-beta > > --disable-gpu, but this kills other stuff I need and won't be working > > anymore as a result :( > > google-chrome-beta --disable-gpu did not help. > > 4.3.3 and xserver-xorg-video-intel 2:2.99.917+git20151217-1~exp1 gave a > full deadlock > > Downgrading to 3.19.8 also gave the full deadlock. > > I've now just downgraded xserver-xorg-video-intel to 2:2.99.917-1 and > will see how that goes. And I got a full deadlock with that combination too :( Sigh. What broke? The driver was never great, but it wasn't nearly as bad as it's been in the last months (i.e. a crash/deadlock every other day on average). This is quite unbearable. I'm not quite sure what else changed or what else I could revert. Adding an nvidia chip that laptop is going to be involved, so getting a new laptop with nvidia out of the box is simpler, but not cheap when my current laptop otherwise works fine. I'd love a software solution, but I'm running out of ideas. Is there anything I missed? > But I have to ask again: > Who is using that Intel(R) HD Graphics 4600 on a 3K screen laptop? > Anyone? > Or am I the only such user on this list? Sigh, so no one is running this chip? That could explain why it works so badly for me, but somehow I'm hoping that at least the intel developers have that chip and a/some laptops equipped with it? Marc -- "A mouse is a device used to point at the xterm you want to type in" - A.S.R. Microsoft is to operating systems what McDonalds is to gourmet cooking Home page: http://marc.merlins.org/ | PGP 1024R/763BE901 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/21] drm_event cleanup
On Fri, Jan 08, 2016 at 09:36:32PM +0100, Daniel Vetter wrote: > Hi all, > > This patch series is inspired by a WIP patch from Rob Clark to consolidate the > drm_event handling a bit. I've went a bit further and also moved the pending > event handling and unlinking into the core, which allows us to nuke a bunch of > code from drivers who all copypasted this themselves. Plus fix up all the > others > who failed to handle this correctly. > > Net -500 lines of code, plus kerneldoc for drm_fops.c and all the new > functions > as bonus. > > Comments and review highly welcome as usual. What I've forgotten to mention: nouveau does something uncommon with events around the usif notification. It looks fishy, since it neither seems to handle file_priv disappearing nor does it properly reserve space upfront for the event. But that's just my guess, I didn't really follow what's going on there. Therefore I left fixing up nouveau (or just moving it over to these new functions here) to someone else. -Daniel > > Cheers, Daniel > > Daniel Vetter (21): > drm: kerneldoc for drm_fops.c > drm: Add functions to setup/tear down drm_events. > drm/exynos: Use the new event init/free functions > drm/vmwgfx: Use the new event init/free functions > drm: Create drm_send_event helpers > drm/fsl: Remove preclose hook > drm/armada: Remove NULL open/pre/postclose hooks > drm/gma500: Remove empty preclose hook > drm: Clean up pending events in the core > drm/i915: Nuke intel_modeset_preclose > drm/atmel: Nuke preclose > drm/exynos: Remove event cancelling from postclose > drm/imx: Unconfuse preclose logic > drm/msm: Nuke preclose hooks > drm/omap: Nuke close hooks > drm/rcar: Nuke preclose hook > drm/shmob: Nuke preclose hook > drm/tegra: Stop cancelling page flip events > drm/tilcdc: Nuke preclose hook > drm/vc4: Nuke preclose hook > drm/vmwgfx: Nuke preclose hook > > Documentation/DocBook/gpu.tmpl | 48 + > drivers/gpu/drm/armada/armada_drv.c| 3 - > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 18 -- > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 10 - > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 3 - > drivers/gpu/drm/drm_atomic.c | 44 ++--- > drivers/gpu/drm/drm_crtc.c | 36 +--- > drivers/gpu/drm/drm_fops.c | 259 > ++--- > drivers/gpu/drm/drm_irq.c | 7 +- > drivers/gpu/drm/exynos/exynos_drm_drv.c| 14 -- > drivers/gpu/drm/exynos/exynos_drm_g2d.c| 36 +--- > drivers/gpu/drm/exynos/exynos_drm_ipp.c| 28 +-- > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 5 - > drivers/gpu/drm/gma500/psb_drv.c | 9 - > drivers/gpu/drm/i915/i915_dma.c| 2 - > drivers/gpu/drm/i915/intel_display.c | 21 -- > drivers/gpu/drm/i915/intel_drv.h | 1 - > drivers/gpu/drm/imx/imx-drm-core.c | 13 -- > drivers/gpu/drm/imx/ipuv3-crtc.c | 4 - > drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 7 - > drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c| 11 -- > drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h| 1 - > drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 6 - > drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c| 11 -- > drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h| 1 - > drivers/gpu/drm/omapdrm/omap_drv.c | 29 --- > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 20 -- > drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 2 - > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 10 - > drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 20 -- > drivers/gpu/drm/shmobile/shmob_drm_crtc.h | 2 - > drivers/gpu/drm/shmobile/shmob_drm_drv.c | 8 - > drivers/gpu/drm/tegra/dc.c | 17 -- > drivers/gpu/drm/tegra/drm.c| 3 - > drivers/gpu/drm/tegra/drm.h| 1 - > drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 20 -- > drivers/gpu/drm/tilcdc/tilcdc_drv.c| 8 - > drivers/gpu/drm/tilcdc/tilcdc_drv.h| 1 - > drivers/gpu/drm/vc4/vc4_crtc.c | 20 -- > drivers/gpu/drm/vc4/vc4_drv.c | 10 - > drivers/gpu/drm/vc4/vc4_drv.h | 1 - > drivers/gpu/drm/vmwgfx/vmwgfx_drv.c| 10 - > drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 73 +-- > drivers/gpu/drm/vmwgfx/vmwgfx_fence.h | 2 - > include/drm/drmP.h | 26 ++- > 45 files changed, 299 insertions(+), 582 deletions(-) > > -- > 2.6.4 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Clean up pending events in the core
There's really no reason to not do so, instead of replicating this
for every use-case and every driver. Now we can't just nuke the events,
since that would still mean that all drm_event users would need to know
when that has happened, since calling e.g. drm_send_event isn't allowed
any more. Instead just unlink them from the file, and detect this case
and handle it appropriately in all functions.
v2: Adjust existing kerneldoc too.
Cc: Alex Deucher
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fops.c | 35 ++-
include/drm/drmP.h | 2 ++
2 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index d85af1b2a238..d32b24c74e08 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -264,6 +264,7 @@ static int drm_open_helper(struct file *filp, struct
drm_minor *minor)
INIT_LIST_HEAD(&priv->fbs);
mutex_init(&priv->fbs_lock);
INIT_LIST_HEAD(&priv->blobs);
+ INIT_LIST_HEAD(&priv->pending_event_list);
INIT_LIST_HEAD(&priv->event_list);
init_waitqueue_head(&priv->event_wait);
priv->event_space = 4096; /* set aside 4k for event buffer */
@@ -353,18 +354,16 @@ static void drm_events_release(struct drm_file *file_priv)
{
struct drm_device *dev = file_priv->minor->dev;
struct drm_pending_event *e, *et;
- struct drm_pending_vblank_event *v, *vt;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
- /* Remove pending flips */
- list_for_each_entry_safe(v, vt, &dev->vblank_event_list, base.link)
- if (v->base.file_priv == file_priv) {
- list_del(&v->base.link);
- drm_vblank_put(dev, v->pipe);
- v->base.destroy(&v->base);
- }
+ /* Unlink pending events */
+ list_for_each_entry_safe(e, et, &file_priv->pending_event_list,
+pending_link) {
+ list_del(&e->pending_link);
+ e->file_priv = NULL;
+ }
/* Remove unconsumed events */
list_for_each_entry_safe(e, et, &file_priv->event_list, link) {
@@ -712,6 +711,7 @@ int drm_event_reserve_init(struct drm_device *dev,
file_priv->event_space -= e->length;
p->event = e;
+ list_add(&p->pending_link, &file_priv->pending_event_list);
p->file_priv = file_priv;
/* we *could* pass this in as arg, but everyone uses kfree: */
@@ -736,7 +736,10 @@ void drm_event_cancel_free(struct drm_device *dev,
{
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
- p->file_priv->event_space += p->event->length;
+ if (p->file_priv) {
+ p->file_priv->event_space += p->event->length;
+ list_del(&p->pending_link);
+ }
spin_unlock_irqrestore(&dev->event_lock, flags);
p->destroy(p);
}
@@ -750,11 +753,21 @@ EXPORT_SYMBOL(drm_event_cancel_free);
* This function sends the event @e, initialized with drm_event_reserve_init(),
* to its associated userspace DRM file. Callers must already hold
* dev->event_lock, see drm_send_event() for the unlocked version.
+ *
+ * Note that the core will take care of unlinking and disarming events when the
+ * corresponding DRM file is closed. Drivers need to worry about that and can
+ * call this function upon completion of the asynchrnous work unconditionally.
*/
void drm_send_event_locked(struct drm_device *dev, struct drm_pending_event *e)
{
assert_spin_locked(&dev->event_lock);
+ if (!e->file_priv) {
+ e->destroy(e);
+ return;
+ }
+
+ list_del(&e->pending_link);
list_add_tail(&e->link,
&e->file_priv->event_list);
wake_up_interruptible(&e->file_priv->event_wait);
@@ -769,6 +782,10 @@ EXPORT_SYMBOL(drm_send_event_locked);
* This function sends the event @e, initialized with drm_event_reserve_init(),
* to its associated userspace DRM file. This function acquires
dev->event_lock,
* see drm_send_event_locked() for callers which already hold this lock.
+ *
+ * Note that the core will take care of unlinking and disarming events when the
+ * corresponding DRM file is closed. Drivers need to worry about that and can
+ * call this function upon completion of the asynchrnous work unconditionally.
*/
void drm_send_event(struct drm_device *dev, struct drm_pending_event *e)
{
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index ae73abf5c2cf..3d78a7406d54 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -283,6 +283,7 @@ struct drm_ioctl_desc {
struct drm_pending_event {
struct drm_event *event;
struct list_head link;
+ struct list_head pending_link;
struct drm_file *file_priv;
pid_t pid; /* pid of requester, no guarantee it's valid by the time
[Intel-gfx] [PATCH] drm: Create drm_send_event helpers
Use them in the core vblank code and exynos/vmwgfx drivers.
Note that the difference between wake_up_all and _interruptible in
vmwgfx doesn't matter since the only waiter is the core code in
drm_fops.c. And that is interruptible.
v2: Adjust existing kerneldoc too.
Reviewed-by: Alex Deucher (v1)
Cc: Alex Deucher
Cc: Thomas Hellstrom
Cc: Inki Dae
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fops.c | 42 -
drivers/gpu/drm/drm_irq.c | 7 ++
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 5 +---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 5 +---
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 3 +--
include/drm/drmP.h | 2 ++
6 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 476408b638e3..d85af1b2a238 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -683,7 +683,9 @@ EXPORT_SYMBOL(drm_poll);
* This function prepares the passed in event for eventual delivery. If the
event
* doesn't get delivered (because the IOCTL fails later on, before queuing up
* anything) then the even must be cancelled and freed using
- * drm_event_cancel_free().
+ * drm_event_cancel_free(). Successfully initialized events should be sent out
+ * using drm_send_event() or drm_send_event_locked() to signal completion of
the
+ * asynchronous event to userspace.
*
* If callers embedded @p into a larger structure it must be allocated with
* kmalloc and @p must be the first member element.
@@ -739,3 +741,41 @@ void drm_event_cancel_free(struct drm_device *dev,
p->destroy(p);
}
EXPORT_SYMBOL(drm_event_cancel_free);
+
+/**
+ * drm_send_event_locked - send DRM event to file descriptor
+ * @dev: DRM device
+ * @e: DRM event to deliver
+ *
+ * This function sends the event @e, initialized with drm_event_reserve_init(),
+ * to its associated userspace DRM file. Callers must already hold
+ * dev->event_lock, see drm_send_event() for the unlocked version.
+ */
+void drm_send_event_locked(struct drm_device *dev, struct drm_pending_event *e)
+{
+ assert_spin_locked(&dev->event_lock);
+
+ list_add_tail(&e->link,
+ &e->file_priv->event_list);
+ wake_up_interruptible(&e->file_priv->event_wait);
+}
+EXPORT_SYMBOL(drm_send_event_locked);
+
+/**
+ * drm_send_event - send DRM event to file descriptor
+ * @dev: DRM device
+ * @e: DRM event to deliver
+ *
+ * This function sends the event @e, initialized with drm_event_reserve_init(),
+ * to its associated userspace DRM file. This function acquires
dev->event_lock,
+ * see drm_send_event_locked() for callers which already hold this lock.
+ */
+void drm_send_event(struct drm_device *dev, struct drm_pending_event *e)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev->event_lock, irqflags);
+ drm_send_event_locked(dev, e);
+ spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
+EXPORT_SYMBOL(drm_send_event);
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index a70b29909974..3fe8dbff6058 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -983,15 +983,12 @@ static void send_vblank_event(struct drm_device *dev,
struct drm_pending_vblank_event *e,
unsigned long seq, struct timeval *now)
{
- assert_spin_locked(&dev->event_lock);
-
e->event.sequence = seq;
e->event.tv_sec = now->tv_sec;
e->event.tv_usec = now->tv_usec;
- list_add_tail(&e->base.link,
- &e->base.file_priv->event_list);
- wake_up_interruptible(&e->base.file_priv->event_wait);
+ drm_send_event_locked(dev, &e->base);
+
trace_drm_vblank_event_delivered(e->base.pid, e->pipe,
e->event.sequence);
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 82e7f95dfed9..db56c8259f18 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -893,10 +893,7 @@ static void g2d_finish_event(struct g2d_data *g2d, u32
cmdlist_no)
e->event.tv_usec = now.tv_usec;
e->event.cmdlist_no = cmdlist_no;
- spin_lock_irqsave(&drm_dev->event_lock, flags);
- list_move_tail(&e->base.link, &e->base.file_priv->event_list);
- wake_up_interruptible(&e->base.file_priv->event_wait);
- spin_unlock_irqrestore(&drm_dev->event_lock, flags);
+ drm_send_event(dev, &e->base);
}
static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index c8819c05e2dd..1f6a6c1881d6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -1520,10 +1520,7 @@ static int ipp_send_event(struct exynos_drm_ippdrv
*ippdrv,
for_each_ipp_ops(i)
[Intel-gfx] [PATCH] drm: Add functions to setup/tear down drm_events.
An attempt at not spreading out the file_priv->event_space stuff out
quite so far and wide. And I think fixes something in ipp_get_event()
that is broken (or if they are doing something more weird/subtle, then
breaks it in a fun way).
Based upon a patch from Rob Clark, rebased and polished.
v2: Spelling fixes (Alex).
Cc: Alex Deucher
Reviewed-by: Alex Deucher
Cc: Rob Clark
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic.c | 44 -
drivers/gpu/drm/drm_crtc.c | 36 +++-
drivers/gpu/drm/drm_fops.c | 67
include/drm/drmP.h | 7 -
4 files changed, 94 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 3f74193885f1..8fb469c4e4b8 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1347,44 +1347,23 @@ static struct drm_pending_vblank_event
*create_vblank_event(
struct drm_device *dev, struct drm_file *file_priv, uint64_t
user_data)
{
struct drm_pending_vblank_event *e = NULL;
- unsigned long flags;
-
- spin_lock_irqsave(&dev->event_lock, flags);
- if (file_priv->event_space < sizeof e->event) {
- spin_unlock_irqrestore(&dev->event_lock, flags);
- goto out;
- }
- file_priv->event_space -= sizeof e->event;
- spin_unlock_irqrestore(&dev->event_lock, flags);
+ int ret;
e = kzalloc(sizeof *e, GFP_KERNEL);
- if (e == NULL) {
- spin_lock_irqsave(&dev->event_lock, flags);
- file_priv->event_space += sizeof e->event;
- spin_unlock_irqrestore(&dev->event_lock, flags);
- goto out;
- }
+ if (!e)
+ return NULL;
e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
- e->event.base.length = sizeof e->event;
+ e->event.base.length = sizeof(e->event);
e->event.user_data = user_data;
- e->base.event = &e->event.base;
- e->base.file_priv = file_priv;
- e->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
-
-out:
- return e;
-}
-static void destroy_vblank_event(struct drm_device *dev,
- struct drm_file *file_priv, struct drm_pending_vblank_event *e)
-{
- unsigned long flags;
+ ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base);
+ if (ret) {
+ kfree(e);
+ return NULL;
+ }
- spin_lock_irqsave(&dev->event_lock, flags);
- file_priv->event_space += sizeof e->event;
- spin_unlock_irqrestore(&dev->event_lock, flags);
- kfree(e);
+ return e;
}
static int atomic_set_prop(struct drm_atomic_state *state,
@@ -1646,8 +1625,7 @@ out:
if (!crtc_state->event)
continue;
- destroy_vblank_event(dev, file_priv,
-crtc_state->event);
+ drm_event_cancel_free(dev, &crtc_state->event->base);
}
}
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 1e75a145834a..60a4184d41b7 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -5264,7 +5264,6 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_framebuffer *fb = NULL;
struct drm_pending_vblank_event *e = NULL;
- unsigned long flags;
int ret = -EINVAL;
if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
@@ -5315,41 +5314,26 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
}
if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
- ret = -ENOMEM;
- spin_lock_irqsave(&dev->event_lock, flags);
- if (file_priv->event_space < sizeof(e->event)) {
- spin_unlock_irqrestore(&dev->event_lock, flags);
- goto out;
- }
- file_priv->event_space -= sizeof(e->event);
- spin_unlock_irqrestore(&dev->event_lock, flags);
-
- e = kzalloc(sizeof(*e), GFP_KERNEL);
- if (e == NULL) {
- spin_lock_irqsave(&dev->event_lock, flags);
- file_priv->event_space += sizeof(e->event);
- spin_unlock_irqrestore(&dev->event_lock, flags);
+ e = kzalloc(sizeof *e, GFP_KERNEL);
+ if (!e) {
+ ret = -ENOMEM;
goto out;
}
-
e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
e->event.base.length = sizeof(e->event);
e->event.user_data = page_flip->user_data;
- e->base.event = &e->event.base;
- e->base.file_priv = file_priv;
- e->base.destroy =
-
[Intel-gfx] [PATCH] igt/gem_trtt: Exercise the TRTT hardware
From: Akash Goel
This patch provides the testcase to exercise the TRTT hardware.
Some platforms have an additional address translation hardware support in
form of Tiled Resource Translation Table (TR-TT) which provides an extra level
of abstraction over PPGTT.
This is useful for mapping Sparse/Tiled texture resources.
TR-TT is tightly coupled with PPGTT, a new instance of TR-TT will be required
for a new PPGTT instance, but TR-TT may not enabled for every context.
1/16th of the 48bit PPGTT space is earmarked for the translation by TR-TT,
which such chunk to use is conveyed to HW through a register.
Any GFX address, which lies in that reserved 44 bit range will be translated
through TR-TT first and then through PPGTT to get the actual physical address.
TRTT is constructed as a 3 level tile Table. Each tile is 64KB is size which
leaves behind 44-16=28 address bits. 28bits are partitioned as 9+9+10, and
each level is contained within a 4KB page hence L3 and L2 is composed of
512 64b entries and L1 is composed of 1024 32b entries.
There is a provision to keep TR-TT Tables in virtual space, where the pages of
TRTT tables will be mapped to PPGTT. This is the adopted mode, as in this mode
UMD will have a full control on TR-TT management, with bare minimum support
from KMD.
So the entries of L3 table will contain the PPGTT offset of L2 Table pages,
similarly entries of L2 table will contain the PPGTT offset of L1 Table pages.
The entries of L1 table will contain the PPGTT offset of BOs actually backing
the Sparse resources.
I915_GEM_CONTEXT_SETPARAM ioctl is used to request KMD to enable TRTT for a
certain context, a new I915_CONTEXT_PARAM_ENABLE_TRTT param has been
added to the CONTEXT_SETPARAM ioctl for that purpose.
Signed-off-by: Akash Goel
---
tests/Makefile.sources | 1 +
tests/gem_trtt.c | 396 +
2 files changed, 397 insertions(+)
create mode 100644 tests/gem_trtt.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..068a44e 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -64,6 +64,7 @@ TESTS_progs_M = \
gem_streaming_writes \
gem_tiled_blits \
gem_tiled_partial_pwrite_pread \
+ gem_trtt \
gem_userptr_blits \
gem_write_read_ring_switch \
kms_addfb_basic \
diff --git a/tests/gem_trtt.c b/tests/gem_trtt.c
new file mode 100644
index 000..f652b67
--- /dev/null
+++ b/tests/gem_trtt.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Akash Goel
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm.h"
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
+#include "i915_drm.h"
+#include
+#include
+#include
+#include
+#include "igt_kms.h"
+#include
+#include
+#include
+
+#define BO_SIZE 4096
+#define EXEC_OBJECT_PINNED (1<<4)
+#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
+
+#define NO_PPGTT 0
+#define ALIASING_PPGTT 1
+#define FULL_32_BIT_PPGTT 2
+#define FULL_48_BIT_PPGTT 3
+/* uses_full_ppgtt
+ * Finds supported PPGTT details.
+ * @fd DRM fd
+ * @min can be
+ * 0 - No PPGTT
+ * 1 - Aliasing PPGTT
+ * 2 - Full PPGTT (32b)
+ * 3 - Full PPGTT (48b)
+ * RETURNS true/false if min support is present
+*/
+static bool uses_full_ppgtt(int fd, int min)
+{
+ struct drm_i915_getparam gp;
+ int val = 0;
+
+ memset(&gp, 0, sizeof(gp));
+ gp.param = 18; /* HAS_ALIASING_PPGTT */
+ gp.value = &val;
+
+ if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
+ return 0;
+
+ errno = 0;
+ return val >= min;
+}
+
+/* has_softpin_support
+ * Finds if softpin feature is supported
+ * @fd DRM fd
+*/
+static bool
[Intel-gfx] [PATCH] drm/i915: Support to enable TRTT on GEN9
From: Akash Goel
Gen9 has an additional address translation hardware support in form of
Tiled Resource Translation Table (TR-TT) which provides an extra level
of abstraction over PPGTT.
This is useful for mapping Sparse/Tiled texture resources.
Sparse resources are created as virtual-only allocations. Regions of the
resource that the application intends to use is bound to the physical memory
on the fly and can be re-bound to different memory allocations over the
lifetime of the resource.
TR-TT is tightly coupled with PPGTT, a new instance of TR-TT will be required
for a new PPGTT instance, but TR-TT may not enabled for every context.
1/16th of the 48bit PPGTT space is earmarked for the translation by TR-TT,
which such chunk to use is conveyed to HW through a register.
Any GFX address, which lies in that reserved 44 bit range will be translated
through TR-TT first and then through PPGTT to get the actual physical address,
so the output of translation from TR-TT will be a PPGTT offset.
TRTT is constructed as a 3 level tile Table. Each tile is 64KB is size which
leaves behind 44-16=28 address bits. 28bits are partitioned as 9+9+10, and
each level is contained within a 4KB page hence L3 and L2 is composed of
512 64b entries and L1 is composed of 1024 32b entries.
There is a provision to keep TR-TT Tables in virtual space, where the pages of
TRTT tables will be mapped to PPGTT.
Currently this is the supported mode, in this mode UMD will have a full control
on TR-TT management, with bare minimum support from KMD.
So the entries of L3 table will contain the PPGTT offset of L2 Table pages,
similarly entries of L2 table will contain the PPGTT offset of L1 Table pages.
The entries of L1 table will contain the PPGTT offset of BOs actually backing
the Sparse resources.
The assumption here is that UMD only will do the complete PPGTT address space
management and use the Soft Pin API for all the buffer objects associated with
a given Context. So UMD will also have to allocate the L3/L2/L1 table pages
as a regular GEM BO only & assign them a PPGTT address through the Soft Pin API.
UMD would have to emit the MI_STORE_DATA_IMM commands in the batch buffer to
program the relevant entries of L3/L2/L1 tables.
Any space in TR-TT segment not bound to any Sparse texture, will be handled
through Invalid tile, User is expected to initialize the entries of a new
L3/L2/L1 table page with the Invalid tile pattern. The entries corresponding to
the holes in the Sparse texture resource will be set with the Null tile pattern
The improper programming of TRTT should only lead to a recoverable GPU hang,
eventually leading to banning of the culprit context without victimizing others.
The association of any Sparse resource with the BOs will be known only to UMD,
and only the Sparse resources shall be assigned an offset from the TR-TT segment
by UMD. The use of TR-TT segment or mapping of Sparse resources will be
abstracted from the KMD, UMD can do the address assignment from TR-TT segment
autonomously and KMD will be oblivious of it.
The BOs must not be assigned an address from TR-TT segment, they will be mapped
to PPGTT in a regular way by KMD, using the Soft Pin offset provided by UMD.
This patch provides an interface through which UMD can convey KMD to enable
TR-TT for a given context. A new I915_CONTEXT_PARAM_ENABLE_TRTT param has been
added to I915_GEM_CONTEXT_SETPARAM ioctl for that purpose.
UMD will have to pass the GFX address of L3 table page, pattern value for the
Null & invalid Tile registers.
Testcase: igt/gem_trtt
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_dma.c | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 12 +++
drivers/gpu/drm/i915/i915_gem_context.c | 45 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 57 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 6
drivers/gpu/drm/i915/i915_reg.h | 19 +++
drivers/gpu/drm/i915/intel_lrc.c| 41
include/uapi/drm/i915_drm.h | 8 +
8 files changed, 191 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..c247c25 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -172,6 +172,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_SOFTPIN:
value = 1;
break;
+ case I915_PARAM_HAS_TRTT:
+ value = HAS_TRTT(dev);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6dd4db..12c612e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -839,6 +839,7 @@ struct i915_ctx_hang_stats {
#define DEFAULT_CONTEXT_HANDLE 0
#define CONTEXT_NO_ZEROMAP (1<<0)
+#d
Re: [Intel-gfx] [PATCH 21/21] drm/vmwgfx: Nuke preclose hook
On Fri, Jan 8, 2016 at 9:53 PM, Thomas Hellstrom wrote: > On 01/08/2016 09:36 PM, Daniel Vetter wrote: >> Again since the drm core takes care of event unlinking/disarming this >> is now just needless code. >> >> Cc: Thomas Hellström >> Signed-off-by: Daniel Vetter > Hmm, > > IIRC this is actually a list of events that core drm is not aware of > yet. They sit on this list waiting for a fence to pass and are then > transferred to core drm Yes I know. Earlier patches in the series extract new core functions to setup/tear down such events and send them out, which is what's needed to make this trick possible. Exynos similarly uses events similarly, and is also converted. Same for nouveau it seems, but there the code doesn't use the reserve/send split, so I'm unclear how/whether at all it correctly handles this race. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
