Re: [Intel-gfx] [PATCH v3] drm/i915: check that rpm ref is held when accessing ringbuf in stolen mem
On Wed, Jan 27, 2016 at 04:44:37PM +, Chris Wilson wrote: > On Wed, Jan 27, 2016 at 03:43:49PM +, daniele.ceraolospu...@intel.com > wrote: > > From: Daniele Ceraolo Spurio > > > > While running some tests on the scheduler patches with rpm enabled I > > came across a corruption in the ringbuffer, which was root-caused to > > the GPU being suspended while commands were being emitted to the > > ringbuffer. The access to memory was failing because the GPU needs to > > be awake when accessing stolen memory (where my ringbuffer was located). > > Since we have this constraint it looks like a sensible idea to check > > that we hold a refcount when we access the rungbuffer. > > > > v2: move the check from ring_begin to ringbuffer iomap time (Chris) > > v3: update comment (Chris) > > > > Cc: John Harrison > > Cc: Chris Wilson > > Signed-off-by: Daniele Ceraolo Spurio > > That explains itself nicely, thanks. > Reviewed-by: Chris Wilson Queued for -next, thanks for the patch. > It also rings alarms bells for intel_fbdev.c Oops, indeed. Might explain why we sometimes just die? And fundamentally it's unfixable (without a shadow fb) since we can't intercept mmaps on fbdev. But maybe we need to do that (and use the damage tracking that's already there in 3 copies in various drivers for uploading). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] agp/intel-gtt: Only register fake agp driver for gen1
On Wed, Jan 27, 2016 at 02:38:00PM +0100, Daniel Vetter wrote:
> The fake agp driver for the intel graphics gart is only needed for ums
> support. And we ditched that a long time ago:
>
> commit 03dae59c72d8ef6e005f48ba356c863e0587
> Author: Daniel Vetter
> Date: Wed Jul 23 16:27:25 2014 +0200
>
> drm/i915: Ditch UMS config option
>
> With this there's no longer the problem that 2 drivers (fake agp
> driver and the drm/i915 driver) fight over the same piece, which fixes
> apparent dma leaks detected by CONFIG_DMA_API_DEBUG.
>
> Note that the leak isn't real since intel-gtt refcounts and will tear
> down eventually. But the debug code assumes that when the i915 driver
> unbinds from the pci device everything should be gone. Which isn't the
> case if we have intel-agp enabled - userspace might need it. But by
> ditching this intel-gtt setup and teardown is completely tied to the
> livetime of the "real" driver.
>
> While at it untangle the init ordering a bit - the fake agp wouldn't
> be initialized correctly if i915.ko loads first. Which isn't a problem
> since when i915 loads in kms mode you won't need the fake agp support
> needed by the ums driver ...
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93793
> Signed-off-by: Daniel Vetter
Merged patches 1&2 from this series. Anyone up for an r-b/ack on this one
here?
Thanks, Daniel
> ---
> drivers/char/agp/intel-gtt.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index e657f989745e..aef87fdbd187 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1348,16 +1348,6 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev,
> struct pci_dev *gpu_pdev,
> {
> int i, mask;
>
> - /*
> - * Can be called from the fake agp driver but also directly from
> - * drm/i915.ko. Hence we need to check whether everything is set up
> - * already.
> - */
> - if (intel_private.driver) {
> - intel_private.refcount++;
> - return 1;
> - }
> -
> for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
> if (gpu_pdev) {
> if (gpu_pdev->device ==
> @@ -1378,16 +1368,26 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev,
> struct pci_dev *gpu_pdev,
> if (!intel_private.driver)
> return 0;
>
> - intel_private.refcount++;
> -
> #if IS_ENABLED(CONFIG_AGP_INTEL)
> if (bridge) {
> + if (INTEL_GTT_GEN > 1)
> + return 0;
> +
> bridge->driver = &intel_fake_agp_driver;
> bridge->dev_private_data = &intel_private;
> bridge->dev = bridge_pdev;
> }
> #endif
>
> +
> + /*
> + * Can be called from the fake agp driver but also directly from
> + * drm/i915.ko. Hence we need to check whether everything is set up
> + * already.
> + */
> + if (intel_private.refcount++)
> + return 1;
> +
> intel_private.bridge_dev = pci_dev_get(bridge_pdev);
>
> dev_info(&bridge_pdev->dev, "Intel %s Chipset\n",
> intel_gtt_chipsets[i].name);
> --
> 2.5.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Capture revision id in error state (rev2)
On Fri, Jan 29, 2016 at 11:08:53AM +, Arun Siluvery wrote: > On 29/01/2016 10:27, Patchwork wrote: > >== Summary == > > > >Series 2850v2 drm/i915: Capture revision id in error state > >http://patchwork.freedesktop.org/api/1.0/series/2850/revisions/2/mbox/ > > > >Test kms_flip: > > Subgroup basic-flip-vs-dpms: > > pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE > [BAT ILK] sporadic fifo underruns in igt@kms_flip@basic-flip-vs-* on > ilk-hp8440p > known issue, https://bugs.freedesktop.org/show_bug.cgi?id=93787 > > >Test kms_force_connector_basic: > > Subgroup prune-stale-modes: > > pass -> SKIP (ilk-hp8440p) > It is not showing up in patchwork results page. > > >Test kms_pipe_crc_basic: > > Subgroup bad-nb-words-1: > > pass -> DMESG-WARN (hsw-gt2) > known issue, it is not on P1 list though, > https://bugs.freedesktop.org/show_bug.cgi?id=93226 > > > > Subgroup nonblocking-crc-pipe-a: > > skip -> PASS (byt-nuc) > It is not showing up in patchwork results page, checked detailed results > page and it was skipped once before. Yeah, something is broken with the edid injection and seems racy, resulting in corruption and who knows what else. Not sure what's going on, but the overall issue is tracked as P1 in https://bugs.freedesktop.org/show_bug.cgi?id=93769 > > > Subgroup nonblocking-crc-pipe-b: > > pass -> DMESG-WARN (ilk-hp8440p) > [BAT ILK] sporadic fifo underruns in igt@kms_flip@basic-flip-vs-* on > ilk-hp8440p > known issue, https://bugs.freedesktop.org/show_bug.cgi?id=93787 > > regards > Arun > > > > >bdw-nuci7total:156 pass:147 dwarn:0 dfail:0 fail:0 skip:9 > >bdw-ultratotal:159 pass:147 dwarn:0 dfail:0 fail:0 skip:12 > >bsw-nuc-2total:159 pass:129 dwarn:0 dfail:0 fail:0 skip:30 > >byt-nuc total:159 pass:136 dwarn:0 dfail:0 fail:0 skip:23 > >hsw-brixbox total:159 pass:146 dwarn:0 dfail:0 fail:0 skip:13 > >hsw-gt2 total:159 pass:148 dwarn:1 dfail:0 fail:0 skip:10 > >ilk-hp8440p total:159 pass:108 dwarn:2 dfail:0 fail:0 skip:49 > >ivb-t430stotal:159 pass:145 dwarn:0 dfail:0 fail:0 skip:14 > >skl-i5k-2total:159 pass:144 dwarn:1 dfail:0 fail:0 skip:14 > >snb-dellxps total:159 pass:137 dwarn:0 dfail:0 fail:0 skip:22 > >snb-x220ttotal:159 pass:137 dwarn:0 dfail:0 fail:1 skip:21 > > > >Results at /archive/results/CI_IGT_test/Patchwork_1313/ > > > >5de97b25e5f3c5a63ee243a9d3b22d30792f7d3e drm-intel-nightly: > >2016y-01m-29d-07h-32m-09s UTC integration manifest > >76d742df11e81b8fa096b65c5f7864c6237afa6b drm/i915: Capture PCI revision and > >subsytem details in error state > > > > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Capture PCI revision and subsytem details in error state
On Thu, Jan 28, 2016 at 05:18:41PM +, Arun Siluvery wrote:
> Revision id along with device id is useful in better identification of the HW
> and its limitations so include this detail in error state.
>
> v2: make it clear that it is PCI revision and We might as well dump PCI
> subsystem details while we update this (Ville, Chris).
>
> Cc: Chris Wilson
> Signed-off-by: Arun Siluvery
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 7eeb244..978c026 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -365,6 +365,10 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> err_printf(m, "Reset count: %u\n", error->reset_count);
> err_printf(m, "Suspend count: %u\n", error->suspend_count);
> err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
> + err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
> + err_printf(m, "PCI Subsystem: %04x:%04x\n",
> +dev->pdev->subsystem_vendor,
> +dev->pdev->subsystem_device);
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
> if (HAS_CSR(dev)) {
> --
> 1.9.1
>
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: fix context/engine cleanup order
On Fri, Jan 22, 2016 at 11:10:06PM +, Dave Gordon wrote:
> From: Nick Hoath
>
> Swap the order of context & engine cleanup, so that contexts are cleaned
> up first, and *then* engines. This is a more sensible order anyway, but
> in particular has become necessary since the 'intel_ring_initialized()
> must be simple and inline' patch, which now uses ring->dev as an
> 'initialised' flag, so it can now be NULL after engine teardown. This
> in turn can cause a problem in the context code, which (used to) check
> the ring->dev->struct_mutex -- causing a fault if ring->dev was NULL.
>
> Also rename the cleanup function to reflect what it actually does
> (cleanup engines, not a ringbuffer), and fix an annoying whitespace issue.
>
> v2: Also make the fix in i915_load_modeset_init, not just in
> i915_driver_unload (Chris Wilson)
> v3: Had extra stuff in it.
> v4: Reverted extra stuff (so we're back to v2).
> Rebased and updated commentary above (Dave Gordon).
>
> Signed-off-by: Nick Hoath
> Signed-off-by: David Gordon
> Reviewed-by: Chris Wilson
>
> Cc: Mika Kuoppala
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Signed-off-by: Dave Gordon
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ---
> 3 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d70d96f..4725e8d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -451,8 +451,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
>
> cleanup_gem:
> mutex_lock(&dev->struct_mutex);
> - i915_gem_cleanup_ringbuffer(dev);
> i915_gem_context_fini(dev);
> + i915_gem_cleanup_engines(dev);
> mutex_unlock(&dev->struct_mutex);
> cleanup_irq:
> intel_guc_ucode_fini(dev);
> @@ -1196,8 +1196,8 @@ int i915_driver_unload(struct drm_device *dev)
>
> intel_guc_ucode_fini(dev);
> mutex_lock(&dev->struct_mutex);
> - i915_gem_cleanup_ringbuffer(dev);
> i915_gem_context_fini(dev);
> + i915_gem_cleanup_engines(dev);
> mutex_unlock(&dev->struct_mutex);
> intel_fbc_cleanup_cfb(dev_priv);
> i915_gem_cleanup_stolen(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 204661f..021e88a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3012,7 +3012,7 @@ int i915_gem_init_rings(struct drm_device *dev);
> int __must_check i915_gem_init_hw(struct drm_device *dev);
> int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
> void i915_gem_init_swizzling(struct drm_device *dev);
> -void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
> +void i915_gem_cleanup_engines(struct drm_device *dev);
> int __must_check i915_gpu_idle(struct drm_device *dev);
> int __must_check i915_gem_suspend(struct drm_device *dev);
> void __i915_add_request(struct drm_i915_gem_request *req,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 371bbb2..799a53a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4912,7 +4912,7 @@ int i915_gem_init_rings(struct drm_device *dev)
> req = i915_gem_request_alloc(ring, NULL);
> if (IS_ERR(req)) {
> ret = PTR_ERR(req);
> - i915_gem_cleanup_ringbuffer(dev);
> + i915_gem_cleanup_engines(dev);
> goto out;
> }
>
> @@ -4925,7 +4925,7 @@ int i915_gem_init_rings(struct drm_device *dev)
> if (ret && ret != -EIO) {
> DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
> i915_gem_request_cancel(req);
> - i915_gem_cleanup_ringbuffer(dev);
> + i915_gem_cleanup_engines(dev);
> goto out;
> }
>
> @@ -4933,7 +4933,7 @@ int i915_gem_init_rings(struct drm_device *dev)
> if (ret && ret != -EIO) {
> DRM_ERROR("Context enable ring #%d failed %d\n", i,
> ret);
> i915_gem_request_cancel(req);
> - i915_gem_cleanup_ringbuffer(dev);
> + i915_gem_cleanup_engines(dev);
> goto out;
> }
>
> @@ -5008,7 +5008,7 @@ int i915_gem_init(struct drm_device *dev)
> }
>
> void
> -i915_gem_cleanup_ringbuffer(struct drm_device *dev)
> +i915_gem_cleanup_engines(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> @@ -5017,13 +5017,14 @@ int i915_gem_init(struct drm_device *dev)
> for_each_ring(ring, dev_priv, i)
> dev_priv->gt.cleanup_ring(ring);
>
> -if (
Re: [Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC
On Tue, Feb 09, 2016 at 02:08:23PM +0200, Martin Peres wrote: > On 26/01/16 19:00, Daniel Vetter wrote: > >On Tue, Jan 26, 2016 at 07:45:42AM -0800, Jesse Barnes wrote: > >>On 01/22/2016 09:00 AM, Daniel Vetter wrote: > >>>On Wed, Jan 20, 2016 at 06:26:02PM -0800, tom.orou...@intel.com wrote: > From: Tom O'Rourke > > > >I'd say we need to keep the boost-deboost stuff alive, e.g. by manually > >telling guc that the we want different limits, then resetting those limits > >again after the boost is done. Same for fast idling - kernel simply has a > >better idea if anyone is about to submit more work (we have execbuf hints > >for specific workloads like libva). > > Since there is soon to be a GPU scheduler, the GuC could get this > information already, right? Unless you are talking about having mesa signal > when it starts creating a new batchbuffer and you would like the GPU to > prepare to ramp-up. We don't tell the guc when we're stalling for a batch, so no it doesn't know. The entire desing seems to center around the idea of just aiming for some average fps, which is silly for spikey workloads. I assuming that without some other magic we'll still need explicit boosting and deboosting. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()
On Thu, Jan 28, 2016 at 08:51:14PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 25, 2016 at 06:30:17PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 20, 2016 at 09:05:29PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > The page aligned surface address calculation needs to know which way
> > > things are rotated. The contract now says that the caller must pass the
> > > rotate x/y coordinates, as well as the tile_height aligned stride in
> > > the tile_height direction. This will make it fairly simple to deal with
> > > 90/270 degree rotation on SKL+ where we have to deal with the rotated
> > > view into the GTT.
> > >
> > > v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs.
> > > 90/270
> > > v3: Introduce intel_tile_dims(), and don't mix up different units so much
> > >
> > > Signed-off-by: Ville Syrjälä
> > > Reviewed-by: Daniel Vetter (v2)
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 66
> > > +---
> > > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > > drivers/gpu/drm/i915/intel_sprite.c | 18 +-
> > > 3 files changed, 59 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index cfd52ea68e34..bda3224021b2 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2269,6 +2269,18 @@ unsigned int intel_tile_height(const struct
> > > drm_i915_private *dev_priv,
> > > intel_tile_width(dev_priv, fb_modifier, cpp);
> > > }
> > >
> > > +/* Return the tile dimensions in pixel units */
> > > +static void intel_tile_dims(const struct drm_i915_private *dev_priv,
> > > + unsigned int *tile_width,
> > > + unsigned int *tile_height,
> > > + uint64_t fb_modifier,
> > > + unsigned int cpp)
> > > +{
> > > + *tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> > > + *tile_height = intel_tile_size(dev_priv) / *tile_width;
> > > + *tile_width /= cpp;
> >
> > Seems like my suggestion to use tile_width in cpp wasn't that awesome, at
> > least we still have a big confusion right here. Not sure what to do,
> > especially since these kind of changes are super-painful to review. Could
> > we perhaps go back to the old versions and untangle this mess afterwards?
> > Iirc I've follow-up with r-b tags to all patches in the old series for
> > that approach.
>
> Hmm. What did I do differently in the old approach again? Other than not
> having the confusion isolated to this one function. One step forward and
> two back doens't sound productive. Plus I have some more patches on top
> of this one already, so not pleasant at all.
Old patch reused the same variables for values both in bytes and pixels
(and the conversion happened deep down in some function call, without any
comments). This here looks better, but still suffers a bit from confusing
naming.
>
> Anyway, to avoid more confusion I suppose one thing that could be done
> is this:
> - intel_tile_width
> + intel_tile_width_bytes
>
> intel_tile_dims()
> {
> tile_width_bytes = intel_tile_width_bytes()
> *tile_height = tile_size / tile_width_bytes;
> *tile_width = tile_width_bytes / cpp;
> }
Yeah that sounds reasonable I think.
-Daniel
>
> >
> > No idea really what would be best here ...
> > -Daniel
> >
> > > +}
> > > +
> > > unsigned int
> > > intel_fb_align_height(struct drm_device *dev, unsigned int height,
> > > uint32_t pixel_format, uint64_t fb_modifier)
> > > @@ -2306,19 +2318,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view
> > > *view, struct drm_framebuffer *fb,
> > > tile_size = intel_tile_size(dev_priv);
> > >
> > > cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > - tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> > > - tile_height = tile_size / tile_width;
> > > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > > + fb->modifier[0], cpp);
> > >
> > > - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> > > + info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> > > info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> > > info->size = info->width_pages * info->height_pages * tile_size;
> > >
> > > if (info->pixel_format == DRM_FORMAT_NV12) {
> > > cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> > > - tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
> > > - tile_height = tile_size / tile_width;
> > > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > > + fb->modifier[1], cpp);
> > >
> > > - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
> > > + info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width
> > > * cpp);
> > >
Re: [Intel-gfx] [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
On Mon, Feb 01, 2016 at 03:20:19PM +0100, Patrik Jakobsson wrote:
> On Fri, Jan 22, 2016 at 01:28:45PM +0200, Gabriel Feceoru wrote:
> > Some Gen7/8 production parts may have the Display Pipe C fused off.
> > In this case, the display hardware will prevent the enable bit in
> > PIPE_CONF register (for Pipe C) from being set to 1.
> >
> > Fixed by adjusting pipe_count to reflect this.
> >
> > v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> > on ivybridge (Ville)
> > v3: Remove unnecessary MMIO read, correct the description (Damien)
> > v4: Be more specific in description (Patrick)
> >
> > Signed-off-by: Gabriel Feceoru
>
> Reviewed-by: Patrik Jakobsson
Queued for -next, thanks for the patch.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 3 +++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index d70d96f..91404aa 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct
> > drm_device *dev)
> > !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> > + DRM_INFO("PipeC fused off\n");
> > + info->num_pipes -= 1;
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 0a98889..a182739 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define IVB_PIPE_C_DISABLE(1 << 28)
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > --
> > 1.9.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> ---
> Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista,
> Stockholm, Sweden Registration Number: 556189-6027
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Check for get_pages instead of shmem (filp) (rev2)
== Summary == Series 3145v2 drm/i915: Check for get_pages instead of shmem (filp) http://patchwork.freedesktop.org/api/1.0/series/3145/revisions/2/mbox/ Test pm_rpm: Subgroup basic-pci-d3-state: fail -> PASS (hsw-gt2) pass -> DMESG-WARN (byt-nuc) Subgroup basic-rte: dmesg-warn -> PASS (bsw-nuc-2) dmesg-warn -> PASS (byt-nuc) UNSTABLE bdw-nuci7total:161 pass:152 dwarn:0 dfail:0 fail:0 skip:9 bdw-ultratotal:164 pass:152 dwarn:0 dfail:0 fail:0 skip:12 bsw-nuc-2total:164 pass:136 dwarn:0 dfail:0 fail:0 skip:28 byt-nuc total:164 pass:140 dwarn:1 dfail:0 fail:0 skip:23 hsw-brixbox total:164 pass:151 dwarn:0 dfail:0 fail:0 skip:13 hsw-gt2 total:164 pass:154 dwarn:0 dfail:0 fail:0 skip:10 ilk-hp8440p total:164 pass:116 dwarn:0 dfail:0 fail:0 skip:48 ivb-t430stotal:164 pass:150 dwarn:0 dfail:0 fail:0 skip:14 snb-dellxps total:164 pass:142 dwarn:0 dfail:0 fail:0 skip:22 snb-x220ttotal:164 pass:142 dwarn:0 dfail:0 fail:1 skip:21 Results at /archive/results/CI_IGT_test/Patchwork_1385/ d9bd337b4b2d46f73005fcdf0e7049e7f8ed5c04 drm-intel-nightly: 2016y-02m-09d-15h-42m-46s UTC integration manifest cb1f5a551af8b6b2f3f75a322a70df5891eee393 drm/i915: Check for get_pages instead of shmem (filp) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
On Wed, Feb 10, 2016 at 12:24:51PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> In file included from drivers/gpu/drm/nouveau/nouveau_drm.c:25:0:
> include/linux/apple-gmux.h: In function 'apple_gmux_present':
> include/linux/apple-gmux.h:36:42: error: implicit declaration of function
> 'acpi_dev_present' [-Werror=implicit-function-declaration]
> return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
> ^
>
> Caused by commit
>
> 2413306c2566 ("apple-gmux: Add helper for presence detect")
>
> I have used the drm-misc tree from next-20160209 for today.
Can you pls attach your .config? The function is there, I suspect we're
just missing some depends in Kconfig.
-Daniel
--
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Re: [Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
couple of questions since i am looking at SKL code for the first time
> seems we are not reading max cd clock from VBIOS like BDW
even though SKL has limit register to say max cd clock i dont think
it is working, so VBIOS saves the value during boot just like in BDW
and we are supposed to use it. please check VBT spec for the details
> why should we store vco in a separate variable when it is already
available as part of "pipe_config->dpll_hw_state.ctrl1"
> still trying to understand the flow but is "ctrl1"/"VCO" in this patch
written to DPLL_CTRL1 before we change the CD Clock ? if not then
it might be a bug and must be fixed as part of changes
here.
regards,
Sivakumar
On 2/10/2016 5:58 AM, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
Signed-off-by: Clint Taylor
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?=
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_ddi.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 83 +-
drivers/gpu/drm/i915/intel_dp.c |9 +++-
drivers/gpu/drm/i915/intel_drv.h |1 +
5 files changed, 81 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..372a68f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640) {
+ dev_priv->skl_vco_freq = 8100;
+ }
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
/* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 :
308570 );
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
s
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi all,
After merging the drm-misc tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:
In file included from drivers/gpu/drm/nouveau/nouveau_drm.c:25:0:
include/linux/apple-gmux.h: In function 'apple_gmux_present':
include/linux/apple-gmux.h:36:42: error: implicit declaration of function
'acpi_dev_present' [-Werror=implicit-function-declaration]
return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
^
Caused by commit
2413306c2566 ("apple-gmux: Add helper for presence detect")
I have used the drm-misc tree from next-20160209 for today.
--
Cheers,
Stephen Rothwell
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Re: [Intel-gfx] Intel graphics on Thinkpad T540p is most unsuable now :( (Intel(R) HD Graphics 4600)
On Sat, Jan 09, 2016 at 04:07:05PM -0800, Marc MERLIN wrote: > On Fri, Jan 08, 2016 at 09:42:24AM -0800, Marc MERLIN wrote: > > On Sun, Jan 03, 2016 at 08:04:27AM -0800, Marc MERLIN wrote: > > > My hunch at this point is that google-chrome-beta is taxing the GPU and > > > causing the driver to misbehave. I'm now back to > > > 2:2.99.917+git20151217-1~exp1 and 4.3.3 and will run google-chrome-beta > > > --disable-gpu, but this kills other stuff I need and won't be working > > > anymore as a result :( > > > > google-chrome-beta --disable-gpu did not help. > > > > 4.3.3 and xserver-xorg-video-intel 2:2.99.917+git20151217-1~exp1 gave a > > full deadlock > > > > Downgrading to 3.19.8 also gave the full deadlock. > > > > I've now just downgraded xserver-xorg-video-intel to 2:2.99.917-1 and > > will see how that goes. > > And I got a full deadlock with that combination too :( > > Sigh. What broke? The driver was never great, but it wasn't nearly as > bad as it's been in the last months (i.e. a crash/deadlock every other > day on average). This is quite unbearable. Well, I had my system board replaced just in case, and this seems to have addressed my hangs. So that's good news, it seems that the driver doesn't have a big regression on my chip afterall. Marc -- "A mouse is a device used to point at the xterm you want to type in" - A.S.R. Microsoft is to operating systems what McDonalds is to gourmet cooking Home page: http://marc.merlins.org/ | PGP 1024R/763BE901 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
Signed-off-by: Clint Taylor
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?=
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_ddi.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 83 +-
drivers/gpu/drm/i915/intel_dp.c |9 +++-
drivers/gpu/drm/i915/intel_drv.h |1 +
5 files changed, 81 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..372a68f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640) {
+ dev_priv->skl_vco_freq = 8100;
+ }
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
/* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 :
308570 );
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9841,64 @@ static void broadwell_modeset_commit_cdclk(struct
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+
[Intel-gfx] [PATCH] drm/i915/guc: Set init value for cached work queue head
From: Alex Dai
The cached work queue header pointer is set to last byte of work
queue buffer. It will make sure the whole work queue buffer is
available after coming back from reset or init.
Do not hold kmap_atomic mapping before going to sleep when work
queue is full.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index d7543ef..41f4a96 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -486,11 +486,11 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size)
return 0;
- base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
- desc = base + gc->proc_desc_offset;
-
while (timeout_counter-- > 0) {
+ base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
+ desc = base + gc->proc_desc_offset;
gc->wq_head = desc->head;
+ kunmap_atomic(base);
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) {
ret = 0;
@@ -501,8 +501,6 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
usleep_range(1000, 2000);
};
- kunmap_atomic(base);
-
return ret;
}
@@ -730,6 +728,8 @@ static struct i915_guc_client *guc_client_alloc(struct
drm_device *dev,
client->client_obj = obj;
client->wq_offset = GUC_DB_SIZE;
client->wq_size = GUC_WQ_SIZE;
+ client->wq_head = GUC_WQ_SIZE - 1;
+ client->wq_tail = 0;
client->doorbell_offset = select_doorbell_cacheline(guc);
--
2.5.0
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: fix error path in intel_setup_gmbus()
On Tue, 09 Feb 2016, Rasmus Villemoes wrote:
> This fails to undo the setup for pin==0; moreover, something
> interesting happens if the setup failed already at pin==0.
>
> Signed-off-by: Rasmus Villemoes
> ---
> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 25254b5c1ac5..deb8282c26d8 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -683,7 +683,7 @@ int intel_setup_gmbus(struct drm_device *dev)
> return 0;
>
> err:
> - while (--pin) {
> + while (pin--) {
> if (!intel_gmbus_is_valid_pin(dev_priv, pin))
> continue;
Reviewed-by: Jani Nikula
Fixes: f899fc64cda8 ("drm/i915: use GMBUS to manage i2c links")
Cc: sta...@vger.kernel.org
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 2/5] drm/i915: fix error path in intel_setup_gmbus()
This fails to undo the setup for pin==0; moreover, something
interesting happens if the setup failed already at pin==0.
Signed-off-by: Rasmus Villemoes
---
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 25254b5c1ac5..deb8282c26d8 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -683,7 +683,7 @@ int intel_setup_gmbus(struct drm_device *dev)
return 0;
err:
- while (--pin) {
+ while (pin--) {
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
--
2.1.4
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[Intel-gfx] [PATCH 0/5] pre-decrement in error paths considered harmful
There are a few instances of
for (i = 0; i < FOO; ++i) {
ret = do_stuff(i)
if (ret)
goto err;
}
...
err:
while (--i)
undo_stuff(i);
At best, this fails to undo_stuff for i==0, but if i==0 was the case
that failed, we'll end up with an "infinite" loop in the error path
doing nasty stuff.
These were found with a simple coccinelle script
@@
expression i;
identifier l;
statement S;
@@
* l:
* while (--i)
S
(and there were no false positives).
There's no dependencies between the patches; I just wanted to include
a common cover letter with a little background info.
Rasmus Villemoes (5):
drm/gma500: fix error path in gma_intel_setup_gmbus()
drm/i915: fix error path in intel_setup_gmbus()
net/mlx4: fix some error handling in mlx4_multi_func_init()
net: sxgbe: fix error paths in sxgbe_platform_probe()
mm/backing-dev.c: fix error path in wb_init()
drivers/gpu/drm/gma500/intel_gmbus.c| 2 +-
drivers/gpu/drm/i915/intel_i2c.c| 2 +-
drivers/net/ethernet/mellanox/mlx4/cmd.c| 4 ++--
drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c | 4 ++--
mm/backing-dev.c| 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
--
2.1.4
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[Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)
This behavior of checking for a shmem backed GEM object was introduced here:
commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab
Author: Brad Volkin
Date: Tue Feb 18 10:15:45 2014 -0800
drm/i915: Refactor shmem pread setup
It is possible for an object to not be a shmem backed GEM object (for example
userptr objects). An example of how we hit this failure can be found through
copy_batch() in the command parser because we allocate a userptr object for the
batch which contains privileged instructions. Userptr calls
drm_gem_private_object_init() which explicitly sets the filp to none.
NOTE: I manually retyped this from a test machine. So I haven't even compiled
this exact patch.
v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon)
Cc: Chris Wilson
Cc: Kristian Høgsberg
Cc: Dave Gordon
Signed-off-by: Ben Widawsky
Tested-by: Jordan Justen (v1)
Reviewed-by: Jordan Justen (v1)
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e9b19bc..7fd79b0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct
drm_i915_gem_object *obj,
*needs_clflush = 0;
- if (!obj->base.filp)
+ if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
return -EINVAL;
if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
--
2.7.0
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Re: [Intel-gfx] [PATCH] drm/i915: Check for get_pages instead of shmem (filp)
On Tue, Feb 09, 2016 at 11:30:34AM +, Dave Gordon wrote: > On 09/02/16 00:20, Kristian Høgsberg wrote: > >On Fri, Feb 5, 2016 at 5:48 PM, Ben Widawsky > > wrote: > >>This behavior of checking for a shmem backed GEM object was introduced here: > >>commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab > >>Author: Brad Volkin > >>Date: Tue Feb 18 10:15:45 2014 -0800 > >> > >> drm/i915: Refactor shmem pread setup > >> > >>It is possible for an object to not be a shmem backed GEM object (for > >>example > >>userptr objects). An example of how we hit this failure can be found through > >>copy_batch() in the command parser because we allocate a userptr object for > >>the > >>batch which contains privileged instructions. Userptr calls > >>drm_gem_private_object_init() which explicitly sets the filp to none. > >> > >>It is equally feasible to simply remove the check altogether. You'll > >>probably > >>oops with get_pages somewhere, but that's okay IMO because this condition > >>should be a driver bug, and not trigger-able by userspace. On this note, the > >>function name could probably benefit from a change, but whatever. > >> > >>NOTE: I manually retyped this from a test machine. So I haven't even > >>compiled > >>this exact patch. > >> > >>Cc: Chris Wilson > >>Cc: Kristian Høgsberg > >>Cc: Jordan Justen > >>Signed-off-by: Ben Widawsky > >>--- > >> drivers/gpu/drm/i915/i915_gem.c | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >>diff --git a/drivers/gpu/drm/i915/i915_gem.c > >>b/drivers/gpu/drm/i915/i915_gem.c > >>index 66b1705..a198928 100644 > >>--- a/drivers/gpu/drm/i915/i915_gem.c > >>+++ b/drivers/gpu/drm/i915/i915_gem.c > >>@@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct > >>drm_i915_gem_object *obj, > >> > >> *needs_clflush = 0; > >> > >>- if (!obj->base.filp) > >>+ if (!obj->ops->get_pages) > > Don't all subclasses have a get_pages() function? Yeah, as I said in the commit message, I didn't think this was particularly appealing, but I figured people would say something if I removed everything. I wasn't aware of Chris' patch. > > >Do we want to do what Chris did in > >a2a4f916c2f344d4e596c875dd1e66764afec8b8 (on drm-intel-fixes): > > > >+ if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == > >0)) > > > >? > > Yes, I think so; i915_gem_shmem_pread() is going to walk the sglist, so the > object had better have a page array for it to iterate over. > > .Dave. > Okay. I'll send v2. Thanks. -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] lib/igt_kms: Add COMMIT_ATOMIC to igt_display_commit2()
Hi,
When submiting the patch you should add i-g-t to your subject.
See CONTRIBUTING file on how to set that.
Also when submiting a new version you should add the version to
the subject. [PATCH i-g-t vX]
I've made some additional small nitpicks when these seem fit.
On Thu, Feb 04, 2016 at 05:23:01PM +0530, Mayuresh Gharpure wrote:
> Co-Author : Marius Vlad
>
> So far we have had only two commit styles, COMMIT_LEGACY
> and COMMIT_UNIVERSAL. This patch adds another commit style
> COMMIT_ATOMIC which makes use of drmModeAtomicCommit()
>
> v2 : (Marius)
> i)Set CRTC_ID to zero while disabling plane
> ii)Modified the log message in igt_atomic_prepare_plane_commit
> https://patchwork.freedesktop.org/patch/71945/
>
> v3 : (Marius)Set FB_ID to zero while disabling plane
> https://patchwork.freedesktop.org/patch/72179/
>
> v4: (Maarten) Corrected the typo in commit message
>
> Signed-off-by: Mayuresh Gharpure
> ---
> lib/igt_kms.c | 318
> +-
> lib/igt_kms.h | 71 -
> 2 files changed, 387 insertions(+), 2 deletions(-)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 90c8da7..6c07223 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -145,6 +145,120 @@ const unsigned char* igt_kms_get_base_edid(void)
> *
> * Returns: an alternate edid block
> */
> +static const char *igt_plane_prop_names[IGT_NUM_PLANE_PROPS] = {
> + "SRC_X",
> + "SRC_Y",
> + "SRC_W",
> + "SRC_H",
> + "CRTC_X",
> + "CRTC_Y",
> + "CRTC_W",
> + "CRTC_H",
> + "FB_ID",
> + "CRTC_ID",
> + "type",
> + "rotation"
> +};
> +
> +static const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> + "background_color"
> +};
> +
> +static const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> + "scaling mode",
> + "DPMS"
> +};
> +
> +/*
> + * Retrieve all the properies specified in props_name and store them into
> + * plane->atomic_props_plane.
> + */
> +static void
> +igt_atomic_fill_plane_props(igt_display_t *display, igt_plane_t *plane,
> + int num_props, const char **prop_names)
> +{
> + drmModeObjectPropertiesPtr props;
> + int i, j, fd;
> +
> + fd = display->drm_fd;
> +
> + props = drmModeObjectGetProperties(fd, plane->drm_plane->plane_id,
> DRM_MODE_OBJECT_PLANE);
> + igt_assert(props);
> +
> + for (i = 0; i < props->count_props; i++) {
> + drmModePropertyPtr prop =
> + drmModeGetProperty(fd, props->props[i]);
> +
> + for (j = 0; j < num_props; j++) {
> + if (strcmp(prop->name, prop_names[j]) != 0)
> + continue;
> +
> + plane->atomic_props_plane[j] = props->props[i];
> + break;
> + }
> +
> + drmModeFreeProperty(prop);
> + }
> +
> + drmModeFreeObjectProperties(props);
> +}
> +
> +/*
> + * Retrieve all the properies specified in props_name and store them into
> + * config->atomic_props_crtc and config->atomic_props_connector.
> + */
> +static void
> +igt_atomic_fill_props(igt_display_t *display, igt_output_t *output,
> + int num_crtc_props, const char **crtc_prop_names,
> + int num_connector_props, const char **conn_prop_names)
> +{
> + drmModeObjectPropertiesPtr props;
> + int i, j, fd;
> +
> + fd = display->drm_fd;
> +
> + props = drmModeObjectGetProperties(fd, output->config.crtc->crtc_id,
> DRM_MODE_OBJECT_CRTC);
> + igt_assert(props);
> +
> + for (i = 0; i < props->count_props; i++) {
> + drmModePropertyPtr prop =
> + drmModeGetProperty(fd, props->props[i]);
> +
> + for (j = 0; j < num_crtc_props; j++) {
> + if (strcmp(prop->name, crtc_prop_names[j]) != 0)
> + continue;
> +
> + output->config.atomic_props_crtc[j] = props->props[i];
> + break;
> + }
> +
> + drmModeFreeProperty(prop);
> + }
> +
> + drmModeFreeObjectProperties(props);
> + props = NULL;
> + props = drmModeObjectGetProperties(fd,
> output->config.connector->connector_id, DRM_MODE_OBJECT_CONNECTOR);
> + igt_assert(props);
> +
> + for (i = 0; i < props->count_props; i++) {
> + drmModePropertyPtr prop =
> + drmModeGetProperty(fd, props->props[i]);
> +
> + for (j = 0; j < num_connector_props; j++) {
> + if (strcmp(prop->name, conn_prop_names[j]) != 0)
> + continue;
> +
> + output->config.atomic_props_connector[j] =
> props->props[i];
> + break;
> + }
> +
> + drmModeFreeProperty(prop);
> + }
> +
> + drmModeFreeObjectProperties(props);
> +
> +}
> +
> const unsi
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev3)
== Summary == Series 2679v3 drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) 2016-02-09T15:30:40.543598 http://patchwork.freedesktop.org/api/1.0/series/2679/revisions/3/mbox/ Applying: drm/i915: Rename the rotated gtt view member to 'rotated' Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_gtt.c M drivers/gpu/drm/i915/i915_gem_gtt.h M drivers/gpu/drm/i915/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c Patch failed at 0001 drm/i915: Rename the rotated gtt view member to 'rotated' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915: move VBT based TV presence check to intel_bios.c
== Summary == Series 3202v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/3202/revisions/1/mbox/ Test core_prop_blob: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Test drv_getparams_basic: Subgroup basic-eu-total: pass -> DMESG-WARN (skl-i5k-2) Test drv_module_reload_basic: pass -> INCOMPLETE (skl-i5k-2) Test gem_basic: Subgroup bad-close: pass -> INCOMPLETE (skl-i5k-2) Subgroup create-close: pass -> INCOMPLETE (skl-i5k-2) Subgroup create-fd-close: pass -> INCOMPLETE (skl-i5k-2) Test gem_ctx_create: Subgroup basic: pass -> DMESG-WARN (skl-i5k-2) Test gem_ctx_param_basic: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-default: pass -> INCOMPLETE (skl-i5k-2) Subgroup invalid-ctx-get: pass -> DMESG-WARN (skl-i5k-2) Subgroup invalid-ctx-set: pass -> INCOMPLETE (skl-i5k-2) Subgroup invalid-param-get: pass -> DMESG-WARN (skl-i5k-2) Subgroup invalid-param-set: pass -> DMESG-WARN (skl-i5k-2) Subgroup invalid-size-set: pass -> INCOMPLETE (skl-i5k-2) Subgroup non-root-set-no-zeromap: pass -> DMESG-WARN (skl-i5k-2) Subgroup root-set: pass -> DMESG-WARN (skl-i5k-2) Subgroup root-set-no-zeromap-disabled: pass -> INCOMPLETE (skl-i5k-2) Subgroup root-set-no-zeromap-enabled: pass -> INCOMPLETE (skl-i5k-2) Test gem_exec_basic: Subgroup basic-bsd1: skip -> INCOMPLETE (skl-i5k-2) Subgroup basic-default: pass -> INCOMPLETE (skl-i5k-2) Test gem_exec_parse: Subgroup basic-allowed: skip -> INCOMPLETE (skl-i5k-2) Subgroup basic-rejected: skip -> INCOMPLETE (skl-i5k-2) Test gem_flink_basic: Subgroup bad-flink: pass -> DMESG-WARN (skl-i5k-2) Subgroup basic: pass -> DMESG-WARN (skl-i5k-2) Test gem_mmap: Subgroup basic-small-bo: pass -> INCOMPLETE (skl-i5k-2) Test gem_mmap_gtt: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-read: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-read-write-distinct: pass -> DMESG-WARN (skl-i5k-2) Subgroup basic-small-bo-tiledy: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-write-cpu-read-gtt: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-write-gtt-no-prefault: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-write-no-prefault: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-write-read: pass -> DMESG-WARN (skl-i5k-2) Test gem_pread: Subgroup basic: pass -> DMESG-WARN (skl-i5k-2) Test gem_render_linear_blits: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Test gem_render_tiled_blits: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Test gem_ringfill: Subgroup basic-default-hang: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-default-interruptible: pass -> INCOMPLETE (skl-i5k-2) Test gem_storedw_loop: Subgroup basic-blt: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-bsd: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-default: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-vebox: pass -> INCOMPLETE (skl-i5k-2) Test gem_sync: Subgroup basic-blt: pass -> INCOMPLETE (skl-i5k-2) Subgroup basic-bsd1: skip -> INCOMPLETE (skl-i5k-2) Subgroup basic-default: pass -> SKIP (skl-i5k-2) Subgroup basic-vebox: pass -> INCOMPLETE (skl-i5k-2) Test gem_tiled_fence_blits: Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Test kms_addfb_basic: Subgroup addfb25-x-tiled: pass -> INCOMPLETE (skl-i5k-2) Subgroup addfb25-x-tiled-mismatch: pass -> DMESG-WARN (skl-i5k-2) Subgroup addfb25-y-tiled: pass -> INCOMPLETE (skl-i5k-2) Subgroup bad-pitch-32: pass -> DMESG-WARN (skl-i5k-2) Subgroup basic: pass -> INCOMPLETE (skl-i5k-2) Subgroup bo-too-small:
Re: [Intel-gfx] [PATCH] drm/i915: Skip DDI PLL selection for DSI
On Tue, 09 Feb 2016, Ville Syrjälä wrote:
> On Tue, Feb 09, 2016 at 01:16:18PM +0530, Thulasimani, Sivakumar wrote:
>>
>>
>> On 2/9/2016 12:02 PM, Jani Nikula wrote:
>> > On Tue, 09 Feb 2016, "Thulasimani, Sivakumar"
>> > wrote:
>> >> On 2/5/2016 4:59 PM, Mika Kahola wrote:
>> >>> Skip DDI PLL selection if display type is DSI/MIPI.
>> >>>
>> >>> Signed-off-by: Mika Kahola
>> >>> ---
>> >>>drivers/gpu/drm/i915/intel_display.c | 9 +++--
>> >>>1 file changed, 7 insertions(+), 2 deletions(-)
>> >>>
>> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> >>> b/drivers/gpu/drm/i915/intel_display.c
>> >>> index d7de2a5..5da98b2 100644
>> >>> --- a/drivers/gpu/drm/i915/intel_display.c
>> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> >>> @@ -9902,8 +9902,13 @@ static void broadwell_modeset_commit_cdclk(struct
>> >>> drm_atomic_state *old_state)
>> >>>static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> >>>struct intel_crtc_state
>> >>> *crtc_state)
>> >>>{
>> >>> -if (!intel_ddi_pll_select(crtc, crtc_state))
>> >>> -return -EINVAL;
>> >>> +struct intel_encoder *intel_encoder =
>> >>> +intel_ddi_get_crtc_new_encoder(crtc_state);
>> >>> +
>> >>> +if (intel_encoder->type != INTEL_OUTPUT_DSI) {
>> >>> +if (!intel_ddi_pll_select(crtc, crtc_state))
>> >>> +return -EINVAL;
>> >>> +}
>> >>>
>> >> can this be moved inside bxt_ddi_pll_select ? we can avoid this check for
>> >> other platforms that also execute this function.
>> > I asked Mika to do it this way, but if you feel strongly about it I
>> > guess I could be persuaded otherwise too.
>> >
>> > My main point is, if we pass on DSI encoders to DDI functions in some
>> > cases but mostly not, it will muddy the waters and eventually people end
>> > up checking for "is dsi" all around DDI just because they can't be
>> > bothered to check if the functions are really called for DDI only or
>> > not. It's more of a maintainability concern than anything else.
>> >
>> > BR,
>> > Jani.
>> >
>> i am fine with this either way. i was thinking of avoid such checks
>> in other platforms where it is not needed but your concern of
>> too many is_dsi checks is valid as well.
>> with that i am fine with this change as is.
>> Reviewed-by: Sivakumar Thulasimani
>
> Another idea would be to use the clock_set thing to skip it, but
> I think historically that has only been used to skip the PLL
> calculations, not the PLL selection. So might be it would just confuse
> things more.
I just pushed this one. Thanks for the patch and review.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH v4 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
From: Ville Syrjälä
Add a few helpers to get the dimensions of the chroma plane(s).
v2: Add kernel-doc (Daniel)
v3: Fix kerneldoc "Returns:" style (Daniel)
Uninline the functions and check for num_planes (Daniel)
v4: Add the required EXPORT_SYMBOL()s
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_crtc.c | 42 ++
include/drm/drm_crtc.h | 2 ++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6e6514ef9968..1685eb33b4f3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -5715,6 +5715,48 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_format_plane_width - width of the plane given the first plane
+ * @width: width of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The width of @plane, given that the width of the first plane is @width.
+ */
+int drm_format_plane_width(int width, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return width;
+
+ return width / drm_format_horz_chroma_subsampling(format);
+}
+EXPORT_SYMBOL(drm_format_plane_width);
+
+/**
+ * drm_format_plane_height - height of the plane given the first plane
+ * @height: height of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The height of @plane, given that the height of the first plane is @height.
+ */
+int drm_format_plane_height(int height, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return height;
+
+ return height / drm_format_vert_chroma_subsampling(format);
+}
+EXPORT_SYMBOL(drm_format_plane_height);
+
+/**
* drm_rotation_simplify() - Try to simplify the rotation
* @rotation: Rotation to be simplified
* @supported_rotations: Supported rotations
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c65a212db77e..3a4b53ecd121 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2482,6 +2482,8 @@ extern int drm_format_num_planes(uint32_t format);
extern int drm_format_plane_cpp(uint32_t format, int plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
+extern int drm_format_plane_width(int width, uint32_t format, int plane);
+extern int drm_format_plane_height(int height, uint32_t format, int plane);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
unsigned int
supported_rotations);
--
2.4.10
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/execlists: Move WA_TAIL_DWORDS to callee (rev2)
== Summary == Series 3133v2 drm/i915/execlists: Move WA_TAIL_DWORDS to callee http://patchwork.freedesktop.org/api/1.0/series/3133/revisions/2/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (ilk-hp8440p) Test gem_mmap_gtt: Subgroup basic-small-bo: pass -> DMESG-WARN (ilk-hp8440p) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> INCOMPLETE (ilk-hp8440p) UNSTABLE Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (skl-i5k-2) Subgroup suspend-read-crc-pipe-c: pass -> DMESG-WARN (skl-i5k-2) Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (byt-nuc) UNSTABLE bdw-nuci7total:161 pass:152 dwarn:0 dfail:0 fail:0 skip:9 bdw-ultratotal:164 pass:152 dwarn:0 dfail:0 fail:0 skip:12 bsw-nuc-2total:164 pass:136 dwarn:0 dfail:0 fail:0 skip:28 byt-nuc total:164 pass:140 dwarn:1 dfail:0 fail:0 skip:23 hsw-brixbox total:164 pass:151 dwarn:0 dfail:0 fail:0 skip:13 hsw-gt2 total:164 pass:154 dwarn:0 dfail:0 fail:0 skip:10 ilk-hp8440p total:70 pass:44 dwarn:2 dfail:0 fail:0 skip:23 ivb-t430stotal:164 pass:150 dwarn:0 dfail:0 fail:0 skip:14 skl-i5k-2total:164 pass:149 dwarn:1 dfail:0 fail:0 skip:14 snb-dellxps total:164 pass:142 dwarn:0 dfail:0 fail:0 skip:22 Results at /archive/results/CI_IGT_test/Patchwork_1382/ 1f4f5acc87d9c2093397076060b1613b486f14d1 drm-intel-nightly: 2016y-02m-09d-14h-30m-13s UTC integration manifest e9915caa1d9c338f5d16ba0cf344f018cbf807ab drm/i915/execlists: Move WA_TAIL_DWORDS to callee ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/6] drm/i915: move VBT based LVDS presence check to intel_bios.c
Hide knowledge about VBT child devices in intel_bios.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 50
drivers/gpu/drm/i915/intel_lvds.c | 53 +--
3 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf3ef03856db..24bf770907ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3394,6 +3394,7 @@ extern void intel_i2c_reset(struct drm_device *dev);
int intel_bios_init(struct drm_i915_private *dev_priv);
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
+bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
*i2c_pin);
/* intel_opregion.c */
#ifdef CONFIG_ACPI
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index d5e6da01adaa..4f7eba36a849 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1472,3 +1472,53 @@ bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv)
return false;
}
+
+/**
+ * intel_bios_is_lvds_present - is LVDS present in VBT
+ * @dev_priv: i915 device instance
+ * @i2c_pin: i2c pin for LVDS if present
+ *
+ * Return true if LVDS is present. If no child devices were parsed from VBT,
+ * assume LVDS is present.
+ */
+bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
+{
+ int i;
+
+ if (!dev_priv->vbt.child_dev_num)
+ return true;
+
+ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+ union child_device_config *uchild = dev_priv->vbt.child_dev + i;
+ struct old_child_dev_config *child = &uchild->old;
+
+ /* If the device type is not LFP, continue.
+* We have to check both the new identifiers as well as the
+* old for compatibility with some BIOSes.
+*/
+ if (child->device_type != DEVICE_TYPE_INT_LFP &&
+ child->device_type != DEVICE_TYPE_LFP)
+ continue;
+
+ if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
+ *i2c_pin = child->i2c_pin;
+
+ /* However, we cannot trust the BIOS writers to populate
+* the VBT correctly. Since LVDS requires additional
+* information from AIM blocks, a non-zero addin offset is
+* a good indicator that the LVDS is actually present.
+*/
+ if (child->addin_offset)
+ return true;
+
+ /* But even then some BIOS writers perform some black magic
+* and instantiate the device without reference to any
+* additional data. Trust that if the VBT was written into
+* the OpRegion then they have validated the LVDS's existence.
+*/
+ if (dev_priv->opregion.vbt)
+ return true;
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 811ddf7799f0..325acfbc02f3 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -773,57 +773,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
{ } /* terminating entry */
};
-/*
- * Enumerate the child dev array parsed from VBT to check whether
- * the LVDS is present.
- * If it is present, return 1.
- * If it is not present, return false.
- * If no child dev is parsed from VBT, it assumes that the LVDS is present.
- */
-static bool lvds_is_present_in_vbt(struct drm_device *dev,
- u8 *i2c_pin)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
- int i;
-
- if (!dev_priv->vbt.child_dev_num)
- return true;
-
- for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
- union child_device_config *uchild = dev_priv->vbt.child_dev + i;
- struct old_child_dev_config *child = &uchild->old;
-
- /* If the device type is not LFP, continue.
-* We have to check both the new identifiers as well as the
-* old for compatibility with some BIOSes.
-*/
- if (child->device_type != DEVICE_TYPE_INT_LFP &&
- child->device_type != DEVICE_TYPE_LFP)
- continue;
-
- if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
- *i2c_pin = child->i2c_pin;
-
- /* However, we cannot trust the BIOS writers to populate
-* the VBT correctly. Since LVDS requires additional
-* information from AIM blocks, a non-zero addin offset is
-
[Intel-gfx] [PATCH v2 6/6] drm/i915/bios: drop has_mipi in favor of intel_bios_is_dsi_present
Favor a single point of truth instead of duplicating the information.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_bios.c | 12 +++-
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e23a40087ca..ae22f4bc7a44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1478,7 +1478,6 @@ struct intel_vbt_data {
unsigned int lvds_use_ssc:1;
unsigned int display_clock_mode:1;
unsigned int fdi_rx_polarity_inverted:1;
- unsigned int has_mipi:1;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 4b6bd6f2e193..aa90dc662e7f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -706,7 +706,7 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
const struct mipi_pps_data *pps;
/* parse MIPI blocks only if LFP type is MIPI */
- if (!dev_priv->vbt.has_mipi)
+ if (!intel_bios_is_dsi_present(dev_priv, NULL))
return;
/* Initialize this to undefined indicating no generic MIPI support */
@@ -1232,13 +1232,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
continue;
}
- if (p_child->common.dvo_port >= DVO_PORT_MIPIA
- && p_child->common.dvo_port <= DVO_PORT_MIPID
- &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
- DRM_DEBUG_KMS("Found MIPI as LFP\n");
- dev_priv->vbt.has_mipi = 1;
- }
-
child_dev_ptr = dev_priv->vbt.child_dev + count;
count++;
@@ -1580,7 +1573,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv,
switch (dvo_port) {
case DVO_PORT_MIPIA:
case DVO_PORT_MIPIC:
- *port = dvo_port - DVO_PORT_MIPIA;
+ if (port)
+ *port = dvo_port - DVO_PORT_MIPIA;
return true;
case DVO_PORT_MIPIB:
case DVO_PORT_MIPID:
--
2.1.4
___
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[Intel-gfx] [PATCH v2 3/6] drm/i915: move VBT based eDP port check to intel_bios.c
Hide knowledge about VBT child devices in intel_bios.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 21 +
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24bf770907ae..ac66552cb135 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3395,6 +3395,7 @@ int intel_bios_init(struct drm_i915_private *dev_priv);
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
*i2c_pin);
+bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
/* intel_opregion.c */
#ifdef CONFIG_ACPI
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 4f7eba36a849..7f61ca8165f0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1522,3 +1522,36 @@ bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv, u8 *i2c_pin)
return false;
}
+
+/**
+ * intel_bios_is_port_edp - is the device in given port eDP
+ * @dev_priv: i915 device instance
+ * @port: port to check
+ *
+ * Return true if the device in %port is eDP.
+ */
+bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
+{
+ union child_device_config *p_child;
+ static const short port_mapping[] = {
+ [PORT_B] = DVO_PORT_DPB,
+ [PORT_C] = DVO_PORT_DPC,
+ [PORT_D] = DVO_PORT_DPD,
+ [PORT_E] = DVO_PORT_DPE,
+ };
+ int i;
+
+ if (!dev_priv->vbt.child_dev_num)
+ return false;
+
+ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+ p_child = dev_priv->vbt.child_dev + i;
+
+ if (p_child->common.dvo_port == port_mapping[port] &&
+ (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
+ (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
+ return true;
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04a5330..9a4cfdf0cd70 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5065,14 +5065,6 @@ put_power:
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- union child_device_config *p_child;
- int i;
- static const short port_mapping[] = {
- [PORT_B] = DVO_PORT_DPB,
- [PORT_C] = DVO_PORT_DPC,
- [PORT_D] = DVO_PORT_DPD,
- [PORT_E] = DVO_PORT_DPE,
- };
/*
* eDP not supported on g4x. so bail out early just
@@ -5084,18 +5076,7 @@ bool intel_dp_is_edp(struct drm_device *dev, enum port
port)
if (port == PORT_A)
return true;
- if (!dev_priv->vbt.child_dev_num)
- return false;
-
- for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
- p_child = dev_priv->vbt.child_dev + i;
-
- if (p_child->common.dvo_port == port_mapping[port] &&
- (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
- (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
- return true;
- }
- return false;
+ return intel_bios_is_port_edp(dev_priv, port);
}
void
--
2.1.4
___
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[Intel-gfx] [PATCH v2 5/6] drm/i915/panel: setup pwm backlight based on connector type
Use the connector type instead of VBT directly to decide which backlight
mechanism to use on VLV/CHV. (Indirectly, this is the same thing, but
hides the VBT use.)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 21ee6477bf98..f7fbb7c223b1 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1745,7 +1745,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
*panel)
panel->backlight.get = pch_get_backlight;
panel->backlight.hz_to_pwm = pch_hz_to_pwm;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- if (dev_priv->vbt.has_mipi) {
+ if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
panel->backlight.setup = pwm_setup_backlight;
panel->backlight.enable = pwm_enable_backlight;
panel->backlight.disable = pwm_disable_backlight;
--
2.1.4
___
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[Intel-gfx] [PATCH v2 4/6] drm/i915: move VBT based DSI presence check to intel_bios.c
Hide knowledge about VBT child devices in intel_bios.c.
v2: Move port check to intel_bios.c (Sivakumar)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_bios.c | 39 ++-
drivers/gpu/drm/i915/intel_dsi.c | 17 -
3 files changed, 47 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac66552cb135..9e23a40087ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,7 +1512,6 @@ struct intel_vbt_data {
/* MIPI DSI */
struct {
- u16 port;
u16 panel_id;
struct mipi_config *config;
struct mipi_pps_data *pps;
@@ -3396,6 +3395,7 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
size);
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
*i2c_pin);
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
+bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port
*port);
/* intel_opregion.c */
#ifdef CONFIG_ACPI
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 7f61ca8165f0..4b6bd6f2e193 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1237,7 +1237,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
&&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
DRM_DEBUG_KMS("Found MIPI as LFP\n");
dev_priv->vbt.has_mipi = 1;
- dev_priv->vbt.dsi.port = p_child->common.dvo_port;
}
child_dev_ptr = dev_priv->vbt.child_dev + count;
@@ -1555,3 +1554,41 @@ bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv, enum port port)
return false;
}
+
+/**
+ * intel_bios_is_dsi_present - is DSI present in VBT
+ * @dev_priv: i915 device instance
+ * @port: port for DSI if present
+ *
+ * Return true if DSI is present, and return the port in %port.
+ */
+bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
+ enum port *port)
+{
+ union child_device_config *p_child;
+ u8 dvo_port;
+ int i;
+
+ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+ p_child = dev_priv->vbt.child_dev + i;
+
+ if (!(p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT))
+ continue;
+
+ dvo_port = p_child->common.dvo_port;
+
+ switch (dvo_port) {
+ case DVO_PORT_MIPIA:
+ case DVO_PORT_MIPIC:
+ *port = dvo_port - DVO_PORT_MIPIA;
+ return true;
+ case DVO_PORT_MIPIB:
+ case DVO_PORT_MIPID:
+ DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
+ port_name(dvo_port - DVO_PORT_MIPIA));
+ break;
+ }
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 378f879f4015..185ec5a13cf6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1112,7 +1112,7 @@ void intel_dsi_init(struct drm_device *dev)
DRM_DEBUG_KMS("\n");
/* There is no detection method for MIPI so rely on VBT */
- if (!dev_priv->vbt.has_mipi)
+ if (!intel_bios_is_dsi_present(dev_priv, &port))
return;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
@@ -1153,16 +1153,15 @@ void intel_dsi_init(struct drm_device *dev)
intel_connector->unregister = intel_connector_unregister;
/* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
- if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
- intel_encoder->crtc_mask = (1 << PIPE_A);
- intel_dsi->ports = (1 << PORT_A);
- } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
- intel_encoder->crtc_mask = (1 << PIPE_B);
- intel_dsi->ports = (1 << PORT_C);
- }
+ if (port == PORT_A)
+ intel_encoder->crtc_mask = 1 << PIPE_A;
+ else
+ intel_encoder->crtc_mask = 1 << PIPE_B;
if (dev_priv->vbt.dsi.config->dual_link)
- intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+ intel_dsi->ports = (1 << PORT_A) | (1 << PORT_C);
+ else
+ intel_dsi->ports = 1 << port;
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
--
2.1.4
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[Intel-gfx] [PATCH v2 1/6] drm/i915: move VBT based TV presence check to intel_bios.c
Hide knowledge about VBT child devices in intel_bios.c.
v2: also move int_tv_support check to intel_bios.c (Sivakumar)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 41 ++
drivers/gpu/drm/i915/intel_tv.c | 46 +--
3 files changed, 43 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665405eb..cf3ef03856db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3393,6 +3393,7 @@ extern void intel_i2c_reset(struct drm_device *dev);
/* intel_bios.c */
int intel_bios_init(struct drm_i915_private *dev_priv);
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
+bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
/* intel_opregion.c */
#ifdef CONFIG_ACPI
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index bf62a19c8f69..d5e6da01adaa 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1431,3 +1431,44 @@ intel_bios_init(struct drm_i915_private *dev_priv)
return 0;
}
+
+/**
+ * intel_bios_is_tv_present - is integrated TV present in VBT
+ * @dev_priv: i915 device instance
+ *
+ * Return true if TV is present. If no child devices were parsed from VBT,
+ * assume TV is present.
+ */
+bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
+{
+ union child_device_config *p_child;
+ int i;
+
+ if (!dev_priv->vbt.int_tv_support)
+ return false;
+
+ if (!dev_priv->vbt.child_dev_num)
+ return true;
+
+ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+ p_child = dev_priv->vbt.child_dev + i;
+ /*
+* If the device type is not TV, continue.
+*/
+ switch (p_child->old.device_type) {
+ case DEVICE_TYPE_INT_TV:
+ case DEVICE_TYPE_TV:
+ case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
+ break;
+ default:
+ continue;
+ }
+ /* Only when the addin_offset is non-zero, it is regarded
+* as present.
+*/
+ if (p_child->old.addin_offset)
+ return true;
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 5034b0055169..c27a6aec25e0 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1530,47 +1530,6 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs
= {
.destroy = intel_encoder_destroy,
};
-/*
- * Enumerate the child dev array parsed from VBT to check whether
- * the integrated TV is present.
- * If it is present, return 1.
- * If it is not present, return false.
- * If no child dev is parsed from VBT, it assumes that the TV is present.
- */
-static int tv_is_present_in_vbt(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
- union child_device_config *p_child;
- int i, ret;
-
- if (!dev_priv->vbt.child_dev_num)
- return 1;
-
- ret = 0;
- for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
- p_child = dev_priv->vbt.child_dev + i;
- /*
-* If the device type is not TV, continue.
-*/
- switch (p_child->old.device_type) {
- case DEVICE_TYPE_INT_TV:
- case DEVICE_TYPE_TV:
- case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
- break;
- default:
- continue;
- }
- /* Only when the addin_offset is non-zero, it is regarded
-* as present.
-*/
- if (p_child->old.addin_offset) {
- ret = 1;
- break;
- }
- }
- return ret;
-}
-
void
intel_tv_init(struct drm_device *dev)
{
@@ -1586,13 +1545,10 @@ intel_tv_init(struct drm_device *dev)
if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
return;
- if (!tv_is_present_in_vbt(dev)) {
+ if (!intel_bios_is_tv_present(dev_priv)) {
DRM_DEBUG_KMS("Integrated TV is not present.\n");
return;
}
- /* Even if we have an encoder we may not have a connector */
- if (!dev_priv->vbt.int_tv_support)
- return;
/*
* Sanity check the TV output by checking to see if the
--
2.1.4
___
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Re: [Intel-gfx] [PATCH i-g-t] lib: Fix build when vc4 headers are present
On Tue, Feb 09, 2016 at 03:45:37PM +0100, Tomeu Vizoso wrote:
> Automake seems to not like variable assignments indented with tabs.
>
> Signed-off-by: Tomeu Vizoso
> Fixes: 9e5478dc4345 ("lib: Only compile igt_vc4 is we have it")
Yay, I'm incompetent. Thanks for fixing this up, applied.
-Daniel
> ---
> lib/Makefile.am | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/lib/Makefile.am b/lib/Makefile.am
> index 460e0046e00f..e3a456bacaf3 100644
> --- a/lib/Makefile.am
> +++ b/lib/Makefile.am
> @@ -9,9 +9,9 @@ noinst_LTLIBRARIES = libintel_tools.la
> noinst_HEADERS = check-ndebug.h
>
> if HAVE_VC4
> - libintel_tools_la_SOURCES +=\
> - igt_vc4.c \
> - igt_vc4.h
> +libintel_tools_la_SOURCES += \
> +igt_vc4.c\
> +igt_vc4.h
> endif
>
> AM_CPPFLAGS = -I$(top_srcdir)
> --
> 2.5.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
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Re: [Intel-gfx] [PATCH RESEND 1/5] drm/i915: move VBT based TV presence check to intel_bios.c
On Mon, 08 Feb 2016, "Thulasimani, Sivakumar"
wrote:
> On 2/5/2016 4:06 PM, Jani Nikula wrote:
>> Hide knowledge about VBT child devices in intel_bios.c.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_bios.c | 38 ++
>> drivers/gpu/drm/i915/intel_tv.c | 43
>> +--
>> 3 files changed, 40 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 77227a39f3d5..715f200cfbf5 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3397,6 +3397,7 @@ extern void intel_i2c_reset(struct drm_device *dev);
>> /* intel_bios.c */
>> int intel_bios_init(struct drm_i915_private *dev_priv);
>> bool intel_bios_is_valid_vbt(const void *buf, size_t size);
>> +bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
>>
>> /* intel_opregion.c */
>> #ifdef CONFIG_ACPI
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index bf62a19c8f69..2800ae50465a 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1431,3 +1431,41 @@ intel_bios_init(struct drm_i915_private *dev_priv)
>>
>> return 0;
>> }
>> +
>> +/**
>> + * intel_bios_is_tv_present - is integrated TV present in VBT
>> + * @dev_priv: i915 device instance
>> + *
>> + * Return true if TV is present. If no child devices were parsed from VBT,
>> + * assume TV is present.
>> + */
>> +bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
>> +{
>> +union child_device_config *p_child;
>> +int i;
>> +
>> +if (!dev_priv->vbt.child_dev_num)
>> +return true;
>> +
> This is old code moved here, but should we return true
> when child_dev_num == 0 ? I understand we shouldn't make
> functional changes when moving code but just pointing out
> to check if this can be fixed in the further patches.
I have no idea, but I'm guessing it's there for historical reasons. No
reason to change it now as the code gets run only for some gen 3/4
hardware.
>> +for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
>> +p_child = dev_priv->vbt.child_dev + i;
>> +/*
>> + * If the device type is not TV, continue.
>> + */
>> +switch (p_child->old.device_type) {
>> +case DEVICE_TYPE_INT_TV:
>> +case DEVICE_TYPE_TV:
>> +case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
>> +break;
>> +default:
>> +continue;
>> +}
>> +/* Only when the addin_offset is non-zero, it is regarded
>> + * as present.
>> + */
>> +if (p_child->old.addin_offset)
>> +return true;
>> +}
>> +
>> +return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_tv.c
>> b/drivers/gpu/drm/i915/intel_tv.c
>> index 5034b0055169..8417fcad02d2 100644
>> --- a/drivers/gpu/drm/i915/intel_tv.c
>> +++ b/drivers/gpu/drm/i915/intel_tv.c
>> @@ -1530,47 +1530,6 @@ static const struct drm_encoder_funcs
>> intel_tv_enc_funcs = {
>> .destroy = intel_encoder_destroy,
>> };
>>
>> -/*
>> - * Enumerate the child dev array parsed from VBT to check whether
>> - * the integrated TV is present.
>> - * If it is present, return 1.
>> - * If it is not present, return false.
>> - * If no child dev is parsed from VBT, it assumes that the TV is present.
>> - */
>> -static int tv_is_present_in_vbt(struct drm_device *dev)
>> -{
>> -struct drm_i915_private *dev_priv = dev->dev_private;
>> -union child_device_config *p_child;
>> -int i, ret;
>> -
>> -if (!dev_priv->vbt.child_dev_num)
>> -return 1;
>> -
>> -ret = 0;
>> -for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
>> -p_child = dev_priv->vbt.child_dev + i;
>> -/*
>> - * If the device type is not TV, continue.
>> - */
>> -switch (p_child->old.device_type) {
>> -case DEVICE_TYPE_INT_TV:
>> -case DEVICE_TYPE_TV:
>> -case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
>> -break;
>> -default:
>> -continue;
>> -}
>> -/* Only when the addin_offset is non-zero, it is regarded
>> - * as present.
>> - */
>> -if (p_child->old.addin_offset) {
>> -ret = 1;
>> -break;
>> -}
>> -}
>> -return ret;
>> -}
>> -
>> void
>> intel_tv_init(struct drm_device *dev)
>> {
>> @@ -1586,7 +1545,7 @@ intel_tv_init(struct drm_device *dev)
>> if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
>> return;
>>
>> -if (!tv_is_present_in_vbt(dev)) {
>> +if (!intel_bios_is_tv_prese
Re: [Intel-gfx] [PATCH RESEND 4/5] drm/i915: move VBT based DSI presence check to intel_bios.c
On Mon, 08 Feb 2016, "Thulasimani, Sivakumar"
wrote:
> On 2/5/2016 4:06 PM, Jani Nikula wrote:
>> Hide knowledge about VBT child devices in intel_bios.c.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_bios.c | 33 -
>> drivers/gpu/drm/i915/intel_dsi.c | 23 ++-
>> 3 files changed, 47 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 234f33708a31..cd2595c25f8d 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1516,7 +1516,6 @@ struct intel_vbt_data {
>>
>> /* MIPI DSI */
>> struct {
>> -u16 port;
>> u16 panel_id;
>> struct mipi_config *config;
>> struct mipi_pps_data *pps;
>> @@ -3400,6 +3399,7 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
>> size);
>> bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
>> bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
>> *i2c_pin);
>> bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port
>> port);
>> +bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port
>> *port);
>>
>> /* intel_opregion.c */
>> #ifdef CONFIG_ACPI
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 1429d8214885..b0cf33234c33 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1237,7 +1237,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
>> &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
>> DRM_DEBUG_KMS("Found MIPI as LFP\n");
>> dev_priv->vbt.has_mipi = 1;
>> -dev_priv->vbt.dsi.port = p_child->common.dvo_port;
>> }
>>
>> child_dev_ptr = dev_priv->vbt.child_dev + count;
>> @@ -1552,3 +1551,35 @@ bool intel_bios_is_port_edp(struct drm_i915_private
>> *dev_priv, enum port port)
>>
>> return false;
>> }
>> +
>> +/**
>> + * intel_bios_is_dsi_present - is DSI present in VBT
>> + * @dev_priv: i915 device instance
>> + * @port: port for DSI if present
>> + *
>> + * Return true if DSI is present, and return the port in %port.
>> + */
>> +bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
>> + enum port *port)
>> +{
>> +union child_device_config *p_child;
>> +int i;
>> +
>> +for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
>> +p_child = dev_priv->vbt.child_dev + i;
>> +
>> +if (!(p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT))
>> +continue;
>> +
>> +switch (p_child->common.dvo_port) {
>> +case DVO_PORT_MIPIA:
>> +case DVO_PORT_MIPIB:
>> +case DVO_PORT_MIPIC:
>> +case DVO_PORT_MIPID:
>> +*port = p_child->common.dvo_port - DVO_PORT_MIPIA;
>> +return true;
>> +}
>> +}
> can we add platform check & vbt.has_mipi check ? it will avoid the need
> to loop through the array.
I'm actually going to remove has_mipi altogether as unnecessary
duplication of information. We run the loop very few times anyway. Also,
I don't want to duplicate the information about platforms, that stuff is
in intel_setup_outputs and in the encoder inits. Single point of truth.
> Also since all platforms so far (VLV/CHV/BXT) has only MIPI A & MIPI C
> is B & D needed here ? we can directly fail here for unsupported ports
> rather than in dsi_init as special check.
Agreed.
>> +
>> +return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> b/drivers/gpu/drm/i915/intel_dsi.c
>> index 378f879f4015..5b6ec567e3ce 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -1112,9 +1112,15 @@ void intel_dsi_init(struct drm_device *dev)
>> DRM_DEBUG_KMS("\n");
>>
>> /* There is no detection method for MIPI so rely on VBT */
>> -if (!dev_priv->vbt.has_mipi)
>> +if (!intel_bios_is_dsi_present(dev_priv, &port))
>> return;
>>
>> +if (port != PORT_A && port != PORT_C) {
>> +DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
>> + port_name(port));
>> +return;
>> +}
>> +
>> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>> } else {
>> @@ -1153,16 +1159,15 @@ void intel_dsi_init(struct drm_device *dev)
>> intel_connector->unregister = intel_connector_unregister;
>>
>> /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
>> -if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
>> -intel_encoder->crtc_mask = (1 << PIPE_A);
>> -
Re: [Intel-gfx] [PATCH RESEND 2/5] drm/i915: move VBT based LVDS presence check to intel_bios.c
On Mon, 08 Feb 2016, "Thulasimani, Sivakumar"
wrote:
> On 2/5/2016 4:06 PM, Jani Nikula wrote:
>> Hide knowledge about VBT child devices in intel_bios.c.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_bios.c | 50
>> drivers/gpu/drm/i915/intel_lvds.c | 53
>> +--
>> 3 files changed, 52 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 715f200cfbf5..d70ef71d2538 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3398,6 +3398,7 @@ extern void intel_i2c_reset(struct drm_device *dev);
>> int intel_bios_init(struct drm_i915_private *dev_priv);
>> bool intel_bios_is_valid_vbt(const void *buf, size_t size);
>> bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
>> +bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
>> *i2c_pin);
>>
>> /* intel_opregion.c */
>> #ifdef CONFIG_ACPI
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 2800ae50465a..f3f4f8e687cf 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1469,3 +1469,53 @@ bool intel_bios_is_tv_present(struct drm_i915_private
>> *dev_priv)
>>
>> return false;
>> }
>> +
>> +/**
>> + * intel_bios_is_lvds_present - is LVDS present in VBT
>> + * @dev_priv: i915 device instance
>> + * @i2c_pin:i2c pin for LVDS if present
>> + *
>> + * Return true if LVDS is present. If no child devices were parsed from VBT,
>> + * assume LVDS is present.
>> + */
>> +bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8
>> *i2c_pin)
>> +{
>> +int i;
>> +
>> +if (!dev_priv->vbt.child_dev_num)
>> +return true;
>> +
> we check if eDP is supported through following code before the call to
> this function. please add this check here so we can avoid vbt
> referencing for that.
Unfortunately, that would change the logic and I want to avoid making
that change at this point. For PCH split, we respect
dev_priv->vbt.edp_support, and bail out early, but otherwise we ignore
VBT if the BIOS has enabled LVDS anyway. I can only guess it's some
hackery to work around some weird setups out there.
BR,
Jani.
>
> intel_lvds.c
> 972 if (HAS_PCH_SPLIT(dev)) {
> 973 if ((lvds & LVDS_DETECTED) == 0)
> 974 return;
> 975 if (dev_priv->vbt.edp_support) {
> 976 DRM_DEBUG_KMS("disable LVDS for eDP
> support\n");
> 977 return;
> 978 }
> 979 }
>
> Sivakumar
>> +for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
>> +union child_device_config *uchild = dev_priv->vbt.child_dev + i;
>> +struct old_child_dev_config *child = &uchild->old;
>> +
>> +/* If the device type is not LFP, continue.
>> + * We have to check both the new identifiers as well as the
>> + * old for compatibility with some BIOSes.
>> + */
>> +if (child->device_type != DEVICE_TYPE_INT_LFP &&
>> +child->device_type != DEVICE_TYPE_LFP)
>> +continue;
>> +
>> +if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
>> +*i2c_pin = child->i2c_pin;
>> +
>> +/* However, we cannot trust the BIOS writers to populate
>> + * the VBT correctly. Since LVDS requires additional
>> + * information from AIM blocks, a non-zero addin offset is
>> + * a good indicator that the LVDS is actually present.
>> + */
>> +if (child->addin_offset)
>> +return true;
>> +
>> +/* But even then some BIOS writers perform some black magic
>> + * and instantiate the device without reference to any
>> + * additional data. Trust that if the VBT was written into
>> + * the OpRegion then they have validated the LVDS's existence.
>> + */
>> +if (dev_priv->opregion.vbt)
>> +return true;
>> +}
>> +
>> +return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
>> b/drivers/gpu/drm/i915/intel_lvds.c
>> index 0da0240caf81..80f8684e5137 100644
>> --- a/drivers/gpu/drm/i915/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/intel_lvds.c
>> @@ -772,57 +772,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
>> { } /* terminating entry */
>> };
>>
>> -/*
>> - * Enumerate the child dev array parsed from VBT to check whether
>> - * the LVDS is present.
>> - * If it is present, return 1.
>> - * If it is not present, return false.
>> - * If no child dev is parsed from VBT, it assumes that the LVDS is present.
>> -
[Intel-gfx] [PATCH v4] drm/i915/execlists: Move WA_TAIL_DWORDS to callee
From: Chris Wilson
Currently emit-request starts writing to the ring and reserves space
for a workaround to be emitted later whilst submitting the request. It
is easier to read if the caller only allocates sufficient space for
its access (then the reader can quickly verify that the ring begin
allocates the exact space for the number of dwords emitted) and closes
the access to the ring. During submit, if we need to add the workaround,
we can reacquire ring access, in the assurance that we reserved space
for ourselves when beginning the request.
v3:
Reinstated #define for WA_TAIL_DWORDS so we could accommodate GPUs
that required different amounts of padding, generalised NOOP fill
[Rodrigo Vivi], added W/A space to reserved amount and updated
code comments [Dave Gordon],
v4:
Made #define for WA_TAIL_DWORDS a function-type macro in case we
want different values on different platforms (or engines!). But
the current value is still the constant (2) on all platforms, so
this doesn't add any overhead.
Originally-by: Rodrigo Vivi
Rewritten-by: Chris Wilson
Further-tweaked-by: Dave Gordon
Signed-off-by: Dave Gordon
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Dave Gordon
Cc: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 84 +---
1 file changed, 53 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3a03646..f2f2d45 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -225,6 +225,17 @@ enum {
#define GEN8_CTX_ID_SHIFT 32
#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
+/*
+ * Reserve space for some NOOPs at the end of each request, to be used by
+ * a workaround for not being allowed to do lite restore with HEAD==TAIL
+ * (WaIdleLiteRestore).
+ *
+ * The number of NOOPs is the same constant on all current platforms that
+ * require this, but in theory could be a platform- or engine- specific
+ * value based on the request.
+ */
+#define WA_TAIL_DWORDS(request)(2)
+
static int intel_lr_context_pin(struct intel_context *ctx,
struct intel_engine_cs *engine);
static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
@@ -462,10 +473,9 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
*/
if (req0->elsp_submitted) {
/*
-* Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
-* as we resubmit the request. See gen8_emit_request()
-* for where we prepare the padding after the end of the
-* request.
+* Consume the W/A NOOPs to prevent ring:HEAD ==
req:TAIL as
+* we resubmit the request. See
intel_logical_ring_submit()
+* where we prepare the padding after the end of the
request.
*/
struct intel_ringbuffer *ringbuf;
@@ -752,33 +762,47 @@ static int logical_ring_wait_for_space(struct
drm_i915_gem_request *req,
}
/*
- * intel_logical_ring_advance_and_submit() - advance the tail and submit the
workload
- * @request: Request to advance the logical ringbuffer of.
+ * intel_logical_ring_submit() - submit the workload (to GuC or execlist queue)
+ * @request: Request to submit
*
- * The tail is updated in our logical ringbuffer struct, not in the actual
context. What
- * really happens during submission is that the context and current tail will
be placed
- * on a queue waiting for the ELSP to be ready to accept a new context
submission. At that
- * point, the tail *inside* the context is updated and the ELSP written to.
+ * The tail is updated in our logical ringbuffer struct, not in the actual
+ * context. What really happens during submission is that the context and
+ * current tail will be placed on a queue waiting for the ELSP to be ready
+ * to accept a new context submission. At that point, the tail *inside* the
+ * context is updated and the ELSP written to by the submitting agent i.e.
+ * either the driver (in execlist mode), or the GuC (in GuC-submission mode).
*/
static int
-intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
+intel_logical_ring_submit(struct drm_i915_gem_request *request)
{
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct drm_i915_private *dev_priv = request->i915;
struct intel_engine_cs *engine = request->ring;
+ int padding = WA_TAIL_DWORDS(request);
- intel_logical_ring_advance(ringbuf);
request->tail = ringbuf->tail;
/*
-* Here we add two extra NOOPs as padding to avoid
-* lite restore of a context with HEAD==TAIL.
-*
-* Caller must reserve WA_TAIL_DWORDS for us!
+* Fill in a few NOOPs after the end of the request proper,
+
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use atomic helpers for suspend.
On Tue, Feb 09, 2016 at 03:05:51PM +0100, Maarten Lankhorst wrote:
> Op 09-02-16 om 14:37 schreef Ville Syrjälä:
> > On Tue, Feb 09, 2016 at 01:52:22PM +0100, Maarten Lankhorst wrote:
> >> Instead of duplicating the functionality now that we no longer need
> >> to preserve dpll state we can move to using the upstream suspend helper.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/drm_atomic_helper.c | 3 +
> >> drivers/gpu/drm/i915/i915_drv.c | 8 ---
> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> drivers/gpu/drm/i915/intel_display.c | 117
> >> ---
> >> 4 files changed, 42 insertions(+), 87 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> >> b/drivers/gpu/drm/drm_atomic_helper.c
> >> index 2b430b05f35d..a2d3b094f27c 100644
> >> --- a/drivers/gpu/drm/drm_atomic_helper.c
> >> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> >> @@ -2102,6 +2102,9 @@ int drm_atomic_helper_resume(struct drm_device *dev,
> >>err = drm_atomic_commit(state);
> >>drm_modeset_unlock_all(dev);
> >>
> >> + if (err)
> >> + drm_atomic_state_free(state);
> >> +
> >>return err;
> >> }
> >> EXPORT_SYMBOL(drm_atomic_helper_resume);
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> >> b/drivers/gpu/drm/i915/i915_drv.c
> >> index 11d8414edbbe..fc9b552bfcd1 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.c
> >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> @@ -600,13 +600,7 @@ static int i915_drm_suspend(struct drm_device *dev)
> >>
> >>intel_suspend_gt_powersave(dev);
> >>
> >> - /*
> >> - * Disable CRTCs directly since we want to preserve sw state
> >> - * for _thaw. Also, power gate the CRTC power wells.
> >> - */
> >> - drm_modeset_lock_all(dev);
> >>intel_display_suspend(dev);
> >> - drm_modeset_unlock_all(dev);
> >>
> >>intel_dp_mst_suspend(dev);
> >>
> >> @@ -761,9 +755,7 @@ static int i915_drm_resume(struct drm_device *dev)
> >>dev_priv->display.hpd_irq_setup(dev);
> >>spin_unlock_irq(&dev_priv->irq_lock);
> >>
> >> - drm_modeset_lock_all(dev);
> >>intel_display_resume(dev);
> >> - drm_modeset_unlock_all(dev);
> >>
> >>intel_dp_mst_resume(dev);
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h
> >> index 8216665405eb..ef289514b97e 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1848,6 +1848,7 @@ struct drm_i915_private {
> >>
> >>enum modeset_restore modeset_restore;
> >>struct mutex modeset_restore_lock;
> >> + struct drm_atomic_state *modeset_restore_state;
> >>
> >>struct list_head vm_list; /* Global list of all address spaces */
> >>struct i915_gtt gtt; /* VM representing the global address space */
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index e496c130364d..4c91fd1c5222 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -6393,58 +6393,19 @@ static void intel_crtc_disable_noatomic(struct
> >> drm_crtc *crtc)
> >> */
> >> int intel_display_suspend(struct drm_device *dev)
> >> {
> >> - struct drm_mode_config *config = &dev->mode_config;
> >> - struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
> >> - struct drm_atomic_state *state;
> >> - struct drm_crtc *crtc;
> >> - unsigned crtc_mask = 0;
> >> - int ret = 0;
> >> -
> >> - if (WARN_ON(!ctx))
> >> - return 0;
> >> -
> >> - lockdep_assert_held(&ctx->ww_ctx);
> >> - state = drm_atomic_state_alloc(dev);
> >> - if (WARN_ON(!state))
> >> - return -ENOMEM;
> >> -
> >> - state->acquire_ctx = ctx;
> >> - state->allow_modeset = true;
> >> -
> >> - for_each_crtc(dev, crtc) {
> >> - struct drm_crtc_state *crtc_state =
> >> - drm_atomic_get_crtc_state(state, crtc);
> >> -
> >> - ret = PTR_ERR_OR_ZERO(crtc_state);
> >> - if (ret)
> >> - goto free;
> >> -
> >> - if (!crtc_state->active)
> >> - continue;
> >> -
> >> - crtc_state->active = false;
> >> - crtc_mask |= 1 << drm_crtc_index(crtc);
> >> - }
> >> -
> >> - if (crtc_mask) {
> >> - ret = drm_atomic_commit(state);
> >> -
> >> - if (!ret) {
> >> - for_each_crtc(dev, crtc)
> >> - if (crtc_mask & (1 << drm_crtc_index(crtc)))
> >> - crtc->state->active = true;
> >> -
> >> - return ret;
> >> - }
> >> - }
> >> + struct drm_i915_private *dev_priv = to_i915(dev);
> >> + int ret;
> >>
> >> -free:
> >> - if (ret)
> >> + dev_priv->modeset_restore_state = drm_atomic_helper_suspend(dev);
> >> + ret = PTR_ERR_OR_ZERO(dev_priv->modeset_restore_state);
> >> + if (ret) {
> >>DRM_ERROR("Suspending crtc's failed with %i\n", ret);
> >> - drm_atomic_st
[Intel-gfx] [PATCH i-g-t] lib: Fix build when vc4 headers are present
Automake seems to not like variable assignments indented with tabs.
Signed-off-by: Tomeu Vizoso
Fixes: 9e5478dc4345 ("lib: Only compile igt_vc4 is we have it")
---
lib/Makefile.am | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 460e0046e00f..e3a456bacaf3 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -9,9 +9,9 @@ noinst_LTLIBRARIES = libintel_tools.la
noinst_HEADERS = check-ndebug.h
if HAVE_VC4
- libintel_tools_la_SOURCES +=\
- igt_vc4.c \
- igt_vc4.h
+libintel_tools_la_SOURCES += \
+igt_vc4.c \
+igt_vc4.h
endif
AM_CPPFLAGS = -I$(top_srcdir)
--
2.5.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v3] lib/igt_core.c: Expand --run-subtest functionality.
On 04/02/16 12:06, Derek Morton wrote: Added extended wildcard support when specifying --run-subtest. Wildcard format is as specified in rfc3977 and the uwildmat() implementation is taken from libinn. See https://tools.ietf.org/html/rfc3977#section-4 for a description of allowed wildcard expressions. v2: Use comma as list separator (Ville Syrjala) support both ^ and ! as not operators (Dave Gordon) v3: Updated to use uwildmat() (Dave Gordon) Signed-off-by: Derek Morton --- COPYING | 21 +++ lib/Makefile.sources| 2 + lib/igt_core.c | 17 +- lib/uwildmat/uwildmat.c | 474 lib/uwildmat/uwildmat.h | 24 +++ 5 files changed, 536 insertions(+), 2 deletions(-) create mode 100644 lib/uwildmat/uwildmat.c create mode 100644 lib/uwildmat/uwildmat.h LGTM. Reviewed-by: Dave Gordon ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use atomic helpers for suspend.
Op 09-02-16 om 14:37 schreef Ville Syrjälä:
> On Tue, Feb 09, 2016 at 01:52:22PM +0100, Maarten Lankhorst wrote:
>> Instead of duplicating the functionality now that we no longer need
>> to preserve dpll state we can move to using the upstream suspend helper.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/drm_atomic_helper.c | 3 +
>> drivers/gpu/drm/i915/i915_drv.c | 8 ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 117
>> ---
>> 4 files changed, 42 insertions(+), 87 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
>> b/drivers/gpu/drm/drm_atomic_helper.c
>> index 2b430b05f35d..a2d3b094f27c 100644
>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>> @@ -2102,6 +2102,9 @@ int drm_atomic_helper_resume(struct drm_device *dev,
>> err = drm_atomic_commit(state);
>> drm_modeset_unlock_all(dev);
>>
>> +if (err)
>> +drm_atomic_state_free(state);
>> +
>> return err;
>> }
>> EXPORT_SYMBOL(drm_atomic_helper_resume);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 11d8414edbbe..fc9b552bfcd1 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -600,13 +600,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>>
>> intel_suspend_gt_powersave(dev);
>>
>> -/*
>> - * Disable CRTCs directly since we want to preserve sw state
>> - * for _thaw. Also, power gate the CRTC power wells.
>> - */
>> -drm_modeset_lock_all(dev);
>> intel_display_suspend(dev);
>> -drm_modeset_unlock_all(dev);
>>
>> intel_dp_mst_suspend(dev);
>>
>> @@ -761,9 +755,7 @@ static int i915_drm_resume(struct drm_device *dev)
>> dev_priv->display.hpd_irq_setup(dev);
>> spin_unlock_irq(&dev_priv->irq_lock);
>>
>> -drm_modeset_lock_all(dev);
>> intel_display_resume(dev);
>> -drm_modeset_unlock_all(dev);
>>
>> intel_dp_mst_resume(dev);
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 8216665405eb..ef289514b97e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1848,6 +1848,7 @@ struct drm_i915_private {
>>
>> enum modeset_restore modeset_restore;
>> struct mutex modeset_restore_lock;
>> +struct drm_atomic_state *modeset_restore_state;
>>
>> struct list_head vm_list; /* Global list of all address spaces */
>> struct i915_gtt gtt; /* VM representing the global address space */
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index e496c130364d..4c91fd1c5222 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6393,58 +6393,19 @@ static void intel_crtc_disable_noatomic(struct
>> drm_crtc *crtc)
>> */
>> int intel_display_suspend(struct drm_device *dev)
>> {
>> -struct drm_mode_config *config = &dev->mode_config;
>> -struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
>> -struct drm_atomic_state *state;
>> -struct drm_crtc *crtc;
>> -unsigned crtc_mask = 0;
>> -int ret = 0;
>> -
>> -if (WARN_ON(!ctx))
>> -return 0;
>> -
>> -lockdep_assert_held(&ctx->ww_ctx);
>> -state = drm_atomic_state_alloc(dev);
>> -if (WARN_ON(!state))
>> -return -ENOMEM;
>> -
>> -state->acquire_ctx = ctx;
>> -state->allow_modeset = true;
>> -
>> -for_each_crtc(dev, crtc) {
>> -struct drm_crtc_state *crtc_state =
>> -drm_atomic_get_crtc_state(state, crtc);
>> -
>> -ret = PTR_ERR_OR_ZERO(crtc_state);
>> -if (ret)
>> -goto free;
>> -
>> -if (!crtc_state->active)
>> -continue;
>> -
>> -crtc_state->active = false;
>> -crtc_mask |= 1 << drm_crtc_index(crtc);
>> -}
>> -
>> -if (crtc_mask) {
>> -ret = drm_atomic_commit(state);
>> -
>> -if (!ret) {
>> -for_each_crtc(dev, crtc)
>> -if (crtc_mask & (1 << drm_crtc_index(crtc)))
>> -crtc->state->active = true;
>> -
>> -return ret;
>> -}
>> -}
>> +struct drm_i915_private *dev_priv = to_i915(dev);
>> +int ret;
>>
>> -free:
>> -if (ret)
>> +dev_priv->modeset_restore_state = drm_atomic_helper_suspend(dev);
>> +ret = PTR_ERR_OR_ZERO(dev_priv->modeset_restore_state);
>> +if (ret) {
>> DRM_ERROR("Suspending crtc's failed with %i\n", ret);
>> -drm_atomic_state_free(state);
>> +dev_priv->modeset_restore_state = NULL;
>> +}
> I would use a local state pointer and only assign it to
> modeset_restore_state once we know it's good.
>
>> retu
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use atomic helpers for suspend.
On Tue, Feb 09, 2016 at 01:52:22PM +0100, Maarten Lankhorst wrote:
> Instead of duplicating the functionality now that we no longer need
> to preserve dpll state we can move to using the upstream suspend helper.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/drm_atomic_helper.c | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 8 ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 117
> ---
> 4 files changed, 42 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 2b430b05f35d..a2d3b094f27c 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2102,6 +2102,9 @@ int drm_atomic_helper_resume(struct drm_device *dev,
> err = drm_atomic_commit(state);
> drm_modeset_unlock_all(dev);
>
> + if (err)
> + drm_atomic_state_free(state);
> +
> return err;
> }
> EXPORT_SYMBOL(drm_atomic_helper_resume);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 11d8414edbbe..fc9b552bfcd1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -600,13 +600,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> intel_suspend_gt_powersave(dev);
>
> - /*
> - * Disable CRTCs directly since we want to preserve sw state
> - * for _thaw. Also, power gate the CRTC power wells.
> - */
> - drm_modeset_lock_all(dev);
> intel_display_suspend(dev);
> - drm_modeset_unlock_all(dev);
>
> intel_dp_mst_suspend(dev);
>
> @@ -761,9 +755,7 @@ static int i915_drm_resume(struct drm_device *dev)
> dev_priv->display.hpd_irq_setup(dev);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - drm_modeset_lock_all(dev);
> intel_display_resume(dev);
> - drm_modeset_unlock_all(dev);
>
> intel_dp_mst_resume(dev);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665405eb..ef289514b97e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1848,6 +1848,7 @@ struct drm_i915_private {
>
> enum modeset_restore modeset_restore;
> struct mutex modeset_restore_lock;
> + struct drm_atomic_state *modeset_restore_state;
>
> struct list_head vm_list; /* Global list of all address spaces */
> struct i915_gtt gtt; /* VM representing the global address space */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e496c130364d..4c91fd1c5222 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6393,58 +6393,19 @@ static void intel_crtc_disable_noatomic(struct
> drm_crtc *crtc)
> */
> int intel_display_suspend(struct drm_device *dev)
> {
> - struct drm_mode_config *config = &dev->mode_config;
> - struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
> - struct drm_atomic_state *state;
> - struct drm_crtc *crtc;
> - unsigned crtc_mask = 0;
> - int ret = 0;
> -
> - if (WARN_ON(!ctx))
> - return 0;
> -
> - lockdep_assert_held(&ctx->ww_ctx);
> - state = drm_atomic_state_alloc(dev);
> - if (WARN_ON(!state))
> - return -ENOMEM;
> -
> - state->acquire_ctx = ctx;
> - state->allow_modeset = true;
> -
> - for_each_crtc(dev, crtc) {
> - struct drm_crtc_state *crtc_state =
> - drm_atomic_get_crtc_state(state, crtc);
> -
> - ret = PTR_ERR_OR_ZERO(crtc_state);
> - if (ret)
> - goto free;
> -
> - if (!crtc_state->active)
> - continue;
> -
> - crtc_state->active = false;
> - crtc_mask |= 1 << drm_crtc_index(crtc);
> - }
> -
> - if (crtc_mask) {
> - ret = drm_atomic_commit(state);
> -
> - if (!ret) {
> - for_each_crtc(dev, crtc)
> - if (crtc_mask & (1 << drm_crtc_index(crtc)))
> - crtc->state->active = true;
> -
> - return ret;
> - }
> - }
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
>
> -free:
> - if (ret)
> + dev_priv->modeset_restore_state = drm_atomic_helper_suspend(dev);
> + ret = PTR_ERR_OR_ZERO(dev_priv->modeset_restore_state);
> + if (ret) {
> DRM_ERROR("Suspending crtc's failed with %i\n", ret);
> - drm_atomic_state_free(state);
> + dev_priv->modeset_restore_state = NULL;
> + }
I would use a local state pointer and only assign it to
modeset_restore_state once we know it's good.
> return ret;
> }
>
> +
Spurious newline.
> void intel_encoder_destroy(struct drm_encoder *encoder)
> {
> struct
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)
On 2/9/2016 6:41 PM, Adebisi, YetundeX wrote:
-Original Message-
From: Thulasimani, Sivakumar
Sent: Monday, February 08, 2016 8:57 AM
To: Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using
DPCD for eDP connectors (v6)
On 2/5/2016 5:48 PM, Yetunde Adebisi wrote:
This patch adds support for eDP backlight control using DPCD registers
to backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets
up function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd
v3: Correct some formatting mistakes
v4: Updated to use AUX backlight control if PWM control is not possible
(Jani)
v5: Moved call to initialize backlight registers to
dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before
setting
up AUX backlight control. To fix BLM_PWM_ENABLE igt test warnings on
bdw_ultra
This patch depends on http://patchwork.freedesktop.org/patch/64253/
Cc: Bob Paauwe
Cc: Jani Nikula
Acked-by: Jesse Barnes
Signed-off-by: Yetunde Adebisi
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 ++-
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170
++
drivers/gpu/drm/i915/intel_drv.h | 6 +
drivers/gpu/drm/i915/intel_panel.c| 4 +
5 files changed, 192 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
diff --git a/drivers/gpu/drm/i915/Makefile
b/drivers/gpu/drm/i915/Makefile index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
dvo_tfp410.o \
intel_crt.o \
intel_ddi.o \
+ intel_dp_aux_backlight.o \
intel_dp_link_training.o \
intel_dp_mst.o \
intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c index a073f04..9f8672e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct
intel_encoder *encoder)
* Sinks are *supposed* to come up within 1ms from an off state, but
we're also
* supposed to retry 3 times per the spec.
*/
-static ssize_t
+ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size)
{
@@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint8_t rev;
if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp-
dpcd,
sizeof(intel_dp->dpcd)) < 0) @@ -3886,6
+3885,15 @@
intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" :
"not supported");
}
+
+ /* Read the eDP Display control capabilities registers */
+ memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp-
edp_dpcd));
+ if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+ (intel_dp_dpcd_read_wake(&intel_dp->aux,
DP_EDP_DPCD_REV,
+ intel_dp->edp_dpcd,
sizeof(intel_dp->edp_dpcd)) ==
+
sizeof(intel_dp->edp_dpcd)))
+ DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int)
sizeof(intel_dp->edp_dpcd),
+ intel_dp->edp_dpcd);
}
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink
%s\n", @@
-3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
/* Intermediate frequency support */
- if (is_edp(intel_dp) &&
- (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
- (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
&rev, 1) == 1) &&
- (rev >= 0x03)) { /* eDp v1.4 or higher */
+ if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp
+v1.4 or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 000..a5361d6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,170 @@
+/*
+ * Co
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Clear shared dpll based on old state.
On Tue, Feb 09, 2016 at 01:52:21PM +0100, Maarten Lankhorst wrote:
> Atomic resume was preserving the dpll state because it was required
> for clearing pll state correctly. If we look at the old_crtc_state
> for pll to clear this is not needed and the hack can be removed.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 19 +++
> 1 file changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3b6bd6e9f7ae..e496c130364d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13093,8 +13093,6 @@ static void intel_modeset_clear_plls(struct
> drm_atomic_state *state)
> struct drm_device *dev = state->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_shared_dpll_config *shared_dpll = NULL;
> - struct intel_crtc *intel_crtc;
> - struct intel_crtc_state *intel_crtc_state;
> struct drm_crtc *crtc;
> struct drm_crtc_state *crtc_state;
> int i;
> @@ -13103,16 +13101,16 @@ static void intel_modeset_clear_plls(struct
> drm_atomic_state *state)
> return;
>
> for_each_crtc_in_state(state, crtc, crtc_state, i) {
> - int dpll;
> -
> - intel_crtc = to_intel_crtc(crtc);
> - intel_crtc_state = to_intel_crtc_state(crtc_state);
> - dpll = intel_crtc_state->shared_dpll;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int dpll = to_intel_crtc_state(crtc->state)->shared_dpll;
>
> - if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
> + if (!needs_modeset(crtc_state))
> continue;
>
> - intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
> + to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE;
> +
> + if (dpll == DPLL_ID_PRIVATE)
> + continue;
Maybe this should be called old_dpll or something for a bit of extra
clarity? Anyway this makes sense to me so
Reviewed-by: Ville Syrjälä
>
> if (!shared_dpll)
> shared_dpll = intel_atomic_get_shared_dpll_state(state);
> @@ -15922,9 +15920,6 @@ void intel_display_resume(struct drm_device *dev)
>
> state->acquire_ctx = dev->mode_config.acquire_ctx;
>
> - /* preserve complete old state, including dpll */
> - intel_atomic_get_shared_dpll_state(state);
> -
> for_each_crtc(dev, crtc) {
> struct drm_crtc_state *crtc_state =
> drm_atomic_get_crtc_state(state, crtc);
> --
> 2.1.0
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)
> -Original Message-
> From: Thulasimani, Sivakumar
> Sent: Monday, February 08, 2016 8:57 AM
> To: Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using
> DPCD for eDP connectors (v6)
>
>
>
> On 2/5/2016 5:48 PM, Yetunde Adebisi wrote:
> > This patch adds support for eDP backlight control using DPCD registers
> > to backlight hooks in intel_panel.
> >
> > It checks for backlight control over AUX channel capability and sets
> > up function pointers to get and set the backlight brightness level if
> > supported.
> >
> > v2: Moved backlight functions from intel_dp.c into a new file
> > intel_dp_aux_backlight.c. Also moved reading of eDP display control
> > registers to intel_dp_get_dpcd
> >
> > v3: Correct some formatting mistakes
> >
> > v4: Updated to use AUX backlight control if PWM control is not possible
> > (Jani)
> > v5: Moved call to initialize backlight registers to
> > dp_aux_setup_backlight
> > v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before
> setting
> > up AUX backlight control. To fix BLM_PWM_ENABLE igt test warnings on
> > bdw_ultra
> >
> > This patch depends on http://patchwork.freedesktop.org/patch/64253/
> >
> > Cc: Bob Paauwe
> > Cc: Jani Nikula
> > Acked-by: Jesse Barnes
> > Signed-off-by: Yetunde Adebisi
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/intel_dp.c | 17 ++-
> > drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170
> ++
> > drivers/gpu/drm/i915/intel_drv.h | 6 +
> > drivers/gpu/drm/i915/intel_panel.c| 4 +
> > 5 files changed, 192 insertions(+), 6 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 0851de07..41250cc 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
> > dvo_tfp410.o \
> > intel_crt.o \
> > intel_ddi.o \
> > + intel_dp_aux_backlight.o \
> > intel_dp_link_training.o \
> > intel_dp_mst.o \
> > intel_dp.o \
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index a073f04..9f8672e 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct
> intel_encoder *encoder)
> >* Sinks are *supposed* to come up within 1ms from an off state, but
> we're also
> >* supposed to retry 3 times per the spec.
> >*/
> > -static ssize_t
> > +ssize_t
> > intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
> > void *buffer, size_t size)
> > {
> > @@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct drm_device *dev = dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > - uint8_t rev;
> >
> > if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp-
> >dpcd,
> > sizeof(intel_dp->dpcd)) < 0) @@ -3886,6
> +3885,15 @@
> > intel_dp_get_dpcd(struct intel_dp *intel_dp)
> > DRM_DEBUG_KMS("PSR2 %s on sink",
> > dev_priv->psr.psr2_support ? "supported" :
> "not supported");
> > }
> > +
> > + /* Read the eDP Display control capabilities registers */
> > + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp-
> >edp_dpcd));
> > + if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
> DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> > + (intel_dp_dpcd_read_wake(&intel_dp->aux,
> DP_EDP_DPCD_REV,
> > + intel_dp->edp_dpcd,
> sizeof(intel_dp->edp_dpcd)) ==
> > +
> sizeof(intel_dp->edp_dpcd)))
> > + DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int)
> sizeof(intel_dp->edp_dpcd),
> > + intel_dp->edp_dpcd);
> > }
> >
> > DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink
> %s\n", @@
> > -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> > yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
> >
> > /* Intermediate frequency support */
> > - if (is_edp(intel_dp) &&
> > - (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
> DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> > - (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> &rev, 1) == 1) &&
> > - (rev >= 0x03)) { /* eDp v1.4 or higher */
> > + if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp
> > +v1.4 or higher */
> > __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> > int i;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp_
[Intel-gfx] [PATCH 1/3] drm/i915: Clear shared dpll based on old state.
Atomic resume was preserving the dpll state because it was required
for clearing pll state correctly. If we look at the old_crtc_state
for pll to clear this is not needed and the hack can be removed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b6bd6e9f7ae..e496c130364d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13093,8 +13093,6 @@ static void intel_modeset_clear_plls(struct
drm_atomic_state *state)
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_shared_dpll_config *shared_dpll = NULL;
- struct intel_crtc *intel_crtc;
- struct intel_crtc_state *intel_crtc_state;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int i;
@@ -13103,16 +13101,16 @@ static void intel_modeset_clear_plls(struct
drm_atomic_state *state)
return;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
- int dpll;
-
- intel_crtc = to_intel_crtc(crtc);
- intel_crtc_state = to_intel_crtc_state(crtc_state);
- dpll = intel_crtc_state->shared_dpll;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int dpll = to_intel_crtc_state(crtc->state)->shared_dpll;
- if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
+ if (!needs_modeset(crtc_state))
continue;
- intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
+ to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE;
+
+ if (dpll == DPLL_ID_PRIVATE)
+ continue;
if (!shared_dpll)
shared_dpll = intel_atomic_get_shared_dpll_state(state);
@@ -15922,9 +15920,6 @@ void intel_display_resume(struct drm_device *dev)
state->acquire_ctx = dev->mode_config.acquire_ctx;
- /* preserve complete old state, including dpll */
- intel_atomic_get_shared_dpll_state(state);
-
for_each_crtc(dev, crtc) {
struct drm_crtc_state *crtc_state =
drm_atomic_get_crtc_state(state, crtc);
--
2.1.0
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[Intel-gfx] [PATCH 3/3] drm/i915: Use atomic state to obtain load detection crtc, v3.
Instead of restoring dpms and a flag for whether a temp fb is allocated
duplicate
an atomic state before the new state is committed, and commit it the old state
in intel_release_load_detect_pipe.
Changes since v1:
- Use a real atomic state. (Ville)
Changes since v2:
- Do not preserve shared_dpll any more, no need to do so. (Ville)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 132 ++-
drivers/gpu/drm/i915/intel_drv.h | 4 +-
2 files changed, 54 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4c91fd1c5222..ad6d23c17d48 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10332,6 +10332,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
if (obj->base.size < mode->vdisplay * fb->pitches[0])
return NULL;
+ drm_framebuffer_reference(fb);
return fb;
#else
return NULL;
@@ -10387,7 +10388,7 @@ bool intel_get_load_detect_pipe(struct drm_connector
*connector,
struct drm_device *dev = encoder->dev;
struct drm_framebuffer *fb;
struct drm_mode_config *config = &dev->mode_config;
- struct drm_atomic_state *state = NULL;
+ struct drm_atomic_state *state = NULL, *restore_state = NULL;
struct drm_connector_state *connector_state;
struct intel_crtc_state *crtc_state;
int ret, i = -1;
@@ -10396,6 +10397,8 @@ bool intel_get_load_detect_pipe(struct drm_connector
*connector,
connector->base.id, connector->name,
encoder->base.id, encoder->name);
+ old->restore_state = NULL;
+
retry:
ret = drm_modeset_lock(&config->connection_mutex, ctx);
if (ret)
@@ -10412,24 +10415,15 @@ retry:
*/
/* See if we already have a CRTC for this connector */
- if (encoder->crtc) {
- crtc = encoder->crtc;
+ if (connector->state->crtc) {
+ crtc = connector->state->crtc;
ret = drm_modeset_lock(&crtc->mutex, ctx);
if (ret)
goto fail;
- ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
- if (ret)
- goto fail;
-
- old->dpms_mode = connector->dpms;
- old->load_detect_temp = false;
/* Make sure the crtc and connector are running */
- if (connector->dpms != DRM_MODE_DPMS_ON)
- connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
-
- return true;
+ goto found;
}
/* Find an unused one (if possible) */
@@ -10437,8 +10431,15 @@ retry:
i++;
if (!(encoder->possible_crtcs & (1 << i)))
continue;
- if (possible_crtc->state->enable)
+
+ ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
+ if (ret)
+ goto fail;
+
+ if (possible_crtc->state->enable) {
+ drm_modeset_unlock(&possible_crtc->mutex);
continue;
+ }
crtc = possible_crtc;
break;
@@ -10452,23 +10453,22 @@ retry:
goto fail;
}
- ret = drm_modeset_lock(&crtc->mutex, ctx);
- if (ret)
- goto fail;
+found:
+ intel_crtc = to_intel_crtc(crtc);
+
ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
if (ret)
goto fail;
- intel_crtc = to_intel_crtc(crtc);
- old->dpms_mode = connector->dpms;
- old->load_detect_temp = true;
- old->release_fb = NULL;
-
state = drm_atomic_state_alloc(dev);
- if (!state)
- return false;
+ restore_state = drm_atomic_state_alloc(dev);
+ if (!state || !restore_state) {
+ ret = -ENOMEM;
+ goto fail;
+ }
state->acquire_ctx = ctx;
+ restore_state->acquire_ctx = ctx;
connector_state = drm_atomic_get_connector_state(state, connector);
if (IS_ERR(connector_state)) {
@@ -10476,7 +10476,9 @@ retry:
goto fail;
}
- connector_state->crtc = crtc;
+ ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
+ if (ret)
+ goto fail;
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
if (IS_ERR(crtc_state)) {
@@ -10500,7 +10502,6 @@ retry:
if (fb == NULL) {
DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
- old->release_fb = fb;
} else
DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
if (IS_ERR(fb)) {
@@ -10512,15 +10513,28 @@ retry:
if (ret)
[Intel-gfx] [PATCH 2/3] drm/i915: Use atomic helpers for suspend.
Instead of duplicating the functionality now that we no longer need
to preserve dpll state we can move to using the upstream suspend helper.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic_helper.c | 3 +
drivers/gpu/drm/i915/i915_drv.c | 8 ---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 117 ---
4 files changed, 42 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 2b430b05f35d..a2d3b094f27c 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2102,6 +2102,9 @@ int drm_atomic_helper_resume(struct drm_device *dev,
err = drm_atomic_commit(state);
drm_modeset_unlock_all(dev);
+ if (err)
+ drm_atomic_state_free(state);
+
return err;
}
EXPORT_SYMBOL(drm_atomic_helper_resume);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 11d8414edbbe..fc9b552bfcd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -600,13 +600,7 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_suspend_gt_powersave(dev);
- /*
-* Disable CRTCs directly since we want to preserve sw state
-* for _thaw. Also, power gate the CRTC power wells.
-*/
- drm_modeset_lock_all(dev);
intel_display_suspend(dev);
- drm_modeset_unlock_all(dev);
intel_dp_mst_suspend(dev);
@@ -761,9 +755,7 @@ static int i915_drm_resume(struct drm_device *dev)
dev_priv->display.hpd_irq_setup(dev);
spin_unlock_irq(&dev_priv->irq_lock);
- drm_modeset_lock_all(dev);
intel_display_resume(dev);
- drm_modeset_unlock_all(dev);
intel_dp_mst_resume(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665405eb..ef289514b97e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1848,6 +1848,7 @@ struct drm_i915_private {
enum modeset_restore modeset_restore;
struct mutex modeset_restore_lock;
+ struct drm_atomic_state *modeset_restore_state;
struct list_head vm_list; /* Global list of all address spaces */
struct i915_gtt gtt; /* VM representing the global address space */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e496c130364d..4c91fd1c5222 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6393,58 +6393,19 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc)
*/
int intel_display_suspend(struct drm_device *dev)
{
- struct drm_mode_config *config = &dev->mode_config;
- struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
- struct drm_atomic_state *state;
- struct drm_crtc *crtc;
- unsigned crtc_mask = 0;
- int ret = 0;
-
- if (WARN_ON(!ctx))
- return 0;
-
- lockdep_assert_held(&ctx->ww_ctx);
- state = drm_atomic_state_alloc(dev);
- if (WARN_ON(!state))
- return -ENOMEM;
-
- state->acquire_ctx = ctx;
- state->allow_modeset = true;
-
- for_each_crtc(dev, crtc) {
- struct drm_crtc_state *crtc_state =
- drm_atomic_get_crtc_state(state, crtc);
-
- ret = PTR_ERR_OR_ZERO(crtc_state);
- if (ret)
- goto free;
-
- if (!crtc_state->active)
- continue;
-
- crtc_state->active = false;
- crtc_mask |= 1 << drm_crtc_index(crtc);
- }
-
- if (crtc_mask) {
- ret = drm_atomic_commit(state);
-
- if (!ret) {
- for_each_crtc(dev, crtc)
- if (crtc_mask & (1 << drm_crtc_index(crtc)))
- crtc->state->active = true;
-
- return ret;
- }
- }
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
-free:
- if (ret)
+ dev_priv->modeset_restore_state = drm_atomic_helper_suspend(dev);
+ ret = PTR_ERR_OR_ZERO(dev_priv->modeset_restore_state);
+ if (ret) {
DRM_ERROR("Suspending crtc's failed with %i\n", ret);
- drm_atomic_state_free(state);
+ dev_priv->modeset_restore_state = NULL;
+ }
return ret;
}
+
void intel_encoder_destroy(struct drm_encoder *encoder)
{
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
@@ -15909,51 +15870,49 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
void intel_display_resume(struct drm_device *dev)
{
- struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
- struct intel_connector *conn;
- struct intel_plane *p
[Intel-gfx] ✗ Fi.CI.BAT: failure for Pipe level color management (rev4)
== Summary == Series 2720v4 Pipe level color management http://patchwork.freedesktop.org/api/1.0/series/2720/revisions/4/mbox/ Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE Subgroup basic-flip-vs-wf_vblank: fail -> PASS (snb-x220t) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (skl-i5k-2) Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (skl-i5k-2) pass -> INCOMPLETE (hsw-gt2) Test pm_rpm: Subgroup basic-pci-d3-state: fail -> PASS (hsw-brixbox) Subgroup basic-rte: dmesg-warn -> PASS (bsw-nuc-2) pass -> DMESG-WARN (byt-nuc) UNSTABLE bdw-nuci7total:161 pass:152 dwarn:0 dfail:0 fail:0 skip:9 bdw-ultratotal:164 pass:152 dwarn:0 dfail:0 fail:0 skip:12 bsw-nuc-2total:164 pass:136 dwarn:0 dfail:0 fail:0 skip:28 byt-nuc total:164 pass:140 dwarn:1 dfail:0 fail:0 skip:23 hsw-brixbox total:164 pass:151 dwarn:0 dfail:0 fail:0 skip:13 hsw-gt2 total:143 pass:134 dwarn:0 dfail:0 fail:0 skip:8 ilk-hp8440p total:164 pass:115 dwarn:1 dfail:0 fail:0 skip:48 ivb-t430stotal:164 pass:150 dwarn:0 dfail:0 fail:0 skip:14 skl-i5k-2total:164 pass:149 dwarn:1 dfail:0 fail:0 skip:14 snb-dellxps total:164 pass:142 dwarn:0 dfail:0 fail:0 skip:22 snb-x220ttotal:164 pass:142 dwarn:0 dfail:0 fail:1 skip:21 Results at /archive/results/CI_IGT_test/Patchwork_1381/ d033b3eb38d06039cad3c78109f6e666c3fb9cf4 drm-intel-nightly: 2016y-02m-09d-10h-52m-16s UTC integration manifest 2fdbc2f724c39d260b1808a6cc5c754c66161d5b drm/i915: Implement color management on chv f0c1f9c7ee77496b458f4bf7b3534496cc08553f drm/i915: Implement color management on bdw/skl/bxt/kbl 0b0c401d55c9239b042dec968d5fbe254ea6f121 drm/i915: enable legacy palette for pipe C 819b94e366ff32cc5ae122d1fb57c350bec21311 drm/i915: enable CSC for pipe C 81d5e67528c425de15f7da75036673f84b8f08e2 drm: introduce color correction properties 7dd958c5472e69591b965a2d67f5a904f0b32f87 drm/i915: Extract out gamma table and CSC to their own file ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm: introduce color correction properties
Patch based on a previous series by Shashank Sharma.
v2: Register LUT size properties as range
v3: Fix round in drm_color_lut_get_value() helper
More docs on how degamma/gamma properties are used
v4: Update contributors
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
Documentation/DocBook/gpu.tmpl | 58 +++-
drivers/gpu/drm/drm_atomic.c| 102 +++-
drivers/gpu/drm/drm_atomic_helper.c | 10
drivers/gpu/drm/drm_crtc.c | 35 +
drivers/gpu/drm/drm_crtc_helper.c | 33
include/drm/drm_crtc.h | 44 +++-
include/drm/drm_crtc_helper.h | 3 ++
include/uapi/drm/drm_mode.h | 15 ++
8 files changed, 295 insertions(+), 5 deletions(-)
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index fe6b36a..7c49a92 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -1816,7 +1816,7 @@ void intel_crt_init(struct drm_device *dev)
Description/Restrictions
- DRM
+ DRM
Generic
“rotation”
BITMASK
@@ -2068,7 +2068,7 @@ void intel_crt_init(struct drm_device *dev)
property to suggest an Y offset for a connector
- Optional
+ Optional
“scaling mode”
ENUM
{ "None", "Full", "Center", "Full aspect" }
@@ -2092,6 +2092,60 @@ void intel_crt_init(struct drm_device *dev)
TBD
+ “DEGAMMA_LUT”
+ BLOB
+ 0
+ CRTC
+ DRM property to set the degamma LUT mapping
+ pixel data from the framebuffer before it is given to the
+ transformation matrix. The data is an interpreted as an array
+ of struct drm_color_lut elements. Hardware might choose not to
+ use the full precision of the LUT elements nor use all the
+ elements of the LUT (for example the hardware might choose to
+ interpolate between LUT[0] and LUT[4]).
+
+
+ “DEGAMMA_LUT_SIZE”
+ RANGE | IMMUTABLE
+ Min=0, Max=UINT_MAX
+ CRTC
+ DRM property to gives the size of the LUT to
+ be set on the DEGAMMA_LUT property (the size depends on the
+ underlying hardware).
+
+
+ “CTM_MATRIX”
+ BLOB
+ 0
+ CRTC
+ DRM property to set the transformation
+ matrix apply to pixel data after the lookup through the
+ degamma LUT and before the lookup through the gamma LUT. The
+ data is an interpreted as a struct drm_color_ctm.
+
+
+ “GAMMA_LUT”
+ BLOB
+ 0
+ CRTC
+ DRM property to set the gamma LUT mapping
+ pixel data after to the transformation matrix to data sent to
+ the connector. The data is an interpreted as an array
+ of struct drm_color_lut elements. Hardware might choose not to
+ use the full precision of the LUT elements nor use all the
+ elements of the LUT (for example the hardware might choose to
+ interpolate between LUT[0] and LUT[4]).
+
+
+ “GAMMA_LUT_SIZE”
+ RANGE | IMMUTABLE
+ Min=0, Max=UINT_MAX
+ CRTC
+ DRM property to gives the size of the LUT to
+ be set on the GAMMA_LUT property (the size depends on the
+ underlying hardware).
+
+
i915
Generic
"Broadcast RGB"
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8fb469c..7507762 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
/**
@@ -388,6 +389,58 @@ int drm_atomic_set_mode_prop_for_crtc(struct
drm_crtc_state *state,
EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/**
+ * drm_atomic_replace_property_blob - replace a blob property
+ * @blob: a pointer to the member blob to be replaced
+ * @new_blob: the new blob to replace with
+ * @expected_size: the expected size of the new blob
+ * @replaced: whether the blob has been replaced
+ *
+ * RETURNS:
+ * Zero on success, error code on failure
+ */
+static int
+drm_atomic_replace_property_blob(struct drm_property_blob **blob,
+struct drm_property_blob *new_blob,
+size_t expected_size,
+bool *replaced)
+{
+ struct drm_property_blob *old_blob = *blob;
+
+ if (old_blob == new_blob)
+ return 0;
+
+ if (new_blob != NULL && new_blob->length != expected_size)
+ return -EINVAL;
+
+ if (old_blob != NULL)
+ drm_property_unreference_blob(old_blob);
+ *blob = new_blob;
+ *rep
[Intel-gfx] [PATCH 3/6] drm/i915: enable CSC for pipe C
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/i915_reg.h | 40 +++-
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 188ad5d..7ba8a99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7634,19 +7634,33 @@ enum skl_disp_power_wells {
#define _PIPE_B_CSC_POSTOFF_ME 0x49144
#define _PIPE_B_CSC_POSTOFF_LO 0x49148
-#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
-#define PIPE_CSC_COEFF_BY(pipe)_MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
-#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
-#define PIPE_CSC_COEFF_BU(pipe)_MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
-#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
-#define PIPE_CSC_COEFF_BV(pipe)_MMIO_PIPE(pipe,
_PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
-#define PIPE_CSC_MODE(pipe)_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE,
_PIPE_B_CSC_MODE)
-#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI,
_PIPE_B_CSC_PREOFF_HI)
-#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME,
_PIPE_B_CSC_PREOFF_ME)
-#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO,
_PIPE_B_CSC_PREOFF_LO)
-#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
-#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
-#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
+#define _PIPE_C_CSC_COEFF_RY_GY0x49210
+#define _PIPE_C_CSC_COEFF_BY 0x49214
+#define _PIPE_C_CSC_COEFF_RU_GU0x49218
+#define _PIPE_C_CSC_COEFF_BU 0x4921c
+#define _PIPE_C_CSC_COEFF_RV_GV0x49220
+#define _PIPE_C_CSC_COEFF_BV 0x49224
+#define _PIPE_C_CSC_MODE 0x49228
+#define _PIPE_C_CSC_PREOFF_HI 0x49230
+#define _PIPE_C_CSC_PREOFF_ME 0x49234
+#define _PIPE_C_CSC_PREOFF_LO 0x49238
+#define _PIPE_C_CSC_POSTOFF_HI 0x49240
+#define _PIPE_C_CSC_POSTOFF_ME 0x49244
+#define _PIPE_C_CSC_POSTOFF_LO 0x49248
+
+#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY, _PIPE_C_CSC_COEFF_RY_GY)
+#define PIPE_CSC_COEFF_BY(pipe)_MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY, _PIPE_C_CSC_COEFF_BY)
+#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU, _PIPE_C_CSC_COEFF_RU_GU)
+#define PIPE_CSC_COEFF_BU(pipe)_MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU, _PIPE_C_CSC_COEFF_BU)
+#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV, _PIPE_C_CSC_COEFF_RV_GV)
+#define PIPE_CSC_COEFF_BV(pipe)_MMIO_PIPE3(pipe,
_PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV, _PIPE_C_CSC_COEFF_BV)
+#define PIPE_CSC_MODE(pipe)_MMIO_PIPE3(pipe, _PIPE_A_CSC_MODE,
_PIPE_B_CSC_MODE, _PIPE_C_CSC_MODE)
+#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI, _PIPE_C_CSC_PREOFF_HI)
+#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME, _PIPE_C_CSC_PREOFF_ME)
+#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO, _PIPE_C_CSC_PREOFF_LO)
+#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI, _PIPE_C_CSC_POSTOFF_HI)
+#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME, _PIPE_C_CSC_POSTOFF_ME)
+#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE3(pipe,
_PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO, _PIPE_C_CSC_POSTOFF_LO)
/* MIPI DSI registers */
--
2.7.0
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[Intel-gfx] [PATCH 5/6] drm/i915: Implement color management on bdw/skl/bxt/kbl
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by
CTM_MATRIX
v4: Update contributors
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
Documentation/DocBook/gpu.tmpl | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 24 ++-
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_reg.h | 22 +++
drivers/gpu/drm/i915/intel_color.c | 367 ++-
drivers/gpu/drm/i915/intel_display.c | 22 ++-
drivers/gpu/drm/i915/intel_drv.h | 6 +-
7 files changed, 396 insertions(+), 60 deletions(-)
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index 7c49a92..78b8877 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -2152,7 +2152,11 @@ void intel_crt_init(struct drm_device *dev)
ENUM
{ "Automatic", "Full", "Limited 16:235" }
Connector
- TBD
+ When this property is set to Limited 16:235
+ and CTM_MATRIX is set, the hardware will be programmed with
+ the result of the multiplication of CTM_MATRIX by the limited
+ range matrix to ensure the pixels normaly in the range 0..1.0
+ are remapped to the range 16/255..235/255.
“audio”
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44912ec..b65aa20 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -66,6 +66,9 @@ static struct drm_driver driver;
#define IVB_CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET,
IVB_CURSOR_C_OFFSET }
+#define BDW_COLORS \
+ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+
static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -288,24 +291,28 @@ static const struct intel_device_info
intel_haswell_m_info = {
.is_mobile = 1,
};
+#define BDW_FEATURES \
+ HSW_FEATURES, \
+ BDW_COLORS
+
static const struct intel_device_info intel_broadwell_d_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
static const struct intel_device_info intel_broadwell_gt3m_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8, .is_mobile = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -321,13 +328,13 @@ static const struct intel_device_info
intel_cherryview_info = {
};
static const struct intel_device_info intel_skylake_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
};
static const struct intel_device_info intel_skylake_gt3_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@ -345,17 +352,18 @@ static const struct intel_device_info intel_broxton_info
= {
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
+ BDW_COLORS,
};
static const struct intel_device_info intel_kabylake_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
};
static const struct intel_device_info intel_kabylake_gt3_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..c1ca4d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -659,6 +659,10 @@ struct drm_i915_display_funcs {
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
+
+ void (*load_degamma_lut)(struct drm_crtc *crtc);
+ void (*load_csc_matrix)(struct drm_crtc *crtc);
+ void (*load_gamma_lut)(struct drm_crtc *crtc);
};
enum forcewake_domain_id {
@@ -806,6 +810,11 @@ struct intel_device_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+
+ struct color_luts {
+ u16 degamma_lut_size;
+ u16 gamma_lut_size;
+ } color;
};
#unde
[Intel-gfx] [PATCH 4/6] drm/i915: enable legacy palette for pipe C
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ba8a99..f8b0d6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5757,7 +5757,8 @@ enum skl_disp_power_wells {
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
-#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+ (i) * 4)
+#define _LGC_PALETTE_C 0x4b000
+#define LGC_PALETTE(pipe, i) _MMIO(_PIPE3(pipe, _LGC_PALETTE_A,
_LGC_PALETTE_B, _LGC_PALETTE_C) + (i) * 4)
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
--
2.7.0
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[Intel-gfx] [PATCH 6/6] drm/i915: Implement color management on chv
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/i915_drv.c| 3 +
drivers/gpu/drm/i915/i915_reg.h| 40 +++
drivers/gpu/drm/i915/intel_color.c | 139 -
3 files changed, 180 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b65aa20..eb69ff2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@ static struct drm_driver driver;
#define BDW_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+#define CHV_COLORS \
+ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -325,6 +327,7 @@ static const struct intel_device_info intel_cherryview_info
= {
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
+ CHV_COLORS,
};
static const struct intel_device_info intel_skylake_info = {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc5d3b..c1e5189 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7685,6 +7685,46 @@ enum skl_disp_power_wells {
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B, _PAL_PREC_GC_MAX_C) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B, _PAL_PREC_EXT_GC_MAX_C) + (i) *
4)
+/* pipe CSC & degamma/gamma LUTs on CHV */
+#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
+#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
+#define _CGM_PIPE_A_CSC_COEFF45(VLV_DISPLAY_BASE + 0x67908)
+#define _CGM_PIPE_A_CSC_COEFF67(VLV_DISPLAY_BASE + 0x6790C)
+#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
+#define _CGM_PIPE_A_DEGAMMA(VLV_DISPLAY_BASE + 0x66000)
+#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
+#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
+#define CGM_PIPE_MODE_GAMMA (1 << 2)
+#define CGM_PIPE_MODE_CSC(1 << 1)
+#define CGM_PIPE_MODE_DEGAMMA(1 << 0)
+
+#define _CGM_PIPE_B_CSC_COEFF01(VLV_DISPLAY_BASE + 0x69900)
+#define _CGM_PIPE_B_CSC_COEFF23(VLV_DISPLAY_BASE + 0x69904)
+#define _CGM_PIPE_B_CSC_COEFF45(VLV_DISPLAY_BASE + 0x69908)
+#define _CGM_PIPE_B_CSC_COEFF67(VLV_DISPLAY_BASE + 0x6990C)
+#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
+#define _CGM_PIPE_B_DEGAMMA(VLV_DISPLAY_BASE + 0x68000)
+#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
+#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
+
+#define _CGM_PIPE_C_CSC_COEFF01(VLV_DISPLAY_BASE + 0x6B900)
+#define _CGM_PIPE_C_CSC_COEFF23(VLV_DISPLAY_BASE + 0x6B904)
+#define _CGM_PIPE_C_CSC_COEFF45(VLV_DISPLAY_BASE + 0x6B908)
+#define _CGM_PIPE_C_CSC_COEFF67(VLV_DISPLAY_BASE + 0x6B90C)
+#define _CGM_PIPE_C_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x6B910)
+#define _CGM_PIPE_C_DEGAMMA(VLV_DISPLAY_BASE + 0x6A000)
+#define _CGM_PIPE_C_GAMMA (VLV_DISPLAY_BASE + 0x6B000)
+#define _CGM_PIPE_C_MODE (VLV_DISPLAY_BASE + 0x6BA00)
+
+#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE3(pipe,
_CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01, _CGM_PIPE_C_CSC_COEFF01)
+#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE3(pipe,
_CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23, _CGM_PIPE_C_CSC_COEFF23)
+#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE3(pipe,
_CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45, _CGM_PIPE_C_CSC_COEFF45)
+#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE3(pipe,
_CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67, _CGM_PIPE_C_CSC_COEFF67)
+#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE3(pipe,
_CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8, _CGM_PIPE_C_CSC_COEFF8)
+#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_DEGAMMA,
_CGM_PIPE_B_DEGAMMA, _CGM_PIPE_C_DEGAMMA) + (i) * 4 + (w) * 4)
+#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_GAMMA,
_CGM_PIPE_B_GAMMA, _CGM_PIPE_C_GAMMA) + (i) * 4 + (w) * 4)
+#define CGM_PIPE_MODE(pipe)_MMIO_PIPE3(pipe, _CGM_PIPE_A_MODE,
_CGM_PIPE_B_MODE, _CGM_PIPE_C_MODE)
+
/* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 782b9d8..da6ff09 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -213,6 +213,54 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
}
}
+/*
+ * S
[Intel-gfx] [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/intel_color.c | 174 +++
drivers/gpu/drm/i915/intel_display.c | 163 +++-
drivers/gpu/drm/i915/intel_drv.h | 10 ++
4 files changed, 197 insertions(+), 151 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_color.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..0516300 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -55,6 +55,7 @@ i915-y += intel_audio.o \
intel_atomic.o \
intel_atomic_plane.o \
intel_bios.o \
+ intel_color.o \
intel_display.o \
intel_fbc.o \
intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
new file mode 100644
index 000..39ca215
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+/*
+ * Set up the pipe CSC unit.
+ *
+ * Currently only full range RGB to limited range RGB conversion
+ * is supported, but eventually this should handle various
+ * RGB<->YCbCr scenarios as well.
+ */
+static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ uint16_t coeff = 0x7800; /* 1.0 */
+
+ /*
+* TODO: Check what kind of values actually come out of the pipe
+* with these coeff/postoff values and adjust to get the best
+* accuracy. Perhaps we even need to take the bpc value into
+* consideration.
+*/
+
+ if (intel_crtc->config->limited_color_range)
+ coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
+
+ /*
+* GY/GU and RY/RU should be the other way around according
+* to BSpec, but reality doesn't agree. Just set them up in
+* a way that results in the correct picture.
+*/
+ I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
+ I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
+
+ I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
+ I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
+
+ I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
+ I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
+
+ I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+ I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+ I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+
+ if (INTEL_INFO(dev)->gen > 6) {
+ uint16_t postoff = 0;
+
+ if (intel_crtc->config->limited_color_range)
+ postoff = (16 * (1 << 12) / 255) & 0x1fff;
+
+ I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
+ I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
+ I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
+
+ I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+ } else {
+ uint32_t mode = CSC_MODE_YUV_TO_RGB;
+
+ if (intel_crtc->config->limited_color_range)
+ mode |= CSC_BLACK_SCREEN_OFFSET;
+
+ I915_WRITE(PIPE_CSC_MODE(pipe), mode);
+ }
+}
+
+void intel_color_set_csc(struct drm_crtc *crtc)
+{
+ i9xx_load_csc_matrix(crtc);
+}
+
+/** Loads the palette/gamma unit for the CRTC with the prepared values on */
+static void i9xx_load_legacy_gamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum pipe pipe = intel_crtc->pipe;
+
[Intel-gfx] [PATCH 0/6] Pipe level color management V4
This series introduces pipe level color management through a set of properties attached to the CRTC. It also provides an implementation for some Intel platforms. This series is based of a previous set of patches by Shashank Sharma. Cheers, Lionel Lionel Landwerlin (6): drm/i915: Extract out gamma table and CSC to their own file drm: introduce color correction properties drm/i915: enable CSC for pipe C drm/i915: enable legacy palette for pipe C drm/i915: Implement color management on bdw/skl/bxt/kbl drm/i915: Implement color management on chv Documentation/DocBook/gpu.tmpl | 64 +++- drivers/gpu/drm/drm_atomic.c | 102 +- drivers/gpu/drm/drm_atomic_helper.c | 10 + drivers/gpu/drm/drm_crtc.c | 35 +++ drivers/gpu/drm/drm_crtc_helper.c| 33 ++ drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_drv.c | 27 +- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_reg.h | 105 ++- drivers/gpu/drm/i915/intel_color.c | 586 +++ drivers/gpu/drm/i915/intel_display.c | 175 ++- drivers/gpu/drm/i915/intel_drv.h | 14 + include/drm/drm_crtc.h | 44 ++- include/drm/drm_crtc_helper.h| 3 + include/uapi/drm/drm_mode.h | 15 + 15 files changed, 1044 insertions(+), 179 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_color.c -- 2.7.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC
On 26/01/16 19:00, Daniel Vetter wrote: On Tue, Jan 26, 2016 at 07:45:42AM -0800, Jesse Barnes wrote: On 01/22/2016 09:00 AM, Daniel Vetter wrote: On Wed, Jan 20, 2016 at 06:26:02PM -0800, tom.orou...@intel.com wrote: From: Tom O'Rourke I'd say we need to keep the boost-deboost stuff alive, e.g. by manually telling guc that the we want different limits, then resetting those limits again after the boost is done. Same for fast idling - kernel simply has a better idea if anyone is about to submit more work (we have execbuf hints for specific workloads like libva). Since there is soon to be a GPU scheduler, the GuC could get this information already, right? Unless you are talking about having mesa signal when it starts creating a new batchbuffer and you would like the GPU to prepare to ramp-up. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC
On 21/01/16 04:26, tom.orou...@intel.com wrote: From: Tom O'Rourke SLPC (Single Loop Power Controller) is a replacement for some host-based power management features. The SLPC implemenation runs in firmware on GuC. This series is a first request for comments. This series is not expected to be merged. After changes based on comments, a later patch series will be sent for merging. This series has been tested with SKL guc firmware versions 4.3 and 4.7. The graphics power management features in SLPC in those versions are DFPS (Dynamic FPS), Turbo, and DCC (Duty Cycle Control). DFPS adjusts requested graphics frequency to maintain target framerate. Turbo adjusts requested graphics frequency to maintain target GT busyness. DCC adjusts requested graphics frequency and stalls guc-scheduler to maintain actual graphics frequency in efficient range. Can we have a benchmark/CI mode that has turbo and reclocking disabled? The frequency would be set to whatever frequency the kernel requests and the GuC would report how many throttling events happened so as our benchmarking system could automatically lower the frequency to provide stable results. We have benchmarks who really need such a mode! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Check for get_pages instead of shmem (filp)
On 09/02/16 00:20, Kristian Høgsberg wrote: On Fri, Feb 5, 2016 at 5:48 PM, Ben Widawsky wrote: This behavior of checking for a shmem backed GEM object was introduced here: commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab Author: Brad Volkin Date: Tue Feb 18 10:15:45 2014 -0800 drm/i915: Refactor shmem pread setup It is possible for an object to not be a shmem backed GEM object (for example userptr objects). An example of how we hit this failure can be found through copy_batch() in the command parser because we allocate a userptr object for the batch which contains privileged instructions. Userptr calls drm_gem_private_object_init() which explicitly sets the filp to none. It is equally feasible to simply remove the check altogether. You'll probably oops with get_pages somewhere, but that's okay IMO because this condition should be a driver bug, and not trigger-able by userspace. On this note, the function name could probably benefit from a change, but whatever. NOTE: I manually retyped this from a test machine. So I haven't even compiled this exact patch. Cc: Chris Wilson Cc: Kristian Høgsberg Cc: Jordan Justen Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 66b1705..a198928 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, *needs_clflush = 0; - if (!obj->base.filp) + if (!obj->ops->get_pages) Don't all subclasses have a get_pages() function? Do we want to do what Chris did in a2a4f916c2f344d4e596c875dd1e66764afec8b8 (on drm-intel-fixes): + if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) ? Yes, I think so; i915_gem_shmem_pread() is going to walk the sglist, so the object had better have a page array for it to iterate over. .Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Kill off intel_crtc->atomic.wait_vblank, v3.
On Tue, Feb 09, 2016 at 12:07:01PM +0100, Maarten Lankhorst wrote: > Op 09-02-16 om 11:42 schreef Ville Syrjälä: > > On Tue, Feb 09, 2016 at 11:27:44AM +0100, Maarten Lankhorst wrote: > >> Hey, > >> > >> Op 13-01-16 om 13:58 schreef Ville Syrjälä: > >>> On Mon, Jan 11, 2016 at 01:27:42PM +0100, Maarten Lankhorst wrote: > Currently we perform our own wait in post_plane_update, > but the atomic core performs another one in wait_for_vblanks. > This means that 2 vblanks are done when a fb is changed, > which is a bit overkill. > > Merge them by creating a helper function that takes a crtc mask > for the planes to wait on. > > The broadwell vblank workaround may look gone entirely but this is > not the case. pipe_config->wm_changed is set to true > when any plane is turned on, which forces a vblank wait. > >>> Still NAK, because you just removed the comment entirely. > >> I may have removed the comment but there will always be an unconditional > >> wait because of the wm changes. > >> In some future commit I will rework do_intel_finish_page_flip to deal with > >> atomic, and in that function the comment > >> will be useful again. > > The comment is the spec here, so it should be kept. Actually what I > > really want is to stop using the flip done interrupt entirely since > > it's arguably broken, at which point the comment should problably be > > moved to somewhere else (interrupt setup code, flip completion code, > > etc.). But removing the comment would be bad since then people might > > not understand why we do it the way we do. > I think the flip done interrupt will still be needed for cs flips, but Chris > was against removing it iirc. I'll move the comment to page_flip_finished for > now. We don't really need it. Using the vblank interrupt should work just fine. > Changes since v1: > - Removing the double vblank wait on broadwell moved to its own commit. > Changes since v2: > - Move out POWER_DOMAIN_MODESET handling to its own commit. > > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_atomic.c | 1 + > drivers/gpu/drm/i915/intel_display.c | 80 > ++-- > drivers/gpu/drm/i915/intel_drv.h | 2 +- > 3 files changed, 61 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c > b/drivers/gpu/drm/i915/intel_atomic.c > index 9682d94af710..ba9a57f33c43 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -98,6 +98,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) > crtc_state->disable_cxsr = false; > crtc_state->wm_changed = false; > crtc_state->wm.need_postvbl_update = false; > +crtc_state->fb_changed = false; > > return &crtc_state->base; > } > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 2aa1c5367625..eac73f005a70 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4796,9 +4796,6 @@ static void intel_post_plane_update(struct > intel_crtc *crtc) > to_intel_crtc_state(crtc->base.state); > struct drm_device *dev = crtc->base.dev; > > -if (atomic->wait_vblank) > -intel_wait_for_vblank(dev, crtc->pipe); > - > intel_frontbuffer_flip(dev, atomic->fb_bits); > > crtc->wm.cxsr_allowed = true; > @@ -11872,6 +11869,9 @@ int intel_plane_atomic_calc_changes(struct > drm_crtc_state *crtc_state, > if (!was_visible && !visible) > return 0; > > +if (fb != old_plane_state->base.fb) > +pipe_config->fb_changed = true; > >>> Isn't that going to slow down cursor updates once again? > >> Very likely.. Shall I add a if (!state->legacy_cursor_update) to > >> intel_atomic_wait_for_vblanks ? > > Not sure. Still wishing we could have just had the proper fps>=vrefresh > > support fron the start. > > > Working on it! -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Kill off intel_crtc->atomic.wait_vblank, v3.
Op 09-02-16 om 11:42 schreef Ville Syrjälä: > On Tue, Feb 09, 2016 at 11:27:44AM +0100, Maarten Lankhorst wrote: >> Hey, >> >> Op 13-01-16 om 13:58 schreef Ville Syrjälä: >>> On Mon, Jan 11, 2016 at 01:27:42PM +0100, Maarten Lankhorst wrote: Currently we perform our own wait in post_plane_update, but the atomic core performs another one in wait_for_vblanks. This means that 2 vblanks are done when a fb is changed, which is a bit overkill. Merge them by creating a helper function that takes a crtc mask for the planes to wait on. The broadwell vblank workaround may look gone entirely but this is not the case. pipe_config->wm_changed is set to true when any plane is turned on, which forces a vblank wait. >>> Still NAK, because you just removed the comment entirely. >> I may have removed the comment but there will always be an unconditional >> wait because of the wm changes. >> In some future commit I will rework do_intel_finish_page_flip to deal with >> atomic, and in that function the comment >> will be useful again. > The comment is the spec here, so it should be kept. Actually what I > really want is to stop using the flip done interrupt entirely since > it's arguably broken, at which point the comment should problably be > moved to somewhere else (interrupt setup code, flip completion code, > etc.). But removing the comment would be bad since then people might > not understand why we do it the way we do. I think the flip done interrupt will still be needed for cs flips, but Chris was against removing it iirc. I'll move the comment to page_flip_finished for now. Changes since v1: - Removing the double vblank wait on broadwell moved to its own commit. Changes since v2: - Move out POWER_DOMAIN_MODESET handling to its own commit. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 1 + drivers/gpu/drm/i915/intel_display.c | 80 ++-- drivers/gpu/drm/i915/intel_drv.h | 2 +- 3 files changed, 61 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 9682d94af710..ba9a57f33c43 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -98,6 +98,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->disable_cxsr = false; crtc_state->wm_changed = false; crtc_state->wm.need_postvbl_update = false; + crtc_state->fb_changed = false; return &crtc_state->base; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2aa1c5367625..eac73f005a70 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4796,9 +4796,6 @@ static void intel_post_plane_update(struct intel_crtc *crtc) to_intel_crtc_state(crtc->base.state); struct drm_device *dev = crtc->base.dev; - if (atomic->wait_vblank) - intel_wait_for_vblank(dev, crtc->pipe); - intel_frontbuffer_flip(dev, atomic->fb_bits); crtc->wm.cxsr_allowed = true; @@ -11872,6 +11869,9 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, if (!was_visible && !visible) return 0; + if (fb != old_plane_state->base.fb) + pipe_config->fb_changed = true; >>> Isn't that going to slow down cursor updates once again? >> Very likely.. Shall I add a if (!state->legacy_cursor_update) to >> intel_atomic_wait_for_vblanks ? > Not sure. Still wishing we could have just had the proper fps>=vrefresh > support fron the start. > Working on it! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Kill off intel_crtc->atomic.wait_vblank, v3.
On Tue, Feb 09, 2016 at 11:27:44AM +0100, Maarten Lankhorst wrote:
> Hey,
>
> Op 13-01-16 om 13:58 schreef Ville Syrjälä:
> > On Mon, Jan 11, 2016 at 01:27:42PM +0100, Maarten Lankhorst wrote:
> >> Currently we perform our own wait in post_plane_update,
> >> but the atomic core performs another one in wait_for_vblanks.
> >> This means that 2 vblanks are done when a fb is changed,
> >> which is a bit overkill.
> >>
> >> Merge them by creating a helper function that takes a crtc mask
> >> for the planes to wait on.
> >>
> >> The broadwell vblank workaround may look gone entirely but this is
> >> not the case. pipe_config->wm_changed is set to true
> >> when any plane is turned on, which forces a vblank wait.
> > Still NAK, because you just removed the comment entirely.
> I may have removed the comment but there will always be an unconditional wait
> because of the wm changes.
> In some future commit I will rework do_intel_finish_page_flip to deal with
> atomic, and in that function the comment
> will be useful again.
The comment is the spec here, so it should be kept. Actually what I
really want is to stop using the flip done interrupt entirely since
it's arguably broken, at which point the comment should problably be
moved to somewhere else (interrupt setup code, flip completion code,
etc.). But removing the comment would be bad since then people might
not understand why we do it the way we do.
> >> Changes since v1:
> >> - Removing the double vblank wait on broadwell moved to its own commit.
> >> Changes since v2:
> >> - Move out POWER_DOMAIN_MODESET handling to its own commit.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/intel_atomic.c | 1 +
> >> drivers/gpu/drm/i915/intel_display.c | 80
> >> ++--
> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> >> 3 files changed, 61 insertions(+), 22 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> >> b/drivers/gpu/drm/i915/intel_atomic.c
> >> index 9682d94af710..ba9a57f33c43 100644
> >> --- a/drivers/gpu/drm/i915/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> >> @@ -98,6 +98,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >>crtc_state->disable_cxsr = false;
> >>crtc_state->wm_changed = false;
> >>crtc_state->wm.need_postvbl_update = false;
> >> + crtc_state->fb_changed = false;
> >>
> >>return &crtc_state->base;
> >> }
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 2aa1c5367625..eac73f005a70 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -4796,9 +4796,6 @@ static void intel_post_plane_update(struct
> >> intel_crtc *crtc)
> >>to_intel_crtc_state(crtc->base.state);
> >>struct drm_device *dev = crtc->base.dev;
> >>
> >> - if (atomic->wait_vblank)
> >> - intel_wait_for_vblank(dev, crtc->pipe);
> >> -
> >>intel_frontbuffer_flip(dev, atomic->fb_bits);
> >>
> >>crtc->wm.cxsr_allowed = true;
> >> @@ -11872,6 +11869,9 @@ int intel_plane_atomic_calc_changes(struct
> >> drm_crtc_state *crtc_state,
> >>if (!was_visible && !visible)
> >>return 0;
> >>
> >> + if (fb != old_plane_state->base.fb)
> >> + pipe_config->fb_changed = true;
> > Isn't that going to slow down cursor updates once again?
> Very likely.. Shall I add a if (!state->legacy_cursor_update) to
> intel_atomic_wait_for_vblanks ?
Not sure. Still wishing we could have just had the proper fps>=vrefresh
support fron the start.
> >> +
> >>turn_off = was_visible && (!visible || mode_changed);
> >>turn_on = visible && (!was_visible || mode_changed);
> >>
> >> @@ -11887,8 +11887,6 @@ int intel_plane_atomic_calc_changes(struct
> >> drm_crtc_state *crtc_state,
> >>
> >>/* must disable cxsr around plane enable/disable */
> >>if (plane->type != DRM_PLANE_TYPE_CURSOR) {
> >> - if (is_crtc_enabled)
> >> - intel_crtc->atomic.wait_vblank = true;
> >>pipe_config->disable_cxsr = true;
> >>}
> >>} else if (intel_wm_need_update(plane, plane_state)) {
> >> @@ -11940,14 +11938,6 @@ int intel_plane_atomic_calc_changes(struct
> >> drm_crtc_state *crtc_state,
> >>plane_state->rotation != BIT(DRM_ROTATE_0))
> >>intel_crtc->atomic.disable_fbc = true;
> >>
> >> - /*
> >> - * BDW signals flip done immediately if the plane
> >> - * is disabled, even if the plane enable is already
> >> - * armed to occur at the next vblank :(
> >> - */
> >> - if (turn_on && IS_BROADWELL(dev))
> >> - intel_crtc->atomic.wait_vblank = true;
> >> -
> >>intel_crtc->atomic.update_fbc |= visible || mode_changed;
> >>break;
> >>case DRM_PLANE_TYPE_CURSOR:
> >> @@ -11962,12 +119
Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Kill off intel_crtc->atomic.wait_vblank, v3.
Hey,
Op 13-01-16 om 13:58 schreef Ville Syrjälä:
> On Mon, Jan 11, 2016 at 01:27:42PM +0100, Maarten Lankhorst wrote:
>> Currently we perform our own wait in post_plane_update,
>> but the atomic core performs another one in wait_for_vblanks.
>> This means that 2 vblanks are done when a fb is changed,
>> which is a bit overkill.
>>
>> Merge them by creating a helper function that takes a crtc mask
>> for the planes to wait on.
>>
>> The broadwell vblank workaround may look gone entirely but this is
>> not the case. pipe_config->wm_changed is set to true
>> when any plane is turned on, which forces a vblank wait.
> Still NAK, because you just removed the comment entirely.
I may have removed the comment but there will always be an unconditional wait
because of the wm changes.
In some future commit I will rework do_intel_finish_page_flip to deal with
atomic, and in that function the comment
will be useful again.
>> Changes since v1:
>> - Removing the double vblank wait on broadwell moved to its own commit.
>> Changes since v2:
>> - Move out POWER_DOMAIN_MODESET handling to its own commit.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/intel_atomic.c | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 80
>> ++--
>> drivers/gpu/drm/i915/intel_drv.h | 2 +-
>> 3 files changed, 61 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
>> b/drivers/gpu/drm/i915/intel_atomic.c
>> index 9682d94af710..ba9a57f33c43 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -98,6 +98,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>> crtc_state->disable_cxsr = false;
>> crtc_state->wm_changed = false;
>> crtc_state->wm.need_postvbl_update = false;
>> +crtc_state->fb_changed = false;
>>
>> return &crtc_state->base;
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 2aa1c5367625..eac73f005a70 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4796,9 +4796,6 @@ static void intel_post_plane_update(struct intel_crtc
>> *crtc)
>> to_intel_crtc_state(crtc->base.state);
>> struct drm_device *dev = crtc->base.dev;
>>
>> -if (atomic->wait_vblank)
>> -intel_wait_for_vblank(dev, crtc->pipe);
>> -
>> intel_frontbuffer_flip(dev, atomic->fb_bits);
>>
>> crtc->wm.cxsr_allowed = true;
>> @@ -11872,6 +11869,9 @@ int intel_plane_atomic_calc_changes(struct
>> drm_crtc_state *crtc_state,
>> if (!was_visible && !visible)
>> return 0;
>>
>> +if (fb != old_plane_state->base.fb)
>> +pipe_config->fb_changed = true;
> Isn't that going to slow down cursor updates once again?
Very likely.. Shall I add a if (!state->legacy_cursor_update) to
intel_atomic_wait_for_vblanks ?
>> +
>> turn_off = was_visible && (!visible || mode_changed);
>> turn_on = visible && (!was_visible || mode_changed);
>>
>> @@ -11887,8 +11887,6 @@ int intel_plane_atomic_calc_changes(struct
>> drm_crtc_state *crtc_state,
>>
>> /* must disable cxsr around plane enable/disable */
>> if (plane->type != DRM_PLANE_TYPE_CURSOR) {
>> -if (is_crtc_enabled)
>> -intel_crtc->atomic.wait_vblank = true;
>> pipe_config->disable_cxsr = true;
>> }
>> } else if (intel_wm_need_update(plane, plane_state)) {
>> @@ -11940,14 +11938,6 @@ int intel_plane_atomic_calc_changes(struct
>> drm_crtc_state *crtc_state,
>> plane_state->rotation != BIT(DRM_ROTATE_0))
>> intel_crtc->atomic.disable_fbc = true;
>>
>> -/*
>> - * BDW signals flip done immediately if the plane
>> - * is disabled, even if the plane enable is already
>> - * armed to occur at the next vblank :(
>> - */
>> -if (turn_on && IS_BROADWELL(dev))
>> -intel_crtc->atomic.wait_vblank = true;
>> -
>> intel_crtc->atomic.update_fbc |= visible || mode_changed;
>> break;
>> case DRM_PLANE_TYPE_CURSOR:
>> @@ -11962,12 +11952,10 @@ int intel_plane_atomic_calc_changes(struct
>> drm_crtc_state *crtc_state,
>> if (IS_IVYBRIDGE(dev) &&
>> needs_scaling(to_intel_plane_state(plane_state)) &&
>> !needs_scaling(old_plane_state)) {
>> -to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
>> -} else if (turn_off && !mode_changed) {
>> -intel_crtc->atomic.wait_vblank = true;
>> +pipe_config->disable_lp_wm = true;
>> +} else if (turn_off && !mode_changed)
>> intel_crtc->atomic.update_sprite_watermarks |=
>> 1 << i;
>> -
Re: [Intel-gfx] [REGRESSION] i915: No HDMI output with 4.4
On Mon, Feb 08, 2016 at 12:17:07PM +0200, Oleksandr Natalenko wrote: > Hi. > > With Linux 4.4 external HDMI-attached monitor in not discovered by i915 > driver. Here is boot log related to drm and i915 for Linux 4.4/4.4.1 kernel: > > === > kernel: [drm] Initialized drm 1.1.0 20060810 > kernel: [drm] Memory usable by graphics device = 2048M > kernel: [drm] Replacing VGA console driver > kernel: [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > kernel: [drm] Driver supports precise vblank timestamp query. > kernel: [drm] Initialized i915 1.6.0 20151010 for :00:02.0 on minor 0 > kernel: i915 :00:02.0: No connectors reported connected with modes > kernel: [drm] Cannot find any crtc or sizes - going 1024x768 > kernel: i915 :00:02.0: fb0: inteldrmfb frame buffer device > === > > i915 is unable to find any connectors. Reattaching HDMI cable does not help. > Note, we are talking about in-kernel i915 drm with no X involved (launching > X does not change anything, though). > > Linux 4.3 worked OK. Here is boot log for 4.3 kernel: > > === > kernel: [drm] Initialized drm 1.1.0 20060810 > kernel: [drm] Memory usable by graphics device = 2048M > kernel: [drm] Replacing VGA console driver > kernel: [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > kernel: [drm] Driver supports precise vblank timestamp query. > kernel: [drm] Initialized i915 1.6.0 20150731 for :00:02.0 on minor 0 > kernel: [drm:intel_set_pch_fifo_underrun_reporting [i915]] *ERROR* uncleared > pch fifo underrun on pch transcoder A > kernel: [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH > transcoder A FIFO underrun > kernel: i915 :00:02.0: fb0: inteldrmfb frame buffer device > === > > Hardware: > > === > [~]$ lscpu | grep "Model name" > Model name:Intel(R) Pentium(R) CPU G2020 @ 2.90GHz > > [~]$ lspci | grep VGA > 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v2/3rd Gen > Core processor Graphics Controller (rev 09) > === > > and xrandr output (with 4.3 kernel): > > === > [~]$ xrandr --listproviders > Providers: number : 1 > Provider 0: id: 0x47 cap: 0xb, Source Output, Sink Output, Sink Offload > crtcs: 4 outputs: 4 associated providers: 0 name:Intel > > [~]$ xrandr > Screen 0: minimum 8 x 8, current 1920 x 1080, maximum 32767 x 32767 > DP1 disconnected (normal left inverted right x axis y axis) > HDMI1 connected primary 1920x1080+0+0 (normal left inverted right x axis y > axis) 510mm x 290mm >1920x1080 60.00*+ 50.0059.94 >1920x1080i60.0050.0059.94 >1680x1050 59.88 >1400x1050 59.95 >1600x900 60.00 >1280x1024 60.02 >1440x900 59.90 >1280x800 59.91 >1152x864 59.97 >1280x720 60.0050.0059.94 >1024x768 60.00 >800x600 60.32 >720x576 50.00 >720x480 60.0059.94 >640x480 60.0059.94 > VGA1 disconnected (normal left inverted right x axis y axis) > VIRTUAL1 disconnected (normal left inverted right x axis y axis) > === > > Ideas? Can you please retest with latest -rc? There's been some bugs in the HDMI detection changes, which should be fixed now. If that doesn't help please try to bisect which exact change caused the regression. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip DDI PLL selection for DSI
On Tue, Feb 09, 2016 at 01:16:18PM +0530, Thulasimani, Sivakumar wrote:
>
>
> On 2/9/2016 12:02 PM, Jani Nikula wrote:
> > On Tue, 09 Feb 2016, "Thulasimani, Sivakumar"
> > wrote:
> >> On 2/5/2016 4:59 PM, Mika Kahola wrote:
> >>> Skip DDI PLL selection if display type is DSI/MIPI.
> >>>
> >>> Signed-off-by: Mika Kahola
> >>> ---
> >>>drivers/gpu/drm/i915/intel_display.c | 9 +++--
> >>>1 file changed, 7 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>> b/drivers/gpu/drm/i915/intel_display.c
> >>> index d7de2a5..5da98b2 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -9902,8 +9902,13 @@ static void broadwell_modeset_commit_cdclk(struct
> >>> drm_atomic_state *old_state)
> >>>static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> >>> struct intel_crtc_state
> >>> *crtc_state)
> >>>{
> >>> - if (!intel_ddi_pll_select(crtc, crtc_state))
> >>> - return -EINVAL;
> >>> + struct intel_encoder *intel_encoder =
> >>> + intel_ddi_get_crtc_new_encoder(crtc_state);
> >>> +
> >>> + if (intel_encoder->type != INTEL_OUTPUT_DSI) {
> >>> + if (!intel_ddi_pll_select(crtc, crtc_state))
> >>> + return -EINVAL;
> >>> + }
> >>>
> >> can this be moved inside bxt_ddi_pll_select ? we can avoid this check for
> >> other platforms that also execute this function.
> > I asked Mika to do it this way, but if you feel strongly about it I
> > guess I could be persuaded otherwise too.
> >
> > My main point is, if we pass on DSI encoders to DDI functions in some
> > cases but mostly not, it will muddy the waters and eventually people end
> > up checking for "is dsi" all around DDI just because they can't be
> > bothered to check if the functions are really called for DDI only or
> > not. It's more of a maintainability concern than anything else.
> >
> > BR,
> > Jani.
> >
> i am fine with this either way. i was thinking of avoid such checks
> in other platforms where it is not needed but your concern of
> too many is_dsi checks is valid as well.
> with that i am fine with this change as is.
> Reviewed-by: Sivakumar Thulasimani
Another idea would be to use the clock_set thing to skip it, but
I think historically that has only been used to skip the PLL
calculations, not the PLL selection. So might be it would just confuse
things more.
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915/skl: Fix typo in DPLL_CFGCR1 definition
On Thu, Feb 04, 2016 at 06:11:28PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2016 at 10:43:21AM -0500, Lyude wrote:
> > We accidentally point both cfgcr registers for the second shared DPLL to
> > the same location in i915_reg.h. This results in a lot of hw pipe state
> > mismatches whenever we try to do a modeset that requires allocating the
> > DPLL to a CRTC:
> >
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> > dpll_hw_state.cfgcr1 (expected 0x8168, found 0x04a5)
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> > base.adjusted_mode.crtc_clock (expected 108000, found 49500)
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock
> > (expected 108000, found 49500)
> >
> > This usually ends up causing blank monitors, since the DPLL never can
> > get set to the right clock.
> >
> > Fixes: f0f59a00a1 ("drm/i915: Type safe register read/write")
>
> Actually
> Fixes: 086f8e84a085 ("drm/i915: Prefix raw register defines with underscore")
>
> That's the second regression from the type safety stuff :( I guess we
> still don't have enough testing coverage since this has gone undetected
> for so long.
>
> Reviewed-by: Ville Syrjälä
Queued for -next, thanks for the patch.
-Daniel
>
> > Signed-off-by: Lyude
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 007ae83..b9a564b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7514,7 +7514,7 @@ enum skl_disp_power_wells {
> > #define DPLL_CFGCR2_PDIV_7 (4<<2)
> > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> >
> > -#define DPLL_CFGCR1(id)_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
> > _DPLL2_CFGCR2)
> > +#define DPLL_CFGCR1(id)_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
> > _DPLL2_CFGCR1)
> > #define DPLL_CFGCR2(id)_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2,
> > _DPLL2_CFGCR2)
> >
> > /* BXT display engine PLL */
> > --
> > 2.5.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Pretend cursor is always on for ILK-style WM calculations (v2)
On Mon, 08 Feb 2016, Matt Roper wrote:
> Due to our lack of two-step watermark programming, our driver has
> historically pretended that the cursor plane is always on for the
> purpose of watermark calculations; this helps avoid serious flickering
> when the cursor turns off/on (e.g., when the user moves the mouse
> pointer to a different screen). That workaround was accidentally
> dropped as we started working toward atomic watermark updates. Since we
> still aren't quite there yet with two-stage updates, we need to
> resurrect the workaround and treat the cursor as always active.
>
> v2: Tweak cursor width calculations slightly to more closely match the
> logic we used before the atomic overhaul began. (Ville)
>
> Cc: simde...@outlook.com
> Cc: manfred.kitzbich...@gmail.com
> Cc: drm-intel-fi...@lists.freedesktop.org
> Reported-by: simde...@outlook.com
> Reported-by: manfred.kitzbich...@gmail.com
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93892
> Fixes: 43d59eda1 ("drm/i915: Eliminate usage of plane_wm_parameters from
> ILK-style WM code (v2)")
> Signed-off-by: Matt Roper
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1454479611-6804-1-git-send-email-matthew.d.ro...@intel.com
> (cherry picked from commit b2435692dbb709d4c8ff3b2f2815c9b8423b72bb)
> ---
> This patch is already merged to dinq, but did not cherry-pick cleanly to
> -fixes
> due to dependence on a separate s/bpp/cpp/ standardization patch. Here's a
> version of the patch that should apply to -fixes cleanly.
Pushed to drm-intel-fixes, thanks for the patch.
BR,
Jani.
>
> drivers/gpu/drm/i915/intel_pm.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index eb5fa05..a234687 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1783,16 +1783,20 @@ static uint32_t ilk_compute_cur_wm(const struct
> intel_crtc_state *cstate,
> const struct intel_plane_state *pstate,
> uint32_t mem_value)
> {
> - int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
> + /*
> + * We treat the cursor plane as always-on for the purposes of watermark
> + * calculation. Until we have two-stage watermark programming merged,
> + * this is necessary to avoid flickering.
> + */
> + int cpp = 4;
> + int width = pstate->visible ? pstate->base.crtc_w : 64;
>
> - if (!cstate->base.active || !pstate->visible)
> + if (!cstate->base.active)
> return 0;
>
> return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
> cstate->base.adjusted_mode.crtc_htotal,
> - drm_rect_width(&pstate->dst),
> - bpp,
> - mem_value);
> + width, cpp, mem_value);
> }
>
> /* Only for WM_LP. */
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
On Tue, Feb 02, 2016 at 10:49:43AM -0500, Lyude wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail:
>
> [ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
> [ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
> [ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
> [ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels
> [ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 0500
> [ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
> [ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
> [ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 0800
> [ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
> …
> [ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too
> many full retries, give up
> [ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train
> DP, aborting
>
> After which the pipe state goes completely out of sync:
>
> [ 70.075596] [drm:check_crtc_state] [CRTC:25]
> [ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> ddi_pll_sel (expected 0x, found 0x0001)
> [ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> shared_dpll (expected -1, found 0)
> [ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> dpll_hw_state.ctrl1 (expected 0x, found 0x0021)
> [ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> dpll_hw_state.cfgcr1 (expected 0x, found 0x80400173)
> [ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> dpll_hw_state.cfgcr2 (expected 0x, found 0x03a5)
> [ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> base.adjusted_mode.crtc_clock (expected 262750, found 72256)
> [ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
> port_clock (expected 54, found 148500)
>
> And if you're especially lucky, it keeps going downhill:
>
> [ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered
> broadcast exception handler
> [ 83.309265]
> [ 83.309265] =
> [ 83.309266] [ INFO: inconsistent lock state ]
> [ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
> [ 83.309267] -
> [ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
> [ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
> [ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at:
> [] gen9_write32+0x63/0x400 [i915]
> [ 83.309293] {IN-HARDIRQ-W} state was registered at:
> [ 83.309297] [] __lock_acquire+0x9c4/0x1d00
> [ 83.309299] [] lock_acquire+0xce/0x1c0
> [ 83.309302] [] _raw_spin_lock_irqsave+0x56/0x90
> [ 83.309321] [] gen9_read32+0x52/0x3d0 [i915]
> [ 83.309332] [] gen8_irq_handler+0x27a/0x6a0 [i915]
> [ 83.309337] [] handle_irq_event_percpu+0x41/0x300
> [ 83.309339] [] handle_irq_event+0x39/0x60
> [ 83.309341] [] handle_edge_irq+0x74/0x130
> [ 83.309344] [] handle_irq+0x73/0x120
> [ 83.309346] [] do_IRQ+0x61/0x120
> [ 83.309348] [] ret_from_intr+0x0/0x20
> [ 83.309351] [] cpuidle_enter_state+0x105/0x330
> [ 83.309353] [] cpuidle_enter+0x17/0x20
> [ 83.309356] [] call_cpuidle+0x2a/0x50
> [ 83.309358] [] cpu_startup_entry+0x26d/0x3a0
> [ 83.309360] [] rest_init+0x13a/0x140
> [ 83.309363] [] start_kernel+0x475/0x482
> [ 83.309365] [] x86_64_start_reservations+0x2a/0x2c
> [ 83.309367] [] x86_64_start_kernel+0x13b/0x14a
>
> Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
> Signed-off-by: Lyude
Somehow CI is ignoring your patch, but then we don't have any dp mst skl
machines in CI anyway yet (would be obvious we'd have noticed this too).
So applied both, with cc: stable for patch 1.
Thanks, Daniel
> ---
> Changes
> * Add "Fixes" line with link to commit that introduced this problem
> * Add some stack traces to aid in future debugging and fixes
>
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
>DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
>wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISP
Re: [Intel-gfx] [PATCH v3 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
On Fri, Jan 29, 2016 at 08:01:19PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Add a few helpers to get the dimensions of the chroma plane(s).
>
> v2: Add kernel-doc (Daniel)
> v3: Fix kerneldoc "Returns:" style (Daniel)
> Uninline the functions and check for num_planes (Daniel)
>
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter
Applied to drm-misc, thanks.
-Daniel
> ---
> drivers/gpu/drm/drm_crtc.c | 40
> include/drm/drm_crtc.h | 2 ++
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 6e6514ef9968..c708b37972de 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -5715,6 +5715,46 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
> EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
>
> /**
> + * drm_format_plane_width - width of the plane given the first plane
> + * @width: width of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
> + * Returns:
> + * The width of @plane, given that the width of the first plane is @width.
> + */
> +int drm_format_plane_width(int width, uint32_t format, int plane)
> +{
> + if (plane >= drm_format_num_planes(format))
> + return 0;
> +
> + if (plane == 0)
> + return width;
> +
> + return width / drm_format_horz_chroma_subsampling(format);
> +}
> +
> +/**
> + * drm_format_plane_height - height of the plane given the first plane
> + * @height: height of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
> + * Returns:
> + * The height of @plane, given that the height of the first plane is @height.
> + */
> +int drm_format_plane_height(int height, uint32_t format, int plane)
> +{
> + if (plane >= drm_format_num_planes(format))
> + return 0;
> +
> + if (plane == 0)
> + return height;
> +
> + return height / drm_format_vert_chroma_subsampling(format);
> +}
> +
> +/**
> * drm_rotation_simplify() - Try to simplify the rotation
> * @rotation: Rotation to be simplified
> * @supported_rotations: Supported rotations
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index c65a212db77e..3a4b53ecd121 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -2482,6 +2482,8 @@ extern int drm_format_num_planes(uint32_t format);
> extern int drm_format_plane_cpp(uint32_t format, int plane);
> extern int drm_format_horz_chroma_subsampling(uint32_t format);
> extern int drm_format_vert_chroma_subsampling(uint32_t format);
> +extern int drm_format_plane_width(int width, uint32_t format, int plane);
> +extern int drm_format_plane_height(int height, uint32_t format, int plane);
> extern const char *drm_get_format_name(uint32_t format);
> extern struct drm_property *drm_mode_create_rotation_property(struct
> drm_device *dev,
> unsigned int
> supported_rotations);
> --
> 2.4.10
>
> ___
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Re: [Intel-gfx] [PATCH v5 10/12] drm/i915: Defer probe if gmux is present but its driver isn't
On Mon, Jan 11, 2016 at 08:09:20PM +0100, Lukas Wunner wrote: > gmux is a microcontroller built into dual GPU MacBook Pros. > On pre-retina MBPs, if we're the inactive GPU, we need apple-gmux > to temporarily switch DDC so that we can probe the panel's EDID. > > The checks for CONFIG_VGA_ARB and CONFIG_VGA_SWITCHEROO are necessary > because if either of them is disabled but gmux is present, the driver > would never load, even if we're the active GPU. (vga_default_device() > would evaluate to NULL and vga_switcheroo_handler_flags() would > evaluate to 0.) > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=88861 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61115 > Tested-by: Lukas Wunner > [MBP 9,1 2012 intel IVB + nvidia GK107 pre-retina 15"] > Signed-off-by: Lukas Wunner > --- > drivers/gpu/drm/i915/i915_drv.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 3ac616d..4a5fc5d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -35,9 +35,12 @@ > #include "i915_trace.h" > #include "intel_drv.h" > > +#include > #include > #include > #include > +#include > +#include > #include > > static struct drm_driver driver; > @@ -967,6 +970,15 @@ static int i915_pci_probe(struct pci_dev *pdev, const > struct pci_device_id *ent) > if (PCI_FUNC(pdev->devfn)) > return -ENODEV; > > + /* > + * apple-gmux is needed on dual GPU MacBook Pro > + * to probe the panel if we're the inactive GPU. > + */ > + if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) && > + apple_gmux_present() && pdev != vga_default_device() && > + !vga_switcheroo_handler_flags()) > + return -EPROBE_DEFER; I pulled in all patches to drm-misc, but this here is imo ugly and needs to be polished a bit. What about adding a vga_switcheroo_ready() function which contains this check (and might in the future contain even more checks)? Then i915/radeon/nouveau would just have a simple if (!vga_switcheroo_ready()) return -EPROBE_DEFER; and instead of duplicating the same comment 3 times we could have it once in one place. Plus some neat kerneldoc for this new helper to describe how it's supposed to be used. Plus better encapsulation of concepts. Can you pls follow up with a patch/series to do that? Thanks, Daniel > + > return drm_get_pci_dev(pdev, ent, &driver); > } > > -- > 1.8.5.2 (Apple Git-48) > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina MacBook Pro
On Mon, Feb 08, 2016 at 10:10:00AM -0800, Darren Hart wrote: > On Mon, Jan 11, 2016 at 08:09:20PM +0100, Lukas Wunner wrote: > > Enable GPU switching on the pre-retina MacBook Pro (2008 - 2013), v5. > > > > The main obstacle on these machines is that the panel mode in VBIOS > > is bogus. Fortunately gmux can switch DDC independently from the > > display, thereby allowing the inactive GPU to probe the panel's EDID. > > > > In short, vga_switcheroo and apple-gmux are amended with hooks to > > switch DDC, DRM core is amended with a drm_get_edid_switcheroo() helper, > > and relevant drivers are amended to call that for LVDS outputs. > > > > The retina MacBook Pro (2012 - present) uses eDP and cannot switch > > AUX independently from the main link. The main obstacle there is link > > training, I'm currently working on this, it will be addressed in a > > future patch set. > > > > This series is also reviewable on GitHub: > > https://github.com/l1k/linux/commits/mbp_switcheroo_v5 > > > > Changes: > > > > * New patch [01/12]: vga_switcheroo handler flags > > Alex Deucher asked if this series might regress on non-Apple laptops. > > To address this concern, I let handlers declare their capabilities in > > a bitmask. DRM drivers call drm_get_edid_switcheroo() only if the > > handler has set the VGA_SWITCHEROO_CAN_SWITCH_DDC flag. > > Currently just one other flag is defined which is used on retinas. > > > > * Changed patch [02/12]: vga_switcheroo DDC locking > > Rename ddc_lock to mux_hw_lock, suggested by Daniel Vetter. > > > > * New patch [03/12]: track switch state of apple-gmux > > Fixes a bug in previous versions of this series which occurred if > > the system was suspended while DDC was temporarily switched: > > On resume DDC was switched to the wrong GPU. > > > > * New patches [09/12 - 12/12]: deferred probing > > Previously I used connector reprobing if the inactive GPU's driver > > loaded before gmux. I've ditched that in favor of deferred driver > > probing, which is much simpler. Thanks to Daniel Vetter for the > > suggestion. > > > > Caution: Patch [09/12] depends on a new acpi_dev_present() API which > > will land in 4.5 via Rafael J. Wysocki's tree. > > > > I would particularly be interested in feedback on the handler flags > > patch [01/12]. I'm not 100% happy with the number of characters > > required to query the flags (e.g.: if (vga_switcheroo_handler_flags() & > > VGA_SWITCHEROO_CAN_SWITCH_DDC)), but failed to come up with something > > shorter. Thierry Reding used a struct of bools instead of a bitmask > > for his recent drm_dp_link_caps patches. Maybe use that instead? > > http://lists.freedesktop.org/archives/dri-devel/2015-December/097025.html > > No objection from the platform-driver-x86 side. I can pull these separately > once > the core is in, or these can be included with that core (preferred) with my > Reviewed-by for 1, 3, 4, and 9. > > Reviewed-by: Darren Hart I pulled them all in through drm-misc, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: Use atomic state to obtain load detection crtc, v2.
Op 03-02-16 om 17:34 schreef Ville Syrjälä:
> On Wed, Feb 03, 2016 at 09:57:55AM +0100, Maarten Lankhorst wrote:
>> Op 02-02-16 om 18:32 schreef Ville Syrjälä:
>>> On Tue, Feb 02, 2016 at 01:48:17PM +0100, Maarten Lankhorst wrote:
drm/i915: Use atomic state to obtain load detection crtc, v2.
Instead of restoring dpms and a flag for whether a temp fb is allocated
duplicate
an atomic state before the new state is committed, and commit it the old
state
in intel_release_load_detect_pipe.
Changes since v1:
- Use a real atomic state.
Signed-off-by: Maarten Lankhorst
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d8c9f7857db..c7ba8f4a971e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10361,6 +10361,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
if (obj->base.size < mode->vdisplay * fb->pitches[0])
return NULL;
+ drm_framebuffer_reference(fb);
return fb;
#else
return NULL;
@@ -10416,7 +10417,7 @@ bool intel_get_load_detect_pipe(struct
drm_connector *connector,
struct drm_device *dev = encoder->dev;
struct drm_framebuffer *fb;
struct drm_mode_config *config = &dev->mode_config;
- struct drm_atomic_state *state = NULL;
+ struct drm_atomic_state *state = NULL, *restore_state = NULL;
struct drm_connector_state *connector_state;
struct intel_crtc_state *crtc_state;
int ret, i = -1;
@@ -10425,6 +10426,8 @@ bool intel_get_load_detect_pipe(struct
drm_connector *connector,
connector->base.id, connector->name,
encoder->base.id, encoder->name);
+ old->restore_state = NULL;
+
retry:
ret = drm_modeset_lock(&config->connection_mutex, ctx);
if (ret)
@@ -10441,24 +10444,15 @@ retry:
*/
/* See if we already have a CRTC for this connector */
- if (encoder->crtc) {
- crtc = encoder->crtc;
+ if (connector->state->crtc) {
+ crtc = connector->state->crtc;
ret = drm_modeset_lock(&crtc->mutex, ctx);
if (ret)
goto fail;
- ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
- if (ret)
- goto fail;
-
- old->dpms_mode = connector->dpms;
- old->load_detect_temp = false;
/* Make sure the crtc and connector are running */
- if (connector->dpms != DRM_MODE_DPMS_ON)
- connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
-
- return true;
+ goto found;
}
/* Find an unused one (if possible) */
@@ -10466,8 +10460,15 @@ retry:
i++;
if (!(encoder->possible_crtcs & (1 << i)))
continue;
- if (possible_crtc->state->enable)
+
+ ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
+ if (ret)
+ goto fail;
+
+ if (possible_crtc->state->enable) {
+ drm_modeset_unlock(&possible_crtc->mutex);
continue;
+ }
crtc = possible_crtc;
break;
@@ -10481,23 +10482,22 @@ retry:
goto fail;
}
- ret = drm_modeset_lock(&crtc->mutex, ctx);
- if (ret)
- goto fail;
+found:
+ intel_crtc = to_intel_crtc(crtc);
+
ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
if (ret)
goto fail;
- intel_crtc = to_intel_crtc(crtc);
- old->dpms_mode = connector->dpms;
- old->load_detect_temp = true;
- old->release_fb = NULL;
-
state = drm_atomic_state_alloc(dev);
- if (!state)
- return false;
+ restore_state = drm_atomic_state_alloc(dev);
+ if (!state || !restore_state) {
+ ret = -ENOMEM;
+ goto fail;
+ }
state->acquire_ctx = ctx;
+ restore_state->acquire_ctx = ctx;
connector_state = drm_atomic_get_connector_state(state, connector);
if (IS_ERR(connector_state)) {
@@ -10505,7 +10505,9 @@ retry:
goto fail;
}
- connector_state->crtc = crtc;
+ ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
+ if (ret)
+ goto fail;
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
if (IS_ERR(crtc_state)) {
@@ -10529,7 +10531,6 @@ retry:
if (fb == NULL) {
DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
fb =
Re: [Intel-gfx] [PATCH v3 5/5] drm/atomic: Add encoder_mask to crtc_state, v3.
On Wed, Feb 03, 2016 at 10:45:07AM -0200, Gustavo Padovan wrote: > Hi Maarten, > > 2016-01-28 Maarten Lankhorst : > > > This allows iteration over encoders without requiring connection_mutex. > > > > Changes since v1: > > - Add a set_best_encoder helper function and update encoder_mask inside > > it. > > Changes since v2: > > - Relax the WARN_ON(!crtc), with explanation. > > - Call set_best_encoder when connector is moved between crtc's. > > - Add some paranoia to steal_encoder to prevent accidentally setting > > best_encoder to NULL. > > > > Signed-off-by: Maarten Lankhorst > > Reviewed-by: Gustavo Padovan All merged to drm-misc, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] lib: Only compile igt_vc4 is we have it
Unbreaks compilation fail. Also appease gcc in gem_exec_basic because. Cc: Eric Anholt Signed-off-by: Daniel Vetter --- lib/Makefile.am| 6 ++ lib/Makefile.sources | 2 -- tests/gem_exec_basic.c | 1 - 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/lib/Makefile.am b/lib/Makefile.am index 7232f9663038..460e0046e00f 100644 --- a/lib/Makefile.am +++ b/lib/Makefile.am @@ -8,6 +8,12 @@ include Makefile.sources noinst_LTLIBRARIES = libintel_tools.la noinst_HEADERS = check-ndebug.h +if HAVE_VC4 + libintel_tools_la_SOURCES +=\ + igt_vc4.c \ + igt_vc4.h +endif + AM_CPPFLAGS = -I$(top_srcdir) AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(LIBUNWIND_CFLAGS) $(DEBUG_CFLAGS) \ -DIGT_SRCDIR=\""$(abs_top_srcdir)/tests"\" \ diff --git a/lib/Makefile.sources b/lib/Makefile.sources index 8a8143f23bbe..4999868052b1 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -16,8 +16,6 @@ libintel_tools_la_SOURCES = \ igt_gt.h\ igt_stats.c \ igt_stats.h \ - igt_vc4.c \ - igt_vc4.h \ instdone.c \ instdone.h \ intel_batchbuffer.c \ diff --git a/tests/gem_exec_basic.c b/tests/gem_exec_basic.c index 3f91b78f9d46..3ee7216472bb 100644 --- a/tests/gem_exec_basic.c +++ b/tests/gem_exec_basic.c @@ -30,7 +30,6 @@ static void noop(int fd, unsigned ring) uint32_t bbe = MI_BATCH_BUFFER_END; struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_exec_object2 exec; - int ret; gem_require_ring(fd, ring); -- 2.7.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
