Re: [Intel-gfx] [REGRESSION] i915: No HDMI output with 4.4
Daniel, I do confirm that this hacky patch: https://lkml.org/lkml/2016/1/19/637 works around my issue. I understand that this is improper fix, so let me know how could I debug my issue further. Thanks. 09.02.2016 12:11, Daniel Vetter wrote: Can you please retest with latest -rc? There's been some bugs in the HDMI detection changes, which should be fixed now. If that doesn't help please try to bisect which exact change caused the regression. Thanks, Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/1] lib/igt_pm: Lib for power management
Move power management related code to a separate library.
Initially this is done only for workarounds that apply to external
components. Modify the users of such workarounds accordingly.
This currently involves HD audio and SATA link power management.
For SATA link PM there's also code to save the previous settings,
to allow for resetting the values after we've finished testing.
Signed-off-by: David Weinehall
---
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
lib/Makefile.sources | 2 +
lib/igt.h | 1 +
lib/igt_aux.c | 15 +-
lib/igt_pm.c | 233 +
lib/igt_pm.h | 31 +++
tests/pm_lpsp.c| 25 +--
tests/pm_rpm.c | 40 +---
8 files changed, 281 insertions(+), 67 deletions(-)
create mode 100644 lib/igt_pm.c
create mode 100644 lib/igt_pm.h
diff --git a/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
b/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
index 618dc5fd7076..3ea3563a029a 100644
--- a/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
+++ b/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
@@ -24,6 +24,7 @@
+
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 4999868052b1..2f0eb2075e14 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -60,6 +60,8 @@ libintel_tools_la_SOURCES = \
igt_core.h \
igt_draw.c \
igt_draw.h \
+ igt_pm.c\
+ igt_pm.h\
$(NULL)
.PHONY: version.h.tmp
diff --git a/lib/igt.h b/lib/igt.h
index 3be25511bb77..d751f2439de2 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -35,6 +35,7 @@
#include "igt_fb.h"
#include "igt_gt.h"
#include "igt_kms.h"
+#include "igt_pm.h"
#include "igt_stats.h"
#include "instdone.h"
#include "intel_batchbuffer.h"
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index ebee119c411d..7d35666eb7f3 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -59,6 +59,7 @@
#include "intel_reg.h"
#include "ioctl_wrappers.h"
#include "igt_kms.h"
+#include "igt_pm.h"
/**
* SECTION:igt_aux
@@ -544,19 +545,7 @@ bool igt_setup_runtime_pm(void)
if (pm_status_fd >= 0)
return true;
- /* The Audio driver can get runtime PM references, so we need to make
-* sure its runtime PM is enabled, so it can release the refs and
-* actually enable us to runtime suspend. */
- fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
- if (fd >= 0) {
- igt_assert(write(fd, "1\n", 2) == 2);
- close(fd);
- }
- fd = open("/sys/bus/pci/devices/:00:03.0/power/control", O_WRONLY);
- if (fd >= 0) {
- igt_assert(write(fd, "auto\n", 5) == 5);
- close(fd);
- }
+ igt_pm_enable_audio_runtime_pm();
/* Our implementation uses autosuspend. Try to set it to 0ms so the test
* suite goes faster and we have a higher probability of triggering race
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
new file mode 100644
index ..2f574961d179
--- /dev/null
+++ b/lib/igt_pm.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright © 2013, 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Paulo Zanoni
+ *David Weinehall
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h"
+#include "igt_pm.h"
+
+enum {
+ POLICY_UNKNOWN = -1,
+ POLICY_MAX_PERFORMANCE = 0,
+ POLICY_MEDIUM_POWER = 1,
+ POLICY_MIN_POWER = 2
+};
+
+#define MAX_PERFORMANCE_STR"max_performance\n"
+#define M
[Intel-gfx] [PATCH v3 0/1] Add a lib for power management helpers
This patch aims to create a separate lib for power management related helpers. Initially it only contains code that modify settings for external components (to handle components with default settings that prevents entering deeper sleep states), but moving i915-related power management helpers to this lib would probably make sense too. v2: Change name of library to igt_pm Namespace all exported functions with igt_pm_ v3: Include igt_pm.xml in intel-gpu-tools-docs.xml Free pm_data Fixed a few typos David Weinehall (1): lib/igt_pm: Lib for power management .../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 + lib/Makefile.sources | 2 + lib/igt.h | 1 + lib/igt_aux.c | 15 +- lib/igt_pm.c | 233 + lib/igt_pm.h | 31 +++ tests/pm_lpsp.c| 25 +-- tests/pm_rpm.c | 40 +--- 8 files changed, 281 insertions(+), 67 deletions(-) create mode 100644 lib/igt_pm.c create mode 100644 lib/igt_pm.h -- 2.7.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm: Add infrastructure for CRTC background color property (v2)
Hi Matt, [auto build test WARNING on drm/drm-next] [also build test WARNING on v4.5-rc3 next-20160210] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Matt-Roper/CRTC-background-color-support-for-i915/20160211-103451 base: git://people.freedesktop.org/~airlied/linux.git drm-next reproduce: make htmldocs All warnings (new ones prefixed by >>): drivers/gpu/drm/i915/i915_irq.c:2659: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2659: warning: No description found for parameter 'fmt' include/drm/drm_crtc.h:447: warning: No description found for parameter 'mode_blob' include/drm/drm_crtc.h:862: warning: No description found for parameter 'name' include/drm/drm_crtc.h:1320: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:1359: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'name' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_mode_id' >> include/drm/drm_crtc.h:2231: warning: No description found for parameter >> 'prop_background_color' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_overscan_property&
[Intel-gfx] [PATCH v2 1/2] drm: Add infrastructure for CRTC background color property (v2)
To support CRTC background color, we need a way of communicating RGB
color values to the DRM. However there is often a mismatch between how
userspace wants to represent the color value vs how it must be
programmed into the hardware; this mismatch can easily lead to
non-obvious bugs. Let's create a kernel-side property type that
standardizes the user<->kernel format and add some macros that allow
drivers to extract the bits they care about without having to worry
about the internal representation. This RGBA property type may also be
useful for future properties like color keys.
These properties are still exposed to userspace as range properties, so
the only userspace change we need are some helpers to build RGBA values
appropriately.
v2:
- Just use 'struct rgba' rather than a typedef as our opaque RGBA
datatype. (Emil)
- Actually use drm_property_create_rgba() to create the background
color property. (Bob)
- Add helper to build 64-bit RGBA internal value in appropriate format
(e.g., for the initial value when attaching a property). (Bob)
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic.c | 4 ++
drivers/gpu/drm/drm_crtc.c | 39 +++
include/drm/drm_crtc.h | 92
3 files changed, 135 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8fb469c..e47c250 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -413,6 +413,8 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
if (property == config->prop_active)
state->active = val;
+ else if (property == config->prop_background_color)
+ state->background_color.v = val;
else if (property == config->prop_mode_id) {
struct drm_property_blob *mode =
drm_property_lookup_blob(dev, val);
@@ -456,6 +458,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = state->active;
else if (property == config->prop_mode_id)
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
+ else if (property == config->prop_background_color)
+ *val = state->background_color.v;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property,
val);
else
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 65258ac..f86fd2d 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3933,6 +3933,30 @@ struct drm_property *drm_property_create_bool(struct
drm_device *dev, int flags,
EXPORT_SYMBOL(drm_property_create_bool);
/**
+ * drm_property_create_rgba - create a new RGBA property type
+ * @dev: drm device
+ * @flags: flags specifying the property type
+ * @name: name of the property
+ *
+ * This creates a new generic drm property which can then be attached to a drm
+ * object with drm_object_attach_property. The returned property object must be
+ * freed with drm_property_destroy.
+ *
+ * Userspace should use the DRM_RGBA() macro to build values with the proper
+ * bit layout.
+ *
+ * Returns:
+ * A pointer to the newly created property on success, NULL on failure.
+ */
+struct drm_property *drm_property_create_rgba(struct drm_device *dev, int
flags,
+ const char *name)
+{
+ return drm_property_create_range(dev, flags, name,
+0, GENMASK_ULL(63, 0));
+}
+EXPORT_SYMBOL(drm_property_create_rgba);
+
+/**
* drm_property_add_enum - add a possible value to an enumeration property
* @property: enumeration property to change
* @index: index of the new enumeration
@@ -5943,6 +5967,21 @@ struct drm_property
*drm_mode_create_rotation_property(struct drm_device *dev,
EXPORT_SYMBOL(drm_mode_create_rotation_property);
/**
+ * drm_mode_create_background_color_property - create CRTC color property
+ * @dev: DRM device
+ *
+ * Creates a property to represent CRTC background/canvas color. Called by a
+ * driver the first time it's needed, must be attached to desired CRTC's.
+ */
+struct drm_property *
+drm_mode_create_background_color_property(struct drm_device *dev)
+{
+ return drm_property_create_rgba(dev, DRM_MODE_PROP_ATOMIC,
+"background_color");
+}
+EXPORT_SYMBOL(drm_mode_create_background_color_property);
+
+/**
* DOC: Tile group
*
* Tile groups are used to represent tiled monitors with a unique
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8c7fb3d..e59dace 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -297,6 +297,90 @@ struct drm_connector_helper_funcs;
struct drm_plane_helper_funcs;
/**
+ * struct drm_rgba - RGBA property value type
+ * @v: Internal representation of RGBA, stored in 16bpc format
+ *
+ * Structure to abstra
[Intel-gfx] [PATCH v2 0/2] CRTC background color support for i915
Some platforms (e.g., Intel SKL+) support a programmable background canvas color below the hardware planes. For more details, see the cover letter for the previous version of the series posted here: https://lists.freedesktop.org/archives/intel-gfx/2015-October/078687.html I haven't made any updates to libdrm or IGT since the last update, so I'm only reposting updates of the kernel patches; use the link above to get to the corresponding libdrm/igt changes. Note that this series isn't mergeable yet since we don't (yet) have an open source userspace that can make use of it. Eventual userspace candidates for this functionality might be Weston, ChromeOS, or Android hwcomposer. Matt Roper (2): drm: Add infrastructure for CRTC background color property (v2) drm/i915/gen9: Add support for pipe background color (v2) Documentation/DocBook/gpu.tmpl | 10 +++- drivers/gpu/drm/drm_atomic.c | 4 ++ drivers/gpu/drm/drm_crtc.c | 39 +++ drivers/gpu/drm/i915/i915_debugfs.c | 8 drivers/gpu/drm/i915/i915_reg.h | 9 drivers/gpu/drm/i915/intel_display.c | 46 ++ include/drm/drm_crtc.h | 92 7 files changed, 207 insertions(+), 1 deletion(-) -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/gen9: Add support for pipe background color (v2)
Gen9 platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes. Let's expose this as a property to
allow userspace to program a desired value.
This patch is based on earlier work by Chandra Konduru; unfortunately
the driver has evolved so much since his patches were written (in the
pre-atomic era) that the functionality had to be pretty much completely
rewritten for the new i915 atomic internals.
v2:
- Set initial background color (black) via proper helper function (Bob)
- Fix debugfs output
- General rebasing
Cc: Chandra Konduru
Cc: Bob Paauwe
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Matt Roper
---
Documentation/DocBook/gpu.tmpl | 10 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_display.c | 46
4 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index fe6b36a..9e003cd 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -2092,7 +2092,7 @@ void intel_crt_init(struct drm_device *dev)
TBD
- i915
+ i915
Generic
"Broadcast RGB"
ENUM
@@ -2108,6 +2108,14 @@ void intel_crt_init(struct drm_device *dev)
TBD
+ CRTC
+ “background_color”
+ RGBA
+
+ CRTC
+ Background color of regions not covered by a
plane
+
+
SDVO-TV
“mode”
ENUM
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ec0c2a05e..e7352fc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3104,6 +3104,14 @@ static int i915_display_info(struct seq_file *m, void
*unused)
intel_scaler_info(m, crtc);
intel_plane_info(m, crtc);
}
+ if (INTEL_INFO(dev)->gen >= 9 && pipe_config->base.active) {
+ struct drm_rgba background =
pipe_config->base.background_color;
+
+ seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
b=%x\n",
+ DRM_RGBA_REDBITS(background, 10),
+ DRM_RGBA_GREENBITS(background, 10),
+ DRM_RGBA_BLUEBITS(background, 10));
+ }
seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
yesno(!crtc->cpu_fifo_underrun_disabled),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 144586e..b0b014d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7649,6 +7649,15 @@ enum skl_disp_power_wells {
#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe,
_PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
+/* Skylake pipe bottom color */
+#define _PIPE_BOTTOM_COLOR_A0x70034
+#define _PIPE_BOTTOM_COLOR_B0x71034
+#define _PIPE_BOTTOM_COLOR_C0x72034
+#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
+#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
+#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
+#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _PIPE_BOTTOM_COLOR_A,
_PIPE_BOTTOM_COLOR_B)
+
/* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 836bbdc..a616ac42 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3299,6 +3299,8 @@ static void intel_update_pipe_config(struct intel_crtc
*crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->base.state);
+ struct drm_rgba background = pipe_config->base.background_color;
+ uint32_t val;
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
crtc->base.mode = crtc->base.state->mode;
@@ -3335,6 +3337,26 @@ static void intel_update_pipe_config(struct intel_crtc
*crtc,
else if (old_crtc_state->pch_pfit.enabled)
ironlake_pfit_disable(crtc, true);
}
+
+ if (INTEL_INFO(dev)->gen >= 9) {
+ /* BGR 16bpc ==> RGB 10bpc */
+ val = DRM_RGBA_REDBITS(background, 10) << 20
+ | DRM_RGBA_GREENBITS(background, 10) << 10
+ | DRM_RGBA_BLUEBITS(background, 10);
+
+ /*
+* Set CSC and gamma for bottom color.
+*
+* FIXME: We turn these on unconditionally for now to match
+* how we've setup the various pla
[Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm: Buffered SVM tests
These tests were initially reviewed/merged under the gem_softpin title.
They use softpinning and userptr mechanism to share buffers between
CPU and GPU.
The userptr part was decoupled from them recently. Adding these tests
under a different name to ensure buffered SVM usage testing.
The only change made was to instantiate the drm fd in the main instead
of every subtest.
Cc: Michel Thierry
Cc: Tvrtko Ursulin
---
tests/Makefile.sources |1 +
tests/gem_buffered_svm.c | 1051 ++
2 files changed, 1052 insertions(+)
create mode 100644 tests/gem_buffered_svm.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index df92586..e6ec6f8 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -17,6 +17,7 @@ TESTS_progs_M = \
drv_hangman \
gem_bad_reloc \
gem_basic \
+ gem_buffered_svm \
gem_busy \
gem_caching \
gem_close_race \
diff --git a/tests/gem_buffered_svm.c b/tests/gem_buffered_svm.c
new file mode 100644
index 000..90e63c4
--- /dev/null
+++ b/tests/gem_buffered_svm.c
@@ -0,0 +1,1051 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Vinay Belgaumkar
+ *Thomas Daniel
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm.h"
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
+#include "i915_drm.h"
+#include
+#include
+#include
+#include
+#include "igt_kms.h"
+#include
+#include
+#include
+#include "igt.h"
+
+#define BO_SIZE 4096
+#define MULTIPAGE_BO_SIZE 2 * BO_SIZE
+#define STORE_BATCH_BUFFER_SIZE 4
+#define EXEC_OBJECT_PINNED (1<<4)
+#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
+#define SHARED_BUFFER_SIZE 4096
+
+typedef struct drm_i915_gem_userptr i915_gem_userptr;
+
+static uint32_t init_userptr(int fd, i915_gem_userptr *, void *ptr, uint64_t
size);
+static void *create_mem_buffer(uint64_t size);
+static int gem_call_userptr_ioctl(int fd, i915_gem_userptr *userptr);
+static void gem_pin_userptr_test(int fd);
+static void gem_pin_bo_test(int fd);
+static void gem_pin_invalid_vma_test(int fd, bool test_decouple_flags, bool
test_canonical_offset);
+static void gem_pin_overlap_test(int fd);
+static void gem_pin_high_address_test(int fd);
+
+#define NO_PPGTT 0
+#define ALIASING_PPGTT 1
+#define FULL_32_BIT_PPGTT 2
+#define FULL_48_BIT_PPGTT 3
+/* uses_full_ppgtt
+ * Finds supported PPGTT details.
+ * @fd DRM fd
+ * @min can be
+ * 0 - No PPGTT
+ * 1 - Aliasing PPGTT
+ * 2 - Full PPGTT (32b)
+ * 3 - Full PPGTT (48b)
+ * RETURNS true/false if min support is present
+*/
+static bool uses_full_ppgtt(int fd, int min)
+{
+ struct drm_i915_getparam gp;
+ int val = 0;
+
+ memset(&gp, 0, sizeof(gp));
+ gp.param = 18; /* HAS_ALIASING_PPGTT */
+ gp.value = &val;
+
+ if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
+ return 0;
+
+ errno = 0;
+ return val >= min;
+}
+
+/* gem_call_userptr_ioctl
+ * Helper to call ioctl - TODO: move to lib
+ * @fd - drm fd
+ * @userptr - pointer to initialised userptr
+ * RETURNS status of ioctl call
+*/
+static int gem_call_userptr_ioctl(int fd, i915_gem_userptr *userptr)
+{
+ int ret;
+
+ ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_USERPTR, userptr);
+
+ if (ret)
+ ret = errno;
+
+ return ret;
+}
+
+/* init_userptr
+ * Helper that inits userptr an returns handle
+ * @fd - drm fd
+ * @userptr - pointer to empty userptr
+ * @ptr - buffer to be shared
+ * @size - size of buffer
+ * @ro - read only flag
+ * RETURNS handle to shared buffer
+*/
+static uint32_t init_userptr(int fd, i915_gem_userptr *userptr, void *ptr,
+uint64_t size)
+{
+
Re: [Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
On 10/02/16 06:27, Ville Syrjälä wrote: > On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.tay...@intel.com wrote: >> From: Clint Taylor >> >> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset >> to set cdclk based on the max required pixel clock based on VCO >> selected. >> >> The vco should be tracked at the atomic level and all CRTCs updated if >> the required vco is changed. At this time the eDP pll is configured >> inside the encoder which has no visibility into the atomic state. > > Yes it does. The passed in pipe_config is the crtc's state. And > if you want to store the thing in the top level atomic state you > just dig up that up from the crtc state: > to_intel_atomic_state(pipe_config->base.state) > or something along those lines). Hi, I'm writing this message with Clint. We understand the following: - This V3 patch as it is now is fixing many use cases for hardware that has been on the shelves for months. - It does not fix all use cases with future eDP 1.4 panels. Example: boot with external monitor and eDP 1.4 lid closed; then lid is opened and causes a VCO change. However such cases are not supported yet anyway! If this happens today, the CD clock will move to some uncontrolled value and the pipelines will NOT be reprogrammed. So this patch does *not regress* any use case - not even future use cases. - Present and future use cases can be addressed in two consecutive patches: first this V3 patch now; then atomic modeset VCO tracking later. This won't increase development complexity in any way. In other words, the second patch will almost not change the code of the first patch. - From a validation perspective this first patch can be validated today with today's hardware. The second patch cannot be validated yet because eDP 1.4 hardware is not readily available yet. - Getting atomic modeset VCO tracking right will take additional development time. And... did I mention validation already? - This first patch is fixing many use cases for hardware that has been on the shelves for months, including failures to reach max resolution. So - you saw me coming from a distance - can we agree on splitting this work in two separate patches so we can merge this first V3 patch now? Products have been needing this for months, thanks! Cheers, Marc ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
On 02/09/2016 07:29 PM, Thulasimani, Sivakumar wrote:
couple of questions since i am looking at SKL code for the first time
> seems we are not reading max cd clock from VBIOS like BDW
even though SKL has limit register to say max cd clock i dont think
it is working, so VBIOS saves the value during boot just like in BDW
and we are supposed to use it. please check VBT spec for the details
Sounds like you might have found a bug. Submit a patch.
> why should we store vco in a separate variable when it is already
available as part of "pipe_config->dpll_hw_state.ctrl1"
We are going to need to know current VCO and target VCO. Current VCO
will have the existing VCO in use and target VCO will be compared to
existing to see in we need a modeset across all CRTCs. ctrl1 will only
contain the new VCO setting. V4 of the patch is in process.
> still trying to understand the flow but is "ctrl1"/"VCO" in this patch
written to DPLL_CTRL1 before we change the CD Clock ? if not then
it might be a bug and must be fixed as part of changes
here.
regards,
Sivakumar
On 2/10/2016 5:58 AM, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
Signed-off-by: Clint Taylor
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?=
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_ddi.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 83
+-
drivers/gpu/drm/i915/intel_dp.c |9 +++-
drivers/gpu/drm/i915/intel_drv.h |1 +
5 files changed, 81 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
-unsigned int skl_boot_cdclk;
+unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-dev_priv->skl_boot_cdclk = cdclk_freq;
+dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..372a68f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned
int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private
*dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
-unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-skl_dpll0_enable(dev_priv, required_vco);
+if (dev_priv->skl_vco_freq != 8640) {
+dev_priv->skl_vco_freq = 8100;
+}
+skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
/* set CDCLK to the frequency the BIOS chose */
-skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500
: 308570 );
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-int freq = dev_priv->skl_boot_cdclk;
+int freq = dev
Re: [Intel-gfx] [v2 5/6] drm/i915: Add support to parse DMI table and get platform memory info
On Wed, Jan 27, 2016 at 09:40:02PM +0530, Shobhit Kumar wrote:
> This is needed for WM computation workaround for arbitrated display
> bandwidth.
>
> v2: Address Matt's review comments
> - Be more paranoid while dmi decoding
> - Also add support for decoding speed from configured memory speed
> if availble in DMI memory entry
>
> Cc: matthew.d.ro...@intel.com
> Signed-off-by: Shobhit Kumar
> ---
> drivers/gpu/drm/i915/i915_dma.c | 47
> +
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> 2 files changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d70d96f..320143b 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -49,6 +49,7 @@
> #include
> #include
> #include
> +#include
>
>
> static int i915_getparam(struct drm_device *dev, void *data,
> @@ -855,6 +856,49 @@ static void intel_init_dpio(struct drm_i915_private
> *dev_priv)
> }
> }
>
> +static void dmi_decode_memory_info(const struct dmi_header *hdr, void *priv)
> +{
> + struct drm_i915_private *dev_priv = (struct drm_i915_private *) priv;
> + const u8 *data = (const u8 *) hdr;
> + uint16_t size, mem_speed;
> +
> +#define DMI_CONF_MEM_SPEED_OFFSET0x20
> +#define DMI_MEM_SPEED_OFFSET 0x15
> +#define DMI_MEM_SIZE_OFFSET 0x0C
> +
> + if (hdr->type == DMI_ENTRY_MEM_DEVICE) {
> + /* Found a memory channel ? */
> + size = (uint16_t) (*((uint16_t *)(data + DMI_MEM_SIZE_OFFSET)));
It might be nicer/cleaner to copy over the memdev_dmi_entry struct from
drivers/edac/i7core_edac.c and cast the data pointer into that to avoid
all the pointer arithmetic. But all of your calculations look correct
to me, so probably not a huge deal either way.
> + if (size == 0)
> + return;
> +
> + dev_priv->dmi.mem_channel++;
> +
> + /* Get the speed */
> + if (hdr->length > DMI_CONF_MEM_SPEED_OFFSET)
> + mem_speed =
> + (uint16_t) (*((uint16_t *)(data +
> DMI_CONF_MEM_SPEED_OFFSET)));
> + else if (hdr->length > DMI_MEM_SPEED_OFFSET)
> + mem_speed =
> + (uint16_t) (*((uint16_t *)(data +
> DMI_MEM_SPEED_OFFSET)));
I think we have more layers of casting here than necessary?
> + else
> + mem_speed = -1;
mem_speed is a uint, so down below it's actually going to pass the
mem_speed > 0 tests, which I don't think was your intent.
Matt
> +
> + /*
> + * Check all channels have same speed
> + * else mark speed as invalid
> + */
> + if (dev_priv->dmi.mem_speed == 0) {
> + if (mem_speed > 0)
> + dev_priv->dmi.mem_speed = mem_speed;
> + else
> + dev_priv->dmi.mem_speed = -1;
> + } else if (dev_priv->dmi.mem_speed > 0 &&
> + dev_priv->dmi.mem_speed != mem_speed)
> + dev_priv->dmi.mem_speed = -1;
> + }
> +}
> +
> /**
> * i915_driver_load - setup chip and create an initial config
> * @dev: DRM device
> @@ -882,6 +926,9 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> dev->dev_private = dev_priv;
> dev_priv->dev = dev;
>
> + /* walk the dmi device table for getting platform memory information */
> + dmi_walk(dmi_decode_memory_info, (void *) dev_priv);
> +
> /* Setup the write-once "constant" device info */
> device_info = (struct intel_device_info *)&dev_priv->info;
> memcpy(device_info, info, sizeof(dev_priv->info));
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 211af53..b040e7a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1968,6 +1968,12 @@ struct drm_i915_private {
>* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
>* will be rejected. Instead look for a better place.
>*/
> +
> + /* DMI data for memory bandwidth calculation */
> + struct {
> + uint16_t mem_channel;
> + int16_t mem_speed;
> + } dmi;
> };
>
> static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
> --
> 2.5.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-firmware-i915 pull request (skl dmc 1.26)
FYI: (Sorry, I had forgotten to cc this list directly there). Forwarded Message From: Rodrigo Vivi To: k...@infradead.org , linux-firmw...@kernel.org Subject: linux-firmware-i915 pull request (skl dmc 1.26) Date: Wed, 10 Feb 2016 13:49:01 -0800 Hi there, Please consider pulling this SKL DMC firmware. The following changes since commit c44bc5b13e570d0756579f5cb63ca104d64e2711: linux-firmware: New minor DMC release for Skylake - ver1_26 (2016-02 -10 13:44:37 -0800) are available in the git repository at: git://people.freedesktop.org/~vivijim/linux-firmware-i915 master for you to fetch changes up to c44bc5b13e570d0756579f5cb63ca104d64e2711: linux-firmware: New minor DMC release for Skylake - ver1_26 (2016-02 -10 13:44:37 -0800) Thanks, Rodrigo. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Set init value for cached work queue head
On 02/10/2016 09:30 AM, Tvrtko Ursulin wrote:
Hi,
On 10/02/16 00:05, yu@intel.com wrote:
> From: Alex Dai
>
> The cached work queue header pointer is set to last byte of work
> queue buffer. It will make sure the whole work queue buffer is
> available after coming back from reset or init.
>
> Do not hold kmap_atomic mapping before going to sleep when work
> queue is full.
Could you please split this into two patches? They are two completely
separate issues and it is customary to do so.
For the kmap_atomic issue you can also reference
https://bugs.freedesktop.org/show_bug.cgi?id=93847 in the commit message.
Yes, will do.
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
> index d7543ef..41f4a96 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -486,11 +486,11 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
>if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size)
>return 0;
>
> - base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
> - desc = base + gc->proc_desc_offset;
> -
>while (timeout_counter-- > 0) {
> + base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
> + desc = base + gc->proc_desc_offset;
>gc->wq_head = desc->head;
> + kunmap_atomic(base);
>
>if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) {
>ret = 0;
> @@ -501,8 +501,6 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
>usleep_range(1000, 2000);
>};
>
> - kunmap_atomic(base);
> -
>return ret;
> }
This part is OK to extinguish this fire. But in general you could also
consider caching the kmap in the client since it looks to me that object
is persistently pinned for its lifetime. So kmap_atomic just complicates
things.
Yes this object must be pinned for its lifetime as it is used by GuC
internally too. I will think about a way to cache it.
> @@ -730,6 +728,8 @@ static struct i915_guc_client *guc_client_alloc(struct
drm_device *dev,
>client->client_obj = obj;
>client->wq_offset = GUC_DB_SIZE;
>client->wq_size = GUC_WQ_SIZE;
> + client->wq_head = GUC_WQ_SIZE - 1;
> + client->wq_tail = 0;
>
>client->doorbell_offset = select_doorbell_cacheline(guc);
>
>
This one I can't really figure out without I suppose knowing more about
the code design. How come it was OK when it was zero (apart after reset)?
The value is otherwise only updated from the GuC shared page and a
driver does not appear to modify it. Perhaps just a better commit
message to explain things?
The way this kernel CIRC_xx works is it leaves one byte free and treat
head == tail case as empty. So, there won't be a problem if this head
happens to be 0. If it comes with some random number between [1,
sizeof(WQ item)], there will be a SW dead looping in driver.
And, I will split this patch into two ones.
Thanks,
Alex
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 4/6] drm/i915/skl+: Use scaling amount for plane data rate calculation
On Wed, Jan 27, 2016 at 09:40:01PM +0530, Shobhit Kumar wrote:
> From: "Kumar, Mahesh"
>
> if downscaling is enabled plane data rate increases according to scaling
> amount. take scaling amount under consideration while calculating plane
> data rate
>
> v2: Address Matt's comments, where data rate was overridden because of
> missing else.
>
> Cc: matthew.d.ro...@intel.com
> Signed-off-by: Kumar, Mahesh
> ---
> drivers/gpu/drm/i915/intel_pm.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 40fff09..a9f9396 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2912,6 +2912,8 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *cstate,
> {
> struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> struct drm_framebuffer *fb = pstate->fb;
> + struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
> + uint32_t down_scale_amount, data_rate;
> uint32_t width = 0, height = 0;
>
> width = drm_rect_width(&intel_pstate->src) >> 16;
> @@ -2923,15 +2925,20 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *cstate,
> /* for planar format */
> if (fb->pixel_format == DRM_FORMAT_NV12) {
> if (y) /* y-plane data rate */
> - return width * height *
> + data_rate = width * height *
> drm_format_plane_cpp(fb->pixel_format, 0);
> else/* uv-plane data rate */
> - return (width / 2) * (height / 2) *
> + data_rate = (width / 2) * (height / 2) *
> drm_format_plane_cpp(fb->pixel_format, 1);
> - }
> + } else
> + /* for packed formats */
> + data_rate = width * height *
> + drm_format_plane_cpp(fb->pixel_format, 0);
According to the coding style, I believe we're supposed to use braces
for both branches if either one of them needs braces.
Aside from that,
Reviewed-by: Matt Roper
> +
> + down_scale_amount = skl_plane_downscale_amount(intel_plane);
> +
> + return DIV_ROUND_UP((data_rate * down_scale_amount), 1000);
>
> - /* for packed formats */
> - return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
> }
>
> /*
> --
> 2.5.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Video glitches E3845 ATOM, Fedora 21
Hi Jani, I have not submitted a bug yet, because no kernel msgs were produced the moment I recreated the issue. I used : drm.debug=0x14 Can you suggest something else ? TIA, Martin -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Wednesday, February 03, 2016 6:41 AM To: Rogers, Martin; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] Video glitches E3845 ATOM, Fedora 21 On Tue, 02 Feb 2016, "Rogers, Martin" wrote: > I'm seeing weird video glitches on the Intel BayLey Bay -i CRB board, > with Fedora 21, XFCE, and I hope someone can help. Please file a bug at https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel Add drm.debug=14 module parameter, and attach dmesg to the bug, from boot to the problem. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ This e-mail and any files transmitted with it are proprietary and intended solely for the use of the individual or entity to whom they are addressed. If you have reason to believe that you have received this e-mail in error, please notify the sender and destroy this email and any attached files. Please note that any views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the Curtiss-Wright Corporation or any of its subsidiaries. Documents attached hereto may contain technology subject to government export regulations. Recipient is solely responsible for ensuring that any re-export, transfer or disclosure of this information is in accordance with applicable government export regulations. The recipient should check this e-mail and any attachments for the presence of viruses. Curtiss-Wright Corporation and its subsidiaries accept no liability for any damage caused by any virus transmitted by this e-mail. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 3/6] drm/i915/skl+: calculate plane pixel rate
On Wed, Jan 27, 2016 at 09:40:00PM +0530, Shobhit Kumar wrote:
> From: "Kumar, Mahesh"
>
> Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel
> according
> to formula
>
> adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount
>
> downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
> if 90/270 rotation use rotated width & height
>
> v2: use intel_plane_state->visible instead of (fb == NULL) as per Matt's
> comment.
>
> Cc: matthew.d.ro...@intel.com
> Signed-off-by: Kumar, Mahesh
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_pm.c | 88
> +++-
> 2 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index bc97012..bb2b1c7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -638,6 +638,8 @@ struct intel_plane_wm_parameters {
> u64 tiling;
> unsigned int rotation;
> uint16_t fifo_size;
> + /* Stores the adjusted plane pixel rate for WM calculation for SKL+ */
> + uint32_t plane_pixel_rate;
> };
>
> struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 708f329..40fff09 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2782,6 +2782,48 @@ skl_wm_plane_id(const struct intel_plane *plane)
> }
> }
>
> +/*
> + * This function takes drm_plane_state as input
> + * and decides the downscale amount according to the formula
> + *
> + * downscale amount = Max[1, Horizontal source size / Horizontal dest size]
> + *
> + * Return value is multiplied by 1000 to retain fractional part
> + * Caller should take care of dividing & Rounding off the value
> + */
> +static uint32_t
> +skl_plane_downscale_amount(const struct intel_plane *intel_plane)
> +{
> + struct drm_plane_state *pstate = intel_plane->base.state;
> + struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> + uint32_t downscale_h, downscale_w;
> + uint32_t src_w, src_h, dst_w, dst_h, tmp;
> +
> + /* If plane not visible return amount as unity */
> + if (!intel_pstate->visible)
> + return 1000;
> +
> + src_w = drm_rect_width(&intel_pstate->src) >> 16;
> + src_h = drm_rect_height(&intel_pstate->src) >> 16;
> +
> + dst_w = drm_rect_width(&intel_pstate->dst);
> + dst_h = drm_rect_height(&intel_pstate->dst);
> +
> + if (intel_rotation_90_or_270(pstate->rotation))
> + swap(dst_w, dst_h);
> +
> + /* Multiply by 1000 for precision */
> + tmp = (1000 * src_h) / dst_h;
> + downscale_h = max_t(uint32_t, 1000, tmp);
> +
> + tmp = (1000 * src_w) / dst_w;
> + downscale_w = max_t(uint32_t, 1000, tmp);
> +
> + /* Reducing precision to 3 decimal places */
> + return DIV_ROUND_UP(downscale_h * downscale_w, 1000);
> +}
I think I mentioned it on my earlier review, but it feels like it would
be simpler/more consistent to just continue using 16.16 binary fixed
point instead of switching over to decimal fixed point (and maybe call
drm_rect_calc_[hv]scale to calculate the scaling). Is there a specific
need to switch?
> +
> +
> static void
> skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> const struct intel_crtc_state *cstate,
> @@ -3183,10 +3225,10 @@ static bool skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> swap(width, height);
>
> bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
> - method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
> + method1 = skl_wm_method1(intel_plane->wm.plane_pixel_rate,
>bytes_per_pixel,
>latency);
> - method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
> + method2 = skl_wm_method2(intel_plane->wm.plane_pixel_rate,
>cstate->base.adjusted_mode.crtc_htotal,
>width,
>bytes_per_pixel,
> @@ -3627,6 +3669,45 @@ static void skl_update_other_pipe_wm(struct drm_device
> *dev,
> }
> }
>
> +static uint32_t
> +skl_plane_pixel_rate(struct intel_crtc_state *cstate, struct intel_plane
> *plane)
> +{
> + uint32_t adjusted_pixel_rate;
> + uint32_t downscale_amount;
> +
> + /*
> + * adjusted plane pixel rate = adjusted pipe pixel rate
> + * Plane pixel rate = adjusted plane pixel rate * plane down scale
> + * amount
> + */
> + adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
> + downscale_amount = skl_plane_downscale_amount(plane);
> +
> + return DIV_ROUND_UP(adjusted_pixel_rate * downscale_amount,
> + 1000);
> +}
> +
> +static void skl_set_plane_pixel_rate(struct drm_crtc *crtc)
> +{
> + struct intel_crtc *intel_crtc = to_
[Intel-gfx] [PATCH] drm/i915: Fix hpd live status bits for g4x
From: Ville Syrjälä
Looks like g4x hpd live status bits actually agree with the spec. At
least they do on the machine I have, and apparently on Nick Bowler's
g4x as well.
So gm45 may be the only platform where they don't agree. At least
that seems to be the case based on the (somewhat incomplete)
logs/dumps in [1], and Daniel has also tested this on his gm45
sometime in the past.
So let's change the bits to match the spec on g4x. That actually makes
the g4x bits identical to vlv/chv so we can just share the code
between those platforms, leaving gm45 as the special case.
[1] https://bugzilla.kernel.org/show_bug.cgi?id=52361
Cc: Shashank Sharma
Cc: Sonika Jindal
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Nick Bowler
References:
https://lists.freedesktop.org/archives/dri-devel/2016-February/100382.html
Reported-by: Nick Bowler
Cc: sta...@vger.kernel.org
Fixes: 237ed86c693d ("drm/i915: Check live status before reading edid")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 15 ---
drivers/gpu/drm/i915/intel_dp.c | 14 +++---
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 188ad5de020f..678faa957e75 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3296,19 +3296,20 @@ enum skl_disp_power_wells {
#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset +
0x61114)
/*
- * HDMI/DP bits are gen4+
+ * HDMI/DP bits are g4x+
*
* WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
* Please check the detailed lore in the commit message for for experimental
* evidence.
*/
-#define PORTD_HOTPLUG_LIVE_STATUS_G4X(1 << 29)
+/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
+#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
+#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
+#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
+/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
+#define PORTD_HOTPLUG_LIVE_STATUS_G4X(1 << 27)
#define PORTC_HOTPLUG_LIVE_STATUS_G4X(1 << 28)
-#define PORTB_HOTPLUG_LIVE_STATUS_G4X(1 << 27)
-/* VLV DP/HDMI bits again match Bspec */
-#define PORTD_HOTPLUG_LIVE_STATUS_VLV(1 << 27)
-#define PORTC_HOTPLUG_LIVE_STATUS_VLV(1 << 28)
-#define PORTB_HOTPLUG_LIVE_STATUS_VLV(1 << 29)
+#define PORTB_HOTPLUG_LIVE_STATUS_G4X(1 << 29)
#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
#define PORTD_HOTPLUG_INT_SHORT_PULSE(1 << 21)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04a5330..bbe18996efe6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4490,20 +4490,20 @@ static bool g4x_digital_port_connected(struct
drm_i915_private *dev_priv,
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
u32 bit;
switch (port->port) {
case PORT_B:
- bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
+ bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
break;
case PORT_C:
- bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
+ bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
break;
case PORT_D:
- bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
+ bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
break;
default:
MISSING_CASE(port->port);
@@ -4555,8 +4555,8 @@ bool intel_digital_port_connected(struct drm_i915_private
*dev_priv,
return cpt_digital_port_connected(dev_priv, port);
else if (IS_BROXTON(dev_priv))
return bxt_digital_port_connected(dev_priv, port);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- return vlv_digital_port_connected(dev_priv, port);
+ else if (IS_GM45(dev_priv))
+ return gm45_digital_port_connected(dev_priv, port);
else
return g4x_digital_port_connected(dev_priv, port);
}
--
2.4.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)
On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote: > On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote: > > Do you guys get the CI mails? This version has regressions. v1 did not. I > > don't > > know what to trust. > > I didn't even see v2 itself! > > > On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote: > > > This behavior of checking for a shmem backed GEM object was introduced > > > here: > > > commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab > > > Author: Brad Volkin > > > Date: Tue Feb 18 10:15:45 2014 -0800 > > > > > > drm/i915: Refactor shmem pread setup > > > > > > It is possible for an object to not be a shmem backed GEM object (for > > > example > > > userptr objects). An example of how we hit this failure can be found > > > through > > > copy_batch() in the command parser because we allocate a userptr object > > > for the > > > batch which contains privileged instructions. Userptr calls > > > drm_gem_private_object_init() which explicitly sets the filp to none. > > > > > > NOTE: I manually retyped this from a test machine. So I haven't even > > > compiled > > > this exact patch. > > > > > > v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon) > > > > > > Cc: Chris Wilson > > > Cc: Kristian Høgsberg > > > Cc: Dave Gordon > > > Signed-off-by: Ben Widawsky > > > Tested-by: Jordan Justen (v1) > > > Reviewed-by: Jordan Justen (v1) > > > > --- > > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > > b/drivers/gpu/drm/i915/i915_gem.c > > > index e9b19bc..7fd79b0 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem.c > > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > > @@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct > > > drm_i915_gem_object *obj, > > > > > > *needs_clflush = 0; > > > > > > - if (!obj->base.filp) > > > + if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) > > Don't use WARN_ON, there is code (or will be) where we use > prepare_shmem_read/write to determine if we can use the shmem paths. > > Also i915_gem_obj_prepare_shmem_write() requires the same treatment. > > My apologies I had this patch but appear to have accidentally squashed > it whilst rebasing. Thanks! > -Chris > So... is someone going to land this fix? We need it. -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Set init value for cached work queue head
Hi,
On 10/02/16 00:05, yu@intel.com wrote:
From: Alex Dai
The cached work queue header pointer is set to last byte of work
queue buffer. It will make sure the whole work queue buffer is
available after coming back from reset or init.
Do not hold kmap_atomic mapping before going to sleep when work
queue is full.
Could you please split this into two patches? They are two completely
separate issues and it is customary to do so.
For the kmap_atomic issue you can also reference
https://bugs.freedesktop.org/show_bug.cgi?id=93847 in the commit message.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index d7543ef..41f4a96 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -486,11 +486,11 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size)
return 0;
- base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
- desc = base + gc->proc_desc_offset;
-
while (timeout_counter-- > 0) {
+ base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
+ desc = base + gc->proc_desc_offset;
gc->wq_head = desc->head;
+ kunmap_atomic(base);
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) {
ret = 0;
@@ -501,8 +501,6 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc)
usleep_range(1000, 2000);
};
- kunmap_atomic(base);
-
return ret;
}
This part is OK to extinguish this fire. But in general you could also
consider caching the kmap in the client since it looks to me that object
is persistently pinned for its lifetime. So kmap_atomic just complicates
things.
@@ -730,6 +728,8 @@ static struct i915_guc_client *guc_client_alloc(struct
drm_device *dev,
client->client_obj = obj;
client->wq_offset = GUC_DB_SIZE;
client->wq_size = GUC_WQ_SIZE;
+ client->wq_head = GUC_WQ_SIZE - 1;
+ client->wq_tail = 0;
client->doorbell_offset = select_doorbell_cacheline(guc);
This one I can't really figure out without I suppose knowing more about
the code design. How come it was OK when it was zero (apart after reset)?
The value is otherwise only updated from the GuC shared page and a
driver does not appear to modify it. Perhaps just a better commit
message to explain things?
Perhaps
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)
On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote: > Do you guys get the CI mails? This version has regressions. v1 did not. I > don't > know what to trust. I didn't even see v2 itself! > On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote: > > This behavior of checking for a shmem backed GEM object was introduced here: > > commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab > > Author: Brad Volkin > > Date: Tue Feb 18 10:15:45 2014 -0800 > > > > drm/i915: Refactor shmem pread setup > > > > It is possible for an object to not be a shmem backed GEM object (for > > example > > userptr objects). An example of how we hit this failure can be found through > > copy_batch() in the command parser because we allocate a userptr object for > > the > > batch which contains privileged instructions. Userptr calls > > drm_gem_private_object_init() which explicitly sets the filp to none. > > > > NOTE: I manually retyped this from a test machine. So I haven't even > > compiled > > this exact patch. > > > > v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon) > > > > Cc: Chris Wilson > > Cc: Kristian Høgsberg > > Cc: Dave Gordon > > Signed-off-by: Ben Widawsky > > Tested-by: Jordan Justen (v1) > > Reviewed-by: Jordan Justen (v1) > > --- > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > b/drivers/gpu/drm/i915/i915_gem.c > > index e9b19bc..7fd79b0 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct > > drm_i915_gem_object *obj, > > > > *needs_clflush = 0; > > > > - if (!obj->base.filp) > > + if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) Don't use WARN_ON, there is code (or will be) where we use prepare_shmem_read/write to determine if we can use the shmem paths. Also i915_gem_obj_prepare_shmem_write() requires the same treatment. My apologies I had this patch but appear to have accidentally squashed it whilst rebasing. Thanks! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/9] drm/i915/error: improve CSB reporting
From: Dave Gordon
v2: add separators for readability
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery (v2)
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 77 +--
2 files changed, 58 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb8de49..549478f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -561,6 +561,8 @@ struct drm_i915_error_state {
u32 execlist_csb[6];
u32 execlist_ctx[6];
+ u64 ctx_desc;
+
struct drm_i915_error_object {
int page_count;
u64 gtt_offset;
@@ -568,7 +570,7 @@ struct drm_i915_error_state {
} *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page;
struct drm_i915_error_request {
- uint64_t ctx_desc;
+ u64 ctx_desc;
long jiffies;
u32 seqno;
u32 tail;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ac83f91..bdbc7ed 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -306,31 +306,57 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
ring->hangcheck_score);
if (i915.enable_execlists) {
+ u32 csb_rd = GEN8_CSB_READ_PTR(ring->execlist_csb_raw_pointer);
+
err_printf(m, " EXECLIST_STATUS: 0x%08x\n",
ring->execlist_status);
err_printf(m, " EXECLIST_CTX_ID: 0x%08x\n",
ring->execlist_ctx_id);
err_printf(m, " EXECLIST_CSBPTR: 0x%08x\n",
ring->execlist_csb_raw_pointer);
- err_printf(m, " EXECLIST_CSB_WR: 0x%08x\n",
ring->execlist_csb_write_pointer);
- err_printf(m, " EXECLIST_CSB_RD: 0x%08x\n",
ring->execlist_csb_read_pointer);
+ err_printf(m, " EXECLIST_CSB_WR: %d\n",
ring->execlist_csb_write_pointer);
+ err_printf(m, " EXECLIST_CSB_RD: %d\n", csb_rd);
+
+ for (i = 1; i <= GEN8_CSB_ENTRIES; ++i) {
+ int n = (ring->execlist_csb_write_pointer + i) %
GEN8_CSB_ENTRIES;
+ u32 ctxid = ring->execlist_ctx[n];
+ u32 csb = ring->execlist_csb[n];
+ u32 tag = 0;
+ char dot = '.';
+ err_printf(m, " EXECLIST_CTX/CSB[%d]: ", n);
+
+ if (ctxid && i915.enable_guc_submission) {
+ /* GuC CtxID is ring + flags + (lrca >> 12) */
+ tag = ((ring_idx << 9) | 1);
+ }
+ if ((ctxid >> 20) != tag)
+ dot = '?'; /* flag unexpected
value */
+ err_printf(m, "0x%03x%c%05x / ",
+ ctxid >> 20, dot, ctxid & 0x000f);
+/* CSB status bits */
#define GEN8_CTX_STATUS_IDLE_ACTIVE(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
-
- for (i = 1; i <= GEN8_CSB_ENTRIES; ++i) {
- int n = (ring->execlist_csb_write_pointer + i) %
GEN8_CSB_ENTRIES;
- u32 csb = ring->execlist_csb[n];
- err_printf(m, " EXECLIST_CTX/CSB[%d]: 0x%08x 0x%08x
",
- n, ring->execlist_ctx[n], csb);
- err_printf(m, "%s %s %s %s %s %s\n",
- csb & GEN8_CTX_STATUS_IDLE_ACTIVE?
"I->A" : "",
- csb & GEN8_CTX_STATUS_PREEMPTED
? "PRMT" : "",
- csb & GEN8_CTX_STATUS_ELEMENT_SWITCH ?
"ELSW" : "",
- csb & GEN8_CTX_STATUS_ACTIVE_IDLE?
"A->I" : "",
- csb & GEN8_CTX_STATUS_COMPLETE
? "DONE" : "",
- csb & GEN8_CTX_STATUS_LITE_RESTORE ?
"LITE" : "");
+#define GEN8_CTX_STATUS_UNKNOWN(~0x801f) /* any other */
+
+ err_printf(m, "0x%08x | %s | %s | %s | %s | %s | %s |
%s\n",
+ csb,
+ csb & GEN8_CTX_STATUS_IDLE_ACTIVE ?
"I->A" : "",
+ csb & GEN8_CTX_STATUS_PREEMPTED ?
"PRMT" : "",
+ csb & GEN8_CTX_STATUS_ELEMENT_SWITCH?
"ELSW" : "",
+ cs
[Intel-gfx] [PATCH v2 9/9] drm/i915/error: Capture WA ctx batch in error state
From Gen8 onwards we apply ctx workarounds using special batch buffers that
execute during save/restore, good to have them in error state.
v2: use wa_ctx->size and print only size values (Mika)
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 28
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7808d3..7ad0b47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -568,7 +568,7 @@ struct drm_i915_error_state {
bool is_ppgtt;
int page_count;
u32 *pages[0];
- } *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page;
+ } *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page, *wa_ctx;
struct drm_i915_error_request {
u64 ctx_desc;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index f426538..b62edbb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -659,6 +659,27 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
}
}
+ if ((obj = error->ring[i].wa_ctx)) {
+ u64 wa_ctx_offset = obj->gtt_offset;
+ u32 *wa_ctx_page = &obj->pages[0][0];
+ struct intel_engine_cs *ring = &dev_priv->ring[RCS];
+ u32 wa_ctx_size = (ring->wa_ctx.indirect_ctx.size +
+ ring->wa_ctx.per_ctx.size);
+
+ err_printf(m, "%s --- WA Ctx batch buffer = 0x%08llx\n",
+ dev_priv->ring[i].name, wa_ctx_offset);
+ offset = 0;
+ for (elt = 0; elt < wa_ctx_size; elt += 4) {
+ err_printf(m, "[%04x] %08x %08x %08x %08x\n",
+ offset,
+ wa_ctx_page[elt],
+ wa_ctx_page[elt+1],
+ wa_ctx_page[elt+2],
+ wa_ctx_page[elt+3]);
+ offset += 16;
+ }
+ }
+
if ((obj = error->ring[i].ctx)) {
err_printf(m, "%s --- HW Context = 0x%08x\n",
dev_priv->ring[i].name,
@@ -752,6 +773,8 @@ static void i915_error_state_free(struct kref *error_ref)
i915_error_object_free(error->ring[i].hws_page);
i915_error_object_free(error->ring[i].ctx);
kfree(error->ring[i].requests);
+ if (i == RCS)
+ i915_error_object_free(error->ring[i].wa_ctx);
}
i915_error_object_free(error->semaphore_obj);
@@ -1267,6 +1290,11 @@ static void i915_gem_record_rings(struct drm_device *dev,
error->ring[i].hws_page =
i915_error_ggtt_object_create(dev_priv,
ring->status_page.obj);
+ if (INTEL_INFO(dev)->gen >= 8 && ring->id == RCS) {
+ error->ring[i].wa_ctx =
+ i915_error_ggtt_object_create(dev_priv,
ring->wa_ctx.obj);
+ }
+
i915_gem_record_active_context(ring, error, &error->ring[i]);
count = 0;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/9] drm/i915/error: capture execlist state on error
From: Dave Gordon
At present, execlist status/ctx_id and CSBs, not the submission queue
v2: dump execlist details only when they are enabled (Mika)
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_gpu_error.c | 36 +--
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..6cca108 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -552,6 +552,15 @@ struct drm_i915_error_state {
u32 rc_psmi; /* sleep state */
u32 semaphore_mboxes[I915_NUM_RINGS - 1];
+ /* Execlists */
+ u32 execlist_status;
+ u32 execlist_ctx_id;
+ u32 execlist_csb_raw_pointer;
+ u32 execlist_csb_write_pointer;
+ u32 execlist_csb_read_pointer;
+ u32 execlist_csb[6];
+ u32 execlist_ctx[6];
+
struct drm_i915_error_object {
int page_count;
u64 gtt_offset;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 978c026..8efc8f9a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -247,6 +247,7 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
int ring_idx)
{
struct drm_i915_error_ring *ring = &error->ring[ring_idx];
+ int i;
if (!ring->valid)
return;
@@ -288,7 +289,6 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
if (INTEL_INFO(dev)->gen >= 8) {
- int i;
for (i = 0; i < 4; i++)
err_printf(m, " PDP%d: 0x%016llx\n",
i, ring->vm_info.pdp[i]);
@@ -304,6 +304,19 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
err_printf(m, " hangcheck: %s [%d]\n",
hangcheck_action_to_str(ring->hangcheck_action),
ring->hangcheck_score);
+
+ if (i915.enable_execlists) {
+ err_printf(m, " EXECLIST_STATUS: 0x%08x\n",
ring->execlist_status);
+ err_printf(m, " EXECLIST_CTX_ID: 0x%08x\n",
ring->execlist_ctx_id);
+ err_printf(m, " EXECLIST_CSBPTR: 0x%08x\n",
ring->execlist_csb_raw_pointer);
+ err_printf(m, " EXECLIST_CSB_WR: 0x%08x\n",
ring->execlist_csb_write_pointer);
+ err_printf(m, " EXECLIST_CSB_RD: 0x%08x\n",
ring->execlist_csb_read_pointer);
+
+ for (i = 0; i < 6; i++) {
+ err_printf(m, " EXECLIST_CSB[%d]: 0x%08x\n", i,
ring->execlist_csb[i]);
+ err_printf(m, " EXECLIST_CTX[%d]: 0x%08x\n", i,
ring->execlist_ctx[i]);
+ }
+ }
}
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -965,8 +978,27 @@ static void i915_record_ring_state(struct drm_device *dev,
I915_READ(GEN8_RING_PDP_LDW(ring, i));
}
}
-}
+ if (i915.enable_execlists) {
+ int i;
+ u32 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
+ u8 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
+ u8 read_pointer = ring->next_context_status_buffer;
+ if (read_pointer > write_pointer)
+ write_pointer += GEN8_CSB_ENTRIES;
+
+ ering->execlist_status =
I915_READ(RING_EXECLIST_STATUS_LO(ring));
+ ering->execlist_ctx_id =
I915_READ(RING_EXECLIST_STATUS_HI(ring));
+ ering->execlist_csb_raw_pointer = status_pointer;
+ ering->execlist_csb_write_pointer = write_pointer;
+ ering->execlist_csb_read_pointer = read_pointer;
+
+ for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
+ ering->execlist_csb[i] =
I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
+ ering->execlist_ctx[i] =
I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
+ }
+ }
+}
static void i915_gem_record_active_context(struct intel_engine_cs *ring,
struct drm_i915_error_state *error,
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 8/9] drm/i915/error: add GuC state error capture & decode
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 107 ++
2 files changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ed991bf..f7808d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -611,6 +611,10 @@ struct drm_i915_error_state {
u32 *active_bo_count, *pinned_bo_count;
u32 vm_count;
+
+ struct intel_guc guc;
+ struct i915_guc_client execbuf_client;
+ struct i915_guc_client preempt_client;
};
struct intel_connector;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 03485ca..f426538 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -361,6 +361,96 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
}
}
+static void i915_guc_firmware_info(struct drm_i915_error_state_buf *m,
+ struct drm_i915_private *dev_priv,
+ struct intel_guc_fw *guc_fw)
+{
+ err_printf(m, "GuC firmware status:\n");
+ err_printf(m, "\tpath: %s\n",
+ guc_fw->guc_fw_path);
+ err_printf(m, "\tfetch: %s\n",
+ intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ err_printf(m, "\tload: %s\n",
+ intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ err_printf(m, "\tversion wanted: %d.%d\n",
+ guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ err_printf(m, "\tversion found: %d.%d\n",
+ guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+}
+
+static void i915_guc_action_info(struct drm_i915_error_state_buf *m,
+struct drm_i915_private *dev_priv,
+struct intel_guc *guc)
+{
+ struct intel_engine_cs *ring;
+ u64 total = 0;
+ int i;
+
+ err_printf(m, "GuC action status:\n");
+ err_printf(m, "\ttotal action count: %llu\n", guc->action_count);
+ err_printf(m, "\tlast action command: 0x%x\n", guc->action_cmd);
+ err_printf(m, "\tlast action status: 0x%x\n", guc->action_status);
+
+ err_printf(m, "\taction failure count: %u\n", guc->action_fail_count);
+ err_printf(m, "\tlast failed action: 0x%x\n", guc->action_fail_cmd);
+ err_printf(m, "\tlast failed status: 0x%x\n", guc->action_fail_status);
+ err_printf(m, "\tlast error code: %d\n", guc->action_err);
+
+ err_printf(m, "GuC submissions:\n");
+ for_each_ring(ring, dev_priv, i) {
+ err_printf(m, "\t%-24s: %10llu, last %-8s 0x%08x %9d\n",
+ ring->name, guc->submissions[i], "seqno",
+ guc->last_seqno[i], guc->last_seqno[i]);
+ total += guc->submissions[i];
+ }
+ err_printf(m, "\t%s: %10llu\n", "Total regular", total);
+}
+
+static void i915_guc_client_info(struct drm_i915_error_state_buf *m,
+struct drm_i915_private *dev_priv,
+struct i915_guc_client *client)
+{
+ struct intel_engine_cs *ring;
+ uint64_t tot = 0;
+ uint32_t i;
+
+ err_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
+ client->priority, client->ctx_index, client->proc_desc_offset);
+ err_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
+ client->doorbell_id, client->doorbell_offset, client->cookie);
+ err_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
+ client->wq_size, client->wq_offset, client->wq_tail);
+
+ err_printf(m, "\tFailed to queue: %u\n", client->q_fail);
+ err_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
+ err_printf(m, "\tLast submission result: %d\n", client->retcode);
+
+ for_each_ring(ring, dev_priv, i) {
+ err_printf(m, "\tSubmissions: %llu %s\n",
+ client->submissions[i],
+ ring->name);
+ tot += client->submissions[i];
+ }
+ err_printf(m, "\tTotal: %llu\n", tot);
+}
+
+static void i915_guc_error_state(struct drm_i915_error_state_buf *m,
+struct drm_i915_private *dev_priv,
+struct drm_i915_error_state *error)
+{
+ struct intel_guc *guc;
+
+ if (!i915.enable_guc_submission)
+ return;
+
+ guc = &error->guc;
+ i915_guc_firmware_info(m, dev_priv, &guc->guc_fw);
+ i915_guc_action_info(m, dev_priv, guc);
+
+ err_printf(m, "GuC execbuf client @ %p:\n", guc->execbuf_client);
+ i915_guc_client_info(m, dev_priv, &error->execbuf_client);
+}
+
void i915_error_printf(struct drm_
[Intel-gfx] [PATCH v2 3/9] drm/i915/error: report ctx id & desc for each request in the queue
From: Dave Gordon
Also decode and output CSB entries, in time order
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +++
2 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84bbd98..cb8de49 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -568,6 +568,7 @@ struct drm_i915_error_state {
} *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page;
struct drm_i915_error_request {
+ uint64_t ctx_desc;
long jiffies;
u32 seqno;
u32 tail;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index d4d46ac..ac83f91 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -312,9 +312,25 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
err_printf(m, " EXECLIST_CSB_WR: 0x%08x\n",
ring->execlist_csb_write_pointer);
err_printf(m, " EXECLIST_CSB_RD: 0x%08x\n",
ring->execlist_csb_read_pointer);
- for (i = 0; i < 6; i++) {
- err_printf(m, " EXECLIST_CSB[%d]: 0x%08x\n", i,
ring->execlist_csb[i]);
- err_printf(m, " EXECLIST_CTX[%d]: 0x%08x\n", i,
ring->execlist_ctx[i]);
+#define GEN8_CTX_STATUS_IDLE_ACTIVE(1 << 0)
+#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
+#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
+#define GEN8_CTX_STATUS_ACTIVE_IDLE(1 << 3)
+#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
+#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
+
+ for (i = 1; i <= GEN8_CSB_ENTRIES; ++i) {
+ int n = (ring->execlist_csb_write_pointer + i) %
GEN8_CSB_ENTRIES;
+ u32 csb = ring->execlist_csb[n];
+ err_printf(m, " EXECLIST_CTX/CSB[%d]: 0x%08x 0x%08x
",
+ n, ring->execlist_ctx[n], csb);
+ err_printf(m, "%s %s %s %s %s %s\n",
+ csb & GEN8_CTX_STATUS_IDLE_ACTIVE?
"I->A" : "",
+ csb & GEN8_CTX_STATUS_PREEMPTED
? "PRMT" : "",
+ csb & GEN8_CTX_STATUS_ELEMENT_SWITCH ?
"ELSW" : "",
+ csb & GEN8_CTX_STATUS_ACTIVE_IDLE?
"A->I" : "",
+ csb & GEN8_CTX_STATUS_COMPLETE
? "DONE" : "",
+ csb & GEN8_CTX_STATUS_LITE_RESTORE ?
"LITE" : "");
}
}
}
@@ -470,10 +486,13 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
dev_priv->ring[i].name,
error->ring[i].num_requests);
for (j = 0; j < error->ring[i].num_requests; j++) {
- err_printf(m, " seqno 0x%08x, emitted %ld,
tail 0x%08x\n",
- error->ring[i].requests[j].seqno,
- error->ring[i].requests[j].jiffies,
- error->ring[i].requests[j].tail);
+ struct drm_i915_error_request *erq;
+ erq = &error->ring[i].requests[j];
+ err_printf(m, " seqno 0x%08x, tail 0x%08x, "
+ "emitted %ld, ctx_desc 0x%08x_%08x\n",
+ erq->seqno, erq->tail, erq->jiffies,
+ upper_32_bits(erq->ctx_desc),
+ lower_32_bits(erq->ctx_desc));
}
}
@@ -1132,6 +1151,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
count = 0;
list_for_each_entry(request, &ring->request_list, list) {
+ struct intel_context *ctx = request->ctx;
struct drm_i915_error_request *erq;
if (count >= error->ring[i].num_requests) {
@@ -1154,8 +1174,9 @@ static void i915_gem_record_rings(struct drm_device *dev,
}
erq = &error->ring[i].requests[count++];
- erq->seqno = request->seqno;
+ erq->ctx_desc = intel_lr_context_descriptor(ctx, ring);
erq->jiffies = request->emitted_jiffies;
+ erq->seqno = request->seqno;
erq->tail = request->postfix;
}
}
--
1.9.1
___
[Intel-gfx] [PATCH v2 6/9] drm/i915/error: enhanced error capture of requests
From: Dave Gordon
Record a few more things about the requests outstanding at the time of
capture ...
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 23 +--
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 549478f..ed991bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -564,8 +564,9 @@ struct drm_i915_error_state {
u64 ctx_desc;
struct drm_i915_error_object {
- int page_count;
u64 gtt_offset;
+ bool is_ppgtt;
+ int page_count;
u32 *pages[0];
} *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page;
@@ -573,7 +574,10 @@ struct drm_i915_error_state {
u64 ctx_desc;
long jiffies;
u32 seqno;
+ u32 head;
u32 tail;
+ u32 submission_count;
+ u64 ringbuffer_gtt;
} *requests;
struct {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c599df6..03485ca 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -493,9 +493,11 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, " (submitted by %s [%d])",
error->ring[i].comm,
error->ring[i].pid);
- err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
+ err_printf(m, " --- %sgtt_offset = 0x%08x %08x; %d
pages\n",
+ obj->is_ppgtt ? "pp" : "g",
upper_32_bits(obj->gtt_offset),
- lower_32_bits(obj->gtt_offset));
+ lower_32_bits(obj->gtt_offset),
+ obj->page_count);
print_error_obj(m, obj);
}
@@ -514,9 +516,13 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
for (j = 0; j < error->ring[i].num_requests; j++) {
struct drm_i915_error_request *erq;
erq = &error->ring[i].requests[j];
- err_printf(m, " seqno 0x%08x, tail 0x%08x, "
- "emitted %ld, ctx_desc 0x%08x_%08x\n",
- erq->seqno, erq->tail, erq->jiffies,
+ err_printf(m, " seqno 0x%08x, ringbuf 0x%llx "
+ "head 0x%08x tail 0x%08x, "
+ "emitted %ld, %d submissions, "
+ "ctx_desc 0x%08x_%08x\n",
+ erq->seqno, erq->ringbuffer_gtt,
+ erq->head, erq->tail,
+ erq->jiffies, erq->submission_count,
upper_32_bits(erq->ctx_desc),
lower_32_bits(erq->ctx_desc));
}
@@ -698,6 +704,8 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
reloc_offset = dst->gtt_offset;
if (i915_is_ggtt(vm))
vma = i915_gem_obj_to_ggtt(src);
+ else
+ dst->is_ppgtt = true;
use_ggtt = (src->cache_level == I915_CACHE_NONE &&
vma && (vma->bound & GLOBAL_BIND) &&
reloc_offset + num_pages * PAGE_SIZE <=
dev_priv->gtt.mappable_end);
@@ -1209,7 +1217,10 @@ static void i915_gem_record_rings(struct drm_device *dev,
erq->ctx_desc = intel_lr_context_descriptor(ctx, ring);
erq->jiffies = request->emitted_jiffies;
erq->seqno = request->seqno;
- erq->tail = request->postfix;
+ erq->tail = request->tail;
+ erq->head = request->head;
+ erq->submission_count = request->elsp_submitted;
+ erq->ringbuffer_gtt =
i915_gem_obj_ggtt_offset(request->ringbuf->obj);
}
}
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 5/9] drm/i915/error: capture errored context based on request context-id
From: Dave Gordon Context capture hasn't worked for a while now, probably since the introduction of execlists; this patch makes it work again by using a different way of identifying the context of interest. For: VIZ-2021 Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/i915_gpu_error.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index bdbc7ed..c599df6 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1075,13 +1075,12 @@ static void i915_gem_record_active_context(struct intel_engine_cs *ring, continue; } - if (!error->ccid) - continue; - if (i915.enable_execlists) base += LRC_PPHWSP_PN * PAGE_SIZE; - if (base == (error->ccid & PAGE_MASK)) + if (error->ccid && base == (error->ccid & PAGE_MASK)) + ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); + else if (((base ^ ering->ctx_desc) & 0xF000ULL) == 0) ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); } } -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 7/9] drm/i915/guc: Improve action error reporting
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c| 17 ++---
drivers/gpu/drm/i915/i915_guc_submission.c | 20
drivers/gpu/drm/i915/intel_guc.h | 9 +++--
3 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ec0c2a05e..2a326ad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2495,19 +2495,22 @@ static int i915_guc_info(struct seq_file *m, void *data)
mutex_unlock(&dev->struct_mutex);
seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
- seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
- seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
+
+ seq_printf(m, "GuC action failure count: %u\n", guc.action_fail_count);
+ seq_printf(m, "GuC last failed action: 0x%x\n", guc.action_fail_cmd);
+ seq_printf(m, "GuC last failed status: 0x%x\n", guc.action_fail_status);
+ seq_printf(m, "GuC last error code: %d\n", guc.action_err);
seq_printf(m, "\nGuC submissions:\n");
for_each_ring(ring, dev_priv, i) {
- seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
- ring->name, guc.submissions[ring->guc_id],
- guc.last_seqno[ring->guc_id]);
- total += guc.submissions[ring->guc_id];
+ seq_printf(m, "\t%-24s: %10llu, last %-8s 0x%08x %9d\n",
+ ring->name, guc.submissions[i], "seqno",
+ guc.last_seqno[i], guc.last_seqno[i]);
+ total += guc.submissions[i];
}
- seq_printf(m, "\t%s: %llu\n", "Total", total);
+ seq_printf(m, "\t%s: %10llu\n", "Total regular", total);
seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
i915_guc_client_info(m, dev_priv, &client);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index d7543ef..8b0a34d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,9 +78,8 @@ static inline bool host2guc_action_response(struct
drm_i915_private *dev_priv,
static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 status;
- int i;
- int ret;
+ u32 status, response;
+ int ret, i;
if (WARN_ON(len < 1 || len > 15))
return -EINVAL;
@@ -99,6 +98,8 @@ static int host2guc_action(struct intel_guc *guc, u32 *data,
u32 len)
/* No HOST2GUC command should take longer than 10ms */
ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
+ response = I915_READ(SOFT_SCRATCH(15));
+ dev_priv->guc.action_status = status;
if (status != GUC2HOST_STATUS_SUCCESS) {
/*
* Either the GuC explicitly returned an error (which
@@ -108,15 +109,15 @@ static int host2guc_action(struct intel_guc *guc, u32
*data, u32 len)
if (ret != -ETIMEDOUT)
ret = -EIO;
- DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
+ DRM_ERROR("GuC: host2guc action 0x%X failed. ret=%d "
"status=0x%08X response=0x%08X\n",
- data[0], ret, status,
- I915_READ(SOFT_SCRATCH(15)));
+ data[0], ret, status, response);
- dev_priv->guc.action_fail += 1;
+ dev_priv->guc.action_fail_count += 1;
+ dev_priv->guc.action_fail_cmd = data[0];
+ dev_priv->guc.action_fail_status = status;
dev_priv->guc.action_err = ret;
}
- dev_priv->guc.action_status = status;
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -589,6 +590,9 @@ int i915_guc_submit(struct i915_guc_client *client,
guc->submissions[engine_id] += 1;
guc->last_seqno[engine_id] = rq->seqno;
+ if (q_ret)
+ guc->failures[engine_id] += 1;
+
return q_ret;
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 73002e9..c3281e7 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -103,11 +103,16 @@ struct intel_guc {
uint64_t action_count; /* Total commands issued*/
uint32_t action_cmd;/* Last command word*/
uint32_t action_status; /* Last return status */
- uint32_t actio
[Intel-gfx] [PATCH v2 2/9] drm/i915/error: capture ringbuffer pointed to by START
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 36 +--
2 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6cca108..84bbd98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -565,7 +565,7 @@ struct drm_i915_error_state {
int page_count;
u64 gtt_offset;
u32 *pages[0];
- } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
+ } *req_ringbuffer, *hw_ringbuffer, *batchbuffer,
*wa_batchbuffer, *ctx, *hws_page;
struct drm_i915_error_request {
long jiffies;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8efc8f9a..d4d46ac 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -477,13 +477,20 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
}
}
- if ((obj = error->ring[i].ringbuffer)) {
+ if ((obj = error->ring[i].req_ringbuffer)) {
err_printf(m, "%s --- ringbuffer = 0x%08x\n",
dev_priv->ring[i].name,
lower_32_bits(obj->gtt_offset));
print_error_obj(m, obj);
}
+ if ((obj = error->ring[i].hw_ringbuffer)) {
+ err_printf(m, "%s --- HW ringbuffer = 0x%08x\n",
+ dev_priv->ring[i].name,
+ lower_32_bits(obj->gtt_offset));
+ print_error_obj(m, obj);
+ }
+
if ((obj = error->ring[i].hws_page)) {
u64 hws_offset = obj->gtt_offset;
u32 *hws_page = &obj->pages[0][0];
@@ -594,7 +601,8 @@ static void i915_error_state_free(struct kref *error_ref)
for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
i915_error_object_free(error->ring[i].batchbuffer);
i915_error_object_free(error->ring[i].wa_batchbuffer);
- i915_error_object_free(error->ring[i].ringbuffer);
+ i915_error_object_free(error->ring[i].req_ringbuffer);
+ i915_error_object_free(error->ring[i].hw_ringbuffer);
i915_error_object_free(error->ring[i].hws_page);
i915_error_object_free(error->ring[i].ctx);
kfree(error->ring[i].requests);
@@ -1006,19 +1014,27 @@ static void i915_gem_record_active_context(struct
intel_engine_cs *ring,
{
struct drm_i915_private *dev_priv = ring->dev->dev_private;
struct drm_i915_gem_object *obj;
-
- /* Currently render ring is the only HW context user */
- if (ring->id != RCS || !error->ccid)
- return;
+ u64 base;
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
if (!i915_gem_obj_ggtt_bound(obj))
continue;
- if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj))
{
- ering->ctx = i915_error_ggtt_object_create(dev_priv,
obj);
- break;
+ base = i915_gem_obj_ggtt_offset(obj);
+
+ if (base == ering->start) {
+ ering->hw_ringbuffer =
i915_error_ggtt_object_create(dev_priv, obj);
+ continue;
}
+
+ if (!error->ccid)
+ continue;
+
+ if (i915.enable_execlists)
+ base += LRC_PPHWSP_PN * PAGE_SIZE;
+
+ if (base == (error->ccid & PAGE_MASK))
+ ering->ctx = i915_error_ggtt_object_create(dev_priv,
obj);
}
}
@@ -1093,7 +1109,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
error->ring[i].cpu_ring_head = rbuf->head;
error->ring[i].cpu_ring_tail = rbuf->tail;
- error->ring[i].ringbuffer =
+ error->ring[i].req_ringbuffer =
i915_error_ggtt_object_create(dev_priv, rbuf->obj);
error->ring[i].hws_page =
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/9] Capture more useful details in error state
Few patches to capture more useful details in error state - these details include execlist state, csb events and their decoded form, GuC firmware fetch and load status, submission stats, WA ctx batch buffer. GuC details are only captured if GuC submission is enabled. Except WA ctx batch all other patches are already sent as part of preemption patch series but these are independent patches; it may take a while before preemption patches are reviewed, merged but these patches can be useful now so extracted them from that series. Example output looks like this, EXECLIST_STATUS: 0x0301 EXECLIST_CTX_ID: 0x EXECLIST_CSBPTR: 0x0505 EXECLIST_CSB_WR: 5 EXECLIST_CSB_RD: 5 EXECLIST_CTX/CSB[0]: 0x000.0 / 0x0001 | I->A | | | | | | EXECLIST_CTX/CSB[1]: 0x000.00a33 / 0x0018 | | | | A->I | DONE | | EXECLIST_CTX/CSB[2]: 0x000.0 / 0x0001 | I->A | | | | | | EXECLIST_CTX/CSB[3]: 0x000.00a33 / 0x0018 | | | | A->I | DONE | | EXECLIST_CTX/CSB[4]: 0x000.0 / 0x0001 | I->A | | | | | | EXECLIST_CTX/CSB[5]: 0x000.00a33 / 0x0018 | | | | A->I | DONE | | v1: http://www.spinics.net/lists/intel-gfx/msg86671.html Arun Siluvery (1): drm/i915/error: Capture WA ctx batch in error state Dave Gordon (8): drm/i915/error: capture execlist state on error drm/i915/error: capture ringbuffer pointed to by START drm/i915/error: report ctx id & desc for each request in the queue drm/i915/error: improve CSB reporting drm/i915/error: capture errored context based on request context-id drm/i915/error: enhanced error capture of requests drm/i915/guc: Improve action error reporting drm/i915/error: add GuC state error capture & decode drivers/gpu/drm/i915/i915_debugfs.c| 17 +- drivers/gpu/drm/i915/i915_drv.h| 24 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 299 ++--- drivers/gpu/drm/i915/i915_guc_submission.c | 20 +- drivers/gpu/drm/i915/intel_guc.h | 9 +- 5 files changed, 324 insertions(+), 45 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [v2] drm/i915: Check for get_pages instead of shmem (filp)
Do you guys get the CI mails? This version has regressions. v1 did not. I don't
know what to trust.
On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote:
> This behavior of checking for a shmem backed GEM object was introduced here:
> commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab
> Author: Brad Volkin
> Date: Tue Feb 18 10:15:45 2014 -0800
>
> drm/i915: Refactor shmem pread setup
>
> It is possible for an object to not be a shmem backed GEM object (for example
> userptr objects). An example of how we hit this failure can be found through
> copy_batch() in the command parser because we allocate a userptr object for
> the
> batch which contains privileged instructions. Userptr calls
> drm_gem_private_object_init() which explicitly sets the filp to none.
>
> NOTE: I manually retyped this from a test machine. So I haven't even compiled
> this exact patch.
>
> v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon)
>
> Cc: Chris Wilson
> Cc: Kristian Høgsberg
> Cc: Dave Gordon
> Signed-off-by: Ben Widawsky
> Tested-by: Jordan Justen (v1)
> Reviewed-by: Jordan Justen (v1)
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e9b19bc..7fd79b0 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -489,7 +489,7 @@ int i915_gem_obj_prepare_shmem_read(struct
> drm_i915_gem_object *obj,
>
> *needs_clflush = 0;
>
> - if (!obj->base.filp)
> + if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
> return -EINVAL;
>
> if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
> --
> 2.7.0
>
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] Use uint64_t in eviction memory subtest parameters
On Mon, Feb 08, 2016 at 04:50:39PM +0200, Mika Kuoppala wrote: > With large apertures we need to use uint64_t for > counts and sizes. commit 0e2071411a4d4e1488a821daf522dffde2809e03 > paved way for this but forgot to change the subtest parameters. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=93849 > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala > --- > tests/gem_evict_alignment.c | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/tests/gem_evict_alignment.c b/tests/gem_evict_alignment.c > index 6fa70f0cd0f9..d7d0ed0aec73 100644 > --- a/tests/gem_evict_alignment.c > +++ b/tests/gem_evict_alignment.c > @@ -129,10 +129,11 @@ copy(int fd, uint32_t dst, uint32_t src, uint32_t > *all_bo, int n_bo, int alignme int n_bo. int alignment -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state.
Yes it does. The passed in pipe_config is the crtc's state. And
if you want to store the thing in the top level atomic state you
just dig up that up from the crtc state:
to_intel_atomic_state(pipe_config->base.state)
or something along those lines).
> When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
>
> Signed-off-by: Clint Taylor
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?=
>
> ---
> drivers/gpu/drm/i915/i915_drv.h |2 +-
> drivers/gpu/drm/i915/intel_ddi.c |2 +-
> drivers/gpu/drm/i915/intel_display.c | 83
> +-
> drivers/gpu/drm/i915/intel_dp.c |9 +++-
> drivers/gpu/drm/i915/intel_drv.h |1 +
> 5 files changed, 81 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..372a68f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private
> *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 :
> 308570 );
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
>* check if the pre-os intialized the display
> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +98
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
On Wed, Feb 10, 2016 at 02:17:41PM +0100, Lukas Wunner wrote:
> Hi,
>
> On Wed, Feb 10, 2016 at 09:41:38AM +0100, Lukas Wunner wrote:
> > On Wed, Feb 10, 2016 at 12:24:51PM +1100, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > After merging the drm-misc tree, today's linux-next build (arm
> > > multi_v7_defconfig) failed like this:
> > >
> > > In file included from drivers/gpu/drm/nouveau/nouveau_drm.c:25:0:
> > > include/linux/apple-gmux.h: In function 'apple_gmux_present':
> > > include/linux/apple-gmux.h:36:42: error: implicit declaration of function
> > > 'acpi_dev_present' [-Werror=implicit-function-declaration]
> > > return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
> > > ^
> > >
> > > Caused by commit
> > >
> > > 2413306c2566 ("apple-gmux: Add helper for presence detect")
> > >
> > > I have used the drm-misc tree from next-20160209 for today.
> >
> > Ugh, apologies, I didn't have a non-ACPI platform available to test
> > this on.
> >
> > Solution is to either add to include/linux/acpi.h
> >
> > static inline bool acpi_dev_present(const char *hid)
> > {
> > return false;
> > }
> >
> > somewhere below
> >
> > #else /* !CONFIG_ACPI */
> >
> > or alternatively to add to include/linux/apple-gmux.h
> >
> > IS_ENABLED(CONFIG_ACPI)
> >
> > in apple_gmux_present().
> >
> > I'll check the other users of acpi_dev_present() to see which of
> > these two solutions is more appropriate and will post a fix shortly.
>
> The patch included below fixes the build if CONFIG_ACPI is not set.
>
> @Daniel Vetter: Would it be possible to squash this with 2413306c2566
> ("apple-gmux: Add helper for presence detect") on topic/drm-misc so
> as to avoid build breakage for anyone trying to bisect between that
> commit and this fix?
>
> I checked all other users of acpi_dev_present() and all of them are
> only compiled if CONFIG_ACPI is set. Hence I opted to fix this in
> rather than in .
>
> Thanks again Stephen for reporting this at such an early stage,
> though doubtlessly it would have been better if I had thought of
> this possibility when preparing the original patch, or if I had
> compile-tested without CONFIG_ACPI. :-(
Since !ACPI and enabling APPLE_GMUX is a bit a fringe config I don't think
this will hurt bisectability at all on a real system. So just applied this
one on top of drm-misc.
Thanks, Daniel
>
> Lukas
>
> -- >8 --
> Subject: [PATCH] apple-gmux: Fix build breakage if !CONFIG_ACPI
>
> The DRM drivers i915, nouveau and radeon may be compiled with
> CONFIG_ACPI not set, in which case acpi_dev_present() is undefined.
>
> Add a no-op stub for apple_gmux_present() which is used if
> CONFIG_APPLE_GMUX is not enabled to avoid build breakage.
> (CONFIG_APPLE_GMUX depends on CONFIG_ACPI.)
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Lukas Wunner
> ---
> include/linux/apple-gmux.h | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/include/linux/apple-gmux.h b/include/linux/apple-gmux.h
> index feebc28..b2d32e0 100644
> --- a/include/linux/apple-gmux.h
> +++ b/include/linux/apple-gmux.h
> @@ -22,6 +22,8 @@
>
> #define GMUX_ACPI_HID "APP000B"
>
> +#if IS_ENABLED(CONFIG_APPLE_GMUX)
> +
> /**
> * apple_gmux_present() - detect if gmux is built into the machine
> *
> @@ -33,7 +35,16 @@
> */
> static inline bool apple_gmux_present(void)
> {
> - return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
> + return acpi_dev_present(GMUX_ACPI_HID);
> }
>
> +#else /* !CONFIG_APPLE_GMUX */
> +
> +static inline bool apple_gmux_present(void)
> +{
> + return false;
> +}
> +
> +#endif /* !CONFIG_APPLE_GMUX */
> +
> #endif /* LINUX_APPLE_GMUX_H */
> --
> 1.8.5.2 (Apple Git-48)
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi,
On Wed, Feb 10, 2016 at 09:41:38AM +0100, Lukas Wunner wrote:
> On Wed, Feb 10, 2016 at 12:24:51PM +1100, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the drm-misc tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> > In file included from drivers/gpu/drm/nouveau/nouveau_drm.c:25:0:
> > include/linux/apple-gmux.h: In function 'apple_gmux_present':
> > include/linux/apple-gmux.h:36:42: error: implicit declaration of function
> > 'acpi_dev_present' [-Werror=implicit-function-declaration]
> > return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
> > ^
> >
> > Caused by commit
> >
> > 2413306c2566 ("apple-gmux: Add helper for presence detect")
> >
> > I have used the drm-misc tree from next-20160209 for today.
>
> Ugh, apologies, I didn't have a non-ACPI platform available to test
> this on.
>
> Solution is to either add to include/linux/acpi.h
>
> static inline bool acpi_dev_present(const char *hid)
> {
> return false;
> }
>
> somewhere below
>
> #else /* !CONFIG_ACPI */
>
> or alternatively to add to include/linux/apple-gmux.h
>
> IS_ENABLED(CONFIG_ACPI)
>
> in apple_gmux_present().
>
> I'll check the other users of acpi_dev_present() to see which of
> these two solutions is more appropriate and will post a fix shortly.
The patch included below fixes the build if CONFIG_ACPI is not set.
@Daniel Vetter: Would it be possible to squash this with 2413306c2566
("apple-gmux: Add helper for presence detect") on topic/drm-misc so
as to avoid build breakage for anyone trying to bisect between that
commit and this fix?
I checked all other users of acpi_dev_present() and all of them are
only compiled if CONFIG_ACPI is set. Hence I opted to fix this in
rather than in .
Thanks again Stephen for reporting this at such an early stage,
though doubtlessly it would have been better if I had thought of
this possibility when preparing the original patch, or if I had
compile-tested without CONFIG_ACPI. :-(
Lukas
-- >8 --
Subject: [PATCH] apple-gmux: Fix build breakage if !CONFIG_ACPI
The DRM drivers i915, nouveau and radeon may be compiled with
CONFIG_ACPI not set, in which case acpi_dev_present() is undefined.
Add a no-op stub for apple_gmux_present() which is used if
CONFIG_APPLE_GMUX is not enabled to avoid build breakage.
(CONFIG_APPLE_GMUX depends on CONFIG_ACPI.)
Reported-by: Stephen Rothwell
Signed-off-by: Lukas Wunner
---
include/linux/apple-gmux.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/linux/apple-gmux.h b/include/linux/apple-gmux.h
index feebc28..b2d32e0 100644
--- a/include/linux/apple-gmux.h
+++ b/include/linux/apple-gmux.h
@@ -22,6 +22,8 @@
#define GMUX_ACPI_HID "APP000B"
+#if IS_ENABLED(CONFIG_APPLE_GMUX)
+
/**
* apple_gmux_present() - detect if gmux is built into the machine
*
@@ -33,7 +35,16 @@
*/
static inline bool apple_gmux_present(void)
{
- return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
+ return acpi_dev_present(GMUX_ACPI_HID);
}
+#else /* !CONFIG_APPLE_GMUX */
+
+static inline bool apple_gmux_present(void)
+{
+ return false;
+}
+
+#endif /* !CONFIG_APPLE_GMUX */
+
#endif /* LINUX_APPLE_GMUX_H */
--
1.8.5.2 (Apple Git-48)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/8] Kill off intel_crtc->atomic!
This is a rebased version of the original series. The upstream fbc changes required a rework of some of the patches, but with atomic encoder masks this series will work as intended. v4 because v3 had a small issue with a compiler error in wait_vblank removal, and I forgot to send it to the ml. Maarten Lankhorst (8): drm/i915: Pass crtc state to modeset_get_crtc_power_domains. drm/i915: Unify power domain handling. drm/i915: Kill off intel_crtc->atomic.wait_vblank, v4. drm/i915: Remove update_sprite_watermarks. drm/i915: Remove some post-commit members from intel_crtc->atomic, v2. drm/i915: Nuke fbc members from intel_crtc->atomic, v2. drm/i915: Do not compute watermarks on a noop. drm/i915: Remove vblank wait from hsw_enable_ips. drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_display.c | 265 +++ drivers/gpu/drm/i915/intel_drv.h | 36 ++--- drivers/gpu/drm/i915/intel_pm.c | 61 4 files changed, 196 insertions(+), 168 deletions(-) -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 6/8] drm/i915: Nuke fbc members from intel_crtc->atomic, v2.
Factor out intel_fbc_supports_rotation and use it in
pre_plane_update as well. This leaves intel_crtc->atomic
empty, so remove it too.
Changes since v1:
- Add a intel_fbc_supports_rotation helper.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 58 +---
drivers/gpu/drm/i915/intel_drv.h | 15 --
2 files changed, 20 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 54be8a255f1f..00cb261c6787 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4782,11 +4782,9 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
- struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_pri_state =
drm_atomic_get_existing_plane_state(old_state, primary);
@@ -4798,22 +4796,19 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
if (pipe_config->wm_changed && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
- if (atomic->update_fbc)
- intel_fbc_post_update(crtc);
-
if (old_pri_state) {
struct intel_plane_state *primary_state =
to_intel_plane_state(primary->state);
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
+ intel_fbc_post_update(crtc);
+
if (primary_state->visible &&
(needs_modeset(&pipe_config->base) ||
!old_primary_state->visible))
intel_post_enable_primary(&crtc->base);
}
-
- memset(atomic, 0, sizeof(*atomic));
}
static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
@@ -4821,7 +4816,6 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->base.state);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
@@ -4830,17 +4824,17 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
drm_atomic_get_existing_plane_state(old_state, primary);
bool modeset = needs_modeset(&pipe_config->base);
- if (atomic->update_fbc)
- intel_fbc_pre_update(crtc);
-
if (old_pri_state) {
struct intel_plane_state *primary_state =
to_intel_plane_state(primary->state);
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
+ bool turn_off = old_primary_state->visible &&
+ (modeset || !primary_state->visible);
+
+ intel_fbc_pre_update(crtc);
- if (old_primary_state->visible &&
- (modeset || !primary_state->visible))
+ if (turn_off)
intel_pre_disable_primary(&crtc->base);
}
@@ -11822,27 +11816,17 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
if (visible || was_visible)
pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
- switch (plane->type) {
- case DRM_PLANE_TYPE_PRIMARY:
- intel_crtc->atomic.update_fbc = true;
-
- break;
- case DRM_PLANE_TYPE_CURSOR:
- break;
- case DRM_PLANE_TYPE_OVERLAY:
- /*
-* WaCxSRDisabledForSpriteScaling:ivb
-*
-* cstate->update_wm was already set above, so this flag will
-* take effect when we commit and program watermarks.
-*/
- if (IS_IVYBRIDGE(dev) &&
- needs_scaling(to_intel_plane_state(plane_state)) &&
- !needs_scaling(old_plane_state))
- pipe_config->disable_lp_wm = true;
+ /*
+* WaCxSRDisabledForSpriteScaling:ivb
+*
+* cstate->update_wm was already set above, so this flag will
+* take effect when we commit and program watermarks.
+*/
+ if (plane->type
[Intel-gfx] [PATCH v4 1/8] drm/i915: Pass crtc state to modeset_get_crtc_power_domains.
Use our newly created encoder_mask to iterate over the encoders.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30d4db0d776f..b479ba6238d7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5301,31 +5301,37 @@ intel_display_port_aux_power_domain(struct
intel_encoder *intel_encoder)
}
}
-static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
+static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->dev;
- struct intel_encoder *intel_encoder;
+ struct drm_encoder *encoder;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
unsigned long mask;
- enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
+ enum transcoder transcoder = crtc_state->cpu_transcoder;
- if (!crtc->state->active)
+ if (!crtc_state->base.active)
return 0;
mask = BIT(POWER_DOMAIN_PIPE(pipe));
mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
- if (intel_crtc->config->pch_pfit.enabled ||
- intel_crtc->config->pch_pfit.force_thru)
+ if (crtc_state->pch_pfit.enabled ||
+ crtc_state->pch_pfit.force_thru)
mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
- for_each_encoder_on_crtc(dev, crtc, intel_encoder)
+ drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
+ struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
+
mask |= BIT(intel_display_port_power_domain(intel_encoder));
+ }
return mask;
}
-static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
+static unsigned long
+modeset_get_crtc_power_domains(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -5333,7 +5339,8 @@ static unsigned long
modeset_get_crtc_power_domains(struct drm_crtc *crtc)
unsigned long domains, new_domains, old_domains;
old_domains = intel_crtc->enabled_power_domains;
- intel_crtc->enabled_power_domains = new_domains =
get_crtc_power_domains(crtc);
+ intel_crtc->enabled_power_domains = new_domains =
+ get_crtc_power_domains(crtc, crtc_state);
domains = new_domains & ~old_domains;
@@ -5365,7 +5372,8 @@ static void modeset_update_crtc_power_domains(struct
drm_atomic_state *state)
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (needs_modeset(crtc->state))
put_domains[to_intel_crtc(crtc)->pipe] =
- modeset_get_crtc_power_domains(crtc);
+ modeset_get_crtc_power_domains(crtc,
+ to_intel_crtc_state(crtc->state));
}
if (dev_priv->display.modeset_commit_cdclk &&
@@ -13486,7 +13494,8 @@ static int intel_atomic_commit(struct drm_device *dev,
}
if (update_pipe) {
- put_domains = modeset_get_crtc_power_domains(crtc);
+ put_domains = modeset_get_crtc_power_domains(crtc,
+ to_intel_crtc_state(crtc->state));
/* make sure intel_modeset_check_state runs */
hw_check = true;
@@ -15830,7 +15839,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
unsigned long put_domains;
- put_domains = modeset_get_crtc_power_domains(&crtc->base);
+ put_domains = modeset_get_crtc_power_domains(&crtc->base,
crtc->config);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
}
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/8] drm/i915: Kill off intel_crtc->atomic.wait_vblank, v4.
Currently we perform our own wait in post_plane_update,
but the atomic core performs another one in wait_for_vblanks.
This means that 2 vblanks are done when a fb is changed,
which is a bit overkill.
Merge them by creating a helper function that takes a crtc mask
for the planes to wait on.
The broadwell vblank workaround may look gone entirely but this is
not the case. pipe_config->wm_changed is set to true
when any plane is turned on, which forces a vblank wait.
Changes since v1:
- Removing the double vblank wait on broadwell moved to its own commit.
Changes since v2:
- Move out POWER_DOMAIN_MODESET handling to its own commit.
Changes since v3:
- Do not wait for vblank on legacy cursor updates. (Ville)
- Move broadwell vblank workaround comment to page_flip_finished. (Ville)
Changes since v4:
- Compile fix, legacy_cursor_flip -> *_update.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 86 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
3 files changed, 67 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 4625f8a9ba12..8e579a8505ac 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -97,6 +97,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
crtc_state->wm_changed = false;
+ crtc_state->fb_changed = false;
return &crtc_state->base;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 804f2c6f260d..4d4dddc1f970 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4785,9 +4785,6 @@ static void intel_post_plane_update(struct intel_crtc
*crtc)
to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
- if (atomic->wait_vblank)
- intel_wait_for_vblank(dev, crtc->pipe);
-
intel_frontbuffer_flip(dev, atomic->fb_bits);
crtc->wm.cxsr_allowed = true;
@@ -10902,6 +10899,12 @@ static bool page_flip_finished(struct intel_crtc *crtc)
return true;
/*
+* BDW signals flip done immediately if the plane
+* is disabled, even if the plane enable is already
+* armed to occur at the next vblank :(
+*/
+
+ /*
* A DSPSURFLIVE check isn't enough in case the mmio and CS flips
* used the same base address. In that case the mmio flip might
* have completed, but the CS hasn't even executed the flip yet.
@@ -11778,6 +11781,9 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
if (!was_visible && !visible)
return 0;
+ if (fb != old_plane_state->base.fb)
+ pipe_config->fb_changed = true;
+
turn_off = was_visible && (!visible || mode_changed);
turn_on = visible && (!was_visible || mode_changed);
@@ -11793,8 +11799,6 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
/* must disable cxsr around plane enable/disable */
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
- if (is_crtc_enabled)
- intel_crtc->atomic.wait_vblank = true;
pipe_config->disable_cxsr = true;
}
} else if (intel_wm_need_update(plane, plane_state)) {
@@ -11810,14 +11814,6 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
intel_crtc->atomic.post_enable_primary = turn_on;
intel_crtc->atomic.update_fbc = true;
- /*
-* BDW signals flip done immediately if the plane
-* is disabled, even if the plane enable is already
-* armed to occur at the next vblank :(
-*/
- if (turn_on && IS_BROADWELL(dev))
- intel_crtc->atomic.wait_vblank = true;
-
break;
case DRM_PLANE_TYPE_CURSOR:
break;
@@ -11831,12 +11827,10 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
if (IS_IVYBRIDGE(dev) &&
needs_scaling(to_intel_plane_state(plane_state)) &&
!needs_scaling(old_plane_state)) {
- to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
- } else if (turn_off && !mode_changed) {
- intel_crtc->atomic.wait_vblank = true;
+ pipe_config->disable_lp_wm = true;
+ } else if (turn_off && !mode_changed)
intel_crtc->atomic.update_sprite_watermarks |=
1 << i;
- }
break;
}
@@ -13370,6 +13364,48 @@
[Intel-gfx] [PATCH v4 8/8] drm/i915: Remove vblank wait from hsw_enable_ips.
intel_post_plane_update did an extra vblank wait that's no longer needed when
enabling ips.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6bb1f5dbc7a0..19a8d376d63e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4569,9 +4569,6 @@ void hsw_enable_ips(struct intel_crtc *crtc)
if (!crtc->config->ips_enabled)
return;
- /* We can only enable IPS after we enable a plane and wait for a vblank
*/
- intel_wait_for_vblank(dev, crtc->pipe);
-
assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(dev)) {
mutex_lock(&dev_priv->rps.hw_lock);
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/8] drm/i915: Do not compute watermarks on a noop.
No atomic state should be included after all validation when nothing has
changed. During modeset all active planes will be added to the state,
while disabled planes won't change their state.
Signed-off-by: Maarten Lankhorst
Cc: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 13
drivers/gpu/drm/i915/intel_pm.c | 61 +---
3 files changed, 51 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 00cb261c6787..6bb1f5dbc7a0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11910,7 +11910,8 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
}
ret = 0;
- if (dev_priv->display.compute_pipe_wm) {
+ if (dev_priv->display.compute_pipe_wm &&
+ (mode_changed || pipe_config->update_pipe ||
crtc_state->planes_changed)) {
ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8effb9ece21e..144597ac74e3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1583,6 +1583,19 @@ intel_atomic_get_crtc_state(struct drm_atomic_state
*state,
return to_intel_crtc_state(crtc_state);
}
+
+static inline struct intel_plane_state *
+intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
+ struct intel_plane *plane)
+{
+ struct drm_plane_state *plane_state;
+
+ plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
+
+ return to_intel_plane_state(plane_state);
+}
+
+
int intel_atomic_setup_scalers(struct drm_device *dev,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 379eabe093cb..8fb8c6891ae6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2010,11 +2010,18 @@ static void ilk_compute_wm_level(const struct
drm_i915_private *dev_priv,
cur_latency *= 5;
}
- result->pri_val = ilk_compute_pri_wm(cstate, pristate,
-pri_latency, level);
- result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
- result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
- result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
+ if (pristate) {
+ result->pri_val = ilk_compute_pri_wm(cstate, pristate,
+pri_latency, level);
+ result->fbc_val = ilk_compute_fbc_wm(cstate, pristate,
result->pri_val);
+ }
+
+ if (sprstate)
+ result->spr_val = ilk_compute_spr_wm(cstate, sprstate,
spr_latency);
+
+ if (curstate)
+ result->cur_val = ilk_compute_cur_wm(cstate, curstate,
cur_latency);
+
result->enable = true;
}
@@ -2287,7 +2294,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc
*intel_crtc,
const struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_state *cstate = NULL;
struct intel_plane *intel_plane;
- struct drm_plane_state *ps;
struct intel_plane_state *pristate = NULL;
struct intel_plane_state *sprstate = NULL;
struct intel_plane_state *curstate = NULL;
@@ -2306,30 +2312,37 @@ static int ilk_compute_pipe_wm(struct intel_crtc
*intel_crtc,
memset(pipe_wm, 0, sizeof(*pipe_wm));
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- ps = drm_atomic_get_plane_state(state,
- &intel_plane->base);
- if (IS_ERR(ps))
- return PTR_ERR(ps);
+ struct intel_plane_state *ps;
+
+ ps = intel_atomic_get_existing_plane_state(state,
+ intel_plane);
+ if (!ps)
+ continue;
if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
- pristate = to_intel_plane_state(ps);
- else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
- sprstate = to_intel_plane_state(ps);
- else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
- curstate = to_intel_plane_state(ps);
+ pristate = ps;
+ else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
+ sprstate = ps;
+
+ if (ps) {
+ pipe_wm->sprites_enabled = sprstate->visible;
+ pipe_wm
[Intel-gfx] [PATCH v4 4/8] drm/i915: Remove update_sprite_watermarks.
Commit 791a32be6eb2 ("drm/i915: Drop intel_update_sprite_watermarks")
removes the use of this variable, but forgot to remove it.
Reviewed-by: Matt Roper
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4dddc1f970..c1f94eee8028 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11748,7 +11748,6 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
struct intel_plane_state *old_plane_state =
to_intel_plane_state(plane->state);
int idx = intel_crtc->base.base.id, ret;
- int i = drm_plane_index(plane);
bool mode_changed = needs_modeset(crtc_state);
bool was_crtc_enabled = crtc->state->active;
bool is_crtc_enabled = crtc_state->active;
@@ -11826,11 +11825,8 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
*/
if (IS_IVYBRIDGE(dev) &&
needs_scaling(to_intel_plane_state(plane_state)) &&
- !needs_scaling(old_plane_state)) {
+ !needs_scaling(old_plane_state))
pipe_config->disable_lp_wm = true;
- } else if (turn_off && !mode_changed)
- intel_crtc->atomic.update_sprite_watermarks |=
- 1 << i;
break;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e911c86f873b..d4e441f3aecf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -549,7 +549,6 @@ struct intel_crtc_atomic_commit {
/* Sleepable operations to perform after commit */
unsigned fb_bits;
bool post_enable_primary;
- unsigned update_sprite_watermarks;
/* Sleepable operations to perform before and after commit */
bool update_fbc;
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 5/8] drm/i915: Remove some post-commit members from intel_crtc->atomic, v2.
fb_bits is useful to have in the crtc_state for cs flips when
the code is updated to use intel_frontbuffer_flip_prepare/complete.
So calculate it in advance and move it to crtc_state. The other stuff
can be calculated in post_plane_update, and aren't useful elsewhere.
Changes since v1:
- Changing wording, remove comment about loop.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 29 +
drivers/gpu/drm/i915/intel_drv.h | 5 +
3 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 8e579a8505ac..9a45cff26767 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -98,6 +98,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->disable_cxsr = false;
crtc_state->wm_changed = false;
crtc_state->fb_changed = false;
+ crtc_state->fb_bits = 0;
return &crtc_state->base;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c1f94eee8028..54be8a255f1f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4778,14 +4778,20 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
hsw_disable_ips(intel_crtc);
}
-static void intel_post_plane_update(struct intel_crtc *crtc)
+static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_atomic_state *old_state = old_crtc_state->base.state;
struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_plane *primary = crtc->base.primary;
+ struct drm_plane_state *old_pri_state =
+ drm_atomic_get_existing_plane_state(old_state, primary);
- intel_frontbuffer_flip(dev, atomic->fb_bits);
+ intel_frontbuffer_flip(dev, pipe_config->fb_bits);
crtc->wm.cxsr_allowed = true;
@@ -4795,8 +4801,17 @@ static void intel_post_plane_update(struct intel_crtc
*crtc)
if (atomic->update_fbc)
intel_fbc_post_update(crtc);
- if (atomic->post_enable_primary)
- intel_post_enable_primary(&crtc->base);
+ if (old_pri_state) {
+ struct intel_plane_state *primary_state =
+ to_intel_plane_state(primary->state);
+ struct intel_plane_state *old_primary_state =
+ to_intel_plane_state(old_pri_state);
+
+ if (primary_state->visible &&
+ (needs_modeset(&pipe_config->base) ||
+!old_primary_state->visible))
+ intel_post_enable_primary(&crtc->base);
+ }
memset(atomic, 0, sizeof(*atomic));
}
@@ -11805,12 +11820,10 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
}
if (visible || was_visible)
- intel_crtc->atomic.fb_bits |=
- to_intel_plane(plane)->frontbuffer_bit;
+ pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
switch (plane->type) {
case DRM_PLANE_TYPE_PRIMARY:
- intel_crtc->atomic.post_enable_primary = turn_on;
intel_crtc->atomic.update_fbc = true;
break;
@@ -13534,7 +13547,7 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
for_each_crtc_in_state(state, crtc, crtc_state, i) {
- intel_post_plane_update(to_intel_crtc(crtc));
+ intel_post_plane_update(to_intel_crtc_state(crtc_state));
if (put_domains[i])
modeset_put_power_domains(dev_priv, put_domains[i]);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d4e441f3aecf..803591d1e613 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -376,6 +376,7 @@ struct intel_crtc_state {
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync
mode.flags */
unsigned long quirks;
+ unsigned fb_bits; /* framebuffers to flip */
bool update_pipe; /* can a fast modeset be performed? */
bool disable_cxsr;
bool wm_changed; /* watermarks are updated */
@@ -547,10 +548,6 @@ struct intel_crtc_atomic_commit {
/* Sleepable operations to perform before commit */
/* Sleepable operations to perform after commit */
- unsigned fb_bits;
- bool post_enable_primary;
-
- /* Sle
[Intel-gfx] [PATCH v4 2/8] drm/i915: Unify power domain handling.
Right now there's separate power domain handling for update_pipe and
modesets. Unify this and only grab POWER_DOMAIN_MODESET once.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 69 +---
1 file changed, 24 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b479ba6238d7..804f2c6f260d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5359,32 +5359,6 @@ static void modeset_put_power_domains(struct
drm_i915_private *dev_priv,
intel_display_power_put(dev_priv, domain);
}
-static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
-{
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct drm_device *dev = state->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned long put_domains[I915_MAX_PIPES] = {};
- struct drm_crtc_state *crtc_state;
- struct drm_crtc *crtc;
- int i;
-
- for_each_crtc_in_state(state, crtc, crtc_state, i) {
- if (needs_modeset(crtc->state))
- put_domains[to_intel_crtc(crtc)->pipe] =
- modeset_get_crtc_power_domains(crtc,
- to_intel_crtc_state(crtc->state));
- }
-
- if (dev_priv->display.modeset_commit_cdclk &&
- intel_state->dev_cdclk != dev_priv->cdclk_freq)
- dev_priv->display.modeset_commit_cdclk(state);
-
- for (i = 0; i < I915_MAX_PIPES; i++)
- if (put_domains[i])
- modeset_put_power_domains(dev_priv, put_domains[i]);
-}
-
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -13422,6 +13396,7 @@ static int intel_atomic_commit(struct drm_device *dev,
struct drm_crtc *crtc;
int ret = 0, i;
bool hw_check = intel_state->modeset;
+ unsigned long put_domains[I915_MAX_PIPES] = {};
ret = intel_atomic_prepare_commit(dev, state, async);
if (ret) {
@@ -13437,11 +13412,22 @@ static int intel_atomic_commit(struct drm_device *dev,
sizeof(intel_state->min_pixclk));
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->atomic_cdclk_freq = intel_state->cdclk;
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
}
for_each_crtc_in_state(state, crtc, crtc_state, i) {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ if (needs_modeset(crtc->state) ||
+ to_intel_crtc_state(crtc->state)->update_pipe) {
+ hw_check = true;
+
+ put_domains[to_intel_crtc(crtc)->pipe] =
+ modeset_get_crtc_power_domains(crtc,
+ to_intel_crtc_state(crtc->state));
+ }
+
if (!needs_modeset(crtc->state))
continue;
@@ -13474,7 +13460,10 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_commit(state);
drm_atomic_helper_update_legacy_modeset_state(state->dev,
state);
- modeset_update_crtc_power_domains(state);
+
+ if (dev_priv->display.modeset_commit_cdclk &&
+ intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ dev_priv->display.modeset_commit_cdclk(state);
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -13483,24 +13472,12 @@ static int intel_atomic_commit(struct drm_device *dev,
bool modeset = needs_modeset(crtc->state);
bool update_pipe = !modeset &&
to_intel_crtc_state(crtc->state)->update_pipe;
- unsigned long put_domains = 0;
-
- if (modeset)
- intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
if (modeset && crtc->state->active) {
update_scanline_offset(to_intel_crtc(crtc));
dev_priv->display.crtc_enable(crtc);
}
- if (update_pipe) {
- put_domains = modeset_get_crtc_power_domains(crtc,
- to_intel_crtc_state(crtc->state));
-
- /* make sure intel_modeset_check_state runs */
- hw_check = true;
- }
-
if (!modeset)
intel_pre_plane_update(to_intel_crtc_state(crtc_state));
@@ -13511,19 +13488,21 @@ static int intel_atomic_commit(struct drm_device *dev,
(crtc->state->planes_changed || update_pipe))
drm_atomic_helper
Re: [Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC
On 10/02/16 09:37, Daniel Vetter wrote: On Tue, Feb 09, 2016 at 02:08:23PM +0200, Martin Peres wrote: On 26/01/16 19:00, Daniel Vetter wrote: On Tue, Jan 26, 2016 at 07:45:42AM -0800, Jesse Barnes wrote: On 01/22/2016 09:00 AM, Daniel Vetter wrote: On Wed, Jan 20, 2016 at 06:26:02PM -0800, tom.orou...@intel.com wrote: From: Tom O'Rourke I'd say we need to keep the boost-deboost stuff alive, e.g. by manually telling guc that the we want different limits, then resetting those limits again after the boost is done. Same for fast idling - kernel simply has a better idea if anyone is about to submit more work (we have execbuf hints for specific workloads like libva). Since there is soon to be a GPU scheduler, the GuC could get this information already, right? Unless you are talking about having mesa signal when it starts creating a new batchbuffer and you would like the GPU to prepare to ramp-up. We don't tell the guc when we're stalling for a batch, so no it doesn't know. The entire desing seems to center around the idea of just aiming for some average fps, which is silly for spikey workloads. I assuming that without some other magic we'll still need explicit boosting and deboosting. Right, the needs for a desktop environment are not taken into account here. I guess this is really because of Android which is likely using planes for compositing so the only problem the GuC developers are trying to solve is to guarantee 60 FPS while playing games while saving as much power as possible. Also, SKIA (GPU accel for Chrome) uses the GPU very little so I guess it is not really helping the browser case in the mind of the GuC developers. While the SLPC is IMO the right approach for fast reclocking and tying power gating, scheduling and power management together, it needs to allow the kernel to give hints and it should listen to them! Battery life should not be optimised at the ms level, but more at the second level. This means that spiky loads should be able to use the boost frequencies (if allowed to by the kernel) but the GPU should ramp down more or less quickly as the task drags on in order to meet the average power consumption target. May I also repeat that all this really have to be bypassable for benchmarking, no boost, fixed frequencies as requested by the kernel and a counter to report the number of throttling events at the GPU level. Without this, the performance team just cannot do its work properly. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev2)
== Summary == Series 1609v2 drm/i915/skl: SKL CDCLK change on modeset tracking VCO http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/2/mbox/ Test core_prop_blob: Subgroup basic: skip -> PASS (bdw-nuci7) Test drv_getparams_basic: Subgroup basic-subslice-total: skip -> PASS (bdw-nuci7) Test drv_hangman: Subgroup error-state-basic: skip -> PASS (bdw-nuci7) Test gem_basic: Subgroup create-close: skip -> PASS (bdw-nuci7) Subgroup create-fd-close: skip -> PASS (bdw-nuci7) Test gem_ctx_basic: skip -> PASS (bdw-nuci7) Test gem_ctx_create: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_ctx_exec: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_ctx_param_basic: Subgroup basic-default: skip -> PASS (bdw-nuci7) Subgroup invalid-ctx-get: skip -> PASS (bdw-nuci7) Subgroup invalid-param-get: skip -> PASS (bdw-nuci7) Subgroup invalid-size-get: skip -> PASS (bdw-nuci7) Subgroup invalid-size-set: skip -> PASS (bdw-nuci7) Subgroup non-root-set-no-zeromap: skip -> PASS (bdw-nuci7) Subgroup root-set-no-zeromap-disabled: skip -> PASS (bdw-nuci7) Test gem_exec_basic: Subgroup basic-bsd1: skip -> PASS (bdw-nuci7) Subgroup basic-bsd2: skip -> PASS (bdw-nuci7) Subgroup basic-default: skip -> PASS (bdw-nuci7) Subgroup basic-render: skip -> PASS (bdw-nuci7) Test gem_flink_basic: Subgroup bad-flink: skip -> PASS (bdw-nuci7) Subgroup bad-open: skip -> PASS (bdw-nuci7) Subgroup basic: skip -> PASS (bdw-nuci7) Subgroup double-flink: skip -> PASS (bdw-nuci7) Test gem_linear_blits: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_mmap: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_mmap_gtt: Subgroup basic: skip -> PASS (bdw-nuci7) Subgroup basic-copy: skip -> PASS (bdw-nuci7) Subgroup basic-read: skip -> PASS (bdw-nuci7) Subgroup basic-read-no-prefault: skip -> PASS (bdw-nuci7) Subgroup basic-read-write: skip -> PASS (bdw-nuci7) Subgroup basic-read-write-distinct: skip -> PASS (bdw-nuci7) Subgroup basic-short: skip -> PASS (bdw-nuci7) Subgroup basic-small-bo-tiledx: skip -> PASS (bdw-nuci7) Subgroup basic-small-bo-tiledy: skip -> PASS (bdw-nuci7) Subgroup basic-small-copy: skip -> PASS (bdw-nuci7) Subgroup basic-write: skip -> PASS (bdw-nuci7) Subgroup basic-write-cpu-read-gtt: skip -> PASS (bdw-nuci7) Subgroup basic-write-gtt: skip -> PASS (bdw-nuci7) Subgroup basic-write-gtt-no-prefault: skip -> PASS (bdw-nuci7) Subgroup basic-write-no-prefault: skip -> PASS (bdw-nuci7) Subgroup basic-write-read: skip -> PASS (bdw-nuci7) Subgroup basic-write-read-distinct: pass -> SKIP (bdw-nuci7) Test gem_pread: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_pwrite: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_render_linear_blits: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_render_tiled_blits: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_ringfill: Subgroup basic-default: skip -> PASS (bdw-nuci7) Subgroup basic-default-bomb: skip -> PASS (bdw-nuci7) Subgroup basic-default-hang: skip -> PASS (bdw-nuci7) Subgroup basic-default-interruptible: skip -> PASS (bdw-nuci7) Test gem_storedw_loop: Subgroup basic-blt: skip -> PASS (bdw-nuci7) Subgroup basic-bsd: skip -> PASS (bdw-nuci7) S
[Intel-gfx] [PATCH 1/5] drm/i915: Splitting intel_dp_detect
intel_dp_detect() is called for not just detection but
during modes enumeration as well. Repeating the whole
sequence during each of these calls is wasteful and
time consuming.
This patch moves probing for panel, DPCD read etc done in
intel_dp_detect() to a new function intel_dp_long_pulse().
Note that the behavior of intel_dp_detect() is changed to
report connected or disconnected depending on whether the
EDID is available or not.
This change will be required by further patches in the series
to avoid performing duplicated DPCD operations on hotplug.
v2: Moved a hunk to next patch of the series.
Moved intel_dp_unset_edid to out. (Ander)
v3: Rephrased commit message and intel_dp_unset_dp() is called
within intel_dp_set_dp() to free the previous EDID. (Ander)
v4: Added overriding of status to disconnected for MST. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 63 -
1 file changed, 43 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..042283a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,6 +129,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp,
bool sync);
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
+static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
@@ -4584,6 +4585,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct edid *edid;
+ intel_dp_unset_edid(intel_dp);
edid = intel_dp_get_edid(intel_dp);
intel_connector->detect_edid = edid;
@@ -4604,9 +4606,10 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_audio = false;
}
-static enum drm_connector_status
-intel_dp_detect(struct drm_connector *connector, bool force)
+static void
+intel_dp_long_pulse(struct intel_connector *intel_connector)
{
+ struct drm_connector *connector = &intel_connector->base;
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *intel_encoder = &intel_dig_port->base;
@@ -4616,17 +4619,6 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
bool ret;
u8 sink_irq_vector;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
- intel_dp_unset_edid(intel_dp);
-
- if (intel_dp->is_mst) {
- /* MST devices are disconnected from a monitor POV */
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
- return connector_status_disconnected;
- }
-
power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(to_i915(dev), power_domain);
@@ -4647,14 +4639,18 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
goto out;
}
+ if (intel_encoder->type != INTEL_OUTPUT_EDP)
+ intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+
intel_dp_probe_oui(intel_dp);
ret = intel_dp_probe_mst(intel_dp);
if (ret) {
- /* if we are in MST mode then this connector
- won't appear connected or have anything with EDID on it */
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+ /*
+* If we are in MST mode then this connector
+* won't appear connected or have anything
+* with EDID on it
+*/
status = connector_status_disconnected;
goto out;
}
@@ -4669,8 +4665,6 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
intel_dp_set_edid(intel_dp);
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
status = connector_status_connected;
/* Try to read the source of the interrupt */
@@ -4688,8 +4682,37 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
}
out:
+ if (status != connector_status_connected)
+ intel_dp_unset_edid(intel_dp);
intel_display_power_put(to_i915(dev), power_domain);
- return status;
+ return;
+}
+
+static enum drm_connector_status
+intel_dp_detect(struct drm_connector *connector, bool force)
+{
+ struct intel_dp *intel_dp = inte
[Intel-gfx] [PATCH 5/5] drm/i915: force full detect on sink count change
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change.
This will allow both detection of hotplug and unplug of panels
through dongles that give only short pulse for such events.
v2: changed variable type from u8 to bool (Jani)
return immediately if perform_full_detect is set(Siva)
v3: changed method of determining full detection from using
pointer to return code (Siva)
v4: changed comments to indicate meaning of return value of
intel_dp_short_pulse and explain the use of return value
from intel_dp_get_dpcd in intel_dp_short_pulse (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a834c5f..f29f8b6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4344,12 +4344,19 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
* 2. Configure link according to Receiver Capabilities
* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
* 4. Check link status on receipt of hot-plug interrupt
+ *
+ * intel_dp_short_pulse - handles short pulse interrupts
+ * when full detection is not required.
+ * Returns %true if short pulse is handled and full detection
+ * is NOT required and %false otherwise.
*/
-static void
+static bool
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
u8 sink_irq_vector;
+ u8 old_sink_count = intel_dp->sink_count;
+ bool ret;
/*
* Clearing compliance test variables to allow capturing
@@ -4359,9 +4366,17 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
intel_dp->compliance_test_type = 0;
intel_dp->compliance_test_data = 0;
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
- return;
+ /*
+* Now read the DPCD to see if it's actually running
+* If the current value of sink count doesn't match with
+* the value that was stored earlier or dpcd read failed
+* we need to do full detection
+*/
+ ret = intel_dp_get_dpcd(intel_dp);
+
+ if ((old_sink_count != intel_dp->sink_count) || !ret) {
+ /* No need to proceed if we are going to do full detect */
+ return false;
}
/* Try to read the source of the interrupt */
@@ -4381,6 +4396,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
intel_dp_check_link_status(intel_dp);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ return true;
}
/* XXX this is probably wrong for multiple downstream ports */
@@ -5115,8 +5132,12 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
}
}
- if (!intel_dp->is_mst)
- intel_dp_short_pulse(intel_dp);
+ if (!intel_dp->is_mst) {
+ if (!intel_dp_short_pulse(intel_dp)) {
+
intel_dp_long_pulse(intel_dp->attached_connector);
+ goto put_power;
+ }
+ }
}
ret = IRQ_HANDLED;
--
2.6.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: Save sink_count for tracking changes to it and read sink_count dpcd always
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd.
SINK_COUNT dpcd is not dependent on DOWNSTREAM_PORT_PRESENT dpcd.
SINK_COUNT denotes if a display is attached, while
DOWNSTREAM_PORT_PRESET indicates how many ports are available
in the dongle where display can be attached. so it is possible
for sink count to change irrespective of value in downstream
port dpcd.
Here is a table of possible values and scenarios
sink_count downstream_port
present
0 0 no display is attached
0 1 dongle is connected without display
1 0 display connected directly
1 1 display connected through dongle
v2: Storing value of intel_dp->sink_count that is ready
for consumption. (Ander)
Squashing two commits into one. (Ander)
v3: Added comment to explain the need of early return when
sink count is 0. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 30 +++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9fe78e1..a834c5f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3862,6 +3862,27 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
return false; /* DPCD not present */
+ if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
+ &intel_dp->sink_count, 1) < 0)
+ return false;
+
+ /*
+* Sink count can change between short pulse hpd hence
+* a member variable in intel_dp will track any changes
+* between short pulse interrupts.
+*/
+ intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
+
+ /*
+* SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
+* a dongle is present but no display. Unless we require to know
+* if a dongle is present or not, we don't need to update
+* downstream port information. So, an early return here saves
+* time from performing other operations which are not required.
+*/
+ if (!intel_dp->sink_count)
+ return false;
+
/* Check if the panel supports PSR */
memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
if (is_edp(intel_dp)) {
@@ -4379,14 +4400,9 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
/* If we're HPD-aware, SINK_COUNT changes dynamically */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
- uint8_t reg;
-
- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
- ®, 1) < 0)
- return connector_status_unknown;
- return DP_GET_SINK_COUNT(reg) ? connector_status_connected
- : connector_status_disconnected;
+ return intel_dp->sink_count ?
+ connector_status_connected : connector_status_disconnected;
}
/* If no HPD, poke DDC gently */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3d003d6..c04db07 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -752,6 +752,7 @@ struct intel_dp {
uint32_t DP;
int link_rate;
uint8_t lane_count;
+ uint8_t sink_count;
bool has_audio;
bool detect_done;
enum hdmi_force_audio force_audio;
--
2.6.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Reorganizing intel_dp_check_link_status
When created originally intel_dp_check_link_status()
was supposed to handle only link training for short
pulse but has grown into handler for short pulse itself.
This patch cleans up this function by splitting it into
two halves. First intel_dp_short_pulse() is called,
which will be entry point and handle all logic for
short pulse handling while intel_dp_check_link_status()
will retain its original purpose of only doing link
status related work.
intel_dp_short_pulse: All existing code other than
link status read and link training upon error status.
intel_dp_check_link_status:
The link status should be read on short pulse
irrespective of panel being enabled or not so
intel_dp_get_link_status() performs dpcd read first
then based on crtc active / enabled it will
perform the link training.
This is because short pulse is a generic interrupt
which should always be handled, because it may mean:
1. Hotplug/unplug of MST panel
2. Hotplug/unplug of dongle
3. Link status change for other DP panels
v2: Added WARN_ON to intel_dp_check_link_status()
Removed a call to intel_dp_get_link_status() (Ander)
v3: Changed commit message to explain need of link status
being read before performing encoder checks (Daniel)
v4: Changed commit message to explain need of reading
link status on short pulse (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 65 +++--
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ad5ec3b..9fe78e1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4286,6 +4286,36 @@ go_again:
return -EINVAL;
}
+static void
+intel_dp_check_link_status(struct intel_dp *intel_dp)
+{
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ DRM_ERROR("Failed to get link status\n");
+ return;
+ }
+
+ if (!intel_encoder->base.crtc)
+ return;
+
+ if (!to_intel_crtc(intel_encoder->base.crtc)->active)
+ return;
+
+ /* if link training is requested we should perform it always */
+ if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
+ (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
+ DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
+ intel_encoder->base.name);
+ intel_dp_start_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp);
+ }
+}
+
/*
* According to DP spec
* 5.1.2:
@@ -4295,14 +4325,10 @@ go_again:
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
u8 sink_irq_vector;
- u8 link_status[DP_LINK_STATUS_SIZE];
-
- WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
/*
* Clearing compliance test variables to allow capturing
@@ -4312,17 +4338,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
intel_dp->compliance_test_type = 0;
intel_dp->compliance_test_data = 0;
- if (!intel_encoder->base.crtc)
- return;
-
- if (!to_intel_crtc(intel_encoder->base.crtc)->active)
- return;
-
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
- return;
- }
-
/* Now read the DPCD to see if it's actually running */
if (!intel_dp_get_dpcd(intel_dp)) {
return;
@@ -4342,14 +4357,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
- /* if link training is requested we should perform it always */
- if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
- (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
- DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
- intel_encoder->base.name);
- intel_dp_start_link_train(intel_dp);
- intel_dp_stop_link_train(intel_dp);
- }
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+ intel_dp_check_link_status(intel_dp);
+
[Intel-gfx] [PATCH 2/5] drm/i915: Cleaning up intel_dp_hpd_pulse
Current DP detection has DPCD operations split across
intel_dp_hpd_pulse and intel_dp_detect which contains
duplicates as well. Also intel_dp_detect is called
during modes enumeration as well which will result
in multiple dpcd operations. So this patch tries
to solve both these by bringing all DPCD operations
in one single function and make intel_dp_detect
use existing values instead of repeating same steps.
v2: Pulled in a hunk from last patch of the series to
this patch. (Ander)
v3: Added MST hotplug handling. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
---
drivers/gpu/drm/i915/intel_dp.c | 72 +---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 47 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 042283a..ad5ec3b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4653,6 +4653,16 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
*/
status = connector_status_disconnected;
goto out;
+ } else if (connector->status == connector_status_connected) {
+ /*
+* If display was connected already and is still connected
+* check links status, there has been known issues of
+* link loss triggerring long pulse
+*/
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+ intel_dp_check_link_status(intel_dp);
+ drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ goto out;
}
/*
@@ -4666,6 +4676,7 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
intel_dp_set_edid(intel_dp);
status = connector_status_connected;
+ intel_dp->detect_done = true;
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
@@ -4682,8 +4693,21 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
}
out:
- if (status != connector_status_connected)
+ if (status != connector_status_connected) {
intel_dp_unset_edid(intel_dp);
+ /*
+* If we were in MST mode, and device is not there,
+* get out of MST mode
+*/
+ if (intel_dp->is_mst) {
+ DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
+ intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
+ intel_dp->is_mst = false;
+ drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
+ intel_dp->is_mst);
+ }
+ }
+
intel_display_power_put(to_i915(dev), power_domain);
return;
}
@@ -4707,7 +4731,11 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
return connector_status_disconnected;
}
- intel_dp_long_pulse(intel_dp->attached_connector);
+ /* If full detect is not performed yet, do a full detect */
+ if (!intel_dp->detect_done)
+ intel_dp_long_pulse(intel_dp->attached_connector);
+
+ intel_dp->detect_done = false;
if (intel_connector->detect_edid)
return connector_status_connected;
@@ -5040,25 +5068,25 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
/* indicate that we need to restart link training */
intel_dp->train_set_valid = false;
- if (!intel_digital_port_connected(dev_priv, intel_dig_port))
- goto mst_fail;
-
- if (!intel_dp_get_dpcd(intel_dp)) {
- goto mst_fail;
- }
-
- intel_dp_probe_oui(intel_dp);
+ intel_dp_long_pulse(intel_dp->attached_connector);
+ if (intel_dp->is_mst)
+ ret = IRQ_HANDLED;
+ goto put_power;
- if (!intel_dp_probe_mst(intel_dp)) {
- drm_modeset_lock(&dev->mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
- drm_modeset_unlock(&dev->mode_config.connection_mutex);
- goto mst_fail;
- }
} else {
if (intel_dp->is_mst) {
- if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
- goto mst_fail;
+ if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
+ /*
+* If we were in MST mode, and device is not
+* there, get out of MST mode
+*/
+
Re: [Intel-gfx] [PATCH 2/5] drm/i915: fix error path in intel_setup_gmbus()
On Tue, 09 Feb 2016, Jani Nikula wrote:
> On Tue, 09 Feb 2016, Rasmus Villemoes wrote:
>> This fails to undo the setup for pin==0; moreover, something
>> interesting happens if the setup failed already at pin==0.
>>
>> Signed-off-by: Rasmus Villemoes
>> ---
>> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
>> b/drivers/gpu/drm/i915/intel_i2c.c
>> index 25254b5c1ac5..deb8282c26d8 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -683,7 +683,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>> return 0;
>>
>> err:
>> -while (--pin) {
>> +while (pin--) {
>> if (!intel_gmbus_is_valid_pin(dev_priv, pin))
>> continue;
>
> Reviewed-by: Jani Nikula
> Fixes: f899fc64cda8 ("drm/i915: use GMBUS to manage i2c links")
> Cc: sta...@vger.kernel.org
And picked up to drm-intel-next-queued, thanks for the patch.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/guc: Set init value for cached work queue head
== Summary == Series 3212v1 drm/i915/guc: Set init value for cached work queue head http://patchwork.freedesktop.org/api/1.0/series/3212/revisions/1/mbox/ Test core_auth: Subgroup basic-auth: pass -> SKIP (bdw-nuci7) Test drv_hangman: Subgroup error-state-basic: skip -> PASS (bdw-nuci7) Test drv_module_reload_basic: pass -> DMESG-WARN (ilk-hp8440p) Test gem_basic: Subgroup create-close: skip -> PASS (bdw-nuci7) Subgroup create-fd-close: pass -> SKIP (bdw-nuci7) Test gem_cpu_reloc: Subgroup basic: pass -> SKIP (bdw-nuci7) Test gem_ctx_basic: pass -> SKIP (bdw-nuci7) Test gem_ctx_exec: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_ctx_param_basic: Subgroup invalid-param-set: skip -> PASS (bdw-nuci7) Subgroup non-root-set-no-zeromap: pass -> SKIP (bdw-nuci7) Test gem_exec_basic: Subgroup basic-blt: pass -> SKIP (bdw-nuci7) Subgroup basic-bsd1: skip -> PASS (bdw-nuci7) Test gem_flink_basic: Subgroup flink-lifetime: pass -> SKIP (bdw-nuci7) Test gem_mmap_gtt: Subgroup basic-read: pass -> SKIP (bdw-nuci7) Subgroup basic-read-write-distinct: pass -> SKIP (bdw-nuci7) Subgroup basic-short: skip -> PASS (bdw-nuci7) Subgroup basic-small-bo: skip -> PASS (bdw-nuci7) Subgroup basic-small-bo-tiledx: skip -> PASS (bdw-nuci7) Subgroup basic-small-bo-tiledy: pass -> DMESG-WARN (ilk-hp8440p) Subgroup basic-small-copy: pass -> SKIP (bdw-nuci7) Subgroup basic-small-copy-xy: skip -> PASS (bdw-nuci7) Subgroup basic-write-cpu-read-gtt: skip -> PASS (bdw-nuci7) Subgroup basic-write-no-prefault: pass -> SKIP (bdw-nuci7) Subgroup basic-write-read: pass -> SKIP (bdw-nuci7) Test gem_pwrite: Subgroup basic: skip -> PASS (bdw-nuci7) Test gem_ringfill: Subgroup basic-default: pass -> SKIP (bdw-nuci7) Subgroup basic-default-bomb: pass -> SKIP (bdw-nuci7) Test gem_storedw_loop: Subgroup basic-blt: pass -> SKIP (bdw-nuci7) Subgroup basic-bsd1: pass -> SKIP (bdw-nuci7) Subgroup basic-bsd2: pass -> SKIP (bdw-nuci7) Test gem_sync: Subgroup basic-blt: pass -> SKIP (bdw-nuci7) Subgroup basic-bsd: skip -> PASS (bdw-nuci7) Test gem_tiled_blits: Subgroup basic: pass -> SKIP (bdw-nuci7) Test gem_tiled_fence_blits: Subgroup basic: pass -> SKIP (bdw-nuci7) Test gem_tiled_pread_basic: skip -> PASS (bdw-nuci7) Test kms_addfb_basic: Subgroup addfb25-framebuffer-vs-set-tiling: skip -> PASS (bdw-nuci7) Subgroup addfb25-modifier-no-flag: skip -> PASS (bdw-nuci7) Subgroup addfb25-y-tiled: pass -> SKIP (bdw-nuci7) Subgroup bad-pitch-1024: pass -> SKIP (bdw-nuci7) Subgroup bad-pitch-128: pass -> SKIP (bdw-nuci7) Subgroup bad-pitch-63: pass -> SKIP (bdw-nuci7) Subgroup bad-pitch-65536: pass -> SKIP (bdw-nuci7) Subgroup basic: skip -> PASS (bdw-nuci7) Subgroup basic-x-tiled: skip -> PASS (bdw-nuci7) Subgroup bo-too-small-due-to-tiling: skip -> PASS (bdw-nuci7) Subgroup no-handle: pass -> SKIP (bdw-nuci7) Subgroup size-max: skip -> PASS (bdw-nuci7) Subgroup small-bo: pass -> SKIP (bdw-nuci7) Subgroup unused-modifier: pass -> SKIP (bdw-nuci7) Subgroup unused-pitches: pass -> SKIP (bdw-nuci7) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: skip -> PASS (bdw-nuci7) pass -> INCOMPLETE (ilk-hp8440p) UNSTABLE Test kms_pipe_crc_basic: Subgroup bad-nb-words-1:
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
[cc += Rafael J. Wysocki, linux-acpi]
Hi Stephen,
On Wed, Feb 10, 2016 at 12:24:51PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> In file included from drivers/gpu/drm/nouveau/nouveau_drm.c:25:0:
> include/linux/apple-gmux.h: In function 'apple_gmux_present':
> include/linux/apple-gmux.h:36:42: error: implicit declaration of function
> 'acpi_dev_present' [-Werror=implicit-function-declaration]
> return IS_ENABLED(CONFIG_APPLE_GMUX) && acpi_dev_present(GMUX_ACPI_HID);
> ^
>
> Caused by commit
>
> 2413306c2566 ("apple-gmux: Add helper for presence detect")
>
> I have used the drm-misc tree from next-20160209 for today.
Ugh, apologies, I didn't have a non-ACPI platform available to test
this on.
Solution is to either add to include/linux/acpi.h
static inline bool acpi_dev_present(const char *hid)
{
return false;
}
somewhere below
#else /* !CONFIG_ACPI */
or alternatively to add to include/linux/apple-gmux.h
IS_ENABLED(CONFIG_ACPI)
in apple_gmux_present().
I'll check the other users of acpi_dev_present() to see which of
these two solutions is more appropriate and will post a fix shortly.
Thanks a lot for reporting this.
Lukas
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] setting primary in multihead xorg.conf causes disregard of DisplaySize
Possibly some fault overlap with https://bugs.freedesktop.org/show_bug.cgi?id=90842 but this is not the same. I found no other filed bugs similar. Both DisplaySize and primary display assigned as I wish with radeon. Both DisplaySize and primary display assigned as I wish with nouveau. With Intel I must choose between having the DPI I want, or having the primary display assigned as I wish. Unlike nouveau and radeon, intel won't let me have both, at least, not using a comparable xorg.conf. I tried on two different Intel gfx machines (both 4 series, one with pair of 1920x1080, other with 1680x1050 and 1920x1080), with same failing result. I ask here before filing a bug to see it there is a workaround or some specific setup requirement that intel requires and neither radeon nor nouveau do. Xorg.0.log with DisplaySize disobeyed: http://fm.no-ip.com/Tmp/Linux/Xorg/xorg.0.log-gx760-dualIntel-goodPrimary-badDPI Xorg.0.log with Primary disobeyed: http://fm.no-ip.com/Tmp/Linux/Xorg/xorg.0.log-gx760-dualIntel-badPrimary-goodDPI config file as last used: http://fm.no-ip.com/Tmp/Linux/Xorg/xorg.conf-intel-1920x1080overunder-120 configs as work with nouveau and radeon: http://fm.no-ip.com/Share/Linux/xorg.conf-radeon-vga1680x1050below-dvi1920x1080above-120 http://fm.no-ip.com/Share/Linux/xorg.conf-nouveauDualDVI-1680x1050under-1920x1080over-120 -- "The wise are known for their understanding, and pleasant words are persuasive." Proverbs 16:21 (New Living Translation) Team OS/2 ** Reg. Linux User #211409 ** a11y rocks! Felix Miata *** http://fm.no-ip.com/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [REGRESSION] i915: No HDMI output with 4.4
Hi. With Linux 4.4 external HDMI-attached monitor in not discovered by i915 driver. Here is boot log related to drm and i915 for Linux 4.4/4.4.1 kernel: === kernel: [drm] Initialized drm 1.1.0 20060810 kernel: [drm] Memory usable by graphics device = 2048M kernel: [drm] Replacing VGA console driver kernel: [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). kernel: [drm] Driver supports precise vblank timestamp query. kernel: [drm] Initialized i915 1.6.0 20151010 for :00:02.0 on minor 0 kernel: i915 :00:02.0: No connectors reported connected with modes kernel: [drm] Cannot find any crtc or sizes - going 1024x768 kernel: i915 :00:02.0: fb0: inteldrmfb frame buffer device === i915 is unable to find any connectors. Reattaching HDMI cable does not help. Note, we are talking about in-kernel i915 drm with no X involved (launching X does not change anything, though). Linux 4.3 worked OK. Here is boot log for 4.3 kernel: === kernel: [drm] Initialized drm 1.1.0 20060810 kernel: [drm] Memory usable by graphics device = 2048M kernel: [drm] Replacing VGA console driver kernel: [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). kernel: [drm] Driver supports precise vblank timestamp query. kernel: [drm] Initialized i915 1.6.0 20150731 for :00:02.0 on minor 0 kernel: [drm:intel_set_pch_fifo_underrun_reporting [i915]] *ERROR* uncleared pch fifo underrun on pch transcoder A kernel: [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder A FIFO underrun kernel: i915 :00:02.0: fb0: inteldrmfb frame buffer device === Hardware: === [~]$ lscpu | grep "Model name" Model name:Intel(R) Pentium(R) CPU G2020 @ 2.90GHz [~]$ lspci | grep VGA 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) === and xrandr output (with 4.3 kernel): === [~]$ xrandr --listproviders Providers: number : 1 Provider 0: id: 0x47 cap: 0xb, Source Output, Sink Output, Sink Offload crtcs: 4 outputs: 4 associated providers: 0 name:Intel [~]$ xrandr Screen 0: minimum 8 x 8, current 1920 x 1080, maximum 32767 x 32767 DP1 disconnected (normal left inverted right x axis y axis) HDMI1 connected primary 1920x1080+0+0 (normal left inverted right x axis y axis) 510mm x 290mm 1920x1080 60.00*+ 50.0059.94 1920x1080i60.0050.0059.94 1680x1050 59.88 1400x1050 59.95 1600x900 60.00 1280x1024 60.02 1440x900 59.90 1280x800 59.91 1152x864 59.97 1280x720 60.0050.0059.94 1024x768 60.00 800x600 60.32 720x576 50.00 720x480 60.0059.94 640x480 60.0059.94 VGA1 disconnected (normal left inverted right x axis y axis) VIRTUAL1 disconnected (normal left inverted right x axis y axis) === Ideas? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Mesa-dev] [PATCH v2 i-g-t] igt/list-workarounds: Extend the script to Mesa
Quoting Damien Lespiau (2016-02-05 15:46:51)
> On Fri, Feb 05, 2016 at 01:55:19PM -0800, Sameer Kibey wrote:
> > Updated the list-workarounds script so that it
> > can parse Mesa directory if provided. Moved the
> > common code to a separate function to allow
> > reuse for both kernel and mesa.
> >
> > The new command line is:
> > Usage: list-workarounds [options] path-to-kernel
> >-k path-to-kernel -m path-to-mesa
> >
> > The legacy usage is retained to avoid breaking
> > backwards compatibility. New parameters -k and
> > -m are added for the new behavior.
> >
> > Either kernel or mesa or both paths can be specified.
> > If path-to-mesa is invalid, error is reported.
> >
> > Signed-off-by: Sameer Kibey
>
> Pushed thanks for the patch.
>
> --
> Damien
>
> > ---
> > scripts/list-workarounds | 74
> > ++--
> > 1 file changed, 53 insertions(+), 21 deletions(-)
> >
> > diff --git a/scripts/list-workarounds b/scripts/list-workarounds
> > index d11b6a9..8b41ae5 100755
> > --- a/scripts/list-workarounds
> > +++ b/scripts/list-workarounds
> > @@ -18,7 +18,7 @@ def find_nth(haystack, needle, n):
> > return start
> >
> > valid_platforms = ('ctg', 'elk', 'ilk', 'snb', 'ivb', 'vlv', 'hsw', 'bdw',
> > -'chv', 'skl', 'bxt')
> > +'chv', 'skl', 'bxt', 'kbl')
> > def parse_platforms(line, p):
> > l = p.split(',')
> > for p in l:
> > @@ -65,9 +65,15 @@ def execute(cmd):
> > return out, err
> >
> > def parse_options(args):
> > - usage = "Usage: list-workarounds [options] path-to-kernel"
> > + usage = "Usage: list-workarounds [options] path-to-kernel -k
> > path-to-kernel -m path-to-mesa"
> > parser = optparse.OptionParser(usage, version=1.0)
> >
> > + parser.add_option("-k", "--kernel-path", dest="kernel_path",
> > default=None,
> > + help="path to kernel")
> > +
> > + parser.add_option("-m", "--mesa-path", dest="mesa_path", default=None,
> > + help="path to mesa")
> > +
> > parser.add_option("-v", "--verbose", action="store_true",
> > dest="verbose", default=False,
> > help="be more verbose")
> > @@ -76,38 +82,64 @@ def parse_options(args):
> > help="List workarounds for the specified platform")
> >
> > (options, args) = parser.parse_args()
> > -
> > return (options, args)
> >
> > -if __name__ == '__main__':
> > - (options, args) = parse_options(sys.argv[1:])
> > - verbose = options.verbose
> > -
> > - if not len(args):
> > - sys.stderr.write("error: A path to a kernel tree is
> > required\n")
> > - sys.exit(1)
> > -
> > - kernel_path = args[0]
> > - kconfig = os.path.join(kernel_path, 'Kconfig')
> > - if not os.path.isfile(kconfig):
> > - sys.stderr.write("error: %s does not point to a kernel tree
> > \n"
> > - % kernel_path)
> > - sys.exit(1)
> > -
> > - i915_dir = os.path.join('drivers', 'gpu', 'drm', 'i915')
> > +def print_workarounds(project_root, driver_dir, project):
> > olddir = os.getcwd()
> > - os.chdir(kernel_path)
> > + os.chdir(project_root)
> > work_arounds, err = execute(['git', 'grep', '-n',
> >'-e', 'W[aA][A-Z0-9][a-zA-Z0-9_]\+',
> > - i915_dir])
> > + driver_dir])
> > os.chdir(olddir)
> > if err:
> > print(err)
> > sys.exit(1)
> >
> > parse(work_arounds)
> > + print "\nList of workarounds found in %s:" % project
Hey Damien, the script says it's python 3, and this ^^^ is broken syntax
in python 3 (but not in 2).
> > for wa in sorted(workarounds.keys()):
> > if not options.platform:
> > print("%s: %s" % (wa, ', '.join(workarounds[wa])))
> > elif options.platform in workarounds[wa]:
> > print(wa)
> > +
> > +
> > +if __name__ == '__main__':
> > + (options, args) = parse_options(sys.argv)
> > + verbose = options.verbose
> > + kernel_path = None
> > +
> > + if not len(args) and options.kernel_path == None and
> > options.mesa_path == None:
> > + sys.stderr.write("error: A path to either a kernel tree or
> > Mesa is required\n")
> > + sys.exit(1)
> > +
> > + if len(args):
> > + kernel_path = args[0]
> > + elif options.kernel_path != None:
> > + kernel_path = options.kernel_path
> > +
> > + if kernel_path != None:
> > + # --- list Kernel workarounds if path is provided ---
> > + kconfig = os.path.join(kernel_path, 'Kconfig')
> > + if not os.path.isfile(kconfig):
> > + sys.stderr.write("error: %s does not point to a
> > kernel tree \n"
> > +
Re: [Intel-gfx] [PATCH i-g-t] list-workarounds: Fix python 2 print statement
Looks good to me.
Reviewed-by: Dylan Baker
Quoting Damien Lespiau (2016-02-08 04:08:29)
> That script is a python 3 script, so we can't use the python 2 print
> statement, it's a function now.
>
> I missed it in the review because reviewing a diff without additional
> context gives you a partial story.
>
> Cc: Sameer Kibey
> Cc: Dylan Baker
> Signed-off-by: Damien Lespiau
> ---
> scripts/list-workarounds | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/list-workarounds b/scripts/list-workarounds
> index 8b41ae5..70c026d 100755
> --- a/scripts/list-workarounds
> +++ b/scripts/list-workarounds
> @@ -96,7 +96,7 @@ def print_workarounds(project_root, driver_dir, project):
> sys.exit(1)
>
> parse(work_arounds)
> - print "\nList of workarounds found in %s:" % project
> + print("\nList of workarounds found in %s:" % project)
> for wa in sorted(workarounds.keys()):
> if not options.platform:
> print("%s: %s" % (wa, ', '.join(workarounds[wa])))
> --
> 2.4.3
>
signature.asc
Description: signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [REGRESSION] i915: No HDMI output with 4.4
4.5-rc3 is affected as well: === kernel: [drm] Initialized drm 1.1.0 20060810 kernel: [drm] Memory usable by graphics device = 2048M kernel: [drm] Replacing VGA console driver kernel: [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). kernel: [drm] Driver supports precise vblank timestamp query. kernel: [drm] Initialized i915 1.6.0 20151218 for :00:02.0 on minor 0 kernel: i915 :00:02.0: No connectors reported connected with modes kernel: [drm] Cannot find any crtc or sizes - going 1024x768 kernel: i915 :00:02.0: fb0: inteldrmfb frame buffer device === Will try to apply the following dirty workaround: https://lkml.org/lkml/2016/1/19/637 I guess the problem described via the link above is not fixed yet: This issue is still present in 4.5-rc1. Stay tuned. 09.02.2016 12:11, Daniel Vetter написав: Can you please retest with latest -rc? There's been some bugs in the HDMI detection changes, which should be fixed now. If that doesn't help please try to bisect which exact change caused the regression. Thanks, Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt 2/3] lib/igt_draw: add support for Y tiling
On Fri, Jan 29, 2016 at 04:46:31PM -0200, Paulo Zanoni wrote:
> Most of the patch is to change the tile/untile functions so they can
> work with Y-major tiling.
>
> We're also skipping on BLT for Y-tiling. Some parts of the spec
> suggest this doesn't work and some parts of the spec suggest it will
> work. Since I couldn't make it work, SKIP for now.
>
> Signed-off-by: Paulo Zanoni
So if we go with not setting tiling by default for Y-tiled then we'd need
a call to get_tiling for the blt functions in igt_draw and an igt_assert
that it matches. Then callers know when exactly they need to set up tiling
themselves.
Of course we also need to document this in the gtkdoc.
Sounds reasonable as an overall plan, or totally nonsense?
-Daniel
> ---
> lib/igt_draw.c | 173
> -
> 1 file changed, 123 insertions(+), 50 deletions(-)
>
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 45fa10f..468a1eb 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -134,71 +134,118 @@ static int swizzle_addr(int addr, int swizzle)
> return addr;
> }
>
> -/* It's all in "pixel coordinates", so make sure you multiply/divide by the
> bpp
> - * if you need to. */
> -static int linear_x_y_to_tiled_pos(int x, int y, uint32_t stride, int
> swizzle,
> -int bpp)
> +static int tile(int x, int y, uint32_t x_tile_size, uint32_t y_tile_size,
> + uint32_t line_size, bool xmajor)
> {
> - int x_tile_size, y_tile_size;
> - int x_tile_n, y_tile_n, x_tile_off, y_tile_off;
> - int line_size, tile_size;
> - int tile_n, tile_off;
> - int tiled_pos, tiles_per_line;
> - int pixel_size = bpp / 8;
> + int tile_size, tiles_per_line, x_tile_n, y_tile_n, tile_off, pos;
> + int tile_n, x_tile_off, y_tile_off;
>
> - line_size = stride;
> - x_tile_size = 512;
> - y_tile_size = 8;
> - tile_size = x_tile_size * y_tile_size;
> tiles_per_line = line_size / x_tile_size;
> + tile_size = x_tile_size * y_tile_size;
>
> + x_tile_n = x / x_tile_size;
> y_tile_n = y / y_tile_size;
> + tile_n = y_tile_n * tiles_per_line + x_tile_n;
> +
> + x_tile_off = x % x_tile_size;
> y_tile_off = y % y_tile_size;
>
> - x_tile_n = (x * pixel_size) / x_tile_size;
> - x_tile_off = (x * pixel_size) % x_tile_size;
> + if (xmajor)
> + tile_off = y_tile_off * x_tile_size + x_tile_off;
> + else
> + tile_off = x_tile_off * y_tile_size + y_tile_off;
>
> - tile_n = y_tile_n * tiles_per_line + x_tile_n;
> - tile_off = y_tile_off * x_tile_size + x_tile_off;
> - tiled_pos = tile_n * tile_size + tile_off;
> + pos = tile_n * tile_size + tile_off;
>
> - tiled_pos = swizzle_addr(tiled_pos, swizzle);
> -
> - return tiled_pos / pixel_size;
> + return pos;
> }
>
> -/* It's all in "pixel coordinates", so make sure you multiply/divide by the
> bpp
> - * if you need to. */
> -static void tiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
> - int swizzle, int bpp, int *x, int *y)
> +static void untile(int tiled_pos, int x_tile_size, int y_tile_size,
> +uint32_t line_size, bool xmajor, int *x, int *y)
> {
> - int tile_n, tile_off, tiles_per_line, line_size;
> + int tile_n, tile_off, tiles_per_line;
> int x_tile_off, y_tile_off;
> int x_tile_n, y_tile_n;
> - int x_tile_size, y_tile_size, tile_size;
> - int pixel_size = bpp / 8;
> -
> - tiled_pos = swizzle_addr(tiled_pos, swizzle);
> + int tile_size;
>
> - line_size = stride;
> - x_tile_size = 512;
> - y_tile_size = 8;
> tile_size = x_tile_size * y_tile_size;
> tiles_per_line = line_size / x_tile_size;
>
> tile_n = tiled_pos / tile_size;
> tile_off = tiled_pos % tile_size;
>
> - y_tile_off = tile_off / x_tile_size;
> - x_tile_off = tile_off % x_tile_size;
> + if (xmajor) {
> + y_tile_off = tile_off / x_tile_size;
> + x_tile_off = tile_off % x_tile_size;
> + } else {
> + y_tile_off = tile_off % y_tile_size;
> + x_tile_off = tile_off / y_tile_size;
> + }
>
> x_tile_n = tile_n % tiles_per_line;
> y_tile_n = tile_n / tiles_per_line;
>
> - *x = (x_tile_n * x_tile_size + x_tile_off) / pixel_size;
> + *x = (x_tile_n * x_tile_size + x_tile_off);
> *y = y_tile_n * y_tile_size + y_tile_off;
> }
>
> +static int linear_x_y_to_xtiled_pos(int x, int y, uint32_t stride, int
> swizzle,
> + int bpp)
> +{
> + int pos;
> + int pixel_size = bpp / 8;
> +
> + x *= pixel_size;
> + pos = tile(x, y, 512, 8, stride, true);
> + pos = swizzle_addr(pos, swizzle);
> + return pos / pixel_size;
> +}
> +
> +static int linear_x_y_to_ytiled_pos(int x, int y, uint32_t stride, int
> swizzle,
> + in
Re: [Intel-gfx] [PATCH igt 1/3] lib/igt_fb: also call __gem_set_tiling for Y tiling
On Tue, Feb 02, 2016 at 09:34:11AM +, Tvrtko Ursulin wrote: > > On 01/02/16 17:57, Ville Syrjälä wrote: > >On Mon, Feb 01, 2016 at 05:44:42PM +, Tvrtko Ursulin wrote: > >> > >>On 01/02/16 17:16, Zanoni, Paulo R wrote: > >>>Em Sex, 2016-01-29 às 21:06 +0200, Ville Syrjälä escreveu: > On Fri, Jan 29, 2016 at 04:46:30PM -0200, Paulo Zanoni wrote: > >The interesting thing is that if we don't do this, we still get a > >Y tiled framebuffer, but there won't be a fence around it, which > >makes > >the GTT mmaps less interesting. Is this a Kernel bug? > > I think some tests currently depend on not having a fence for Y tiled > fbs. So this could break stuff. > >>> > >>>Do you have any additional information that could help me discover > >>>which ones? A quick look on the IGT tests mentioning tiling didn't > >>>point anything obvious. > >>> > >>>Besides, I think it's probably not a good idea to have such a high > >>>level helper function behaving differently depending on the tiling > >>>type, I'd vote to either call set_tiling on both or on none. > >> > >>Noticed the thread by accident. :) > >> > >>I can't help with the question of which tests might be affected by this. > >>Some low level ones like kms_addfb don't use the fb helpers so they > >>shouldn't be. Can't remember if any other would be. > >> > >>But just a little bit of background: > >> > >>Basically with the introduction of Y tiled (and Yf) scanout in Gen9 we > >>have forked the path and destroyed the coupling between obj->tiling and > >>framebuffer tiling. > >> > >>The X special casing in create_bo_for_fb is for compatibility with old > >>userspace, but going forward it was decided fb modifiers should be used > >>to tell the driver about tiling and get/set_tiling ioctl is about > >>fencing and only that. > >> > >>Paths implemented in IGT back then were rendering to Y and Yf tiling fbs > >>via a temporary linear surface which is then blitted (blit?) to the real > >>fb obj. (With the blitter doing the appropriate transformation.) > >> > >>So in that respect adding Y tiling to create_bo_for_fb would be wrong > >>because it is not aligned with the above, and also you cannot support Yf > >>this way at all. > >> > >>But I do agree this creates a problem for some use cases within the IGT > >>since the fb and backing obj are created atomically and once that is > >>done you cannot fiddle with obj->tiling (aka fencing). > > > >I suppose we could either make it easier to create the obj and fb > >separately, or we could add a parameter to the fb funcs to indicate > >whether we want a fence or not. > > Either way sounds good to me. Will depend on whatever fits better with what > Paulo is working on at the moment. I'm ok with not tiling by default for anything but X-tiled in the igt_fb code. Users can just call set_tiling on the underlying bo if they want it, but in the shiny new world of Yf/Ys we should by default not use gtt mmaps really for anything. See also some of the changes planned and then cancelled/delayed for future products, where the gtt might go poof entirely. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/gem_exec_params: test all valid execution flags
On Mon, Feb 01, 2016 at 02:24:37PM +, daniele.ceraolospu...@intel.com wrote:
> From: Daniele Ceraolo Spurio
>
> The control subtest has been extended to check the execution flags for
> all the rings that are present in the HW.
>
> Cc: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio
Applied, thanks.
-Daniel
> ---
> tests/gem_exec_params.c | 39 ---
> 1 file changed, 32 insertions(+), 7 deletions(-)
>
> diff --git a/tests/gem_exec_params.c b/tests/gem_exec_params.c
> index 06dfd63..e192150 100644
> --- a/tests/gem_exec_params.c
> +++ b/tests/gem_exec_params.c
> @@ -46,6 +46,30 @@
> #define LOCAL_I915_EXEC_BSD_RING2 (2<<13)
> #define LOCAL_I915_EXEC_RESOURCE_STREAMER (1<<15)
>
> +static bool has_ring(int fd, unsigned ring_exec_flags)
> +{
> + switch (ring_exec_flags & I915_EXEC_RING_MASK) {
> + case 0:
> + case I915_EXEC_RENDER:
> + return true;
> +
> + case I915_EXEC_BSD:
> + if (ring_exec_flags & LOCAL_I915_EXEC_BSD_MASK)
> + return gem_has_bsd2(fd);
> + else
> + return gem_has_bsd(fd);
> +
> + case I915_EXEC_BLT:
> + return gem_has_blt(fd);
> +
> + case I915_EXEC_VEBOX:
> + return gem_has_vebox(fd);
> + }
> +
> + igt_assert_f(0, "invalid exec flag 0x%x\n", ring_exec_flags);
> + return false;
> +}
> +
> struct drm_i915_gem_execbuffer2 execbuf;
> struct drm_i915_gem_exec_object2 gem_exec[1];
> uint32_t batch[2] = {MI_BATCH_BUFFER_END};
> @@ -54,6 +78,8 @@ int fd;
>
> igt_main
> {
> + const struct intel_execution_engine *e;
> +
> igt_fixture {
> fd = drm_open_driver(DRIVER_INTEL);
>
> @@ -85,13 +111,12 @@ igt_main
> }
>
> igt_subtest("control") {
> - igt_assert(drmIoctl(fd,
> - DRM_IOCTL_I915_GEM_EXECBUFFER2,
> - &execbuf) == 0);
> - execbuf.flags = I915_EXEC_RENDER;
> - igt_assert(drmIoctl(fd,
> - DRM_IOCTL_I915_GEM_EXECBUFFER2,
> - &execbuf) == 0);
> + for (e = intel_execution_engines; e->name; e++) {
> + if (has_ring(fd, e->exec_id | e->flags)) {
> + execbuf.flags = e->exec_id | e->flags;
> + gem_execbuf(fd, &execbuf);
> + }
> + }
> }
>
> #define RUN_FAIL(expected_errno) do { \
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [maintainer-tools RFC PATCH] dim: add cherry-pick-[next-]fixes subcommands
On Fri, Jan 29, 2016 at 09:40:32AM +0200, Jani Nikula wrote:
> Add two new subcommands for cherry-picking fixes from dinq to
> drm-intel-fixes and drm-intel-next-fixes. The only difference in the
> subcommands is the assert branch check to ensure the user is on the
> right branch.
>
> The commands scan dinq for commits Cc'd to stable or drm-intel-fixes,
> checks whether they've already been backported, attempts cherry-pick,
> and asks for directions on failed cherry-pick.
>
> It's still rough around the edges and slow as molasses due to unlimited
> scan for backports (should just check a release or two back at most),
> and an aborted run just starts over next time (though it should take the
> freshly backported commits into account).
>
> Signed-off-by: Jani Nikula
>
> ---
>
> Undecided whether we should apply this already or not. It's crude, but I
> use it.
Imo add help text and push it. We can prettify later on. Oh and maybe bash
completion too. Wrt speeding this up, have you looked at gregkh's
toolchaing for stable kernels? It should be out there somewhere.
-Daniel
> ---
> dim | 49 +
> 1 file changed, 49 insertions(+)
>
> diff --git a/dim b/dim
> index 203c6b60cf1b..c64f6e86af62 100755
> --- a/dim
> +++ b/dim
> @@ -473,6 +473,55 @@ function dim_cherry_pick
> $DRY git cherry-pick $1
> }
>
> +function dim_cherry_pick_branch
> +{
> + for commit in $(git log --reverse --format=format:%h
> --grep="drm-intel-fi...@lists.freedesktop.org"
> --grep="sta...@vger.kernel.org"
> origin/master..$DIM_DRM_INTEL_REMOTE/drm-intel-next-queued --
> drivers/gpu/drm/i915); do
> + echo "Considering $(git --no-pager log --oneline -1 $commit)"
> + log=$(mktemp)
> + # note *local* branches to account for unpushed ones
> + git log drm-intel-fixes --oneline --grep="cherry picked .*
> $commit" > $log
> + git log drm-intel-next-fixes --oneline --grep="cherry picked .*
> $commit" >> $log
> + if [ "$(cat $log)" = "" ]; then
> + if ! git cherry-pick -e -x -s $commit; then
> + select choice in "Diff" "Resolve" "Skip"
> "Abort"; do
> + case $choice in
> + Diff)
> + git diff
> + ;;
> + Resolve)
> + exit
> + ;;
> + Skip)
> + git cherry-pick --abort
> + break
> + ;;
> + Abort)
> + git cherry-pick --abort
> + exit
> + ;;
> + esac
> + done
> + fi
> + else
> + echo "Already backported as:"
> + sed 's/^/\t/' < $log
> + fi
> + rm -f $log
> + done
> +}
> +
> +function dim_cherry_pick_fixes
> +{
> + assert_branch drm-intel-fixes
> + dim_cherry_pick_branch "$@"
> +}
> +
> +function dim_cherry_pick_next_fixes
> +{
> + assert_branch drm-intel-next-fixes
> + dim_cherry_pick_branch "$@"
> +}
> +
> dim_alias_ar=apply-resolved
> function dim_apply_resolved
> {
> --
> 2.1.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 02/29] drm/i915: Introduce host graphics memory balloon for gvt
On Thu, Jan 28, 2016 at 06:21:24PM +0800, Zhi Wang wrote:
> From: Bing Niu
>
> This patch introduces host graphics memory ballon when GVT-g is enabled.
>
> As under GVT-g, i915 only owned limited graphics resources, others are
> managed by GVT-g resource allocator and kept for other vGPUs.
>
> For graphics memory space partition, a typical layout looks like:
>
> +---+---+--+---+
> |* Host | *GVT-g Resource |* Host| *GVT-g Resource |
> | Owned | Allocator Managed | Owned| Allocator Managed |
> | | | | |
> +---+---+--+---+---+
> | | | | | | | | |
> | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 |
> | | | | | | | | |
> +---+---+---+--+---+---+---+
> | Aperture|Hidden|
> +---+--+
> | GGTT memory space |
> +--+
>
> Similar with fence registers partition:
>
> +-- +---+
> | * Host|GVT-g Resource |
> | Owned | Allocator Managed +
> 0 | 31
> +---+---+---+
> | | | | |
> | i915 | vm 1 | vm 2 | vm 3 |
> | | | | |
> +---+---+---+---+
This kind of pretty graphs should be in the kerneldoc - with the asciidoc
support we have already in drm-intel-nightly (and hopefully soonish in
upstream). See
http://blog.ffwll.ch/2016/01/better-markup-for-kernel-gpu-docbook.html
Cheers, Daniel
>
> i915 host will read the amount of allocated resources via GVT-g kernel
> parameters.
>
> Signed-off-by: Bing Niu
> Signed-off-by: Zhi Wang
> ---
> drivers/gpu/drm/i915/gvt/params.h | 3 +++
> drivers/gpu/drm/i915/i915_gem.c | 3 +++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.c| 16
> drivers/gpu/drm/i915/i915_vgpu.h| 1 +
> 5 files changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/params.h
> b/drivers/gpu/drm/i915/gvt/params.h
> index d2955b9..0656a98 100644
> --- a/drivers/gpu/drm/i915/gvt/params.h
> +++ b/drivers/gpu/drm/i915/gvt/params.h
> @@ -27,6 +27,9 @@
> struct gvt_kernel_params {
> bool enable;
> int debug;
> + int dom0_low_gm_sz;
> + int dom0_high_gm_sz;
> + int dom0_fence_sz;
> };
>
> extern struct gvt_kernel_params gvt;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 799a53a..e916e43 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5080,6 +5080,9 @@ i915_gem_load(struct drm_device *dev)
> else
> dev_priv->num_fence_regs = 8;
>
> + if(intel_gvt_host_active(dev))
> + dev_priv->num_fence_regs = gvt.dom0_fence_sz;
> +
> if (intel_vgpu_active(dev))
> dev_priv->num_fence_regs =
> I915_READ(vgtif_reg(avail_rs.fence_num));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7377b67..0540de2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2713,7 +2713,7 @@ static int i915_gem_setup_global_gtt(struct drm_device
> *dev,
> i915_address_space_init(ggtt_vm, dev_priv);
> ggtt_vm->total += PAGE_SIZE;
>
> - if (intel_vgpu_active(dev)) {
> + if (intel_vgpu_active(dev) || intel_gvt_host_active(dev)) {
> ret = intel_vgt_balloon(dev);
> if (ret)
> return ret;
> @@ -2810,7 +2810,7 @@ void i915_global_gtt_cleanup(struct drm_device *dev)
> }
>
> if (drm_mm_initialized(&vm->mm)) {
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev) || intel_gvt_host_active(dev))
> intel_vgt_deballoon();
>
> drm_mm_takedown(&vm->mm);
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index dea7429..fbe6114 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -188,10 +188,18 @@ int intel_vgt_balloon(struct drm_device *dev)
> unsigned long unmappable_base, unmappable_size, unmappable_end;
> int ret;
>
> - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
> + if(intel_gvt_host_active(d
