Re: [Intel-gfx] [PATCH v3] drm/i915/fbc: FBC causes display flicker when VT-d is enabled on Skylake
On Thu, 23 Jun 2016, "Zanoni, Paulo R" wrote:
> Em Ter, 2016-06-21 às 08:25 +0100, Chris Wilson escreveu:
>> Erratum SKL075: Display Flicker May Occur When Both VT-d And FBC Are
>> Enabled
>>
>> "Display flickering may occur when both FBC (Frame Buffer
>> Compression)
>> and VT - d (Intel® Virtualization Technology for Directed I/O) are
>> enabled
>> and in use by the display controller."
>>
>> Ville found the w/a name in the database:
>> WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl
>>
>> v2: Log when the quirk is applied.
>> v3: Ensure i915.enable_fbc is false when !HAS_FBC()
>>
>> Signed-off-by: Chris Wilson
>> Cc: Paulo Zanoni
>> Cc: Ville Syrjälä
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/intel_fbc.c | 19 +++
>> 2 files changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 89298d3ad94b..f1e9fd07d441 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2586,6 +2586,8 @@ struct drm_i915_cmd_table {
>> #define INTEL_GEN(p)(INTEL_INFO(p)->gen)
>> #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
>>
>> +#define mkwrite_intel_info(p) ((struct intel_device_info
>> *)INTEL_INFO(p))
>
> So why don't we un-const struct intel_device_info?
Yeah, this is more than a little ugly. Either it should stay const and
we shouldn't modify it (except in intel_device_info_runtime_init(), and
even that is a bit ugly), or we make it non-const.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC loading status check
Hi Peter,
Besides debugfs, could you add a IOCTL to check HuC loading status?
Userspace media driver needs to advertise the features based on HuC to
user.
Thanks
Haihao
> From: Alex Dai
>
> Add debugfs entry for HuC loading status check.
>
> Signed-off-by: Alex Dai
> Signed-off-by: Peter Antoine
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 32
>
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 69964c2..f5976f8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void
> *data)
> return 0;
> }
>
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> + struct drm_info_node *node = m->private;
> + struct drm_i915_private *dev_priv = node->minor->dev-
> >dev_private;
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + if (!HAS_HUC_UCODE(dev_priv->dev))
> + return 0;
> +
> + seq_puts(m, "HuC firmware status:\n");
> + seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> + seq_printf(m, "\tfetch: %s\n",
> + intel_uc_fw_status_repr(huc_fw->fetch_status));
> + seq_printf(m, "\tload: %s\n",
> + intel_uc_fw_status_repr(huc_fw->load_status));
> + seq_printf(m, "\tversion wanted: %d.%d\n",
> + huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> + seq_printf(m, "\tversion found: %d.%d\n",
> + huc_fw->major_ver_found, huc_fw->minor_ver_found);
> + seq_printf(m, "\theader: offset is %d; size = %d\n",
> + huc_fw->header_offset, huc_fw->header_size);
> + seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> + huc_fw->ucode_offset, huc_fw->ucode_size);
> + seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> + huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> + seq_printf(m, "\nHuC status 0x%08x:\n",
> I915_READ(HUC_STATUS2));
> +
> + return 0;
> +}
> +
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_info_node *node = m->private;
> @@ -5432,6 +5463,7 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
> {"i915_guc_info", i915_guc_info, 0},
> {"i915_guc_load_status", i915_guc_load_status_info, 0},
> {"i915_guc_log_dump", i915_guc_log_dump, 0},
> + {"i915_huc_load_status", i915_huc_load_status_info, 0},
> {"i915_frequency_info", i915_frequency_info, 0},
> {"i915_hangcheck_info", i915_hangcheck_info, 0},
> {"i915_drpc_info", i915_drpc_info, 0},
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[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] lib/gt: Omit illegal instruction on hang injection with gen 8+
== Series Details == Series: series starting with [1/2] lib/gt: Omit illegal instruction on hang injection with gen 8+ URL : https://patchwork.freedesktop.org/series/8452/ State : failure == Summary == Applying: lib/gt: Omit illegal instruction on hang injection with gen 8+ fatal: sha1 information is lacking or useless (lib/igt_gt.c). error: could not build fake ancestor Patch failed at 0001 lib/gt: Omit illegal instruction on hang injection with gen 8+ The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for Runtime: set the sub slice according to kernel pooled EU configure.
== Series Details == Series: Runtime: set the sub slice according to kernel pooled EU configure. URL : https://patchwork.freedesktop.org/series/8724/ State : failure == Summary == Applying: Runtime: set the sub slice according to kernel pooled EU configure. fatal: sha1 information is lacking or useless (CMakeLists.txt). error: could not build fake ancestor Patch failed at 0001 Runtime: set the sub slice according to kernel pooled EU configure. The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for Convert requests to use struct fence (rev9)
== Series Details == Series: Convert requests to use struct fence (rev9) URL : https://patchwork.freedesktop.org/series/1068/ State : failure == Summary == Applying: drm/i915: Add per context timelines for fence objects fatal: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_gem.c). error: could not build fake ancestor Patch failed at 0001 drm/i915: Add per context timelines for fence objects The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/3] drm/i915/dp: Free the drm_dp_aux along with the encoder
== Series Details == Series: series starting with [1/3] drm/i915/dp: Free the drm_dp_aux along with the encoder URL : https://patchwork.freedesktop.org/series/8847/ State : failure == Summary == Applying: drm/i915/dp: Free the drm_dp_aux along with the encoder Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_dp.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm/i915: Move intel_connector->unregister to connector->early_unregister Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/intel_crt.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_dp.c M drivers/gpu/drm/i915/intel_dp_mst.c M drivers/gpu/drm/i915/intel_drv.h M drivers/gpu/drm/i915/intel_dsi.c M drivers/gpu/drm/i915/intel_dvo.c M drivers/gpu/drm/i915/intel_hdmi.c M drivers/gpu/drm/i915/intel_lvds.c M drivers/gpu/drm/i915/intel_sdvo.c M drivers/gpu/drm/i915/intel_tv.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_dp.c Auto-merging drivers/gpu/drm/i915/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.c error: Failed to merge in the changes. Patch failed at 0002 drm/i915: Move intel_connector->unregister to connector->early_unregister The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 0/8] Add two-stage watermark programming for VLV/CHV (v4)
From: root In addition to calculating final watermarks, we also pre-calculate a set of intermediate watermark values at atomic check time. These intermediate watermarks are a combination of the watermarks for the old state and the new state; they should satisfy the requirements of both states which means they can be programmed immediately when we commit the atomic state (without waiting for a vblank). Once the vblank does happen, we can then re-program watermarks to the more optimal final value. The DSPARB Display Arbitration Control register is double buffered. The FIFO repartitioning happens atomically with plane updates but how the register double buffering works isn't clear at the moment. It needs to be figured out to fix the watermark updates. v2: Split the first patch of v1 into the following patches - Remove unused parameters from intel_plane_wm_parameters. - Rename skl_plane_id to wm_plane_id. - Move fifo_size from intel_plane_wm_parameters to vlv_wm_state. v3: Split the 3rd patch of v2 into the following two patches - Move fifo_size from intel_plane_wm_parameters to vlv_wm_state - Change to use intel_crtc_state instead of base CRTC object - The patch headlines are also changed to fit the requirement. v4: - Split the 3rd patch of v3 "Move fifo_size from intel_plane_wm_parameters to vlv_wm_state" to add a new one "return EINVAL when computed watermark exceeds system limitation" - Add a new patch "Move active watermarks into intel_crtc->wm.active.vlv" to be consistent with what we do on other platforms - Change the patch "Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark" to use macro drm_atomic_crtc_state_for_each_plane_state to simplify the code - Change the patch "Add optimal field in intel_crtc_wm_state" to use mutex in vlv_update_wm to make assigning currently active wm_state and merging multiple wm_state become one atomic operation Signed-off-by: Maarten Lankhorst Signed-off-by: Chi Ding Maarten Lankhorst (8): drm/i915: Remove unused parameters from intel_plane_wm_parameters drm/i915: Rename skl_plane_id to wm_plane_id drm/i915/vlv: Move fifo_size from intel_plane_wm_parameters to vlv_wm_state drm/i915/vlv: return EINVAL when computed watermark exceeds system limitation drm/i915/vlv: Change to use intel_crtc_state instead of base CRTC object drm/i915/vlv: Add optimal field in intel_crtc_wm_state drm/i915/vlv: Move active watermarks into intel_crtc->wm.active.vlv drm/i915/vlv: Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark drivers/gpu/drm/i915/intel_display.c | 7 +- drivers/gpu/drm/i915/intel_drv.h | 52 ++ drivers/gpu/drm/i915/intel_pm.c | 328 +++ 3 files changed, 233 insertions(+), 154 deletions(-) -- 1.8.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 4/8] drm/i915/vlv: return EINVAL when computed watermark exceeds system limitation
From: Maarten Lankhorst
When computing normal watermarks in vlv_compute_wm(), if the value
is bigger than system limitation, return EINVAL
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a8aba2d..3dbe160 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1127,9 +1127,14 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
int wm = vlv_compute_wm_level(plane, crtc, state,
level);
int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR
? 63 : 511;
- /* hack */
- if (WARN_ON(level == 0 && wm > max_wm))
- wm = max_wm;
+ if (level == 0 && wm > max_wm) {
+ DRM_DEBUG_KMS("Requested display configuration "
+ "exceeds system watermark limitations\n");
+ DRM_DEBUG_KMS("Plane %d.%d: blocks required =
%u/%u\n",
+ crtc->pipe,
+ drm_plane_index(&plane->base), wm,
max_wm);
+ return -EINVAL;
+ }
if (wm > wm_state->fifo_size[wm_plane_id(plane)])
break;
--
1.8.0.1
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Re: [Intel-gfx] DP link training and performance issues with HDMI USB-C dongle and Skylake
On Thu, 23 Jun 2016, Andy Lutomirski wrote: > I have a Dell XPS 13 9350 (Skylake) and a Dell DA200 adapter. The > latter is a Thunderbolt device that includes an HDMI port and connects > over USB Type C. I believe that it's internally using DP Alternate > Mode. > I don't know whether this is a hardware issue, an Alpine Ridge > firmware issue (mine is out of date because it appears to be > impossible to update it on Linux for now), or an i915 driver issue. At least a driver issue. The support is not there yet. Bug at [1]. BR, Jani. [1] https://bugs.freedesktop.org/show_bug.cgi?id=93578 -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/8] drm/i915: Rename skl_plane_id to wm_plane_id
From: Maarten Lankhorst
This function will be used not only by SKL but also VLV/CHV.
Therefore it's renamed
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 59 +
1 file changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29bdd79..adbd438 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -54,6 +54,28 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
+/*
+ * Return the index of a plane in the DDB and wm result arrays. Primary
+ * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
+ * other universal planes are in indices 1..n. Note that this may leave unused
+ * indices between the top "sprite" plane and the cursor.
+ */
+static int
+wm_plane_id(const struct intel_plane *plane)
+{
+ switch (plane->base.type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ return 0;
+ case DRM_PLANE_TYPE_CURSOR:
+ return PLANE_CURSOR;
+ case DRM_PLANE_TYPE_OVERLAY:
+ return plane->plane + 1;
+ default:
+ MISSING_CASE(plane->base.type);
+ return plane->plane;
+ }
+}
+
static void bxt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2828,27 +2850,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
#define SKL_DDB_SIZE 896 /* in blocks */
#define BXT_DDB_SIZE 512
-/*
- * Return the index of a plane in the SKL DDB and wm result arrays. Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n. Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
- switch (plane->base.type) {
- case DRM_PLANE_TYPE_PRIMARY:
- return 0;
- case DRM_PLANE_TYPE_CURSOR:
- return PLANE_CURSOR;
- case DRM_PLANE_TYPE_OVERLAY:
- return plane->plane + 1;
- default:
- MISSING_CASE(plane->base.type);
- return plane->plane;
- }
-}
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
@@ -3011,7 +3012,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate)
/* Calculate and cache data rate for each plane */
for_each_plane_in_state(state, plane, pstate, i) {
- id = skl_wm_plane_id(to_intel_plane(plane));
+ id = wm_plane_id(to_intel_plane(plane));
intel_plane = to_intel_plane(plane);
if (intel_plane->pipe != intel_crtc->pipe)
@@ -3030,7 +3031,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate)
/* Calculate CRTC's total data rate from cached values */
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
/* packed/uv */
total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
@@ -3088,7 +3089,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
/* 1. Allocate the mininum required blocks for each active plane */
for_each_plane_in_state(state, plane, pstate, i) {
intel_plane = to_intel_plane(plane);
- id = skl_wm_plane_id(intel_plane);
+ id = wm_plane_id(intel_plane);
if (intel_plane->pipe != pipe)
continue;
@@ -3130,7 +3131,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
unsigned int data_rate, y_data_rate;
uint16_t plane_blocks, y_plane_blocks = 0;
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
data_rate = cstate->wm.skl.plane_data_rate[id];
@@ -3321,7 +3322,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
DRM_DEBUG_KMS("Requested display configuration exceeds
system watermark limitations\n");
DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u,
lines required = %u/31\n",
to_intel_crtc(cstate->base.crtc)->pipe,
-
skl_wm_plane_id(to_intel_plane(pstate->plane)),
+
wm_plane_id(to_intel_plane(pstate->plane)),
res_blocks, ddb_allocation, res_lines);
return -EINVAL;
@@ -3359,7 +3360,7 @@ skl_compute_wm_level(const struct drm_i915_private
*dev_priv,
[Intel-gfx] [RFC 5/8] drm/i915/vlv: Change to use intel_crtc_state instead of base CRTC object
From: Maarten Lankhorst
This commit changs some functions to operate on intel_crtc_state rather
than the base CRTC objects in order to transit to atomic. The reason we
want to do this is to allow future patches to move the computation steps
into the atomic 'check' phase where they'll be operating on in-flight CRTC
states rather than already-committed states.
v2: make the change for vlv_compute_wm_level() which is forgotten in v1
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3dbe160..03cd139 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -947,7 +947,7 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
}
static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
-struct intel_crtc *crtc,
+ const struct intel_crtc_state *cstate,
const struct intel_plane_state *state,
int level)
{
@@ -961,9 +961,9 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return 0;
cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- clock = crtc->config->base.adjusted_mode.crtc_clock;
- htotal = crtc->config->base.adjusted_mode.crtc_htotal;
- width = crtc->config->pipe_src_w;
+ clock = cstate->base.adjusted_mode.crtc_clock;
+ htotal = cstate->base.adjusted_mode.crtc_htotal;
+ width = cstate->pipe_src_w;
if (WARN_ON(htotal == 0))
htotal = 1;
@@ -983,8 +983,9 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return min_t(int, wm, USHRT_MAX);
}
-static void vlv_compute_fifo(struct intel_crtc *crtc)
+static void vlv_compute_fifo(struct intel_crtc_state *cstate)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct vlv_wm_state *wm_state = &crtc->wm_state;
struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
@@ -1088,8 +1089,9 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
}
}
-static int vlv_compute_wm(struct intel_crtc *crtc)
+static int vlv_compute_wm(struct intel_crtc_state *cstate)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct vlv_wm_state *wm_state = &crtc->wm_state;
struct intel_plane *plane;
@@ -1103,7 +1105,7 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
wm_state->num_active_planes = 0;
- vlv_compute_fifo(crtc);
+ vlv_compute_fifo(cstate);
if (wm_state->num_active_planes != 1)
wm_state->cxsr = false;
@@ -1124,7 +1126,7 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
/* normal watermarks */
for (level = 0; level < wm_state->num_levels; level++) {
- int wm = vlv_compute_wm_level(plane, crtc, state,
level);
+ int wm = vlv_compute_wm_level(plane, cstate, state,
level);
int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR
? 63 : 511;
if (level == 0 && wm > max_wm) {
@@ -1328,7 +1330,7 @@ static void vlv_update_wm(struct drm_crtc *crtc)
enum pipe pipe = intel_crtc->pipe;
struct vlv_wm_values wm = {};
- vlv_compute_wm(intel_crtc);
+ vlv_compute_wm(intel_crtc->config);
vlv_merge_wm(dev, &wm);
if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
--
1.8.0.1
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[Intel-gfx] [RFC 3/8] drm/i915/vlv: Move fifo_size from intel_plane_wm_parameters to vlv_wm_state
From: Maarten Lankhorst
This commit saves watermark for each plane in vlv_wm_state to prepare
for two-level watermark because we'll compute and save intermediate and
optimal watermark and fifo size for each plane.
v2:
- remove redundant debug statements in vlv_pipe_set_fifo_size()
- reverse passing vlv_wm_state by parameter because it's unrelated to the
patch
- reverse the change of returning EINVAL when wm > max_wm in vlv_compute_wm
because it's unrelated to the patch
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 12 +-
drivers/gpu/drm/i915/intel_pm.c | 90
2 files changed, 46 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ec34d649..9d83494 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -621,6 +621,7 @@ struct intel_crtc_state {
struct vlv_wm_state {
struct vlv_pipe_wm wm[3];
struct vlv_sr_wm sr[3];
+ uint16_t fifo_size[I915_MAX_PLANES];
uint8_t num_active_planes;
uint8_t num_levels;
uint8_t level;
@@ -693,10 +694,6 @@ struct intel_crtc {
struct vlv_wm_state wm_state;
};
-struct intel_plane_wm_parameters {
- uint16_t fifo_size;
-};
-
struct intel_plane {
struct drm_plane base;
int plane;
@@ -705,13 +702,6 @@ struct intel_plane {
int max_downscale;
uint32_t frontbuffer_bit;
- /* Since we need to change the watermarks before/after
-* enabling/disabling the planes, we need to store the parameters here
-* as the other pieces of the struct may not reflect the values we want
-* for the watermark calculations. Currently only Haswell uses this.
-*/
- struct intel_plane_wm_parameters wm;
-
/*
* NOTE: Do not place new plane state fields here (e.g., when adding
* new plane properties). New runtime state should now be placed in
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adbd438..a8aba2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -985,12 +985,14 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
static void vlv_compute_fifo(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
unsigned int total_rate = 0;
const int fifo_size = 512 - 1;
int fifo_extra, fifo_left = fifo_size;
+ int rate[I915_MAX_PLANES] = {};
+ int i;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct intel_plane_state *state =
@@ -1001,49 +1003,46 @@ static void vlv_compute_fifo(struct intel_crtc *crtc)
if (state->visible) {
wm_state->num_active_planes++;
- total_rate +=
drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ rate[wm_plane_id(plane)] =
+ drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ total_rate += rate[wm_plane_id(plane)];
}
}
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct intel_plane_state *state =
- to_intel_plane_state(plane->base.state);
- unsigned int rate;
-
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
- plane->wm.fifo_size = 63;
+ for (i = 0; i < I915_MAX_PLANES; i++) {
+ if (i == PLANE_CURSOR) {
+ wm_state->fifo_size[i] = 63;
continue;
}
- if (!state->visible) {
- plane->wm.fifo_size = 0;
+ if (!rate[i]) {
+ wm_state->fifo_size[i] = 0;
continue;
}
- rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- plane->wm.fifo_size = fifo_size * rate / total_rate;
- fifo_left -= plane->wm.fifo_size;
+ wm_state->fifo_size[i] = fifo_size * rate[i] / total_rate;
+ fifo_left -= wm_state->fifo_size[i];
}
fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
/* spread the remainder evenly */
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for (i = 0; i < I915_MAX_PLANES; i++) {
int plane_extra;
if (fifo_left == 0)
break;
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ if (i == PLANE_CURSOR)
continue;
/* give it all to the first plane if none are active */
- if (plane->wm.fifo_size ==
[Intel-gfx] [RFC 1/8] drm/i915: Remove unused parameters from intel_plane_wm_parameters
From: Maarten Lankhorst
Everything except fifo_size is unused and therefore removed
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 97de5e0..ec34d649 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -694,21 +694,6 @@ struct intel_crtc {
};
struct intel_plane_wm_parameters {
- uint32_t horiz_pixels;
- uint32_t vert_pixels;
- /*
-* For packed pixel formats:
-* bytes_per_pixel - holds bytes per pixel
-* For planar pixel formats:
-* bytes_per_pixel - holds bytes per pixel for uv-plane
-* y_bytes_per_pixel - holds bytes per pixel for y-plane
-*/
- uint8_t bytes_per_pixel;
- uint8_t y_bytes_per_pixel;
- bool enabled;
- bool scaled;
- u64 tiling;
- unsigned int rotation;
uint16_t fifo_size;
};
--
1.8.0.1
___
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[Intel-gfx] [RFC 7/8] drm/i915/vlv: Move active watermarks into intel_crtc->wm.active.vlv
From: Maarten Lankhorst
Previously the active watermarks is saved in intel_crtc->wm_state
This commit adds a new field "vlv" into intel_crtc->wm.active and save
the active watermarks in it to be consistent with what we do on other
platforms.
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6d616b6..2d3dfec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -678,6 +678,7 @@ struct intel_crtc {
union {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
+ struct vlv_wm_state vlv;
} active;
/* allow CxSR on this pipe */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0076716..ceded5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1204,7 +1204,7 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
- const struct vlv_wm_state *wm_state = &crtc->wm_state;
+ const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
WARN_ON(wm_state->fifo_size[PLANE_CURSOR] != 63);
@@ -1286,7 +1286,7 @@ static void vlv_merge_wm(struct drm_device *dev,
wm->cxsr = true;
for_each_intel_crtc(dev, crtc) {
- const struct vlv_wm_state *wm_state = &crtc->wm_state;
+ const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
if (!crtc->active)
continue;
@@ -1305,7 +1305,7 @@ static void vlv_merge_wm(struct drm_device *dev,
wm->level = VLV_WM_LEVEL_PM2;
for_each_intel_crtc(dev, crtc) {
- struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
enum pipe pipe = crtc->pipe;
if (!crtc->active)
@@ -1332,7 +1332,7 @@ static void vlv_update_wm(struct drm_crtc *crtc)
vlv_compute_wm(intel_crtc->config);
mutex_lock(&dev_priv->wm.wm_mutex);
- intel_crtc->wm_state = intel_crtc->config->wm.vlv.optimal;
+ intel_crtc->wm.active.vlv = intel_crtc->config->wm.vlv.optimal;
vlv_merge_wm(dev, &wm);
mutex_unlock(&dev_priv->wm.wm_mutex);
@@ -4234,7 +4234,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
int i = wm_plane_id(plane);
crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, plane->pipe));
- wm_state = &crtc->wm_state;
+ wm_state = &crtc->wm.active.vlv;
switch (plane->base.type) {
case DRM_PLANE_TYPE_CURSOR:
@@ -4288,7 +4288,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
pipe = crtc->pipe;
to_intel_crtc_state(crtc->base.state)->wm.vlv.optimal
- = crtc->wm_state;
+ = crtc->wm.active.vlv;
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d,
cursor=%d, sprite0=%d, sprite1=%d\n",
pipe_name(pipe), wm->pipe[pipe].primary,
wm->pipe[pipe].cursor,
--
1.8.0.1
___
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[Intel-gfx] [RFC 8/8] drm/i915/vlv: Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark
From: Maarten Lankhorst
Rename vlv_compute_wm to vlv_compute_pipe_wm to compute optimal watermark
Add vlv_compute_intermediate_wm to computer intermediate watermark
Add vlv_initial_watermarks to write intermediate watermark into hardware
Add vlv_optimize_watermarks to write optimal watermark into hardware
Change valleyview_crtc_enable to call .initial_watermarks handler
This patch adds the handlers for two-level atomic watermark for VLV/CHV.
It makes use of the optimal and intermediate watermark fields added in
the previous commits to calculate the optimal and intermediate state.
It sets the intermediate watermark which is the safer value of the
currently active and the optimal watermark pre-vblank. Then it sets the
optimal watermark after-vblank.
v2:
- use macro drm_atomic_crtc_state_for_each_plane_state
- remove redundant debug statements in vlv_pipe_set_fifo_size
v3:
- use macro drm_atomic_crtc_state_for_each_plane_state to simplify the code
- check !new_state->active || modeset in computing intermediate watermark
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_display.c | 7 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 150 +++
3 files changed, 121 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3f8987b..431d082 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4598,8 +4598,6 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
intel_frontbuffer_flip(dev, pipe_config->fb_bits);
- crtc->wm.cxsr_allowed = true;
-
if (pipe_config->update_wm_post && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
@@ -4645,7 +4643,6 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
}
if (pipe_config->disable_cxsr) {
- crtc->wm.cxsr_allowed = false;
/*
* Vblank time updates from the shadow to live plane control
register
@@ -6092,7 +6089,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
intel_color_load_luts(&pipe_config->base);
- intel_update_watermarks(crtc);
+ dev_priv->display.initial_watermarks(pipe_config);
intel_enable_pipe(intel_crtc);
assert_vblank_disabled(crtc);
@@ -14310,8 +14307,6 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
intel_crtc->cursor_cntl = ~0;
intel_crtc->cursor_size = ~0;
- intel_crtc->wm.cxsr_allowed = true;
-
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2d3dfec..c207148 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -447,6 +447,7 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ struct vlv_wm_state intermediate;
struct vlv_wm_state optimal;
} vlv;
@@ -681,8 +682,6 @@ struct intel_crtc {
struct vlv_wm_state vlv;
} active;
- /* allow CxSR on this pipe */
- bool cxsr_allowed;
} wm;
int scanline_offset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ceded5b..d9d1ecb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -30,6 +30,7 @@
#include "intel_drv.h"
#include "../../../platform/x86/intel_ips.h"
#include
+#include
/**
* DOC: RC6
@@ -964,6 +965,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
clock = cstate->base.adjusted_mode.crtc_clock;
htotal = cstate->base.adjusted_mode.crtc_htotal;
width = cstate->pipe_src_w;
+
if (WARN_ON(htotal == 0))
htotal = 1;
@@ -986,27 +988,28 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
static void vlv_compute_fifo(struct intel_crtc_state *cstate,
struct vlv_wm_state *wm_state)
{
- struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
- struct drm_device *dev = crtc->base.dev;
- struct intel_plane *plane;
unsigned int total_rate = 0;
const int fifo_size = 512 - 1;
int fifo_extra, fifo_left = fifo_size;
int rate[I915_MAX_PLANES] = {};
int i;
+ const struct drm_plane_state *pstate;
+ struct drm_plane *plane;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
&cstate->base) {
struct intel_p
[Intel-gfx] [RFC 6/8] drm/i915/vlv: Add optimal field in intel_crtc_wm_state
From: Maarten Lankhorst
For two-stage watermark programming, we need to calculate optimal
watermark which is set after vblank and intermediate watermark which
can be set without waiting for vblank.
This commit adds optimal watermark field and changes the code to use it
in vlv_compute_wm(), vlv_update_wm() and vlv_wm_get_hw_state()
v2:
- use mutex in vlv_update_wm to make assigning currently active wm_state
and merging multiple wm_state become one atomic operation
- change vlv_compute_fifo and vlv_invert_wms to pass wm_state as parameter
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 23 ++-
drivers/gpu/drm/i915/intel_pm.c | 24
2 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d83494..6d616b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -417,6 +417,16 @@ struct skl_pipe_wm {
uint32_t linetime;
};
+struct vlv_wm_state {
+ struct vlv_pipe_wm wm[3];
+ struct vlv_sr_wm sr[3];
+ uint16_t fifo_size[I915_MAX_PLANES];
+ uint8_t num_active_planes;
+ uint8_t num_levels;
+ uint8_t level;
+ bool cxsr;
+};
+
struct intel_crtc_wm_state {
union {
struct {
@@ -437,6 +447,10 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ struct vlv_wm_state optimal;
+ } vlv;
+
+ struct {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
@@ -618,15 +632,6 @@ struct intel_crtc_state {
uint32_t gamma_mode;
};
-struct vlv_wm_state {
- struct vlv_pipe_wm wm[3];
- struct vlv_sr_wm sr[3];
- uint16_t fifo_size[I915_MAX_PLANES];
- uint8_t num_active_planes;
- uint8_t num_levels;
- uint8_t level;
- bool cxsr;
-};
struct intel_crtc {
struct drm_crtc base;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03cd139..0076716 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -983,10 +983,10 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return min_t(int, wm, USHRT_MAX);
}
-static void vlv_compute_fifo(struct intel_crtc_state *cstate)
+static void vlv_compute_fifo(struct intel_crtc_state *cstate,
+ struct vlv_wm_state *wm_state)
{
struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
- struct vlv_wm_state *wm_state = &crtc->wm_state;
struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
unsigned int total_rate = 0;
@@ -1050,9 +1050,9 @@ static void vlv_compute_fifo(struct intel_crtc_state
*cstate)
WARN_ON(fifo_left != 0);
}
-static void vlv_invert_wms(struct intel_crtc *crtc)
+static void vlv_invert_wms(struct intel_crtc *crtc,
+ struct vlv_wm_state *wm_state)
{
- struct vlv_wm_state *wm_state = &crtc->wm_state;
int level;
for (level = 0; level < wm_state->num_levels; level++) {
@@ -1093,7 +1093,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
{
struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
- struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct vlv_wm_state *wm_state = &cstate->wm.vlv.optimal;
struct intel_plane *plane;
int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
int level;
@@ -1105,7 +1105,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
wm_state->num_active_planes = 0;
- vlv_compute_fifo(cstate);
+ vlv_compute_fifo(cstate, wm_state);
if (wm_state->num_active_planes != 1)
wm_state->cxsr = false;
@@ -1191,7 +1191,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
}
- vlv_invert_wms(crtc);
+ vlv_invert_wms(crtc, wm_state);
return 0;
}
@@ -1331,7 +1331,10 @@ static void vlv_update_wm(struct drm_crtc *crtc)
struct vlv_wm_values wm = {};
vlv_compute_wm(intel_crtc->config);
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ intel_crtc->wm_state = intel_crtc->config->wm.vlv.optimal;
vlv_merge_wm(dev, &wm);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
/* FIXME should be part of crtc atomic commit */
@@ -4282,10 +4285,15 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
- for_each_pipe(dev_priv, pipe)
+ for_each_intel_crtc(dev, crtc) {
+ pipe = crtc->pipe;
+
[Intel-gfx] ✗ Ro.CI.BAT: failure for Add two-stage watermark programming for VLV/CHV (v4)
== Series Details == Series: Add two-stage watermark programming for VLV/CHV (v4) URL : https://patchwork.freedesktop.org/series/9067/ State : failure == Summary == Applying: drm/i915: Remove unused parameters from intel_plane_wm_parameters Applying: drm/i915: Rename skl_plane_id to wm_plane_id Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_pm.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_pm.c error: Failed to merge in the changes. Patch failed at 0002 drm/i915: Rename skl_plane_id to wm_plane_id The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915 4.5/4.6 stable backport request for CHV
Hi guys,
2016-06-06 11:32 GMT+02:00 Ville Syrjälä :
> On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> > On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrj...@linux.intel.com
> wrote:
> > > From: Ville Syrjälä
> > >
> > > Several nasty i915 regressions affecting CHV slipped through
> > > to 4.5 and 4.6.
> > >
> > > The first fix we want in 4.5 and 4.6 is
> > > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> > > It won't cherry-pick cleanly to either one, so I've included conflict
> > > free versions for both. This one fixes display FIFO underruns that can
> > > lead to the screen totally blanking out.
> >
> > Now applied, thanks.
> >
> > > The other one I'd like to have in 4.6 is
> > > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to
> .update_plane()")
> > > which avoids a totally corrupted display in some cases.
> >
> > Now applied.
> >
> > > And the third on is a bit more annoying. The regression is caused by
> > > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after
> one pass")
> > > which I though we had prevented from getting out on its own, but turns
> > > out I was wrong. It basically makes the GPU unusable, so we do need to
> > > fix it somehow. The simple solution would be to revert it in 4.6 only.
> > > The more complicated solution is to backport the proper fix, which more
> > > or less requires the following set of commits [1], which is maybe a bit
> > > too much for stable. I could try to trim it a bit perhaps, but then we
> > > start to enter the territory of untested code which I don't
> particularly
> > > like. Let me know what you think.
> > >
> > > [1]
> > > 1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> > > a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> > > 4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> > > 7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> > > 34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> > > e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> > > 71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to
> vlv_display_irq_reset()")
> > > 6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh
> display irq postinstall")
> > > 9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in
> vlv_display_irq_postinstall()")
> > > d6c698035892 ("drm/i915: Clear display interrupt before enabling when
> turning on the power well")
> > > 8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more
> logical place")
> > > 9918271efc7a ("drm/i915: Skip display irq setup if display irqs
> aren't flagged as enabled")
> > > ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> > > 93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> >
> > I think reverting that one patch for 4.6 makes more sense than adding
> > all of these patches. I'll do that if you want me to.
>
> That works for me. Thanks.
>
> --
> Ville Syrjälä
> Intel OTC
Sorry for bothering you. Will the revert make it into 4.6.3? Without it BSW
on 4.6 is not really usable.
Thanks much in advance
Peter
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[Intel-gfx] [PACTH i-g-t v4 00/13] Remove compile time depencencies on libdrm_intel.
From: Robert Foss Hey, I've been looking at the possibilty of removing the compile time depency on libdrm_intel. There are two technical solutions to this problem as far as I can see; stubs and conditional compilation. This series uses the stubbing approach. Changes since v1: - Replaced the automake flags HAVE_VC4/NOUVEAU/INTEL with HAVE_LIBDRM_XXX. - Move conditionals from Makefile.sources to Arduino.mk/Makefile.am. - Removed duplicated i915_drm.h symbols from intel_drm_stubs.h. - Replaced igt_require with igt_require_f to communicate stubs being the cause of failure. - Rename intel_drm_stubs to intel_bufmgr. - Moved intel_bufmgr to lib/stubs/drm. - Remove header inclusion changes in favor for inclusion of stubs in lib/stubs/drm using build scripts. - Rebased on trunk. Changes since v2: - Removed conditional compilation from intel_bufmgr.h. - Enable HAVE_LIBDRM_INTEL on android platforms. - Remove unnecessary whitespace. - Remove unnecessary inclusion of C files. - De-duplicated intel_bufmgr.c error string. - Changed Makefile.sources variable names to be non-automake specific Changes since v3: - Added signoff to two commits. - Changed automake if not statement. - Removed accidental space character. - Copied in new copy of intel_bufmgr.h - Improved wording of lib/stubs/drm/README. Robert Foss (13): configure.ac: Test for libdrm_intel and build for it if present. configure.ac: Harmonize HAVE_XXX flag for all drm platforms to HAVE_LIBDRM_XXX. Enable HAVE_LIBDRM_INTEL unconditionally for Android. benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel. tools/Makefile: Don't build tools that depend on libdrm_intel. tools/Makefile: Format whitespace. demos/Makefile: Don't build tools that depend on libdrm_intel. lib/stubs: Add stubs for intel_bufmgr. demos/Makefile: Replace automake specific name of listing in Makfile.sources benchmarks/Makefile: Replace automake specific name of listing in Makfile.sources tools/Makefile: Replace automake specific name of listings in Makfile.sources lib/tests/Makefile: Replace automake specific names of listings in Makefile.sources lib/Makefile: Replace automake specific names of listings in Makefile.sources Android.mk | 2 + benchmarks/Android.mk| 6 +- benchmarks/Makefile.am | 7 +- benchmarks/Makefile.sources | 15 +- configure.ac | 25 +++- demos/Android.mk | 5 +- demos/Makefile.am| 10 +- demos/Makefile.sources | 7 + lib/Android.mk | 2 +- lib/Makefile.am | 10 +- lib/Makefile.sources | 2 +- lib/stubs/drm/README | 4 + lib/stubs/drm/intel_bufmgr.c | 269 lib/stubs/drm/intel_bufmgr.h | 321 +++ lib/tests/Android.mk | 2 +- lib/tests/Makefile.am| 3 + lib/tests/Makefile.sources | 8 +- tests/Makefile.am| 4 +- tools/Android.mk | 6 + tools/Makefile.am| 7 + tools/Makefile.sources | 73 +- 21 files changed, 723 insertions(+), 65 deletions(-) create mode 100644 demos/Makefile.sources create mode 100644 lib/stubs/drm/README create mode 100644 lib/stubs/drm/intel_bufmgr.c create mode 100644 lib/stubs/drm/intel_bufmgr.h -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 01/13] configure.ac: Test for libdrm_intel and build for it if present.
From: Robert Foss Test for libdrm_intel and build for it if present. Also expose the HAVE_INTEL #define to allow code to be conditionally compiled. Signed-off-by: Robert Foss --- configure.ac | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 0405c8b..49903e4 100644 --- a/configure.ac +++ b/configure.ac @@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then fi AC_SUBST(ASSEMBLER_WARN_CFLAGS) -PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm]) +PKG_CHECK_MODULES(DRM, [libdrm]) PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10]) case "$target_cpu" in @@ -150,6 +150,21 @@ PKG_CHECK_MODULES(GLIB, glib-2.0) # - # Configuration options # - +AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel], + [Enable building of intel specific parts (default: auto)]), + [INTEL=$enableval], [INTEL=auto]) +if test "x$INTEL" = xauto; then + PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no]) +fi +if test "x$INTEL" = xyes; then + PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64]) + AC_DEFINE(HAVE_LIBDRM_INTEL, 1, [Have intel support]) +else + DRM_INTEL_CFLAGS=$(top_srcdir)/lib/stubs/drm/ + AC_SUBST([DRM_INTEL_CFLAGS]) +fi +AM_CONDITIONAL(HAVE_LIBDRM_INTEL, [test "x$INTEL" = xyes]) + # for dma-buf tests AC_ARG_ENABLE(nouveau, AS_HELP_STRING([--disable-nouveau], [Enable use of nouveau API for prime tests (default: auto)]), -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 10/13] benchmarks/Makefile: Replace automake specific name of listing in Makfile.sources
From: Robert Foss Replace the automake specific name of listings in Makefile.sources with something not automake specific. Signed-off-by: Robert Foss --- benchmarks/Android.mk | 2 +- benchmarks/Makefile.am | 2 ++ benchmarks/Makefile.sources | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/benchmarks/Android.mk b/benchmarks/Android.mk index 22ecd2f..147f5db 100644 --- a/benchmarks/Android.mk +++ b/benchmarks/Android.mk @@ -32,7 +32,7 @@ endef ## -benchmark_list := $(benchmarks_PROGRAMS) +benchmark_list := $(benchmarks_prog_list) ifeq ($(HAVE_LIBDRM_INTEL),true) benchmark_list += $(LIBDRM_INTEL_BENCHMARKS) diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am index 7400dd0..8ae3cb3 100644 --- a/benchmarks/Makefile.am +++ b/benchmarks/Makefile.am @@ -1,5 +1,7 @@ include Makefile.sources +benchmarks_PROGRAMS = $(benchmarks_prog_list) + if HAVE_LIBDRM_INTEL benchmarks_PROGRAMS += $(LIBDRM_INTEL_BENCHMARKS) endif diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources index 5804d3b..8fb342a 100644 --- a/benchmarks/Makefile.sources +++ b/benchmarks/Makefile.sources @@ -1,6 +1,6 @@ benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks -benchmarks_PROGRAMS = \ +benchmarks_prog_list = \ gem_blt \ gem_create \ gem_exec_ctx\ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 06/13] tools/Makefile: Format whitespace.
From: Robert Foss Harmonize tabs/spaces etc. Signed-off-by: Robert Foss --- tools/Makefile.sources | 57 +- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/tools/Makefile.sources b/tools/Makefile.sources index 07d8d9b..7ed5fe5 100644 --- a/tools/Makefile.sources +++ b/tools/Makefile.sources @@ -1,33 +1,34 @@ -noinst_PROGRAMS = \ - hsw_compute_wrpll \ - skl_compute_wrpll \ - skl_ddb_allocation \ +noinst_PROGRAMS = \ + hsw_compute_wrpll \ + skl_compute_wrpll \ + skl_ddb_allocation \ $(NULL) -bin_PROGRAMS = \ - igt_stats \ - intel_audio_dump\ - intel_reg \ - intel_backlight \ - intel_bios_dumper \ - intel_bios_reader \ - intel_display_crc \ - intel_display_poller\ - intel_forcewaked\ - intel_gpu_frequency \ - intel_firmware_decode \ - intel_gpu_time \ - intel_gpu_top \ - intel_gtt \ - intel_infoframes\ - intel_l3_parity \ - intel_lid \ - intel_opregion_decode \ - intel_panel_fitter \ - intel_reg_checker \ - intel_residency \ - intel_stepping \ - intel_watermark +bin_PROGRAMS = \ + igt_stats \ + intel_audio_dump\ + intel_reg \ + intel_backlight \ + intel_bios_dumper \ + intel_bios_reader \ + intel_display_crc \ + intel_display_poller\ + intel_forcewaked\ + intel_gpu_frequency \ + intel_firmware_decode \ + intel_gpu_time \ + intel_gpu_top \ + intel_gtt \ + intel_infoframes\ + intel_l3_parity \ + intel_lid \ + intel_opregion_decode \ + intel_panel_fitter \ + intel_reg_checker \ + intel_residency \ + intel_stepping \ + intel_watermark \ + $(NULL) dist_bin_SCRIPTS = intel_gpu_abrt -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 08/13] lib/stubs: Add stubs for intel_bufmgr.
From: Robert Foss
This patch provides stubs for functionality otherwise provided by intel_bufmgr.
The stubbed functions all fail with a call to igt_require_f(false,"").
Defines and enums have been copied from libdrm_intel.
Due to the stubbed tests failing with an igt_require_f() call, these stubs are
not well suited for non-tests, since tools/benchmarks/etc 'skipping'
execution is unhelpful.
Signed-off-by: Robert Foss
---
lib/Makefile.am | 6 +
lib/stubs/drm/README | 4 +
lib/stubs/drm/intel_bufmgr.c | 269
lib/stubs/drm/intel_bufmgr.h | 321 +++
4 files changed, 600 insertions(+)
create mode 100644 lib/stubs/drm/README
create mode 100644 lib/stubs/drm/intel_bufmgr.c
create mode 100644 lib/stubs/drm/intel_bufmgr.h
diff --git a/lib/Makefile.am b/lib/Makefile.am
index d2ae98d..365d7d9 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -14,6 +14,12 @@ if HAVE_LIBDRM_VC4
igt_vc4.h
endif
+if !HAVE_LIBDRM_INTEL
+libintel_tools_la_SOURCES += \
+stubs/drm/intel_bufmgr.c \
+stubs/drm/intel_bufmgr.h
+endif
+
AM_CPPFLAGS = -I$(top_srcdir)
AM_CFLAGS = $(CWARNFLAGS) $(DRM_CFLAGS) $(PCIACCESS_CFLAGS)
$(LIBUNWIND_CFLAGS) $(DEBUG_CFLAGS) \
-DIGT_SRCDIR=\""$(abs_top_srcdir)/tests"\" \
diff --git a/lib/stubs/drm/README b/lib/stubs/drm/README
new file mode 100644
index 000..79f2b5f
--- /dev/null
+++ b/lib/stubs/drm/README
@@ -0,0 +1,4 @@
+intel_bufmgr.h is a local copy of the file provided by libdrm
(intel/intel_bufmgr.h).
+
+Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into
+this directory of i-g-t.
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
new file mode 100644
index 000..bc1c196
--- /dev/null
+++ b/lib/stubs/drm/intel_bufmgr.c
@@ -0,0 +1,269 @@
+#include
+
+#include "igt_core.h"
+#include "intel_bufmgr.h"
+
+const char * const missing_support_str = "Not compiled with libdrm_intel
support\n";
+
+drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size)
+{
+ igt_require_f(false, missing_support_str);
+ return (drm_intel_bufmgr *) NULL;
+}
+
+void drm_intel_bo_unreference(drm_intel_bo *bo)
+{
+ igt_require_f(false, missing_support_str);
+}
+
+drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
+unsigned long size, unsigned int alignment)
+{
+ igt_require_f(false, missing_support_str);
+ return (drm_intel_bo *) NULL;
+}
+
+int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
+unsigned long size, const void *data)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
+ int used, unsigned int flags)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo, uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo,
+ uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t * swizzle_mode)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects,
+ int DR4, unsigned int flags)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
+ drm_intel_aub_annotation
*annotations,
+ unsigned count)
+{
+ igt_require_f(false, missing_support_str);
+}
+
+void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
+{
+ igt_require_f(false, missing_support_str);
+}
+
+int drm_intel_bo_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects, int
DR4)
+{
+ igt_require_f(false, missing_support_str);
+ return 0;
+}
+
+void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
+{
+ igt_require_f(false, missing_support_str);
+}
+
+void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
+{
+ igt_require_f(false, missing_support_str);
+}
+
+int drm_intel_bo_get_subdata(drm_intel_bo *bo
[Intel-gfx] [PACTH i-g-t v4 04/13] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel.
From: Robert Foss Use the HAS_INTEL automake flag to avoid building benchmarks that won't compile unless libdrm_intel is available in the build system. Signed-off-by: Robert Foss --- benchmarks/Android.mk | 4 benchmarks/Makefile.am | 5 - benchmarks/Makefile.sources | 13 - 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/benchmarks/Android.mk b/benchmarks/Android.mk index 207a177..22ecd2f 100644 --- a/benchmarks/Android.mk +++ b/benchmarks/Android.mk @@ -34,4 +34,8 @@ endef benchmark_list := $(benchmarks_PROGRAMS) +ifeq ($(HAVE_LIBDRM_INTEL),true) +benchmark_list += $(LIBDRM_INTEL_BENCHMARKS) +endif + $(foreach item,$(benchmark_list),$(eval $(call add_benchmark,$(item diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am index 49d2f64..7400dd0 100644 --- a/benchmarks/Makefile.am +++ b/benchmarks/Makefile.am @@ -1,6 +1,9 @@ - include Makefile.sources +if HAVE_LIBDRM_INTEL + benchmarks_PROGRAMS += $(LIBDRM_INTEL_BENCHMARKS) +endif + AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) \ $(WERROR_CFLAGS) diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources index bc4f2b5..5804d3b 100644 --- a/benchmarks/Makefile.sources +++ b/benchmarks/Makefile.sources @@ -1,10 +1,6 @@ benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks benchmarks_PROGRAMS = \ - intel_upload_blit_large \ - intel_upload_blit_large_gtt \ - intel_upload_blit_large_map \ - intel_upload_blit_small \ gem_blt \ gem_create \ gem_exec_ctx\ @@ -17,6 +13,13 @@ benchmarks_PROGRAMS =\ gem_prw \ gem_set_domain \ gem_syslatency \ - gem_userptr_benchmark \ kms_vblank \ $(NULL) + +LIBDRM_INTEL_BENCHMARKS = \ + intel_upload_blit_large \ + intel_upload_blit_large_gtt \ + intel_upload_blit_large_map \ + intel_upload_blit_small \ + gem_userptr_benchmark \ + $(NULL) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 02/13] configure.ac: Harmonize HAVE_XXX flag for all drm platforms to HAVE_LIBDRM_XXX.
From: Robert Foss Replace the automake flag HAVE_XXX for VC4/NOUVEAU with HAVE_LIBDRM_XXX in order for the flags to be more descriptive and also follow the same convention as HAVE_LIBDRM_INTEL. Signed-off-by: Robert Foss --- configure.ac | 8 lib/Makefile.am | 2 +- tests/Makefile.am | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/configure.ac b/configure.ac index 49903e4..a6210ae 100644 --- a/configure.ac +++ b/configure.ac @@ -174,9 +174,9 @@ if test "x$NOUVEAU" = xauto; then fi if test "x$NOUVEAU" = xyes; then PKG_CHECK_MODULES(DRM_NOUVEAU, [libdrm_nouveau >= 2.4.33]) - AC_DEFINE(HAVE_NOUVEAU, 1, [Have nouveau support]) + AC_DEFINE(HAVE_LIBDRM_NOUVEAU, 1, [Have nouveau support]) fi -AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" = xyes]) +AM_CONDITIONAL(HAVE_LIBDRM_NOUVEAU, [test "x$NOUVEAU" = xyes]) AC_ARG_ENABLE(vc4, AS_HELP_STRING([--disable-vc4], [Enable building of vc4 tests (default: auto)]), @@ -186,9 +186,9 @@ if test "x$VC4" = xauto; then fi if test "x$VC4" = xyes; then PKG_CHECK_MODULES(DRM_VC4, [libdrm_vc4]) - AC_DEFINE(HAVE_VC4, 1, [Have vc4 support]) + AC_DEFINE(HAVE_LIBDRM_VC4, 1, [Have vc4 support]) fi -AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) +AM_CONDITIONAL(HAVE_LIBDRM_VC4, [test "x$VC4" = xyes]) # Define a configure option for the shader debugger AC_ARG_ENABLE(shader-debugger, AS_HELP_STRING([--enable-shader-debugger], diff --git a/lib/Makefile.am b/lib/Makefile.am index d2f2e16..d2ae98d 100644 --- a/lib/Makefile.am +++ b/lib/Makefile.am @@ -8,7 +8,7 @@ include Makefile.sources noinst_LTLIBRARIES = libintel_tools.la noinst_HEADERS = check-ndebug.h -if HAVE_VC4 +if HAVE_LIBDRM_VC4 libintel_tools_la_SOURCES += \ igt_vc4.c \ igt_vc4.h diff --git a/tests/Makefile.am b/tests/Makefile.am index c2c2025..737afbe 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -1,10 +1,10 @@ include Makefile.sources -if HAVE_NOUVEAU +if HAVE_LIBDRM_NOUVEAU TESTS_progs_M += $(NOUVEAU_TESTS_M) endif -if HAVE_VC4 +if HAVE_LIBDRM_VC4 TESTS_progs_M += $(VC4_TESTS_M) endif -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 11/13] tools/Makefile: Replace automake specific name of listings in Makfile.sources
From: Robert Foss Replace the automake specific names of listings in Makefile.sources with something not automake specific. Signed-off-by: Robert Foss --- tools/Android.mk | 1 + tools/Makefile.am | 2 ++ tools/Makefile.sources | 2 +- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/Android.mk b/tools/Android.mk index 306a4b5..6cdedeb 100644 --- a/tools/Android.mk +++ b/tools/Android.mk @@ -55,6 +55,7 @@ endef $(shell mkdir -p $(TARGET_OUT_VENDOR)/$(LOCAL_TOOLS_DIR)/registers) $(shell cp $(LOCAL_PATH)/registers/* $(TARGET_OUT_VENDOR)/$(LOCAL_TOOLS_DIR)/registers) +bin_PROGRAMS := $(tools_prog_lists) skip_tools_list := \ intel_framebuffer_dump \ diff --git a/tools/Makefile.am b/tools/Makefile.am index f8ac0d8..d324321 100644 --- a/tools/Makefile.am +++ b/tools/Makefile.am @@ -1,5 +1,7 @@ include Makefile.sources +bin_PROGRAMS = $(tools_prog_lists) + if HAVE_LIBDRM_INTEL bin_PROGRAMS += $(LIBDRM_INTEL_BIN) intel_error_decode_LDFLAGS = -lz diff --git a/tools/Makefile.sources b/tools/Makefile.sources index 7ed5fe5..2bb6c8e 100644 --- a/tools/Makefile.sources +++ b/tools/Makefile.sources @@ -4,7 +4,7 @@ noinst_PROGRAMS = \ skl_ddb_allocation \ $(NULL) -bin_PROGRAMS = \ +tools_prog_lists = \ igt_stats \ intel_audio_dump\ intel_reg \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 12/13] lib/tests/Makefile: Replace automake specific names of listings in Makefile.sources
From: Robert Foss
Replace the automake specific names of listings with something that isn't
automake specific.
Signed-off-by: Robert Foss
---
lib/tests/Android.mk | 2 +-
lib/tests/Makefile.am | 3 +++
lib/tests/Makefile.sources | 8
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/lib/tests/Android.mk b/lib/tests/Android.mk
index df8e159..026f17f 100644
--- a/lib/tests/Android.mk
+++ b/lib/tests/Android.mk
@@ -37,5 +37,5 @@ IGT_LOCAL_C_INCLUDES +=
${ANDROID_BUILD_TOP}/external/PRIVATE/drm/include/drm
IGT_LOCAL_STATIC_LIBRARIES := libintel_gpu_tools
IGT_LOCAL_SHARED_LIBRARIES := libpciaccess libdrm libdrm_intel
-$(foreach item,$(check_PROGRAMS),$(eval $(call add_test,$(item
+$(foreach item,$($(check_prog_list)),$(eval $(call add_test,$(item
diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
index 582cc3e..c2fa2eb 100644
--- a/lib/tests/Makefile.am
+++ b/lib/tests/Makefile.am
@@ -1,5 +1,8 @@
include Makefile.sources
+check_PROGRAMS = $(check_prog_list)
+check_SCRIPTS = $(check_script_list)
+
AM_TESTS_ENVIRONMENT = \
top_builddir=$(top_builddir) \
top_srcdir=$(top_srcdir)
diff --git a/lib/tests/Makefile.sources b/lib/tests/Makefile.sources
index 707c445..5d8c785 100644
--- a/lib/tests/Makefile.sources
+++ b/lib/tests/Makefile.sources
@@ -1,4 +1,4 @@
-check_PROGRAMS = \
+check_prog_list = \
igt_no_exit \
igt_no_exit_list_only \
igt_fork_helper \
@@ -15,13 +15,13 @@ check_PROGRAMS = \
igt_exit_handler \
$(NULL)
-check_SCRIPTS = \
+check_script_list = \
igt_command_line.sh \
$(NULL)
TESTS = \
- $(check_PROGRAMS) \
- $(check_SCRIPTS) \
+ $(check_prog_list) \
+ $(check_script_list) \
$(NULL)
# Test that exercise specific asserts in the test framework library and are
--
2.7.4
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[Intel-gfx] [PACTH i-g-t v4 09/13] demos/Makefile: Replace automake specific name of listing in Makfile.sources
From: Robert Foss Replace the automake specific name of listings in Makefile.sources with something not automake specific. Signed-off-by: Robert Foss --- demos/Android.mk | 2 +- demos/Makefile.am | 2 ++ demos/Makefile.sources | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/demos/Android.mk b/demos/Android.mk index add2414..90d8b37 100644 --- a/demos/Android.mk +++ b/demos/Android.mk @@ -4,7 +4,7 @@ LOCAL_PATH := $(call my-dir) include $(CLEAR_VARS) -LOCAL_SRC_FILES := +LOCAL_SRC_FILES := $(demos_prog_lists) ifeq ($(HAVE_LIBDRM_INTEL),true) LOCAL_SRC_FILES += $(LIBDRM_INTEL_BIN) diff --git a/demos/Makefile.am b/demos/Makefile.am index 48eb6c2..fe0ff1f 100644 --- a/demos/Makefile.am +++ b/demos/Makefile.am @@ -1,5 +1,7 @@ include Makefile.sources +bin_PROGRAMS = $(demos_prog_list) + if HAVE_LIBDRM_INTEL bin_PROGRAMS += $(LIBDRM_INTEL_BIN) endif diff --git a/demos/Makefile.sources b/demos/Makefile.sources index 302f6d9..31f7f83 100644 --- a/demos/Makefile.sources +++ b/demos/Makefile.sources @@ -1,4 +1,4 @@ -bin_PROGRAMS = \ +demos_prog_list = \ $(NULL) HAVE_LIBDRM_INTEL_BIN =\ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 07/13] demos/Makefile: Don't build tools that depend on libdrm_intel.
From: Robert Foss Use the HAS_INTEL automake flag to avoid building tools that won't compile unless libdrm_intel is available in the build system. Signed-off-by: Robert Foss --- demos/Android.mk | 5 - demos/Makefile.am | 8 +--- demos/Makefile.sources | 7 +++ 3 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 demos/Makefile.sources diff --git a/demos/Android.mk b/demos/Android.mk index 7d06c9a..add2414 100644 --- a/demos/Android.mk +++ b/demos/Android.mk @@ -4,8 +4,11 @@ LOCAL_PATH := $(call my-dir) include $(CLEAR_VARS) -LOCAL_SRC_FILES := intel_sprite_on.c +LOCAL_SRC_FILES := +ifeq ($(HAVE_LIBDRM_INTEL),true) +LOCAL_SRC_FILES += $(LIBDRM_INTEL_BIN) +endif LOCAL_CFLAGS += -DHAVE_TERMIOS_H LOCAL_CFLAGS += -DANDROID -UNDEBUG diff --git a/demos/Makefile.am b/demos/Makefile.am index f5725f4..48eb6c2 100644 --- a/demos/Makefile.am +++ b/demos/Makefile.am @@ -1,6 +1,8 @@ -bin_PROGRAMS = \ - intel_sprite_on \ - $(NULL) +include Makefile.sources + +if HAVE_LIBDRM_INTEL + bin_PROGRAMS += $(LIBDRM_INTEL_BIN) +endif AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \ diff --git a/demos/Makefile.sources b/demos/Makefile.sources new file mode 100644 index 000..302f6d9 --- /dev/null +++ b/demos/Makefile.sources @@ -0,0 +1,7 @@ +bin_PROGRAMS = \ + $(NULL) + +HAVE_LIBDRM_INTEL_BIN =\ + intel_sprite_on \ + $(NULL) + -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 13/13] lib/Makefile: Replace automake specific names of listings in Makefile.sources
From: Robert Foss Replace the automake specific variable names for listings in Makefile.sources with something not automake specific. Signed-off-by: Robert Foss --- lib/Android.mk | 2 +- lib/Makefile.am | 2 ++ lib/Makefile.sources | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/Android.mk b/lib/Android.mk index badec1e..eb72f84 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -44,7 +44,7 @@ skip_lib_list := \ -DANDROID_HAS_CAIRO=0 endif -LOCAL_SRC_FILES := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) +LOCAL_SRC_FILES := $(filter-out $(skip_lib_list),$(lib_source_list)) include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Makefile.am b/lib/Makefile.am index 365d7d9..4c0893d 100644 --- a/lib/Makefile.am +++ b/lib/Makefile.am @@ -5,6 +5,8 @@ SUBDIRS = . tests include Makefile.sources +libintel_tools_la_SOURCES = $(lib_source_list) + noinst_LTLIBRARIES = libintel_tools.la noinst_HEADERS = check-ndebug.h diff --git a/lib/Makefile.sources b/lib/Makefile.sources index f50ff4d..3cc33f4 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -1,4 +1,4 @@ -libintel_tools_la_SOURCES =\ +lib_source_list = \ debug.h \ drmtest.c \ drmtest.h \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t v4 05/13] tools/Makefile: Don't build tools that depend on libdrm_intel.
From: Robert Foss
Use the HAS_INTEL automake flag to avoid building tools that won't
compile unless libdrm_intel is available in the build system.
Signed-off-by: Robert Foss
---
tools/Android.mk | 5 +
tools/Makefile.am | 5 +
tools/Makefile.sources | 16 ++--
3 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/tools/Android.mk b/tools/Android.mk
index 5f64184..306a4b5 100644
--- a/tools/Android.mk
+++ b/tools/Android.mk
@@ -67,6 +67,11 @@ ifneq ("${ANDROID_HAS_CAIRO}", "1")
skip_tools_list += intel_residency
endif
+ifeq ($(HAVE_LIBDRM_INTEL),true)
+bin_PROGRAMS += $(LIBDRM_INTEL_BIN)
+intel_error_decode_LDFLAGS = -lz
+endif
+
tools_list := $(filter-out $(skip_tools_list),$(bin_PROGRAMS))
$(foreach item,$(tools_list),$(eval $(call add_tool,$(item
diff --git a/tools/Makefile.am b/tools/Makefile.am
index 5f45144..f8ac0d8 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -1,5 +1,10 @@
include Makefile.sources
+if HAVE_LIBDRM_INTEL
+ bin_PROGRAMS += $(LIBDRM_INTEL_BIN)
+ intel_error_decode_LDFLAGS = -lz
+endif
+
SUBDIRS = null_state_gen registers
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 5d5958d..07d8d9b 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -13,11 +13,8 @@ bin_PROGRAMS = \
intel_bios_reader \
intel_display_crc \
intel_display_poller\
- intel_dump_decode \
- intel_error_decode \
intel_forcewaked\
intel_gpu_frequency \
- intel_framebuffer_dump \
intel_firmware_decode \
intel_gpu_time \
intel_gpu_top \
@@ -27,7 +24,6 @@ bin_PROGRAMS =\
intel_lid \
intel_opregion_decode \
intel_panel_fitter \
- intel_perf_counters \
intel_reg_checker \
intel_residency \
intel_stepping \
@@ -35,8 +31,12 @@ bin_PROGRAMS = \
dist_bin_SCRIPTS = intel_gpu_abrt
-intel_dump_decode_SOURCES =\
- intel_dump_decode.c
+LIBDRM_INTEL_BIN = \
+ intel_dump_decode \
+ intel_error_decode \
+ intel_framebuffer_dump \
+ intel_perf_counters \
+ $(NULL)
intel_reg_SOURCES =\
intel_reg.c \
@@ -44,10 +44,6 @@ intel_reg_SOURCES = \
intel_reg_spec.c\
intel_reg_spec.h
-intel_error_decode_SOURCES = \
- intel_error_decode.c
-intel_error_decode_LDFLAGS = -lz
-
intel_bios_reader_SOURCES =\
intel_bios_reader.c \
intel_bios.h
--
2.7.4
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[Intel-gfx] [PACTH i-g-t v4 03/13] Enable HAVE_LIBDRM_INTEL unconditionally for Android.
From: Robert Foss Always set HAVE_LIBDRM_INTEL to true for Android targets. Signed-off-by: Robert Foss --- Android.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Android.mk b/Android.mk index 681d114..3690fc5 100644 --- a/Android.mk +++ b/Android.mk @@ -1,2 +1,4 @@ +HAVE_LIBDRM_INTEL := true + include $(call all-named-subdir-makefiles, lib tests tools benchmarks) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC loading status check
On Thu, 23 Jun 2016, Xiang, Haihao wrote:
Hi Peter,
Besides debugfs, could you add a IOCTL to check HuC loading status?
Userspace media driver needs to advertise the features based on HuC to
user.
Thanks
Haihao
From: Alex Dai
Add debugfs entry for HuC loading status check.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_debugfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 69964c2..f5976f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void
*data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_i915_private *dev_priv = node->minor->dev-
dev_private;
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv->dev))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n",
I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -5432,6 +5463,7 @@ static const struct drm_info_list
i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
Peter Antoine (Android Graphics Driver Software Engineer)
-
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Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47___
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Re: [Intel-gfx] [PATCH] drm/i915/gen9: Add WaInPlaceDecompressionHang
On 17/06/2016 13:39, Mika Kuoppala wrote:
Add this workaround to prevent hang when in place compression
is used.
References: HSD#2135774
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fa9698fe247..d6818dcd9930 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2709,6 +2709,8 @@ struct drm_i915_cmd_table {
#define SKL_REVID_D0 0x3
#define SKL_REVID_E0 0x4
#define SKL_REVID_F0 0x5
+#define SKL_REVID_G0 0x6
+#define SKL_REVID_H0 0x7
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ff87d0b58d91..aaaba9fc2ed2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1686,6 +1686,9 @@ enum skl_disp_power_wells {
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
+#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
+#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
+
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING(1<<28)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fedd27049814..c3399be9f917 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1128,6 +1128,11 @@ static int skl_init_workarounds(struct intel_engine_cs
*engine)
/* WaDisableGafsUnitClkGating:skl */
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+ /* WaInPlaceDecompressionHang:skl */
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
+ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
indentation issue.
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
@@ -1197,6 +1202,11 @@ static int bxt_init_workarounds(struct intel_engine_cs
*engine)
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+ /* WaInPlaceDecompressionHang:bxt */
+ if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
+ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
return 0;
}
@@ -1244,6 +1254,10 @@ static int kbl_init_workarounds(struct intel_engine_cs
*engine)
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ /* WaInPlaceDecompressionHang:kbl */
+ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
with the indentation fixed, it is,
Reviewed-by: Arun Siluvery
regards
Arun
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC loading status check
Daniel,
Is this suggestion acceptable? I don't want to waste time and effort
writing code that is not going to be accepted?
Peter.
On Thu, 23 Jun 2016, Xiang, Haihao wrote:
Hi Peter,
Besides debugfs, could you add a IOCTL to check HuC loading status?
Userspace media driver needs to advertise the features based on HuC to
user.
Thanks
Haihao
From: Alex Dai
Add debugfs entry for HuC loading status check.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_debugfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 69964c2..f5976f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void
*data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_i915_private *dev_priv = node->minor->dev-
dev_private;
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv->dev))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n",
I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -5432,6 +5463,7 @@ static const struct drm_info_list
i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
Peter Antoine (Android Graphics Driver Software Engineer)
-
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Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47___
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Re: [Intel-gfx] [PATCH 3/6] drm/i915/huc: Add HuC fw loading support
On 22/06/16 09:31, Daniel Vetter wrote:
On Tue, Jun 21, 2016 at 07:11:22PM +0100, Peter Antoine wrote:
From: Alex Dai
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_dma.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 13 +-
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc.h| 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 11 +-
drivers/gpu/drm/i915/intel_huc.h| 44 ++
drivers/gpu/drm/i915/intel_huc_loader.c | 262
9 files changed, 331 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 276abf1..7384db0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -44,6 +44,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e28c0dd..a449a59 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -507,6 +507,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev);
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -532,6 +533,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
cleanup_gem:
i915_gem_fini(dev);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1563,6 +1565,7 @@ int i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
flush_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c81757..8b88227 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -54,6 +54,7 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
@@ -1749,6 +1750,7 @@ struct drm_i915_private {
struct intel_gvt gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2841,6 +2843,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_UCODE(dev)(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)(HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6abd5e5..549dd3f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5143,9 +5143,16 @@ i915_gem_init_hw(struct drm_device *dev)
intel_mocs_init_l3cc_table(dev);
/* We can't enable contexts until all firmware is loaded */
- ret = intel_guc_setup(dev);
- if (ret)
- goto out;
+ if (HAS_GUC(dev)) {
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
+
+ intel_huc_load(dev);
+ ret = intel_guc_setup(dev);
+ if (ret)
+ goto out;
+ }
/*
* Increment the next seqno by 0x100 so we have a visible break
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
b/drivers/gpu/drm/i915/i915_guc_reg.h
index cf5a65b..51533f1 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL(1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_VALUE0x8
Re: [Intel-gfx] [PATCH v2] drm/i915: Small compaction of the engine init code
On 22/06/16 17:59, Chris Wilson wrote:
On Wed, Jun 22, 2016 at 05:35:48PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Effectively removes one layer of indirection between the mask of
possible engines and the engine constructors. Instead of spelling
out in code the mapping of HAS_ to constructors, makes
more use of the recently added data driven approach by putting
engine constructor vfuncs into the table as well.
Effect is fewer lines of source and smaller binary.
At the same time simplify the error handling since engine
destructors can run on unitialized engines anyway.
Similar approach could be done for legacy submission is wanted.
v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
ENGINE_MASK and HAS_ENGINE macros.
Also removed the forward declarations by shuffling functions
around.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Reviewed-by: Chris Wilson
int intel_logical_rings_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_engine_cs *engine;
+ unsigned int i;
int ret;
- ret = logical_render_ring_init(dev);
- if (ret)
- return ret;
-
- if (HAS_BSD(dev)) {
- ret = logical_bsd_ring_init(dev);
- if (ret)
- goto cleanup_render_ring;
- }
-
- if (HAS_BLT(dev)) {
- ret = logical_blt_ring_init(dev);
- if (ret)
- goto cleanup_bsd_ring;
- }
-
- if (HAS_VEBOX(dev)) {
- ret = logical_vebox_ring_init(dev);
- if (ret)
- goto cleanup_blt_ring;
- }
-
- if (HAS_BSD2(dev)) {
- ret = logical_bsd2_ring_init(dev);
- if (ret)
- goto cleanup_vebox_ring;
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
One more thing to consider is that logical_rings[] has an unspecified
size. Either we set NUM_ENGINES there or use ARRAY_SIZE here, either way
we risk not initialising all engines we expect.
I think we need:
unsigned mask = 0;
+ if (HAS_ENGINE(dev_priv, i)) {
+ engine = logical_ring_setup(dev_priv, i);
+ ret = logical_rings[i].init(engine);
+ if (ret)
+ goto cleanup;
mask |= intel_engine_flag(engine);
+ }
}
if (WARN_ON(mask != dev_priv->info.rings_mask))
mkwrite_intel_info(dev_priv)->rings_mask = mask;
To catch any future forgotten additions without exploding.
Hm, if logical_rings does not contain all required engines it can either
crash or, if somehow it magically manages to initialize it from random
data, still pass your test.
Perhaps we just need:
BUILD_BUG_ON(ARRAY_SIZE(logical_rings) == I915_NUM_ENGINES)
?
What is this mkwrite_intel_info thing? There is a facility nowadays to
write to the rodata section? :)
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v2] drm/i915: Small compaction of the engine init code
On Thu, Jun 23, 2016 at 11:26:27AM +0100, Tvrtko Ursulin wrote:
>
> On 22/06/16 17:59, Chris Wilson wrote:
> >On Wed, Jun 22, 2016 at 05:35:48PM +0100, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Effectively removes one layer of indirection between the mask of
> >>possible engines and the engine constructors. Instead of spelling
> >>out in code the mapping of HAS_ to constructors, makes
> >>more use of the recently added data driven approach by putting
> >>engine constructor vfuncs into the table as well.
> >>
> >>Effect is fewer lines of source and smaller binary.
> >>
> >>At the same time simplify the error handling since engine
> >>destructors can run on unitialized engines anyway.
> >>
> >>Similar approach could be done for legacy submission is wanted.
> >>
> >>v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
> >> ENGINE_MASK and HAS_ENGINE macros.
> >> Also removed the forward declarations by shuffling functions
> >> around.
> >>
> >>Signed-off-by: Tvrtko Ursulin
> >>Cc: Chris Wilson
> >Reviewed-by: Chris Wilson
> >
> >> int intel_logical_rings_init(struct drm_device *dev)
> >> {
> >>struct drm_i915_private *dev_priv = dev->dev_private;
> >>+ struct intel_engine_cs *engine;
> >>+ unsigned int i;
> >>int ret;
> >>
> >>- ret = logical_render_ring_init(dev);
> >>- if (ret)
> >>- return ret;
> >>-
> >>- if (HAS_BSD(dev)) {
> >>- ret = logical_bsd_ring_init(dev);
> >>- if (ret)
> >>- goto cleanup_render_ring;
> >>- }
> >>-
> >>- if (HAS_BLT(dev)) {
> >>- ret = logical_blt_ring_init(dev);
> >>- if (ret)
> >>- goto cleanup_bsd_ring;
> >>- }
> >>-
> >>- if (HAS_VEBOX(dev)) {
> >>- ret = logical_vebox_ring_init(dev);
> >>- if (ret)
> >>- goto cleanup_blt_ring;
> >>- }
> >>-
> >>- if (HAS_BSD2(dev)) {
> >>- ret = logical_bsd2_ring_init(dev);
> >>- if (ret)
> >>- goto cleanup_vebox_ring;
> >>+ for (i = 0; i < I915_NUM_ENGINES; i++) {
> >
> >One more thing to consider is that logical_rings[] has an unspecified
> >size. Either we set NUM_ENGINES there or use ARRAY_SIZE here, either way
> >we risk not initialising all engines we expect.
> >
> >I think we need:
> >unsigned mask = 0;
> >
> >>+ if (HAS_ENGINE(dev_priv, i)) {
> >>+ engine = logical_ring_setup(dev_priv, i);
> >>+ ret = logical_rings[i].init(engine);
> >>+ if (ret)
> >>+ goto cleanup;
> > mask |= intel_engine_flag(engine);
> >>+ }
> >>}
> >
> >if (WARN_ON(mask != dev_priv->info.rings_mask))
> > mkwrite_intel_info(dev_priv)->rings_mask = mask;
> >
> >To catch any future forgotten additions without exploding.
>
> Hm, if logical_rings does not contain all required engines it can
> either crash or, if somehow it magically manages to initialize it
> from random data, still pass your test.
I was expecting you to use if (!init()) continue or something to stop
the crash and so leave holes in the mask :)
> Perhaps we just need:
>
> BUILD_BUG_ON(ARRAY_SIZE(logical_rings) == I915_NUM_ENGINES)
>
> ?
Yeah, I can't see what more information we can provide other than
pointing out the piece of forgotten code. But what if we add new engines
to a future submission mechanism that we don't need in execlists?
When the build bug fires, would be the time to consider how to fix it.
> What is this mkwrite_intel_info thing? There is a facility nowadays
> to write to the rodata section? :)
It's not rodata, intel_info is copied into dev_priv, modified, then
treated as const.
-Chris
--
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC loading status check
On 6/23/2016 11:01 AM, Peter Antoine wrote:
Daniel,
Is this suggestion acceptable? I don't want to waste time and effort
writing code that is not going to be accepted?
Peter.
Reuse I915_GETPARAM and do more-less what Chris did for i915.enable_gvt? [1]
[1]
https://cgit.freedesktop.org/drm-intel/commit/?id=7822492fd21a44eeb3568082b0ab915df7388061
On Thu, 23 Jun 2016, Xiang, Haihao wrote:
Hi Peter,
Besides debugfs, could you add a IOCTL to check HuC loading status?
Userspace media driver needs to advertise the features based on HuC to
user.
Thanks
Haihao
From: Alex Dai
Add debugfs entry for HuC loading status check.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_debugfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 69964c2..f5976f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void
*data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+struct drm_info_node *node = m->private;
+struct drm_i915_private *dev_priv = node->minor->dev-
dev_private;
+struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+if (!HAS_HUC_UCODE(dev_priv->dev))
+return 0;
+
+seq_puts(m, "HuC firmware status:\n");
+seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+seq_printf(m, "\tfetch: %s\n",
+intel_uc_fw_status_repr(huc_fw->fetch_status));
+seq_printf(m, "\tload: %s\n",
+intel_uc_fw_status_repr(huc_fw->load_status));
+seq_printf(m, "\tversion wanted: %d.%d\n",
+huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+seq_printf(m, "\tversion found: %d.%d\n",
+huc_fw->major_ver_found, huc_fw->minor_ver_found);
+seq_printf(m, "\theader: offset is %d; size = %d\n",
+huc_fw->header_offset, huc_fw->header_size);
+seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+huc_fw->ucode_offset, huc_fw->ucode_size);
+seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+huc_fw->rsa_offset, huc_fw->rsa_size);
+
+seq_printf(m, "\nHuC status 0x%08x:\n",
I915_READ(HUC_STATUS2));
+
+return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -5432,6 +5463,7 @@ static const struct drm_info_list
i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
Peter Antoine (Android Graphics Driver Software Engineer)
-
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47
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[Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
From: Tvrtko Ursulin
Effectively removes one layer of indirection between the mask of
possible engines and the engine constructors. Instead of spelling
out in code the mapping of HAS_ to constructors, makes
more use of the recently added data driven approach by putting
engine constructor vfuncs into the table as well.
Effect is fewer lines of source and smaller binary.
At the same time simplify the error handling since engine
destructors can run on unitialized engines anyway.
Similar approach could be done for legacy submission is wanted.
v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
ENGINE_MASK and HAS_ENGINE macros.
Also removed the forward declarations by shuffling functions
around.
v3: Warn when logical_rings table does not contain enough data
and disable the engines which could not be initialized.
(Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 27 +++--
drivers/gpu/drm/i915/intel_lrc.c | 256 +--
2 files changed, 129 insertions(+), 154 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74d0a61de75a..6d96b14b53c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2759,17 +2759,22 @@ struct drm_i915_cmd_table {
#define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
#define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
-#define RENDER_RING(1ring_mask & BSD2_RING)
-#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
+#define ENGINE_MASK(id)BIT(id)
+#define RENDER_RINGENGINE_MASK(RCS)
+#define BSD_RING ENGINE_MASK(VCS)
+#define BLT_RING ENGINE_MASK(BCS)
+#define VEBOX_RING ENGINE_MASK(VECS)
+#define BSD2_RING ENGINE_MASK(VCS2)
+#define ALL_ENGINES(~0)
+
+#define HAS_ENGINE(dev_priv, id) \
+ (INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
+
+#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
+#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
+#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
+#define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
+
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index debed011a958..c80aa22d3367 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2016,12 +2016,90 @@ lrc_setup_hws(struct intel_engine_cs *engine,
return 0;
}
+static int
+logical_ring_init(struct intel_engine_cs *engine)
+{
+ struct i915_gem_context *dctx = engine->i915->kernel_context;
+ int ret;
+
+ ret = i915_cmd_parser_init_ring(engine);
+ if (ret)
+ goto error;
+
+ ret = execlists_context_deferred_alloc(dctx, engine);
+ if (ret)
+ goto error;
+
+ /* As this is the default context, always pin it */
+ ret = intel_lr_context_pin(dctx, engine);
+ if (ret) {
+ DRM_ERROR("Failed to pin context for %s: %d\n",
+ engine->name, ret);
+ goto error;
+ }
+
+ /* And setup the hardware status page. */
+ ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
+ if (ret) {
+ DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
+ goto error;
+ }
+
+ return 0;
+
+error:
+ intel_logical_ring_cleanup(engine);
+ return ret;
+}
+
+static int logical_render_ring_init(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+ int ret;
+
+ if (HAS_L3_DPF(dev_priv))
+ engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+
+ /* Override some for render ring. */
+ if (INTEL_GEN(dev_priv) >= 9)
+ engine->init_hw = gen9_init_render_ring;
+ else
+ engine->init_hw = gen8_init_render_ring;
+ engine->init_context = gen8_init_rcs_context;
+ engine->cleanup = intel_fini_pipe_control;
+ engine->emit_flush = gen8_emit_flush_render;
+ engine->emit_request = gen8_emit_request_render;
+
+ ret = intel_init_pipe_control(engine);
+ if (ret)
+ return ret;
+
+ ret = intel_init_workaround_bb(engine);
+ if (ret) {
+ /*
+* We continue even if we fail to initialize WA batch
+* because we only expect rare glitches but nothing
+* critical to prevent us from using GPU
+*/
+ DRM_ERROR("WA batch buffer initialization failed: %d\
Re: [Intel-gfx] [PATCH i-g-t] assembler/: Fix lex warnings for %empty and %nonassoc.
Thanks for the tip. I haven't noticed any differences in the generated output, so I've applied it. On Thu, May 19, 2016 at 03:07:46PM +0100, Damien Lespiau wrote: > On Thu, May 19, 2016 at 07:02:40AM -0700, Ben Widawsky wrote: > > On Thu, May 19, 2016 at 12:28:10PM +0100, Damien Lespiau wrote: > > > On Mon, May 16, 2016 at 01:39:10PM +0300, Marius Vlad wrote: > > > > Signed-off-by: Marius Vlad > > > > --- > > > > assembler/gram.y | 74 > > > > > > > > 1 file changed, 37 insertions(+), 37 deletions(-) > > > > > > The only way to test the change is to regenerate the vaapi shaders from > > > source and check for differences in the generated opcodes. > > > > Didn't we have something like this in the test/ directory? > > We have just a few unmaintained tests that don't pass (or do they?) and > they barely scratch the surface of what would be needed to decent > coverage. They do pass, but wasn't sure if they are sufficient. > > vaapi-driver is a much better test suite. > > -- > Damien signature.asc Description: Digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
On Thu, Jun 23, 2016 at 12:12:29PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Effectively removes one layer of indirection between the mask of
> possible engines and the engine constructors. Instead of spelling
> out in code the mapping of HAS_ to constructors, makes
> more use of the recently added data driven approach by putting
> engine constructor vfuncs into the table as well.
>
> Effect is fewer lines of source and smaller binary.
>
> At the same time simplify the error handling since engine
> destructors can run on unitialized engines anyway.
>
> Similar approach could be done for legacy submission is wanted.
>
> v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
> ENGINE_MASK and HAS_ENGINE macros.
> Also removed the forward declarations by shuffling functions
> around.
>
> v3: Warn when logical_rings table does not contain enough data
> and disable the engines which could not be initialized.
> (Chris Wilson)
I was happy with the BUILD_BUG suggestion :)
> + for (i = 0;
> + i < I915_NUM_ENGINES && i < ARRAY_SIZE(logical_rings); i++) {
HAS_ENGINE() == false if i >= I915_NUM_ENGINES
-Chris
--
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Re: [Intel-gfx] Bad flicker on skylake HQD due to code in the 4.7 merge window
On Tue, 2016-06-21 at 17:00 -0400, James Bottomley wrote: > On Tue, 2016-06-21 at 18:44 +0300, Ville Syrjälä wrote: > > On Tue, Jun 21, 2016 at 09:53:15AM -0400, James Bottomley wrote: > > > On Mon, 2016-06-20 at 11:03 +0300, Jani Nikula wrote: > > > > Cc: Ville > > > > > > > > On Mon, 20 Jun 2016, James Bottomley < > > > > james.bottom...@hansenpartnership.com> wrote: > > > > > OK, my candidate bad commit is this one: > > > > > > > > > > commit a05628195a0d9f3173dd9aa76f482aef692e46ee > > > > > Author: Ville Syrjälä > > > > > Date: Mon Apr 11 10:23:51 2016 +0300 > > > > > > > > > > drm/i915: Get panel_type from OpRegion panel details > > > > > > > > > > After being more careful about waiting to identify flicker, > > > > > this one seems to be the one the bisect finds. I'm now > > > > > running v4.7-rc3 with this one reverted and am currently > > > > > seeing no flicker problems. It is, however, early days > > > > > because the flicker can hide for long periods, so I 'll wait > > > > > until Monday evening and a few reboots before declaring > > > > > victory. > > > > > > > > If that turns out to be the bad commit, it doesn't really > > > > surprise me, and that in itself is depressing. > > > > > > As far as I can tell, after running for a day with this reverted, > > > this is the problem. The flicker hasn't appeared with it > > > reverted. It's pretty noticeable with this commit included. > > > > Hmm. The only difference I can see is low vs. normal vswing. Panel > > 0 has low, panel 2 has normal. So either the VBT or opregion is > > telling utter lies, or there's some other bug in our low vswing > > support. > > > > To confirm it's really a vswing issue, you should be able to run > > with i915.edp_vswing=2 without flickers on the broken kernel. > > Preliminary boot indicates no flicker with the bad commit included > and this option, but I'll have to run for quite a bit longer to > verify, since it can sometimes be elusive. Two days of runtime seems to confirm this is the problem (still no flicker issues). James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/atomic: Make drm_atomic_legacy_backoff reset crtc->acquire_ctx
Atomic updates may acquire more state than initially locked through
drm_modeset_lock_crtc, running with heavy stress can cause a
WARN_ON(crtc->acquire_ctx) in drm_modeset_lock_crtc:
[ 601.491296] [ cut here ]
[ 601.491366] WARNING: CPU: 0 PID: 2411 at
drivers/gpu/drm/drm_modeset_lock.c:191 drm_modeset_lock_crtc+0xeb/0xf0 [drm]
[ 601.491369] Modules linked in: drm i915 drm_kms_helper
[ 601.491414] CPU: 0 PID: 2411 Comm: kms_cursor_lega Tainted: G U
4.7.0-rc4-patser+ #4798
[ 601.491417] Hardware name: Intel Corporation Skylake Client
[ 601.491420] 88044d153c98 812ead28
[ 601.491425] 88044d153cd8 810868e6
00bf58058030
[ 601.491431] 880088b415e8 880458058030 88008a271548
88008a271568
[ 601.491436] Call Trace:
[ 601.491443] [] dump_stack+0x4d/0x65
[ 601.491447] [] __warn+0xc6/0xe0
[ 601.491452] [] warn_slowpath_null+0x18/0x20
[ 601.491472] [] drm_modeset_lock_crtc+0xeb/0xf0 [drm]
[ 601.491491] [] drm_mode_cursor_common+0x66/0x180 [drm]
[ 601.491509] [] drm_mode_cursor_ioctl+0x3c/0x40 [drm]
[ 601.491524] [] drm_ioctl+0x14d/0x530 [drm]
[ 601.491540] [] ? drm_mode_setcrtc+0x520/0x520 [drm]
[ 601.491545] [] ? handle_mm_fault+0x106b/0x1430
[ 601.491550] [] ? stop_one_cpu+0x61/0x70
[ 601.491556] [] do_vfs_ioctl+0x8d/0x570
[ 601.491560] [] ? security_file_ioctl+0x3e/0x60
[ 601.491565] [] SyS_ioctl+0x74/0x80
[ 601.491571] [] ? posix_get_monotonic_raw+0xc/0x10
[ 601.491576] [] entry_SYSCALL_64_fastpath+0x13/0x8f
[ 601.491581] ---[ end trace 56f3d3d85f000d00 ]---
For good measure, test mode_config.acquire_ctx too, although this should
never happen.
Testcase: kms_cursor_legacy
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index d99ab2f6663f..3cee084e9d28 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1299,14 +1299,39 @@ EXPORT_SYMBOL(drm_atomic_add_affected_planes);
*/
void drm_atomic_legacy_backoff(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
+ unsigned crtc_mask = 0;
+ struct drm_crtc *crtc;
int ret;
+ bool global = false;
+
+ drm_for_each_crtc(crtc, dev) {
+ if (crtc->acquire_ctx != state->acquire_ctx)
+ continue;
+
+ crtc_mask |= drm_crtc_mask(crtc);
+ crtc->acquire_ctx = NULL;
+ }
+
+ if (WARN_ON(dev->mode_config.acquire_ctx == state->acquire_ctx)) {
+ global = true;
+
+ dev->mode_config.acquire_ctx = NULL;
+ }
retry:
drm_modeset_backoff(state->acquire_ctx);
- ret = drm_modeset_lock_all_ctx(state->dev, state->acquire_ctx);
+ ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
if (ret)
goto retry;
+
+ drm_for_each_crtc(crtc, dev)
+ if (drm_crtc_mask(crtc) & crtc_mask)
+ crtc->acquire_ctx = state->acquire_ctx;
+
+ if (global)
+ dev->mode_config.acquire_ctx = state->acquire_ctx;
}
EXPORT_SYMBOL(drm_atomic_legacy_backoff);
--
2.5.5
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Re: [Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
On 23/06/16 12:25, Chris Wilson wrote:
On Thu, Jun 23, 2016 at 12:12:29PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Effectively removes one layer of indirection between the mask of
possible engines and the engine constructors. Instead of spelling
out in code the mapping of HAS_ to constructors, makes
more use of the recently added data driven approach by putting
engine constructor vfuncs into the table as well.
Effect is fewer lines of source and smaller binary.
At the same time simplify the error handling since engine
destructors can run on unitialized engines anyway.
Similar approach could be done for legacy submission is wanted.
v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
ENGINE_MASK and HAS_ENGINE macros.
Also removed the forward declarations by shuffling functions
around.
v3: Warn when logical_rings table does not contain enough data
and disable the engines which could not be initialized.
(Chris Wilson)
I was happy with the BUILD_BUG suggestion :)
I've changed my mind later. :)
+ for (i = 0;
+ i < I915_NUM_ENGINES && i < ARRAY_SIZE(logical_rings); i++) {
HAS_ENGINE() == false if i >= I915_NUM_ENGINES
Don't follow. :) Why is v3 not good enough?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
On Thu, Jun 23, 2016 at 12:46:42PM +0100, Tvrtko Ursulin wrote:
>
> On 23/06/16 12:25, Chris Wilson wrote:
> >On Thu, Jun 23, 2016 at 12:12:29PM +0100, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Effectively removes one layer of indirection between the mask of
> >>possible engines and the engine constructors. Instead of spelling
> >>out in code the mapping of HAS_ to constructors, makes
> >>more use of the recently added data driven approach by putting
> >>engine constructor vfuncs into the table as well.
> >>
> >>Effect is fewer lines of source and smaller binary.
> >>
> >>At the same time simplify the error handling since engine
> >>destructors can run on unitialized engines anyway.
> >>
> >>Similar approach could be done for legacy submission is wanted.
> >>
> >>v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
> >> ENGINE_MASK and HAS_ENGINE macros.
> >> Also removed the forward declarations by shuffling functions
> >> around.
> >>
> >>v3: Warn when logical_rings table does not contain enough data
> >> and disable the engines which could not be initialized.
> >> (Chris Wilson)
> >
> >I was happy with the BUILD_BUG suggestion :)
>
> I've changed my mind later. :)
>
> >>+ for (i = 0;
> >>+ i < I915_NUM_ENGINES && i < ARRAY_SIZE(logical_rings); i++) {
> >
> >HAS_ENGINE() == false if i >= I915_NUM_ENGINES
>
> Don't follow. :) Why is v3 not good enough?
Both (all three) is overkill.
I feel like HAS_ENGINE() should encompass i < I915_NUM_ENGINES quite
succinctly. For belt and braces,
WARN_ON(dev_priv->intel_info.rings_mask & -(1 << I915_NUM_ENGINES)));
for (i = 0; i < ARRAY_SIZE(); i++) {
if (!HAS_ENGINE(i))
continue;
if (!logical_rings[i].init)
continue;
ret = logical_rings[i].init(logical_rings_engine(i));
if (ret)
goto err;
mask |= ENGINE_MASK(i);
}
WARN_ON(mask != dev_priv->intel_info.rings_mask) ...
?
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH i-g-t 1/6] tests/kms_flip: Print timestamps in a consistent form
On Wed, Jun 22, 2016 at 09:33:13PM +0100, Chris Wilson wrote: > On Wed, Jun 22, 2016 at 04:26:01PM +0300, Ville Syrjälä wrote: > > On Wed, Jun 22, 2016 at 02:11:51PM +0100, Chris Wilson wrote: > > > On Wed, Jun 22, 2016 at 04:01:12PM +0300, Ville Syrjälä wrote: > > > > On Wed, Jun 22, 2016 at 01:34:16PM +0100, Chris Wilson wrote: > > > > > On Tue, Jun 21, 2016 at 08:25:27PM +0300, > > > > > ville.syrj...@linux.intel.com wrote: > > > > > > From: Ville Syrjälä > > > > > > > > > > Would it be possible for writing timing requirement tests for > > > > > individual > > > > > updates of planes on the same CRTC? E.g. making sure that legacy > > > > > cursor > > > > > doesn't block pageflips and vice versa. Also extending that to > > > > > independent updates of primary vs sprite planes? > > > > > > > > I guess all that should be doable. > > > > > > > > I was also thinking we should at least have some kind of basic > > > > performance benchmark for atomic ioctls. Eg. do TEST_ONLY ioctls > > > > with different sets of properties and make sure we don't totally > > > > suck. > > > > > > Would it fit into kms_flip? > > > > Possibly, but I wouldn't. Maybe if we would try to split up the main > > test function into different functions for different tests instead of > > continuing with the flag galore. But still I'd probably prefer a > > separate test so the the entire thing easier to read. > > > > > > > > For starters, I'm going to try and replicate the current cursor bogosity > > > inside ./kms_cursor_legacy. Biggest challenge is defining pass/fail > > > criteria. :| > > > > What do we need? > > - make sure >1 cursor updates can be performed per frame w/o > > errors/blocking. > > - issue >1 one cursor updates, followed by a flip that should not > > error/block > > - issue flip, followed by >1 cursor updates that should not error/block > > I've put together an initial sketch to try and load as many cursor > updates before the the pageflip as possible to try and detect if (a) the > cursor updates are then synchronous with each other and (b) if the > pageflip serialises with the cursor updates. That's enough to catch the > current bug (and I think the previous cursor bug). > > > Maybe crc check at the end to make sure it's really the last submitted > > thing that got latched. And maybe we should change the crc frame counter > > to use the sw counter so we could check that update happens on the frame > > we expected? > > In theory, that should be caught by kms_cursor_crc, right? Probably > worth a look to see why we don't have a representative test case in BAT > (or if we do, why it was ineffective). I don't think that one tries multiple updates per frame. It might even do one update every n frames on account of starting/stopping the crc capture around every check, which implies a few extra vblank waits IIRC. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 0/8] Add two-stage watermark programming for VLV/CHV (v5)
From: root In addition to calculating final watermarks, we also pre-calculate a set of intermediate watermark values at atomic check time. These intermediate watermarks are a combination of the watermarks for the old state and the new state; they should satisfy the requirements of both states which means they can be programmed immediately when we commit the atomic state (without waiting for a vblank). Once the vblank does happen, we can then re-program watermarks to the more optimal final value. The DSPARB Display Arbitration Control register is double buffered. The FIFO repartitioning happens atomically with plane updates but how the register double buffering works isn't clear at the moment. It needs to be figured out to fix the watermark updates. v2: Split the first patch of v1 into the following patches - Remove unused parameters from intel_plane_wm_parameters. - Rename skl_plane_id to wm_plane_id. - Move fifo_size from intel_plane_wm_parameters to vlv_wm_state. v3: Split the 3rd patch of v2 into the following two patches - Move fifo_size from intel_plane_wm_parameters to vlv_wm_state - Change to use intel_crtc_state instead of base CRTC object - The patch headlines are also changed to fit the requirement. v4: - Split the 3rd patch of v3 "Move fifo_size from intel_plane_wm_parameters to vlv_wm_state" to add a new one "return EINVAL when computed watermark exceeds system limitation" - Add a new patch "Move active watermarks into intel_crtc->wm.active.vlv" to be consistent with what we do on other platforms - Change the patch "Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark" to use macro drm_atomic_crtc_state_for_each_plane_state to simplify the code - Change the patch "Add optimal field in intel_crtc_wm_state" to use mutex in vlv_update_wm to make assigning currently active wm_state and merging multiple wm_state become one atomic operation v5: recreated the patches because v4 patches were created with drm-intel kernel 4.7.0-rc1+ and can't be applied on the current version 4.7.0-rc4+ Signed-off-by: Maarten Lankhorst Signed-off-by: Chi Ding Maarten Lankhorst (8): drm/i915: Remove unused parameters from intel_plane_wm_parameters drm/i915: Rename skl_wm_plane_id to wm_plane_id drm/i915/vlv: Move fifo_size from intel_plane_wm_parameters to vlv_wm_state drm/i915/vlv: return EINVAL when computed watermark exceeds system limitation drm/i915/vlv: Change to use intel_crtc_state instead of base CRTC object drm/i915/vlv: Add optimal field in intel_crtc_wm_state drm/i915/vlv: Move active watermarks into intel_crtc->wm.active.vlv drm/i915/vlv: Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark drivers/gpu/drm/i915/intel_display.c | 8 +- drivers/gpu/drm/i915/intel_drv.h | 52 ++ drivers/gpu/drm/i915/intel_pm.c | 326 +++ 3 files changed, 232 insertions(+), 154 deletions(-) -- 1.8.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 4/8] drm/i915/vlv: return EINVAL when computed watermark exceeds system limitation
From: Maarten Lankhorst
When computing normal watermarks in vlv_compute_wm(), if the value
is bigger than system limitation, return EINVAL
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e239af..3fb896a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1152,9 +1152,14 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
int wm = vlv_compute_wm_level(plane, crtc, state,
level);
int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR
? 63 : 511;
- /* hack */
- if (WARN_ON(level == 0 && wm > max_wm))
- wm = max_wm;
+ if (level == 0 && wm > max_wm) {
+ DRM_DEBUG_KMS("Requested display configuration "
+ "exceeds system watermark limitations\n");
+ DRM_DEBUG_KMS("Plane %d.%d: blocks required =
%u/%u\n",
+ crtc->pipe,
+ drm_plane_index(&plane->base), wm,
max_wm);
+ return -EINVAL;
+ }
if (wm > wm_state->fifo_size[wm_plane_id(plane)])
break;
--
1.8.0.1
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[Intel-gfx] [RFC 3/8] drm/i915/vlv: Move fifo_size from intel_plane_wm_parameters to vlv_wm_state
From: Maarten Lankhorst
This commit saves watermark for each plane in vlv_wm_state to prepare
for two-level watermark because we'll compute and save intermediate and
optimal watermark and fifo size for each plane.
v2:
- remove redundant debug statements in vlv_pipe_set_fifo_size()
- reverse passing vlv_wm_state by parameter because it's unrelated to the
patch
- reverse the change of returning EINVAL when wm > max_wm in vlv_compute_wm
because it's unrelated to the patch
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 12 +-
drivers/gpu/drm/i915/intel_pm.c | 90
2 files changed, 46 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e6dea69..ae3e73e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -623,6 +623,7 @@ struct intel_crtc_state {
struct vlv_wm_state {
struct vlv_pipe_wm wm[3];
struct vlv_sr_wm sr[3];
+ uint16_t fifo_size[I915_MAX_PLANES];
uint8_t num_active_planes;
uint8_t num_levels;
uint8_t level;
@@ -695,10 +696,6 @@ struct intel_crtc {
struct vlv_wm_state wm_state;
};
-struct intel_plane_wm_parameters {
- uint16_t fifo_size;
-};
-
struct intel_plane {
struct drm_plane base;
int plane;
@@ -707,13 +704,6 @@ struct intel_plane {
int max_downscale;
uint32_t frontbuffer_bit;
- /* Since we need to change the watermarks before/after
-* enabling/disabling the planes, we need to store the parameters here
-* as the other pieces of the struct may not reflect the values we want
-* for the watermark calculations. Currently only Haswell uses this.
-*/
- struct intel_plane_wm_parameters wm;
-
/*
* NOTE: Do not place new plane state fields here (e.g., when adding
* new plane properties). New runtime state should now be placed in
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29820e2..3e239af 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1010,12 +1010,14 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
static void vlv_compute_fifo(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
unsigned int total_rate = 0;
const int fifo_size = 512 - 1;
int fifo_extra, fifo_left = fifo_size;
+ int rate[I915_MAX_PLANES] = {};
+ int i;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct intel_plane_state *state =
@@ -1026,49 +1028,46 @@ static void vlv_compute_fifo(struct intel_crtc *crtc)
if (state->visible) {
wm_state->num_active_planes++;
- total_rate +=
drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ rate[wm_plane_id(plane)] =
+ drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ total_rate += rate[wm_plane_id(plane)];
}
}
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct intel_plane_state *state =
- to_intel_plane_state(plane->base.state);
- unsigned int rate;
-
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
- plane->wm.fifo_size = 63;
+ for (i = 0; i < I915_MAX_PLANES; i++) {
+ if (i == PLANE_CURSOR) {
+ wm_state->fifo_size[i] = 63;
continue;
}
- if (!state->visible) {
- plane->wm.fifo_size = 0;
+ if (!rate[i]) {
+ wm_state->fifo_size[i] = 0;
continue;
}
- rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- plane->wm.fifo_size = fifo_size * rate / total_rate;
- fifo_left -= plane->wm.fifo_size;
+ wm_state->fifo_size[i] = fifo_size * rate[i] / total_rate;
+ fifo_left -= wm_state->fifo_size[i];
}
fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
/* spread the remainder evenly */
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for (i = 0; i < I915_MAX_PLANES; i++) {
int plane_extra;
if (fifo_left == 0)
break;
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ if (i == PLANE_CURSOR)
continue;
/* give it all to the first plane if none are active */
- if (plane->wm.fifo_size =
[Intel-gfx] [RFC 1/8] drm/i915: Remove unused parameters from intel_plane_wm_parameters
From: Maarten Lankhorst
Everything except fifo_size is unused and therefore removed
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1f82dcc..e6dea69 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -696,21 +696,6 @@ struct intel_crtc {
};
struct intel_plane_wm_parameters {
- uint32_t horiz_pixels;
- uint32_t vert_pixels;
- /*
-* For packed pixel formats:
-* bytes_per_pixel - holds bytes per pixel
-* For planar pixel formats:
-* bytes_per_pixel - holds bytes per pixel for uv-plane
-* y_bytes_per_pixel - holds bytes per pixel for y-plane
-*/
- uint8_t bytes_per_pixel;
- uint8_t y_bytes_per_pixel;
- bool enabled;
- bool scaled;
- u64 tiling;
- unsigned int rotation;
uint16_t fifo_size;
};
--
1.8.0.1
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[Intel-gfx] [RFC 7/8] drm/i915/vlv: Move active watermarks into intel_crtc->wm.active.vlv
From: Maarten Lankhorst
Previously the active watermarks is saved in intel_crtc->wm_state
This commit adds a new field "vlv" into intel_crtc->wm.active and save
the active watermarks in it to be consistent with what we do on other
platforms.
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ac0124c..8e77adb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -680,6 +680,7 @@ struct intel_crtc {
union {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
+ struct vlv_wm_state vlv;
} active;
/* allow CxSR on this pipe */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04265ea..cc43c1e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1229,7 +1229,7 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
- const struct vlv_wm_state *wm_state = &crtc->wm_state;
+ const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
WARN_ON(wm_state->fifo_size[PLANE_CURSOR] != 63);
@@ -1311,7 +1311,7 @@ static void vlv_merge_wm(struct drm_device *dev,
wm->cxsr = true;
for_each_intel_crtc(dev, crtc) {
- const struct vlv_wm_state *wm_state = &crtc->wm_state;
+ const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
if (!crtc->active)
continue;
@@ -1330,7 +1330,7 @@ static void vlv_merge_wm(struct drm_device *dev,
wm->level = VLV_WM_LEVEL_PM2;
for_each_intel_crtc(dev, crtc) {
- struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
enum pipe pipe = crtc->pipe;
if (!crtc->active)
@@ -1357,7 +1357,7 @@ static void vlv_update_wm(struct drm_crtc *crtc)
vlv_compute_wm(intel_crtc->config);
mutex_lock(&dev_priv->wm.wm_mutex);
- intel_crtc->wm_state = intel_crtc->config->wm.vlv.optimal;
+ intel_crtc->wm.active.vlv = intel_crtc->config->wm.vlv.optimal;
vlv_merge_wm(dev, &wm);
mutex_unlock(&dev_priv->wm.wm_mutex);
@@ -4372,7 +4372,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
int i = wm_plane_id(plane);
crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, plane->pipe));
- wm_state = &crtc->wm_state;
+ wm_state = &crtc->wm.active.vlv;
switch (plane->base.type) {
case DRM_PLANE_TYPE_CURSOR:
@@ -4426,7 +4426,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
for_each_intel_crtc(dev, crtc) {
pipe = crtc->pipe;
to_intel_crtc_state(crtc->base.state)->wm.vlv.optimal
- = crtc->wm_state;
+ = crtc->wm.active.vlv;
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d,
cursor=%d, sprite0=%d, sprite1=%d\n",
pipe_name(pipe), wm->pipe[pipe].primary,
wm->pipe[pipe].cursor,
--
1.8.0.1
___
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[Intel-gfx] [RFC 6/8] drm/i915/vlv: Add optimal field in intel_crtc_wm_state
From: Maarten Lankhorst
For two-stage watermark programming, we need to calculate optimal
watermark which is set after vblank and intermediate watermark which
can be set without waiting for vblank.
This commit adds optimal watermark field and changes the code to use it
in vlv_compute_wm(), vlv_update_wm() and vlv_wm_get_hw_state()
v2:
- use mutex in vlv_update_wm to make assigning currently active wm_state
and merging multiple wm_state become one atomic operation
- change vlv_compute_fifo and vlv_invert_wms to pass wm_state as parameter
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_drv.h | 23 ++-
drivers/gpu/drm/i915/intel_pm.c | 24
2 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ae3e73e..ac0124c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -413,6 +413,16 @@ struct skl_pipe_wm {
uint32_t linetime;
};
+struct vlv_wm_state {
+ struct vlv_pipe_wm wm[3];
+ struct vlv_sr_wm sr[3];
+ uint16_t fifo_size[I915_MAX_PLANES];
+ uint8_t num_active_planes;
+ uint8_t num_levels;
+ uint8_t level;
+ bool cxsr;
+};
+
struct intel_crtc_wm_state {
union {
struct {
@@ -433,6 +443,10 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ struct vlv_wm_state optimal;
+ } vlv;
+
+ struct {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
@@ -620,15 +634,6 @@ struct intel_crtc_state {
uint32_t gamma_mode;
};
-struct vlv_wm_state {
- struct vlv_pipe_wm wm[3];
- struct vlv_sr_wm sr[3];
- uint16_t fifo_size[I915_MAX_PLANES];
- uint8_t num_active_planes;
- uint8_t num_levels;
- uint8_t level;
- bool cxsr;
-};
struct intel_crtc {
struct drm_crtc base;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 963b919..04265ea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1008,10 +1008,10 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return min_t(int, wm, USHRT_MAX);
}
-static void vlv_compute_fifo(struct intel_crtc_state *cstate)
+static void vlv_compute_fifo(struct intel_crtc_state *cstate,
+ struct vlv_wm_state *wm_state)
{
struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
- struct vlv_wm_state *wm_state = &crtc->wm_state;
struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
unsigned int total_rate = 0;
@@ -1075,9 +1075,9 @@ static void vlv_compute_fifo(struct intel_crtc_state
*cstate)
WARN_ON(fifo_left != 0);
}
-static void vlv_invert_wms(struct intel_crtc *crtc)
+static void vlv_invert_wms(struct intel_crtc *crtc,
+ struct vlv_wm_state *wm_state)
{
- struct vlv_wm_state *wm_state = &crtc->wm_state;
int level;
for (level = 0; level < wm_state->num_levels; level++) {
@@ -1118,7 +1118,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
{
struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
- struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct vlv_wm_state *wm_state = &cstate->wm.vlv.optimal;
struct intel_plane *plane;
int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
int level;
@@ -1130,7 +1130,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
wm_state->num_active_planes = 0;
- vlv_compute_fifo(cstate);
+ vlv_compute_fifo(cstate, wm_state);
if (wm_state->num_active_planes != 1)
wm_state->cxsr = false;
@@ -1216,7 +1216,7 @@ static int vlv_compute_wm(struct intel_crtc_state *cstate)
memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
}
- vlv_invert_wms(crtc);
+ vlv_invert_wms(crtc, wm_state);
return 0;
}
@@ -1356,7 +1356,10 @@ static void vlv_update_wm(struct drm_crtc *crtc)
struct vlv_wm_values wm = {};
vlv_compute_wm(intel_crtc->config);
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ intel_crtc->wm_state = intel_crtc->config->wm.vlv.optimal;
vlv_merge_wm(dev, &wm);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
/* FIXME should be part of crtc atomic commit */
@@ -4420,10 +4423,15 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
- for_each_pipe(dev_priv, pipe)
+ for_each_intel_crtc(dev, crtc) {
+ pipe = crtc->pipe;
+
[Intel-gfx] [RFC 5/8] drm/i915/vlv: Change to use intel_crtc_state instead of base CRTC object
From: Maarten Lankhorst
This commit changs some functions to operate on intel_crtc_state rather
than the base CRTC objects in order to transit to atomic. The reason we
want to do this is to allow future patches to move the computation steps
into the atomic 'check' phase where they'll be operating on in-flight CRTC
states rather than already-committed states.
v2: make the change for vlv_compute_wm_level() which is forgotten in v1
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fb896a..963b919 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -972,7 +972,7 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
}
static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
-struct intel_crtc *crtc,
+ const struct intel_crtc_state *cstate,
const struct intel_plane_state *state,
int level)
{
@@ -986,9 +986,9 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return 0;
cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- clock = crtc->config->base.adjusted_mode.crtc_clock;
- htotal = crtc->config->base.adjusted_mode.crtc_htotal;
- width = crtc->config->pipe_src_w;
+ clock = cstate->base.adjusted_mode.crtc_clock;
+ htotal = cstate->base.adjusted_mode.crtc_htotal;
+ width = cstate->pipe_src_w;
if (WARN_ON(htotal == 0))
htotal = 1;
@@ -1008,8 +1008,9 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
return min_t(int, wm, USHRT_MAX);
}
-static void vlv_compute_fifo(struct intel_crtc *crtc)
+static void vlv_compute_fifo(struct intel_crtc_state *cstate)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct vlv_wm_state *wm_state = &crtc->wm_state;
struct drm_device *dev = crtc->base.dev;
struct intel_plane *plane;
@@ -1113,8 +1114,9 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
}
}
-static int vlv_compute_wm(struct intel_crtc *crtc)
+static int vlv_compute_wm(struct intel_crtc_state *cstate)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
struct vlv_wm_state *wm_state = &crtc->wm_state;
struct intel_plane *plane;
@@ -1128,7 +1130,7 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
wm_state->num_active_planes = 0;
- vlv_compute_fifo(crtc);
+ vlv_compute_fifo(cstate);
if (wm_state->num_active_planes != 1)
wm_state->cxsr = false;
@@ -1149,7 +1151,7 @@ static int vlv_compute_wm(struct intel_crtc *crtc)
/* normal watermarks */
for (level = 0; level < wm_state->num_levels; level++) {
- int wm = vlv_compute_wm_level(plane, crtc, state,
level);
+ int wm = vlv_compute_wm_level(plane, cstate, state,
level);
int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR
? 63 : 511;
if (level == 0 && wm > max_wm) {
@@ -1353,7 +1355,7 @@ static void vlv_update_wm(struct drm_crtc *crtc)
enum pipe pipe = intel_crtc->pipe;
struct vlv_wm_values wm = {};
- vlv_compute_wm(intel_crtc);
+ vlv_compute_wm(intel_crtc->config);
vlv_merge_wm(dev, &wm);
if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
--
1.8.0.1
___
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[Intel-gfx] [RFC 2/8] drm/i915: Rename skl_wm_plane_id to wm_plane_id
From: Maarten Lankhorst
This function will be used not only by SKL but also VLV/CHV.
Therefore it's renamed
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_pm.c | 57 +
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c94521cc..29820e2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -55,6 +55,28 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
+/*
+ * Return the index of a plane in the DDB and wm result arrays. Primary
+ * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
+ * other universal planes are in indices 1..n. Note that this may leave unused
+ * indices between the top "sprite" plane and the cursor.
+ */
+static int
+wm_plane_id(const struct intel_plane *plane)
+{
+ switch (plane->base.type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ return 0;
+ case DRM_PLANE_TYPE_CURSOR:
+ return PLANE_CURSOR;
+ case DRM_PLANE_TYPE_OVERLAY:
+ return plane->plane + 1;
+ default:
+ MISSING_CASE(plane->base.type);
+ return plane->plane;
+ }
+}
+
static void gen9_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2853,27 +2875,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
#define SKL_DDB_SIZE 896 /* in blocks */
#define BXT_DDB_SIZE 512
-/*
- * Return the index of a plane in the SKL DDB and wm result arrays. Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n. Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
- switch (plane->base.type) {
- case DRM_PLANE_TYPE_PRIMARY:
- return 0;
- case DRM_PLANE_TYPE_CURSOR:
- return PLANE_CURSOR;
- case DRM_PLANE_TYPE_OVERLAY:
- return plane->plane + 1;
- default:
- MISSING_CASE(plane->base.type);
- return plane->plane;
- }
-}
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
@@ -3081,7 +3082,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate)
/* Calculate and cache data rate for each plane */
for_each_plane_in_state(state, plane, pstate, i) {
- id = skl_wm_plane_id(to_intel_plane(plane));
+ id = wm_plane_id(to_intel_plane(plane));
intel_plane = to_intel_plane(plane);
if (intel_plane->pipe != intel_crtc->pipe)
@@ -3100,7 +3101,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate)
/* Calculate CRTC's total data rate from cached values */
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
/* packed/uv */
total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
@@ -3221,7 +3222,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
/* 1. Allocate the mininum required blocks for each active plane */
for_each_plane_in_state(state, plane, pstate, i) {
intel_plane = to_intel_plane(plane);
- id = skl_wm_plane_id(intel_plane);
+ id = wm_plane_id(intel_plane);
if (intel_plane->pipe != pipe)
continue;
@@ -3260,7 +3261,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
unsigned int data_rate, y_data_rate;
uint16_t plane_blocks, y_plane_blocks = 0;
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
data_rate = cstate->wm.skl.plane_data_rate[id];
@@ -3477,7 +3478,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
DRM_DEBUG_KMS("Requested display configuration exceeds
system watermark limitations\n");
DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u,
lines required = %u/31\n",
to_intel_crtc(cstate->base.crtc)->pipe,
-
skl_wm_plane_id(to_intel_plane(pstate->plane)),
+
wm_plane_id(to_intel_plane(pstate->plane)),
res_blocks, ddb_allocation, res_lines);
return -EINVAL;
@@ -3515,7 +3516,7 @@ skl_compute_wm_level(const struct drm_i915_private
*dev_priv,
[Intel-gfx] [RFC 8/8] drm/i915/vlv: Add intermediate field in intel_crtc_wm_state and handlers for two-level watermark
From: Maarten Lankhorst
Rename vlv_compute_wm to vlv_compute_pipe_wm to compute optimal watermark
Add vlv_compute_intermediate_wm to computer intermediate watermark
Add vlv_initial_watermarks to write intermediate watermark into hardware
Add vlv_optimize_watermarks to write optimal watermark into hardware
Change valleyview_crtc_enable to call .initial_watermarks handler
This patch adds the handlers for two-level atomic watermark for VLV/CHV.
It makes use of the optimal and intermediate watermark fields added in
the previous commits to calculate the optimal and intermediate state.
It sets the intermediate watermark which is the safer value of the
currently active and the optimal watermark pre-vblank. Then it sets the
optimal watermark after-vblank.
v2:
- use macro drm_atomic_crtc_state_for_each_plane_state
- remove redundant debug statements in vlv_pipe_set_fifo_size
v3:
- use macro drm_atomic_crtc_state_for_each_plane_state to simplify the code
- check !new_state->active || modeset in computing intermediate watermark
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chi Ding
---
drivers/gpu/drm/i915/intel_display.c | 8 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 150 +++
3 files changed, 121 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1141b86..1ceda24 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4602,8 +4602,6 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
intel_frontbuffer_flip(dev, pipe_config->fb_bits);
- crtc->wm.cxsr_allowed = true;
-
if (pipe_config->update_wm_post && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
@@ -4649,8 +4647,6 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
}
if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
- crtc->wm.cxsr_allowed = false;
-
/*
* Vblank time updates from the shadow to live plane control
register
* are blocked if the memory self-refresh mode is active at that
@@ -6180,7 +6176,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
intel_color_load_luts(&pipe_config->base);
- intel_update_watermarks(crtc);
+ dev_priv->display.initial_watermarks(pipe_config);
intel_enable_pipe(intel_crtc);
assert_vblank_disabled(crtc);
@@ -14591,8 +14587,6 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
intel_crtc->cursor_cntl = ~0;
intel_crtc->cursor_size = ~0;
- intel_crtc->wm.cxsr_allowed = true;
-
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8e77adb..30a6304 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -443,6 +443,7 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ struct vlv_wm_state intermediate;
struct vlv_wm_state optimal;
} vlv;
@@ -683,8 +684,6 @@ struct intel_crtc {
struct vlv_wm_state vlv;
} active;
- /* allow CxSR on this pipe */
- bool cxsr_allowed;
} wm;
int scanline_offset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cc43c1e..9a5e6e9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -31,6 +31,7 @@
#include "intel_drv.h"
#include "../../../platform/x86/intel_ips.h"
#include
+#include
/**
* DOC: RC6
@@ -989,6 +990,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
clock = cstate->base.adjusted_mode.crtc_clock;
htotal = cstate->base.adjusted_mode.crtc_htotal;
width = cstate->pipe_src_w;
+
if (WARN_ON(htotal == 0))
htotal = 1;
@@ -1011,27 +1013,28 @@ static uint16_t vlv_compute_wm_level(struct intel_plane
*plane,
static void vlv_compute_fifo(struct intel_crtc_state *cstate,
struct vlv_wm_state *wm_state)
{
- struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
- struct drm_device *dev = crtc->base.dev;
- struct intel_plane *plane;
unsigned int total_rate = 0;
const int fifo_size = 512 - 1;
int fifo_extra, fifo_left = fifo_size;
int rate[I915_MAX_PLANES] = {};
int i;
+ const struct drm_plane_state *pstate;
+ struct drm_plane *plane;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+
Re: [Intel-gfx] Bad flicker on skylake HQD due to code in the 4.7 merge window
On Thu, 23 Jun 2016, Steven Newbury wrote: > [ Unknown signature status ] > On Sun, 2016-06-19 at 14:53 -0700, James Bottomley wrote: >> On Fri, 2016-06-17 at 16:06 -0700, James Bottomley wrote: >> > On Fri, 2016-06-17 at 16:34 +0300, Jani Nikula wrote: >> > > On Fri, 17 Jun 2016, Daniel Vetter wrote: >> > > > On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley >> > > > wrote: >> > > > > On Thu, 2016-06-16 at 14:29 -0700, James Bottomley wrote: >> > > > > > On Thu, 2016-06-16 at 23:24 +0200, Daniel Vetter wrote: >> > > > > > > I guess we'll need the bisect on this one to make >> > > > > > > progress. >> > > > > > >> > > > > > Sigh, I was afraid that might be the next step. >> > > > > >> > > > > OK, I have a curious data point. I assumed the problem would >> > > > > be >> > > > > somewhere in the drm update, so I started bisecting that at >> > > > > the >> > > > > top. >> > > > > However, the top most commit: >> > > > > >> > > > > commit 1d6da87a3241deb13d073c4125d19ed0e5a0c62c >> > > > > Merge: 1f40c49 a39ed68 >> > > > > Author: Linus Torvalds >> > > > > Date: Mon May 23 11:48:48 2016 -0700 >> > > > > >> > > > > Merge branch 'drm-next' of >> > > > > git://people.freedesktop.org/~airlied/linux >> > > > > >> > > > > Isn't actually bad. There's no flicker here, so whatever >> > > > > caused >> > > > > the >> > > > > problem came from some update after this. >> > > > >> > > > There was a fixes pull after this. Might be worth it to >> > > > restrict >> > > > to >> > > > just >> > > > the i915 changes, which are just >> > > > 5b4fd5bb1230cd037..157d2c7fad0863222 >> > > > >> > > > Looking at those nothing seems to stick out which might explain >> > > > what's >> > > > happening for you. >> > >> > OK, so just on the firmware, the system seems less flickery with >> > the >> > new 1.4.3 UEFI, so I'm starting to think it is a Skylake errata >> > issue. The flicker isn't gone for good, but seems to be reboot >> > dependent (it's there in some boots, but gone on a reboot). >> > >> > > This should be easy enough to try before bisecting: >> > > http://patchwork.freedesktop.org/patch/msgid/1466162081-12042-1-g >> > > it >> > > -s >> > > end-email-mika.kah...@intel.com >> > >> > Applying this didn't seem to make a difference: still there on >> > some >> > and gone on other reboots. >> >> OK, my candidate bad commit is this one: >> >> commit a05628195a0d9f3173dd9aa76f482aef692e46ee >> Author: Ville Syrjälä >> Date: Mon Apr 11 10:23:51 2016 +0300 >> >> drm/i915: Get panel_type from OpRegion panel details >> >> After being more careful about waiting to identify flicker, this one >> seems to be the one the bisect finds. I'm now running v4.7-rc3 with >> this one reverted and am currently seeing no flicker problems. It >> is, >> however, early days because the flicker can hide for long periods, so >> I >> 'll wait until Monday evening and a few reboots before declaring >> victory. >> >> > I'm seeing this on my IvyBridge. I'll try reverting the commit here > too, to see if it's the same issue. IvyBridge doesn't have low vswing for eDP. If reverting helps, it's a different failure mode. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915: Eliminate DDI encoder->type frobbery (rev2)
On Thu, Jun 23, 2016 at 05:42:33AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Eliminate DDI encoder->type frobbery (rev2) > URL : https://patchwork.freedesktop.org/series/8439/ > State : warning > > == Summary == > > Series 8439v2 drm/i915: Eliminate DDI encoder->type frobbery > http://patchwork.freedesktop.org/api/1.0/series/8439/revisions/2/mbox > > Test gem_exec_flush: > Subgroup basic-batch-kernel-default-cmd: > fail -> PASS (ro-byt-n2820) > Subgroup basic-wb-pro-default: > pass -> DMESG-WARN (ro-ivb2-i7-3770) [ 261.726080] [drm:i915_hangcheck_elapsed [i915]] *ERROR* Hangcheck timer elapsed... render ring idle These seem to happen occasionally on that machine. I see one other instance in the CI long term history. > Test kms_pipe_crc_basic: > Subgroup suspend-read-crc-pipe-b: > dmesg-warn -> SKIP (ro-bdw-i7-5557U) > dmesg-warn -> SKIP (ro-bdw-i5-5250u) During resume link training failed due to AUX timing out, and then it decided that the monitors got disconnected as well. ... [ 422.558869] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7145000c [ 422.558876] [drm:drm_dp_dpcd_access] too many retries, giving up [ 422.559339] [drm:intel_enable_pipe] enabling pipe A [ 422.559366] [drm:intel_fbc_alloc_cfb] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 422.559367] [drm:intel_fbc_enable] Enabling FBC on pipe A [ 422.576135] [drm:intel_connector_verify_state] [CONNECTOR:42:DP-1] [ 422.576145] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 422.576174] [drm:verify_single_dpll_state] LCPLL 1350 [ 422.576179] [drm:verify_crtc_state] [CRTC:30:pipe B] [ 422.576188] [drm:verify_crtc_state] [CRTC:34:pipe C] [ 422.576499] [drm:intel_hdmi_detect] [CONNECTOR:37:HDMI-A-1] [ 422.664223] [drm:intel_hdmi_detect] HDMI live status down [ 422.664232] [drm:drm_helper_hpd_irq_event] [CONNECTOR:37:HDMI-A-1] status updated from disconnected to disconnected [ 422.664235] [drm:intel_dp_detect] [CONNECTOR:42:DP-1] [ 422.664276] [drm:drm_helper_hpd_irq_event] [CONNECTOR:42:DP-1] status updated from connected to disconnected [ 422.664278] [drm:intel_hdmi_detect] [CONNECTOR:46:HDMI-A-2] [ 422.752270] [drm:intel_hdmi_detect] HDMI live status down [ 422.752279] [drm:drm_helper_hpd_irq_event] [CONNECTOR:46:HDMI-A-2] status updated from disconnected to disconnected [ 422.774482] [drm:intel_didl_outputs] More than 15 outputs detected via ACPI [ 422.779213] PM: resume of devices complete after 918.864 msecs [ 422.781308] Restarting tasks ... done. [ 422.892455] kms_pipe_crc_basic: exiting, ret=77 [ 422.926390] [drm:drm_fb_helper_hotplug_event] [ 422.926396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:HDMI-A-1] [ 422.926399] [drm:intel_hdmi_detect] [CONNECTOR:37:HDMI-A-1] [ 422.940414] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on [ 422.994389] [drm:intel_get_hpd_pins] hotplug event received, stat 0x0040, dig 0x10101210, pins 0x0040 [ 422.994395] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 422.994397] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 422.994431] [drm:intel_dp_hpd_pulse] got hpd irq on port C - long [ 422.994980] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 41 00 03 01 81 00 00 00 00 08 00 00 [ 422.995383] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 422.995392] [drm:intel_dp_print_rates] source rates: 162000, 27, 54 [ 422.995397] [drm:intel_dp_print_rates] sink rates: 162000, 27 [ 422.995401] [drm:intel_dp_print_rates] common rates: 162000, 27 [ 422.996322] [drm:intel_dp_probe_oui] Sink OUI: 0022b9 [ 422.996693] [drm:intel_dp_probe_oui] Branch OUI: 0022b9 [ 422.997278] [drm:drm_dp_i2c_do_msg] native defer ... [ 423.014081] [drm:drm_dp_i2c_do_msg] native defer [ 423.014434] [drm:intel_hdmi_detect] HDMI live status down [ 423.014446] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:HDMI-A-1] disconnected [ 423.014451] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] [ 423.014456] [drm:intel_dp_detect] [CONNECTOR:42:DP-1] [ 423.015491] [drm:drm_dp_i2c_do_msg] native defer [ 423.016589] [drm:drm_dp_i2c_do_msg] native defer [ 423.018016] [drm:drm_dp_i2c_do_msg] native defer [ 423.019087] [drm:drm_dp_i2c_do_msg] native defer [ 423.021079] [drm:intel_dp_long_pulse] CP or sink specific irq unhandled [ 423.021657] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 41 00 03 01 81 00 00 00 00 08 00 00 [ 423.022032] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 423.022037] [drm:intel_dp_print_rates] source rates: 162000, 27, 54 [ 423.022041] [drm:intel_dp_print_rates] sink rates: 162000, 27 [ 423.022043] [drm:intel_dp_print_rates] common rates: 162000, 27 [ 423.022916] [drm:intel_dp_probe_oui] Sink OUI: 0022b9 [ 423.023284] [dr
Re: [Intel-gfx] Bad flicker on skylake HQD due to code in the 4.7 merge window
On Thu, 2016-06-23 at 15:59 +0300, Jani Nikula wrote: > On Thu, 23 Jun 2016, Steven Newbury wrote: > > [ Unknown signature status ] > > On Sun, 2016-06-19 at 14:53 -0700, James Bottomley wrote: > > > On Fri, 2016-06-17 at 16:06 -0700, James Bottomley wrote: > > > > On Fri, 2016-06-17 at 16:34 +0300, Jani Nikula wrote: > > > > > On Fri, 17 Jun 2016, Daniel Vetter wrote: > > > > > > On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley > > > > > > wrote: > > > > > > > On Thu, 2016-06-16 at 14:29 -0700, James Bottomley wrote: > > > > > > > > On Thu, 2016-06-16 at 23:24 +0200, Daniel Vetter wrote: > > > > > > > > > I guess we'll need the bisect on this one to make > > > > > > > > > progress. > > > > > > > > > > > > > > > > Sigh, I was afraid that might be the next step. > > > > > > > > > > > > > > OK, I have a curious data point. I assumed the problem > > > > > > > would > > > > > > > be > > > > > > > somewhere in the drm update, so I started bisecting that > > > > > > > at > > > > > > > the > > > > > > > top. > > > > > > > However, the top most commit: > > > > > > > > > > > > > > commit 1d6da87a3241deb13d073c4125d19ed0e5a0c62c > > > > > > > Merge: 1f40c49 a39ed68 > > > > > > > Author: Linus Torvalds > > > > > > > Date: Mon May 23 11:48:48 2016 -0700 > > > > > > > > > > > > > > Merge branch 'drm-next' of > > > > > > > git://people.freedesktop.org/~airlied/linux > > > > > > > > > > > > > > Isn't actually bad. There's no flicker here, so whatever > > > > > > > caused > > > > > > > the > > > > > > > problem came from some update after this. > > > > > > > > > > > > There was a fixes pull after this. Might be worth it to > > > > > > restrict > > > > > > to > > > > > > just > > > > > > the i915 changes, which are just > > > > > > 5b4fd5bb1230cd037..157d2c7fad0863222 > > > > > > > > > > > > Looking at those nothing seems to stick out which might > > > > > > explain > > > > > > what's > > > > > > happening for you. > > > > > > > > OK, so just on the firmware, the system seems less flickery > > > > with > > > > the > > > > new 1.4.3 UEFI, so I'm starting to think it is a Skylake > > > > errata > > > > issue. The flicker isn't gone for good, but seems to be > > > > reboot > > > > dependent (it's there in some boots, but gone on a reboot). > > > > > > > > > This should be easy enough to try before bisecting: > > > > > http://patchwork.freedesktop.org/patch/msgid/1466162081-12042 > > > > > -1-g > > > > > it > > > > > -s > > > > > end-email-mika.kah...@intel.com > > > > > > > > Applying this didn't seem to make a difference: still there on > > > > some > > > > and gone on other reboots. > > > > > > OK, my candidate bad commit is this one: > > > > > > commit a05628195a0d9f3173dd9aa76f482aef692e46ee > > > Author: Ville Syrjälä > > > Date: Mon Apr 11 10:23:51 2016 +0300 > > > > > > drm/i915: Get panel_type from OpRegion panel details > > > > > > After being more careful about waiting to identify flicker, this > > > one > > > seems to be the one the bisect finds. I'm now running v4.7-rc3 > > > with > > > this one reverted and am currently seeing no flicker > > > problems. It > > > is, > > > however, early days because the flicker can hide for long > > > periods, so > > > I > > > 'll wait until Monday evening and a few reboots before declaring > > > victory. > > > > > > > > I'm seeing this on my IvyBridge. I'll try reverting the commit > > here > > too, to see if it's the same issue. > > IvyBridge doesn't have low vswing for eDP. If reverting helps, it's a > different failure mode. > It must be something else then. Actually, in my case linus/master is okay. I saw the subject and though it must be the same issue. I'm seeing it with drm-intel nightly/next branches. Shall I try to bisect it? Symptoms are similar, although I would describe it more like flashes of a different buffer across parts of the screen. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
On 23/06/16 13:11, Chris Wilson wrote:
On Thu, Jun 23, 2016 at 12:46:42PM +0100, Tvrtko Ursulin wrote:
On 23/06/16 12:25, Chris Wilson wrote:
On Thu, Jun 23, 2016 at 12:12:29PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Effectively removes one layer of indirection between the mask of
possible engines and the engine constructors. Instead of spelling
out in code the mapping of HAS_ to constructors, makes
more use of the recently added data driven approach by putting
engine constructor vfuncs into the table as well.
Effect is fewer lines of source and smaller binary.
At the same time simplify the error handling since engine
destructors can run on unitialized engines anyway.
Similar approach could be done for legacy submission is wanted.
v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
ENGINE_MASK and HAS_ENGINE macros.
Also removed the forward declarations by shuffling functions
around.
v3: Warn when logical_rings table does not contain enough data
and disable the engines which could not be initialized.
(Chris Wilson)
I was happy with the BUILD_BUG suggestion :)
I've changed my mind later. :)
+ for (i = 0;
+ i < I915_NUM_ENGINES && i < ARRAY_SIZE(logical_rings); i++) {
HAS_ENGINE() == false if i >= I915_NUM_ENGINES
Don't follow. :) Why is v3 not good enough?
Both (all three) is overkill.
I feel like HAS_ENGINE() should encompass i < I915_NUM_ENGINES quite
succinctly. For belt and braces,
WARN_ON(dev_priv->intel_info.rings_mask & -(1 << I915_NUM_ENGINES)));
I don't think this works - you meant testing that bits higher than
BIT(I915_NUM_ENGINES) were not set in ring_mask?
And it probably belongs somewhere else, in common code which initializes
intel_device_info I think.
for (i = 0; i < ARRAY_SIZE(); i++) {
if (!HAS_ENGINE(i))
continue;
if (!logical_rings[i].init)
continue;
ret = logical_rings[i].init(logical_rings_engine(i));
if (ret)
goto err;
mask |= ENGINE_MASK(i);
}
WARN_ON(mask != dev_priv->intel_info.rings_mask) ...
?
I like it, will resend when we clarify the above. Also solves one more
issue than the previous versions which is a potentially sparse
logical_rings array if engine ids get renumbered.
Tvrtko
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Re: [Intel-gfx] Bad flicker on skylake HQD due to code in the 4.7 merge window
On Sun, 2016-06-19 at 14:53 -0700, James Bottomley wrote: > On Fri, 2016-06-17 at 16:06 -0700, James Bottomley wrote: > > On Fri, 2016-06-17 at 16:34 +0300, Jani Nikula wrote: > > > On Fri, 17 Jun 2016, Daniel Vetter wrote: > > > > On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley > > > > wrote: > > > > > On Thu, 2016-06-16 at 14:29 -0700, James Bottomley wrote: > > > > > > On Thu, 2016-06-16 at 23:24 +0200, Daniel Vetter wrote: > > > > > > > I guess we'll need the bisect on this one to make > > > > > > > progress. > > > > > > > > > > > > Sigh, I was afraid that might be the next step. > > > > > > > > > > OK, I have a curious data point. I assumed the problem would > > > > > be > > > > > somewhere in the drm update, so I started bisecting that at > > > > > the > > > > > top. > > > > > However, the top most commit: > > > > > > > > > > commit 1d6da87a3241deb13d073c4125d19ed0e5a0c62c > > > > > Merge: 1f40c49 a39ed68 > > > > > Author: Linus Torvalds > > > > > Date: Mon May 23 11:48:48 2016 -0700 > > > > > > > > > > Merge branch 'drm-next' of > > > > > git://people.freedesktop.org/~airlied/linux > > > > > > > > > > Isn't actually bad. There's no flicker here, so whatever > > > > > caused > > > > > the > > > > > problem came from some update after this. > > > > > > > > There was a fixes pull after this. Might be worth it to > > > > restrict > > > > to > > > > just > > > > the i915 changes, which are just > > > > 5b4fd5bb1230cd037..157d2c7fad0863222 > > > > > > > > Looking at those nothing seems to stick out which might explain > > > > what's > > > > happening for you. > > > > OK, so just on the firmware, the system seems less flickery with > > the > > new 1.4.3 UEFI, so I'm starting to think it is a Skylake errata > > issue. The flicker isn't gone for good, but seems to be reboot > > dependent (it's there in some boots, but gone on a reboot). > > > > > This should be easy enough to try before bisecting: > > > http://patchwork.freedesktop.org/patch/msgid/1466162081-12042-1-g > > > it > > > -s > > > end-email-mika.kah...@intel.com > > > > Applying this didn't seem to make a difference: still there on > > some > > and gone on other reboots. > > OK, my candidate bad commit is this one: > > commit a05628195a0d9f3173dd9aa76f482aef692e46ee > Author: Ville Syrjälä > Date: Mon Apr 11 10:23:51 2016 +0300 > > drm/i915: Get panel_type from OpRegion panel details > > After being more careful about waiting to identify flicker, this one > seems to be the one the bisect finds. I'm now running v4.7-rc3 with > this one reverted and am currently seeing no flicker problems. It > is, > however, early days because the flicker can hide for long periods, so > I > 'll wait until Monday evening and a few reboots before declaring > victory. > > I'm seeing this on my IvyBridge. I'll try reverting the commit here too, to see if it's the same issue. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Small compaction of the engine init code
On Thu, Jun 23, 2016 at 02:16:55PM +0100, Tvrtko Ursulin wrote:
>
> On 23/06/16 13:11, Chris Wilson wrote:
> >On Thu, Jun 23, 2016 at 12:46:42PM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 23/06/16 12:25, Chris Wilson wrote:
> >>>On Thu, Jun 23, 2016 at 12:12:29PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Effectively removes one layer of indirection between the mask of
> possible engines and the engine constructors. Instead of spelling
> out in code the mapping of HAS_ to constructors, makes
> more use of the recently added data driven approach by putting
> engine constructor vfuncs into the table as well.
>
> Effect is fewer lines of source and smaller binary.
>
> At the same time simplify the error handling since engine
> destructors can run on unitialized engines anyway.
>
> Similar approach could be done for legacy submission is wanted.
>
> v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
> ENGINE_MASK and HAS_ENGINE macros.
> Also removed the forward declarations by shuffling functions
> around.
>
> v3: Warn when logical_rings table does not contain enough data
> and disable the engines which could not be initialized.
> (Chris Wilson)
> >>>
> >>>I was happy with the BUILD_BUG suggestion :)
> >>
> >>I've changed my mind later. :)
> >>
> + for (i = 0;
> + i < I915_NUM_ENGINES && i < ARRAY_SIZE(logical_rings); i++) {
> >>>
> >>>HAS_ENGINE() == false if i >= I915_NUM_ENGINES
> >>
> >>Don't follow. :) Why is v3 not good enough?
> >
> >Both (all three) is overkill.
> >
> >I feel like HAS_ENGINE() should encompass i < I915_NUM_ENGINES quite
> >succinctly. For belt and braces,
> >
> >WARN_ON(dev_priv->intel_info.rings_mask & -(1 << I915_NUM_ENGINES)));
>
> I don't think this works - you meant testing that bits higher than
> BIT(I915_NUM_ENGINES) were not set in ring_mask?
Yes. Higher than BIT(NUM_ENGINES-1), just to make sure we don't end up
setting garbage at some point.
> And it probably belongs somewhere else, in common code which
> initializes intel_device_info I think.
Possibly. I think the engine initialisation path is a good choice
though, since that has the knowlege of what will be setup.
Either here (with the goal of using this as the basis for future
unification), or in the caller.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/atomic: Make drm_atomic_legacy_backoff reset crtc->acquire_ctx
On Thu, Jun 23, 2016 at 01:45:06PM +0200, Maarten Lankhorst wrote:
> Atomic updates may acquire more state than initially locked through
> drm_modeset_lock_crtc, running with heavy stress can cause a
> WARN_ON(crtc->acquire_ctx) in drm_modeset_lock_crtc:
>
> [ 601.491296] [ cut here ]
> [ 601.491366] WARNING: CPU: 0 PID: 2411 at
> drivers/gpu/drm/drm_modeset_lock.c:191 drm_modeset_lock_crtc+0xeb/0xf0 [drm]
> [ 601.491369] Modules linked in: drm i915 drm_kms_helper
> [ 601.491414] CPU: 0 PID: 2411 Comm: kms_cursor_lega Tainted: G U
> 4.7.0-rc4-patser+ #4798
> [ 601.491417] Hardware name: Intel Corporation Skylake Client
> [ 601.491420] 88044d153c98 812ead28
>
> [ 601.491425] 88044d153cd8 810868e6
> 00bf58058030
> [ 601.491431] 880088b415e8 880458058030 88008a271548
> 88008a271568
> [ 601.491436] Call Trace:
> [ 601.491443] [] dump_stack+0x4d/0x65
> [ 601.491447] [] __warn+0xc6/0xe0
> [ 601.491452] [] warn_slowpath_null+0x18/0x20
> [ 601.491472] [] drm_modeset_lock_crtc+0xeb/0xf0 [drm]
> [ 601.491491] [] drm_mode_cursor_common+0x66/0x180 [drm]
> [ 601.491509] [] drm_mode_cursor_ioctl+0x3c/0x40 [drm]
> [ 601.491524] [] drm_ioctl+0x14d/0x530 [drm]
> [ 601.491540] [] ? drm_mode_setcrtc+0x520/0x520 [drm]
> [ 601.491545] [] ? handle_mm_fault+0x106b/0x1430
> [ 601.491550] [] ? stop_one_cpu+0x61/0x70
> [ 601.491556] [] do_vfs_ioctl+0x8d/0x570
> [ 601.491560] [] ? security_file_ioctl+0x3e/0x60
> [ 601.491565] [] SyS_ioctl+0x74/0x80
> [ 601.491571] [] ? posix_get_monotonic_raw+0xc/0x10
> [ 601.491576] [] entry_SYSCALL_64_fastpath+0x13/0x8f
> [ 601.491581] ---[ end trace 56f3d3d85f000d00 ]---
>
> For good measure, test mode_config.acquire_ctx too, although this should
> never happen.
>
> Testcase: kms_cursor_legacy
> Signed-off-by: Maarten Lankhorst
It's kinda a bug in the skl wm code which unecessarily looks at other
plane state.
Reviewed-by: Daniel Vetter
Given that this is fairly hard to hit, but will blow in really strange
ways in practice I think also justified for backporting.
Cc: sta...@vger.kernel.org
Dave, can you pls pick up for -fixes directly?
Thanks, Daniel
> ---
> drivers/gpu/drm/drm_atomic.c | 27 ++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index d99ab2f6663f..3cee084e9d28 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1299,14 +1299,39 @@ EXPORT_SYMBOL(drm_atomic_add_affected_planes);
> */
> void drm_atomic_legacy_backoff(struct drm_atomic_state *state)
> {
> + struct drm_device *dev = state->dev;
> + unsigned crtc_mask = 0;
> + struct drm_crtc *crtc;
> int ret;
> + bool global = false;
> +
> + drm_for_each_crtc(crtc, dev) {
> + if (crtc->acquire_ctx != state->acquire_ctx)
> + continue;
> +
> + crtc_mask |= drm_crtc_mask(crtc);
> + crtc->acquire_ctx = NULL;
> + }
> +
> + if (WARN_ON(dev->mode_config.acquire_ctx == state->acquire_ctx)) {
> + global = true;
> +
> + dev->mode_config.acquire_ctx = NULL;
> + }
>
> retry:
> drm_modeset_backoff(state->acquire_ctx);
>
> - ret = drm_modeset_lock_all_ctx(state->dev, state->acquire_ctx);
> + ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
> if (ret)
> goto retry;
> +
> + drm_for_each_crtc(crtc, dev)
> + if (drm_crtc_mask(crtc) & crtc_mask)
> + crtc->acquire_ctx = state->acquire_ctx;
> +
> + if (global)
> + dev->mode_config.acquire_ctx = state->acquire_ctx;
> }
> EXPORT_SYMBOL(drm_atomic_legacy_backoff);
>
> --
> 2.5.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/6] drm/i915/huc: Add HuC fw loading support
On Thu, 23 Jun 2016, Dave Gordon wrote:
On 22/06/16 09:31, Daniel Vetter wrote:
On Tue, Jun 21, 2016 at 07:11:22PM +0100, Peter Antoine wrote:
From: Alex Dai
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_dma.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 13 +-
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc.h| 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 11 +-
drivers/gpu/drm/i915/intel_huc.h| 44 ++
drivers/gpu/drm/i915/intel_huc_loader.c | 262
9 files changed, 331 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 276abf1..7384db0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -44,6 +44,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_dma.c
b/drivers/gpu/drm/i915/i915_dma.c
index e28c0dd..a449a59 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -507,6 +507,7 @@ static int i915_load_modeset_init(struct drm_device
*dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev);
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -532,6 +533,7 @@ static int i915_load_modeset_init(struct drm_device
*dev)
cleanup_gem:
i915_gem_fini(dev);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1563,6 +1565,7 @@ int i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
flush_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 7c81757..8b88227 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -54,6 +54,7 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
@@ -1749,6 +1750,7 @@ struct drm_i915_private {
struct intel_gvt gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2841,6 +2843,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_UCODE(dev)(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)(HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 6abd5e5..549dd3f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5143,9 +5143,16 @@ i915_gem_init_hw(struct drm_device *dev)
intel_mocs_init_l3cc_table(dev);
/* We can't enable contexts until all firmware is loaded */
- ret = intel_guc_setup(dev);
- if (ret)
- goto out;
+ if (HAS_GUC(dev)) {
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
+
+ intel_huc_load(dev);
+ ret = intel_guc_setup(dev);
+ if (ret)
+ goto out;
+ }
/*
* Increment the next seqno by 0x100 so we have a visible break
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
b/drivers/gpu/drm/i915/i915_guc_reg.h
index cf5a65b..51533f1 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL(1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<
[Intel-gfx] [PATCH v4] drm/i915: Small compaction of the engine init code
From: Tvrtko Ursulin
Effectively removes one layer of indirection between the mask of
possible engines and the engine constructors. Instead of spelling
out in code the mapping of HAS_ to constructors, makes
more use of the recently added data driven approach by putting
engine constructor vfuncs into the table as well.
Effect is fewer lines of source and smaller binary.
At the same time simplify the error handling since engine
destructors can run on unitialized engines anyway.
Similar approach could be done for legacy submission is wanted.
v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced
ENGINE_MASK and HAS_ENGINE macros.
Also removed the forward declarations by shuffling functions
around.
v3: Warn when logical_rings table does not contain enough data
and disable the engines which could not be initialized.
(Chris Wilson)
v4: Chris Wilson suggested a nicer engine init loop.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 27 +++--
drivers/gpu/drm/i915/intel_lrc.c | 253 ++-
2 files changed, 130 insertions(+), 150 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74d0a61de75a..6d96b14b53c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2759,17 +2759,22 @@ struct drm_i915_cmd_table {
#define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
#define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
-#define RENDER_RING(1ring_mask & BSD2_RING)
-#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
+#define ENGINE_MASK(id)BIT(id)
+#define RENDER_RINGENGINE_MASK(RCS)
+#define BSD_RING ENGINE_MASK(VCS)
+#define BLT_RING ENGINE_MASK(BCS)
+#define VEBOX_RING ENGINE_MASK(VECS)
+#define BSD2_RING ENGINE_MASK(VCS2)
+#define ALL_ENGINES(~0)
+
+#define HAS_ENGINE(dev_priv, id) \
+ (INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
+
+#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
+#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
+#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
+#define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
+
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index debed011a958..62b0dc6c2642 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2016,12 +2016,90 @@ lrc_setup_hws(struct intel_engine_cs *engine,
return 0;
}
+static int
+logical_ring_init(struct intel_engine_cs *engine)
+{
+ struct i915_gem_context *dctx = engine->i915->kernel_context;
+ int ret;
+
+ ret = i915_cmd_parser_init_ring(engine);
+ if (ret)
+ goto error;
+
+ ret = execlists_context_deferred_alloc(dctx, engine);
+ if (ret)
+ goto error;
+
+ /* As this is the default context, always pin it */
+ ret = intel_lr_context_pin(dctx, engine);
+ if (ret) {
+ DRM_ERROR("Failed to pin context for %s: %d\n",
+ engine->name, ret);
+ goto error;
+ }
+
+ /* And setup the hardware status page. */
+ ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
+ if (ret) {
+ DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
+ goto error;
+ }
+
+ return 0;
+
+error:
+ intel_logical_ring_cleanup(engine);
+ return ret;
+}
+
+static int logical_render_ring_init(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+ int ret;
+
+ if (HAS_L3_DPF(dev_priv))
+ engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+
+ /* Override some for render ring. */
+ if (INTEL_GEN(dev_priv) >= 9)
+ engine->init_hw = gen9_init_render_ring;
+ else
+ engine->init_hw = gen8_init_render_ring;
+ engine->init_context = gen8_init_rcs_context;
+ engine->cleanup = intel_fini_pipe_control;
+ engine->emit_flush = gen8_emit_flush_render;
+ engine->emit_request = gen8_emit_request_render;
+
+ ret = intel_init_pipe_control(engine);
+ if (ret)
+ return ret;
+
+ ret = intel_init_workaround_bb(engine);
+ if (ret) {
+ /*
+* We continue even if we fail to initialize WA batch
+* because we only expect rare glitches but nothing
+* critical to prevent us from using GPU
+*/
+
Re: [Intel-gfx] [PATCH v4] drm/i915: Small compaction of the engine init code
On Thu, Jun 23, 2016 at 02:52:41PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Effectively removes one layer of indirection between the mask of > possible engines and the engine constructors. Instead of spelling > out in code the mapping of HAS_ to constructors, makes > more use of the recently added data driven approach by putting > engine constructor vfuncs into the table as well. > > Effect is fewer lines of source and smaller binary. > > At the same time simplify the error handling since engine > destructors can run on unitialized engines anyway. > > Similar approach could be done for legacy submission is wanted. > > v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced > ENGINE_MASK and HAS_ENGINE macros. > Also removed the forward declarations by shuffling functions > around. > > v3: Warn when logical_rings table does not contain enough data > and disable the engines which could not be initialized. > (Chris Wilson) > > v4: Chris Wilson suggested a nicer engine init loop. > > Signed-off-by: Tvrtko Ursulin > Cc: Chris Wilson Reviewed-by: Chris Wilson > + WARN_ON(INTEL_INFO(dev_priv)->ring_mask & > + GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); It's computed as a long, so BITS_PER_LONG would suffice p/x GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)) = ((~0UL) << I915_NUM_ENGINES) = 0xffc0 p/x -(1 << I915_NUM_ENGINES) = 0xffc0 -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/vgem: Fix mmaping
The vGEM mmap code has bitrotted slightly and now immediately BUGs.
Since vGEM was last updated, there are new core GEM facilities to
provide more common functions, so let's use those here.
v2: drm_gem_free_mmap_offset() is performed from
drm_gem_object_release() so we can remove the redundant call.
Testcase: igt/vgem_basic/mmap
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96603
Signed-off-by: Chris Wilson
Cc: Sean Paul
Cc: Zach Reizner
Cc: Matthew Auld
Tested-by: Humberto Israel Perez Rodriguez
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/vgem/vgem_drv.c | 164 +++-
drivers/gpu/drm/vgem/vgem_drv.h | 6 --
2 files changed, 61 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index 35ea5d02a827..c161b6d7e427 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -42,81 +42,38 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
-void vgem_gem_put_pages(struct drm_vgem_gem_object *obj)
-{
- drm_gem_put_pages(&obj->base, obj->pages, false, false);
- obj->pages = NULL;
-}
-
static void vgem_gem_free_object(struct drm_gem_object *obj)
{
struct drm_vgem_gem_object *vgem_obj = to_vgem_bo(obj);
- drm_gem_free_mmap_offset(obj);
-
- if (vgem_obj->use_dma_buf && obj->dma_buf) {
- dma_buf_put(obj->dma_buf);
- obj->dma_buf = NULL;
- }
-
drm_gem_object_release(obj);
-
- if (vgem_obj->pages)
- vgem_gem_put_pages(vgem_obj);
-
- vgem_obj->pages = NULL;
-
kfree(vgem_obj);
}
-int vgem_gem_get_pages(struct drm_vgem_gem_object *obj)
-{
- struct page **pages;
-
- if (obj->pages || obj->use_dma_buf)
- return 0;
-
- pages = drm_gem_get_pages(&obj->base);
- if (IS_ERR(pages)) {
- return PTR_ERR(pages);
- }
-
- obj->pages = pages;
-
- return 0;
-}
-
static int vgem_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
struct drm_vgem_gem_object *obj = vma->vm_private_data;
- loff_t num_pages;
- pgoff_t page_offset;
- int ret;
-
/* We don't use vmf->pgoff since that has the fake offset */
- page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
- PAGE_SHIFT;
-
- num_pages = DIV_ROUND_UP(obj->base.size, PAGE_SIZE);
-
- if (page_offset > num_pages)
- return VM_FAULT_SIGBUS;
-
- ret = vm_insert_page(vma, (unsigned long)vmf->virtual_address,
-obj->pages[page_offset]);
- switch (ret) {
- case 0:
- return VM_FAULT_NOPAGE;
- case -ENOMEM:
- return VM_FAULT_OOM;
- case -EBUSY:
- return VM_FAULT_RETRY;
- case -EFAULT:
- case -EINVAL:
- return VM_FAULT_SIGBUS;
- default:
- WARN_ON(1);
- return VM_FAULT_SIGBUS;
+ unsigned long vaddr = (unsigned long)vmf->virtual_address;
+ struct page *page;
+
+ page = shmem_read_mapping_page(file_inode(obj->base.filp)->i_mapping,
+ (vaddr - vma->vm_start) >> PAGE_SHIFT);
+ if (!IS_ERR(page)) {
+ vmf->page = page;
+ return 0;
+ } else switch (PTR_ERR(page)) {
+ case -ENOSPC:
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ case -EBUSY:
+ return VM_FAULT_RETRY;
+ case -EFAULT:
+ case -EINVAL:
+ return VM_FAULT_SIGBUS;
+ default:
+ WARN_ON_ONCE(PTR_ERR(page));
+ return VM_FAULT_SIGBUS;
}
}
@@ -134,57 +91,43 @@ static struct drm_gem_object *vgem_gem_create(struct
drm_device *dev,
unsigned long size)
{
struct drm_vgem_gem_object *obj;
- struct drm_gem_object *gem_object;
- int err;
-
- size = roundup(size, PAGE_SIZE);
+ int ret;
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
if (!obj)
return ERR_PTR(-ENOMEM);
- gem_object = &obj->base;
-
- err = drm_gem_object_init(dev, gem_object, size);
- if (err)
- goto out;
-
- err = vgem_gem_get_pages(obj);
- if (err)
- goto out;
-
- err = drm_gem_handle_create(file, gem_object, handle);
- if (err)
- goto handle_out;
+ ret = drm_gem_object_init(dev, &obj->base, roundup(size, PAGE_SIZE));
+ if (ret)
+ goto err_free;
- drm_gem_object_unreference_unlocked(gem_object);
+ ret = drm_gem_handle_create(file, &obj->base, handle);
+ drm_gem_object_unreference_unlocked(&obj->base);
+ if (ret)
+ goto err;
- return gem_object;
+ return &o
[Intel-gfx] [PATCH 2/3] drm/vgem: Enable dmabuf interface for export
Enable the standard GEM dma-buf interface provided by the DRM core, but
only for exporting the VGEM object. This allows passing around the VGEM
objects created from the dumb interface and using them as sources
elsewhere. Creating a VGEM object for a foriegn handle is not supported.
v2: With additional completeness.
v3: Need to clear the CPU cache upon exporting the dma-addresses.
v4: Use drm_gem_put_pages() as well.
Testcase: igt/vgem_basic/dmabuf-*
Testcase: igt/prime_vgem
Signed-off-by: Chris Wilson
Cc: Sean Paul
Cc: Zach Reizner
---
drivers/gpu/drm/vgem/vgem_drv.c | 104 +++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index c161b6d7e427..69468b5f3d82 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -192,14 +192,116 @@ static const struct file_operations vgem_driver_fops = {
.release= drm_release,
};
+static int vgem_prime_pin(struct drm_gem_object *obj)
+{
+ long n_pages = obj->size >> PAGE_SHIFT;
+ struct page **pages;
+
+ /* Flush the object from the CPU cache so that importers can rely
+* on coherent indirect access via the exported dma-address.
+*/
+ pages = drm_gem_get_pages(obj);
+ if (IS_ERR(pages))
+ return PTR_ERR(pages);
+
+ drm_clflush_pages(pages, n_pages);
+ drm_gem_put_pages(obj, pages, true, false);
+
+ return 0;
+}
+
+static struct sg_table *vgem_prime_get_sg_table(struct drm_gem_object *obj)
+{
+ long n_pages = obj->size >> PAGE_SHIFT;
+ struct sg_table *st;
+ struct page **pages;
+ int ret;
+
+ st = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
+ if (st == NULL)
+ return ERR_PTR(-ENOMEM);
+
+ pages = drm_gem_get_pages(obj);
+ if (IS_ERR(pages)) {
+ ret = PTR_ERR(pages);
+ goto err;
+ }
+
+ ret = sg_alloc_table_from_pages(st, pages, n_pages,
+ 0, obj->size, GFP_KERNEL);
+ drm_gem_put_pages(obj, pages, false, false);
+ if (ret)
+ goto err;
+
+ return st;
+
+err:
+ kfree(st);
+ return ERR_PTR(ret);
+}
+
+static void *vgem_prime_vmap(struct drm_gem_object *obj)
+{
+ long n_pages = obj->size >> PAGE_SHIFT;
+ struct page **pages;
+ void *addr;
+
+ pages = drm_gem_get_pages(obj);
+ if (IS_ERR(pages))
+ return NULL;
+
+ addr = vmap(pages, n_pages, 0, pgprot_writecombine(PAGE_KERNEL_IO));
+ drm_gem_put_pages(obj, pages, false, false);
+
+ return addr;
+}
+
+static void vgem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
+{
+ vunmap(vaddr);
+}
+
+static int vgem_prime_mmap(struct drm_gem_object *obj,
+ struct vm_area_struct *vma)
+{
+ int ret;
+
+ if (obj->size < vma->vm_end - vma->vm_start)
+ return -EINVAL;
+
+ if (!obj->filp)
+ return -ENODEV;
+
+ ret = obj->filp->f_op->mmap(obj->filp, vma);
+ if (ret)
+ return ret;
+
+ fput(vma->vm_file);
+ vma->vm_file = get_file(obj->filp);
+ vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
+ vma->vm_page_prot =
pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
+
+ return 0;
+}
+
static struct drm_driver vgem_driver = {
- .driver_features= DRIVER_GEM,
+ .driver_features= DRIVER_GEM | DRIVER_PRIME,
.gem_free_object_unlocked = vgem_gem_free_object,
.gem_vm_ops = &vgem_gem_vm_ops,
.ioctls = vgem_ioctls,
.fops = &vgem_driver_fops,
+
.dumb_create= vgem_gem_dumb_create,
.dumb_map_offset= vgem_gem_dumb_map,
+
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .gem_prime_pin = vgem_prime_pin,
+ .gem_prime_export = drm_gem_prime_export,
+ .gem_prime_get_sg_table = vgem_prime_get_sg_table,
+ .gem_prime_vmap = vgem_prime_vmap,
+ .gem_prime_vunmap = vgem_prime_vunmap,
+ .gem_prime_mmap = vgem_prime_mmap,
+
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.date = DRIVER_DATE,
--
2.8.1
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[Intel-gfx] [PATCH 3/3] drm/vgem: Attach sw fences to exported vGEM dma-buf (ioctl)
vGEM buffers are useful for passing data between software clients and
hardware renders. By allowing the user to create and attach fences to
the exported vGEM buffers (on the dma-buf), the user can implement a
deferred renderer and queue hardware operations like flipping and then
signal the buffer readiness (i.e. this allows the user to schedule
operations out-of-order, but have them complete in-order).
This also makes it much easier to write tightly controlled testcases for
dma-buf fencing and signaling between hardware drivers.
Testcase: igt/vgem_basic/dmabuf-fence
Signed-off-by: Chris Wilson
Cc: Sean Paul
Cc: Zach Reizner
---
drivers/gpu/drm/vgem/Makefile | 2 +-
drivers/gpu/drm/vgem/vgem_drv.c | 34 ++
drivers/gpu/drm/vgem/vgem_drv.h | 18
drivers/gpu/drm/vgem/vgem_fence.c | 217 ++
include/uapi/drm/vgem_drm.h | 62 +++
5 files changed, 332 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/vgem/vgem_fence.c
create mode 100644 include/uapi/drm/vgem_drm.h
diff --git a/drivers/gpu/drm/vgem/Makefile b/drivers/gpu/drm/vgem/Makefile
index 3f4c7b842028..bfcdea1330e6 100644
--- a/drivers/gpu/drm/vgem/Makefile
+++ b/drivers/gpu/drm/vgem/Makefile
@@ -1,4 +1,4 @@
ccflags-y := -Iinclude/drm
-vgem-y := vgem_drv.o
+vgem-y := vgem_drv.o vgem_fence.o
obj-$(CONFIG_DRM_VGEM) += vgem.o
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index 69468b5f3d82..56e348701382 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -83,6 +83,34 @@ static const struct vm_operations_struct vgem_gem_vm_ops = {
.close = drm_gem_vm_close,
};
+static int vgem_open(struct drm_device *dev, struct drm_file *file)
+{
+ struct vgem_file *vfile;
+ int ret;
+
+ vfile = kzalloc(sizeof(*vfile), GFP_KERNEL);
+ if (!vfile)
+ return -ENOMEM;
+
+ file->driver_priv = vfile;
+
+ ret = vgem_fence_open(vfile);
+ if (ret) {
+ kfree(vfile);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void vgem_preclose(struct drm_device *dev, struct drm_file *file)
+{
+ struct vgem_file *vfile = file->driver_priv;
+
+ vgem_fence_close(vfile);
+ kfree(vfile);
+}
+
/* ioctls */
static struct drm_gem_object *vgem_gem_create(struct drm_device *dev,
@@ -164,6 +192,8 @@ unref:
}
static struct drm_ioctl_desc vgem_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(VGEM_FENCE_ATTACH, vgem_fence_attach_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(VGEM_FENCE_SIGNAL, vgem_fence_signal_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
};
static int vgem_mmap(struct file *filp, struct vm_area_struct *vma)
@@ -286,9 +316,12 @@ static int vgem_prime_mmap(struct drm_gem_object *obj,
static struct drm_driver vgem_driver = {
.driver_features= DRIVER_GEM | DRIVER_PRIME,
+ .open = vgem_open,
+ .preclose = vgem_preclose,
.gem_free_object_unlocked = vgem_gem_free_object,
.gem_vm_ops = &vgem_gem_vm_ops,
.ioctls = vgem_ioctls,
+ .num_ioctls = ARRAY_SIZE(vgem_ioctls),
.fops = &vgem_driver_fops,
.dumb_create= vgem_gem_dumb_create,
@@ -343,5 +376,6 @@ module_init(vgem_init);
module_exit(vgem_exit);
MODULE_AUTHOR("Red Hat, Inc.");
+MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/vgem/vgem_drv.h b/drivers/gpu/drm/vgem/vgem_drv.h
index 988cbaae7588..88ce21010e28 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.h
+++ b/drivers/gpu/drm/vgem/vgem_drv.h
@@ -32,9 +32,27 @@
#include
#include
+#include
+
+struct vgem_file {
+ struct idr fence_idr;
+ struct mutex fence_mutex;
+ u64 fence_context;
+ atomic_t fence_seqno;
+};
+
#define to_vgem_bo(x) container_of(x, struct drm_vgem_gem_object, base)
struct drm_vgem_gem_object {
struct drm_gem_object base;
};
+int vgem_fence_open(struct vgem_file *file);
+int vgem_fence_attach_ioctl(struct drm_device *dev,
+ void *data,
+ struct drm_file *file);
+int vgem_fence_signal_ioctl(struct drm_device *dev,
+ void *data,
+ struct drm_file *file);
+void vgem_fence_close(struct vgem_file *file);
+
#endif
diff --git a/drivers/gpu/drm/vgem/vgem_fence.c
b/drivers/gpu/drm/vgem/vgem_fence.c
new file mode 100644
index ..46130e4a3506
--- /dev/null
+++ b/drivers/gpu/drm/vgem/vgem_fence.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software")
+ *
[Intel-gfx] [PATCH i-g-t 1/2] tests/{kms_cursor_legacy, drv_missed_irq}, lib/drmtest: Fix warnings about unused function return values.
Signed-off-by: Marius Vlad
CC: Chris Wilson
---
lib/drmtest.c | 8 +++-
tests/drv_missed_irq.c| 2 +-
tests/kms_cursor_legacy.c | 8 ++--
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 9a1232f..1e28f60 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -218,11 +218,11 @@ int drm_get_card(void)
return -1;
}
-static void modprobe(const char *driver)
+static int modprobe(const char *driver)
{
char buf[128];
snprintf(buf, sizeof(buf), "/sbin/modprobe -s %s", driver);
- system(buf);
+ return system(buf);
}
/**
@@ -236,8 +236,6 @@ static void modprobe(const char *driver)
*/
int __drm_open_driver(int chipset)
{
- if (chipset & DRIVER_VGEM)
- modprobe("vgem");
for (int i = 0; i < 16; i++) {
char name[80];
@@ -258,7 +256,7 @@ int __drm_open_driver(int chipset)
if (chipset & DRIVER_VGEM &&
is_vgem_device(fd))
- return fd;
+ return (modprobe("vgem") == -1) ? -1 : fd;
close(fd);
}
diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c
index 66d20ed..130a6aa 100644
--- a/tests/drv_missed_irq.c
+++ b/tests/drv_missed_irq.c
@@ -130,7 +130,7 @@ igt_simple_main
fclose(file);
file = igt_debugfs_fopen("i915_ring_test_irq", "r");
- fscanf(file, "%x", &expect_rings);
+ igt_assert_eq(fscanf(file, "%x", &expect_rings), 1);
fclose(file);
igt_debug("Testing rings %x\n", expect_rings);
diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c
index 00890c9..2228e99 100644
--- a/tests/kms_cursor_legacy.c
+++ b/tests/kms_cursor_legacy.c
@@ -238,6 +238,7 @@ static void flip(struct data *data,
}
igt_fork(child, 1) {
unsigned long count = 0;
+ ssize_t nread;
unsigned crtc = data->resources->crtcs[flip_pipe];
igt_until_timeout(timeout) {
@@ -245,7 +246,8 @@ static void flip(struct data *data,
drmModePageFlip(data->fd, crtc, fb_id,
DRM_MODE_PAGE_FLIP_EVENT,
NULL);
- read(data->fd, buf, sizeof(buf));
+ nread = read(data->fd, buf, sizeof(buf));
+ igt_assert_eq(nread, sizeof(buf));
count++;
}
@@ -286,6 +288,7 @@ static void basic_flip(struct data *data)
struct igt_fb fb_info;
unsigned vblank_start;
int target;
+ ssize_t nread;
struct drm_event buf;
uint32_t fb_id;
@@ -338,7 +341,8 @@ static void basic_flip(struct data *data)
igt_assert_eq(get_vblank(data->fd, 0, 0), vblank_start);
igt_set_timeout(1, "Stuck page flip");
- read(data->fd, &buf, sizeof(buf));
+ nread = read(data->fd, &buf, sizeof(buf));
+ igt_assert_eq(nread, sizeof(buf));
igt_assert_eq(get_vblank(data->fd, 0, 0), vblank_start + 1);
igt_reset_timeout();
--
2.5.0
___
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[Intel-gfx] [PATCH i-g-t 2/2] lib/drmtest: Report proper err message when opening the driver.
Signed-off-by: Marius Vlad
CC: Chris Wilson
---
lib/drmtest.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 1e28f60..d2ee2d1 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -261,7 +261,17 @@ int __drm_open_driver(int chipset)
close(fd);
}
- igt_skip("No intel gpu found\n");
+ switch (chipset & (DRIVER_INTEL | DRIVER_VC4 | DRIVER_VGEM)) {
+ case DRIVER_INTEL:
+ igt_skip("No intel gpu found\n");
+ break;
+ case DRIVER_VC4:
+ igt_skip("No vc4 gpu found\n");
+ break;
+ case DRIVER_VGEM:
+ igt_skip("No vgem support found\n");
+ break;
+ }
return -1;
}
--
2.5.0
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Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config
The bspec says "These are basic methods that can be used for single and multi-pipe modes. For optimal power usage, the display driver can choose to use more advanced allocation techniques as desired." So we leave it up to the driver to optimize as it sees fit. -Original Message- From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] Sent: Thursday, June 16, 2016 4:20 PM To: Sripada, Radhakrishna Cc: intel-gfx; drm-intel-fi...@lists.freedesktop.org; Runyan, Arthur J Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config I believe we should use whatever BSpec recommends. If that is not the best behavior and block things out than the spec needs to be updated or a workaround documented there. Art? thoughts? On Mon, Jun 13, 2016 at 3:03 PM, Radhakrishna Sripada wrote: > The bspec suggests giving cursor planes a fixed allocation of 8 blocks > when running in a multi-CRTC configuration. However we have found > that this small allocation can only accommodate level > 0 watermarks on many platforms, which in turn prevents the system from > entering deeper sleep states. Let's use a slightly higher allocation > of 16 blocks for the cursor to increase our chances of enabling lower > power states. > > Signed-off-by: Radhakrishna Sripada > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c index 658a756..a949dac 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2933,7 +2933,8 @@ static unsigned int skl_cursor_allocation(int > num_active) > if (num_active == 1) > return 32; > > - return 8; > + /* higher than bspec recommendation (8) */ > + return 16; > } > > static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, > u32 reg) > -- > 1.9.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config
Thanks Art. I believe the commit message should be updated to reflect this is flexible. Probably coping and pasting this part of spec: "More allocation might be required to support deeper low power states." So I went now to the spec to review the code and besides the line above I also notice for this specific case BSpec actually recommend 8 * num_active. "For each enabled cursor CursorBufAlloc = 8" "BlocksAvailable = TotalBlocksAvailable - (8 * NumPipes)." What I believe in this code it should be return 8 * num_active instead of a fixed number of 8 or 16. Right? Thanks, Rodrigo. On Thu, Jun 23, 2016 at 12:20 PM, Runyan, Arthur J wrote: > The bspec says "These are basic methods that can be used for single and > multi-pipe modes. For optimal power usage, the display driver can choose to > use more advanced allocation techniques as desired." > So we leave it up to the driver to optimize as it sees fit. > > -Original Message- > From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] > Sent: Thursday, June 16, 2016 4:20 PM > To: Sripada, Radhakrishna > Cc: intel-gfx; drm-intel-fi...@lists.freedesktop.org; Runyan, Arthur J > Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in > multi-pipe config > > I believe we should use whatever BSpec recommends. > > If that is not the best behavior and block things out than the spec needs to > be updated or a workaround documented there. > > Art? thoughts? > > On Mon, Jun 13, 2016 at 3:03 PM, Radhakrishna Sripada > wrote: >> The bspec suggests giving cursor planes a fixed allocation of 8 blocks >> when running in a multi-CRTC configuration. However we have found >> that this small allocation can only accommodate level >> 0 watermarks on many platforms, which in turn prevents the system from >> entering deeper sleep states. Let's use a slightly higher allocation >> of 16 blocks for the cursor to increase our chances of enabling lower >> power states. >> >> Signed-off-by: Radhakrishna Sripada >> Signed-off-by: Matt Roper >> --- >> drivers/gpu/drm/i915/intel_pm.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c >> b/drivers/gpu/drm/i915/intel_pm.c index 658a756..a949dac 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -2933,7 +2933,8 @@ static unsigned int skl_cursor_allocation(int >> num_active) >> if (num_active == 1) >> return 32; >> >> - return 8; >> + /* higher than bspec recommendation (8) */ >> + return 16; >> } >> >> static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, >> u32 reg) >> -- >> 1.9.1 >> >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/{kms_cursor_legacy, drv_missed_irq}, lib/drmtest: Fix warnings about unused function return values.
On Thu, Jun 23, 2016 at 07:46:02PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
> CC: Chris Wilson
> ---
> lib/drmtest.c | 8 +++-
> tests/drv_missed_irq.c| 2 +-
> tests/kms_cursor_legacy.c | 8 ++--
> 3 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 9a1232f..1e28f60 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -218,11 +218,11 @@ int drm_get_card(void)
> return -1;
> }
>
> -static void modprobe(const char *driver)
> +static int modprobe(const char *driver)
> {
> char buf[128];
> snprintf(buf, sizeof(buf), "/sbin/modprobe -s %s", driver);
> - system(buf);
> + return system(buf);
> }
>
> /**
> @@ -236,8 +236,6 @@ static void modprobe(const char *driver)
> */
> int __drm_open_driver(int chipset)
> {
> - if (chipset & DRIVER_VGEM)
> - modprobe("vgem");
If you don't modprobe it first...
> for (int i = 0; i < 16; i++) {
> char name[80];
> @@ -258,7 +256,7 @@ int __drm_open_driver(int chipset)
>
> if (chipset & DRIVER_VGEM &&
> is_vgem_device(fd))
> - return fd;
> + return (modprobe("vgem") == -1) ? -1 : fd;
it won't be available as /dev/dri/cardN.
As I noted, we do *NOT* care about the return value of the system call.
> close(fd);
> }
> diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c
> index 66d20ed..130a6aa 100644
> --- a/tests/drv_missed_irq.c
> +++ b/tests/drv_missed_irq.c
> @@ -130,7 +130,7 @@ igt_simple_main
> fclose(file);
>
> file = igt_debugfs_fopen("i915_ring_test_irq", "r");
> - fscanf(file, "%x", &expect_rings);
> + igt_assert_eq(fscanf(file, "%x", &expect_rings), 1);
NO.
> fclose(file);
>
> igt_debug("Testing rings %x\n", expect_rings);
> diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c
> index 00890c9..2228e99 100644
> --- a/tests/kms_cursor_legacy.c
> +++ b/tests/kms_cursor_legacy.c
> @@ -238,6 +238,7 @@ static void flip(struct data *data,
> }
> igt_fork(child, 1) {
> unsigned long count = 0;
> + ssize_t nread;
> unsigned crtc = data->resources->crtcs[flip_pipe];
>
> igt_until_timeout(timeout) {
> @@ -245,7 +246,8 @@ static void flip(struct data *data,
> drmModePageFlip(data->fd, crtc, fb_id,
> DRM_MODE_PAGE_FLIP_EVENT,
> NULL);
> - read(data->fd, buf, sizeof(buf));
> + nread = read(data->fd, buf, sizeof(buf));
> + igt_assert_eq(nread, sizeof(buf));
NO.
> count++;
> }
>
> @@ -286,6 +288,7 @@ static void basic_flip(struct data *data)
> struct igt_fb fb_info;
> unsigned vblank_start;
> int target;
> + ssize_t nread;
> struct drm_event buf;
> uint32_t fb_id;
>
> @@ -338,7 +341,8 @@ static void basic_flip(struct data *data)
> igt_assert_eq(get_vblank(data->fd, 0, 0), vblank_start);
>
> igt_set_timeout(1, "Stuck page flip");
> - read(data->fd, &buf, sizeof(buf));
> + nread = read(data->fd, &buf, sizeof(buf));
NO, NO, NO.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH i-g-t 2/2] lib/drmtest: Report proper err message when opening the driver.
On Thu, Jun 23, 2016 at 07:46:03PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
> CC: Chris Wilson
> ---
> lib/drmtest.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 1e28f60..d2ee2d1 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -261,7 +261,17 @@ int __drm_open_driver(int chipset)
> close(fd);
> }
>
> - igt_skip("No intel gpu found\n");
> + switch (chipset & (DRIVER_INTEL | DRIVER_VC4 | DRIVER_VGEM)) {
> + case DRIVER_INTEL:
> + igt_skip("No intel gpu found\n");
> + break;
> + case DRIVER_VC4:
> + igt_skip("No vc4 gpu found\n");
> + break;
> + case DRIVER_VGEM:
> + igt_skip("No vgem support found\n");
> + break;
That is just as silly as the first error message.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config
That part is trying to just allocate 8 to each cursor. The buffer used up will be 8*numpipes, but that's because its assuming you can end up enabling a cursor on each pipe. I think its good to go up to 16. The kind of latencies we get on skl mean that a 64x64 32bpp cursor with 8 blocks will be restricting package C states even at 1920x1080 60hz. The 8 number was based on what hardware did for allocation on past projects. -Original Message- From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] Sent: Thursday, June 23, 2016 12:50 PM To: Runyan, Arthur J Cc: Sripada, Radhakrishna; intel-gfx; drm-intel-fi...@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config Thanks Art. I believe the commit message should be updated to reflect this is flexible. Probably coping and pasting this part of spec: "More allocation might be required to support deeper low power states." So I went now to the spec to review the code and besides the line above I also notice for this specific case BSpec actually recommend 8 * num_active. "For each enabled cursor CursorBufAlloc = 8" "BlocksAvailable = TotalBlocksAvailable - (8 * NumPipes)." What I believe in this code it should be return 8 * num_active instead of a fixed number of 8 or 16. Right? Thanks, Rodrigo. On Thu, Jun 23, 2016 at 12:20 PM, Runyan, Arthur J wrote: > The bspec says "These are basic methods that can be used for single and > multi-pipe modes. For optimal power usage, the display driver can choose to > use more advanced allocation techniques as desired." > So we leave it up to the driver to optimize as it sees fit. > > -Original Message- > From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] > Sent: Thursday, June 16, 2016 4:20 PM > To: Sripada, Radhakrishna > Cc: intel-gfx; drm-intel-fi...@lists.freedesktop.org; Runyan, Arthur J > Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb > blocks in multi-pipe config > > I believe we should use whatever BSpec recommends. > > If that is not the best behavior and block things out than the spec needs to > be updated or a workaround documented there. > > Art? thoughts? > > On Mon, Jun 13, 2016 at 3:03 PM, Radhakrishna Sripada > wrote: >> The bspec suggests giving cursor planes a fixed allocation of 8 >> blocks when running in a multi-CRTC configuration. However we have >> found that this small allocation can only accommodate level >> 0 watermarks on many platforms, which in turn prevents the system >> from entering deeper sleep states. Let's use a slightly higher >> allocation of 16 blocks for the cursor to increase our chances of >> enabling lower power states. >> >> Signed-off-by: Radhakrishna Sripada >> Signed-off-by: Matt Roper >> --- >> drivers/gpu/drm/i915/intel_pm.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c >> b/drivers/gpu/drm/i915/intel_pm.c index 658a756..a949dac 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -2933,7 +2933,8 @@ static unsigned int skl_cursor_allocation(int >> num_active) >> if (num_active == 1) >> return 32; >> >> - return 8; >> + /* higher than bspec recommendation (8) */ >> + return 16; >> } >> >> static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, >> u32 reg) >> -- >> 1.9.1 >> >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] lib/intel_chipset: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs. Signed-off-by: Rodrigo Vivi --- lib/intel_chipset.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 2f2e435..1c894d5 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -213,7 +213,9 @@ void intel_check_pch(void); #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 #define PCI_CHIP_KABYLAKE_ULT_GT1_50x5913 #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT3_00x5923 +#define PCI_CHIP_KABYLAKE_ULT_GT3_10x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT3_20x5927 #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 #define PCI_CHIP_KABYLAKE_ULX_GT1_50x5915 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E @@ -224,7 +226,8 @@ void intel_check_pch(void); #define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B -#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_H_GT1_0 0x5908 +#define PCI_CHIP_KABYLAKE_H_GT1_1 0x590B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A #define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A @@ -430,7 +433,8 @@ void intel_check_pch(void); (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \ +(devid) == PCI_CHIP_KABYLAKE_H_GT1_0|| \ +(devid) == PCI_CHIP_KABYLAKE_H_GT1_1|| \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \ @@ -441,7 +445,9 @@ void intel_check_pch(void); (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \ +#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0|| \ +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1|| \ +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2|| \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs. Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 9094599..87dde1c 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -309,6 +309,7 @@ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ @@ -322,7 +323,9 @@ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ #define INTEL_KBL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] pciids: : Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Signed-off-by: Rodrigo Vivi --- src/i915_pciids.h | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/i915_pciids.h b/src/i915_pciids.h index 87dde1c..33466bf 100644 --- a/src/i915_pciids.h +++ b/src/i915_pciids.h @@ -325,15 +325,10 @@ #define INTEL_KBL_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ - INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ #define INTEL_KBL_GT4_IDS(info) \ - INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ - INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ - INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ - INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] intel: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs. Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index e2554c3..0c3ca82 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -194,7 +194,9 @@ #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 #define PCI_CHIP_KABYLAKE_ULT_GT1_50x5913 #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT3_00x5923 +#define PCI_CHIP_KABYLAKE_ULT_GT3_10x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT3_20x5927 #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 #define PCI_CHIP_KABYLAKE_ULX_GT1_50x5915 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E @@ -206,7 +208,8 @@ #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B #define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B -#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_H_GT1_0 0x5908 +#define PCI_CHIP_KABYLAKE_H_GT1_1 0x590B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A #define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A @@ -414,7 +417,8 @@ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT1 || \ +(devid) == PCI_CHIP_KABYLAKE_H_GT1_0 || \ +(devid) == PCI_CHIP_KABYLAKE_H_GT1_1 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ @@ -425,7 +429,9 @@ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3 || \ +#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT3 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] i956: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs. Signed-off-by: Rodrigo Vivi --- include/pci_ids/i965_pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index fce00da..7a7897f 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -137,6 +137,7 @@ CHIPSET(0x193D, skl_gt4, "Intel(R) Iris Pro Graphics P580 (Skylake GT4e)") CHIPSET(0x5902, kbl_gt1, "Intel(R) Kabylake GT1") CHIPSET(0x5906, kbl_gt1, "Intel(R) Kabylake GT1") CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x5908, kbl_gt1, "Intel(R) Kabylake GT1") CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1") CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1") CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5") @@ -149,7 +150,9 @@ CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2") CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2") CHIPSET(0x591E, kbl_gt2, "Intel(R) Kabylake GT2") CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") +CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x5926, kbl_gt3, "Intel(R) Kabylake GT3") +CHIPSET(0x5927, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x592A, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x592B, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x5932, kbl_gt4, "Intel(R) Kabylake GT4") -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] lib/intel_chipset: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Signed-off-by: Rodrigo Vivi --- lib/intel_chipset.h | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 1c894d5..3967468 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -223,18 +223,13 @@ void intel_check_pch(void); #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B #define PCI_CHIP_KABYLAKE_H_GT1_0 0x5908 #define PCI_CHIP_KABYLAKE_H_GT1_1 0x590B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A -#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D -#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 @@ -447,14 +442,9 @@ void intel_check_pch(void); #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0|| \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1|| \ -(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2|| \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ -(devid) == PCI_CHIP_KABYLAKE_SRV_GT3) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \ -(devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \ -(devid) == PCI_CHIP_KABYLAKE_WKS_GT4) +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) + +#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ IS_KBL_GT2(devid) || \ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] intel: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 0c3ca82..79c152e 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -204,18 +204,13 @@ #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B #define PCI_CHIP_KABYLAKE_H_GT1_0 0x5908 #define PCI_CHIP_KABYLAKE_H_GT1_1 0x590B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D -#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 @@ -431,14 +426,9 @@ #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ -(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2 || \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT3 || \ -(devid) == PCI_CHIP_KABYLAKE_SRV_GT3) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \ -(devid) == PCI_CHIP_KABYLAKE_HALO_GT4 || \ -(devid) == PCI_CHIP_KABYLAKE_SRV_GT4 || \ -(devid) == PCI_CHIP_KABYLAKE_WKS_GT4) +(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) + +#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ IS_KBL_GT2(devid) || \ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] pciids: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs. Signed-off-by: Rodrigo Vivi --- src/i915_pciids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/i915_pciids.h b/src/i915_pciids.h index 9094599..87dde1c 100644 --- a/src/i915_pciids.h +++ b/src/i915_pciids.h @@ -309,6 +309,7 @@ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ @@ -322,7 +323,9 @@ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ #define INTEL_KBL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] i965: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Signed-off-by: Rodrigo Vivi --- include/pci_ids/i965_pci_ids.h | 5 - 1 file changed, 5 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 7a7897f..1566afd 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -153,12 +153,7 @@ CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x5926, kbl_gt3, "Intel(R) Kabylake GT3") CHIPSET(0x5927, kbl_gt3, "Intel(R) Kabylake GT3") -CHIPSET(0x592A, kbl_gt3, "Intel(R) Kabylake GT3") -CHIPSET(0x592B, kbl_gt3, "Intel(R) Kabylake GT3") -CHIPSET(0x5932, kbl_gt4, "Intel(R) Kabylake GT4") -CHIPSET(0x593A, kbl_gt4, "Intel(R) Kabylake GT4") CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") -CHIPSET(0x593D, kbl_gt4, "Intel(R) Kabylake GT4") CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherrytrail)") CHIPSET(0x22B1, chv, "Intel(R) HD Graphics XXX (Braswell)") /* Overridden in brw_get_renderer_string */ CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 87dde1c..33466bf 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -325,15 +325,10 @@ #define INTEL_KBL_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ - INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ #define INTEL_KBL_GT4_IDS(info) \ - INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ - INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ - INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ - INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ -- 2.5.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC loading status check
> -Original Message-
> From: Thierry, Michel
> Sent: Thursday, June 23, 2016 3:48 AM
> To: Antoine, Peter ; Xiang, Haihao
> ; daniel.vet...@ffwll.ch
> Cc: Kelley, Sean V ; intel-
> g...@lists.freedesktop.org; Li, Lawrence T ; Vivi,
> Rodrigo
> Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/huc: Add debugfs for HuC
> loading status check
>
> On 6/23/2016 11:01 AM, Peter Antoine wrote:
> > Daniel,
> >
> > Is this suggestion acceptable? I don't want to waste time and effort
> > writing code that is not going to be accepted?
> >
> > Peter.
> >
>
> Reuse I915_GETPARAM and do more-less what Chris did for
> i915.enable_gvt? [1]
>
>
> [1]
> https://cgit.freedesktop.org/drm-
> intel/commit/?id=7822492fd21a44eeb3568082b0ab915df7388061
Something along those lines would work for me with our media UMD.
Thanks,
Sean
>
> > On Thu, 23 Jun 2016, Xiang, Haihao wrote:
> >
> >>
> >> Hi Peter,
> >>
> >> Besides debugfs, could you add a IOCTL to check HuC loading status?
> >> Userspace media driver needs to advertise the features based on HuC
> >> to user.
> >>
> >> Thanks
> >> Haihao
> >>
> >>
> >>> From: Alex Dai
> >>>
> >>> Add debugfs entry for HuC loading status check.
> >>>
> >>> Signed-off-by: Alex Dai
> >>> Signed-off-by: Peter Antoine
> >>> ---
> >>> drivers/gpu/drm/i915/i915_debugfs.c | 32
> >>>
> >>> 1 file changed, 32 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> >>> b/drivers/gpu/drm/i915/i915_debugfs.c
> >>> index 69964c2..f5976f8 100644
> >>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >>> @@ -2479,6 +2479,37 @@ static int i915_llc(struct seq_file *m, void
> >>> *data)
> >>> return 0;
> >>> }
> >>>
> >>> +static int i915_huc_load_status_info(struct seq_file *m, void
> >>> +*data) {
> >>> +struct drm_info_node *node = m->private;
> >>> +struct drm_i915_private *dev_priv = node->minor->dev-
> dev_private;
> >>> +struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> >>> +
> >>> +if (!HAS_HUC_UCODE(dev_priv->dev))
> >>> +return 0;
> >>> +
> >>> +seq_puts(m, "HuC firmware status:\n");
> >>> +seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> >>> +seq_printf(m, "\tfetch: %s\n",
> >>> +intel_uc_fw_status_repr(huc_fw->fetch_status));
> >>> +seq_printf(m, "\tload: %s\n",
> >>> +intel_uc_fw_status_repr(huc_fw->load_status));
> >>> +seq_printf(m, "\tversion wanted: %d.%d\n",
> >>> +huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> >>> +seq_printf(m, "\tversion found: %d.%d\n",
> >>> +huc_fw->major_ver_found, huc_fw->minor_ver_found);
> >>> +seq_printf(m, "\theader: offset is %d; size = %d\n",
> >>> +huc_fw->header_offset, huc_fw->header_size);
> >>> +seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> >>> +huc_fw->ucode_offset, huc_fw->ucode_size);
> >>> +seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> >>> +huc_fw->rsa_offset, huc_fw->rsa_size);
> >>> +
> >>> +seq_printf(m, "\nHuC status 0x%08x:\n",
> >>> I915_READ(HUC_STATUS2));
> >>> +
> >>> +return 0;
> >>> +}
> >>> +
> >>> static int i915_guc_load_status_info(struct seq_file *m, void
> >>> *data) {
> >>> struct drm_info_node *node = m->private; @@ -5432,6 +5463,7 @@
> >>> static const struct drm_info_list i915_debugfs_list[] = {
> >>> {"i915_guc_info", i915_guc_info, 0},
> >>> {"i915_guc_load_status", i915_guc_load_status_info, 0},
> >>> {"i915_guc_log_dump", i915_guc_log_dump, 0},
> >>> +{"i915_huc_load_status", i915_huc_load_status_info, 0},
> >>> {"i915_frequency_info", i915_frequency_info, 0},
> >>> {"i915_hangcheck_info", i915_hangcheck_info, 0},
> >>> {"i915_drpc_info", i915_drpc_info, 0},
> >
> > --
> > Peter Antoine (Android Graphics Driver Software Engineer)
> > -
> > Intel Corporation (UK) Limited
> > Registered No. 1134945 (England)
> > Registered Office: Pipers Way, Swindon SN3 1RJ
> > VAT No: 860 2173 47
> >
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[Intel-gfx] drm/i915: Delay with fbc enabled
Hello, since Kernel 4.6, the fbc is broken for me. Some specific X software (e.g. wireshark-qt, sakura and sublime) display UI modifications, such as keyboard input, with a delay up to ~1s. Either downgrading to 4.5 or disabling fbc solve this problem. This affects at least multiple Thinkpad and other users on Arch Linux: https://bugs.archlinux.org/task/49623 I am no expert in this. So if I could provide anything more useful for you, please let me know. -- Grüße/Regards Manuel Groß ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
