[Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
== Series Details == Series: series starting with [01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() URL : https://patchwork.freedesktop.org/series/10246/ State : warning == Summary == Series 10246v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/10246/revisions/1/mbox Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-skl-i5-6260u) Test gem_sync: Subgroup basic-store-each: pass -> SKIP (ro-bdw-i7-5600u) pass -> SKIP (ro-bdw-i5-5250u) fi-skl-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12 fi-skl-i7-6700k total:235 pass:209 dwarn:0 dfail:0 fail:0 skip:26 fi-snb-i7-2600 total:235 pass:195 dwarn:0 dfail:0 fail:0 skip:40 ro-bdw-i5-5250u total:235 pass:217 dwarn:4 dfail:0 fail:0 skip:14 ro-bdw-i7-5557U total:235 pass:218 dwarn:3 dfail:0 fail:0 skip:14 ro-bdw-i7-5600u total:235 pass:203 dwarn:0 dfail:0 fail:0 skip:32 ro-bsw-n3050 total:235 pass:191 dwarn:0 dfail:0 fail:1 skip:43 ro-byt-n2820 total:235 pass:196 dwarn:0 dfail:0 fail:1 skip:38 ro-hsw-i3-4010u total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24 ro-hsw-i7-4770r total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24 ro-ilk-i7-620lm total:235 pass:171 dwarn:0 dfail:0 fail:1 skip:63 ro-ilk1-i5-650 total:230 pass:171 dwarn:0 dfail:0 fail:1 skip:58 ro-ivb-i7-3770 total:235 pass:202 dwarn:0 dfail:0 fail:0 skip:33 ro-skl3-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12 ro-snb-i7-2620M total:235 pass:193 dwarn:0 dfail:0 fail:1 skip:41 fi-hsw-i7-4770k failed to connect after reboot fi-kbl-qkkr failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1600/ 5c9e3d9 drm-intel-nightly: 2016y-07m-25d-06h-32m-37s UTC integration manifest 3a6c9ea Revert "drm/i915: Clean up associated VMAs on context destruction" 104e392 drm/i915: Mark the context and address space as closed ab44ea4 drm/i915: Release vma when the handle is closed 036a52b drm/i915: Track active vma requests 2228d78 drm/i915: i915_vma_move_to_active prep patch ed8d84b drm/i915: Move request list retirement to i915_gem_request.c 859cf08 drm/i915: Double check activity before relocations 6b6e54a drm/i915: s/__i915_wait_request/i915_wait_request/ a982b45 drm/i915: Disable waitboosting for a saturated engine 82ae751 drm/i915: Move the special case wait-request handling to its one caller c3068e1 drm/i915: Convert intel_overlay to request tracking c8e87f4 drm/i915: Track requests inside each intel_ring 16410e2 drm/i915: Refactor activity tracking for requests dc9a175 drm/i915: Remove obsolete i915_gem_object_flush_active() 344267b drm/i915: Rename request->list to link for consistency 847bf87 drm/i915: Refactor blocking waits 129d043 drm/i915: Mark up i915_gem_active for locking annotation 35ae483 drm/i915: Prepare i915_gem_active for annotations e3d1035 drm/i915: Introduce i915_gem_active for request tracking d30434e drm/i915: Kill drop_pages() 9dea465 drm/i915: Be more careful when unbinding vma 6a05061 drm/i915: Count how many VMA are bound for an object bfaea2a drm/i915: Store owning file on the i915_address_space efc808f drm/i915: Split early global GTT initialisation c880e6e drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers 67995be drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals 59f8fce drm/i915: Simplify calling engine->sync_to 18b15e1 drm/i915: Unify legacy/execlists submit_execbuf callbacks e08e8c3 drm/i915: Refactor golden render state emission to unconfuse gcc dfe4e0f drm/i915: Remove duplicate golden render state init from execlists d129ca2 drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores d75b5e2 drm/i915: Reuse legacy breadcrumbs + tail emission c8ef3d6 drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal() 651c830 drm/i915/lrc: Update function names to match request flow ab762f1 drm/i915: Unify request submission 9538f16 drm/i915: Convert engine->write_tail to operate on a request 021c340 drm/i915: Remove intel_ring_get_tail() 991637b drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START a8a086d drm/i915: Simplify request_alloc by returning the allocated request 10bda31 drm/i915: Remove obsolete engine->gpu_caches_dirty b66909e drm/i915: Rename intel_pin_and_map_ring() d1c2132 drm/i915: Rename residual ringbuf parameters db81db7 drm/i915: Rename struct intel_ringbuffer to struct intel_ring edf9a57 drm/i915: Rename intel_context[engine].ringbuf 3bb63b1 drm/i915: Rename request->ringbuf to request->ring c085269 drm/i915: Unify intel_logical_ring_emit and intel_ring_emit 5806a2f drm/i915: Update a couple of hangcheck comments to talk about engines 64de0a6 drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c c3ebb54 drm/i9
Re: [Intel-gfx] [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
On ma, 2016-07-25 at 18:32 +0100, Chris Wilson wrote:
> As we can now have multiple VMA inside the global GTT (with partial
> mappings, rotations, etc), it is no longer true that there may just be a
> single GGTT entry and so we should walk the full vma_list to count up
> the actual usage. In addition to unifying the two walkers, switch from
> multiplying the object size for each vma to summing the bound vma sizes.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 46
> +++--
> 1 file changed, 18 insertions(+), 28 deletions(-)
>
>
> @@ -342,41 +343,30 @@ static int per_file_stats(int id, void *ptr, void *data)
> if (obj->base.name || obj->base.dma_buf)
> stats->shared += obj->base.size;
>
> - if (USES_FULL_PPGTT(obj->base.dev)) {
> - list_for_each_entry(vma, &obj->vma_list, obj_link) {
> - struct i915_hw_ppgtt *ppgtt;
> + list_for_each_entry(vma, &obj->vma_list, obj_link) {
> + if (!drm_mm_node_allocated(&vma->node))
> + continue;
>
> - if (!drm_mm_node_allocated(&vma->node))
> - continue;
> + bound++;
>
> - if (vma->is_ggtt) {
> - stats->global += obj->base.size;
> - continue;
> - }
> -
> - ppgtt = container_of(vma->vm, struct i915_hw_ppgtt,
> base);
> + if (vma->is_ggtt) {
> + stats->global += vma->node.size;
> + } else {
> + struct i915_hw_ppgtt *ppgtt
> + = container_of(vma->vm,
> + struct i915_hw_ppgtt,
> + base);
Use i915_vm_to_ppgtt(vma->vm). With that,
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> If is simpler and leads to more readable code through the callstack if
> the allocation returns the allocated struct through the return value.
>
> The importance of this is that it no longer looks like we accidentally
> allocate requests as side-effect of calling certain functions.
>
I already added in previous series; CC'ing Dave again.
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-19-git-send-email-ch...@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_drv.h| 3 +-
> drivers/gpu/drm/i915/i915_gem.c| 75
> --
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++---
> drivers/gpu/drm/i915/i915_gem_request.c| 58 ---
> drivers/gpu/drm/i915/i915_trace.h | 13 +++---
> drivers/gpu/drm/i915/intel_display.c | 36 ++
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_overlay.c | 20
> 8 files changed, 79 insertions(+), 140 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7e298b4253e..2259983d2ec6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3171,8 +3171,7 @@ static inline void i915_gem_object_unpin_map(struct
> drm_i915_gem_object *obj)
>
> int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
> int i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request **to_req);
> + struct drm_i915_gem_request *to);
> void i915_vma_move_to_active(struct i915_vma *vma,
> struct drm_i915_gem_request *req);
> int i915_gem_dumb_create(struct drm_file *file_priv,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 59890f523c5f..b6c4ff63725f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2845,51 +2845,35 @@ out:
>
> static int
> __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request *from_req,
> - struct drm_i915_gem_request **to_req)
> + struct drm_i915_gem_request *to,
> + struct drm_i915_gem_request *from)
> {
> - struct intel_engine_cs *from;
> int ret;
>
> - from = i915_gem_request_get_engine(from_req);
> - if (to == from)
> + if (to->engine == from->engine)
> return 0;
>
> - if (i915_gem_request_completed(from_req))
> + if (i915_gem_request_completed(from))
> return 0;
>
> if (!i915.semaphores) {
> - struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - ret = __i915_wait_request(from_req,
> - i915->mm.interruptible,
> + ret = __i915_wait_request(from,
> + from->i915->mm.interruptible,
> NULL,
> NO_WAITBOOST);
> if (ret)
> return ret;
>
> - i915_gem_object_retire_request(obj, from_req);
> + i915_gem_object_retire_request(obj, from);
> } else {
> - int idx = intel_engine_sync_index(from, to);
> - u32 seqno = i915_gem_request_get_seqno(from_req);
> + int idx = intel_engine_sync_index(from->engine, to->engine);
> + u32 seqno = i915_gem_request_get_seqno(from);
>
> - WARN_ON(!to_req);
> -
> - if (seqno <= from->semaphore.sync_seqno[idx])
> + if (seqno <= from->engine->semaphore.sync_seqno[idx])
> return 0;
>
> - if (*to_req == NULL) {
> - struct drm_i915_gem_request *req;
> -
> - req = i915_gem_request_alloc(to, NULL);
> - if (IS_ERR(req))
> - return PTR_ERR(req);
> -
> - *to_req = req;
> - }
> -
> - trace_i915_gem_ring_sync_to(*to_req, from, from_req);
> - ret = to->semaphore.sync_to(*to_req, from, seqno);
> + trace_i915_gem_ring_sync_to(to, from);
> + ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
> if (ret)
> return ret;
>
> @@ -2897,8 +2881,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> * might have just caused seqno wrap under
> * the radar.
> */
> - from->semaphore.sync_seqno[idx] =
> -
> i915_gem_request_get_seqno(obj->last_read_req[from->id]);
>
Re: [Intel-gfx] [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Since intel_engine_enable_signaling() is now only called via
> fence_enable_sw_signaling(), we can rely on it to provide serialisation
> and run-once for us and so make ourselves slightly simpler.
>
Done in previous series, copying here;
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-2-git-send-email-ch...@chris-wilson.co.uk
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index d893ccdd62ac..90867446f1a5 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -480,19 +480,15 @@ void intel_engine_enable_signaling(struct
> drm_i915_gem_request *request)
> struct rb_node *parent, **p;
> bool first, wakeup;
>
> - if (unlikely(READ_ONCE(request->signaling.wait.tsk)))
> - return;
> -
> - spin_lock(&b->lock);
> - if (unlikely(request->signaling.wait.tsk)) {
> - wakeup = false;
> - goto unlock;
> - }
> + /* locked by fence_enable_sw_signaling() */
> + assert_spin_locked(&request->lock);
>
> request->signaling.wait.tsk = b->signaler;
> request->signaling.wait.seqno = request->fence.seqno;
> i915_gem_request_get(request);
>
> + spin_lock(&b->lock);
> +
> /* First add ourselves into the list of waiters, but register our
> * bottom-half as the signaller thread. As per usual, only the oldest
> * waiter (not just signaller) is tasked as the bottom-half waking
> @@ -525,7 +521,6 @@ void intel_engine_enable_signaling(struct
> drm_i915_gem_request *request)
> if (first)
> smp_store_mb(b->first_signal, request);
>
> -unlock:
> spin_unlock(&b->lock);
>
> if (wakeup)
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Space for flushing the GPU cache prior to completing the request is
> preallocated and so cannot fail - the GPU caches will always be flushed
> along with the completed request. This means we no longer have to track
> whether the GPU cache is dirty between batches like we had to with the
> outstanding_lazy_seqno.
>
> With the removal of the duplication in the per-backend entry points for
> emitting the obsolete lazy flush, we can then further unify the
> engine->emit_flush.
>
> v2: Expand a bit on the legacy of gpu_caches_dirty
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-ch...@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_gem_context.c| 2 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +---
> drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++--
> drivers/gpu/drm/i915/i915_gem_request.c| 8 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 47 +++
> drivers/gpu/drm/i915/intel_lrc.h | 2 -
> drivers/gpu/drm/i915/intel_ringbuffer.c| 72
> +++---
> drivers/gpu/drm/i915/intel_ringbuffer.h| 7 ---
> 8 files changed, 37 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 3336a5fcd029..beece8feb8fe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32
> hw_flags)
> * itlb_before_ctx_switch.
> */
> if (IS_GEN6(dev_priv)) {
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
> + ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index d0ef675fb169..35c4c595e5ba 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct
> drm_i915_gem_request *req,
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
>
> - /* Unconditionally invalidate gpu caches and ensure that we do flush
> - * any residual writes from the previous batch.
> - */
> - return intel_engine_invalidate_all_caches(req);
> + /* Unconditionally invalidate GPU caches and TLBs. */
> + return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> }
>
> static bool
> @@ -1163,9 +1161,6 @@ i915_gem_execbuffer_move_to_active(struct list_head
> *vmas,
> static void
> i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
> {
> - /* Unconditionally force add_request to emit a full flush. */
> - params->engine->gpu_caches_dirty = true;
> -
> /* Add a breadcrumb for the completion of the batch buffer */
> __i915_add_request(params->request, params->batch_obj, true);
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ebfa0406a6a1..39fa9eb10514 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1666,7 +1666,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1693,7 +1694,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1711,8 +1713,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>
> /* XXX: RCS is the only one to auto invalidate the TLBs? */
> if (engine->id != RCS) {
> - ret = engine->flush(req,
> - I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
> b/drivers/gpu/drm/i915/i915_gem_request.c
> index 942b5b1f1602..7e3206051ced 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_requ
Re: [Intel-gfx] [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> A few places we use ring when referring to the struct intel_engine_cs. An
> anachronism we are pruning out.
>
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-ch...@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_gem.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e155e8dd28ed..7bfce1d5c61b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct
> drm_i915_gem_object *o
> static void
> i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
> static void
> -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
> +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
I vote for engine_idx variable name, that much I dislike differing
naming in signature and implementation.
Regards, Joonas
>
> static bool cpu_cache_is_coherent(struct drm_device *dev,
> enum i915_cache_level level)
> @@ -1385,10 +1385,10 @@ static void
> i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_request *req)
> {
> - int ring = req->engine->id;
> + int idx = req->engine->id;
>
> - if (obj->last_read_req[ring] == req)
> - i915_gem_object_retire__read(obj, ring);
> + if (obj->last_read_req[idx] == req)
> + i915_gem_object_retire__read(obj, idx);
> else if (obj->last_write_req == req)
> i915_gem_object_retire__write(obj);
>
> @@ -2381,20 +2381,20 @@ i915_gem_object_retire__write(struct
> drm_i915_gem_object *obj)
> }
>
> static void
> -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
> {
> struct i915_vma *vma;
>
> - GEM_BUG_ON(obj->last_read_req[ring] == NULL);
> - GEM_BUG_ON(!(obj->active & (1 << ring)));
> + GEM_BUG_ON(obj->last_read_req[idx] == NULL);
> + GEM_BUG_ON(!(obj->active & (1 << idx)));
>
> - list_del_init(&obj->engine_list[ring]);
> - i915_gem_request_assign(&obj->last_read_req[ring], NULL);
> + list_del_init(&obj->engine_list[idx]);
> + i915_gem_request_assign(&obj->last_read_req[idx], NULL);
>
> - if (obj->last_write_req && obj->last_write_req->engine->id == ring)
> + if (obj->last_write_req && obj->last_write_req->engine->id == idx)
> i915_gem_object_retire__write(obj);
>
> - obj->active &= ~(1 << ring);
> + obj->active &= ~(1 << idx);
> if (obj->active)
> return;
>
> @@ -4599,7 +4599,7 @@ int i915_gem_init(struct drm_device *dev)
>
> ret = i915_gem_init_hw(dev);
> if (ret == -EIO) {
> - /* Allow ring initialisation to fail by marking the GPU as
> + /* Allow engine initialisation to fail by marking the GPU as
> * wedged. But we only want to do this where the GPU is angry,
> * for all other failure, such as an allocation failure, bail.
> */
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
On ma, 2016-07-25 at 18:31 +0100, Chris Wilson wrote:
> Inside the error capture itself, we refer to not only the hardware
> engine, its ringbuffer but also the capture state. Finding clear names
> for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
> compromise we keep using ering for the error capture.
>
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-ch...@chris-wilson.co.uk
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 255
> +-
> 2 files changed, 134 insertions(+), 127 deletions(-)
>
> @@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum
> intel_ring_hangcheck_action a)
> }
>
> static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> - struct drm_device *dev,
> - struct drm_i915_error_state *error,
> - int ring_idx)
> + struct drm_device *dev,
> + struct drm_i915_error_state *error,
> + int engine_idx)
> {
> - struct drm_i915_error_ring *ring = &error->ring[ring_idx];
> + struct drm_i915_error_engine *ering = &error->engine[engine_idx];
>
I'd be inclined keeping the struct and variable names close, so rather
eengine. Even though the error state is a mashup. We fill the ring
state to the engine error state. Function could be
i915_engine_error_ring_state() or so, to "reduce" confusion?
> @@ -414,7 +416,7 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> if (IS_GEN7(dev))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> - for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> + for (i = 0; i < ARRAY_SIZE(error->engine); i++)
> i915_ring_error_state(m, dev, error, i);
>
This captures the engine related ring state, I think it's even worth a
comment when there is engine vs. error disparity.
And how about the messages? Should we update them more agressively
where necessary.
Regards, Joonas
--
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 01/31] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Since intel_engine_enable_signaling() is now only called via
> fence_enable_sw_signaling(), we can rely on it to provide serialisation
> and run-once for us and so make ourselves slightly simpler.
>
Originally left this patch for Tvrtko, not remembering he's traveling.
assert_spin_locked() should make this enough robust that it'll still do
what it did perviously.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index d893ccdd62ac..90867446f1a5 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -480,19 +480,15 @@ void intel_engine_enable_signaling(struct
> drm_i915_gem_request *request)
> struct rb_node *parent, **p;
> bool first, wakeup;
>
> - if (unlikely(READ_ONCE(request->signaling.wait.tsk)))
> - return;
> -
> - spin_lock(&b->lock);
> - if (unlikely(request->signaling.wait.tsk)) {
> - wakeup = false;
> - goto unlock;
> - }
> + /* locked by fence_enable_sw_signaling() */
> + assert_spin_locked(&request->lock);
>
> request->signaling.wait.tsk = b->signaler;
> request->signaling.wait.seqno = request->fence.seqno;
> i915_gem_request_get(request);
>
> + spin_lock(&b->lock);
> +
> /* First add ourselves into the list of waiters, but register our
> * bottom-half as the signaller thread. As per usual, only the oldest
> * waiter (not just signaller) is tasked as the bottom-half waking
> @@ -525,7 +521,6 @@ void intel_engine_enable_signaling(struct
> drm_i915_gem_request *request)
> if (first)
> smp_store_mb(b->first_signal, request);
>
> -unlock:
> spin_unlock(&b->lock);
>
> if (wakeup)
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH 32/55] drm/i915: Split early global GTT initialisation
Initialising the global GTT is tricky as we wish to use the drm_mm range
manager during the modesetting initialisation (to capture stolen
allocations from the BIOS) before we actually enable GEM. To overcome
this, we currently setup the drm_mm first and then carefully rebind
them.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c| 19 ---
drivers/gpu/drm/i915/i915_gem.c| 6 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c| 99 +-
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 17 +++---
5 files changed, 50 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 83afdd0597b5..478e8168ad94 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -993,8 +993,6 @@ static void intel_sanitize_options(struct drm_i915_private
*dev_priv)
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
- uint32_t aperture_size;
int ret;
if (i915_inject_load_failure())
@@ -1040,7 +1038,6 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
}
}
-
/* 965GM sometimes incorrectly writes to hardware status page (HWS)
* using 32bit addressing, overwriting memory if HWS is located
* above 4GB.
@@ -1059,19 +1056,6 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
}
}
- aperture_size = ggtt->mappable_end;
-
- ggtt->mappable =
- io_mapping_create_wc(ggtt->mappable_base,
-aperture_size);
- if (!ggtt->mappable) {
- ret = -EIO;
- goto out_ggtt;
- }
-
- ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
- aperture_size);
-
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
@@ -1112,14 +1096,11 @@ out_ggtt:
static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
if (dev->pdev->msi_enabled)
pci_disable_msi(dev->pdev);
pm_qos_remove_request(&dev_priv->pm_qos);
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_free(ggtt->mappable);
i915_ggtt_cleanup_hw(dev);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3df6b485d2d4..a0ea1ee16f67 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4543,7 +4543,10 @@ int i915_gem_init(struct drm_device *dev)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
i915_gem_init_userptr(dev_priv);
- i915_gem_init_ggtt(dev);
+
+ ret = i915_gem_init_ggtt(dev);
+ if (ret)
+ goto out_unlock;
ret = i915_gem_context_init(dev);
if (ret)
@@ -4634,7 +4637,6 @@ i915_gem_load_init(struct drm_device *dev)
SLAB_HWCACHE_ALIGN,
NULL);
- INIT_LIST_HEAD(&dev_priv->vm_list);
INIT_LIST_HEAD(&dev_priv->context_list);
INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
INIT_LIST_HEAD(&dev_priv->mm.bound_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 39fa9eb10514..44007ec344fd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2750,10 +2750,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node
*node,
*end -= 4096;
}
-static int i915_gem_setup_global_gtt(struct drm_device *dev,
-u64 start,
-u64 mappable_end,
-u64 end)
+int i915_gem_init_ggtt(struct drm_device *dev)
{
/* Let GEM Manage all of the aperture.
*
@@ -2766,46 +2763,14 @@ static int i915_gem_setup_global_gtt(struct drm_device
*dev,
*/
struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- struct drm_mm_node *entry;
- struct drm_i915_gem_object *obj;
unsigned long hole_start, hole_end;
+ struct drm_mm_node *entry;
int ret;
- BUG_ON(mappable_end > end);
-
- ggtt->base.start = start;
-
- /* Subtract the guard page before address space initialization to
-* shrink the range used by drm_mm */
- ggtt->base.total = end - start - PAGE_SIZE;
- i915_address_space_init(&ggtt->base, dev_priv);
- ggtt->base.total += PAGE_SIZE;
-
ret = intel_vgt_balloon(dev_priv);
if (ret)
return ret;
- if (!HAS_LLC(dev))
-
[Intel-gfx] [PATCH 30/55] drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals
In order to be more consistent with the rest of the request construction
and ring emission, use the common names for the ring and request.
Rather than using signaler_req, waiter_req, and intel_ring *wait, we use
plain req and ring.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-32-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 132
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +-
2 files changed, 68 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index df9f8a58a519..7be7666c894e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1322,108 +1322,105 @@ static void render_ring_cleanup(struct
intel_engine_cs *engine)
intel_fini_pipe_control(engine);
}
-static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
+static int gen8_rcs_signal(struct drm_i915_gem_request *req)
{
- struct intel_ring *signaller = signaller_req->ring;
- struct drm_i915_private *dev_priv = signaller_req->i915;
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
+ ret = intel_ring_begin(req, (num_rings-1) * 8);
if (ret)
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset =
- signaller_req->engine->semaphore.signal_ggtt[id];
+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring,
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_CS_STALL);
- intel_ring_emit(signaller, lower_32_bits(gtt_offset));
- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, signaller_req->fence.seqno);
- intel_ring_emit(signaller, 0);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, lower_32_bits(gtt_offset));
+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring,
MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter->hw_id));
- intel_ring_emit(signaller, 0);
+ intel_ring_emit(ring, 0);
}
- intel_ring_advance(signaller);
+ intel_ring_advance(ring);
return 0;
}
-static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
+static int gen8_xcs_signal(struct drm_i915_gem_request *req)
{
- struct intel_ring *signaller = signaller_req->ring;
- struct drm_i915_private *dev_priv = signaller_req->i915;
+ struct intel_ring *ring = req->ring;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
+ ret = intel_ring_begin(req, (num_rings-1) * 6);
if (ret)
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u64 gtt_offset =
- signaller_req->engine->semaphore.signal_ggtt[id];
+ u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller,
+ intel_ring_emit(ring,
(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring,
lower_32_bits(gtt_offset) |
MI_FLUSH_DW_USE_GTT);
- intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, signaller_req->fence.seqno);
- intel_ring_emit(signaller,
+ intel_ring_emit(ring, upper_32_bits(gtt_offset));
+ intel_ring_emit(ring, req->fence.seqno);
+ intel_ring_e
[Intel-gfx] [PATCH 42/55] drm/i915: Remove obsolete i915_gem_object_flush_active()
Since we track requests, and requests are always added to the GPU fully
formed, we never have to flush the incomplete request and know that the
given request will eventually complete without any further action on our
part.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 59 +++--
1 file changed, 3 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5be4eb0a397..3bff6b560f97 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2746,35 +2746,6 @@ out_rearm:
}
/**
- * Ensures that an object will eventually get non-busy by flushing any required
- * write domains, emitting any outstanding lazy request and retiring and
- * completed requests.
- * @obj: object to flush
- */
-static int
-i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
-{
- int i;
-
- if (!obj->active)
- return 0;
-
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_active_peek(&obj->last_read[i],
- &obj->base.dev->struct_mutex);
- if (req == NULL)
- continue;
-
- if (i915_gem_request_completed(req))
- i915_gem_object_retire__read(obj, i);
- }
-
- return 0;
-}
-
-/**
* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
* @dev: drm device pointer
* @data: ioctl data blob
@@ -2820,24 +2791,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return -ENOENT;
}
- /* Need to make sure the object gets inactive eventually. */
- ret = i915_gem_object_flush_active(obj);
- if (ret)
- goto out;
-
if (!obj->active)
goto out;
- /* Do this after OLR check to make sure we make forward progress polling
-* on this IOCTL with a timeout == 0 (like busy ioctl)
-*/
- if (args->timeout_ns == 0) {
- ret = -ETIME;
- goto out;
- }
-
- i915_gem_object_put(obj);
-
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct drm_i915_gem_request *req;
@@ -2847,6 +2803,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
requests[n++] = req;
}
+out:
+ i915_gem_object_put(obj);
mutex_unlock(&dev->struct_mutex);
for (i = 0; i < n; i++) {
@@ -2857,11 +2815,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
i915_gem_request_put(requests[i]);
}
return ret;
-
-out:
- i915_gem_object_put(obj);
- mutex_unlock(&dev->struct_mutex);
- return ret;
}
static int
@@ -4036,13 +3989,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
/* Count all active objects as busy, even if they are currently not used
* by the gpu. Users of this interface expect objects to eventually
-* become non-busy without any further actions, therefore emit any
-* necessary flushes here.
+* become non-busy without any further actions.
*/
- ret = i915_gem_object_flush_active(obj);
- if (ret)
- goto unref;
-
args->busy = 0;
if (obj->active) {
struct drm_i915_gem_request *req;
@@ -4060,7 +4008,6 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
args->busy |= req->engine->exec_id;
}
-unref:
i915_gem_object_put(obj);
unlock:
mutex_unlock(&dev->struct_mutex);
--
2.8.1
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[Intel-gfx] [PATCH 45/55] drm/i915: Convert intel_overlay to request tracking
intel_overlay already tracks its last flip request, along with action to
take after its completion. Refactor intel_overlay to reuse the common
i915_gem_active tracker.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_overlay.c | 84
1 file changed, 36 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index 651efe4e468e..1a42efb4f263 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -183,8 +183,7 @@ struct intel_overlay {
u32 flip_addr;
struct drm_i915_gem_object *reg_bo;
/* flip handling */
- struct drm_i915_gem_request *last_flip_req;
- void (*flip_tail)(struct intel_overlay *);
+ struct i915_gem_active last_flip;
};
static struct overlay_registers __iomem *
@@ -210,23 +209,26 @@ static void intel_overlay_unmap_regs(struct intel_overlay
*overlay,
io_mapping_unmap(regs);
}
-static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
+static void intel_overlay_submit_request(struct intel_overlay *overlay,
struct drm_i915_gem_request *req,
-void (*tail)(struct intel_overlay *))
+void (*retire)(struct i915_gem_active
*,
+ struct
drm_i915_gem_request *))
{
- int ret;
-
- WARN_ON(overlay->last_flip_req);
- i915_gem_request_assign(&overlay->last_flip_req, req);
+ GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
+ &overlay->i915->drm.struct_mutex));
+ overlay->last_flip.retire = retire;
+ i915_gem_active_set(&overlay->last_flip, req);
i915_add_request(req);
+}
- overlay->flip_tail = tail;
- ret = i915_wait_request(overlay->last_flip_req);
- if (ret)
- return ret;
-
- i915_gem_request_assign(&overlay->last_flip_req, NULL);
- return 0;
+static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
+struct drm_i915_gem_request *req,
+void (*retire)(struct i915_gem_active
*,
+ struct
drm_i915_gem_request *))
+{
+ intel_overlay_submit_request(overlay, req, retire);
+ return i915_gem_active_retire(&overlay->last_flip,
+ &overlay->i915->drm.struct_mutex);
}
static struct drm_i915_gem_request *alloc_request(struct intel_overlay
*overlay)
@@ -306,25 +308,32 @@ static int intel_overlay_continue(struct intel_overlay
*overlay,
intel_ring_emit(ring, flip_addr);
intel_ring_advance(ring);
- WARN_ON(overlay->last_flip_req);
- i915_gem_request_assign(&overlay->last_flip_req, req);
- i915_add_request(req);
+ intel_overlay_submit_request(overlay, req, NULL);
return 0;
}
-static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
+static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
+ struct drm_i915_gem_request *req)
{
+ struct intel_overlay *overlay =
+ container_of(active, typeof(*overlay), last_flip);
struct drm_i915_gem_object *obj = overlay->old_vid_bo;
+ i915_gem_track_fb(obj, NULL,
+ INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
+
i915_gem_object_ggtt_unpin(obj);
i915_gem_object_put(obj);
overlay->old_vid_bo = NULL;
}
-static void intel_overlay_off_tail(struct intel_overlay *overlay)
+static void intel_overlay_off_tail(struct i915_gem_active *active,
+ struct drm_i915_gem_request *req)
{
+ struct intel_overlay *overlay =
+ container_of(active, typeof(*overlay), last_flip);
struct drm_i915_gem_object *obj = overlay->vid_bo;
/* never have the overlay hw on without showing a frame */
@@ -387,27 +396,16 @@ static int intel_overlay_off(struct intel_overlay
*overlay)
}
intel_ring_advance(ring);
- return intel_overlay_do_wait_request(overlay, req,
intel_overlay_off_tail);
+ return intel_overlay_do_wait_request(overlay, req,
+intel_overlay_off_tail);
}
/* recover from an interruption due to a signal
* We have to be careful not to repeat work forever an make forward progess. */
static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
{
- int ret;
-
- if (overlay->last_flip_req == NULL)
- return 0;
-
- ret = i915_wait_request(overlay->last_flip_req);
- if (ret)
- return ret;
-
- if (overlay->flip_tail)
- overlay->f
[Intel-gfx] [PATCH 41/55] drm/i915: Rename request->list to link for consistency
We use "list" to denote the list and "link" to denote an element on that
list. Rename request->list to match this idiom.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_request.c | 12 ++--
drivers/gpu/drm/i915/i915_gem_request.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
6 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 16fa1f527ef5..6693dfbca4f1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -748,13 +748,13 @@ static int i915_gem_request_info(struct seq_file *m, void
*data)
int count;
count = 0;
- list_for_each_entry(req, &engine->request_list, list)
+ list_for_each_entry(req, &engine->request_list, link)
count++;
if (count == 0)
continue;
seq_printf(m, "%s requests: %d\n", engine->name, count);
- list_for_each_entry(req, &engine->request_list, list) {
+ list_for_each_entry(req, &engine->request_list, link) {
struct task_struct *task;
rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2d86a0c3f295..e5be4eb0a397 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2475,7 +2475,7 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
* extra delay for a recent interrupt is pointless. Hence, we do
* not need an engine->irq_seqno_barrier() before the seqno reads.
*/
- list_for_each_entry(request, &engine->request_list, list) {
+ list_for_each_entry(request, &engine->request_list, link) {
if (i915_gem_request_completed(request))
continue;
@@ -2497,7 +2497,7 @@ static void i915_gem_reset_engine_status(struct
intel_engine_cs *engine)
ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
i915_set_reset_status(request->ctx, ring_hung);
- list_for_each_entry_continue(request, &engine->request_list, list)
+ list_for_each_entry_continue(request, &engine->request_list, link)
i915_set_reset_status(request->ctx, false);
}
@@ -2546,7 +2546,7 @@ static void i915_gem_reset_engine_cleanup(struct
intel_engine_cs *engine)
request = list_last_entry(&engine->request_list,
struct drm_i915_gem_request,
- list);
+ link);
i915_gem_request_retire_upto(request);
}
@@ -2609,7 +2609,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs
*engine)
request = list_first_entry(&engine->request_list,
struct drm_i915_gem_request,
- list);
+ link);
if (!i915_gem_request_completed(request))
break;
@@ -2629,7 +2629,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs
*engine)
engine_list[engine->id]);
if
(!list_empty(&i915_gem_active_peek(&obj->last_read[engine->id],
-
&obj->base.dev->struct_mutex)->list))
+
&obj->base.dev->struct_mutex)->link))
break;
i915_gem_object_retire__read(obj, engine->id);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index d7011185a4ee..065e9e61265b 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -160,7 +160,7 @@ i915_gem_request_remove_from_client(struct
drm_i915_gem_request *request)
static void i915_gem_request_retire(struct drm_i915_gem_request *request)
{
trace_i915_gem_request_retire(request);
- list_del_init(&request->list);
+ list_del_init(&request->link);
/* We know the GPU must have read the request to have
* sent us the seqno + interrupt, so use the position
@@ -191,12 +191,12 @@ void i915_gem_request_retire_upto(struct
drm_i915_gem_request *req)
lockdep_assert_held(&req->i915->drm.struct_mutex);
- if (list_empty(&req->list))
+ if (list_empty(&req->link))
return;
do {
tmp = list_first_entry(&engine->request_list,
- typeof(*tmp), list);
+ typeof(*tmp), link);
[Intel-gfx] [PATCH 40/55] drm/i915: Refactor blocking waits
Tidy up the for loops that handle waiting for read/write vs read-only
access.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 158 +++-
1 file changed, 75 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f6b69dcaccb..2d86a0c3f295 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1339,6 +1339,23 @@ put_rpm:
return ret;
}
+static void
+i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
+ struct drm_i915_gem_request *req)
+{
+ int idx = req->engine->id;
+
+ if (i915_gem_active_peek(&obj->last_read[idx],
+&obj->base.dev->struct_mutex) == req)
+ i915_gem_object_retire__read(obj, idx);
+ else if (i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex) == req)
+ i915_gem_object_retire__write(obj);
+
+ if (!i915_reset_in_progress(&req->i915->gpu_error))
+ i915_gem_request_retire_upto(req);
+}
+
/**
* Ensures that all rendering to the object has completed and the object is
* safe to unbind from the GTT or access from the CPU.
@@ -1349,39 +1366,34 @@ int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
bool readonly)
{
- struct drm_i915_gem_request *request;
struct reservation_object *resv;
- int ret, i;
+ struct i915_gem_active *active;
+ unsigned long active_mask;
+ int idx, ret;
- if (readonly) {
- request = i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex);
- if (request) {
- ret = i915_wait_request(request);
- if (ret)
- return ret;
+ lockdep_assert_held(&obj->base.dev->struct_mutex);
- i = request->engine->id;
- if (i915_gem_active_peek(&obj->last_read[i],
-&obj->base.dev->struct_mutex)
== request)
- i915_gem_object_retire__read(obj, i);
- else
- i915_gem_object_retire__write(obj);
- }
+ if (!readonly) {
+ active = obj->last_read;
+ active_mask = obj->active;
} else {
- for (i = 0; i < I915_NUM_ENGINES; i++) {
- request = i915_gem_active_peek(&obj->last_read[i],
-
&obj->base.dev->struct_mutex);
- if (!request)
- continue;
+ active_mask = 1;
+ active = &obj->last_write;
+ }
- ret = i915_wait_request(request);
- if (ret)
- return ret;
+ for_each_active(active_mask, idx) {
+ struct drm_i915_gem_request *request;
- i915_gem_object_retire__read(obj, i);
- }
- GEM_BUG_ON(obj->active);
+ request = i915_gem_active_peek(&active[idx],
+ &obj->base.dev->struct_mutex);
+ if (!request)
+ continue;
+
+ ret = i915_wait_request(request);
+ if (ret)
+ return ret;
+
+ i915_gem_object_retire_request(obj, request);
}
resv = i915_gem_object_get_dmabuf_resv(obj);
@@ -1397,23 +1409,6 @@ i915_gem_object_wait_rendering(struct
drm_i915_gem_object *obj,
return 0;
}
-static void
-i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *req)
-{
- int idx = req->engine->id;
-
- if (i915_gem_active_peek(&obj->last_read[idx],
-&obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__write(obj);
-
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-}
-
/* A nonblocking variant of the above wait. This is a highly dangerous routine
* as the object state may change during this call.
*/
@@ -1425,34 +1420,31 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
+ struct i915_gem_active *active;
+ unsigned l
[Intel-gfx] [PATCH 52/55] drm/i915: Track active vma requests
Hook the vma itself into the i915_gem_request_retire() so that we can
accurately track when a solitary vma is inactive (as opposed to having
to wait for the entire object to be idle). This improves the interaction
when using multiple contexts (with full-ppgtt) and eliminates some
frequent list walking when retiring objects after a completed request.
A side-effect is that we get an active vma reference for free. The
consequence of this is shown in the next patch...
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_gem.c| 50 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 20
drivers/gpu/drm/i915/i915_gem_gtt.h| 28 +
5 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6693dfbca4f1..3870eaeeddb4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -367,7 +367,7 @@ static int per_file_stats(int id, void *ptr, void *data)
continue;
}
- if (obj->active) /* XXX per-vma statistic */
+ if (i915_vma_is_active(vma))
stats->active += vma->node.size;
else
stats->inactive += vma->node.size;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2e0b54fa03f9..61fa8049076e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2354,7 +2354,6 @@ i915_gem_object_retire__read(struct i915_gem_active
*active,
int idx = request->engine->id;
struct drm_i915_gem_object *obj =
container_of(active, struct drm_i915_gem_object,
last_read[idx]);
- struct i915_vma *vma;
GEM_BUG_ON((obj->active & (1 << idx)) == 0);
@@ -2366,12 +2365,9 @@ i915_gem_object_retire__read(struct i915_gem_active
*active,
* so that we don't steal from recently used but inactive objects
* (unless we are forced to ofc!)
*/
- list_move_tail(&obj->global_list, &request->i915->mm.bound_list);
-
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
- if (!list_empty(&vma->vm_link))
- list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
- }
+ if (obj->bind_count)
+ list_move_tail(&obj->global_list,
+ &request->i915->mm.bound_list);
i915_gem_object_put(obj);
}
@@ -2804,8 +2800,29 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
{
struct drm_i915_gem_object *obj = vma->obj;
+ unsigned long active;
int ret;
+ /* First wait upon any activity as retiring the request may
+* have side-effects such as unpinning or even unbinding this vma.
+*/
+ active = vma->active;
+ if (active && wait) {
+ int idx;
+
+ for_each_active(active, idx) {
+ ret = i915_gem_active_retire(&vma->last_read[idx],
+ &vma->vm->dev->struct_mutex);
+ if (ret)
+ return ret;
+ }
+
+ GEM_BUG_ON(i915_vma_is_active(vma));
+ }
+
+ if (vma->pin_count)
+ return -EBUSY;
+
if (list_empty(&vma->obj_link))
return 0;
@@ -2814,18 +2831,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
return 0;
}
- if (vma->pin_count)
- return -EBUSY;
-
GEM_BUG_ON(obj->bind_count == 0);
GEM_BUG_ON(!obj->pages);
- if (wait) {
- ret = i915_gem_object_wait_rendering(obj, false);
- if (ret)
- return ret;
- }
-
if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
i915_gem_object_finish_gtt(obj);
@@ -3208,9 +3216,6 @@ i915_gem_object_flush_cpu_write_domain(struct
drm_i915_gem_object *obj)
int
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
uint32_t old_write_domain, old_read_domains;
struct i915_vma *vma;
int ret;
@@ -3263,9 +3268,10 @@ i915_gem_object_set_to_gtt_domain(struct
drm_i915_gem_object *obj, bool write)
/* And bump the LRU for this access */
vma = i915_gem_obj_to_ggtt(obj);
- if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
- list_move_tail(&vma->vm_link,
- &ggtt->base.inactive_list)
[Intel-gfx] [PATCH 53/55] drm/i915: Release vma when the handle is closed
In order to prevent a leak of the vma on shared objects, we need to
hook into the object_close callback to destroy the vma on the object for
this file. However, if we destroyed that vma immediately we may cause
unexpected application stalls as we try to unbind a busy vma - hence we
defer the unbind to when we retire the vma.
v2: Keep vma allocated until closed. This is useful for a later
optimisation, but it is required now in order to handle potential
recursion of i915_vma_unbind() by retiring itself.
v3: Comments are important.
Testcase: igt/gem_ppggtt/flink-and-close-vma-leak
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 88 ++-
drivers/gpu/drm/i915/i915_gem_evict.c | 8 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
6 files changed, 77 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 478e8168ad94..869baa6a5196 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2574,6 +2574,7 @@ static struct drm_driver driver = {
.postclose = i915_driver_postclose,
.set_busid = drm_pci_set_busid,
+ .gem_close_object = i915_gem_close_object,
.gem_free_object = i915_gem_free_object,
.gem_vm_ops = &i915_gem_vm_ops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4876d2a6c2c4..56d6cf1749a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3014,8 +3014,8 @@ struct drm_i915_gem_object *i915_gem_object_create(struct
drm_device *dev,
size_t size);
struct drm_i915_gem_object *i915_gem_object_create_from_data(
struct drm_device *dev, const void *data, size_t size);
+void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
void i915_gem_free_object(struct drm_gem_object *obj);
-void i915_gem_vma_destroy(struct i915_vma *vma);
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE (1<<0)
@@ -3048,6 +3048,8 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
* _guarantee_ VMA in question is _not in use_ anywhere.
*/
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
+void i915_vma_close(struct i915_vma *vma);
+void i915_vma_destroy(struct i915_vma *vma);
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61fa8049076e..9d9dcb3c817f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2603,6 +2603,19 @@ out_rearm:
}
}
+void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
+{
+ struct drm_i915_gem_object *obj = to_intel_bo(gem);
+ struct drm_i915_file_private *fpriv = file->driver_priv;
+ struct i915_vma *vma, *vn;
+
+ mutex_lock(&obj->base.dev->struct_mutex);
+ list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
+ if (vma->vm->file == fpriv)
+ i915_vma_close(vma);
+ mutex_unlock(&obj->base.dev->struct_mutex);
+}
+
/**
* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
* @dev: drm device pointer
@@ -2810,26 +2823,32 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
if (active && wait) {
int idx;
+ /* When a closed VMA is retired, it is unbound - eek.
+* In order to prevent it from being recursively closed,
+* take a pin on the vma so that the second unbind is
+* aborted.
+*/
+ vma->pin_count++;
+
for_each_active(active, idx) {
ret = i915_gem_active_retire(&vma->last_read[idx],
&vma->vm->dev->struct_mutex);
if (ret)
- return ret;
+ break;
}
+ vma->pin_count--;
+ if (ret)
+ return ret;
+
GEM_BUG_ON(i915_vma_is_active(vma));
}
if (vma->pin_count)
return -EBUSY;
- if (list_empty(&vma->obj_link))
- return 0;
-
- if (!drm_mm_node_allocated(&vma->node)) {
- i915_gem_vma_destroy(vma);
- return 0;
- }
+ if (!drm_mm_node_allocated(&vma->node))
+ goto destroy;
GEM_BUG_ON(obj->bind_count == 0);
GEM_BUG_ON(!obj->pages);
@@ -2862,7 +2881,6 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
}
[Intel-gfx] [PATCH 43/55] drm/i915: Refactor activity tracking for requests
With the introduction of requests, we amplified the number of atomic
refcounted objects we use and update every execbuffer; from none to
several references, and a set of references that need to be changed. We
also introduced interesting side-effects in the order of retiring
requests and objects.
Instead of independently tracking the last request for an object, track
the active objects for each request. The object will reside in the
buffer list of its most recent active request and so we reduce the kref
interchange to a list_move. Now retirements are entirely driven by the
request, dramatically simplifying activity tracking on the object
themselves, and removing the ambiguity between retiring objects and
retiring requests.
Furthermore with the consolidation of managing the activity tracking
centrally, we can look forward to using RCU to enable lockless lookup of
the current active requests for an object. In the future, we will be
able to query the status or wait upon rendering to an object without
even touching the struct_mutex BKL.
All told, less code, simpler and faster, and more extensible.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/i915_drv.h | 10 ---
drivers/gpu/drm/i915/i915_gem.c | 139 +++-
drivers/gpu/drm/i915/i915_gem_debug.c | 70
drivers/gpu/drm/i915/i915_gem_fence.c | 11 +--
drivers/gpu/drm/i915/i915_gem_request.c | 35 ++--
drivers/gpu/drm/i915/i915_gem_request.h | 90 +++--
drivers/gpu/drm/i915/intel_engine_cs.c | 1 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ---
9 files changed, 125 insertions(+), 244 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/i915_gem_debug.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6092f0ea24df..dda724f04445 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,7 +25,6 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o
i915-y += i915_cmd_parser.o \
i915_gem_batch_pool.o \
i915_gem_context.o \
- i915_gem_debug.o \
i915_gem_dmabuf.o \
i915_gem_evict.o \
i915_gem_execbuffer.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76b5611aba9e..03f12304308a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -432,8 +432,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
#define DRIVER_MINOR 6
#define DRIVER_PATCHLEVEL 0
-#define WATCH_LISTS0
-
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
@@ -2153,7 +2151,6 @@ struct drm_i915_gem_object {
struct drm_mm_node *stolen;
struct list_head global_list;
- struct list_head engine_list[I915_NUM_ENGINES];
/** Used in execbuf to temporarily hold a ref */
struct list_head obj_exec_link;
@@ -3463,13 +3460,6 @@ static inline bool
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
obj->tiling_mode != I915_TILING_NONE;
}
-/* i915_gem_debug.c */
-#if WATCH_LISTS
-int i915_verify_lists(struct drm_device *dev);
-#else
-#define i915_verify_lists(dev) 0
-#endif
-
/* i915_debugfs.c */
#ifdef CONFIG_DEBUG_FS
int i915_debugfs_register(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3bff6b560f97..b9874a99ae04 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -43,10 +43,6 @@
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj);
-static void
-i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
-static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
static bool cpu_cache_is_coherent(struct drm_device *dev,
enum i915_cache_level level)
@@ -141,7 +137,6 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
if (ret)
return ret;
- WARN_ON(i915_verify_lists(dev));
return 0;
}
@@ -1339,23 +1334,6 @@ put_rpm:
return ret;
}
-static void
-i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *req)
-{
- int idx = req->engine->id;
-
- if (i915_gem_active_peek(&obj->last_read[idx],
-&obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write,
- &obj->base.dev->struct_mutex) == req)
- i915_gem_object_retire__write(obj);
-
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-}
-
/**
* Ensures that all rende
[Intel-gfx] [PATCH 48/55] drm/i915: s/__i915_wait_request/i915_wait_request/
There is onl one wait on request function now, so drop the "expert"
indication of leading __.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 18 +-
drivers/gpu/drm/i915/i915_gem_request.c | 16
drivers/gpu/drm/i915/i915_gem_request.h | 12 ++--
drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/intel_display.c| 14 +++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8
6 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b9874a99ae04..cc84f00cf883 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1420,7 +1420,7 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
mutex_unlock(&dev->struct_mutex);
ret = 0;
for (i = 0; ret == 0 && i < n; i++)
- ret = __i915_wait_request(requests[i], true, NULL, rps);
+ ret = i915_wait_request(requests[i], true, NULL, rps);
mutex_lock(&dev->struct_mutex);
for (i = 0; i < n; i++)
@@ -2733,9 +2733,9 @@ out:
for (i = 0; i < n; i++) {
if (ret == 0)
- ret = __i915_wait_request(requests[i], true,
- args->timeout_ns > 0 ?
&args->timeout_ns : NULL,
- to_rps_client(file));
+ ret = i915_wait_request(requests[i], true,
+ args->timeout_ns > 0 ?
&args->timeout_ns : NULL,
+ to_rps_client(file));
i915_gem_request_put(requests[i]);
}
return ret;
@@ -2751,10 +2751,10 @@ __i915_gem_object_sync(struct drm_i915_gem_request *to,
return 0;
if (!i915.semaphores) {
- ret = __i915_wait_request(from,
- from->i915->mm.interruptible,
- NULL,
- NO_WAITBOOST);
+ ret = i915_wait_request(from,
+ from->i915->mm.interruptible,
+ NULL,
+ NO_WAITBOOST);
if (ret)
return ret;
} else {
@@ -3723,7 +3723,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct
drm_file *file)
if (target == NULL)
return 0;
- ret = __i915_wait_request(target, true, NULL, NULL);
+ ret = i915_wait_request(target, true, NULL, NULL);
i915_gem_request_put(target);
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 2c0c6a37f46a..1935591a98c1 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -70,9 +70,9 @@ static signed long i915_fence_wait(struct fence *fence,
timeout = NULL;
}
- ret = __i915_wait_request(to_request(fence),
- interruptible, timeout,
- NO_WAITBOOST);
+ ret = i915_wait_request(to_request(fence),
+ interruptible, timeout,
+ NO_WAITBOOST);
if (ret == -ETIME)
return 0;
@@ -564,7 +564,7 @@ bool __i915_spin_request(const struct drm_i915_gem_request
*req,
}
/**
- * __i915_wait_request - wait until execution of request has finished
+ * i915_wait_request - wait until execution of request has finished
* @req: duh!
* @interruptible: do an interruptible wait (normally yes)
* @timeout: in - how long to wait (NULL forever); out - how much time
remaining
@@ -580,10 +580,10 @@ bool __i915_spin_request(const struct
drm_i915_gem_request *req,
* Returns 0 if the request was found within the alloted time. Else returns the
* errno with remaining time filled in timeout argument.
*/
-int __i915_wait_request(struct drm_i915_gem_request *req,
- bool interruptible,
- s64 *timeout,
- struct intel_rps_client *rps)
+int i915_wait_request(struct drm_i915_gem_request *req,
+ bool interruptible,
+ s64 *timeout,
+ struct intel_rps_client *rps)
{
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
DEFINE_WAIT(reset);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index f4aab8e60c9e..828e304b2f11 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -214,10 +214,10 @@ struct intel_rps_client;
#define IS_RPS_CLIENT(p) (!IS_ERR(p))
#define IS_RPS_USER(p) (!IS_ERR_OR_NULL(p))
-int __i915_wait_
[Intel-gfx] [PATCH 54/55] drm/i915: Mark the context and address space as closed
When the user closes the context mark it and the dependent address space
as closed. As we use an asynchronous destruct method, this has two
purposes. First it allows us to flag the closed context and detect
internal errors if we to create any new objects for it (as it is removed
from the user's namespace, these should be internal bugs only). And
secondly, it allows us to immediately reap stale vma.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 15 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 43 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +--
drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +++
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
6 files changed, 63 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56d6cf1749a9..c6c64003504f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -907,6 +907,7 @@ struct i915_gem_context {
struct list_head link;
u8 remap_slice;
+ bool closed:1;
};
enum fb_op_origin {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9d9dcb3c817f..0d9a80b41101 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2864,12 +2864,15 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
__i915_vma_iounmap(vma);
}
- trace_i915_vma_unbind(vma);
-
- vma->vm->unbind_vma(vma);
+ if (likely(!vma->vm->closed)) {
+ trace_i915_vma_unbind(vma);
+ vma->vm->unbind_vma(vma);
+ }
vma->bound = 0;
- list_del_init(&vma->vm_link);
+ drm_mm_remove_node(&vma->node);
+ list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
+
if (vma->is_ggtt) {
if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
obj->map_and_fenceable = false;
@@ -2880,8 +2883,6 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
vma->ggtt_view.pages = NULL;
}
- drm_mm_remove_node(&vma->node);
-
/* Since the unbound list is global, only move to that list if
* no more VMAs exist. */
if (--obj->bind_count == 0)
@@ -3123,7 +3124,7 @@ search_free:
goto err_remove_node;
list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
- list_add_tail(&vma->vm_link, &vm->inactive_list);
+ list_move_tail(&vma->vm_link, &vm->inactive_list);
obj->bind_count++;
return vma;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 29b2547a2b4c..1ba6c0bb856a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -156,6 +156,7 @@ void i915_gem_context_free(struct kref *ctx_ref)
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
trace_i915_context_free(ctx);
+ GEM_BUG_ON(!ctx->closed);
/*
* This context is going away and we need to remove all VMAs still
@@ -224,6 +225,37 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t
size)
return obj;
}
+static void i915_ppgtt_close(struct i915_address_space *vm)
+{
+ struct list_head *phases[] = {
+ &vm->active_list,
+ &vm->inactive_list,
+ &vm->unbound_list,
+ NULL,
+ }, **phase;
+
+ GEM_BUG_ON(vm->closed);
+ vm->closed = true;
+
+ for (phase = phases; *phase; phase++) {
+ struct i915_vma *vma, *vn;
+
+ list_for_each_entry_safe(vma, vn, *phase, vm_link)
+ if (!vma->closed)
+ i915_vma_close(vma);
+ }
+}
+
+static void context_close(struct i915_gem_context *ctx)
+{
+ GEM_BUG_ON(ctx->closed);
+ ctx->closed = true;
+ if (ctx->ppgtt)
+ i915_ppgtt_close(&ctx->ppgtt->base);
+ ctx->file_priv = ERR_PTR(-EBADF);
+ i915_gem_context_put(ctx);
+}
+
static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
{
int ret;
@@ -305,7 +337,7 @@ __create_hw_context(struct drm_device *dev,
return ctx;
err_out:
- i915_gem_context_put(ctx);
+ context_close(ctx);
return ERR_PTR(ret);
}
@@ -334,7 +366,7 @@ i915_gem_create_context(struct drm_device *dev,
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
idr_remove(&file_priv->context_idr, ctx->user_handle);
- i915_gem_context_put(ctx);
+ context_close(ctx);
return ERR_CAST(ppgtt);
}
@@ -505,7 +537,7 @@ void i915_gem_context_fini(struct drm_device *dev)
lockdep_assert_hel
[Intel-gfx] [PATCH 46/55] drm/i915: Move the special case wait-request handling to its one caller
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 25 -
drivers/gpu/drm/i915/i915_gem_request.h | 4
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +-
3 files changed, 13 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index f1c37b7891cb..2c0c6a37f46a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -716,28 +716,3 @@ complete:
return ret;
}
-
-/**
- * Waits for a request to be signaled, and cleans up the
- * request and object lists appropriately for that event.
- */
-int i915_wait_request(struct drm_i915_gem_request *req)
-{
- int ret;
-
- lockdep_assert_held(&req->i915->drm.struct_mutex);
- GEM_BUG_ON(list_empty(&req->link));
-
- ret = __i915_wait_request(req,
- req->i915->mm.interruptible,
- NULL,
- NULL);
- if (ret)
- return ret;
-
- /* If the GPU hung, we want to keep the requests to find the guilty. */
- if (!i915_reset_in_progress(&req->i915->gpu_error))
- i915_gem_request_retire_upto(req);
-
- return 0;
-}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index b1ee37896feb..f4aab8e60c9e 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -220,10 +220,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
__attribute__((nonnull(1)));
-int __must_check
-i915_wait_request(struct drm_i915_gem_request *req)
- __attribute__((nonnull));
-
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
/**
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index af76869c8db2..507576ef8077 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2284,6 +2284,7 @@ static int wait_for_space(struct drm_i915_gem_request
*req, int bytes)
{
struct intel_ring *ring = req->ring;
struct drm_i915_gem_request *target;
+ int ret;
intel_ring_update_space(ring);
if (ring->space >= bytes)
@@ -2313,7 +2314,18 @@ static int wait_for_space(struct drm_i915_gem_request
*req, int bytes)
if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
- return i915_wait_request(target);
+ ret = __i915_wait_request(target, true, NULL, NULL);
+ if (ret)
+ return ret;
+
+ if (i915_reset_in_progress(&target->i915->gpu_error))
+ return -EAGAIN;
+
+ i915_gem_request_retire_upto(target);
+
+ intel_ring_update_space(ring);
+ GEM_BUG_ON(ring->space < bytes);
+ return 0;
}
int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
@@ -2351,10 +2363,6 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
int num_dwords)
int ret = wait_for_space(req, wait_bytes);
if (unlikely(ret))
return ret;
-
- intel_ring_update_space(ring);
- if (unlikely(ring->space < wait_bytes))
- return -EAGAIN;
}
if (unlikely(need_wrap)) {
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 49/55] drm/i915: Double check activity before relocations
If the object is active and we need to perform a relocation upon it, we
need to take the slow relocation path. Before we do, double check the
active requests to see if they have completed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e1dfdbd8fc2e..9778b1bc6336 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -441,6 +441,20 @@ relocate_entry_clflush(struct drm_i915_gem_object *obj,
return 0;
}
+static bool object_is_idle(struct drm_i915_gem_object *obj)
+{
+ unsigned long active = obj->active;
+ int idx;
+
+ for_each_active(active, idx) {
+ if (!i915_gem_active_is_idle(&obj->last_read[idx],
+&obj->base.dev->struct_mutex))
+ return false;
+ }
+
+ return true;
+}
+
static int
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct eb_vmas *eb,
@@ -524,7 +538,7 @@ i915_gem_execbuffer_relocate_entry(struct
drm_i915_gem_object *obj,
}
/* We can't wait for rendering with pagefaults disabled */
- if (obj->active && pagefault_disabled())
+ if (pagefault_disabled() && !object_is_idle(obj))
return -EFAULT;
if (use_cpu_reloc(obj))
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 55/55] Revert "drm/i915: Clean up associated VMAs on context destruction"
This reverts commit e9f24d5fb7cf3628b195b18ff3ac4e37937ceeae.
The patch was only a stop-gap measure that fixed half the problem - the
leak of the fbcon when restarting X. A complete solution required
releasing the VMA when the object itself was closed rather than rely on
file/process exit. The previous patches add the VMA tracking necessary
to do close them along with the object, context or file, and so the time
has come to remove the partial fix.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/i915_gem.c | 14 ++
drivers/gpu/drm/i915/i915_gem_context.c | 22 --
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
4 files changed, 3 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6c64003504f..40033ca30e55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3044,11 +3044,6 @@ int i915_vma_bind(struct i915_vma *vma, enum
i915_cache_level cache_level,
u32 flags);
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
int __must_check i915_vma_unbind(struct i915_vma *vma);
-/*
- * BEWARE: Do not use the function below unless you can _absolutely_
- * _guarantee_ VMA in question is _not in use_ anywhere.
- */
-int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
void i915_vma_close(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0d9a80b41101..e3278f4e1ad2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2810,7 +2810,7 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
vma->iomap = NULL;
}
-static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
+int i915_vma_unbind(struct i915_vma *vma)
{
struct drm_i915_gem_object *obj = vma->obj;
unsigned long active;
@@ -2820,7 +2820,7 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
* have side-effects such as unpinning or even unbinding this vma.
*/
active = vma->active;
- if (active && wait) {
+ if (active) {
int idx;
/* When a closed VMA is retired, it is unbound - eek.
@@ -2902,16 +2902,6 @@ destroy:
return 0;
}
-int i915_vma_unbind(struct i915_vma *vma)
-{
- return __i915_vma_unbind(vma, true);
-}
-
-int __i915_vma_unbind_no_wait(struct i915_vma *vma)
-{
- return __i915_vma_unbind(vma, false);
-}
-
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1ba6c0bb856a..e9da841d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -134,21 +134,6 @@ static int get_context_size(struct drm_i915_private
*dev_priv)
return ret;
}
-static void i915_gem_context_clean(struct i915_gem_context *ctx)
-{
- struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
- struct i915_vma *vma, *next;
-
- if (!ppgtt)
- return;
-
- list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
-vm_link) {
- if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
- break;
- }
-}
-
void i915_gem_context_free(struct kref *ctx_ref)
{
struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
@@ -158,13 +143,6 @@ void i915_gem_context_free(struct kref *ctx_ref)
trace_i915_context_free(ctx);
GEM_BUG_ON(!ctx->closed);
- /*
-* This context is going away and we need to remove all VMAs still
-* around. This is to handle imported shared objects for which
-* destructor did not run when their handles were closed.
-*/
- i915_gem_context_clean(ctx);
-
i915_ppgtt_put(ctx->ppgtt);
for (i = 0; i < I915_NUM_ENGINES; i++) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d2130da3de9d..e19a5fd5f15f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3365,7 +3365,7 @@ void i915_vma_close(struct i915_vma *vma)
list_del_init(&vma->obj_link);
if (!i915_vma_is_active(vma) && !vma->pin_count)
- WARN_ON(__i915_vma_unbind_no_wait(vma));
+ WARN_ON(i915_vma_unbind(vma));
}
static struct i915_vma *
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 50/55] drm/i915: Move request list retirement to i915_gem_request.c
As the list retirement is now clean of implementation details, we can
move it closer to the request management.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 44 -
drivers/gpu/drm/i915/i915_gem_request.c | 35 ++
2 files changed, 35 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cc84f00cf883..c572c80a6604 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2541,50 +2541,6 @@ void i915_gem_reset(struct drm_device *dev)
i915_gem_restore_fences(dev);
}
-/**
- * This function clears the request list as sequence numbers are passed.
- * @engine: engine to retire requests on
- */
-void
-i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
-{
- while (!list_empty(&engine->request_list)) {
- struct drm_i915_gem_request *request;
-
- request = list_first_entry(&engine->request_list,
- struct drm_i915_gem_request,
- link);
-
- if (!i915_gem_request_completed(request))
- break;
-
- i915_gem_request_retire_upto(request);
- }
-}
-
-void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
-
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
-
- if (dev_priv->gt.active_engines == 0)
- return;
-
- GEM_BUG_ON(!dev_priv->gt.awake);
-
- for_each_engine(engine, dev_priv) {
- i915_gem_retire_requests_ring(engine);
- if (list_empty(&engine->request_list))
- dev_priv->gt.active_engines &=
~intel_engine_flag(engine);
- }
-
- if (dev_priv->gt.active_engines == 0)
- queue_delayed_work(dev_priv->wq,
- &dev_priv->gt.idle_work,
- msecs_to_jiffies(100));
-}
-
static void
i915_gem_retire_work_handler(struct work_struct *work)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 1935591a98c1..f41572aa53d4 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -716,3 +716,38 @@ complete:
return ret;
}
+
+void i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
+{
+ struct drm_i915_gem_request *request, *next;
+
+ list_for_each_entry_safe(request, next, &engine->request_list, link) {
+ if (!i915_gem_request_completed(request))
+ break;
+
+ i915_gem_request_retire(request);
+ }
+}
+
+void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *engine;
+
+ lockdep_assert_held(&dev_priv->drm.struct_mutex);
+
+ if (dev_priv->gt.active_engines == 0)
+ return;
+
+ GEM_BUG_ON(!dev_priv->gt.awake);
+
+ for_each_engine(engine, dev_priv) {
+ i915_gem_retire_requests_ring(engine);
+ if (list_empty(&engine->request_list))
+ dev_priv->gt.active_engines &=
~intel_engine_flag(engine);
+ }
+
+ if (dev_priv->gt.active_engines == 0)
+ queue_delayed_work(dev_priv->wq,
+ &dev_priv->gt.idle_work,
+ msecs_to_jiffies(100));
+}
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 47/55] drm/i915: Disable waitboosting for a saturated engine
If the user floods the GPU with so many requests that the engine stalls waiting for free space, don't automatically promote the GPU to maximum frequencies. If the GPU really is saturated with work, it will migrate to high clocks by itself, otherwise it is merely a user flooding us with busy-work. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 507576ef8077..90e46d1b04e2 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2314,7 +2314,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes) if (WARN_ON(&target->ring_link == &ring->request_list)) return -ENOSPC; - ret = __i915_wait_request(target, true, NULL, NULL); + ret = __i915_wait_request(target, true, NULL, NO_WAITBOOST); if (ret) return ret; -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 51/55] drm/i915: i915_vma_move_to_active prep patch
This patch is broken out of the next just to remove the code motion from
that patch and make it more readable. What we do here is move the
i915_vma_move_to_active() to i915_gem_execbuffer.c and put the three
stages (read, write, fenced) together so that future modifications to
active handling are all located in the same spot. The importance of this
is so that we can more simply control the order in which the requests
are place in the retirement list (i.e. control the order at which we
retire and so control the lifetimes to avoid having to hold onto
references).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_gem.c | 18
drivers/gpu/drm/i915/i915_gem_context.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 65 ++--
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
5 files changed, 51 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 03f12304308a..4876d2a6c2c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3153,7 +3153,8 @@ int __must_check i915_mutex_lock_interruptible(struct
drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *to);
void i915_vma_move_to_active(struct i915_vma *vma,
-struct drm_i915_gem_request *req);
+struct drm_i915_gem_request *req,
+unsigned int flags);
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c572c80a6604..2e0b54fa03f9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2330,24 +2330,6 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj)
return obj->mapping;
}
-void i915_vma_move_to_active(struct i915_vma *vma,
-struct drm_i915_gem_request *req)
-{
- struct drm_i915_gem_object *obj = vma->obj;
- struct intel_engine_cs *engine;
-
- engine = i915_gem_request_get_engine(req);
-
- /* Add a reference if we're newly entering the active list. */
- if (obj->active == 0)
- i915_gem_object_get(obj);
- obj->active |= intel_engine_flag(engine);
-
- i915_gem_active_set(&obj->last_read[engine->id], req);
-
- list_move_tail(&vma->vm_link, &vma->vm->active_list);
-}
-
static void
i915_gem_object_retire__fence(struct i915_gem_active *active,
struct drm_i915_gem_request *req)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 60861f616f24..29b2547a2b4c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -816,8 +816,8 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
* MI_SET_CONTEXT instead of when the next seqno has completed.
*/
if (from != NULL) {
- from->engine[RCS].state->base.read_domains =
I915_GEM_DOMAIN_INSTRUCTION;
-
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
+ struct drm_i915_gem_object *obj = from->engine[RCS].state;
+
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
* whole damn pipeline, we don't need to explicitly mark the
* object dirty. The only exception is that the context must be
@@ -825,10 +825,11 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
* able to defer doing this until we know the object would be
* swapped, but there is no way to do that yet.
*/
- from->engine[RCS].state->dirty = 1;
+ obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj), req, 0);
/* obj is kept alive until the next request by its active ref */
- i915_gem_object_ggtt_unpin(from->engine[RCS].state);
+ i915_gem_object_ggtt_unpin(obj);
i915_gem_context_put(from);
}
engine->last_context = i915_gem_context_get(to);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9778b1bc6336..d0f1da2863e4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1143,43 +1143,64 @@ i915_gem_validate_context(struct drm_device *dev,
struct drm_file *file,
return ctx;
}
+void i915_vma_move_to_active(struct i915_vma *vma,
+struct drm_i915_gem_request *req,
+unsigned int
[Intel-gfx] [PATCH 44/55] drm/i915: Track requests inside each intel_ring
By tracking each request occupying space inside an individual
intel_ring, we can greatly simplify the logic of tracking available
space and not worry about other timelines. (Each ring is an ordered
timeline of committed requests.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 2 ++
drivers/gpu/drm/i915/i915_gem_request.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ---
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 0216d6c093da..f1c37b7891cb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -174,6 +174,7 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
* Note this requires that we are always called in request
* completion order.
*/
+ list_del(&request->ring_link);
request->ring->last_retired_head = request->postfix;
/* Walk through the active list, calling retire on each. This allows
@@ -472,6 +473,7 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
request->previous_seqno = engine->last_submitted_seqno;
smp_store_mb(engine->last_submitted_seqno, request->fence.seqno);
list_add_tail(&request->link, &engine->request_list);
+ list_add_tail(&request->ring_link, &ring->request_list);
/* Record the position of the start of the request so that
* should we detect the updated seqno part-way through the
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index f0b91207aaa4..b1ee37896feb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -109,6 +109,9 @@ struct drm_i915_gem_request {
/** engine->request_list entry for this request */
struct list_head link;
+ /** ring->request_list entry for this request */
+ struct list_head ring_link;
+
struct drm_i915_file_private *file_priv;
/** file_priv list entry for this request */
struct list_head client_list;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5e0ba9416bd9..af76869c8db2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2059,6 +2059,8 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
int size)
ring->engine = engine;
list_add(&ring->link, &engine->buffers);
+ INIT_LIST_HEAD(&ring->request_list);
+
ring->size = size;
/* Workaround an erratum on the i830 which causes a hang if
* the TAIL pointer points to within the last 2 cachelines
@@ -2281,7 +2283,6 @@ int intel_ring_alloc_request_extras(struct
drm_i915_gem_request *request)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
struct intel_ring *ring = req->ring;
- struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
intel_ring_update_space(ring);
@@ -2299,17 +2300,9 @@ static int wait_for_space(struct drm_i915_gem_request
*req, int bytes)
*/
GEM_BUG_ON(!req->reserved_space);
- list_for_each_entry(target, &engine->request_list, link) {
+ list_for_each_entry(target, &ring->request_list, ring_link) {
unsigned space;
- /*
-* The request queue is per-engine, so can contain requests
-* from multiple ringbuffers. Here, we must ignore any that
-* aren't from the ringbuffer we're considering.
-*/
- if (target->ring != ring)
- continue;
-
/* Would completion of this request free enough space? */
space = __intel_ring_space(target->postfix, ring->tail,
ring->size);
@@ -2317,7 +2310,7 @@ static int wait_for_space(struct drm_i915_gem_request
*req, int bytes)
break;
}
- if (WARN_ON(&target->link == &engine->request_list))
+ if (WARN_ON(&target->ring_link == &ring->request_list))
return -ENOSPC;
return i915_wait_request(target);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 51c059d8c917..2681106948a5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,6 +90,8 @@ struct intel_ring {
struct intel_engine_cs *engine;
struct list_head link;
+ struct list_head request_list;
+
u32 head;
u32 tail;
int space;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 37/55] drm/i915: Introduce i915_gem_active for request tracking
In the next patch, request tracking is made more generic and for that we
need a new expanded struct and to separate out the logic changes from
the mechanical churn, we split out the structure renaming into this
patch.
v2: Writer's block. Add some spiel about why we track requests.
v3: Now i915_gem_active.
v4: Now with i915_gem_active_set() for attaching to the active request.
v5: Use i915_gem_active_set() from inside the retirement handlers
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 11 +++---
drivers/gpu/drm/i915/i915_drv.h| 9 +++--
drivers/gpu/drm/i915/i915_gem.c| 58 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +--
drivers/gpu/drm/i915/i915_gem_fence.c | 6 ++--
drivers/gpu/drm/i915/i915_gem_request.h| 41 +
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c| 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 7 ++--
drivers/gpu/drm/i915/intel_display.c | 8 ++---
10 files changed, 93 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b638ecea0c03..f67892215136 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
-
i915_gem_request_get_seqno(obj->last_read_req[id]));
+
i915_gem_request_get_seqno(obj->last_read[id].request));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_request_get_seqno(obj->last_write_req),
- i915_gem_request_get_seqno(obj->last_fenced_req),
+ i915_gem_request_get_seqno(obj->last_write.request),
+ i915_gem_request_get_seqno(obj->last_fence.request),
i915_cache_level_str(to_i915(obj->base.dev),
obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -195,9 +195,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj)
*t = '\0';
seq_printf(m, " (%s mappable)", s);
}
- if (obj->last_write_req != NULL)
- seq_printf(m, " (%s)",
-
i915_gem_request_get_engine(obj->last_write_req)->name);
+ if (obj->last_write.request)
+ seq_printf(m, " (%s)", obj->last_write.request->engine->name);
if (obj->frontbuffer_bits)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2abae63258a3..76b5611aba9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2242,11 +2242,10 @@ struct drm_i915_gem_object {
* requests on one ring where the write request is older than the
* read request. This allows for the CPU to read from an active
* buffer by only waiting for the write to complete.
-* */
- struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
- struct drm_i915_gem_request *last_write_req;
- /** Breadcrumb of last fenced GPU access to the buffer. */
- struct drm_i915_gem_request *last_fenced_req;
+*/
+ struct i915_gem_active last_read[I915_NUM_ENGINES];
+ struct i915_gem_active last_write;
+ struct i915_gem_active last_fence;
/** Current tiling stride for the object, if it's tiled. */
uint32_t stride;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bcc05dd2be5a..98dc97c8c2bf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1353,23 +1353,23 @@ i915_gem_object_wait_rendering(struct
drm_i915_gem_object *obj,
int ret, i;
if (readonly) {
- if (obj->last_write_req != NULL) {
- ret = i915_wait_request(obj->last_write_req);
+ if (obj->last_write.request) {
+ ret = i915_wait_request(obj->last_write.request);
if (ret)
return ret;
- i = obj->last_write_req->engine->id;
- if (obj->last_read_req[i] == obj->last_write_req)
+ i = obj->last_write.request->engine->id;
+ if (obj->last_read[i].request ==
obj->last_write.request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
-
[Intel-gfx] [PATCH 34/55] drm/i915: Count how many VMA are bound for an object
Since we may have VMA allocated for an object, but we interrupted their
binding, there is a disparity between have elements on the obj->vma_list
and being bound. i915_gem_obj_bound_any() does this check, but this is
not rigorously observed - add an explicit count to make it easier.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 34 +---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 17 +---
drivers/gpu/drm/i915/i915_gem_stolen.c | 1 +
5 files changed, 23 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2fc81865e657..b638ecea0c03 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -174,6 +174,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj)
if (obj->fence_reg != I915_FENCE_REG_NONE)
seq_printf(m, " (fence: %d)", obj->fence_reg);
list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ if (!drm_mm_node_allocated(&vma->node))
+ continue;
+
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
vma->is_ggtt ? "g" : "pp",
vma->node.start, vma->node.size);
@@ -335,11 +338,11 @@ static int per_file_stats(int id, void *ptr, void *data)
struct drm_i915_gem_object *obj = ptr;
struct file_stats *stats = data;
struct i915_vma *vma;
- int bound = 0;
stats->count++;
stats->total += obj->base.size;
-
+ if (!obj->bind_count)
+ stats->unbound += obj->base.size;
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
@@ -347,8 +350,6 @@ static int per_file_stats(int id, void *ptr, void *data)
if (!drm_mm_node_allocated(&vma->node))
continue;
- bound++;
-
if (vma->is_ggtt) {
stats->global += vma->node.size;
} else {
@@ -366,9 +367,6 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->inactive += vma->node.size;
}
- if (!bound)
- stats->unbound += obj->base.size;
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4c38307d2554..e28228c6f383 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2221,6 +2221,8 @@ struct drm_i915_gem_object {
unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
unsigned int has_wc_mmap;
+ /** Count of VMA actually bound by this object */
+ unsigned int bind_count;
unsigned int pin_display;
struct sg_table *pages;
@@ -3266,7 +3268,6 @@ i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
}
-bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
const struct i915_ggtt_view *view);
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a0ea1ee16f67..a3defd7b4046 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2107,7 +2107,7 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
if (obj->pages_pin_count)
return -EBUSY;
- BUG_ON(i915_gem_obj_bound_any(obj));
+ GEM_BUG_ON(obj->bind_count);
/* ->put_pages might need to allocate memory for the bit17 swizzle
* array, hence protect them from being reaped by removing them from gtt
@@ -2965,7 +2965,6 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
{
struct drm_i915_gem_object *obj = vma->obj;
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
int ret;
if (list_empty(&vma->obj_link))
@@ -2979,7 +2978,8 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
if (vma->pin_count)
return -EBUSY;
- BUG_ON(obj->pages == NULL);
+ GEM_BUG_ON(obj->bind_count == 0);
+ GEM_BUG_ON(!obj->pages);
if (wait) {
ret = i915_gem_object_wait_rendering(obj, false);
@@ -3019,8 +3019,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool
wait)
/* Since the unbound list is global, only move to that list if
* no more VMAs exist. */
- if (list_empty(&obj->vma_list))
- list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
+ if (--obj->bind_count == 0)
+
[Intel-gfx] [PATCH 38/55] drm/i915: Prepare i915_gem_active for annotations
In the future, we will want to add annotations to the i915_gem_active
struct. The API is thus expanded to hide direct access to the contents
of i915_gem_active and mediated instead through a number of helpers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 ++--
drivers/gpu/drm/i915/i915_gem.c | 85 -
drivers/gpu/drm/i915/i915_gem_fence.c | 11 ++-
drivers/gpu/drm/i915/i915_gem_request.h | 131 +++-
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 8 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 9 ++-
drivers/gpu/drm/i915/intel_display.c| 15 ++--
8 files changed, 206 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f67892215136..b41561bdfb85 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,10 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
-
i915_gem_request_get_seqno(obj->last_read[id].request));
+ i915_gem_active_get_seqno(&obj->last_read[id]));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_request_get_seqno(obj->last_write.request),
- i915_gem_request_get_seqno(obj->last_fence.request),
+ i915_gem_active_get_seqno(&obj->last_write),
+ i915_gem_active_get_seqno(&obj->last_fence),
i915_cache_level_str(to_i915(obj->base.dev),
obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -195,8 +195,11 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
*t = '\0';
seq_printf(m, " (%s mappable)", s);
}
- if (obj->last_write.request)
- seq_printf(m, " (%s)", obj->last_write.request->engine->name);
+
+ engine = i915_gem_active_get_engine(&obj->last_write);
+ if (engine)
+ seq_printf(m, " (%s)", engine->name);
+
if (obj->frontbuffer_bits)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 98dc97c8c2bf..b8d541f212ff 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1349,27 +1349,30 @@ int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
bool readonly)
{
+ struct drm_i915_gem_request *request;
struct reservation_object *resv;
int ret, i;
if (readonly) {
- if (obj->last_write.request) {
- ret = i915_wait_request(obj->last_write.request);
+ request = i915_gem_active_peek(&obj->last_write);
+ if (request) {
+ ret = i915_wait_request(request);
if (ret)
return ret;
- i = obj->last_write.request->engine->id;
- if (obj->last_read[i].request ==
obj->last_write.request)
+ i = request->engine->id;
+ if (i915_gem_active_peek(&obj->last_read[i]) == request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
- if (!obj->last_read[i].request)
+ request = i915_gem_active_peek(&obj->last_read[i]);
+ if (!request)
continue;
- ret = i915_wait_request(obj->last_read[i].request);
+ ret = i915_wait_request(request);
if (ret)
return ret;
@@ -1397,9 +1400,9 @@ i915_gem_object_retire_request(struct drm_i915_gem_object
*obj,
{
int idx = req->engine->id;
- if (obj->last_read[idx].request == req)
+ if (i915_gem_active_peek(&obj->last_read[idx]) == req)
i915_gem_object_retire__read(obj, idx);
- else if (obj->last_write.request == req)
+ else if (i915_gem_active_peek(&obj->last_write) == req)
i915_gem_object_retire__write(obj);
if (!i915_reset_in_progress(&req->i915->gpu_error))
@@ -1428,20 +1431,20 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
if (readonly) {
struct drm_i915_gem_request *req;
- req = obj->last_write.request;
+ req = i915_gem_active_get(&obj->last
[Intel-gfx] [PATCH 12/55] drm/i915: Rename intel_context[engine].ringbuf
Perform s/ringbuf/ring/ on the context struct for consistency with the
ring/engine split.
v2: Kill an outdated error_ringbuf label
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-14-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c| 8 +++
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem_context.c| 4 ++--
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 37 ++
5 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9aa62c5b5f65..bde68741809b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -425,8 +425,8 @@ static int per_file_ctx_stats(int id, void *ptr, void *data)
for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
if (ctx->engine[n].state)
per_file_stats(0, ctx->engine[n].state, data);
- if (ctx->engine[n].ringbuf)
- per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
+ if (ctx->engine[n].ring)
+ per_file_stats(0, ctx->engine[n].ring->obj, data);
}
return 0;
@@ -2066,8 +2066,8 @@ static int i915_context_status(struct seq_file *m, void
*unused)
seq_putc(m, ce->initialised ? 'I' : 'i');
if (ce->state)
describe_obj(m, ce->state);
- if (ce->ringbuf)
- describe_ctx_ringbuf(m, ce->ringbuf);
+ if (ce->ring)
+ describe_ctx_ringbuf(m, ce->ring);
seq_putc(m, '\n');
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11c0204aac23..e2067e195c16 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -894,7 +894,7 @@ struct i915_gem_context {
struct intel_context {
struct drm_i915_gem_object *state;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
struct i915_vma *lrc_vma;
uint32_t *lrc_reg_state;
u64 lrc_desc;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f7f4a8c40afe..f825b1e4aadf 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -173,8 +173,8 @@ void i915_gem_context_free(struct kref *ctx_ref)
continue;
WARN_ON(ce->pin_count);
- if (ce->ringbuf)
- intel_ringbuffer_free(ce->ringbuf);
+ if (ce->ring)
+ intel_ringbuffer_free(ce->ring);
i915_gem_object_put(ce->state);
}
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 01c1c1671811..eccd34832fe6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -363,7 +363,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
(engine->guc_id << GUC_ELC_ENGINE_OFFSET);
- obj = ce->ringbuf->obj;
+ obj = ce->ring->obj;
gfx_addr = i915_gem_obj_ggtt_offset(obj);
lrc->ring_begin = gfx_addr;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 041868c1ee9e..5dce6fa5179a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -482,11 +482,8 @@ static void execlists_context_unqueue(struct
intel_engine_cs *engine)
* resubmit the request. See gen8_emit_request() for where we
* prepare the padding after the end of the request.
*/
- struct intel_ringbuffer *ringbuf;
-
- ringbuf = req0->ctx->engine[engine->id].ringbuf;
req0->tail += 8;
- req0->tail &= ringbuf->size - 1;
+ req0->tail &= req0->ring->size - 1;
}
execlists_submit_requests(req0, req1);
@@ -714,7 +711,7 @@ int intel_logical_ring_alloc_request_extras(struct
drm_i915_gem_request *request
return ret;
}
- request->ring = ce->ringbuf;
+ request->ring = ce->ring;
if (i915.enable_guc_submission) {
/*
@@ -976,14 +973,14 @@ static int intel_lr_context_pin(struct i915_gem_context
*ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ce->ringbuf);
+ ret
[Intel-gfx] [PATCH 35/55] drm/i915: Be more careful when unbinding vma
When we call i915_vma_unbind(), we will wait upon outstanding rendering.
This will also trigger a retirement phase, which may update the object
lists. If, we extend request tracking to the VMA itself (rather than
keep it at the encompassing object), then there is a potential that the
obj->vma_list be modified for other elements upon i915_vma_unbind(). As
a result, if we walk over the object list and call i915_vma_unbind(), we
need to be prepared for that list to change.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 57 +++-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 +
drivers/gpu/drm/i915/i915_gem_userptr.c | 4 +--
4 files changed, 46 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e28228c6f383..2abae63258a3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3052,6 +3052,8 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
* _guarantee_ VMA in question is _not in use_ anywhere.
*/
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
+
+int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a3defd7b4046..9169f5f3d20c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -283,18 +283,38 @@ static const struct drm_i915_gem_object_ops
i915_gem_phys_ops = {
.release = i915_gem_object_release_phys,
};
+int
+i915_gem_object_unbind(struct drm_i915_gem_object *obj)
+{
+ struct i915_vma *vma;
+ LIST_HEAD(still_in_list);
+ int ret;
+
+ /* The vma will only be freed if it is marked as closed, and if we wait
+* upon rendering to the vma, we may unbind anything in the list.
+*/
+ while ((vma = list_first_entry_or_null(&obj->vma_list,
+ struct i915_vma,
+ obj_link))) {
+ list_move_tail(&vma->obj_link, &still_in_list);
+ ret = i915_vma_unbind(vma);
+ if (ret)
+ break;
+ }
+ list_splice(&still_in_list, &obj->vma_list);
+
+ return ret;
+}
+
static int
drop_pages(struct drm_i915_gem_object *obj)
{
- struct i915_vma *vma, *next;
int ret;
i915_gem_object_get(obj);
- list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
- if (i915_vma_unbind(vma))
- break;
-
- ret = i915_gem_object_put_pages(obj);
+ ret = i915_gem_object_unbind(obj);
+ if (ret == 0)
+ ret = i915_gem_object_put_pages(obj);
i915_gem_object_put(obj);
return ret;
@@ -3450,8 +3470,7 @@ i915_gem_object_set_to_gtt_domain(struct
drm_i915_gem_object *obj, bool write)
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level)
{
- struct drm_device *dev = obj->base.dev;
- struct i915_vma *vma, *next;
+ struct i915_vma *vma;
int ret = 0;
if (obj->cache_level == cache_level)
@@ -3462,7 +3481,8 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
* catch the issue of the CS prefetch crossing page boundaries and
* reading an invalid PTE on older architectures.
*/
- list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
+restart:
+ list_for_each_entry(vma, &obj->vma_list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3471,11 +3491,18 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
return -EBUSY;
}
- if (!i915_gem_valid_gtt_space(vma, cache_level)) {
- ret = i915_vma_unbind(vma);
- if (ret)
- return ret;
- }
+ if (i915_gem_valid_gtt_space(vma, cache_level))
+ continue;
+
+ ret = i915_vma_unbind(vma);
+ if (ret)
+ return ret;
+
+ /* As unbinding may affect other elements in the
+* obj->vma_list (due to side-effects from retiring
+* an active vma), play safe and restart the iterator.
+*/
+ goto restart;
}
/* We can reuse the existing drm_mm nodes but need to change the
@@ -3494,7 +3521,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object
[Intel-gfx] [PATCH 39/55] drm/i915: Mark up i915_gem_active for locking annotation
The future annotations will track the locking used for access to ensure
that it is always sufficient. We make the preparations now to present
the API ahead and to make sure that GCC can eliminate the unused
parameter.
Before: 6298417 3619610 696320 10614347 a1f64b vmlinux
After: 6298417 3619610 696320 10614347 a1f64b vmlinux
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
drivers/gpu/drm/i915/i915_gem.c | 49 ++---
drivers/gpu/drm/i915/i915_gem_fence.c | 3 +-
drivers/gpu/drm/i915/i915_gem_request.h | 38 +++--
drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 29 +++
drivers/gpu/drm/i915/intel_display.c| 12 +---
8 files changed, 102 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b41561bdfb85..16fa1f527ef5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -155,10 +155,13 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->base.write_domain);
for_each_engine_id(engine, dev_priv, id)
seq_printf(m, "%x ",
- i915_gem_active_get_seqno(&obj->last_read[id]));
+ i915_gem_active_get_seqno(&obj->last_read[id],
+
&obj->base.dev->struct_mutex));
seq_printf(m, "] %x %x%s%s%s",
- i915_gem_active_get_seqno(&obj->last_write),
- i915_gem_active_get_seqno(&obj->last_fence),
+ i915_gem_active_get_seqno(&obj->last_write,
+&obj->base.dev->struct_mutex),
+ i915_gem_active_get_seqno(&obj->last_fence,
+&obj->base.dev->struct_mutex),
i915_cache_level_str(to_i915(obj->base.dev),
obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
@@ -196,7 +199,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj)
seq_printf(m, " (%s mappable)", s);
}
- engine = i915_gem_active_get_engine(&obj->last_write);
+ engine = i915_gem_active_get_engine(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (engine)
seq_printf(m, " (%s)", engine->name);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b8d541f212ff..3f6b69dcaccb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1354,21 +1354,24 @@ i915_gem_object_wait_rendering(struct
drm_i915_gem_object *obj,
int ret, i;
if (readonly) {
- request = i915_gem_active_peek(&obj->last_write);
+ request = i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex);
if (request) {
ret = i915_wait_request(request);
if (ret)
return ret;
i = request->engine->id;
- if (i915_gem_active_peek(&obj->last_read[i]) == request)
+ if (i915_gem_active_peek(&obj->last_read[i],
+&obj->base.dev->struct_mutex)
== request)
i915_gem_object_retire__read(obj, i);
else
i915_gem_object_retire__write(obj);
}
} else {
for (i = 0; i < I915_NUM_ENGINES; i++) {
- request = i915_gem_active_peek(&obj->last_read[i]);
+ request = i915_gem_active_peek(&obj->last_read[i],
+
&obj->base.dev->struct_mutex);
if (!request)
continue;
@@ -1400,9 +1403,11 @@ i915_gem_object_retire_request(struct
drm_i915_gem_object *obj,
{
int idx = req->engine->id;
- if (i915_gem_active_peek(&obj->last_read[idx]) == req)
+ if (i915_gem_active_peek(&obj->last_read[idx],
+&obj->base.dev->struct_mutex) == req)
i915_gem_object_retire__read(obj, idx);
- else if (i915_gem_active_peek(&obj->last_write) == req)
+ else if (i915_gem_active_peek(&obj->last_write,
+ &obj->base.dev->struct_mutex) == req)
i915_gem_object_retire__write(obj);
if (!i915_reset_in_progress(&req->i915->gpu_error))
@@ -1431,7 +1436,8 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem
[Intel-gfx] [PATCH 29/55] drm/i915: Simplify calling engine->sync_to
Since requests can no longer be generated as a side-effect of
intel_ring_begin(), we know that the seqno will be unchanged during
ring-emission. This predicatablity then means we do not have to check
for the seqno wrapping around whilst emitting the semaphore for
engine->sync_to().
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-31-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 13 ++-
drivers/gpu/drm/i915/i915_gem_request.c | 9 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 64 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++-
5 files changed, 30 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4d8116ece0be..76ed215eb265 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1757,7 +1757,7 @@ struct drm_i915_private {
struct i915_gem_context *kernel_context;
struct intel_engine_cs engine[I915_NUM_ENGINES];
struct drm_i915_gem_object *semaphore_obj;
- uint32_t last_seqno, next_seqno;
+ u32 next_seqno;
struct drm_dma_handle *status_page_dmah;
struct resource mch_res;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d79b949fb4c4..3df6b485d2d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2867,22 +2867,15 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
i915_gem_object_retire_request(obj, from);
} else {
int idx = intel_engine_sync_index(from->engine, to->engine);
- u32 seqno = i915_gem_request_get_seqno(from);
-
- if (seqno <= from->engine->semaphore.sync_seqno[idx])
+ if (from->fence.seqno <=
from->engine->semaphore.sync_seqno[idx])
return 0;
trace_i915_gem_ring_sync_to(to, from);
- ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
+ ret = to->engine->semaphore.sync_to(to, from);
if (ret)
return ret;
- /* We use last_read_req because sync_to()
-* might have just caused seqno wrap under
-* the radar.
-*/
- from->engine->semaphore.sync_seqno[idx] =
-
i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
+ from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
}
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index e7f4cf559a41..d7011185a4ee 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -264,14 +264,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
if (ret)
return ret;
- /* Carefully set the last_seqno value so that wrap
-* detection still works
-*/
dev_priv->next_seqno = seqno;
- dev_priv->last_seqno = seqno - 1;
- if (dev_priv->last_seqno == 0)
- dev_priv->last_seqno--;
-
return 0;
}
@@ -288,7 +281,7 @@ static int i915_gem_get_seqno(struct drm_i915_private
*dev_priv, u32 *seqno)
dev_priv->next_seqno = 1;
}
- *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
+ *seqno = dev_priv->next_seqno++;
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cb918d304c47..df9f8a58a519 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1509,12 +1509,6 @@ static int gen8_render_emit_request(struct
drm_i915_gem_request *req)
return 0;
}
-static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private
*dev_priv,
- u32 seqno)
-{
- return dev_priv->last_seqno < seqno;
-}
-
/**
* intel_ring_sync - sync the waiter to the signaller on seqno
*
@@ -1524,24 +1518,23 @@ static inline bool i915_gem_has_seqno_wrapped(struct
drm_i915_private *dev_priv,
*/
static int
-gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
- struct intel_engine_cs *signaller,
- u32 seqno)
+gen8_ring_sync(struct drm_i915_gem_request *wait,
+ struct drm_i915_gem_request *signal)
{
- struct intel_ring *waiter = waiter_req->ring;
- struct drm_i915_private *dev_priv = waiter_req->i915;
- u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id);
+ struct intel_ring *waiter = wait->ring;
+ struct drm_i915_private *dev_priv = wait->i915;
+ u64 offset = GEN8_WAIT_OFFSET(wait->engine, signal->engine->id);
struct i915_hw_ppg
[Intel-gfx] [PATCH 36/55] drm/i915: Kill drop_pages()
The drop_pages() function is a dangerous trap in that it can release the
passed in object pointer and so unless the caller is aware, it can
easily trick us into using the stale object afterwards. Move it into its
solitary callsite where we know it is safe.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9169f5f3d20c..bcc05dd2be5a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -306,20 +306,6 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
return ret;
}
-static int
-drop_pages(struct drm_i915_gem_object *obj)
-{
- int ret;
-
- i915_gem_object_get(obj);
- ret = i915_gem_object_unbind(obj);
- if (ret == 0)
- ret = i915_gem_object_put_pages(obj);
- i915_gem_object_put(obj);
-
- return ret;
-}
-
int
i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align)
@@ -340,7 +326,11 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj,
if (obj->base.filp == NULL)
return -EINVAL;
- ret = drop_pages(obj);
+ ret = i915_gem_object_unbind(obj);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_put_pages(obj);
if (ret)
return ret;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 27/55] drm/i915: Refactor golden render state emission to unconfuse gcc
GCC was inlining the init and setup functions, but was getting itself
confused into thinking that variables could be used uninitialised. If we
do the inline for gcc, it is happy! As a bonus we shrink the code.
v2: A couple of minor tweaks from Joonas
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-29-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 95
1 file changed, 27 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index a9b56d18a93b..f85c5505bce2 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -32,15 +32,14 @@ struct render_state {
const struct intel_renderstate_rodata *rodata;
struct drm_i915_gem_object *obj;
u64 ggtt_offset;
- int gen;
u32 aux_batch_size;
u32 aux_batch_offset;
};
static const struct intel_renderstate_rodata *
-render_state_get_rodata(const int gen)
+render_state_get_rodata(const struct drm_i915_gem_request *req)
{
- switch (gen) {
+ switch (INTEL_GEN(req->i915)) {
case 6:
return &gen6_null_state;
case 7:
@@ -54,36 +53,6 @@ render_state_get_rodata(const int gen)
return NULL;
}
-static int render_state_init(struct render_state *so,
-struct drm_i915_private *dev_priv)
-{
- int ret;
-
- so->gen = INTEL_GEN(dev_priv);
- so->ggtt_offset = 0; /* keep gcc quiet */
- so->rodata = render_state_get_rodata(so->gen);
- if (so->rodata == NULL)
- return 0;
-
- if (so->rodata->batch_items * 4 > 4096)
- return -EINVAL;
-
- so->obj = i915_gem_object_create(&dev_priv->drm, 4096);
- if (IS_ERR(so->obj))
- return PTR_ERR(so->obj);
-
- ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
- if (ret)
- goto free_gem;
-
- so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);
- return 0;
-
-free_gem:
- i915_gem_object_put(so->obj);
- return ret;
-}
-
/*
* Macro to add commands to auxiliary batch.
* This macro only checks for page overflow before inserting the commands,
@@ -106,6 +75,7 @@ static int render_state_setup(struct render_state *so)
{
struct drm_device *dev = so->obj->base.dev;
const struct intel_renderstate_rodata *rodata = so->rodata;
+ const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
unsigned int i = 0, reloc_index = 0;
struct page *page;
u32 *d;
@@ -124,7 +94,7 @@ static int render_state_setup(struct render_state *so)
if (i * 4 == rodata->reloc[reloc_index]) {
u64 r = s + so->ggtt_offset;
s = lower_32_bits(r);
- if (so->gen >= 8) {
+ if (has_64bit_reloc) {
if (i + 1 >= rodata->batch_items ||
rodata->batch[i + 1] != 0) {
ret = -EINVAL;
@@ -202,53 +172,40 @@ err_out:
#undef OUT_BATCH
-static void render_state_fini(struct render_state *so)
-{
- i915_gem_object_ggtt_unpin(so->obj);
- i915_gem_object_put(so->obj);
-}
-
-static int render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so)
+int i915_gem_render_state_init(struct drm_i915_gem_request *req)
{
+ struct render_state so;
int ret;
- if (WARN_ON(engine->id != RCS))
+ if (WARN_ON(req->engine->id != RCS))
return -ENOENT;
- ret = render_state_init(so, engine->i915);
- if (ret)
- return ret;
-
- if (so->rodata == NULL)
+ so.rodata = render_state_get_rodata(req);
+ if (!so.rodata)
return 0;
- ret = render_state_setup(so);
- if (ret) {
- render_state_fini(so);
- return ret;
- }
-
- return 0;
-}
+ if (so.rodata->batch_items * 4 > 4096)
+ return -EINVAL;
-int i915_gem_render_state_init(struct drm_i915_gem_request *req)
-{
- struct render_state so;
- int ret;
+ so.obj = i915_gem_object_create(&req->i915->drm, 4096);
+ if (IS_ERR(so.obj))
+ return PTR_ERR(so.obj);
- ret = render_state_prepare(req->engine, &so);
+ ret = i915_gem_obj_ggtt_pin(so.obj, 4096, 0);
if (ret)
- return ret;
+ goto err_obj;
- if (so.rodata == NULL)
- return 0;
+ so.ggtt_offset = i915_gem_obj_ggtt_offset(so.obj);
+
+ ret = render_state_setup(&so);
+ if (ret)
+ goto err_unpin;
ret = req->engine->emit_bb_start(req, so.ggtt_offset,
[Intel-gfx] [PATCH 31/55] drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
As we can now have multiple VMA inside the global GTT (with partial
mappings, rotations, etc), it is no longer true that there may just be a
single GGTT entry and so we should walk the full vma_list to count up
the actual usage. In addition to unifying the two walkers, switch from
multiplying the object size for each vma to summing the bound vma sizes.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 46 +++--
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index dccc72d63dd0..e9ff1ec19e61 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -335,6 +335,7 @@ static int per_file_stats(int id, void *ptr, void *data)
struct drm_i915_gem_object *obj = ptr;
struct file_stats *stats = data;
struct i915_vma *vma;
+ int bound = 0;
stats->count++;
stats->total += obj->base.size;
@@ -342,41 +343,30 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- if (USES_FULL_PPGTT(obj->base.dev)) {
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
- struct i915_hw_ppgtt *ppgtt;
+ list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ if (!drm_mm_node_allocated(&vma->node))
+ continue;
- if (!drm_mm_node_allocated(&vma->node))
- continue;
+ bound++;
- if (vma->is_ggtt) {
- stats->global += obj->base.size;
- continue;
- }
-
- ppgtt = container_of(vma->vm, struct i915_hw_ppgtt,
base);
+ if (vma->is_ggtt) {
+ stats->global += vma->node.size;
+ } else {
+ struct i915_hw_ppgtt *ppgtt
+ = container_of(vma->vm,
+ struct i915_hw_ppgtt,
+ base);
if (ppgtt->file_priv != stats->file_priv)
continue;
-
- if (obj->active) /* XXX per-vma statistic */
- stats->active += obj->base.size;
- else
- stats->inactive += obj->base.size;
-
- return 0;
- }
- } else {
- if (i915_gem_obj_ggtt_bound(obj)) {
- stats->global += obj->base.size;
- if (obj->active)
- stats->active += obj->base.size;
- else
- stats->inactive += obj->base.size;
- return 0;
}
+
+ if (obj->active) /* XXX per-vma statistic */
+ stats->active += vma->node.size;
+ else
+ stats->inactive += vma->node.size;
}
- if (!list_empty(&obj->global_list))
+ if (!bound)
stats->unbound += obj->base.size;
return 0;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 33/55] drm/i915: Store owning file on the i915_address_space
For the global GTT (and aliasing GTT), the address space is owned by the
device (it is a global resource) and so the per-file owner field is
NULL. For per-process GTT (where we create an address space per
context), each is owned by the opening file. We can use this ownership
information to both distinguish GGTT and ppGTT address spaces, as well
as occasionally inspect the owner.
v2: Whitespace, tells us who owns i915_address_space
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_context.c | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 +++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 17 +++--
5 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e9ff1ec19e61..2fc81865e657 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -356,7 +356,7 @@ static int per_file_stats(int id, void *ptr, void *data)
= container_of(vma->vm,
struct i915_hw_ppgtt,
base);
- if (ppgtt->file_priv != stats->file_priv)
+ if (ppgtt->base.file != stats->file_priv)
continue;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76ed215eb265..4c38307d2554 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3300,7 +3300,6 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
return container_of(vm, struct i915_hw_ppgtt, base);
}
-
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 4e233dffb592..60861f616f24 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -327,7 +327,8 @@ i915_gem_create_context(struct drm_device *dev,
return ctx;
if (USES_FULL_PPGTT(dev)) {
- struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
+ struct i915_hw_ppgtt *ppgtt =
+ i915_ppgtt_create(to_i915(dev), file_priv);
if (IS_ERR(ppgtt)) {
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 44007ec344fd..9d493b8e3bfc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2108,11 +2108,12 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
return 0;
}
-static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
+ struct drm_i915_private *dev_priv)
{
- ppgtt->base.dev = dev;
+ ppgtt->base.dev = &dev_priv->drm;
- if (INTEL_INFO(dev)->gen < 8)
+ if (INTEL_INFO(dev_priv)->gen < 8)
return gen6_ppgtt_init(ppgtt);
else
return gen8_ppgtt_init(ppgtt);
@@ -2147,15 +2148,17 @@ static void gtt_write_workarounds(struct drm_device
*dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
}
-static int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
+ struct drm_i915_private *dev_priv,
+ struct drm_i915_file_private *file_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- int ret = 0;
+ int ret;
- ret = __hw_ppgtt_init(dev, ppgtt);
+ ret = __hw_ppgtt_init(ppgtt, dev_priv);
if (ret == 0) {
kref_init(&ppgtt->ref);
i915_address_space_init(&ppgtt->base, dev_priv);
+ ppgtt->base.file = file_priv;
}
return ret;
@@ -2187,7 +2190,8 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
}
struct i915_hw_ppgtt *
-i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
+i915_ppgtt_create(struct drm_i915_private *dev_priv,
+ struct drm_i915_file_private *fpriv)
{
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -2196,14 +2200,12 @@ i915_ppgtt_create(struct drm_device *dev, struct
drm_i915_file_private *fpriv)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ret = i915_ppgtt_init(dev, ppgtt);
+ ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv);
if (ret) {
kfree(ppgtt);
return ERR_PTR(ret);
}
- ppgtt->file_priv = fpriv;
-
[Intel-gfx] [PATCH 26/55] drm/i915: Remove duplicate golden render state init from execlists
Now that we use the same vfuncs for emitting the batch buffer in both
execlists and legacy, the golden render state initialisation is
identical between both.
v2: gcc wants so.ggtt_offset initialised (even though it is not used)
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-28-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 23 +--
drivers/gpu/drm/i915/i915_gem_render_state.h | 18 ---
drivers/gpu/drm/i915/intel_lrc.c | 34 +---
drivers/gpu/drm/i915/intel_renderstate.h | 16 +
4 files changed, 28 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 2ba759f3ab6f..a9b56d18a93b 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -28,6 +28,15 @@
#include "i915_drv.h"
#include "intel_renderstate.h"
+struct render_state {
+ const struct intel_renderstate_rodata *rodata;
+ struct drm_i915_gem_object *obj;
+ u64 ggtt_offset;
+ int gen;
+ u32 aux_batch_size;
+ u32 aux_batch_offset;
+};
+
static const struct intel_renderstate_rodata *
render_state_get_rodata(const int gen)
{
@@ -51,6 +60,7 @@ static int render_state_init(struct render_state *so,
int ret;
so->gen = INTEL_GEN(dev_priv);
+ so->ggtt_offset = 0; /* keep gcc quiet */
so->rodata = render_state_get_rodata(so->gen);
if (so->rodata == NULL)
return 0;
@@ -192,14 +202,14 @@ err_out:
#undef OUT_BATCH
-void i915_gem_render_state_fini(struct render_state *so)
+static void render_state_fini(struct render_state *so)
{
i915_gem_object_ggtt_unpin(so->obj);
i915_gem_object_put(so->obj);
}
-int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so)
+static int render_state_prepare(struct intel_engine_cs *engine,
+ struct render_state *so)
{
int ret;
@@ -215,7 +225,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs
*engine,
ret = render_state_setup(so);
if (ret) {
- i915_gem_render_state_fini(so);
+ render_state_fini(so);
return ret;
}
@@ -227,7 +237,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request
*req)
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(req->engine, &so);
+ ret = render_state_prepare(req->engine, &so);
if (ret)
return ret;
@@ -251,8 +261,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request
*req)
}
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
-
out:
- i915_gem_render_state_fini(&so);
+ render_state_fini(&so);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h
b/drivers/gpu/drm/i915/i915_gem_render_state.h
index 6aaa3a10a630..c44fca8599bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.h
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -26,24 +26,6 @@
#include
-struct intel_renderstate_rodata {
- const u32 *reloc;
- const u32 *batch;
- const u32 batch_items;
-};
-
-struct render_state {
- const struct intel_renderstate_rodata *rodata;
- struct drm_i915_gem_object *obj;
- u64 ggtt_offset;
- int gen;
- u32 aux_batch_size;
- u32 aux_batch_offset;
-};
-
int i915_gem_render_state_init(struct drm_i915_gem_request *req);
-void i915_gem_render_state_fini(struct render_state *so);
-int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
- struct render_state *so);
#endif /* _I915_GEM_RENDER_STATE_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 42b50ec0719a..c86f8c453b6a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1803,38 +1803,6 @@ static int gen8_emit_request_render(struct
drm_i915_gem_request *request)
return intel_logical_ring_advance(request);
}
-static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
-{
- struct render_state so;
- int ret;
-
- ret = i915_gem_render_state_prepare(req->engine, &so);
- if (ret)
- return ret;
-
- if (so.rodata == NULL)
- return 0;
-
- ret = req->engine->emit_bb_start(req, so.ggtt_offset,
-so.rodata->batch_items * 4,
-I915_DISPATCH_SECURE);
- if (ret)
- goto out;
-
- ret = req->engine->emit_bb_start(req,
-(so.ggtt_offset + so.aux_batch_offset),
-
[Intel-gfx] [PATCH 25/55] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores
As gen6_emit_request() only differs from i9xx_emit_request() when
semaphores are enabled, only use the specialised vfunc in that scenario.
v2: Reorder semaphore init so as to keep engine->emit_request default
vfunc selection compact.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-27-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index df87bb7aefbd..3471e19fc784 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1457,22 +1457,20 @@ static int i9xx_emit_request(struct
drm_i915_gem_request *req)
}
/**
- * gen6_emit_request - Update the semaphore mailbox registers
+ * gen6_sema_emit_request - Update the semaphore mailbox registers
*
* @request - request to write to the ring
*
* Update the mailbox registers in the *other* rings with the current seqno.
* This acts like a signal in the canonical semaphore.
*/
-static int gen6_emit_request(struct drm_i915_gem_request *req)
+static int gen6_sema_emit_request(struct drm_i915_gem_request *req)
{
- if (req->engine->semaphore.signal) {
- int ret;
+ int ret;
- ret = req->engine->semaphore.signal(req);
- if (ret)
- return ret;
- }
+ ret = req->engine->semaphore.signal(req);
+ if (ret)
+ return ret;
return i9xx_emit_request(req);
}
@@ -2802,12 +2800,15 @@ static void intel_ring_init_irq(struct drm_i915_private
*dev_priv,
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
+ intel_ring_init_irq(dev_priv, engine);
+ intel_ring_init_semaphores(dev_priv, engine);
+
engine->init_hw = init_ring_common;
engine->emit_request = i9xx_emit_request;
- if (INTEL_GEN(dev_priv) >= 6)
- engine->emit_request = gen6_emit_request;
engine->submit_request = i9xx_submit_request;
+ if (i915.semaphores)
+ engine->emit_request = gen6_sema_emit_request;
if (INTEL_GEN(dev_priv) >= 8)
engine->emit_bb_start = gen8_emit_bb_start;
@@ -2819,9 +2820,6 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
engine->emit_bb_start = i830_emit_bb_start;
else
engine->emit_bb_start = i915_emit_bb_start;
-
- intel_ring_init_irq(dev_priv, engine);
- intel_ring_init_semaphores(dev_priv, engine);
}
int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 24/55] drm/i915: Reuse legacy breadcrumbs + tail emission
As GEN6+ is now a simple variant on the basic breadcrumbs + tail write,
reuse the common code.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-26-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 74 +
1 file changed, 30 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fbda43841d7f..df87bb7aefbd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1428,26 +1428,19 @@ static int gen6_signal(struct drm_i915_gem_request
*signaller_req)
return 0;
}
-/**
- * gen6_emit_request - Update the semaphore mailbox registers
- *
- * @request - request to write to the ring
- *
- * Update the mailbox registers in the *other* rings with the current seqno.
- * This acts like a signal in the canonical semaphore.
- */
-static int gen6_emit_request(struct drm_i915_gem_request *req)
+static void i9xx_submit_request(struct drm_i915_gem_request *request)
+{
+ struct drm_i915_private *dev_priv = request->i915;
+
+ I915_WRITE_TAIL(request->engine,
+ request->tail % (request->ring->size - 1));
+}
+
+static int i9xx_emit_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->engine;
struct intel_ring *ring = req->ring;
int ret;
- if (engine->semaphore.signal) {
- ret = engine->semaphore.signal(req);
- if (ret)
- return ret;
- }
-
ret = intel_ring_begin(req, 4);
if (ret)
return ret;
@@ -1463,6 +1456,27 @@ static int gen6_emit_request(struct drm_i915_gem_request
*req)
return 0;
}
+/**
+ * gen6_emit_request - Update the semaphore mailbox registers
+ *
+ * @request - request to write to the ring
+ *
+ * Update the mailbox registers in the *other* rings with the current seqno.
+ * This acts like a signal in the canonical semaphore.
+ */
+static int gen6_emit_request(struct drm_i915_gem_request *req)
+{
+ if (req->engine->semaphore.signal) {
+ int ret;
+
+ ret = req->engine->semaphore.signal(req);
+ if (ret)
+ return ret;
+ }
+
+ return i9xx_emit_request(req);
+}
+
static int gen8_render_emit_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
@@ -1697,34 +1711,6 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
return 0;
}
-static int i9xx_emit_request(struct drm_i915_gem_request *req)
-{
- struct intel_ring *ring = req->ring;
- int ret;
-
- ret = intel_ring_begin(req, 4);
- if (ret)
- return ret;
-
- intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
- intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(ring, req->fence.seqno);
- intel_ring_emit(ring, MI_USER_INTERRUPT);
- intel_ring_advance(ring);
-
- req->tail = ring->tail;
-
- return 0;
-}
-
-static void i9xx_submit_request(struct drm_i915_gem_request *request)
-{
- struct drm_i915_private *dev_priv = request->i915;
-
- I915_WRITE_TAIL(request->engine,
- request->tail % (request->ring->size - 1));
-}
-
static void
gen6_irq_enable(struct intel_engine_cs *engine)
{
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/55] drm/i915: Rename residual ringbuf parameters
Now that we have a clear ring/engine split and a struct intel_ring, we
no longer need the stopgap ringbuf names.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-16-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 66 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +--
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index acbabbdececd..5dd720e7feaa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -47,15 +47,15 @@ int __intel_ring_space(int head, int tail, int size)
return space - I915_RING_FREE_SPACE;
}
-void intel_ring_update_space(struct intel_ring *ringbuf)
+void intel_ring_update_space(struct intel_ring *ring)
{
- if (ringbuf->last_retired_head != -1) {
- ringbuf->head = ringbuf->last_retired_head;
- ringbuf->last_retired_head = -1;
+ if (ring->last_retired_head != -1) {
+ ring->head = ring->last_retired_head;
+ ring->last_retired_head = -1;
}
- ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
- ringbuf->tail, ringbuf->size);
+ ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
+ring->tail, ring->size);
}
static void __intel_engine_submit(struct intel_engine_cs *engine)
@@ -1993,25 +1993,25 @@ static int init_phys_status_page(struct intel_engine_cs
*engine)
return 0;
}
-void intel_unpin_ring(struct intel_ring *ringbuf)
+void intel_unpin_ring(struct intel_ring *ring)
{
- GEM_BUG_ON(!ringbuf->vma);
- GEM_BUG_ON(!ringbuf->vaddr);
+ GEM_BUG_ON(!ring->vma);
+ GEM_BUG_ON(!ring->vaddr);
- if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
- i915_gem_object_unpin_map(ringbuf->obj);
+ if (HAS_LLC(ring->obj->base.dev) && !ring->obj->stolen)
+ i915_gem_object_unpin_map(ring->obj);
else
- i915_vma_unpin_iomap(ringbuf->vma);
- ringbuf->vaddr = NULL;
+ i915_vma_unpin_iomap(ring->vma);
+ ring->vaddr = NULL;
- i915_gem_object_ggtt_unpin(ringbuf->obj);
- ringbuf->vma = NULL;
+ i915_gem_object_ggtt_unpin(ring->obj);
+ ring->vma = NULL;
}
int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ringbuf)
+ struct intel_ring *ring)
{
- struct drm_i915_gem_object *obj = ringbuf->obj;
+ struct drm_i915_gem_object *obj = ring->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
void *addr;
@@ -2052,8 +2052,8 @@ int intel_pin_and_map_ring(struct drm_i915_private
*dev_priv,
}
}
- ringbuf->vaddr = addr;
- ringbuf->vma = i915_gem_obj_to_ggtt(obj);
+ ring->vaddr = addr;
+ ring->vma = i915_gem_obj_to_ggtt(obj);
return 0;
err_unpin:
@@ -2061,29 +2061,29 @@ err_unpin:
return ret;
}
-static void intel_destroy_ringbuffer_obj(struct intel_ring *ringbuf)
+static void intel_destroy_ringbuffer_obj(struct intel_ring *ring)
{
- i915_gem_object_put(ringbuf->obj);
- ringbuf->obj = NULL;
+ i915_gem_object_put(ring->obj);
+ ring->obj = NULL;
}
static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
- struct intel_ring *ringbuf)
+ struct intel_ring *ring)
{
struct drm_i915_gem_object *obj;
obj = NULL;
if (!HAS_LLC(dev))
- obj = i915_gem_object_create_stolen(dev, ringbuf->size);
+ obj = i915_gem_object_create_stolen(dev, ring->size);
if (obj == NULL)
- obj = i915_gem_object_create(dev, ringbuf->size);
+ obj = i915_gem_object_create(dev, ring->size);
if (IS_ERR(obj))
return PTR_ERR(obj);
/* mark ring buffers as read-only from GPU side by default */
obj->gt_ro = 1;
- ringbuf->obj = obj;
+ ring->obj = obj;
return 0;
}
@@ -2190,7 +2190,7 @@ static void intel_ring_context_unpin(struct
i915_gem_context *ctx,
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct intel_ring *ringbuf;
+ struct intel_ring *ring;
int ret;
WARN_ON(engine->buffer);
@@ -2215,12 +2215,12 @@ static int intel_init_ring_buffer(struct
intel_engine_cs *engine)
if (ret)
goto error;
- ringbuf = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
- if (IS_ERR(ringbuf)) {
-
[Intel-gfx] [PATCH 28/55] drm/i915: Unify legacy/execlists submit_execbuf callbacks
Now that emitting requests is identical between legacy and execlists, we
can use the same function to build up the ring for submitting to either
engine. (With the exception of i915_switch_contexts(), but in time that
will also be handled gracefully.)
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-30-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 20 -
drivers/gpu/drm/i915/i915_gem.c| 2 -
drivers/gpu/drm/i915/i915_gem_context.c| 7 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 24 --
drivers/gpu/drm/i915/intel_lrc.c | 123 -
drivers/gpu/drm/i915/intel_lrc.h | 4 -
drivers/gpu/drm/i915/intel_ringbuffer.c| 6 +-
7 files changed, 23 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2259983d2ec6..4d8116ece0be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1705,18 +1705,6 @@ struct i915_virtual_gpu {
bool active;
};
-struct i915_execbuffer_params {
- struct drm_device *dev;
- struct drm_file *file;
- uint32_tdispatch_flags;
- uint32_targs_batch_start_offset;
- uint64_tbatch_obj_vm_offset;
- struct intel_engine_cs *engine;
- struct drm_i915_gem_object *batch_obj;
- struct i915_gem_context*ctx;
- struct drm_i915_gem_request *request;
-};
-
/* used in computing the new watermarks state */
struct intel_wm_config {
unsigned int num_pipes_active;
@@ -2016,9 +2004,6 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
struct {
- int (*execbuf_submit)(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
void (*cleanup_engine)(struct intel_engine_cs *engine);
void (*stop_engine)(struct intel_engine_cs *engine);
@@ -2993,11 +2978,6 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
- struct drm_i915_gem_request *req);
-int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b6c4ff63725f..d79b949fb4c4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4534,11 +4534,9 @@ int i915_gem_init(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
if (!i915.enable_execlists) {
- dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
dev_priv->gt.cleanup_engine = intel_engine_cleanup;
dev_priv->gt.stop_engine = intel_engine_stop;
} else {
- dev_priv->gt.execbuf_submit = intel_execlists_submission;
dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
dev_priv->gt.stop_engine = intel_logical_ring_stop;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index beece8feb8fe..4e233dffb592 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -894,8 +894,9 @@ int i915_switch_context(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- WARN_ON(i915.enable_execlists);
lockdep_assert_held(&req->i915->drm.struct_mutex);
+ if (i915.enable_execlists)
+ return 0;
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -943,9 +944,7 @@ int i915_gem_switch_to_kernel_context(struct
drm_i915_private *dev_priv)
if (IS_ERR(req))
return PTR_ERR(req);
- ret = 0;
- if (!i915.enable_execlists)
- ret = i915_switch_context(req);
+ ret = i915_switch_context(req);
i915_add_request_no_flush(req);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i9
[Intel-gfx] [PATCH 22/55] drm/i915/lrc: Update function names to match request flow
With adding engine->submit_request, we now have a bunch of functions
with similar names used at different stages of the execlist submission.
Try a different coat of paint, to hopefully reduce confusion between the
requests, intel_engine_cs and the actual execlists submision process.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-24-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 51818a883f0c..42b50ec0719a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -384,8 +384,8 @@ static void execlists_update_context(struct
drm_i915_gem_request *rq)
execlists_update_context_pdps(ppgtt, reg_state);
}
-static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
- struct drm_i915_gem_request *rq1)
+static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
+ struct drm_i915_gem_request *rq1)
{
struct drm_i915_private *dev_priv = rq0->i915;
unsigned int fw_domains = rq0->engine->fw_domains;
@@ -418,7 +418,7 @@ static inline void execlists_context_status_change(
atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
}
-static void execlists_context_unqueue(struct intel_engine_cs *engine)
+static void execlists_unqueue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
struct drm_i915_gem_request *cursor, *tmp;
@@ -486,7 +486,7 @@ static void execlists_context_unqueue(struct
intel_engine_cs *engine)
req0->tail &= req0->ring->size - 1;
}
- execlists_submit_requests(req0, req1);
+ execlists_elsp_submit_contexts(req0, req1);
}
static unsigned int
@@ -597,7 +597,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (submit_contexts) {
if (!engine->disable_lite_restore_wa ||
(csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
- execlists_context_unqueue(engine);
+ execlists_unqueue(engine);
}
spin_unlock(&engine->execlist_lock);
@@ -606,7 +606,7 @@ static void intel_lrc_irq_handler(unsigned long data)
DRM_ERROR("More than two context complete events?\n");
}
-static void execlists_context_queue(struct drm_i915_gem_request *request)
+static void execlists_submit_request(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
struct drm_i915_gem_request *cursor;
@@ -637,7 +637,7 @@ static void execlists_context_queue(struct
drm_i915_gem_request *request)
list_add_tail(&request->execlist_link, &engine->execlist_queue);
request->ctx_hw_id = request->ctx->hw_id;
if (num_elements == 0)
- execlists_context_unqueue(engine);
+ execlists_unqueue(engine);
spin_unlock_bh(&engine->execlist_lock);
}
@@ -1908,7 +1908,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->init_hw = gen8_init_common_ring;
engine->emit_flush = gen8_emit_flush;
engine->emit_request = gen8_emit_request;
- engine->submit_request = execlists_context_queue;
+ engine->submit_request = execlists_submit_request;
engine->irq_enable = gen8_logical_ring_enable_irq;
engine->irq_disable = gen8_logical_ring_disable_irq;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/55] drm/i915: Remove intel_ring_get_tail()
Joonas doesn't like the tiny function, especially if I go around making
it more complicated and using it elsewhere. To remove that temptation,
remove the function!
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-21-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_request.c | 8
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 47e46c9da4e7..44cdca9a2194 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -419,7 +419,7 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
* should already have been reserved in the ring buffer. Let the ring
* know that it is time to use that space up.
*/
- request_start = intel_ring_get_tail(ring);
+ request_start = ring->tail;
reserved_tail = request->reserved_space;
request->reserved_space = 0;
@@ -464,19 +464,19 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
* GPU processing the request, we never over-estimate the
* position of the head.
*/
- request->postfix = intel_ring_get_tail(ring);
+ request->postfix = ring->tail;
if (i915.enable_execlists) {
ret = engine->emit_request(request);
} else {
ret = engine->add_request(request);
- request->tail = intel_ring_get_tail(ring);
+ request->tail = ring->tail;
}
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
/* Sanity check that the reserved size was large enough. */
- ret = intel_ring_get_tail(ring) - request_start;
+ ret = ring->tail - request_start;
if (ret < 0)
ret += ring->size;
WARN_ONCE(ret > reserved_tail,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1ec7b47f6188..d5a866ddaded 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -488,11 +488,6 @@ static inline u32 intel_engine_get_seqno(struct
intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine);
-static inline u32 intel_ring_get_tail(struct intel_ring *ring)
-{
- return ring->tail;
-}
-
/*
* Arbitrary size for largest possible 'add request' sequence. The code paths
* are complex and variable. Empirical measurement shows that the worst case
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/55] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal()
Rather than pass in the num_dwords that the caller wishes to use after
the signal command packet, split the breadcrumb emission into two phases
and have both the signal and breadcrumb individiually acquire space on
the ring. This makes the interface simpler for the reader, and will
simplify for patches.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-25-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 51 ++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
2 files changed, 23 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 27e5f081893c..fbda43841d7f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1322,10 +1322,8 @@ static void render_ring_cleanup(struct intel_engine_cs
*engine)
intel_fini_pipe_control(engine);
}
-static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
{
-#define MBOX_UPDATE_DWORDS 8
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
@@ -1333,10 +1331,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req,
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
if (ret)
return ret;
@@ -1360,14 +1355,13 @@ static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req,
MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
+ intel_ring_advance(signaller);
return 0;
}
-static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
{
-#define MBOX_UPDATE_DWORDS 6
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
@@ -1375,10 +1369,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req,
int ret, num_rings;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
if (ret)
return ret;
@@ -1400,12 +1391,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req,
MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
}
+ intel_ring_advance(signaller);
return 0;
}
-static int gen6_signal(struct drm_i915_gem_request *signaller_req,
- unsigned int num_dwords)
+static int gen6_signal(struct drm_i915_gem_request *signaller_req)
{
struct intel_ring *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
@@ -1413,12 +1404,8 @@ static int gen6_signal(struct drm_i915_gem_request
*signaller_req,
enum intel_engine_id id;
int ret, num_rings;
-#define MBOX_UPDATE_DWORDS 3
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
- num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
-#undef MBOX_UPDATE_DWORDS
-
- ret = intel_ring_begin(signaller_req, num_dwords);
+ ret = intel_ring_begin(signaller_req, round_up((num_rings-1) * 3, 2));
if (ret)
return ret;
@@ -1436,6 +1423,7 @@ static int gen6_signal(struct drm_i915_gem_request
*signaller_req,
/* If num_dwords was rounded, make sure the tail pointer is correct */
if (num_rings % 2 == 0)
intel_ring_emit(signaller, MI_NOOP);
+ intel_ring_advance(signaller);
return 0;
}
@@ -1454,11 +1442,13 @@ static int gen6_emit_request(struct
drm_i915_gem_request *req)
struct intel_ring *ring = req->ring;
int ret;
- if (engine->semaphore.signal)
- ret = engine->semaphore.signal(req, 4);
- else
- ret = intel_ring_begin(req, 4);
+ if (engine->semaphore.signal) {
+ ret = engine->semaphore.signal(req);
+ if (ret)
+ return ret;
+ }
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret
[Intel-gfx] [PATCH 16/55] drm/i915: Remove obsolete engine->gpu_caches_dirty
Space for flushing the GPU cache prior to completing the request is
preallocated and so cannot fail - the GPU caches will always be flushed
along with the completed request. This means we no longer have to track
whether the GPU cache is dirty between batches like we had to with the
outstanding_lazy_seqno.
With the removal of the duplication in the per-backend entry points for
emitting the obsolete lazy flush, we can then further unify the
engine->emit_flush.
v2: Expand a bit on the legacy of gpu_caches_dirty
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c| 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +---
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++--
drivers/gpu/drm/i915/i915_gem_request.c| 8 ++--
drivers/gpu/drm/i915/intel_lrc.c | 47 +++
drivers/gpu/drm/i915/intel_lrc.h | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.c| 72 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 7 ---
8 files changed, 37 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3336a5fcd029..beece8feb8fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32
hw_flags)
* itlb_before_ctx_switch.
*/
if (IS_GEN6(dev_priv)) {
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
+ ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d0ef675fb169..35c4c595e5ba 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct
drm_i915_gem_request *req,
if (flush_domains & I915_GEM_DOMAIN_GTT)
wmb();
- /* Unconditionally invalidate gpu caches and ensure that we do flush
-* any residual writes from the previous batch.
-*/
- return intel_engine_invalidate_all_caches(req);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
}
static bool
@@ -1163,9 +1161,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
static void
i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
{
- /* Unconditionally force add_request to emit a full flush. */
- params->engine->gpu_caches_dirty = true;
-
/* Add a breadcrumb for the completion of the batch buffer */
__i915_add_request(params->request, params->batch_obj, true);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ebfa0406a6a1..39fa9eb10514 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1666,7 +1666,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1693,7 +1694,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1711,8 +1713,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
/* XXX: RCS is the only one to auto invalidate the TLBs? */
if (engine->id != RCS) {
- ret = engine->flush(req,
- I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req,
+I915_GEM_GPU_DOMAINS,
+I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 942b5b1f1602..7e3206051ced 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -451,12 +451,10 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
* what.
*/
if (flush_caches) {
- if (i915.enable_execlists)
- ret = logical
[Intel-gfx] [PATCH 17/55] drm/i915: Simplify request_alloc by returning the allocated request
If is simpler and leads to more readable code through the callstack if
the allocation returns the allocated struct through the return value.
The importance of this is that it no longer looks like we accidentally
allocate requests as side-effect of calling certain functions.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-19-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 3 +-
drivers/gpu/drm/i915/i915_gem.c| 75 --
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++---
drivers/gpu/drm/i915/i915_gem_request.c| 58 ---
drivers/gpu/drm/i915/i915_trace.h | 13 +++---
drivers/gpu/drm/i915/intel_display.c | 36 ++
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 20
8 files changed, 79 insertions(+), 140 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7e298b4253e..2259983d2ec6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3171,8 +3171,7 @@ static inline void i915_gem_object_unpin_map(struct
drm_i915_gem_object *obj)
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
-struct intel_engine_cs *to,
-struct drm_i915_gem_request **to_req);
+struct drm_i915_gem_request *to);
void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req);
int i915_gem_dumb_create(struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 59890f523c5f..b6c4ff63725f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2845,51 +2845,35 @@ out:
static int
__i915_gem_object_sync(struct drm_i915_gem_object *obj,
- struct intel_engine_cs *to,
- struct drm_i915_gem_request *from_req,
- struct drm_i915_gem_request **to_req)
+ struct drm_i915_gem_request *to,
+ struct drm_i915_gem_request *from)
{
- struct intel_engine_cs *from;
int ret;
- from = i915_gem_request_get_engine(from_req);
- if (to == from)
+ if (to->engine == from->engine)
return 0;
- if (i915_gem_request_completed(from_req))
+ if (i915_gem_request_completed(from))
return 0;
if (!i915.semaphores) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- ret = __i915_wait_request(from_req,
- i915->mm.interruptible,
+ ret = __i915_wait_request(from,
+ from->i915->mm.interruptible,
NULL,
NO_WAITBOOST);
if (ret)
return ret;
- i915_gem_object_retire_request(obj, from_req);
+ i915_gem_object_retire_request(obj, from);
} else {
- int idx = intel_engine_sync_index(from, to);
- u32 seqno = i915_gem_request_get_seqno(from_req);
+ int idx = intel_engine_sync_index(from->engine, to->engine);
+ u32 seqno = i915_gem_request_get_seqno(from);
- WARN_ON(!to_req);
-
- if (seqno <= from->semaphore.sync_seqno[idx])
+ if (seqno <= from->engine->semaphore.sync_seqno[idx])
return 0;
- if (*to_req == NULL) {
- struct drm_i915_gem_request *req;
-
- req = i915_gem_request_alloc(to, NULL);
- if (IS_ERR(req))
- return PTR_ERR(req);
-
- *to_req = req;
- }
-
- trace_i915_gem_ring_sync_to(*to_req, from, from_req);
- ret = to->semaphore.sync_to(*to_req, from, seqno);
+ trace_i915_gem_ring_sync_to(to, from);
+ ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
if (ret)
return ret;
@@ -2897,8 +2881,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
* might have just caused seqno wrap under
* the radar.
*/
- from->semaphore.sync_seqno[idx] =
-
i915_gem_request_get_seqno(obj->last_read_req[from->id]);
+ from->engine->semaphore.sync_seqno[idx] =
+
i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
}
return 0;
@@ -2908,17 +2892,12 @@ __i915_gem_object_sync(struct drm_i915_gem_object
[Intel-gfx] [PATCH 15/55] drm/i915: Rename intel_pin_and_map_ring()
For more consistent oop-naming, we would use intel_ring_verb, so pick
intel_ring_pin() and intel_ring_unpin().
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-17-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c| 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 38 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a664f258e2c..86b8f41c254d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -973,7 +973,7 @@ static int intel_lr_context_pin(struct i915_gem_context
*ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ret = intel_pin_and_map_ring(dev_priv, ce->ring);
+ ret = intel_ring_pin(ce->ring);
if (ret)
goto unpin_map;
@@ -1011,7 +1011,7 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx,
if (--ce->pin_count)
return;
- intel_unpin_ring(ce->ring);
+ intel_ring_unpin(ce->ring);
i915_gem_object_unpin_map(ce->state);
i915_gem_object_ggtt_unpin(ce->state);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5dd720e7feaa..e7a7f67ab06d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1993,24 +1993,9 @@ static int init_phys_status_page(struct intel_engine_cs
*engine)
return 0;
}
-void intel_unpin_ring(struct intel_ring *ring)
-{
- GEM_BUG_ON(!ring->vma);
- GEM_BUG_ON(!ring->vaddr);
-
- if (HAS_LLC(ring->obj->base.dev) && !ring->obj->stolen)
- i915_gem_object_unpin_map(ring->obj);
- else
- i915_vma_unpin_iomap(ring->vma);
- ring->vaddr = NULL;
-
- i915_gem_object_ggtt_unpin(ring->obj);
- ring->vma = NULL;
-}
-
-int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ring)
+int intel_ring_pin(struct intel_ring *ring)
{
+ struct drm_i915_private *dev_priv = ring->engine->i915;
struct drm_i915_gem_object *obj = ring->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
@@ -2061,6 +2046,21 @@ err_unpin:
return ret;
}
+void intel_ring_unpin(struct intel_ring *ring)
+{
+ GEM_BUG_ON(!ring->vma);
+ GEM_BUG_ON(!ring->vaddr);
+
+ if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen)
+ i915_gem_object_unpin_map(ring->obj);
+ else
+ i915_vma_unpin_iomap(ring->vma);
+ ring->vaddr = NULL;
+
+ i915_gem_object_ggtt_unpin(ring->obj);
+ ring->vma = NULL;
+}
+
static void intel_destroy_ringbuffer_obj(struct intel_ring *ring)
{
i915_gem_object_put(ring->obj);
@@ -2233,7 +2233,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs
*engine)
goto error;
}
- ret = intel_pin_and_map_ring(dev_priv, ring);
+ ret = intel_ring_pin(ring);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
@@ -2261,7 +2261,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
intel_engine_stop(engine);
WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) &
MODE_IDLE) == 0);
- intel_unpin_ring(engine->buffer);
+ intel_ring_unpin(engine->buffer);
intel_ring_free(engine->buffer);
engine->buffer = NULL;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 2dfc418c5102..ba54ffcdd55a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -441,9 +441,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
struct intel_ring *
intel_engine_create_ring(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ring(struct drm_i915_private *dev_priv,
- struct intel_ring *ring);
-void intel_unpin_ring(struct intel_ring *ring);
+int intel_ring_pin(struct intel_ring *ring);
+void intel_ring_unpin(struct intel_ring *ring);
void intel_ring_free(struct intel_ring *ring);
void intel_engine_stop(struct intel_engine_cs *engine);
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/55] drm/i915: Use engine to refer to the user's BSD intel_engine_cs
This patch transitions the execbuf engine selection away from using the
ring nomenclature - though we still refer to the user's incoming
selector as their user_ring_id.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-7-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h| 4 ++--
drivers/gpu/drm/i915/i915_gem.c| 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ---
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea9b95335a67..97f827979a66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -402,7 +402,7 @@ struct drm_i915_file_private {
unsigned boosts;
} rps;
- unsigned int bsd_ring;
+ unsigned int bsd_engine;
};
/* Used by dp and fdi links */
@@ -1331,7 +1331,7 @@ struct i915_gem_mm {
bool interruptible;
/* the indicator for dispatch video commands on two BSD rings */
- unsigned int bsd_ring_dispatch_index;
+ unsigned int bsd_engine_dispatch_index;
/** Bit 6 swizzling required for X tiling */
uint32_t bit_6_swizzle_x;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3730aecc1eae..e155e8dd28ed 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4782,7 +4782,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file
*file)
spin_lock_init(&file_priv->mm.lock);
INIT_LIST_HEAD(&file_priv->mm.request_list);
- file_priv->bsd_ring = -1;
+ file_priv->bsd_engine = -1;
ret = i915_gem_context_open(dev, file);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index cd3f87345757..aa35867f3032 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1351,23 +1351,24 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
/**
* Find one BSD ring to dispatch the corresponding BSD command.
- * The ring index is returned.
+ * The engine index is returned.
*/
static unsigned int
-gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file
*file)
+gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
+struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
/* Check whether the file_priv has already selected one ring. */
- if ((int)file_priv->bsd_ring < 0) {
+ if ((int)file_priv->bsd_engine < 0) {
/* If not, use the ping-pong mechanism to select one. */
mutex_lock(&dev_priv->drm.struct_mutex);
- file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
- dev_priv->mm.bsd_ring_dispatch_index ^= 1;
+ file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index;
+ dev_priv->mm.bsd_engine_dispatch_index ^= 1;
mutex_unlock(&dev_priv->drm.struct_mutex);
}
- return file_priv->bsd_ring;
+ return file_priv->bsd_engine;
}
#define I915_USER_RINGS (4)
@@ -1404,7 +1405,7 @@ eb_select_engine(struct drm_i915_private *dev_priv,
unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
+ bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
--
2.8.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/55] drm/i915: Rename struct intel_ringbuffer to struct intel_ring
The state stored in this struct is not only the information about the
buffer object, but the ring used to communicate with the hardware. Using
buffer here is overly specific and, for me at least, conflates with the
notion of buffer objects themselves.
s/struct intel_ringbuffer/struct intel_ring/
s/enum intel_ring_hangcheck/enum intel_engine_hangcheck/
s/describe_ctx_ringbuf()/describe_ctx_ring()/
s/intel_ring_get_active_head()/intel_engine_get_active_head()/
s/intel_ring_sync_index()/intel_engine_sync_index()/
s/intel_ring_init_seqno()/intel_engine_init_seqno()/
s/ring_stuck()/engine_stuck()/
s/intel_cleanup_engine()/intel_engine_cleanup()/
s/intel_stop_engine()/intel_engine_stop()/
s/intel_pin_and_map_ringbuffer_obj()/intel_pin_and_map_ring()/
s/intel_unpin_ringbuffer()/intel_unpin_ring()/
s/intel_engine_create_ringbuffer()/intel_engine_create_ring()/
s/intel_ring_flush_all_caches()/intel_engine_flush_all_caches()/
s/intel_ring_invalidate_all_caches()/intel_engine_invalidate_all_caches()/
s/intel_ringbuffer_free()/intel_ring_free()/
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-15-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c| 11 ++-
drivers/gpu/drm/i915/i915_drv.h| 4 +-
drivers/gpu/drm/i915/i915_gem.c| 16 ++--
drivers/gpu/drm/i915/i915_gem_context.c| 6 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 6 +-
drivers/gpu/drm/i915/i915_gem_request.c| 6 +-
drivers/gpu/drm/i915/i915_gem_request.h| 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c| 14 ++--
drivers/gpu/drm/i915/intel_display.c | 10 +--
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 34
drivers/gpu/drm/i915/intel_mocs.c | 4 +-
drivers/gpu/drm/i915/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 128 ++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 51 ++--
17 files changed, 157 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bde68741809b..dccc72d63dd0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1419,7 +1419,7 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
for_each_engine_id(engine, dev_priv, id) {
- acthd[id] = intel_ring_get_active_head(engine);
+ acthd[id] = intel_engine_get_active_head(engine);
seqno[id] = intel_engine_get_seqno(engine);
}
@@ -2017,12 +2017,11 @@ static int i915_gem_framebuffer_info(struct seq_file
*m, void *data)
return 0;
}
-static void describe_ctx_ringbuf(struct seq_file *m,
-struct intel_ringbuffer *ringbuf)
+static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
{
seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head:
%d)",
- ringbuf->space, ringbuf->head, ringbuf->tail,
- ringbuf->last_retired_head);
+ ring->space, ring->head, ring->tail,
+ ring->last_retired_head);
}
static int i915_context_status(struct seq_file *m, void *unused)
@@ -2067,7 +2066,7 @@ static int i915_context_status(struct seq_file *m, void
*unused)
if (ce->state)
describe_obj(m, ce->state);
if (ce->ring)
- describe_ctx_ringbuf(m, ce->ring);
+ describe_ctx_ring(m, ce->ring);
seq_putc(m, '\n');
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2067e195c16..b7e298b4253e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -518,7 +518,7 @@ struct drm_i915_error_state {
bool waiting;
int num_waiters;
int hangcheck_score;
- enum intel_ring_hangcheck_action hangcheck_action;
+ enum intel_engine_hangcheck_action hangcheck_action;
int num_requests;
/* our own tracking of ring head and tail */
@@ -894,7 +894,7 @@ struct i915_gem_context {
struct intel_context {
struct drm_i915_gem_object *state;
- struct intel_ringbuffer *ring;
+ struct intel_ring *ring;
struct i915_vma *lrc_vma;
uint32_t *lrc_reg_state;
u64 lrc_desc;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7bfce1d5c61b..59890f523c5f 100644
--- a/drivers/gpu/drm/i915/i915_gem.
[Intel-gfx] [PATCH 21/55] drm/i915: Unify request submission
Move request submission from emit_request into its own common vfunc
from i915_add_request().
v2: Convert I915_DISPATCH_flags to BIT(x) whilst passing
v3: Rename a few functions to match.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-23-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_request.c| 8 +++-
drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++---
drivers/gpu/drm/i915/intel_guc.h | 1 -
drivers/gpu/drm/i915/intel_lrc.c | 18 +++---
drivers/gpu/drm/i915/intel_ringbuffer.c| 23 +--
drivers/gpu/drm/i915/intel_ringbuffer.h| 23 +++
6 files changed, 36 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 8af514e42c30..e7f4cf559a41 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -466,12 +466,9 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
*/
request->postfix = ring->tail;
- if (i915.enable_execlists)
- ret = engine->emit_request(request);
- else
- ret = engine->add_request(request);
/* Not allowed to fail! */
- WARN(ret, "emit|add_request failed: %d!\n", ret);
+ ret = engine->emit_request(request);
+ WARN(ret, "(%s)->emit_request failed: %d!\n", engine->name, ret);
/* Sanity check that the reserved size was large enough. */
ret = ring->tail - request_start;
@@ -483,6 +480,7 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
reserved_tail, ret);
i915_gem_mark_busy(engine);
+ engine->submit_request(request);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index eccd34832fe6..32d0e1890950 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -585,7 +585,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
* The only error here arises if the doorbell hardware isn't functioning
* as expected, which really shouln't happen.
*/
-int i915_guc_submit(struct drm_i915_gem_request *rq)
+static void i915_guc_submit(struct drm_i915_gem_request *rq)
{
unsigned int engine_id = rq->engine->id;
struct intel_guc *guc = &rq->i915->guc;
@@ -602,8 +602,6 @@ int i915_guc_submit(struct drm_i915_gem_request *rq)
guc->submissions[engine_id] += 1;
guc->last_seqno[engine_id] = rq->fence.seqno;
-
- return b_ret;
}
/*
@@ -992,6 +990,7 @@ int i915_guc_submission_enable(struct drm_i915_private
*dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
struct i915_guc_client *client;
+ struct intel_engine_cs *engine;
/* client for execbuf submission */
client = guc_client_alloc(dev_priv,
@@ -1006,6 +1005,10 @@ int i915_guc_submission_enable(struct drm_i915_private
*dev_priv)
host2guc_sample_forcewake(guc, client);
guc_init_doorbell_hw(guc);
+ /* Take over from manual control of ELSP (execlists) */
+ for_each_engine(engine, dev_priv)
+ engine->submit_request = i915_guc_submit;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3e3e743740c0..623cf26cd784 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -160,7 +160,6 @@ extern int intel_guc_resume(struct drm_device *dev);
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
-int i915_guc_submit(struct drm_i915_gem_request *rq);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5e08b95813fe..51818a883f0c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -738,7 +738,7 @@ err_unpin:
}
/*
- * intel_logical_ring_advance_and_submit() - advance the tail and submit the
workload
+ * intel_logical_ring_advance() - advance the tail and prepare for submission
* @request: Request to advance the logical ringbuffer of.
*
* The tail is updated in our logical ringbuffer struct, not in the actual
context. What
@@ -747,7 +747,7 @@ err_unpin:
* point, the tail *inside* the context is updated and the ELSP written to.
*/
static int
-intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
+intel_logical_ring_advance(struct drm_i915_gem_request *request)
{
struct intel_ring *ring = request->ring;
struct in
[Intel-gfx] [PATCH 20/55] drm/i915: Convert engine->write_tail to operate on a request
If we rewrite the I915_WRITE_TAIL specialisation for the legacy
ringbuffer as submitting the request onto the ringbuffer, we can unify
the vfunc with both execlists and GuC in the next patch.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-22-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_request.c | 8 ++---
drivers/gpu/drm/i915/intel_lrc.c| 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
4 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 44cdca9a2194..8af514e42c30 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -466,15 +466,13 @@ void __i915_add_request(struct drm_i915_gem_request
*request,
*/
request->postfix = ring->tail;
- if (i915.enable_execlists) {
+ if (i915.enable_execlists)
ret = engine->emit_request(request);
- } else {
+ else
ret = engine->add_request(request);
-
- request->tail = ring->tail;
- }
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
+
/* Sanity check that the reserved size was large enough. */
ret = ring->tail - request_start;
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 80a28ebb5e06..5e08b95813fe 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -373,7 +373,7 @@ static void execlists_update_context(struct
drm_i915_gem_request *rq)
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
- reg_state[CTX_RING_TAIL+1] = rq->tail;
+ reg_state[CTX_RING_TAIL+1] = rq->tail % (rq->ring->size - 1);
/* True 32b PPGTT with dynamic page allocation: update PDP
* registers and point the unallocated PDPs to scratch page.
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b91dc6acb84a..211b57614764 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -58,14 +58,6 @@ void intel_ring_update_space(struct intel_ring *ring)
ring->tail, ring->size);
}
-static void __intel_engine_submit(struct intel_engine_cs *engine)
-{
- struct intel_ring *ring = engine->buffer;
-
- ring->tail &= ring->size - 1;
- engine->write_tail(engine, ring->tail);
-}
-
static int
gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
@@ -421,13 +413,6 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
return gen8_emit_pipe_control(req, flags, scratch_addr);
}
-static void ring_write_tail(struct intel_engine_cs *engine,
- u32 value)
-{
- struct drm_i915_private *dev_priv = engine->i915;
- I915_WRITE_TAIL(engine, value);
-}
-
u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -541,7 +526,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
I915_WRITE_CTL(engine, 0);
I915_WRITE_HEAD(engine, 0);
- engine->write_tail(engine, 0);
+ I915_WRITE_TAIL(engine, 0);
if (!IS_GEN2(dev_priv)) {
(void)I915_READ_CTL(engine);
@@ -1482,7 +1467,10 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, req->fence.seqno);
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_engine_submit(engine);
+ intel_ring_advance(ring);
+
+ req->tail = ring->tail;
+ engine->submit_request(req);
return 0;
}
@@ -1512,7 +1500,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(ring, MI_NOOP);
- __intel_engine_submit(engine);
+
+ req->tail = ring->tail;
+ engine->submit_request(req);
return 0;
}
@@ -1731,11 +1721,22 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, req->fence.seqno);
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_engine_submit(req->engine);
+ intel_ring_advance(ring);
+
+ req->tail = ring->tail;
+ req->engine->submit_request(req);
return 0;
}
+static void i9xx_submit_request(struct drm_i915_gem_request *request)
+{
+ struct drm_i915_private *dev_priv = request->i915;
+
+
[Intel-gfx] [PATCH 18/55] drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START
Both the ->dispatch_execbuffer and ->emit_bb_start callbacks do exactly
the same thing, add MI_BATCHBUFFER_START to the request's ringbuffer -
we need only one vfunc.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-20-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 ++--
drivers/gpu/drm/i915/i915_gem_render_state.c | 16 +-
drivers/gpu/drm/i915/intel_lrc.c | 15 ++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 12 +++
5 files changed, 50 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index eacd78fc93c4..29407787b219 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1326,9 +1326,9 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
if (exec_len == 0)
exec_len = params->batch_obj->base.size;
- ret = params->engine->dispatch_execbuffer(params->request,
- exec_start, exec_len,
- params->dispatch_flags);
+ ret = params->engine->emit_bb_start(params->request,
+ exec_start, exec_len,
+ params->dispatch_flags);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index b2be4676a5cf..2ba759f3ab6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -234,18 +234,18 @@ int i915_gem_render_state_init(struct
drm_i915_gem_request *req)
if (so.rodata == NULL)
return 0;
- ret = req->engine->dispatch_execbuffer(req, so.ggtt_offset,
-so.rodata->batch_items * 4,
-I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req, so.ggtt_offset,
+so.rodata->batch_items * 4,
+I915_DISPATCH_SECURE);
if (ret)
goto out;
if (so.aux_batch_size > 8) {
- ret = req->engine->dispatch_execbuffer(req,
-(so.ggtt_offset +
- so.aux_batch_offset),
-so.aux_batch_size,
-I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req,
+(so.ggtt_offset +
+ so.aux_batch_offset),
+so.aux_batch_size,
+I915_DISPATCH_SECURE);
if (ret)
goto out;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1e57f48250ce..80a28ebb5e06 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -859,7 +859,9 @@ int intel_execlists_submission(struct
i915_execbuffer_params *params,
exec_start = params->batch_obj_vm_offset +
args->batch_start_offset;
- ret = engine->emit_bb_start(params->request, exec_start,
params->dispatch_flags);
+ ret = engine->emit_bb_start(params->request,
+ exec_start, args->batch_len,
+ params->dispatch_flags);
if (ret)
return ret;
@@ -1543,7 +1545,8 @@ static int intel_logical_ring_emit_pdps(struct
drm_i915_gem_request *req)
}
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
- u64 offset, unsigned dispatch_flags)
+ u64 offset, u32 len,
+ unsigned int dispatch_flags)
{
struct intel_ring *ring = req->ring;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
@@ -1819,13 +1822,15 @@ static int intel_lr_context_render_state_init(struct
drm_i915_gem_request *req)
return 0;
ret = req->engine->emit_bb_start(req, so.ggtt_offset,
- I915_DISPATCH_SECURE);
+so.rodata->batch_items * 4,
+I915_DISPATCH_SECURE);
if (ret)
goto out;
ret = req->engine->emit_bb_start(req,
- (so.ggtt_offset + so.aux_batch_offset),
- I915_DISPA
[Intel-gfx] [PATCH 04/55] drm/i915: Only drop the batch-pool's object reference
The obj->batch_pool_link is only inspected when traversing the batch
pool list and when on the batch pool list the object is referenced. Thus
when freeing the batch pool list, we only need to unreference the object
and do not have to worry about the obj->batch_pool_link.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-5-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index 3507b2753fd3..825981b5aa40 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -68,15 +68,14 @@ void i915_gem_batch_pool_fini(struct i915_gem_batch_pool
*pool)
WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex));
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {
- while (!list_empty(&pool->cache_list[n])) {
- struct drm_i915_gem_object *obj =
- list_first_entry(&pool->cache_list[n],
-struct drm_i915_gem_object,
-batch_pool_link);
+ struct drm_i915_gem_object *obj, *next;
- list_del(&obj->batch_pool_link);
+ list_for_each_entry_safe(obj, next,
+&pool->cache_list[n],
+batch_pool_link)
i915_gem_object_put(obj);
- }
+
+ INIT_LIST_HEAD(&pool->cache_list[n]);
}
}
--
2.8.1
___
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[Intel-gfx] [PATCH 11/55] drm/i915: Rename request->ringbuf to request->ring
Now that we have disambuigated ring and engine, we can use the clearer
and more consistent name for the intel_ringbuffer pointer in the
request.
@@
struct drm_i915_gem_request *r;
@@
- r->ringbuf
+ r->ring
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-12-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c| 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 6 +-
drivers/gpu/drm/i915/i915_gem_request.c| 16 +++---
drivers/gpu/drm/i915/i915_gem_request.h| 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 20 +++
drivers/gpu/drm/i915/intel_display.c | 10 ++--
drivers/gpu/drm/i915/intel_lrc.c | 57 +-
drivers/gpu/drm/i915/intel_mocs.c | 36 ++--
drivers/gpu/drm/i915/intel_overlay.c | 8 +--
drivers/gpu/drm/i915/intel_ringbuffer.c| 92 +++---
11 files changed, 126 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index a0e24eb5e167..f7f4a8c40afe 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -552,7 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
struct drm_i915_private *dev_priv = req->i915;
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
@@ -655,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32
hw_flags)
static int remap_l3(struct drm_i915_gem_request *req, int slice)
{
u32 *remap_info = req->i915->l3_parity.remap_info[slice];
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int i, ret;
if (!remap_info)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2f9f0daa1bc2..42389de4752a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1173,7 +1173,7 @@ i915_gem_execbuffer_retire_commands(struct
i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret, i;
if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
@@ -1303,7 +1303,7 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
if (params->engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
- struct intel_ringbuffer *ring = params->request->ringbuf;
+ struct intel_ringbuffer *ring = params->request->ring;
ret = intel_ring_begin(params->request, 4);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b38a5311f996..46cae2a92bda 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -669,7 +669,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1661,7 +1661,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
@@ -1688,7 +1688,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 49396b895a36..d2133c41be13 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -170,7 +170,7 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
* Note this requires that we are always called in request
* completion order.
*/
- request->ringbuf->last_retired_head = request->postfix;
+ request->ring->last_retired_head = request->postfix;
i915_gem_request_r
[Intel-gfx] [PATCH 10/55] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
Both perform the same actions with more or less indirection, so just
unify the code.
v2: Add back a few intel_engine_cs locals
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-11-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_context.c| 47 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 53 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c| 48 ++--
drivers/gpu/drm/i915/intel_display.c | 80 +++---
drivers/gpu/drm/i915/intel_lrc.c | 183 +++---
drivers/gpu/drm/i915/intel_lrc.h | 26 --
drivers/gpu/drm/i915/intel_mocs.c | 38 ++-
drivers/gpu/drm/i915/intel_overlay.c | 50 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c| 382 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 25 +-
10 files changed, 450 insertions(+), 482 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index bd13d084e19c..a0e24eb5e167 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -552,6 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
struct drm_i915_private *dev_priv = req->i915;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
@@ -589,64 +590,64 @@ mi_set_context(struct drm_i915_gem_request *req, u32
hw_flags)
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
if (INTEL_GEN(dev_priv) >= 7) {
- intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(num_rings));
for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
- intel_ring_emit_reg(engine,
+ intel_ring_emit_reg(ring,
RING_PSMI_CTL(signaller->mmio_base));
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
}
}
}
- intel_ring_emit(engine, MI_NOOP);
- intel_ring_emit(engine, MI_SET_CONTEXT);
- intel_ring_emit(engine,
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_SET_CONTEXT);
+ intel_ring_emit(ring,
i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
*/
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
if (INTEL_GEN(dev_priv) >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(num_rings));
for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
last_reg = RING_PSMI_CTL(signaller->mmio_base);
- intel_ring_emit_reg(engine, last_reg);
- intel_ring_emit(engine,
+ intel_ring_emit_reg(ring, last_reg);
+ intel_ring_emit(ring,
_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
}
/* Insert a delay before the next switch! */
- intel_ring_emit(engine,
+ intel_ring_emit(ring,
MI_STORE_REGISTER_MEM |
MI_SRM_LRM_GLOBAL_GTT);
- intel_ring_emit_reg(engine, last_reg);
- intel_ring_emit(engine, engine->scratch.gtt_offset);
- intel_ring_emit(engine, MI_NOOP);
+ intel_ring_emit_reg(ring, last_reg);
+ intel_ring_emit(ring, engine->scratch.gtt_offset);
+ intel_ring_
[Intel-gfx] [PATCH 08/55] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
A few places we use ring when referring to the struct intel_engine_cs. An
anachronism we are pruning out.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-9-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e155e8dd28ed..7bfce1d5c61b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct
drm_i915_gem_object *o
static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
+i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
static bool cpu_cache_is_coherent(struct drm_device *dev,
enum i915_cache_level level)
@@ -1385,10 +1385,10 @@ static void
i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *req)
{
- int ring = req->engine->id;
+ int idx = req->engine->id;
- if (obj->last_read_req[ring] == req)
- i915_gem_object_retire__read(obj, ring);
+ if (obj->last_read_req[idx] == req)
+ i915_gem_object_retire__read(obj, idx);
else if (obj->last_write_req == req)
i915_gem_object_retire__write(obj);
@@ -2381,20 +2381,20 @@ i915_gem_object_retire__write(struct
drm_i915_gem_object *obj)
}
static void
-i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
+i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
{
struct i915_vma *vma;
- GEM_BUG_ON(obj->last_read_req[ring] == NULL);
- GEM_BUG_ON(!(obj->active & (1 << ring)));
+ GEM_BUG_ON(obj->last_read_req[idx] == NULL);
+ GEM_BUG_ON(!(obj->active & (1 << idx)));
- list_del_init(&obj->engine_list[ring]);
- i915_gem_request_assign(&obj->last_read_req[ring], NULL);
+ list_del_init(&obj->engine_list[idx]);
+ i915_gem_request_assign(&obj->last_read_req[idx], NULL);
- if (obj->last_write_req && obj->last_write_req->engine->id == ring)
+ if (obj->last_write_req && obj->last_write_req->engine->id == idx)
i915_gem_object_retire__write(obj);
- obj->active &= ~(1 << ring);
+ obj->active &= ~(1 << idx);
if (obj->active)
return;
@@ -4599,7 +4599,7 @@ int i915_gem_init(struct drm_device *dev)
ret = i915_gem_init_hw(dev);
if (ret == -EIO) {
- /* Allow ring initialisation to fail by marking the GPU as
+ /* Allow engine initialisation to fail by marking the GPU as
* wedged. But we only want to do this where the GPU is angry,
* for all other failure, such as an allocation failure, bail.
*/
--
2.8.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/55] drm/i915: Update a couple of hangcheck comments to talk about engines
We still have lots of comments that refer to the old ring when we mean
struct intel_engine_cs and its hardware correspondence. This patch fixes
an instance inside hangcheck to talk about engines.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-10-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7104dc1463eb..f5bf4f913a91 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3140,13 +3140,13 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
}
} else {
/* We always increment the hangcheck score
-* if the ring is busy and still processing
+* if the engine is busy and still processing
* the same request, so that no single request
* can run indefinitely (such as a chain of
* batches). The only time we do not increment
* the hangcheck score on this ring, if this
-* ring is in a legitimate wait for another
-* ring. In that case the waiting ring is a
+* engine is in a legitimate wait for another
+* engine. In that case the waiting engine is a
* victim and we want to be sure we catch the
* right culprit. Then every time we do kick
* the ring, add a small increment to the
--
2.8.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/55] drm/i915: Avoid using intel_engine_cs *ring for GPU error capture
Inside the error capture itself, we refer to not only the hardware
engine, its ringbuffer but also the capture state. Finding clear names
for each whilst avoiding mixing ring/intel_engine_cs is tricky. As a
compromise we keep using ering for the error capture.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-8-git-send-email-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 255 +-
2 files changed, 134 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97f827979a66..11c0204aac23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,7 +512,7 @@ struct drm_i915_error_state {
struct intel_display_error_state *display;
struct drm_i915_error_object *semaphore_obj;
- struct drm_i915_error_ring {
+ struct drm_i915_error_engine {
bool valid;
/* Software tracked state */
bool waiting;
@@ -578,7 +578,7 @@ struct drm_i915_error_state {
pid_t pid;
char comm[TASK_COMM_LEN];
- } ring[I915_NUM_ENGINES];
+ } engine[I915_NUM_ENGINES];
struct drm_i915_error_buffer {
u32 size;
@@ -593,7 +593,7 @@ struct drm_i915_error_state {
u32 dirty:1;
u32 purgeable:1;
u32 userptr:1;
- s32 ring:4;
+ s32 engine:4;
u32 cache_level:3;
} **active_bo, **pinned_bo;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4d39c7284605..0ec917fa115d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -30,9 +30,9 @@
#include
#include "i915_drv.h"
-static const char *ring_str(int ring)
+static const char *engine_str(int engine)
{
- switch (ring) {
+ switch (engine) {
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
@@ -207,8 +207,8 @@ static void print_error_buffers(struct
drm_i915_error_state_buf *m,
err_puts(m, dirty_flag(err->dirty));
err_puts(m, purgeable_flag(err->purgeable));
err_puts(m, err->userptr ? " userptr" : "");
- err_puts(m, err->ring != -1 ? " " : "");
- err_puts(m, ring_str(err->ring));
+ err_puts(m, err->engine != -1 ? " " : "");
+ err_puts(m, engine_str(err->engine));
err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
if (err->name)
@@ -240,69 +240,71 @@ static const char *hangcheck_action_to_str(enum
intel_ring_hangcheck_action a)
}
static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
- struct drm_device *dev,
- struct drm_i915_error_state *error,
- int ring_idx)
+ struct drm_device *dev,
+ struct drm_i915_error_state *error,
+ int engine_idx)
{
- struct drm_i915_error_ring *ring = &error->ring[ring_idx];
+ struct drm_i915_error_engine *ering = &error->engine[engine_idx];
- if (!ring->valid)
+ if (!ering->valid)
return;
- err_printf(m, "%s command stream:\n", ring_str(ring_idx));
- err_printf(m, " START: 0x%08x\n", ring->start);
- err_printf(m, " HEAD: 0x%08x\n", ring->head);
- err_printf(m, " TAIL: 0x%08x\n", ring->tail);
- err_printf(m, " CTL: 0x%08x\n", ring->ctl);
- err_printf(m, " HWS: 0x%08x\n", ring->hws);
- err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32),
(u32)ring->acthd);
- err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
- err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
- err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
+ err_printf(m, "%s command stream:\n", engine_str(engine_idx));
+ err_printf(m, " START: 0x%08x\n", ering->start);
+ err_printf(m, " HEAD: 0x%08x\n", ering->head);
+ err_printf(m, " TAIL: 0x%08x\n", ering->tail);
+ err_printf(m, " CTL: 0x%08x\n", ering->ctl);
+ err_printf(m, " HWS: 0x%08x\n", ering->hws);
+ err_printf(m, " ACTHD: 0x%08x %08x\n",
+ (u32)(ering->acthd>>32), (u32)ering->acthd);
+ err_printf(m, " IPEIR: 0x%08x\n", ering->ipeir);
+ err_printf(m, " IPEHR: 0x%08x\n", ering->ipehr);
+ err_printf(m, " INSTDONE: 0x%08x\n", ering->instdone);
if (INTEL_INFO(dev)->gen >= 4) {
- err_printf(m, " BBADDR: 0x%08x %08x\n",
(u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
- err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
-
[Intel-gfx] [PATCH 05/55] drm/i915/cmdparser: Remove stray intel_engine_cs *ring
When we refer to intel_engine_cs, we want to use engine so as not to
confuse ourselves about ringbuffers.
v2: Rename all the functions as well, as well as a few more stray comments.
v3: Split the really long error message strings
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-6-git-send-email-ch...@chris-wilson.co.uk
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 74 --
drivers/gpu/drm/i915/i915_drv.h| 23 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h| 10 ++--
7 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index b0fd6a7b0603..1db829c8b912 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -62,23 +62,23 @@
* The parser always rejects such commands.
*
* The majority of the problematic commands fall in the MI_* range, with only a
- * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
+ * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
*
* Implementation:
- * Each ring maintains tables of commands and registers which the parser uses
in
- * scanning batch buffers submitted to that ring.
+ * Each engine maintains tables of commands and registers which the parser
+ * uses in scanning batch buffers submitted to that engine.
*
* Since the set of commands that the parser must check for is significantly
* smaller than the number of commands supported, the parser tables contain
only
* those commands required by the parser. This generally works because command
* opcode ranges have standard command length encodings. So for commands that
* the parser does not need to check, it can easily skip them. This is
- * implemented via a per-ring length decoding vfunc.
+ * implemented via a per-engine length decoding vfunc.
*
* Unfortunately, there are a number of commands that do not follow the
standard
* length encoding for their opcode range, primarily amongst the MI_* commands.
* To handle this, the parser provides a way to define explicit "skip" entries
- * in the per-ring command tables.
+ * in the per-engine command tables.
*
* Other command table entries map fairly directly to high level categories
* mentioned above: rejected, master-only, register whitelist. The parser
@@ -603,7 +603,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
return 0;
}
-static bool validate_cmds_sorted(struct intel_engine_cs *engine,
+static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_cmd_table *cmd_tables,
int cmd_table_count)
{
@@ -624,8 +624,10 @@ static bool validate_cmds_sorted(struct intel_engine_cs
*engine,
u32 curr = desc->cmd.value & desc->cmd.mask;
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d
table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
- engine->id, i, j, curr, previous);
+ DRM_ERROR("CMD: %s [%d] command table not
sorted: "
+ "table=%d entry=%d cmd=0x%08X
prev=0x%08X\n",
+ engine->name, engine->id,
+ i, j, curr, previous);
ret = false;
}
@@ -636,7 +638,7 @@ static bool validate_cmds_sorted(struct intel_engine_cs
*engine,
return ret;
}
-static bool check_sorted(int ring_id,
+static bool check_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_reg_descriptor *reg_table,
int reg_count)
{
@@ -648,8 +650,10 @@ static bool check_sorted(int ring_id,
u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d entry=%d
reg=0x%08X prev=0x%08X\n",
- ring_id, i, curr, previous);
+ DRM_ERROR("CMD: %s [%d] register table not sorted: "
+ "entry=%d reg=0x%08X prev=0x%08X\n",
+ engine->name, engine->id,
+ i, curr, previous);
ret = false;
}
@@ -666,7 +670,7 @@ static bool validate_regs_sorted(struct intel_engine_cs
*engine)
for (i = 0; i < engine->reg_table_count; i++) {
table = &e
[Intel-gfx] [PATCH 01/55] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling()
Since intel_engine_enable_signaling() is now only called via
fence_enable_sw_signaling(), we can rely on it to provide serialisation
and run-once for us and so make ourselves slightly simpler.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-2-git-send-email-ch...@chris-wilson.co.uk
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index d893ccdd62ac..90867446f1a5 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -480,19 +480,15 @@ void intel_engine_enable_signaling(struct
drm_i915_gem_request *request)
struct rb_node *parent, **p;
bool first, wakeup;
- if (unlikely(READ_ONCE(request->signaling.wait.tsk)))
- return;
-
- spin_lock(&b->lock);
- if (unlikely(request->signaling.wait.tsk)) {
- wakeup = false;
- goto unlock;
- }
+ /* locked by fence_enable_sw_signaling() */
+ assert_spin_locked(&request->lock);
request->signaling.wait.tsk = b->signaler;
request->signaling.wait.seqno = request->fence.seqno;
i915_gem_request_get(request);
+ spin_lock(&b->lock);
+
/* First add ourselves into the list of waiters, but register our
* bottom-half as the signaller thread. As per usual, only the oldest
* waiter (not just signaller) is tasked as the bottom-half waking
@@ -525,7 +521,6 @@ void intel_engine_enable_signaling(struct
drm_i915_gem_request *request)
if (first)
smp_store_mb(b->first_signal, request);
-unlock:
spin_unlock(&b->lock);
if (wakeup)
--
2.8.1
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[Intel-gfx] [PATCH 02/55] drm/i915: Prefer list_first_entry_or_null
list_first_entry_or_null() can generate better code than using
if (!list_empty()) {ptr = list_first_entry()) ..., so put it to use.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-3-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +---
drivers/gpu/drm/i915/i915_gem_request.c | 8 +++-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 9 +
3 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 30da543e1bdf..38e7d992a20d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2736,13 +2736,11 @@ static void i915_gtt_color_adjust(struct drm_mm_node
*node,
if (node->color != color)
*start += 4096;
- if (!list_empty(&node->node_list)) {
- node = list_entry(node->node_list.next,
- struct drm_mm_node,
- node_list);
- if (node->allocated && node->color != color)
- *end -= 4096;
- }
+ node = list_first_entry_or_null(&node->node_list,
+ struct drm_mm_node,
+ node_list);
+ if (node && node->allocated && node->color != color)
+ *end -= 4096;
}
static int i915_gem_setup_global_gtt(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 60a3a343b3a8..49396b895a36 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -317,12 +317,10 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
return ret;
/* Move the oldest request to the slab-cache (if not in use!) */
- if (!list_empty(&engine->request_list)) {
- req = list_first_entry(&engine->request_list,
+ req = list_first_entry_or_null(&engine->request_list,
typeof(*req), list);
- if (i915_gem_request_completed(req))
- i915_gem_request_retire(req);
- }
+ if (req && i915_gem_request_completed(req))
+ i915_gem_request_retire(req);
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (!req)
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index afaa2597e35e..5d4772c146b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -163,17 +163,18 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
*/
for (phase = phases; phase->list; phase++) {
struct list_head still_in_list;
+ struct drm_i915_gem_object *obj;
if ((flags & phase->bit) == 0)
continue;
INIT_LIST_HEAD(&still_in_list);
- while (count < target && !list_empty(phase->list)) {
- struct drm_i915_gem_object *obj;
+ while (count < target &&
+ (obj = list_first_entry_or_null(phase->list,
+ typeof(*obj),
+ global_list))) {
struct i915_vma *vma, *v;
- obj = list_first_entry(phase->list,
- typeof(*obj), global_list);
list_move_tail(&obj->global_list, &still_in_list);
if (flags & I915_SHRINK_PURGEABLE &&
--
2.8.1
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[Intel-gfx] [PATCH 03/55] drm/i915: Only clear the client pointer when tearing down the file
Upon release of the file (i.e. the user calls close(fd)), we decouple
all objects from the client list so that we don't chase the dangling
file_priv. As we always inspect file_priv first, we only need to nullify
that pointer and can safely ignore the list_head.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-4-git-send-email-ch...@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c8436639b3ed..3730aecc1eae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4745,21 +4745,15 @@ int i915_gem_freeze_late(struct drm_i915_private
*dev_priv)
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_i915_gem_request *request;
/* Clean up our request list when the client is going away, so that
* later retire_requests won't dereference our soon-to-be-gone
* file_priv.
*/
spin_lock(&file_priv->mm.lock);
- while (!list_empty(&file_priv->mm.request_list)) {
- struct drm_i915_gem_request *request;
-
- request = list_first_entry(&file_priv->mm.request_list,
- struct drm_i915_gem_request,
- client_list);
- list_del(&request->client_list);
+ list_for_each_entry(request, &file_priv->mm.request_list, client_list)
request->file_priv = NULL;
- }
spin_unlock(&file_priv->mm.lock);
if (!list_empty(&file_priv->rps.link)) {
--
2.8.1
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[Intel-gfx] Fix the vma leak
Long, long ago vma were found to exist after the parent ppgtt had ceased. They still do. This series fixes the leak by introducing vma activity tracking, with this a vma for one client does not stall another client and we can track when each client's vm are idle independently. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915: avoid "may be used uninitialised" warnings
== Series Details == Series: drm/i915: avoid "may be used uninitialised" warnings URL : https://patchwork.freedesktop.org/series/10243/ State : warning == Summary == Series 10243v1 drm/i915: avoid "may be used uninitialised" warnings http://patchwork.freedesktop.org/api/1.0/series/10243/revisions/1/mbox Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-skl-i5-6260u) Test gem_sync: Subgroup basic-store-each: pass -> SKIP (ro-bdw-i7-5600u) pass -> SKIP (ro-bdw-i5-5250u) fi-hsw-i7-4770k total:235 pass:215 dwarn:0 dfail:0 fail:0 skip:20 fi-kbl-qkkr total:235 pass:179 dwarn:28 dfail:1 fail:0 skip:27 fi-skl-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12 fi-skl-i7-6700k total:235 pass:209 dwarn:0 dfail:0 fail:0 skip:26 fi-snb-i7-2600 total:235 pass:195 dwarn:0 dfail:0 fail:0 skip:40 ro-bdw-i5-5250u total:235 pass:217 dwarn:4 dfail:0 fail:0 skip:14 ro-bdw-i7-5557U total:235 pass:218 dwarn:3 dfail:0 fail:0 skip:14 ro-bdw-i7-5600u total:235 pass:203 dwarn:0 dfail:0 fail:0 skip:32 ro-bsw-n3050 total:235 pass:193 dwarn:0 dfail:0 fail:0 skip:42 ro-byt-n2820 total:235 pass:196 dwarn:0 dfail:0 fail:1 skip:38 ro-hsw-i3-4010u total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24 ro-hsw-i7-4770r total:235 pass:211 dwarn:0 dfail:0 fail:0 skip:24 ro-ilk-i7-620lm total:235 pass:171 dwarn:0 dfail:0 fail:1 skip:63 ro-ilk1-i5-650 total:230 pass:171 dwarn:0 dfail:0 fail:1 skip:58 ro-ivb-i7-3770 total:235 pass:202 dwarn:0 dfail:0 fail:0 skip:33 ro-skl3-i5-6260u total:235 pass:223 dwarn:0 dfail:0 fail:0 skip:12 ro-snb-i7-2620M total:235 pass:193 dwarn:0 dfail:0 fail:1 skip:41 Results at /archive/results/CI_IGT_test/RO_Patchwork_1599/ 5c9e3d9 drm-intel-nightly: 2016y-07m-25d-06h-32m-37s UTC integration manifest 9b271c1 drm/i915: avoid "may be used uninitialised" warnings ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: avoid "may be used uninitialised" warnings
On Mon, Jul 25, 2016 at 05:29:45PM +0100, Dave Gordon wrote: > gcc is getting false positives in its detection of uninitialised values. > Specifically it thinks 'gtt_entry' can be used in a WARN_ON() macro > without previously being assigned (the assigment is inside a conditional > loop), bu actually the WARN_ON() can only be reached if the assignment > has also been executed at least once. gcc 4.7 through 6.1 doesn't generate the warning for me, and the kbuilder can happily ignore it. At any rate the markup is uninitialised_var(). -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: avoid "may be used uninitialised" warnings
gcc is getting false positives in its detection of uninitialised values.
Specifically it thinks 'gtt_entry' can be used in a WARN_ON() macro
without previously being assigned (the assigment is inside a conditional
loop), bu actually the WARN_ON() can only be reached if the assignment
has also been executed at least once.
To avoid the annoying warning, though, this patch reorganises the code a
little and adds an explicit initialisation of the suspect variable.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 30da543..90e1cf3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2368,7 +2368,7 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
struct sgt_iter sgt_iter;
gen8_pte_t __iomem *gtt_entries;
- gen8_pte_t gtt_entry;
+ gen8_pte_t gtt_entry = I915_NULL_PTE;
dma_addr_t addr;
int rpm_atomic_seq;
int i = 0;
@@ -2389,8 +2389,10 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
* of NUMA access patterns. Therefore, even with the way we assume
* hardware should work, we must keep this posting read for paranoia.
*/
- if (i != 0)
- WARN_ON(readq(>t_entries[i-1]) != gtt_entry);
+ if (i != 0) {
+ gen8_pte_t last_gtt_entry = readq(>t_entries[i-1]);
+ WARN_ON(last_gtt_entry != gtt_entry);
+ }
/* This next bit makes the above posting read even more important. We
* want to flush the TLBs only after we're certain all the PTE updates
@@ -2465,7 +2467,7 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
struct sgt_iter sgt_iter;
gen6_pte_t __iomem *gtt_entries;
- gen6_pte_t gtt_entry;
+ gen6_pte_t gtt_entry = I915_NULL_PTE;
dma_addr_t addr;
int rpm_atomic_seq;
int i = 0;
@@ -2479,14 +2481,17 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
iowrite32(gtt_entry, >t_entries[i++]);
}
- /* XXX: This serves as a posting read to make sure that the PTE has
+ /*
+* XXX: This serves as a posting read to make sure that the PTE has
* actually been updated. There is some concern that even though
* registers and PTEs are within the same BAR that they are potentially
* of NUMA access patterns. Therefore, even with the way we assume
* hardware should work, we must keep this posting read for paranoia.
*/
- if (i != 0)
- WARN_ON(readl(>t_entries[i-1]) != gtt_entry);
+ if (i != 0) {
+ gen8_pte_t last_gtt_entry = readl(>t_entries[i-1]);
+ WARN_ON(last_gtt_entry != gtt_entry);
+ }
/* This next bit makes the above posting read even more important. We
* want to flush the TLBs only after we're certain all the PTE updates
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c4a6579..e088210 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -54,6 +54,7 @@ typedef uint64_t gen8_ppgtt_pml4e_t;
#define GEN6_PTE_UNCACHED (1 << 1)
#define GEN6_PTE_VALID (1 << 0)
+#defineI915_NULL_PTE 0
#define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
#define I915_PDES 512
--
1.9.1
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Re: [Intel-gfx] [PATCH v6 05/10] drm: Read DP branch device id
On Wed, Jul 06, 2016 at 02:04:49PM +0300, Mika Kahola wrote:
> Read DisplayPort branch device id string.
Reviewed-by: Jim Bride
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/drm_dp_helper.c | 12
> include/drm/drm_dp_helper.h | 2 ++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 95d624a..4003464 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -513,6 +513,18 @@ int drm_dp_downstream_max_bpc(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> }
> EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
>
> +/**
> + * drm_dp_downstream_id() - identify branch device
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns branch device id on success or NULL on failure
> + */
> +int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
> +{
> + return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_id);
> +
> /*
> * I2C-over-AUX implementation
> */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 47ae8ed..8264d54 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -445,6 +445,7 @@
> #define DP_SOURCE_OUI0x300
> #define DP_SINK_OUI 0x400
> #define DP_BRANCH_OUI0x500
> +#define DP_BRANCH_ID0x503
>
> #define DP_SET_POWER0x600
> # define DP_SET_POWER_D00x1
> @@ -810,6 +811,7 @@ int drm_dp_downstream_max_clock(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> const u8 port_cap[4]);
> int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> const u8 port_cap[4]);
> +int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
>
> void drm_dp_aux_init(struct drm_dp_aux *aux);
> int drm_dp_aux_register(struct drm_dp_aux *aux);
> --
> 1.9.1
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Re: [Intel-gfx] [PATCH v6 07/10] drm: Read DP branch device SW revision
On Wed, Jul 06, 2016 at 02:04:51PM +0300, Mika Kahola wrote:
> SW revision is mandatory field for DisplayPort branch
> devices. This is defined in DPCD register field 0x50A.
Reviewed-by: Jim Bride
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/drm_dp_helper.c | 21 +
> include/drm/drm_dp_helper.h | 2 ++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index cfd75df..19e06a0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -535,6 +535,27 @@ struct drm_dp_revision drm_dp_downstream_hw_rev(struct
> drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_dp_downstream_hw_rev);
>
> /**
> + * drm_dp_downstream_sw_rev() - read DP branch device SW revision
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns SW revision on success or negative error code on failure
> + */
> +struct drm_dp_revision drm_dp_downstream_sw_rev(struct drm_dp_aux *aux)
> +{
> + uint8_t tmp[2];
> + struct drm_dp_revision rev = { .major = -EINVAL, .minor = -EINVAL };
> +
> + if (drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, tmp, 2) != 2)
> + return rev;
> +
> + rev.major = tmp[0];
> + rev.minor = tmp[1];
> +
> + return rev;
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_sw_rev);
> +
> +/**
> * drm_dp_downstream_id() - identify branch device
> * @aux: DisplayPort AUX channel
> *
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 5f577e4..764a309 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -447,6 +447,7 @@
> #define DP_BRANCH_OUI0x500
> #define DP_BRANCH_ID0x503
> #define DP_BRANCH_HW_REV0x509
> +#define DP_BRANCH_SW_REV0x50A
>
> #define DP_SET_POWER0x600
> # define DP_SET_POWER_D00x1
> @@ -819,6 +820,7 @@ int drm_dp_downstream_max_bpc(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> const u8 port_cap[4]);
> int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
> struct drm_dp_revision drm_dp_downstream_hw_rev(struct drm_dp_aux *aux);
> +struct drm_dp_revision drm_dp_downstream_sw_rev(struct drm_dp_aux *aux);
>
> void drm_dp_aux_init(struct drm_dp_aux *aux);
> int drm_dp_aux_register(struct drm_dp_aux *aux);
> --
> 1.9.1
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Re: [Intel-gfx] [PATCH v6 04/10] drm: Helper to read max bits per component
On Wed, Jul 06, 2016 at 02:04:48PM +0300, Mika Kahola wrote:
> Helper routine to read out maximum supported bits per
> component for DisplayPort legay converters.
>
> v2: Return early if detailed port cap info is not available.
> Replace if-else ladder with switch-case (Ville)
Reviewed-by: Jim Bride
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/drm_dp_helper.c | 42
> +
> include/drm/drm_dp_helper.h | 2 ++
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 0d4117c..95d624a 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -471,6 +471,48 @@ int drm_dp_downstream_max_clock(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> }
> EXPORT_SYMBOL(drm_dp_downstream_max_clock);
>
> +/**
> + * drm_dp_downstream_max_bpc() - extract branch device max
> + * bits per component
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Returns max bpc on success or 0 if max bpc not defined
> + */
> +int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> + const u8 port_cap[4])
> +{
> + int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
> + bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> + DP_DETAILED_CAP_INFO_AVAILABLE;
> + int bpc;
> +
> + if (!detailed_cap_info)
> + return 0;
> +
> + switch (type) {
> + case DP_DS_PORT_TYPE_VGA:
> + case DP_DS_PORT_TYPE_DVI:
> + case DP_DS_PORT_TYPE_HDMI:
> + case DP_DS_PORT_TYPE_DP_DUALMODE:
> + bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
> +
> + switch (bpc) {
> + case DP_DS_8BPC:
> + return 8;
> + case DP_DS_10BPC:
> + return 10;
> + case DP_DS_12BPC:
> + return 12;
> + case DP_DS_16BPC:
> + return 16;
> + }
> + default:
> + return 0;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
> +
> /*
> * I2C-over-AUX implementation
> */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index de8e9ae..47ae8ed 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -808,6 +808,8 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct
> drm_dp_link *link);
> int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
> int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> const u8 port_cap[4]);
> +int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> + const u8 port_cap[4]);
>
> void drm_dp_aux_init(struct drm_dp_aux *aux);
> int drm_dp_aux_register(struct drm_dp_aux *aux);
> --
> 1.9.1
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Re: [Intel-gfx] [PATCH v6 03/10] drm: Helper to read max clock rate
On Wed, Jul 06, 2016 at 02:04:47PM +0300, Mika Kahola wrote:
> Helper routine to read out maximum supported pixel rate
> for DisplayPort legay VGA converter or TMDS clock rate
> for other digital legacy converters. The helper returns
> clock rate in kHz.
>
> v2: Return early if detailed port cap info is not available.
> Replace if-else ladder with switch-case (Ville)
Reviewed-by: Jim Bride
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/drm_dp_helper.c | 33 +
> include/drm/drm_dp_helper.h | 2 ++
> 2 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 091053e..0d4117c 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -438,6 +438,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct
> drm_dp_link *link)
> }
> EXPORT_SYMBOL(drm_dp_link_configure);
>
> +/**
> + * drm_dp_downstream_max_clock() - extract branch device max
> + * pixel rate for legacy VGA
> + * converter or max TMDS clock
> + * rate for others
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Returns max clock in kHz on success or 0 if max clock not defined
> + */
> +int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> + const u8 port_cap[4])
> +{
> + int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
> + bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> + DP_DETAILED_CAP_INFO_AVAILABLE;
> +
> + if (!detailed_cap_info)
> + return 0;
> +
> + switch (type) {
> + case DP_DS_PORT_TYPE_VGA:
> + return port_cap[1] * 8 * 1000;
> + case DP_DS_PORT_TYPE_DVI:
> + case DP_DS_PORT_TYPE_HDMI:
> + case DP_DS_PORT_TYPE_DP_DUALMODE:
> + return port_cap[1] * 2500;
> + default:
> + return 0;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_max_clock);
> +
> /*
> * I2C-over-AUX implementation
> */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 336d742..de8e9ae 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -806,6 +806,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct
> drm_dp_link *link);
> int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
> int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
> int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
> +int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> + const u8 port_cap[4]);
>
> void drm_dp_aux_init(struct drm_dp_aux *aux);
> int drm_dp_aux_register(struct drm_dp_aux *aux);
> --
> 1.9.1
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Re: [Intel-gfx] [PATCH v6 02/10] drm: Drop VGA from bpc definitions
On Wed, Jul 06, 2016 at 02:04:46PM +0300, Mika Kahola wrote: > Drop "VGA" from bits per component definitions as these > are also used by other standards such as DVI, HDMI, > DP++. Reviewed-by: Jim Bride > > Signed-off-by: Mika Kahola > --- > include/drm/drm_dp_helper.h | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 6e8b92e..336d742 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -216,11 +216,11 @@ > # define DP_DS_PORT_HPD (1 << 3) > /* offset 1 for VGA is maximum megapixels per second / 8 */ > /* offset 2 */ > -# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) > -# define DP_DS_VGA_8BPC 0 > -# define DP_DS_VGA_10BPC 1 > -# define DP_DS_VGA_12BPC 2 > -# define DP_DS_VGA_16BPC 3 > +# define DP_DS_MAX_BPC_MASK (3 << 0) > +# define DP_DS_8BPC 0 > +# define DP_DS_10BPC 1 > +# define DP_DS_12BPC 2 > +# define DP_DS_16BPC 3 > > /* link configuration */ > #define DP_LINK_BW_SET 0x100 > -- > 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 01/10] drm: Add missing DP downstream port types
On Wed, Jul 06, 2016 at 02:04:45PM +0300, Mika Kahola wrote: > Add missing DisplayPort downstream port types. The introduced > new port types are DP++ and Wireless. Looks good relative to the DP spec. Reviewed-by: Jim Bride > > Signed-off-by: Mika Kahola > --- > include/drm/drm_dp_helper.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 4d85cf2..6e8b92e 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -211,6 +211,8 @@ > # define DP_DS_PORT_TYPE_DVI 2 > # define DP_DS_PORT_TYPE_HDMI3 > # define DP_DS_PORT_TYPE_NON_EDID4 > +# define DP_DS_PORT_TYPE_DP_DUALMODE5 > +# define DP_DS_PORT_TYPE_WIRELESS 6 > # define DP_DS_PORT_HPD (1 << 3) > /* offset 1 for VGA is maximum megapixels per second / 8 */ > /* offset 2 */ > -- > 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/vlv: Fix off-by-1 error in calculating num_levels.
On Mon, Jul 25, 2016 at 02:46:01PM +0200, Maarten Lankhorst wrote:
> Op 25-07-16 om 13:51 schreef Ville Syrjälä:
> > On Mon, Jul 25, 2016 at 01:32:45PM +0200, Maarten Lankhorst wrote:
> >> Hey,
> >>
> >> Op 19-07-16 om 18:21 schreef Ville Syrjälä:
> >>> On Tue, Jul 19, 2016 at 04:50:49PM +0100, Chris Wilson wrote:
> On Tue, Jul 19, 2016 at 06:25:42PM +0300, Ville Syrjälä wrote:
> > On Tue, Jul 19, 2016 at 05:14:23PM +0200, Maarten Lankhorst wrote:
> >> num_levels should be level+1, not level, else num_levels - 1 becomes
> >> negative. This resulted in bogus watermarks being written to the first
> >> 255 levels like below:
> >>
> >> [drm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0,
> >> sprite1=0, SR: plane=0, cursor=0 level=255 cxsr=0
> >> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit
> >> DDR DVFS request
> >> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C
> >> FIFO underrun
> >> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit
> >> DDR DVFS request
> >>
> >> Testcase: kms_atomic_transition
> >> Fixes: 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another
> >> watermark rewrite")
> >> Cc: sta...@vger.kernel.org
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> Urgent fix for watermark support. This is definitely a pre-requisite
> >> for this series.
> >> With this I've noticed that patch "[RFC 3/8] drm/i915/vlv: Move
> >> fifo_size from
> >> intel_plane_wm_parameters to vlv_wm_state" introduces a regression
> >> with invalid FIFO split.
> >>
> >> I need to find out what's going wrong in that patch before this series
> >> can be applied.
> >>
> >> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> b/drivers/gpu/drm/i915/intel_pm.c
> >> index 376c60b98515..8defdcc54529 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -1148,7 +1148,7 @@ static void vlv_compute_wm(struct intel_crtc
> >> *crtc)
> >>}
> >>}
> >>
> >> - wm_state->num_levels = level;
> >> + wm_state->num_levels = level + 1;
> > Nope. The loop above breaks when the current level is bad, hence level-1
> > is actually the higher usable level.
> Without knowing the limits of plane->wm.fifo_size, it looks like it can
> break on level == 0 though.
> >>> Hmm. That shouldn't be possible. So looks like a bug snuck in.
> >>>
> Might as well set that hack to paranoid levels:
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 630b116988f6..e8c2874b8629 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1124,11 +1124,13 @@ static void vlv_compute_wm(struct intel_crtc
> *crtc)
> /* normal watermarks */
> for (level = 0; level < wm_state->num_levels; level++) {
> int wm = vlv_compute_wm_level(plane, crtc,
> state, level);
> - int max_wm = plane->base.type ==
> DRM_PLANE_TYPE_CURSOR ? 63 : 511;
> -
> /* hack */
> - if (WARN_ON(level == 0 && wm > max_wm))
> - wm = max_wm;
> >>> Actually this should just be
> >>>
> >>> if (WARN_ON(level == 0 && wm > fifo_size))
> >>> wm = fifo_size;
> >>>
> >>> assuming we want to keep the hack around for now.
> >>>
> >>> Eventually we'll want to make it just return an error though.
> >> Yes, that's what I came up with.
> >>
> >> But we still need to clamp further, probably to plane->wm.fifo_size.
> >> However sr_fifo_size is also clamped to 511 because of the level
> >> calculations here.
> >>
> >> Below it sets sr[level].plane = min(sr_fifo_size, wm[level].plane),
> >> which seems weird. How can this ever end up being something other than
> >> wm[level].plane?
> > There are three planes. CHV was supposed to have maxfifo with up to 2 active
> > planes. But I'm not sure that feature made it in. I never got around
> > testing it.
> I don't know, we only enable it with a single plane, plus cursor. I don't see
> where the other
> plane wm's would fit in?
The FIFO would be split 1:1 when two planes are enabled. But as stated, I
never actually tried it, so I never enabled it.
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH i-g-t v2 05/15] tests/kms: Clean up more users of unassigned pipes.
How about this? tests/kms: Clean up more users of unassigned pipes. Use for_each_pipe_with_valid_output instead. This may increase test time slightly on the affected tests, because now outputs will be tested on every pipe instead of the first pipe. This will increase test coverage to all usable pipes though, so it shouldn't be an issue. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
Op 21-07-16 om 21:23 schreef Lyude: > From: Matt Roper > > When we write watermark values to the hardware, those values are stored > in dev_priv->wm.skl_hw. However with recent watermark changes, the > results structure we're copying from only contains valid watermark and > DDB values for the pipes that are actually changing; the values for > other pipes remain 0. Thus a blind copy of the entire skl_wm_values > structure will clobber the values for unchanged pipes...we need to be > more selective and only copy over the values for the changing pipes. > > This mistake was hidden until recently due to another bug that caused us > to erroneously re-calculate watermarks for all active pipes rather than > changing pipes. Only when that bug was fixed was the impact of this bug > discovered (e.g., modesets failing with "Requested display configuration > exceeds system watermark limitations" messages and leaving watermarks > non-functional, even ones initiated by intel_fbdev_restore_mode). > > Changes since v1: > - Add a function for copying a pipe's wm values >(skl_copy_wm_for_pipe()) so we can reuse this later Looks like I can hit this when I wrote some tests for patch 2 in this series. testcase will be kms_cursor_legacy.2x-flip-vs-cursor-legacy, but I haven't committed the changes yet. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/vlv: Fix off-by-1 error in calculating num_levels.
Op 25-07-16 om 13:51 schreef Ville Syrjälä:
> On Mon, Jul 25, 2016 at 01:32:45PM +0200, Maarten Lankhorst wrote:
>> Hey,
>>
>> Op 19-07-16 om 18:21 schreef Ville Syrjälä:
>>> On Tue, Jul 19, 2016 at 04:50:49PM +0100, Chris Wilson wrote:
On Tue, Jul 19, 2016 at 06:25:42PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 19, 2016 at 05:14:23PM +0200, Maarten Lankhorst wrote:
>> num_levels should be level+1, not level, else num_levels - 1 becomes
>> negative. This resulted in bogus watermarks being written to the first
>> 255 levels like below:
>>
>> [drm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0,
>> sprite1=0, SR: plane=0, cursor=0 level=255 cxsr=0
>> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
>> DVFS request
>> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO
>> underrun
>> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
>> DVFS request
>>
>> Testcase: kms_atomic_transition
>> Fixes: 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another
>> watermark rewrite")
>> Cc: sta...@vger.kernel.org
>> Cc: Ville Syrjälä
>> Signed-off-by: Maarten Lankhorst
>> ---
>> Urgent fix for watermark support. This is definitely a pre-requisite for
>> this series.
>> With this I've noticed that patch "[RFC 3/8] drm/i915/vlv: Move
>> fifo_size from
>> intel_plane_wm_parameters to vlv_wm_state" introduces a regression with
>> invalid FIFO split.
>>
>> I need to find out what's going wrong in that patch before this series
>> can be applied.
>>
>> drivers/gpu/drm/i915/intel_pm.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 376c60b98515..8defdcc54529 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -1148,7 +1148,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>> }
>> }
>>
>> -wm_state->num_levels = level;
>> +wm_state->num_levels = level + 1;
> Nope. The loop above breaks when the current level is bad, hence level-1
> is actually the higher usable level.
Without knowing the limits of plane->wm.fifo_size, it looks like it can
break on level == 0 though.
>>> Hmm. That shouldn't be possible. So looks like a bug snuck in.
>>>
Might as well set that hack to paranoid levels:
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index 630b116988f6..e8c2874b8629 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1124,11 +1124,13 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
/* normal watermarks */
for (level = 0; level < wm_state->num_levels; level++) {
int wm = vlv_compute_wm_level(plane, crtc, state,
level);
- int max_wm = plane->base.type ==
DRM_PLANE_TYPE_CURSOR ? 63 : 511;
-
/* hack */
- if (WARN_ON(level == 0 && wm > max_wm))
- wm = max_wm;
>>> Actually this should just be
>>>
>>> if (WARN_ON(level == 0 && wm > fifo_size))
>>> wm = fifo_size;
>>>
>>> assuming we want to keep the hack around for now.
>>>
>>> Eventually we'll want to make it just return an error though.
>> Yes, that's what I came up with.
>>
>> But we still need to clamp further, probably to plane->wm.fifo_size.
>> However sr_fifo_size is also clamped to 511 because of the level
>> calculations here.
>>
>> Below it sets sr[level].plane = min(sr_fifo_size, wm[level].plane),
>> which seems weird. How can this ever end up being something other than
>> wm[level].plane?
> There are three planes. CHV was supposed to have maxfifo with up to 2 active
> planes. But I'm not sure that feature made it in. I never got around
> testing it.
I don't know, we only enable it with a single plane, plus cursor. I don't see
where the other
plane wm's would fit in?
~Maarten
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Re: [Intel-gfx] [PATCH] drm/i915/vlv: Fix off-by-1 error in calculating num_levels.
On Mon, Jul 25, 2016 at 01:32:45PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 19-07-16 om 18:21 schreef Ville Syrjälä:
> > On Tue, Jul 19, 2016 at 04:50:49PM +0100, Chris Wilson wrote:
> >> On Tue, Jul 19, 2016 at 06:25:42PM +0300, Ville Syrjälä wrote:
> >>> On Tue, Jul 19, 2016 at 05:14:23PM +0200, Maarten Lankhorst wrote:
> num_levels should be level+1, not level, else num_levels - 1 becomes
> negative. This resulted in bogus watermarks being written to the first
> 255 levels like below:
>
> [drm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0,
> sprite1=0, SR: plane=0, cursor=0 level=255 cxsr=0
> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
> DVFS request
> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO
> underrun
> [drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
> DVFS request
>
> Testcase: kms_atomic_transition
> Fixes: 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another
> watermark rewrite")
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjälä
> Signed-off-by: Maarten Lankhorst
> ---
> Urgent fix for watermark support. This is definitely a pre-requisite for
> this series.
> With this I've noticed that patch "[RFC 3/8] drm/i915/vlv: Move
> fifo_size from
> intel_plane_wm_parameters to vlv_wm_state" introduces a regression with
> invalid FIFO split.
>
> I need to find out what's going wrong in that patch before this series
> can be applied.
>
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 376c60b98515..8defdcc54529 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1148,7 +1148,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
> }
> }
>
> -wm_state->num_levels = level;
> +wm_state->num_levels = level + 1;
> >>> Nope. The loop above breaks when the current level is bad, hence level-1
> >>> is actually the higher usable level.
> >> Without knowing the limits of plane->wm.fifo_size, it looks like it can
> >> break on level == 0 though.
> > Hmm. That shouldn't be possible. So looks like a bug snuck in.
> >
> >> Might as well set that hack to paranoid levels:
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> b/drivers/gpu/drm/i915/intel_pm.c
> >> index 630b116988f6..e8c2874b8629 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -1124,11 +1124,13 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
> >> /* normal watermarks */
> >> for (level = 0; level < wm_state->num_levels; level++) {
> >> int wm = vlv_compute_wm_level(plane, crtc, state,
> >> level);
> >> - int max_wm = plane->base.type ==
> >> DRM_PLANE_TYPE_CURSOR ? 63 : 511;
> >> -
> >> /* hack */
> >> - if (WARN_ON(level == 0 && wm > max_wm))
> >> - wm = max_wm;
> > Actually this should just be
> >
> > if (WARN_ON(level == 0 && wm > fifo_size))
> > wm = fifo_size;
> >
> > assuming we want to keep the hack around for now.
> >
> > Eventually we'll want to make it just return an error though.
> Yes, that's what I came up with.
>
> But we still need to clamp further, probably to plane->wm.fifo_size.
> However sr_fifo_size is also clamped to 511 because of the level calculations
> here.
>
> Below it sets sr[level].plane = min(sr_fifo_size, wm[level].plane),
> which seems weird. How can this ever end up being something other than
> wm[level].plane?
There are three planes. CHV was supposed to have maxfifo with up to 2 active
planes. But I'm not sure that feature made it in. I never got around
testing it.
> Because sr_fifo_size >= max_wm is always true.
>
> I guess vlv_invert_wms will invert it, but we could simply only set it there
> then, or remove the min()..
>
> ~Maarten
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Re: [Intel-gfx] [PATCH] drm/i915/vlv: Fix off-by-1 error in calculating num_levels.
Hey,
Op 19-07-16 om 18:21 schreef Ville Syrjälä:
> On Tue, Jul 19, 2016 at 04:50:49PM +0100, Chris Wilson wrote:
>> On Tue, Jul 19, 2016 at 06:25:42PM +0300, Ville Syrjälä wrote:
>>> On Tue, Jul 19, 2016 at 05:14:23PM +0200, Maarten Lankhorst wrote:
num_levels should be level+1, not level, else num_levels - 1 becomes
negative. This resulted in bogus watermarks being written to the first
255 levels like below:
[drm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0,
sprite1=0, SR: plane=0, cursor=0 level=255 cxsr=0
[drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
DVFS request
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO
underrun
[drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR
DVFS request
Testcase: kms_atomic_transition
Fixes: 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another watermark
rewrite")
Cc: sta...@vger.kernel.org
Cc: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
---
Urgent fix for watermark support. This is definitely a pre-requisite for
this series.
With this I've noticed that patch "[RFC 3/8] drm/i915/vlv: Move fifo_size
from
intel_plane_wm_parameters to vlv_wm_state" introduces a regression with
invalid FIFO split.
I need to find out what's going wrong in that patch before this series can
be applied.
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index 376c60b98515..8defdcc54529 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1148,7 +1148,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
}
}
- wm_state->num_levels = level;
+ wm_state->num_levels = level + 1;
>>> Nope. The loop above breaks when the current level is bad, hence level-1
>>> is actually the higher usable level.
>> Without knowing the limits of plane->wm.fifo_size, it looks like it can
>> break on level == 0 though.
> Hmm. That shouldn't be possible. So looks like a bug snuck in.
>
>> Might as well set that hack to paranoid levels:
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 630b116988f6..e8c2874b8629 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -1124,11 +1124,13 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>> /* normal watermarks */
>> for (level = 0; level < wm_state->num_levels; level++) {
>> int wm = vlv_compute_wm_level(plane, crtc, state,
>> level);
>> - int max_wm = plane->base.type ==
>> DRM_PLANE_TYPE_CURSOR ? 63 : 511;
>> -
>> /* hack */
>> - if (WARN_ON(level == 0 && wm > max_wm))
>> - wm = max_wm;
> Actually this should just be
>
> if (WARN_ON(level == 0 && wm > fifo_size))
> wm = fifo_size;
>
> assuming we want to keep the hack around for now.
>
> Eventually we'll want to make it just return an error though.
Yes, that's what I came up with.
But we still need to clamp further, probably to plane->wm.fifo_size.
However sr_fifo_size is also clamped to 511 because of the level calculations
here.
Below it sets sr[level].plane = min(sr_fifo_size, wm[level].plane),
which seems weird. How can this ever end up being something other than
wm[level].plane?
Because sr_fifo_size >= max_wm is always true.
I guess vlv_invert_wms will invert it, but we could simply only set it there
then, or remove the min()..
~Maarten
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Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: Remove stray intel_engine_cs *ring
On Mon, Jul 25, 2016 at 02:01:05PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 10:06 +0100, Chris Wilson wrote:
> > When we refer to intel_engine_cs, we want to use engine so as not to
> > confuse ourselves about ringbuffers.
> >
> > v2: Rename all the functions as well, as well as a few more stray comments.
> >
> > Signed-off-by: Chris Wilson
> > Link:
> > http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-6-git-send-email-ch...@chris-wilson.co.uk
> > Cc: Joonas Lahtinen
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 72
> > +++---
> > drivers/gpu/drm/i915/i915_drv.h| 23 +-
> > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.c| 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.h| 10 ++---
> > 7 files changed, 64 insertions(+), 61 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index b0fd6a7..8db144b 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -62,23 +62,23 @@
> > * The parser always rejects such commands.
> > *
> > * The majority of the problematic commands fall in the MI_* range, with
> > only a
> > - * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
> > + * few specific commands on each engine (e.g. PIPE_CONTROL and
> > MI_FLUSH_DW).
> > *
> > * Implementation:
> > - * Each ring maintains tables of commands and registers which the parser
> > uses in
> > - * scanning batch buffers submitted to that ring.
> > + * Each engine maintains tables of commands and registers which the parser
> > + * uses in scanning batch buffers submitted to that engine.
> > *
> > * Since the set of commands that the parser must check for is
> > significantly
> > * smaller than the number of commands supported, the parser tables
> > contain only
> > * those commands required by the parser. This generally works because
> > command
> > * opcode ranges have standard command length encodings. So for commands
> > that
> > * the parser does not need to check, it can easily skip them. This is
> > - * implemented via a per-ring length decoding vfunc.
> > + * implemented via a per-engine length decoding vfunc.
> > *
> > * Unfortunately, there are a number of commands that do not follow the
> > standard
> > * length encoding for their opcode range, primarily amongst the MI_*
> > commands.
> > * To handle this, the parser provides a way to define explicit "skip"
> > entries
> > - * in the per-ring command tables.
> > + * in the per-engine command tables.
> > *
> > * Other command table entries map fairly directly to high level categories
> > * mentioned above: rejected, master-only, register whitelist. The parser
> > @@ -603,7 +603,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
> > return 0;
> > }
> >
> > -static bool validate_cmds_sorted(struct intel_engine_cs *engine,
> > +static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
>
> This otherwise unrelated change is a dependency from a signature change
> below.
>
> > const struct drm_i915_cmd_table *cmd_tables,
> > int cmd_table_count)
> > {
> > @@ -624,8 +624,9 @@ static bool validate_cmds_sorted(struct intel_engine_cs
> > *engine,
> > u32 curr = desc->cmd.value & desc->cmd.mask;
> >
> > if (curr < previous) {
> > - DRM_ERROR("CMD: table not sorted ring=%d
> > table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
> > - engine->id, i, j, curr, previous);
> > + DRM_ERROR("CMD: %s [%d] command table not
> > sorted: table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
>
> Cut this line here like;
>
> DRM_ERROR("CMD: %s [%d] command table not sorted: "
> "table=%d entry=%d cmd=0x%08X prev=0x%08X\n"
checkpatch.pl dislikes split strings just as much as it dislikes long
lines, but done.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: Remove stray intel_engine_cs *ring
On ma, 2016-07-25 at 10:06 +0100, Chris Wilson wrote:
> When we refer to intel_engine_cs, we want to use engine so as not to
> confuse ourselves about ringbuffers.
>
> v2: Rename all the functions as well, as well as a few more stray comments.
>
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-6-git-send-email-ch...@chris-wilson.co.uk
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 72
> +++---
> drivers/gpu/drm/i915/i915_drv.h| 23 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c| 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h| 10 ++---
> 7 files changed, 64 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index b0fd6a7..8db144b 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -62,23 +62,23 @@
> * The parser always rejects such commands.
> *
> * The majority of the problematic commands fall in the MI_* range, with
> only a
> - * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
> + * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
> *
> * Implementation:
> - * Each ring maintains tables of commands and registers which the parser
> uses in
> - * scanning batch buffers submitted to that ring.
> + * Each engine maintains tables of commands and registers which the parser
> + * uses in scanning batch buffers submitted to that engine.
> *
> * Since the set of commands that the parser must check for is significantly
> * smaller than the number of commands supported, the parser tables contain
> only
> * those commands required by the parser. This generally works because
> command
> * opcode ranges have standard command length encodings. So for commands that
> * the parser does not need to check, it can easily skip them. This is
> - * implemented via a per-ring length decoding vfunc.
> + * implemented via a per-engine length decoding vfunc.
> *
> * Unfortunately, there are a number of commands that do not follow the
> standard
> * length encoding for their opcode range, primarily amongst the MI_*
> commands.
> * To handle this, the parser provides a way to define explicit "skip"
> entries
> - * in the per-ring command tables.
> + * in the per-engine command tables.
> *
> * Other command table entries map fairly directly to high level categories
> * mentioned above: rejected, master-only, register whitelist. The parser
> @@ -603,7 +603,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
> return 0;
> }
>
> -static bool validate_cmds_sorted(struct intel_engine_cs *engine,
> +static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
This otherwise unrelated change is a dependency from a signature change
below.
> const struct drm_i915_cmd_table *cmd_tables,
> int cmd_table_count)
> {
> @@ -624,8 +624,9 @@ static bool validate_cmds_sorted(struct intel_engine_cs
> *engine,
> u32 curr = desc->cmd.value & desc->cmd.mask;
>
> if (curr < previous) {
> - DRM_ERROR("CMD: table not sorted ring=%d
> table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
> - engine->id, i, j, curr, previous);
> + DRM_ERROR("CMD: %s [%d] command table not
> sorted: table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
Cut this line here like;
DRM_ERROR("CMD: %s [%d] command table not sorted: "
"table=%d entry=%d cmd=0x%08X prev=0x%08X\n"
> + engine->name, engine->id,
> + i, j, curr, previous);
Then this cut makes more sense, too.
Apart from that, looks fairly mechanical;
Reviewed-by: Joonas Lahtinen
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Re: [Intel-gfx] [PATCH 04/31] drm/i915: Only drop the batch-pool's object reference
On ma, 2016-07-25 at 09:44 +0100, Chris Wilson wrote:
> On Mon, Jul 25, 2016 at 11:38:07AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> > >
> > > The obj->batch_pool_link is only inspected when traversing the batch
> > > pool list and when on the batch pool list the object is referenced. Thus
> > > when freeing the batch pool list, we only need to unreference the object
> > > and do not have to worry about the obj->batch_pool_link.
> > >
> > > Signed-off-by: Chris Wilson
> > > ---
> > > drivers/gpu/drm/i915/i915_gem_batch_pool.c | 13 ++---
> > > 1 file changed, 6 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > > b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > > index 3507b2753fd3..825981b5aa40 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > > @@ -68,15 +68,14 @@ void i915_gem_batch_pool_fini(struct
> > > i915_gem_batch_pool *pool)
> > > WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex));
> > >
> > > for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {
> > > - while (!list_empty(&pool->cache_list[n])) {
> > > - struct drm_i915_gem_object *obj =
> > > - list_first_entry(&pool->cache_list[n],
> > > - struct drm_i915_gem_object,
> > > - batch_pool_link);
> > > + struct drm_i915_gem_object *obj, *next;
> > >
> > > - list_del(&obj->batch_pool_link);
> > > + list_for_each_entry_safe(obj, next,
> > Why _safe? i915_gem_free_object does not touch the batch_pool_link.
Yeah, that'd be true.
Reviewed-by: Joonas Lahtinen
> Not directly, but it does free the memory including the batch_pool_link. :)
> -Chris
>
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Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm: BIT(DRM_ROTATE_?) -> DRM_ROTATE_?
On ma, 2016-07-25 at 07:39 +, Patchwork wrote: > == Series Details == > > Series: drm: BIT(DRM_ROTATE_?) -> DRM_ROTATE_? > URL : https://patchwork.freedesktop.org/series/10229/ > State : failure > > == Summary == > > Series 10229v1 drm: BIT(DRM_ROTATE_?) -> DRM_ROTATE_? > http://patchwork.freedesktop.org/api/1.0/series/10229/revisions/1/mbox > > Test drv_module_reload_basic: > pass -> SKIP (ro-hsw-i3-4010u) > Test gem_sync: > Subgroup basic-store-each: > pass -> DMESG-FAIL (ro-bdw-i7-5600u) Filed a new bug; https://bugs.freedesktop.org/show_bug.cgi?id=97071 Kernel error: [drm:i915_hangcheck_elapsed [i915]] *ERROR* Hangcheck timer elapsed... video enhancement ring idle > > ro-bdw-i5-5250u total:244 pass:219 dwarn:4 dfail:0 fail:8 skip:13 > ro-bdw-i7-5600u total:244 pass:203 dwarn:0 dfail:1 fail:8 skip:32 > ro-bsw-n3050 total:218 pass:173 dwarn:0 dfail:0 fail:2 skip:42 > ro-byt-n2820 total:244 pass:197 dwarn:0 dfail:0 fail:9 skip:38 > ro-hsw-i3-4010u total:244 pass:211 dwarn:0 dfail:0 fail:8 skip:25 > ro-hsw-i7-4770r total:244 pass:212 dwarn:0 dfail:0 fail:8 skip:24 > ro-ilk-i7-620lm total:244 pass:172 dwarn:0 dfail:0 fail:9 skip:63 > ro-ilk1-i5-650 total:239 pass:172 dwarn:0 dfail:0 fail:9 skip:58 > ro-ivb-i7-3770 total:244 pass:203 dwarn:0 dfail:0 fail:8 skip:33 > ro-skl3-i5-6260u total:244 pass:224 dwarn:0 dfail:0 fail:8 skip:12 > ro-snb-i7-2620M total:244 pass:193 dwarn:0 dfail:0 fail:9 skip:42 > ro-bdw-i7-5557U failed to connect after reboot > > Results at /archive/results/CI_IGT_test/RO_Patchwork_1594/ > > 5c9e3d9 drm-intel-nightly: 2016y-07m-25d-06h-32m-37s UTC integration manifest > 7e91383 drm: BIT(DRM_ROTATE_?) -> DRM_ROTATE_? > -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/31] drm/i915: Prefer list_first_entry_or_null
On ma, 2016-07-25 at 09:03 +0100, Chris Wilson wrote:
> On Mon, Jul 25, 2016 at 10:55:24AM +0300, Joonas Lahtinen wrote:
> >
> > On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> > >
> > > list_first_entry_or_null() can generate better code than using
> > > if (!list_empty()) {ptr = list_first_entry()) ..., so put it to use.
> > >
> > > Signed-off-by: Chris Wilson
> > It looks cleaner, not so sure of the code impact.
> After the patch I sent to linux-kernel@ to improve code gneration for
> list_first_entry_or_null() is applied we save a few bytes on each
> invocation.
Ok, I've not spotted those, but sounds good.
Regards, Joonas
--
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 28/31] drm/i915: Refactor golden render state emission to unconfuse gcc
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote: > + so.obj = i915_gem_object_create(&req->i915->drm, 4096); > + if (IS_ERR(so.obj)) > + return PTR_ERR(so.obj); I remember earlier discussion about having GPU_PAGE_SIZE, did that ever go anywhere? Nor related to this patch specifically, so; Reviewed-by: Joonas Lahtinen -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 26/31] drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote: > As gen6_emit_request() only differs from i9xx_emit_request() when > semaphores are enabled, only use the specialised vfunc in that scenario. > > v2: Reorder semaphore init so as to keep engine->emit_request default > vfunc selection compact. With this change, Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 24/31] drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal()
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Rather than pass in the num_dwords that the caller wishes to use after
> the signal command packet, split the breadcrumb emission into two phases
> and have both the signal and breadcrumb individiually acquire space on
> the ring. This makes the interface simpler for the reader, and will
> simplify for patches.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 51
> ++---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
> 2 files changed, 23 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2fa7db5331c3..68df689a9d1e 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1322,10 +1322,8 @@ static void render_ring_cleanup(struct intel_engine_cs
> *engine)
> intel_fini_pipe_control(engine);
> }
>
> -static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> - unsigned int num_dwords)
> +static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req)
> {
> -#define MBOX_UPDATE_DWORDS 8
> struct intel_ring *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> @@ -1333,10 +1331,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request
> *signaller_req,
> int ret, num_rings;
>
> num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> - num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> -#undef MBOX_UPDATE_DWORDS
> -
> - ret = intel_ring_begin(signaller_req, num_dwords);
> + ret = intel_ring_begin(signaller_req, (num_rings-1) * 8);
> if (ret)
> return ret;
>
> @@ -1360,14 +1355,13 @@ static int gen8_rcs_signal(struct
> drm_i915_gem_request *signaller_req,
> MI_SEMAPHORE_TARGET(waiter->hw_id));
> intel_ring_emit(signaller, 0);
> }
> + intel_ring_advance(signaller);
>
> return 0;
> }
>
> -static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> - unsigned int num_dwords)
> +static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req)
> {
> -#define MBOX_UPDATE_DWORDS 6
> struct intel_ring *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> @@ -1375,10 +1369,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request
> *signaller_req,
> int ret, num_rings;
>
> num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> - num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> -#undef MBOX_UPDATE_DWORDS
> -
> - ret = intel_ring_begin(signaller_req, num_dwords);
> + ret = intel_ring_begin(signaller_req, (num_rings-1) * 6);
> if (ret)
> return ret;
>
> @@ -1400,12 +1391,12 @@ static int gen8_xcs_signal(struct
> drm_i915_gem_request *signaller_req,
> MI_SEMAPHORE_TARGET(waiter->hw_id));
> intel_ring_emit(signaller, 0);
> }
> + intel_ring_advance(signaller);
>
> return 0;
> }
>
> -static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> - unsigned int num_dwords)
> +static int gen6_signal(struct drm_i915_gem_request *signaller_req)
> {
> struct intel_ring *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> @@ -1413,12 +1404,8 @@ static int gen6_signal(struct drm_i915_gem_request
> *signaller_req,
> enum intel_engine_id id;
> int ret, num_rings;
>
> -#define MBOX_UPDATE_DWORDS 3
> num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> - num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
> -#undef MBOX_UPDATE_DWORDS
> -
> - ret = intel_ring_begin(signaller_req, num_dwords);
> + ret = intel_ring_begin(signaller_req, round_up((num_rings-1) * 3, 2));
> if (ret)
> return ret;
>
> @@ -1436,6 +1423,7 @@ static int gen6_signal(struct drm_i915_gem_request
> *signaller_req,
> /* If num_dwords was rounded, make sure the tail pointer is correct */
> if (num_rings % 2 == 0)
> intel_ring_emit(signaller, MI_NOOP);
> + intel_ring_advance(signaller);
>
> return 0;
> }
> @@ -1454,11 +1442,13 @@ static int gen6_emit_request(struct
> drm_i915_gem_request *req)
> struct intel_ring *ring = req->ring;
> int ret;
>
> - if (engine->semaphore.signal)
> - ret = engine->semaphore.signal(req, 4);
> - else
> - ret = intel_ring_begin(req, 4);
> + if (engine->semaphore.signal) {
> + ret = engine->semaphore.signal(req);
> + if (ret)
> + return ret;
> + }
>
Re: [Intel-gfx] [PATCH 23/31] drm/i915/lrc: Update function names to match request flow
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> With adding engine->submit_request, we now have a bunch of functions
> with similar names used at different stages of the execlist submission.
> Try a different coat of paint, to hopefully reduce confusion between the
> requests, intel_engine_cs and the actual execlists submision process.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
You forgot to pick my R-b from previous series, to make it easier for
Patchwork, here it is again;
Reviewed-by: Joonas Lahtinen
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index a9ca31c113c3..149a0dc7aeed 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -384,8 +384,8 @@ static void execlists_update_context(struct
> drm_i915_gem_request *rq)
> execlists_update_context_pdps(ppgtt, reg_state);
> }
>
> -static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
> - struct drm_i915_gem_request *rq1)
> +static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
> + struct drm_i915_gem_request *rq1)
> {
> struct drm_i915_private *dev_priv = rq0->i915;
> unsigned int fw_domains = rq0->engine->fw_domains;
> @@ -418,7 +418,7 @@ static inline void execlists_context_status_change(
> atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
> }
>
> -static void execlists_context_unqueue(struct intel_engine_cs *engine)
> +static void execlists_unqueue(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
> struct drm_i915_gem_request *cursor, *tmp;
> @@ -486,7 +486,7 @@ static void execlists_context_unqueue(struct
> intel_engine_cs *engine)
> req0->tail &= req0->ring->size - 1;
> }
>
> - execlists_submit_requests(req0, req1);
> + execlists_elsp_submit_contexts(req0, req1);
> }
>
> static unsigned int
> @@ -597,7 +597,7 @@ static void intel_lrc_irq_handler(unsigned long data)
> if (submit_contexts) {
> if (!engine->disable_lite_restore_wa ||
> (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
> - execlists_context_unqueue(engine);
> + execlists_unqueue(engine);
> }
>
> spin_unlock(&engine->execlist_lock);
> @@ -606,7 +606,7 @@ static void intel_lrc_irq_handler(unsigned long data)
> DRM_ERROR("More than two context complete events?\n");
> }
>
> -static void execlists_context_queue(struct drm_i915_gem_request *request)
> +static void execlists_submit_request(struct drm_i915_gem_request *request)
> {
> struct intel_engine_cs *engine = request->engine;
> struct drm_i915_gem_request *cursor;
> @@ -637,7 +637,7 @@ static void execlists_context_queue(struct
> drm_i915_gem_request *request)
> list_add_tail(&request->execlist_link, &engine->execlist_queue);
> request->ctx_hw_id = request->ctx->hw_id;
> if (num_elements == 0)
> - execlists_context_unqueue(engine);
> + execlists_unqueue(engine);
>
> spin_unlock_bh(&engine->execlist_lock);
> }
> @@ -1908,7 +1908,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs
> *engine)
> engine->init_hw = gen8_init_common_ring;
> engine->emit_flush = gen8_emit_flush;
> engine->emit_request = gen8_emit_request;
> - engine->submit_request = execlists_context_queue;
> + engine->submit_request = execlists_submit_request;
>
> engine->irq_enable = gen8_logical_ring_enable_irq;
> engine->irq_disable = gen8_logical_ring_disable_irq;
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 22/31] drm/i915: Unify request submission
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Move request submission from emit_request into its own common vfunc
> from i915_add_request().
>
> v2: Convert I915_DISPATCH_flags to BIT(x) whilst passing
> v3: Rename a few functions to match.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_gem_request.c| 8 +++-
> drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++---
> drivers/gpu/drm/i915/intel_guc.h | 1 -
> drivers/gpu/drm/i915/intel_lrc.c | 18 +++---
> drivers/gpu/drm/i915/intel_ringbuffer.c| 23 +--
> drivers/gpu/drm/i915/intel_ringbuffer.h| 23 +++
> 6 files changed, 36 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
> b/drivers/gpu/drm/i915/i915_gem_request.c
> index 8814e9c5266b..f4bf9f669eed 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -467,12 +467,9 @@ void __i915_add_request(struct drm_i915_gem_request
> *request,
> */
> request->postfix = ring->tail;
>
> - if (i915.enable_execlists)
> - ret = engine->emit_request(request);
> - else
> - ret = engine->add_request(request);
> /* Not allowed to fail! */
> - WARN(ret, "emit|add_request failed: %d!\n", ret);
> + ret = engine->emit_request(request);
> + WARN(ret, "(%s)->emit_request failed: %d!\n", engine->name, ret);
>
> /* Sanity check that the reserved size was large enough. */
> ret = ring->tail - request_start;
> @@ -484,6 +481,7 @@ void __i915_add_request(struct drm_i915_gem_request
> *request,
> reserved_tail, ret);
>
> i915_gem_mark_busy(engine);
> + engine->submit_request(request);
> }
>
> static unsigned long local_clock_us(unsigned int *cpu)
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index eccd34832fe6..32d0e1890950 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -585,7 +585,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
> * The only error here arises if the doorbell hardware isn't functioning
> * as expected, which really shouln't happen.
> */
> -int i915_guc_submit(struct drm_i915_gem_request *rq)
> +static void i915_guc_submit(struct drm_i915_gem_request *rq)
> {
> unsigned int engine_id = rq->engine->id;
> struct intel_guc *guc = &rq->i915->guc;
> @@ -602,8 +602,6 @@ int i915_guc_submit(struct drm_i915_gem_request *rq)
>
> guc->submissions[engine_id] += 1;
> guc->last_seqno[engine_id] = rq->fence.seqno;
> -
> - return b_ret;
> }
>
> /*
> @@ -992,6 +990,7 @@ int i915_guc_submission_enable(struct drm_i915_private
> *dev_priv)
> {
> struct intel_guc *guc = &dev_priv->guc;
> struct i915_guc_client *client;
> + struct intel_engine_cs *engine;
>
> /* client for execbuf submission */
> client = guc_client_alloc(dev_priv,
> @@ -1006,6 +1005,10 @@ int i915_guc_submission_enable(struct drm_i915_private
> *dev_priv)
> host2guc_sample_forcewake(guc, client);
> guc_init_doorbell_hw(guc);
>
> + /* Take over from manual control of ELSP (execlists) */
> + for_each_engine(engine, dev_priv)
> + engine->submit_request = i915_guc_submit;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index 3e3e743740c0..623cf26cd784 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -160,7 +160,6 @@ extern int intel_guc_resume(struct drm_device *dev);
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
> -int i915_guc_submit(struct drm_i915_gem_request *rq);
> void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 250edb2bcef7..a9ca31c113c3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -738,7 +738,7 @@ err_unpin:
> }
>
> /*
> - * intel_logical_ring_advance_and_submit() - advance the tail and submit the
> workload
> + * intel_logical_ring_advance() - advance the tail and prepare for submission
> * @request: Request to advance the logical ringbuffer of.
> *
> * The tail is updated in our logical ringbuffer struct, not in the actual
> context. What
> @@ -747,7 +747,7 @@ err_unpin:
> * point, the tail *inside* the context is updated and the ELSP written to.
> */
> static int
> -intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> +
Re: [Intel-gfx] [PATCH 20/31] drm/i915: Remove intel_ring_get_tail()
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Joonas doesn't like the tiny function, especially if I go around making
> it more complicated and using it elsewhere. To remove that temptation,
> remove the function!
>
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_request.c | 8
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
> 2 files changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
> b/drivers/gpu/drm/i915/i915_gem_request.c
> index 995ae99e9cf7..1c185e293bf0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -419,7 +419,7 @@ void __i915_add_request(struct drm_i915_gem_request
> *request,
> * should already have been reserved in the ring buffer. Let the ring
> * know that it is time to use that space up.
> */
> - request_start = intel_ring_get_tail(ring);
> + request_start = ring->tail;
> reserved_tail = request->reserved_space;
> request->reserved_space = 0;
>
> @@ -465,19 +465,19 @@ void __i915_add_request(struct drm_i915_gem_request
> *request,
> * GPU processing the request, we never over-estimate the
> * position of the head.
> */
> - request->postfix = intel_ring_get_tail(ring);
> + request->postfix = ring->tail;
>
> if (i915.enable_execlists) {
> ret = engine->emit_request(request);
> } else {
> ret = engine->add_request(request);
>
> - request->tail = intel_ring_get_tail(ring);
> + request->tail = ring->tail;
> }
> /* Not allowed to fail! */
> WARN(ret, "emit|add_request failed: %d!\n", ret);
> /* Sanity check that the reserved size was large enough. */
> - ret = intel_ring_get_tail(ring) - request_start;
> + ret = ring->tail - request_start;
> if (ret < 0)
> ret += ring->size;
> WARN_ONCE(ret > reserved_tail,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index cbd46d5e8d6b..13b816f2d264 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -488,11 +488,6 @@ static inline u32 intel_engine_get_seqno(struct
> intel_engine_cs *engine)
>
> int init_workarounds_ring(struct intel_engine_cs *engine);
>
> -static inline u32 intel_ring_get_tail(struct intel_ring *ring)
> -{
> - return ring->tail;
> -}
> -
> /*
> * Arbitrary size for largest possible 'add request' sequence. The code paths
> * are complex and variable. Empirical measurement shows that the worst case
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✓ Ro.CI.BAT: success for series starting with [01/31] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2)
== Series Details == Series: series starting with [01/31] drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() (rev2) URL : https://patchwork.freedesktop.org/series/10230/ State : success == Summary == Series 10230v2 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/10230/revisions/2/mbox ro-bdw-i5-5250u total:244 pass:219 dwarn:4 dfail:0 fail:8 skip:13 ro-bdw-i7-5557U total:244 pass:221 dwarn:1 dfail:0 fail:8 skip:14 ro-bdw-i7-5600u total:244 pass:204 dwarn:0 dfail:0 fail:8 skip:32 ro-bsw-n3050 total:218 pass:173 dwarn:0 dfail:0 fail:2 skip:42 ro-byt-n2820 total:244 pass:197 dwarn:0 dfail:0 fail:9 skip:38 ro-hsw-i3-4010u total:244 pass:212 dwarn:0 dfail:0 fail:8 skip:24 ro-hsw-i7-4770r total:244 pass:212 dwarn:0 dfail:0 fail:8 skip:24 ro-ilk-i7-620lm total:244 pass:172 dwarn:0 dfail:0 fail:9 skip:63 ro-ilk1-i5-650 total:239 pass:172 dwarn:0 dfail:0 fail:9 skip:58 ro-ivb-i7-3770 total:244 pass:203 dwarn:0 dfail:0 fail:8 skip:33 ro-skl3-i5-6260u total:244 pass:224 dwarn:0 dfail:0 fail:8 skip:12 ro-snb-i7-2620M total:244 pass:193 dwarn:0 dfail:0 fail:9 skip:42 Results at /archive/results/CI_IGT_test/RO_Patchwork_1597/ 5c9e3d9 drm-intel-nightly: 2016y-07m-25d-06h-32m-37s UTC integration manifest bedeecf drm/i915: Rename engine->semaphore.sync_to, engine->sempahore.signal locals 7e586ab drm/i915: Simplify calling engine->sync_to 542fe17 drm/i915: Unify legacy/execlists submit_execbuf callbacks ff10e7e drm/i915: Refactor golden render state emission to unconfuse gcc 32095db drm/i915: Remove duplicate golden render state init from execlists 2a3e2d7 drm/i915/ringbuffer: Specialise SNB+ request emission for semaphores a622ad64b drm/i915: Reuse legacy breadcrumbs + tail emission 4446715 drm/i915: Stop passing caller's num_dwords to engine->semaphore.signal() 50f4681 drm/i915/lrc: Update function names to match request flow 39e9cef drm/i915: Unify request submission ae05ba0 drm/i915: Convert engine->write_tail to operate on a request 5495322 drm/i915: Remove intel_ring_get_tail() 14e06f3 drm/i915: Unify legacy/execlists emission of MI_BATCHBUFFER_START e337284 drm/i915: Simplify request_alloc by returning the allocated request 47701d5 drm/i915: Remove obsolete engine->gpu_caches_dirty c1cdbc6 drm/i915: Rename intel_pin_and_map_ring() a3b5cc8 drm/i915: Rename residual ringbuf parameters b296387 drm/i915: Rename struct intel_ringbuffer to struct intel_ring 9bdf7e2 drm/i915: Rename intel_context[engine].ringbuf 3ae54a2e drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs b4b003c drm/i915: Rename request->ringbuf to request->ring d40ec77 drm/i915: Unify intel_logical_ring_emit and intel_ring_emit 2b302ad drm/i915: Update a couple of hangcheck comments to talk about engines dc1807f drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c 38001ff drm/i915: Avoid using intel_engine_cs *ring for GPU error capture f68488d drm/i915: Use engine to refer to the user's BSD intel_engine_cs ce8c1ab drm/i915/cmdparser: Remove stray intel_engine_cs *ring 5596a46 drm/i915: Only drop the batch-pool's object reference 0ab690f drm/i915: Only clear the client pointer when tearing down the file 7c850c6 drm/i915: Prefer list_first_entry_or_null baf2c02 drm/i915: Reduce breadcrumb lock coverage for intel_engine_enable_signaling() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/31] drm/i915: Remove obsolete engine->gpu_caches_dirty
On Mon, Jul 25, 2016 at 12:14:44PM +0300, Joonas Lahtinen wrote: > On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote: > > Space for flushing the GPU cache prior to completing the request is > > preallocated and so cannot fail. > > Patch title and commit message have some disconnect. Could you explain > in a bit more detail what made gpu_caches_dirty obsolete? Introduction of requests. gpu_caches_dirty tracked the GPU cache state for the outstanding_lazy_seqno, long obsolete, since we only submit complete requests. (Previously we could cancel the breadcrumb due to an interrupt without having flushed the caches and so before the next batch we had to emit a cache flush.) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/31] drm/i915: Simplify request_alloc by returning the allocated request
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> If is simpler and leads to more readable code through the callstack if
> the allocation returns the allocated struct through the return value.
>
> The importance of this is that it no longer looks like we accidentally
> allocate requests as side-effect of calling certain functions.
>
Dave seems to have expressed to wish to review this around January, so
CC'ing him here.
From me,
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h| 3 +-
> drivers/gpu/drm/i915/i915_gem.c| 75
> --
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++---
> drivers/gpu/drm/i915/i915_gem_request.c| 58 ---
> drivers/gpu/drm/i915/i915_trace.h | 13 +++---
> drivers/gpu/drm/i915/intel_display.c | 36 ++
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_overlay.c | 20
> 8 files changed, 79 insertions(+), 140 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 09e72b0510ab..1031f5a7126a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3171,8 +3171,7 @@ static inline void i915_gem_object_unpin_map(struct
> drm_i915_gem_object *obj)
>
> int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
> int i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request **to_req);
> + struct drm_i915_gem_request *to);
> void i915_vma_move_to_active(struct i915_vma *vma,
> struct drm_i915_gem_request *req);
> int i915_gem_dumb_create(struct drm_file *file_priv,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 59890f523c5f..b6c4ff63725f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2845,51 +2845,35 @@ out:
>
> static int
> __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> - struct intel_engine_cs *to,
> - struct drm_i915_gem_request *from_req,
> - struct drm_i915_gem_request **to_req)
> + struct drm_i915_gem_request *to,
> + struct drm_i915_gem_request *from)
> {
> - struct intel_engine_cs *from;
> int ret;
>
> - from = i915_gem_request_get_engine(from_req);
> - if (to == from)
> + if (to->engine == from->engine)
> return 0;
>
> - if (i915_gem_request_completed(from_req))
> + if (i915_gem_request_completed(from))
> return 0;
>
> if (!i915.semaphores) {
> - struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - ret = __i915_wait_request(from_req,
> - i915->mm.interruptible,
> + ret = __i915_wait_request(from,
> + from->i915->mm.interruptible,
> NULL,
> NO_WAITBOOST);
> if (ret)
> return ret;
>
> - i915_gem_object_retire_request(obj, from_req);
> + i915_gem_object_retire_request(obj, from);
> } else {
> - int idx = intel_engine_sync_index(from, to);
> - u32 seqno = i915_gem_request_get_seqno(from_req);
> + int idx = intel_engine_sync_index(from->engine, to->engine);
> + u32 seqno = i915_gem_request_get_seqno(from);
>
> - WARN_ON(!to_req);
> -
> - if (seqno <= from->semaphore.sync_seqno[idx])
> + if (seqno <= from->engine->semaphore.sync_seqno[idx])
> return 0;
>
> - if (*to_req == NULL) {
> - struct drm_i915_gem_request *req;
> -
> - req = i915_gem_request_alloc(to, NULL);
> - if (IS_ERR(req))
> - return PTR_ERR(req);
> -
> - *to_req = req;
> - }
> -
> - trace_i915_gem_ring_sync_to(*to_req, from, from_req);
> - ret = to->semaphore.sync_to(*to_req, from, seqno);
> + trace_i915_gem_ring_sync_to(to, from);
> + ret = to->engine->semaphore.sync_to(to, from->engine, seqno);
> if (ret)
> return ret;
>
> @@ -2897,8 +2881,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> * might have just caused seqno wrap under
> * the radar.
> */
> - from->semaphore.sync_seqno[idx] =
> -
> i915_gem_request_get_seqno(obj->last_read_req[from->id]);
> + from->engine->semaphore.sync_seqno[idx] =
> +
Re: [Intel-gfx] [PATCH 17/31] drm/i915: Remove obsolete engine->gpu_caches_dirty
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Space for flushing the GPU cache prior to completing the request is
> preallocated and so cannot fail.
Patch title and commit message have some disconnect. Could you explain
in a bit more detail what made gpu_caches_dirty obsolete?
Also, worth mentioning that after this change legacy/execlist flushing
code is unified (could be split patch too? With your "Now that ..."
reasoning).
Somebody not reviewing the series linearly might feel lost.
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index ca1d4f573832..048050176ff9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct
> drm_i915_gem_request *req,
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
>
> - /* Unconditionally invalidate gpu caches and ensure that we do flush
> - * any residual writes from the previous batch.
> - */
> - return intel_engine_invalidate_all_caches(req);
> + /* Unconditionally invalidate gpu caches and TLBs. */
A nitpick, but maybe s/gpu/GPU/
> + return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);
> }
>
> static bool
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
> b/drivers/gpu/drm/i915/i915_gem_request.c
> index 942b5b1f1602..7b772d914e23 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -451,10 +451,9 @@ void __i915_add_request(struct drm_i915_gem_request
> *request,
> * what.
> */
> if (flush_caches) {
> - if (i915.enable_execlists)
> - ret = logical_ring_flush_all_caches(request);
> - else
> - ret = intel_engine_flush_all_caches(request);
> + ret = request->engine->emit_flush(request,
> + 0, I915_GEM_GPU_DOMAINS);
> +
> /* Not allowed to fail! */
> WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
Fix this message too.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 12/31] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
On Mon, Jul 25, 2016 at 11:49:45AM +0300, Joonas Lahtinen wrote: > On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote: > > Having ringbuf->ring point to an engine is confusing, so rename it once > > again to ring->engine. > > > > Signed-off-by: Chris Wilson > > I still do not see a connection between commit message and content, so > you could mentione renaming the function (which is all this patch > does). That's weird, I thought I had dropped this patch - it wasn't intended to be sent again as thinking about how this would look in an intel_legacy_submission.c says this is pointless churn. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/cmdparser: Remove stray intel_engine_cs *ring
When we refer to intel_engine_cs, we want to use engine so as not to
confuse ourselves about ringbuffers.
v2: Rename all the functions as well, as well as a few more stray comments.
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-6-git-send-email-ch...@chris-wilson.co.uk
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 72 +++---
drivers/gpu/drm/i915/i915_drv.h| 23 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h| 10 ++---
7 files changed, 64 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index b0fd6a7..8db144b 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -62,23 +62,23 @@
* The parser always rejects such commands.
*
* The majority of the problematic commands fall in the MI_* range, with only a
- * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
+ * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
*
* Implementation:
- * Each ring maintains tables of commands and registers which the parser uses
in
- * scanning batch buffers submitted to that ring.
+ * Each engine maintains tables of commands and registers which the parser
+ * uses in scanning batch buffers submitted to that engine.
*
* Since the set of commands that the parser must check for is significantly
* smaller than the number of commands supported, the parser tables contain
only
* those commands required by the parser. This generally works because command
* opcode ranges have standard command length encodings. So for commands that
* the parser does not need to check, it can easily skip them. This is
- * implemented via a per-ring length decoding vfunc.
+ * implemented via a per-engine length decoding vfunc.
*
* Unfortunately, there are a number of commands that do not follow the
standard
* length encoding for their opcode range, primarily amongst the MI_* commands.
* To handle this, the parser provides a way to define explicit "skip" entries
- * in the per-ring command tables.
+ * in the per-engine command tables.
*
* Other command table entries map fairly directly to high level categories
* mentioned above: rejected, master-only, register whitelist. The parser
@@ -603,7 +603,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
return 0;
}
-static bool validate_cmds_sorted(struct intel_engine_cs *engine,
+static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_cmd_table *cmd_tables,
int cmd_table_count)
{
@@ -624,8 +624,9 @@ static bool validate_cmds_sorted(struct intel_engine_cs
*engine,
u32 curr = desc->cmd.value & desc->cmd.mask;
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d
table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
- engine->id, i, j, curr, previous);
+ DRM_ERROR("CMD: %s [%d] command table not
sorted: table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
+ engine->name, engine->id,
+ i, j, curr, previous);
ret = false;
}
@@ -636,7 +637,7 @@ static bool validate_cmds_sorted(struct intel_engine_cs
*engine,
return ret;
}
-static bool check_sorted(int ring_id,
+static bool check_sorted(const struct intel_engine_cs *engine,
const struct drm_i915_reg_descriptor *reg_table,
int reg_count)
{
@@ -648,8 +649,9 @@ static bool check_sorted(int ring_id,
u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
if (curr < previous) {
- DRM_ERROR("CMD: table not sorted ring=%d entry=%d
reg=0x%08X prev=0x%08X\n",
- ring_id, i, curr, previous);
+ DRM_ERROR("CMD: engine %s [%d] register table not
sorted: entry=%d reg=0x%08X prev=0x%08X\n",
+ engine->name, engine->id,
+ i, curr, previous);
ret = false;
}
@@ -666,7 +668,7 @@ static bool validate_regs_sorted(struct intel_engine_cs
*engine)
for (i = 0; i < engine->reg_table_count; i++) {
table = &engine->reg_tables[i];
- if (!check_sorted(engine->id, table->regs, table->num_regs))
+ if (!check_sorted(engine, table->regs, table->num
Re: [Intel-gfx] [PATCH 15/31] drm/i915: Rename residual ringbuf parameters
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Now that we have a clear ring/engine split and a struct intel_ring, we
> no longer need the stopgap ringbuf names.
+1 vote for squashing related renames, should be make picking them
later easier, unless there is huge pieces of code in between.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 66
> -
> drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +--
> 2 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 90572b862eec..5ff44eb46f55 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -47,15 +47,15 @@ int __intel_ring_space(int head, int tail, int size)
> return space - I915_RING_FREE_SPACE;
> }
>
> -void intel_ring_update_space(struct intel_ring *ringbuf)
> +void intel_ring_update_space(struct intel_ring *ring)
> {
> - if (ringbuf->last_retired_head != -1) {
> - ringbuf->head = ringbuf->last_retired_head;
> - ringbuf->last_retired_head = -1;
> + if (ring->last_retired_head != -1) {
> + ring->head = ring->last_retired_head;
> + ring->last_retired_head = -1;
> }
>
> - ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
> - ringbuf->tail, ringbuf->size);
> + ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
> + ring->tail, ring->size);
See, no getter function used here either for ring->tail and how clean
it looks.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 12/31] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> Having ringbuf->ring point to an engine is confusing, so rename it once
> again to ring->engine.
>
> Signed-off-by: Chris Wilson
I still do not see a connection between commit message and content, so
you could mentione renaming the function (which is all this patch
does).
For code,
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 7ba31724feaf..c4582b9a6862 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2186,7 +2186,7 @@ static void intel_ring_context_unpin(struct
> i915_gem_context *ctx,
> i915_gem_context_put(ctx);
> }
>
> -static int intel_init_ring_buffer(struct intel_engine_cs *engine)
> +static int intel_init_engine(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> struct intel_ringbuffer *ringbuf;
> @@ -2883,7 +2883,7 @@ int intel_init_render_ring_buffer(struct
> intel_engine_cs *engine)
> engine->init_hw = init_render_ring;
> engine->cleanup = render_ring_cleanup;
>
> - ret = intel_init_ring_buffer(engine);
> + ret = intel_init_engine(engine);
> if (ret)
> return ret;
>
> @@ -2922,7 +2922,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs
> *engine)
> engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
> }
>
> - return intel_init_ring_buffer(engine);
> + return intel_init_engine(engine);
> }
>
> /**
> @@ -2936,7 +2936,7 @@ int intel_init_bsd2_ring_buffer(struct intel_engine_cs
> *engine)
>
> engine->flush = gen6_bsd_ring_flush;
>
> - return intel_init_ring_buffer(engine);
> + return intel_init_engine(engine);
> }
>
> int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
> @@ -2949,7 +2949,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs
> *engine)
> if (INTEL_GEN(dev_priv) < 8)
> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>
> - return intel_init_ring_buffer(engine);
> + return intel_init_engine(engine);
> }
>
> int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
> @@ -2966,7 +2966,7 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs
> *engine)
> engine->irq_disable = hsw_vebox_irq_disable;
> }
>
> - return intel_init_ring_buffer(engine);
> + return intel_init_engine(engine);
> }
>
> int
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 08/31] drm/i915: Remove stray intel_engine_cs ring identifiers from i915_gem.c
On Mon, Jul 25, 2016 at 11:45:42AM +0300, Joonas Lahtinen wrote:
> On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> > A few places we use ring when referring to the struct intel_engine_cs. An
> > anachronism we are pruning out.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 24
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index e155e8dd28ed..7bfce1d5c61b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -46,7 +46,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct
> > drm_i915_gem_object *o
> > static void
> > i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
> > static void
> > -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
> > +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine);
> >
> > static bool cpu_cache_is_coherent(struct drm_device *dev,
> > enum i915_cache_level level)
> > @@ -1385,10 +1385,10 @@ static void
> > i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> > struct drm_i915_gem_request *req)
> > {
> > - int ring = req->engine->id;
> > + int idx = req->engine->id;
>
> See below.
>
> >
> > - if (obj->last_read_req[ring] == req)
> > - i915_gem_object_retire__read(obj, ring);
> > + if (obj->last_read_req[idx] == req)
> > + i915_gem_object_retire__read(obj, idx);
> > else if (obj->last_write_req == req)
> > i915_gem_object_retire__write(obj);
> >
> > @@ -2381,20 +2381,20 @@ i915_gem_object_retire__write(struct
> > drm_i915_gem_object *obj)
> > }
> >
> > static void
> > -i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> > +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx)
>
> I do not fancy declaring different variable names than are used. Also,
> idx is very cryptic in this function signature (one would think of
> object index).
If you look at the later patches (posted earlier ;) using index is the
less cryptic option as it really does refer to the index of the tracker.
There was a desired to avoid using ring and here I was trying to avoid
confusion with activity tracking.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 09/31] drm/i915: Update a couple of hangcheck comments to talk about engines
On ma, 2016-07-25 at 08:44 +0100, Chris Wilson wrote:
> We still have lots of comments that refer to the old ring when we mean
> struct intel_engine_cs and its hardware correspondence. This patch fixes
> an instance inside hangcheck to talk about engines.
>
These could be squashed down a bit too.
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 7104dc1463eb..f5bf4f913a91 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3140,13 +3140,13 @@ static void i915_hangcheck_elapsed(struct work_struct
> *work)
> }
> } else {
> /* We always increment the hangcheck score
> - * if the ring is busy and still processing
> + * if the engine is busy and still processing
> * the same request, so that no single request
> * can run indefinitely (such as a chain of
> * batches). The only time we do not increment
> * the hangcheck score on this ring, if this
> - * ring is in a legitimate wait for another
> - * ring. In that case the waiting ring is a
> + * engine is in a legitimate wait for another
> + * engine. In that case the waiting engine is a
> * victim and we want to be sure we catch the
> * right culprit. Then every time we do kick
> * the ring, add a small increment to the
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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