Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Joonas Lahtinen]

On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote:
> We're no longer using any invalid PTEs - everything that's not used
> should be pointing to scratch.
> 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Michel Thierry 
> Cc: Mika Kuoppala 
> Signed-off-by: Michał Winiarski 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

[Joonas Lahtinen]

I wonder if GCC is doing the right thing, do we have some benchmark for
this, Chris, Mika? The code is much more readable in my eyes after the
changes.

On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote:
> +static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + uint64_t start,
> + uint64_t length,
> + bool use_scratch)
>  {
>   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> +
> + unsigned int pte_start = gen8_pte_index(start);
> + unsigned int num_entries = min(gen8_pte_count(start, length),
> +    GEN8_PTES);

i915_pte_count (called by gen8_pte_count) states following;

"the max value would be GEN6_PTES for GEN6, and GEN8_PTES for GEN8."

GEM_BUG_ON(num_entries > GEN8_PTES); would be the standard recipe for
paranoia. But I don't think it's needed here. 

> + uint64_t pte;
> +

No newlines to the variable block, keep it tight.

> @@ -768,21 +793,13 @@ static void gen8_ppgtt_clear_range(struct 
> i915_address_space *vm,
>      bool use_scratch)
>  {
>   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> - gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
> -  I915_CACHE_LLC, use_scratch);
>  
> - if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
> - gen8_ppgtt_clear_pte_range(vm, >pdp, start, length,
> -    scratch_pte);
> - } else {
> - uint64_t pml4e;
> - struct i915_page_directory_pointer *pdp;
> -
> - gen8_for_each_pml4e(pdp, >pml4, start, length, pml4e) {
> - gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
> -    scratch_pte);
> - }
> - }
> + if (!USES_FULL_48BIT_PPGTT(vm->dev))

Now that this is so much simplified, the negation could be removed, and
just just write if (USES_FULL_...)

Other than above, looks good to me.

Regards, Joonas
-- 
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Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Praveen Paneri]

Thanks Chris for the review. Will fix these and resend.

~Praveen

On Wednesday 05 October 2016 01:26 AM, Chris Wilson wrote:

On Tue, Oct 04, 2016 at 09:16:06PM +0530, Praveen Paneri wrote:

+#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \
+   && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))


Edit dev_priv->info.has_decoupled_mmio on init.


+static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
+u32 reg,
+enum forcewake_domains fw_engine,
+enum decoupled_ops operation)
+{
+   enum decoupled_power_domains dpd_engine;
+   u32 ctrl_reg_data = 0;
+
+   dpd_engine = fw2dpd_engine[fw_engine - 1];


enum decoupled_power_domains dpd = fw2dpd_engine[fw_engine - 1];

enum decoupled_power_domain

And don't call it fw_engine. fw_domain, if you must.


+
+   ctrl_reg_data |= reg;
+   ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
+   ctrl_reg_data |= (dpd_engine << GEN9_DECOUPLED_PD_SHIFT);
+   __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
+
+   ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
+   __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
+
+   if (wait_for_atomic((__raw_i915_read32(dev_priv,
+   GEN9_DECOUPLED_REG0_DW1) & GEN9_DECOUPLED_DW1_GO) == 0,
+   FORCEWAKE_ACK_TIMEOUT_MS))
+   DRM_ERROR("Decoupled MMIO wait timed out\n");
+}
+
+static inline u32 __gen9_decoupled_mmio_read(struct drm_i915_private *dev_priv,
+  u32 reg,
+  enum forcewake_domains fw)


__gen9_decoupeld_mmio_read32()


+{
+   __gen9_decoupled_mmio_access(dev_priv,
+   reg,
+   fw_engine,
+   GEN9_DECOUPLED_OP_READ);


__gen9_decoupled_mmio_access(dev_priv, reg, fw, GEN9_DECOUPLED_OP_READ);


+
+   return __raw_i915_read32(dev_priv,
+   GEN9_DECOUPLED_REG0_DW0);


Everywhere! Please be careful with alignment.


+#define __gen9_decoupled_read(x) \
+static u##x \
+gen9_decoupled_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool 
trace) { \
+   enum forcewake_domains fw_engine; \
+   GEN6_READ_HEADER(x); \
+   fw_engine = __fwtable_reg_read_fw_domains(offset); \
+   if (!fw_engine || !(fw_engine & ~dev_priv->uncore.fw_domains_active)) { 
\
+   val = __raw_i915_read##x(dev_priv, reg); \
+   } else { \
+   unsigned i; \
+   u32 *ptr_data = (u32 *)  \
+   for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
+   *ptr_data = __gen9_decoupled_mmio_read(dev_priv, \
+offset, \
+fw_engine); \
+   } \
+   GEN6_READ_FOOTER; \
+}


Reverse it,

if (domain & ~dev_priv->uncore.fw_domains_active) {
u32 *ptr = (u32 *)
unsigned i;

for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr++)
*ptr = __gen9_decoupled_mmio_read32(dev_priv, offset, 
domain);
} else {
val = __raw_i915_read##x(dev_priv, reg);
}


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[Intel-gfx] No HW acceleration for HDPI scaling

[Oleg German]

Hello, I've recently tried to combine HD display with laptop HDPI display
(1920x1200 + 3200x1800)

I've tried to follow this instruction
https://wiki.archlinux.org/index.php/HiDPI#Side_display

And final script looks like this
xrandr --output DP1 --scale 2x2 --mode 1920x1200 --fb 3840x4200 --pos 0x0
xrandr --output eDP1 --scale 1x1 --pos 0x2400

Now it looks good, but everything becomes very slow like there is HW
acceleration at all.

I'm using Intel® HD Graphics 520 on Ubuntu 16.04 + latest updates via Intel
Graphics Update Tool

Can anyone suggest how to make it fast or maybe better scaling method?
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915: Share the computation of ring size for RING_CTL register

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/8] drm/i915: Share the computation of ring 
size for RING_CTL register
URL   : https://patchwork.freedesktop.org/series/13295/
State : success

== Summary ==

Series 13295v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13295/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (fi-byt-n2820)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2626/

2e47fbed60d05480cfbd097c1912e6823c0310ee drm-intel-nightly: 
2016y-10m-04d-14h-08m-17s UTC integration manifest
6aa8454 drm/i915: Show waiters in i915_hangcheck_info
66aa83a drm/i915: Show RING registers through debugfs
76ceffc drm/i915: Show bounds of active request in the ring on GPU hang
054e9da drm/i915: Double check hangcheck.seqno after reset
b54dc9e drm/i915: Disable irqs across GPU reset
ff5f38f drm/i915/execlists: Move clearing submission count from reset to init
4728a3c drm/i915/execlists: Reinitialise context image after GPU hang
ad6ea1a drm/i915: Share the computation of ring size for RING_CTL register

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[Intel-gfx] [CI 2/8] drm/i915/execlists: Reinitialise context image after GPU hang

[Chris Wilson]

On Braswell, at least, we observe that the context image is written in
multiple phases. The first phase is to clear the register state, and
subsequently rewrite it. A GPU reset at the right moment can interrupt
the context update leaving it corrupt, and our update of the RING_HEAD
is not sufficient to restart the engine afterwards. To recover, we need
to reset the registers back to their original values. The context state
is lost. What we need is a better mechanism to serialise the reset with
pending flushes from the GPU.

Fixes: 821ed7df6e2a ("drm/i915: Update reset path to fix incomplete requests")
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 103 +++
 1 file changed, 62 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5ede272eb4d2..0ea992ba2723 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -226,10 +226,16 @@ enum {
 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
 
+#define WA_TAIL_DWORDS 2
+
 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine);
 static int intel_lr_context_pin(struct i915_gem_context *ctx,
struct intel_engine_cs *engine);
+static void execlists_init_reg_state(u32 *reg_state,
+struct i915_gem_context *ctx,
+struct intel_engine_cs *engine,
+struct intel_ring *ring);
 
 /**
  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
@@ -707,7 +713,6 @@ static int intel_lr_context_pin(struct i915_gem_context 
*ctx,
 {
struct intel_context *ce = >engine[engine->id];
void *vaddr;
-   u32 *lrc_reg_state;
int ret;
 
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -726,17 +731,16 @@ static int intel_lr_context_pin(struct i915_gem_context 
*ctx,
goto unpin_vma;
}
 
-   lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
-
ret = intel_ring_pin(ce->ring);
if (ret)
goto unpin_map;
 
intel_lr_context_descriptor_update(ctx, engine);
 
-   lrc_reg_state[CTX_RING_BUFFER_START+1] =
+   ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
+   ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
i915_ggtt_offset(ce->ring->vma);
-   ce->lrc_reg_state = lrc_reg_state;
+
ce->state->obj->dirty = true;
 
/* Invalidate GuC TLB. */
@@ -1284,8 +1288,21 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
struct execlist_port *port = engine->execlist_port;
struct intel_context *ce = >ctx->engine[engine->id];
 
+   /* We want a simple context + ring to execute the breadcrumb update.
+* We cannot rely on the context being intact across the GPU hang,
+* so clear it and rebuild just what we need for the breadcrumb.
+* All pending requests for this context will be zapped, and any
+* future request will be after userspace has had the opportunity
+* to recreate its own state.
+*/
+   execlists_init_reg_state(ce->lrc_reg_state,
+request->ctx, engine, ce->ring);
+
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
+   ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
+   i915_ggtt_offset(ce->ring->vma);
ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
+
request->ring->head = request->postfix;
request->ring->last_retired_head = -1;
intel_ring_update_space(request->ring);
@@ -1305,6 +1322,9 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
GEM_BUG_ON(request->ctx != port[0].request->ctx);
port[0].count = 0;
port[1].count = 0;
+
+   /* Reset WaIdleLiteRestore:bdw,skl as well */
+   request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
 }
 
 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
@@ -1542,7 +1562,6 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs 
*engine)
  * used as a workaround for not being allowed to do lite
  * restore with HEAD==TAIL (WaIdleLiteRestore).
  */
-#define WA_TAIL_DWORDS 2
 
 static int gen8_emit_request(struct drm_i915_gem_request *request)
 {
@@ -1889,38 +1908,13 @@ static u32 intel_lr_indirect_ctx_offset(struct 
intel_engine_cs *engine)
return indirect_ctx_offset;
 }
 
-static int
-populate_lr_context(struct i915_gem_context *ctx,
-   struct drm_i915_gem_object *ctx_obj,
-   struct intel_engine_cs *engine,
-   struct 

[Intel-gfx] [CI 5/8] drm/i915: Double check hangcheck.seqno after reset

[Chris Wilson]

Check that there was not a late recovery between us declaring the GPU
hung and processing the reset. If the GPU did recover by itself, let the
request remain on the active list and see if it hangs again!

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0cae8acdf906..a89a88922448 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2589,6 +2589,9 @@ static void i915_gem_reset_engine(struct intel_engine_cs 
*engine)
return;
 
ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
+   if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
+   ring_hung = false;
+
i915_set_reset_status(request->ctx, ring_hung);
if (!ring_hung)
return;
-- 
2.9.3

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[Intel-gfx] [CI 7/8] drm/i915: Show RING registers through debugfs

[Chris Wilson]

Knowing where the RINGs are pointing is extremely useful in diagnosing
if the engines are executing the ringbuffers you expect - and igt may be
suppressing the usual method of looking in the GPU error state.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 239 
 drivers/gpu/drm/i915/intel_engine_cs.c  |  30 
 drivers/gpu/drm/i915/intel_ringbuffer.c |  16 ---
 drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +
 4 files changed, 179 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index da7141382b00..35ce21f9aa6a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -645,6 +645,23 @@ static int i915_gem_batch_pool_info(struct seq_file *m, 
void *data)
return 0;
 }
 
+static void print_request(struct seq_file *m,
+ struct drm_i915_gem_request *rq,
+ const char *prefix)
+{
+   struct pid *pid = rq->ctx->pid;
+   struct task_struct *task;
+
+   rcu_read_lock();
+   task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
+   seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
+  rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
+  jiffies_to_msecs(jiffies - rq->emitted_jiffies),
+  task ? task->comm : "",
+  task ? task->pid : -1);
+   rcu_read_unlock();
+}
+
 static int i915_gem_request_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -668,19 +685,8 @@ static int i915_gem_request_info(struct seq_file *m, void 
*data)
continue;
 
seq_printf(m, "%s requests: %d\n", engine->name, count);
-   list_for_each_entry(req, >request_list, link) {
-   struct pid *pid = req->ctx->pid;
-   struct task_struct *task;
-
-   rcu_read_lock();
-   task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
-   seq_printf(m, "%x @ %d: %s [%d]\n",
-  req->fence.seqno,
-  (int) (jiffies - req->emitted_jiffies),
-  task ? task->comm : "",
-  task ? task->pid : -1);
-   rcu_read_unlock();
-   }
+   list_for_each_entry(req, >request_list, link)
+   print_request(m, req, "");
 
any++;
}
@@ -2046,84 +2052,6 @@ static int i915_dump_lrc(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_execlists(struct seq_file *m, void *data)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   u32 status_pointer;
-   u8 read_pointer;
-   u8 write_pointer;
-   u32 status;
-   u32 ctx_id;
-   struct list_head *cursor;
-   int i, ret;
-
-   if (!i915.enable_execlists) {
-   seq_puts(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   intel_runtime_pm_get(dev_priv);
-
-   for_each_engine(engine, dev_priv) {
-   struct drm_i915_gem_request *head_req = NULL;
-   int count = 0;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
-   ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
-   seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
-  status, ctx_id);
-
-   status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
-   seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
-
-   read_pointer = GEN8_CSB_READ_PTR(status_pointer);
-   write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
-   if (read_pointer > write_pointer)
-   write_pointer += GEN8_CSB_ENTRIES;
-   seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
-  read_pointer, write_pointer);
-
-   for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
-   status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, 
i));
-   ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, 
i));
-
-   seq_printf(m, "\tStatus buffer %d: 0x%08X, context: 
%u\n",
-  i, status, ctx_id);
-   }
-
-   spin_lock_bh(>execlist_lock);
-   list_for_each(cursor, 

[Intel-gfx] [CI 8/8] drm/i915: Show waiters in i915_hangcheck_info

[Chris Wilson]

It is convenient to know what processes are waiting when looking at
hangcheck status in debugfs.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 35ce21f9aa6a..dd6348cb43b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1353,6 +1353,9 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
seq_printf(m, "Hangcheck inactive\n");
 
for_each_engine_id(engine, dev_priv, id) {
+   struct intel_breadcrumbs *b = >breadcrumbs;
+   struct rb_node *rb;
+
seq_printf(m, "%s:\n", engine->name);
seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
   engine->hangcheck.seqno,
@@ -1362,6 +1365,15 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
   yesno(intel_engine_has_waiter(engine)),
   yesno(test_bit(engine->id,
  
_priv->gpu_error.missed_irq_rings)));
+   spin_lock(>lock);
+   for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
+   struct intel_wait *w = container_of(rb, typeof(*w), 
node);
+
+   seq_printf(m, "\t%s [%d] waiting for %x\n",
+  w->tsk->comm, w->tsk->pid, w->seqno);
+   }
+   spin_unlock(>lock);
+
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
   (long long)engine->hangcheck.acthd,
   (long long)acthd[id]);
-- 
2.9.3

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[Intel-gfx] [CI 3/8] drm/i915/execlists: Move clearing submission count from reset to init

[Chris Wilson]

After a GPU reset, we want to replay our queue of requests. However, the
GPU reset clobbered the state and we only fixup the state for the guilty
request - and engines deemed innocent we try to leave untouched so that
we recover as completely as possible. However, we need to clear the sw
tracking of the ELSP ports even for innocent requests, so move the clear
to the common path of init_hw (from reset_hw).

Reported-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0ea992ba2723..936f6f63f626 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1242,8 +1242,12 @@ static int gen8_init_common_ring(struct intel_engine_cs 
*engine)
 
intel_engine_init_hangcheck(engine);
 
-   if (!execlists_elsp_idle(engine))
+   /* After a GPU reset, we may have requests to replay */
+   if (!execlists_elsp_idle(engine)) {
+   engine->execlist_port[0].count = 0;
+   engine->execlist_port[1].count = 0;
execlists_submit_ports(engine);
+   }
 
return 0;
 }
@@ -1318,10 +1322,7 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
memset([1], 0, sizeof(port[1]));
}
 
-   /* CS is stopped, and we will resubmit both ports on resume */
GEM_BUG_ON(request->ctx != port[0].request->ctx);
-   port[0].count = 0;
-   port[1].count = 0;
 
/* Reset WaIdleLiteRestore:bdw,skl as well */
request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
-- 
2.9.3

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[Intel-gfx] [CI 1/8] drm/i915: Share the computation of ring size for RING_CTL register

[Chris Wilson]

Since both legacy and execlists want to populate the RING_CTL register,
share the computation of the right bits for the ring->size. We can then
stop masking errors and explicitly forbid them during creation!

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_lrc.c| 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d44cee710f0..acc767a52d8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1605,6 +1605,7 @@ enum skl_disp_power_wells {
 #define RING_HEAD(base)_MMIO((base)+0x34)
 #define RING_START(base)   _MMIO((base)+0x38)
 #define RING_CTL(base) _MMIO((base)+0x3c)
+#define   RING_CTL_SIZE(size)  ((size) - PAGE_SIZE) /* in bytes -> pages */
 #define RING_SYNC_0(base)  _MMIO((base)+0x40)
 #define RING_SYNC_1(base)  _MMIO((base)+0x44)
 #define RING_SYNC_2(base)  _MMIO((base)+0x48)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2d8eb2eb2b72..5ede272eb4d2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1946,7 +1946,7 @@ populate_lr_context(struct i915_gem_context *ctx,
   RING_START(engine->mmio_base), 0);
ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
   RING_CTL(engine->mmio_base),
-  ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
+  RING_CTL_SIZE(ring->size) | RING_VALID);
ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
   RING_BBADDR_UDW(engine->mmio_base), 0);
ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 67ea9dd5921e..8206e2aa03c6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -585,9 +585,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
I915_WRITE_TAIL(engine, ring->tail);
(void)I915_READ_TAIL(engine);
 
-   I915_WRITE_CTL(engine,
-   ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
-   | RING_VALID);
+   I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 
/* If the head is still not zero, the ring is dead */
if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base),
@@ -1951,6 +1949,7 @@ intel_engine_create_ring(struct intel_engine_cs *engine, 
int size)
struct i915_vma *vma;
 
GEM_BUG_ON(!is_power_of_2(size));
+   GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
 
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
if (!ring)
-- 
2.9.3

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[Intel-gfx] [CI 6/8] drm/i915: Show bounds of active request in the ring on GPU hang

[Chris Wilson]

Include the position of the active request in the ring, and display that
alongside the current RING registers (on a GPU hang).

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h   | 3 +++
 drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8c66eea06bc..4613f031d127 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -788,6 +788,9 @@ struct drm_i915_error_state {
struct i915_address_space *vm;
int num_requests;
 
+   /* position of active request inside the ring */
+   u32 rq_head, rq_post, rq_tail;
+
/* our own tracking of ring head and tail */
u32 cpu_ring_head;
u32 cpu_ring_tail;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2bbab226a46c..8b85efbdfa04 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -262,8 +262,9 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,
 {
err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
err_printf(m, "  START: 0x%08x\n", ee->start);
-   err_printf(m, "  HEAD:  0x%08x\n", ee->head);
-   err_printf(m, "  TAIL:  0x%08x\n", ee->tail);
+   err_printf(m, "  HEAD:  0x%08x\n [0x%08x]", ee->head, ee->rq_head);
+   err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
+  ee->tail, ee->rq_post, ee->rq_tail);
err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
err_printf(m, "  MODE:  0x%08x\n", ee->mode);
err_printf(m, "  HWS:   0x%08x\n", ee->hws);
@@ -1230,6 +1231,10 @@ static void i915_gem_record_rings(struct 
drm_i915_private *dev_priv,
error->simulated |=
request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
 
+   ee->rq_head = request->head;
+   ee->rq_post = request->postfix;
+   ee->rq_tail = request->tail;
+
ring = request->ring;
ee->cpu_ring_head = ring->head;
ee->cpu_ring_tail = ring->tail;
-- 
2.9.3

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[Intel-gfx] [CI 4/8] drm/i915: Disable irqs across GPU reset

[Chris Wilson]

Whilst we reset the GPU, we want to prevent execlists from submitting
new work (which it does via an interrupt handler). To achieve this we
disable the irq (and drain the irq tasklet) around the reset. When we
enable it again afters, the interrupt queue should be empty and we can
reinitialise from a known state without fear of the tasklet running
concurrently.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.c | 19 +++
 drivers/gpu/drm/i915/i915_gem.c |  2 --
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c1543240e27..89d322215c84 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1728,6 +1728,21 @@ int i915_resume_switcheroo(struct drm_device *dev)
return i915_drm_resume(dev);
 }
 
+static void disable_engines_irq(struct drm_i915_private *dev_priv)
+{
+   struct intel_engine_cs *engine;
+
+   /* Ensure irq handler finishes, and not run again. */
+   disable_irq(dev_priv->drm.irq);
+   for_each_engine(engine, dev_priv)
+   tasklet_kill(>irq_tasklet);
+}
+
+static void enable_engines_irq(struct drm_i915_private *dev_priv)
+{
+   enable_irq(dev_priv->drm.irq);
+}
+
 /**
  * i915_reset - reset chip after a hang
  * @dev: drm device to reset
@@ -1761,7 +1776,11 @@ void i915_reset(struct drm_i915_private *dev_priv)
error->reset_count++;
 
pr_notice("drm/i915: Resetting chip after gpu hang\n");
+
+   disable_engines_irq(dev_priv);
ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
+   enable_engines_irq(dev_priv);
+
if (ret) {
if (ret != -ENODEV)
DRM_ERROR("Failed to reset chip: %i\n", ret);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1418c1c522cb..0cae8acdf906 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2581,8 +2581,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs 
*engine)
struct i915_gem_context *incomplete_ctx;
bool ring_hung;
 
-   /* Ensure irq handler finishes, and not run again. */
-   tasklet_kill(>irq_tasklet);
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
 
-- 
2.9.3

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Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Chris Wilson]

On Tue, Oct 04, 2016 at 09:16:06PM +0530, Praveen Paneri wrote:
> +#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \
> + && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))

Edit dev_priv->info.has_decoupled_mmio on init.

> +static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
> +  u32 reg,
> +  enum forcewake_domains fw_engine,
> +  enum decoupled_ops operation)
> +{
> + enum decoupled_power_domains dpd_engine;
> + u32 ctrl_reg_data = 0;
> +
> + dpd_engine = fw2dpd_engine[fw_engine - 1];

enum decoupled_power_domains dpd = fw2dpd_engine[fw_engine - 1];

enum decoupled_power_domain

And don't call it fw_engine. fw_domain, if you must.

> +
> + ctrl_reg_data |= reg;
> + ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
> + ctrl_reg_data |= (dpd_engine << GEN9_DECOUPLED_PD_SHIFT);
> + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
> +
> + ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
> + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
> +
> + if (wait_for_atomic((__raw_i915_read32(dev_priv,
> + GEN9_DECOUPLED_REG0_DW1) & GEN9_DECOUPLED_DW1_GO) == 0,
> + FORCEWAKE_ACK_TIMEOUT_MS))
> + DRM_ERROR("Decoupled MMIO wait timed out\n");
> +}
> +
> +static inline u32 __gen9_decoupled_mmio_read(struct drm_i915_private 
> *dev_priv,
> +  u32 reg,
> +  enum forcewake_domains fw)

__gen9_decoupeld_mmio_read32()

> +{
> + __gen9_decoupled_mmio_access(dev_priv,
> + reg,
> + fw_engine,
> + GEN9_DECOUPLED_OP_READ);

__gen9_decoupled_mmio_access(dev_priv, reg, fw, GEN9_DECOUPLED_OP_READ);

> +
> + return __raw_i915_read32(dev_priv,
> + GEN9_DECOUPLED_REG0_DW0);

Everywhere! Please be careful with alignment.

> +#define __gen9_decoupled_read(x) \
> +static u##x \
> +gen9_decoupled_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, 
> bool trace) { \
> + enum forcewake_domains fw_engine; \
> + GEN6_READ_HEADER(x); \
> + fw_engine = __fwtable_reg_read_fw_domains(offset); \
> + if (!fw_engine || !(fw_engine & ~dev_priv->uncore.fw_domains_active)) { 
> \
> + val = __raw_i915_read##x(dev_priv, reg); \
> + } else { \
> + unsigned i; \
> + u32 *ptr_data = (u32 *)  \
> + for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
> + *ptr_data = __gen9_decoupled_mmio_read(dev_priv, \
> +  offset, \
> +  fw_engine); \
> + } \
> + GEN6_READ_FOOTER; \
> +}

Reverse it,

if (domain & ~dev_priv->uncore.fw_domains_active) {
u32 *ptr = (u32 *)
unsigned i;

for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr++)
*ptr = __gen9_decoupled_mmio_read32(dev_priv, offset, 
domain);
} else {
val = __raw_i915_read##x(dev_priv, reg);
}

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9: fix DDB partitioning for multi-screen cases

[Patchwork]

== Series Details ==

Series: drm/i915/gen9: fix DDB partitioning for multi-screen cases
URL   : https://patchwork.freedesktop.org/series/13293/
State : success

== Summary ==

Series 13293v1 drm/i915/gen9: fix DDB partitioning for multi-screen cases
https://patchwork.freedesktop.org/api/1.0/series/13293/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (fi-byt-n2820)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:212  dwarn:0   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2625/

2e47fbed60d05480cfbd097c1912e6823c0310ee drm-intel-nightly: 
2016y-10m-04d-14h-08m-17s UTC integration manifest
128e9a1 drm/i915/gen9: fix DDB partitioning for multi-screen cases

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Re: [Intel-gfx] [PATCH] drm/i915/gen9: fix DDB partitioning for multi-screen cases

[Paulo Zanoni]

Em Ter, 2016-10-04 às 14:37 -0300, Paulo Zanoni escreveu:
> With the previous code we were only recomputing the DDB partitioning
> for the CRTCs included in the atomic commit, so any other active
> CRTCs
> would end up having their DDB registers zeroed. In this patch we make
> sure that the computed state starts as a copy of the current
> partitioning, and then we only zero the DDBs that we're actually
> going to recompute.
> 
> How to reproduce the bug:
>   1 - Enable the primary plane on pipe A
>   2 - Enable the primary plane on pipe B
>   3 - Enable the sprite plane on pipe A

Forgot to mention: sprite or cursor.

> 
> Step 3 will zero the DDB partitioning for pipe B since it's not
> included in the commit that enabled the sprite for pipe A.
> 
> I expect this to fix many FIFO underrun problems on gen9+.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96226
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96828
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97450
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97596
> Bugzilla: https://www.phoronix.com/scan.php?page=news_item=Intel-S
> kylake-Multi-Screen-Woes
> Cc: sta...@vger.kernel.org
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> I still have to confirm whether this closes the above bugs, but it
> certainly fixes the problem I described.
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 425544b..0c2e252 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3362,13 +3362,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
>   int num_active;
>   int id, i;
>  
> + /* Clear the partitioning for disabled planes. */
> + memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> + memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
> +
>   if (WARN_ON(!state))
>   return 0;
>  
>   if (!cstate->base.active) {
>   ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
> - memset(ddb->plane[pipe], 0, sizeof(ddb-
> >plane[pipe]));
> - memset(ddb->y_plane[pipe], 0, sizeof(ddb-
> >y_plane[pipe]));
>   return 0;
>   }
>  
> @@ -4054,6 +4056,12 @@ skl_compute_ddb(struct drm_atomic_state
> *state)
>   intel_state->wm_results.dirty_pipes = ~0;
>   }
>  
> + /*
> +  * We're not recomputing for the pipes not included in the
> commit, so
> +  * make sure we start with the current state.
> +  */
> + memcpy(ddb, _priv->wm.skl_hw.ddb, sizeof(*ddb));
> +
>   for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
>   struct intel_crtc_state *cstate;
>  
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Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Vivi, Rodrigo]

Is this still an embargoed feature? why?

With Apollolake out there we need to work to get permission to upstream
this feature already and post it to intel-gfx@lists.freedesktop.org in
order to get this merged upstream.

A decoupled version for BXT stayed in the internal for so long time and
caused so much trouble on rebase that end up removed.

So, could you please work to get this approved for upstream?

Thanks,
Rodrigo.

On Tue, 2016-10-04 at 21:16 +0530, Praveen Paneri wrote:
> Decoupled MMIO is an alternative way to access forcewake domain
> registers, which requires less cycles for a single read/write and
> avoids frequent software forcewake.
> This certainly gives advantage over the forcewake as this new
> mechanism “decouples” CPU cycles and allow them to complete even
> when GT is in a CPD (frequency change) or C6 state.
> 
> This can co-exist with forcewake and we will continue to use forcewake
> as appropriate. E.g. 64-bit register writes to avoid writing 2 dwords
> separately and land into funny situations.
> 
> v2:
> - Moved platform check out of the function and got rid of duplicate
>  functions to find out decoupled power domain (Chris)
> - Added a check for forcewake already held and skipped decoupled
>  access (Chris)
> - Skipped writing 64 bit registers through decoupled MMIO (Chris)
> 
> v3:
> - Improved commit message with more info on decoupled mmio (Tvrtko)
> - Changed decoupled operation to enum and used u32 instead of
>  uint_32 data type for register offset (Tvrtko)
> - Moved HAS_DECOUPLED_MMIO to device info (Tvrtko)
> - Added lookup table for converting fw_engine to pd_engine (Tvrtko)
> - Improved __gen9_decoupled_read and __gen9_decoupled_write routines (Tvrtko)
> 
> Signed-off-by: Zhe Wang 
> Signed-off-by: Praveen Paneri 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  18 +-
>  drivers/gpu/drm/i915/i915_pci.c |   1 +
>  drivers/gpu/drm/i915/i915_reg.h |   7 +++
>  drivers/gpu/drm/i915/intel_uncore.c | 113 
> 
>  4 files changed, 138 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f8c66ee..bfdd55a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -559,6 +559,18 @@ enum forcewake_domains {
>  #define FW_REG_READ  (1)
>  #define FW_REG_WRITE (2)
>  
> +enum decoupled_power_domains {
> + GEN9_DECOUPLED_PD_BLITTER = 0,
> + GEN9_DECOUPLED_PD_RENDER,
> + GEN9_DECOUPLED_PD_MEDIA,
> + GEN9_DECOUPLED_PD_ALL
> +};
> +
> +enum decoupled_ops {
> + GEN9_DECOUPLED_OP_WRITE = 0,
> + GEN9_DECOUPLED_OP_READ
> +};
> +
>  enum forcewake_domains
>  intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>  i915_reg_t reg, unsigned int op);
> @@ -690,7 +702,8 @@ struct intel_csr {
>   func(has_snoop) sep \
>   func(has_ddi) sep \
>   func(has_fpga_dbg) sep \
> - func(has_pooled_eu)
> + func(has_pooled_eu) sep \
> + func(has_decoupled_mmio)
>  
>  #define DEFINE_FLAG(name) u8 name:1
>  #define SEP_SEMICOLON ;
> @@ -2869,6 +2882,9 @@ struct drm_i915_cmd_table {
>  #define GT_FREQUENCY_MULTIPLIER 50
>  #define GEN9_FREQ_SCALER 3
>  
> +#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \
> + && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))
> +
>  #include "i915_trace.h"
>  
>  static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private 
> *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 31e6edd..5c56c0c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -360,6 +360,7 @@ static const struct intel_device_info intel_broxton_info 
> = {
>   .has_hw_contexts = 1,
>   .has_logical_ring_contexts = 1,
>   .has_guc = 1,
> + .has_decoupled_mmio = 1,
>   .ddb_size = 512,
>   GEN_DEFAULT_PIPEOFFSETS,
>   IVB_CURSOR_OFFSETS,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d44cee..bf7b4c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7398,6 +7398,13 @@ enum {
>  #define  SKL_FUSE_PG1_DIST_STATUS  (1<<26)
>  #define  SKL_FUSE_PG2_DIST_STATUS  (1<<25)
>  
> +/* Decoupled MMIO register pair for kernel driver */
> +#define GEN9_DECOUPLED_REG0_DW0  _MMIO(0xF00)
> +#define GEN9_DECOUPLED_REG0_DW1  _MMIO(0xF04)
> +#define GEN9_DECOUPLED_DW1_GO(1<<31)
> +#define GEN9_DECOUPLED_PD_SHIFT  28
> +#define GEN9_DECOUPLED_OP_SHIFT  24
> +
>  /* Per-pipe DDI Function Control */
>  #define _TRANS_DDI_FUNC_CTL_A0x60400
>  #define _TRANS_DDI_FUNC_CTL_B0x61400
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> 

[Intel-gfx] [PATCH] drm/i915/gen9: fix DDB partitioning for multi-screen cases

[Paulo Zanoni]

With the previous code we were only recomputing the DDB partitioning
for the CRTCs included in the atomic commit, so any other active CRTCs
would end up having their DDB registers zeroed. In this patch we make
sure that the computed state starts as a copy of the current
partitioning, and then we only zero the DDBs that we're actually
going to recompute.

How to reproduce the bug:
  1 - Enable the primary plane on pipe A
  2 - Enable the primary plane on pipe B
  3 - Enable the sprite plane on pipe A

Step 3 will zero the DDB partitioning for pipe B since it's not
included in the commit that enabled the sprite for pipe A.

I expect this to fix many FIFO underrun problems on gen9+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96226
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96828
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97450
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97596
Bugzilla: 
https://www.phoronix.com/scan.php?page=news_item=Intel-Skylake-Multi-Screen-Woes
Cc: sta...@vger.kernel.org
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

I still have to confirm whether this closes the above bugs, but it
certainly fixes the problem I described.

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 425544b..0c2e252 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3362,13 +3362,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int num_active;
int id, i;
 
+   /* Clear the partitioning for disabled planes. */
+   memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
+   memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+
if (WARN_ON(!state))
return 0;
 
if (!cstate->base.active) {
ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
-   memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-   memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
return 0;
}
 
@@ -4054,6 +4056,12 @@ skl_compute_ddb(struct drm_atomic_state *state)
intel_state->wm_results.dirty_pipes = ~0;
}
 
+   /*
+* We're not recomputing for the pipes not included in the commit, so
+* make sure we start with the current state.
+*/
+   memcpy(ddb, _priv->wm.skl_hw.ddb, sizeof(*ddb));
+
for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
struct intel_crtc_state *cstate;
 
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/bxt: Broxton decoupled MMIO (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Broxton decoupled MMIO (rev3)
URL   : https://patchwork.freedesktop.org/series/12028/
State : warning

== Summary ==

Series 12028v3 drm/i915/bxt: Broxton decoupled MMIO
https://patchwork.freedesktop.org/api/1.0/series/12028/revisions/3/mbox/

Test drv_module_reload_basic:
pass   -> DMESG-WARN (fi-bxt-t5700)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:213  dwarn:1   dfail:0   fail:0   skip:30 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2624/

2e47fbed60d05480cfbd097c1912e6823c0310ee drm-intel-nightly: 
2016y-10m-04d-14h-08m-17s UTC integration manifest
eedb511 drm/i915/bxt: Broxton decoupled MMIO

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[Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Praveen Paneri]

Decoupled MMIO is an alternative way to access forcewake domain
registers, which requires less cycles for a single read/write and
avoids frequent software forcewake.
This certainly gives advantage over the forcewake as this new
mechanism “decouples” CPU cycles and allow them to complete even
when GT is in a CPD (frequency change) or C6 state.

This can co-exist with forcewake and we will continue to use forcewake
as appropriate. E.g. 64-bit register writes to avoid writing 2 dwords
separately and land into funny situations.

v2:
- Moved platform check out of the function and got rid of duplicate
 functions to find out decoupled power domain (Chris)
- Added a check for forcewake already held and skipped decoupled
 access (Chris)
- Skipped writing 64 bit registers through decoupled MMIO (Chris)

v3:
- Improved commit message with more info on decoupled mmio (Tvrtko)
- Changed decoupled operation to enum and used u32 instead of
 uint_32 data type for register offset (Tvrtko)
- Moved HAS_DECOUPLED_MMIO to device info (Tvrtko)
- Added lookup table for converting fw_engine to pd_engine (Tvrtko)
- Improved __gen9_decoupled_read and __gen9_decoupled_write routines (Tvrtko)

Signed-off-by: Zhe Wang 
Signed-off-by: Praveen Paneri 
---
 drivers/gpu/drm/i915/i915_drv.h |  18 +-
 drivers/gpu/drm/i915/i915_pci.c |   1 +
 drivers/gpu/drm/i915/i915_reg.h |   7 +++
 drivers/gpu/drm/i915/intel_uncore.c | 113 
 4 files changed, 138 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8c66ee..bfdd55a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -559,6 +559,18 @@ enum forcewake_domains {
 #define FW_REG_READ  (1)
 #define FW_REG_WRITE (2)
 
+enum decoupled_power_domains {
+   GEN9_DECOUPLED_PD_BLITTER = 0,
+   GEN9_DECOUPLED_PD_RENDER,
+   GEN9_DECOUPLED_PD_MEDIA,
+   GEN9_DECOUPLED_PD_ALL
+};
+
+enum decoupled_ops {
+   GEN9_DECOUPLED_OP_WRITE = 0,
+   GEN9_DECOUPLED_OP_READ
+};
+
 enum forcewake_domains
 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
   i915_reg_t reg, unsigned int op);
@@ -690,7 +702,8 @@ struct intel_csr {
func(has_snoop) sep \
func(has_ddi) sep \
func(has_fpga_dbg) sep \
-   func(has_pooled_eu)
+   func(has_pooled_eu) sep \
+   func(has_decoupled_mmio)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -2869,6 +2882,9 @@ struct drm_i915_cmd_table {
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
+#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \
+   && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))
+
 #include "i915_trace.h"
 
 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 31e6edd..5c56c0c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -360,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+   .has_decoupled_mmio = 1,
.ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d44cee..bf7b4c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7398,6 +7398,13 @@ enum {
 #define  SKL_FUSE_PG1_DIST_STATUS  (1<<26)
 #define  SKL_FUSE_PG2_DIST_STATUS  (1<<25)
 
+/* Decoupled MMIO register pair for kernel driver */
+#define GEN9_DECOUPLED_REG0_DW0_MMIO(0xF00)
+#define GEN9_DECOUPLED_REG0_DW1_MMIO(0xF04)
+#define GEN9_DECOUPLED_DW1_GO  (1<<31)
+#define GEN9_DECOUPLED_PD_SHIFT28
+#define GEN9_DECOUPLED_OP_SHIFT24
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A  0x60400
 #define _TRANS_DDI_FUNC_CTL_B  0x61400
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index e2b188d..0af602e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -831,6 +831,72 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
__unclaimed_reg_debug(dev_priv, reg, read, before);
 }
 
+static const enum decoupled_power_domains fw2dpd_engine[] = {
+   GEN9_DECOUPLED_PD_RENDER,
+   GEN9_DECOUPLED_PD_BLITTER,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_MEDIA,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_ALL
+};
+
+/*
+ * Decoupled MMIO access for only 1 DWORD
+ */
+static void __gen9_decoupled_mmio_access(struct drm_i915_private 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gtt: Split 
gen8_ppgtt_clear_pte_range
URL   : https://patchwork.freedesktop.org/series/13282/
State : failure

== Summary ==

Series 13282v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13282/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-bsw-n3050)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2623/

cedbdecff4c878309133e066f696ea63d41cee73 drm-intel-nightly: 
2016y-10m-04d-10h-53m-20s UTC integration manifest
02532d3 drm/i915: Remove unused "valid" parameter from pte_encode
945d61e drm/i915/gtt: Free unused lower-level page tables
22b7a6e drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

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[Intel-gfx] [PATCH] aubdump: add --command option to stream aubdump to another program

[Lionel Landwerlin]

This comes handy if you want to look at your application output without
having to save it into a file. For example, use this with aubinator from
Mesa :

$ intel_aubdump -c '/path/to/aubinator --gen=hsw' my_gl_app

Signed-off-by: Lionel Landwerlin 
Cc: Kristian Høgsberg 
---
 tools/aubdump.c| 101 +++--
 tools/intel_aubdump.in |  26 -
 2 files changed, 106 insertions(+), 21 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index 30dc742..5c0e2bb 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -50,6 +50,7 @@ static int (*libc_close)(int fd) = close_init_helper;
 static int (*libc_ioctl)(int fd, unsigned long request, ...) = 
ioctl_init_helper;
 
 static int drm_fd = -1;
+static char *command;
 static char *filename;
 static FILE *file;
 static int gen = 0;
@@ -113,6 +114,76 @@ fail_if(int cond, const char *format, ...)
raise(SIGTRAP);
 }
 
+static FILE *
+launch_command(void)
+{
+   int i = 0, fds[2];
+   char **args = calloc(strlen(command), sizeof(char *));
+   char *iter = command;
+
+   args[i++] = iter = command;
+
+   while ((iter = strstr(iter, ",")) != NULL) {
+   *iter = '\0';
+   iter += 1;
+   args[i++] = iter;
+   }
+
+   if (pipe(fds) == -1)
+   return NULL;
+
+   switch (fork()) {
+   case 0:
+   dup2(fds[0], 0);
+   fail_if(execv(args[0], args) == -1,
+   "intel_aubdump: fail to launch child command\n");
+   return NULL;
+
+   default:
+   free(args);
+   return fdopen(fds[1], "w");
+
+   case -1:
+   return NULL;
+   }
+}
+
+static void
+maybe_init_output(void)
+{
+   const char *args;
+   static bool initialized = false;
+   int nb_args;
+
+   if (initialized)
+   return;
+
+   args = getenv("INTEL_AUBDUMP_ARGS");
+
+   nb_args = sscanf(args, 
"verbose=%d;file=%m[^;];device=%i;command=%m[^;];",
+, , , );
+   fail_if(nb_args != 4, "intel_aubdump: invalid number of arguments");
+fail_if(filename == NULL || command == NULL,
+"intel_aubdump: out of memory\n");
+   if (device)
+   device_override = true;
+
+   bos = malloc(MAX_BO_COUNT * sizeof(bos[0]));
+   fail_if(bos == NULL, "intel_aubdump: out of memory\n");
+
+if (strlen(command) != 0) {
+  file = launch_command();
+  fail_if(file == NULL,
+  "intel_aubdump: failed to launch command '%s'\n", command);
+} else {
+  file = fopen(filename, "w+");
+  fail_if(file == NULL,
+  "intel_aubdump: failed to open file '%s'\n", filename);
+}
+
+   initialized = true;
+}
+
 static struct bo *
 get_bo(uint32_t handle)
 {
@@ -140,13 +211,18 @@ align_u64(uint64_t v, uint64_t a)
 static void
 dword_out(uint32_t data)
 {
-   fwrite(, 1, 4, file);
+   fail_if(fwrite(, 1, 4, file) == 0,
+   "Writing to output failed\n");
 }
 
 static void
 data_out(const void *data, size_t size)
 {
-   fwrite(data, 1, size, file);
+   if (size == 0)
+   return;
+
+   fail_if(fwrite(data, 1, size, file) == 0,
+   "Writing to output failed\n");
 }
 
 static void
@@ -447,6 +523,8 @@ ioctl(int fd, unsigned long request, ...)
}
 
if (fd == drm_fd) {
+   maybe_init_output();
+
switch (request) {
case DRM_IOCTL_I915_GETPARAM: {
struct drm_i915_getparam *getparam = argp;
@@ -550,26 +628,8 @@ ioctl(int fd, unsigned long request, ...)
 static void
 init(void)
 {
-   const char *args = getenv("INTEL_AUBDUMP_ARGS");
-
libc_close = dlsym(RTLD_NEXT, "close");
libc_ioctl = dlsym(RTLD_NEXT, "ioctl");
-   fail_if(libc_close == NULL || libc_ioctl == NULL,
-   "intel_aubdump: failed to get libc ioctl or close\n");
-
-   if (sscanf(args, "verbose=%d;file=%m[^;];device=%i",
-  , , ) != 3)
-   filename = strdup("intel.aub");
-   fail_if(filename == NULL, "intel_aubdump: out of memory\n");
-
-   if (device)
-   device_override = true;
-
-   bos = malloc(MAX_BO_COUNT * sizeof(bos[0]));
-   fail_if(bos == NULL, "intel_aubdump: out of memory\n");
-
-   file = fopen(filename, "w+");
-   fail_if(file == NULL, "intel_aubdump: failed to open file '%s'\n", 
filename);
 }
 
 static int
@@ -596,6 +656,7 @@ ioctl_init_helper(int fd, unsigned long request, ...)
 static void __attribute__ ((destructor))
 fini(void)
 {
+   free(command);
free(filename);
if (file)
fclose(file);
diff --git a/tools/intel_aubdump.in b/tools/intel_aubdump.in
index 3666b6e..2357e9b 100644
--- a/tools/intel_aubdump.in
+++ 

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Jani Nikula]

On Tue, 04 Oct 2016, Joonas Lahtinen  wrote:
> Get rid of SEP_SEMICOLON and SEP_BLANK in DEV_INFO_FOR_EACH_FLAG.
>
> Signed-off-by: Joonas Lahtinen 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  6 +-
>  drivers/gpu/drm/i915/i915_drv.h  | 98 
> +++-
>  drivers/gpu/drm/i915/i915_gpu_error.c|  6 +-
>  drivers/gpu/drm/i915/intel_device_info.c | 11 ++--
>  4 files changed, 55 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 4fb9d82..4119235 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -68,11 +68,9 @@ static int i915_capabilities(struct seq_file *m, void 
> *data)
>  
>   seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
>   seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
> -#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
> -#define SEP_SEMICOLON ;
> - DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
> +#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x));
> + DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG)

NAK.

Leaving out the semicolon throws off a bunch of editor autoidenting
stuff. And is aesthetically displeasing.

BR,
Jani.


>  #undef PRINT_FLAG
> -#undef SEP_SEMICOLON
>  
>   return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 91ff3d7..f13b958 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -634,55 +634,52 @@ struct intel_csr {
>   uint32_t allowed_dc_mask;
>  };
>  
> -#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
> - func(is_mobile) sep \
> - func(is_i85x) sep \
> - func(is_i915g) sep \
> - func(is_i945gm) sep \
> - func(is_g33) sep \
> - func(hws_needs_physical) sep \
> - func(is_g4x) sep \
> - func(is_pineview) sep \
> - func(is_broadwater) sep \
> - func(is_crestline) sep \
> - func(is_ivybridge) sep \
> - func(is_valleyview) sep \
> - func(is_cherryview) sep \
> - func(is_haswell) sep \
> - func(is_broadwell) sep \
> - func(is_skylake) sep \
> - func(is_broxton) sep \
> - func(is_kabylake) sep \
> - func(is_preliminary) sep \
> - func(has_fbc) sep \
> - func(has_psr) sep \
> - func(has_runtime_pm) sep \
> - func(has_csr) sep \
> - func(has_resource_streamer) sep \
> - func(has_rc6) sep \
> - func(has_rc6p) sep \
> - func(has_dp_mst) sep \
> - func(has_gmbus_irq) sep \
> - func(has_hw_contexts) sep \
> - func(has_logical_ring_contexts) sep \
> - func(has_l3_dpf) sep \
> - func(has_gmch_display) sep \
> - func(has_guc) sep \
> - func(has_pipe_cxsr) sep \
> - func(has_hotplug) sep \
> - func(cursor_needs_physical) sep \
> - func(has_overlay) sep \
> - func(overlay_needs_physical) sep \
> - func(supports_tv) sep \
> - func(has_llc) sep \
> - func(has_snoop) sep \
> - func(has_ddi) sep \
> - func(has_fpga_dbg) sep \
> +#define DEV_INFO_FOR_EACH_FLAG(func) \
> + func(is_mobile) \
> + func(is_i85x) \
> + func(is_i915g) \
> + func(is_i945gm) \
> + func(is_g33) \
> + func(hws_needs_physical) \
> + func(is_g4x) \
> + func(is_pineview) \
> + func(is_broadwater) \
> + func(is_crestline) \
> + func(is_ivybridge) \
> + func(is_valleyview) \
> + func(is_cherryview) \
> + func(is_haswell) \
> + func(is_broadwell) \
> + func(is_skylake) \
> + func(is_broxton) \
> + func(is_kabylake) \
> + func(is_preliminary) \
> + func(has_fbc) \
> + func(has_psr) \
> + func(has_runtime_pm) \
> + func(has_csr) \
> + func(has_resource_streamer) \
> + func(has_rc6) \
> + func(has_rc6p) \
> + func(has_dp_mst) \
> + func(has_gmbus_irq) \
> + func(has_hw_contexts) \
> + func(has_logical_ring_contexts) \
> + func(has_l3_dpf) \
> + func(has_gmch_display) \
> + func(has_guc) \
> + func(has_pipe_cxsr) \
> + func(has_hotplug) \
> + func(cursor_needs_physical) \
> + func(has_overlay) \
> + func(overlay_needs_physical) \
> + func(supports_tv) \
> + func(has_llc) \
> + func(has_snoop) \
> + func(has_ddi) \
> + func(has_fpga_dbg) \
>   func(has_pooled_eu)
>  
> -#define DEFINE_FLAG(name) u8 name:1
> -#define SEP_SEMICOLON ;
> -
>  struct sseu_dev_info {
>   u8 slice_mask;
>   u8 subslice_mask;
> @@ -710,7 +707,9 @@ struct intel_device_info {
>   u16 gen_mask;
>   u8 ring_mask; /* Rings supported by the HW */
>   u8 num_rings;
> - DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> +#define DEFINE_FLAG(name) u8 name:1;
> + DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG)
> +#undef DEFINE_FLAG
>   u16 ddb_size; /* in blocks */
>   /* Register offsets for the various display pipes and 

[Intel-gfx] [PATCH 2/3] drm/i915/gtt: Free unused lower-level page tables

[Michał Winiarski]

Since "Dynamic page table allocations" were introduced, our page tables
can grow (being dynamically allocated) with address space range usage.
Unfortunately, their lifetime is bound to vm. This is not a huge problem
when we're not using softpin - drm_mm is creating an upper bound on used
range by causing addresses for our VMAs to eventually be reused.

With softpin, long lived contexts can drain the system out of memory
even with a single "small" object. For example:

bo = bo_alloc(size);
while(true)
offset += size;
exec(bo, offset);

Will cause us to create new allocations until all memory in the system
is used for tracking GPU pages (even though almost all PTEs in this vm
are pointing to scratch).

Let's free unused page tables in clear_range to prevent this - if no
entries are used, we can safely free it and return this information to
the caller (so that higher-level entry is pointing to scratch).

Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 103 ++--
 1 file changed, 88 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6086122..281e349 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -218,9 +218,10 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 }
 
 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
- const enum i915_cache_level level)
+ const enum i915_cache_level level,
+ bool valid)
 {
-   gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+   gen8_pde_t pde = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
pde |= addr;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE_INDEX;
@@ -532,7 +533,8 @@ static void gen8_initialize_pd(struct i915_address_space 
*vm,
 {
gen8_pde_t scratch_pde;
 
-   scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
+   scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC,
+ true);
 
fill_px(vm->dev, pd, scratch_pde);
 }
@@ -613,7 +615,8 @@ static void gen8_initialize_pdp(struct i915_address_space 
*vm,
 {
gen8_ppgtt_pdpe_t scratch_pdpe;
 
-   scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
+   scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC,
+   true);
 
fill_px(vm->dev, pdp, scratch_pdpe);
 }
@@ -624,7 +627,7 @@ static void gen8_initialize_pml4(struct i915_address_space 
*vm,
gen8_ppgtt_pml4e_t scratch_pml4e;
 
scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
- I915_CACHE_LLC);
+ I915_CACHE_LLC, true);
 
fill_px(vm->dev, pml4, scratch_pml4e);
 }
@@ -641,7 +644,8 @@ gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
return;
 
page_directorypo = kmap_px(pdp);
-   page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
+   page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC,
+  true);
kunmap_px(ppgtt, page_directorypo);
 }
 
@@ -654,7 +658,7 @@ gen8_setup_page_directory_pointer(struct i915_hw_ppgtt 
*ppgtt,
gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 
WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
-   pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
+   pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC, true);
kunmap_px(ppgtt, pagemap);
 }
 
@@ -706,7 +710,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(>pml4));
 }
 
-static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
uint64_t start,
uint64_t length,
@@ -724,50 +728,102 @@ static void gen8_ppgtt_clear_pt(struct 
i915_address_space *vm,
 I915_CACHE_LLC, use_scratch);
 
if (WARN_ON(!px_page(pt)))
-   return;
+   return false;
 
bitmap_clear(pt->used_ptes, pte_start, num_entries);
 
+   if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
+   free_pt(vm->dev, pt);
+   return true;
+   }
+
pt_vaddr = kmap_px(pt);
 
for (pte = pte_start; pte < num_entries; pte++)
pt_vaddr[pte] = scratch_pte;
 
   

[Intel-gfx] [PATCH 1/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

[Michał Winiarski]

Let's use more top-down approach, where each gen8_ppgtt_clear_* function
is responsible for clearing the struct passed as an argument and calling
relevant clear_range functions on lower-level tables.
Doing this rather than operating on PTE ranges makes the implementation
of shrinking page tables quite simple.

Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 115 +---
 1 file changed, 66 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bb4232..6086122 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -706,59 +706,84 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(>pml4));
 }
 
-static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
-  struct i915_page_directory_pointer *pdp,
-  uint64_t start,
-  uint64_t length,
-  gen8_pte_t scratch_pte)
+static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+   struct i915_page_table *pt,
+   uint64_t start,
+   uint64_t length,
+   bool use_scratch)
 {
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+   unsigned int pte_start = gen8_pte_index(start);
+   unsigned int num_entries = min(gen8_pte_count(start, length),
+  GEN8_PTES);
+   uint64_t pte;
+
gen8_pte_t *pt_vaddr;
-   unsigned pdpe = gen8_pdpe_index(start);
-   unsigned pde = gen8_pde_index(start);
-   unsigned pte = gen8_pte_index(start);
-   unsigned num_entries = length >> PAGE_SHIFT;
-   unsigned last_pte, i;
+   gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
+I915_CACHE_LLC, use_scratch);
 
-   if (WARN_ON(!pdp))
+   if (WARN_ON(!px_page(pt)))
return;
 
-   while (num_entries) {
-   struct i915_page_directory *pd;
-   struct i915_page_table *pt;
+   bitmap_clear(pt->used_ptes, pte_start, num_entries);
 
-   if (WARN_ON(!pdp->page_directory[pdpe]))
-   break;
+   pt_vaddr = kmap_px(pt);
 
-   pd = pdp->page_directory[pdpe];
+   for (pte = pte_start; pte < num_entries; pte++)
+   pt_vaddr[pte] = scratch_pte;
 
+   kunmap_px(ppgtt, pt_vaddr);
+}
+
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+   struct i915_page_directory *pd,
+   uint64_t start,
+   uint64_t length,
+   bool use_scratch)
+{
+   struct i915_page_table *pt;
+   uint64_t pde;
+
+   gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
 
-   pt = pd->page_table[pde];
+   gen8_ppgtt_clear_pt(vm, pt, start, length, use_scratch);
+   }
+}
 
-   if (WARN_ON(!px_page(pt)))
-   break;
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+struct i915_page_directory_pointer *pdp,
+uint64_t start,
+uint64_t length,
+bool use_scratch)
+{
+   struct i915_page_directory *pd;
+   uint64_t pdpe;
 
-   last_pte = pte + num_entries;
-   if (last_pte > GEN8_PTES)
-   last_pte = GEN8_PTES;
+   gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
+   if (WARN_ON(!pdp->page_directory[pdpe]))
+   break;
 
-   pt_vaddr = kmap_px(pt);
+   gen8_ppgtt_clear_pd(vm, pd, start, length, use_scratch);
+   }
+}
 
-   for (i = pte; i < last_pte; i++) {
-   pt_vaddr[i] = scratch_pte;
-   num_entries--;
-   }
+static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm,
+ struct i915_pml4 *pml4,
+ uint64_t start,
+ uint64_t length,
+ bool use_scratch)
+{
+   struct i915_page_directory_pointer *pdp;
+   uint64_t pml4e;
 
-   kunmap_px(ppgtt, pt_vaddr);
+   gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
+   if 

[Intel-gfx] [PATCH 3/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Michał Winiarski]

We're no longer using any invalid PTEs - everything that's not used
should be pointing to scratch.

Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem.c|   6 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c| 154 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.h|   5 +-
 4 files changed, 65 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1418c1c..b344340 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -919,8 +919,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(>base,
-  node.start, node.size,
-  true);
+  node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node();
} else {
@@ -1228,8 +1227,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(>base,
-  node.start, node.size,
-  true);
+  node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node();
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 33c8522..54b091b 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -370,8 +370,7 @@ static void reloc_cache_fini(struct reloc_cache *cache)
 
ggtt->base.clear_range(>base,
   cache->node.start,
-  cache->node.size,
-  true);
+  cache->node.size);
drm_mm_remove_node(>node);
} else {
i915_vma_unpin((struct i915_vma *)cache->node.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 281e349..fa78bb1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -191,15 +191,13 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
 {
vma->vm->clear_range(vma->vm,
 vma->node.start,
-vma->size,
-true);
+vma->size);
 }
 
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- bool valid)
+ enum i915_cache_level level)
 {
-   gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+   gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
pte |= addr;
 
switch (level) {
@@ -218,10 +216,9 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 }
 
 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
- const enum i915_cache_level level,
- bool valid)
+ const enum i915_cache_level level)
 {
-   gen8_pde_t pde = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+   gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
pde |= addr;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE_INDEX;
@@ -235,9 +232,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 
 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
 {
-   gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+   gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
switch (level) {
@@ -257,9 +254,9 @@ static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 
 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
 {
-   gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+   gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
switch (level) {
@@ -281,9 +278,9 @@ static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 
 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 flags)
+   

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Reduce trickery in 
DEV_INFO_FOR_EACH_FLAG
URL   : https://patchwork.freedesktop.org/series/13278/
State : warning

== Summary ==

Series 13278v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13278/revisions/1/mbox/

Test drv_module_reload_basic:
pass   -> SKIP   (fi-snb-2520m)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:212  dwarn:0   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:181  dwarn:1   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2622/

cedbdecff4c878309133e066f696ea63d41cee73 drm-intel-nightly: 
2016y-10m-04d-10h-53m-20s UTC integration manifest
b1a39fa drm/i915: Sort DEV_INFO_FOR_EACH_FLAG
dcd5eeb drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Chris Wilson]

On Tue, Oct 04, 2016 at 03:42:58PM +0300, Joonas Lahtinen wrote:
> Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).
> 
> Signed-off-by: Joonas Lahtinen 

Ok. Looks like it should be easier to read.
Reviewed-by: Chris Wilson 

Could you add something like:

/* Keep is_* in chronological order */

/* Keep has_* in alphabetical order */
...
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

[Lyude]

Reviewed-by: Lyude 

On Tue, 2016-10-04 at 12:29 +0300, Jani Nikula wrote:
> Fix sparse warning:
> 
> drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol
> 'skl_ddb_add_affected_planes' was not declared. Should it be static?
> 
> Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually
> affected by ddb changes")
> Cc: Lyude 
> Cc: Paulo Zanoni 
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> Please run sparse on your patches, please run sparse before you push.
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 425544b1f733..7f1748a1e614 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3966,7 +3966,7 @@ pipes_modified(struct drm_atomic_state *state)
>   return ret;
>  }
>  
> -int
> +static int
>  skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
>  {
>   struct drm_atomic_state *state = cstate->base.state;
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[Intel-gfx] ✗ Fi.CI.BAT: warning for Shared DPLL kernel doc and improvements

[Patchwork]

== Series Details ==

Series: Shared DPLL kernel doc and improvements
URL   : https://patchwork.freedesktop.org/series/13277/
State : warning

== Summary ==

Series 13277v1 Shared DPLL kernel doc and improvements
https://patchwork.freedesktop.org/api/1.0/series/13277/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass   -> DMESG-WARN (fi-skl-6770hq)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:218  dwarn:2   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:227  dwarn:2   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2621/

cedbdecff4c878309133e066f696ea63d41cee73 drm-intel-nightly: 
2016y-10m-04d-10h-53m-20s UTC integration manifest
1ffe86b drm/i915: Add entrypoints for mapping dplls to encoders and crtcs
1d399a4 drm/i915: Add dpll entrypoint for dumping hw state
60e1afa drm/i915: Update kerneldoc for intel_dpll_mgr.c
d45c74f drm/i915: Rename intel_shared_dpll->mode_set() to prepare()
33dd291 drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state
bb39d86 drm/i915: Rename intel_shared_dpll_commit() to _swap_state()
ddec815 drm/i915: Introduce intel_release_shared_dpll()

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Chris Wilson]

On Tue, Oct 04, 2016 at 03:42:57PM +0300, Joonas Lahtinen wrote:
>  #define PRINT_S(name) "%s"
> -#define SEP_EMPTY
> -#define PRINT_FLAG(name) info->name ? #name "," : ""
> -#define SEP_COMMA ,
> +#define PRINT_FLAG(name) info->name ? #name "," : "",
>   DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x 
> flags="
> -  DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
> +  DEV_INFO_FOR_EACH_FLAG(PRINT_S) "%s",
>info->gen,
>dev_priv->drm.pdev->device,
>dev_priv->drm.pdev->revision,
> -  DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
> +  DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG)
> +  "");

Why did we need the trailing fmt + arg? Oh. PRINT_FLAG has the trailing
'.' so needs a sentinel.

Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

[Mika Kuoppala]

Chris Wilson  writes:

> Signed-off-by: Chris Wilson 

With commit message stating the obvious added,

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9c95ce73f2aa..39b76c24c84f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1343,6 +1343,9 @@ static int i915_hangcheck_info(struct seq_file *m, void 
> *unused)
>   seq_printf(m, "Hangcheck inactive\n");
>  
>   for_each_engine_id(engine, dev_priv, id) {
> + struct intel_breadcrumbs *b = >breadcrumbs;
> + struct rb_node *rb;
> +
>   seq_printf(m, "%s:\n", engine->name);
>   seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
>  engine->hangcheck.seqno,
> @@ -1352,6 +1355,15 @@ static int i915_hangcheck_info(struct seq_file *m, 
> void *unused)
>  yesno(intel_engine_has_waiter(engine)),
>  yesno(test_bit(engine->id,
> 
> _priv->gpu_error.missed_irq_rings)));
> + spin_lock(>lock);
> + for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
> + struct intel_wait *w = container_of(rb, typeof(*w), 
> node);
> +
> + seq_printf(m, "\t%s [%d] waiting for %x\n",
> +w->tsk->comm, w->tsk->pid, w->seqno);
> + }
> + spin_unlock(>lock);
> +
>   seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
>  (long long)engine->hangcheck.acthd,
>  (long long)acthd[id]);
> -- 
> 2.9.3
>
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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Show RING registers through debugfs

[Chris Wilson]

On Tue, Oct 04, 2016 at 03:35:20PM +0300, Mika Kuoppala wrote:
> Chris Wilson  writes:
> > +   rcu_read_unlock();
> > +
> > +   addr = intel_engine_get_active_head(engine);
> > +   seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
> > +  upper_32_bits(addr), lower_32_bits(addr));
> > +   addr = intel_engine_get_last_batch_head(engine);
> > +   seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
> > +  upper_32_bits(addr), lower_32_bits(addr));
> > +
> > +   if (i915.enable_execlists) {
> > +   u32 ptr, read, write;
> >
> 
> Ok, in here I am thinking that the requests in ports would be intresting
> also. But it seems impossible to sample the ports without taking
> locks. And we don't want to go there.

It's even worse than that. execlist_port[] are entirely unlocked and
only updated by the sole owner. However... We can read them under the
rcu guarantee that the requests themselves will not disappear (with the
exception that the contents may be reallocated - but not explode!).
-Chris

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

[Chris Wilson]

On Tue, Oct 04, 2016 at 03:41:24PM +0300, Mika Kuoppala wrote:
> Chris Wilson  writes:
> 
> The commit message is missing.
> 
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 9c95ce73f2aa..39b76c24c84f 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1343,6 +1343,9 @@ static int i915_hangcheck_info(struct seq_file *m, 
> > void *unused)
> > seq_printf(m, "Hangcheck inactive\n");
> >  
> > for_each_engine_id(engine, dev_priv, id) {
> > +   struct intel_breadcrumbs *b = >breadcrumbs;
> > +   struct rb_node *rb;
> > +
> > seq_printf(m, "%s:\n", engine->name);
> > seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
> >engine->hangcheck.seqno,
> > @@ -1352,6 +1355,15 @@ static int i915_hangcheck_info(struct seq_file *m, 
> > void *unused)
> >yesno(intel_engine_has_waiter(engine)),
> >yesno(test_bit(engine->id,
> >   
> > _priv->gpu_error.missed_irq_rings)));
> > +   spin_lock(>lock);
> > +   for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
> 
> The waiters are embeddded in requests? So we need the rcu_read_lock?

spin_lock outweighs rcu_read_lock, but the waiters are in a separate
per-engine list guarded by the breadcrumbs.lock, we need the spin lock
here.
-Chris

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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Share the computation of ring size for RING_CTL register

[Mika Kuoppala]

Chris Wilson  writes:

> On Mon, Oct 03, 2016 at 01:52:39PM +0100, Chris Wilson wrote:
>> Since both legacy and execlists want to poopulate the RING_CTL register,
>> share the computation of the right bits for the ring->size. We can then
>> stop masking errors and explicitly forbid them during creation!
>> 
>> Signed-off-by: Chris Wilson 
>> Cc: Mika Kuoppala 
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>>  drivers/gpu/drm/i915/intel_lrc.c| 2 +-
>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
>>  3 files changed, 4 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 8d44cee710f0..acc767a52d8e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1605,6 +1605,7 @@ enum skl_disp_power_wells {
>>  #define RING_HEAD(base) _MMIO((base)+0x34)
>>  #define RING_START(base)_MMIO((base)+0x38)
>>  #define RING_CTL(base)  _MMIO((base)+0x3c)
>> +#define   RING_CTL_SIZE(size)   ((size) - PAGE_SIZE) /* in bytes -> 
>> pages */
>>  #define RING_SYNC_0(base)   _MMIO((base)+0x40)
>>  #define RING_SYNC_1(base)   _MMIO((base)+0x44)
>>  #define RING_SYNC_2(base)   _MMIO((base)+0x48)
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index 2d8eb2eb2b72..5ede272eb4d2 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1946,7 +1946,7 @@ populate_lr_context(struct i915_gem_context *ctx,
>> RING_START(engine->mmio_base), 0);
>>  ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
>> RING_CTL(engine->mmio_base),
>> -   ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
>> +   RING_CTL_SIZE(ring->size) | RING_VALID);
>>  ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
>> RING_BBADDR_UDW(engine->mmio_base), 0);
>>  ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 67ea9dd5921e..26aa4c5e268f 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -585,9 +585,7 @@ static int init_ring_common(struct intel_engine_cs 
>> *engine)
>>  I915_WRITE_TAIL(engine, ring->tail);
>>  (void)I915_READ_TAIL(engine);
>>  
>> -I915_WRITE_CTL(engine,
>> -((ring->size - PAGE_SIZE) & RING_NR_PAGES)
>> -| RING_VALID);
>> +I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
>>  
>>  /* If the head is still not zero, the ring is dead */
>>  if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base),
>> @@ -1951,6 +1949,7 @@ intel_engine_create_ring(struct intel_engine_cs 
>> *engine, int size)
>>  struct i915_vma *vma;
>>  
>>  GEM_BUG_ON(!is_power_of_2(size));
>> +GEM_BUG_ON(size & ~RING_NR_PAGES);
>
> (size - PAGE_SIZE) & ~RING_NR_PAGES

Oops. Or even RING_CTL_SIZE(size) & ~RING_NR_PAGES.

-Mika

> -Chris
>
> -- 
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[Intel-gfx] [PATCH 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).

Signed-off-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f13b958..2ce1171 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -640,7 +640,6 @@ struct intel_csr {
func(is_i915g) \
func(is_i945gm) \
func(is_g33) \
-   func(hws_needs_physical) \
func(is_g4x) \
func(is_pineview) \
func(is_broadwater) \
@@ -654,31 +653,32 @@ struct intel_csr {
func(is_broxton) \
func(is_kabylake) \
func(is_preliminary) \
-   func(has_fbc) \
-   func(has_psr) \
-   func(has_runtime_pm) \
func(has_csr) \
-   func(has_resource_streamer) \
-   func(has_rc6) \
-   func(has_rc6p) \
+   func(has_ddi) \
func(has_dp_mst) \
+   func(has_fbc) \
+   func(has_fpga_dbg) \
func(has_gmbus_irq) \
-   func(has_hw_contexts) \
-   func(has_logical_ring_contexts) \
-   func(has_l3_dpf) \
func(has_gmch_display) \
func(has_guc) \
-   func(has_pipe_cxsr) \
func(has_hotplug) \
-   func(cursor_needs_physical) \
-   func(has_overlay) \
-   func(overlay_needs_physical) \
-   func(supports_tv) \
+   func(has_hw_contexts) \
+   func(has_l3_dpf) \
func(has_llc) \
+   func(has_logical_ring_contexts) \
+   func(has_overlay) \
+   func(has_pipe_cxsr) \
+   func(has_pooled_eu) \
+   func(has_psr) \
+   func(has_rc6) \
+   func(has_rc6p) \
+   func(has_resource_streamer) \
+   func(has_runtime_pm) \
func(has_snoop) \
-   func(has_ddi) \
-   func(has_fpga_dbg) \
-   func(has_pooled_eu)
+   func(hws_needs_physical) \
+   func(cursor_needs_physical) \
+   func(overlay_needs_physical) \
+   func(supports_tv)
 
 struct sseu_dev_info {
u8 slice_mask;
-- 
2.7.4

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[Intel-gfx] [PATCH 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

Get rid of SEP_SEMICOLON and SEP_BLANK in DEV_INFO_FOR_EACH_FLAG.

Signed-off-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 +-
 drivers/gpu/drm/i915/i915_drv.h  | 98 +++-
 drivers/gpu/drm/i915/i915_gpu_error.c|  6 +-
 drivers/gpu/drm/i915/intel_device_info.c | 11 ++--
 4 files changed, 55 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4fb9d82..4119235 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -68,11 +68,9 @@ static int i915_capabilities(struct seq_file *m, void *data)
 
seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
-#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
-#define SEP_SEMICOLON ;
-   DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
+#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x));
+   DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG)
 #undef PRINT_FLAG
-#undef SEP_SEMICOLON
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ff3d7..f13b958 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -634,55 +634,52 @@ struct intel_csr {
uint32_t allowed_dc_mask;
 };
 
-#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
-   func(is_mobile) sep \
-   func(is_i85x) sep \
-   func(is_i915g) sep \
-   func(is_i945gm) sep \
-   func(is_g33) sep \
-   func(hws_needs_physical) sep \
-   func(is_g4x) sep \
-   func(is_pineview) sep \
-   func(is_broadwater) sep \
-   func(is_crestline) sep \
-   func(is_ivybridge) sep \
-   func(is_valleyview) sep \
-   func(is_cherryview) sep \
-   func(is_haswell) sep \
-   func(is_broadwell) sep \
-   func(is_skylake) sep \
-   func(is_broxton) sep \
-   func(is_kabylake) sep \
-   func(is_preliminary) sep \
-   func(has_fbc) sep \
-   func(has_psr) sep \
-   func(has_runtime_pm) sep \
-   func(has_csr) sep \
-   func(has_resource_streamer) sep \
-   func(has_rc6) sep \
-   func(has_rc6p) sep \
-   func(has_dp_mst) sep \
-   func(has_gmbus_irq) sep \
-   func(has_hw_contexts) sep \
-   func(has_logical_ring_contexts) sep \
-   func(has_l3_dpf) sep \
-   func(has_gmch_display) sep \
-   func(has_guc) sep \
-   func(has_pipe_cxsr) sep \
-   func(has_hotplug) sep \
-   func(cursor_needs_physical) sep \
-   func(has_overlay) sep \
-   func(overlay_needs_physical) sep \
-   func(supports_tv) sep \
-   func(has_llc) sep \
-   func(has_snoop) sep \
-   func(has_ddi) sep \
-   func(has_fpga_dbg) sep \
+#define DEV_INFO_FOR_EACH_FLAG(func) \
+   func(is_mobile) \
+   func(is_i85x) \
+   func(is_i915g) \
+   func(is_i945gm) \
+   func(is_g33) \
+   func(hws_needs_physical) \
+   func(is_g4x) \
+   func(is_pineview) \
+   func(is_broadwater) \
+   func(is_crestline) \
+   func(is_ivybridge) \
+   func(is_valleyview) \
+   func(is_cherryview) \
+   func(is_haswell) \
+   func(is_broadwell) \
+   func(is_skylake) \
+   func(is_broxton) \
+   func(is_kabylake) \
+   func(is_preliminary) \
+   func(has_fbc) \
+   func(has_psr) \
+   func(has_runtime_pm) \
+   func(has_csr) \
+   func(has_resource_streamer) \
+   func(has_rc6) \
+   func(has_rc6p) \
+   func(has_dp_mst) \
+   func(has_gmbus_irq) \
+   func(has_hw_contexts) \
+   func(has_logical_ring_contexts) \
+   func(has_l3_dpf) \
+   func(has_gmch_display) \
+   func(has_guc) \
+   func(has_pipe_cxsr) \
+   func(has_hotplug) \
+   func(cursor_needs_physical) \
+   func(has_overlay) \
+   func(overlay_needs_physical) \
+   func(supports_tv) \
+   func(has_llc) \
+   func(has_snoop) \
+   func(has_ddi) \
+   func(has_fpga_dbg) \
func(has_pooled_eu)
 
-#define DEFINE_FLAG(name) u8 name:1
-#define SEP_SEMICOLON ;
-
 struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask;
@@ -710,7 +707,9 @@ struct intel_device_info {
u16 gen_mask;
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
-   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+#define DEFINE_FLAG(name) u8 name:1;
+   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG)
+#undef DEFINE_FLAG
u16 ddb_size; /* in blocks */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
@@ -727,9 +726,6 @@ struct intel_device_info {
} color;
 };
 
-#undef DEFINE_FLAG
-#undef SEP_SEMICOLON
-
 struct intel_display_error_state;
 
 struct drm_i915_error_state {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Show waiters in i915_hangcheck_info

[Mika Kuoppala]

Chris Wilson  writes:

The commit message is missing.

> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9c95ce73f2aa..39b76c24c84f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1343,6 +1343,9 @@ static int i915_hangcheck_info(struct seq_file *m, void 
> *unused)
>   seq_printf(m, "Hangcheck inactive\n");
>  
>   for_each_engine_id(engine, dev_priv, id) {
> + struct intel_breadcrumbs *b = >breadcrumbs;
> + struct rb_node *rb;
> +
>   seq_printf(m, "%s:\n", engine->name);
>   seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
>  engine->hangcheck.seqno,
> @@ -1352,6 +1355,15 @@ static int i915_hangcheck_info(struct seq_file *m, 
> void *unused)
>  yesno(intel_engine_has_waiter(engine)),
>  yesno(test_bit(engine->id,
> 
> _priv->gpu_error.missed_irq_rings)));
> + spin_lock(>lock);
> + for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {

The waiters are embeddded in requests? So we need the rcu_read_lock?

-Mika


> + struct intel_wait *w = container_of(rb, typeof(*w), 
> node);
> +
> + seq_printf(m, "\t%s [%d] waiting for %x\n",
> +w->tsk->comm, w->tsk->pid, w->seqno);
> + }
> + spin_unlock(>lock);
> +
>   seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
>  (long long)engine->hangcheck.acthd,
>  (long long)acthd[id]);
> -- 
> 2.9.3
>
> ___
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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Show RING registers through debugfs

[Mika Kuoppala]

Chris Wilson  writes:

> Knowing where the RINGs are pointing is extremely useful in diagnosing
> if the engines are executing the ringbuffers you expect - and igt may be
> suppressing the usual method of looking in the GPU error state.
>
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 230 
> +++-
>  drivers/gpu/drm/i915/intel_engine_cs.c  |  30 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  16 ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +
>  4 files changed, 170 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 4fb9d829884e..9c95ce73f2aa 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -635,6 +635,23 @@ static int i915_gem_batch_pool_info(struct seq_file *m, 
> void *data)
>   return 0;
>  }
>  
> +static void print_request(struct seq_file *m,
> +   struct drm_i915_gem_request *rq,
> +   const char *prefix)
> +{
> + struct pid *pid = rq->ctx->pid;
> + struct task_struct *task;
> +
> + rcu_read_lock();
> + task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
> + seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
> +rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
> +jiffies_to_msecs(jiffies - rq->emitted_jiffies),
> +task ? task->comm : "",
> +task ? task->pid : -1);
> + rcu_read_unlock();
> +}
> +
>  static int i915_gem_request_info(struct seq_file *m, void *data)
>  {
>   struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -658,19 +675,8 @@ static int i915_gem_request_info(struct seq_file *m, 
> void *data)
>   continue;
>  
>   seq_printf(m, "%s requests: %d\n", engine->name, count);
> - list_for_each_entry(req, >request_list, link) {
> - struct pid *pid = req->ctx->pid;
> - struct task_struct *task;
> -
> - rcu_read_lock();
> - task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
> - seq_printf(m, "%x @ %d: %s [%d]\n",
> -req->fence.seqno,
> -(int) (jiffies - req->emitted_jiffies),
> -task ? task->comm : "",
> -task ? task->pid : -1);
> - rcu_read_unlock();
> - }
> + list_for_each_entry(req, >request_list, link)
> + print_request(m, req, "");
>  
>   any++;
>   }
> @@ -2036,84 +2042,6 @@ static int i915_dump_lrc(struct seq_file *m, void 
> *unused)
>   return 0;
>  }
>  
> -static int i915_execlists(struct seq_file *m, void *data)
> -{
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct drm_device *dev = _priv->drm;
> - struct intel_engine_cs *engine;
> - u32 status_pointer;
> - u8 read_pointer;
> - u8 write_pointer;
> - u32 status;
> - u32 ctx_id;
> - struct list_head *cursor;
> - int i, ret;
> -
> - if (!i915.enable_execlists) {
> - seq_puts(m, "Logical Ring Contexts are disabled\n");
> - return 0;
> - }
> -
> - ret = mutex_lock_interruptible(>struct_mutex);
> - if (ret)
> - return ret;
> -
> - intel_runtime_pm_get(dev_priv);
> -
> - for_each_engine(engine, dev_priv) {
> - struct drm_i915_gem_request *head_req = NULL;
> - int count = 0;
> -
> - seq_printf(m, "%s\n", engine->name);
> -
> - status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
> - ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
> - seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
> -status, ctx_id);
> -
> - status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
> - seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
> -
> - read_pointer = GEN8_CSB_READ_PTR(status_pointer);
> - write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
> - if (read_pointer > write_pointer)
> - write_pointer += GEN8_CSB_ENTRIES;
> - seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
> -read_pointer, write_pointer);
> -
> - for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
> - status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, 
> i));
> - ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, 
> i));
> -
> - seq_printf(m, "\tStatus buffer %d: 0x%08X, context: 
> %u\n",
> -i, status, ctx_id);
> 

[Intel-gfx] [PATCH 7/7] drm/i915: Add entrypoints for mapping dplls to encoders and crtcs

[Ander Conselvan de Oliveira]

Abstract the platform specific bits of mapping the dplls under a
platform independ entrypoints so the differences between platforms are
contained in the dpll code. I.e., it removes IS_PLATFORM() macros from
other parts of the code.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  |  51 ++
 drivers/gpu/drm/i915/intel_display.c  | 124 +-
 drivers/gpu/drm/i915/intel_dp_mst.c   |   4 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 299 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   7 +
 drivers/gpu/drm/i915/intel_drv.h  |   4 +-
 6 files changed, 334 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4077205..144fe5c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -319,6 +319,19 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder 
*encoder)
}
 }
 
+struct intel_encoder *
+intel_ddi_get_port_encoder(struct drm_i915_private *dev_priv, enum port port)
+{
+   struct intel_encoder *encoder;
+
+   for_each_intel_encoder(_priv->drm, encoder) {
+   if (port == intel_ddi_get_encoder_port(encoder))
+   return encoder;
+   }
+
+   return NULL;
+}
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
@@ -582,11 +595,12 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
-   u32 temp, i, rx_ctl_val, ddi_pll_sel;
+   u32 temp, i, rx_ctl_val;
 
for_each_encoder_on_crtc(dev, crtc, encoder) {
WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
intel_prepare_dp_ddi_buffers(encoder);
+   break;
}
 
/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
@@ -613,9 +627,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
/* Configure Port Clock Select */
-   ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
-   I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
-   WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
+   intel_dpll_map_to_encoder(intel_crtc->config->shared_dpll, encoder);
 
/* Start the training iterating through available voltages and emphasis,
 * testing each value twice. */
@@ -1607,33 +1619,6 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
 }
 
-void intel_ddi_clk_select(struct intel_encoder *encoder,
- struct intel_shared_dpll *pll)
-{
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   enum port port = intel_ddi_get_encoder_port(encoder);
-
-   if (WARN_ON(!pll))
-   return;
-
-   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-   uint32_t val;
-
-   /* DDI -> PLL mapping  */
-   val = I915_READ(DPLL_CTRL2);
-
-   val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-   DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-   val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
-   DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-   I915_WRITE(DPLL_CTRL2, val);
-
-   } else if (INTEL_INFO(dev_priv)->gen < 9) {
-   I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
-   }
-}
-
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
int link_rate, uint32_t lane_count,
struct intel_shared_dpll *pll,
@@ -1648,7 +1633,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
if (encoder->type == INTEL_OUTPUT_EDP)
intel_edp_panel_on(intel_dp);
 
-   intel_ddi_clk_select(encoder, pll);
+   intel_dpll_map_to_encoder(pll, encoder);
intel_prepare_dp_ddi_buffers(encoder);
intel_ddi_init_dp_buf_reg(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -1669,7 +1654,7 @@ static void intel_ddi_pre_enable_hdmi(struct 
intel_encoder *encoder,
int level = intel_ddi_hdmi_level(dev_priv, port);
 
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
-   intel_ddi_clk_select(encoder, pll);
+   intel_dpll_map_to_encoder(pll, encoder);
intel_prepare_hdmi_ddi_buffers(encoder);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_set_iboost(encoder, level);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8ecaf18..22e3c46 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4555,19 +4555,7 @@ static void 

[Intel-gfx] [PATCH 4/7] drm/i915: Rename intel_shared_dpll->mode_set() to prepare()

[Ander Conselvan de Oliveira]

The hook is called from intel_prepare_shared_dpll(). The name doesn't
make sense after all the changes to modeset code. So just call it
prepare.

Signed-off-by: Ander Conselvan de Oliveira 

Reviewed-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 8 
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index c88fc07..9446446 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -112,7 +112,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
WARN_ON(pll->on);
assert_shared_dpll_disabled(dev_priv, pll);
 
-   pll->funcs.mode_set(dev_priv, pll);
+   pll->funcs.prepare(dev_priv, pll);
}
mutex_unlock(_priv->dpll_lock);
 }
@@ -302,8 +302,8 @@ static bool ibx_pch_dpll_get_hw_state(struct 
drm_i915_private *dev_priv,
return val & DPLL_VCO_ENABLE;
 }
 
-static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll)
 {
I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
@@ -392,7 +392,7 @@ ibx_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
 }
 
 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
-   .mode_set = ibx_pch_dpll_mode_set,
+   .prepare = ibx_pch_dpll_prepare,
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 6e3a0f1..9a7db65 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -101,7 +101,7 @@ struct intel_shared_dpll_state {
 struct intel_shared_dpll_funcs {
/* The mode_set hook is optional and should be used together with the
 * intel_prepare_shared_dpll function. */
-   void (*mode_set)(struct drm_i915_private *dev_priv,
+   void (*prepare)(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll);
void (*enable)(struct drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll);
-- 
2.5.5

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[Intel-gfx] [PATCH 6/7] drm/i915: Add dpll entrypoint for dumping hw state

[Ander Conselvan de Oliveira]

Remove the IS_PLATFORM() macros from intel_dump_pipe_config() and split
that logic in platform specific implementations inside the dpll code,
accessed through a platform independent interface.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c  | 35 +---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +++
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  3 ++
 3 files changed, 84 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e6fe85b..8ecaf18 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12744,6 +12744,7 @@ static void intel_dump_pipe_config(struct intel_crtc 
*crtc,
   const char *context)
 {
struct drm_device *dev = crtc->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_plane *plane;
struct intel_plane *intel_plane;
struct intel_plane_state *state;
@@ -12805,39 +12806,7 @@ static void intel_dump_pipe_config(struct intel_crtc 
*crtc,
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 
-   if (IS_BROXTON(dev)) {
-   DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
- "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
- "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, 
pcsdw12: 0x%x\n",
- pipe_config->dpll_hw_state.ebb0,
- pipe_config->dpll_hw_state.ebb4,
- pipe_config->dpll_hw_state.pll0,
- pipe_config->dpll_hw_state.pll1,
- pipe_config->dpll_hw_state.pll2,
- pipe_config->dpll_hw_state.pll3,
- pipe_config->dpll_hw_state.pll6,
- pipe_config->dpll_hw_state.pll8,
- pipe_config->dpll_hw_state.pll9,
- pipe_config->dpll_hw_state.pll10,
- pipe_config->dpll_hw_state.pcsdw12);
-   } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
-   DRM_DEBUG_KMS("dpll_hw_state: "
- "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
- pipe_config->dpll_hw_state.ctrl1,
- pipe_config->dpll_hw_state.cfgcr1,
- pipe_config->dpll_hw_state.cfgcr2);
-   } else if (HAS_DDI(dev)) {
-   DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
- pipe_config->dpll_hw_state.wrpll,
- pipe_config->dpll_hw_state.spll);
-   } else {
-   DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
- "fp0: 0x%x, fp1: 0x%x\n",
- pipe_config->dpll_hw_state.dpll,
- pipe_config->dpll_hw_state.dpll_md,
- pipe_config->dpll_hw_state.fp0,
- pipe_config->dpll_hw_state.fp1);
-   }
+   intel_dpll_dump_hw_state(dev_priv, _config->dpll_hw_state);
 
DRM_DEBUG_KMS("planes on this crtc\n");
list_for_each_entry(plane, >mode_config.plane_list, head) {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8c4efa9..9b02d9c 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -447,6 +447,17 @@ ibx_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
return pll;
 }
 
+static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_dpll_hw_state *hw_state)
+{
+   DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
+ "fp0: 0x%x, fp1: 0x%x\n",
+ hw_state->dpll,
+ hw_state->dpll_md,
+ hw_state->fp0,
+ hw_state->fp1);
+}
+
 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
.prepare = ibx_pch_dpll_prepare,
.enable = ibx_pch_dpll_enable,
@@ -833,6 +844,13 @@ hsw_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
return pll;
 }
 
+static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_dpll_hw_state *hw_state)
+{
+   DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
+ hw_state->wrpll, hw_state->spll);
+}
+
 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
@@ -1388,6 +1406,16 @@ skl_get_dpll(struct intel_crtc *crtc, 

[Intel-gfx] [PATCH 5/7] drm/i915: Update kerneldoc for intel_dpll_mgr.c

[Ander Conselvan de Oliveira]

The documentation for most of the non-static members and structs were
missing. Fix that.

v2: Fix typos (Durga)

v3: Rebase.
Fix make docs warnings.
Document more.

Signed-off-by: Ander Conselvan de Oliveira 

---
 Documentation/gpu/i915.rst|  12 +++
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  90 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 155 ++
 3 files changed, 237 insertions(+), 20 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 87aaffc..c19e437 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -204,6 +204,18 @@ Video BIOS Table (VBT)
 .. kernel-doc:: drivers/gpu/drm/i915/intel_vbt_defs.h
:internal:
 
+Display PLLs
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.c
+   :doc: Display PLLs
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.c
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.h
+   :internal:
+
 Memory Management and Command Submission
 
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 9446446..8c4efa9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -23,6 +23,25 @@
 
 #include "intel_drv.h"
 
+/**
+ * DOC: Display PLLs
+ *
+ * Display PLLs used for driving outputs vary by platform. While some have
+ * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
+ * from a pool. In the latter scenario, it is possible that multiple pipes
+ * share a PLL if their configurations match.
+ *
+ * This file provides an abstraction over display PLLs. The function
+ * intel_shared_dpll_init() initializes the PLLs for the given platform.  The
+ * users of a PLL are tracked and that tracking is integrated with the atomic
+ * modest interface. During an atomic operation, a PLL can be requested for a
+ * given crtc and encoder configuration by calling intel_get_shared_dpll() and
+ * a previously used PLL can be released with intel_release_shared_dpll().
+ * Changes to the users are first staged in the atomic state, and then made
+ * effective by calling intel_shared_dpll_swap_state() during the atomic
+ * commit phase.
+ */
+
 struct intel_shared_dpll *
 skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
 {
@@ -61,6 +80,14 @@ skl_find_link_pll(struct drm_i915_private *dev_priv, int 
clock)
return pll;
 }
 
+/**
+ * intel_get_shared_dpll_by_id - get a DPLL given its id
+ * @dev_priv: i915 device instance
+ * @id: pll id
+ *
+ * Returns:
+ * A pointer to the DPLL with @id
+ */
 struct intel_shared_dpll *
 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
@@ -68,6 +95,14 @@ intel_get_shared_dpll_by_id(struct drm_i915_private 
*dev_priv,
return _priv->shared_dplls[id];
 }
 
+/**
+ * intel_get_shared_dpll_id - get the id of a DPLL
+ * @dev_priv: i915 device instance
+ * @pll: the DPLL
+ *
+ * Returns:
+ * The id of @pll
+ */
 enum intel_dpll_id
 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
@@ -96,6 +131,13 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->name, onoff(state), onoff(cur_state));
 }
 
+/**
+ * intel_prepare_shared_dpll - call a dpll's prepare hook
+ * @crtc: crtc which has a shared dpll
+ *
+ * This calls the PLL's prepare hook if it has one and if the PLL is not
+ * already enabled. The prepare hook is platform specific.
+ */
 void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
@@ -118,12 +160,10 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 }
 
 /**
- * intel_enable_shared_dpll - enable PCH PLL
- * @dev_priv: i915 private structure
- * @pipe: pipe PLL to enable
+ * intel_enable_shared_dpll - enable a crtc's shared DPLL
+ * @crtc: crtc which has a shared DPLL
  *
- * The PCH PLL needs to be enabled before the PCH transcoder, since it
- * drives the transcoder clock.
+ * Enable the shared DPLL used by @crtc.
  */
 void intel_enable_shared_dpll(struct intel_crtc *crtc)
 {
@@ -164,6 +204,12 @@ out:
mutex_unlock(_priv->dpll_lock);
 }
 
+/**
+ * intel_disable_shared_dpll - disable a crtc's shared DPLL
+ * @crtc: crtc which has a shared DPLL
+ *
+ * Disable the shared DPLL used by @crtc.
+ */
 void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
@@ -266,6 +312,16 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
 }
 
+/**
+ * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
+ * @state: atomic state
+ *
+ * This is the dpll version of drm_atomic_helper_swap_state() since the
+ * helper does not handle 

[Intel-gfx] [PATCH 2/7] drm/i915: Rename intel_shared_dpll_commit() to _swap_state()

[Ander Conselvan de Oliveira]

The function intel_shared_dpll_commit() performs the equivalent of
drm_atomic_helper_swap_state() for the shared dpll state, which is not
handled by the helpers. So rename it for consistency.

v2: Fix typo in the commit message. (Durga)
v3: Rebase.
Signed-off-by: Ander Conselvan de Oliveira 

Reviewed-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_display.c  | 2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 28d9d3e..b8bfde0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14530,7 +14530,7 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_helper_swap_state(state, true);
dev_priv->wm.distrust_bios_wm = false;
dev_priv->wm.skl_results = intel_state->wm_results;
-   intel_shared_dpll_commit(state);
+   intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
 
if (nonblock)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index f1b3feb..15bf462 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -266,7 +266,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
 }
 
-void intel_shared_dpll_commit(struct drm_atomic_state *state)
+void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_shared_dpll_config *shared_dpll;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 99a82c9..06d61c5 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -152,7 +152,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll 
*dpll,
 void intel_prepare_shared_dpll(struct intel_crtc *crtc);
 void intel_enable_shared_dpll(struct intel_crtc *crtc);
 void intel_disable_shared_dpll(struct intel_crtc *crtc);
-void intel_shared_dpll_commit(struct drm_atomic_state *state);
+void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
 void intel_shared_dpll_init(struct drm_device *dev);
 
 /* BXT dpll related functions */
-- 
2.5.5

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[Intel-gfx] [PATCH 3/7] drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state

[Ander Conselvan de Oliveira]

Struct intel_shared_dpll_config is used to hold the state of the DPLL in
the "atomic" sense, so call it state like everything else atomic.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_debugfs.c   | 12 +++
 drivers/gpu/drm/i915/intel_atomic.c   |  6 ++--
 drivers/gpu/drm/i915/intel_ddi.c  | 10 +++---
 drivers/gpu/drm/i915/intel_display.c  | 22 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 68 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  4 +--
 drivers/gpu/drm/i915/intel_drv.h  |  4 +--
 7 files changed, 63 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index da71413..12b97af 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3229,14 +3229,14 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
 
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
-  pll->config.crtc_mask, pll->active_mask, 
yesno(pll->on));
+  pll->state.crtc_mask, pll->active_mask, 
yesno(pll->on));
seq_printf(m, " tracked hardware state:\n");
-   seq_printf(m, " dpll:0x%08x\n", pll->config.hw_state.dpll);
+   seq_printf(m, " dpll:0x%08x\n", pll->state.hw_state.dpll);
seq_printf(m, " dpll_md: 0x%08x\n",
-  pll->config.hw_state.dpll_md);
-   seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
-   seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
-   seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
+  pll->state.hw_state.dpll_md);
+   seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
+   seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
+   seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
}
drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index c5a1667..fa6dc43 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -267,7 +267,7 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
 
 static void
 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll_config *shared_dpll)
+ struct intel_shared_dpll_state *shared_dpll)
 {
enum intel_dpll_id i;
 
@@ -275,11 +275,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private 
*dev_priv,
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = _priv->shared_dplls[i];
 
-   shared_dpll[i] = pll->config;
+   shared_dpll[i] = pll->state;
}
 }
 
-struct intel_shared_dpll_config *
+struct intel_shared_dpll_state *
 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 {
struct intel_atomic_state *state = to_intel_atomic_state(s);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c..4077205 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -992,7 +992,7 @@ static int bxt_calc_pll_link(struct drm_i915_private 
*dev_priv,
return 0;
 
pll = _priv->shared_dplls[dpll];
-   state = >config.hw_state;
+   state = >state.hw_state;
 
clock.m1 = 2;
clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
@@ -2401,7 +2401,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int 
clock)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_shared_dpll *pll = NULL;
-   struct intel_shared_dpll_config tmp_pll_config;
+   struct intel_shared_dpll_state tmp_pll_state;
enum intel_dpll_id dpll_id;
 
if (IS_BROXTON(dev_priv)) {
@@ -2417,11 +2417,11 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int 
clock)
  pll->active_mask);
return NULL;
}
-   tmp_pll_config = pll->config;
+   tmp_pll_state = pll->state;
if (!bxt_ddi_dp_set_dpll_hw_state(clock,
- >config.hw_state)) {
+ >state.hw_state)) {
DRM_ERROR("Could not setup DPLL\n");
-   pll->config = tmp_pll_config;
+   pll->state = tmp_pll_state;
return NULL;
}
} else if (IS_SKYLAKE(dev_priv) || 

[Intel-gfx] [PATCH 0/7] Shared DPLL kernel doc and improvements

[Ander Conselvan de Oliveira]

Hi,

This is a resend of some previous patches adding documentation to the
shared dpll stuff, which I didn't merge since the first patch still
lacks review, plus some more changes on top to make the interface
more self contained.

Thanks,
Ander

Ander Conselvan de Oliveira (7):
  drm/i915: Introduce intel_release_shared_dpll()
  drm/i915: Rename intel_shared_dpll_commit() to _swap_state()
  drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state
  drm/i915: Rename intel_shared_dpll->mode_set() to prepare()
  drm/i915: Update kerneldoc for intel_dpll_mgr.c
  drm/i915: Add dpll entrypoint for dumpoing hw state
  drm/i915: Add entrypoints for mapping dplls to encoders and crtcs

 Documentation/gpu/i915.rst|  12 +
 drivers/gpu/drm/i915/i915_debugfs.c   |  12 +-
 drivers/gpu/drm/i915/intel_atomic.c   |   6 +-
 drivers/gpu/drm/i915/intel_ddi.c  |  61 ++--
 drivers/gpu/drm/i915/intel_display.c  | 189 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c   |   4 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 581 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 184 +--
 drivers/gpu/drm/i915/intel_drv.h  |   8 +-
 9 files changed, 745 insertions(+), 312 deletions(-)

-- 
2.5.5

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[Intel-gfx] [PATCH 1/7] drm/i915: Introduce intel_release_shared_dpll()

[Ander Conselvan de Oliveira]

While the details of getting a shared dpll are wrapped by
intel_get_shared_dpll(), the release was still hand rolled into the
modeset code. Fix that by creating an entry point for releasing the
pll and move that code there.

v2: Take old_dpll from crtc->state instead of crtc_state. (CI)
Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c  |  6 +
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 41 +++
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 11 +++---
 3 files changed, 22 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a366656..28d9d3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13768,7 +13768,6 @@ static void intel_modeset_clear_plls(struct 
drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_shared_dpll_config *shared_dpll = NULL;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int i;
@@ -13789,10 +13788,7 @@ static void intel_modeset_clear_plls(struct 
drm_atomic_state *state)
if (!old_dpll)
continue;
 
-   if (!shared_dpll)
-   shared_dpll = intel_atomic_get_shared_dpll_state(state);
-
-   intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
+   intel_release_shared_dpll(old_dpll, intel_crtc, state);
}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 1c59ca5..f1b3feb 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -79,28 +79,6 @@ intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
 }
 
-void
-intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
-
-   config[id].crtc_mask |= 1 << crtc->pipe;
-}
-
-void
-intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
-
-   config[id].crtc_mask &= ~(1 << crtc->pipe);
-}
-
 /* For ILK+ */
 void assert_shared_dpll(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
@@ -285,7 +263,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
 pipe_name(crtc->pipe));
 
-   intel_shared_dpll_config_get(shared_dpll, pll, crtc);
+   shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
 }
 
 void intel_shared_dpll_commit(struct drm_atomic_state *state)
@@ -1900,3 +1878,20 @@ intel_get_shared_dpll(struct intel_crtc *crtc,
 
return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
 }
+
+/**
+ * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
+ * @dpll: dpll in use by @crtc
+ * @crtc: crtc
+ * @state: atomic state
+ *
+ */
+void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
+  struct intel_crtc *crtc,
+  struct drm_atomic_state *state)
+{
+   struct intel_shared_dpll_config *shared_dpll_config;
+
+   shared_dpll_config = intel_atomic_get_shared_dpll_state(state);
+   shared_dpll_config[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
+}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index f438535..99a82c9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -138,14 +138,6 @@ intel_get_shared_dpll_by_id(struct drm_i915_private 
*dev_priv,
 enum intel_dpll_id
 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll);
-void
-intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc);
-void
-intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc);
 void assert_shared_dpll(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
bool state);
@@ -154,6 +146,9 @@ void assert_shared_dpll(struct 

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Show bounds of active request in the ring on GPU hang

[Mika Kuoppala]

Chris Wilson  writes:

> Include the position of the active request in the ring, and display that
> alongside the current RING registers (on a GPU hang).
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 

> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   | 3 +++
>  drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++--
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 91ac283d733e..e48044b3a447 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -776,6 +776,9 @@ struct drm_i915_error_state {
>   struct i915_address_space *vm;
>   int num_requests;
>  
> + /* position of active request inside the ring */
> + u32 rq_head, rq_post, rq_tail;
> +
>   /* our own tracking of ring head and tail */
>   u32 cpu_ring_head;
>   u32 cpu_ring_tail;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2bbab226a46c..8b85efbdfa04 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -262,8 +262,9 @@ static void error_print_engine(struct 
> drm_i915_error_state_buf *m,
>  {
>   err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
>   err_printf(m, "  START: 0x%08x\n", ee->start);
> - err_printf(m, "  HEAD:  0x%08x\n", ee->head);
> - err_printf(m, "  TAIL:  0x%08x\n", ee->tail);
> + err_printf(m, "  HEAD:  0x%08x\n [0x%08x]", ee->head, ee->rq_head);
> + err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
> +ee->tail, ee->rq_post, ee->rq_tail);
>   err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
>   err_printf(m, "  MODE:  0x%08x\n", ee->mode);
>   err_printf(m, "  HWS:   0x%08x\n", ee->hws);
> @@ -1230,6 +1231,10 @@ static void i915_gem_record_rings(struct 
> drm_i915_private *dev_priv,
>   error->simulated |=
>   request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
>  
> + ee->rq_head = request->head;
> + ee->rq_post = request->postfix;
> + ee->rq_tail = request->tail;
> +
>   ring = request->ring;
>   ee->cpu_ring_head = ring->head;
>   ee->cpu_ring_tail = ring->tail;
> -- 
> 2.9.3
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [RESEND,1/2] drm/i915: workaround sparse warning on variable length arrays

[Patchwork]

== Series Details ==

Series: series starting with [RESEND,1/2] drm/i915: workaround sparse warning 
on variable length arrays
URL   : https://patchwork.freedesktop.org/series/13269/
State : warning

== Summary ==

Series 13269v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13269/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2620/

cedbdecff4c878309133e066f696ea63d41cee73 drm-intel-nightly: 
2016y-10m-04d-10h-53m-20s UTC integration manifest
323d3a4 drm/i915: silence io mapping/unmapping sparse warnings on different 
address spaces

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Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

[Jani Nikula]

On Tue, 04 Oct 2016, Joonas Lahtinen  wrote:
> On ti, 2016-10-04 at 12:29 +0300, Jani Nikula wrote:
>> Fix sparse warning:
>> 
>> drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol
>> 'skl_ddb_add_affected_planes' was not declared. Should it be static?
>> 
>> Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually affected 
>> by ddb changes")
>> Cc: Lyude 
>> Cc: Paulo Zanoni 
>> Signed-off-by: Jani Nikula 
>
> Reviewed-by: Joonas Lahtinen 

Thanks, pushed to dinq.

BR,
Jani.

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Re: [Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

[Joonas Lahtinen]

On ti, 2016-10-04 at 12:29 +0300, Jani Nikula wrote:
> Fix sparse warning:
> 
> drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol
> 'skl_ddb_add_affected_planes' was not declared. Should it be static?
> 
> Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually affected by 
> ddb changes")
> Cc: Lyude 
> Cc: Paulo Zanoni 
> Signed-off-by: Jani Nikula 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: make skl_ddb_add_affected_planes static

[Patchwork]

== Series Details ==

Series: drm/i915: make skl_ddb_add_affected_planes static
URL   : https://patchwork.freedesktop.org/series/13267/
State : warning

== Summary ==

Series 13267v1 drm/i915: make skl_ddb_add_affected_planes static
https://patchwork.freedesktop.org/api/1.0/series/13267/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-flip-before-cursor-legacy:
pass   -> DMESG-WARN (fi-skl-6700k)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-snb-2520m)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> DMESG-WARN (fi-skl-6700k)
Subgroup basic-rte:
pass   -> DMESG-WARN (fi-skl-6700k)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:216  dwarn:4   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2619/

51bf114bf6c0ac7de7b8e6fbbdc3cb4a2f7dc75f drm-intel-nightly: 
2016y-10m-04d-09h-20m-32s UTC integration manifest
39061ec drm/i915: make skl_ddb_add_affected_planes static

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

[Tvrtko Ursulin]

On 04/10/2016 10:37, Joonas Lahtinen wrote:

On ti, 2016-10-04 at 10:18 +0100, Tvrtko Ursulin wrote:
  
Joonas what do you think, worth merging on balance?
  

+1 on merging.


Pushed to dinq, first one from the new office. :)

Thanks for the review guys!

Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH RESEND 2/2] drm/i915: silence io mapping/unmapping sparse warnings on different address spaces

[Joonas Lahtinen]

On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote:
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52: warning: incorrect type in 
> argument 1 (different address spaces)
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:expected void [noderef] 
> *vaddr
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:got void *
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15: warning: incorrect type in 
> assignment (different address spaces)
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15:expected void *vaddr
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15:got void [noderef] 
> *
> 
> Cc: Chris Wilson 
> Signed-off-by: Jani Nikula 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

[Jani Nikula]

On Tue, 04 Oct 2016, Joonas Lahtinen  wrote:
> On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote:
>> @@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct 
>> drm_i915_private *dev_priv)
>>  struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
>>  const int s_max = 3, ss_max = 3, eu_max = 8;
>
> Does sparse shut up if you split these into their own lines?
>
>>  int s, ss;
>> -u32 fuse2, eu_disable[s_max];
>> +u32 fuse2, eu_disable[3]; /* s_max */
>
> If not;
>
> Reviewed-by: Joonas Lahtinen 

No go, pushed this one. Thanks for the review.

How about patch 2/2?

BR,
Jani.


-- 
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Re: [Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

[Joonas Lahtinen]

On ti, 2016-10-04 at 12:54 +0300, Jani Nikula wrote:
> @@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct 
> drm_i915_private *dev_priv)
>   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
>   const int s_max = 3, ss_max = 3, eu_max = 8;

Does sparse shut up if you split these into their own lines?

>   int s, ss;
> - u32 fuse2, eu_disable[s_max];
> + u32 fuse2, eu_disable[3]; /* s_max */

If not;

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH RESEND 2/2] drm/i915: silence io mapping/unmapping sparse warnings on different address spaces

[Jani Nikula]

drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52: warning: incorrect type in 
argument 1 (different address spaces)
drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:expected void [noderef] 
*vaddr
drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:got void *
drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15: warning: incorrect type in 
assignment (different address spaces)
drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15:expected void *vaddr
drivers/gpu/drm/i915/i915_gem_execbuffer.c:477:15:got void [noderef] 
*

Cc: Chris Wilson 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 33c85227643d..e88786ea1219 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -429,7 +429,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
}
 
if (cache->vaddr) {
-   io_mapping_unmap_atomic(unmask_page(cache->vaddr));
+   io_mapping_unmap_atomic((void __force __iomem *) 
unmask_page(cache->vaddr));
} else {
struct i915_vma *vma;
int ret;
@@ -474,7 +474,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
offset += page << PAGE_SHIFT;
}
 
-   vaddr = io_mapping_map_atomic_wc(>i915->ggtt.mappable, offset);
+   vaddr = (void __force *) 
io_mapping_map_atomic_wc(>i915->ggtt.mappable, offset);
cache->page = page;
cache->vaddr = (unsigned long)vaddr;
 
-- 
2.1.4

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[Intel-gfx] [PATCH RESEND 1/2] drm/i915: workaround sparse warning on variable length arrays

[Jani Nikula]

Fix sparse warning:

drivers/gpu/drm/i915/intel_device_info.c:195:31: warning: Variable
length array is used.

In truth the array does have constant length, but sparse is too dumb to
realize. This is a bit ugly, but silence the warning no matter what.

Fixes: 91bedd34abf0 ("drm/i915/bdw: Check for slice, subslice and EU count for 
BDW")
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 73b6858600ac..1b20e160bc1f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct 
drm_i915_private *dev_priv)
struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
const int s_max = 3, ss_max = 3, eu_max = 8;
int s, ss;
-   u32 fuse2, eu_disable[s_max];
+   u32 fuse2, eu_disable[3]; /* s_max */
 
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
-- 
2.1.4

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

[Joonas Lahtinen]

On ti, 2016-10-04 at 10:18 +0100, Tvrtko Ursulin wrote:
> 
> Joonas what do you think, worth merging on balance?
> 

+1 on merging.

Regards, Joonas

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Intel Corporation
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[Intel-gfx] [PATCH] drm/i915: make skl_ddb_add_affected_planes static

[Jani Nikula]

Fix sparse warning:

drivers/gpu/drm/i915/intel_pm.c:3970:1: warning: symbol
'skl_ddb_add_affected_planes' was not declared. Should it be static?

Fixes: 7f60e200e254 ("drm/i915/gen9: only add the planes actually affected by 
ddb changes")
Cc: Lyude 
Cc: Paulo Zanoni 
Signed-off-by: Jani Nikula 

---

Please run sparse on your patches, please run sparse before you push.
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 425544b1f733..7f1748a1e614 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3966,7 +3966,7 @@ pipes_modified(struct drm_atomic_state *state)
return ret;
 }
 
-int
+static int
 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 {
struct drm_atomic_state *state = cstate->base.state;
-- 
2.1.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/dp/i915: Enable audio codec after the HDA audio driver is initialized

[Patchwork]

== Series Details ==

Series: drm/dp/i915: Enable audio codec after the HDA audio driver is 
initialized
URL   : https://patchwork.freedesktop.org/series/13265/
State : warning

== Summary ==

Series 13265v1 drm/dp/i915: Enable audio codec after the HDA audio driver is 
initialized
https://patchwork.freedesktop.org/api/1.0/series/13265/revisions/1/mbox/

Test drv_module_reload_basic:
pass   -> DMESG-WARN (fi-bxt-t5700)
pass   -> DMESG-WARN (fi-skl-6770hq)
Test gem_busy:
Subgroup basic-hang-default:
fail   -> PASS   (fi-hsw-4770r)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:213  dwarn:1   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:227  dwarn:2   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2618/

981382a8204271db3e29da9929625e26f251fadf drm-intel-nightly: 
2016y-10m-04d-06h-31m-31s UTC integration manifest
2464646 drm/dp/i915: Enable audio codec after the HDA audio driver is 
initialized

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Re: [Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

[Jani Nikula]

On Tue, 04 Oct 2016, Chris Wilson  wrote:
> On Tue, Oct 04, 2016 at 10:53:48AM +0300, Jani Nikula wrote:
>> Move the outcast intel_fbdev_output_poll_changed() stub for
>> CONFIG_DRM_FBDEV_EMULATION=n next to its friends.
>> 
>> Signed-off-by: Jani Nikula 
> Reviewed-by: Chris Wilson 

Thanks, pushed to dinq.

BR,
Jani.


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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

[Tvrtko Ursulin]

On 04/10/2016 09:55, Chris Wilson wrote:


On Tue, Oct 04, 2016 at 09:46:50AM +0100, Tvrtko Ursulin wrote:

On 03/10/2016 10:27, Patchwork wrote:

fi-bdw-5557u total:236  pass:220  dwarn:0   dfail:0   fail:0   skip:15
fi-bxt-t5700 total:236  pass:205  dwarn:0   dfail:0   fail:0   skip:30
fi-byt-j1900 total:236  pass:202  dwarn:1   dfail:0   fail:1   skip:31
fi-byt-n2820 total:245  pass:208  dwarn:0   dfail:0   fail:2   skip:35
fi-hsw-4770  total:236  pass:213  dwarn:0   dfail:0   fail:0   skip:22
fi-hsw-4770r total:245  pass:222  dwarn:0   dfail:0   fail:1   skip:22
fi-ilk-650   total:236  pass:173  dwarn:0   dfail:0   fail:2   skip:60
fi-skl-6700k total:236  pass:209  dwarn:2   dfail:0   fail:0   skip:24
fi-skl-6770hqtotal:245  pass:228  dwarn:1   dfail:0   fail:2   skip:14
fi-snb-2520m total:245  pass:208  dwarn:0   dfail:0   fail:1   skip:36
fi-snb-2600  total:236  pass:198  dwarn:0   dfail:0   fail:0   skip:37
fi-ivb-3520m failed to connect after reboot
fi-ivb-3770 failed to collect. IGT log at Patchwork_2612/fi-ivb-3770/igt.log
fi-skl-6260u failed to collect. IGT log at Patchwork_2612/fi-skl-6260u/igt.log
fi-skl-6700hq failed to collect. IGT log at Patchwork_2612/fi-skl-6700hq/igt.log

Results at /archive/results/CI_IGT_test/Patchwork_2612/

d0534bd0217c83c083ba146b9c987e19b219e0e4 drm-intel-nightly: 
2016y-09m-30d-10h-31m-00s UTC integration manifest
c5237e5 drm/i915: Inline binary search
9b4e3c9 drm/i915: Use binary search when looking for shadowed registers
0b12dbd drm/i915: Sort the shadow register table
7978e69 drm/i915: Remove identical write mmmio functions
b0960d1 drm/i915: Remove identical mmio read functions
354b09a drm/i915: Remove identical macros
e608845 drm/i915: Store the active forcewake range table pointer
79f3cb4 drm/i915: Eliminate Gen9 special case
7fe1499 drm/i915: Use binary search when looking up forcewake domains
1a71a14 drm/i915: Sort forcewake mapping tables
d34328e drm/i915: Data driven register to forcewake domains lookup
82e0e23 drm/i915: Do not inline forcewake taking in mmio accessors
920037b drm/i915: Keep track of active forcewake domains in a bitmask
e6741b5 drm/i915: Remove redundant hsw_write* mmio functions

Results look good. If everyone is happy we could merge this.

Hmm, ivb a sporadic fail? That both died is a bit concerning, but
https://patchwork.freedesktop.org/series/13264/ is happy, right?


Yes, and also they did not both die, one was just over the allocated 
time for the run. Same with the two SKLs. So perhaps we are close to the 
cut off with the whole suite again.



Lgtm.


Cool, thanks.

Joonas what do you think, worth merging on balance?

Regards,

Tvrtko

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

[Chris Wilson]

On Tue, Oct 04, 2016 at 09:46:50AM +0100, Tvrtko Ursulin wrote:
> On 03/10/2016 10:27, Patchwork wrote:
> >fi-bdw-5557u total:236  pass:220  dwarn:0   dfail:0   fail:0   skip:15
> >fi-bxt-t5700 total:236  pass:205  dwarn:0   dfail:0   fail:0   skip:30
> >fi-byt-j1900 total:236  pass:202  dwarn:1   dfail:0   fail:1   skip:31
> >fi-byt-n2820 total:245  pass:208  dwarn:0   dfail:0   fail:2   skip:35
> >fi-hsw-4770  total:236  pass:213  dwarn:0   dfail:0   fail:0   skip:22
> >fi-hsw-4770r total:245  pass:222  dwarn:0   dfail:0   fail:1   skip:22
> >fi-ilk-650   total:236  pass:173  dwarn:0   dfail:0   fail:2   skip:60
> >fi-skl-6700k total:236  pass:209  dwarn:2   dfail:0   fail:0   skip:24
> >fi-skl-6770hqtotal:245  pass:228  dwarn:1   dfail:0   fail:2   skip:14
> >fi-snb-2520m total:245  pass:208  dwarn:0   dfail:0   fail:1   skip:36
> >fi-snb-2600  total:236  pass:198  dwarn:0   dfail:0   fail:0   skip:37
> >fi-ivb-3520m failed to connect after reboot
> >fi-ivb-3770 failed to collect. IGT log at Patchwork_2612/fi-ivb-3770/igt.log
> >fi-skl-6260u failed to collect. IGT log at 
> >Patchwork_2612/fi-skl-6260u/igt.log
> >fi-skl-6700hq failed to collect. IGT log at 
> >Patchwork_2612/fi-skl-6700hq/igt.log
> >
> >Results at /archive/results/CI_IGT_test/Patchwork_2612/
> >
> >d0534bd0217c83c083ba146b9c987e19b219e0e4 drm-intel-nightly: 
> >2016y-09m-30d-10h-31m-00s UTC integration manifest
> >c5237e5 drm/i915: Inline binary search
> >9b4e3c9 drm/i915: Use binary search when looking for shadowed registers
> >0b12dbd drm/i915: Sort the shadow register table
> >7978e69 drm/i915: Remove identical write mmmio functions
> >b0960d1 drm/i915: Remove identical mmio read functions
> >354b09a drm/i915: Remove identical macros
> >e608845 drm/i915: Store the active forcewake range table pointer
> >79f3cb4 drm/i915: Eliminate Gen9 special case
> >7fe1499 drm/i915: Use binary search when looking up forcewake domains
> >1a71a14 drm/i915: Sort forcewake mapping tables
> >d34328e drm/i915: Data driven register to forcewake domains lookup
> >82e0e23 drm/i915: Do not inline forcewake taking in mmio accessors
> >920037b drm/i915: Keep track of active forcewake domains in a bitmask
> >e6741b5 drm/i915: Remove redundant hsw_write* mmio functions
> 
> Results look good. If everyone is happy we could merge this.

Hmm, ivb a sporadic fail? That both died is a bit concerning, but
https://patchwork.freedesktop.org/series/13264/ is happy, right?

Lgtm.
-Chris

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Forcewake binary search & code shrink (rev6)

[Tvrtko Ursulin]

On 03/10/2016 10:27, Patchwork wrote:

== Series Details ==

Series: Forcewake binary search & code shrink (rev6)
URL   : https://patchwork.freedesktop.org/series/13080/
State : warning

== Summary ==

Series 13080v6 Forcewake binary search & code shrink
https://patchwork.freedesktop.org/api/1.0/series/13080/revisions/6/mbox/

Test kms_pipe_crc_basic:
 Subgroup nonblocking-crc-pipe-b:
 pass   -> DMESG-WARN (fi-skl-6700k)


Test passed but kernel logged:

[  520.080543] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU 
pipe B FIFO underrun

Sporadically happening since CI_DRM_1645.

Raised new bug https://bugs.freedesktop.org/show_bug.cgi?id=98041


 Subgroup suspend-read-crc-pipe-a:
 pass   -> DMESG-WARN (fi-byt-j1900)


Test passes but kernel error is logged:

[  626.726086] [drm:intel_dp_aux_ch] *ERROR* dp_aux_ch not done status 
0x0005


Happening since mid-September, build CI_DRM_1635.

Raised new https://bugs.freedesktop.org/show_bug.cgi?id=98040


fi-bdw-5557u total:236  pass:220  dwarn:0   dfail:0   fail:0   skip:15
fi-bxt-t5700 total:236  pass:205  dwarn:0   dfail:0   fail:0   skip:30
fi-byt-j1900 total:236  pass:202  dwarn:1   dfail:0   fail:1   skip:31
fi-byt-n2820 total:245  pass:208  dwarn:0   dfail:0   fail:2   skip:35
fi-hsw-4770  total:236  pass:213  dwarn:0   dfail:0   fail:0   skip:22
fi-hsw-4770r total:245  pass:222  dwarn:0   dfail:0   fail:1   skip:22
fi-ilk-650   total:236  pass:173  dwarn:0   dfail:0   fail:2   skip:60
fi-skl-6700k total:236  pass:209  dwarn:2   dfail:0   fail:0   skip:24
fi-skl-6770hqtotal:245  pass:228  dwarn:1   dfail:0   fail:2   skip:14
fi-snb-2520m total:245  pass:208  dwarn:0   dfail:0   fail:1   skip:36
fi-snb-2600  total:236  pass:198  dwarn:0   dfail:0   fail:0   skip:37
fi-ivb-3520m failed to connect after reboot
fi-ivb-3770 failed to collect. IGT log at Patchwork_2612/fi-ivb-3770/igt.log
fi-skl-6260u failed to collect. IGT log at Patchwork_2612/fi-skl-6260u/igt.log
fi-skl-6700hq failed to collect. IGT log at Patchwork_2612/fi-skl-6700hq/igt.log

Results at /archive/results/CI_IGT_test/Patchwork_2612/

d0534bd0217c83c083ba146b9c987e19b219e0e4 drm-intel-nightly: 
2016y-09m-30d-10h-31m-00s UTC integration manifest
c5237e5 drm/i915: Inline binary search
9b4e3c9 drm/i915: Use binary search when looking for shadowed registers
0b12dbd drm/i915: Sort the shadow register table
7978e69 drm/i915: Remove identical write mmmio functions
b0960d1 drm/i915: Remove identical mmio read functions
354b09a drm/i915: Remove identical macros
e608845 drm/i915: Store the active forcewake range table pointer
79f3cb4 drm/i915: Eliminate Gen9 special case
7fe1499 drm/i915: Use binary search when looking up forcewake domains
1a71a14 drm/i915: Sort forcewake mapping tables
d34328e drm/i915: Data driven register to forcewake domains lookup
82e0e23 drm/i915: Do not inline forcewake taking in mmio accessors
920037b drm/i915: Keep track of active forcewake domains in a bitmask
e6741b5 drm/i915: Remove redundant hsw_write* mmio functions


Results look good. If everyone is happy we could merge this.

Regards,

Tvrtko

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[Intel-gfx] [PATCH] drm/dp/i915: Enable audio codec after the HDA audio driver is initialized

[Dhinakaran Pandiyan]

This fixes the underruns that are seen in DP MST multi-monitor
setups when audio is enabled with
commit 3708d5e082c3 ("drm/i915: start adding dp mst audio"). The underruns
triggered continuous cycles of display on/off cycles.

Signed-off-by: Dhinakaran Pandiyan 
Cc: Libin Yang 
Cc: Ville Syrjälä 
Cc: Jani Nikula 
Cc: Zanoni, Paulo R 
---
Not exactly sure why this works for me, but I am sending this patch to get
some feedback in case the idea is completely wrong. In the meantime, I
will try to get some testing done on platforms other than SKL.

 drivers/gpu/drm/i915/intel_audio.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 9583f43..3f4e741 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -497,6 +497,9 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
if (!connector)
return;
 
+   if (!acomp)
+   return;
+
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 connector->base.id,
 connector->name,
@@ -546,6 +549,9 @@ void intel_audio_codec_disable(struct intel_encoder 
*intel_encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
enum pipe pipe = crtc->pipe;
 
+   if (!acomp)
+   return;
+
if (dev_priv->display.audio_codec_disable)
dev_priv->display.audio_codec_disable(intel_encoder);
 
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

[Patchwork]

== Series Details ==

Series: drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together
URL   : https://patchwork.freedesktop.org/series/13262/
State : success

== Summary ==

Series 13262v1 drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs 
together
https://patchwork.freedesktop.org/api/1.0/series/13262/revisions/1/mbox/

Test gem_busy:
Subgroup basic-hang-default:
fail   -> PASS   (fi-hsw-4770r)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2617/

981382a8204271db3e29da9929625e26f251fadf drm-intel-nightly: 
2016y-10m-04d-06h-31m-31s UTC integration manifest
e41ad3d drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

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Re: [Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

[Chris Wilson]

On Tue, Oct 04, 2016 at 10:53:48AM +0300, Jani Nikula wrote:
> Move the outcast intel_fbdev_output_poll_changed() stub for
> CONFIG_DRM_FBDEV_EMULATION=n next to its friends.
> 
> Signed-off-by: Jani Nikula 
Reviewed-by: Chris Wilson 
-Chris

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[Intel-gfx] [PATCH] drm/i915: keep CONFIG_DRM_FBDEV_EMULATION=n function stubs together

[Jani Nikula]

Move the outcast intel_fbdev_output_poll_changed() stub for
CONFIG_DRM_FBDEV_EMULATION=n next to its friends.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_display.c | 6 --
 drivers/gpu/drm/i915/intel_drv.h | 4 
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0b1ca67fd14c..a366656bcec5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15837,12 +15837,6 @@ intel_user_framebuffer_create(struct drm_device *dev,
return fb;
 }
 
-#ifndef CONFIG_DRM_FBDEV_EMULATION
-static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
-{
-}
-#endif
-
 static const struct drm_mode_config_funcs intel_mode_funcs = {
.fb_create = intel_user_framebuffer_create,
.output_poll_changed = intel_fbdev_output_poll_changed,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0d5ddb7cb94f..f48e79ae2ac6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1488,6 +1488,10 @@ static inline void intel_fbdev_set_suspend(struct 
drm_device *dev, int state, bo
 {
 }
 
+static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
+{
+}
+
 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 {
 }
-- 
2.1.4

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: KBL - Recommended buffer translation programming for DisplayPort

[Jani Nikula]

On Tue, 04 Oct 2016, "Vivi, Rodrigo"  wrote:
> On Mon, 2016-10-03 at 13:50 +0300, Jani Nikula wrote:
>> On Fri, 30 Sep 2016, Rodrigo Vivi  wrote:
>> > According to spec: "KBL re-uses SKL values, except where
>> > specific KBL values are listed."
>> >
>> > And recently spec has changed adding different table for Display Port only.
>> > But for all SKUs (H,S,U,Y) we have slightly different values.
>> >
>> > Cc: Manasi Navare 
>> > Cc: Arthur Runyan 
>> > Signed-off-by: Rodrigo Vivi 
>> > ---
>> >  drivers/gpu/drm/i915/intel_ddi.c | 88 
>> > +++-
>> >  1 file changed, 78 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
>> > b/drivers/gpu/drm/i915/intel_ddi.c
>> > index 018964b..1573360 100644
>> > --- a/drivers/gpu/drm/i915/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> > @@ -167,8 +167,47 @@ static const struct ddi_buf_trans 
>> > skl_y_ddi_translations_dp[] = {
>> >{ 0x80005012, 0x00C0, 0x3 },
>> >  };
>> >  
>> > +/* Kabylake H and S */
>> > +static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
>> > +  { 0x2016, 0x00A0, 0x0 },
>> > +  { 0x5012, 0x009B, 0x0 },
>> > +  { 0x7011, 0x0088, 0x0 },
>> > +  { 0x80009010, 0x00C0, 0x1 },
>> > +  { 0x2016, 0x009B, 0x0 },
>> > +  { 0x5012, 0x0088, 0x0 },
>> > +  { 0x80007011, 0x00C0, 0x1 },
>> > +  { 0x2016, 0x009F, 0x0 },
>> > +  { 0x80005012, 0x00C0, 0x1 },
>> > +};
>> > +
>> > +/* Kabylake U */
>> > +static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
>> > +  { 0x201B, 0x00A1, 0x0 },
>> > +  { 0x5012, 0x0088, 0x0 },
>> > +  { 0x80007011, 0x00CD, 0x3 },
>> > +  { 0x80009010, 0x00C0, 0x3 },
>> > +  { 0x201B, 0x009D, 0x0 },
>> > +  { 0x80005012, 0x00C0, 0x3 },
>> > +  { 0x80007011, 0x00C0, 0x3 },
>> > +  { 0x2016, 0x004F, 0x0 },
>> > +  { 0x80005012, 0x00C0, 0x3 },
>> > +};
>> > +
>> > +/* Kabylake Y */
>> > +static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
>> > +  { 0x1017, 0x00A1, 0x0 },
>> > +  { 0x5012, 0x0088, 0x0 },
>> > +  { 0x80007011, 0x00CD, 0x3 },
>> > +  { 0x8000800F, 0x00C0, 0x3 },
>> > +  { 0x1017, 0x009D, 0x0 },
>> > +  { 0x80005012, 0x00C0, 0x3 },
>> > +  { 0x80007011, 0x00C0, 0x3 },
>> > +  { 0x1017, 0x004C, 0x0 },
>> > +  { 0x80005012, 0x00C0, 0x3 },
>> > +};
>> > +
>> >  /*
>> > - * Skylake H and S
>> > + * Skylake/Kabylake H and S
>> >   * eDP 1.4 low vswing translation parameters
>> >   */
>> >  static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
>> > @@ -185,7 +224,7 @@ static const struct ddi_buf_trans 
>> > skl_ddi_translations_edp[] = {
>> >  };
>> >  
>> >  /*
>> > - * Skylake U
>> > + * Skylake/Kabylake U
>> >   * eDP 1.4 low vswing translation parameters
>> >   */
>> >  static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
>> > @@ -202,7 +241,7 @@ static const struct ddi_buf_trans 
>> > skl_u_ddi_translations_edp[] = {
>> >  };
>> >  
>> >  /*
>> > - * Skylake Y
>> > + * Skylake/Kabylake Y
>> >   * eDP 1.4 low vswing translation parameters
>> >   */
>> >  static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
>> > @@ -218,7 +257,7 @@ static const struct ddi_buf_trans 
>> > skl_y_ddi_translations_edp[] = {
>> >{ 0x0018, 0x008A, 0x0 },
>> >  };
>> >  
>> > -/* Skylake U, H and S */
>> > +/* Skylake/Kabylake U, H and S */
>> >  static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
>> >{ 0x0018, 0x00AC, 0x0 },
>> >{ 0x5012, 0x009D, 0x0 },
>> > @@ -233,7 +272,7 @@ static const struct ddi_buf_trans 
>> > skl_ddi_translations_hdmi[] = {
>> >{ 0x8018, 0x00C0, 0x1 },
>> >  };
>> >  
>> > -/* Skylake Y */
>> > +/* Skylake/Kabylake Y */
>> >  static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
>> >{ 0x0018, 0x00A1, 0x0 },
>> >{ 0x5012, 0x00DF, 0x0 },
>> > @@ -334,10 +373,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private 
>> > *dev_priv, int *n_entries)
>> >  static const struct ddi_buf_trans *
>> >  skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
>> >  {
>> > -  if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
>> > +  if (IS_SKL_ULX(dev_priv)) {
>> >*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
>> >return skl_y_ddi_translations_dp;
>> > -  } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
>> > +  } else if (IS_SKL_ULT(dev_priv)) {
>> >*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
>> >return skl_u_ddi_translations_dp;
>> >} else {
>> > @@ -347,6 +386,21 @@ skl_get_buf_trans_dp(struct drm_i915_private 
>> > *dev_priv, int *n_entries)
>> >  }
>> >  
>> >  static const struct ddi_buf_trans *
>> >