Re: [Intel-gfx] [PATCH 02/10] mm: remove write/force parameters from __get_user_pages_unlocked()
On 13/10/2016 02:20, Lorenzo Stoakes wrote:
> This patch removes the write and force parameters from
> __get_user_pages_unlocked() to make the use of FOLL_FORCE explicit in callers
> as
> use of this flag can result in surprising behaviour (and hence bugs) within
> the
> mm subsystem.
>
> Signed-off-by: Lorenzo Stoakes
> ---
> include/linux/mm.h | 3 +--
> mm/gup.c | 17 +
> mm/nommu.c | 12 +---
> mm/process_vm_access.c | 7 +--
> virt/kvm/async_pf.c| 3 ++-
> virt/kvm/kvm_main.c| 11 ---
> 6 files changed, 34 insertions(+), 19 deletions(-)
>
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index e9caec6..2db98b6 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -1285,8 +1285,7 @@ long get_user_pages_locked(unsigned long start,
> unsigned long nr_pages,
> int write, int force, struct page **pages, int *locked);
> long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
> unsigned long start, unsigned long nr_pages,
> -int write, int force, struct page **pages,
> -unsigned int gup_flags);
> +struct page **pages, unsigned int gup_flags);
> long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
> int write, int force, struct page **pages);
> int get_user_pages_fast(unsigned long start, int nr_pages, int write,
> diff --git a/mm/gup.c b/mm/gup.c
> index ba83942..3d620dd 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -865,17 +865,11 @@ EXPORT_SYMBOL(get_user_pages_locked);
> */
> __always_inline long __get_user_pages_unlocked(struct task_struct *tsk,
> struct mm_struct *mm,
> unsigned long start, unsigned
> long nr_pages,
> -int write, int force, struct
> page **pages,
> -unsigned int gup_flags)
> +struct page **pages, unsigned
> int gup_flags)
> {
> long ret;
> int locked = 1;
>
> - if (write)
> - gup_flags |= FOLL_WRITE;
> - if (force)
> - gup_flags |= FOLL_FORCE;
> -
> down_read(&mm->mmap_sem);
> ret = __get_user_pages_locked(tsk, mm, start, nr_pages, pages, NULL,
> &locked, false, gup_flags);
> @@ -905,8 +899,15 @@ EXPORT_SYMBOL(__get_user_pages_unlocked);
> long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
>int write, int force, struct page **pages)
> {
> + unsigned int flags = FOLL_TOUCH;
> +
> + if (write)
> + flags |= FOLL_WRITE;
> + if (force)
> + flags |= FOLL_FORCE;
> +
> return __get_user_pages_unlocked(current, current->mm, start, nr_pages,
> - write, force, pages, FOLL_TOUCH);
> + pages, flags);
> }
> EXPORT_SYMBOL(get_user_pages_unlocked);
>
> diff --git a/mm/nommu.c b/mm/nommu.c
> index 95daf81..925dcc1 100644
> --- a/mm/nommu.c
> +++ b/mm/nommu.c
> @@ -185,8 +185,7 @@ EXPORT_SYMBOL(get_user_pages_locked);
>
> long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
> unsigned long start, unsigned long nr_pages,
> -int write, int force, struct page **pages,
> -unsigned int gup_flags)
> +struct page **pages, unsigned int gup_flags)
> {
> long ret;
> down_read(&mm->mmap_sem);
> @@ -200,8 +199,15 @@ EXPORT_SYMBOL(__get_user_pages_unlocked);
> long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
>int write, int force, struct page **pages)
> {
> + unsigned int flags = 0;
> +
> + if (write)
> + flags |= FOLL_WRITE;
> + if (force)
> + flags |= FOLL_FORCE;
> +
> return __get_user_pages_unlocked(current, current->mm, start, nr_pages,
> - write, force, pages, 0);
> + pages, flags);
> }
> EXPORT_SYMBOL(get_user_pages_unlocked);
>
> diff --git a/mm/process_vm_access.c b/mm/process_vm_access.c
> index 07514d4..be8dc8d 100644
> --- a/mm/process_vm_access.c
> +++ b/mm/process_vm_access.c
> @@ -88,12 +88,16 @@ static int process_vm_rw_single_vec(unsigned long addr,
> ssize_t rc = 0;
> unsigned long max_pages_per_loop = PVM_MAX_KMALLOC_PAGES
> / sizeof(struct pages *);
> + unsigned int flags = FOLL_REMOTE;
>
> /* Work out address and page range required */
> if (len == 0)
> return 0;
> nr_pages = (addr + len - 1) / PAGE_SIZE - addr / PAGE_SIZE + 1;
>
> + if (vm_write)
> + flag
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode
On Thu, Oct 13, 2016 at 06:05:51AM +, Saarinen, Jani wrote: > > == Summary == > > > > Series 13663v1 Series without cover letter > > https://patchwork.freedesktop.org/api/1.0/series/13663/revisions/1/mbox/ > > > > Test core_auth: > > Subgroup basic-auth: > > pass -> INCOMPLETE (fi-bsw-n3050) > running: igt/core_auth/basic-auth > [000/248] > And then system just hanged. Re-test maybe. Fix CI. The machine oopsed, this should be reported. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Sanitory checks for platform that dont have GuC (rev3)
> == Series Details ==
>
> Series: drm/i915/guc: Sanitory checks for platform that dont have GuC (rev3)
> URL : https://patchwork.freedesktop.org/series/13358/
> State : failure
>
> == Summary ==
>
> Series 13358v3 drm/i915/guc: Sanitory checks for platform that dont have
> GuC
> https://patchwork.freedesktop.org/api/1.0/series/13358/revisions/3/mbox/
>
> Test drv_module_reload_basic:
> skip -> PASS (fi-skl-6770hq)
> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> dmesg-warn -> PASS (fi-skl-6770hq)
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b-frame-sequence:
> pass -> DMESG-WARN (fi-ilk-650)
[drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO
underrun
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO
underrun
> Subgroup suspend-read-crc-pipe-a:
> pass -> DMESG-WARN (fi-ilk-650)
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO
underrun
[drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO
underrun
> pass -> FAIL (fi-ivb-3520m)
rtcwake: wakeup from "mem" using /dev/rtc0 at Wed Oct 12 23:44:55 2016
IGT-Version: 1.16-gdcab159
Stack trace:
#0 [__igt_fail_assert+0x101]
#1 [igt_system_suspend_autoresume+0x9f]
#2 [__real_main183+0x30f]
#3 [main+0x23]
#4 [__libc_start_main+0xf0]
#5 [_start+0x29]
Subtest suspend-read-crc-pipe-A: FAIL (20.295s)
Stderr
rtcwake: write error
(kms_pipe_crc_basic:11232) igt-aux-CRITICAL: Test assertion failure function
igt_system_suspend_autoresume, file igt_aux.c:651:
(kms_pipe_crc_basic:11232) igt-aux-CRITICAL: Failed assertion: system("rtcwake
-s 15 -m mem") == 0
(kms_pipe_crc_basic:11232) igt-aux-CRITICAL: This failure means that something
is wrong with the rtcwake tool or how your distro is set up. This is not a
i915.ko or i-g-t bug.
> Subgroup suspend-read-crc-pipe-b:
> pass -> FAIL (fi-ivb-3520m)
Stdout
rtcwake: wakeup from "mem" using /dev/rtc0 at Wed Oct 12 23:45:16 2016
IGT-Version: 1.16-gdcab159
Stack trace:
#0 [__igt_fail_assert+0x101]
#1 [igt_system_suspend_autoresume+0x9f]
#2 [__real_main183+0x30f]
#3 [main+0x23]
#4 [__libc_start_main+0xf0]
#5 [_start+0x29]
Subtest suspend-read-crc-pipe-B: FAIL (20.263s)
rtcwake: write error
(kms_pipe_crc_basic:11241) igt-aux-CRITICAL: Test assertion failure function
igt_system_suspend_autoresume, file igt_aux.c:651:
(kms_pipe_crc_basic:11241) igt-aux-CRITICAL: Failed assertion: system("rtcwake
-s 15 -m mem") == 0
(kms_pipe_crc_basic:11241) igt-aux-CRITICAL: This failure means that something
is wrong with the rtcwake tool or how your distro is set up. This is not a
i915.ko or i-g-t bug.
> Subgroup suspend-read-crc-pipe-c:
> pass -> FAIL (fi-ivb-3520m)
Stdout
rtcwake: wakeup from "mem" using /dev/rtc0 at Wed Oct 12 23:45:37 2016
IGT-Version: 1.16-gdcab159
Stack trace:
#0 [__igt_fail_assert+0x101]
#1 [igt_system_suspend_autoresume+0x9f]
#2 [__real_main183+0x30f]
#3 [main+0x23]
#4 [__libc_start_main+0xf0]
#5 [_start+0x29]
Subtest suspend-read-crc-pipe-C: FAIL (20.218s)
rtcwake: write error
(kms_pipe_crc_basic:11252) igt-aux-CRITICAL: Test assertion failure function
igt_system_suspend_autoresume, file igt_aux.c:651:
(kms_pipe_crc_basic:11252) igt-aux-CRITICAL: Failed assertion: system("rtcwake
-s 15 -m mem") == 0
(kms_pipe_crc_basic:11252) igt-aux-CRITICAL: This failure means that something
is wrong with the rtcwake tool or how your distro is set up. This is not a
i915.ko or i-g-t bug.
Subtest suspend-read-crc-pipe-C failed.
> Test kms_psr_sink_crc:
> Subgroup psr_basic:
> dmesg-warn -> PASS (fi-skl-6700hq)
> Test vgem_basic:
> Subgroup unload:
> skip -> PASS (fi-kbl-7200u)
> pass -> SKIP (fi-byt-n2820)
> skip -> PASS (fi-hsw-4770)
> Test vgem_reload_basic:
> pass -> FAIL (fi-byt-n2820)
>
> fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16
> fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43
> fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31
> fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32
> fi-byt-n2820 total:248 pass:209 dwarn:0 dfail:0 fail:2 skip:37
> fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23
> fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23
> fi-ilk-650 total:248 pass:183 dwarn:2 dfail:0 fail:2 skip:61
> fi-ivb-3520m total:248 pass:219 dwarn:0 dfail:0 fail:3 skip:26
> fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26
> fi-kbl-7200u total:248
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode
> == Summary == > > Series 13663v1 Series without cover letter > https://patchwork.freedesktop.org/api/1.0/series/13663/revisions/1/mbox/ > > Test core_auth: > Subgroup basic-auth: > pass -> INCOMPLETE (fi-bsw-n3050) running: igt/core_auth/basic-auth [000/248] And then system just hanged. Re-test maybe. > Test drv_module_reload_basic: > pass -> SKIP (fi-skl-6260u) > skip -> PASS (fi-skl-6770hq) > Test kms_flip: > Subgroup basic-flip-vs-modeset: > dmesg-warn -> PASS (fi-skl-6770hq) > Test kms_psr_sink_crc: > Subgroup psr_basic: > dmesg-warn -> PASS (fi-skl-6700hq) > Test vgem_basic: > Subgroup unload: > skip -> PASS (fi-hsw-4770) > pass -> SKIP (fi-skl-6260u) > skip -> PASS (fi-kbl-7200u) > > fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 > fi-bsw-n3050 total:1pass:0dwarn:0 dfail:0 fail:0 skip:0 > fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 > fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 > fi-skl-6260u total:248 pass:231 dwarn:0 dfail:0 fail:0 skip:17 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > > Results at /archive/results/CI_IGT_test/Patchwork_2694/ > > 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m- > 12d-16h-18m-24s UTC integration manifest 944860b drm/i915/gtt: Free > unused lower-level page tables > c6b70f4 drm/i915/gtt: Split gen8_ppgtt_clear_pte_range 8d6718d drm/i915: > Remove unused "valid" parameter from pte_encode > Jani Saarinen ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Sanitory checks for platform that dont have GuC (rev3)
== Series Details == Series: drm/i915/guc: Sanitory checks for platform that dont have GuC (rev3) URL : https://patchwork.freedesktop.org/series/13358/ State : failure == Summary == Series 13358v3 drm/i915/guc: Sanitory checks for platform that dont have GuC https://patchwork.freedesktop.org/api/1.0/series/13358/revisions/3/mbox/ Test drv_module_reload_basic: skip -> PASS (fi-skl-6770hq) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (fi-ilk-650) pass -> FAIL (fi-ivb-3520m) Subgroup suspend-read-crc-pipe-b: pass -> FAIL (fi-ivb-3520m) Subgroup suspend-read-crc-pipe-c: pass -> FAIL (fi-ivb-3520m) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: skip -> PASS (fi-kbl-7200u) pass -> SKIP (fi-byt-n2820) skip -> PASS (fi-hsw-4770) Test vgem_reload_basic: pass -> FAIL (fi-byt-n2820) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:209 dwarn:0 dfail:0 fail:2 skip:37 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:183 dwarn:2 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:219 dwarn:0 dfail:0 fail:3 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2695/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest babaf2a drm/i915/guc: Sanitory checks for platform that dont have GuC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Sanitory checks for platform that dont have GuC
i915.enable_guc_loading/submission=2 forces the usage of GuC.
For platforms that do not have a GuC, asking the kernel to
use a GuC should not result in an error state. Do extra checks
to see if the platform even has a GuC or not, regardless of the
kernel parameter.
v2: Based on Rodrigo's patch and Paulo's suggestion(Paulo, Rodrigo)
v3: Correct the Indentation(Jani, Paulo)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97573
Cc: Rodrigo Vivi
Cc: Zanoni Paulo
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_loader.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96b..811080f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -718,12 +718,16 @@ void intel_guc_init(struct drm_device *dev)
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
- /* A negative value means "use platform default" */
- if (i915.enable_guc_loading < 0)
- i915.enable_guc_loading = HAS_GUC_UCODE(dev);
- if (i915.enable_guc_submission < 0)
- i915.enable_guc_submission = HAS_GUC_SCHED(dev);
-
+ if (!HAS_GUC(dev)) {
+ i915.enable_guc_loading = 0;
+ i915.enable_guc_submission = 0;
+ } else {
+ /* A negative value means "use platform default" */
+ if (i915.enable_guc_loading < 0)
+ i915.enable_guc_loading = HAS_GUC_UCODE(dev);
+ if (i915.enable_guc_submission < 0)
+ i915.enable_guc_submission = HAS_GUC_SCHED(dev);
+ }
if (!HAS_GUC_UCODE(dev)) {
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
--
2.7.4
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Re: [Intel-gfx] [PATCH v2] drm/i915: Allow compaction upto SWIOTLB max segment size
On Wed, Oct 12, 2016 at 05:19:14PM -0400, Konrad Rzeszutek Wilk wrote:
> On Mon, Oct 10, 2016 at 11:27:00PM +0100, Chris Wilson wrote:
> > commit 1625e7e549c5 ("drm/i915: make compact dma scatter lists creation
> > work with SWIOTLB backend") took a heavy handed approach to undo the
> > scatterlist compaction in the face of SWIOTLB. (The compaction hit a bug
> > whereby we tried to pass a segment larger than SWIOTLB could handle.) We
> > can be a little more intelligent and try compacting the scatterlist up
> > to the maximum SWIOTLB segment size (when using SWIOTLB).
> >
>
> Won't this cause a bigger usage of the SWIOTLB bounce buffer ?
It won't change the frequency of the usage of the bounce buffer, if that
is what you mean. Either you have intel-iommu and so will not go through
swiotlb, or you are forced to use swiotlb even though the hw doesn't
require it (swiotlb config is byzantium and always enabled unless you
hack it out and can rejoice at the lower cpu usage).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [CI 3/3] drm/i915/gtt: Free unused lower-level page tables
On Wed, Oct 12, 2016 at 06:47:38PM +0200, Michał Winiarski wrote:
> +static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
> struct i915_page_directory *pd,
> uint64_t start,
> uint64_t length)
> {
> + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> struct i915_page_table *pt;
> uint64_t pde;
> + gen8_pde_t *pde_vaddr;
> + gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt),
> + I915_CACHE_LLC);
> + bool reduce;
>
> gen8_for_each_pde(pt, pd, start, length, pde) {
> if (WARN_ON(!pd->page_table[pde]))
> break;
>
> - gen8_ppgtt_clear_pt(vm, pt, start, length);
> + reduce = gen8_ppgtt_clear_pt(vm, pt, start, length);
> +
> + if (reduce) {
> + __clear_bit(pde, pd->used_pdes);
> + pde_vaddr = kmap_px(pd);
> + pde_vaddr[pde] = scratch_pde;
> + kunmap_px(ppgtt, pde_vaddr);
On !48b (bsw), the pd is only partially set up, it is not backed by a
page, but i915_page_dir_dma_addr() converts the empty bit into the
scratch address instead.
Obnoxiously this requires another if (USES_FULL_48BIT_PPGTT(0)) {}
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH v2] drm/i915: Allow compaction upto SWIOTLB max segment size
On Mon, Oct 10, 2016 at 11:27:00PM +0100, Chris Wilson wrote:
> commit 1625e7e549c5 ("drm/i915: make compact dma scatter lists creation
> work with SWIOTLB backend") took a heavy handed approach to undo the
> scatterlist compaction in the face of SWIOTLB. (The compaction hit a bug
> whereby we tried to pass a segment larger than SWIOTLB could handle.) We
> can be a little more intelligent and try compacting the scatterlist up
> to the maximum SWIOTLB segment size (when using SWIOTLB).
>
Won't this cause a bigger usage of the SWIOTLB bounce buffer ?
> v2: Tidy sg_mark_end() and cpp
>
> Signed-off-by: Chris Wilson
> CC: Imre Deak
> CC: Daniel Vetter
> Cc: Konrad Rzeszutek Wilk
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_gem.c | 30 ++
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index dff8d05d80ee..50fd611926cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2201,6 +2201,15 @@ unlock:
> mutex_unlock(&obj->mm.lock);
> }
>
> +static unsigned long swiotlb_max_size(void)
> +{
> +#if IS_ENABLED(CONFIG_SWIOTLB)
> + return swiotlb_nr_tbl() << IO_TLB_SHIFT;
> +#else
> + return 0;
> +#endif
> +}
> +
> static struct sg_table *
> i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
> {
> @@ -2212,6 +2221,7 @@ i915_gem_object_get_pages_gtt(struct
> drm_i915_gem_object *obj)
> struct sgt_iter sgt_iter;
> struct page *page;
> unsigned long last_pfn = 0; /* suppress gcc warning */
> + unsigned long max_segment;
> int ret;
> gfp_t gfp;
>
> @@ -,6 +2232,10 @@ i915_gem_object_get_pages_gtt(struct
> drm_i915_gem_object *obj)
> GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
> GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
>
> + max_segment = swiotlb_max_size();
> + if (!max_segment)
> + max_segment = obj->base.size;
> +
> st = kmalloc(sizeof(*st), GFP_KERNEL);
> if (st == NULL)
> return ERR_PTR(-ENOMEM);
> @@ -2263,15 +2277,9 @@ i915_gem_object_get_pages_gtt(struct
> drm_i915_gem_object *obj)
> goto err_pages;
> }
> }
> -#ifdef CONFIG_SWIOTLB
> - if (swiotlb_nr_tbl()) {
> - st->nents++;
> - sg_set_page(sg, page, PAGE_SIZE, 0);
> - sg = sg_next(sg);
> - continue;
> - }
> -#endif
> - if (!i || page_to_pfn(page) != last_pfn + 1) {
> + if (!i ||
> + sg->length >= max_segment ||
> + page_to_pfn(page) != last_pfn + 1) {
> if (i)
> sg = sg_next(sg);
> st->nents++;
> @@ -2284,9 +2292,7 @@ i915_gem_object_get_pages_gtt(struct
> drm_i915_gem_object *obj)
> /* Check that the i965g/gm workaround works. */
> WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x0010UL));
> }
> -#ifdef CONFIG_SWIOTLB
> - if (!swiotlb_nr_tbl())
> -#endif
> + if (sg) /* loop terminated early; short sg table */
> sg_mark_end(sg);
>
> ret = i915_gem_gtt_prepare_pages(obj, st);
> --
> 2.9.3
>
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode
== Series Details == Series: series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode URL : https://patchwork.freedesktop.org/series/13663/ State : failure == Summary == Series 13663v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/13663/revisions/1/mbox/ Test core_auth: Subgroup basic-auth: pass -> INCOMPLETE (fi-bsw-n3050) Test drv_module_reload_basic: pass -> SKIP (fi-skl-6260u) skip -> PASS (fi-skl-6770hq) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: skip -> PASS (fi-hsw-4770) pass -> SKIP (fi-skl-6260u) skip -> PASS (fi-kbl-7200u) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:1pass:0dwarn:0 dfail:0 fail:0 skip:0 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:231 dwarn:0 dfail:0 fail:0 skip:17 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2694/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest 944860b drm/i915/gtt: Free unused lower-level page tables c6b70f4 drm/i915/gtt: Split gen8_ppgtt_clear_pte_range 8d6718d drm/i915: Remove unused "valid" parameter from pte_encode ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Add support for Legacy Hdmi audio
> == Series Details == > > Series: Add support for Legacy Hdmi audio > URL : https://patchwork.freedesktop.org/series/13661/ > State : warning > > == Summary == > > Series 13661v1 Add support for Legacy Hdmi audio > https://patchwork.freedesktop.org/api/1.0/series/13661/revisions/1/mbox/ > > Test drv_module_reload_basic: > skip -> PASS (fi-skl-6770hq) > Test kms_flip: > Subgroup basic-flip-vs-dpms: > pass -> DMESG-WARN (fi-snb-2520m) [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 236 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 236 > Subgroup basic-flip-vs-modeset: > dmesg-warn -> PASS (fi-skl-6770hq) > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-a: > pass -> DMESG-WARN (fi-ilk-650) [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO underrun [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun > Test kms_psr_sink_crc: > Subgroup psr_basic: > dmesg-warn -> PASS (fi-skl-6700hq) > Test vgem_basic: > Subgroup unload: > skip -> PASS (fi-hsw-4770) > skip -> PASS (fi-kbl-7200u) > > fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 > fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 > fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 > fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:210 dwarn:1 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > fi-bxt-t5700 failed to collect. IGT log at Patchwork_2693/fi-bxt-t5700/igt.log > > Results at /archive/results/CI_IGT_test/Patchwork_2693/ > > 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m- > 12d-16h-18m-24s UTC integration manifest f326d3c hdmi_audio: continue > audio playback even when display resolution changes > 4a31c16 hdmi_audio: Fixup some monitor > 0f6f765 hdmi_audio: Improve position reporting Using a hw register to > calculate sub-period position reports. > 98ed9c5 drm/i915: Add support for audio driver notifications > f5a7592 drm/i915: Add support for enabling/disabling hdmi audio interrupts > c8bed7a ALSA: Add support for hdmi audio driver > d8bab54 ALSA: add shell for Intel HDMI LPE audio driver > daa4014 drm/i915: setup bridge for HDMI LPE audio driver Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for Add support for Legacy Hdmi audio
== Series Details == Series: Add support for Legacy Hdmi audio URL : https://patchwork.freedesktop.org/series/13661/ State : warning == Summary == Series 13661v1 Add support for Legacy Hdmi audio https://patchwork.freedesktop.org/api/1.0/series/13661/revisions/1/mbox/ Test drv_module_reload_basic: skip -> PASS (fi-skl-6770hq) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (fi-snb-2520m) Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-a: pass -> DMESG-WARN (fi-ilk-650) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: skip -> PASS (fi-hsw-4770) skip -> PASS (fi-kbl-7200u) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:210 dwarn:1 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 fi-bxt-t5700 failed to collect. IGT log at Patchwork_2693/fi-bxt-t5700/igt.log Results at /archive/results/CI_IGT_test/Patchwork_2693/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest f326d3c hdmi_audio: continue audio playback even when display resolution changes 4a31c16 hdmi_audio: Fixup some monitor 0f6f765 hdmi_audio: Improve position reporting Using a hw register to calculate sub-period position reports. 98ed9c5 drm/i915: Add support for audio driver notifications f5a7592 drm/i915: Add support for enabling/disabling hdmi audio interrupts c8bed7a ALSA: Add support for hdmi audio driver d8bab54 ALSA: add shell for Intel HDMI LPE audio driver daa4014 drm/i915: setup bridge for HDMI LPE audio driver ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
On Wed, 2016-10-12 at 14:06 +0200, Paul Bolle wrote: > That might take some time. Because bisecting always takes a long time > and especially since hitting this WARNING sometimes takes over an hour. > Anyhow, please prod me if I stay silent for too long. For the record: I just had to power cycle this laptop because it got into that lovely state where it just locks without accepting any input (no, I don't have netconsole enabled). Assuming this lockup is related: this could be more urgent than I thought. Paul Bolle ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Support for sustained capturing of GuC firmware logs (rev11)
> == Series Details == > > Series: Support for sustained capturing of GuC firmware logs (rev11) > URL : https://patchwork.freedesktop.org/series/7910/ > State : warning > > == Summary == > > Series 7910v11 Support for sustained capturing of GuC firmware logs > https://patchwork.freedesktop.org/api/1.0/series/7910/revisions/11/mbox/ > > Test drv_module_reload_basic: > skip -> PASS (fi-skl-6770hq) > Test kms_flip: > Subgroup basic-flip-vs-modeset: > dmesg-warn -> PASS (fi-skl-6770hq) > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-c: > pass -> DMESG-WARN (fi-ivb-3770) [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 215 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 215 > Test kms_psr_sink_crc: > Subgroup psr_basic: > dmesg-warn -> PASS (fi-skl-6700hq) > Test vgem_basic: > Subgroup unload: > skip -> PASS (fi-kbl-7200u) > skip -> PASS (fi-hsw-4770) > > fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 > fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 > fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 > fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 > fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > > Results at /archive/results/CI_IGT_test/Patchwork_2691/ > > 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m- > 12d-16h-18m-24s UTC integration manifest a590f8c drm/i915: Mark the GuC > log buffer flush interrupts handling WQ as freezable a001c3d drm/i915: Early > creation of relay channel for capturing boot time logs af3ee1c drm/i915: Use > SSE4.1 movntdqa based memcpy for sampling GuC log buffer > fbbd457 drm/i915: Debugfs support for GuC logging control 656513f > drm/i915: Support for forceful flush of GuC log buffer a68d17f drm/i915: > Augment i915 error state to include the dump of GuC log buffer da8274a > drm/i915: Increase GuC log buffer size to reduce flush interrupts > 4f24c12 drm/i915: Optimization to reduce the sampling time of GuC log > buffer > 4739ad8 drm/i915: Add stats for GuC log buffer flush interrupts > 2e8c052 drm/i915: New lock to serialize the Host2GuC actions 954e48b > drm/i915: Add a relay backed debugfs interface for capturing GuC logs > 23a81bb relay: Use per CPU constructs for the relay channel buffer pointers > 8fd01d3 drm/i915: Handle log buffer flush interrupt event from GuC > 44610d4 drm/i915: Support for GuC interrupts > 05ede72 drm/i915: Add low level set of routines for programming PM > IER/IIR/IMR register set ffbd48f drm/i915: New structure to contain GuC > logging related fields 317ba9e drm/i915: Add GuC ukernel logging related > fields to fw interface file > 4832507 drm/i915: Decouple GuC log setup from verbosity parameter > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/hsw: Fix GPU hang during resume from S3-devices state
> == Series Details == > > Series: drm/i915/hsw: Fix GPU hang during resume from S3-devices state > URL : https://patchwork.freedesktop.org/series/13654/ > State : warning > > == Summary == > > Series 13654v1 drm/i915/hsw: Fix GPU hang during resume from S3-devices > state > https://patchwork.freedesktop.org/api/1.0/series/13654/revisions/1/mbox/ > > Test drv_module_reload_basic: > skip -> PASS (fi-skl-6770hq) > Test kms_cursor_legacy: > Subgroup basic-flip-after-cursor-legacy: > pass -> DMESG-WARN (fi-ivb-3770) [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 144 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 144 > Test kms_flip: > Subgroup basic-flip-vs-modeset: > dmesg-warn -> PASS (fi-skl-6770hq) > Test kms_pipe_crc_basic: > Subgroup suspend-read-crc-pipe-b: > dmesg-warn -> PASS (fi-byt-j1900) > Test kms_psr_sink_crc: > Subgroup psr_basic: > dmesg-warn -> PASS (fi-skl-6700hq) > Test vgem_basic: > Subgroup unload: > pass -> SKIP (fi-bdw-5557u) > skip -> PASS (fi-hsw-4770) > > fi-bdw-5557u total:248 pass:231 dwarn:0 dfail:0 fail:0 skip:17 > fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 > fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 > fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > > Results at /archive/results/CI_IGT_test/Patchwork_2690/ > > 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m- > 12d-16h-18m-24s UTC integration manifest > 78a5d29 drm/i915/hsw: Fix GPU hang during resume from S3-devices state > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Treat a framebuffer reference as an active reference whilst shrinking
> == Series Details == > > Series: drm/i915: Treat a framebuffer reference as an active reference whilst > shrinking > URL : https://patchwork.freedesktop.org/series/13648/ > State : failure > > == Summary == > > Series 13648v1 drm/i915: Treat a framebuffer reference as an active > reference whilst shrinking > https://patchwork.freedesktop.org/api/1.0/series/13648/revisions/1/mbox/ > > Test kms_force_connector_basic: > Subgroup force-connector-state: > pass -> DMESG-WARN (fi-ivb-3770) [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 114 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 114 > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-c-frame-sequence: > pass -> DMESG-WARN (fi-skl-6770hq) [drm:skl_set_cdclk [i915]] *ERROR* failed to inform PCU about cdclk change > Subgroup suspend-read-crc-pipe-a: > dmesg-warn -> PASS (fi-ilk-650) [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO underrun [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun > Test pm_rps: > Subgroup basic-api: > pass -> FAIL (fi-hsw-4770r) (pm_rps:11618) CRITICAL: Test assertion failure function checkit, file pm_rps.c:148: (pm_rps:11618) CRITICAL: Failed assertion: freqs[CUR] <= freqs[MAX] (pm_rps:11618) CRITICAL: Last errno: 22, Invalid argument (pm_rps:11618) CRITICAL: error: 1300 > 750 Subtest basic-api failed. > Test vgem_basic: > Subgroup unload: > skip -> PASS (fi-bdw-5557u) > pass -> SKIP (fi-hsw-4770r) > skip -> PASS (fi-hsw-4770) > Test vgem_reload_basic: > pass -> FAIL (fi-hsw-4770r) > > fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 > fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 > fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 > fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:222 dwarn:0 dfail:0 fail:2 skip:24 > fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 > fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:230 dwarn:2 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > > Results at /archive/results/CI_IGT_test/Patchwork_2688/ > > 4c3e00c4630b732518abf737580d927bb52346fa drm-intel-nightly: 2016y-10m- > 12d-14h-36m-58s UTC integration manifest > 2ac1007 drm/i915: Treat a framebuffer reference as an active reference > whilst shrinking > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Record the current requests queue for execlists upon hang
== Series Details == Series: drm/i915: Record the current requests queue for execlists upon hang URL : https://patchwork.freedesktop.org/series/13660/ State : success == Summary == Series 13660v1 drm/i915: Record the current requests queue for execlists upon hang https://patchwork.freedesktop.org/api/1.0/series/13660/revisions/1/mbox/ Test drv_module_reload_basic: skip -> PASS (fi-skl-6770hq) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: skip -> PASS (fi-kbl-7200u) skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2692/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest 988e045 drm/i915: Record the current requests queue for execlists upon hang ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for Support for sustained capturing of GuC firmware logs (rev11)
== Series Details == Series: Support for sustained capturing of GuC firmware logs (rev11) URL : https://patchwork.freedesktop.org/series/7910/ State : warning == Summary == Series 7910v11 Support for sustained capturing of GuC firmware logs https://patchwork.freedesktop.org/api/1.0/series/7910/revisions/11/mbox/ Test drv_module_reload_basic: skip -> PASS (fi-skl-6770hq) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c: pass -> DMESG-WARN (fi-ivb-3770) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: skip -> PASS (fi-kbl-7200u) skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2691/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest a590f8c drm/i915: Mark the GuC log buffer flush interrupts handling WQ as freezable a001c3d drm/i915: Early creation of relay channel for capturing boot time logs af3ee1c drm/i915: Use SSE4.1 movntdqa based memcpy for sampling GuC log buffer fbbd457 drm/i915: Debugfs support for GuC logging control 656513f drm/i915: Support for forceful flush of GuC log buffer a68d17f drm/i915: Augment i915 error state to include the dump of GuC log buffer da8274a drm/i915: Increase GuC log buffer size to reduce flush interrupts 4f24c12 drm/i915: Optimization to reduce the sampling time of GuC log buffer 4739ad8 drm/i915: Add stats for GuC log buffer flush interrupts 2e8c052 drm/i915: New lock to serialize the Host2GuC actions 954e48b drm/i915: Add a relay backed debugfs interface for capturing GuC logs 23a81bb relay: Use per CPU constructs for the relay channel buffer pointers 8fd01d3 drm/i915: Handle log buffer flush interrupt event from GuC 44610d4 drm/i915: Support for GuC interrupts 05ede72 drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set ffbd48f drm/i915: New structure to contain GuC logging related fields 317ba9e drm/i915: Add GuC ukernel logging related fields to fw interface file 4832507 drm/i915: Decouple GuC log setup from verbosity parameter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/hsw: Fix GPU hang during resume from S3-devices state
== Series Details == Series: drm/i915/hsw: Fix GPU hang during resume from S3-devices state URL : https://patchwork.freedesktop.org/series/13654/ State : warning == Summary == Series 13654v1 drm/i915/hsw: Fix GPU hang during resume from S3-devices state https://patchwork.freedesktop.org/api/1.0/series/13654/revisions/1/mbox/ Test drv_module_reload_basic: skip -> PASS (fi-skl-6770hq) Test kms_cursor_legacy: Subgroup basic-flip-after-cursor-legacy: pass -> DMESG-WARN (fi-ivb-3770) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-j1900) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (fi-skl-6700hq) Test vgem_basic: Subgroup unload: pass -> SKIP (fi-bdw-5557u) skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:231 dwarn:0 dfail:0 fail:0 skip:17 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2690/ 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-12d-16h-18m-24s UTC integration manifest 78a5d29 drm/i915/hsw: Fix GPU hang during resume from S3-devices state ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion
Accidentally sent original view twice and found one more issue after
looking at the rest of them, sorry about that!
On Wed, 2016-10-12 at 13:04 -0400, Lyude wrote:
> Loving this patch so far! Would it be possible to get this split into
> two separate patches though? One for removing skl_results and one for
> programming watermarks as a separate step.
>
> On Wed, 2016-10-12 at 15:28 +0200, Maarten Lankhorst wrote:
> >
> > Instead of running the watermark updates from the callbacks run
> > them from a separate hook atomic_evade_watermarks.
> >
> > This also gets rid of the global skl_results, which was required
> > for
> > keeping track of the current atomic commit.
> >
> > Signed-off-by: Maarten Lankhorst > >
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 7 ---
> > drivers/gpu/drm/i915/intel_display.c | 36 +---
> > --
> >
> > drivers/gpu/drm/i915/intel_drv.h | 7 ---
> > drivers/gpu/drm/i915/intel_pm.c | 38 ++--
> >
> > drivers/gpu/drm/i915/intel_sprite.c | 18 -
> > 5 files changed, 28 insertions(+), 78 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 09588c58148f..28e44cb611b8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2027,13 +2027,6 @@ struct drm_i915_private {
> > */
> > uint16_t skl_latency[8];
> >
> > - /*
> > - * The skl_wm_values structure is a bit too big
> > for
> > stack
> > - * allocation, so we keep the staging struct where
> > we store
> > - * intermediate results here instead.
> > - */
> > - struct skl_wm_values skl_results;
> > -
> > /* current hardware state */
> > union {
> > struct ilk_wm_values hw;
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 340861826c46..d3d7d9dc14a8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3377,9 +3377,6 @@ static void
> > skylake_update_primary_plane(struct
> > drm_plane *plane,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> > >
> > > base.crtc);
> > struct drm_framebuffer *fb = plane_state->base.fb;
> > - const struct skl_wm_values *wm = &dev_priv-
> > >wm.skl_results;
> > - const struct skl_plane_wm *p_wm =
> > - &crtc_state->wm.skl.optimal.planes[0];
> > int pipe = intel_crtc->pipe;
> > u32 plane_ctl;
> > unsigned int rotation = plane_state->base.rotation;
> > @@ -3415,9 +3412,6 @@ static void
> > skylake_update_primary_plane(struct
> > drm_plane *plane,
> > intel_crtc->adjusted_x = src_x;
> > intel_crtc->adjusted_y = src_y;
> >
> > - if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
> > - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
> > -
> > I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> > I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> > I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> > @@ -3450,18 +3444,8 @@ static void
> > skylake_disable_primary_plane(struct drm_plane *primary,
> > struct drm_device *dev = crtc->dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > - struct intel_crtc_state *cstate =
> > to_intel_crtc_state(crtc-
> > >
> > > state);
> > - const struct skl_plane_wm *p_wm = &cstate-
> > >
> > > wm.skl.optimal.planes[0];
> > int pipe = intel_crtc->pipe;
> >
> > - /*
> > - * We only populate skl_results on watermark updates, and
> > if
> > the
> > - * plane's visiblity isn't actually changing neither is
> > its
> > watermarks.
> > - */
> > - if (!crtc->primary->state->visible)
> > - skl_write_plane_wm(intel_crtc, p_wm,
> > - &dev_priv->wm.skl_results.ddb,
> > 0);
> > -
> > I915_WRITE(PLANE_CTL(pipe, 0), 0);
> > I915_WRITE(PLANE_SURF(pipe, 0), 0);
> > POSTING_READ(PLANE_SURF(pipe, 0));
> > @@ -10824,16 +10808,9 @@ static void i9xx_update_cursor(struct
> > drm_crtc *crtc, u32 base,
> > struct drm_device *dev = crtc->dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > - struct intel_crtc_state *cstate =
> > to_intel_crtc_state(crtc-
> > >
> > > state);
> > - const struct skl_wm_values *wm = &dev_priv-
> > >wm.skl_results;
> > - const struct skl_plane_wm *p_wm =
> > - &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
> > int pipe = intel_crtc->pipe;
> > uint32_t cntl = 0;
> >
> > - if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes &
> > drm_crtc_mask(crtc))
> > - skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
> > -
> > if (plane_st
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion
Loving this patch so far! Would it be possible to get this split into
two separate patches though? One for removing skl_results and one for
programming watermarks as a separate step.
On Wed, 2016-10-12 at 15:28 +0200, Maarten Lankhorst wrote:
> Instead of running the watermark updates from the callbacks run
> them from a separate hook atomic_evade_watermarks.
>
> This also gets rid of the global skl_results, which was required for
> keeping track of the current atomic commit.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 ---
> drivers/gpu/drm/i915/intel_display.c | 36 +-
>
> drivers/gpu/drm/i915/intel_drv.h | 7 ---
> drivers/gpu/drm/i915/intel_pm.c | 38 ++--
>
> drivers/gpu/drm/i915/intel_sprite.c | 18 -
> 5 files changed, 28 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 09588c58148f..28e44cb611b8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2027,13 +2027,6 @@ struct drm_i915_private {
> */
> uint16_t skl_latency[8];
>
> - /*
> - * The skl_wm_values structure is a bit too big for
> stack
> - * allocation, so we keep the staging struct where
> we store
> - * intermediate results here instead.
> - */
> - struct skl_wm_values skl_results;
> -
> /* current hardware state */
> union {
> struct ilk_wm_values hw;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 340861826c46..d3d7d9dc14a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3377,9 +3377,6 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
> struct drm_framebuffer *fb = plane_state->base.fb;
> - const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
> - const struct skl_plane_wm *p_wm =
> - &crtc_state->wm.skl.optimal.planes[0];
> int pipe = intel_crtc->pipe;
> u32 plane_ctl;
> unsigned int rotation = plane_state->base.rotation;
> @@ -3415,9 +3412,6 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
> intel_crtc->adjusted_x = src_x;
> intel_crtc->adjusted_y = src_y;
>
> - if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
> - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
> -
> I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> @@ -3450,18 +3444,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> - const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[0];
> int pipe = intel_crtc->pipe;
>
> - /*
> - * We only populate skl_results on watermark updates, and if
> the
> - * plane's visiblity isn't actually changing neither is its
> watermarks.
> - */
> - if (!crtc->primary->state->visible)
> - skl_write_plane_wm(intel_crtc, p_wm,
> - &dev_priv->wm.skl_results.ddb,
> 0);
> -
> I915_WRITE(PLANE_CTL(pipe, 0), 0);
> I915_WRITE(PLANE_SURF(pipe, 0), 0);
> POSTING_READ(PLANE_SURF(pipe, 0));
> @@ -10824,16 +10808,9 @@ static void i9xx_update_cursor(struct
> drm_crtc *crtc, u32 base,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> - const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
> - const struct skl_plane_wm *p_wm =
> - &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
> int pipe = intel_crtc->pipe;
> uint32_t cntl = 0;
>
> - if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes &
> drm_crtc_mask(crtc))
> - skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
> -
> if (plane_state && plane_state->base.visible) {
> cntl = MCURSOR_GAMMA_ENABLE;
> switch (plane_state->base.crtc_w) {
> @@ -14436,8 +14413,13 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> intel_check_cpu_fifo_underruns(dev_priv);
> intel_check_pch_fifo_underruns(dev_priv);
>
> -
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion
Loving this patch so far! Would it be possible to get this split into
two separate patches though? One for removing skl_results and one for
programming watermarks as a separate step.
On Wed, 2016-10-12 at 15:28 +0200, Maarten Lankhorst wrote:
> Instead of running the watermark updates from the callbacks run
> them from a separate hook atomic_evade_watermarks.
>
> This also gets rid of the global skl_results, which was required for
> keeping track of the current atomic commit.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 ---
> drivers/gpu/drm/i915/intel_display.c | 36 +-
>
> drivers/gpu/drm/i915/intel_drv.h | 7 ---
> drivers/gpu/drm/i915/intel_pm.c | 38 ++--
>
> drivers/gpu/drm/i915/intel_sprite.c | 18 -
> 5 files changed, 28 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 09588c58148f..28e44cb611b8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2027,13 +2027,6 @@ struct drm_i915_private {
> */
> uint16_t skl_latency[8];
>
> - /*
> - * The skl_wm_values structure is a bit too big for
> stack
> - * allocation, so we keep the staging struct where
> we store
> - * intermediate results here instead.
> - */
> - struct skl_wm_values skl_results;
> -
> /* current hardware state */
> union {
> struct ilk_wm_values hw;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 340861826c46..d3d7d9dc14a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3377,9 +3377,6 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
> struct drm_framebuffer *fb = plane_state->base.fb;
> - const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
> - const struct skl_plane_wm *p_wm =
> - &crtc_state->wm.skl.optimal.planes[0];
> int pipe = intel_crtc->pipe;
> u32 plane_ctl;
> unsigned int rotation = plane_state->base.rotation;
> @@ -3415,9 +3412,6 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
> intel_crtc->adjusted_x = src_x;
> intel_crtc->adjusted_y = src_y;
>
> - if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
> - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
> -
> I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> @@ -3450,18 +3444,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> - const struct skl_plane_wm *p_wm = &cstate-
> >wm.skl.optimal.planes[0];
> int pipe = intel_crtc->pipe;
>
> - /*
> - * We only populate skl_results on watermark updates, and if
> the
> - * plane's visiblity isn't actually changing neither is its
> watermarks.
> - */
> - if (!crtc->primary->state->visible)
> - skl_write_plane_wm(intel_crtc, p_wm,
> - &dev_priv->wm.skl_results.ddb,
> 0);
> -
> I915_WRITE(PLANE_CTL(pipe, 0), 0);
> I915_WRITE(PLANE_SURF(pipe, 0), 0);
> POSTING_READ(PLANE_SURF(pipe, 0));
> @@ -10824,16 +10808,9 @@ static void i9xx_update_cursor(struct
> drm_crtc *crtc, u32 base,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> - const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
> - const struct skl_plane_wm *p_wm =
> - &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
> int pipe = intel_crtc->pipe;
> uint32_t cntl = 0;
>
> - if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes &
> drm_crtc_mask(crtc))
> - skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
> -
> if (plane_state && plane_state->base.visible) {
> cntl = MCURSOR_GAMMA_ENABLE;
> switch (plane_state->base.crtc_w) {
> @@ -14436,8 +14413,13 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> intel_check_cpu_fifo_underruns(dev_priv);
> intel_check_pch_fifo_underruns(dev_priv);
>
> -
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Respect alternate_ddc_pin for all DDI ports
Retested the _2 branch, works fine as well.
On Wed, Oct 12, 2016 at 12:57 PM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Tue, Oct 11, 2016 at 10:04:00PM +0200, Maarten Maathuis wrote:
> > My name does not include the word "show" (Tested-by tag).
>
> Sorry about that. Some copy-paste fail I suspect. I'll fix it up.
>
> And you actually tested the v1 patches, so I totally forgot to note that
> in the tested-by tags :( Care to re-test these v2 versions, just to make
> sure I didn't seriously fumble anything?
>
> >
> > On Tue, Oct 11, 2016 at 7:52 PM, wrote:
> >
> > > From: Ville Syrjälä
> > >
> > > The VBT provides the platform a way to mix and match the DDI ports vs.
> > > GMBUS pins. Currently we only trust the VBT for DDI E, which I suppose
> > > has no standard GMBUS pin assignment. However, there are machines out
> > > there that use a non-standard mapping for the other ports as well.
> > > Let's start trusting the VBT on this one for all ports on DDI
> platforms.
> > >
> > > I've structured the code such that other platforms could easily start
> > > using this as well, by simply filling in the ddi_port_info. IIRC there
> > > may be CHV system that might actually need this.
> > >
> > > v2: Include a commit message, include a debug message during init
> > >
> > > Cc: sta...@vger.kernel.org
> > > Cc: Maarten Maathuis
> > > Tested-by: Maarten Maatt show huis
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97877
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/intel_hdmi.c | 84 ++
> > > -
> > > 1 file changed, 48 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 8d46f5836746..9ca86e901fc8 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -1799,6 +1799,50 @@ intel_hdmi_add_properties(struct intel_hdmi
> > > *intel_hdmi, struct drm_connector *c
> > > intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> > > }
> > >
> > > +static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
> > > +enum port port)
> > > +{
> > > + const struct ddi_vbt_port_info *info =
> > > + &dev_priv->vbt.ddi_port_info[port];
> > > + u8 ddc_pin;
> > > +
> > > + if (info->alternate_ddc_pin) {
> > > + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
> > > + info->alternate_ddc_pin,
> port_name(port));
> > > + return info->alternate_ddc_pin;
> > > + }
> > > +
> > > + switch (port) {
> > > + case PORT_B:
> > > + if (IS_BROXTON(dev_priv))
> > > + ddc_pin = GMBUS_PIN_1_BXT;
> > > + else
> > > + ddc_pin = GMBUS_PIN_DPB;
> > > + break;
> > > + case PORT_C:
> > > + if (IS_BROXTON(dev_priv))
> > > + ddc_pin = GMBUS_PIN_2_BXT;
> > > + else
> > > + ddc_pin = GMBUS_PIN_DPC;
> > > + break;
> > > + case PORT_D:
> > > + if (IS_CHERRYVIEW(dev_priv))
> > > + ddc_pin = GMBUS_PIN_DPD_CHV;
> > > + else
> > > + ddc_pin = GMBUS_PIN_DPD;
> > > + break;
> > > + default:
> > > + MISSING_CASE(port);
> > > + ddc_pin = GMBUS_PIN_DPB;
> > > + break;
> > > + }
> > > +
> > > + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform
> > > default)\n",
> > > + ddc_pin, port_name(port));
> > > +
> > > + return ddc_pin;
> > > +}
> > > +
> > > void intel_hdmi_init_connector(struct intel_digital_port
> *intel_dig_port,
> > >struct intel_connector *intel_connector)
> > > {
> > > @@ -1808,7 +1852,6 @@ void intel_hdmi_init_connector(struct
> > > intel_digital_port *intel_dig_port,
> > > struct drm_device *dev = intel_encoder->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum port port = intel_dig_port->port;
> > > - uint8_t alternate_ddc_pin;
> > >
> > > DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
> > > port_name(port));
> > > @@ -1826,12 +1869,10 @@ void intel_hdmi_init_connector(struct
> > > intel_digital_port *intel_dig_port,
> > > connector->doublescan_allowed = 0;
> > > connector->stereo_allowed = 1;
> > >
> > > + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
> > > +
> > > switch (port) {
> > > case PORT_B:
> > > - if (IS_BROXTON(dev_priv))
> > > - intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
> > > - else
> > > - intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
> > > /*
> > >
[Intel-gfx] [CI 3/3] drm/i915/gtt: Free unused lower-level page tables
Since "Dynamic page table allocations" were introduced, our page tables
can grow (being dynamically allocated) with address space range usage.
Unfortunately, their lifetime is bound to vm. This is not a huge problem
when we're not using softpin - drm_mm is creating an upper bound on used
range by causing addresses for our VMAs to eventually be reused.
With softpin, long lived contexts can drain the system out of memory
even with a single "small" object. For example:
bo = bo_alloc(size);
while(true)
offset += size;
exec(bo, offset);
Will cause us to create new allocations until all memory in the system
is used for tracking GPU pages (even though almost all PTEs in this vm
are pointing to scratch).
Let's free unused page tables in clear_range to prevent this - if no
entries are used, we can safely free it and return this information to
the caller (so that higher-level entry is pointing to scratch).
v2: Document return value and free semantics (Joonas)
v3: No newlines in vars block (Joonas)
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 84 +
1 file changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c284d8d..e733657 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,13 +704,14 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
}
-static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+/* Removes entries from a single page table, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries */
+static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
uint64_t start,
uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
-
unsigned int pte_start = gen8_pte_index(start);
unsigned int num_entries = gen8_pte_count(start, length);
uint64_t pte;
@@ -719,63 +720,130 @@ static void gen8_ppgtt_clear_pt(struct
i915_address_space *vm,
I915_CACHE_LLC);
if (WARN_ON(!px_page(pt)))
- return;
+ return false;
bitmap_clear(pt->used_ptes, pte_start, num_entries);
+ if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
+ free_pt(vm->dev, pt);
+ return true;
+ }
+
pt_vaddr = kmap_px(pt);
for (pte = pte_start; pte < num_entries; pte++)
pt_vaddr[pte] = scratch_pte;
kunmap_px(ppgtt, pt_vaddr);
+
+ return false;
}
-static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+/* Removes entries from a single page dir, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
uint64_t start,
uint64_t length)
{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_table *pt;
uint64_t pde;
+ gen8_pde_t *pde_vaddr;
+ gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt),
+I915_CACHE_LLC);
+ bool reduce;
gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
- gen8_ppgtt_clear_pt(vm, pt, start, length);
+ reduce = gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+ if (reduce) {
+ __clear_bit(pde, pd->used_pdes);
+ pde_vaddr = kmap_px(pd);
+ pde_vaddr[pde] = scratch_pde;
+ kunmap_px(ppgtt, pde_vaddr);
+ }
+ }
+
+ if (bitmap_empty(pd->used_pdes, I915_PDES)) {
+ free_pd(vm->dev, pd);
+ return true;
}
+
+ return false;
}
-static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+/* Removes entries from a single page dir pointer, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp,
uint64_t start,
uint64_t length)
{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory *pd;
uint64_t pdpe;
+ gen8_ppgtt_pdpe_t *pdpe_vaddr;
+ gen8_ppgtt_pdpe_t scratch_
[Intel-gfx] [CI 2/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range
Let's use more top-down approach, where each gen8_ppgtt_clear_* function
is responsible for clearing the struct passed as an argument and calling
relevant clear_range functions on lower-level tables.
Doing this rather than operating on PTE ranges makes the implementation
of shrinking page tables quite simple.
v2: Drop min when calculating num_entries, no negation in 48b ppgtt
check, no newlines in vars block (Joonas)
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 107 +++-
1 file changed, 58 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 48ec9c5..c284d8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,59 +704,78 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
}
-static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
- struct i915_page_directory_pointer *pdp,
- uint64_t start,
- uint64_t length,
- gen8_pte_t scratch_pte)
+static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ uint64_t start,
+ uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ unsigned int pte_start = gen8_pte_index(start);
+ unsigned int num_entries = gen8_pte_count(start, length);
+ uint64_t pte;
gen8_pte_t *pt_vaddr;
- unsigned pdpe = gen8_pdpe_index(start);
- unsigned pde = gen8_pde_index(start);
- unsigned pte = gen8_pte_index(start);
- unsigned num_entries = length >> PAGE_SHIFT;
- unsigned last_pte, i;
+ gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
+I915_CACHE_LLC);
- if (WARN_ON(!pdp))
+ if (WARN_ON(!px_page(pt)))
return;
- while (num_entries) {
- struct i915_page_directory *pd;
- struct i915_page_table *pt;
+ bitmap_clear(pt->used_ptes, pte_start, num_entries);
- if (WARN_ON(!pdp->page_directory[pdpe]))
- break;
+ pt_vaddr = kmap_px(pt);
+
+ for (pte = pte_start; pte < num_entries; pte++)
+ pt_vaddr[pte] = scratch_pte;
- pd = pdp->page_directory[pdpe];
+ kunmap_px(ppgtt, pt_vaddr);
+}
+
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ uint64_t start,
+ uint64_t length)
+{
+ struct i915_page_table *pt;
+ uint64_t pde;
+ gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
- pt = pd->page_table[pde];
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+ }
+}
- if (WARN_ON(!px_page(pt)))
- break;
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+struct i915_page_directory_pointer *pdp,
+uint64_t start,
+uint64_t length)
+{
+ struct i915_page_directory *pd;
+ uint64_t pdpe;
- last_pte = pte + num_entries;
- if (last_pte > GEN8_PTES)
- last_pte = GEN8_PTES;
+ gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
+ if (WARN_ON(!pdp->page_directory[pdpe]))
+ break;
- pt_vaddr = kmap_px(pt);
+ gen8_ppgtt_clear_pd(vm, pd, start, length);
+ }
+}
- for (i = pte; i < last_pte; i++) {
- pt_vaddr[i] = scratch_pte;
- num_entries--;
- }
+static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm,
+ struct i915_pml4 *pml4,
+ uint64_t start,
+ uint64_t length)
+{
+ struct i915_page_directory_pointer *pdp;
+ uint64_t pml4e;
- kunmap_px(ppgtt, pt_vaddr);
+ gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
+ if (WARN_ON(!pml4->pdps[pml4e]))
+ break;
- pte = 0;
- if (++pde == I915_PDES) {
- if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
- break;
- pde = 0;
- }
+ gen8_ppgtt_clear_pdp(vm, pdp,
[Intel-gfx] [CI 1/3] drm/i915: Remove unused "valid" parameter from pte_encode
We never used any invalid ptes, those were put in place for
a possibility of doing gpu faults. However our batchbuffers are not
restricted in length, so everything needs to be pointing to something
and thus out-of-bounds is pointing to scratch.
Remove the valid flag as it is always true.
v2: Expand commit msg, patch reorder (Mika)
v3: Rebase
Cc: Chris Wilson
Cc: Michel Thierry
Reviewed-by: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 98 --
drivers/gpu/drm/i915/i915_gem_gtt.h| 5 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
5 files changed, 46 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e..ec2335c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -919,8 +919,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(&ggtt->base,
- node.start, node.size,
- true);
+ node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node(&node);
} else {
@@ -1228,8 +1227,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(&ggtt->base,
- node.start, node.size,
- true);
+ node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node(&node);
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 72c7c18..6835074 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -370,8 +370,7 @@ static void reloc_cache_fini(struct reloc_cache *cache)
ggtt->base.clear_range(&ggtt->base,
cache->node.start,
- cache->node.size,
- true);
+ cache->node.size);
drm_mm_remove_node(&cache->node);
} else {
i915_vma_unpin((struct i915_vma *)cache->node.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2d846aa..48ec9c5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -191,15 +191,13 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
{
vma->vm->clear_range(vma->vm,
vma->node.start,
-vma->size,
-true);
+vma->size);
}
static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- bool valid)
+ enum i915_cache_level level)
{
- gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+ gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
pte |= addr;
switch (level) {
@@ -234,9 +232,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
static gen6_pte_t snb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
switch (level) {
@@ -256,9 +254,9 @@ static gen6_pte_t snb_pte_encode(dma_addr_t addr,
static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
switch (level) {
@@ -280,9 +278,9 @@ static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
static gen6_pte_t byt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 flags)
+u32 flags)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
if (!(flags & PTE_READ_ONLY))
@@ -296,9 +294,9 @@ static gen6_pte_t byt_pte_encode(dma_addr_t addr,
static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
[Intel-gfx] [PATCH i-g-t] build: Fix assmebler/etc. tools build for 32bit x86
From: Ville Syrjälä
Match the i?86 pattern when looking for an x86 to catch 32bit build
systems as well.
Cc: Daniel Stone
Cc: Eric Anholt
Fixes: bccc0ec6a3fd ("build: Disable x86-specific utilities on non-x86")
Signed-off-by: Ville Syrjälä
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 1f3d0dee0217..735cfd59a664 100644
--- a/configure.ac
+++ b/configure.ac
@@ -123,7 +123,7 @@ PKG_CHECK_MODULES(DRM, [libdrm])
PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
case "$target_cpu" in
- x86*)
+ x86*|i?86)
build_x86="yes"
;;
*)
--
2.7.4
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Re: [Intel-gfx] [PATCH i-g-t] intel-ci: Remove kms_psr_sink_crc@psr_basic from BAT
On Wed, 12 Oct 2016, Petri Latvala wrote: > The test is producing a lot of CI noise. > > Signed-off-by: Petri Latvala > --- > > Will be pushed shortly. Visible in CI results tomorrow-ish. > > > tests/intel-ci/fast-feedback.testlist | 1 - I know this is the completely wrong patch to discuss this... but anyway, why is BAT == fast-feedback.testlist, instead of, you know, bat.testlist? BR, Jani. > 1 file changed, 1 deletion(-) > > diff --git a/tests/intel-ci/fast-feedback.testlist > b/tests/intel-ci/fast-feedback.testlist > index ae94381..e2fc9ac 100644 > --- a/tests/intel-ci/fast-feedback.testlist > +++ b/tests/intel-ci/fast-feedback.testlist > @@ -208,7 +208,6 @@ igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence > igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a > igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b > igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c > -igt@kms_psr_sink_crc@psr_basic > igt@kms_setmode@basic-clone-single-crtc > igt@kms_sink_crc_basic > igt@pm_backlight@basic-brightness -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH v2 4/8] drm/i915: Add support for enabling/disabling hdmi audio interrupts
API definitions for enabling/disabling hdmi audio interrupts in
different hdmi pipes are implemented.
Signed-off-by: Jerome Anand
---
drivers/gpu/drm/i915/i915_irq.c | 69
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d8f515f..1e3663f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2867,6 +2867,67 @@ static void gen8_disable_vblank(struct drm_device *dev,
unsigned int pipe)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+/* Added for HDMI Audio */
+int i915_enable_hdmi_audio_int(struct drm_i915_private *dev_priv)
+{
+ unsigned long irqflags;
+ u32 imr, int_bit;
+ int pipe = -1;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ imr = I915_READ(VLV_IMR);
+
+ if (IS_CHERRYVIEW(&dev_priv->drm)) {
+ pipe = PIPE_C;
+ int_bit = (pipe ? (I915_LPE_PIPE_B_INTERRUPT >>
+ ((pipe - 1) * 9)) :
+ I915_LPE_PIPE_A_INTERRUPT);
+ imr &= ~int_bit;
+ } else {
+ /* Audio is on Stream A but uses HDMI PIPE B */
+ pipe = PIPE_B;
+ imr &= ~I915_LPE_PIPE_B_INTERRUPT;
+ }
+
+ I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(VLV_IER, ~imr);
+ POSTING_READ(VLV_IER);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
+/* Added for HDMI Audio */
+int i915_disable_hdmi_audio_int(struct drm_i915_private *dev_priv)
+{
+ unsigned long irqflags;
+ u32 imr, int_bit;
+ int pipe = -1;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ imr = I915_READ(VLV_IMR);
+
+ if (IS_CHERRYVIEW(&dev_priv->drm)) {
+ pipe = PIPE_C;
+ int_bit = (pipe ? (I915_LPE_PIPE_B_INTERRUPT >>
+ ((pipe - 1) * 9)) :
+ I915_LPE_PIPE_A_INTERRUPT);
+ imr |= int_bit;
+ } else {
+ pipe = PIPE_B;
+ imr |= I915_LPE_PIPE_B_INTERRUPT;
+ }
+
+ I915_WRITE(VLV_IER, ~imr);
+ I915_WRITE(VLV_IMR, imr);
+ POSTING_READ(VLV_IMR);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
static bool
ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
{
@@ -3364,6 +3425,14 @@ static void vlv_display_irq_postinstall(struct
drm_i915_private *dev_priv)
WARN_ON(dev_priv->irq_mask != ~0);
+ if (IS_LPE_AUDIO_ENABLED(dev_priv)) {
+ u32 val = (I915_LPE_PIPE_A_INTERRUPT |
+ I915_LPE_PIPE_B_INTERRUPT |
+ I915_LPE_PIPE_C_INTERRUPT);
+
+ enable_mask |= val;
+ }
+
dev_priv->irq_mask = ~enable_mask;
GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30e3f49..e6504ea 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1116,6 +1116,8 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv);
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
+int i915_enable_hdmi_audio_int(struct drm_i915_private *dev_priv);
+int i915_disable_hdmi_audio_int(struct drm_i915_private *dev_priv);
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
{
/*
--
2.9.3
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[Intel-gfx] [RFC PATCH v2 2/8] ALSA: add shell for Intel HDMI LPE audio driver
On Baytrail and Cherrytrail, HDaudio may be fused out or disabled
by the BIOS. This driver enables an alternate path to the i915
display registers and DMA.
Although there is no hardware path between i915 display and LPE/SST
audio clusters, this HDMI capability is referred to in the documentation
as "HDMI LPE Audio" so we keep the name for consistency. There is no
hardware path or control dependencies with the LPE/SST DSP functionality.
The hdmi-lpe-audio driver will be probed when the i915 driver creates
a child platform device.
Since this driver is neither SoC nor PCI, a new x86 folder is added
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
sound/Kconfig| 2 +
sound/Makefile | 2 +-
sound/x86/Kconfig| 16 +
sound/x86/Makefile | 8 +
sound/x86/intel_hdmi_lpe_audio.c | 622 +++
sound/x86/intel_hdmi_lpe_audio.h | 692 +++
6 files changed, 1341 insertions(+), 1 deletion(-)
create mode 100644 sound/x86/Kconfig
create mode 100644 sound/x86/Makefile
create mode 100644 sound/x86/intel_hdmi_lpe_audio.c
create mode 100644 sound/x86/intel_hdmi_lpe_audio.h
diff --git a/sound/Kconfig b/sound/Kconfig
index 5a240e0..ee2e69a 100644
--- a/sound/Kconfig
+++ b/sound/Kconfig
@@ -108,6 +108,8 @@ source "sound/parisc/Kconfig"
source "sound/soc/Kconfig"
+source "sound/x86/Kconfig"
+
endif # SND
menuconfig SOUND_PRIME
diff --git a/sound/Makefile b/sound/Makefile
index c41bdf5..6de45d2 100644
--- a/sound/Makefile
+++ b/sound/Makefile
@@ -5,7 +5,7 @@ obj-$(CONFIG_SOUND) += soundcore.o
obj-$(CONFIG_SOUND_PRIME) += oss/
obj-$(CONFIG_DMASOUND) += oss/
obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
- firewire/ sparc/ spi/ parisc/ pcmcia/ mips/ soc/ atmel/ hda/
+ firewire/ sparc/ spi/ parisc/ pcmcia/ mips/ soc/ atmel/ hda/ x86/
obj-$(CONFIG_SND_AOA) += aoa/
# This one must be compilable even if sound is configured out
diff --git a/sound/x86/Kconfig b/sound/x86/Kconfig
new file mode 100644
index 000..182adf3
--- /dev/null
+++ b/sound/x86/Kconfig
@@ -0,0 +1,16 @@
+menuconfig SND_X86
+ tristate "X86 sound devices"
+ ---help---
+
+ X86 sound devices that don't fall under SoC or PCI categories
+
+if SND_X86
+
+config HDMI_LPE_AUDIO
+ tristate "HDMI audio without HDaudio on Intel Atom platforms"
+ depends on DRM_I915
+default n
+help
+ Choose this option to support HDMI LPE Audio mode
+
+endif # SND_X86
diff --git a/sound/x86/Makefile b/sound/x86/Makefile
new file mode 100644
index 000..78b2ae1
--- /dev/null
+++ b/sound/x86/Makefile
@@ -0,0 +1,8 @@
+DRIVER_NAME := hdmi_lpe_audio
+
+ccflags-y += -Idrivers/gpu/drm/i915
+
+$(DRIVER_NAME)-objs += \
+ intel_hdmi_lpe_audio.o
+
+obj-$(CONFIG_HDMI_LPE_AUDIO) += $(DRIVER_NAME).o
diff --git a/sound/x86/intel_hdmi_lpe_audio.c b/sound/x86/intel_hdmi_lpe_audio.c
new file mode 100644
index 000..f31ab72
--- /dev/null
+++ b/sound/x86/intel_hdmi_lpe_audio.c
@@ -0,0 +1,622 @@
+/*
+ * intel_hdmi_lpe_audio.c - Intel HDMI LPE audio driver for Atom platforms
+ *
+ * Copyright (C) 2016 Intel Corp
+ * Authors:
+ * Jerome Anand
+ * Aravind Siddappaji
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * ~~
+ */
+
+#define pr_fmt(fmt)"hdmi_lpe_audio: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_hdmi_lpe_audio.h"
+
+/* globals*/
+struct platform_device *gpdev;
+int _hdmi_state;
+union otm_hdmi_eld_t hdmi_eld;
+
+struct hdmi_lpe_audio_ctx {
+ int irq;
+ void __iomem *mmio_start;
+ had_event_call_back had_event_callbacks;
+ struct snd_intel_had_interface *had_interface;
+ void *had_pvt_data;
+ int tmds_clock_speed;
+ unsigned int had_config_offset;
+ int hdmi_audio_interrupt_mask;
+ struct work_struct hdmi_audio_wq;
+};
+
+static inline void hdmi_set_eld(void *eld)
+{
+ int size = (sizeof(hdmi_eld)) > HDMI_MAX_ELD_BYTES ?
+ HDMI_MAX_ELD_BYTES :
+ (sizeof(hdmi_eld));
+
+ memcpy((void *)&hdmi_eld, eld, size);
+}
+
+static inline int hdmi_get_eld(void *eld)
+{
+
[Intel-gfx] [RFC PATCH v2 8/8] hdmi_audio: continue audio playback even when display resolution changes
When the display resolution changes, the drm disables the
display pipes due to which audio rendering stops. At this
time, we need to ensure the existing audio pointers and
buffers are cleared out so that the playback can restarted
once the display pipe is enabled with a different N/CTS values
Signed-off-by: Jerome Anand
---
sound/x86/intel_hdmi_audio.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 7fd90ff..8415a32 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -43,6 +43,7 @@ static DEFINE_MUTEX(had_mutex);
static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
static struct snd_intelhad *had_data;
+static int underrun_count;
module_param(hdmi_card_index, int, 0444);
MODULE_PARM_DESC(hdmi_card_index,
@@ -1114,6 +1115,7 @@ static int snd_intelhad_open(struct snd_pcm_substream
*substream)
intelhaddata = snd_pcm_substream_chip(substream);
had_stream = intelhaddata->private_data;
runtime = substream->runtime;
+ underrun_count = 0;
pm_runtime_get(intelhaddata->dev);
@@ -1505,10 +1507,23 @@ static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
buf_id = intelhaddata->curr_buf % 4;
had_read_register(AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
- if (t == 0) {
- pr_debug("discovered buffer done for buf %d\n", buf_id);
- /* had_process_buffer_done(intelhaddata); */
+
+ if ((t == 0) || (t == ((u32)-1L))) {
+ underrun_count++;
+ pr_debug("discovered buffer done for buf %d, count = %d\n",
+ buf_id, underrun_count);
+
+ if (underrun_count > (HAD_MIN_PERIODS/2)) {
+ pr_debug("assume audio_codec_reset, underrun = %d - do
xrun\n",
+ underrun_count);
+ underrun_count = 0;
+ return SNDRV_PCM_POS_XRUN;
+ }
+ } else {
+ /* Reset Counter */
+ underrun_count = 0;
}
+
t = intelhaddata->buf_info[buf_id].buf_size - t;
if (intelhaddata->stream_info.buffer_rendered)
--
2.9.3
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[Intel-gfx] [RFC PATCH v2 1/8] drm/i915: setup bridge for HDMI LPE audio driver
Enable support for HDMI LPE audio mode on Baytrail and
Cherrytrail when HDaudio controller is not detected
Setup minimum required resources during i915_driver_load:
1. Create a platform device to share MMIO/IRQ resources
2. Make the platform device child of i915 device for runtime PM.
3. Create IRQ chip to forward HDMI LPE audio irqs.
HDMI LPE audio driver (a standalone sound driver) probes the
LPE audio device and creates a new sound card.
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_drv.c| 13 +-
drivers/gpu/drm/i915/i915_drv.h| 19 ++
drivers/gpu/drm/i915/i915_irq.c| 14 ++
drivers/gpu/drm/i915/i915_reg.h| 3 +
drivers/gpu/drm/i915/intel_lpe_audio.c | 357 +
include/drm/intel_lpe_audio.h | 45 +
7 files changed, 452 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_lpe_audio.c
create mode 100644 include/drm/intel_lpe_audio.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e6fe004..11f9741 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -115,6 +115,9 @@ i915-y += intel_gvt.o
include $(src)/gvt/Makefile
endif
+# LPE Audio for VLV and CHT
+i915-y += intel_lpe_audio.o
+
obj-$(CONFIG_DRM_I915) += i915.o
CFLAGS_i915_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 31b2b63..ab1e4768 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1141,7 +1141,13 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
if (IS_GEN5(dev_priv))
intel_gpu_ips_init(dev_priv);
- i915_audio_component_init(dev_priv);
+ if (intel_lpe_audio_detect(dev_priv)) {
+ if (intel_lpe_audio_setup(dev_priv) < 0)
+ DRM_ERROR("failed to setup LPE Audio bridge\n");
+ }
+
+ if (!IS_LPE_AUDIO_ENABLED(dev_priv))
+ i915_audio_component_init(dev_priv);
/*
* Some ports require correctly set-up hpd registers for detection to
@@ -1159,7 +1165,10 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
- i915_audio_component_cleanup(dev_priv);
+ if (IS_LPE_AUDIO_ENABLED(dev_priv))
+ intel_lpe_audio_teardown(dev_priv);
+ else
+ i915_audio_component_cleanup(dev_priv);
intel_gpu_ips_teardown();
acpi_video_unregister();
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ff3d7..399a8ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2087,6 +2087,12 @@ struct drm_i915_private {
/* Used to save the pipe-to-encoder mapping for audio */
struct intel_encoder *av_enc_map[I915_MAX_PIPES];
+ /* necessary resource sharing with HDMI LPE audio driver. */
+ struct {
+ struct platform_device *platdev;
+ int irq;
+ } lpe_audio;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
@@ -2827,6 +2833,13 @@ struct drm_i915_cmd_table {
#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
+#define HAS_LPE_AUDIO(dev) (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+#define IS_LPE_AUDIO_ENABLED(dev_priv) \
+ (__I915__(dev_priv)->lpe_audio.platdev != NULL)
+#define IS_LPE_AUDIO_IRQ_VALID(dev_priv) \
+ (__I915__(dev_priv)->lpe_audio.irq >= 0)
+
+
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
@@ -3579,6 +3592,12 @@ extern int i915_restore_state(struct drm_device *dev);
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
+/* i915_lpe_audio.c */
+int intel_lpe_audio_setup(struct drm_i915_private *dev_priv);
+void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
+void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
+int intel_lpe_audio_detect(struct drm_i915_private *dev_priv);
+
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6ed5b24..d8f515f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1827,6 +1827,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void
*arg)
* signalled in iir */
valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+
[Intel-gfx] [RFC PATCH v2 7/8] hdmi_audio: Fixup some monitor
I think this change was given to us, and they claimed it fixed an issue
on some monitor brand. I'm not sure what this patch actually does.
Signed-off-by: David Henningsson
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
sound/x86/intel_hdmi_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 0802b29..7fd90ff 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -337,6 +337,7 @@ static void snd_intelhad_reset_audio_v2(u8 reset)
static int had_prog_status_reg(struct snd_pcm_substream *substream,
struct snd_intelhad *intelhaddata)
{
+ union aud_cfg cfg_val = {.cfg_regval = 0};
union aud_ch_status_0 ch_stat0 = {.status_0_regval = 0};
union aud_ch_status_1 ch_stat1 = {.status_1_regval = 0};
int format;
@@ -347,6 +348,7 @@ static int had_prog_status_reg(struct snd_pcm_substream
*substream,
IEC958_AES0_NONAUDIO)>>1;
ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
IEC958_AES3_CON_CLOCK)>>4;
+ cfg_val.cfg_regx.val_bit = ch_stat0.status_0_regx.lpcm_id;
switch (substream->runtime->rate) {
case AUD_SAMPLE_RATE_32:
@@ -426,7 +428,6 @@ int snd_intelhad_prog_audio_ctrl_v2(struct
snd_pcm_substream *substream,
else
cfg_val.cfg_regx_v2.layout = LAYOUT1;
- cfg_val.cfg_regx_v2.val_bit = 1;
had_write_register(AUD_CONFIG, cfg_val.cfg_regval);
return 0;
}
@@ -482,7 +483,6 @@ int snd_intelhad_prog_audio_ctrl_v1(struct
snd_pcm_substream *substream,
}
- cfg_val.cfg_regx.val_bit = 1;
had_write_register(AUD_CONFIG, cfg_val.cfg_regval);
return 0;
}
--
2.9.3
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH v2 3/8] ALSA: Add support for hdmi audio driver
Hdmi audio driver based on the child platform device
created by gfx driver is implemented.
This audio driver is derived from legacy intel
hdmi audio driver.
The interfaces for interaction between gfx and audio
are updated and the driver implementation updated to
derive interrupts in its own address space based on
irq chip framework
Signed-off-by: Jerome Anand
---
sound/x86/Makefile |2 +
sound/x86/intel_hdmi_audio.c | 1904 ++
sound/x86/intel_hdmi_audio.h | 201
sound/x86/intel_hdmi_audio_if.c | 551 +++
sound/x86/intel_hdmi_lpe_audio.c | 16 +-
5 files changed, 2668 insertions(+), 6 deletions(-)
create mode 100644 sound/x86/intel_hdmi_audio.c
create mode 100644 sound/x86/intel_hdmi_audio.h
create mode 100644 sound/x86/intel_hdmi_audio_if.c
diff --git a/sound/x86/Makefile b/sound/x86/Makefile
index 78b2ae1..bc074d0 100644
--- a/sound/x86/Makefile
+++ b/sound/x86/Makefile
@@ -3,6 +3,8 @@ DRIVER_NAME := hdmi_lpe_audio
ccflags-y += -Idrivers/gpu/drm/i915
$(DRIVER_NAME)-objs += \
+ intel_hdmi_audio.o \
+ intel_hdmi_audio_if.o \
intel_hdmi_lpe_audio.o
obj-$(CONFIG_HDMI_LPE_AUDIO) += $(DRIVER_NAME).o
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
new file mode 100644
index 000..2dc0881
--- /dev/null
+++ b/sound/x86/intel_hdmi_audio.c
@@ -0,0 +1,1904 @@
+/*
+ * intel_hdmi_audio.c - Intel HDMI audio driver
+ *
+ * Copyright (C) 2016 Intel Corp
+ * Authors: Sailaja Bandarupalli
+ * Ramesh Babu K V
+ * Vaibhav Agarwal
+ * Jerome Anand
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * ~~
+ * ALSA driver for Intel HDMI audio
+ */
+
+#define pr_fmt(fmt)"had: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_hdmi_audio.h"
+
+static DEFINE_MUTEX(had_mutex);
+
+/*standard module options for ALSA. This module supports only one card*/
+static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
+static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
+static struct snd_intelhad *had_data;
+
+module_param(hdmi_card_index, int, 0444);
+MODULE_PARM_DESC(hdmi_card_index,
+ "Index value for INTEL Intel HDMI Audio controller.");
+module_param(hdmi_card_id, charp, 0444);
+MODULE_PARM_DESC(hdmi_card_id,
+ "ID string for INTEL Intel HDMI Audio controller.");
+
+/*
+ * ELD SA bits in the CEA Speaker Allocation data block
+*/
+static int eld_speaker_allocation_bits[] = {
+ [0] = FL | FR,
+ [1] = LFE,
+ [2] = FC,
+ [3] = RL | RR,
+ [4] = RC,
+ [5] = FLC | FRC,
+ [6] = RLC | RRC,
+ /* the following are not defined in ELD yet */
+ [7] = 0,
+};
+
+/*
+ * This is an ordered list!
+ *
+ * The preceding ones have better chances to be selected by
+ * hdmi_channel_allocation().
+ */
+static struct cea_channel_speaker_allocation channel_allocations[] = {
+/*channel: 7 6543 210 */
+{ .ca_index = 0x00, .speakers = { 0,0, 0, 0, 0,0, FR, FL }
},
+ /* 2.1 */
+{ .ca_index = 0x01, .speakers = { 0,0, 0, 0, 0, LFE, FR, FL }
},
+ /* Dolby Surround */
+{ .ca_index = 0x02, .speakers = { 0,0, 0, 0, FC,0, FR, FL }
},
+ /* surround40 */
+{ .ca_index = 0x08, .speakers = { 0,0, RR, RL, 0,0, FR, FL }
},
+ /* surround41 */
+{ .ca_index = 0x09, .speakers = { 0,0, RR, RL, 0, LFE, FR, FL }
},
+ /* surround50 */
+{ .ca_index = 0x0a, .speakers = { 0,0, RR, RL, FC,0, FR, FL }
},
+ /* surround51 */
+{ .ca_index = 0x0b, .speakers = { 0,0, RR, RL, FC, LFE, FR, FL }
},
+ /* 6.1 */
+{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL }
},
+ /* surround71 */
+{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL }
},
+
+{ .ca_index = 0x03, .speakers = { 0,0, 0, 0, FC, LFE, FR, FL }
},
+{ .ca_index = 0x04, .speakers = { 0,0, 0, RC, 0,0, FR, FL }
},
+{ .ca_inde
[Intel-gfx] [RFC PATCH v2 5/8] drm/i915: Add support for audio driver notifications
Notifiations like mode change, hot plug and edid to
the audio driver are added. This is inturn used by the
audio driver for its functionality.
A new interface file capturing the notifications needed by the
audio driver is added
Signed-off-by: Jerome Anand
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/intel_audio.c | 8 ++
drivers/gpu/drm/i915/intel_hdmi.c | 18 -
drivers/gpu/drm/i915/intel_lpe_audio.c | 49 ++
include/drm/intel_lpe_audio.h | 1 +
5 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 399a8ee..51a6d71 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3597,6 +3597,9 @@ int intel_lpe_audio_setup(struct drm_i915_private
*dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
int intel_lpe_audio_detect(struct drm_i915_private *dev_priv);
+void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
+ void *eld, int port, int tmds_clk_speed,
+ bool connected);
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 9583f43..61a9a98 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include "intel_drv.h"
#include
@@ -528,6 +529,10 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
(int) port, (int) pipe);
+
+ if (IS_LPE_AUDIO_ENABLED(dev_priv))
+ intel_lpe_audio_notify(dev_priv, connector->eld, port,
+ crtc->config->port_clock, true);
}
/**
@@ -561,6 +566,9 @@ void intel_audio_codec_disable(struct intel_encoder
*intel_encoder)
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
(int) port, (int) pipe);
+
+ if (IS_LPE_AUDIO_ENABLED(dev_priv))
+ intel_lpe_audio_notify(dev_priv, NULL, port, 0, true);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8d46f58..0e20788 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -36,6 +36,7 @@
#include
#include "intel_drv.h"
#include
+#include
#include "i915_drv.h"
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
@@ -1501,9 +1502,24 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
status = connector_status_connected;
- } else
+
+ i915_enable_hdmi_audio_int(dev_priv);
+
+ if (IS_LPE_AUDIO_ENABLED(dev_priv))
+ intel_lpe_audio_notify(dev_priv,
+ connector->eld, 0,
+ 0, true);
+ } else {
status = connector_status_disconnected;
+ i915_disable_hdmi_audio_int(dev_priv);
+
+ if (IS_LPE_AUDIO_ENABLED(dev_priv))
+ intel_lpe_audio_notify(dev_priv,
+ NULL, 0,
+ 0, false);
+ }
+
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
return status;
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c
b/drivers/gpu/drm/i915/intel_lpe_audio.c
index acfe22f..28266e4 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -355,3 +355,52 @@ void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+
+
+/**
+ * intel_lpe_audio_notify() - notify lpe audio event
+ * audio driver and i915
+ * @dev_priv: the i915 drm device private data
+ * @eld : ELD data
+ * @port: port id
+ * @tmds_clk_speed: tmds clock frequency in Hz
+ * @connected: hdmi connected/disconnected
+ *
+ * Notify lpe audio driver of eld change.
+ */
+void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
+ void *eld, int port, int tmds_clk_speed,
+ bool connected)
+{
+ unsigned long irq_flags;
+
+ if (IS_LPE_AUDIO_ENABLED(dev_priv)) {
+ struct intel_hdmi_lpe_audio_pdata *pdata = dev_get_platdata(
+ &(dev_priv->lpe_audio.platdev->dev));
+
+ if (pdata) {
+ spin_lock_irqsav
[Intel-gfx] [RFC PATCH v2 6/8] hdmi_audio: Improve position reporting Using a hw register to calculate sub-period position reports.
This makes PulseAudio happier.
Signed-off-by: David Henningsson
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
sound/x86/intel_hdmi_audio.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 2dc0881..0802b29 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -1491,6 +1491,8 @@ static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
{
struct snd_intelhad *intelhaddata;
u32 bytes_rendered = 0;
+ u32 t;
+ int buf_id;
/* pr_debug("snd_intelhad_pcm_pointer called\n"); */
@@ -1501,6 +1503,14 @@ static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
return SNDRV_PCM_POS_XRUN;
}
+ buf_id = intelhaddata->curr_buf % 4;
+ had_read_register(AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
+ if (t == 0) {
+ pr_debug("discovered buffer done for buf %d\n", buf_id);
+ /* had_process_buffer_done(intelhaddata); */
+ }
+ t = intelhaddata->buf_info[buf_id].buf_size - t;
+
if (intelhaddata->stream_info.buffer_rendered)
div_u64_rem(intelhaddata->stream_info.buffer_rendered,
intelhaddata->stream_info.ring_buf_size,
@@ -1508,7 +1518,7 @@ static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
intelhaddata->stream_info.buffer_ptr = bytes_to_frames(
substream->runtime,
- bytes_rendered);
+ bytes_rendered + t);
return intelhaddata->stream_info.buffer_ptr;
}
--
2.9.3
___
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[Intel-gfx] [RFC PATCH v2 0/8] Add support for Legacy Hdmi audio
Legacy Hdmi audio drivers are added. Added support for audio/ gfx interface using irq chip framework Jerome Anand (8): drm/i915: setup bridge for HDMI LPE audio driver ALSA: add shell for Intel HDMI LPE audio driver ALSA: Add support for hdmi audio driver drm/i915: Add support for enabling/disabling hdmi audio interrupts drm/i915: Add support for audio driver notifications hdmi_audio: Improve position reporting Using a hw register to calculate sub-period position reports. hdmi_audio: Fixup some monitor hdmi_audio: continue audio playback even when display resolution changes drivers/gpu/drm/i915/Makefile |3 + drivers/gpu/drm/i915/i915_drv.c| 13 +- drivers/gpu/drm/i915/i915_drv.h| 22 + drivers/gpu/drm/i915/i915_irq.c| 83 ++ drivers/gpu/drm/i915/i915_reg.h|3 + drivers/gpu/drm/i915/intel_audio.c |8 + drivers/gpu/drm/i915/intel_drv.h |2 + drivers/gpu/drm/i915/intel_hdmi.c | 18 +- drivers/gpu/drm/i915/intel_lpe_audio.c | 406 +++ include/drm/intel_lpe_audio.h | 46 + sound/Kconfig |2 + sound/Makefile |2 +- sound/x86/Kconfig | 16 + sound/x86/Makefile | 10 + sound/x86/intel_hdmi_audio.c | 1929 sound/x86/intel_hdmi_audio.h | 201 sound/x86/intel_hdmi_audio_if.c| 551 + sound/x86/intel_hdmi_lpe_audio.c | 626 +++ sound/x86/intel_hdmi_lpe_audio.h | 692 19 files changed, 4629 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_lpe_audio.c create mode 100644 include/drm/intel_lpe_audio.h create mode 100644 sound/x86/Kconfig create mode 100644 sound/x86/Makefile create mode 100644 sound/x86/intel_hdmi_audio.c create mode 100644 sound/x86/intel_hdmi_audio.h create mode 100644 sound/x86/intel_hdmi_audio_if.c create mode 100644 sound/x86/intel_hdmi_lpe_audio.c create mode 100644 sound/x86/intel_hdmi_lpe_audio.h -- 2.9.3 base-commit: 2fbc239494fa3883e164cc89d35f54d22f0c9e1f ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Record the current requests queue for execlists upon hang
Mika wanted to know what requests were pending at the time of a hang as
we now track which requests we have submitted to the hardware.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 64 ---
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf397b643cc0..6360e807c6ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -832,10 +832,11 @@ struct drm_i915_error_state {
struct drm_i915_error_request {
long jiffies;
pid_t pid;
+ u32 context;
u32 seqno;
u32 head;
u32 tail;
- } *requests;
+ } *requests, execlist[2];
struct drm_i915_error_waiter {
char comm[TASK_COMM_LEN];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 78cc13b9b2a5..026b78c66219 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -363,6 +363,20 @@ static void error_print_instdone(struct
drm_i915_error_state_buf *m,
ee->instdone.row[slice][subslice]);
}
+static void error_print_request(struct drm_i915_error_state_buf *m,
+ const char *prefix,
+ struct drm_i915_error_request *erq)
+{
+ if (!erq->seqno)
+ return;
+
+ err_printf(m, "%s pid %d, seqno %8x:%08x, emitted %dms ago, head %08x,
tail %08x\n",
+ prefix, erq->pid,
+ erq->context, erq->seqno,
+ jiffies_to_msecs(jiffies - erq->jiffies),
+ erq->head, erq->tail);
+}
+
static void error_print_engine(struct drm_i915_error_state_buf *m,
struct drm_i915_error_engine *ee)
{
@@ -434,6 +448,8 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
err_printf(m, " hangcheck: %s [%d]\n",
hangcheck_action_to_str(ee->hangcheck_action),
ee->hangcheck_score);
+ error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
+ error_print_request(m, " ELSP[1]: ", &ee->execlist[1]);
}
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -649,14 +665,8 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, "%s --- %d requests\n",
dev_priv->engine[i].name,
ee->num_requests);
- for (j = 0; j < ee->num_requests; j++) {
- err_printf(m, " pid %d, seqno 0x%08x, emitted
%ld, head 0x%08x, tail 0x%08x\n",
- ee->requests[j].pid,
- ee->requests[j].seqno,
- ee->requests[j].jiffies,
- ee->requests[j].head,
- ee->requests[j].tail);
- }
+ for (j = 0; j < ee->num_requests; j++)
+ error_print_request(m, " ", &ee->requests[j]);
}
if (IS_ERR(ee->waiters)) {
@@ -1155,6 +1165,20 @@ static void error_record_engine_registers(struct
drm_i915_error_state *error,
}
}
+static void record_request(struct drm_i915_gem_request *request,
+ struct drm_i915_error_request *erq)
+{
+ erq->context = request->ctx->hw_id;
+ erq->seqno = request->fence.seqno;
+ erq->jiffies = request->emitted_jiffies;
+ erq->head = request->head;
+ erq->tail = request->tail;
+
+ rcu_read_lock();
+ erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
+ rcu_read_unlock();
+}
+
static void engine_record_requests(struct intel_engine_cs *engine,
struct drm_i915_gem_request *first,
struct drm_i915_error_engine *ee)
@@ -1178,8 +1202,6 @@ static void engine_record_requests(struct intel_engine_cs
*engine,
count = 0;
request = first;
list_for_each_entry_from(request, &engine->request_list, link) {
- struct drm_i915_error_request *erq;
-
if (count >= ee->num_requests) {
/*
* If the ring request list was changed in
@@ -1199,19 +1221,22 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
break;
}
- erq = &ee->requests[count++];
- erq->seqno = request->fence.seqno;
-
[Intel-gfx] [PATCH 16/18] drm/i915: Use SSE4.1 movntdqa based memcpy for sampling GuC log buffer
From: Akash Goel
To ensure that we always get the up-to-date data from log buffer, its
better to access the buffer through an uncached CPU mapping. Also the way
buffer is accessed from GuC & Host side, manually doing cache flush may
not be effective always if cached CPU mapping is used. In order to avoid
any performance drop & have fast reads from the GuC log buffer, used SSE4.1
movntdqa based memcpy function i915_memcpy_from_wc, as copying using
movntqda from WC type memory is almost as fast as reading from WB memory.
This way log buffer sampling time will not get increased and so would be
able to deal with the flush interrupt storm when GuC is generating logs at
a very high rate.
Ideally SSE 4.1 should be present on all chipsets supporting GuC based
submisssions, but if not then logging will not be enabled.
v2: Rebase.
v3: Squash the WC type vmalloc mapping patch with this patch. (Chris)
Suggested-by: Chris Wilson
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 92bc14a..24d356d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1148,18 +1148,16 @@ static void guc_read_update_log_buffer(struct intel_guc
*guc)
/* Just copy the newly written data */
if (read_offset > write_offset) {
- memcpy(dst_data, src_data, write_offset);
+ i915_memcpy_from_wc(dst_data, src_data, write_offset);
bytes_to_copy = buffer_size - read_offset;
} else {
bytes_to_copy = write_offset - read_offset;
}
- memcpy(dst_data + read_offset,
- src_data + read_offset, bytes_to_copy);
+ i915_memcpy_from_wc(dst_data + read_offset,
+ src_data + read_offset, bytes_to_copy);
src_data += buffer_size;
dst_data += buffer_size;
-
- /* FIXME: invalidate/flush for log buffer needed */
}
if (log_buf_snapshot_state)
@@ -1219,8 +1217,11 @@ static int guc_log_create_extras(struct intel_guc *guc)
return 0;
if (!guc->log.buf_addr) {
- /* Create a vmalloc mapping of log buffer pages */
- vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WB);
+ /* Create a WC (Uncached for read) vmalloc mapping of log
+* buffer pages, so that we can directly get the data
+* (up-to-date) from memory.
+*/
+ vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
@@ -1263,6 +1264,16 @@ static void guc_log_create(struct intel_guc *guc)
vma = guc->log.vma;
if (!vma) {
+ /* We require SSE 4.1 for fast reads from the GuC log buffer and
+* it should be present on the chipsets supporting GuC based
+* submisssions.
+*/
+ if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) {
+ /* logging will not be enabled */
+ i915.guc_log_level = -1;
+ return;
+ }
+
vma = guc_allocate_vma(guc, size);
if (IS_ERR(vma)) {
/* logging will be off */
--
1.9.2
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[Intel-gfx] [PATCH 15/18] drm/i915: Debugfs support for GuC logging control
From: Sagar Arun Kamble
This patch provides debugfs interface i915_guc_output_control for
on the fly enabling/disabling of logging in GuC firmware and controlling
the verbosity level of logs.
The value written to the file, should have bit 0 set to enable logging and
bits 4-7 should contain the verbosity info.
v2: Add a forceful flush, to collect left over logs, on disabling logging.
Useful for Validation.
v3: Besides minor cleanup, implement read method for the debugfs file and
set the guc_log_level to -1 when logging is disabled. (Tvrtko)
v4: Minor cleanup & rebase. (Tvrtko)
v5:
- Lock struct_mutex after the NULL check for guc log buffer vma. (Chris)
- Rebase.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 41 -
drivers/gpu/drm/i915/i915_guc_submission.c | 59 ++
drivers/gpu/drm/i915/intel_guc.h | 1 +
3 files changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e04329b..3690911 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2540,6 +2540,44 @@ static int i915_guc_log_dump(struct seq_file *m, void
*data)
return 0;
}
+static int i915_guc_log_control_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (!dev_priv->guc.log.vma)
+ return -EINVAL;
+
+ *val = i915.guc_log_level;
+
+ return 0;
+}
+
+static int i915_guc_log_control_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+
+ if (!dev_priv->guc.log.vma)
+ return -EINVAL;
+
+ ret = mutex_lock_interruptible(&dev->struct_mutex);
+ if (ret)
+ return ret;
+
+ intel_runtime_pm_get(dev_priv);
+ ret = i915_guc_log_control(dev_priv, val);
+ intel_runtime_pm_put(dev_priv);
+
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
+ i915_guc_log_control_get, i915_guc_log_control_set,
+ "%lld\n");
+
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5441,7 +5479,8 @@ static const struct i915_debugfs_files {
{"i915_fbc_false_color", &i915_fbc_fc_fops},
{"i915_dp_test_data", &i915_displayport_test_data_fops},
{"i915_dp_test_type", &i915_displayport_test_type_fops},
- {"i915_dp_test_active", &i915_displayport_test_active_fops}
+ {"i915_dp_test_active", &i915_displayport_test_active_fops},
+ {"i915_guc_log_control", &i915_guc_log_control_fops}
};
void intel_display_crc_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 1564b65..92bc14a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -193,6 +193,16 @@ static int host2guc_force_logbuffer_flush(struct intel_guc
*guc)
return host2guc_action(guc, data, 2);
}
+static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
+{
+ u32 data[2];
+
+ data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING;
+ data[1] = control_val;
+
+ return host2guc_action(guc, data, 2);
+}
+
/*
* Initialise, update, or clear doorbell data shared with the GuC
*
@@ -1603,3 +1613,52 @@ void i915_guc_register(struct drm_i915_private *dev_priv)
guc_log_late_setup(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
+
+int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
+{
+ union guc_log_control log_param;
+ int ret;
+
+ log_param.value = control_val;
+
+ if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN ||
+ log_param.verbosity > GUC_LOG_VERBOSITY_MAX)
+ return -EINVAL;
+
+ /* This combination doesn't make sense & won't have any effect */
+ if (!log_param.logging_enabled && (i915.guc_log_level < 0))
+ return 0;
+
+ ret = host2guc_logging_control(&dev_priv->guc, log_param.value);
+ if (ret < 0) {
+ DRM_DEBUG_DRIVER("host2guc action failed %d\n", ret);
+ return ret;
+ }
+
+ i915.guc_log_level = log_param.verbosity;
+
+ /* If log_level was set as -1 at boot time, then the relay channel file
+* wouldn't have been created by now and interrupts also would not have
+* been enabled.
+*/
+ if (!dev_priv->guc.log.relay_chan) {
+ ret = guc_log_late_setup(&dev_priv->guc);
+ if (!ret)
+ gen9_enable_guc_i
[Intel-gfx] [PATCH 17/18] drm/i915: Early creation of relay channel for capturing boot time logs
From: Akash Goel
As per the current i915 Driver load sequence, debugfs registration is done
at the end and so the relay channel debugfs file is also created after that
but the GuC firmware is loaded much earlier in the sequence.
As a result Driver could miss capturing the boot-time logs of GuC firmware
if there are flush interrupts from the GuC side.
Relay has a provision to support early logging where initially only relay
channel can be created, to have buffers for storing logs, and later on
channel can be associated with a debugfs file at appropriate time.
Have availed that, which allows Driver to capture boot time logs also,
which can be collected once Userspace comes up.
v2:
- Remove the couple of FIXMEs, as now the relay channel will be created
early before enabling the flush interrupts, so no possibility of relay
channel pointer being modified & read at the same time from 2 different
execution contexts.
- Rebase.
v3:
- Add a comment to justiy setting 'is_global' before the NULL check on the
parent directory dentry pointer.
Suggested-by: Chris Wilson
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 71 --
1 file changed, 47 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 24d356d..43de16f 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -915,15 +915,16 @@ static struct dentry *create_buf_file_callback(const char
*filename,
{
struct dentry *buf_file;
- if (!parent)
- return NULL;
-
/* This to enable the use of a single buffer for the relay channel and
* correspondingly have a single file exposed to User, through which
* it can collect the logs in order without any post-processing.
+* Need to set 'is_global' even if parent is NULL for early logging.
*/
*is_global = 1;
+ if (!parent)
+ return NULL;
+
/* Not using the channel filename passed as an argument, since for each
* channel relay appends the corresponding CPU number to the filename
* passed in relay_open(). This should be fine as relay just needs a
@@ -956,13 +957,40 @@ static void guc_log_remove_relay_file(struct intel_guc
*guc)
relay_close(guc->log.relay_chan);
}
-static int guc_log_create_relay_file(struct intel_guc *guc)
+static int guc_log_create_relay_channel(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct rchan *guc_log_relay_chan;
- struct dentry *log_dir;
size_t n_subbufs, subbuf_size;
+ /* Keep the size of sub buffers same as shared log buffer */
+ subbuf_size = guc->log.vma->obj->base.size;
+
+ /* Store up to 8 snapshots, which is large enough to buffer sufficient
+* boot time logs and provides enough leeway to User, in terms of
+* latency, for consuming the logs from relay. Also doesn't take
+* up too much memory.
+*/
+ n_subbufs = 8;
+
+ guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
+ n_subbufs, &relay_callbacks, dev_priv);
+ if (!guc_log_relay_chan) {
+ DRM_ERROR("Couldn't create relay chan for GuC logging\n");
+ return -ENOMEM;
+ }
+
+ GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
+ guc->log.relay_chan = guc_log_relay_chan;
+ return 0;
+}
+
+static int guc_log_create_relay_file(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct dentry *log_dir;
+ int ret;
+
/* For now create the log file in /sys/kernel/debug/dri/0 dir */
log_dir = dev_priv->drm.primary->debugfs_root;
@@ -982,26 +1010,12 @@ static int guc_log_create_relay_file(struct intel_guc
*guc)
return -ENODEV;
}
- /* Keep the size of sub buffers same as shared log buffer */
- subbuf_size = guc->log.vma->obj->base.size;
-
- /* Store up to 8 snapshots, which is large enough to buffer sufficient
-* boot time logs and provides enough leeway to User, in terms of
-* latency, for consuming the logs from relay. Also doesn't take
-* up too much memory.
-*/
- n_subbufs = 8;
-
- guc_log_relay_chan = relay_open("guc_log", log_dir, subbuf_size,
- n_subbufs, &relay_callbacks, dev_priv);
- if (!guc_log_relay_chan) {
- DRM_ERROR("Couldn't create relay chan for GuC logging\n");
- return -ENOMEM;
+ ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir);
+ if (ret) {
+ DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
+ return ret;
}
- GEM_BUG_ON(gu
[Intel-gfx] [PATCH 18/18] drm/i915: Mark the GuC log buffer flush interrupts handling WQ as freezable
From: Akash Goel
The GuC log buffer flush work item has to do a register access to send the
ack to GuC and this work item, if not synced before suspend, can potentially
get executed after the GFX device is suspended. This work item function uses
rpm get/put calls around the Hw access, which covers the rpm suspend case
but for system suspend a sync would be required as kernel can potentially
schedule the work items even after some devices, including GFX, have been
put to suspend. But sync has to be done only for the system suspend case,
as sync along with rpm get/put can cause a deadlock for rpm suspend path.
To have the sync, but like a NOOP, for rpm suspend path also this work
item could have been queued from the irq handler only when the device is
runtime active & kept active while that work item is pending or getting
executed but an interrupt can come even after the device is out of use and
so can potentially lead to missing of this work item.
By marking the workqueue, dedicated for handling GuC log buffer flush
interrupts, as freezable we don't have to bother about flushing of this
work item from the suspend hooks, the pending work item if any will be
either executed before the suspend or scheduled later on resume. This way
the handling of log buffer flush work item can be kept same between system
suspend & rpm suspend.
Suggested-by: Imre Deak
Cc: Imre Deak
Signed-off-by: Akash Goel
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/i915_guc_submission.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 43de16f..d476db7 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1257,10 +1257,19 @@ static int guc_log_create_extras(struct intel_guc *guc)
if (!guc->log.flush_wq) {
INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
- /* Need a dedicated wq to process log buffer flush interrupts
-* from GuC without much delay so as to avoid any loss of logs.
+/*
+* GuC log buffer flush work item has to do register access to
+* send the ack to GuC and this work item, if not synced before
+* suspend, can potentially get executed after the GFX device is
+* suspended.
+* By marking the WQ as freezable, we don't have to bother about
+* flushing of this work item from the suspend hooks, the
pending
+* work item if any will be either executed before the suspend
+* or scheduled later on resume. This way the handling of work
+* item can be kept same between system suspend & rpm suspend.
*/
- guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
WQ_HIGHPRI);
+ guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
+ WQ_HIGHPRI |
WQ_FREEZABLE);
if (guc->log.flush_wq == NULL) {
DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
return -ENOMEM;
--
1.9.2
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[Intel-gfx] [PATCH 11/18] drm/i915: Optimization to reduce the sampling time of GuC log buffer
From: Akash Goel
GuC firmware sends an interrupt to flush the log buffer when it becomes
half full, so Driver doesn't really need to sample the complete buffer
and can just copy only the newly written data by GuC into the local
buffer, i.e. as per the read & write pointer values.
Moreover the flush interrupt would generally come for one type of log
buffer, when it becomes half full, so at that time the other 2 types of
log buffer would comparatively have much lesser unread data in them.
In case of overflow reported by GuC, Driver do need to copy the entire
buffer as the whole buffer would contain the unread data.
v2: Rebase.
v3: Fix the blooper of doing the copy twice. (Tvrtko)
v4: Add curlies for 'else' case also, matching the 'if'. (Tvrtko)
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e6239d3..c584362 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1057,11 +1057,12 @@ static unsigned int guc_get_log_buffer_size(enum
guc_log_buffer_type type)
static void guc_read_update_log_buffer(struct intel_guc *guc)
{
+ unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
- unsigned int buffer_size, write_offset, full_cnt;
enum guc_log_buffer_type type;
void *src_data, *dst_data;
+ bool new_overflow;
if (WARN_ON(!guc->log.buf_addr))
return;
@@ -1084,12 +1085,13 @@ static void guc_read_update_log_buffer(struct intel_guc
*guc)
memcpy(&log_buf_state_local, log_buf_state,
sizeof(struct guc_log_buffer_state));
buffer_size = guc_get_log_buffer_size(type);
+ read_offset = log_buf_state_local.read_ptr;
write_offset = log_buf_state_local.sampled_write_ptr;
full_cnt = log_buf_state_local.buffer_full_cnt;
/* Bookkeeping stuff */
guc->log.flush_count[type] += log_buf_state_local.flush_to_file;
- guc_check_log_buf_overflow(guc, type, full_cnt);
+ new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt);
/* Update the state of shared log buffer */
log_buf_state->read_ptr = write_offset;
@@ -1112,7 +1114,27 @@ static void guc_read_update_log_buffer(struct intel_guc
*guc)
log_buf_snapshot_state++;
/* Now copy the actual logs. */
- memcpy(dst_data, src_data, buffer_size);
+ if (unlikely(new_overflow)) {
+ /* copy the whole buffer in case of overflow */
+ read_offset = 0;
+ write_offset = buffer_size;
+ } else if (unlikely((read_offset > buffer_size) ||
+ (write_offset > buffer_size))) {
+ DRM_ERROR("invalid log buffer state\n");
+ /* copy whole buffer as offsets are unreliable */
+ read_offset = 0;
+ write_offset = buffer_size;
+ }
+
+ /* Just copy the newly written data */
+ if (read_offset > write_offset) {
+ memcpy(dst_data, src_data, write_offset);
+ bytes_to_copy = buffer_size - read_offset;
+ } else {
+ bytes_to_copy = write_offset - read_offset;
+ }
+ memcpy(dst_data + read_offset,
+ src_data + read_offset, bytes_to_copy);
src_data += buffer_size;
dst_data += buffer_size;
--
1.9.2
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[Intel-gfx] [PATCH 14/18] drm/i915: Support for forceful flush of GuC log buffer
From: Sagar Arun Kamble
GuC firmware sends a flush interrupt to Host when the log buffer is half
full and at that time only it updates the log buffer state.
But in certain cases, as described below, it could be useful to have all
that even when log buffer is only partially full. For that there is a force
log buffer flush Host2GuC action supported by GuC firmware.
For Validation requirements, a forceful flush is needed to collect the
left over logs on disabling logging. The same can be done before proceeding
with GPU/GuC reset as there could be some data in log buffer which is yet
to be captured and those logs would be particularly useful to understand
that why the reset was initiated.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 30 ++
drivers/gpu/drm/i915/intel_guc.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c584362..1564b65 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -183,6 +183,16 @@ static int host2guc_logbuffer_flush_complete(struct
intel_guc *guc)
return host2guc_action(guc, data, 1);
}
+static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
+{
+ u32 data[2];
+
+ data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
+ data[1] = 0;
+
+ return host2guc_action(guc, data, 2);
+}
+
/*
* Initialise, update, or clear doorbell data shared with the GuC
*
@@ -1554,6 +1564,26 @@ void i915_guc_capture_logs(struct drm_i915_private
*dev_priv)
intel_runtime_pm_put(dev_priv);
}
+void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
+{
+ if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
+ return;
+
+ /* First disable the interrupts, will be renabled afterwards */
+ gen9_disable_guc_interrupts(dev_priv);
+
+ /* Before initiating the forceful flush, wait for any pending/ongoing
+* flush to complete otherwise forceful flush may not actually happen.
+*/
+ flush_work(&dev_priv->guc.log.flush_work);
+
+ /* Ask GuC to update the log buffer state */
+ host2guc_force_logbuffer_flush(&dev_priv->guc);
+
+ /* GuC would have updated log buffer by now, so capture it */
+ i915_guc_capture_logs(dev_priv);
+}
+
void i915_guc_unregister(struct drm_i915_private *dev_priv)
{
if (!i915.enable_guc_submission)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d034c98..71da75e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -185,6 +185,7 @@ void i915_guc_wq_unreserve(struct drm_i915_gem_request
*request);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
void i915_guc_capture_logs(struct drm_i915_private *dev_priv);
+void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
void i915_guc_register(struct drm_i915_private *dev_priv);
void i915_guc_unregister(struct drm_i915_private *dev_priv);
--
1.9.2
___
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[Intel-gfx] [PATCH 12/18] drm/i915: Increase GuC log buffer size to reduce flush interrupts
From: Akash Goel
In cases where GuC generate logs at a very high rate, correspondingly
the rate of flush interrupts is also very high.
So far total 8 pages were allocated for storing both ISR & DPC logs.
As per the half-full draining protocol followed by GuC, by doubling
the number of pages, the frequency of flush interrupts can be cut down
to almost half, which then helps in reducing the logging overhead.
So now allocating 8 pages apiece for ISR & DPC logs.
This also helps in reducing the output log file size, apart from
reducing the flush interrupt count. With the original settings,
44 KB was needed for one snapshot. With modified settings, 76 KB is
needed for a snapshot which will be equivalent to 2 snapshots of the
original setting. So 12KB saving, every 88 KB, over the original setting.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index adb1ffd..324ea90 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -104,9 +104,9 @@
#define GUC_LOG_ALLOC_IN_MEGABYTE(1 << 3)
#define GUC_LOG_CRASH_PAGES 1
#define GUC_LOG_CRASH_SHIFT 4
-#define GUC_LOG_DPC_PAGES3
+#define GUC_LOG_DPC_PAGES7
#define GUC_LOG_DPC_SHIFT6
-#define GUC_LOG_ISR_PAGES3
+#define GUC_LOG_ISR_PAGES7
#define GUC_LOG_ISR_SHIFT9
#define GUC_LOG_BUF_ADDR_SHIFT 12
@@ -437,9 +437,9 @@ enum guc_log_buffer_type {
*| Crash dump state header |
* Page1 +---+
*| ISR logs|
- * Page5 +---+
- *| DPC logs|
* Page9 +---+
+ *| DPC logs|
+ * Page17 +---+
*| Crash Dump logs |
*+---+
*
--
1.9.2
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[Intel-gfx] [PATCH 10/18] drm/i915: Add stats for GuC log buffer flush interrupts
From: Akash Goel
GuC firmware sends an interrupt to flush the log buffer when it
becomes half full. GuC firmware also tracks how many times the
buffer overflowed.
It would be useful to maintain a statistics of how many flush
interrupts were received and for which type of log buffer,
along with the overflow count of each buffer type.
Augmented i915_log_info debugfs to report back these statistics.
v2:
- Update the logic to detect multiple overflows between the 2
flush interrupts and also log a message for overflow (Tvrtko)
- Track the number of times there was no free sub buffer to capture
the GuC log buffer. (Tvrtko)
v3:
- Fix the printf field width for overflow counter, set it to 10 as per the
max value of u32, which takes 10 digits in decimal form. (Tvrtko)
v4:
- Move the log buffer overflow handling to a new function for better
readability. (Tvrtko)
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 28 +++
drivers/gpu/drm/i915/i915_guc_submission.c | 31 +-
drivers/gpu/drm/i915/i915_irq.c| 2 ++
drivers/gpu/drm/i915/intel_guc.h | 7 +++
4 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0fb9938..e04329b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2408,6 +2408,32 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
return 0;
}
+static void i915_guc_log_info(struct seq_file *m,
+ struct drm_i915_private *dev_priv)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+
+ seq_puts(m, "\nGuC logging stats:\n");
+
+ seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
+ guc->log.flush_count[GUC_ISR_LOG_BUFFER],
+ guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
+
+ seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
+ guc->log.flush_count[GUC_DPC_LOG_BUFFER],
+ guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
+
+ seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
+ guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
+ guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
+
+ seq_printf(m, "\tTotal flush interrupt count: %u\n",
+ guc->log.flush_interrupt_count);
+
+ seq_printf(m, "\tCapture miss count: %u\n",
+ guc->log.capture_miss_count);
+}
+
static void i915_guc_client_info(struct seq_file *m,
struct drm_i915_private *dev_priv,
struct i915_guc_client *client)
@@ -2481,6 +2507,8 @@ static int i915_guc_info(struct seq_file *m, void *data)
seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
i915_guc_client_info(m, dev_priv, &client);
+ i915_guc_log_info(m, dev_priv);
+
/* Add more as required ... */
return 0;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 04b2e87..e6239d3 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1016,6 +1016,29 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
return relay_reserve(guc->log.relay_chan, 0);
}
+static bool
+guc_check_log_buf_overflow(struct intel_guc *guc,
+ enum guc_log_buffer_type type, unsigned int full_cnt)
+{
+ unsigned int prev_full_cnt = guc->log.prev_overflow_count[type];
+ bool overflow = false;
+
+ if (full_cnt != prev_full_cnt) {
+ overflow = true;
+
+ guc->log.prev_overflow_count[type] = full_cnt;
+ guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt;
+
+ if (full_cnt < prev_full_cnt) {
+ /* buffer_full_cnt is a 4 bit counter */
+ guc->log.total_overflow_count[type] += 16;
+ }
+ DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+ }
+
+ return overflow;
+}
+
static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
{
switch (type) {
@@ -1036,7 +1059,7 @@ static void guc_read_update_log_buffer(struct intel_guc
*guc)
{
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
struct guc_log_buffer_state log_buf_state_local;
- unsigned int buffer_size, write_offset;
+ unsigned int buffer_size, write_offset, full_cnt;
enum guc_log_buffer_type type;
void *src_data, *dst_data;
@@ -1062,6 +1085,11 @@ static void guc_read_update_log_buffer(struct intel_guc
*guc)
sizeof(struct guc_log_buffer_state));
buffer_size = guc_get_log_buf
[Intel-gfx] [PATCH 04/18] drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set
From: Akash Goel
So far PM IER/IIR/IMR registers were being used only for Turbo related
interrupts. But interrupts coming from GuC also use the same set.
As a precursor to supporting GuC interrupts, added new low level routines
so as to allow sharing the programming of PM IER/IIR/IMR registers between
Turbo & GuC.
Also similar to PM IMR, maintaining a bitmask for PM IER register, to allow
easy sharing of it between Turbo & GuC without involving a rmw operation.
v2:
- For appropriateness & avoid any ambiguity, rename old functions
enable/disable pm_irq to mask/unmask pm_irq and rename new functions
enable/disable pm_interrupts to enable/disable pm_irq. (Tvrtko)
- Use u32 in place of uint32_t. (Tvrtko)
v3:
- Rename the fields pm_irq_mask & pm_ier_mask and do some cleanup. (Chris)
- Rebase.
v4: Fix the inadvertent disabling of User interrupt for VECS ring causing
failure for certain IGTs.
v5: Use dev_priv with HAS_VEBOX macro. (Tvrtko)
Suggested-by: Chris Wilson
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 75 ++---
drivers/gpu/drm/i915/intel_drv.h| 3 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +-
4 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf397b6..3870786 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1834,7 +1834,8 @@ struct drm_i915_private {
u32 de_irq_mask[I915_MAX_PIPES];
};
u32 gt_irq_mask;
- u32 pm_irq_mask;
+ u32 pm_imr;
+ u32 pm_ier;
u32 pm_rps_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ddff6f9..3a7ab2e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -303,18 +303,18 @@ static void snb_update_pm_irq(struct drm_i915_private
*dev_priv,
assert_spin_locked(&dev_priv->irq_lock);
- new_val = dev_priv->pm_irq_mask;
+ new_val = dev_priv->pm_imr;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->pm_irq_mask) {
- dev_priv->pm_irq_mask = new_val;
- I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
+ if (new_val != dev_priv->pm_imr) {
+ dev_priv->pm_imr = new_val;
+ I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
POSTING_READ(gen6_pm_imr(dev_priv));
}
}
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
{
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
@@ -322,28 +322,54 @@ void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv, uint32_t mask)
snb_update_pm_irq(dev_priv, mask, mask);
}
-static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
- uint32_t mask)
+static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
{
snb_update_pm_irq(dev_priv, mask, 0);
}
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
{
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
- __gen6_disable_pm_irq(dev_priv, mask);
+ __gen6_mask_pm_irq(dev_priv, mask);
}
-void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
{
i915_reg_t reg = gen6_pm_iir(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
- I915_WRITE(reg, dev_priv->pm_rps_events);
- I915_WRITE(reg, dev_priv->pm_rps_events);
+ assert_spin_locked(&dev_priv->irq_lock);
+
+ I915_WRITE(reg, reset_mask);
+ I915_WRITE(reg, reset_mask);
POSTING_READ(reg);
+}
+
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
+{
+ assert_spin_locked(&dev_priv->irq_lock);
+
+ dev_priv->pm_ier |= enable_mask;
+ I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ gen6_unmask_pm_irq(dev_priv, enable_mask);
+ /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
+}
+
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
+{
+ assert_spin_locked(&dev_priv->irq_lock);
+
+ dev_priv->pm_ier &= ~disable_mask;
+ __gen6_mask_pm_irq(dev_priv, disable_mask);
+ I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ /* though a barrier is missing here, but don't really need a one */
+}
+
+void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ gen6_reset_pm_iir(dev_
[Intel-gfx] [PATCH 13/18] drm/i915: Augment i915 error state to include the dump of GuC log buffer
From: Akash Goel
Added the dump of GuC log buffer to i915 error state, as the contents of
GuC log buffer would also be useful to determine that why the GPU reset
was triggered.
v2:
- For uniformity use existing helper function print_error_obj() to
dump out contents of GuC log buffer, pretty printing is better left
to userspace. (Chris)
- Skip the dumping of GuC log buffer when logging is disabled as it
won't be of any use.
- Rebase.
v3: Rebase.
Suggested-by: Chris Wilson
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8389af..c67dea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,7 @@ struct drm_i915_error_state {
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
struct drm_i915_error_object *semaphore;
+ struct drm_i915_error_object *guc_log;
struct drm_i915_error_engine {
int engine_id;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 78cc13b..fc0f0b4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -692,6 +692,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
print_error_obj(m, NULL, "Semaphores", error->semaphore);
+ print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
+
if (error->overlay)
intel_overlay_print_error_state(m, error->overlay);
@@ -772,6 +774,7 @@ static void i915_error_state_free(struct kref *error_ref)
}
i915_error_object_free(error->semaphore);
+ i915_error_object_free(error->guc_log);
for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
kfree(error->active_bo[i]);
@@ -1382,6 +1385,17 @@ static void i915_capture_pinned_buffers(struct
drm_i915_private *dev_priv,
error->pinned_bo = bo;
}
+static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
+ struct drm_i915_error_state *error)
+{
+ /* Capturing log buf contents won't be useful if logging was disabled */
+ if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
+ return;
+
+ error->guc_log = i915_error_object_create(dev_priv,
+ dev_priv->guc.log.vma);
+}
+
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
@@ -1506,6 +1520,7 @@ static int capture(void *data)
i915_gem_record_rings(error->i915, error);
i915_capture_active_buffers(error->i915, error);
i915_capture_pinned_buffers(error->i915, error);
+ i915_gem_capture_guc_log_buffer(error->i915, error);
do_gettimeofday(&error->time);
--
1.9.2
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[Intel-gfx] [PATCH 08/18] drm/i915: Add a relay backed debugfs interface for capturing GuC logs
From: Akash Goel
Added a new debugfs interface '/sys/kernel/debug/dri/guc_log' for the
User to capture GuC firmware logs. Availed relay framework to implement
the interface, where Driver will have to just use a relay API to store
snapshots of the GuC log buffer in the buffer managed by relay.
The snapshot will be taken when GuC firmware sends a log buffer flush
interrupt and up to four snapshots could be stored in the relay buffer.
The relay buffer will be operated in a mode where it will overwrite the
data not yet collected by User.
Besides mmap method, through which User can directly access the relay
buffer contents, relay also supports the 'poll' method. Through the 'poll'
call on log file, User can come to know whenever a new snapshot of the
log buffer is taken by Driver, so can run in tandem with the Driver and
capture the logs in a sustained/streaming manner, without any loss of data.
v2: Defer the creation of relay channel & associated debugfs file, as
debugfs setup is now done at the end of i915 Driver load. (Chris)
v3:
- Switch to no-overwrite mode for relay.
- Fix the relay sub buffer switching sequence.
v4:
- Update i915 Kconfig to select RELAY config. (TvrtKo)
- Log a message when there is no sub buffer available to capture
the GuC log buffer. (Tvrtko)
- Increase the number of relay sub buffers to 8 from 4, to have
sufficient buffering for boot time logs
v5:
- Fix the alignment, indentation issues and some minor cleanup. (Tvrtko)
- Update the comment to elaborate on why a relay channel has to be
associated with the debugfs file. (Tvrtko)
v6:
- Move the write to 'is_global' after the NULL check on parent directory
dentry pointer. (Tvrtko)
v7: Add a BUG_ON to validate relay buffer allocation size. (Chris)
Testcase: igt/tools/intel_guc_logger
Suggested-by: Chris Wilson
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/i915_drv.c| 2 +
drivers/gpu/drm/i915/i915_guc_submission.c | 213 -
drivers/gpu/drm/i915/intel_guc.h | 3 +
4 files changed, 217 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 6aedc96..105c468 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -12,6 +12,7 @@ config DRM_I915
select DRM_KMS_HELPER
select DRM_PANEL
select DRM_MIPI_DSI
+ select RELAY
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
select BACKLIGHT_LCD_SUPPORT if ACPI
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d3222..09a2944 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1128,6 +1128,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
i915_debugfs_register(dev_priv);
+ i915_guc_register(dev_priv);
i915_setup_sysfs(dev_priv);
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
@@ -1166,6 +1167,7 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
intel_opregion_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
+ i915_guc_unregister(dev_priv);
i915_debugfs_unregister(dev_priv);
drm_dev_unregister(&dev_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index b3c81a2..2cdc3ca 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -23,6 +23,8 @@
*/
#include
#include
+#include
+#include
#include "i915_drv.h"
#include "intel_guc.h"
@@ -856,13 +858,160 @@ err:
return NULL;
}
+/*
+ * Sub buffer switch callback. Called whenever relay has to switch to a new
+ * sub buffer, relay stays on the same sub buffer if 0 is returned.
+ */
+static int subbuf_start_callback(struct rchan_buf *buf,
+void *subbuf,
+void *prev_subbuf,
+size_t prev_padding)
+{
+ /* Use no-overwrite mode by default, where relay will stop accepting
+* new data if there are no empty sub buffers left.
+* There is no strict synchronization enforced by relay between Consumer
+* and Producer. In overwrite mode, there is a possibility of getting
+* inconsistent/garbled data, the producer could be writing on to the
+* same sub buffer from which Consumer is reading. This can't be avoided
+* unless Consumer is fast enough and can always run in tandem with
+* Producer.
+*/
+ if (relay_buf_full(buf))
+ return
[Intel-gfx] [PATCH 05/18] drm/i915: Support for GuC interrupts
From: Sagar Arun Kamble
There are certain types of interrupts which Host can receive from GuC.
GuC ukernel sends an interrupt to Host for certain events, like for
example retrieve/consume the logs generated by ukernel.
This patch adds support to receive interrupts from GuC but currently
enables & partially handles only the interrupt sent by GuC ukernel.
Future patches will add support for handling other interrupt types.
v2:
- Use common low level routines for PM IER/IIR programming (Chris)
- Rename interrupt functions to gen9_xxx from gen8_xxx (Chris)
- Replace disabling of wake ref asserts with rpm get/put (Chris)
v3:
- Update comments for more clarity. (Tvrtko)
- Remove the masking of GuC interrupt, which was kept masked till the
start of bottom half, its not really needed as there is only a
single instance of work item & wq is ordered. (Tvrtko)
v4:
- Rebase.
- Rename guc_events to pm_guc_events so as to be indicative of the
register/control block it is associated with. (Chris)
- Add handling for back to back log buffer flush interrupts.
v5:
- Move the read & clearing of register, containing Guc2Host message
bits, outside the irq spinlock. (Tvrtko)
v6:
- Move the log buffer flush interrupt related stuff to the following
patch so as to do only generic bits in this patch. (Tvrtko)
- Rebase.
v7:
- Remove the interrupts_enabled check from gen9_guc_irq_handler, want to
process that last interrupt also before disabling the interrupt, sync
against the work queued by irq handler will be done by caller disabling
the interrupt.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 5 +++
drivers/gpu/drm/i915/i915_irq.c| 56 +++---
drivers/gpu/drm/i915/i915_reg.h| 11 ++
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_guc.h | 3 ++
drivers/gpu/drm/i915/intel_guc_loader.c| 4 +++
7 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3870786..f8389af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1837,6 +1837,7 @@ struct drm_i915_private {
u32 pm_imr;
u32 pm_ier;
u32 pm_rps_events;
+ u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ef38a32..889a72b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1084,6 +1084,8 @@ int intel_guc_suspend(struct drm_device *dev)
if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
return 0;
+ gen9_disable_guc_interrupts(dev_priv);
+
ctx = dev_priv->kernel_context;
data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
@@ -1110,6 +1112,9 @@ int intel_guc_resume(struct drm_device *dev)
if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
return 0;
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
+
ctx = dev_priv->kernel_context;
data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3a7ab2e..69f737f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -170,6 +170,7 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv,
} while (0)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
+static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
/* For display hotplug interrupt */
static inline void
@@ -417,6 +418,38 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
+void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (!dev_priv->guc.interrupts_enabled) {
+ WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+ dev_priv->pm_guc_events);
+ dev_priv->guc.interrupts_enabled = true;
+ gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+ }
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->guc.interrupts_enabled = false;
+
+ gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_eve
[Intel-gfx] [PATCH 09/18] drm/i915: New lock to serialize the Host2GuC actions
From: Akash Goel
With the addition of new Host2GuC actions related to GuC logging, there
is a need of a lock to serialize them, as they can execute concurrently
with each other and also with other existing actions.
v2: Use mutex in place of spinlock to serialize, as sleep can happen
while waiting for the action's response from GuC. (Tvrtko)
v3: To conform to the general rules, acquire mutex before taking the
forcewake. (Tvrtko)
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 +++
drivers/gpu/drm/i915/intel_guc.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 2cdc3ca..04b2e87 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -87,6 +87,7 @@ static int host2guc_action(struct intel_guc *guc, u32 *data,
u32 len)
if (WARN_ON(len < 1 || len > 15))
return -EINVAL;
+ mutex_lock(&guc->action_lock);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
dev_priv->guc.action_count += 1;
@@ -125,6 +126,7 @@ static int host2guc_action(struct intel_guc *guc, u32
*data, u32 len)
dev_priv->guc.action_status = status;
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ mutex_unlock(&guc->action_lock);
return ret;
}
@@ -1365,6 +1367,7 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
guc->ctx_pool_vma = vma;
ida_init(&guc->ctx_ids);
+ mutex_init(&guc->action_lock);
guc_log_create(guc);
guc_addon_create(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index e7999dd..907d13a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -157,6 +157,9 @@ struct intel_guc {
uint64_t submissions[I915_NUM_ENGINES];
uint32_t last_seqno[I915_NUM_ENGINES];
+
+ /* To serialize the Host2GuC actions */
+ struct mutex action_lock;
};
/* intel_guc_loader.c */
--
1.9.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/18] drm/i915: Handle log buffer flush interrupt event from GuC
From: Sagar Arun Kamble
GuC ukernel sends an interrupt to Host to flush the log buffer
and expects Host to correspondingly update the read pointer
information in the state structure, once it has consumed the
log buffer contents by copying them to a file or buffer.
Even if Host couldn't copy the contents, it can still update the
read pointer so that logging state is not disturbed on GuC side.
v2:
- Use a dedicated workqueue for handling flush interrupt. (Tvrtko)
- Reduce the overall log buffer copying time by skipping the copy of
crash buffer area for regular cases and copying only the state
structure data in first page.
v3:
- Create a vmalloc mapping of log buffer. (Chris)
- Cover the flush acknowledgment under rpm get & put.(Chris)
- Revert the change of skipping the copy of crash dump area, as
not really needed, will be covered by subsequent patch.
v4:
- Destroy the wq under the same condition in which it was created,
pass dev_piv pointer instead of dev to newly added GuC function,
add more comments & rename variable for clarity. (Tvrtko)
v5:
- Allocate & destroy the dedicated wq, for handling flush interrupt,
from the setup/teardown routines of GuC logging. (Chris)
- Validate the log buffer size value retrieved from state structure
and do some minor cleanup. (Tvrtko)
- Fix error/warnings reported by checkpatch. (Tvrtko)
- Rebase.
v6:
- Remove the interrupts_enabled check from guc_capture_logs_work, need
to process that last work item also, queued just before disabling the
interrupt as log buffer flush interrupt handling is a bit different
case where GuC is actually expecting an ACK from host, which should be
provided to keep the logging going.
Sync against the work will be done by caller disabling the interrupt.
- Don't sample the log buffer size value from state structure, directly
use the expected value to move the pointer & do the copy and that cannot
go wrong (out of bounds) as Driver only allocated the log buffer and the
relay buffers. Driver should refrain from interpreting the log packet,
as much possible and let Userspace parser detect the anomaly. (Chris)
v7:
- Use switch statement instead of 'if else' for retrieving the GuC log
buffer size. (Tvrtko)
- Refactored the log buffer copying function and shortended the name of
couple of variables for better readability. (Tvrtko)
v8:
- Make the dedicated wq as a high priority one to further reduce the
turnaround time of handing log buffer flush event from GuC.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 186 +
drivers/gpu/drm/i915/i915_irq.c| 28 -
drivers/gpu/drm/i915/intel_guc.h | 4 +
3 files changed, 217 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 889a72b..b3c81a2 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -170,6 +170,15 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
return host2guc_action(guc, data, ARRAY_SIZE(data));
}
+static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
+{
+ u32 data[1];
+
+ data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
+
+ return host2guc_action(guc, data, 1);
+}
+
/*
* Initialise, update, or clear doorbell data shared with the GuC
*
@@ -847,6 +856,163 @@ err:
return NULL;
}
+static void guc_move_to_next_buf(struct intel_guc *guc)
+{
+}
+
+static void *guc_get_write_buffer(struct intel_guc *guc)
+{
+ return NULL;
+}
+
+static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
+{
+ switch (type) {
+ case GUC_ISR_LOG_BUFFER:
+ return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
+ case GUC_DPC_LOG_BUFFER:
+ return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
+ case GUC_CRASH_DUMP_LOG_BUFFER:
+ return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
+ default:
+ MISSING_CASE(type);
+ }
+
+ return 0;
+}
+
+static void guc_read_update_log_buffer(struct intel_guc *guc)
+{
+ struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
+ struct guc_log_buffer_state log_buf_state_local;
+ unsigned int buffer_size, write_offset;
+ enum guc_log_buffer_type type;
+ void *src_data, *dst_data;
+
+ if (WARN_ON(!guc->log.buf_addr))
+ return;
+
+ /* Get the pointer to shared GuC log buffer */
+ log_buf_state = src_data = guc->log.buf_addr;
+
+ /* Get the pointer to local buffer to store the logs */
+ log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
+
+ /* Actual logs are present from the 2nd page */
+ src_data += PAGE_SIZE;
+ dst_data += PAGE_SIZE;
+
+ for (type = GUC_ISR_LOG
[Intel-gfx] [PATCH 07/18] relay: Use per CPU constructs for the relay channel buffer pointers
From: Akash Goel
relay essentially needs to maintain the per CPU array of channel buffer
pointers but it manually creates that array.
Instead its better to avail the per CPU constructs, provided by the
kernel, to allocate & access the array of pointer to channel buffers.
This patch is queued for merge in linux-next via akpm.
v2: Include in relay.h so that it pulls in the percpu
api explicitly. (Chris)
Link:
http://lkml.kernel.org/r/1470909140-25919-1-git-send-email-akash.g...@intel.com
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Akash Goel
Reviewed-by: Chris Wilson
---
include/linux/relay.h | 17 +++-
kernel/relay.c| 74 +--
2 files changed, 52 insertions(+), 39 deletions(-)
diff --git a/include/linux/relay.h b/include/linux/relay.h
index d7c8359..eb295e3 100644
--- a/include/linux/relay.h
+++ b/include/linux/relay.h
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
/*
* Tracks changes to rchan/rchan_buf structs
@@ -63,7 +64,7 @@ struct rchan
struct kref kref; /* channel refcount */
void *private_data; /* for user-defined data */
size_t last_toobig; /* tried to log event > subbuf size */
- struct rchan_buf *buf[NR_CPUS]; /* per-cpu channel buffers */
+ struct rchan_buf ** __percpu buf; /* per-cpu channel buffers */
int is_global; /* One global buffer ? */
struct list_head list; /* for channel list */
struct dentry *parent; /* parent dentry passed to open */
@@ -204,7 +205,7 @@ static inline void relay_write(struct rchan *chan,
struct rchan_buf *buf;
local_irq_save(flags);
- buf = chan->buf[smp_processor_id()];
+ buf = *this_cpu_ptr(chan->buf);
if (unlikely(buf->offset + length > chan->subbuf_size))
length = relay_switch_subbuf(buf, length);
memcpy(buf->data + buf->offset, data, length);
@@ -230,12 +231,12 @@ static inline void __relay_write(struct rchan *chan,
{
struct rchan_buf *buf;
- buf = chan->buf[get_cpu()];
+ buf = *get_cpu_ptr(chan->buf);
if (unlikely(buf->offset + length > buf->chan->subbuf_size))
length = relay_switch_subbuf(buf, length);
memcpy(buf->data + buf->offset, data, length);
buf->offset += length;
- put_cpu();
+ put_cpu_ptr(chan->buf);
}
/**
@@ -251,17 +252,19 @@ static inline void __relay_write(struct rchan *chan,
*/
static inline void *relay_reserve(struct rchan *chan, size_t length)
{
- void *reserved;
- struct rchan_buf *buf = chan->buf[smp_processor_id()];
+ void *reserved = NULL;
+ struct rchan_buf *buf = *get_cpu_ptr(chan->buf);
if (unlikely(buf->offset + length > buf->chan->subbuf_size)) {
length = relay_switch_subbuf(buf, length);
if (!length)
- return NULL;
+ goto end;
}
reserved = buf->data + buf->offset;
buf->offset += length;
+end:
+ put_cpu_ptr(chan->buf);
return reserved;
}
diff --git a/kernel/relay.c b/kernel/relay.c
index d797502..f55ab82 100644
--- a/kernel/relay.c
+++ b/kernel/relay.c
@@ -214,7 +214,7 @@ static void relay_destroy_buf(struct rchan_buf *buf)
__free_page(buf->page_array[i]);
relay_free_page_array(buf->page_array);
}
- chan->buf[buf->cpu] = NULL;
+ *per_cpu_ptr(chan->buf, buf->cpu) = NULL;
kfree(buf->padding);
kfree(buf);
kref_put(&chan->kref, relay_destroy_channel);
@@ -382,20 +382,21 @@ static void __relay_reset(struct rchan_buf *buf, unsigned
int init)
*/
void relay_reset(struct rchan *chan)
{
+ struct rchan_buf *buf;
unsigned int i;
if (!chan)
return;
- if (chan->is_global && chan->buf[0]) {
- __relay_reset(chan->buf[0], 0);
+ if (chan->is_global && (buf = *per_cpu_ptr(chan->buf, 0))) {
+ __relay_reset(buf, 0);
return;
}
mutex_lock(&relay_channels_mutex);
for_each_possible_cpu(i)
- if (chan->buf[i])
- __relay_reset(chan->buf[i], 0);
+ if ((buf = *per_cpu_ptr(chan->buf, i)))
+ __relay_reset(buf, 0);
mutex_unlock(&relay_channels_mutex);
}
EXPORT_SYMBOL_GPL(relay_reset);
@@ -440,7 +441,7 @@ static struct rchan_buf *relay_open_buf(struct rchan *chan,
unsigned int cpu)
struct dentry *dentry;
if (chan->is_global)
- return chan->buf[0];
+ return *per_cpu_ptr(chan->buf, 0);
buf = relay_create_buf(chan);
if (!buf)
@@ -464,7 +465,7 @@ static struct rchan_buf *relay_open_buf(struct rchan *chan,
unsigned int cpu)
__relay_reset(buf, 1);
if(chan->is_global) {
-
[Intel-gfx] [PATCH v10 00/18] Support for sustained capturing of GuC firmware logs
From: Akash Goel GuC firmware log its debug messages into a Host-GuC shared memory buffer and when the buffer is half full it sends a Flush interrupt to Host. GuC firmware follows the half-full draining protocol where it expects that while it is writing to 2nd half of the buffer, 1st half would get consumed by Host and then get a flush completed acknowledgment from Host, so that it does not end up doing any overwrite causing loss of logs. So far flush interrupt wasn't enabled on Host side & User could capture the contents/snapshot of log buffer through 'i915_guc_log_dump' debugfs iface. But this couldn't meet couple of key requirements, especially of Validation, first is to ensure capturing of all boot time logs even with high verbosity level and second is to enable capturing of logs in a sustained manner like for the entire duration of a workload. Now Driver will enable flush interrupt and on receiving it, would copy the contents of log buffer into its local buffer. The size of local buffer would be big enough to contain multiple snapshots of the log buffer giving ample time to User to pull boot time messages. Have added a debugfs interface '/sys/kernel/debug/dri/guc_log' for User to collect the logs. Availed relay framework to implement this interface, where Driver will have to just use a relay API to store snapshots of GuC log buffer in a buffer managed by relay. The relay buffer can be operated in a mode, equivalent to 'dmesg -c' where the old data, not yet collected by User, will be overwritten if buffer becomes full or it can be operated in no-overwrite mode where relay will stop accepting new data if all sub buffers are full. Have used the latter mode to avoid the possibility of getting garbled data. Besides mmap method, through which User can directly access the relay buffer contents, relay also supports the 'poll' method. Through the 'poll' call on log file, User can come to know whenever a new snapshot of the log buffer is taken by Driver, so can run in tandem with the Driver and thus capture logs in a sustained/streaming manner, without any loss of data. The logs can be captured from relay backed debugfs file through the utility igt/tools/intel_guc_logger. v2: Rebased to the latest drm-intel-nightly. v3: Aligned with the modification of late debugfs registration, at the end of i915 Driver load. Did cleanup as per Tvrtko's review comments, added 3 new patches to optimize the log-buffer flush interrupt handling, gather and report the logging related stats. v4: Added 2 new patches to further optimize the log-buffer flush interrupt handling. Did cleanup as per Chris's review comments, fixed couple of issues related to clearing of Guc2Host message register. Switched to no-overwrite mode for the relay. v5: Added a new patch to avail MOVNTDQA instruction based fast memcpy provided by a patch from Chris. Dropped the rt priority kthread patch, after evaluating all the optimizations with certain benchmarks like synmark_oglmultithread, synmark_oglbatch5 which generates flush interupts almost at every ms or less. Updated the older patches as per the review comments from Tvrtko and Chris W. Added a new patch to augment i915 error state with the GuC log buffer contents. Fixed the issue of User interrupt getting disabled for VEBOX ring, causing failure for certain IGTs. Also included 2 patches to support early logging for capturing boot time logs and use per CPU constructs on the relay side so as to address a WARNING issue with the call to relay_reserve(), without disabling preemption. v6: Mainly did the rebasing, refactoring, cleanup as per the review comments and fixed error/warnings reported by checkpatch. v7: Added a new patch to complete the pending log buffer flush work item in system suspend case. Cleaned up the irq handler & work item function by removing the check for GuC interrupts. v8: Replaced the patch added in last version with a patch which marks the GuC log buffer flush interrupt handling WQ as freezable, as per the inputs from Imre. Refactored the log buffer sampling function and added a new helper function to improve the readability as per suggestions from Tvrtko. v9: As per Chris's comment, removed the forceful flush of GuC log buffer from the error state capture path as that could have disturbed the atomicity required in error state path. Squashed the wc type vmalloc mapping patch with SSE4.1 movntdqa based memcpy patch. Added a BUG_ON for the relay buffer allocation size. v10: Mainly rebasing. Made the dedicated WQ as a high priority one. Akash Goel (12): drm/i915: New structure to contain GuC logging related fields drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set relay: Use per CPU constructs for the relay channel buffer pointers drm/i915: Add a relay backed debugfs interface for capturing GuC logs drm/i915: New lock to
[Intel-gfx] [PATCH 03/18] drm/i915: New structure to contain GuC logging related fields
From: Akash Goel
So far there were 2 fields related to GuC logs in 'intel_guc' structure.
For the support of capturing GuC logs & storing them in a local buffer,
multiple new fields would have to be added. This warrants a separate
structure to contain the fields related to GuC logging state.
Added a new structure 'intel_guc_log' and instance of it inside
'intel_guc' structure.
v2: Rebase.
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 4 ++--
drivers/gpu/drm/i915/i915_guc_submission.c | 8
drivers/gpu/drm/i915/intel_guc.h | 8 ++--
drivers/gpu/drm/i915/intel_guc_loader.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 358663e..0fb9938 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2492,10 +2492,10 @@ static int i915_guc_log_dump(struct seq_file *m, void
*data)
struct drm_i915_gem_object *obj;
int i = 0, pg;
- if (!dev_priv->guc.log_vma)
+ if (!dev_priv->guc.log.vma)
return 0;
- obj = dev_priv->guc.log_vma->obj;
+ obj = dev_priv->guc.log.vma->obj;
for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 2ce98aaf..ef38a32 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -862,7 +862,7 @@ static void guc_log_create(struct intel_guc *guc)
GUC_LOG_ISR_PAGES + 1 +
GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
- vma = guc->log_vma;
+ vma = guc->log.vma;
if (!vma) {
vma = guc_allocate_vma(guc, size);
if (IS_ERR(vma)) {
@@ -871,7 +871,7 @@ static void guc_log_create(struct intel_guc *guc)
return;
}
- guc->log_vma = vma;
+ guc->log.vma = vma;
}
/* each allocated unit is a page */
@@ -881,7 +881,7 @@ static void guc_log_create(struct intel_guc *guc)
(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
- guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
+ guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
}
static void guc_policies_init(struct guc_policies *policies)
@@ -1063,7 +1063,7 @@ void i915_guc_submission_fini(struct drm_i915_private
*dev_priv)
struct intel_guc *guc = &dev_priv->guc;
i915_vma_unpin_and_release(&guc->ads_vma);
- i915_vma_unpin_and_release(&guc->log_vma);
+ i915_vma_unpin_and_release(&guc->log.vma);
if (guc->ctx_pool_vma)
ida_destroy(&guc->ctx_ids);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 5cdf7aa..c732941 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -123,10 +123,14 @@ struct intel_guc_fw {
uint32_t ucode_offset;
};
+struct intel_guc_log {
+ uint32_t flags;
+ struct i915_vma *vma;
+};
+
struct intel_guc {
struct intel_guc_fw guc_fw;
- uint32_t log_flags;
- struct i915_vma *log_vma;
+ struct intel_guc_log log;
struct i915_vma *ads_vma;
struct i915_vma *ctx_pool_vma;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index c37829f..410d98a 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -209,7 +209,7 @@ static void guc_params_init(struct drm_i915_private
*dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
- params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
+ params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
if (i915.guc_log_level >= 0) {
params[GUC_CTL_DEBUG] =
--
1.9.2
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[Intel-gfx] [PATCH 02/18] drm/i915: Add GuC ukernel logging related fields to fw interface file
From: Sagar Arun Kamble
The first page of the GuC log buffer contains state info or meta data
which is required to parse the logs contained in the subsequent pages.
The structure representing the state info is added to interface file
as Driver would need to handle log buffer flush interrupts from GuC.
Added an enum for the different message/event types that can be send
by the GuC ukernel to Host.
Also added 2 new Host to GuC action types to inform GuC when Host has
flushed the log buffer and forcefuly cause the GuC to send a new
log buffer flush interrupt.
v2:
- Make documentation of log buffer state structure more elaborate &
rename LOGBUFFERFLUSH action to LOG_BUFFER_FLUSH for consistency.(Tvrtko)
v3: Add GuC log buffer layout diagram for more clarity.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 78 +++
1 file changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index e40db2d..adb1ffd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -419,15 +419,87 @@ struct guc_ads {
u32 reserved2[4];
} __packed;
+/* GuC logging structures */
+
+enum guc_log_buffer_type {
+ GUC_ISR_LOG_BUFFER,
+ GUC_DPC_LOG_BUFFER,
+ GUC_CRASH_DUMP_LOG_BUFFER,
+ GUC_MAX_LOG_BUFFER
+};
+
+/**
+ * DOC: GuC Log buffer Layout
+ *
+ * Page0 +---+
+ *| ISR state header (32 bytes) |
+ *| DPC state header |
+ *| Crash dump state header |
+ * Page1 +---+
+ *| ISR logs|
+ * Page5 +---+
+ *| DPC logs|
+ * Page9 +---+
+ *| Crash Dump logs |
+ *+---+
+ *
+ * Below state structure is used for coordination of retrieval of GuC firmware
+ * logs. Separate state is maintained for each log buffer type.
+ * read_ptr points to the location where i915 read last in log buffer and
+ * is read only for GuC firmware. write_ptr is incremented by GuC with number
+ * of bytes written for each log entry and is read only for i915.
+ * When any type of log buffer becomes half full, GuC sends a flush interrupt.
+ * GuC firmware expects that while it is writing to 2nd half of the buffer,
+ * first half would get consumed by Host and then get a flush completed
+ * acknowledgment from Host, so that it does not end up doing any overwrite
+ * causing loss of logs. So when buffer gets half filled & i915 has requested
+ * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
+ * to the value of write_ptr and raise the interrupt.
+ * On receiving the interrupt i915 should read the buffer, clear flush_to_file
+ * field and also update read_ptr with the value of sample_write_ptr, before
+ * sending an acknowledgment to GuC. marker & version fields are for internal
+ * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
+ * time GuC detects the log buffer overflow.
+ */
+struct guc_log_buffer_state {
+ u32 marker[2];
+ u32 read_ptr;
+ u32 write_ptr;
+ u32 size;
+ u32 sampled_write_ptr;
+ union {
+ struct {
+ u32 flush_to_file:1;
+ u32 buffer_full_cnt:4;
+ u32 reserved:27;
+ };
+ u32 flags;
+ };
+ u32 version;
+} __packed;
+
+union guc_log_control {
+ struct {
+ u32 logging_enabled:1;
+ u32 reserved1:3;
+ u32 verbosity:4;
+ u32 reserved2:24;
+ };
+ u32 value;
+} __packed;
+
/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
enum host2guc_action {
HOST2GUC_ACTION_DEFAULT = 0x0,
HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
+ HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
+ HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
+ HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
HOST2GUC_ACTION_LIMIT
};
@@ -449,4 +521,10 @@ enum guc2host_status {
GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0xF000)
};
+/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
+enum guc2host_message {
+ GUC2HOST_MSG_CRASH_DUMP_POSTED = (1 << 1),
+ GUC2HOST_MSG_FLUSH_LOG_BUFFER = (1 << 3)
+};
+
#endif
--
1.9.2
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[Intel-gfx] [PATCH 01/18] drm/i915: Decouple GuC log setup from verbosity parameter
From: Sagar Arun Kamble
GuC Log buffer allocation was tied up with verbosity level module param
i915.guc_log_level. User would be given a provision to enable firmware
logging at runtime, through a host2guc action, and not necessarily during
Driver load time. But the address of log buffer can be passed only in
init params, at firmware load time, so GuC has to be reset and firmware
needs to be reloaded to pass the log buffer address at runtime.
To avoid reset of GuC & reload of firmware, allocation of log buffer will
be done always but logging would be enabled initially on GuC side based on
the value of module parameter guc_log_level.
v2: Update commit message to describe the constraint with allocation of
log buffer at runtime. (Tvrtko)
v3: Rebase.
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 ---
drivers/gpu/drm/i915/intel_guc_loader.c| 6 --
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 3106dcc..2ce98aaf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -853,9 +853,6 @@ static void guc_log_create(struct intel_guc *guc)
unsigned long offset;
uint32_t size, flags;
- if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
- return;
-
if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96b..c37829f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -209,11 +209,13 @@ static void guc_params_init(struct drm_i915_private
*dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
+ params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
+
if (i915.guc_log_level >= 0) {
- params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
params[GUC_CTL_DEBUG] =
i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
- }
+ } else
+ params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
if (guc->ads_vma) {
u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
--
1.9.2
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Treat a framebuffer reference as an active reference whilst shrinking
== Series Details == Series: drm/i915: Treat a framebuffer reference as an active reference whilst shrinking URL : https://patchwork.freedesktop.org/series/13648/ State : failure == Summary == Series 13648v1 drm/i915: Treat a framebuffer reference as an active reference whilst shrinking https://patchwork.freedesktop.org/api/1.0/series/13648/revisions/1/mbox/ Test kms_force_connector_basic: Subgroup force-connector-state: pass -> DMESG-WARN (fi-ivb-3770) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-ilk-650) Test pm_rps: Subgroup basic-api: pass -> FAIL (fi-hsw-4770r) Test vgem_basic: Subgroup unload: skip -> PASS (fi-bdw-5557u) pass -> SKIP (fi-hsw-4770r) skip -> PASS (fi-hsw-4770) Test vgem_reload_basic: pass -> FAIL (fi-hsw-4770r) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:222 dwarn:0 dfail:0 fail:2 skip:24 fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:230 dwarn:2 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2688/ 4c3e00c4630b732518abf737580d927bb52346fa drm-intel-nightly: 2016y-10m-12d-14h-36m-58s UTC integration manifest 2ac1007 drm/i915: Treat a framebuffer reference as an active reference whilst shrinking ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/hsw: Fix GPU hang during resume from S3-devices state
On Wed, Oct 12, 2016 at 05:46:37PM +0300, Imre Deak wrote: > Currently resuming on HSW from S3 pm_test/devices state leads to an > unrecoverable GPU hang. Resetting the GPU during suspend fixes this. For > a full S3 cycle this change only means the reset happens earlier (before > reaching S3). For S4 the reset will happen now both during the freeze > and quiesce phases, which is a benefit since it will guarantee that the > GPU is idle before creating and loading the hibernation image. > > Cc: Mika Kuoppala > Cc: Chris Wilson > Suggested-by: Chris Wilson > Signed-off-by: Imre Deak Makes sense, we should treat the transition to suspend just like unload. We should do the symmetric reset on load/resume as well. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt/gem_wait: Use explicit timers
Rather than guestimating a workload that should take a certain amount of
time, use a sigitimer to terminate a batch (and so complete the wait)
after an exact amount of time. And in the process expand testing to
cover multiple rings and hangcheck.
Signed-off-by: Chris Wilson
---
lib/igt_core.h | 27
tests/gem_wait.c | 443 +++
2 files changed, 277 insertions(+), 193 deletions(-)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 433b88c..03be757 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -403,6 +403,24 @@ static inline void igt_ignore_warn(bool value)
} while (0)
/**
+ * igt_assert_cmps64:
+ * @n1: first value
+ * @cmp: compare operator
+ * @ncmp: negated version of @cmp
+ * @n2: second value
+ *
+ * Like igt_assert_cmpuint(), but for larger signed ints.
+ */
+#define igt_assert_cmps64(n1, cmp, ncmp, n2) \
+ do { \
+ int64_t __n1 = (n1), __n2 = (n2); \
+ if (__n1 cmp __n2) ; else \
+ __igt_fail_assert(IGT_LOG_DOMAIN, __FILE__, __LINE__, __func__,
\
+ #n1 " " #cmp " " #n2, \
+ "error: %lld " #ncmp " %lld\n", (long
long)__n1, (long long)__n2); \
+ } while (0)
+
+/**
* igt_assert_cmpu64:
* @n1: first value
* @cmp: compare operator
@@ -461,6 +479,15 @@ static inline void igt_ignore_warn(bool value)
#define igt_assert_eq_u32(n1, n2) igt_assert_cmpuint(n1, ==, !=, n2)
/**
+ * igt_assert_eq_s64:
+ * @n1: first integer
+ * @n2: second integer
+ *
+ * Like igt_assert_eq_u32(), but for int64_t.
+ */
+#define igt_assert_eq_s64(n1, n2) igt_assert_cmps64(n1, ==, !=, n2)
+
+/**
* igt_assert_eq_u64:
* @n1: first integer
* @n2: second integer
diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index 461efdb..0ecb92f 100644
--- a/tests/gem_wait.c
+++ b/tests/gem_wait.c
@@ -26,233 +26,290 @@
*/
#include "igt.h"
-#include
+
+#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include "intel_bufmgr.h"
-
-#define MSEC_PER_SEC 1000L
-#define USEC_PER_MSEC 1000L
-#define NSEC_PER_USEC 1000L
-#define NSEC_PER_MSEC 100L
-#define USEC_PER_SEC 100L
-#define NSEC_PER_SEC 10L
-
-#define ENOUGH_WORK_IN_SECONDS 2
-#define BUF_SIZE (8<<20)
-#define BUF_PAGES ((8<<20)>>12)
-drm_intel_bo *dst, *dst2;
-
-/* returns time diff in milliseconds */
-static int64_t
-do_time_diff(struct timespec *end, struct timespec *start)
-{
- int64_t ret;
- ret = (MSEC_PER_SEC * difftime(end->tv_sec, start->tv_sec)) +
- ((end->tv_nsec/NSEC_PER_MSEC) - (start->tv_nsec/NSEC_PER_MSEC));
- return ret;
-}
+#include
-static void blt_color_fill(struct intel_batchbuffer *batch,
- drm_intel_bo *buf,
- const unsigned int pages)
-{
- const unsigned short height = pages/4;
- const unsigned short width = 4096;
-
- COLOR_BLIT_COPY_BATCH_START(COLOR_BLT_WRITE_ALPHA |
- XY_COLOR_BLT_WRITE_RGB);
- OUT_BATCH((3 << 24) | /* 32 Bit Color */
- (0xF0 << 16) | /* Raster OP copy background register */
- 0); /* Dest pitch is 0 */
- OUT_BATCH(0);
- OUT_BATCH(width << 16 |
- height);
- OUT_RELOC_FENCED(buf, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
- OUT_BATCH(rand()); /* random pattern */
- ADVANCE_BATCH();
-}
+#define gettid() syscall(__NR_gettid)
+#define sigev_notify_thread_id _sigev_un._tid
-static void render_timeout(int fd)
+#define LOCAL_I915_EXEC_BSD_SHIFT (13)
+#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
+
+#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
+
+static int __gem_wait(int fd, struct drm_i915_gem_wait *w)
{
- drm_intel_bufmgr *bufmgr;
- struct intel_batchbuffer *batch;
- int64_t timeout = ENOUGH_WORK_IN_SECONDS * NSEC_PER_SEC;
- int64_t negative_timeout = -1;
- int ret;
- const bool do_signals = true; /* signals will seem to make the operation
- * use less process CPU time */
- bool done = false;
- int i, iter = 1;
+ int err;
- igt_skip_on_simulation();
+ err = 0;
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_WAIT, w))
+ err = -errno;
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
- dst = drm_intel_bo_alloc(bufmgr, "dst", BUF_SIZE, 4096);
- dst2 = drm_intel_bo_alloc(bufmgr, "dst2", BUF_SIZE, 4096);
-
- igt_skip_on_f(gem_wait(fd, dst->handle, &timeout) == -EINVAL,
- "kernel doesn't support wait_timeout, skipping test\n");
- timeout = ENOUGH_WORK_IN
[Intel-gfx] [PATCH igt] igt: Add exerciser for execbuf fence-out <-> fence-in
When execbuf2 supports explicit fencing with sync_file in/out fences
(via a fence-fd), we can control execution via the fence.
Signed-off-by: Chris Wilson
---
tests/Makefile.sources | 1 +
tests/gem_exec_fence.c | 377 +
2 files changed, 378 insertions(+)
create mode 100644 tests/gem_exec_fence.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ddd8d7a..1938944 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -36,6 +36,7 @@ TESTS_progs_M = \
gem_exec_basic \
gem_exec_create \
gem_exec_faulting_reloc \
+ gem_exec_fence \
gem_exec_flush \
gem_exec_gttfill \
gem_exec_latency \
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
new file mode 100644
index 000..815b666
--- /dev/null
+++ b/tests/gem_exec_fence.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+#include
+#include
+
+IGT_TEST_DESCRIPTION("Check that execbuf waits for explicit fences");
+
+#define LOCAL_PARAM_HAS_EXEC_FENCE 42
+#define LOCAL_EXEC_FENCE_IN (1 << 16)
+#define LOCAL_EXEC_FENCE_OUT (1 << 17)
+#define LOCAL_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+
+static bool can_mi_store_dword(int gen, unsigned engine)
+{
+ return !(gen == 6 && (engine & ~(3<<13)) == I915_EXEC_BSD);
+}
+
+static void store(int fd, unsigned ring, int fence, uint32_t target, unsigned
offset_value)
+{
+ const int SCRATCH = 0;
+ const int BATCH = 1;
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t batch[16];
+ int i;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = (uintptr_t)obj;
+ execbuf.buffer_count = 2;
+ execbuf.flags = ring | LOCAL_EXEC_FENCE_IN;
+ execbuf.rsvd2 = fence;
+ if (gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+
+ memset(obj, 0, sizeof(obj));
+ obj[SCRATCH].handle = target;
+
+ obj[BATCH].handle = gem_create(fd, 4096);
+ obj[BATCH].relocs_ptr = (uintptr_t)&reloc;
+ obj[BATCH].relocation_count = 1;
+ memset(&reloc, 0, sizeof(reloc));
+
+ i = 0;
+ reloc.target_handle = obj[SCRATCH].handle;
+ reloc.presumed_offset = -1;
+ reloc.offset = sizeof(uint32_t) * (i + 1);
+ reloc.delta = sizeof(uint32_t) * offset_value;
+ reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+ reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = reloc.delta;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = reloc.delta;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = reloc.delta;
+ }
+ batch[++i] = offset_value;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[BATCH].handle);
+}
+
+static int __gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ int err = 0;
+ if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_EXECBUFFER2_WR, execbuf))
+ err = -errno;
+ errno = 0;
+ return err;
+}
+
+static void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ igt_assert_eq(__gem_execbuf_wr(fd, execbuf), 0);
+}
+
+static bool fence_busy(int fence)
+{
+ return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0
Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
On Wed, 2016-10-12 at 17:34 +0300, Jani Nikula wrote: > In the mean time, please file a bug over at [1] so we don't lose > track. Done: https://bugs.freedesktop.org/show_bug.cgi?id=98214 Paul Bolle ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/hsw: Fix GPU hang during resume from S3-devices state
Currently resuming on HSW from S3 pm_test/devices state leads to an
unrecoverable GPU hang. Resetting the GPU during suspend fixes this. For
a full S3 cycle this change only means the reset happens earlier (before
reaching S3). For S4 the reset will happen now both during the freeze
and quiesce phases, which is a benefit since it will guarantee that the
GPU is idle before creating and loading the hibernation image.
Cc: Mika Kuoppala
Cc: Chris Wilson
Suggested-by: Chris Wilson
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c | 28 ++--
drivers/gpu/drm/i915/i915_gem.c | 24
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d3222..e9b3bfc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -532,32 +532,6 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
static void i915_gem_fini(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- /*
-* Neither the BIOS, ourselves or any other kernel
-* expects the system to be in execlists mode on startup,
-* so we need to reset the GPU back to legacy mode. And the only
-* known way to disable logical contexts is through a GPU reset.
-*
-* So in order to leave the system in a known default configuration,
-* always reset the GPU upon unload. Afterwards we then clean up the
-* GEM state tracking, flushing off the requests and leaving the
-* system in a known idle state.
-*
-* Note that is of the upmost importance that the GPU is idle and
-* all stray writes are flushed *before* we dismantle the backing
-* storage for the pinned objects.
-*
-* However, since we are uncertain that reseting the GPU on older
-* machines is a good idea, we don't - just in case it leaves the
-* machine in an unusable condition.
-*/
- if (HAS_HW_CONTEXTS(dev)) {
- int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
- WARN_ON(reset && reset != -ENODEV);
- }
-
mutex_lock(&dev->struct_mutex);
i915_gem_cleanup_engines(dev);
i915_gem_context_fini(dev);
@@ -636,6 +610,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
+ if (i915_gem_suspend(dev))
+ DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev);
cleanup_irq:
intel_guc_fini(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e..a86bc8f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4273,6 +4273,30 @@ int i915_gem_suspend(struct drm_device *dev)
*/
WARN_ON(dev_priv->gt.awake);
+ /*
+* Neither the BIOS, ourselves or any other kernel
+* expects the system to be in execlists mode on startup,
+* so we need to reset the GPU back to legacy mode. And the only
+* known way to disable logical contexts is through a GPU reset.
+*
+* So in order to leave the system in a known default configuration,
+* always reset the GPU upon unload and suspend. Afterwards we then
+* clean up the GEM state tracking, flushing off the requests and
+* leaving the system in a known idle state.
+*
+* Note that is of the upmost importance that the GPU is idle and
+* all stray writes are flushed *before* we dismantle the backing
+* storage for the pinned objects.
+*
+* However, since we are uncertain that reseting the GPU on older
+* machines is a good idea, we don't - just in case it leaves the
+* machine in an unusable condition.
+*/
+ if (HAS_HW_CONTEXTS(dev)) {
+ int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
+ WARN_ON(reset && reset != -ENODEV);
+ }
+
return 0;
err:
--
2.5.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
On Wed, 12 Oct 2016, Paul Bolle wrote: > On Wed, 2016-10-12 at 14:08 +0300, Joonas Lahtinen wrote: >> Bisecting the offending commit between v4.8 and v4.8.1 would be a good >> start. > > That would be between v4.7 and v4.8. (I guess my report was ambiguous.) > > That might take some time. Because bisecting always takes a long time > and especially since hitting this WARNING sometimes takes over an hour. > Anyhow, please prod me if I stay silent for too long. In the mean time, please file a bug over at [1] so we don't lose track. BR, Jani. [1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode
== Series Details == Series: series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode URL : https://patchwork.freedesktop.org/series/13646/ State : failure == Summary == LD fs/btrfs/built-in.o LD arch/x86/kernel/cpu/built-in.o LD arch/x86/kernel/built-in.o LD net/ipv4/built-in.o LD drivers/usb/host/xhci-hcd.o LD drivers/tty/vt/built-in.o LD arch/x86/built-in.o LD drivers/tty/built-in.o LD drivers/usb/host/built-in.o LD drivers/usb/built-in.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o LD fs/ext4/ext4.o LD fs/ext4/built-in.o LD fs/built-in.o LD drivers/md/md-mod.o LD drivers/md/built-in.o LD net/core/built-in.o LD net/built-in.o LD [M] drivers/net/ethernet/intel/igb/igb.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o LD drivers/net/ethernet/built-in.o LD drivers/net/built-in.o scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:440: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:968: recipe for target 'drivers' failed make: *** [drivers] Error 2 Full logs at /archive/deploy/logs/Patchwork_2687 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Use fence_write() from rpm resume
== Series Details == Series: series starting with [CI,1/2] drm/i915: Use fence_write() from rpm resume URL : https://patchwork.freedesktop.org/series/13642/ State : failure == Summary == Series 13642v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/13642/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup bad-nb-words-1: pass -> DMESG-WARN (fi-ilk-650) Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-j1900) Test vgem_reload_basic: pass -> FAIL (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:223 dwarn:0 dfail:0 fail:1 skip:24 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2686/ 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-12d-11h-06m-41s UTC integration manifest 3556a2e drm/i915: Update debugfs describe_obj() to show fault-mappable 652a473 drm/i915: Use fence_write() from rpm resume ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make sure the base lives at offset 0 of all kms objects
On Wed, Oct 12, 2016 at 02:33:11PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We occasionally depend on eg. to_intel_crtc(NULL) being NULL as > well. Sprinkle in some BUILD_BUG_ON()s to make sure we don't > accidentally change things in a way that would violate this > assumption. > > Signed-off-by: Ville Syrjälä bikeshed would be to convert the macros into typechecking inlines and place the BUILD_BUG_ON there. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: GMBUS don't need no forcewake
== Series Details == Series: drm/i915: GMBUS don't need no forcewake URL : https://patchwork.freedesktop.org/series/13641/ State : warning == Summary == Series 13641v1 drm/i915: GMBUS don't need no forcewake https://patchwork.freedesktop.org/api/1.0/series/13641/revisions/1/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (fi-ilk-650) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-byt-j1900) Test vgem_basic: Subgroup unload: skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2685/ 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-12d-11h-06m-41s UTC integration manifest 3d9fd0b drm/i915: GMBUS don't need no forcewake ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On 10/10/2016 15:31, Goel, Akash wrote:
On 10/10/2016 7:22 PM, Tvrtko Ursulin wrote:
On 10/10/2016 11:59, akash.g...@intel.com wrote:
From: Akash Goel
This patch provides a test utility which helps capture GuC firmware
logs and
then dump them to file.
The logs are pulled from a debugfs file
'/sys/kernel/debug/dri/guc_log' and
by default stored into a file 'guc_log_dump.dat'. The name,
including the
location, of the output file can be changed through a command line
argument.
The utility goes into an infinite loop where it waits for the arrival
of new
logs and as soon as new set of logs are produced it captures them in
its local
buffer which is then flushed out to the file on disk.
Any time when logging needs to be ended, User can stop this utility
(CTRL+C).
Before entering into a loop, it first discards whatever logs are
present in
the debugfs file.
This way User can first launch this utility and then start a
workload/activity
for which GuC firmware logs are to be actually captured and keep
running the
utility for as long as its needed, like once the workload is over this
utility
can be forcefully stopped.
If the logging wasn't enabled on GuC side by the Driver at boot time,
utility
will first enable the logging and later on when it is stopped (CTRL+C)
it will
also pause the logging on GuC side.
v2:
- Use combination of alarm system call & SIGALRM signal to run the
utility
for required duration. (Tvrtko)
- Fix inconsistencies, do minor cleanup and refactoring. (Tvrtko)
v3:
- Fix discrepancy for the output file command line option and update
the
Usage/help string.
v4:
- Update the exit condition for flusher thread, now will exit only
after
the capture loop is over and not when the flag to stop logging is
set.
This handles a corner case, due to which the dump of last captured
buffer
was getting missed.
- Add a newline character at the end of assert messages.
- Avoid the assert for the case, which occurs very rarely, when there
are no
bytes read from the relay file.
Cc: Tvrtko Ursulin
Signed-off-by: Akash Goel
Reviewed-by: Tvrtko Ursulin (v3)
---
tools/Makefile.sources | 1 +
tools/intel_guc_logger.c | 438
+++
2 files changed, 439 insertions(+)
create mode 100644 tools/intel_guc_logger.c
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 2bb6c8e..be58871 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -19,6 +19,7 @@ tools_prog_lists =\
intel_gpu_time\
intel_gpu_top\
intel_gtt\
+intel_guc_logger\
intel_infoframes\
intel_l3_parity\
intel_lid\
diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
new file mode 100644
index 000..159a54e
--- /dev/null
+++ b/tools/intel_guc_logger.c
@@ -0,0 +1,438 @@
+
+#define _GNU_SOURCE /* For using O_DIRECT */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+#define MB(x) ((uint64_t)(x) * 1024 * 1024)
+#ifndef PAGE_SIZE
+ #define PAGE_SIZE 4096
+#endif
+/* Currently the size of GuC log buffer is 19 pages & so is the size
of relay
+ * subbuffer. If the size changes in future, then this define also
needs to be
+ * updated accordingly.
+ */
+#define SUBBUF_SIZE (19*PAGE_SIZE)
+/* Need large buffering from logger side to hide the DISK IO latency,
Driver
+ * can only store 8 snapshots of GuC log buffer in relay.
+ */
+#define NUM_SUBBUFS 100
+
+#define RELAY_FILE_NAME "guc_log"
+#define DEFAULT_OUTPUT_FILE_NAME "guc_log_dump.dat"
+#define CONTROL_FILE_NAME "i915_guc_log_control"
+
+char *read_buffer;
+char *out_filename;
+int poll_timeout = 2; /* by default 2ms timeout */
+pthread_mutex_t mutex;
+pthread_t flush_thread;
+int verbosity_level = 3; /* by default capture logs at max
verbosity */
+uint32_t produced, consumed;
+uint64_t total_bytes_written;
+int num_buffers = NUM_SUBBUFS;
+int relay_fd, outfile_fd = -1;
+uint32_t test_duration, max_filesize;
+pthread_cond_t underflow_cond, overflow_cond;
+bool stop_logging, discard_oldlogs, capturing_stopped;
+
+static void guc_log_control(bool enable_logging)
+{
+int control_fd;
+char data[19];
+uint64_t val;
+int ret;
+
+control_fd = igt_debugfs_open(CONTROL_FILE_NAME, O_WRONLY);
+igt_assert_f(control_fd >= 0, "couldn't open the guc log control
file\n");
+
+val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
+
+ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
+igt_assert(ret > 2 && ret < sizeof(data));
+
+ret = write(control_fd, data, ret);
+igt_assert_f(ret > 0, "couldn't write to the log control file\n");
+
+close(control_fd);
+}
+
+static void int_sig_handler(int sig)
+{
+igt_info("received signal %d\n", sig);
+
+stop_logging = true;
+}
+
+static void pull
[Intel-gfx] [PATCH 1/8] drm/i915/skl+: Prepare for removing data rate from skl watermark state
Caching is not required, drm_atomic_crtc_state_for_each_plane_state
can be used to inspect all plane_states that are assigned to the
current crtc_state, so we can just recalculate every time.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af1587e9d84..b96a899c899d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -31,6 +31,7 @@
#include "intel_drv.h"
#include "../../../platform/x86/intel_ips.h"
#include
+#include
/**
* DOC: RC6
@@ -3242,18 +3243,17 @@ skl_get_total_relative_data_rate(struct
intel_crtc_state *intel_cstate)
struct drm_crtc *crtc = cstate->crtc;
struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- const struct drm_plane *plane;
+ struct drm_plane *plane;
const struct intel_plane *intel_plane;
- struct drm_plane_state *pstate;
+ const struct drm_plane_state *pstate;
unsigned int rate, total_data_rate = 0;
int id;
- int i;
if (WARN_ON(!state))
return 0;
/* Calculate and cache data rate for each plane */
- for_each_plane_in_state(state, plane, pstate, i) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
id = skl_wm_plane_id(to_intel_plane(plane));
intel_plane = to_intel_plane(plane);
@@ -3356,7 +3356,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane;
struct drm_plane *plane;
- struct drm_plane_state *pstate;
+ const struct drm_plane_state *pstate;
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
uint16_t alloc_size, start, cursor_blocks;
@@ -3392,14 +3392,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
alloc_size -= cursor_blocks;
/* 1. Allocate the mininum required blocks for each active plane */
- for_each_plane_in_state(state, plane, pstate, i) {
+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
&cstate->base) {
intel_plane = to_intel_plane(plane);
id = skl_wm_plane_id(intel_plane);
if (intel_plane->pipe != pipe)
continue;
- if (!to_intel_plane_state(pstate)->base.visible) {
+ if (!pstate->visible) {
minimum[id] = 0;
y_minimum[id] = 0;
continue;
@@ -3948,7 +3948,7 @@ skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate)
WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
- drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
+ drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
id = skl_wm_plane_id(to_intel_plane(plane));
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
@@ -4063,14 +4063,12 @@ skl_print_wm_changes(const struct drm_atomic_state
*state)
to_intel_atomic_state(state);
const struct drm_crtc *crtc;
const struct drm_crtc_state *cstate;
- const struct drm_plane *plane;
const struct intel_plane *intel_plane;
- const struct drm_plane_state *pstate;
const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
enum pipe pipe;
int id;
- int i, j;
+ int i;
for_each_crtc_in_state(state, crtc, cstate, i) {
if (!crtc->state)
@@ -4078,10 +4076,9 @@ skl_print_wm_changes(const struct drm_atomic_state
*state)
pipe = to_intel_crtc(crtc)->pipe;
- for_each_plane_in_state(state, plane, pstate, j) {
+ for_each_intel_plane_on_crtc(dev, to_intel_crtc(crtc),
intel_plane) {
const struct skl_ddb_entry *old, *new;
- intel_plane = to_intel_plane(plane);
id = skl_wm_plane_id(intel_plane);
old = &old_ddb->plane[pipe][id];
new = &new_ddb->plane[pipe][id];
@@ -4094,13 +4091,13 @@ skl_print_wm_changes(const struct drm_atomic_state
*state)
if (id != PLANE_CURSOR) {
DRM_DEBUG_ATOMIC("[PLANE:%d:plane %d%c] ddb (%d
- %d) -> (%d - %d)\n",
-plane->base.id, id + 1,
+intel_plane->base.base.id, id
+ 1,
pipe_name(pipe),
old->start, old->end,
[Intel-gfx] [PATCH 2/8] drm/i915/skl+: Remove data_rate from watermark struct.
It's only used in one function, and can be calculated without caching it
in the global struct by using drm_atomic_crtc_state_for_each_plane_state.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_drv.h | 4
drivers/gpu/drm/i915/intel_pm.c | 44 +++-
2 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bb468c974e14..888054518f3c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -502,10 +502,6 @@ struct intel_crtc_wm_state {
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
- /* cached plane data rate */
- unsigned plane_data_rate[I915_MAX_PLANES];
- unsigned plane_y_data_rate[I915_MAX_PLANES];
-
/* minimum block allocation */
uint16_t minimum_blocks[I915_MAX_PLANES];
uint16_t minimum_y_blocks[I915_MAX_PLANES];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b96a899c899d..97b6202c4097 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3236,12 +3236,13 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *cstate,
* 3 * 4096 * 8192 * 4 < 2^32
*/
static unsigned int
-skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
+skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
+unsigned *plane_data_rate,
+unsigned *plane_y_data_rate)
{
struct drm_crtc_state *cstate = &intel_cstate->base;
struct drm_atomic_state *state = cstate->state;
struct drm_crtc *crtc = cstate->crtc;
- struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_plane *plane;
const struct intel_plane *intel_plane;
@@ -3263,21 +3264,16 @@ skl_get_total_relative_data_rate(struct
intel_crtc_state *intel_cstate)
/* packed/uv */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
- intel_cstate->wm.skl.plane_data_rate[id] = rate;
+ plane_data_rate[id] = rate;
+
+ total_data_rate += rate;
/* y-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
- intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
- }
-
- /* Calculate CRTC's total data rate from cached values */
- for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- int id = skl_wm_plane_id(intel_plane);
+ plane_y_data_rate[id] = rate;
- /* packed/uv */
- total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
- total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
+ total_data_rate += rate;
}
return total_data_rate;
@@ -3366,6 +3362,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int num_active;
int id, i;
+ unsigned data_rate[I915_MAX_PLANES] = {};
+ unsigned y_data_rate[I915_MAX_PLANES] = {};
+
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
@@ -3425,29 +3424,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*
* FIXME: we may not allocate every single block here.
*/
- total_data_rate = skl_get_total_relative_data_rate(cstate);
+ total_data_rate = skl_get_total_relative_data_rate(cstate, data_rate,
y_data_rate);
if (total_data_rate == 0)
return 0;
start = alloc->start;
- for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- unsigned int data_rate, y_data_rate;
+ for (id = 0; id < I915_MAX_PLANES; id++) {
+ unsigned rate;
uint16_t plane_blocks, y_plane_blocks = 0;
- int id = skl_wm_plane_id(intel_plane);
- data_rate = cstate->wm.skl.plane_data_rate[id];
+ rate = data_rate[id];
/*
* allocation for (packed formats) or (uv-plane part of planar
format):
* promote the expression to 64 bits to avoid overflowing, the
-* result is < available as data_rate / total_data_rate < 1
+* result is < available as rate / total_data_rate < 1
*/
plane_blocks = minimum[id];
- plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
+ plane_blocks += div_u64((uint
[Intel-gfx] [PATCH 0/8] drm/i915/gen9+: Atomic wm fixes.
This patch series applies on top of Lyude's patches. They clean up the remainder of SKL style wm's, and finally makes SKL watermarks ready for nonblocking modeset by using the crtc_state for watermarks as much as possible. Maarten Lankhorst (8): drm/i915/skl+: Prepare for removing data rate from skl watermark state drm/i915/skl+: Remove data_rate from watermark struct. drm/i915/skl+: Remove minimum block allocation from crtc state. drm/i915/skl+: Clean up minimum allocations. drm/i915: Add a atomic evasion step to watermark programming. drm/i915/gen9+: Use the watermarks from crtc_state for everything. drm/i915/gen9+: Program watermarks as a separate step during evasion drm/i915/gen9+: Preserve old allocation from crtc_state. drivers/gpu/drm/i915/i915_drv.h | 13 +-- drivers/gpu/drm/i915/intel_display.c | 58 -- drivers/gpu/drm/i915/intel_drv.h | 16 --- drivers/gpu/drm/i915/intel_pm.c | 206 +++ drivers/gpu/drm/i915/intel_sprite.c | 18 --- 5 files changed, 136 insertions(+), 175 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915: Add a atomic evasion step to watermark programming.
Allow the driver to write watermarks during atomic evasion.
This will make it possible to write the watermarks in a cleaner
way on gen9+.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/intel_display.c | 18 --
drivers/gpu/drm/i915/intel_pm.c | 19 +--
3 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f65ccf9b0bea..09588c58148f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -484,6 +484,7 @@ struct sdvo_device_mapping {
struct intel_connector;
struct intel_encoder;
+struct intel_atomic_state;
struct intel_crtc_state;
struct intel_initial_plane_config;
struct intel_crtc;
@@ -497,8 +498,9 @@ struct drm_i915_display_funcs {
int (*compute_intermediate_wm)(struct drm_device *dev,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *newstate);
- void (*initial_watermarks)(struct intel_crtc_state *cstate);
- void (*optimize_watermarks)(struct intel_crtc_state *cstate);
+ void (*initial_watermarks)(struct intel_atomic_state *state, struct
intel_crtc_state *cstate);
+ void (*atomic_evade_watermarks)(struct intel_atomic_state *state,
struct intel_crtc_state *cstate);
+ void (*optimize_watermarks)(struct intel_atomic_state *state, struct
intel_crtc_state *cstate);
int (*compute_global_watermarks)(struct drm_atomic_state *state);
void (*update_wm)(struct drm_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 55f8ec8c76ae..23d8c72dade3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5160,7 +5160,7 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
* us to.
*/
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(pipe_config);
+
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state),
pipe_config);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(&crtc->base);
}
@@ -5374,7 +5374,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_color_load_luts(&pipe_config->base);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(intel_crtc->config);
+
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state),
intel_crtc->config);
intel_enable_pipe(intel_crtc);
if (intel_crtc->config->has_pch_encoder)
@@ -5480,7 +5480,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_ddi_enable_transcoder_func(crtc);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(pipe_config);
+
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state),
pipe_config);
else
intel_update_watermarks(crtc);
@@ -14503,7 +14503,7 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
intel_cstate = to_intel_crtc_state(crtc->state);
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(intel_cstate);
+ dev_priv->display.optimize_watermarks(intel_state,
intel_cstate);
}
for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
@@ -14908,7 +14908,6 @@ static void intel_begin_crtc_commit(struct drm_crtc
*crtc,
struct intel_crtc_state *old_intel_state =
to_intel_crtc_state(old_crtc_state);
bool modeset = needs_modeset(crtc->state);
- enum pipe pipe = intel_crtc->pipe;
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(intel_crtc);
@@ -14923,12 +14922,11 @@ static void intel_begin_crtc_commit(struct drm_crtc
*crtc,
if (intel_cstate->update_pipe)
intel_update_pipe_config(intel_crtc, old_intel_state);
- else if (INTEL_GEN(dev_priv) >= 9) {
+ else if (INTEL_GEN(dev_priv) >= 9)
skl_detach_scalers(intel_crtc);
- I915_WRITE(PIPE_WM_LINETIME(pipe),
- intel_cstate->wm.skl.optimal.linetime);
- }
+ if (dev_priv->display.atomic_evade_watermarks)
+
dev_priv->display.atomic_evade_watermarks(to_intel_atomic_state(old_crtc_state->state),
intel_cstate);
}
static void intel_finish_crtc_commit(struct drm_crtc *crtc,
@@ -16388,7 +16386,7 @@ retry:
struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
cs
[Intel-gfx] [PATCH 6/8] drm/i915/gen9+: Use the watermarks from crtc_state for everything.
There's no need to keep a duplicate skl_pipe_wm around any more,
everything can be discovered from crtc_state, which we pass around
correctly now even in case of plane disable.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 11 +--
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 23d8c72dade3..340861826c46 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13455,7 +13455,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
return;
skl_pipe_wm_get_hw_state(crtc, &hw_wm);
- sw_wm = &intel_crtc->wm.active.skl;
+ sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
skl_ddb_get_hw_state(dev_priv, &hw_ddb);
sw_ddb = &dev_priv->wm.skl_hw.ddb;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a176e6cebab3..9f04e26c4365 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -723,7 +723,6 @@ struct intel_crtc {
/* watermarks currently being used */
union {
struct intel_pipe_wm ilk;
- struct skl_pipe_wm skl;
} active;
/* allow CxSR on this pipe */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 05ccd253fd7a..be3dd8cdc7ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3904,9 +3904,9 @@ bool skl_ddb_allocation_overlaps(struct drm_atomic_state
*state,
static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
struct skl_ddb_allocation *ddb, /* out */
struct skl_pipe_wm *pipe_wm, /* out */
+ const struct skl_pipe_wm *old_pipe_wm,
bool *changed /* out */)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
int ret;
@@ -3914,7 +3914,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state
*cstate,
if (ret)
return ret;
- if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
+ if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
*changed = false;
else
*changed = true;
@@ -4155,10 +4155,12 @@ skl_compute_wm(struct drm_atomic_state *state)
for_each_crtc_in_state(state, crtc, cstate, i) {
struct intel_crtc_state *intel_cstate =
to_intel_crtc_state(cstate);
+ const struct skl_pipe_wm *old_pipe_wm =
+ &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
pipe_wm = &intel_cstate->wm.skl.optimal;
ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
-&changed);
+old_pipe_wm, &changed);
if (ret)
return ret;
@@ -4203,8 +4205,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
return;
- intel_crtc->wm.active.skl = *pipe_wm;
-
mutex_lock(&dev_priv->wm.wm_mutex);
/*
@@ -4371,7 +4371,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
cstate = to_intel_crtc_state(crtc->state);
skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
- intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
if (!intel_crtc->active)
hw->dirty_pipes |= drm_crtc_mask(crtc);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915/skl+: Clean up minimum allocations.
Move calculating minimum allocations to a helper, which cleans up the
code some more. The cursor is still allocated in advance because it
doesn't count towards data rate and should always be reserved.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 66 -
1 file changed, 39 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 83c1b0acef38..45fb8275abea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3342,6 +3342,32 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
}
+static void
+skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
+uint16_t *minimum, uint16_t *y_minimum)
+{
+ const struct drm_plane_state *pstate;
+ struct drm_plane *plane;
+ enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
+
+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
&cstate->base) {
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int id = skl_wm_plane_id(intel_plane);
+
+ if (intel_plane->pipe != pipe ||
+ id == PLANE_CURSOR)
+ continue;
+
+ if (!pstate->visible)
+ continue;
+
+ minimum[id] = skl_ddb_min_alloc(pstate, 0);
+ y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
+ }
+
+ minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct skl_ddb_allocation *ddb /* out */)
@@ -3350,12 +3376,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_plane *intel_plane;
- struct drm_plane *plane;
- const struct drm_plane_state *pstate;
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
- uint16_t alloc_size, start, cursor_blocks;
+ uint16_t alloc_size, start;
uint16_t minimum[I915_MAX_PLANES] = {};
uint16_t y_minimum[I915_MAX_PLANES] = {};
unsigned int total_data_rate;
@@ -3384,35 +3407,21 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0;
}
- cursor_blocks = skl_cursor_allocation(num_active);
- ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
- ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
-
- alloc_size -= cursor_blocks;
-
- /* 1. Allocate the mininum required blocks for each active plane */
- drm_atomic_crtc_state_for_each_plane_state(plane, pstate,
&cstate->base) {
- intel_plane = to_intel_plane(plane);
- id = skl_wm_plane_id(intel_plane);
-
- if (intel_plane->pipe != pipe)
- continue;
-
- if (!pstate->visible)
- continue;
+ skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
- if (plane->type == DRM_PLANE_TYPE_CURSOR)
- continue;
-
- minimum[id] = skl_ddb_min_alloc(pstate, 0);
- y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
- }
+ /* 1. Allocate the mininum required blocks for each active plane
+* and allocate the cursor, it doesn't require extra allocation
+* proportional to the data rate.
+*/
- for (i = 0; i < PLANE_CURSOR; i++) {
+ for (i = 0; i < I915_MAX_PLANES; i++) {
alloc_size -= minimum[i];
alloc_size -= y_minimum[i];
}
+ ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
minimum[PLANE_CURSOR];
+ ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
+
/*
* 2. Distribute the remaining space in proportion to the amount of
* data each plane needs to fetch from memory.
@@ -3428,6 +3437,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
unsigned rate;
uint16_t plane_blocks, y_plane_blocks = 0;
+ if (id == PLANE_CURSOR)
+ continue;
+
rate = data_rate[id];
/*
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion
Instead of running the watermark updates from the callbacks run
them from a separate hook atomic_evade_watermarks.
This also gets rid of the global skl_results, which was required for
keeping track of the current atomic commit.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
drivers/gpu/drm/i915/intel_display.c | 36 +-
drivers/gpu/drm/i915/intel_drv.h | 7 ---
drivers/gpu/drm/i915/intel_pm.c | 38 ++--
drivers/gpu/drm/i915/intel_sprite.c | 18 -
5 files changed, 28 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 09588c58148f..28e44cb611b8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2027,13 +2027,6 @@ struct drm_i915_private {
*/
uint16_t skl_latency[8];
- /*
-* The skl_wm_values structure is a bit too big for stack
-* allocation, so we keep the staging struct where we store
-* intermediate results here instead.
-*/
- struct skl_wm_values skl_results;
-
/* current hardware state */
union {
struct ilk_wm_values hw;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 340861826c46..d3d7d9dc14a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3377,9 +3377,6 @@ static void skylake_update_primary_plane(struct drm_plane
*plane,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb;
- const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
- const struct skl_plane_wm *p_wm =
- &crtc_state->wm.skl.optimal.planes[0];
int pipe = intel_crtc->pipe;
u32 plane_ctl;
unsigned int rotation = plane_state->base.rotation;
@@ -3415,9 +3412,6 @@ static void skylake_update_primary_plane(struct drm_plane
*plane,
intel_crtc->adjusted_x = src_x;
intel_crtc->adjusted_y = src_y;
- if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
- skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
-
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
@@ -3450,18 +3444,8 @@ static void skylake_disable_primary_plane(struct
drm_plane *primary,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
int pipe = intel_crtc->pipe;
- /*
-* We only populate skl_results on watermark updates, and if the
-* plane's visiblity isn't actually changing neither is its watermarks.
-*/
- if (!crtc->primary->state->visible)
- skl_write_plane_wm(intel_crtc, p_wm,
- &dev_priv->wm.skl_results.ddb, 0);
-
I915_WRITE(PLANE_CTL(pipe, 0), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0);
POSTING_READ(PLANE_SURF(pipe, 0));
@@ -10824,16 +10808,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc,
u32 base,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
- const struct skl_plane_wm *p_wm =
- &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
int pipe = intel_crtc->pipe;
uint32_t cntl = 0;
- if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
- skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
-
if (plane_state && plane_state->base.visible) {
cntl = MCURSOR_GAMMA_ENABLE;
switch (plane_state->base.crtc_w) {
@@ -14436,8 +14413,13 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
- if (!crtc->state->active)
- intel_update_watermarks(crtc);
+ if (!crtc->state->active) {
+ if (dev_priv->display.initial_watermarks)
+
dev_priv->display.initial_watermarks(intel_state,
+
[Intel-gfx] [PATCH 3/8] drm/i915/skl+: Remove minimum block allocation from crtc state.
This is not required any more now that we get fresh state from
drm_atomic_crtc_state_for_each_plane_state. Zero all state
in advance.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_drv.h | 4
drivers/gpu/drm/i915/intel_pm.c | 15 +--
2 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 888054518f3c..a176e6cebab3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -501,10 +501,6 @@ struct intel_crtc_wm_state {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
-
- /* minimum block allocation */
- uint16_t minimum_blocks[I915_MAX_PLANES];
- uint16_t minimum_y_blocks[I915_MAX_PLANES];
} skl;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 97b6202c4097..83c1b0acef38 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3356,8 +3356,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
uint16_t alloc_size, start, cursor_blocks;
- uint16_t *minimum = cstate->wm.skl.minimum_blocks;
- uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
+ uint16_t minimum[I915_MAX_PLANES] = {};
+ uint16_t y_minimum[I915_MAX_PLANES] = {};
unsigned int total_data_rate;
int num_active;
int id, i;
@@ -3398,16 +3398,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
if (intel_plane->pipe != pipe)
continue;
- if (!pstate->visible) {
- minimum[id] = 0;
- y_minimum[id] = 0;
+ if (!pstate->visible)
continue;
- }
- if (plane->type == DRM_PLANE_TYPE_CURSOR) {
- minimum[id] = 0;
- y_minimum[id] = 0;
+
+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
continue;
- }
minimum[id] = skl_ddb_min_alloc(pstate, 0);
y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
--
2.7.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915/gen9+: Preserve old allocation from crtc_state.
This is the last bit required for making nonblocking modesets work
correctly. The state in intel_crtc->hw_ddb is not updated until
somewhere in atomic commit, while the previous crtc state should be
accurate if the ddb hasn't changed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d3d7d9dc14a8..93e16da0aa51 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14332,7 +14332,7 @@ static void skl_update_crtcs(struct drm_atomic_state
*state,
* new ddb allocation to take effect.
*/
if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
-&intel_crtc->hw_ddb) &&
+
&to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
!crtc->state->active_changed &&
intel_state->wm_results.dirty_pipes != updated)
vbl_wait = true;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 18c62d1eea19..182e6b30b60a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3091,7 +3091,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
* we currently hold.
*/
if (!intel_state->active_pipe_changes) {
- *alloc = to_intel_crtc(for_crtc)->hw_ddb;
+ /*
+* alloc may be cleared by clear_intel_crtc_state,
+* copy from old state to be sure
+*/
+ *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
return;
}
--
2.7.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make sure the base lives at offset 0 of all kms objects
== Series Details == Series: drm/i915: Make sure the base lives at offset 0 of all kms objects URL : https://patchwork.freedesktop.org/series/13640/ State : failure == Summary == Series 13640v1 drm/i915: Make sure the base lives at offset 0 of all kms objects https://patchwork.freedesktop.org/api/1.0/series/13640/revisions/1/mbox/ Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6700hq) Test vgem_basic: Subgroup unload: pass -> SKIP (fi-kbl-7200u) pass -> SKIP (fi-bdw-5557u) Test vgem_reload_basic: pass -> FAIL (fi-bdw-5557u) fi-bdw-5557u total:248 pass:230 dwarn:0 dfail:0 fail:1 skip:17 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:224 dwarn:1 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2684/ 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-12d-11h-06m-41s UTC integration manifest 6c56c1c drm/i915: Make sure the base lives at offset 0 of all kms objects ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh
On Wed, Oct 12, 2016 at 04:04:34PM +0300, Jani Nikula wrote: > On Wed, 12 Oct 2016, Joonas Lahtinen wrote: > > On ke, 2016-10-12 at 14:16 +0300, Jani Nikula wrote: > >> If you really care, go ahead and send the patches to make these Bourne > >> shell compatible, but then do also sign up for testing them on non-bash > >> shells. The CI won't. I don't think it's worth the trouble, but YMMV. > > > > If they're re-written using POSIX sh constructs only, I don't think > > they need to be tested outside of POSIX sh? That's what standards are > > for. > > It's just that if the majority of folks and the CI have bash as /bin/sh, > we won't notice when we accidentally add bashisms, and it'll eventually > break. Maybe you could keep running shellcheck [1] on them, or > something. At the very least most/all Debian and Ubuntu systems use dash as /bin/sh. It supports a very small subset of the bashisms (most notably local), and is faster than bash. > [1] https://www.shellcheck.net/ > > > I also remember FreeBSD guys being all for letting bash dependency go. > > So there'd be actual gains too. > > I'm biting my lips not to quip on that. > > > All are easily convertible. So let's do this. > > If you have the time, go ahead. But don't break *any* functionality, no > compromises. Kind regards, David ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD
> Test kms_flip: > Subgroup basic-flip-vs-modeset: > pass -> DMESG-WARN (fi-skl-6770hq) [ 468.807117] [drm:skl_set_cdclk [i915]] *ERROR* failed to inform PCU about cdclk change [ 468.816844] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (fi-ilk-650) [ 445.727655] [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO underrun [ 445.727682] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun > Test vgem_basic: > Subgroup unload: > skip -> PASS (fi-hsw-4770) > > fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 > fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 > fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 > fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 > fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 > fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 > fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 > fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 > fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 > fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 > fi-skl-6770hqtotal:248 pass:230 dwarn:2 dfail:0 fail:1 skip:15 > fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 > fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 > > Results at /archive/results/CI_IGT_test/Patchwork_2683/ > > 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m- > 12d-11h-06m-41s UTC integration manifest > 35edc31 drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh
On Wed, 12 Oct 2016, Joonas Lahtinen wrote: > On ke, 2016-10-12 at 14:16 +0300, Jani Nikula wrote: >> If you really care, go ahead and send the patches to make these Bourne >> shell compatible, but then do also sign up for testing them on non-bash >> shells. The CI won't. I don't think it's worth the trouble, but YMMV. > > If they're re-written using POSIX sh constructs only, I don't think > they need to be tested outside of POSIX sh? That's what standards are > for. It's just that if the majority of folks and the CI have bash as /bin/sh, we won't notice when we accidentally add bashisms, and it'll eventually break. Maybe you could keep running shellcheck [1] on them, or something. [1] https://www.shellcheck.net/ > I also remember FreeBSD guys being all for letting bash dependency go. > So there'd be actual gains too. I'm biting my lips not to quip on that. > All are easily convertible. So let's do this. If you have the time, go ahead. But don't break *any* functionality, no compromises. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD
== Series Details == Series: drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD URL : https://patchwork.freedesktop.org/series/13639/ State : warning == Summary == Series 13639v1 drm/i915: Fix misplaced ' ' in printing the GPU error's RING_HEAD https://patchwork.freedesktop.org/api/1.0/series/13639/revisions/1/mbox/ Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Test vgem_basic: Subgroup unload: skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:184 dwarn:1 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:230 dwarn:2 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2683/ 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-12d-11h-06m-41s UTC integration manifest 35edc31 drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test
Op 07-10-16 om 13:45 schreef Mika Kahola:
> This is a testcase with multiple planes. The idea here is the following
>
> - draw a uniform frame with blue color
> - grab crc for reference
> - put planes randomly on top with the same blue color
> - punch holes with black color into the primary framebuffer
> - ideally the planes should cover these holes so that the output is the
>identical to reference crc
> - composite all with one ioctl call
> - grab crc and verify that the reference crc is equal
> - repeat this for dozen iterations to maximize coverage
>
> Signed-off-by: Mika Kahola
> ---
> tests/Makefile.sources | 1 +
> tests/kms_plane_multiple.c | 332
> +
> 2 files changed, 333 insertions(+)
> create mode 100644 tests/kms_plane_multiple.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 598ec6f..aed0f3a 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -105,6 +105,7 @@ TESTS_progs_M = \
> kms_pipe_color \
> kms_pipe_crc_basic \
> kms_plane \
> + kms_plane_multiple \
> kms_properties \
> kms_psr_sink_crc \
> kms_render \
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> new file mode 100644
> index 000..153d6d1
> --- /dev/null
> +++ b/tests/kms_plane_multiple.c
> @@ -0,0 +1,332 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define SIZE 128
> +
> +typedef struct {
> + float red;
> + float green;
> + float blue;
> +} color_t;
> +
> +typedef struct {
> + int drm_fd;
> + igt_display_t display;
> + igt_pipe_crc_t *pipe_crc;
> + igt_plane_t *primary;
> + igt_plane_t *sprite[IGT_MAX_PLANES-1];
> + struct igt_fb primary_fb;
> + struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
Single array, instead of primary/sprite separate? See also below for index
change..
> +} data_t;
> +
> +typedef struct {
> + data_t *data;
> + igt_crc_t reference_crc;
> +} test_position_t;
> +
> +/*
> + * Common code across all tests, acting on data_t
> + */
> +static void test_init(data_t *data, enum pipe pipe)
> +{
> + data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
> +}
> +
> +static void test_fini(data_t *data, igt_output_t *output, int nplanes)
> +{
> + igt_plane_set_fb(data->primary, NULL);
> +
> + for (int i = 0; i < nplanes; i++)
> + igt_plane_set_fb(data->sprite[i], NULL);
> +
> + /* reset the constraint on the pipe */
> + igt_output_set_pipe(output, PIPE_ANY);
> +
> + igt_pipe_crc_free(data->pipe_crc);
> +}
> +
> +static void
> +test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
> + color_t *color, uint64_t tiling, int commit,
> + igt_crc_t *crc /* out */)
> +{
> + struct igt_fb fb;
> + drmModeModeInfo *mode;
> + igt_plane_t *primary;
> +
> + igt_output_set_pipe(output, pipe);
> +
> + primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
> +
> + mode = igt_output_get_mode(output);
> +
> + igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + color->red, color->green, color->blue,
> + &fb);
> +
> + igt_plane_set_fb(primary, &fb);
> +
> + igt_display_commit2(&data->display, commit);
> +
> + igt_wait_for_vblank(data->drm_fd, pipe);
> +
> + igt_pipe_crc_collect_crc(data->pipe_crc, crc);
> +
> + igt_plane_set_fb(primary, NULL);
> +
> + igt_display_commit2(&data->display, commit);
> +
> + igt_remove_fb(data->drm_fd, &fb
Re: [Intel-gfx] [PATCH 20/42] drm/i915: Implement pread without struct-mutex
On pe, 2016-10-07 at 10:46 +0100, Chris Wilson wrote:
> @@ -871,7 +845,7 @@ shmem_clflush_swizzled_range(char *addr, unsigned long
> length,
> /* Only difference to the fast-path function is that this can handle bit17
> * and uses non-atomic copy and kmap functions. */
> static int
> -shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
> +shmem_pread_slow(struct page *page, int offset, int length,
Lets maybe call this shmem_pread_cpu? I understand it's been faster on
recent generations even for swizzling. Can be added as follow-up.
> +static int
> +i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
> + struct drm_i915_gem_pread *args)
> +{
> + char __user *user_data;
> + u64 remain;
> + unsigned int obj_do_bit17_swizzling;
> + unsigned int needs_clflush;
> + unsigned int idx, offset;
> + int ret;
> +
> + obj_do_bit17_swizzling = 0;
> + if (i915_gem_object_needs_bit17_swizzle(obj))
> + obj_do_bit17_swizzling = 1 << 17;
Could use BIT(17) to make it super explicit.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
PS. Something like C context-aware diff would be super, would make
reading these much more fun. Or maybe patchwork 2-way diff view.
--
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake
On Wed, Oct 12, 2016 at 03:39:47PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 12, 2016 at 12:58:34PM +0100, Chris Wilson wrote:
> > On Wed, Oct 12, 2016 at 02:44:47PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > GMBUS is part of the display engine, and thus has no need for
> > > forcewake. Let's not bother trying to grab it then.
> > >
> > > I don't recall if the display engine suffers from system hangs
> > > due to multiple accesses to the same "cacheline" in mmio space.
> > > I hope not since we're no longer protected by the uncore lock
> > > since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
> > > the entire GMBUS transaction")
> >
> > Only applies to concurrent access to the same cacheline, in this case
> > should be serialised by the mutex around the gmbus xfer.
>
> Hmm. Yeah, I suppose there shouldn't be unrelated stuff nearby. Haven't
> double checked though.
>
> >
> > > Cc: Chris Wilson
> > > Cc: David Weinehall
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/intel_i2c.c | 5 -
> > > 1 file changed, 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > > b/drivers/gpu/drm/i915/intel_i2c.c
> > > index 79aab9ad6faa..49c7824a4c29 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct
> > > i2c_msg *msgs, int num)
> > > struct intel_gmbus,
> > > adapter);
> > > struct drm_i915_private *dev_priv = bus->dev_priv;
> > > - const unsigned int fw =
> > > - intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > > -FW_REG_READ | FW_REG_WRITE);
> > > int i = 0, inc, try = 0;
> > > int ret = 0;
> >
> > I915_WARN_ON(intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > FW_REG_READ |
> > FW_REG_WRITE));
> >
> > ? Would be good to test the fw handling as well.
>
> Not sure I'd want to sprinkle forcewake testing into modeset code.
You never use registers here? ;)
Reviewed-by: Chris Wilson
-Chris
--
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Re: [Intel-gfx] [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
On Wed, Oct 12, 2016 at 01:06:51PM +0100, Tvrtko Ursulin wrote:
>
> On 12/10/2016 12:52, David Weinehall wrote:
> > On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Saves 1392 bytes of .rodata strings.
> > >
> > > v2: Add parantheses around dev_priv. (Ville Syrjala)
> > >
> > > Signed-off-by: Tvrtko Ursulin
> > This patch does quite a bit more than just change IS_BROXTON to use
> > dev_priv...
>
> Some cascade effects on function prototypes here and there - if you find it
> objectionable I can try to eliminate or at least minimise?
I don't find the changes objectionable -- they are, as you say, cascade
effects. It might, however, be worth explaining in the patch description
that the patch does a bit more than just more than IS_BROXTON(). Doing
so for just minor differences is overkill, but in this case it feels
justified.
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> > > drivers/gpu/drm/i915/i915_gem_gtt.c | 40
> > > +
> > > drivers/gpu/drm/i915/i915_irq.c | 2 +-
> > > drivers/gpu/drm/i915/intel_ddi.c| 4 ++--
> > > drivers/gpu/drm/i915/intel_display.c| 31 ++---
> > > drivers/gpu/drm/i915/intel_dp.c | 16 ++---
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> > > drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
> > > drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++
> > > drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> > > 13 files changed, 89 insertions(+), 82 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index d854ea4a7e92..18af6d1ccec9 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> > > if (IS_GEN6(dev_priv))
> > > intel_init_pch_refclk(dev);
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > bxt_disable_dc9(dev_priv);
> > > bxt_display_core_init(dev_priv, true);
> > > if (dev_priv->csr.dmc_payload &&
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 9784e61400e5..ad9299196d13 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
> > > #define IS_HASWELL(dev_priv)((dev_priv)->info.is_haswell)
> > > #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> > > #define IS_SKYLAKE(dev_priv)((dev_priv)->info.is_skylake)
> > > -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> > > +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> > > #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> > > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
> > > #define BXT_REVID_B00x3
> > > #define BXT_REVID_C00x9
> > > -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p,
> > > since, until))
> > > +#define IS_BXT_REVID(dev_priv, since, until) \
> > > + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> > > #define KBL_REVID_A00x0
> > > #define KBL_REVID_B00x1
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index cf43a5632961..e628691fe97e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> > > /* We use the flushing unmap only with ppgtt structures:
> > >* page directories, page tables and scratch pages.
> > >*/
> > > -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> > > +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void
> > > *vaddr)
> > > {
> > > /* There are only few exceptions for gen >=6. chv and bxt.
> > >* And we are not sure about the latter so play safe for now.
> > >*/
> > > - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > drm_clflush_virt_range(vaddr, PAGE_SIZE);
> > > kunmap_atomic(vaddr);
> > > }
> > > #define kmap_px(px) kmap_page_dma(px_base(px))
> > > -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev,
> > > (vaddr))
> > > +#define kunmap_px(ppgtt, vaddr) \
> > > + kunmap_page
[Intel-gfx] [CI] drm/i915: Treat a framebuffer reference as an active reference whilst shrinking
Treat a framebuffer reference with the same priority as an active reference whilst shrinking. Framebuffers are likely to be reused and typically cost more to migrate to and from GPU memory (on LLC architectures we need to clflush), so defer the temptation to purge them during a kswapd run until we have run out of cheap buffers. Signed-off-by: Chris Wilson Reviewed-by: John Harrison --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 1c237d02f30b..de25b6e0a101 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -182,8 +182,9 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, !is_vmalloc_addr(obj->mapping)) continue; - if ((flags & I915_SHRINK_ACTIVE) == 0 && - i915_gem_object_is_active(obj)) + if (!(flags & I915_SHRINK_ACTIVE) && + (i915_gem_object_is_active(obj) || +obj->framebuffer_references)) continue; if (!can_release_pages(obj)) -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test
This is a testcase with multiple planes. The idea here is the following
- draw a uniform frame with blue color
- grab crc for reference
- put planes randomly on top with the same blue color
- punch holes with black color into the primary framebuffer
- ideally the planes should cover these holes so that the output is the
identical to reference crc
- composite all with one ioctl call
- grab crc and verify that the reference crc is equal
- repeat this for dozen iterations to maximize coverage
v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 421 +
1 file changed, 421 insertions(+)
create mode 100644 tests/kms_plane_multiple.c
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..cafd409
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include
+#include
+#include
+#include
+#include
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define SIZE 128
+
+typedef struct {
+ float red;
+ float green;
+ float blue;
+} color_t;
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ igt_pipe_crc_t *pipe_crc;
+ igt_plane_t *primary;
+ igt_plane_t *sprite[IGT_MAX_PLANES-1];
+ struct igt_fb primary_fb;
+ struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
+} data_t;
+
+typedef struct {
+ data_t *data;
+ igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+ bool user_seed;
+ int seed;
+ bool user_logfile;
+ char logfile[SIZE];
+} opt = {
+ .user_seed = false,
+ .seed = 1,
+ .user_logfile = false,
+ .logfile = "kms_plane_multiple.log",
+};
+
+
+static int logwrite(const char *testname)
+{
+ time_t curr_time;
+ FILE *fid;
+ char *time_str;
+
+ fid = fopen(opt.logfile, "a");
+
+ if (fid == NULL) {
+ igt_debug("Could not open file %s\n", opt.logfile);
+ return -1;
+ }
+
+ curr_time = time(NULL);
+
+ time_str = ctime(&curr_time);
+ time_str[strlen(time_str)-1] = '\0';
+
+ fprintf(fid, "%s: kms_plane_multiple --run-subtest %s --seed %d\n",
+ time_str, testname, opt.seed);
+
+ fclose(fid);
+
+ return 0;
+}
+
+/*
+ * Common code across all tests, acting on data_t
+ */
+static void test_init(data_t *data, enum pipe pipe)
+{
+ data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+}
+
+static void test_fini(data_t *data, igt_output_t *output, int nplanes)
+{
+ igt_plane_set_fb(data->primary, NULL);
+
+ for (int i = 0; i < nplanes; i++)
+ igt_plane_set_fb(data->sprite[i], NULL);
+
+ /* reset the constraint on the pipe */
+ igt_output_set_pipe(output, PIPE_ANY);
+
+ igt_pipe_crc_free(data->pipe_crc);
+}
+
+static void
+test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
+ color_t *color, uint64_t tiling, int commit,
+ igt_crc_t *crc /* out */)
+{
+ struct igt_fb fb;
+ drmModeModeInfo *mode;
+ igt_plane_t *primary;
+
+ igt_output_set_pipe(output, pipe);
+
+ primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+
+ mode = igt_output_get_mode(output);
+
+ igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_DRM_FORMAT_MOD_NONE,
+ color->red, color->green, color->blue,
+ &fb);
+
+ igt_plane_set_fb(
Re: [Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake
On Wed, Oct 12, 2016 at 12:58:34PM +0100, Chris Wilson wrote:
> On Wed, Oct 12, 2016 at 02:44:47PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > GMBUS is part of the display engine, and thus has no need for
> > forcewake. Let's not bother trying to grab it then.
> >
> > I don't recall if the display engine suffers from system hangs
> > due to multiple accesses to the same "cacheline" in mmio space.
> > I hope not since we're no longer protected by the uncore lock
> > since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
> > the entire GMBUS transaction")
>
> Only applies to concurrent access to the same cacheline, in this case
> should be serialised by the mutex around the gmbus xfer.
Hmm. Yeah, I suppose there shouldn't be unrelated stuff nearby. Haven't
double checked though.
>
> > Cc: Chris Wilson
> > Cc: David Weinehall
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_i2c.c | 5 -
> > 1 file changed, 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > b/drivers/gpu/drm/i915/intel_i2c.c
> > index 79aab9ad6faa..49c7824a4c29 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct
> > i2c_msg *msgs, int num)
> >struct intel_gmbus,
> >adapter);
> > struct drm_i915_private *dev_priv = bus->dev_priv;
> > - const unsigned int fw =
> > - intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > - FW_REG_READ | FW_REG_WRITE);
> > int i = 0, inc, try = 0;
> > int ret = 0;
>
> I915_WARN_ON(intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> FW_REG_READ |
> FW_REG_WRITE));
>
> ? Would be good to test the fw handling as well.
Not sure I'd want to sprinkle forcewake testing into modeset code.
--
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Intel OTC
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[Intel-gfx] [CI 2/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range
Let's use more top-down approach, where each gen8_ppgtt_clear_* function
is responsible for clearing the struct passed as an argument and calling
relevant clear_range functions on lower-level tables.
Doing this rather than operating on PTE ranges makes the implementation
of shrinking page tables quite simple.
v2: Drop min when calculating num_entries, no negation in 48b ppgtt
check, no newlines in vars block (Joonas)
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 107 +++-
1 file changed, 58 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 48ec9c5..c284d8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,59 +704,78 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
}
-static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
- struct i915_page_directory_pointer *pdp,
- uint64_t start,
- uint64_t length,
- gen8_pte_t scratch_pte)
+static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ uint64_t start,
+ uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ unsigned int pte_start = gen8_pte_index(start);
+ unsigned int num_entries = gen8_pte_count(start, length);
+ uint64_t pte;
gen8_pte_t *pt_vaddr;
- unsigned pdpe = gen8_pdpe_index(start);
- unsigned pde = gen8_pde_index(start);
- unsigned pte = gen8_pte_index(start);
- unsigned num_entries = length >> PAGE_SHIFT;
- unsigned last_pte, i;
+ gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
+I915_CACHE_LLC);
- if (WARN_ON(!pdp))
+ if (WARN_ON(!px_page(pt)))
return;
- while (num_entries) {
- struct i915_page_directory *pd;
- struct i915_page_table *pt;
+ bitmap_clear(pt->used_ptes, pte_start, num_entries);
- if (WARN_ON(!pdp->page_directory[pdpe]))
- break;
+ pt_vaddr = kmap_px(pt);
+
+ for (pte = pte_start; pte < num_entries; pte++)
+ pt_vaddr[pte] = scratch_pte;
- pd = pdp->page_directory[pdpe];
+ kunmap_px(ppgtt, pt_vaddr);
+}
+
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ uint64_t start,
+ uint64_t length)
+{
+ struct i915_page_table *pt;
+ uint64_t pde;
+ gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
- pt = pd->page_table[pde];
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+ }
+}
- if (WARN_ON(!px_page(pt)))
- break;
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+struct i915_page_directory_pointer *pdp,
+uint64_t start,
+uint64_t length)
+{
+ struct i915_page_directory *pd;
+ uint64_t pdpe;
- last_pte = pte + num_entries;
- if (last_pte > GEN8_PTES)
- last_pte = GEN8_PTES;
+ gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
+ if (WARN_ON(!pdp->page_directory[pdpe]))
+ break;
- pt_vaddr = kmap_px(pt);
+ gen8_ppgtt_clear_pd(vm, pd, start, length);
+ }
+}
- for (i = pte; i < last_pte; i++) {
- pt_vaddr[i] = scratch_pte;
- num_entries--;
- }
+static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm,
+ struct i915_pml4 *pml4,
+ uint64_t start,
+ uint64_t length)
+{
+ struct i915_page_directory_pointer *pdp;
+ uint64_t pml4e;
- kunmap_px(ppgtt, pt_vaddr);
+ gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
+ if (WARN_ON(!pml4->pdps[pml4e]))
+ break;
- pte = 0;
- if (++pde == I915_PDES) {
- if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
- break;
- pde = 0;
- }
+ gen8_ppgtt_clear_pdp(vm, pdp,
[Intel-gfx] [CI 1/3] drm/i915: Remove unused "valid" parameter from pte_encode
We never used any invalid ptes, those were put in place for
a possibility of doing gpu faults. However our batchbuffers are not
restricted in length, so everything needs to be pointing to something
and thus out-of-bounds is pointing to scratch.
Remove the valid flag as it is always true.
v2: Expand commit msg, patch reorder (Mika)
Cc: Chris Wilson
Cc: Michel Thierry
Reviewed-by: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 98 --
drivers/gpu/drm/i915/i915_gem_gtt.h| 5 +-
4 files changed, 45 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e..ec2335c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -919,8 +919,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(&ggtt->base,
- node.start, node.size,
- true);
+ node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node(&node);
} else {
@@ -1228,8 +1227,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(&ggtt->base,
- node.start, node.size,
- true);
+ node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node(&node);
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 72c7c18..6835074 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -370,8 +370,7 @@ static void reloc_cache_fini(struct reloc_cache *cache)
ggtt->base.clear_range(&ggtt->base,
cache->node.start,
- cache->node.size,
- true);
+ cache->node.size);
drm_mm_remove_node(&cache->node);
} else {
i915_vma_unpin((struct i915_vma *)cache->node.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2d846aa..48ec9c5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -191,15 +191,13 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
{
vma->vm->clear_range(vma->vm,
vma->node.start,
-vma->size,
-true);
+vma->size);
}
static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- bool valid)
+ enum i915_cache_level level)
{
- gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+ gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
pte |= addr;
switch (level) {
@@ -234,9 +232,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
static gen6_pte_t snb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
switch (level) {
@@ -256,9 +254,9 @@ static gen6_pte_t snb_pte_encode(dma_addr_t addr,
static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
switch (level) {
@@ -280,9 +278,9 @@ static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
static gen6_pte_t byt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-bool valid, u32 flags)
+u32 flags)
{
- gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+ gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
if (!(flags & PTE_READ_ONLY))
@@ -296,9 +294,9 @@ static gen6_pte_t byt_pte_encode(dma_addr_t addr,
static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
-
[Intel-gfx] [CI 3/3] drm/i915/gtt: Free unused lower-level page tables
Since "Dynamic page table allocations" were introduced, our page tables
can grow (being dynamically allocated) with address space range usage.
Unfortunately, their lifetime is bound to vm. This is not a huge problem
when we're not using softpin - drm_mm is creating an upper bound on used
range by causing addresses for our VMAs to eventually be reused.
With softpin, long lived contexts can drain the system out of memory
even with a single "small" object. For example:
bo = bo_alloc(size);
while(true)
offset += size;
exec(bo, offset);
Will cause us to create new allocations until all memory in the system
is used for tracking GPU pages (even though almost all PTEs in this vm
are pointing to scratch).
Let's free unused page tables in clear_range to prevent this - if no
entries are used, we can safely free it and return this information to
the caller (so that higher-level entry is pointing to scratch).
v2: Document return value and free semantics (Joonas)
v3: No newlines in vars block (Joonas)
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 84 +
1 file changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c284d8d..e733657 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,13 +704,14 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
}
-static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+/* Removes entries from a single page table, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries */
+static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
uint64_t start,
uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
-
unsigned int pte_start = gen8_pte_index(start);
unsigned int num_entries = gen8_pte_count(start, length);
uint64_t pte;
@@ -719,63 +720,130 @@ static void gen8_ppgtt_clear_pt(struct
i915_address_space *vm,
I915_CACHE_LLC);
if (WARN_ON(!px_page(pt)))
- return;
+ return false;
bitmap_clear(pt->used_ptes, pte_start, num_entries);
+ if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
+ free_pt(vm->dev, pt);
+ return true;
+ }
+
pt_vaddr = kmap_px(pt);
for (pte = pte_start; pte < num_entries; pte++)
pt_vaddr[pte] = scratch_pte;
kunmap_px(ppgtt, pt_vaddr);
+
+ return false;
}
-static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+/* Removes entries from a single page dir, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
uint64_t start,
uint64_t length)
{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_table *pt;
uint64_t pde;
+ gen8_pde_t *pde_vaddr;
+ gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt),
+I915_CACHE_LLC);
+ bool reduce;
gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
- gen8_ppgtt_clear_pt(vm, pt, start, length);
+ reduce = gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+ if (reduce) {
+ __clear_bit(pde, pd->used_pdes);
+ pde_vaddr = kmap_px(pd);
+ pde_vaddr[pde] = scratch_pde;
+ kunmap_px(ppgtt, pde_vaddr);
+ }
+ }
+
+ if (bitmap_empty(pd->used_pdes, I915_PDES)) {
+ free_pd(vm->dev, pd);
+ return true;
}
+
+ return false;
}
-static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+/* Removes entries from a single page dir pointer, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp,
uint64_t start,
uint64_t length)
{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory *pd;
uint64_t pdpe;
+ gen8_ppgtt_pdpe_t *pdpe_vaddr;
+ gen8_ppgtt_pdpe_t scratch_
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/5] drm/i915: Use fence_write() from rpm resume
== Series Details == Series: series starting with [1/5] drm/i915: Use fence_write() from rpm resume URL : https://patchwork.freedesktop.org/series/13636/ State : warning == Summary == Series 13636v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/13636/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6700k) Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-j1900) Test vgem_basic: Subgroup unload: skip -> PASS (fi-hsw-4770) fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16 fi-bsw-n3050 total:248 pass:205 dwarn:0 dfail:0 fail:0 skip:43 fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31 fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32 fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36 fi-hsw-4770 total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-hsw-4770r total:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61 fi-ivb-3520m total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-ivb-3770 total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26 fi-kbl-7200u total:248 pass:223 dwarn:0 dfail:0 fail:0 skip:25 fi-skl-6260u total:248 pass:233 dwarn:0 dfail:0 fail:0 skip:15 fi-skl-6700hqtotal:248 pass:225 dwarn:0 dfail:0 fail:0 skip:23 fi-skl-6700k total:248 pass:221 dwarn:2 dfail:0 fail:0 skip:25 fi-skl-6770hqtotal:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37 fi-snb-2600 total:248 pass:210 dwarn:0 dfail:0 fail:0 skip:38 Results at /archive/results/CI_IGT_test/Patchwork_2682/ 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-12d-11h-06m-41s UTC integration manifest e4a3f83 drm/i915: Remove superfluous locking around userfault_list 1cacb0e drm/i915: Use RPM as the barrier for controlling user mmap access 8092cc0 drm/i915: Move user fault tracking to a separate list 9b29980 drm/i915: Update debugfs describe_obj() to show fault-mappable 42b8e6b drm/i915: Use fence_write() from rpm resume ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] intel-ci: Remove kms_psr_sink_crc@psr_basic from BAT
The test is producing a lot of CI noise. Signed-off-by: Petri Latvala --- Will be pushed shortly. Visible in CI results tomorrow-ish. tests/intel-ci/fast-feedback.testlist | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index ae94381..e2fc9ac 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -208,7 +208,6 @@ igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c -igt@kms_psr_sink_crc@psr_basic igt@kms_setmode@basic-clone-single-crtc igt@kms_sink_crc_basic igt@pm_backlight@basic-brightness -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW only take dev_priv
On Tue, Oct 11, 2016 at 02:21:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Saves 864 bytes of .rodata strings and ~100 of .text.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_audio.c | 4 +-
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c| 67
> +
> drivers/gpu/drm/i915/intel_dp.c | 55 ++-
> drivers/gpu/drm/i915/intel_dsi.c| 8 ++--
> drivers/gpu/drm/i915/intel_hdmi.c | 10 ++---
> drivers/gpu/drm/i915/intel_i2c.c| 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_psr.c| 4 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_sprite.c | 10 +++--
> 14 files changed, 93 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 18af6d1ccec9..5e7b6a1cb2c8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -424,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
> u32 temp;
> bool enabled;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return;
>
> dev_priv->mchbar_need_disable = false;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f54465ea2f44..96846ecfc224 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2660,7 +2660,7 @@ struct drm_i915_cmd_table {
>INTEL_DEVID(dev_priv) == 0x0152 || \
>INTEL_DEVID(dev_priv) == 0x015a)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> -#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> +#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> @@ -3838,11 +3838,11 @@ __raw_write(64, q)
> #define INTEL_BROADCAST_RGB_FULL 1
> #define INTEL_BROADCAST_RGB_LIMITED 2
>
> -static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
> +static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
> {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return VLV_VGACNTRL;
> - else if (INTEL_INFO(dev)->gen >= 5)
> + else if (INTEL_GEN(dev_priv) >= 5)
> return CPU_VGACNTRL;
> else
> return VGACNTRL;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e628691fe97e..4211b9a4a918 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device
> *dev)
> /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 13b726916f98..d1275cbd5905 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -428,8 +428,8 @@ static void ilk_audio_codec_enable(struct drm_connector
> *connector,
> aud_config = IBX_AUD_CFG(pipe);
> aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
> aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> - } else if (IS_VALLEYVIEW(connector->dev) ||
> -IS_CHERRYVIEW(connector->dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) ||
> +IS_CHERRYVIEW(dev_priv)) {
> hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
> aud_config = VLV_AUD_CFG(pipe);
> aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index da76a799411a..445108855275 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -534,7 +534,7 @@ void intel_color_init(struct drm_crtc *crtc)
>
> drm_mode_crtc_set_gamma_size(crtc, 256);
>
> - if (IS_CHERRYVI
Re: [Intel-gfx] [PATCH 09/19] drm/i915: Make IS_BROADWELL only take dev_priv
On Tue, Oct 11, 2016 at 02:21:42PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Saves 1808 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_drv.h | 6 +++---
> drivers/gpu/drm/i915/i915_gem.c | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c| 21 +++--
> drivers/gpu/drm/i915/intel_dp.c | 19 ++-
> drivers/gpu/drm/i915/intel_pm.c | 20 +++-
> drivers/gpu/drm/i915/intel_psr.c| 4 ++--
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> drivers/gpu/drm/i915/intel_sprite.c | 8
> 11 files changed, 52 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f6ba8f262238..8899835fffab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(IS_HSW_ULT(dev_priv) ||
> IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(!IS_HSW_ULT(dev_priv) &&
> !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f321932d18a..13e409554fcc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev)(INTEL_INFO(dev)->is_broadwell)
> +#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> @@ -2769,8 +2769,8 @@ struct drm_i915_cmd_table {
> #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
> #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
> #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap &
> EDRAM_ENABLED))
> -#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> - HAS_EDRAM(dev))
> +#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> + IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
> #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
>
> #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6da841500510..aefb88f987b2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3473,7 +3473,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
> void *data,
> level = I915_CACHE_LLC;
> break;
> case I915_CACHING_DISPLAY:
> - level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
> + level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
> break;
> default:
> return -EINVAL;
> @@ -3531,7 +3531,8 @@ i915_gem_object_pin_to_display_plane(struct
> drm_i915_gem_object *obj,
>* with that bit in the PTE to main memory with just one PIPE_CONTROL.
>*/
> ret = i915_gem_object_set_cache_level(obj,
> - HAS_WT(obj->base.dev) ?
> I915_CACHE_WT : I915_CACHE_NONE);
> + HAS_WT(to_i915(obj->base.dev)) ?
> + I915_CACHE_WT : I915_CACHE_NONE);
>
Re: [Intel-gfx] [RFC i-g-t PATCH 2/3] igt/gem_wait: Use new igt_dummyload api
On Wed, Oct 12, 2016 at 02:59:53PM +0300, Abdiel Janulgue wrote: > Signed-off-by: Abdiel Janulgue > --- > tests/gem_wait.c | 77 > +--- > 1 file changed, 12 insertions(+), 65 deletions(-) We can do so much better than a dummy load here. We can precisely control how long we want the object to be busy by using a recursive batch buffer (and terminating that batch at the exact moment we require). -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
On 12/10/2016 12:52, David Weinehall wrote:
On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Saves 1392 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin
This patch does quite a bit more than just change IS_BROXTON to use
dev_priv...
Some cascade effects on function prototypes here and there - if you find
it objectionable I can try to eliminate or at least minimise?
Regards,
Tvrtko
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c| 4 ++--
drivers/gpu/drm/i915/intel_display.c| 31 ++---
drivers/gpu/drm/i915/intel_dp.c | 16 ++---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++
drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
13 files changed, 89 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d854ea4a7e92..18af6d1ccec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9784e61400e5..ad9299196d13 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv)((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
-#define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
+#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev)(INTEL_INFO(dev)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
#define BXT_REVID_B0 0x3
#define BXT_REVID_C0 0x9
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+#define IS_BXT_REVID(dev_priv, since, until) \
+ (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cf43a5632961..e628691fe97e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
/* We use the flushing unmap only with ppgtt structures:
* page directories, page tables and scratch pages.
*/
-static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
{
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
}
#define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define kunmap_px(ppgtt, vaddr) \
+ kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
-#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
-#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
+#define fill32_px(dev_priv, px, v) \
+ fill_page_dma_32((dev_priv), px_base(px), (v))
-static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
- const uint64_t val)
+static void fill_page_dma(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint64_t val)
{
int i;
uint64_t * const vaddr = kmap_page_dma(p);
@@ -401,17 +403,17 @@ static void f
Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
On Wed, 2016-10-12 at 14:08 +0300, Joonas Lahtinen wrote: > Bisecting the offending commit between v4.8 and v4.8.1 would be a good > start. That would be between v4.7 and v4.8. (I guess my report was ambiguous.) That might take some time. Because bisecting always takes a long time and especially since hitting this WARNING sometimes takes over an hour. Anyhow, please prod me if I stay silent for too long. Thanks, Paul Bolle ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
