date:20170823

Re: [Intel-gfx] [PATCH] drm/i915/gvt: Remove one duplicated MMIO

2017-08-23 Thread Zhenyu Wang

On 2017.08.23 13:23:10 +0800, Jian Jun Chen wrote:
> Remove one duplicated MMIO GEN6_PCODE_MAILBOX. Duplicated MMIO will
> cause host GVT-g initialization failure.
> 
> Fixes: 9c3a16c887f0 ("drm/i915/hsw+: Add support for multiple power well 
> regs")
> Signed-off-by: Jian Jun Chen 
> ---

oh, as this is a regression that cause gvt init fail, cc Imre, looks
that extra line was not in original patch but might be added during
push. As this is pushed for 4.14, I will send this fix later.

thanks

>  drivers/gpu/drm/i915/gvt/handlers.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3502a59166ff..2294466dd415 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2659,7 +2659,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>   MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
>   MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
>   skl_power_well_ctl_write);
> - MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);
>  
>   MMIO_D(0xa210, D_SKL_PLUS);
>   MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> -- 
> 2.13.0
> 
> ___
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> intel-gvt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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[Intel-gfx] [GIT PULL] gvt final fixes for 4.13

2017-08-23 Thread Zhenyu Wang


Hi, here's one final gvt fix for 4.13. One possible null ptr
reference issue fixed by Fred.

Thanks
--
The following changes since commit d6086598d34e1cf9091c7be201f5b2041dc6203e:

  drm/i915/gvt: Change the max length of mmio_reg_rw from 4 to 8 (2017-08-07 
15:50:39 +0800)

are available in the git repository at:

  https://github.com/01org/gvt-linux.git tags/gvt-fixes-2017-08-23

for you to fetch changes up to ffeaf9aaf97b4bdaf114d6df52f800d71918768c:

  drm/i915/gvt: Fix the kernel null pointer error (2017-08-23 14:08:57 +0800)


gvt-fixes-2017-08-23

- Fix possible null ptr reference in error path (Fred)


fred gao (1):
  drm/i915/gvt: Fix the kernel null pointer error

 drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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Re: [Intel-gfx] [PATCH] drm/i915/gvt: Remove one duplicated MMIO

2017-08-23 Thread Imre Deak

On Wed, Aug 23, 2017 at 03:12:01PM +0800, Zhenyu Wang wrote:
> On 2017.08.23 13:23:10 +0800, Jian Jun Chen wrote:
> > Remove one duplicated MMIO GEN6_PCODE_MAILBOX. Duplicated MMIO will
> > cause host GVT-g initialization failure.
> > 
> > Fixes: 9c3a16c887f0 ("drm/i915/hsw+: Add support for multiple power well 
> > regs")
> > Signed-off-by: Jian Jun Chen 
> > ---
> 
> oh, as this is a regression that cause gvt init fail, cc Imre, looks
> that extra line was not in original patch but might be added during
> push. As this is pushed for 4.14, I will send this fix later.
> 
> thanks
> 
> >  drivers/gpu/drm/i915/gvt/handlers.c | 1 -
> >  1 file changed, 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
> > b/drivers/gpu/drm/i915/gvt/handlers.c
> > index 3502a59166ff..2294466dd415 100644
> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > @@ -2659,7 +2659,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> > MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
> > MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
> > skl_power_well_ctl_write);
> > -   MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);

Oops, not sure how this happened. This line was part of the context but
was removed by the time the patch was actually pushed. Maybe git am -3
resolved it in this way?

Thanks for catching it:
Acked-by: Imre Deak 

> >  
> > MMIO_D(0xa210, D_SKL_PLUS);
> > MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> > -- 
> > 2.13.0
> > 
> > ___
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> > intel-gvt-...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
> 
> -- 
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> 
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[Intel-gfx] [RFCv3 0/3] Introduce private PAT management

2017-08-23 Thread Zhi Wang

This patchset introduces private PPAT managment which enables dynamically
configuring PPAT at runtime. The previous static PPAT configuration is
kept unchanged.

More background of this patchset can be found at:
https://lists.freedesktop.org/archives/intel-gfx/2017-August/135415.html

v3:
- Remove intel_ppat_reserved. (Chris)

v2:
- Rewrite the i915 parts after discussing with Chris. Now PPAT management
sits in i915.

Zhi Wang (3):
  drm/i915: Factor out setup_private_pat()
  drm/i915: Introduce private PAT management
  drm/i915: Introduce per-platform PPAT configurations

 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 275 +---
 drivers/gpu/drm/i915/i915_gem_gtt.h |  35 +
 3 files changed, 258 insertions(+), 54 deletions(-)

-- 
2.7.4

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[Intel-gfx] [RFCv3 1/3] drm/i915: Factor out setup_private_pat()

2017-08-23 Thread Zhi Wang

Factor out setup_private_pat() for introducing the following patches.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0f73998..09d1d48 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2841,6 +2841,16 @@ static void gen6_gmch_remove(struct i915_address_space 
*vm)
cleanup_scratch_page(vm);
 }
 
+static void setup_private_pat(struct drm_i915_private *dev_priv)
+{
+   if (INTEL_GEN(dev_priv) >= 10)
+   cnl_setup_private_ppat(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+   chv_setup_private_ppat(dev_priv);
+   else
+   bdw_setup_private_ppat(dev_priv);
+}
+
 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -2873,14 +2883,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
}
 
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-
-   if (INTEL_GEN(dev_priv) >= 10)
-   cnl_setup_private_ppat(dev_priv);
-   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-   chv_setup_private_ppat(dev_priv);
-   else
-   bdw_setup_private_ppat(dev_priv);
-
ggtt->base.cleanup = gen6_gmch_remove;
ggtt->base.bind_vma = ggtt_bind_vma;
ggtt->base.unbind_vma = ggtt_unbind_vma;
@@ -2901,6 +2903,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
ggtt->invalidate = gen6_ggtt_invalidate;
 
+   setup_private_pat(dev_priv);
+
return ggtt_probe_common(ggtt, size);
 }
 
-- 
2.7.4

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[Intel-gfx] [RFCv3 3/3] drm/i915: Introduce per-platform PPAT configurations

2017-08-23 Thread Zhi Wang

The previous static PPAT configuration for each platform is kept unchanged.
Also the PPAT feature of each platform is described in intel PPAT instance
during the initialization and related callbacks which supports the PPAT
management framework will be hooked.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 145 
 1 file changed, 96 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c88ed76..82e8395 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2844,41 +2844,92 @@ void intel_ppat_put(struct intel_ppat_entry *entry)
kref_put(&entry->ref_count, put_ppat);
 }
 
-static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+static void cnl_private_pat_update(struct drm_i915_private *dev_priv)
 {
+   struct intel_ppat *ppat = &dev_priv->ppat;
+   int i;
+
+   for (i = 0; i < ppat->max_entries; i++)
+   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
+}
+
+static void bdw_private_pat_update(struct drm_i915_private *dev_priv)
+{
+   struct intel_ppat *ppat = &dev_priv->ppat;
+   u64 pat = 0;
+   int i;
+
+   for (i = 0; i < ppat->max_entries; i++)
+   pat |= GEN8_PPAT(i, ppat->entries[i].value);
+
+   I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+   I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+}
+
+#define gen8_pat_ca(v) ((v) & 0x3)
+#define gen8_pat_tc(v) (((v) >> 2) & 0x3)
+#define gen8_pat_age(v) (((v) >> 4) & 0x3)
+
+static unsigned int bdw_private_pat_match(u8 src, u8 dst)
+{
+   unsigned int score = 0;
+
+   /* Cache attribute has to be matched. */
+   if (gen8_pat_ca(src) != gen8_pat_ca(dst))
+   return 0;
+
+   if (gen8_pat_age(src) == gen8_pat_age(dst))
+   score += 1;
+
+   if (gen8_pat_tc(src) == gen8_pat_tc(dst))
+   score += 2;
+
+   if (score == 3)
+   return INTEL_PPAT_PERFECT_MATCH;
+
+   return score;
+}
+
+#define chv_get_snoop(v) (((v) >> 6) & 0x1)
+
+static unsigned int chv_private_pat_match(u8 src, u8 dst)
+{
+   if (chv_get_snoop(src) == chv_get_snoop(dst))
+   return ~0;
+
+   return 0;
+}
+
+static void cnl_setup_private_ppat(struct intel_ppat *ppat)
+{
+   ppat->max_entries = 8;
+   ppat->update = cnl_private_pat_update;
+   ppat->match = bdw_private_pat_match;
+   ppat->dummy_value = GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
+
/* XXX: spec is unclear if this is still needed for CNL+ */
if (!USES_PPGTT(dev_priv)) {
-   I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
+   alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
return;
}
 
-   I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
-   I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-   I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-   I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
-   I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-   I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-   I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-   I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+   alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
+   alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+   alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
+   alloc_ppat_entry(ppat, 4, GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
-static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
+static void bdw_setup_private_ppat(struct intel_ppat *ppat)
 {
-   u64 pat;
+   ppat->max_entries = 8;
+   ppat->update = bdw_private_pat_update;
+   ppat->match = bdw_private_pat_match;
+   ppat->dummy_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
 
-   pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal 
objects, no eLLC */
- GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something 
pointing to ptes? */
- GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout 
with eLLC */
- GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached 
objects, mostly for scanout */
- GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) 
|
- GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) 
|
- GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) 
|
- GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
-
-   if (!USES_PPGTT(dev_priv

[Intel-gfx] [RFCv3 2/3] drm/i915: Introduce private PAT management

2017-08-23 Thread Zhi Wang

The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_set.

intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate or
return a partially matched PPAT entry if there is any available PPAT
indexes or not.

intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.

Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 116 
 drivers/gpu/drm/i915/i915_gem_gtt.h |  35 +++
 3 files changed, 153 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60267e3..97b46f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2307,6 +2307,8 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
 
+   struct intel_ppat ppat;
+
/* Kernel Modesetting */
 
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 09d1d48..c88ed76 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2742,6 +2742,108 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
u64 size)
return 0;
 }
 
+static struct intel_ppat_entry *alloc_ppat_entry(struct intel_ppat *ppat,
+unsigned int index,
+u8 value)
+{
+   struct intel_ppat_entry *entry;
+
+   entry = &ppat->entries[index];
+   entry->value = value;
+   kref_init(&entry->ref_count);
+   set_bit(index, ppat->used);
+
+   return entry;
+}
+
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @dev_priv: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, the partially
+ * matched entry will be used.
+ */
+struct intel_ppat_entry *intel_ppat_get(struct drm_i915_private *dev_priv,
+   u8 value)
+{
+   struct intel_ppat *ppat = &dev_priv->ppat;
+   struct intel_ppat_entry *entry;
+   int i, used;
+   unsigned int score, best_score;
+
+   score = best_score = 0;
+   used = 0;
+
+   /* First, find a suitable value from available entries */
+   for_each_set_bit(i, ppat->used, ppat->max_entries) {
+   score = ppat->match(ppat->entries[i].value, value);
+   /* Perfect match */
+   if (score == INTEL_PPAT_PERFECT_MATCH) {
+   entry = &ppat->entries[i];
+   kref_get(&entry->ref_count);
+   return entry;
+   }
+
+   if (score > best_score) {
+   entry = &ppat->entries[i];
+   best_score = score;
+   }
+   used++;
+   }
+
+   /* No matched entry and we can't allocate a new entry. */
+   if (!best_score && used == ppat->max_entries) {
+   DRM_ERROR("Fail to get PPAT entry\n");
+   return ERR_PTR(-ENOSPC);
+   }
+
+   /*
+* Found a matched entry which is not perfect,
+* and we can't allocate a new entry.
+*/
+   if (best_score && used == ppat->max_entries) {
+   kref_get(&entry->ref_count);
+   return entry;
+   }
+
+   /* Allocate a new entry */
+   i = find_first_zero_bit(ppat->used, ppat->max_entries);
+   entry = alloc_ppat_entry(ppat, i, value);
+   ppat->update(dev_priv);
+   return entry;
+}
+
+static void put_ppat(struct kref *kref)
+{
+   struct intel_ppat_entry *entry =
+   container_of(kref, struct intel_ppat_entry, ref_count);
+   struct intel_ppat *ppat = entry->ppat;
+   struct drm_i915_private *dev_priv = ppat->dev_priv;
+   int index = entry - ppat->entries;
+
+   entry->value = ppat->dummy_value;
+   clear_bit(index, ppat->used);
+   ppat->update(dev_priv);
+}
+
+/**
+ * intel_ppat_put -

Re: [Intel-gfx] [maintainer-tools PATCH] dim.rst: Document aliases extension on dimrc.

2017-08-23 Thread Jani Nikula

On Tue, 22 Aug 2017, Rodrigo Vivi  wrote:
> On my own workflow I was missing a way to download mboxes
> directly from patchwork with the patchwork id. So my first
> reflex was to modify dim to fulfil my needs. However that
> was increasing dim in complexity and dependencies and leaving
> that messy.
>
> That was when Jani suggested me the dimrc extension with the
> example that is now part of this spec.
>
> That was clean and simple enough to understand, so Daniel
> suggested me to add it to the spec.
>
> For record let's put my final local solution that lays now on
> my own ~/.dimrc
>
> dim_pwaq()
> {
>   if [ -n "$1" ]; then
>   curl https://patchwork.freedesktop.org/patch/$1/mbox/ | 
> dim_apply_queued
>   else
>   echo "Give me a patchwork id"
>   fi
> }
>
> v2: Use code-block directive. Get's cleaner and make check happy.
> v3: Use a generic block instead of sphinx directive otherwise
> rst2man can get confused on pur man generation.
>
> Cc: Jani Nikula 
> Cc: Daniel Vetter 
> Signed-off-by: Rodrigo Vivi 

Pushed, thanks.

BR,
Jani.

> ---
>  dim.rst | 16 
>  1 file changed, 16 insertions(+)
>
> diff --git a/dim.rst b/dim.rst
> index 802c776e03f9..00e4511a1fce 100644
> --- a/dim.rst
> +++ b/dim.rst
> @@ -441,6 +441,22 @@ usage
>  Short form usage help listing all subcommands. Run by default or if an 
> unknown
>  subcommand was passed on the cmdline.
>  
> +ALIASES
> +===
> +
> +Extending **dim** functionalities
> +-
> +
> +It is possible to create your own dim helper and aliases by adding them to 
> \$HOME/.dimrc::
> +
> + dim_my_fancy_list_aliases()
> + {
> + echo "Hello world!":
> + dim_list_aliases:
> + }
> +
> + dim_alias_list_aliases=my-fancy-list-aliases
> +
>  ENVIRONMENT
>  ===

-- 
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Re: [Intel-gfx] [maintainer-tools PATCH] dim: Properly handle series on apply_branch

2017-08-23 Thread Jani Nikula

On Tue, 22 Aug 2017, Rodrigo Vivi  wrote:
> So far we could use *dim* to apply a whole series
> in a mbox, but only the very last patch was receiving
> all the checks and patchwork link.
>
> So this patch remove this limitation by using git mailsplit
> to split the mbox and than use git am and checks individually
> on each patch.
>
> v2: a. Don't loop with `ls $dir` nor use ls. Shellcheck recommends
>globs instead. Reference: SC2045
> c. Split the apply patch in a separated function as suggested
>by Jani.
> b. Use -b on git mailsplit so it will automatically it is not
>an mbox file and parse it assuming a single mail message.
>This fixes the issue Jani notice with input directly from
>MUA: "corrupt mailbox".
> v3: Pass $@ to apply_patch function and properly handle the shift.
> Handle returns. If any patch in the series had some kind of goof
> return 1.
>
> Cc: Jani Nikula 
> Cc: Daniel Vetter 
> Signed-off-by: Rodrigo Vivi 
> ---
>  dim | 52 ++--
>  1 file changed, 34 insertions(+), 18 deletions(-)
>
> diff --git a/dim b/dim
> index 11aa675cc3bc..80ad23a1cd31 100755
> --- a/dim
> +++ b/dim
> @@ -756,33 +756,21 @@ function dim_push
>   dim_push_branch $(git_current_branch) "$@"
>  }
>  
> -# ensure we're on branch $1, and apply patches. the rest of the arguments are
> -# passed to git am.
> -dim_alias_ab=apply-branch
> -dim_alias_sob=apply-branch
> -function dim_apply_branch
> +function apply_patch #patch_file
>  {
> - local branch file message_id committer_email patch_from sob rv
> + local patch message_id committer_email patch_from sob rv
>  
> - branch=${1:?$usage}
> + patch="$1"
>   shift
> - file=$(mktemp)
> -
> - assert_branch $branch
> - assert_repo_clean
> -
> - cat > $file
> -
> - message_id=$(message_get_id $file)
> -
> + message_id=$(message_get_id $patch)
>   committer_email=$(git_committer_email)
>  
> - patch_from=$(grep "From:" "$file" | head -1)
> + patch_from=$(grep "From:" "$patch" | head -1)
>   if [[ "$patch_from" != *"$committer_email"* ]] ; then
>   sob=-s
>   fi
>  
> - git am --scissors -3 $sob "$@" $file
> + git am --scissors -3 $sob "$@" $patch
>  
>   if [ -n "$message_id" ]; then
>   dim_commit_add_tag "Link: 
> https://patchwork.freedesktop.org/patch/msgid/$message_id";
> @@ -799,6 +787,34 @@ function dim_apply_branch
>   fi
>  
>   eval $DRY $DIM_POST_APPLY_ACTION
> + return $rv
> +}
> +
> +# ensure we're on branch $1, and apply patches. the rest of the arguments are
> +# passed to git am.
> +dim_alias_ab=apply-branch
> +dim_alias_sob=apply-branch
> +function dim_apply_branch
> +{
> + local branch file rv
> +
> + branch=${1:?$usage}
> + shift
> + file=$(mktemp)
> + dir=$(mktemp -d)
> +
> + assert_branch $branch
> + assert_repo_clean
> +
> + cat > $file
> + git mailsplit -b -o$dir $file > /dev/null
> +
> + for patch in $dir/*; do
> + apply_patch $patch $@

Should be quoted "$@".

> + if [[ $? -eq "1" ]] ; then

This if will never be executed if apply_patch exit code is != 0 because
of set -e. I gave you the example how to call apply_patch! ;)

> + rv=1
> + fi
> + done

Hmm, could do rm -rf $(file) $(dir) here.

>  
>   return $rv
>  }

-- 
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[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce private PAT management (rev2)

2017-08-23 Thread Patchwork

== Series Details ==

Series: Introduce private PAT management (rev2)
URL   : https://patchwork.freedesktop.org/series/29166/
State : success

== Summary ==

Series 29166v2 Introduce private PAT management
https://patchwork.freedesktop.org/api/1.0/series/29166/revisions/2/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:437s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:545s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:518s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:524s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7260u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:498s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:607s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:601s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:532s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:470s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:485s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:484s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:503s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:407s

489147dfdcc735baf773a6ec3698cf85a01d7008 drm-tip: 2017y-08m-22d-18h-44m-32s UTC 
integration manifest
5eac05bc6d87 drm/i915: Introduce per-platform PPAT configurations
2f2e968797b5 drm/i915: Introduce private PAT management
1acf373125f5 drm/i915: Factor out setup_private_pat()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5472/
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Re: [Intel-gfx] [maintainer-tools PATCH] dim: Properly handle series on apply_branch

2017-08-23 Thread Jani Nikula

On Wed, 23 Aug 2017, Jani Nikula  wrote:
> I gave you the example how to call apply_patch! ;)

Huh, I *thought* I did, maybe I didn't. Sorry.

if ! apply_patch $patch "$@"; then
rv=1
fi

Similar to the checkpatch_commit call in dim_apply_branch.

BR
Jani.


-- 
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[Intel-gfx] [PATCH 01/20] drm/i915: "Race-to-idle" on switching to the kernel context

2017-08-23 Thread Chris Wilson

During suspend we want to flush out all active contexts and their
rendering. To do so we queue a request from the kernel's context, once
we know that request is done, we know the GPU is completely idle. To
speed up that switch bump the GPU clocks.

Switching to the kernel context prior to idling is also used to enforce
a barrier before changing OA properties, and when evicting active
rendering from the global GTT. All cases where we do want to
race-to-idle.

Signed-off-by: Chris Wilson 
Cc: David Weinehall 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 58a2a44f88bd..ca1423ad2708 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -895,6 +895,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
+   bool active = false;
int ret;
 
if (engine_has_kernel_context(engine))
@@ -913,13 +914,17 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
prev = i915_gem_active_raw(&tl->last_request,
   &dev_priv->drm.struct_mutex);
if (prev)
-   i915_sw_fence_await_sw_fence_gfp(&req->submit,
-&prev->submit,
-GFP_KERNEL);
+   active |= 
i915_sw_fence_await_sw_fence_gfp(&req->submit,
+  
&prev->submit,
+  
GFP_KERNEL) > 0;
}
 
ret = i915_switch_context(req);
+
+   if (active)
+   gen6_rps_boost(req, NULL);
i915_add_request(req);
+
if (ret)
return ret;
}
-- 
2.14.1

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[Intel-gfx] [PATCH 02/20] drm/i915: Assert the context is not closed on object-close

2017-08-23 Thread Chris Wilson

During the context-close, we should be decoupling all the vma from the
object so that upon object-closing we shouldn't see any vma from the
already closed contexts. So include a check upon closing the object that
the context is still open.

v2: Eek, the fpriv check is required for shared objects. Double eek, BAT
passed?

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b9e8e0d6e97b..3ed9fb0921e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3253,11 +3253,11 @@ void i915_gem_close_object(struct drm_gem_object *gem, 
struct drm_file *file)
struct i915_gem_context *ctx = lut->ctx;
struct i915_vma *vma;
 
+   GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));
if (ctx->file_priv != fpriv)
continue;
 
vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
-
if (!i915_vma_is_ggtt(vma))
i915_vma_close(vma);
 
-- 
2.14.1

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[Intel-gfx] [PATCH 05/20] drm/i915: Prevent overflow of execbuf.buffer_count and num_cliprects

2017-08-23 Thread Chris Wilson

We check whether the multiplies will overflow prior to calling
kmalloc_array so that we can respond with -EINVAL for the invalid user
arguments rather than treating it as an -ENOMEM that would otherwise
occur. However, as Dan Carpenter pointed out, we did an addition on the
unsigned int prior to passing to kmalloc_array where it would be
promoted to size_t for the calculation, thereby allowing it to overflow
and underallocate.

v2: buffer_count is currently limited to INT_MAX because we treat it as
signaled variable for LUT_HANDLE in eb_lookup_vma

Reported-by: Dan Carpenter 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 33 --
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1c4fac032329..166ba296c6a4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2058,7 +2058,7 @@ static struct drm_syncobj **
 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
struct drm_file *file)
 {
-   const unsigned int nfences = args->num_cliprects;
+   const size_t nfences = args->num_cliprects;
struct drm_i915_gem_exec_fence __user *user;
struct drm_syncobj **fences;
unsigned int n;
@@ -2067,14 +2067,14 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
if (!(args->flags & I915_EXEC_FENCE_ARRAY))
return NULL;
 
-   if (nfences > SIZE_MAX / sizeof(*fences))
+   if (nfences > SIZE_MAX / max(sizeof(*fences), 2*sizeof(u32)))
return ERR_PTR(-EINVAL);
 
user = u64_to_user_ptr(args->cliprects_ptr);
if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32)))
return ERR_PTR(-EFAULT);
 
-   fences = kvmalloc_array(args->num_cliprects, sizeof(*fences),
+   fences = kvmalloc_array(nfences, sizeof(*fences),
__GFP_NOWARN | GFP_TEMPORARY);
if (!fences)
return ERR_PTR(-ENOMEM);
@@ -2439,11 +2439,13 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_i915_gem_execbuffer2 exec2;
struct drm_i915_gem_exec_object *exec_list = NULL;
struct drm_i915_gem_exec_object2 *exec2_list = NULL;
+   const size_t count = args->buffer_count;
unsigned int i;
int err;
 
-   if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
-   DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
+   /* Lookups via HANDLE_LUT are limited to INT_MAX (see eb_create()) */
+   if (count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1) {
+   DRM_DEBUG("execbuf2 with %zd buffers\n", count);
return -EINVAL;
}
 
@@ -2462,9 +2464,9 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
return -EINVAL;
 
/* Copy in the exec list from userland */
-   exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list),
+   exec_list = kvmalloc_array(count, sizeof(*exec_list),
   __GFP_NOWARN | GFP_TEMPORARY);
-   exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
+   exec2_list = kvmalloc_array(count + 1, sz,
__GFP_NOWARN | GFP_TEMPORARY);
if (exec_list == NULL || exec2_list == NULL) {
DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
@@ -2475,7 +2477,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
}
err = copy_from_user(exec_list,
 u64_to_user_ptr(args->buffers_ptr),
-sizeof(*exec_list) * args->buffer_count);
+sizeof(*exec_list) * count);
if (err) {
DRM_DEBUG("copy %d exec entries failed %d\n",
  args->buffer_count, err);
@@ -2531,10 +2533,11 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
struct drm_i915_gem_execbuffer2 *args = data;
struct drm_i915_gem_exec_object2 *exec2_list;
struct drm_syncobj **fences = NULL;
+   const size_t count = args->buffer_count;
int err;
 
-   if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
-   DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
+   if (count < 1 || count > SIZE_MAX / sz - 1) {
+   DRM_DEBUG("execbuf2 with %zd buffers\n", count);
return -EINVAL;
}
 
@@ -2542,17 +2545,17 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
return -EINVAL;
 
/* Allocate an extra slot for use by the command parser */
-   exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
+   exec2_list = kvmalloc_array(count + 1, sz,
__GFP_NOWARN | GFP_TEMPORARY);
if (exec2_lis

[Intel-gfx] [PATCH 04/20] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT

2017-08-23 Thread Chris Wilson

By using drm_gem_flink/drm_gem_open on an object using the same fd, it
is possible for a client to create multiple handles pointing to the same
object (tied to the same contexts and VMA), as exemplified by
igt::gem_handle_to_libdrm_bo(). Since this duplication has been possible
since forever, we cannot assume that the handle:(fpriv, object) is
unique and so must handle the multiple users of a single VMA.

Testcase: igt/gem_close
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c| 8 +++-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
 drivers/gpu/drm/i915/i915_vma.h| 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5dc396c20c06..ac02785fdaff 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3258,7 +3258,13 @@ void i915_gem_close_object(struct drm_gem_object *gem, 
struct drm_file *file)
continue;
 
vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
-   if (!i915_vma_is_ggtt(vma))
+   GEM_BUG_ON(vma->obj != obj);
+
+   /* We allow the process to have multiple handles to the same
+* vma, in the same fd namespace, by virtue of flink/open.
+*/
+   GEM_BUG_ON(!vma->open_count);
+   if (!--vma->open_count && !i915_vma_is_ggtt(vma))
i915_vma_close(vma);
 
list_del(&lut->obj_link);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 3d74f3a27c13..1c4fac032329 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
goto err_obj;
}
 
+   vma->open_count++;
list_add(&lut->obj_link, &obj->lut_list);
list_add(&lut->ctx_link, &eb->ctx->handles_list);
lut->ctx = eb->ctx;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 1fd61e88cfd0..893467a28801 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -59,6 +59,7 @@ struct i915_vma {
u32 fence_size;
u32 fence_alignment;
 
+   unsigned int open_count;
unsigned int flags;
/**
 * How many users have pinned this object in GTT space. The following
-- 
2.14.1

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[Intel-gfx] The bunch of mm patches in the queue, mostly for shard testing

2017-08-23 Thread Chris Wilson

Lots of mostly reviewed shrinker patches, one contentious core mm patch,
that makes vmpressure behave much better.
-Chris

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[Intel-gfx] [PATCH 07/20] drm/i915: Rename obj->pin_display to obj->pin_global

2017-08-23 Thread Chris Wilson

In the next patch, we want to extend use of the global pin counter for
semi-permanent pinning of context/ring objects. Given that we plan to
extend the usage to encompass a disparate set of objects, we want a name
that reflects both and should entail less confusion.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 ++--
 drivers/gpu/drm/i915/i915_gem.c | 20 ++--
 drivers/gpu/drm/i915/i915_gem_object.h  |  3 ++-
 drivers/gpu/drm/i915/i915_gem_userptr.c |  4 ++--
 4 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 48572b157222..ee3a11ca5340 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -81,7 +81,7 @@ static char get_active_flag(struct drm_i915_gem_object *obj)
 
 static char get_pin_flag(struct drm_i915_gem_object *obj)
 {
-   return obj->pin_display ? 'p' : ' ';
+   return obj->pin_global ? 'p' : ' ';
 }
 
 static char get_tiling_flag(struct drm_i915_gem_object *obj)
@@ -148,8 +148,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object 
*obj)
pin_count++;
}
seq_printf(m, " (pinned x %d)", pin_count);
-   if (obj->pin_display)
-   seq_printf(m, " (display)");
+   if (obj->pin_global)
+   seq_printf(m, " (global)");
list_for_each_entry(vma, &obj->vma_list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -439,7 +439,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
size += obj->base.size;
++count;
 
-   if (obj->pin_display) {
+   if (obj->pin_global) {
dpy_size += obj->base.size;
++dpy_count;
}
@@ -460,7 +460,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   purgeable_count, purgeable_size);
seq_printf(m, "%u mapped objects, %llu bytes\n",
   mapped_count, mapped_size);
-   seq_printf(m, "%u display objects (pinned), %llu bytes\n",
+   seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
   dpy_count, dpy_size);
 
seq_printf(m, "%llu [%llu] gtt total\n",
@@ -524,7 +524,7 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data)
 
total_obj_size = total_gtt_size = count = 0;
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
-   if (show_pin_display_only && !obj->pin_display)
+   if (show_pin_display_only && !obj->pin_global)
continue;
 
seq_puts(m, "   ");
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d6f5f0598b6b..681b218ecc20 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -55,7 +55,7 @@ static bool cpu_write_needs_clflush(struct 
drm_i915_gem_object *obj)
if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
return true;
 
-   return obj->pin_display;
+   return obj->pin_global; /* currently in use by HW, keep flushed */
 }
 
 static int
@@ -3438,7 +3438,7 @@ static void __i915_gem_object_flush_for_display(struct 
drm_i915_gem_object *obj)
 
 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
 {
-   if (!READ_ONCE(obj->pin_display))
+   if (!READ_ONCE(obj->pin_global))
return;
 
mutex_lock(&obj->base.dev->struct_mutex);
@@ -3805,10 +3805,10 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
 
lockdep_assert_held(&obj->base.dev->struct_mutex);
 
-   /* Mark the pin_display early so that we account for the
+   /* Mark the global pin early so that we account for the
 * display coherency whilst setting up the cache domains.
 */
-   obj->pin_display++;
+   obj->pin_global++;
 
/* The display engine is not coherent with the LLC cache on gen6.  As
 * a result, we make sure that the pinning that is about to occur is
@@ -3824,7 +3824,7 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
  I915_CACHE_WT : I915_CACHE_NONE);
if (ret) {
vma = ERR_PTR(ret);
-   goto err_unpin_display;
+   goto err_unpin_global;
}
 
/* As the user may map the buffer once pinned in the display plane
@@ -3855,7 +3855,7 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
}
if (IS_ERR(vma))
-   goto err_unpin_display;
+   goto err_unpin_global;
 
vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
 
@@ -38

[Intel-gfx] [PATCH 10/20] drm/i915: Move dev_priv->mm.[un]bound_list to its own lock

2017-08-23 Thread Chris Wilson

Remove the struct_mutex requirement around dev_priv->mm.bound_list and
dev_priv->mm.unbound_list by giving it its own spinlock. This reduces
one more requirement for struct_mutex and in the process gives us
slightly more accurate unbound_list tracking, which should improve the
shrinker - but the drawback is that we drop the retirement before
counting so i915_gem_object_is_active() may be stale and lead us to
underestimate the number of objects that may be shrunk (see commit
bed50aea61df ("drm/i915/shrinker: Flush active on objects before
counting")).

v2: Crosslink the spinlock to the lists it protects, and btw this
changes s/obj->global_link/obj->mm.link/

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 39 +++---
 drivers/gpu/drm/i915/i915_drv.h   |  3 ++
 drivers/gpu/drm/i915/i915_gem.c   | 41 ---
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  3 +-
 drivers/gpu/drm/i915/i915_gem_object.h|  7 ++-
 drivers/gpu/drm/i915/i915_gem_shrinker.c  | 64 +--
 drivers/gpu/drm/i915/i915_gem_stolen.c|  5 +-
 drivers/gpu/drm/i915/i915_vma.c   | 16 --
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c   |  8 ++-
 10 files changed, 122 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5cc7de5dadf5..52173e92864f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -238,7 +238,9 @@ static int i915_gem_stolen_list_info(struct seq_file *m, 
void *data)
goto out;
 
total_obj_size = total_gtt_size = count = 0;
-   list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
+
+   spin_lock(&dev_priv->mm.obj_lock);
+   list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
if (count == total)
break;
 
@@ -250,7 +252,7 @@ static int i915_gem_stolen_list_info(struct seq_file *m, 
void *data)
total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 
}
-   list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
+   list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
if (count == total)
break;
 
@@ -260,6 +262,7 @@ static int i915_gem_stolen_list_info(struct seq_file *m, 
void *data)
objects[count++] = obj;
total_obj_size += obj->base.size;
}
+   spin_unlock(&dev_priv->mm.obj_lock);
 
sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 
@@ -418,7 +421,9 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
size = count = 0;
mapped_size = mapped_count = 0;
purgeable_size = purgeable_count = 0;
-   list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
+
+   spin_lock(&dev_priv->mm.obj_lock);
+   list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
size += obj->base.size;
++count;
 
@@ -435,7 +440,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 
size = count = dpy_size = dpy_count = 0;
-   list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
+   list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
size += obj->base.size;
++count;
 
@@ -454,6 +459,8 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
mapped_size += obj->base.size;
}
}
+   spin_unlock(&dev_priv->mm.obj_lock);
+
seq_printf(m, "%u bound objects, %llu bytes\n",
   count, size);
seq_printf(m, "%u purgeable objects, %llu bytes\n",
@@ -513,28 +520,46 @@ static int i915_gem_gtt_info(struct seq_file *m, void 
*data)
struct drm_info_node *node = m->private;
struct drm_i915_private *dev_priv = node_to_i915(node);
struct drm_device *dev = &dev_priv->drm;
+   struct drm_i915_gem_object **objects;
struct drm_i915_gem_object *obj;
u64 total_obj_size, total_gtt_size;
+   unsigned long nobject, n;
int count, ret;
 
+   nobject = READ_ONCE(dev_priv->mm.object_count);
+   objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
+   if (!objects)
+   return -ENOMEM;
+
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
 
-   total_obj_size = total_gtt_size = count = 0;
-   list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
+   count = 0;
+   spin_lock(&dev_priv->mm.obj_lock);
+   list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
+   objects[count++]

[Intel-gfx] [PATCH 11/20] drm/i915: Set our shrinker->batch to 4096 (~16MiB)

2017-08-23 Thread Chris Wilson

Prefer to defer activating our GEM shrinker until we have a few
megabytes to free; or we have accumulated sufficient mempressure by
deferring the reclaim to force a shrink. The intent is that because our
objects may typically be large, we are too effective at shrinking and
are not rewarded for freeing more pages than the batch. It will also
defer the initial shrinking to hopefully put it at a lower priority than
say the buffer cache (although it will balance out over a number of
reclaims, with GEM being more bursty).

v2: Give it a feedback system to try and tune the batch size towards
an effective size for the available objects.
v3: Start keeping track of shrinker stats in debugfs
v4: Protect against finding no shrinkable objects (div-by-zero)

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 11 +++
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 34 +---
 2 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 52173e92864f..6bad53f89738 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3414,6 +3414,16 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_shrinker_info(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *i915 = node_to_i915(m->private);
+
+   seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
+   seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
+
+   return 0;
+}
+
 static int i915_semaphore_status(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4842,6 +4852,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
+   {"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 2afca480bbea..38fc54221850 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -288,20 +288,39 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private 
*dev_priv)
 static unsigned long
 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
 {
-   struct drm_i915_private *dev_priv =
+   struct drm_i915_private *i915 =
container_of(shrinker, struct drm_i915_private, mm.shrinker);
struct drm_i915_gem_object *obj;
+   unsigned long num_objects = 0;
unsigned long count = 0;
 
-   spin_lock(&dev_priv->mm.obj_lock);
-   list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link)
-   if (can_release_pages(obj))
+   spin_lock(&i915->mm.obj_lock);
+   list_for_each_entry(obj, &i915->mm.unbound_list, mm.link)
+   if (can_release_pages(obj)) {
count += obj->base.size >> PAGE_SHIFT;
+   num_objects++;
+   }
 
-   list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link)
-   if (!i915_gem_object_is_active(obj) && can_release_pages(obj))
+   list_for_each_entry(obj, &i915->mm.bound_list, mm.link)
+   if (!i915_gem_object_is_active(obj) && can_release_pages(obj)) {
count += obj->base.size >> PAGE_SHIFT;
-   spin_unlock(&dev_priv->mm.obj_lock);
+   num_objects++;
+   }
+   spin_unlock(&i915->mm.obj_lock);
+
+   /* Update our prefered vmscan batch size for the next pass.
+* Our rough guess for an effective batch size is roughly 2
+* available GEM objects worth of pages. That is we don't want
+* the shrinker to fire, until it is worth the cost of freeing an
+* entire GEM object.
+*/
+   if (num_objects) {
+   unsigned long avg = 2 * count / num_objects;
+
+   i915->mm.shrinker.batch =
+   max((i915->mm.shrinker.batch + avg) >> 1,
+   128ul /* default SHRINK_BATCH */);
+   }
 
return count;
 }
@@ -461,6 +480,7 @@ void i915_gem_shrinker_init(struct drm_i915_private 
*dev_priv)
dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
+   dev_priv->mm.shrinker.batch = 4096;
WARN_ON(register_shrinker(&dev_priv->mm.shrinker));
 
dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
-- 
2.14.1

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[Intel-gfx] [PATCH 14/20] drm/i915: Discard VMA lut handles upon purging the object

2017-08-23 Thread Chris Wilson

If we purge the object from the shrinker, it is no longer accessible and
so we can reclaim it from the per-context lookup caches. For example,
if the client is leaking objects (but leaving as I915_MADV_DONTNEED)
then we still end up with significant mempressure from the unreclaimed
radixtrees and slabs.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index fb5c10d25bf3..2a272045cf4d 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -116,6 +116,26 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object 
*obj)
return !i915_gem_object_has_pages(obj);
 }
 
+static void close_object(struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   struct i915_lut_handle *lut, *ln;
+
+   list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) {
+   struct i915_vma *vma;
+
+   vma = radix_tree_delete(&lut->ctx->handles_vma, lut->handle);
+   if (!--vma->open_count && !i915_vma_is_ggtt(vma))
+   i915_vma_close(vma);
+
+   list_del(&lut->ctx_link);
+
+   kmem_cache_free(i915->luts, lut);
+   i915_gem_object_put(obj);
+   }
+   INIT_LIST_HEAD(&obj->lut_list);
+}
+
 static void __start_writeback(struct drm_i915_gem_object *obj,
  unsigned int flags)
 {
@@ -136,6 +156,7 @@ static void __start_writeback(struct drm_i915_gem_object 
*obj,
case I915_MADV_DONTNEED:
__i915_gem_object_truncate(obj);
case __I915_MADV_PURGED:
+   close_object(obj);
return;
}
 
-- 
2.14.1

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[Intel-gfx] [PATCH 08/20] drm/i915: Drop debugfs/i915_gem_pin_display

2017-08-23 Thread Chris Wilson

It has now lost its meaning (it shows more than just pin_display), I do
not believe that we are using in preference to the complete listing from
i915_gem_gtt, or the listing from i915_gem_framebuffer, or the listing
of active display objects in i915_display_info.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ee3a11ca5340..5cc7de5dadf5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -513,7 +513,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data)
struct drm_info_node *node = m->private;
struct drm_i915_private *dev_priv = node_to_i915(node);
struct drm_device *dev = &dev_priv->drm;
-   bool show_pin_display_only = !!node->info_ent->data;
struct drm_i915_gem_object *obj;
u64 total_obj_size, total_gtt_size;
int count, ret;
@@ -524,9 +523,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data)
 
total_obj_size = total_gtt_size = count = 0;
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
-   if (show_pin_display_only && !obj->pin_global)
-   continue;
-
seq_puts(m, "   ");
describe_obj(m, obj);
seq_putc(m, '\n');
@@ -4782,7 +4778,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_capabilities", i915_capabilities, 0},
{"i915_gem_objects", i915_gem_object_info, 0},
{"i915_gem_gtt", i915_gem_gtt_info, 0},
-   {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
{"i915_gem_stolen", i915_gem_stolen_list_info },
{"i915_gem_request", i915_gem_request_info, 0},
{"i915_gem_seqno", i915_gem_seqno_info, 0},
-- 
2.14.1

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[Intel-gfx] [PATCH 12/20] drm/i915: Trim struct_mutex hold duration for i915_gem_free_objects

2017-08-23 Thread Chris Wilson

We free objects in bulk after they wait for their RCU grace period.
Currently, we take struct_mutex and unbind all the objects. This can lead
to a long lock duration during which time those objects have their pages
unfreeable (i.e. the shrinker is prevented from reaping those pages). If
we only process a single object under the struct_mutex and then free the
pages, the number of objects locked away from the shrinker is minimal
and we allow regular clients better access to struct_mutex if they need
it.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 96be7969b3bd..88b52f23ee7a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4409,13 +4409,14 @@ static void __i915_gem_free_objects(struct 
drm_i915_private *i915,
 {
struct drm_i915_gem_object *obj, *on;
 
-   mutex_lock(&i915->drm.struct_mutex);
intel_runtime_pm_get(i915);
-   llist_for_each_entry(obj, freed, freed) {
+   llist_for_each_entry_safe(obj, on, freed, freed) {
struct i915_vma *vma, *vn;
 
trace_i915_gem_object_destroy(obj);
 
+   mutex_lock(&i915->drm.struct_mutex);
+
GEM_BUG_ON(i915_gem_object_is_active(obj));
list_for_each_entry_safe(vma, vn,
 &obj->vma_list, obj_link) {
@@ -4438,13 +4439,8 @@ static void __i915_gem_free_objects(struct 
drm_i915_private *i915,
spin_unlock(&i915->mm.obj_lock);
}
 
-   }
-   intel_runtime_pm_put(i915);
-   mutex_unlock(&i915->drm.struct_mutex);
+   mutex_unlock(&i915->drm.struct_mutex);
 
-   cond_resched();
-
-   llist_for_each_entry_safe(obj, on, freed, freed) {
GEM_BUG_ON(obj->bind_count);
GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
GEM_BUG_ON(!list_empty(&obj->lut_list));
@@ -4466,7 +4462,11 @@ static void __i915_gem_free_objects(struct 
drm_i915_private *i915,
 
kfree(obj->bit_17);
i915_gem_object_free(obj);
+
+   if (on)
+   cond_resched();
}
+   intel_runtime_pm_put(i915);
 }
 
 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
-- 
2.14.1

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[Intel-gfx] [PATCH 03/20] drm/i915: Assert that the handle->vma lut is empty on object close

2017-08-23 Thread Chris Wilson

Make sure that we are not leaking an entry in the ctx->handles_lut by
asserting that the object was removed prior to being freed. This should
be enforced by all such handles being removed by i915_gem_close_object.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3ed9fb0921e2..5dc396c20c06 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4416,6 +4416,7 @@ static void __i915_gem_free_objects(struct 
drm_i915_private *i915,
llist_for_each_entry_safe(obj, on, freed, freed) {
GEM_BUG_ON(obj->bind_count);
GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
+   GEM_BUG_ON(!list_empty(&obj->lut_list));
 
if (obj->ops->release)
obj->ops->release(obj);
-- 
2.14.1

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[Intel-gfx] [PATCH 15/20] drm/i915: Only free the oldest stale object before a fresh allocation

2017-08-23 Thread Chris Wilson

Inspired by Tvrtko's critique of the reaping of the stale contexts
before allocating a new one, also limit the freed object reaping to the
oldest stale object before allocating a fresh object. Unlike contexts,
objects may have radically different sizes of backing storage, but
similar to contexts, whilst we want to prevent starvation due to
excessive freed lists, we also want do not want to delay fresh
allocations for too long. Only freeing the oldest on the freed object
list before each allocation is a reasonable compromise.

v2: Only a single consumer of llist_del_first() is allowed (although
multiple llist_add are still allowed in parallel). Unlike
i915_gem_context, i915_gem_flush_free_objects() is itself not serialized
and so we need to add our own spinlock. Otherwise KASAN eventually spots
a use-after-free for the race on *first->next.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin  #v1
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 14 --
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f94cb9c8d7ed..cf49c01d60e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1467,6 +1467,7 @@ struct i915_gem_mm {
 */
struct llist_head free_list;
struct work_struct free_work;
+   spinlock_t free_lock;
 
/**
 * Small stash of WC pages
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b3e865a7e0fc..5284d30187ac 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4453,9 +4453,18 @@ static void i915_gem_flush_free_objects(struct 
drm_i915_private *i915)
 {
struct llist_node *freed;
 
-   freed = llist_del_all(&i915->mm.free_list);
-   if (unlikely(freed))
+   /* Free the oldest, most stale object to keep the free_list short */
+   freed = NULL;
+   if (!llist_empty(&i915->mm.free_list)) { /* quick test for hotpath */
+   /* Only one consumer of llist_del_first() allowed */
+   spin_lock(&i915->mm.free_lock);
+   freed = llist_del_first(&i915->mm.free_list);
+   spin_unlock(&i915->mm.free_lock);
+   }
+   if (unlikely(freed)) {
+   freed->next = NULL;
__i915_gem_free_objects(i915, freed);
+   }
 }
 
 static void __i915_gem_free_work(struct work_struct *work)
@@ -4940,6 +4949,7 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
 
spin_lock_init(&dev_priv->mm.obj_lock);
+   spin_lock_init(&dev_priv->mm.free_lock);
init_llist_head(&dev_priv->mm.free_list);
INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
INIT_LIST_HEAD(&dev_priv->mm.bound_list);
-- 
2.14.1

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[Intel-gfx] [PATCH 06/20] drm/i915: Refactor testing obj->mm.pages

2017-08-23 Thread Chris Wilson

Since we occasionally stuff an error pointer into obj->mm.pages for a
semi-permanent or even permanent failure, we have to be more careful and
not just test against NULL when deciding if the object has a complete
set of its concurrent pages.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h  | 10 --
 drivers/gpu/drm/i915/i915_gem.c  | 19 ++-
 drivers/gpu/drm/i915/i915_gem_clflush.c  |  1 +
 drivers/gpu/drm/i915/i915_gem_render_state.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 10 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_userptr.c  |  2 +-
 7 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef53026b..4670639e267f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3443,10 +3443,16 @@ i915_gem_object_pin_pages(struct drm_i915_gem_object 
*obj)
return __i915_gem_object_get_pages(obj);
 }
 
+static inline bool
+i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
+{
+   return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
+}
+
 static inline void
 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
 {
-   GEM_BUG_ON(!obj->mm.pages);
+   GEM_BUG_ON(!i915_gem_object_has_pages(obj));
 
atomic_inc(&obj->mm.pages_pin_count);
 }
@@ -3460,8 +3466,8 @@ i915_gem_object_has_pinned_pages(struct 
drm_i915_gem_object *obj)
 static inline void
 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
 {
+   GEM_BUG_ON(!i915_gem_object_has_pages(obj));
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
-   GEM_BUG_ON(!obj->mm.pages);
 
atomic_dec(&obj->mm.pages_pin_count);
 }
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ac02785fdaff..d6f5f0598b6b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2165,7 +2165,7 @@ void __i915_gem_object_invalidate(struct 
drm_i915_gem_object *obj)
struct address_space *mapping;
 
lockdep_assert_held(&obj->mm.lock);
-   GEM_BUG_ON(obj->mm.pages);
+   GEM_BUG_ON(i915_gem_object_has_pages(obj));
 
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
@@ -2228,7 +2228,7 @@ void __i915_gem_object_put_pages(struct 
drm_i915_gem_object *obj,
return;
 
GEM_BUG_ON(obj->bind_count);
-   if (!READ_ONCE(obj->mm.pages))
+   if (!i915_gem_object_has_pages(obj))
return;
 
/* May be called by shrinker from within get_pages() (on another bo) */
@@ -2507,7 +2507,7 @@ int __i915_gem_object_get_pages(struct 
drm_i915_gem_object *obj)
if (err)
return err;
 
-   if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+   if (unlikely(!i915_gem_object_has_pages(obj))) {
err = i915_gem_object_get_pages(obj);
if (err)
goto unlock;
@@ -2585,7 +2585,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object 
*obj,
 
pinned = true;
if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
-   if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+   if (unlikely(!i915_gem_object_has_pages(obj))) {
ret = i915_gem_object_get_pages(obj);
if (ret)
goto err_unlock;
@@ -2595,7 +2595,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object 
*obj,
atomic_inc(&obj->mm.pages_pin_count);
pinned = false;
}
-   GEM_BUG_ON(!obj->mm.pages);
+   GEM_BUG_ON(!i915_gem_object_has_pages(obj));
 
ptr = page_unpack_bits(obj->mm.mapping, &has_type);
if (ptr && has_type != type) {
@@ -2650,7 +2650,7 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object 
*obj,
 * allows it to avoid the cost of retrieving a page (either swapin
 * or clearing-before-use) before it is overwritten.
 */
-   if (READ_ONCE(obj->mm.pages))
+   if (i915_gem_object_has_pages(obj))
return -ENODEV;
 
/* Before the pages are instantiated the object is treated as being
@@ -4218,7 +4218,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
if (err)
goto out;
 
-   if (obj->mm.pages &&
+   if (i915_gem_object_has_pages(obj) &&
i915_gem_object_is_tiled(obj) &&
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
if (obj->mm.madv == I915_MADV_WILLNEED) {
@@ -4237,7 +4237,8 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
obj->mm.madv = args->madv;
 
/* if the object is no longer attached, discard its backing storage */
-   if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
+   if (obj->mm.madv == I915_MADV_D

[Intel-gfx] [PATCH 18/20] mm, drm/i915: Mark pinned shmemfs pages as unevictable

2017-08-23 Thread Chris Wilson

Similar in principle to the treatment of get_user_pages, pages that
i915.ko acquires from shmemfs are not immediately reclaimable and so
should be excluded from the mm accounting and vmscan until they have
been returned to the system via shrink_slab/i915_gem_shrink. By moving
the unreclaimable pages off the inactive anon lru, not only should
vmscan be improved by avoiding walking unreclaimable pages, but the
system should also have a better idea of how much memory it can reclaim
at that moment in time.

Note, however, the interaction with shrink_slab which will move some
mlocked pages back to the inactive anon lru.

Suggested-by: Dave Hansen 
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Cc: Dave Hansen 
Cc: "Kirill A . Shutemov" 
Cc: Andrew Morton 
Cc: Michal Hocko 
---
 drivers/gpu/drm/i915/i915_gem.c | 18 +-
 mm/mlock.c  |  2 ++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b5ea75187064..96dcfd6e02ca 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2161,6 +2161,9 @@ void __i915_gem_object_truncate(struct 
drm_i915_gem_object *obj)
obj->mm.pages = ERR_PTR(-EFAULT);
 }
 
+extern void mlock_vma_page(struct page *page);
+extern unsigned int munlock_vma_page(struct page *page);
+
 static void
 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
  struct sg_table *pages)
@@ -2182,6 +2185,10 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object 
*obj,
if (obj->mm.madv == I915_MADV_WILLNEED)
mark_page_accessed(page);
 
+   lock_page(page);
+   munlock_vma_page(page);
+   unlock_page(page);
+
put_page(page);
}
obj->mm.dirty = false;
@@ -2386,6 +2393,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
}
last_pfn = page_to_pfn(page);
 
+   lock_page(page);
+   mlock_vma_page(page);
+   unlock_page(page);
+
/* Check that the i965g/gm workaround works. */
WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x0010UL));
}
@@ -2424,8 +2435,13 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
 err_sg:
sg_mark_end(sg);
 err_pages:
-   for_each_sgt_page(page, sgt_iter, st)
+   for_each_sgt_page(page, sgt_iter, st) {
+   lock_page(page);
+   munlock_vma_page(page);
+   unlock_page(page);
+
put_page(page);
+   }
sg_free_table(st);
kfree(st);
 
diff --git a/mm/mlock.c b/mm/mlock.c
index b562b5523a65..531d9f8fd033 100644
--- a/mm/mlock.c
+++ b/mm/mlock.c
@@ -94,6 +94,7 @@ void mlock_vma_page(struct page *page)
putback_lru_page(page);
}
 }
+EXPORT_SYMBOL_GPL(mlock_vma_page);
 
 /*
  * Isolate a page from LRU with optional get_page() pin.
@@ -211,6 +212,7 @@ unsigned int munlock_vma_page(struct page *page)
 out:
return nr_pages - 1;
 }
+EXPORT_SYMBOL_GPL(munlock_vma_page);
 
 /*
  * convert get_user_pages() return value to posix mlock() error
-- 
2.14.1

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[Intel-gfx] [PATCH 20/20] drm/i915: Make GPU pages movable

2017-08-23 Thread Chris Wilson

On a long run of more than 2-3 days, physical memory tends to get
fragmented severely, which considerably slows down the system. In such a
scenario, the shrinker is also unable to help as lack of memory is not
the actual problem, since it has been observed that there are enough free
pages of 0 order. This also manifests itself when an indiviual zone in
the mm runs out of pages and if we cannot migrate pages between zones,
the kernel hits an out-of-memory even though there are free pages (and
often all of swap) available.

To address the issue of external fragementation, kernel does a compaction
(which involves migration of pages) but it's efficacy depends upon how
many pages are marked as MOVABLE, as only those pages can be migrated.

Currently the backing pages for GPU buffers are allocated from shmemfs
with GFP_RECLAIMABLE flag, in units of 4KB pages.  In the case of limited
swap space, it may not be possible always to reclaim or swap-out pages of
all the inactive objects, to make way for free space allowing formation
of higher order groups of physically-contiguous pages on compaction.

Just marking the GPU pages as MOVABLE will not suffice, as i915.ko has to
pin the pages if they are in use by GPU, which will prevent their
migration. So the migratepage callback in shmem is also hooked up to get
a notification when kernel initiates the page migration. On the
notification, i915.ko appropriately unpin the pages.  With this we can
effectively mark the GPU pages as MOVABLE and hence mitigate the
fragmentation problem.

v2:
 - Rename the migration routine to gem_shrink_migratepage, move it to the
   shrinker file, and use the existing constructs (Chris)
 - To cleanup, add a new helper function to encapsulate all page migration
   skip conditions (Chris)
 - Add a new local helper function in shrinker file, for dropping the
   backing pages, and call the same from gem_shrink() also (Chris)

v3:
 - Fix/invert the check on the return value of unsafe_drop_pages (Chris)

v4:
 - Minor tidy

v5:
 - Fix unsafe usage of unsafe_drop_pages()
 - Rebase onto vmap-notifier

Testcase: igt/gem_shrink
Bugzilla: (e.g.) https://bugs.freedesktop.org/show_bug.cgi?id=90254
Cc: Hugh Dickins 
Cc: linux...@kvack.org
Signed-off-by: Sourab Gupta 
Signed-off-by: Akash Goel 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_gem.c  |   6 +-
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 114 +++
 3 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ba1a242fb89a..1ef9cbde20e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1438,6 +1438,8 @@ struct intel_l3_parity {
 };
 
 struct i915_gem_mm {
+   struct shmem_dev_info shmem_info;
+
/** Memory allocator for GTT stolen memory */
struct drm_mm stolen;
/** Protects the usage of the GTT stolen memory allocator. This is
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 96dcfd6e02ca..f70e0d5b2ef9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2187,6 +2187,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object 
*obj,
 
lock_page(page);
munlock_vma_page(page);
+   set_page_private(page, 0);
unlock_page(page);
 
put_page(page);
@@ -2394,6 +2395,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
last_pfn = page_to_pfn(page);
 
lock_page(page);
+   set_page_private(page, (unsigned long)obj);
mlock_vma_page(page);
unlock_page(page);
 
@@ -2438,6 +2440,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
for_each_sgt_page(page, sgt_iter, st) {
lock_page(page);
munlock_vma_page(page);
+   set_page_private(page, 0);
unlock_page(page);
 
put_page(page);
@@ -4332,7 +4335,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, 
u64 size)
if (ret)
goto fail;
 
-   mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
+   mask = GFP_HIGHUSER_MOVABLE;
if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
/* 965gm cannot relocate objects above 4GiB. */
mask &= ~__GFP_HIGHMEM;
@@ -4342,6 +4345,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, 
u64 size)
mapping = obj->base.filp->f_mapping;
mapping_set_gfp_mask(mapping, mask);
GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
+   shmem_set_device_ops(mapping, &dev_priv->mm.shmem_info);
 
i915_gem_object_init(obj, &i915_gem_object_ops);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index

[Intel-gfx] [PATCH 13/20] drm/i915: Start writeback from the shrinker

2017-08-23 Thread Chris Wilson

When we are called to relieve mempressue via the shrinker, the only way
we can make progress is either by discarding unwanted pages (those
objects that userspace has marked MADV_DONTNEED) or by reclaiming the
dirty objects via swap. As we know that is the only way to make further
progress, we can initiate the writeback as we invalidate the objects.
This means the objects we put onto the inactive anon lru list are
already marked for reclaim+writeback and so will trigger a wait upon the
writeback inside direct reclaim, greatly improving the success rate of
direct reclaim on i915 objects.

The corollary is that we may start a slow swap on opportunistic
mempressure from the likes of the compaction + migration kthreads. This
is limited by those threads only being allowed to shrink idle pages, but
also that if we reactivate the page before it is swapped out by gpu
activity, we only page the cost of repinning the page. The cost is most
felt when an object is reused after mempressure, which hopefully
excludes the latency sensitive tasks (as we are just extending the
impact of swap thrashing to them).

Apparently this is not the first time we've had this idea. Back in
commit 5537252b6b6d ("drm/i915: Invalidate our pages under memory
pressure") we wanted to start writeback but settled on invalidate after
Hugh Dickins warned us about a possibility of a deadlock within shmemfs
if we started writeback from shrink_slab. Looking at the callchain,
using writeback from i915_gem_shrink should be equivalent to the pageout
also employed by shrink_slab, i.e. it should not be any riskier afaict.

v2: Leave mmapings intact. At this point, the only mmapings of our
objects will be via CPU mmaps on the shmemfs filp, which are
out-of-scope for our LRU tracking. Instead leave those pages to the
inactive anon LRU page list for aging and pageout as normal.

v3: Be selective on which paths trigger writeback, in particular
excluding paths shrinking just to reclaim vm space (e.g. mmap, vmap
reapers) and avoid starting writeback on the entire process space from
within the pm freezer.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Matthew Auld 
Cc: Daniel Vetter 
Cc: Michal Hocko 
Reviewed-by: Joonas Lahtinen  #v1
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +-
 drivers/gpu/drm/i915/i915_gem.c  | 32 +++--
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 77 ++--
 3 files changed, 81 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63306aa85749..f94cb9c8d7ed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3488,7 +3488,7 @@ enum i915_mm_subclass { /* lockdep subclass for 
obj->mm.lock */
 
 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
 enum i915_mm_subclass subclass);
-void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
+void __i915_gem_object_truncate(struct drm_i915_gem_object *obj);
 
 enum i915_map_type {
I915_MAP_WB = 0,
@@ -3762,6 +3762,7 @@ unsigned long i915_gem_shrink(struct drm_i915_private 
*dev_priv,
 #define I915_SHRINK_BOUND 0x4
 #define I915_SHRINK_ACTIVE 0x8
 #define I915_SHRINK_VMAPS 0x10
+#define I915_SHRINK_WRITEBACK 0x20
 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 88b52f23ee7a..b3e865a7e0fc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2144,8 +2144,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void 
*data,
 }
 
 /* Immediately discard the backing storage */
-static void
-i915_gem_object_truncate(struct drm_i915_gem_object *obj)
+void __i915_gem_object_truncate(struct drm_i915_gem_object *obj)
 {
i915_gem_object_free_mmap_offset(obj);
 
@@ -2162,28 +2161,6 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj)
obj->mm.pages = ERR_PTR(-EFAULT);
 }
 
-/* Try to discard unwanted pages */
-void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
-{
-   struct address_space *mapping;
-
-   lockdep_assert_held(&obj->mm.lock);
-   GEM_BUG_ON(i915_gem_object_has_pages(obj));
-
-   switch (obj->mm.madv) {
-   case I915_MADV_DONTNEED:
-   i915_gem_object_truncate(obj);
-   case __I915_MADV_PURGED:
-   return;
-   }
-
-   if (obj->base.filp == NULL)
-   return;
-
-   mapping = obj->base.filp->f_mapping,
-   invalidate_mapping_pages(mapping, 0, (loff_t)-1);
-}
-
 static void
 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
  struct sg_table *pages)
@@ -2347,7 +2324,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*o

[Intel-gfx] [PATCH 16/20] mm: Track actual nr_scanned during shrink_slab()

2017-08-23 Thread Chris Wilson

Some shrinkers may only be able to free a bunch of objects at a time, and
so free more than the requested nr_to_scan in one pass. Whilst other
shrinkers may find themselves even unable to scan as many objects as
they counted, and so underreport. Account for the extra freed/scanned
objects against the total number of objects we intend to scan, otherwise
we may end up penalising the slab far more than intended. Similarly,
we want to add the underperforming scan to the deferred pass so that we
try harder and harder in future passes.

v2: Andrew's shrinkctl->nr_scanned

Signed-off-by: Chris Wilson 
Cc: Andrew Morton 
Cc: Michal Hocko 
Cc: Johannes Weiner 
Cc: Hillf Danton 
Cc: Minchan Kim 
Cc: Vlastimil Babka 
Cc: Mel Gorman 
Cc: Shaohua Li 
Cc: linux...@kvack.org
---
 include/linux/shrinker.h | 7 +++
 mm/vmscan.c  | 7 ---
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/include/linux/shrinker.h b/include/linux/shrinker.h
index 4fcacd915d45..51d189615bda 100644
--- a/include/linux/shrinker.h
+++ b/include/linux/shrinker.h
@@ -18,6 +18,13 @@ struct shrink_control {
 */
unsigned long nr_to_scan;
 
+   /*
+* How many objects did scan_objects process?
+* This defaults to nr_to_scan before every call, but the callee
+* should track its actual progress.
+*/
+   unsigned long nr_scanned;
+
/* current node being shrunk (for NUMA aware shrinkers) */
int nid;
 
diff --git a/mm/vmscan.c b/mm/vmscan.c
index a1af041930a6..339b8fc95fc9 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -393,14 +393,15 @@ static unsigned long do_shrink_slab(struct shrink_control 
*shrinkctl,
unsigned long nr_to_scan = min(batch_size, total_scan);
 
shrinkctl->nr_to_scan = nr_to_scan;
+   shrinkctl->nr_scanned = nr_to_scan;
ret = shrinker->scan_objects(shrinker, shrinkctl);
if (ret == SHRINK_STOP)
break;
freed += ret;
 
-   count_vm_events(SLABS_SCANNED, nr_to_scan);
-   total_scan -= nr_to_scan;
-   scanned += nr_to_scan;
+   count_vm_events(SLABS_SCANNED, shrinkctl->nr_scanned);
+   total_scan -= shrinkctl->nr_scanned;
+   scanned += shrinkctl->nr_scanned;
 
cond_resched();
}
-- 
2.14.1

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[Intel-gfx] [PATCH 17/20] drm/i915: Wire up shrinkctl->nr_scanned

2017-08-23 Thread Chris Wilson

shrink_slab() allows us to report back the number of objects we
successfully scanned (out of the target shrinkctl->nr_to_scan). As
report the number of pages owned by each GEM object as a separate item
to the shrinker, we cannot precisely control the number of shrinker
objects we scan on each pass; and indeed may free more than requested.
If we fail to tell the shrinker about the number of objects we process,
it will continue to hold a grudge against us as any objects left
unscanned are added to the next reclaim -- and so we will keep on
"unfairly" shrinking our own slab in comparison to other slabs.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Andrew Morton 
Cc: Michal Hocko 
Cc: Johannes Weiner 
Cc: Hillf Danton 
Cc: Minchan Kim 
Cc: Vlastimil Babka 
Cc: Mel Gorman 
Cc: Shaohua Li 
Cc: linux...@kvack.org
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_gem.c  |  4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 26 +++---
 5 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6bad53f89738..ed979cc6fb5d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4338,10 +4338,10 @@ i915_drop_caches_set(void *data, u64 val)
 
lockdep_set_current_reclaim_state(GFP_KERNEL);
if (val & DROP_BOUND)
-   i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
+   i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
 
if (val & DROP_UNBOUND)
-   i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
+   i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
 
if (val & DROP_SHRINK_ALL)
i915_gem_shrink_all(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf49c01d60e5..ba1a242fb89a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3757,6 +3757,7 @@ i915_gem_object_create_internal(struct drm_i915_private 
*dev_priv,
 /* i915_gem_shrinker.c */
 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
  unsigned long target,
+ unsigned long *nr_scanned,
  unsigned flags);
 #define I915_SHRINK_PURGEABLE 0x1
 #define I915_SHRINK_UNBOUND 0x2
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5284d30187ac..b5ea75187064 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2342,7 +2342,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
goto err_sg;
}
 
-   i915_gem_shrink(dev_priv, 2 * page_count, *s++);
+   i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++);
cond_resched();
 
/* We've tried hard to allocate the memory by reaping
@@ -5040,7 +5040,7 @@ int i915_gem_freeze_late(struct drm_i915_private 
*dev_priv)
 * the objects as well, see i915_gem_freeze()
 */
 
-   i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
+   i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_UNBOUND);
i915_gem_drain_freed_objects(dev_priv);
 
spin_lock(&dev_priv->mm.obj_lock);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e7d359f89df0..c3756805bc52 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2128,7 +2128,7 @@ int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object 
*obj,
 */
GEM_BUG_ON(obj->mm.pages == pages);
} while (i915_gem_shrink(to_i915(obj->base.dev),
-obj->base.size >> PAGE_SHIFT,
+obj->base.size >> PAGE_SHIFT, NULL,
 I915_SHRINK_BOUND |
 I915_SHRINK_UNBOUND |
 I915_SHRINK_ACTIVE));
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 2a272045cf4d..a909787c209e 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -202,6 +202,7 @@ static void __start_writeback(struct drm_i915_gem_object 
*obj,
  * i915_gem_shrink - Shrink buffer object caches
  * @dev_priv: i915 device
  * @target: amount of memory to make available, in pages
+ * @nr_scanned: optional output for number of pages scanned (incremental)
  * @flags: control flags for selecting cache types
  *
  * This function is the main interface to the shrinker. It will try to release
@@ -224,7 +225,9 @@ static void __start_writeback(struct drm_i9

[Intel-gfx] [PATCH 09/20] drm/i915: Remove walk over obj->vma_list for the shrinker

2017-08-23 Thread Chris Wilson

In the next patch, we want to reduce the lock coverage within the
shrinker, and one of the dangerous walks we have is over obj->vma_list.
We are only walking the obj->vma_list in order to check whether it has
been permanently pinned by HW access, typically via use on the scanout.
But we have a couple of other long term pins, the context objects for
which we currently have to check the individual vma pin_count. If we
instead mark these using obj->pin_display, we can forgo the dangerous
and sometimes slow list iteration.

v2: Rearrange code to try and avoid confusion from false associations
due to arrangement of whitespace along with rebasing on obj->pin_global.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 27 +++
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  7 ++-
 3 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 80caeadb9d34..efb201911cdb 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -71,25 +71,6 @@ static void shrinker_unlock(struct drm_i915_private 
*dev_priv, bool unlock)
mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
-static bool any_vma_pinned(struct drm_i915_gem_object *obj)
-{
-   struct i915_vma *vma;
-
-   list_for_each_entry(vma, &obj->vma_list, obj_link) {
-   /* Only GGTT vma may be permanently pinned, and are always
-* at the start of the list. We can stop hunting as soon
-* as we see a ppGTT vma.
-*/
-   if (!i915_vma_is_ggtt(vma))
-   break;
-
-   if (i915_vma_is_pinned(vma))
-   return true;
-   }
-
-   return false;
-}
-
 static bool swap_available(void)
 {
return get_nr_swap_pages() > 0;
@@ -115,7 +96,13 @@ static bool can_release_pages(struct drm_i915_gem_object 
*obj)
if (atomic_read(&obj->mm.pages_pin_count) > obj->bind_count)
return false;
 
-   if (any_vma_pinned(obj))
+   /* If any vma are "permanently" pinned, it will prevent us from
+* reclaiming the obj->mm.pages. We only allow scanout objects to claim
+* a permanent pin, along with a few others like the context objects.
+* To simplify the scan, and to avoid walking the list of vma under the
+* object, we just check the count of its permanently pinned.
+*/
+   if (obj->pin_global)
return false;
 
/* We can only return physical pages to the system if we can either
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d89e1b8e1cc5..68deede1f666 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -866,6 +866,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
i915_ggtt_offset(ce->ring->vma);
 
ce->state->obj->mm.dirty = true;
+   ce->state->obj->pin_global++;
 
i915_gem_context_get(ctx);
 out:
@@ -893,6 +894,7 @@ static void execlists_context_unpin(struct intel_engine_cs 
*engine,
 
intel_ring_unpin(ce->ring);
 
+   ce->state->obj->pin_global--;
i915_gem_object_unpin_map(ce->state->obj);
i915_vma_unpin(ce->state);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cdf084ef5aae..c3b1f10aa98a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1321,6 +1321,7 @@ int intel_ring_pin(struct intel_ring *ring,
if (IS_ERR(addr))
goto err;
 
+   vma->obj->pin_global++;
ring->vaddr = addr;
return 0;
 
@@ -1352,6 +1353,7 @@ void intel_ring_unpin(struct intel_ring *ring)
i915_gem_object_unpin_map(ring->vma->obj);
ring->vaddr = NULL;
 
+   ring->vma->obj->pin_global--;
i915_vma_unpin(ring->vma);
 }
 
@@ -1515,6 +1517,7 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
 
+   ce->state->obj->pin_global++;
ce->state->obj->mm.dirty = true;
}
 
@@ -1550,8 +1553,10 @@ static void intel_ring_context_unpin(struct 
intel_engine_cs *engine,
if (--ce->pin_count)
return;
 
-   if (ce->state)
+   if (ce->state) {
+   ce->state->obj->pin_global--;
i915_vma_unpin(ce->state);
+   }
 
i915_gem_context_put(ctx);
 }
-- 
2.14.1

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[Intel-gfx] [PATCH 19/20] shmem: Support for registration of driver/file owner specific ops

2017-08-23 Thread Chris Wilson

From: Akash Goel 

This provides support for the drivers or shmem file owners to register
a set of callbacks, which can be invoked from the address space
operations methods implemented by shmem.  This allow the file owners to
hook into the shmem address space operations to do some extra/custom
operations in addition to the default ones.

The private_data field of address_space struct is used to store the
pointer to driver specific ops.  Currently only one ops field is defined,
which is migratepage, but can be extended on an as-needed basis.

The need for driver specific operations arises since some of the
operations (like migratepage) may not be handled completely within shmem,
so as to be effective, and would need some driver specific handling also.
Specifically, i915.ko would like to participate in migratepage().
i915.ko uses shmemfs to provide swappable backing storage for its user
objects, but when those objects are in use by the GPU it must pin the
entire object until the GPU is idle.  As a result, large chunks of memory
can be arbitrarily withdrawn from page migration, resulting in premature
out-of-memory due to fragmentation.  However, if i915.ko can receive the
migratepage() request, it can then flush the object from the GPU, remove
its pin and thus enable the migration.

Since gfx allocations are one of the major consumer of system memory, its
imperative to have such a mechanism to effectively deal with
fragmentation.  And therefore the need for such a provision for initiating
driver specific actions during address space operations.

Cc: Hugh Dickins 
Cc: linux...@kvack.org
Cc: linux-ker...@vger.linux.org
Signed-off-by: Sourab Gupta 
Signed-off-by: Akash Goel 
Reviewed-by: Chris Wilson 
---
 include/linux/shmem_fs.h | 17 +
 mm/shmem.c   | 17 -
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
index a7d6bd2a918f..16d48b621d3c 100644
--- a/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@ -39,11 +39,28 @@ struct shmem_sb_info {
unsigned long shrinklist_len; /* Length of shrinklist */
 };
 
+struct shmem_dev_info {
+   void *dev_private_data;
+   int (*dev_migratepage)(struct address_space *mapping,
+  struct page *newpage, struct page *page,
+  enum migrate_mode mode, void *dev_priv_data);
+};
+
 static inline struct shmem_inode_info *SHMEM_I(struct inode *inode)
 {
return container_of(inode, struct shmem_inode_info, vfs_inode);
 }
 
+static inline int shmem_set_device_ops(struct address_space *mapping,
+  struct shmem_dev_info *info)
+{
+   if (mapping->private_data)
+   return -EEXIST;
+
+   mapping->private_data = info;
+   return 0;
+}
+
 /*
  * Functions in mm/shmem.c called directly from elsewhere:
  */
diff --git a/mm/shmem.c b/mm/shmem.c
index 6540e5982444..fa9226033a20 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -1340,6 +1340,21 @@ static int shmem_writepage(struct page *page, struct 
writeback_control *wbc)
return 0;
 }
 
+#ifdef CONFIG_MIGRATION
+static int shmem_migratepage(struct address_space *mapping,
+struct page *newpage, struct page *page,
+enum migrate_mode mode)
+{
+   struct shmem_dev_info *dev_info = mapping->private_data;
+
+   if (dev_info && dev_info->dev_migratepage)
+   return dev_info->dev_migratepage(mapping, newpage, page,
+   mode, dev_info->dev_private_data);
+
+   return migrate_page(mapping, newpage, page, mode);
+}
+#endif
+
 #if defined(CONFIG_NUMA) && defined(CONFIG_TMPFS)
 static void shmem_show_mpol(struct seq_file *seq, struct mempolicy *mpol)
 {
@@ -3841,7 +3856,7 @@ static const struct address_space_operations shmem_aops = 
{
.write_end  = shmem_write_end,
 #endif
 #ifdef CONFIG_MIGRATION
-   .migratepage= migrate_page,
+   .migratepage= shmem_migratepage,
 #endif
.error_remove_page = generic_error_remove_page,
 };
-- 
2.14.1

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Re: [Intel-gfx] [GIT PULL] gvt final fixes for 4.13

2017-08-23 Thread Jani Nikula

On Wed, 23 Aug 2017, Zhenyu Wang  wrote:
> Hi, here's one final gvt fix for 4.13. One possible null ptr
> reference issue fixed by Fred.

Pulled to drm-intel-fixes, thanks.

BR,
Jani.

>
> Thanks
> --
> The following changes since commit d6086598d34e1cf9091c7be201f5b2041dc6203e:
>
>   drm/i915/gvt: Change the max length of mmio_reg_rw from 4 to 8 (2017-08-07 
> 15:50:39 +0800)
>
> are available in the git repository at:
>
>   https://github.com/01org/gvt-linux.git tags/gvt-fixes-2017-08-23
>
> for you to fetch changes up to ffeaf9aaf97b4bdaf114d6df52f800d71918768c:
>
>   drm/i915/gvt: Fix the kernel null pointer error (2017-08-23 14:08:57 +0800)
>
> 
> gvt-fixes-2017-08-23
>
> - Fix possible null ptr reference in error path (Fred)
>
> 
> fred gao (1):
>   drm/i915/gvt: Fix the kernel null pointer error
>
>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH i-g-t 05/11] tests/perf: rework oa-exponent test

2017-08-23 Thread Lionel Landwerlin


On 22/08/17 17:13, Matthew Auld wrote:

On 22 August 2017 at 15:56, Lionel Landwerlin
 wrote:

On 10/08/17 14:15, Matthew Auld wrote:

On 4 August 2017 at 12:20, Lionel Landwerlin
 wrote:

New issues that were discovered while making the tests work on Gen8+ :

  - we need to measure timings between periodic reports and discard all
other kind of reports

  - it seems periodicity of the reports can be affected outside of RC6
(frequency change), we can detect this by looking at the amount of
clock cycles per timestamp deltas

I think this would be easier to review if we split this into two patches...

Also, somewhat worrying is that I've yet to see the oa-exponents test
pass on my BDW machine.

See here:
https://paste.fedoraproject.org/paste/SmOw7eHEGOTjrLsvPVcZOw/raw

Was your screen off?

I don't think so, same result with it on/off though. I'm guessing that
is passes for you then?

Here's the pastebin again, since the other one is now toast:
https://paste.fedoraproject.org/paste/tjSb4jPZ87sWjhj7qAD~UA/raw

Chris helped prove that this probably be power management preventing the 
unit to write its report to memory.
I don't think there is a way to tune that from userspace, so I guess 
I'll try to detect this. It's pretty reproducible on my system with 
screen off.

Maybe you're on battery only?

-
Lionel
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Re: [Intel-gfx] [PATCH 01/23] mm/shmem: introduce shmem_file_setup_with_mnt

2017-08-23 Thread Joonas Lahtinen

Hi Andrew,

This patch has been floating around for a while now Acked and without
further comments. It is blocking us from merging huge page support to
drm/i915.

Would you mind merging it, or prodding the right people to get it in?

Regards, Joonas

On Mon, 2017-08-21 at 19:34 +0100, Matthew Auld wrote:
> We are planning to use our own tmpfs mnt in i915 in place of the
> shm_mnt, such that we can control the mount options, in particular
> huge=, which we require to support huge-gtt-pages. So rather than roll
> our own version of __shmem_file_setup, it would be preferred if we could
> just give shmem our mnt, and let it do the rest.
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Dave Hansen 
> Cc: Kirill A. Shutemov 
> Cc: Hugh Dickins 
> Cc: linux...@kvack.org
> Acked-by: Kirill A. Shutemov 
> Reviewed-by: Joonas Lahtinen 
> ---
>  include/linux/shmem_fs.h |  2 ++
>  mm/shmem.c   | 30 ++
>  2 files changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
> index a7d6bd2a918f..27de676f0b63 100644
> --- a/include/linux/shmem_fs.h
> +++ b/include/linux/shmem_fs.h
> @@ -53,6 +53,8 @@ extern struct file *shmem_file_setup(const char *name,
>   loff_t size, unsigned long flags);
>  extern struct file *shmem_kernel_file_setup(const char *name, loff_t size,
>   unsigned long flags);
> +extern struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt,
> + const char *name, loff_t size, unsigned long flags);
>  extern int shmem_zero_setup(struct vm_area_struct *);
>  extern unsigned long shmem_get_unmapped_area(struct file *, unsigned long 
> addr,
>   unsigned long len, unsigned long pgoff, unsigned long flags);
> diff --git a/mm/shmem.c b/mm/shmem.c
> index 6540e5982444..0975e65ea61c 100644
> --- a/mm/shmem.c
> +++ b/mm/shmem.c
> @@ -4141,7 +4141,7 @@ static const struct dentry_operations anon_ops = {
>   .d_dname = simple_dname
>  };
>  
> -static struct file *__shmem_file_setup(const char *name, loff_t size,
> +static struct file *__shmem_file_setup(struct vfsmount *mnt, const char 
> *name, loff_t size,
>  unsigned long flags, unsigned int 
> i_flags)
>  {
>   struct file *res;
> @@ -4150,8 +4150,8 @@ static struct file *__shmem_file_setup(const char 
> *name, loff_t size,
>   struct super_block *sb;
>   struct qstr this;
>  
> - if (IS_ERR(shm_mnt))
> - return ERR_CAST(shm_mnt);
> + if (IS_ERR(mnt))
> + return ERR_CAST(mnt);
>  
>   if (size < 0 || size > MAX_LFS_FILESIZE)
>   return ERR_PTR(-EINVAL);
> @@ -4163,8 +4163,8 @@ static struct file *__shmem_file_setup(const char 
> *name, loff_t size,
>   this.name = name;
>   this.len = strlen(name);
>   this.hash = 0; /* will go */
> - sb = shm_mnt->mnt_sb;
> - path.mnt = mntget(shm_mnt);
> + sb = mnt->mnt_sb;
> + path.mnt = mntget(mnt);
>   path.dentry = d_alloc_pseudo(sb, &this);
>   if (!path.dentry)
>   goto put_memory;
> @@ -4209,7 +4209,7 @@ static struct file *__shmem_file_setup(const char 
> *name, loff_t size,
>   */
>  struct file *shmem_kernel_file_setup(const char *name, loff_t size, unsigned 
> long flags)
>  {
> - return __shmem_file_setup(name, size, flags, S_PRIVATE);
> + return __shmem_file_setup(shm_mnt, name, size, flags, S_PRIVATE);
>  }
>  
>  /**
> @@ -4220,11 +4220,25 @@ struct file *shmem_kernel_file_setup(const char 
> *name, loff_t size, unsigned lon
>   */
>  struct file *shmem_file_setup(const char *name, loff_t size, unsigned long 
> flags)
>  {
> - return __shmem_file_setup(name, size, flags, 0);
> + return __shmem_file_setup(shm_mnt, name, size, flags, 0);
>  }
>  EXPORT_SYMBOL_GPL(shmem_file_setup);
>  
>  /**
> + * shmem_file_setup_with_mnt - get an unlinked file living in tmpfs
> + * @mnt: the tmpfs mount where the file will be created
> + * @name: name for dentry (to be seen in /proc//maps
> + * @size: size to be set for the file
> + * @flags: VM_NORESERVE suppresses pre-accounting of the entire object size
> + */
> +struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt, const char 
> *name,
> +loff_t size, unsigned long flags)
> +{
> + return __shmem_file_setup(mnt, name, size, flags, 0);
> +}
> +EXPORT_SYMBOL_GPL(shmem_file_setup_with_mnt);
> +
> +/**
>   * shmem_zero_setup - setup a shared anonymous mapping
>   * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
>   */
> @@ -4239,7 +4253,7 @@ int shmem_zero_setup(struct vm_area_struct *vma)
>* accessible to the user through its mapping, use S_PRIVATE flag to
>* bypass file security, in the same way as shmem_kernel_file_setup().
>*/
> - file = __shmem_file_setup("dev/zero", size, vma->vm_flags, S_PRIVATE);
>

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/20] drm/i915: "Race-to-idle" on switching to the kernel context

2017-08-23 Thread Patchwork

== Series Details ==

Series: series starting with [01/20] drm/i915: "Race-to-idle" on switching to 
the kernel context
URL   : https://patchwork.freedesktop.org/series/29201/
State : failure

== Summary ==

Series 29201v1 series starting with [01/20] drm/i915: "Race-to-idle" on 
switching to the kernel context
https://patchwork.freedesktop.org/api/1.0/series/29201/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> FAIL   (fi-bdw-gvtdvm)

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-bdw-gvtdvmtotal:279  pass:264  dwarn:0   dfail:0   fail:1   skip:14  
time:435s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:547s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:531s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:512s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:608s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:447s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:501s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7260u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:496s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:522s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:484s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:482s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:434s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:407s

489147dfdcc735baf773a6ec3698cf85a01d7008 drm-tip: 2017y-08m-22d-18h-44m-32s UTC 
integration manifest
805381f2460c drm/i915: Make GPU pages movable
2cc3c8ae2cc4 shmem: Support for registration of driver/file owner specific ops
b3e979a66431 mm, drm/i915: Mark pinned shmemfs pages as unevictable
491feb03b336 drm/i915: Wire up shrinkctl->nr_scanned
9814885137e4 mm: Track actual nr_scanned during shrink_slab()
90b4f2e3138c drm/i915: Only free the oldest stale object before a fresh 
allocation
9bbe81783cd4 drm/i915: Discard VMA lut handles upon purging the object
573ed4343ede drm/i915: Start writeback from the shrinker
2d4c59712d3e drm/i915: Trim struct_mutex hold duration for i915_gem_free_objects
d3a045670786 drm/i915: Set our shrinker->batch to 4096 (~16MiB)
f1a586304a9e drm/i915: Move dev_priv->mm.[un]bound_list to its own lock
ea3deac6516b drm/i915: Remove walk over obj->vma_list for the shrinker
e411bdf2cbd1 drm/i915: Drop debugfs/i915_gem_pin_display
eae4b83d4dbd drm/i915: Rename obj->pin_display to obj->pin_global
0a6d26bc5b82 drm/i915: Refactor testing obj->mm.pages
e590903719c4 drm/i915: Prevent overflow of execbuf.buffer_count and 
num_cliprects
71d5706f89ae drm/i915: Ignore duplicate VMA stored within the per-object handle 
LUT
877632c04a01 drm/i915: Assert that the handle->vma lut is empty on object close
e6409d2d2d8d drm/i915: Assert the context is not closed on object-close
c410482a4a3b drm/i915: "Race-to-idle" on switching to the kernel context

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5473/
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[Intel-gfx] [PATCH v2 01/10] tests/perf: make stream_fd a global variable

2017-08-23 Thread Lionel Landwerlin

When debugging unstable tests on new platforms we currently we don't
cleanup everything well in between different tests. Since only a
single OA stream fd can be opened at a time, having the stream_fd as a
global variable helps us cleanup the state between tests.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 121 ---
 1 file changed, 65 insertions(+), 56 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index dd2263ee..ca5bfdc5 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -285,6 +285,7 @@ static bool hsw_undefined_a_counters[45] = {
 static bool gen8_undefined_a_counters[45];
 
 static int drm_fd = -1;
+static int stream_fd = -1;
 static uint32_t devid;
 static int card = -1;
 static int n_eus;
@@ -306,10 +307,22 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static void
+__perf_close(int fd)
+{
+   close(fd);
+   stream_fd = -1;
+}
+
 static int
 __perf_open(int fd, struct drm_i915_perf_open_param *param)
 {
-   int ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
+   int ret;
+
+   if (stream_fd >= 0)
+   __perf_close(stream_fd);
+
+   ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
 
igt_assert(ret >= 0);
errno = 0;
@@ -960,14 +973,12 @@ test_system_wide_paranoid(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
-
write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
 
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1015,7 +1026,6 @@ test_invalid_oa_metric_set_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m, EINVAL);
 
@@ -1025,7 +1035,7 @@ test_invalid_oa_metric_set_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_metric_set_id;
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA metric set ID... */
param.num_properties--;
@@ -1050,7 +1060,6 @@ test_invalid_oa_format_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m, EINVAL);
 
@@ -1060,7 +1069,7 @@ test_invalid_oa_format_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_oa_format;
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA format... */
param.num_properties--;
@@ -1088,8 +1097,7 @@ test_missing_sample_flags(void)
 }
 
 static void
-read_2_oa_reports(int stream_fd,
- int format_id,
+read_2_oa_reports(int format_id,
  int exponent,
  uint32_t *oa_report0,
  uint32_t *oa_report1,
@@ -1223,12 +1231,13 @@ open_and_read_2_oa_reports(int format_id,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, ¶m);
 
-   read_2_oa_reports(stream_fd, format_id, exponent,
+   stream_fd = __perf_open(drm_fd, ¶m);
+
+   read_2_oa_reports(format_id, exponent,
  oa_report0, oa_report1, timer_only);
 
-   close(stream_fd);
+   __perf_close(stream_fd);
 }
 
 static void
@@ -1528,9 +1537,10 @@ test_invalid_oa_exponent(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, ¶m);
 
-   close(stream_fd);
+   stream_fd = __perf_open(drm_fd, ¶m);
+
+   __perf_close(stream_fd);
 
for (int i = 32; i < 65; i++) {
properties[7] = i;
@@ -1580,12 +1590,10 @@ test_low_oa_exponent_permissions(void)
properties[7] = ok_exponent;
 
igt_fork(child, 1) {
-   int stream_fd;
-
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1634,7 +1642,6 @@ test_per_context_mode_unprivileged(void)
igt_fork(child,

[Intel-gfx] [PATCH v2 02/10] tests/perf: add per context filtering test for gen8+

2017-08-23 Thread Lionel Landwerlin

From: Robert Bragg 

v2: Remove the changes touching oa-exponent test (Matthew)
Cleanup some comments bits (Matthew)

Signed-off-by: Robert Bragg 
Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 777 ---
 1 file changed, 745 insertions(+), 32 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index ca5bfdc5..5058315c 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -48,7 +48,9 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming 
interface");
 #define OAREPORT_REASON_MASK   0x3f
 #define OAREPORT_REASON_SHIFT  19
 #define OAREPORT_REASON_TIMER  (1<<0)
+#define OAREPORT_REASON_INTERNAL   (3<<1)
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
+#define OAREPORT_REASON_GO (1<<4)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
 #define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24))
@@ -574,6 +576,22 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_ctx_is_valid(uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   return false; /* TODO */
+   } else if (IS_GEN8(devid)) {
+   return report[0] & (1ul << 25);
+   } else if (IS_GEN9(devid)) {
+   return report[0] & (1ul << 16);
+   }
+
+   /* Need to update this function for newer Gen. */
+   igt_assert(!"reached");
+}
+
+
 static void
 hsw_sanity_check_render_basic_reports(uint32_t *oa_report0, uint32_t 
*oa_report1,
  enum drm_i915_oa_format fmt)
@@ -678,6 +696,100 @@ gen8_40bit_a_delta(uint64_t value0, uint64_t value1)
return value1 - value0;
 }
 
+static void
+accumulate_uint32(size_t offset,
+ uint32_t *report0,
+  uint32_t *report1,
+  uint64_t *delta)
+{
+   uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset);
+   uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset);
+
+   *delta += (uint32_t)(value1 - value0);
+}
+
+static void
+accumulate_uint40(int a_index,
+  uint32_t *report0,
+  uint32_t *report1,
+ enum drm_i915_oa_format format,
+  uint64_t *delta)
+{
+   uint64_t value0 = gen8_read_40bit_a_counter(report0, format, a_index),
+value1 = gen8_read_40bit_a_counter(report1, format, a_index);
+
+   *delta += gen8_40bit_a_delta(value0, value1);
+}
+
+static void
+accumulate_reports(struct accumulator *accumulator,
+  uint32_t *start,
+  uint32_t *end)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   if (intel_gen(devid) >= 8) {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+
+   /* clock cycles */
+   accumulate_uint32(12, start, end, deltas + idx++);
+   } else {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   accumulate_uint40(i, start, end, format, deltas + idx++);
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   accumulate_uint32(oa_formats[format].a_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_b; i++) {
+   accumulate_uint32(oa_formats[format].b_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_c; i++) {
+   accumulate_uint32(oa_formats[format].c_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+}
+
+static void
+accumulator_print(struct accumulator *accumulator, const char *title)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   igt_debug("%s:\n", title);
+   if (intel_gen(devid) >= 8) {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   igt_debug("\tclock cycle delta = %lu\n", deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   igt_debug("\tA%u = %lu\n", i, deltas[idx++]);
+   } else {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   int a_id = oa_formats[format].first_a + i;
+   igt_debug("\tA%u = %lu\n", a_id, deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++)
+   igt_debug("\tB%u = %lu\n", i, deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_c; i++)
+   igt_debug("\tC%u = %lu\n", i, d

[Intel-gfx] [PATCH v2 00/10] Improve robustness of the i915 perf tests

2017-08-23 Thread Lionel Landwerlin

Hi all,

Here is an updated patch series containing mostly cleanups.

Cheers,

Lionel Landwerlin (9):
  tests/perf: make stream_fd a global variable
  tests/perf: update max buffer size for reading reports
  tests/perf: rc6: try to guess when rc6 is disabled
  tests/perf: remove frequency related changes
  tests/perf: rework oa-exponent test
  tests/perf: make enable-disable more reliable
  tests/perf: make buffer-fill more reliable
  tests/perf: add Kabylake support
  tests/perf: add Geminilake support

Robert Bragg (1):
  tests/perf: add per context filtering test for gen8+

 tests/perf.c | 1958 +++---
 1 file changed, 1612 insertions(+), 346 deletions(-)

--
2.14.1
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[Intel-gfx] [PATCH v2 05/10] tests/perf: remove frequency related changes

2017-08-23 Thread Lionel Landwerlin

Experience shows that most of the issues we face with periodicity of
the reports produced by the OA unit are related to power management,
not frequency.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 143 +--
 1 file changed, 10 insertions(+), 133 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 1b441601..b7deb9b2 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -293,12 +293,9 @@ static int card = -1;
 static int n_eus;
 
 static uint64_t test_metric_set_id = UINT64_MAX;
-static uint64_t gt_min_freq_mhz_saved = 0;
-static uint64_t gt_max_freq_mhz_saved = 0;
-static uint64_t gt_min_freq_mhz = 0;
-static uint64_t gt_max_freq_mhz = 0;
 
 static uint64_t timestamp_frequency = 1250;
+static uint64_t gt_max_freq_mhz = 0;
 static enum drm_i915_oa_format test_oa_format;
 static bool *undefined_a_counters;
 static uint64_t oa_exp_1_millisec;
@@ -402,16 +399,6 @@ sysfs_read(const char *file)
return read_u64_file(buf);
 }
 
-static void
-sysfs_write(const char *file, uint64_t val)
-{
-   char buf[512];
-
-   snprintf(buf, sizeof(buf), "/sys/class/drm/card%d/%s", card, file);
-
-   write_u64_file(buf, val);
-}
-
 static char *
 read_debugfs_record(int device, const char *file, const char *key)
 {
@@ -990,54 +977,6 @@ init_sys_info(void)
return try_read_u64_file(buf, &test_metric_set_id);
 }
 
-static void
-gt_frequency_range_save(void)
-{
-   gt_min_freq_mhz_saved = sysfs_read("gt_min_freq_mhz");
-   gt_max_freq_mhz_saved = sysfs_read("gt_max_freq_mhz");
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
-static void
-gt_frequency_pin(int gt_freq_mhz)
-{
-   igt_debug("requesting pinned GT freq = %dmhz\n", gt_freq_mhz);
-
-   if (gt_freq_mhz > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   }
-   gt_min_freq_mhz = gt_freq_mhz;
-   gt_max_freq_mhz = gt_freq_mhz;
-}
-
-static void
-gt_frequency_range_restore(void)
-{
-   igt_debug("restoring GT frequency range: min = %dmhz, max =%dmhz, 
current: min=%dmhz, max=%dmhz\n",
- (int)gt_min_freq_mhz_saved,
- (int)gt_max_freq_mhz_saved,
- (int)gt_min_freq_mhz,
- (int)gt_max_freq_mhz);
-
-   /* Assume current min/max are the same */
-   if (gt_min_freq_mhz_saved > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   }
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
 static int
 i915_read_reports_until_timestamp(enum drm_i915_oa_format oa_format,
  uint8_t *buf,
@@ -1614,33 +1553,9 @@ test_oa_formats(void)
 }
 
 static void
-test_oa_exponents(int gt_freq_mhz)
+test_oa_exponents(void)
 {
-   uint32_t freq_margin;
-
-   /* This test tries to use the sysfs interface for pinning the GT
-* frequency so we have another point of reference for comparing with
-* the clock frequency as derived from OA reports.
-*
-* This test has been finicky to stabilise while the
-* gt_min/max_freq_mhz files in sysfs don't seem to be a reliable
-* mechanism for fixing the gpu frequency.
-*
-* Since these unit tests are focused on the OA unit not the ability to
-* pin the frequency via sysfs we make the test account for pinning not
-* being reliable and read back the current frequency for each
-* iteration of this test to take this into account.
-*/
-   gt_frequency_pin(gt_freq_mhz);
-
-   igt_debug("Testing OA timer exponents with requested GT frequency = 
%dmhz\n",
- gt_freq_mhz);
-
-   /* allow a +- 10% error margin when checking that the frequency
-* calculated from the OA reports matches the frequency according to
-* sysfs.
-*/
-   freq_margin = gt_freq_mhz * 0.1;
+   igt_debug("Testing OA timer exponents\n");
 
/* It's asking a lot to sample with a 160 nanosecond period and the
 * test can fail due to buffer overflows if it wasn't possible to
@@ -1655,7 +1570,6 @@ test_oa_exponents(int gt_freq_mhz)
uint32_t clock_delta;
uint32_t freq;
int n_tested = 0;
-   int n_freq_matches = 0;
 
/* The exponent is effectively selecting a bit in the timestamp
 * to trigger reports on and so in practi

[Intel-gfx] [PATCH v2 07/10] tests/perf: make enable-disable more reliable

2017-08-23 Thread Lionel Landwerlin

Estimation of the amount of reports can only refer to periodic ones,
as context switch reports completely depend on what happens on the
system. Also generate some load to prevent clock frequency changes to
impact our measurement.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 96 
 1 file changed, 90 insertions(+), 6 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index d9afa494..299706cd 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2779,10 +2779,18 @@ test_enable_disable(void)
int n_full_oa_reports = oa_buf_size / report_size;
uint64_t fill_duration = n_full_oa_reports * oa_period;
 
+   load_helper_init();
+   load_helper_run(HIGH);
+
stream_fd = __perf_open(drm_fd, ¶m);
 
for (int i = 0; i < 5; i++) {
int len;
+   uint32_t n_periodic_reports;
+   struct drm_i915_perf_record_header *header;
+   uint32_t first_timestamp = 0, last_timestamp = 0;
+   uint32_t last_periodic_report[64];
+   double tick_per_period;
 
/* Giving enough time for an overflow might help catch whether
 * the OA unit has been enabled even if the driver might at
@@ -2802,18 +2810,91 @@ test_enable_disable(void)
 
nanosleep(&(struct timespec){ .tv_sec = 0,
  .tv_nsec = fill_duration / 2 },
- NULL);
+   NULL);
 
-   while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == 
EINTR)
-   ;
+   n_periodic_reports = 0;
 
-   igt_assert_neq(len, -1);
+   /* Because of the race condition between notification of new
+* reports and reports landing in memory, we need to rely on
+* timestamps to figure whether we've read enough of them.
+*/
+   while (((last_timestamp - first_timestamp) * 
oa_exponent_to_ns(oa_exponent)) <
+  (fill_duration / 2)) {
 
-   igt_assert(len > report_size * n_full_oa_reports * 0.45);
-   igt_assert(len < report_size * n_full_oa_reports * 0.55);
+   while ((len = read(stream_fd, buf, buf_size)) == -1 && 
errno == EINTR)
+   ;
+
+   igt_assert_neq(len, -1);
+
+   for (int offset = 0; offset < len; offset += 
header->size) {
+   uint32_t *report;
+   double previous_tick_per_period;
+
+   header = (void *) (buf + offset);
+   report = (void *) (header + 1);
+
+   switch (header->type) {
+   case DRM_I915_PERF_RECORD_OA_REPORT_LOST:
+   break;
+   case DRM_I915_PERF_RECORD_SAMPLE:
+   if (first_timestamp == 0)
+   first_timestamp = report[1];
+   last_timestamp = report[1];
+
+   previous_tick_per_period = 
tick_per_period;
+
+   if (n_periodic_reports > 0 &&
+   oa_report_is_periodic(oa_exponent, 
report)) {
+   tick_per_period =
+   
oa_reports_tick_per_period(last_periodic_report,
+   
   report);
+
+   if 
(!double_value_within(tick_per_period,
+
previous_tick_per_period, 5))
+   igt_debug("clock 
change!\n");
+
+   igt_debug(" > report ts=%u"
+ " 
ts_delta_last_periodic=%8u is_timer=%i ctx_id=%8x gpu_ticks=%u 
nb_periodic=%u\n",
+ report[1],
+ report[1] - 
last_periodic_report[1],
+ 
oa_report_is_periodic(oa_exponent, report),
+ 
oa_report_get_ctx_id(report),
+ report[3] - 
last_periodic_report[3],
+ n_periodic_reports);
+
+   memcpy(last_periodic_report, 
report,
+  
sizeof(last_periodic_report));
+

[Intel-gfx] [PATCH v2 04/10] tests/perf: rc6: try to guess when rc6 is disabled

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index bc5ea133..1b441601 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -3445,6 +3445,17 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
+static bool
+rc6_enabled(void)
+{
+   char *rc6_status = read_debugfs_record(drm_fd, "i915_drpc_info",
+  "RC6 Enabled");
+   bool enabled = strcmp(rc6_status, "yes") == 0;
+
+   free(rc6_status);
+   return enabled;
+}
+
 static void
 test_rc6_disable(void)
 {
@@ -3464,6 +3475,8 @@ test_rc6_disable(void)
};
uint64_t n_events_start, n_events_end;
 
+   igt_skip_on(!rc6_enabled());
+
stream_fd = __perf_open(drm_fd, ¶m);
 
n_events_start = read_debugfs_u64_record(drm_fd, "i915_drpc_info",
-- 
2.14.1

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[Intel-gfx] [PATCH v2 10/10] tests/perf: add Geminilake support

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index 2f492679..1462a3fd 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1124,6 +1124,9 @@ init_sys_info(void)
return false;
}
timestamp_frequency = 1200;
+   } else if (IS_GEMINILAKE(devid)) {
+   test_set_uuid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
+   timestamp_frequency = 1920;
} else {
igt_debug("unsupported GT\n");
return false;
-- 
2.14.1

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[Intel-gfx] [PATCH v2 09/10] tests/perf: add Kabylake support

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index 4a2cc38d..2f492679 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -,8 +,23 @@ init_sys_info(void)
} else if (IS_BROXTON(devid)) {
test_set_uuid = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
timestamp_frequency = 1920;
-   } else
+   } else if (IS_KABYLAKE(devid)) {
+   switch (intel_gt(devid)) {
+   case 1:
+   test_set_uuid = 
"baa3c7e4-52b6-4b85-801e-465a94b746dd";
+   break;
+   case 2:
+   test_set_uuid = 
"f1792f32-6db2-4b50-b4b2-557128f1688d";
+   break;
+   default:
+   igt_debug("unsupported Kabylake GT size\n");
+   return false;
+   }
+   timestamp_frequency = 1200;
+   } else {
+   igt_debug("unsupported GT\n");
return false;
+   }
 
gp.param = I915_PARAM_EU_TOTAL;
gp.value = &n_eus;
-- 
2.14.1

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[Intel-gfx] [PATCH v2 08/10] tests/perf: make buffer-fill more reliable

2017-08-23 Thread Lionel Landwerlin

Filling rate of the buffer must discard context switch reports as they
do not depend upon the periodicity, instead they're a factor on the
amount of different applications concurrently running on the system.

Signed-off-by: Lionel Landwerlin 
Tested-by: Matthew Auld 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 120 ++-
 1 file changed, 103 insertions(+), 17 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 299706cd..4a2cc38d 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2687,22 +2687,30 @@ test_buffer_fill(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
+   struct drm_i915_perf_record_header *header;
int buf_size = 65536 * (256 + sizeof(struct 
drm_i915_perf_record_header));
uint8_t *buf = malloc(buf_size);
+   int len;
size_t oa_buf_size = 16 * 1024 * 1024;
size_t report_size = oa_formats[test_oa_format].size;
int n_full_oa_reports = oa_buf_size / report_size;
uint64_t fill_duration = n_full_oa_reports * oa_period;
 
+   load_helper_init();
+   load_helper_run(HIGH);
+
igt_assert(fill_duration < 10);
 
stream_fd = __perf_open(drm_fd, ¶m);
 
for (int i = 0; i < 5; i++) {
-   struct drm_i915_perf_record_header *header;
bool overflow_seen;
-   int offset = 0;
-   int len;
+   uint32_t n_periodic_reports;
+   uint32_t first_timestamp = 0, last_timestamp = 0;
+   uint32_t last_periodic_report[64];
+   double tick_per_period;
+
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
 
nanosleep(&(struct timespec){ .tv_sec = 0,
  .tv_nsec = fill_duration * 1.25 },
@@ -2714,7 +2722,7 @@ test_buffer_fill(void)
igt_assert_neq(len, -1);
 
overflow_seen = false;
-   for (offset = 0; offset < len; offset += header->size) {
+   for (int offset = 0; offset < len; offset += header->size) {
header = (void *)(buf + offset);
 
if (header->type == DRM_I915_PERF_RECORD_OA_BUFFER_LOST)
@@ -2723,32 +2731,110 @@ test_buffer_fill(void)
 
igt_assert_eq(overflow_seen, true);
 
+   do_ioctl(stream_fd, I915_PERF_IOCTL_DISABLE, 0);
+
+   igt_debug("fill_duration = %luns, oa_exponent = %u\n",
+ fill_duration, oa_exponent);
+
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+
nanosleep(&(struct timespec){ .tv_sec = 0,
- .tv_nsec = fill_duration / 2 },
- NULL);
+   .tv_nsec = fill_duration / 2 },
+   NULL);
 
-   while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == 
EINTR)
-   ;
+   n_periodic_reports = 0;
 
-   igt_assert_neq(len, -1);
+   /* Because of the race condition between notification of new
+* reports and reports landing in memory, we need to rely on
+* timestamps to figure whether we've read enough of them.
+*/
+   while (((last_timestamp - first_timestamp) * oa_period) < 
(fill_duration / 2)) {
 
-   igt_assert(len > report_size * n_full_oa_reports * 0.45);
-   igt_assert(len < report_size * n_full_oa_reports * 0.55);
+   igt_debug("dts=%u elapsed=%lu duration=%lu\n",
+ last_timestamp - first_timestamp,
+ (last_timestamp - first_timestamp) * 
oa_period,
+ fill_duration / 2);
 
-   overflow_seen = false;
-   for (offset = 0; offset < len; offset += header->size) {
-   header = (void *)(buf + offset);
+   while ((len = read(stream_fd, buf, buf_size)) == -1 && 
errno == EINTR)
+   ;
 
-   if (header->type == DRM_I915_PERF_RECORD_OA_BUFFER_LOST)
-   overflow_seen = true;
+   igt_assert_neq(len, -1);
+
+   for (int offset = 0; offset < len; offset += 
header->size) {
+   uint32_t *report;
+   double previous_tick_per_period;
+
+   header = (void *) (buf + offset);
+   report = (void *) (header + 1);
+
+   switch (header->type) {
+   case DRM_I915_PERF_RECORD_OA_REPORT_LOST:
+   igt_debug("report loss, trying 
again\n");
+

[Intel-gfx] [PATCH v2 03/10] tests/perf: update max buffer size for reading reports

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 5058315c..bc5ea133 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1280,9 +1280,7 @@ read_2_oa_reports(int format_id,
/* Note: we allocate a large buffer so that each read() iteration
 * should scrape *all* pending records.
 *
-* The largest buffer the OA unit supports is 16MB and the smallest
-* OA report format is 64bytes allowing up to 262144 reports to
-* be buffered.
+* The largest buffer the OA unit supports is 16MB.
 *
 * Being sure we are fetching all buffered reports allows us to
 * potentially throw away / skip all reports whenever we see
@@ -1295,7 +1293,8 @@ read_2_oa_reports(int format_id,
 * to indicate that the OA unit may be over taxed if lots of reports
 * are being lost.
 */
-   int buf_size = 262144 * (64 + sizeof(struct 
drm_i915_perf_record_header));
+   int max_reports = (16 * 1024 * 1024) / format_size;
+   int buf_size = sample_size * max_reports * 1.5;
uint8_t *buf = malloc(buf_size);
int n = 0;
 
@@ -1307,6 +1306,7 @@ read_2_oa_reports(int format_id,
;
 
igt_assert(len > 0);
+   igt_debug("read %d bytes\n", (int)len);
 
for (size_t offset = 0; offset < len; offset += header->size) {
const uint32_t *report;
-- 
2.14.1

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[Intel-gfx] [PATCH v2 06/10] tests/perf: rework oa-exponent test

2017-08-23 Thread Lionel Landwerlin

New issues that were discovered while making the tests work on Gen8+ :

 - we need to measure timings between periodic reports and discard all
   other kind of reports

 - it seems periodicity of the reports can be affected outside of RC6
   (frequency change), we can detect this by looking at the amount of
   clock cycles per timestamp deltas

v2: Drop unused frequency related bits (Matthew)

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 734 ---
 1 file changed, 600 insertions(+), 134 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index b7deb9b2..d9afa494 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -306,6 +307,25 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static bool
+timestamp_delta_within(uint32_t delta,
+  uint32_t expected_delta,
+  uint32_t margin)
+{
+   return delta >= (expected_delta - margin) &&
+  delta <= (expected_delta + margin);
+}
+
+static bool
+double_value_within(double value,
+   double expected,
+   double percent_margin)
+{
+   return value >= (expected - expected * percent_margin / 100.0) &&
+  value <= (expected + expected * percent_margin / 100.0);
+
+}
+
 static void
 __perf_close(int fd)
 {
@@ -472,6 +492,20 @@ gen8_read_report_ticks(uint32_t *report, enum 
drm_i915_oa_format format)
return report[3];
 }
 
+static void
+gen8_read_report_clock_ratios(uint32_t *report,
+ uint32_t *slice_freq_mhz,
+ uint32_t *unslice_freq_mhz)
+{
+   uint32_t unslice_freq = report[0] & 0x1ff;
+   uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+   uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+   uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+   *slice_freq_mhz = (slice_freq * 1) / 1000;
+   *unslice_freq_mhz = (unslice_freq * 1) / 1000;
+}
+
 static const char *
 gen8_read_report_reason(const uint32_t *report)
 {
@@ -494,29 +528,6 @@ gen8_read_report_reason(const uint32_t *report)
return "unknown";
 }
 
-static bool
-oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
-{
-   if (IS_HASWELL(devid)) {
-   /* For Haswell we don't have a documented report reason field
-* (though empirically report[0] bit 10 does seem to correlate
-* with a timer trigger reason) so we instead infer which
-* reports are timer triggered by checking if the least
-* significant bits are zero and the exponent bit is set.
-*/
-   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
-
-   if ((report[1] & oa_exponent_mask) != (1 << oa_exponent))
-   return true;
-   } else {
-   if ((report[0] >> OAREPORT_REASON_SHIFT) &
-   OAREPORT_REASON_TIMER)
-   return true;
-   }
-
-   return false;
-}
-
 static uint64_t
 timebase_scale(uint32_t u32_delta)
 {
@@ -563,6 +574,29 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   /* For Haswell we don't have a documented report reason field
+* (though empirically report[0] bit 10 does seem to correlate
+* with a timer trigger reason) so we instead infer which
+* reports are timer triggered by checking if the least
+* significant bits are zero and the exponent bit is set.
+*/
+   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
+
+   if ((report[1] & oa_exponent_mask) == (1 << oa_exponent))
+   return true;
+   } else {
+   if ((report[0] >> OAREPORT_REASON_SHIFT) &
+   OAREPORT_REASON_TIMER)
+   return true;
+   }
+
+   return false;
+}
+
 static bool
 oa_report_ctx_is_valid(uint32_t *report)
 {
@@ -578,6 +612,128 @@ oa_report_ctx_is_valid(uint32_t *report)
igt_assert(!"reached");
 }
 
+static uint32_t
+oa_report_get_ctx_id(uint32_t *report)
+{
+   if (!oa_report_ctx_is_valid(report))
+   return 0x;
+   return report[2];
+}
+
+static double
+oa_reports_tick_per_period(uint32_t *report0, uint32_t *report1)
+{
+   if (intel_gen(devid) < 8)
+   return 0.0;
+
+   /* Measure the number GPU tick delta to timestamp delta. */
+   return (double) (report1[3] - report0[3

Re: [Intel-gfx] [PATCH v14 1/7] drm/i915/gvt: Add framebuffer decoder support

2017-08-23 Thread Zhenyu Wang

On 2017.08.18 18:21:30 +0800, Tina Zhang wrote:
> This patch is to introduce the framebuffer decoder which can decode guest
> OS's framebuffer information, including primary, cursor and sprite plane.
> 
> v14:
> - refine pixel format table. (Zhenyu)
> 
> v9:
> - move drm format change to a separate patch. (Xiaoguang)
> 
> v8:
> - fix a bug in decoding primary plane. (Tina)
> 
> v7:
> - refine framebuffer decoder code. (Zhenyu)
> 
> Signed-off-by: Tina Zhang 
> Cc: Zhenyu Wang 
>

> +static struct pixel_format bdw_pixel_formats[] = {
> + {DRM_FORMAT_C8, 8, "8-bit Indexed"},
> + {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
> + {DRM_FORMAT_XRGB, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
> + {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
> +
> + {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
> + {DRM_FORMAT_XBGR, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
> +
> + /* non-supported format has bpp default to 0 */
> + {0, 0, NULL},
> +};
> +
> +static struct pixel_format skl_pixel_formats[] = {
> + {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
> + {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
> + {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
> + {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
> +
> + {DRM_FORMAT_C8, 8, "8-bit Indexed"},
> + {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
> + {DRM_FORMAT_ABGR, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
> + {DRM_FORMAT_XBGR, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
> +
> + {DRM_FORMAT_ARGB, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
> + {DRM_FORMAT_XRGB, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
> + {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
> + {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
> +
> + /* non-supported format has bpp default to 0 */
> + {0, 0, NULL},
> +};

What about KBL support of this? If not fully supported now, need to set
proper state at "probe" ioctl time.

-- 
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT

2017-08-23 Thread Joonas Lahtinen

On Tue, 2017-08-22 at 12:05 +0100, Chris Wilson wrote:
> By using drm_gem_flink/drm_gem_open on an object using the same fd, it
> is possible for a client to create multiple handles pointing to the same
> object (tied to the same contexts and VMA), as exemplified by
> igt::gem_handle_to_libdrm_bo(). Since this duplication has been possible
> since forever, we cannot assume that the handle:(fpriv, object) is
> unique and so must handle the multiple users of a single VMA.
> 
> Testcase: igt/gem_close
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
> Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> Signed-off-by: Chris Wilson 
> Cc: Tvrtko Ursulin 
> Cc: Joonas Lahtinen 



> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
>   goto err_obj;
>   }
>  
> + vma->open_count++;
>   list_add(&lut->obj_link, &obj->lut_list);

This code maybe should be in i915_gem.c as "i915_gem_object_add_lut" or
something.

> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -59,6 +59,7 @@ struct i915_vma {
>   u32 fence_size;
>   u32 fence_alignment;
>  
> + unsigned int open_count;
>   unsigned int flags;

Kerneldocs.

Regards, Joonas
-- 
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Open Source Technology Center
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[Intel-gfx] Merging iosf_mbi patches via the drm-tip tree

2017-08-23 Thread Imre Deak

Hi Thomas et al,

would it be ok to merge patch [1] - which contains changes in the
iosf_mbi code - via the drm-tip tree? It's part of patchset [2] from
Hans.

Thanks,
Imre

[1]
https://lists.freedesktop.org/archives/intel-gfx/2017-August/135991.html
[2]
https://lists.freedesktop.org/archives/intel-gfx/2017-August/135989.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT

2017-08-23 Thread Chris Wilson

Quoting Joonas Lahtinen (2017-08-23 11:05:18)
> On Tue, 2017-08-22 at 12:05 +0100, Chris Wilson wrote:
> > By using drm_gem_flink/drm_gem_open on an object using the same fd, it
> > is possible for a client to create multiple handles pointing to the same
> > object (tied to the same contexts and VMA), as exemplified by
> > igt::gem_handle_to_libdrm_bo(). Since this duplication has been possible
> > since forever, we cannot assume that the handle:(fpriv, object) is
> > unique and so must handle the multiple users of a single VMA.
> > 
> > Testcase: igt/gem_close
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
> > Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > Cc: Joonas Lahtinen 
> 
> 
> 
> > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > @@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
> >   goto err_obj;
> >   }
> >  
> > + vma->open_count++;
> >   list_add(&lut->obj_link, &obj->lut_list);
> 
> This code maybe should be in i915_gem.c as "i915_gem_object_add_lut" or
> something.

I disagree. It's very much tied to being an execbuf only interaction,
that obj/ctx/handle.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm: Add retries for dp dual mode read

2017-08-23 Thread Jani Nikula

On Tue, 22 Aug 2017, Shashank Sharma  wrote:
> From the CI builds, its been observed that during a driver
> reload/insert, dp dual mode read function sometimes fails to
> read from dual mode devices (like LSPCON) over i2c-over-aux
> channel.
>
> This patch:
> - adds some delay and few retries, allowing a scope for these
>   devices to settle down and respond.
> - changes one error log's level from ERROR->DEBUG as we want
>   to call it an error only after all the retries are exhausted.
>
> Cc: Ville Syrjala 
> Cc: Imre Deak 
> Signed-off-by: Shashank Sharma 
> ---
>  drivers/gpu/drm/drm_dp_dual_mode_helper.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c 
> b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
> index 80e62f6..13f67a36 100644
> --- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
> +++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
> @@ -75,8 +75,15 @@ ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter,
>   },
>   };
>   int ret;
> + int retry;
> +
> + for (retry = 5; ; ) {

As I said, I think the paradigm for loop (i = 0; i < N; i++) is always
more obvious and faster for humans to parse.

BR,
Jani.

> + ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
> + if (ret > 0 || !retry--)
> + break;
> + usleep_range(500, 1000);
> + }
>  
> - ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
>   if (ret < 0)
>   return ret;
>   if (ret != ARRAY_SIZE(msgs))
> @@ -420,7 +427,7 @@ int drm_lspcon_get_mode(struct i2c_adapter *adapter,
>   ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_LSPCON_CURRENT_MODE,
>   &data, sizeof(data));
>   if (ret < 0) {
> - DRM_ERROR("LSPCON read(0x80, 0x41) failed\n");
> + DRM_DEBUG_KMS("LSPCON read(0x80, 0x41) failed\n");
>   return -EFAULT;
>   }

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH] drm/i915: Expose a wakeref debugfs to disable (i915) runtime pm

2017-08-23 Thread Chris Wilson

Some igt do nothing more active than peek at buffers through a gtt mmap.
The pagefault into the GTT wakes the device up, but it will promptly
autosuspend and zap the GTT mmap, forcing the cycle to repeat
continuously. This makes those tests much, much slower than expected as
every GTT access becomes a page-fault (and that is magnified by the
slow devices also being unable to use WC updates of the GTT).

Whilst real userspace may fall into the same trap, we hold wakerefs
while rendering and while the display is active so all in likelihood the
device will be kept awake by activity during the access; and we strongly
discourage userspace from using GTT for performance reasons anyway. So
hopefully there is no pressing issue that requires a proper fix, and not
just an opt-out for igt!

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 48572b157222..ba6dfb145e90 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4671,6 +4671,24 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_wakeref_open(struct inode *inode, struct file *file)
+{
+   intel_runtime_pm_get(inode->i_private);
+   return 0;
+}
+
+static int i915_wakeref_release(struct inode *inode, struct file *file)
+{
+   intel_runtime_pm_put(inode->i_private);
+   return 0;
+}
+
+static const struct file_operations i915_wakeref_fops = {
+   .owner = THIS_MODULE,
+   .open = i915_wakeref_open,
+   .release = i915_wakeref_release,
+};
+
 static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
struct drm_i915_private *dev_priv = inode->i_private;
@@ -4867,6 +4885,12 @@ int i915_debugfs_register(struct drm_i915_private 
*dev_priv)
struct dentry *ent;
int ret, i;
 
+   ent = debugfs_create_file("i915_wakeref_user", S_IRUSR,
+ minor->debugfs_root, to_i915(minor->dev),
+ &i915_wakeref_fops);
+   if (!ent)
+   return -ENOMEM;
+
ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
  minor->debugfs_root, to_i915(minor->dev),
  &i915_forcewake_fops);
-- 
2.14.1

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[Intel-gfx] [PATCH v2 1/2] drm: Add retries for dp dual mode read

2017-08-23 Thread Shashank Sharma

From the CI builds, its been observed that during a driver
reload/insert, dp dual mode read function sometimes fails to
read from dual mode devices (like LSPCON) over i2c-over-aux
channel.

This patch:
- adds some delay and few retries, allowing a scope for these
  devices to settle down and respond.
- changes one error log's level from ERROR->DEBUG as we want
  to call it an error only after all the retries are exhausted.

V2: Addressed review comments from Jani (for loop for retry)

Cc: Ville Syrjala 
Cc: Imre Deak 
Cc: Jani Nikula 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_dp_dual_mode_helper.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c 
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index 80e62f6..09bf962 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -75,8 +75,16 @@ ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter,
},
};
int ret;
+   int retry;
+
+   for (retry = 0; retry < 6; retry++) {
+   if (retry)
+   usleep_range(500, 1000);
+   ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
+   if (ret > 0)
+   break;
+   }
 
-   ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
return ret;
if (ret != ARRAY_SIZE(msgs))
@@ -420,7 +428,7 @@ int drm_lspcon_get_mode(struct i2c_adapter *adapter,
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_LSPCON_CURRENT_MODE,
&data, sizeof(data));
if (ret < 0) {
-   DRM_ERROR("LSPCON read(0x80, 0x41) failed\n");
+   DRM_DEBUG_KMS("LSPCON read(0x80, 0x41) failed\n");
return -EFAULT;
}
 
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose a wakeref debugfs to disable (i915) runtime pm

2017-08-23 Thread Patchwork

== Series Details ==

Series: drm/i915: Expose a wakeref debugfs to disable (i915) runtime pm
URL   : https://patchwork.freedesktop.org/series/29207/
State : success

== Summary ==

Series 29207v1 drm/i915: Expose a wakeref debugfs to disable (i915) runtime pm
https://patchwork.freedesktop.org/api/1.0/series/29207/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:452s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:437s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:362s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:567s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:527s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:432s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:602s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:454s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:515s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:600s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:529s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:484s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:478s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:403s

ebd0ddf26a92d346469b3eb6ca9917793e5542b9 drm-tip: 2017y-08m-23d-09h-28m-47s UTC 
integration manifest
4b64169d6e46 drm/i915: Expose a wakeref debugfs to disable (i915) runtime pm

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5474/
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[Intel-gfx] [PATCH igt] igt/gem_fence_thresh: Use streaming reads for verify

2017-08-23 Thread Chris Wilson

At the moment, the verify tests use an extremely brutal write-read of
every dword, degrading performance to UC. If we break those up into
cachelines, we can do a wcb write/read at a time instead, roughly 8x
faster. We lose the accuracy of the forced wcb flushes around every dword,
but we are retaining the overall behaviour of checking reads following
writes instead. To compensate, we do check that a single dword write/read
before using wcb aligned accesses.

Signed-off-by: Chris Wilson 
---
 tests/gem_fence_thrash.c | 116 +--
 1 file changed, 101 insertions(+), 15 deletions(-)

diff --git a/tests/gem_fence_thrash.c b/tests/gem_fence_thrash.c
index 52095f26..3e1edb73 100644
--- a/tests/gem_fence_thrash.c
+++ b/tests/gem_fence_thrash.c
@@ -30,7 +30,6 @@
 #include "config.h"
 #endif
 
-#include "igt.h"
 #include 
 #include 
 #include 
@@ -43,6 +42,12 @@
 #include 
 #include "drm.h"
 
+#include "igt.h"
+#include "igt_x86.h"
+
+#define PAGE_SIZE 4096
+#define CACHELINE 64
+
 #define OBJECT_SIZE (128*1024) /* restricted to 1MiB alignment on i915 fences 
*/
 
 /* Before introduction of the LRU list for fences, allocation of a fence for a 
page
@@ -104,15 +109,78 @@ bo_copy (void *_arg)
return NULL;
 }
 
+#if defined(__x86_64__) && !defined(__clang__)
+#define MOVNT 512
+
+#pragma GCC push_options
+#pragma GCC target("sse4.1")
+
+#include 
+__attribute__((noinline))
+static void copy_wc_page(void *dst, void *src)
+{
+   if (igt_x86_features() & SSE4_1) {
+   __m128i *S = (__m128i *)src;
+   __m128i *D = (__m128i *)dst;
+
+   for (int i = 0; i < PAGE_SIZE/CACHELINE; i++) {
+   __m128i tmp[4];
+
+   tmp[0] = _mm_stream_load_si128(S++);
+   tmp[1] = _mm_stream_load_si128(S++);
+   tmp[2] = _mm_stream_load_si128(S++);
+   tmp[3] = _mm_stream_load_si128(S++);
+
+   _mm_store_si128(D++, tmp[0]);
+   _mm_store_si128(D++, tmp[1]);
+   _mm_store_si128(D++, tmp[2]);
+   _mm_store_si128(D++, tmp[3]);
+   }
+   } else
+   memcpy(dst, src, PAGE_SIZE);
+}
+static void copy_wc_cacheline(void *dst, void *src)
+{
+   if (igt_x86_features() & SSE4_1) {
+   __m128i *S = (__m128i *)src;
+   __m128i *D = (__m128i *)dst;
+   __m128i tmp[4];
+
+   tmp[0] = _mm_stream_load_si128(S++);
+   tmp[1] = _mm_stream_load_si128(S++);
+   tmp[2] = _mm_stream_load_si128(S++);
+   tmp[3] = _mm_stream_load_si128(S++);
+
+   _mm_store_si128(D++, tmp[0]);
+   _mm_store_si128(D++, tmp[1]);
+   _mm_store_si128(D++, tmp[2]);
+   _mm_store_si128(D++, tmp[3]);
+   } else
+   memcpy(dst, src, CACHELINE);
+}
+
+#pragma GCC pop_options
+
+#else
+static void copy_wc_page(void *dst, const void *src)
+{
+   memcpy(dst, src, PAGE_SIZE);
+}
+static void copy_wc_cacheline(void *dst, const void *src)
+{
+   memcpy(dst, src, CACHELINE);
+}
+#endif
+
 static void
 _bo_write_verify(struct test *t)
 {
int fd = t->fd;
int i, k;
uint32_t **s;
-   uint32_t v;
unsigned int dwords = OBJECT_SIZE >> 2;
const char *tile_str[] = { "none", "x", "y" };
+   uint32_t tmp[PAGE_SIZE/sizeof(uint32_t)];
 
igt_assert(t->tiling >= 0 && t->tiling <= I915_TILING_Y);
igt_assert_lt(0, t->num_surfaces);
@@ -124,21 +192,39 @@ _bo_write_verify(struct test *t)
s[k] = bo_create(fd, t->tiling);
 
for (k = 0; k < t->num_surfaces; k++) {
-   volatile uint32_t *a = s[k];
-
-   for (i = 0; i < dwords; i++) {
-   a[i] = i;
-   v = a[i];
-   igt_assert_f(v == i,
-"tiling %s: write failed at %d (%x)\n",
-tile_str[t->tiling], i, v);
+   uint32_t *a = s[k];
+
+   a[0] = 0xdeadbeef;
+   igt_assert_f(a[0] == 0xdeadbeef,
+"tiling %s: write failed at start (%x)\n",
+tile_str[t->tiling], a[0]);
+
+   a[dwords - 1] = 0xc0ffee;
+   igt_assert_f(a[dwords - 1] == 0xc0ffee,
+"tiling %s: write failed at end (%x)\n",
+tile_str[t->tiling], a[dwords - 1]);
+
+   for (i = 0; i < dwords; i += CACHELINE/sizeof(uint32_t)) {
+   for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
+   a[i + j] = ~(i + j);
+
+   copy_wc_cacheline(tmp, a + i);
+   for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
+   igt_assert_f(tmp[j] == ~(i+ j),
+

[Intel-gfx] ✓ Fi.CI.BAT: success for Add retries for dp dual mode reads (rev2)

2017-08-23 Thread Patchwork

== Series Details ==

Series: Add retries for dp dual mode reads (rev2)
URL   : https://patchwork.freedesktop.org/series/29155/
State : success

== Summary ==

Series 29155v2 Add retries for dp dual mode reads
https://patchwork.freedesktop.org/api/1.0/series/29155/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:442s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:366s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:563s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:533s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:532s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:530s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:439s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:613s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:450s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:428s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:559s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:607s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:639s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:479s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:494s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:449s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:490s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:554s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:410s
fi-pnv-d510 failed to connect after reboot

ebd0ddf26a92d346469b3eb6ca9917793e5542b9 drm-tip: 2017y-08m-23d-09h-28m-47s UTC 
integration manifest
444e42d7e599 drm/i915: Don't give up waiting on INVALID_MODE
89db7936ed6a drm: Add retries for dp dual mode read

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5475/
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Re: [Intel-gfx] [PATCH] drm/doc: Document ioctl errno value patterns

2017-08-23 Thread Daniel Vetter

On Fri, Aug 18, 2017 at 07:43:28PM +0200, Daniel Vetter wrote:
> We're not super-consistent about these, but I think it's worth to
> document at least the commmon patterns.
> 
> v2:
> - Add a not about ENOTTY (it's just a confusing name, but used
> exactly what it's meant for in DRM) (Chris).
> - Unconfuse the text for ENODEV (Daniel)
> - Move text undert the IOCTL heading (Chris).
> - typos
> 
> Cc: Daniel Stone 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: "Zhang, Tina" 
> Reviewed-by: Chris Wilson 
> Signed-off-by: Daniel Vetter 

Pushed to drm-misc-next.
-Daniel

> ---
>  Documentation/gpu/drm-uapi.rst | 55 
> ++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst
> index 679373b4a03f..a2214cc1f821 100644
> --- a/Documentation/gpu/drm-uapi.rst
> +++ b/Documentation/gpu/drm-uapi.rst
> @@ -168,6 +168,61 @@ IOCTL Support on Device Nodes
>  .. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
> :doc: driver specific ioctls
>  
> +Recommended IOCTL Return Values
> +---
> +
> +In theory a driver's IOCTL callback is only allowed to return very few error
> +codes. In practice it's good to abuse a few more. This section documents 
> common
> +practice within the DRM subsystem:
> +
> +ENOENT:
> +Strictly this should only be used when a file doesn't exist e.g. when
> +calling the open() syscall. We reuse that to signal any kind of 
> object
> +lookup failure, e.g. for unknown GEM buffer object handles, unknown 
> KMS
> +object handles and similar cases.
> +
> +ENOSPC:
> +Some drivers use this to differentiate "out of kernel memory" from 
> "out
> +of VRAM". Sometimes also applies to other limited gpu resources used 
> for
> +rendering (e.g. when you have a special limited compression buffer).
> +Sometimes resource allocation/reservation issues in command 
> submission
> +IOCTLs are also signalled through EDEADLK.
> +
> +Simply running out of kernel/system memory is signalled through 
> ENOMEM.
> +
> +EPERM/EACCESS:
> +Returned for an operation that is valid, but needs more privileges.
> +E.g. root-only or much more common, DRM master-only operations return
> +this when when called by unpriviledged clients. There's no clear
> +difference between EACCESS and EPERM.
> +
> +ENODEV:
> +Feature (like PRIME, modesetting, GEM) is not supported by the 
> driver.
> +
> +ENXIO:
> +Remote failure, either a hardware transaction (like i2c), but also 
> used
> +when the exporting driver of a shared dma-buf or fence doesn't 
> support a
> +feature needed.
> +
> +EINTR:
> +DRM drivers assume that userspace restarts all IOCTLs. Any DRM IOCTL 
> can
> +return EINTR and in such a case should be restarted with the IOCTL
> +parameters left unchanged.
> +
> +EIO:
> +The GPU died and couldn't be resurrected through a reset. Modesetting
> +hardware failures are signalled through the "link status" connector
> +property.
> +
> +EINVAL:
> +Catch-all for anything that is an invalid argument combination which
> +cannot work.
> +
> +IOCTL also use other error codes like ETIME, EFAULT, EBUSY, ENOTTY but their
> +usage is in line with the common meanings. The above list tries to just 
> document
> +DRM specific patterns. Note that ENOTTY has the slightly unintuitive meaning 
> of
> +"this IOCTL does not exist", and is used exactly as such in DRM.
> +
>  .. kernel-doc:: include/drm/drm_ioctl.h
> :internal:
>  
> -- 
> 2.13.3
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/gem_fence_thresh: Use streaming reads for verify

2017-08-23 Thread Patchwork

== Series Details ==

Series: igt/gem_fence_thresh: Use streaming reads for verify
URL   : https://patchwork.freedesktop.org/series/29208/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2994
ebd0ddf26a92 drm-tip: 2017y-08m-23d-09h-28m-47s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770)
Subgroup basic-flip-before-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:440s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:567s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:525s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:531s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:520s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:617s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:597s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:528s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:483s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:488s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:404s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_85/
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[Intel-gfx] [PATCH i-g-t] lib/core: Use igt_info instead of printf

2017-08-23 Thread Daniel Vetter

igt_info doesn't add anything when printing to stdout, but so looks
the same. But it has the upside of appending the lines also to the igt
crashdump log, where I especially want the backtraces. Atm they're the
only thing that doesn't end up in there, which is a bit confusing.

While at it also convert the other lines - the test summary usually
doesn't make it since the test fails before that, and the version line
tends to scroll off the crashdump.

Signed-off-by: Daniel Vetter 
---
 lib/igt_core.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/lib/igt_core.c b/lib/igt_core.c
index 9eb99eda0244..58d64dc2d466 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -588,9 +588,9 @@ static void print_version(void)
 
uname(&uts);
 
-   fprintf(stdout, "IGT-Version: %s-%s (%s) (%s: %s %s)\n", 
PACKAGE_VERSION,
-   IGT_GIT_SHA1, TARGET_CPU_PLATFORM,
-   uts.sysname, uts.release, uts.machine);
+   igt_info("IGT-Version: %s-%s (%s) (%s: %s %s)\n", PACKAGE_VERSION,
+IGT_GIT_SHA1, TARGET_CPU_PLATFORM,
+uts.sysname, uts.release, uts.machine);
 }
 
 static void print_usage(const char *help_str, bool output_on_stderr)
@@ -1028,10 +1028,10 @@ static void exit_subtest(const char *result)
struct timespec now;
 
gettime(&now);
-   printf("%sSubtest %s: %s (%.3fs)%s\n",
-  (!__igt_plain_output) ? "\x1b[1m" : "",
-  in_subtest, result, time_elapsed(&subtest_time, &now),
-  (!__igt_plain_output) ? "\x1b[0m" : "");
+   igt_info("%sSubtest %s: %s (%.3fs)%s\n",
+(!__igt_plain_output) ? "\x1b[1m" : "",
+in_subtest, result, time_elapsed(&subtest_time, &now),
+(!__igt_plain_output) ? "\x1b[0m" : "");
fflush(stdout);
 
in_subtest = NULL;
@@ -1216,7 +1216,7 @@ static void print_backtrace(void)
unw_context_t uc;
int stack_num = 0;
 
-   printf("Stack trace:\n");
+   igt_info("Stack trace:\n");
 
unw_getcontext(&uc);
unw_init_local(&cursor, &uc);
@@ -1227,8 +1227,8 @@ static void print_backtrace(void)
if (unw_get_proc_name(&cursor, name, 255, &off) < 0)
strcpy(name, "");
 
-   printf("  #%d [%s+0x%x]\n", stack_num++, name,
-  (unsigned int) off);
+   igt_info("  #%d [%s+0x%x]\n", stack_num++, name,
+(unsigned int) off);
}
 }
 
-- 
2.5.5

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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/core: Use igt_info instead of printf

2017-08-23 Thread Patchwork

== Series Details ==

Series: lib/core: Use igt_info instead of printf
URL   : https://patchwork.freedesktop.org/series/29210/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2995
2964b2f40295 drm-tip: 2017y-08m-23d-13h-11m-32s UTC integration manifest

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:437s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:553s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:530s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:521s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:616s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:451s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:429s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:602s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:604s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:528s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:486s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:447s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:487s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:546s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:412s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_86/
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[Intel-gfx] [PATCH igt] igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep

2017-08-23 Thread Chris Wilson

These tests are not intended to exercise runtime pm, but the device
going to sleep in the middle of these tests can significantly slow them
down as the GTT mmapping is torn down and must be rebuilt. This can be a
major nuisance if the device autosuspends many times a second.

These tests differ from typical applications as they are not doing any
rendering or utilizing the display which would ordinarily keep the
device awake.

Signed-off-by: Chris Wilson 
---
 tests/gem_fence_thrash.c | 17 +
 tests/gem_mmap_gtt.c | 15 ++-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/tests/gem_fence_thrash.c b/tests/gem_fence_thrash.c
index 3e1edb73..03e971aa 100644
--- a/tests/gem_fence_thrash.c
+++ b/tests/gem_fence_thrash.c
@@ -287,10 +287,27 @@ static int run_test(int threads_per_fence, void *f, int 
tiling,
return 0;
 }
 
+static int wakeref_open(int device)
+{
+   int dir, fd;
+
+   dir = igt_debugfs_dir(device);
+   fd = openat(dir, "i915_wakeref_user", O_RDONLY);
+   close(dir);
+
+   return fd;
+}
+
 igt_main
 {
igt_skip_on_simulation();
 
+   igt_fixture {
+   int fd = drm_open_driver(DRIVER_INTEL);
+   wakeref_open(fd);
+   close(fd);
+   }
+
igt_subtest("bo-write-verify-none")
igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) 
== 0);
 
diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c
index 61c08406..fc44cfb5 100644
--- a/tests/gem_mmap_gtt.c
+++ b/tests/gem_mmap_gtt.c
@@ -864,6 +864,17 @@ run_without_prefault(int fd,
igt_enable_prefault();
 }
 
+static int wakeref_open(int device)
+{
+   int dir, fd;
+
+   dir = igt_debugfs_dir(device);
+   fd = openat(dir, "i915_wakeref_user", O_RDONLY);
+   close(dir);
+
+   return fd;
+}
+
 int fd;
 
 igt_main
@@ -871,8 +882,10 @@ igt_main
if (igt_run_in_simulation())
OBJECT_SIZE = 1 * 1024 * 1024;
 
-   igt_fixture
+   igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
+   wakeref_open(fd);
+   }
 
igt_subtest("basic")
test_access(fd);
-- 
2.14.1

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Wire up shrinkctl->nr_scanned

2017-08-23 Thread Chris Wilson

Quoting Andrew Morton (2017-08-22 23:45:50)
> On Tue, 22 Aug 2017 14:53:25 +0100 Chris Wilson  
> wrote:
> 
> > shrink_slab() allows us to report back the number of objects we
> > successfully scanned (out of the target shrinkctl->nr_to_scan). As
> > report the number of pages owned by each GEM object as a separate item
> > to the shrinker, we cannot precisely control the number of shrinker
> > objects we scan on each pass; and indeed may free more than requested.
> > If we fail to tell the shrinker about the number of objects we process,
> > it will continue to hold a grudge against us as any objects left
> > unscanned are added to the next reclaim -- and so we will keep on
> > "unfairly" shrinking our own slab in comparison to other slabs.
> 
> It's unclear which tree this is against but I think I got it all fixed
> up.  Please check the changes to i915_gem_shrink().

My apologies, I wrote it against drm-tip for running against our CI. The
changes look fine, thank you.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: "Race-to-idle" on switching to the kernel context

2017-08-23 Thread David Weinehall

On Mon, Aug 21, 2017 at 12:48:03PM +0300, Mika Kuoppala wrote:
> Chris Wilson  writes:
> 
> > Quoting Chris Wilson (2017-08-21 10:28:16)
> >> Quoting Mika Kuoppala (2017-08-21 10:17:52)
> >> > Chris Wilson  writes:
> >> > 
> >> > > During suspend we want to flush out all active contexts and their
> >> > > rendering. To do so we queue a request from the kernel's context, once
> >> > > we know that request is done, we know the GPU is completely idle. To
> >> > > speed up that switch bump the GPU clocks.
> >> > >
> >> > > Switching to the kernel context prior to idling is also used to enforce
> >> > > a barrier before changing OA properties, and when evicting active
> >> > > rendering from the global GTT. All cases where we do want to
> >> > > race-to-idle.
> >> > >
> >> > > Signed-off-by: Chris Wilson 
> >> > > Cc: David Weinehall 
> >> > > ---
> >> > >  drivers/gpu/drm/i915/i915_gem_context.c | 11 ---
> >> > >  1 file changed, 8 insertions(+), 3 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> >> > > b/drivers/gpu/drm/i915/i915_gem_context.c
> >> > > index 58a2a44f88bd..ca1423ad2708 100644
> >> > > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> >> > > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> >> > > @@ -895,6 +895,7 @@ int i915_gem_switch_to_kernel_context(struct 
> >> > > drm_i915_private *dev_priv)
> >> > >  
> >> > >   for_each_engine(engine, dev_priv, id) {
> >> > >   struct drm_i915_gem_request *req;
> >> > > + bool active = false;
> >> > >   int ret;
> >> > >  
> >> > >   if (engine_has_kernel_context(engine))
> >> > > @@ -913,13 +914,17 @@ int i915_gem_switch_to_kernel_context(struct 
> >> > > drm_i915_private *dev_priv)
> >> > >   prev = i915_gem_active_raw(&tl->last_request,
> >> > >  
> >> > > &dev_priv->drm.struct_mutex);
> >> > >   if (prev)
> >> > > - 
> >> > > i915_sw_fence_await_sw_fence_gfp(&req->submit,
> >> > > -  
> >> > > &prev->submit,
> >> > > -  
> >> > > GFP_KERNEL);
> >> > > + active |= 
> >> > > i915_sw_fence_await_sw_fence_gfp(&req->submit,
> >> > > +  
> >> > >   &prev->submit,
> >> > > +  
> >> > >   GFP_KERNEL) > 0;
> >> > 
> >> > There is no point of kicking the clocks if we are the only request left?
> >> > 
> >> > Well logical as the request is empty, just pondering if the actual ctx
> >> > save/restore would finish quicker.
> >> 
> >> I was thinking if it was just the context save itself, it not would be
> >> enough of a difference to justify itself. Just gut feeling and not
> >> measured, I worry about the irony of boosting from idle just to idle.
> >
> > Hmm, or we could be more precise and just set the clocks high rather
> > than queue a task. The complication isn't worth it for just a single
> > callsite, but I am contemplating supplying boost/clocks information
> > along with the request.
> 
> For the purposes of suspend, I think the approach is simple and
> good enough.
> 
> Can David give a Tested-by?

Didn't notice this until now, but I'll give it a whirl.

> Reviewed-by: Mika Kuoppala 
> 
> > -Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep

2017-08-23 Thread Patchwork

== Series Details ==

Series: igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep
URL   : https://patchwork.freedesktop.org/series/29215/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2995
2964b2f40295 drm-tip: 2017y-08m-23d-13h-11m-32s UTC integration manifest

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:438s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:557s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:526s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:529s
fi-byt-n2820 total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:528s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:620s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:449s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:502s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:601s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:535s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:491s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:434s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:488s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:408s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_87/
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[Intel-gfx] [PATCH igt] igt/kms_hdmi_inject: Require /proc/asound before asserting

2017-08-23 Thread Chris Wilson

The subtest "inject-audio" tries to load an EDID and confirm that it is
being passed through to the audio driver (as an ELD). This cannot work
if the audio driver is not present, so skip instead.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102370
Signed-off-by: Chris Wilson 
---
 tests/kms_hdmi_inject.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/tests/kms_hdmi_inject.c b/tests/kms_hdmi_inject.c
index cb916ace..31d7d69f 100644
--- a/tests/kms_hdmi_inject.c
+++ b/tests/kms_hdmi_inject.c
@@ -23,6 +23,7 @@
  */
 
 #include 
+#include 
 #include "igt.h"
 
 #define HDISPLAY_4K3840
@@ -246,6 +247,12 @@ hdmi_inject_audio(int drm_fd, drmModeConnector *connector)
free(edid);
 }
 
+static bool has_proc_asound(void)
+{
+   struct stat st;
+   return stat("/proc/asound", &st) == 0;
+}
+
 igt_main
 {
int drm_fd;
@@ -263,8 +270,10 @@ igt_main
igt_subtest("inject-4k")
hdmi_inject_4k(drm_fd, connector);
 
-   igt_subtest("inject-audio")
+   igt_subtest("inject-audio") {
+   igt_require(has_proc_asound());
hdmi_inject_audio(drm_fd, connector);
+   }
 
igt_fixture {
drmModeFreeConnector(connector);
-- 
2.14.1

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Re: [Intel-gfx] [PATCH] drm/i915: "Race-to-idle" on switching to the kernel context

2017-08-23 Thread David Weinehall

On Fri, Aug 18, 2017 at 03:08:15PM +0100, Chris Wilson wrote:
> During suspend we want to flush out all active contexts and their
> rendering. To do so we queue a request from the kernel's context, once
> we know that request is done, we know the GPU is completely idle. To
> speed up that switch bump the GPU clocks.
> 
> Switching to the kernel context prior to idling is also used to enforce
> a barrier before changing OA properties, and when evicting active
> rendering from the global GTT. All cases where we do want to
> race-to-idle.
> 
> Signed-off-by: Chris Wilson 
> Cc: David Weinehall 

No statistically significant speedup on suspend in our typical
benchmark, but that one doesn't take into account systems in load--it
suspends from idle, and from the description it seems that this patch
would mostly affect systems with load.

But no regression either, so I'm fine with the patch.

Tested-by: David Weinehall 
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 58a2a44f88bd..ca1423ad2708 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -895,6 +895,7 @@ int i915_gem_switch_to_kernel_context(struct 
> drm_i915_private *dev_priv)
>  
>   for_each_engine(engine, dev_priv, id) {
>   struct drm_i915_gem_request *req;
> + bool active = false;
>   int ret;
>  
>   if (engine_has_kernel_context(engine))
> @@ -913,13 +914,17 @@ int i915_gem_switch_to_kernel_context(struct 
> drm_i915_private *dev_priv)
>   prev = i915_gem_active_raw(&tl->last_request,
>  &dev_priv->drm.struct_mutex);
>   if (prev)
> - i915_sw_fence_await_sw_fence_gfp(&req->submit,
> -  &prev->submit,
> -  GFP_KERNEL);
> + active |= 
> i915_sw_fence_await_sw_fence_gfp(&req->submit,
> +
> &prev->submit,
> +
> GFP_KERNEL) > 0;
>   }
>  
>   ret = i915_switch_context(req);
> +
> + if (active)
> + gen6_rps_boost(req, NULL);
>   i915_add_request(req);
> +
>   if (ret)
>   return ret;
>   }
> -- 
> 2.14.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: "Race-to-idle" on switching to the kernel context

2017-08-23 Thread Chris Wilson

Quoting David Weinehall (2017-08-23 15:54:13)
> On Fri, Aug 18, 2017 at 03:08:15PM +0100, Chris Wilson wrote:
> > During suspend we want to flush out all active contexts and their
> > rendering. To do so we queue a request from the kernel's context, once
> > we know that request is done, we know the GPU is completely idle. To
> > speed up that switch bump the GPU clocks.
> > 
> > Switching to the kernel context prior to idling is also used to enforce
> > a barrier before changing OA properties, and when evicting active
> > rendering from the global GTT. All cases where we do want to
> > race-to-idle.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: David Weinehall 
> 
> No statistically significant speedup on suspend in our typical
> benchmark, but that one doesn't take into account systems in load--it
> suspends from idle, and from the description it seems that this patch
> would mostly affect systems with load.

In terms of everything else, I doubt we ever are significantly waiting
for the GPU upon suspend, the user interface would finish showing its
"going to suspend" screen before starting the suspend, so its only going
to be background tasks still rendering to the gpu oblivious of the
incoming suspend. Rare -- I'm going to squirrel this patch away until we
have a need for it.

Thanks for the review and testing, and if you do come across a workload
which could benefit do let me know. It may well be that userspace isn't
as smart as I expect...
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] pm_rps: Extended testcases with checking PMINTRMSK register value

2017-08-23 Thread Daniel Vetter

On Tue, Aug 22, 2017 at 01:14:19PM +, Szwichtenberg, Radoslaw wrote:
> On Tue, 2017-08-22 at 13:33 +0100, Chris Wilson wrote:
> > Quoting Szwichtenberg, Radoslaw (2017-08-22 12:56:00)
> > > On Tue, 2017-08-22 at 01:31 +0300, Arkadiusz Hiler wrote:
> > > > On Mon, Aug 21, 2017 at 09:39:24PM +0200, Daniel Vetter wrote:
> > > > > On Mon, Aug 21, 2017 at 11:21:49AM +0100, Chris Wilson wrote:
> > > > > > Quoting Chris Wilson (2017-08-21 10:53:36)
> > > > > > > Quoting Arkadiusz Hiler (2017-08-21 10:42:25)
> > > > > > > > On Mon, Aug 21, 2017 at 08:05:58AM +, Dec, Katarzyna wrote:
> > > > > > > > > I understand we do not want to check registers in IGT tests.
> > > > > > > > > What
> > > > > > > > > about reading interrupt masks from debugfs
> > > > > > > > > (i915_frequency_info).
> > > > > > > > 
> > > > > > > > Hey Kasia
> > > > > > > > 
> > > > > > > > It would be pretty much the same thing, but instead of us 
> > > > > > > > reading
> > > > > > > > the
> > > > > > > > PMINTRMASK directly we would ask the kernel to do that on our
> > > > > > > > behalf.
> > > > > > > > 
> > > > > > > > That would just hide register read, not get rid of it.
> > > > > > > > 
> > > > > > > > 
> > > > > > > > I think you are missing the point. The idea is that we do not 
> > > > > > > > want
> > > > > > > > to
> > > > > > > > test details of in-kernel implementation, not ban the register
> > > > > > > > reads
> > > > > > > > completely.
> > > > > > > > 
> > > > > > > > Reading register directly, especially just to make sure that the
> > > > > > > > kernel
> > > > > > > > set something correctly is a good indicator that we are trying 
> > > > > > > > to
> > > > > > > > do
> > > > > > > > just that - test the internal details.
> > > > > > > > 
> > > > > > > > > Would that be better approach? You guys suggested to get
> > > > > > > > > interested
> > > > > > > > > in
> > > > > > > > > kselftests for having such checks, but I am afraid that it 
> > > > > > > > > could
> > > > > > > > > be
> > > > > > > > > too much job and we have too few hands to work.
> > > > > > > > 
> > > > > > > > How much of an effort would the kselftest be, since it seems 
> > > > > > > > that
> > > > > > > > you
> > > > > > > > did some
> > > > > > > > investigation already?
> > > > > > > 
> > > > > > > It doesn't even require a whole selftest, just something like
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > index 448e71af4772..e83b67fe0354 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > @@ -7733,7 +7733,8 @@ void intel_suspend_gt_powersave(struct
> > > > > > > drm_i915_private *dev_priv)
> > > > > > > if (cancel_delayed_work_sync(&dev_priv-
> > > > > > > >rps.autoenable_work))
> > > > > > > intel_runtime_pm_put(dev_priv);
> > > > > > >  
> > > > > > > -   /* gen6_rps_idle() will be called later to disable
> > > > > > > interrupts */
> > > > > > > +   WARN_ON(I915_READ(GEN6_PMINTRMSK) !=
> > > > > > > +   gen6_sanitize_rps_pm_mask(dev_priv, ~0));
> > > > > > >  }
> > > > > > 
> > > > > > Wrong spot. We actually need a call from
> > > > > > intel_runtime_pm_disable_interrupts.
> > > > > 
> > > > > Yeah, for consistency checks which are very closely tied to the
> > > > > implementation we tend to sprinkle WARN_ON all over the place. In some
> > > > > cases those checks are too expensive for production, then we add a
> > > > > compile-time-option to hide them (e.g. GEM_BUG_ON).
> > > > > 
> > > > > I chatted with Radek, and if I understand things correctly, the main
> > > > > value
> > > > > you derive from these is making sure a frankenstein port to an older
> > > > > kernel doesn't miss or miss-apply any critical patches. In-kernel
> > > > > consistency checks unfortunately don't really help with that, but we
> > > > > heavily rely on these for validation.
> > > > 
> > > > Having that stated on the mailing list from the beginning (e.g. in the
> > > > commit message or as one of the first replies) would help directing the
> > > > whole discussion on the right track and make us understand your needs
> > > > better.
> > > > 
> > > > I agree with Daniel's earlier statement that we should be very
> > > > (over)verbose about the changes we are making and purpose they are
> > > > serving.
> > > > 
> > > > > There's also examples of this (and again, they're very important)
> > > > > outside
> > > > > of i915, like kasan, lockdep (and maybe we'll even get kmemleak 
> > > > > somehow
> > > > > integrated into CI/igt eventually).
> > > > > 
> > > > > So still no idea what would be the best suggestion here for your team.
> > > > 
> > > > Kasia and Radek, can you elaborate a little more on the "frankenstein
> > > > port" and your use cases for such tests?
> > > > 
> > > > How is that comparable to backports to stable/LTS kernel branches?
> > > > 
> > > 
> >

[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/kms_hdmi_inject: Require /proc/asound before asserting

2017-08-23 Thread Patchwork

== Series Details ==

Series: igt/kms_hdmi_inject: Require /proc/asound before asserting
URL   : https://patchwork.freedesktop.org/series/29217/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2995
2964b2f40295 drm-tip: 2017y-08m-23d-13h-11m-32s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770)
Subgroup basic-flip-before-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770)

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:434s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:567s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:255s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:526s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:522s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:425s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:607s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:595s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:595s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:537s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:475s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:495s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:505s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:553s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:416s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_88/
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Re: [Intel-gfx] [PATCH igt] igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep

2017-08-23 Thread Daniel Vetter

On Wed, Aug 23, 2017 at 03:13:55PM +0100, Chris Wilson wrote:
> These tests are not intended to exercise runtime pm, but the device
> going to sleep in the middle of these tests can significantly slow them
> down as the GTT mmapping is torn down and must be rebuilt. This can be a
> major nuisance if the device autosuspends many times a second.
> 
> These tests differ from typical applications as they are not doing any
> rendering or utilizing the display which would ordinarily keep the
> device awake.
> 
> Signed-off-by: Chris Wilson 

Can we just disable rpm while the test is on? Or at least set the
autosuspend timer to something huge like 60s, plus exit handler ofc.

Not as neat uabi as a fd-based wakeref, but has the upside that it doesn't
require a new kernel. Since we just discussed igt compat in another thread
...

Maybe should even extract that into lib/ from pm_rpm.
-Daniel

> ---
>  tests/gem_fence_thrash.c | 17 +
>  tests/gem_mmap_gtt.c | 15 ++-
>  2 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/gem_fence_thrash.c b/tests/gem_fence_thrash.c
> index 3e1edb73..03e971aa 100644
> --- a/tests/gem_fence_thrash.c
> +++ b/tests/gem_fence_thrash.c
> @@ -287,10 +287,27 @@ static int run_test(int threads_per_fence, void *f, int 
> tiling,
>   return 0;
>  }
>  
> +static int wakeref_open(int device)
> +{
> + int dir, fd;
> +
> + dir = igt_debugfs_dir(device);
> + fd = openat(dir, "i915_wakeref_user", O_RDONLY);
> + close(dir);
> +
> + return fd;
> +}
> +
>  igt_main
>  {
>   igt_skip_on_simulation();
>  
> + igt_fixture {
> + int fd = drm_open_driver(DRIVER_INTEL);
> + wakeref_open(fd);
> + close(fd);
> + }
> +
>   igt_subtest("bo-write-verify-none")
>   igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) 
> == 0);
>  
> diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c
> index 61c08406..fc44cfb5 100644
> --- a/tests/gem_mmap_gtt.c
> +++ b/tests/gem_mmap_gtt.c
> @@ -864,6 +864,17 @@ run_without_prefault(int fd,
>   igt_enable_prefault();
>  }
>  
> +static int wakeref_open(int device)
> +{
> + int dir, fd;
> +
> + dir = igt_debugfs_dir(device);
> + fd = openat(dir, "i915_wakeref_user", O_RDONLY);
> + close(dir);
> +
> + return fd;
> +}
> +
>  int fd;
>  
>  igt_main
> @@ -871,8 +882,10 @@ igt_main
>   if (igt_run_in_simulation())
>   OBJECT_SIZE = 1 * 1024 * 1024;
>  
> - igt_fixture
> + igt_fixture {
>   fd = drm_open_driver(DRIVER_INTEL);
> + wakeref_open(fd);
> + }
>  
>   igt_subtest("basic")
>   test_access(fd);
> -- 
> 2.14.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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http://blog.ffwll.ch
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Re: [Intel-gfx] [maintainer-tools PATCH 30/30] qf: Use .dimrc to config and extend qf.

2017-08-23 Thread Daniel Vetter

On Tue, Aug 22, 2017 at 11:16:35AM -0700, Rodrigo Vivi wrote:
> On Tue, Aug 22, 2017 at 12:33 AM, Jani Nikula  wrote:
> > On Mon, 21 Aug 2017, Rodrigo Vivi  wrote:
> >> Soon we will need to extend qf for very specific
> >> usages of our internal maintenance and rebase bot.
> >>
> >> So instead of creating yet another config file
> >> let's use the existent one.
> >
> > I think I'd prefer a separate config file for qf.
> 
> hm.. I was here accepting this suggestion, but then I noticed our qf_help
> already referrence $DIM_PREFIX
> 
> so, if we change to .qfrc we will have to redefine this prefix while re-using
> dimrc we don't need any duplication.
> 
> what do you think?

I think encouraging people to have entirely separate public/internal trees
would be good. Maybe even add a warning if QF_PREFIX matches DIM_PREFIX.

The risk is that the rerere magic in dim could accidentally leak internal
stuff.

So +1 from me for going with .qfrc, and maybe for paranoia on top insist
that QF_PREFIX != DIM_PREFIX. I'm one of those idiots who does this wrong,
and it's not good :-)

Cheers, Daniel

> 
> >
> > BR,
> > Jani.
> >
> >>
> >> Cc: Daniel Vetter 
> >> Cc: Jani Nikula 
> >> Cc: Joonas Lahtinen 
> >> Signed-off-by: Rodrigo Vivi 
> >> ---
> >>  dimrc.sample |  9 -
> >>  qf   | 18 +++---
> >>  2 files changed, 23 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/dimrc.sample b/dimrc.sample
> >> index be7b99cb6b76..bbddecabd519 100644
> >> --- a/dimrc.sample
> >> +++ b/dimrc.sample
> >> @@ -1,4 +1,4 @@
> >> -# Sample configuration file for dim. Place this at $HOME/.dimrc or point
> >> +# Sample configuration file for dim and qf. Place this at $HOME/.dimrc or 
> >> point
> >>  # DIM_CONFIG environment variable to it.
> >>  #
> >>  # Defaults are in the comments below.
> >> @@ -20,3 +20,10 @@
> >>
> >>  # Command to run after dim apply
> >>  #DIM_POST_APPLY_ACTION=
> >> +
> >> +#
> >> +# qf
> >> +#
> >> +
> >> +# Quilt branch prefix
> >> +#QUILT_PREFIX=
> >> \ No newline at end of file
> >> diff --git a/qf b/qf
> >> index be234e72fa15..befdb2c15b5f 100755
> >> --- a/qf
> >> +++ b/qf
> >> @@ -26,12 +26,24 @@
> >>
> >>  # quilt git flow script
> >>
> >> -# config
> >> -QUILT_PREFIX=quilt/
> >> -
> >>  # fail on any goof-up
> >>  set -e
> >>
> >> +#
> >> +# User configuration. Set in environment or configuration file. See
> >> +# dimrc.sample for an example.
> >> +#
> >> +
> >> +# dim configuration file
> >> +DIM_CONFIG=${DIM_CONFIG:-$HOME/.dimrc}
> >> +if [ -r $DIM_CONFIG ]; then
> >> + # shellcheck source=/dev/null
> >> + . $DIM_CONFIG
> >> +fi
> >> +
> >> +# prefix for quilt branch
> >> +QUILT_PREFIX=${QUILT_PREFIX:-quilt/}
> >> +
> >>  function cd_toplevel
> >>  {
> >>   cd $(git rev-parse --show-toplevel)
> >
> > --
> > Jani Nikula, Intel Open Source Technology Center
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
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Re: [Intel-gfx] [PATCH igt] igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep

2017-08-23 Thread Chris Wilson

Quoting Daniel Vetter (2017-08-23 16:09:50)
> On Wed, Aug 23, 2017 at 03:13:55PM +0100, Chris Wilson wrote:
> > These tests are not intended to exercise runtime pm, but the device
> > going to sleep in the middle of these tests can significantly slow them
> > down as the GTT mmapping is torn down and must be rebuilt. This can be a
> > major nuisance if the device autosuspends many times a second.
> > 
> > These tests differ from typical applications as they are not doing any
> > rendering or utilizing the display which would ordinarily keep the
> > device awake.
> > 
> > Signed-off-by: Chris Wilson 
> 
> Can we just disable rpm while the test is on? Or at least set the
> autosuspend timer to something huge like 60s, plus exit handler ofc.
> 
> Not as neat uabi as a fd-based wakeref, but has the upside that it doesn't
> require a new kernel. Since we just discussed igt compat in another thread
> ...

We don't depend upon for correct test functionality, just to avoid
emulating the page-fault-of-doom. It's just a nice-to-have from that
pov. The fallback would be to take i915_forcewake_user instead. That's a
bit of an overkill, but both have the drawback of disabling some
important sanity checking by the runtime-pm infra. If we do accept that
some bludging is necessary to help bxt, we should at least add a couple
of tests before the wakeref to see if we can exercise those internal
checks.

> Maybe should even extract that into lib/ from pm_rpm.

I carefully stopped before the third instance.
-Chris
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[Intel-gfx] [PATCH i-g-t 1/3] tests/chamelium: Introduce fast basic hpd tests, with limited toggles

2017-08-23 Thread Paul Kocialkowski

This introduces a fast fashion of testing basic hotplug detect, with
only 3 toggles. It drastically reduces the run time of the test, which
is necessary for the fast-feedback test list.

Signed-off-by: Paul Kocialkowski 
---
 tests/chamelium.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tests/chamelium.c b/tests/chamelium.c
index 881b7fa9..0339c635 100644
--- a/tests/chamelium.c
+++ b/tests/chamelium.c
@@ -48,6 +48,7 @@ typedef struct {
 
 #define HPD_TOGGLE_COUNT_VGA 5
 #define HPD_TOGGLE_COUNT_DP_HDMI 15
+#define HPD_TOGGLE_COUNT_FAST 3
 
 static void
 get_connectors_link_status_failed(data_t *data, bool *link_status_failed)
@@ -775,6 +776,10 @@ igt_main
test_basic_hotplug(&data, port,
   HPD_TOGGLE_COUNT_DP_HDMI);
 
+   connector_subtest("dp-hpd-fast", DisplayPort)
+   test_basic_hotplug(&data, port,
+  HPD_TOGGLE_COUNT_FAST);
+
connector_subtest("dp-edid-read", DisplayPort) {
test_edid_read(&data, port, edid_id,
   igt_kms_get_base_edid());
@@ -832,6 +837,10 @@ igt_main
test_basic_hotplug(&data, port,
   HPD_TOGGLE_COUNT_DP_HDMI);
 
+   connector_subtest("hdmi-hpd-fast", HDMIA)
+   test_basic_hotplug(&data, port,
+  HPD_TOGGLE_COUNT_FAST);
+
connector_subtest("hdmi-edid-read", HDMIA) {
test_edid_read(&data, port, edid_id,
   igt_kms_get_base_edid());
@@ -888,6 +897,9 @@ igt_main
connector_subtest("vga-hpd", VGA)
test_basic_hotplug(&data, port, HPD_TOGGLE_COUNT_VGA);
 
+   connector_subtest("vga-hpd-fast", VGA)
+   test_basic_hotplug(&data, port, HPD_TOGGLE_COUNT_FAST);
+
connector_subtest("vga-edid-read", VGA) {
test_edid_read(&data, port, edid_id,
   igt_kms_get_base_edid());
-- 
2.14.0

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[Intel-gfx] [PATCH i-g-t 3/3] intel-ci: Add fast chamelium tests to the fast-feedback list

2017-08-23 Thread Paul Kocialkowski

This adds the fastest chamelium tests to the Intel CI fast-feedback
list, with the objective of running in under a minute.

Signed-off-by: Paul Kocialkowski 
---
 tests/intel-ci/fast-feedback.testlist | 9 +
 1 file changed, 9 insertions(+)

diff --git a/tests/intel-ci/fast-feedback.testlist 
b/tests/intel-ci/fast-feedback.testlist
index 79160624..a8e9c5be 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,5 +1,14 @@
 # Keep alphabetically sorted by default
 
+igt@chamelium@dp-hpd-fast
+igt@chamelium@dp-edid-read
+igt@chamelium@dp-crc-fast
+igt@chamelium@hdmi-hpd-fast
+igt@chamelium@hdmi-edid-read
+igt@chamelium@hdmi-crc-fast
+igt@chamelium@vga-hpd-fast
+igt@chamelium@vga-edid-read
+igt@chamelium@common-hpd-after-suspend
 igt@core_auth@basic-auth
 igt@core_prop_blob@basic
 igt@debugfs_test@read_all_entries
-- 
2.14.0

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[Intel-gfx] [PATCH i-g-t 2/3] tests/chamelium: Introduce fast CRC tests, with a single mode

2017-08-23 Thread Paul Kocialkowski

This introduces a fast fashion of testing display CRC, that only tests
a single mode (the highest resolution). It drastically reduces the run
time of the test, which is necessary for the fast-feedback test list.

Signed-off-by: Paul Kocialkowski 
---
 tests/chamelium.c | 22 --
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/tests/chamelium.c b/tests/chamelium.c
index 0339c635..00ae484b 100644
--- a/tests/chamelium.c
+++ b/tests/chamelium.c
@@ -497,7 +497,8 @@ disable_output(data_t *data,
 }
 
 static void
-test_display_crc(data_t *data, struct chamelium_port *port, int count)
+test_display_crc(data_t *data, struct chamelium_port *port, int count,
+bool fast)
 {
igt_display_t display;
igt_output_t *output;
@@ -509,6 +510,7 @@ test_display_crc(data_t *data, struct chamelium_port *port, 
int count)
drmModeModeInfo *mode;
drmModeConnector *connector;
int fb_id, i, j, captured_frame_count;
+   int count_modes;
 
reset_state(data, port);
 
@@ -517,7 +519,9 @@ test_display_crc(data_t *data, struct chamelium_port *port, 
int count)
primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
igt_assert(primary);
 
-   for (i = 0; i < connector->count_modes; i++) {
+   count_modes = fast ? 1 : connector->count_modes;
+
+   for (i = 0; i < count_modes; i++) {
mode = &connector->modes[i];
fb_id = igt_create_color_pattern_fb(data->drm_fd,
mode->hdisplay,
@@ -818,10 +822,13 @@ igt_main
edid_id, alt_edid_id);
 
connector_subtest("dp-crc-single", DisplayPort)
-   test_display_crc(&data, port, 1);
+   test_display_crc(&data, port, 1, false);
+
+   connector_subtest("dp-crc-fast", DisplayPort)
+   test_display_crc(&data, port, 1, true);
 
connector_subtest("dp-crc-multiple", DisplayPort)
-   test_display_crc(&data, port, 3);
+   test_display_crc(&data, port, 3, false);
 
connector_subtest("dp-frame-dump", DisplayPort)
test_display_frame_dump(&data, port);
@@ -879,10 +886,13 @@ igt_main
edid_id, alt_edid_id);
 
connector_subtest("hdmi-crc-single", HDMIA)
-   test_display_crc(&data, port, 1);
+   test_display_crc(&data, port, 1, false);
+
+   connector_subtest("hdmi-crc-fast", HDMIA)
+   test_display_crc(&data, port, 1, true);
 
connector_subtest("hdmi-crc-multiple", HDMIA)
-   test_display_crc(&data, port, 3);
+   test_display_crc(&data, port, 3, false);
 
connector_subtest("hdmi-frame-dump", HDMIA)
test_display_frame_dump(&data, port);
-- 
2.14.0

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[Intel-gfx] [PATCH 3/7] drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

Use explicit old/new states instead of relying on obj->state.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +
 drivers/gpu/drm/i915/intel_drv.h |  8 
 drivers/gpu/drm/i915/intel_pm.c  | 30 +++---
 3 files changed, 32 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef53026b..1072fbd70eae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -569,6 +569,15 @@ struct i915_hotplug {
 (__i)++) \
for_each_if (plane_state)
 
+#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, 
new_plane_state, __i) \
+   for ((__i) = 0; \
+(__i) < (__state)->base.dev->mode_config.num_total_plane && \
+((plane) = 
to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+(__i)++) \
+   for_each_if (plane)
+
 struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9a7c7dd0ea84..e2e9b8215864 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1191,6 +1191,14 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 }
 
 static inline struct intel_crtc_state *
+intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
+&crtc->base));
+}
+
+static inline struct intel_crtc_state *
 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ff0b9f999f..b9cbc5fec909 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1322,21 +1322,21 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state 
*crtc_state)
int num_active_planes = hweight32(crtc_state->active_planes &
  ~BIT(PLANE_CURSOR));
const struct g4x_pipe_wm *raw;
-   struct intel_plane_state *plane_state;
+   const struct intel_plane_state *old_plane_state;
+   const struct intel_plane_state *new_plane_state;
struct intel_plane *plane;
enum plane_id plane_id;
int i, level;
unsigned int dirty = 0;
 
-   for_each_intel_plane_in_state(state, plane, plane_state, i) {
-   const struct intel_plane_state *old_plane_state =
-   to_intel_plane_state(plane->base.state);
-
-   if (plane_state->base.crtc != &crtc->base &&
+   for_each_oldnew_intel_plane_in_state(state, plane,
+old_plane_state,
+new_plane_state, i) {
+   if (new_plane_state->base.crtc != &crtc->base &&
old_plane_state->base.crtc != &crtc->base)
continue;
 
-   if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
+   if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
dirty |= BIT(plane->id);
}
 
@@ -1831,21 +1831,21 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state 
*crtc_state)
int num_active_planes = hweight32(crtc_state->active_planes &
  ~BIT(PLANE_CURSOR));
bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
-   struct intel_plane_state *plane_state;
+   const struct intel_plane_state *old_plane_state;
+   const struct intel_plane_state *new_plane_state;
struct intel_plane *plane;
enum plane_id plane_id;
int level, ret, i;
unsigned int dirty = 0;
 
-   for_each_intel_plane_in_state(state, plane, plane_state, i) {
-   const struct intel_plane_state *old_plane_state =
-   to_intel_plane_state(plane->base.state);
-
-   if (plane_state->base.crtc != &crtc->base &&
+   for_each_oldnew_intel_plane_in_state(state, plane,
+old_plane_state,
+new_plane_state, i) {
+   if (new_plane_state->base.crtc != &crtc->base &&
old_plane_state->base.crtc != &crtc->base)
continue;
 
-   if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
+   if (vlv_raw_plane_wm_compute(crtc_state,

[Intel-gfx] [PATCH 1/7] drm/i915: Pass the new crtc state to color management code

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

In an effort to eliminate the obj->state usage let's pass on the
new crtc state pointer (which we already have!) to the color management
code.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ad74d1d11dbe..80a14b30e4d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12928,8 +12928,8 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
if (!modeset &&
(intel_cstate->base.color_mgmt_changed ||
 intel_cstate->update_pipe)) {
-   intel_color_set_csc(crtc->state);
-   intel_color_load_luts(crtc->state);
+   intel_color_set_csc(&intel_cstate->base);
+   intel_color_load_luts(&intel_cstate->base);
}
 
/* Perform vblank evasion around commit operation */
-- 
2.13.0

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[Intel-gfx] [PATCH 2/7] drm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

Pass the appropriate new crtc state explicitly to
intel_pipe_update_start/end() instead of of mucking around with
crtc->state.

v2: The mmio flip stuff is gone

Reviewed-by: Maarten Lankhorst  #v1
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 14 +-
 drivers/gpu/drm/i915/intel_drv.h | 12 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 27 +--
 3 files changed, 32 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 80a14b30e4d3..cee4db0a1626 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12917,13 +12917,13 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   struct intel_crtc_state *intel_cstate =
-   to_intel_crtc_state(crtc->state);
struct intel_crtc_state *old_intel_cstate =
to_intel_crtc_state(old_crtc_state);
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_crtc_state->state);
-   bool modeset = needs_modeset(crtc->state);
+   struct intel_crtc_state *intel_cstate =
+   intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
+   bool modeset = needs_modeset(&intel_cstate->base);
 
if (!modeset &&
(intel_cstate->base.color_mgmt_changed ||
@@ -12933,7 +12933,7 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
}
 
/* Perform vblank evasion around commit operation */
-   intel_pipe_update_start(intel_crtc);
+   intel_pipe_update_start(intel_cstate);
 
if (modeset)
goto out;
@@ -12953,8 +12953,12 @@ static void intel_finish_crtc_commit(struct drm_crtc 
*crtc,
 struct drm_crtc_state *old_crtc_state)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_atomic_state *old_intel_state =
+   to_intel_atomic_state(old_crtc_state->state);
+   struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
 
-   intel_pipe_update_end(intel_crtc);
+   intel_pipe_update_end(new_crtc_state);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f60995fe455c..9a7c7dd0ea84 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1190,6 +1190,14 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 }
 
+static inline struct intel_crtc_state *
+intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
+&crtc->base));
+}
+
 /* intel_fifo_underrun.c */
 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
   enum pipe pipe, bool enable);
@@ -1888,8 +1896,8 @@ struct intel_plane *intel_sprite_plane_create(struct 
drm_i915_private *dev_priv,
  enum pipe pipe, int plane);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  struct drm_file *file_priv);
-void intel_pipe_update_start(struct intel_crtc *crtc);
-void intel_pipe_update_end(struct intel_crtc *crtc);
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 524933b01483..b0d6e3e28d07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -70,8 +70,7 @@ int intel_usecs_to_scanlines(const struct drm_display_mode 
*adjusted_mode,
 
 /**
  * intel_pipe_update_start() - start update of a set of display registers
- * @crtc: the crtc of which the registers are going to be updated
- * @start_vbl_count: vblank counter return pointer used for error checking
+ * @new_crtc_state: the new crtc state
  *
  * Mark the start of an update to pipe registers that should be updated
  * atomically regarding vblank. If the next vblank will happens within
@@ -79,18 +78,18 @@ int intel_usecs_to_scanlines(const struct drm_display_mode 
*adjusted_mode,
  *
  * After a successful call to this function, interrupts will be disabled
  * until a subsequent call to intel_pipe_update_end(). That is done to
- * avoid random delays. The value written to @start_vbl_count should be
-

[Intel-gfx] [PATCH 4/7] drm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

Eliminate plane->state and crtc->state usage from
intel_plane_atomic_check_with_state() and its callers. Instead pass the
proper states in or dig them up from the top level atomic state.

Note that intel_plane_atomic_check_with_state() itself isn't allowed to
use the top level atomic state as there is none when it gets called from
the legacy cursor short circuit path.

v2: Rename some variables for easier comprehension (Maarten)

Cc: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 49 +++
 drivers/gpu/drm/i915/intel_display.c  | 12 
 drivers/gpu/drm/i915/intel_drv.h  | 16 --
 3 files changed, 51 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index ee76fab7bb6f..8e6dc159f64d 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
 }
 
-int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
+int intel_plane_atomic_check_with_state(const struct intel_crtc_state 
*old_crtc_state,
+   struct intel_crtc_state *crtc_state,
+   const struct intel_plane_state 
*old_plane_state,
struct intel_plane_state *intel_state)
 {
struct drm_plane *plane = intel_state->base.plane;
@@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(struct 
intel_crtc_state *crtc_state,
 * anything driver-specific we need to test in that case, so
 * just return success.
 */
-   if (!intel_state->base.crtc && !plane->state->crtc)
+   if (!intel_state->base.crtc && !old_plane_state->base.crtc)
return 0;
 
/* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */
@@ -194,16 +196,21 @@ int intel_plane_atomic_check_with_state(struct 
intel_crtc_state *crtc_state,
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
 
-   return intel_plane_atomic_calc_changes(&crtc_state->base, state);
+   return intel_plane_atomic_calc_changes(old_crtc_state,
+  &crtc_state->base,
+  old_plane_state,
+  state);
 }
 
 static int intel_plane_atomic_check(struct drm_plane *plane,
-   struct drm_plane_state *state)
+   struct drm_plane_state *new_plane_state)
 {
-   struct drm_crtc *crtc = state->crtc;
-   struct drm_crtc_state *drm_crtc_state;
-
-   crtc = crtc ? crtc : plane->state->crtc;
+   struct drm_atomic_state *state = new_plane_state->state;
+   const struct drm_plane_state *old_plane_state =
+   drm_atomic_get_old_plane_state(state, plane);
+   struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
+   const struct drm_crtc_state *old_crtc_state;
+   struct drm_crtc_state *new_crtc_state;
 
/*
 * Both crtc and plane->crtc could be NULL if we're updating a
@@ -214,29 +221,33 @@ static int intel_plane_atomic_check(struct drm_plane 
*plane,
if (!crtc)
return 0;
 
-   drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
-   if (WARN_ON(!drm_crtc_state))
-   return -EINVAL;
+   old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
+   new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 
-   return 
intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state),
-  to_intel_plane_state(state));
+   return 
intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
+  
to_intel_crtc_state(new_crtc_state),
+  
to_intel_plane_state(old_plane_state),
+  
to_intel_plane_state(new_plane_state));
 }
 
 static void intel_plane_atomic_update(struct drm_plane *plane,
  struct drm_plane_state *old_state)
 {
+   struct intel_atomic_state *state = 
to_intel_atomic_state(old_state->state);
struct intel_plane *intel_plane = to_intel_plane(plane);
-   struct intel_plane_state *intel_state =
-   to_intel_plane_state(plane->state);
-   struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc;
+   const struct intel_plane_state *new_plane_state =
+   intel_atomic_get_new_plane_state(state, intel_plane);
+   struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc;
+
+   if (ne

[Intel-gfx] [PATCH 6/7] drm/i915: Eliminate crtc->state usage from intel_update_pipe_config()

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

Pass the correct new crtc state to intel_update_pipe_config() instead
of using crtc->state.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ed5f63de6769..49020ffd9ac6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3784,15 +3784,14 @@ void intel_finish_reset(struct drm_i915_private 
*dev_priv)
clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
 }
 
-static void intel_update_pipe_config(struct intel_crtc *crtc,
-struct intel_crtc_state *old_crtc_state)
+static void intel_update_pipe_config(const struct intel_crtc_state 
*old_crtc_state,
+const struct intel_crtc_state 
*new_crtc_state)
 {
+   struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->base.state);
 
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
-   crtc->base.mode = crtc->base.state->mode;
+   crtc->base.mode = new_crtc_state->base.mode;
 
/*
 * Update pipe size and adjust fitter if needed: the reason for this is
@@ -3804,17 +3803,17 @@ static void intel_update_pipe_config(struct intel_crtc 
*crtc,
 */
 
I915_WRITE(PIPESRC(crtc->pipe),
-  ((pipe_config->pipe_src_w - 1) << 16) |
-  (pipe_config->pipe_src_h - 1));
+  ((new_crtc_state->pipe_src_w - 1) << 16) |
+  (new_crtc_state->pipe_src_h - 1));
 
/* on skylake this is done by detaching scalers */
if (INTEL_GEN(dev_priv) >= 9) {
skl_detach_scalers(crtc);
 
-   if (pipe_config->pch_pfit.enabled)
+   if (new_crtc_state->pch_pfit.enabled)
skylake_pfit_enable(crtc);
} else if (HAS_PCH_SPLIT(dev_priv)) {
-   if (pipe_config->pch_pfit.enabled)
+   if (new_crtc_state->pch_pfit.enabled)
ironlake_pfit_enable(crtc);
else if (old_crtc_state->pch_pfit.enabled)
ironlake_pfit_disable(crtc, true);
@@ -12942,7 +12941,7 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
goto out;
 
if (intel_cstate->update_pipe)
-   intel_update_pipe_config(intel_crtc, old_intel_cstate);
+   intel_update_pipe_config(old_intel_cstate, intel_cstate);
else if (INTEL_GEN(dev_priv) >= 9)
skl_detach_scalers(intel_crtc);
 
-- 
2.13.0

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[Intel-gfx] [PATCH 7/7] drm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail and .crtc_update()

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

We already have the correct new crtc state so just use that instead of
crtc->state.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 49020ffd9ac6..593459368cab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12256,7 +12256,7 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state,
unsigned int cmask = drm_crtc_mask(crtc);
 
intel_crtc = to_intel_crtc(crtc);
-   cstate = to_intel_crtc_state(crtc->state);
+   cstate = to_intel_crtc_state(new_crtc_state);
pipe = intel_crtc->pipe;
 
if (updated & cmask || !cstate->base.active)
@@ -12385,7 +12385,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
 
-   if (!crtc->state->active) {
+   if (!new_crtc_state->active) {
/*
 * Make sure we don't call initial_watermarks
 * for ILK-style watermark updates.
@@ -12394,7 +12394,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
 */
if (INTEL_GEN(dev_priv) >= 9)

dev_priv->display.initial_watermarks(intel_state,
-
to_intel_crtc_state(crtc->state));
+
to_intel_crtc_state(new_crtc_state));
}
}
}
-- 
2.13.0

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[Intel-gfx] [PATCH 5/7] drm/i915: Eliminate obj->state usage from pre/post plane update

2017-08-23 Thread ville . syrjala

From: Ville Syrjälä 

Dig up the appropriate new crtc and plane states from the top level
atomic state in intel_pre_plane_update() and intel_post_plane_update().

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 50617f390dce..ed5f63de6769 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5098,7 +5098,8 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->base.state);
+   
intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
+   crtc);
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_pri_state =
drm_atomic_get_existing_plane_state(old_state, primary);
@@ -5110,7 +5111,8 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
 
if (old_pri_state) {
struct intel_plane_state *primary_state =
-   to_intel_plane_state(primary->state);
+   
intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
+
to_intel_plane(primary));
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
 
@@ -5139,7 +5141,8 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
 
if (old_pri_state) {
struct intel_plane_state *primary_state =
-   to_intel_plane_state(primary->state);
+   intel_atomic_get_new_plane_state(old_intel_state,
+
to_intel_plane(primary));
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
 
-- 
2.13.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] tests/chamelium: Introduce fast basic hpd tests, with limited toggles

2017-08-23 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] tests/chamelium: Introduce fast basic hpd 
tests, with limited toggles
URL   : https://patchwork.freedesktop.org/series/29218/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2995
2964b2f40295 drm-tip: 2017y-08m-23d-13h-11m-32s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:461s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:436s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:365s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:559s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:254s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:530s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:527s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:607s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:444s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:505s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:602s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:531s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:446s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:488s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:553s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:411s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_89/
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Pass the new crtc state to color management code

2017-08-23 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/i915: Pass the new crtc state to color 
management code
URL   : https://patchwork.freedesktop.org/series/29219/
State : success

== Summary ==

Series 29219v1 series starting with [1/7] drm/i915: Pass the new crtc state to 
color management code
https://patchwork.freedesktop.org/api/1.0/series/29219/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:436s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:362s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:560s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:523s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:529s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:520s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:440s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:616s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:508s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:604s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:534s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:484s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:486s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:442s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:480s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:553s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:408s

2964b2f4029594399c4e3c28d64c504dcd914ab4 drm-tip: 2017y-08m-23d-13h-11m-32s UTC 
integration manifest
771ec71694a9 drm/i915: Eliminate crtc->state usage from 
intel_atomic_commit_tail and .crtc_update()
886ed5e6aee8 drm/i915: Eliminate crtc->state usage from 
intel_update_pipe_config()
f6951661fdef drm/i915: Eliminate obj->state usage from pre/post plane update
1385856883f1 drm/i915: Pass proper old/new states to 
intel_plane_atomic_check_with_state()
83ae0a82ef4a drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation
2a84e3cce6c3 drm/i915: Pass the crtc state explicitly to 
intel_pipe_update_start/end()
3c63369bd59c drm/i915: Pass the new crtc state to color management code

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5476/
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[Intel-gfx] [PATCH v3 00/12] Improve robustness of the i915 perf tests

2017-08-23 Thread Lionel Landwerlin

Hi all,

Finally figured the final issue with the flakyness of the tests on
Broadwell (patch 12). Some fallout of that generated patch 11.

Cheers,

Lionel Landwerlin (11):
  tests/perf: make stream_fd a global variable
  tests/perf: update max buffer size for reading reports
  tests/perf: rc6: try to guess when rc6 is disabled
  tests/perf: remove frequency related changes
  tests/perf: rework oa-exponent test
  tests/perf: make enable-disable more reliable
  tests/perf: make buffer-fill more reliable
  tests/perf: add Kabylake support
  tests/perf: add Geminilake support
  tests/perf: estimate number of blocking/polling based on time spent
  tests/perf: prevent power management to kick in when necessary

Robert Bragg (1):
  tests/perf: add per context filtering test for gen8+

 tests/perf.c | 2038 +++---
 1 file changed, 1673 insertions(+), 365 deletions(-)

--
2.14.1
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[Intel-gfx] [PATCH v3 03/12] tests/perf: update max buffer size for reading reports

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 5058315c..bc5ea133 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1280,9 +1280,7 @@ read_2_oa_reports(int format_id,
/* Note: we allocate a large buffer so that each read() iteration
 * should scrape *all* pending records.
 *
-* The largest buffer the OA unit supports is 16MB and the smallest
-* OA report format is 64bytes allowing up to 262144 reports to
-* be buffered.
+* The largest buffer the OA unit supports is 16MB.
 *
 * Being sure we are fetching all buffered reports allows us to
 * potentially throw away / skip all reports whenever we see
@@ -1295,7 +1293,8 @@ read_2_oa_reports(int format_id,
 * to indicate that the OA unit may be over taxed if lots of reports
 * are being lost.
 */
-   int buf_size = 262144 * (64 + sizeof(struct 
drm_i915_perf_record_header));
+   int max_reports = (16 * 1024 * 1024) / format_size;
+   int buf_size = sample_size * max_reports * 1.5;
uint8_t *buf = malloc(buf_size);
int n = 0;
 
@@ -1307,6 +1306,7 @@ read_2_oa_reports(int format_id,
;
 
igt_assert(len > 0);
+   igt_debug("read %d bytes\n", (int)len);
 
for (size_t offset = 0; offset < len; offset += header->size) {
const uint32_t *report;
-- 
2.14.1

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[Intel-gfx] [PATCH v3 04/12] tests/perf: rc6: try to guess when rc6 is disabled

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index bc5ea133..1b441601 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -3445,6 +3445,17 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
+static bool
+rc6_enabled(void)
+{
+   char *rc6_status = read_debugfs_record(drm_fd, "i915_drpc_info",
+  "RC6 Enabled");
+   bool enabled = strcmp(rc6_status, "yes") == 0;
+
+   free(rc6_status);
+   return enabled;
+}
+
 static void
 test_rc6_disable(void)
 {
@@ -3464,6 +3475,8 @@ test_rc6_disable(void)
};
uint64_t n_events_start, n_events_end;
 
+   igt_skip_on(!rc6_enabled());
+
stream_fd = __perf_open(drm_fd, ¶m);
 
n_events_start = read_debugfs_u64_record(drm_fd, "i915_drpc_info",
-- 
2.14.1

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[Intel-gfx] [PATCH v3 01/12] tests/perf: make stream_fd a global variable

2017-08-23 Thread Lionel Landwerlin

When debugging unstable tests on new platforms we currently we don't
cleanup everything well in between different tests. Since only a
single OA stream fd can be opened at a time, having the stream_fd as a
global variable helps us cleanup the state between tests.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 121 ---
 1 file changed, 65 insertions(+), 56 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index dd2263ee..ca5bfdc5 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -285,6 +285,7 @@ static bool hsw_undefined_a_counters[45] = {
 static bool gen8_undefined_a_counters[45];
 
 static int drm_fd = -1;
+static int stream_fd = -1;
 static uint32_t devid;
 static int card = -1;
 static int n_eus;
@@ -306,10 +307,22 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static void
+__perf_close(int fd)
+{
+   close(fd);
+   stream_fd = -1;
+}
+
 static int
 __perf_open(int fd, struct drm_i915_perf_open_param *param)
 {
-   int ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
+   int ret;
+
+   if (stream_fd >= 0)
+   __perf_close(stream_fd);
+
+   ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
 
igt_assert(ret >= 0);
errno = 0;
@@ -960,14 +973,12 @@ test_system_wide_paranoid(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
-
write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
 
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1015,7 +1026,6 @@ test_invalid_oa_metric_set_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m, EINVAL);
 
@@ -1025,7 +1035,7 @@ test_invalid_oa_metric_set_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_metric_set_id;
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA metric set ID... */
param.num_properties--;
@@ -1050,7 +1060,6 @@ test_invalid_oa_format_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m, EINVAL);
 
@@ -1060,7 +1069,7 @@ test_invalid_oa_format_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_oa_format;
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA format... */
param.num_properties--;
@@ -1088,8 +1097,7 @@ test_missing_sample_flags(void)
 }
 
 static void
-read_2_oa_reports(int stream_fd,
- int format_id,
+read_2_oa_reports(int format_id,
  int exponent,
  uint32_t *oa_report0,
  uint32_t *oa_report1,
@@ -1223,12 +1231,13 @@ open_and_read_2_oa_reports(int format_id,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, ¶m);
 
-   read_2_oa_reports(stream_fd, format_id, exponent,
+   stream_fd = __perf_open(drm_fd, ¶m);
+
+   read_2_oa_reports(format_id, exponent,
  oa_report0, oa_report1, timer_only);
 
-   close(stream_fd);
+   __perf_close(stream_fd);
 }
 
 static void
@@ -1528,9 +1537,10 @@ test_invalid_oa_exponent(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, ¶m);
 
-   close(stream_fd);
+   stream_fd = __perf_open(drm_fd, ¶m);
+
+   __perf_close(stream_fd);
 
for (int i = 32; i < 65; i++) {
properties[7] = i;
@@ -1580,12 +1590,10 @@ test_low_oa_exponent_permissions(void)
properties[7] = ok_exponent;
 
igt_fork(child, 1) {
-   int stream_fd;
-
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, ¶m);
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1634,7 +1642,6 @@ test_per_context_mode_unprivileged(void)
igt_fork(child,

[Intel-gfx] [PATCH v3 02/12] tests/perf: add per context filtering test for gen8+

2017-08-23 Thread Lionel Landwerlin

From: Robert Bragg 

Signed-off-by: Robert Bragg 
Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 777 ---
 1 file changed, 745 insertions(+), 32 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index ca5bfdc5..5058315c 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -48,7 +48,9 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming 
interface");
 #define OAREPORT_REASON_MASK   0x3f
 #define OAREPORT_REASON_SHIFT  19
 #define OAREPORT_REASON_TIMER  (1<<0)
+#define OAREPORT_REASON_INTERNAL   (3<<1)
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
+#define OAREPORT_REASON_GO (1<<4)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
 #define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24))
@@ -574,6 +576,22 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_ctx_is_valid(uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   return false; /* TODO */
+   } else if (IS_GEN8(devid)) {
+   return report[0] & (1ul << 25);
+   } else if (IS_GEN9(devid)) {
+   return report[0] & (1ul << 16);
+   }
+
+   /* Need to update this function for newer Gen. */
+   igt_assert(!"reached");
+}
+
+
 static void
 hsw_sanity_check_render_basic_reports(uint32_t *oa_report0, uint32_t 
*oa_report1,
  enum drm_i915_oa_format fmt)
@@ -678,6 +696,100 @@ gen8_40bit_a_delta(uint64_t value0, uint64_t value1)
return value1 - value0;
 }
 
+static void
+accumulate_uint32(size_t offset,
+ uint32_t *report0,
+  uint32_t *report1,
+  uint64_t *delta)
+{
+   uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset);
+   uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset);
+
+   *delta += (uint32_t)(value1 - value0);
+}
+
+static void
+accumulate_uint40(int a_index,
+  uint32_t *report0,
+  uint32_t *report1,
+ enum drm_i915_oa_format format,
+  uint64_t *delta)
+{
+   uint64_t value0 = gen8_read_40bit_a_counter(report0, format, a_index),
+value1 = gen8_read_40bit_a_counter(report1, format, a_index);
+
+   *delta += gen8_40bit_a_delta(value0, value1);
+}
+
+static void
+accumulate_reports(struct accumulator *accumulator,
+  uint32_t *start,
+  uint32_t *end)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   if (intel_gen(devid) >= 8) {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+
+   /* clock cycles */
+   accumulate_uint32(12, start, end, deltas + idx++);
+   } else {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   accumulate_uint40(i, start, end, format, deltas + idx++);
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   accumulate_uint32(oa_formats[format].a_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_b; i++) {
+   accumulate_uint32(oa_formats[format].b_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_c; i++) {
+   accumulate_uint32(oa_formats[format].c_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+}
+
+static void
+accumulator_print(struct accumulator *accumulator, const char *title)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   igt_debug("%s:\n", title);
+   if (intel_gen(devid) >= 8) {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   igt_debug("\tclock cycle delta = %lu\n", deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   igt_debug("\tA%u = %lu\n", i, deltas[idx++]);
+   } else {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   int a_id = oa_formats[format].first_a + i;
+   igt_debug("\tA%u = %lu\n", a_id, deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++)
+   igt_debug("\tB%u = %lu\n", i, deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_c; i++)
+   igt_debug("\tC%u = %lu\n", i, deltas[idx++]);
+}
+
 /* The TestOa metric set is designed so */
 static void
 gen8_sanity_check_test_

[Intel-gfx] [PATCH v3 07/12] tests/perf: make enable-disable more reliable

2017-08-23 Thread Lionel Landwerlin

Estimation of the amount of reports can only refer to periodic ones,
as context switch reports completely depend on what happens on the
system. Also generate some load to prevent clock frequency changes to
impact our measurement.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 96 
 1 file changed, 90 insertions(+), 6 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index e54a14ed..faab2efc 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2779,10 +2779,18 @@ test_enable_disable(void)
int n_full_oa_reports = oa_buf_size / report_size;
uint64_t fill_duration = n_full_oa_reports * oa_period;
 
+   load_helper_init();
+   load_helper_run(HIGH);
+
stream_fd = __perf_open(drm_fd, ¶m);
 
for (int i = 0; i < 5; i++) {
int len;
+   uint32_t n_periodic_reports;
+   struct drm_i915_perf_record_header *header;
+   uint32_t first_timestamp = 0, last_timestamp = 0;
+   uint32_t last_periodic_report[64];
+   double tick_per_period;
 
/* Giving enough time for an overflow might help catch whether
 * the OA unit has been enabled even if the driver might at
@@ -2802,18 +2810,91 @@ test_enable_disable(void)
 
nanosleep(&(struct timespec){ .tv_sec = 0,
  .tv_nsec = fill_duration / 2 },
- NULL);
+   NULL);
 
-   while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == 
EINTR)
-   ;
+   n_periodic_reports = 0;
 
-   igt_assert_neq(len, -1);
+   /* Because of the race condition between notification of new
+* reports and reports landing in memory, we need to rely on
+* timestamps to figure whether we've read enough of them.
+*/
+   while (((last_timestamp - first_timestamp) * 
oa_exponent_to_ns(oa_exponent)) <
+  (fill_duration / 2)) {
 
-   igt_assert(len > report_size * n_full_oa_reports * 0.45);
-   igt_assert(len < report_size * n_full_oa_reports * 0.55);
+   while ((len = read(stream_fd, buf, buf_size)) == -1 && 
errno == EINTR)
+   ;
+
+   igt_assert_neq(len, -1);
+
+   for (int offset = 0; offset < len; offset += 
header->size) {
+   uint32_t *report;
+   double previous_tick_per_period;
+
+   header = (void *) (buf + offset);
+   report = (void *) (header + 1);
+
+   switch (header->type) {
+   case DRM_I915_PERF_RECORD_OA_REPORT_LOST:
+   break;
+   case DRM_I915_PERF_RECORD_SAMPLE:
+   if (first_timestamp == 0)
+   first_timestamp = report[1];
+   last_timestamp = report[1];
+
+   previous_tick_per_period = 
tick_per_period;
+
+   if (n_periodic_reports > 0 &&
+   oa_report_is_periodic(oa_exponent, 
report)) {
+   tick_per_period =
+   
oa_reports_tick_per_period(last_periodic_report,
+   
   report);
+
+   if 
(!double_value_within(tick_per_period,
+
previous_tick_per_period, 5))
+   igt_debug("clock 
change!\n");
+
+   igt_debug(" > report ts=%u"
+ " 
ts_delta_last_periodic=%8u is_timer=%i ctx_id=%8x gpu_ticks=%u 
nb_periodic=%u\n",
+ report[1],
+ report[1] - 
last_periodic_report[1],
+ 
oa_report_is_periodic(oa_exponent, report),
+ 
oa_report_get_ctx_id(report),
+ report[3] - 
last_periodic_report[3],
+ n_periodic_reports);
+
+   memcpy(last_periodic_report, 
report,
+  
sizeof(last_periodic_report));
+

[Intel-gfx] [PATCH v3 05/12] tests/perf: remove frequency related changes

2017-08-23 Thread Lionel Landwerlin

Experience shows that most of the issues we face with periodicity of
the reports produced by the OA unit are related to power management,
not frequency.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 141 ---
 1 file changed, 9 insertions(+), 132 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 1b441601..ca69440d 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -293,12 +293,9 @@ static int card = -1;
 static int n_eus;
 
 static uint64_t test_metric_set_id = UINT64_MAX;
-static uint64_t gt_min_freq_mhz_saved = 0;
-static uint64_t gt_max_freq_mhz_saved = 0;
-static uint64_t gt_min_freq_mhz = 0;
-static uint64_t gt_max_freq_mhz = 0;
 
 static uint64_t timestamp_frequency = 1250;
+static uint64_t gt_max_freq_mhz = 0;
 static enum drm_i915_oa_format test_oa_format;
 static bool *undefined_a_counters;
 static uint64_t oa_exp_1_millisec;
@@ -402,16 +399,6 @@ sysfs_read(const char *file)
return read_u64_file(buf);
 }
 
-static void
-sysfs_write(const char *file, uint64_t val)
-{
-   char buf[512];
-
-   snprintf(buf, sizeof(buf), "/sys/class/drm/card%d/%s", card, file);
-
-   write_u64_file(buf, val);
-}
-
 static char *
 read_debugfs_record(int device, const char *file, const char *key)
 {
@@ -990,54 +977,6 @@ init_sys_info(void)
return try_read_u64_file(buf, &test_metric_set_id);
 }
 
-static void
-gt_frequency_range_save(void)
-{
-   gt_min_freq_mhz_saved = sysfs_read("gt_min_freq_mhz");
-   gt_max_freq_mhz_saved = sysfs_read("gt_max_freq_mhz");
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
-static void
-gt_frequency_pin(int gt_freq_mhz)
-{
-   igt_debug("requesting pinned GT freq = %dmhz\n", gt_freq_mhz);
-
-   if (gt_freq_mhz > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   }
-   gt_min_freq_mhz = gt_freq_mhz;
-   gt_max_freq_mhz = gt_freq_mhz;
-}
-
-static void
-gt_frequency_range_restore(void)
-{
-   igt_debug("restoring GT frequency range: min = %dmhz, max =%dmhz, 
current: min=%dmhz, max=%dmhz\n",
- (int)gt_min_freq_mhz_saved,
- (int)gt_max_freq_mhz_saved,
- (int)gt_min_freq_mhz,
- (int)gt_max_freq_mhz);
-
-   /* Assume current min/max are the same */
-   if (gt_min_freq_mhz_saved > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   }
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
 static int
 i915_read_reports_until_timestamp(enum drm_i915_oa_format oa_format,
  uint8_t *buf,
@@ -1614,33 +1553,9 @@ test_oa_formats(void)
 }
 
 static void
-test_oa_exponents(int gt_freq_mhz)
+test_oa_exponents(void)
 {
-   uint32_t freq_margin;
-
-   /* This test tries to use the sysfs interface for pinning the GT
-* frequency so we have another point of reference for comparing with
-* the clock frequency as derived from OA reports.
-*
-* This test has been finicky to stabilise while the
-* gt_min/max_freq_mhz files in sysfs don't seem to be a reliable
-* mechanism for fixing the gpu frequency.
-*
-* Since these unit tests are focused on the OA unit not the ability to
-* pin the frequency via sysfs we make the test account for pinning not
-* being reliable and read back the current frequency for each
-* iteration of this test to take this into account.
-*/
-   gt_frequency_pin(gt_freq_mhz);
-
-   igt_debug("Testing OA timer exponents with requested GT frequency = 
%dmhz\n",
- gt_freq_mhz);
-
-   /* allow a +- 10% error margin when checking that the frequency
-* calculated from the OA reports matches the frequency according to
-* sysfs.
-*/
-   freq_margin = gt_freq_mhz * 0.1;
+   igt_debug("Testing OA timer exponents\n");
 
/* It's asking a lot to sample with a 160 nanosecond period and the
 * test can fail due to buffer overflows if it wasn't possible to
@@ -1655,7 +1570,6 @@ test_oa_exponents(int gt_freq_mhz)
uint32_t clock_delta;
uint32_t freq;
int n_tested = 0;
-   int n_freq_matches = 0;
 
/* The exponent is effectively selecting a bit in the timestamp
 * to trigger reports on and so in practic

[Intel-gfx] [PATCH v3 10/12] tests/perf: add Geminilake support

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index b7d9f96d..9f12da40 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1124,6 +1124,9 @@ init_sys_info(void)
return false;
}
timestamp_frequency = 1200;
+   } else if (IS_GEMINILAKE(devid)) {
+   test_set_uuid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
+   timestamp_frequency = 1920;
} else {
igt_debug("unsupported GT\n");
return false;
-- 
2.14.1

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[Intel-gfx] [PATCH v3 08/12] tests/perf: make buffer-fill more reliable

2017-08-23 Thread Lionel Landwerlin

Filling rate of the buffer must discard context switch reports as they
do not depend upon the periodicity, instead they're a factor on the
amount of different applications concurrently running on the system.

Signed-off-by: Lionel Landwerlin 
Tested-by: Matthew Auld 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 120 ++-
 1 file changed, 103 insertions(+), 17 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index faab2efc..59cd50aa 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2687,22 +2687,30 @@ test_buffer_fill(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
+   struct drm_i915_perf_record_header *header;
int buf_size = 65536 * (256 + sizeof(struct 
drm_i915_perf_record_header));
uint8_t *buf = malloc(buf_size);
+   int len;
size_t oa_buf_size = 16 * 1024 * 1024;
size_t report_size = oa_formats[test_oa_format].size;
int n_full_oa_reports = oa_buf_size / report_size;
uint64_t fill_duration = n_full_oa_reports * oa_period;
 
+   load_helper_init();
+   load_helper_run(HIGH);
+
igt_assert(fill_duration < 10);
 
stream_fd = __perf_open(drm_fd, ¶m);
 
for (int i = 0; i < 5; i++) {
-   struct drm_i915_perf_record_header *header;
bool overflow_seen;
-   int offset = 0;
-   int len;
+   uint32_t n_periodic_reports;
+   uint32_t first_timestamp = 0, last_timestamp = 0;
+   uint32_t last_periodic_report[64];
+   double tick_per_period;
+
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
 
nanosleep(&(struct timespec){ .tv_sec = 0,
  .tv_nsec = fill_duration * 1.25 },
@@ -2714,7 +2722,7 @@ test_buffer_fill(void)
igt_assert_neq(len, -1);
 
overflow_seen = false;
-   for (offset = 0; offset < len; offset += header->size) {
+   for (int offset = 0; offset < len; offset += header->size) {
header = (void *)(buf + offset);
 
if (header->type == DRM_I915_PERF_RECORD_OA_BUFFER_LOST)
@@ -2723,32 +2731,110 @@ test_buffer_fill(void)
 
igt_assert_eq(overflow_seen, true);
 
+   do_ioctl(stream_fd, I915_PERF_IOCTL_DISABLE, 0);
+
+   igt_debug("fill_duration = %luns, oa_exponent = %u\n",
+ fill_duration, oa_exponent);
+
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+
nanosleep(&(struct timespec){ .tv_sec = 0,
- .tv_nsec = fill_duration / 2 },
- NULL);
+   .tv_nsec = fill_duration / 2 },
+   NULL);
 
-   while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == 
EINTR)
-   ;
+   n_periodic_reports = 0;
 
-   igt_assert_neq(len, -1);
+   /* Because of the race condition between notification of new
+* reports and reports landing in memory, we need to rely on
+* timestamps to figure whether we've read enough of them.
+*/
+   while (((last_timestamp - first_timestamp) * oa_period) < 
(fill_duration / 2)) {
 
-   igt_assert(len > report_size * n_full_oa_reports * 0.45);
-   igt_assert(len < report_size * n_full_oa_reports * 0.55);
+   igt_debug("dts=%u elapsed=%lu duration=%lu\n",
+ last_timestamp - first_timestamp,
+ (last_timestamp - first_timestamp) * 
oa_period,
+ fill_duration / 2);
 
-   overflow_seen = false;
-   for (offset = 0; offset < len; offset += header->size) {
-   header = (void *)(buf + offset);
+   while ((len = read(stream_fd, buf, buf_size)) == -1 && 
errno == EINTR)
+   ;
 
-   if (header->type == DRM_I915_PERF_RECORD_OA_BUFFER_LOST)
-   overflow_seen = true;
+   igt_assert_neq(len, -1);
+
+   for (int offset = 0; offset < len; offset += 
header->size) {
+   uint32_t *report;
+   double previous_tick_per_period;
+
+   header = (void *) (buf + offset);
+   report = (void *) (header + 1);
+
+   switch (header->type) {
+   case DRM_I915_PERF_RECORD_OA_REPORT_LOST:
+   igt_debug("report loss, trying 
again\n");
+

[Intel-gfx] [PATCH v3 11/12] tests/perf: estimate number of blocking/polling based on time spent

2017-08-23 Thread Lionel Landwerlin

Blocking & polling tests define an amount of time to spend in the test
and then estimate the number of syscalls that should successfully
return. The problem is that while running the test we might spend
slightly more time than initiallly planned. This change estimates the
number of syscalls based on time spent after the fact.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 42 +-
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 9f12da40..266d422f 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2373,7 +2373,8 @@ test_blocking(void)
DRM_I915_PERF_PROP_OA_EXPONENT, oa_exponent,
};
struct drm_i915_perf_open_param param = {
-   .flags = I915_PERF_FLAG_FD_CLOEXEC,
+   .flags = I915_PERF_FLAG_FD_CLOEXEC |
+   I915_PERF_FLAG_DISABLED,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
@@ -2398,16 +2399,17 @@ test_blocking(void)
 */
int min_iterations = (test_duration_ns / (oa_period + 600ull));
 
-   int64_t start;
+   int64_t start, end;
int n = 0;
 
stream_fd = __perf_open(drm_fd, ¶m);
 
times(&start_times);
 
-   igt_debug("tick length = %dns, test duration = %"PRIu64"ns, min iter. = 
%d, max iter. = %d\n",
+   igt_debug("tick length = %dns, test duration = %"PRIu64"ns, min iter. = 
%d,"
+ " estimated max iter. = %d, oa_period = %"PRIu64"ns\n",
  (int)tick_ns, test_duration_ns,
- min_iterations, max_iterations);
+ min_iterations, max_iterations, oa_period);
 
/* In the loop we perform blocking polls while the HW is sampling at
 * ~25Hz, with the expectation that we spend most of our time blocked
@@ -2426,8 +2428,13 @@ test_blocking(void)
 * floor(real_stime)).
 *
 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+*
+* Also enable the stream just before poll/read to minimize
+* the error delta.
 */
-   for (start = get_time(); (get_time() - start) < test_duration_ns; /* 
nop */) {
+   start = get_time();
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+   for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop 
*/) {
struct drm_i915_perf_record_header *header;
bool timer_report_read = false;
bool non_timer_report_read = false;
@@ -2469,6 +2476,12 @@ test_blocking(void)
n++;
}
 
+   /* Updated the maximum of iterations based on the time spent
+* in the loop.
+*/
+   max_iterations = (end - start) / oa_period + 1;
+   igt_debug("adjusted max iter. = %d\n", max_iterations);
+
times(&end_times);
 
/* Using nanosecond units is fairly silly here, given the tick in-
@@ -2525,6 +2538,7 @@ test_polling(void)
};
struct drm_i915_perf_open_param param = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
+   I915_PERF_FLAG_DISABLED |
I915_PERF_FLAG_FD_NONBLOCK,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
@@ -2549,7 +2563,7 @@ test_polling(void)
 * to check for data and giving some time to read().
 */
int min_iterations = (test_duration_ns / (oa_period + 600ull));
-   int64_t start;
+   int64_t start, end;
int n = 0;
 
stream_fd = __perf_open(drm_fd, ¶m);
@@ -2577,8 +2591,13 @@ test_polling(void)
 * floor(real_stime)).
 *
 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+*
+* Also enable the stream just before poll/read to minimize
+* the error delta.
 */
-   for (start = get_time(); (get_time() - start) < test_duration_ns; /* 
nop */) {
+   start = get_time();
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+   for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop 
*/) {
struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
struct drm_i915_perf_record_header *header;
bool timer_report_read = false;
@@ -2626,8 +2645,7 @@ test_polling(void)
if (header->type == 
DRM_I915_PERF_RECORD_SAMPLE) {
uint32_t *report = (void *)(header + 1);
 
-   if (oa_report_is_periodic(oa_exponent,
- report))
+   if (oa_report_is_periodic(oa_exponent, 
report))
timer_report_read = true;
else

[Intel-gfx] [PATCH v3 09/12] tests/perf: add Kabylake support

2017-08-23 Thread Lionel Landwerlin

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index 59cd50aa..b7d9f96d 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -,8 +,23 @@ init_sys_info(void)
} else if (IS_BROXTON(devid)) {
test_set_uuid = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
timestamp_frequency = 1920;
-   } else
+   } else if (IS_KABYLAKE(devid)) {
+   switch (intel_gt(devid)) {
+   case 1:
+   test_set_uuid = 
"baa3c7e4-52b6-4b85-801e-465a94b746dd";
+   break;
+   case 2:
+   test_set_uuid = 
"f1792f32-6db2-4b50-b4b2-557128f1688d";
+   break;
+   default:
+   igt_debug("unsupported Kabylake GT size\n");
+   return false;
+   }
+   timestamp_frequency = 1200;
+   } else {
+   igt_debug("unsupported GT\n");
return false;
+   }
 
gp.param = I915_PARAM_EU_TOTAL;
gp.value = &n_eus;
-- 
2.14.1

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[Intel-gfx] [PATCH v3 06/12] tests/perf: rework oa-exponent test

2017-08-23 Thread Lionel Landwerlin

New issues that were discovered while making the tests work on Gen8+ :

 - we need to measure timings between periodic reports and discard all
   other kind of reports

 - it seems periodicity of the reports can be affected outside of RC6
   (frequency change), we can detect this by looking at the amount of
   clock cycles per timestamp deltas

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 734 ---
 1 file changed, 600 insertions(+), 134 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index ca69440d..e54a14ed 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -306,6 +307,25 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static bool
+timestamp_delta_within(uint32_t delta,
+  uint32_t expected_delta,
+  uint32_t margin)
+{
+   return delta >= (expected_delta - margin) &&
+  delta <= (expected_delta + margin);
+}
+
+static bool
+double_value_within(double value,
+   double expected,
+   double percent_margin)
+{
+   return value >= (expected - expected * percent_margin / 100.0) &&
+  value <= (expected + expected * percent_margin / 100.0);
+
+}
+
 static void
 __perf_close(int fd)
 {
@@ -472,6 +492,20 @@ gen8_read_report_ticks(uint32_t *report, enum 
drm_i915_oa_format format)
return report[3];
 }
 
+static void
+gen8_read_report_clock_ratios(uint32_t *report,
+ uint32_t *slice_freq_mhz,
+ uint32_t *unslice_freq_mhz)
+{
+   uint32_t unslice_freq = report[0] & 0x1ff;
+   uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+   uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+   uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+   *slice_freq_mhz = (slice_freq * 1) / 1000;
+   *unslice_freq_mhz = (unslice_freq * 1) / 1000;
+}
+
 static const char *
 gen8_read_report_reason(const uint32_t *report)
 {
@@ -494,29 +528,6 @@ gen8_read_report_reason(const uint32_t *report)
return "unknown";
 }
 
-static bool
-oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
-{
-   if (IS_HASWELL(devid)) {
-   /* For Haswell we don't have a documented report reason field
-* (though empirically report[0] bit 10 does seem to correlate
-* with a timer trigger reason) so we instead infer which
-* reports are timer triggered by checking if the least
-* significant bits are zero and the exponent bit is set.
-*/
-   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
-
-   if ((report[1] & oa_exponent_mask) != (1 << oa_exponent))
-   return true;
-   } else {
-   if ((report[0] >> OAREPORT_REASON_SHIFT) &
-   OAREPORT_REASON_TIMER)
-   return true;
-   }
-
-   return false;
-}
-
 static uint64_t
 timebase_scale(uint32_t u32_delta)
 {
@@ -563,6 +574,29 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   /* For Haswell we don't have a documented report reason field
+* (though empirically report[0] bit 10 does seem to correlate
+* with a timer trigger reason) so we instead infer which
+* reports are timer triggered by checking if the least
+* significant bits are zero and the exponent bit is set.
+*/
+   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
+
+   if ((report[1] & oa_exponent_mask) == (1 << oa_exponent))
+   return true;
+   } else {
+   if ((report[0] >> OAREPORT_REASON_SHIFT) &
+   OAREPORT_REASON_TIMER)
+   return true;
+   }
+
+   return false;
+}
+
 static bool
 oa_report_ctx_is_valid(uint32_t *report)
 {
@@ -578,6 +612,128 @@ oa_report_ctx_is_valid(uint32_t *report)
igt_assert(!"reached");
 }
 
+static uint32_t
+oa_report_get_ctx_id(uint32_t *report)
+{
+   if (!oa_report_ctx_is_valid(report))
+   return 0x;
+   return report[2];
+}
+
+static double
+oa_reports_tick_per_period(uint32_t *report0, uint32_t *report1)
+{
+   if (intel_gen(devid) < 8)
+   return 0.0;
+
+   /* Measure the number GPU tick delta to timestamp delta. */
+   return (double) (report1[3] - report0[3]) /
+  (double) (report1[1] - report0

[Intel-gfx] [PATCH v3 12/12] tests/perf: prevent power management to kick in when necessary

2017-08-23 Thread Lionel Landwerlin

Some of our tests measure that the OA unit produces reports at
expected time intervals (as configured through the PERF_OPEN
ioctl). It turns out the power management plays a role in the decision
of the OA unit to write reports to memory. Under normal circumstances
we don't really mind if the unit misses one report here or there, but
for our tests it makes pretty difficult to verify whether we've made a
mistake in the configuration.

To work around this, let's prevent power management to kick in by
holding /dev/cpu_dma_latency opened for the following tests :

  - blocking
  - polling
  - buffer-fill
  - oa-exponents

Many thanks to Chris Wilson for suggesting this!

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 64 ++--
 1 file changed, 41 insertions(+), 23 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 266d422f..ea348161 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -288,6 +288,7 @@ static bool hsw_undefined_a_counters[45] = {
 static bool gen8_undefined_a_counters[45];
 
 static int drm_fd = -1;
+static int pm_fd = -1;
 static int stream_fd = -1;
 static uint32_t devid;
 static int card = -1;
@@ -331,21 +332,38 @@ __perf_close(int fd)
 {
close(fd);
stream_fd = -1;
+
+   if (pm_fd >= 0) {
+   close(pm_fd);
+   pm_fd = -1;
+   }
 }
 
 static int
-__perf_open(int fd, struct drm_i915_perf_open_param *param)
+__perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm)
 {
int ret;
+   int32_t pm_value = 0;
 
if (stream_fd >= 0)
__perf_close(stream_fd);
+   if (pm_fd >= 0) {
+   close(pm_fd);
+   pm_fd = -1;
+   }
 
ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
 
igt_assert(ret >= 0);
errno = 0;
 
+   if (prevent_pm) {
+   pm_fd = open("/dev/cpu_dma_latency", O_RDWR);
+   igt_assert(pm_fd >= 0);
+
+   igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), 
sizeof(pm_value));
+   }
+
return ret;
 }
 
@@ -1257,7 +1275,7 @@ test_system_wide_paranoid(void)
 
igt_drop_root();
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
__perf_close(stream_fd);
}
 
@@ -1314,7 +1332,7 @@ test_invalid_oa_metric_set_id(void)
 
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_metric_set_id;
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
__perf_close(stream_fd);
 
/* There's no valid default OA metric set ID... */
@@ -1348,7 +1366,7 @@ test_invalid_oa_format_id(void)
 
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_oa_format;
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
__perf_close(stream_fd);
 
/* There's no valid default OA format... */
@@ -1512,7 +1530,7 @@ open_and_read_2_oa_reports(int format_id,
.properties_ptr = to_user_pointer(properties),
};
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
 
read_2_oa_reports(format_id, exponent,
  oa_report0, oa_report1, timer_only);
@@ -1918,7 +1936,7 @@ test_oa_exponents(void)
  oa_exponent_to_ns(exponent) / 1000.0,
  oa_exponent_to_ns(exponent) / (1000.0 * 
1000.0));
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, true /* 
prevent_pm */);
 
/* Right after opening the OA stream, read a
 * first timestamp as way to filter previously
@@ -2193,7 +2211,7 @@ test_invalid_oa_exponent(void)
.properties_ptr = to_user_pointer(properties),
};
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
 
__perf_close(stream_fd);
 
@@ -2247,7 +2265,7 @@ test_low_oa_exponent_permissions(void)
igt_fork(child, 1) {
igt_drop_root();
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
__perf_close(stream_fd);
}
 
@@ -2313,7 +2331,7 @@ test_per_context_mode_unprivileged(void)
 
properties[1] = ctx_id;
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   stream_fd = __perf_open(drm_fd, ¶m, false);
__perf_close(stream_fd);
 
drm_intel_gem_context_destroy(context);
@@ -2402,7 +2420,7 @@ test_blocking(void)
int64_t start, end;
int n = 0;
 
-   stream_fd = __perf_open(drm_fd, ¶m);
+   st

[Intel-gfx] [PATCH igt v2] igt/pm_rpm: Use libc 'ftw' rather than opencoding our own filetree walk

2017-08-23 Thread Chris Wilson

By using ftw, we avoid the issue of having to handle directory recursion
ourselves and can focus on the test of checking the reading a
sysfs/debugfs does not break runtime suspend. In the process, disregard
errors when opening the individual files as they may fail for other
reasons.

v2: Bracket the file open/close with the wait_for_suspended() tests.
Whilst the fd is open, it may be keeping the device awake, e.g.
i915_forcewake_user.

Signed-off-by: Chris Wilson 
---
 lib/igt_debugfs.c | 50 +-
 lib/igt_debugfs.h |  1 +
 lib/igt_sysfs.c   | 41 +++--
 lib/igt_sysfs.h   |  1 +
 tests/pm_rpm.c| 91 ---
 5 files changed, 108 insertions(+), 76 deletions(-)

diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index ee1f0f54..84066ab8 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -127,38 +127,38 @@ const char *igt_debugfs_mount(void)
 }
 
 /**
- * igt_debugfs_dir:
+ * igt_debugfs_path:
  * @device: fd of the device
+ * @path: buffer to store path
+ * @pathlen: len of @path buffer.
  *
- * This opens the debugfs directory corresponding to device for use
- * with igt_sysfs_get() and related functions.
+ * This finds the debugfs directory corresponding to @device.
  *
  * Returns:
- * The directory fd, or -1 on failure.
+ * The directory path, or NULL on failure.
  */
-int igt_debugfs_dir(int device)
+char *igt_debugfs_path(int device, char *path, int pathlen)
 {
struct stat st;
const char *debugfs_root;
-   char path[200];
int idx;
 
if (fstat(device, &st)) {
igt_debug("Couldn't stat FD for DRM device: %s\n", 
strerror(errno));
-   return -1;
+   return NULL;
}
 
if (!S_ISCHR(st.st_mode)) {
igt_debug("FD for DRM device not a char device!\n");
-   return -1;
+   return NULL;
}
 
debugfs_root = igt_debugfs_mount();
 
idx = minor(st.st_rdev);
-   snprintf(path, sizeof(path), "%s/dri/%d/name", debugfs_root, idx);
+   snprintf(path, pathlen, "%s/dri/%d/name", debugfs_root, idx);
if (stat(path, &st))
-   return -1;
+   return NULL;
 
if (idx >= 64) {
int file, name_len, cmp_len;
@@ -166,17 +166,17 @@ int igt_debugfs_dir(int device)
 
file = open(path, O_RDONLY);
if (file < 0)
-   return -1;
+   return NULL;
 
name_len = read(file, name, sizeof(name));
close(file);
 
for (idx = 0; idx < 16; idx++) {
-   snprintf(path, sizeof(path), "%s/dri/%d/name",
+   snprintf(path, pathlen, "%s/dri/%d/name",
 debugfs_root, idx);
file = open(path, O_RDONLY);
if (file < 0)
-   return -1;
+   return NULL;
 
cmp_len = read(file, cmp, sizeof(cmp));
close(file);
@@ -186,10 +186,30 @@ int igt_debugfs_dir(int device)
}
 
if (idx == 16)
-   return -1;
+   return NULL;
}
 
-   snprintf(path, sizeof(path), "%s/dri/%d", debugfs_root, idx);
+   snprintf(path, pathlen, "%s/dri/%d", debugfs_root, idx);
+   return path;
+}
+
+/**
+ * igt_debugfs_dir:
+ * @device: fd of the device
+ *
+ * This opens the debugfs directory corresponding to device for use
+ * with igt_sysfs_get() and related functions.
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int igt_debugfs_dir(int device)
+{
+   char path[200];
+
+   if (!igt_debugfs_path(device, path, sizeof(path)))
+   return -1;
+
igt_debug("Opening debugfs directory '%s'\n", path);
return open(path, O_RDONLY);
 }
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index f1a76406..4fa49d21 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -32,6 +32,7 @@
 enum pipe;
 
 const char *igt_debugfs_mount(void);
+char *igt_debugfs_path(int device, char *path, int pathlen);
 
 int igt_debugfs_dir(int device);
 
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
index 15ed34be..d412610d 100644
--- a/lib/igt_sysfs.c
+++ b/lib/igt_sysfs.c
@@ -86,26 +86,26 @@ static int writeN(int fd, const char *buf, int len)
 }
 
 /**
- * igt_sysfs_open:
+ * igt_sysfs_path:
  * @device: fd of the device (or -1 to default to Intel)
+ * @path: buffer to fill with the sysfs path to the device
+ * @pathlen: length of @path buffer
  * @idx: optional pointer to store the card index of the opened device
  *
- * This opens the sysfs directory corresponding to device for use
- * with igt_sysfs_set() and igt_sysfs_get().
+ * This finds the sysfs directory corresponding to @device.
  *
  * Returns:
- * The directory fd, or -1 on failure.
+

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/pm_rpm: Use libc 'ftw' rather than opencoding our own filetree walk (rev2)

2017-08-23 Thread Patchwork

== Series Details ==

Series: igt/pm_rpm: Use libc 'ftw' rather than opencoding our own filetree walk 
(rev2)
URL   : https://patchwork.freedesktop.org/series/29141/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
42b42c99cd9d1b890807ae97cbd1c593396ae051 tests/Makefile.am: Wrap audio test 
with dedicated conditional

with latest DRM-Tip kernel build CI_DRM_2995
2964b2f40295 drm-tip: 2017y-08m-23d-13h-11m-32s UTC integration manifest

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:439s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:369s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:557s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:255s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:612s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:513s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:498s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:491s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:554s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:408s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_90/
___
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