[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop using long platform names on clock gating functions.

[Patchwork]

== Series Details ==

Series: drm/i915: Stop using long platform names on clock gating functions.
URL   : https://patchwork.freedesktop.org/series/29453/
State : success

== Summary ==

Series 29453v1 drm/i915: Stop using long platform names on clock gating 
functions.
https://patchwork.freedesktop.org/api/1.0/series/29453/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:444s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:555s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:254s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:517s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:519s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:509s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:609s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:448s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:430s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:510s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:606s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:521s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:466s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:509s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:407s

ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC 
integration manifest
ff16968a8d96 drm/i915: Stop using long platform names on clock gating functions.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5515/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Wa 1181: Fix Backlight issue
URL   : https://patchwork.freedesktop.org/series/29452/
State : success

== Summary ==

Series 29452v1 drm/i915/cnp: Wa 1181: Fix Backlight issue
https://patchwork.freedesktop.org/api/1.0/series/29452/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:442s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:362s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:555s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:251s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:523s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:527s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:441s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:614s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:444s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:428s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:510s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:597s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:490s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:506s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:546s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:402s

ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC 
integration manifest
7bf9c172e305 drm/i915/cnp: Wa 1181: Fix Backlight issue

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5514/
___
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[Intel-gfx] [PATCH] drm/i915: Stop using long platform names on clock gating functions.

[Rodrigo Vivi]

No functional changes.

Our code was only a bit messy with mixed style there so
let's clean up a bit using the short codenames for the platforms.

Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_pm.c | 44 -
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ff0b9f999f..4bdf1fb1df7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7981,7 +7981,7 @@ static void ilk_init_lp_watermarks(struct 
drm_i915_private *dev_priv)
 */
 }
 
-static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 {
uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
 
@@ -8264,7 +8264,7 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
@@ -8285,7 +8285,7 @@ static void cannonlake_init_clock_gating(struct 
drm_i915_private *dev_priv)
   SARBUNIT_CLKGATE_DIS);
 }
 
-static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
gen9_init_clock_gating(dev_priv);
 
@@ -8304,7 +8304,7 @@ static void kabylake_init_clock_gating(struct 
drm_i915_private *dev_priv)
   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
gen9_init_clock_gating(dev_priv);
 
@@ -8317,7 +8317,7 @@ static void skylake_init_clock_gating(struct 
drm_i915_private *dev_priv)
   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
+static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
enum pipe pipe;
 
@@ -8375,7 +8375,7 @@ static void broadwell_init_clock_gating(struct 
drm_i915_private *dev_priv)
   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
-static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
+static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
ilk_init_lp_watermarks(dev_priv);
 
@@ -8429,7 +8429,7 @@ static void haswell_init_clock_gating(struct 
drm_i915_private *dev_priv)
lpt_init_clock_gating(dev_priv);
 }
 
-static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 {
uint32_t snpcr;
 
@@ -8526,7 +8526,7 @@ static void ivybridge_init_clock_gating(struct 
drm_i915_private *dev_priv)
gen6_check_mch_setup(dev_priv);
 }
 
-static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
+static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* WaDisableEarlyCull:vlv */
I915_WRITE(_3D_CHICKEN3,
@@ -8606,7 +8606,7 @@ static void valleyview_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
-static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
+static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* WaVSRefCountFullforceMissDisable:chv */
/* WaDSRefCountFullforceMissDisable:chv */
@@ -8666,7 +8666,7 @@ static void g4x_init_clock_gating(struct drm_i915_private 
*dev_priv)
g4x_disable_trickle_feed(dev_priv);
 }
 
-static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
 {
I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
I915_WRITE(RENCLK_GATE_D2, 0);
@@ -8680,7 +8680,7 @@ static void crestline_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 }
 
-static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
 {
I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
   I965_RCC_CLOCK_GATE_DISABLE |
@@ -8766,35 +8766,35 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = 
cannonlake_init_clock_gating;
+   dev_priv->display.init_clock_gating = cnl_init_clock_gating;

[Intel-gfx] [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue

[Rodrigo Vivi]

This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.

During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.

The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.

The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.

Cc: Arthur J Runyan 
Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 11 ++-
 drivers/gpu/drm/i915/intel_pm.c | 27 +--
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c59c590e45c4..31b1b1dfb754 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7474,11 +7474,12 @@ enum {
 #define  FDI_RX_PHASE_SYNC_POINTER_EN  (1<<0)
 #define FDI_RX_CHICKEN(pipe)   _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, 
_FDI_RXB_CHICKEN)
 
-#define SOUTH_DSPCLK_GATE_D_MMIO(0xc2020)
-#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
-#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
-#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
-#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
+#define SOUTH_DSPCLK_GATE_D_MMIO(0xc2020)
+#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE(1<<30)
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE   (1<<29)
+#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
+#define  CNP_PWM_CGE_GATING_DISABLE(1<<13)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE(1<<12)
 
 /* CPU: FDI_TX */
 #define _FDI_TXA_CTL0x60100
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88bbbc44c00d..5a4b41ea0c3a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+   if (!HAS_PCH_CNP(dev_priv))
+   return;
+
+   /* Wa #1181 */
+   I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+}
+
 static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+   cnp_init_clock_gating(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct 
drm_i915_private *dev_priv)
   SARBUNIT_CLKGATE_DIS);
 }
 
+static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+   cnp_init_clock_gating(dev_priv);
+   gen9_init_clock_gating(dev_priv);
+
+   /* WaFbcNukeOnHostModify:cfl */
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+}
+
 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
gen9_init_clock_gating(dev_priv);
@@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-   /* WaFbcNukeOnHostModify:kbl,cfl */
+   /* WaFbcNukeOnHostModify:kbl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
@@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = 
cannonlake_init_clock_gating;
+   else if (IS_COFFEELAKE(dev_priv))
+   dev_priv->display.init_clock_gating = 
coffeelake_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
-   else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+   else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = 
kabylake_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-- 
2.13.2

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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/gem_exec_reuse: Adds cleanup at the end of test.

[Patchwork]

== Series Details ==

Series: tests/gem_exec_reuse: Adds cleanup at the end of test.
URL   : https://patchwork.freedesktop.org/series/29447/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw)

shard-hswtotal:2230 pass:1231 dwarn:0   dfail:0   fail:17  skip:982 
time:9703s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_114/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/gem_exec_reuse: Adds cleanup at the end of test.

[Patchwork]

== Series Details ==

Series: tests/gem_exec_reuse: Adds cleanup at the end of test.
URL   : https://patchwork.freedesktop.org/series/29447/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d937dd7997059bc2801095ffb0c50f646da1ab01 docs: Add user documentation about 
audio support

with latest DRM-Tip kernel build CI_DRM_3012
ee53909d971d drm-tip: 2017y-08m-28d-15h-03m-59s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:555s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:526s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:521s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:444s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:447s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:429s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:510s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:595s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:519s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:485s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:437s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:480s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:404s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_114/
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[Intel-gfx] [PATCH v2 2/2] drm/i915/guc : Decouple logs from submission

[Sujaritha Sundaresan]

The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.

v2: Decoupling ads together with logs
v2: Group initialization of GuC objects


Cc: Michal Wajdeczko 
Cc: Oscar Mateo 
Cc: Anusha Srivatsa 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sujaritha Sundaresan 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
 drivers/gpu/drm/i915/intel_uc.c| 140 ++---
 drivers/gpu/drm/i915/intel_uc.h|   6 +-
 3 files changed, 134 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
  * represents in-order queue. The kernel driver packs ring tail pointer and an
  * ELSP context descriptor dword into Work Item.
  * See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
  */
 
 static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
 }
 
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
 {
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies 
*policies)
policies->is_valid = 1;
 }
 
-static int guc_ads_create(struct intel_guc *guc)
-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   struct i915_vma *vma;
-   struct page *page;
-   /* The ads obj includes the struct itself and buffers passed to GuC */
-   struct {
-   struct guc_ads ads;
-   struct guc_policies policies;
-   struct guc_mmio_reg_state reg_state;
-   u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
-   } __packed *blob;
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-   u32 base;
-
-   GEM_BUG_ON(guc->ads_vma);
-
-   vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
-   if (IS_ERR(vma))
-   return PTR_ERR(vma);
-
-   guc->ads_vma = vma;
-
-   page = i915_vma_first_page(vma);
-   blob = kmap(page);
-
-   /* GuC scheduling policies */
-   guc_policies_init(>policies);
-
-   /* MMIO reg state */
-   for_each_engine(engine, dev_priv, id) {
-   blob->reg_state.white_list[engine->guc_id].mmio_start =
-   engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
-   /* Nothing to be saved or restored for now. */
-   blob->reg_state.white_list[engine->guc_id].count = 0;
-   }
-
-   /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
-   blob->ads.golden_context_lrca =
-   dev_priv->engine[RCS]->status_page.ggtt_offset;
-
-   for_each_engine(engine, dev_priv, id)
-   blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
-   base = guc_ggtt_offset(vma);
-   blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
-   blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
-   blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
-   kunmap(page);
-
-   return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
-   i915_vma_unpin_and_release(>ads_vma);
-}
-
 /*
  * Set up the memory resources to be shared with the GuC (via the GGTT)
  * at firmware loading time.
  */
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
 {
-   struct intel_guc *guc = _priv->guc;

[Intel-gfx] [PATCH v2 1/2] drm/i915/guc : Removing enable_guc_loading module

[Sujaritha Sundaresan]

We currently have two module parameters that control GuC: "enable_guc_loading" 
and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need 
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC, which is 
every time we have a HuC (but all platforms with HuC have a GuC and viceversa).

v2: Unify seq_puts messages, correcting inconsistencies (Michal)
v2: Clarifying the commit message (Anusha)

Cc: Michal Wajdeczko 
Cc: Anusha Srivatsa 
Cc: Oscar Mateo 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sujaritha Sundaresan 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 18 +++---
 drivers/gpu/drm/i915/i915_drv.c|  4 +-
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 15 -
 drivers/gpu/drm/i915/intel_guc_loader.c| 50 ++---
 drivers/gpu/drm/i915/intel_guc_log.c   |  6 +-
 drivers/gpu/drm/i915/intel_huc.c   | 14 ++---
 drivers/gpu/drm/i915/intel_uc.c| 90 ++
 drivers/gpu/drm/i915/intel_uc.h|  3 +-
 9 files changed, 97 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7cc53c2..9396de0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1612,7 +1612,7 @@ static int i915_fbc_status(struct seq_file *m, void 
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
 
if (!HAS_FBC(dev_priv)) {
-   seq_puts(m, "FBC unsupported on this chipset\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -1779,7 +1779,7 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
 
if (!HAS_LLC(dev_priv)) {
-   seq_puts(m, "unsupported on this chipset\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -2339,7 +2339,7 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
 
if (!HAS_GUC(dev_priv)){
-   seq_puts(m, "No HuC support in HW\n");
+   seq_puts(m, "not supported\n");
return 0;
}

@@ -2375,7 +2375,7 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
u32 tmp, i;
 
if (!HAS_GUC(dev_priv)){
-   seq_puts(m, "No GuC supprot in HW\n");
+   seq_puts(m, "not supported\n");
return 0;
}

@@ -2476,7 +2476,7 @@ static bool check_guc_submission(struct seq_file *m)
const struct intel_guc *guc = _priv->guc;
 
if (!guc->execbuf_client) {
-   seq_printf(m, "GuC submission %s\n",
+   seq_printf(m,
   HAS_GUC(dev_priv) ?
   "disabled" :
   "not supported");
@@ -2666,7 +2666,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
bool enabled = false;
 
if (!HAS_PSR(dev_priv)) {
-   seq_puts(m, "PSR not supported\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -2819,7 +2819,7 @@ static int i915_runtime_pm_status(struct seq_file *m, 
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
 
if (!HAS_RUNTIME_PM(dev_priv))
-   seq_puts(m, "Runtime power management not supported\n");
+   seq_puts(m, "not supported\n");
 
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3639,7 +3639,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
-   seq_puts(m, "\tDRRS Supported : No");
+   seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
 }
@@ -5039,4 +5039,4 @@ int i915_debugfs_connector_add(struct drm_connector 
*connector)
connector, _panel_fops);
 
return 0;
-}
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 00594dc..1c8d136 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,7 +1046,7 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
 
-   intel_guc_sanitize_submission(dev_priv);
+   intel_uc_sanitize_options(dev_priv);
 

[Intel-gfx] [PATCH i-g-t] tests/gem_exec_reuse: Adds cleanup at the end of test.

[Antonio Argenziano]

This patch introduces a fixture at the end of the test to destroy
objects that have been created and stop the hang detector.

Cc: Chris Wilson 

Signed-off-by: Antonio Argenziano 
---
 tests/gem_exec_reuse.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/tests/gem_exec_reuse.c b/tests/gem_exec_reuse.c
index cdfa9783..db26e57c 100644
--- a/tests/gem_exec_reuse.c
+++ b/tests/gem_exec_reuse.c
@@ -234,4 +234,11 @@ igt_main
for (n = 0; n < ncontexts; n++)
gem_context_destroy(no.fd, contexts[n]);
}
+
+   igt_fixture {
+   igt_stop_hang_detector();
+
+   gem_close(no.fd, no.batch);
+   close(no.fd);
+   }
 }
-- 
2.14.1

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Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries

[Rogozhkin, Dmitry V]

On Wed, 2017-08-23 at 20:22 +0200, Peter Zijlstra wrote:
> On Wed, Aug 23, 2017 at 05:51:38PM +, Rogozhkin, Dmitry V wrote:
> 
> > Anyhow, returning to the metrics i915 exposes. Some metrics are just
> > exposure of some counters supported already inside i915 PMU which do not
> > require any special sampling: at any given moment you can request the
> > counter value (these are interrupts counts, i915 power consumption).
> 
> > Other metrics are similar to the ever-existing which I just described,
> > but they require activation for i915 to start to count them - this is
> > done on the event initialization (these are engine busy stats).
> 
> Right, so depending on how expensive this activation is and if it can be
> done without scheduling, there are two options:
> 
>  1) activate/deactivate from pmu::start()/pmu::stop()
>  2) activate/deactivate from pmu::event_init()/event->destroy() and
> disregard all counting between pmu::stop() and pmu::start().
> 
> > Finally, there is a third group which require sampling counting: they
> > are needed to be initialized and i915 pmu starts an internal timer to
> > count these values (these are some engines characteristics referenced
> > in the code as QUEUED, SEMA, WAIT).
> 
> So uncore PMUs can't really do sampling. That is, perf defines sampling
> as interrupting the relevant task and then providing things like the
> %RIP value at interrupt time. Since uncore activity cannot be associated
> with any one task, no sampling allowed.
> 
> Now, I'm thinking that what i915 does is slightly different, it doesn't
> provide registers to read out the counter state, but instead
> periodically writes state snapshots into some memory buffer, right?
> 
> That's a bit tricky, maybe the best fit would be what PPC HV 24x7 does.
> They create an event-group, that is a set of counters that are
> co-scheduled, matching the set of counters they get from the HV
> interface (or a subset) and then sys_read() will use a TXN_READ to
> group-read the entire thing at once. In your case it could consume the
> last state snapshot instead of request one (or wait for the next,
> whatever works best).
> 
> Would that work?

Hi Peter,

I have updated my fixes to Tvrtko's PMU, they are here:
https://patchwork.freedesktop.org/series/28842/, and I started to check
whether we will be able to cover all the use cases for this PMU which we
had in mind. Here I have some concerns and further questions.

So, as soon as I registered PMU with the perf_invalid_context, i.e. as
an uncore PMU, I got the effect that metrics from our PMU are available
under root only. This happens since we fall to the following case
described in 'man perf_event_open': "A pid == -1 and cpu >= 0 setting is
per-CPU and measures all processes on the specified CPU.  Per-CPU events
need  the  CAP_SYS_ADMIN  capability  or
a /proc/sys/kernel/perf_event_paranoid value of less than 1."

This a trouble point for us... So, could you, please, clarify:
1. How PMU API is positioned? It is for debug purposes only or it can be
used in the end-user release applications to monitor system activity and
make some decisions based on that?
2. How applications can access uncore PMU metrics from non-privileged
applications?
3. Is that a strong requirement to restrict uncore PMU metrics reporting
to privileged applications or this can be relaxed?


I understand why restriction was relevant in the time when only CPU
level were available: system-wide were expensive, but I don't quite
understand why these restrictions are in place now for uncore PMUs when
they actually report metrics right away. Is that just a remnant of
CPU-only times and no one needed this to be changed? Can this be changed
and uncore metrics allowed to be accessed from general applications?


Regards,
Dmitry.

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Re: [Intel-gfx] [RFC v2 2/3] drm/i915/pmu: serve global events and support perf stat

[Rogozhkin, Dmitry V]

Peter, any comments?

On Wed, 2017-08-23 at 23:38 +, Rogozhkin, Dmitry V wrote:
> On Wed, 2017-08-23 at 08:26 -0700, Dmitry Rogozhkin wrote:
> > +static cpumask_t i915_pmu_cpumask = CPU_MASK_CPU0;
> 
> 
> Peter, this hardcoding of cpumask to use CPU0 works, but should I
> implement something smarter or this will be sufficient? I see that
> cstate.c you have pointed me to tries to track CPUs going online/offline
> and migrates PMU context to another CPU if selected one went offline.
> Should I follow this way?
> 
> If I should track CPUs going online/offline, then I have questions:
> 1. How I should register tracking callbacks? I see that cstate.c
> registers CPUHP_AP_PERF_X86_CSTATE_STARTING and
> CPUHP_AP_PERF_X86_CSTATE_ONLINE, uncore.c registers
> CPUHP_AP_PERF_X86_UNCORE_ONLINE. What I should use? I incline to UNCORE.
> 2. If I will register for, say UNCORE, then how double registrations
> will be handled if both uncore.c and i915.c will register callbacks? Any
> conflict here?
> 3. What I should pass as 2nd argument? Will "perf/x86/intel/i915:online"
> be ok?
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] lib: Add some syncobj helpers (v2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] lib: Add some syncobj helpers (v2)
URL   : https://patchwork.freedesktop.org/series/29439/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453

fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453

shard-hswtotal:2300 pass:1232 dwarn:0   dfail:0   fail:18  skip:1050 
time:9674s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_113/shards.html
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Re: [Intel-gfx] [PATCH i-g-t 1/4] lib: Add some syncobj helpers (v2)

[Daniel Vetter]

On Mon, Aug 28, 2017 at 02:10:12PM -0700, Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand 

gtkdocs would be lovely for this, if I can motivate you ...

Thanks, Daniel

> ---
>  lib/Makefile.sources |   2 +
>  lib/igt_syncobj.c| 207 
> +++
>  lib/igt_syncobj.h|  71 ++
>  3 files changed, 280 insertions(+)
>  create mode 100644 lib/igt_syncobj.c
>  create mode 100644 lib/igt_syncobj.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 53fdb54..692fe30 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -83,6 +83,8 @@ lib_source_list =   \
>   uwildmat/uwildmat.c \
>   igt_kmod.c  \
>   igt_kmod.h  \
> + igt_syncobj.c   \
> + igt_syncobj.h   \
>   $(NULL)
>  
>  .PHONY: version.h.tmp
> diff --git a/lib/igt_syncobj.c b/lib/igt_syncobj.c
> new file mode 100644
> index 000..5caef2a
> --- /dev/null
> +++ b/lib/igt_syncobj.c
> @@ -0,0 +1,207 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +
> +#include "igt.h"
> +#include "igt_syncobj.h"
> +
> +static int
> +__syncobj_create(int fd, uint32_t *handle, uint32_t flags)
> +{
> + struct drm_syncobj_create create = { 0 };
> + int err = 0;
> +
> + create.flags = flags;
> + if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, ))
> + err = -errno;
> + *handle = create.handle;
> + return err;
> +}
> +
> +uint32_t
> +syncobj_create(int fd, uint32_t flags)
> +{
> + uint32_t handle;
> + igt_assert_eq(__syncobj_create(fd, , flags), 0);
> + igt_assert(handle);
> + return handle;
> +}
> +
> +static int
> +__syncobj_destroy(int fd, uint32_t handle)
> +{
> + struct drm_syncobj_destroy destroy = { 0 };
> + int err = 0;
> +
> + destroy.handle = handle;
> + if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, ))
> + err = -errno;
> + return err;
> +}
> +
> +void
> +syncobj_destroy(int fd, uint32_t handle)
> +{
> + igt_assert_eq(__syncobj_destroy(fd, handle), 0);
> +}
> +
> +int
> +__syncobj_handle_to_fd(int fd, struct drm_syncobj_handle *args)
> +{
> + int err = 0;
> + if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, args))
> + err = -errno;
> + return err;
> +}
> +
> +int
> +syncobj_handle_to_fd(int fd, uint32_t handle, uint32_t flags)
> +{
> + struct drm_syncobj_handle args = { 0 };
> + args.handle = handle;
> + args.flags = flags;
> + igt_assert_eq(__syncobj_handle_to_fd(fd, ), 0);
> + igt_assert(args.fd >= 0);
> + return args.fd;
> +}
> +
> +int
> +__syncobj_fd_to_handle(int fd, struct drm_syncobj_handle *args)
> +{
> + int err = 0;
> + if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, args))
> + err = -errno;
> + return err;
> +}
> +
> +uint32_t
> +syncobj_fd_to_handle(int fd, int syncobj_fd, uint32_t flags)
> +{
> + struct drm_syncobj_handle args = { 0 };
> + args.fd = syncobj_fd;
> + args.flags = flags;
> + igt_assert_eq(__syncobj_fd_to_handle(fd, ), 0);
> + igt_assert(args.handle > 0);
> + return args.handle;
> +}
> +
> +void
> +syncobj_import_sync_file(int fd, uint32_t handle, int sync_file)
> +{
> + struct drm_syncobj_handle args = { 0 };
> + args.handle = handle;
> + args.fd = sync_file;
> + args.flags = DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE;
> + igt_assert_eq(__syncobj_fd_to_handle(fd, ), 0);
> +}
> +
> +int
> +__syncobj_wait(int fd, struct local_syncobj_wait *args)
> +{
> + int err = 0;
> + if (drmIoctl(fd, LOCAL_IOCTL_SYNCOBJ_WAIT, args))
> + err = -errno;
> + return err;
> +}
> +
> +int
> +syncobj_wait_err(int fd, uint32_t *handles, uint32_t count,
> +   

Re: [Intel-gfx] [i-g-t PATCH 00/10] tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h

[Daniel Vetter]

On Mon, Aug 28, 2017 at 03:19:52PM +0300, Jani Nikula wrote:
> There's little point in duplicating the efforts of describing the same
> data in two places. This series lets us use the verbatim copy of the
> intel_vbt_defs.h from kernel. Going forward, we should add the changes
> in kernel first, then copy the header over to igt.
> 
> If we need local tweaks, we can still have them in intel_bios.h, and
> indeed we'll still have some after this series.

I assume the end result matches what we now have in the kernel. Might be
good practice to reference the sha1 of the kernel commit (needs to be a
stable sha1, not drm-tip ofc) when resyncing in the future. On the series:

Acked-by: Daniel Vetter 
> 
> BR,
> Jani.
> 
> Jani Nikula (10):
>   tools/intel_lid: use local register definition
>   tools/intel_vbt_decode: remove unused definitions from intel_bios.h
>   tools/intel_vbt_decode: clean up struct lvds_dvo_timing
>   tools/intel_vbt_decode: start migrating to kernel intel_vbt_defs.h
>   tools/intel_vbt_decode: migrate timing dumping to kernel struct
>   tools/intel_vbt_decode: migrate child device dumping to kernel struct
>   tools/intel_vbt_decode: migrate psr dumping to kernel struct
>   tools/intel_vbt_decode: migrate edp dumping to kernel struct
>   tools/intel_vbt_decode: migrate child device type bits decoding to
> kernel defs
>   tools/intel_vbt_defs: migrate backlight dumping to kernel struct
> 
>  tools/intel_bios.h   | 760 +--
>  tools/intel_lid.c|   5 +-
>  tools/intel_vbt_decode.c | 180 +-
>  tools/intel_vbt_defs.h   | 897 
> +++
>  4 files changed, 996 insertions(+), 846 deletions(-)
>  create mode 100644 tools/intel_vbt_defs.h
> 
> -- 
> 2.11.0
> 
> ___
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Re: [Intel-gfx] [PATCH 0/6] Adding NV12 support

[Daniel Vetter]

On Mon, Aug 28, 2017 at 04:22:16PM +0530, Vidya Srinivas wrote:
> This patch series is adding NV12 support for Broxton display after
> rebasing on latest drm-intel-nightly. Initial series of the patches
> can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
> 
> Previous revision history:
> Patches were initial reviewed last when floated but
> currently there was a design change with respect to
> - the way fb offset is handled
> - the way rotation is handled
> Rebase of the current NV12 patch series has been done as per the
> current changes on drm-intel-nightly.
> Review comments from Ville (12th June 2017) have been addressed
> Review comments from Clinton A Taylor (7th July 2017) have been
> addressed
> Review comments from Clinton A Taylor (10th July 2017) have been
> addressed. Had missed out tested-by/reviewed-by in the patches.
> Fixed that error in this series.
> Review comments from Ville (11th July 2017) addressed.
> Review comments from Paauwe, Bob (29th July 2017) addressed.
> 
> Update from last rev:
> Rebased the series as Ville's patches are merged. Previously,
> this series included those floating patches.
> 
> Chandra Konduru (6):
>   drm/i915: Set scaler mode for NV12
>   drm/i915: Update format_is_yuv() to include NV12
>   drm/i915: Upscale scaler max scale for NV12
>   drm/i915: Add NV12 as supported format for primary plane
>   drm/i915: Add NV12 as supported format for sprite plane
>   drm/i915: Add NV12 support to intel_framebuffer_init

Needs serious work on the plane scaling igt (it's atm all broken, and
doesn't test any atomic interactions).

Then this needs serious work on the nv12 plane igts (which don't yet
exist).

Then this probably needs pile more igts to test interactions between
everything (e.g. rotation, ...).

In short: This needs itgs. Lots of them :-)

Before those exist, and before we've tracked down the bug in the existing
code you're building on it imo makes no sense to start reviewing these
here.

Thanks, Daniel

> 
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_atomic.c  |  8 -
>  drivers/gpu/drm/i915/intel_display.c | 67 
> +---
>  drivers/gpu/drm/i915/intel_drv.h |  3 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 34 ++
>  5 files changed, 92 insertions(+), 21 deletions(-)
> 
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Remove excess indent in intel_finish_reset() caught by sparse

[Daniel Vetter]

On Mon, Aug 28, 2017 at 11:46:04AM +0100, Chris Wilson wrote:
>   CHECK   drivers/gpu/drm/i915/intel_display.c
> drivers/gpu/drm/i915/intel_display.c:3753 intel_finish_reset() warn: 
> inconsistent indenting
> 
> Signed-off-by: Chris Wilson 

Ooops, I think that was me :-(

Reviewed-by: Daniel Vetter 

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 7cd392f2cd94..7317e1d1c1e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3750,8 +3750,8 @@ void intel_finish_reset(struct drm_i915_private 
> *dev_priv)
>   if (!gpu_reset_clobbers_display(dev_priv)) {
>   /* for testing only restore the display */
>   ret = __intel_display_resume(dev, state, ctx);
> - if (ret)
> - DRM_ERROR("Restoring old state failed with 
> %i\n", ret);
> + if (ret)
> + DRM_ERROR("Restoring old state failed with %i\n", ret);
>   } else {
>   /*
>* The display has been reset as well,
> -- 
> 2.14.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] lib: Add some syncobj helpers (v2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] lib: Add some syncobj helpers (v2)
URL   : https://patchwork.freedesktop.org/series/29439/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d937dd7997059bc2801095ffb0c50f646da1ab01 docs: Add user documentation about 
audio support

with latest DRM-Tip kernel build CI_DRM_3012
ee53909d971d drm-tip: 2017y-08m-28d-15h-03m-59s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:460s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:449s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:362s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:557s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:251s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:530s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:525s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:521s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:442s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:617s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:428s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:512s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:476s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:483s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:599s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:531s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:475s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:491s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:447s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:518s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:413s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_113/
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[Intel-gfx] [PULL] drm-misc-next-fixes

[Sean Paul]

Hi Dave,
Only one change in -misc-next-fixes as well. Simply a rename to use consistent
types across ioctl structs.

drm-misc-next-fixes-2017-08-28:
UAPI Changes:
- Rename u32 to __u32 in struct drm_format_modifier_blob (Lionel)

Cc: Lionel Landwerlin 

Cheers, Sean


The following changes since commit 0e8841ec7ee5b1ffe416c3be7743985b1896ec00:

  Merge airlied/drm-next into drm-misc-next (2017-08-18 10:52:44 -0400)

are available in the git repository at:

  git://anongit.freedesktop.org/git/drm-misc tags/drm-misc-next-fixes-2017-08-28

for you to fetch changes up to f44d85389e17b2e960620c1c6d89bda978a11f2b:

  drm: rename u32 in __u32 in uapi (2017-08-25 10:07:30 +0100)


UAPI Changes:
- Rename u32 to __u32 in struct drm_format_modifier_blob (Lionel)

Cc: Lionel Landwerlin 


Lionel Landwerlin (1):
  drm: rename u32 in __u32 in uapi

 include/uapi/drm/drm_mode.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

-- 
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[Intel-gfx] [PULL] drm-misc-fixes

[Sean Paul]

Hi Dave,
Apologies for the late pull req. This is a regression fix to a patch committed 
in
Feb which prevents writes to an incorrect register.

Andrzej: once this lands in Linus' tree, please send it over to stable@ so they
can add it to the stable releases of the affected trees.

drm-misc-fixes-2017-08-28:
Driver Changes:
- bridge/sii8620: Fix out-of-bounds write to incorrect register

Cc: Maciej Purski 
Cc: Andrzej Hajda 

Cheers, Sean


The following changes since commit fe4600a548f2763dec91b3b27a1245c370ceee2a:

  drm: Release driver tracking before making the object available again 
(2017-08-22 16:03:43 +0300)

are available in the git repository at:

  git://anongit.freedesktop.org/git/drm-misc tags/drm-misc-fixes-2017-08-28

for you to fetch changes up to 79964dbaf662229253b281c42e82e2675a9d3b80:

  drm/bridge/sii8620: Fix memory corruption (2017-08-24 19:06:32 +0200)


Driver Changes:
- bridge/sii8620: Fix out-of-bounds write to incorrect register

Cc: Maciej Purski 
Cc: Andrzej Hajda 


Maciej Purski (1):
  drm/bridge/sii8620: Fix memory corruption

 drivers/gpu/drm/bridge/sil-sii8620.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
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[Intel-gfx] [PATCH i-g-t 2/4] tests/syncobj: Convert the basic test over to the helpers

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 tests/syncobj_basic.c | 77 +--
 1 file changed, 19 insertions(+), 58 deletions(-)

diff --git a/tests/syncobj_basic.c b/tests/syncobj_basic.c
index a7a6742..0a304f1 100644
--- a/tests/syncobj_basic.c
+++ b/tests/syncobj_basic.c
@@ -22,6 +22,7 @@
  */
 
 #include "igt.h"
+#include "igt_syncobj.h"
 #include 
 #include 
 #include "drm.h"
@@ -48,14 +49,11 @@ static void
 test_bad_handle_to_fd(int fd)
 {
struct drm_syncobj_handle handle;
-   int ret;
 
handle.handle = 0xdeadbeef;
handle.flags = 0;
 
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
-
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_handle_to_fd(fd, ), -EINVAL);
 }
 
 /* fd to handle a bad fd */
@@ -63,14 +61,11 @@ static void
 test_bad_fd_to_handle(int fd)
 {
struct drm_syncobj_handle handle;
-   int ret;
 
handle.fd = -1;
handle.flags = 0;
 
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, );
-
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), -EINVAL);
 }
 
 /* fd to handle an fd but not a sync file one */
@@ -78,58 +73,47 @@ static void
 test_illegal_fd_to_handle(int fd)
 {
struct drm_syncobj_handle handle;
-   int ret;
 
handle.fd = fd;
handle.flags = 0;
 
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, );
-
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), -EINVAL);
 }
 
 static void
 test_bad_flags_fd_to_handle(int fd)
 {
struct drm_syncobj_handle handle = { 0 };
-   int ret;
 
handle.flags = 0xdeadbeef;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, );
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), -EINVAL);
 }
 
 static void
 test_bad_flags_handle_to_fd(int fd)
 {
struct drm_syncobj_handle handle = { 0 };
-   int ret;
 
handle.flags = 0xdeadbeef;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_handle_to_fd(fd, ), -EINVAL);
 }
 
 static void
 test_bad_pad_handle_to_fd(int fd)
 {
struct drm_syncobj_handle handle = { 0 };
-   int ret;
 
handle.pad = 0xdeadbeef;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_handle_to_fd(fd, ), -EINVAL);
 }
 
 static void
 test_bad_pad_fd_to_handle(int fd)
 {
struct drm_syncobj_handle handle = { 0 };
-   int ret;
 
handle.pad = 0xdeadbeef;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, );
-   igt_assert(ret == -1 && errno == EINVAL);
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), -EINVAL);
 }
 
 
@@ -138,24 +122,17 @@ test_bad_pad_fd_to_handle(int fd)
 static void
 test_bad_destroy_pad(int fd)
 {
-   struct drm_syncobj_create create = { 0 };
struct drm_syncobj_destroy destroy;
int ret;
 
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, );
-
-   destroy.handle = create.handle;
+   destroy.handle = syncobj_create(fd, 0);
destroy.pad = 0xdeadbeef;
 
ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, );
 
igt_assert(ret == -1 && errno == EINVAL);
 
-   destroy.handle = create.handle;
-   destroy.pad = 0;
-
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, );
-   igt_assert(ret == 0);
+   syncobj_destroy(fd, destroy.handle);
 }
 
 static void
@@ -176,34 +153,18 @@ test_bad_create_flags(int fd)
 static void
 test_valid_cycle(int fd)
 {
-   int ret;
-   struct drm_syncobj_create create = { 0 };
-   struct drm_syncobj_handle handle = { 0 };
-   struct drm_syncobj_destroy destroy = { 0 };
-   uint32_t first_handle;
-
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, );
-   igt_assert(ret == 0);
+   uint32_t first_handle, second_handle;
+   int syncobj_fd;
 
-   first_handle = create.handle;
+   first_handle = syncobj_create(fd, 0);
+   syncobj_fd = syncobj_handle_to_fd(fd, first_handle, 0);
+   second_handle = syncobj_fd_to_handle(fd, syncobj_fd, 0);
+   close(syncobj_fd);
 
-   handle.handle = create.handle;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
-   igt_assert(ret == 0);
-   handle.handle = 0;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, );
-   close(handle.fd);
-   igt_assert(ret == 0);
+   igt_assert(first_handle != second_handle);
 
-   igt_assert(handle.handle != first_handle);
-
-   destroy.handle = handle.handle;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, );
-   igt_assert(ret == 0);
-
-   destroy.handle = first_handle;
-   ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, );
-   igt_assert(ret == 0);
+   syncobj_destroy(fd, 

[Intel-gfx] [PATCH i-g-t 3/4] tests/syncobj: Add some wait and reset tests (v7)

[Jason Ekstrand]

This adds both trivial error-checking tests as well as more complex
tests which actually test whether or not waits do what they're supposed
to do.  They only currently work on i915 but it should be simple to hook
them up for other drivers by simply implementing the little function
pointer hook provided at the top for triggering a syncobj.

v2:
 - Actually add the reset tests.
v3:
 - Only do one execbuf for trigger
 - Use do_ioctl and do_ioctl_err
 - Better check for syncobj support
 - Add local_/LOCAL_ defines of things
 - Use a timer instead of a pthread
v4:
 - Use ioctl wrappers
 - Use VGEM instead of i915
 - Combine a bunch of the simple tests into one function
v5:
 - Combinatorially generate basic tests
 - Use sw_sync instead of using vgem directly
 - Add even more tests
v6:
 - Rebase on the new SYNCOBJ_RESET API
 - Add tests for SYNCOBJ_SIGNAL
v7:
 - Improve the signal and reset bad pad tests

Signed-off-by: Jason Ekstrand 

stuff
---
 tests/Makefile.sources |   1 +
 tests/syncobj_wait.c   | 915 +
 2 files changed, 916 insertions(+)
 create mode 100644 tests/syncobj_wait.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..430b637 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -230,6 +230,7 @@ TESTS_progs = \
prime_vgem \
sw_sync \
syncobj_basic \
+   syncobj_wait \
template \
tools_test \
vgem_basic \
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
new file mode 100644
index 000..02699af
--- /dev/null
+++ b/tests/syncobj_wait.c
@@ -0,0 +1,915 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "sw_sync.h"
+#include "igt_syncobj.h"
+#include 
+#include 
+#include 
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
+
+/* One tenth of a second */
+#define SHORT_TIME_NSEC 1ull
+
+#define NSECS_PER_SEC 10ull
+
+static uint64_t
+gettime_ns(void)
+{
+   struct timespec current;
+   clock_gettime(CLOCK_MONOTONIC, );
+   return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
+}
+
+static void
+sleep_nsec(uint64_t time_nsec)
+{
+   struct timespec t;
+   t.tv_sec = time_nsec / NSECS_PER_SEC;
+   t.tv_nsec = time_nsec % NSECS_PER_SEC;
+   igt_assert_eq(nanosleep(, NULL), 0);
+}
+
+static uint64_t
+short_timeout(void)
+{
+   return gettime_ns() + SHORT_TIME_NSEC;
+}
+
+static int
+syncobj_attach_sw_sync(int fd, uint32_t handle)
+{
+   struct drm_syncobj_handle;
+   int timeline, fence;
+
+   timeline = sw_sync_timeline_create();
+   fence = sw_sync_timeline_create_fence(timeline, 1);
+   syncobj_import_sync_file(fd, handle, fence);
+   close(fence);
+
+   return timeline;
+}
+
+static void
+syncobj_trigger(int fd, uint32_t handle)
+{
+   int timeline = syncobj_attach_sw_sync(fd, handle);
+   sw_sync_timeline_inc(timeline, 1);
+   close(timeline);
+}
+
+static timer_t
+set_timer(void (*cb)(union sigval), void *ptr, int i, uint64_t nsec)
+{
+timer_t timer;
+struct sigevent sev;
+struct itimerspec its;
+
+memset(, 0, sizeof(sev));
+sev.sigev_notify = SIGEV_THREAD;
+   if (ptr)
+   sev.sigev_value.sival_ptr = ptr;
+   else
+   sev.sigev_value.sival_int = i;
+sev.sigev_notify_function = cb;
+igt_assert(timer_create(CLOCK_MONOTONIC, , ) == 0);
+
+memset(, 0, sizeof(its));
+its.it_value.tv_sec = nsec / NSEC_PER_SEC;
+its.it_value.tv_nsec = nsec % NSEC_PER_SEC;
+igt_assert(timer_settime(timer, 0, , NULL) == 0);
+
+   return timer;
+}
+
+struct fd_handle_pair {
+   int fd;
+   uint32_t handle;
+};
+
+static void
+timeline_inc_func(union sigval 

[Intel-gfx] [PATCH i-g-t 4/4] syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED

[Jason Ekstrand]

---
 tests/syncobj_basic.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/tests/syncobj_basic.c b/tests/syncobj_basic.c
index 0a304f1..acc4a64 100644
--- a/tests/syncobj_basic.c
+++ b/tests/syncobj_basic.c
@@ -146,6 +146,16 @@ test_bad_create_flags(int fd)
igt_assert(ret == -1 && errno == EINVAL);
 }
 
+static void
+test_create_signaled(int fd)
+{
+   uint32_t syncobj = syncobj_create(fd, LOCAL_SYNCOBJ_CREATE_SIGNALED);
+
+   igt_assert_eq(syncobj_wait_err(fd, , 1, 0, 0), 0);
+
+   syncobj_destroy(fd, syncobj);
+}
+
 /*
  * currently don't do handle deduplication
  * test we get a different handle back.
@@ -215,6 +225,9 @@ igt_main
igt_subtest("bad-destroy-pad")
test_bad_destroy_pad(fd);
 
+   igt_subtest("create-signaled")
+   test_create_signaled(fd);
+
igt_subtest("test-valid-cycle")
test_valid_cycle(fd);
 
-- 
2.5.0.400.gff86faf

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[Intel-gfx] [PATCH i-g-t 1/4] lib: Add some syncobj helpers (v2)

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 lib/Makefile.sources |   2 +
 lib/igt_syncobj.c| 207 +++
 lib/igt_syncobj.h|  71 ++
 3 files changed, 280 insertions(+)
 create mode 100644 lib/igt_syncobj.c
 create mode 100644 lib/igt_syncobj.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 53fdb54..692fe30 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -83,6 +83,8 @@ lib_source_list = \
uwildmat/uwildmat.c \
igt_kmod.c  \
igt_kmod.h  \
+   igt_syncobj.c   \
+   igt_syncobj.h   \
$(NULL)
 
 .PHONY: version.h.tmp
diff --git a/lib/igt_syncobj.c b/lib/igt_syncobj.c
new file mode 100644
index 000..5caef2a
--- /dev/null
+++ b/lib/igt_syncobj.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+
+#include "igt.h"
+#include "igt_syncobj.h"
+
+static int
+__syncobj_create(int fd, uint32_t *handle, uint32_t flags)
+{
+   struct drm_syncobj_create create = { 0 };
+   int err = 0;
+
+   create.flags = flags;
+   if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, ))
+   err = -errno;
+   *handle = create.handle;
+   return err;
+}
+
+uint32_t
+syncobj_create(int fd, uint32_t flags)
+{
+   uint32_t handle;
+   igt_assert_eq(__syncobj_create(fd, , flags), 0);
+   igt_assert(handle);
+   return handle;
+}
+
+static int
+__syncobj_destroy(int fd, uint32_t handle)
+{
+   struct drm_syncobj_destroy destroy = { 0 };
+   int err = 0;
+
+   destroy.handle = handle;
+   if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, ))
+   err = -errno;
+   return err;
+}
+
+void
+syncobj_destroy(int fd, uint32_t handle)
+{
+   igt_assert_eq(__syncobj_destroy(fd, handle), 0);
+}
+
+int
+__syncobj_handle_to_fd(int fd, struct drm_syncobj_handle *args)
+{
+   int err = 0;
+   if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, args))
+   err = -errno;
+   return err;
+}
+
+int
+syncobj_handle_to_fd(int fd, uint32_t handle, uint32_t flags)
+{
+   struct drm_syncobj_handle args = { 0 };
+   args.handle = handle;
+   args.flags = flags;
+   igt_assert_eq(__syncobj_handle_to_fd(fd, ), 0);
+   igt_assert(args.fd >= 0);
+   return args.fd;
+}
+
+int
+__syncobj_fd_to_handle(int fd, struct drm_syncobj_handle *args)
+{
+   int err = 0;
+   if (drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, args))
+   err = -errno;
+   return err;
+}
+
+uint32_t
+syncobj_fd_to_handle(int fd, int syncobj_fd, uint32_t flags)
+{
+   struct drm_syncobj_handle args = { 0 };
+   args.fd = syncobj_fd;
+   args.flags = flags;
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), 0);
+   igt_assert(args.handle > 0);
+   return args.handle;
+}
+
+void
+syncobj_import_sync_file(int fd, uint32_t handle, int sync_file)
+{
+   struct drm_syncobj_handle args = { 0 };
+   args.handle = handle;
+   args.fd = sync_file;
+   args.flags = DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE;
+   igt_assert_eq(__syncobj_fd_to_handle(fd, ), 0);
+}
+
+int
+__syncobj_wait(int fd, struct local_syncobj_wait *args)
+{
+   int err = 0;
+   if (drmIoctl(fd, LOCAL_IOCTL_SYNCOBJ_WAIT, args))
+   err = -errno;
+   return err;
+}
+
+int
+syncobj_wait_err(int fd, uint32_t *handles, uint32_t count,
+uint64_t abs_timeout_nsec, uint32_t flags)
+{
+   struct local_syncobj_wait wait;
+
+   wait.handles = to_user_pointer(handles);
+   wait.timeout_nsec = abs_timeout_nsec;
+   wait.count_handles = count;
+   wait.flags = flags;
+   wait.first_signaled = 0;
+   wait.pad = 0;
+
+   return __syncobj_wait(fd, );
+}

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Patchwork]

== Series Details ==

Series: drm/i915: Clear local engine-needs-reset bit if in progress elsewhere
URL   : https://patchwork.freedesktop.org/series/29437/
State : warning

== Summary ==

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (shard-hsw)
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw)

shard-hswtotal:2230 pass:1230 dwarn:1   dfail:0   fail:17  skip:982 
time:9656s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5513/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Jeff McGee]

On Mon, Aug 28, 2017 at 08:44:48PM +0100, Chris Wilson wrote:
> Quoting jeff.mc...@intel.com (2017-08-28 20:25:30)
> > From: Jeff McGee 
> > 
> > If someone else is resetting the engine we should clear our own bit as
> > part of skipping that engine. Otherwise we will later believe that it
> > has not been reset successfully and then trigger full gpu reset. If the
> > other guy's reset actually fails, he will trigger the full gpu reset.
> 
> The reason we did continue on to the global reset was to serialise
> i915_handle_error() with the other thread. Not a huge issue, but a
> reasonable property to keep -- and we definitely want a to explain why
> only one reset at a time is important.
> 
> bool intel_engine_lock_reset() {
>   if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
> >i915->gpu_error.flags))
>   return true;
> 
>   intel_engine_wait_for_reset(engine);
The current code doesn't wait for the other thread to finish the reset, but
this would add that wait. Did you intend that as an additional change to
the current code? I don't think it is necessary. Each thread wants to
reset some subset of engines, so it seems the thread can safely exit as soon
as it knows each of those engines has been reset or is being reset as part
of another thread that got the lock first. If any of the threads fail to
reset an engine they "own", then full gpu reset is assured.
-Jeff

>   return false; /* somebody else beat us to the reset */
> }
> 
> void intel_engine_wait_for_reset() {
>   while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>   >i915->gpu_error.flags))
>   wait_on_bit(>i915->gpu_error.flags, I915_RESET_ENGINE + 
> engine->id,
>   TASK_UNINTERRUPTIBLE);
> }
> 
> It can also be used by selftests/intel_hangcheck.c, so let's refactor
> before we have 3 copies.
> -Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always wake the device to flush the GTT

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT
URL   : https://patchwork.freedesktop.org/series/29436/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2230 pass:1230 dwarn:0   dfail:0   fail:18  skip:982 
time:9646s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5511/shards.html
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Re: [Intel-gfx] [PATCH i-g-t v2 3/3] docs: Add user documentation about audio support

[Lyude Paul]

With some small typos I fixed (nothing major):

Reviewed-by: Lyude Paul 

I've already pushed the patches upstream, thanks!

On Mon, 2017-08-28 at 11:12 +0300, Paul Kocialkowski wrote:
> This introduces plain-text documentation about the audio test, aimed
> at
> users who wish to setup and run the audio tests.
> 
> Given the contents of this documentation, it felt more relevant to
> make
> it part of the tree instead of the API reference.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  docs/audio.txt | 45 +
>  1 file changed, 45 insertions(+)
>  create mode 100644 docs/audio.txt
> 
> diff --git a/docs/audio.txt b/docs/audio.txt
> new file mode 100644
> index ..158ad5d1
> --- /dev/null
> +++ b/docs/audio.txt
> @@ -0,0 +1,45 @@
> +Audio Support in IGT
> +
> +
> +This document provides information and instructions about audio
> support in IGT.
> +
> +Introduction
> +
> +
> +The audio test is aimed at testing the audio features of display
> connectors,
> +such as HDMI.
> +
> +Test setup
> +--
> +
> +The setup required for the audio test consists of using an HDMI-VGA
> adapter with
> +an audio-out 3.5 mm jack to extract the audio from the HDMI
> interface.
> +The audio-out jack is connected back to the device-under-test's
> line-in.
> +
> +Depending on the behavior of the adapter, it may be necessary to
> connect a
> +ghost VGA dongle to it (in order to emulate a connected display) to
> enable the
> +audio output. There are guides available detailing how to build
> these.
> +
> +When executed, the test will automatically send the test audio
> signal to all
> +ALSA audio HDMI outputs and record from the standard ALSA capture
> device.
> +
> +Configuration
> +-
> +
> +In order to deploy the test, ALSA controls have to be configured to
> set the
> +ALSA capture source to line-in. On Intel x86 systems, this can be
> achieved
> +with the following calls to the amixer utility:
> +# amixer sset Line 31 on
> +# amixer sset "Input Source" Line
> +
> +It is then useful to store the ALSA state permanently with the
> alsactl utility:
> +# alsactl store
> +
> +These settings can be restored with the alsactl utility:
> +# alsactl restore
> +
> +It is desirable to ensure that the alsa-restore and alsa-state
> systemd services
> +are enabled to do this job automatically, especially in the case of
> an
> +automated testing system:
> +# systemctl enable alsa-restore
> +# systemctl enable alsa-state
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Jeff McGee]

On Mon, Aug 28, 2017 at 12:41:58PM -0700, Michel Thierry wrote:
> On 28/08/17 12:25, jeff.mc...@intel.com wrote:
> >From: Jeff McGee 
> >
> >If someone else is resetting the engine we should clear our own bit as
> >part of skipping that engine. Otherwise we will later believe that it
> >has not been reset successfully and then trigger full gpu reset. If the
> >other guy's reset actually fails, he will trigger the full gpu reset.
> >
> 
> Did you hit this by manually setting wedged to 'x' ring repeatedly?
> 
I haven't actually reproduced it. Have just been looking at the code a
lot to try to develop reset for preemption enforcement. The implementation
will call i915_handle_error from another work item that can run concurrent
with hangcheck.

> >Signed-off-by: Jeff McGee 
> >---
> >  drivers/gpu/drm/i915/i915_irq.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_irq.c 
> >b/drivers/gpu/drm/i915/i915_irq.c
> >index 5d391e689070..575d618ccdbf 100644
> >--- a/drivers/gpu/drm/i915/i915_irq.c
> >+++ b/drivers/gpu/drm/i915/i915_irq.c
> >@@ -2711,8 +2711,10 @@ void i915_handle_error(struct drm_i915_private 
> >*dev_priv,
> > for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
> > BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
> > if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
> >- _priv->gpu_error.flags))
> >+ _priv->gpu_error.flags)) {
> >+engine_mask &= ~intel_engine_flag(engine);
> > continue;
> >+}
> > if (i915_reset_engine(engine, 0) == 0)
> > engine_mask &= ~intel_engine_flag(engine);
> >
> 
> Reviewed-by: Michel Thierry 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Patchwork]

== Series Details ==

Series: drm/i915: Clear local engine-needs-reset bit if in progress elsewhere
URL   : https://patchwork.freedesktop.org/series/29437/
State : success

== Summary ==

Series 29437v1 drm/i915: Clear local engine-needs-reset bit if in progress 
elsewhere
https://patchwork.freedesktop.org/api/1.0/series/29437/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:436s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:552s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:511s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:615s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:509s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:520s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:464s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:476s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:486s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:509s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:406s

ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC 
integration manifest
9ccbefee6663 drm/i915: Clear local engine-needs-reset bit if in progress 
elsewhere

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5513/
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Chris Wilson]

Quoting jeff.mc...@intel.com (2017-08-28 20:25:30)
> From: Jeff McGee 
> 
> If someone else is resetting the engine we should clear our own bit as
> part of skipping that engine. Otherwise we will later believe that it
> has not been reset successfully and then trigger full gpu reset. If the
> other guy's reset actually fails, he will trigger the full gpu reset.

The reason we did continue on to the global reset was to serialise
i915_handle_error() with the other thread. Not a huge issue, but a
reasonable property to keep -- and we definitely want a to explain why
only one reset at a time is important.

bool intel_engine_lock_reset() {
if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
  >i915->gpu_error.flags))
return true;

intel_engine_wait_for_reset(engine);
return false; /* somebody else beat us to the reset */
}

void intel_engine_wait_for_reset() {
while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>i915->gpu_error.flags))
wait_on_bit(>i915->gpu_error.flags, I915_RESET_ENGINE + 
engine->id,
TASK_UNINTERRUPTIBLE);
}

It can also be used by selftests/intel_hangcheck.c, so let's refactor
before we have 3 copies.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Michel Thierry]

On 28/08/17 12:25, jeff.mc...@intel.com wrote:

From: Jeff McGee 

If someone else is resetting the engine we should clear our own bit as
part of skipping that engine. Otherwise we will later believe that it
has not been reset successfully and then trigger full gpu reset. If the
other guy's reset actually fails, he will trigger the full gpu reset.



Did you hit this by manually setting wedged to 'x' ring repeatedly?


Signed-off-by: Jeff McGee 
---
  drivers/gpu/drm/i915/i915_irq.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e689070..575d618ccdbf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2711,8 +2711,10 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
-_priv->gpu_error.flags))
+_priv->gpu_error.flags)) {
+   engine_mask &= ~intel_engine_flag(engine);
continue;
+   }
  
  			if (i915_reset_engine(engine, 0) == 0)

engine_mask &= ~intel_engine_flag(engine);



Reviewed-by: Michel Thierry 
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[Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[jeff . mcgee]

From: Jeff McGee 

If someone else is resetting the engine we should clear our own bit as
part of skipping that engine. Otherwise we will later believe that it
has not been reset successfully and then trigger full gpu reset. If the
other guy's reset actually fails, he will trigger the full gpu reset.

Signed-off-by: Jeff McGee 
---
 drivers/gpu/drm/i915/i915_irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e689070..575d618ccdbf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2711,8 +2711,10 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
-_priv->gpu_error.flags))
+_priv->gpu_error.flags)) {
+   engine_mask &= ~intel_engine_flag(engine);
continue;
+   }
 
if (i915_reset_engine(engine, 0) == 0)
engine_mask &= ~intel_engine_flag(engine);
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Always wake the device to flush the GTT

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT
URL   : https://patchwork.freedesktop.org/series/29436/
State : success

== Summary ==

Series 29436v1 drm/i915: Always wake the device to flush the GTT
https://patchwork.freedesktop.org/api/1.0/series/29436/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:438s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:539s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:512s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:427s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:469s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:597s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:434s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:488s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:408s

ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC 
integration manifest
2dc5cdc900aa drm/i915: Always wake the device to flush the GTT

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5511/
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[Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Experimental patch for bxt/gem_pwrite.
---
 drivers/gpu/drm/i915/i915_gem.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 37fbc64d9ffe..4f6af401320c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -695,12 +695,11 @@ flush_write_domain(struct drm_i915_gem_object *obj, 
unsigned int flush_domains)
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-   if (intel_runtime_pm_get_if_in_use(dev_priv)) {
-   spin_lock_irq(_priv->uncore.lock);
-   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
-   spin_unlock_irq(_priv->uncore.lock);
-   intel_runtime_pm_put(dev_priv);
-   }
+   intel_runtime_pm_get(dev_priv);
+   spin_lock_irq(_priv->uncore.lock);
+   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+   spin_unlock_irq(_priv->uncore.lock);
+   intel_runtime_pm_put(dev_priv);
}
 
intel_fb_obj_flush(obj,
-- 
2.14.1

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Re: [Intel-gfx] [PATCH 3/4] drm/i915/bios: amend child device flags based on intel_vbt_decode

[Jani Nikula]

On Fri, 25 Aug 2017, Ville Syrjälä  wrote:
> On Fri, Aug 25, 2017 at 05:11:22PM +0300, Jani Nikula wrote:
>> Copy over some fields defined in the intel_vbt_decode tool. No
>> functional changes.
>> 
>> Cc: Ville Syrjälä 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/intel_vbt_defs.h | 9 +++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h 
>> b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> index 14623748b388..ea508ecc74b3 100644
>> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> @@ -380,7 +380,11 @@ struct child_device_config {
>>  } __packed;
>>  } __packed;
>>  
>> -u8 capabilities;
>> +u8 pipe_cap:2;
>> +u8 sdvo_stall:1;
>
> igt has a /* 158 */ comment here.
>
> Otherwise it all looks to match. For the series
> Reviewed-by: Ville Syrjälä 

Pushed the lot, thanks for the review. I took the liberty of adding the
comment while applying.

BR,
Jani.

>
>> +u8 hpd_status:2;
>> +u8 integrated_encoder:1;
>> +u8 capabilities_reserved:2;
>>  u8 dvo_wiring; /* See DEVICE_WIRE_* above */
>>  
>>  union {
>> @@ -390,7 +394,8 @@ struct child_device_config {
>>  
>>  u16 extended_type;
>>  u8 dvo_function;
>> -u8 flags2;  /* 195 */
>> +u8 dp_usb_type_c:1; /* 195 */
>> +u8 flags2_reserved:7;   /* 195 */
>>  u8 dp_gpio_index;   /* 195 */
>>  u16 dp_gpio_pin_num;/* 195 */
>>  u8 dp_iboost_level:4;   /* 196 */
>> -- 
>> 2.11.0

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h

[Patchwork]

== Series Details ==

Series: tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h
URL   : https://patchwork.freedesktop.org/series/29427/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:19  skip:982 
time:9638s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_111/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: warning for tests/chamelium: Let the Chamelium itself wait for a stable video input

[Patchwork]

== Series Details ==

Series: tests/chamelium: Let the Chamelium itself wait for a stable video input
URL   : https://patchwork.freedesktop.org/series/29432/
State : warning

== Summary ==

IGT patchset tested on top of latest successful build
60f6a12195395934f179d5ecc080353190d19a6c tests: chamelium: Eliminate reset when 
preparing output

with latest DRM-Tip kernel build CI_DRM_3011
5774a266e918 drm-tip: 2017y-08m-28d-14h-39m-13s UTC integration manifest

Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-fail -> PASS   (fi-glk-2a)
Subgroup basic-s4-devices:
skip   -> PASS   (fi-glk-2a)
Test gem_linear_blits:
Subgroup basic:
skip   -> PASS   (fi-glk-2a)
Test gem_render_linear_blits:
Subgroup basic:
skip   -> PASS   (fi-glk-2a)
Test gem_render_tiled_blits:
Subgroup basic:
skip   -> PASS   (fi-glk-2a)
Test gem_ringfill:
Subgroup basic-default:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-default-interruptible:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-default-forked:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-default-fd:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-default-hang:
skip   -> PASS   (fi-glk-2a)
Test gem_sync:
Subgroup basic-all:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-each:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-many-each:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-store-all:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-store-each:
skip   -> PASS   (fi-glk-2a)
Test gem_tiled_blits:
Subgroup basic:
skip   -> PASS   (fi-glk-2a)
Test gem_tiled_fence_blits:
Subgroup basic:
skip   -> PASS   (fi-glk-2a)
Test gem_wait:
Subgroup basic-busy-all:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-wait-all:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-await-all:
skip   -> PASS   (fi-glk-2a)
Test gem_workarounds:
Subgroup basic-read:
skip   -> PASS   (fi-glk-2a)
Test kms_busy:
Subgroup basic-flip-a:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-flip-b:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-flip-c:
skip   -> PASS   (fi-glk-2a)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
skip   -> PASS   (fi-glk-2a)
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
skip   -> PASS   (fi-glk-2a)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (fi-bdw-5557u)
incomplete -> PASS   (fi-bsw-n3050) fdo#101707
fail   -> PASS   (fi-glk-2a)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101707 https://bugs.freedesktop.org/show_bug.cgi?id=101707

fi-bdw-5557u total:279  pass:267  dwarn:1   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:441s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:565s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:517s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:534s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:516s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:443s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:617s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:450s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:509s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:476s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:279  

[Intel-gfx] [PATCH i-g-t] tests/chamelium: Let the Chamelium itself wait for a stable video input

[Paul Kocialkowski]

Before capturing video, the Chamelium will always wait for the video
input to be stable (and perform the FSM if it was not). This means that
there is no need to explicitly do it beforehand.

When the receiver needs to be reset, the call will result in a timeout,
after which the follow-up call to capture the video will perform the FSM
that resets it. Skipping the explicit wait for video input stable allows
the Chamelium to perform the FSM directly, which saves valuable time.

Removing the associated call does not negatively impact the execution of
the CRC and frame comparison tests either.

Signed-off-by: Paul Kocialkowski 
---
 tests/chamelium.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/tests/chamelium.c b/tests/chamelium.c
index 484bb537..e3d81357 100644
--- a/tests/chamelium.c
+++ b/tests/chamelium.c
@@ -474,9 +474,6 @@ enable_output(data_t *data,
if (chamelium_port_get_type(port) == DRM_MODE_CONNECTOR_VGA)
usleep(25);
 
-   chamelium_port_wait_video_input_stable(data->chamelium, port,
-  HOTPLUG_TIMEOUT);
-
drmModeFreeConnector(connector);
 }
 
-- 
2.14.0

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Re: [Intel-gfx] [PATCH 00/12] drm/i915: Fix up the CCS code

[Ville Syrjälä]

On Mon, Aug 28, 2017 at 02:35:54PM +0100, Daniel Stone wrote:
> Hi Daniel,
> 
> On 25 August 2017 at 18:17, Daniel Vetter  wrote:
> > Which of these do we need to cherry-pick over to -next-fixes? There's no
> > annotations about that. If the answer is "most" I'm leaning towards
> > disabling CCS for 4.14, minimal set would be ideal (and first in the patch
> > series).
> 
> My opinion below; tl;dr is that I don't think most of them are
> super-critical. Ville obviously has a far stronger opinion than me on
> the shape of the code, so I'm fine with this series, which seems to
> mostly be a merge back of the delta between whatever Ville's latest
> branch was, and whatever the last patchset Ben sent out was.
> 
> >> Ville Syrjälä (12):
> >>   drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear
> >> offset
> 
> This should land into -fixes. I trust Ville that it has no UABI
> impact, but seems like something to be very consistent on.

It does change the uabi. That's the whole point. What was merged doesn't
agree with what userspace wants. So this we want in definitely so that
we don't end up exposing the wrong uabi in any released kernel.

> 
> >>   drm/i915: Skip fence alignemnt check for the CCS plane
> 
> Not sure if this is -fixes material really, just a cleanup?

It makes the kernel less likely to reject the fb entirely. So
without this userspace has to be rather careful where it places
the aux surface. I would include this as well.

> 
> >>   drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for
> >> CCS
> 
> Not -fixes, performance optimisation.

We hope. It does change the layout of the compressed data though so if
our testcases try to generate compressed data with the CPU it'll not go
well if the test assumes the wrong hash mode. I would include this as
well so that we don't end up in any kind of a mess later when we try to
change it.

So the patches were more or less sorted in priority order, and we want
at least 01,02 and maybe 03.

> 
> >>   drm/i915: Add a comment exlaining CCS hsub/vsub
> 
> Seems harmless to land to -fixes.
> 
> >>   drm/i915: Nuke a pointless unreachable()
> 
> Ditto.
> 
> >>   drm/i915: Add the missing Y/Yf modifiers for SKL+ sprites
> 
> Per my previous reply, NAK to landing at all, since DDB/WM allocation
> seems too broken for it to work.
> 
> >>   drm/i915: Clean up the sprite modifier checks
> 
> Fine with this, but doesn't seem like -fixes material.
> 
> >>   drm/i915: Add CCS capability for sprites
> 
> NAK, same reason as Y/Yf.
> 
> >>   drm/i915: Allow up to 32KB stride on SKL+ "sprites"
> 
> Again doesn't seem like -fixes necessarily?
> 
> >>   drm: Fix modifiers_property kernel doc
> 
> Good for -fixes.
> 
> >>   drm: Check that the plane supports the request format+modifier combo
> 
> Good for core (not Intel) -fixes.
> 
> >>   drm/i915: Remove the pipe/plane ID checks from
> >> skl_check_ccs_aux_surface()
> 
> Seems fine but probably not -fixes material; land in Intel after a merge?
> 
> Cheers,
> Daniel

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Beef up of Beef up the IPS vs. CRC workaround (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Beef up of Beef up the IPS vs. CRC workaround (rev2)
URL   : https://patchwork.freedesktop.org/series/29425/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1230 dwarn:0   dfail:0   fail:18  skip:982 
time:9636s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5509/shards.html
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Re: [Intel-gfx] [PATCH v2] drm/i915: Beef up of Beef up the IPS vs. CRC workaround

[Ville Syrjälä]

On Mon, Aug 28, 2017 at 03:18:10PM +0300, Marta Lofstedt wrote:
> Commit 6e644626945c7c1a7f4d4f83b806b898297846d0 was

I fixed that commit reference to use the correct format and pushed the
patch to dinq. Thanks for fixing my mess.

> supposed to solve below bug. However, the patch I tested
> is not the same as the one that got merged.
> With this addition the test pass.
> 
> V2: removed unused: "struct intel_crtc *intel_crtc"
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101664
> 
> Signed-off-by: Marta Lofstedt 
> ---
>  drivers/gpu/drm/i915/intel_pipe_crc.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 4e22bb927fed..96043a51c1bf 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -919,7 +919,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, 
> const char *source_name,
>  {
>   struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>   struct intel_pipe_crc *pipe_crc = _priv->pipe_crc[crtc->index];
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   enum intel_display_power_domain power_domain;
>   enum intel_pipe_crc_source source;
>   u32 val = 0; /* shut up gcc */
> @@ -951,8 +950,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, 
> const char *source_name,
>   else if ((IS_HASWELL(dev_priv) ||
> IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
>   hsw_pipe_A_crc_wa(dev_priv, false);
> -
> - hsw_enable_ips(intel_crtc);
>   }
>  
>   pipe_crc->skipped = 0;
> -- 
> 2.11.0

-- 
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Re: [Intel-gfx] [PATCH 18/23] drm/i915/selftests: huge page tests

[Chris Wilson]

Excuse the piggy-backing, the original never arrived!

+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+   enum i915_map_type level;
+   int err;
+
+   for (level = I915_MAP_WB; level <= I915_MAP_WC; level++) {
+   u32 *map, offset;
+
+   if (level == I915_MAP_WB)
+   err = i915_gem_object_set_to_cpu_domain(obj, false);
+   else
+   err = i915_gem_object_set_to_wc_domain(obj, false);
+   if (err)
+   return err;
+
+   unmap_mapping(obj);
+   map = i915_gem_object_pin_map(obj, level);
+   if (IS_ERR(map))
+   return PTR_ERR(map);
+
+   for (offset = dword; offset < obj->base.size/sizeof(u32);
+offset += DWORDS_PER_PAGE) {
+   if (map[offset] != val) {
+   pr_err("map[%u] = %u, expected %u\n",
+  offset, map[offset], val);
+   err = -EINVAL;
+   goto out_close;
+   }
+   }
+
+   i915_gem_object_unpin_map(obj);
+   }
+
+   return 0;
+
+out_close:
+   i915_gem_object_unpin_map(obj);
+
+   return err;
+}

We are testing the GTT layout, so we only need a single CPU check. Using
WC is going to be terrible in performance, and we really don't need to
vmap the whole thing either as we are just reading one dword per page.
Just a kmap and clflush (with a wait_for_rendering) is going to be a lot
quicker.

+static struct i915_vma *
+gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
+{
+   struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+   const int gen = INTEL_GEN(vma->vm->i915);
+   unsigned int count = vma->size >> PAGE_SHIFT;
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *batch;
+   unsigned int size;
+   u32 *cmd;
+   int n;
+   int err;
+
+   size = 1 + 4 * count * sizeof(u32);

Should be (1 + 4 * count) * sizeof(u32); Likelihood of it mattering, 0.

+static int gpu_write(struct i915_vma *vma,
+struct i915_gem_context *ctx,
+u32 dword,
+u32 value)
+{
...
+   err = rq->engine->emit_bb_start(rq,
+   batch->node.start, batch->node.size,
+   flags);
+   if (err)
+   goto err_request;
+
+   i915_vma_move_to_active(vma, rq, 0);

Should pass EXEC_OBJECT_WRITE. 

+   reservation_object_lock(vma->resv, NULL);
+   reservation_object_add_excl_fence(vma->resv, >fence);
+   reservation_object_unlock(vma->resv);

And remind me to finish moving this export to i915_vma_move_to_active(),
just need to be sure that we can't create any dependency loops.

+
+err_request:
+   __i915_add_request(rq, err == 0);
+
+   return err;
+}

+static int igt_write_huge(struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   unsigned long supported = INTEL_INFO(i915)->page_size_mask;
+   struct i915_gem_context *ctx = i915->kernel_context;
+   struct i915_address_space *vm = ctx->ppgtt ? >ppgtt->base : 
>ggtt.base;
+   unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
+   struct i915_vma *vma;
+   int bit, last;
+   int err;
+
+   GEM_BUG_ON(obj->base.size != SZ_2M);
+
+   err = i915_gem_object_pin_pages(obj);
+   if (err)
+   return err;
+
+   /* We want to run the test even if the platform doesn't support huge gtt
+* pages -- our only requirement is that we were able to allocate a
+* "huge-page".
+*/
+   if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_2M) {
+   pr_info("Unable to allocate huge-page, finishing test early\n");
+   goto out_unpin;
+   }
+
+   vma = i915_vma_instance(obj, vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto out_unpin;
+   }
+
+   last = ilog2(I915_GTT_PAGE_SIZE_2M);
+
+   for_each_set_bit(bit, , last + 1) {
+   IGT_TIMEOUT(end_time);
+   unsigned int page_size = BIT(bit);
+   u32 max = vm->total / I915_GTT_PAGE_SIZE_2M - 1;
+   u32 num;
+
+   /* Force the page size */
+   vma->page_sizes.sg = obj->mm.page_sizes.sg = page_size;
+
+   /* Try various offsets until we timeout -- we want to avoid
+* issues hidden by effectively always using offset = 0.
+*/
+   for_each_prime_number_from(num, 0, max) {
...
+
+   for (dword = 0; dword < DWORDS_PER_PAGE; ++dword) {

We want to focus on the GTT testing, so checking every offset in the page
is less important than checking the various GTT offsets.

If you use dword = 

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_chamelium: Remove any special handling for the connector FSM

[Paul Kocialkowski]

On Fri, 2017-08-04 at 17:10 +0300, Paul Kocialkowski wrote:
> No specific treatment should be required for handling the connector
> FSM,
> since the chamelium-side daemon will automatically send an HPD event
> to
> reset the source.
> 
> The event is sufficient to make the receiver on the chamelium consider
> the input as stable after it. On the other hand, toggling DPMS was
> found
> to sometimes confuse the receiver so that it does not consider the
> input
> as stable at any point. Doing nothing special instead works in all
> cases.
> 
> This issue can be witnessed with i915 when drm debugging is enabled
> and
> leads to DP frame-related tests failing on the test farm.

It turns out the receiver was (most likely) confused by the extra reset
that was taking place in enable_output.

Now that it was removed, DP FSM does not fail anymore in this case, so
let's keep this as-is and forget about this change.

> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/igt_chamelium.c | 113 ---
> -
>  1 file changed, 25 insertions(+), 88 deletions(-)
> 
> diff --git a/lib/igt_chamelium.c b/lib/igt_chamelium.c
> index dcd8855f..4cea5fdb 100644
> --- a/lib/igt_chamelium.c
> +++ b/lib/igt_chamelium.c
> @@ -209,57 +209,13 @@ void chamelium_destroy_frame_dump(struct
> chamelium_frame_dump *dump)
>   free(dump);
>  }
>  
> -struct fsm_monitor_args {
> - struct chamelium *chamelium;
> - struct chamelium_port *port;
> - struct udev_monitor *mon;
> -};
> -
> -/*
> - * Whenever resolutions or other factors change with the display
> output, the
> - * Chamelium's display receivers need to be fully reset in order to
> perform any
> - * frame-capturing related tasks. This requires cutting off the
> display then
> - * turning it back on, and is indicated by the Chamelium sending
> hotplug events
> - */
> -static void *chamelium_fsm_mon(void *data)
> -{
> - struct fsm_monitor_args *args = data;
> - drmModeConnector *connector;
> - int drm_fd = args->chamelium->drm_fd;
> -
> - /*
> -  * Wait for the chamelium to try unplugging the connector,
> otherwise
> -  * the thread calling chamelium_rpc will kill us
> -  */
> - igt_hotplug_detected(args->mon, 60);
> -
> - /*
> -  * Just in case the RPC call being executed returns before we
> complete
> -  * the FSM modesetting sequence, so we don't leave the
> display in a bad
> -  * state.
> -  */
> - pthread_setcancelstate(PTHREAD_CANCEL_DISABLE, NULL);
> -
> - igt_debug("Chamelium needs FSM, handling\n");
> - connector = chamelium_port_get_connector(args->chamelium,
> args->port,
> -  false);
> - kmstest_set_connector_dpms(drm_fd, connector,
> DRM_MODE_DPMS_OFF);
> - kmstest_set_connector_dpms(drm_fd, connector,
> DRM_MODE_DPMS_ON);
> -
> - drmModeFreeConnector(connector);
> - return NULL;
> -}
> -
>  static xmlrpc_value *chamelium_rpc(struct chamelium *chamelium,
> -struct chamelium_port *fsm_port,
>  const char *method_name,
>  const char *format_str,
>  ...)
>  {
>   xmlrpc_value *res;
>   va_list va_args;
> - struct fsm_monitor_args monitor_args;
> - pthread_t fsm_thread_id;
>  
>   /* Cleanup the last error, if any */
>   if (chamelium->env.fault_occurred) {
> @@ -267,31 +223,12 @@ static xmlrpc_value *chamelium_rpc(struct
> chamelium *chamelium,
>   xmlrpc_env_init(>env);
>   }
>  
> - /* Unfortunately xmlrpc_client's event loop helpers are
> rather useless
> -  * for implementing any sort of event loop, since they
> provide no way
> -  * to poll for events other then the RPC response. This means
> in order
> -  * to handle the chamelium attempting FSM, we have to fork
> into another
> -  * thread and have that handle hotplugging displays
> -  */
> - if (fsm_port) {
> - monitor_args.chamelium = chamelium;
> - monitor_args.port = fsm_port;
> - monitor_args.mon = igt_watch_hotplug();
> - pthread_create(_thread_id, NULL,
> chamelium_fsm_mon,
> -_args);
> - }
> -
>   va_start(va_args, format_str);
>   xmlrpc_client_call2f_va(>env, chamelium->client,
>   chamelium->url, method_name,
> format_str, ,
>   va_args);
>   va_end(va_args);
>  
> - if (fsm_port) {
> - pthread_cancel(fsm_thread_id);
> - igt_cleanup_hotplug(monitor_args.mon);
> - }
> -
>   igt_assert_f(!chamelium->env.fault_occurred,
>"Chamelium RPC call failed: %s\n",
>chamelium->env.fault_string);
> @@ -310,7 +247,7 @@ static xmlrpc_value *chamelium_rpc(struct
> chamelium *chamelium,
>  void 

Re: [Intel-gfx] [PATCH v2 00/10] Improve robustness of the i915 perf tests

[Arkadiusz Hiler]

On Mon, Aug 28, 2017 at 02:33:13PM +0100, Lionel Landwerlin wrote:
> On 28/08/17 08:21, Arkadiusz Hiler wrote:
> > On Wed, Aug 23, 2017 at 10:43:08AM +0100, Lionel Landwerlin wrote:
> > > Hi all,
> > > 
> > > Here is an updated patch series containing mostly cleanups.
> > > 
> > > Cheers,
> > Hi,
> > 
> > Our CI hasn't pick this series up for a spin due to missing a "i-g-t" tag.
> > 
> > Direct quote from CONTRIBUTING file:
> > -
> > Please use --subject-prefix="PATCH i-g-t" so that i-g-t patches are easily
> > identified in the massive amount mails on intel-gfx. To ensure this is 
> > always
> > done, autogen.sh will run:
> > 
> > git config format.subjectprefix "PATCH i-g-t"
> > 
> > on its first invocation.
> > -
> > 
> > 
> If only there was a wrapper around git (much like chromium has git cl), it's
> too easy to get this stuff wrong when you want to send a v2 and you have to
> use --subject-prefix :/


Luckily there is, quote from man git-format-patch:


-v , --reroll-count=
Mark the series as the -th iteration of the topic. The output
filenames have v prepended to them, and the subject prefix
("PATCH" by default, but configurable via the --subject-prefix
option) has ` v` appended to it. E.g.  --reroll-count=4 may
produce v4-0001-add-makefile.patch file that has "Subject: [PATCH v4
1/20] Add makefile" in it.


I wasn't aware of that until recently I found as an usage example posted
on some internet forum and was really surprised it an option :-)

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: dspaddr_offset doesn't need to be 
more than local variable
URL   : https://patchwork.freedesktop.org/series/29429/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_display.o
drivers/gpu/drm/i915/intel_display.c: In function ‘intel_primary_plane_create’:
drivers/gpu/drm/i915/intel_display.c:13174:27: error: 
‘skylake_update_primary_plane’ undeclared (first use in this function)
   primary->update_plane = skylake_update_primary_plane;
   ^~~~
drivers/gpu/drm/i915/intel_display.c:13174:27: note: each undeclared identifier 
is reported only once for each function it appears in
drivers/gpu/drm/i915/intel_display.c:13175:28: error: 
‘skylake_disable_primary_plane’ undeclared (first use in this function)
   primary->disable_plane = skylake_disable_primary_plane;
^
scripts/Makefile.build:302: recipe for target 
'drivers/gpu/drm/i915/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] [PATCH 2/3] drm/i915: Unify skylake plane update

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 79 +---
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 5 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f922e2f..96eac33 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3534,83 +3534,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_ctl;
 }
 
-static void skylake_update_primary_plane(struct intel_plane *plane,
-const struct intel_crtc_state 
*crtc_state,
-const struct intel_plane_state 
*plane_state)
-{
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-   const struct drm_framebuffer *fb = plane_state->base.fb;
-   enum plane_id plane_id = plane->id;
-   enum pipe pipe = plane->pipe;
-   u32 plane_ctl = plane_state->ctl;
-   unsigned int rotation = plane_state->base.rotation;
-   u32 stride = skl_plane_stride(fb, 0, rotation);
-   u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-   u32 surf_addr = plane_state->main.offset;
-   int scaler_id = plane_state->scaler_id;
-   int src_x = plane_state->main.x;
-   int src_y = plane_state->main.y;
-   int src_w = drm_rect_width(_state->base.src) >> 16;
-   int src_h = drm_rect_height(_state->base.src) >> 16;
-   int dst_x = plane_state->base.dst.x1;
-   int dst_y = plane_state->base.dst.y1;
-   int dst_w = drm_rect_width(_state->base.dst);
-   int dst_h = drm_rect_height(_state->base.dst);
-   unsigned long irqflags;
-
-   /* Sizes are 0 based */
-   src_w--;
-   src_h--;
-   dst_w--;
-   dst_h--;
-
-   crtc->dspaddr_offset = surf_addr;
-
-   crtc->adjusted_x = src_x;
-   crtc->adjusted_y = src_y;
-
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
- PLANE_COLOR_PIPE_GAMMA_ENABLE |
- PLANE_COLOR_PIPE_CSC_ENABLE |
- PLANE_COLOR_PLANE_GAMMA_DISABLE);
-   }
-
-   I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-   I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-   I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-   I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-   I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->aux.offset - surf_addr) | aux_stride);
-   I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->aux.y << 16) | plane_state->aux.x);
-
-   if (scaler_id >= 0) {
-   uint32_t ps_ctrl = 0;
-
-   WARN_ON(!dst_w || !dst_h);
-   ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-   crtc_state->scaler_state.scalers[scaler_id].mode;
-   I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-   I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-   I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | 
dst_y);
-   I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | 
dst_h);
-   I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-   } else {
-   I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-   }
-
-   I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
-
-   POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-}
-
 static void skylake_disable_primary_plane(struct intel_plane *primary,
  struct intel_crtc *crtc)
 {
@@ -13275,7 +13198,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
else
modifiers = skl_format_modifiers_noccs;
 
-   primary->update_plane = skylake_update_primary_plane;
+   primary->update_plane = skl_update_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 4) {
intel_primary_formats = i965_primary_formats;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0d0abed1..1efd612 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1887,6 +1887,9 @@ int intel_sprite_set_colorkey(struct 

[Intel-gfx] [PATCH 3/3] drm/i915: Unify skylake plane disable

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 19 +--
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 96eac33..66a83cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3534,23 +3534,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_ctl;
 }
 
-static void skylake_disable_primary_plane(struct intel_plane *primary,
- struct intel_crtc *crtc)
-{
-   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-   enum plane_id plane_id = primary->id;
-   enum pipe pipe = primary->pipe;
-   unsigned long irqflags;
-
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
-   I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
-   I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
-   POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-}
-
 static int
 __intel_display_resume(struct drm_device *dev,
   struct drm_atomic_state *state,
@@ -13199,7 +13182,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
modifiers = skl_format_modifiers_noccs;
 
primary->update_plane = skl_update_plane;
-   primary->disable_plane = skylake_disable_primary_plane;
+   primary->disable_plane = skl_disable_plane;
} else if (INTEL_GEN(dev_priv) >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1efd612..18752b7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1890,6 +1890,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc);
 void skl_update_plane(struct intel_plane *plane,
  const struct intel_crtc_state *crtc_state,
  const struct intel_plane_state *plane_state);
+void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index ef16519..bc6bae6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -306,7 +306,7 @@ skl_update_plane(struct intel_plane *plane,
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 }
 
-static void
+void
 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-- 
2.7.4

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[Intel-gfx] [PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f..f922e2f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3287,13 +3287,14 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
int x = plane_state->main.x;
int y = plane_state->main.y;
unsigned long irqflags;
+   u32 dspaddr_offset;
 
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
if (INTEL_GEN(dev_priv) >= 4)
-   crtc->dspaddr_offset = plane_state->main.offset;
+   dspaddr_offset = plane_state->main.offset;
else
-   crtc->dspaddr_offset = linear_offset;
+   dspaddr_offset = linear_offset;
 
crtc->adjusted_x = x;
crtc->adjusted_y = y;
@@ -3322,18 +3323,18 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
}
POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f1..0d0abed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,7 +805,6 @@ struct intel_crtc {
/* Display surface base address adjustement for pageflips. Note that on
 * gen4+ this only adjusts up to a tile, offsets within a tile are
 * handled in the hw itself (with the TILEOFF register). */
-   u32 dspaddr_offset;
int adjusted_x;
int adjusted_y;
 
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Recreate vmapping even when the object is pinned (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Recreate vmapping even when the object is pinned (rev2)
URL   : https://patchwork.freedesktop.org/series/29388/
State : success

== Summary ==

shard-hswtotal:2230 pass:1232 dwarn:0   dfail:0   fail:16  skip:982 
time:9615s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5507/shards.html
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Re: [Intel-gfx] [PATCH v2] drm/i915: Recreate vmapping even when the object is pinned

[Joonas Lahtinen]

On Mon, 2017-08-28 at 11:46 +0100, Chris Wilson wrote:
> Sometimes we know we are the only user of the bo, but since we take a
> protective pin_pages early on, an attempt to change the vmap on the
> object is denied because it is busy. i915_gem_object_pin_map() cannot
> tell from our single pin_count if the operation is safe. Instead we must
> pass that information down from the caller in the manner of
> I915_MAP_OVERRIDE.
> 
> This issue has existed from the introduction of the mapping, but was
> never noticed as the only place where this conflict might happen is for
> cached kernel buffers (such as allocated by i915_gem_batch_pool_get()).
> Until recently there was only a single user (the cmdparser) so no
> conflicts ever occurred. However, we now use it to allocate batches for
> different operations (using MAP_WC on !llc for writes) in addition to the
> existing shadow batch (using MAP_WB for reads).
> 
> We could either keep both mappings cached, or use a different write
> mechanism if we detect a MAP_WB already exists (i.e. clflush
> afterwards), but as we haven't seen this issue in the wild (it requires
> hitting the GPU reloc path in addition to the cmdparser) for simplicity
> just allow the mappings to be recreated.
> 
> v2: Include the i915_MAP_OVERRIDE bit in the enum so the compiler knows
> about all the valid values.
> 
> Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
> Testcase: igt/gem_lut_handle # byt, completely by accident
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 00/12] drm/i915: Fix up the CCS code

[Daniel Stone]

Hi Daniel,

On 25 August 2017 at 18:17, Daniel Vetter  wrote:
> Which of these do we need to cherry-pick over to -next-fixes? There's no
> annotations about that. If the answer is "most" I'm leaning towards
> disabling CCS for 4.14, minimal set would be ideal (and first in the patch
> series).

My opinion below; tl;dr is that I don't think most of them are
super-critical. Ville obviously has a far stronger opinion than me on
the shape of the code, so I'm fine with this series, which seems to
mostly be a merge back of the delta between whatever Ville's latest
branch was, and whatever the last patchset Ben sent out was.

>> Ville Syrjälä (12):
>>   drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear
>> offset

This should land into -fixes. I trust Ville that it has no UABI
impact, but seems like something to be very consistent on.

>>   drm/i915: Skip fence alignemnt check for the CCS plane

Not sure if this is -fixes material really, just a cleanup?

>>   drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for
>> CCS

Not -fixes, performance optimisation.

>>   drm/i915: Add a comment exlaining CCS hsub/vsub

Seems harmless to land to -fixes.

>>   drm/i915: Nuke a pointless unreachable()

Ditto.

>>   drm/i915: Add the missing Y/Yf modifiers for SKL+ sprites

Per my previous reply, NAK to landing at all, since DDB/WM allocation
seems too broken for it to work.

>>   drm/i915: Clean up the sprite modifier checks

Fine with this, but doesn't seem like -fixes material.

>>   drm/i915: Add CCS capability for sprites

NAK, same reason as Y/Yf.

>>   drm/i915: Allow up to 32KB stride on SKL+ "sprites"

Again doesn't seem like -fixes necessarily?

>>   drm: Fix modifiers_property kernel doc

Good for -fixes.

>>   drm: Check that the plane supports the request format+modifier combo

Good for core (not Intel) -fixes.

>>   drm/i915: Remove the pipe/plane ID checks from
>> skl_check_ccs_aux_surface()

Seems fine but probably not -fixes material; land in Intel after a merge?

Cheers,
Daniel
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Re: [Intel-gfx] [PATCH v2 00/10] Improve robustness of the i915 perf tests

[Lionel Landwerlin]

On 28/08/17 08:21, Arkadiusz Hiler wrote:

On Wed, Aug 23, 2017 at 10:43:08AM +0100, Lionel Landwerlin wrote:

Hi all,

Here is an updated patch series containing mostly cleanups.

Cheers,

Hi,

Our CI hasn't pick this series up for a spin due to missing a "i-g-t" tag.

Direct quote from CONTRIBUTING file:
-
Please use --subject-prefix="PATCH i-g-t" so that i-g-t patches are easily
identified in the massive amount mails on intel-gfx. To ensure this is always
done, autogen.sh will run:

git config format.subjectprefix "PATCH i-g-t"

on its first invocation.
-


If only there was a wrapper around git (much like chromium has git cl), 
it's too easy to get this stuff wrong when you want to send a v2 and you 
have to use --subject-prefix :/


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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Remove excess indent in intel_finish_reset() caught by sparse

[Patchwork]

== Series Details ==

Series: drm/i915: Remove excess indent in intel_finish_reset() caught by sparse
URL   : https://patchwork.freedesktop.org/series/29424/
State : warning

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb-draw-render:
pass   -> SKIP   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2186 pass:1211 dwarn:0   dfail:0   fail:17  skip:958 
time:9510s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5506/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h

[Patchwork]

== Series Details ==

Series: tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h
URL   : https://patchwork.freedesktop.org/series/29427/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
60f6a12195395934f179d5ecc080353190d19a6c tests: chamelium: Eliminate reset when 
preparing output

with latest DRM-Tip kernel build CI_DRM_3010
00b77f621f83 drm-tip: 2017y-08m-28d-10h-25m-08s UTC integration manifest

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:458s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:451s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:362s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:560s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:524s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:518s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:429s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:609s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:451s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:594s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:600s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:525s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:486s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:447s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:507s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_111/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Beef up of Beef up the IPS vs. CRC workaround (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Beef up of Beef up the IPS vs. CRC workaround (rev2)
URL   : https://patchwork.freedesktop.org/series/29425/
State : success

== Summary ==

Series 29425v2 drm/i915: Beef up of Beef up the IPS vs. CRC workaround
https://patchwork.freedesktop.org/api/1.0/series/29425/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:357s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:559s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:255s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:518s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:511s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:433s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:606s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:461s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:428s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:501s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:595s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:516s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:469s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:483s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:442s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:499s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:410s

00b77f621f835bc114b79ec897b9aa277ea5726b drm-tip: 2017y-08m-28d-10h-25m-08s UTC 
integration manifest
e19ac29f9da6 drm/i915: Beef up of Beef up the IPS vs. CRC workaround

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5509/
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[Intel-gfx] [i-g-t PATCH 07/10] tools/intel_vbt_decode: migrate psr dumping to kernel struct

[Jani Nikula]

No functional changes.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 15 ---
 tools/intel_vbt_decode.c | 26 ++
 tools/intel_vbt_defs.h   | 18 ++
 3 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 3f441a6da17b..f4b0b9795221 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -163,21 +163,6 @@ struct bdb_edp { /* 155 */
struct edp_full_link_params full_link_params[16]; /* 199 */
 } __attribute__ ((packed));
 
-struct psr_params {
-   uint8_t full_link:1;
-   uint8_t require_aux_to_wakeup:1;
-   uint8_t rsvd1:6;
-   uint8_t idle_frames:4;
-   uint8_t lines_to_wait:3;
-   uint8_t rsvd2:1;
-   uint16_t tp1_wakeup_time;
-   uint16_t tp2_tp3_wakeup_time;
-} __attribute__ ((packed));
-
-struct bdb_psr {
-   struct psr_params psr[16];
-} __attribute__ ((packed));
-
 /* Block 52 contains MiPi Panel info
  * 6 such enteries will there. Index into correct
  * entery is based on the panel_index in #40 LFP
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index 711f29979418..d0b91a3de3ef 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -891,7 +891,7 @@ static void dump_edp(struct context *context,
 static void dump_psr(struct context *context,
 const struct bdb_block *block)
 {
-   const struct bdb_psr *psr = block->data;
+   const struct bdb_psr *psr_block = block->data;
int i;
 
/* The same block ID was used for something else before? */
@@ -899,41 +899,43 @@ static void dump_psr(struct context *context,
return;
 
for (i = 0; i < 16; i++) {
+   const struct psr_table *psr = _block->psr_table[i];
+
if (i != context->panel_type && !context->dump_all_panel_types)
continue;
 
printf("\tPanel %d%s\n", i, context->panel_type == i ? " *" : 
"");
 
-   printf("\t\tFull link: %s\n", YESNO(psr->psr[i].full_link));
-   printf("\t\tRequire AUX to wakeup: %s\n", 
YESNO(psr->psr[i].require_aux_to_wakeup));
+   printf("\t\tFull link: %s\n", YESNO(psr->full_link));
+   printf("\t\tRequire AUX to wakeup: %s\n", 
YESNO(psr->require_aux_to_wakeup));
 
-   switch (psr->psr[i].lines_to_wait) {
+   switch (psr->lines_to_wait) {
case 0:
case 1:
printf("\t\tLines to wait before link standby: %d\n",
-  psr->psr[i].lines_to_wait);
+  psr->lines_to_wait);
break;
case 2:
case 3:
printf("\t\tLines to wait before link standby: %d\n",
-  1 << psr->psr[i].lines_to_wait);
+  1 << psr->lines_to_wait);
break;
default:
printf("\t\tLines to wait before link standby: 
(unknown) (0x%x)\n",
-  psr->psr[i].lines_to_wait);
+  psr->lines_to_wait);
break;
}
 
printf("\t\tIdle frames to for PSR enable: %d\n",
-  psr->psr[i].idle_frames);
+  psr->idle_frames);
 
printf("\t\tTP1 wakeup time: %d usec (0x%x)\n",
-  psr->psr[i].tp1_wakeup_time * 100,
-  psr->psr[i].tp1_wakeup_time);
+  psr->tp1_wakeup_time * 100,
+  psr->tp1_wakeup_time);
 
printf("\t\tTP2/TP3 wakeup time: %d usec (0x%x)\n",
-  psr->psr[i].tp2_tp3_wakeup_time * 100,
-  psr->psr[i].tp2_tp3_wakeup_time);
+  psr->tp2_tp3_wakeup_time * 100,
+  psr->tp2_tp3_wakeup_time);
}
 }
 
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index dcb6f36443ad..a43ec2d1c02e 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -671,7 +671,25 @@ struct bdb_driver_features {
 #define EDP_VSWING_0_8V2
 #define EDP_VSWING_1_2V3
 
+struct psr_table {
+   /* Feature bits */
+   u8 full_link:1;
+   u8 require_aux_to_wakeup:1;
+   u8 feature_bits_rsvd:6;
+
+   /* Wait times */
+   u8 idle_frames:4;
+   u8 lines_to_wait:3;
+   u8 wait_times_rsvd:1;
+
+   /* TP wake up time in multiple of 100 */
+   u16 tp1_wakeup_time;
+   u16 tp2_tp3_wakeup_time;
+} __packed;
 
+struct bdb_psr {
+   struct psr_table psr_table[16];
+} __packed;
 
 /*
  * Driver<->VBIOS interaction occurs through scratch bits in
-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 06/10] tools/intel_vbt_decode: migrate child device dumping to kernel struct

[Jani Nikula]

Retain the legacy definition for the obsolete child device block, at
least for now. No functional changes.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 58 +
 tools/intel_vbt_decode.c | 45 ++-
 tools/intel_vbt_defs.h   | 96 
 3 files changed, 118 insertions(+), 81 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 8d1bf7ae0c81..3f441a6da17b 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -72,7 +72,7 @@
 #define DEVICE_PORT_DPC8
 #define DEVICE_PORT_DPD9
 
-struct child_device_config {
+struct legacy_child_device_config {
uint16_t handle;
uint16_t device_type;   /* See DEVICE_TYPE_* above */
uint8_t device_id[10];
@@ -94,65 +94,11 @@ struct child_device_config {
uint8_t dvo_function;
 } __attribute__ ((packed));
 
-struct efp_child_device_config {
-   uint16_t handle;
-   uint16_t device_type;
-   uint8_t i2c_speed;
-   uint8_t dp_onboard_redriver; /* 158 */
-   uint8_t dp_ondock_redriver; /* 158 */
-   uint8_t hdmi_level_shifter_value:4; /* 169 */
-   uint8_t hdmi_max_data_rate:4; /* 204 */
-   uint16_t dtd_buf_ptr; /* 161 */
-   uint8_t edidless_efp:1; /* 161 */
-   uint8_t compression_enable:1; /* 198 */
-   uint8_t compression_method:1; /* 198 */
-   uint8_t ganged_edp:1; /* 202 */
-   uint8_t skip0:4;
-   uint8_t compression_structure_index:4; /* 198 */
-   uint8_t skip1:4;
-   uint8_t slave_port; /*  202 */
-   uint8_t skip2;
-   uint16_t addin_offset;
-   uint8_t port;
-   uint8_t i2c_pin; /* for add-in card */
-   uint8_t slave_addr; /* for add-in card */
-   uint8_t ddc_pin;
-   uint16_t edid_ptr;
-   uint8_t dvo_config;
-   uint8_t efp_docked_port:1; /* 158 */
-   uint8_t lane_reversal:1; /* 184 */
-   uint8_t onboard_lspcon:1; /* 192 */
-   uint8_t iboost_enable:1; /* 196 */
-   uint8_t hpd_invert:1; /* BXT 196 */
-   uint8_t slip3:3;
-   uint8_t hdmi_compat:1;
-   uint8_t dp_compat:1;
-   uint8_t tmds_compat:1;
-   uint8_t skip4:5;
-   uint8_t aux_chan;
-   uint8_t dongle_detect;
-   uint8_t pipe_cap:2;
-   uint8_t sdvo_stall:1; /* 158 */
-   uint8_t hpd_status:2;
-   uint8_t integrated_encoder:1;
-   uint8_t skip5:2;
-   uint8_t dvo_wiring;
-   uint8_t mipi_bridge_type; /* 171 */
-   uint16_t device_class_ext;
-   uint8_t dvo_function;
-   uint8_t dp_usb_type_c:1; /* 195 */
-   uint8_t skip6:7;
-   uint8_t dp_usb_type_c_2x_gpio_index; /* 195 */
-   uint16_t dp_usb_type_c_2x_gpio_pin; /* 195 */
-   uint8_t iboost_dp:4; /* 196 */
-   uint8_t iboost_hdmi:4; /* 196 */
-} __attribute__ ((packed));
-
 #define DEVICE_CHILD_SIZE 7
 
 struct bdb_child_devices {
uint8_t child_structure_size;
-   struct child_device_config children[DEVICE_CHILD_SIZE];
+   struct legacy_child_device_config children[DEVICE_CHILD_SIZE];
 } __attribute__ ((packed));
 
 struct blc_struct {
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index beb33672835e..711f29979418 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -383,6 +383,7 @@ static const char *efp_port(uint8_t type)
 static void dump_child_device(struct context *context,
  const struct child_device_config *child)
 {
+   const struct child_device_config *efp = child;
char child_id[11];
 
if (!child->device_type)
@@ -399,8 +400,6 @@ static void dump_child_device(struct context *context,
printf("\t\tAIM offset: %d\n", child->addin_offset);
printf("\t\tDVO port: 0x%02x\n", child->dvo_port);
} else { /* 152+ have EFP blocks here */
-   const struct efp_child_device_config *efp =
-   (const struct efp_child_device_config *)child;
printf("\tEFP device info:\n");
printf("\t\tDevice handle: 0x%04x (%s)\n", efp->handle,
   child_device_handle(efp->handle));
@@ -420,21 +419,21 @@ static void dump_child_device(struct context *context,
printf("\t\tCompression structure index: 0x%02x)\n", 
efp->compression_structure_index);
printf("\t\tSlave DDI port: 0x%02x (%s)\n", efp->slave_port, 
efp_port(efp->slave_port));
printf("\t\tAIM offset: %d\n", child->addin_offset);
-   printf("\t\tPort: 0x%02x (%s)\n", efp->port, 
efp_port(efp->port));
+   printf("\t\tPort: 0x%02x (%s)\n", efp->dvo_port, 
efp_port(efp->dvo_port));
printf("\t\tAIM I2C pin: 0x%02x\n", efp->i2c_pin);
printf("\t\tAIM Slave address: 0x%02x\n", efp->slave_addr);
printf("\t\tDDC pin: 0x%02x\n", efp->ddc_pin);
printf("\t\tEDID buffer ptr: 

[Intel-gfx] [i-g-t PATCH 08/10] tools/intel_vbt_decode: migrate edp dumping to kernel struct

[Jani Nikula]

No functional changes.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 33 -
 tools/intel_vbt_decode.c |  7 ---
 tools/intel_vbt_defs.h   | 35 +++
 3 files changed, 39 insertions(+), 36 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index f4b0b9795221..9f0bc84f372c 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -130,39 +130,6 @@ struct edp_power_seq {
uint16_t t12;
 } __attribute__ ((packed));
 
-struct edp_fast_link_params {
-   uint8_t rate:4;
-   uint8_t lanes:4;
-   uint8_t preemphasis:4;
-   uint8_t vswing:4;
-} __attribute__ ((packed));
-
-struct edp_pwm_delays {
-   uint16_t pwm_on_to_backlight_enable;
-   uint16_t backlight_disable_to_pwm_off;
-} __attribute__ ((packed));
-
-struct edp_full_link_params {
-   uint8_t preemphasis:4;
-   uint8_t vswing:4;
-} __attribute__ ((packed));
-
-struct bdb_edp { /* 155 */
-   struct edp_power_seq power_seqs[16];
-   uint32_t color_depth;
-   struct edp_fast_link_params fast_link_params[16];
-   uint32_t sdrrs_msa_timing_delay;
-
-   uint16_t s3d_feature; /* 163 */
-   uint16_t t3_optimization; /* 165 */
-   uint64_t vswing_preemph_table_selection; /* 173 */
-   uint16_t fast_link_training; /* 182 */
-   uint16_t dpcd_600h_write_required; /* 185 */
-   struct edp_pwm_delays pwm_delays[16]; /* 186 */
-   uint16_t full_link_params_provided; /* 199 */
-   struct edp_full_link_params full_link_params[16]; /* 199 */
-} __attribute__ ((packed));
-
 /* Block 52 contains MiPi Panel info
  * 6 such enteries will there. Index into correct
  * entery is based on the panel_index in #40 LFP
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index d0b91a3de3ef..ed0b90bd63e6 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -44,6 +44,7 @@
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
+typedef uint64_t u64;
 #define __packed __attribute__ ((packed))
 
 #define _INTEL_BIOS_PRIVATE
@@ -797,17 +798,17 @@ static void dump_edp(struct context *context,
}
 
if (context->bdb->version >= 162) {
-   bool val = (edp->s3d_feature >> i) & 1;
+   bool val = (edp->edp_s3d_feature >> i) & 1;
printf("\t\tStereo 3D feature: %s\n", YESNO(val));
}
 
if (context->bdb->version >= 165) {
-   bool val = (edp->t3_optimization >> i) & 1;
+   bool val = (edp->edp_t3_optimization >> i) & 1;
printf("\t\tT3 optimization: %s\n", YESNO(val));
}
 
if (context->bdb->version >= 173) {
-   int val = (edp->vswing_preemph_table_selection >> (i * 
4)) & 0xf;
+   int val = (edp->edp_vswing_preemph >> (i * 4)) & 0xf;
 
printf("\t\tVswing/preemphasis table selection: ");
switch (val) {
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index a43ec2d1c02e..9513f9dc21ab 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -671,6 +671,41 @@ struct bdb_driver_features {
 #define EDP_VSWING_0_8V2
 #define EDP_VSWING_1_2V3
 
+
+struct edp_fast_link_params {
+   u8 rate:4;
+   u8 lanes:4;
+   u8 preemphasis:4;
+   u8 vswing:4;
+} __packed;
+
+struct edp_pwm_delays {
+   u16 pwm_on_to_backlight_enable;
+   u16 backlight_disable_to_pwm_off;
+} __packed;
+
+struct edp_full_link_params {
+   u8 preemphasis:4;
+   u8 vswing:4;
+} __packed;
+
+struct bdb_edp {
+   struct edp_power_seq power_seqs[16];
+   u32 color_depth;
+   struct edp_fast_link_params fast_link_params[16];
+   u32 sdrrs_msa_timing_delay;
+
+   /* ith bit indicates enabled/disabled for (i+1)th panel */
+   u16 edp_s3d_feature;/* 162 */
+   u16 edp_t3_optimization;/* 165 */
+   u64 edp_vswing_preemph; /* 173 */
+   u16 fast_link_training; /* 182 */
+   u16 dpcd_600h_write_required;   /* 185 */
+   struct edp_pwm_delays pwm_delays[16];   /* 186 */
+   u16 full_link_params_provided;  /* 199 */
+   struct edp_full_link_params full_link_params[16];   /* 199 */
+} __packed;
+
 struct psr_table {
/* Feature bits */
u8 full_link:1;
-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 10/10] tools/intel_vbt_defs: migrate backlight dumping to kernel struct

[Jani Nikula]

Drop obsolete field dumping.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 16 
 tools/intel_vbt_decode.c | 20 
 2 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 85aa38e085be..4e06ef74e459 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -83,22 +83,6 @@ struct bdb_child_devices {
struct legacy_child_device_config children[DEVICE_CHILD_SIZE];
 } __attribute__ ((packed));
 
-struct blc_struct {
-   uint8_t inverter_type:2;
-   uint8_t inverter_polarity:1;/* 1 means inverted (0 = max 
brightness) */
-   uint8_t gpio_pins:3;
-   uint8_t gmbus_speed:2;
-   uint16_t pwm_freq;  /* in Hz */
-   uint8_t min_brightness; /* (0-255) */
-   uint8_t i2c_slave_addr;
-   uint8_t i2c_cmd;
-} __attribute__ ((packed));
-
-struct bdb_lvds_backlight {
-   uint8_t blcstruct_size;
-   struct blc_struct panels[16];
-} __attribute__ ((packed));
-
 #define BDB_DRIVER_NO_LVDS 0
 #define BDB_DRIVER_INT_LVDS1
 #define BDB_DRIVER_SDVO_LVDS   2
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index d8ca0ee87198..3535459d3353 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -225,25 +225,21 @@ static void dump_general_features(struct context *context,
 static void dump_backlight_info(struct context *context,
const struct bdb_block *block)
 {
-   const struct bdb_lvds_backlight *backlight = block->data;
-   const struct blc_struct *blc;
+   const struct bdb_lfp_backlight_data *backlight = block->data;
+   const struct bdb_lfp_backlight_data_entry *blc;
 
-   if (sizeof(struct blc_struct) != backlight->blcstruct_size) {
+   if (sizeof(*blc) != backlight->entry_size) {
printf("\tBacklight struct sizes don't match (expected %zu, got 
%u), skipping\n",
-sizeof(struct blc_struct), backlight->blcstruct_size);
+sizeof(*blc), backlight->entry_size);
return;
}
 
-   blc = >panels[context->panel_type];
+   blc = >data[context->panel_type];
 
-   printf("\tInverter type: %d\n", blc->inverter_type);
-   printf("\t polarity: %d\n", blc->inverter_polarity);
-   printf("\tGPIO pins: %d\n", blc->gpio_pins);
-   printf("\t  GMBUS speed: %d\n", blc->gmbus_speed);
-   printf("\t PWM freq: %d\n", blc->pwm_freq);
+   printf("\tInverter type: %d\n", blc->type);
+   printf("\t polarity: %d\n", blc->active_low_pwm);
+   printf("\t PWM freq: %d\n", blc->pwm_freq_hz);
printf("\tMinimum brightness: %d\n", blc->min_brightness);
-   printf("\tI2C slave addr: 0x%02x\n", blc->i2c_slave_addr);
-   printf("\tI2C command: 0x%02x\n", blc->i2c_cmd);
 }
 
 static const struct {
-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 09/10] tools/intel_vbt_decode: migrate child device type bits decoding to kernel defs

[Jani Nikula]

This lets us use the verbatim copy of the kernel intel_vbt_defs.h file.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 18 --
 tools/intel_vbt_decode.c | 47 +--
 tools/intel_vbt_defs.h   | 16 
 3 files changed, 41 insertions(+), 40 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 9f0bc84f372c..85aa38e085be 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -38,24 +38,6 @@
 #define DEVICE_HANDLE_LPF1 0x08
 #define DEVICE_HANDLE_LFP2 0x80
 
-/* device type bits */
-#define DEVICE_TYPE_CLASS_EXTENSION15
-#define DEVICE_TYPE_POWER_MANAGEMENT   14
-#define DEVICE_TYPE_HOTPLUG_SIGNALING  13
-#define DEVICE_TYPE_INTERNAL_CONNECTOR 12
-#define DEVICE_TYPE_NOT_HDMI_OUTPUT11
-#define DEVICE_TYPE_MIPI_OUTPUT10
-#define DEVICE_TYPE_COMPOSITE_OUTPUT   9
-#define DEVICE_TYPE_DIAL_CHANNEL   8
-#define DEVICE_TYPE_CONTENT_PROTECTION 7
-#define DEVICE_TYPE_HIGH_SPEED_LINK6
-#define DEVICE_TYPE_LVDS_SIGNALING 5
-#define DEVICE_TYPE_TMDS_DVI_SIGNALING 4
-#define DEVICE_TYPE_VIDEO_SIGNALING3
-#define DEVICE_TYPE_DISPLAYPORT_OUTPUT 2
-#define DEVICE_TYPE_DIGITAL_OUTPUT 1
-#define DEVICE_TYPE_ANALOG_OUTPUT  0
-
 #define DEVICE_TYPE_DP_DVI 0x68d6
 #define DEVICE_TYPE_DVI0x68d2
 #define DEVICE_TYPE_MIPI   0x7cc2
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index ed0b90bd63e6..d8ca0ee87198 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -299,34 +299,37 @@ static const char *child_device_type(unsigned short type)
return "unknown";
 }
 
-static const char * const child_device_type_bits[] = {
-   [DEVICE_TYPE_CLASS_EXTENSION] = "Class extension",
-   [DEVICE_TYPE_POWER_MANAGEMENT] = "Power management",
-   [DEVICE_TYPE_HOTPLUG_SIGNALING] = "Hotplug signaling",
-   [DEVICE_TYPE_INTERNAL_CONNECTOR] = "Internal connector",
-   [DEVICE_TYPE_NOT_HDMI_OUTPUT] = "HDMI output", /* decoded as inverse */
-   [DEVICE_TYPE_MIPI_OUTPUT] = "MIPI output",
-   [DEVICE_TYPE_COMPOSITE_OUTPUT] = "Composite output",
-   [DEVICE_TYPE_DIAL_CHANNEL] = "Dual channel",
-   [DEVICE_TYPE_CONTENT_PROTECTION] = "Content protection",
-   [DEVICE_TYPE_HIGH_SPEED_LINK] = "High speel link",
-   [DEVICE_TYPE_LVDS_SIGNALING] = "LVDS signaling",
-   [DEVICE_TYPE_TMDS_DVI_SIGNALING] = "TMDS/DVI signaling",
-   [DEVICE_TYPE_VIDEO_SIGNALING] = "Video signaling",
-   [DEVICE_TYPE_DISPLAYPORT_OUTPUT] = "DisplayPort output",
-   [DEVICE_TYPE_DIGITAL_OUTPUT] = "Digital output",
-   [DEVICE_TYPE_ANALOG_OUTPUT] = "Analog output",
+static const struct {
+   unsigned short mask;
+   const char *name;
+} child_device_type_bits[] = {
+   { DEVICE_TYPE_CLASS_EXTENSION, "Class extension" },
+   { DEVICE_TYPE_POWER_MANAGEMENT, "Power management" },
+   { DEVICE_TYPE_HOTPLUG_SIGNALING, "Hotplug signaling" },
+   { DEVICE_TYPE_INTERNAL_CONNECTOR, "Internal connector" },
+   { DEVICE_TYPE_NOT_HDMI_OUTPUT, "HDMI output" }, /* decoded as inverse */
+   { DEVICE_TYPE_MIPI_OUTPUT, "MIPI output" },
+   { DEVICE_TYPE_COMPOSITE_OUTPUT, "Composite output" },
+   { DEVICE_TYPE_DUAL_CHANNEL, "Dual channel" },
+   { 1 << 7, "Content protection" },
+   { DEVICE_TYPE_HIGH_SPEED_LINK, "High speel link" },
+   { DEVICE_TYPE_LVDS_SINGALING, "LVDS signaling" },
+   { DEVICE_TYPE_TMDS_DVI_SIGNALING, "TMDS/DVI signaling" },
+   { DEVICE_TYPE_VIDEO_SIGNALING, "Video signaling" },
+   { DEVICE_TYPE_DISPLAYPORT_OUTPUT, "DisplayPort output" },
+   { DEVICE_TYPE_DIGITAL_OUTPUT, "Digital output" },
+   { DEVICE_TYPE_ANALOG_OUTPUT, "Analog output" },
 };
 
 static void dump_child_device_type_bits(uint16_t type)
 {
-   int bit;
+   int i;
 
-   type ^= 1 << DEVICE_TYPE_NOT_HDMI_OUTPUT;
+   type ^= DEVICE_TYPE_NOT_HDMI_OUTPUT;
 
-   for (bit = 15; bit >= 0; bit--) {
-   if (type & (1 << bit))
-   printf("\t\t\t%s\n", child_device_type_bits[bit]);
+   for (i = 0; i < ARRAY_SIZE(child_device_type_bits); i++) {
+   if (child_device_type_bits[i].mask & type)
+   printf("\t\t\t%s\n", child_device_type_bits[i].name);
}
 }
 
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index 9513f9dc21ab..404569c9fdfc 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -218,6 +218,22 @@ struct bdb_general_features {
 #define DEVICE_TYPE_DP_DUAL_MODE   0x60D6
 #define DEVICE_TYPE_eDP0x78C6
 
+#define DEVICE_TYPE_CLASS_EXTENSION(1 << 15)
+#define DEVICE_TYPE_POWER_MANAGEMENT   (1 << 14)
+#define DEVICE_TYPE_HOTPLUG_SIGNALING  (1 << 13)
+#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
+#define DEVICE_TYPE_NOT_HDMI_OUTPUT(1 << 11)
+#define 

[Intel-gfx] [i-g-t PATCH 04/10] tools/intel_vbt_decode: start migrating to kernel intel_vbt_defs.h

[Jani Nikula]

Copy over most of intel_vbt_defs.h, and use everything that matches with
minor changes from there.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 305 -
 tools/intel_vbt_decode.c |  20 +-
 tools/intel_vbt_defs.h   | 701 +++
 3 files changed, 715 insertions(+), 311 deletions(-)
 create mode 100644 tools/intel_vbt_defs.h

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 69d8aa6d7fe9..65e64ccb41ef 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -30,108 +30,6 @@
 
 #include 
 
-
-struct vbt_header {
-   char signature[20]; /**< Always starts with 'VBT$' */
-   uint16_t version;   /**< decimal */
-   uint16_t header_size;   /**< in bytes */
-   uint16_t vbt_size;  /**< in bytes */
-   uint8_t vbt_checksum;
-   uint8_t reserved0;
-   uint32_t bdb_offset;/**< from beginning of VBT */
-   uint32_t aim_offset[4]; /**< from beginning of VBT */
-} __attribute__ ((packed));
-
-struct bdb_header {
-   char signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
-   uint16_t version;   /**< decimal */
-   uint16_t header_size;   /**< in bytes */
-   uint16_t bdb_size;  /**< in bytes */
-} __attribute__ ((packed));
-
-/*
- * There are several types of BIOS data blocks (BDBs), each block has
- * an ID and size in the first 3 bytes (ID in first, size in next 2).
- * Known types are listed below.
- */
-#define BDB_GENERAL_FEATURES 1
-#define BDB_GENERAL_DEFINITIONS  2
-#define BDB_OLD_TOGGLE_LIST  3
-#define BDB_MODE_SUPPORT_LIST4
-#define BDB_GENERIC_MODE_TABLE   5
-#define BDB_EXT_MMIO_REGS6
-#define BDB_SWF_IO   7
-#define BDB_SWF_MMIO 8
-#define BDB_DOT_CLOCK_TABLE  9
-#define BDB_PSR  9
-#define BDB_MODE_REMOVAL_TABLE  10
-#define BDB_CHILD_DEVICE_TABLE  11
-#define BDB_DRIVER_FEATURES 12
-#define BDB_DRIVER_PERSISTENCE  13
-#define BDB_EXT_TABLE_PTRS  14
-#define BDB_DOT_CLOCK_OVERRIDE  15
-#define BDB_DISPLAY_SELECT  16
-/* 17 rsvd */
-#define BDB_DRIVER_ROTATION 18
-#define BDB_DISPLAY_REMOVE  19
-#define BDB_OEM_CUSTOM  20
-#define BDB_EFP_LIST21 /* workarounds for VGA hsync/vsync */
-#define BDB_SDVO_LVDS_OPTIONS   22
-#define BDB_SDVO_PANEL_DTDS 23
-#define BDB_SDVO_LVDS_PNP_IDS   24
-#define BDB_SDVO_LVDS_POWER_SEQ 25
-#define BDB_TV_OPTIONS  26
-#define BDB_EDP 27
-#define BDB_LVDS_OPTIONS40
-#define BDB_LVDS_LFP_DATA_PTRS  41
-#define BDB_LVDS_LFP_DATA   42
-#define BDB_LVDS_BACKLIGHT  43
-#define BDB_LVDS_POWER  44
-#define BDB_MIPI_CONFIG 52
-#define BDB_MIPI_SEQUENCE   53
-#define BDB_SKIP   254 /* VBIOS private block, ignore */
-
-struct bdb_general_features {
-   /* bits 1 */
-   unsigned char panel_fitting:2;
-   unsigned char flexaim:1;
-   unsigned char msg_enable:1;
-   unsigned char clear_screen:3;
-   unsigned char color_flip:1;
-
-   /* bits 2 */
-   unsigned char download_ext_vbt:1;
-   unsigned char enable_ssc:1;
-   unsigned char ssc_freq:1;
-   unsigned char enable_lfp_on_override:1;
-   unsigned char disable_ssc_ddt:1;
-   unsigned char underscan_vga_timings:1;
-   unsigned char dynamic_cdclk:1; /* 183 */
-   unsigned char vbios_hotplug_support:1;
-
-   /* bits 3 */
-   unsigned char disable_smooth_vision:1;
-   unsigned char single_dvi:1;
-   unsigned char rotate_180:1; /* 181 */
-   unsigned char fdi_rx_polarity:1;
-   unsigned char vbios_extended_mode:1; /* 160 */
-   unsigned char copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
-   unsigned char panel_best_fit_timing:1; /* 160 */
-   unsigned char ignore_strap_state:1; /* 160 */
-
-   /* bits 4 */
-   unsigned char legacy_monitor_detect;
-
-   /* bits 5 */
-   unsigned char int_crt_support:1;
-   unsigned char int_tv_support:1;
-   unsigned char int_efp_support:1;
-   unsigned char dp_ssc_enable:1;
-   unsigned char dp_ssc_freq:1;
-   unsigned char dp_ssc_dongle_supported:1;
-   unsigned char rsvd11:2; /* finish byte */
-} __attribute__ ((packed));
-
 #define DEVICE_HANDLE_CRT  0x01
 #define DEVICE_HANDLE_EFP1 0x04
 #define DEVICE_HANDLE_EFP2 0x40
@@ -158,43 +56,8 @@ struct bdb_general_features {
 #define DEVICE_TYPE_DIGITAL_OUTPUT 1
 #define DEVICE_TYPE_ANALOG_OUTPUT  0
 
-/* Pre 915 */
-#define DEVICE_TYPE_NONE   0x00
-#define DEVICE_TYPE_CRT0x01
-#define DEVICE_TYPE_TV 0x09
-#define DEVICE_TYPE_EFP0x12
-#define DEVICE_TYPE_LFP0x22
-/* On 915+ */
-#define DEVICE_TYPE_CRT_DPMS   0x6001
-#define DEVICE_TYPE_CRT_DPMS_HOTPLUG   0x4001

[Intel-gfx] [i-g-t PATCH 00/10] tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h

[Jani Nikula]

There's little point in duplicating the efforts of describing the same
data in two places. This series lets us use the verbatim copy of the
intel_vbt_defs.h from kernel. Going forward, we should add the changes
in kernel first, then copy the header over to igt.

If we need local tweaks, we can still have them in intel_bios.h, and
indeed we'll still have some after this series.

BR,
Jani.

Jani Nikula (10):
  tools/intel_lid: use local register definition
  tools/intel_vbt_decode: remove unused definitions from intel_bios.h
  tools/intel_vbt_decode: clean up struct lvds_dvo_timing
  tools/intel_vbt_decode: start migrating to kernel intel_vbt_defs.h
  tools/intel_vbt_decode: migrate timing dumping to kernel struct
  tools/intel_vbt_decode: migrate child device dumping to kernel struct
  tools/intel_vbt_decode: migrate psr dumping to kernel struct
  tools/intel_vbt_decode: migrate edp dumping to kernel struct
  tools/intel_vbt_decode: migrate child device type bits decoding to
kernel defs
  tools/intel_vbt_defs: migrate backlight dumping to kernel struct

 tools/intel_bios.h   | 760 +--
 tools/intel_lid.c|   5 +-
 tools/intel_vbt_decode.c | 180 +-
 tools/intel_vbt_defs.h   | 897 +++
 4 files changed, 996 insertions(+), 846 deletions(-)
 create mode 100644 tools/intel_vbt_defs.h

-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 02/10] tools/intel_vbt_decode: remove unused definitions from intel_bios.h

[Jani Nikula]

This is prep work for refactoring VBT definitions.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h | 268 -
 1 file changed, 268 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index f2ccb55ab6c3..c998031041fd 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -132,20 +132,6 @@ struct bdb_general_features {
unsigned char rsvd11:2; /* finish byte */
 } __attribute__ ((packed));
 
-#define GPIO_PIN_NONE  0x00/* "N/A" */
-#defineGPIO_PIN_I2C0x01/* "I2C GPIO pins" */
-#defineGPIO_PIN_CRT_DDC0x02/* "Analog CRT DDC GPIO pins" */
-/* 915+ */
-#defineGPIO_PIN_LVDS   0x03/* "Integrated LVDS DDC GPIO 
pins" */
-#defineGPIO_PIN_SDVO_I2C   0x05/* "sDVO I2C GPIO pins" */
-#defineGPIO_PIN_SDVO_DDC1  0x1D/* "SDVO DDC1 GPIO pins" */
-#defineGPIO_PIN_SDVO_DDC2  0x2D/* "SDVO DDC2 GPIO pins" */
-/* pre-915 */
-#defineGPIO_PIN_DVI_LVDS   0x03/* "DVI/LVDS DDC GPIO pins" */
-#defineGPIO_PIN_ADD_I2C0x05/* "ADDCARD I2C GPIO pins" */
-#defineGPIO_PIN_ADD_DDC0x04/* "ADDCARD DDC GPIO pins" */
-#defineGPIO_PIN_ADD_DDC_I2C0x06/* "ADDCARD DDC/I2C GPIO pins" 
*/
-
 #define DEVICE_HANDLE_CRT  0x01
 #define DEVICE_HANDLE_EFP1 0x04
 #define DEVICE_HANDLE_EFP2 0x40
@@ -211,26 +197,6 @@ struct bdb_general_features {
 #define DEVICE_TYPE_eDP0x78C6
 #define DEVICE_TYPE_MIPI   0x7cc2
 
-#define DEVICE_CFG_NONE0x00
-#define DEVICE_CFG_12BIT_DVOB  0x01
-#define DEVICE_CFG_12BIT_DVOC  0x02
-#define DEVICE_CFG_24BIT_DVOBC 0x09
-#define DEVICE_CFG_24BIT_DVOCB 0x0a
-#define DEVICE_CFG_DUAL_DVOB   0x11
-#define DEVICE_CFG_DUAL_DVOC   0x12
-#define DEVICE_CFG_DUAL_DVOBC  0x13
-#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
-#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
-
-#define DEVICE_WIRE_NONE   0x00
-#define DEVICE_WIRE_DVOB   0x01
-#define DEVICE_WIRE_DVOC   0x02
-#define DEVICE_WIRE_DVOBC  0x03
-#define DEVICE_WIRE_DVOBB  0x05
-#define DEVICE_WIRE_DVOCC  0x06
-#define DEVICE_WIRE_DVOB_MASTER0x0d
-#define DEVICE_WIRE_DVOC_MASTER0x0e
-
 #define DEVICE_PORT_DVOA   0x00/* none on 845+ */
 #define DEVICE_PORT_DVOB   0x01
 #define DEVICE_PORT_DVOC   0x02
@@ -243,11 +209,6 @@ struct bdb_general_features {
 #define DEVICE_PORT_DPC8
 #define DEVICE_PORT_DPD9
 
-#define DEVICE_INFO_NONE   0
-#define DEVICE_INFO_HDMI_CERT  1
-#define DEVICE_INFO_DP 2
-#define DEVICE_INFO_DVI3
-
 struct child_device_config {
uint16_t handle;
uint16_t device_type;   /* See DEVICE_TYPE_* above */
@@ -370,16 +331,6 @@ struct bdb_lvds_options {
uint8_t rsvd4;
 } __attribute__ ((packed));
 
-/* 915+ only */
-struct bdb_tv_features {
-   /* need to verify bit ordering */
-   uint16_t under_over_scan_via_yprpb:2;
-   uint16_t rsvd1:10;
-   uint16_t under_over_scan_via_dvi:2;
-   uint16_t add_overscan_mode:1;
-   uint16_t rsvd2:1;
-} __attribute__ ((packed));
-
 struct lvds_fp_timing {
uint16_t x_res;
uint16_t y_res;
@@ -476,79 +427,6 @@ struct bdb_lvds_lfp_data {
struct bdb_lvds_lfp_data_entry data[16];
 } __attribute__ ((packed));
 
-#define BACKLIGHT_TYPE_NONE 0
-#define BACKLIGHT_TYPE_I2C 1
-#define BACKLIGHT_TYPE_PWM 2
-
-#define BACKLIGHT_GMBUS_100KHZ 0
-#define BACKLIGHT_GMBUS_50KHZ  1
-#define BACKLIGHT_GMBUS_400KHZ 2
-#define BACKLIGHT_GMBUS_1MHZ   3
-
-struct backlight_info {
-   uint8_t inverter_type:2;/* see BACKLIGHT_TYPE_* above */
-   uint8_t inverter_polarity:1;/* 1 means 0 is max, 255 is min */
-   uint8_t gpio_pins:3;/* see GPIO_PIN_* above */
-   uint8_t gmbus_speed:2;
-   uint16_t pwm_frequency; /* in Hz */
-   uint8_t min_brightness;
-   /* Next two are only for 915+ systems */
-   uint8_t i2c_addr;
-   uint8_t i2c_cmd;
-} __attribute((packed));
-
-struct bdb_backlight_control {
-   uint8_t row_size;
-   struct backlight_info lfps[16];
-} __attribute__ ((packed));
-
-struct bdb_bia {
-   uint8_t bia_enable:1;
-   uint8_t bia_level:3;
-   uint8_t rsvd1:3;
-   uint8_t als_enable:1;
-   uint8_t als_response_data[20];
-} __attribute((packed));
-
-struct aimdb_header {
-   char signature[16];
-   char oem_device[20];
-   uint16_t aimdb_version;
-   uint16_t aimdb_header_size;
-   uint16_t aimdb_size;
-} __attribute__ ((packed));
-
-struct aimdb_block {
-   uint8_t aimdb_id;
-   uint16_t aimdb_size;
-} __attribute__ ((packed));
-
-struct vch_panel_data {
-   uint16_t fp_timing_offset;
-   uint8_t fp_timing_size;
-   uint16_t dvo_timing_offset;
-   uint8_t dvo_timing_size;
-   uint16_t 

[Intel-gfx] [i-g-t PATCH 03/10] tools/intel_vbt_decode: clean up struct lvds_dvo_timing

[Jani Nikula]

For reasons unknown, we have two copies of the struct. Deduplicate.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 19 ---
 tools/intel_vbt_decode.c |  6 +++---
 2 files changed, 3 insertions(+), 22 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index c998031041fd..69d8aa6d7fe9 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -348,25 +348,6 @@ struct lvds_fp_timing {
 } __attribute__ ((packed));
 
 struct lvds_dvo_timing {
-   uint16_t dclk;  /**< In 10khz */
-   uint8_t hactive;
-   uint8_t hblank;
-   uint8_t high_h; /**< 7:4 = hactive 11:8, 3:0 = hblank 11:8 */
-   uint8_t vactive;
-   uint8_t vblank;
-   uint8_t high_v; /**< 7:4 = vactive 11:8, 3:0 = vblank 11:8 */
-   uint8_t hsync_off;
-   uint8_t hsync_pulse_width;
-   uint8_t vsync_off;
-   uint8_t high_hsync_off; /**< 7:6 = hsync off 9:8 */
-   uint8_t h_image;
-   uint8_t v_image;
-   uint8_t max_hv;
-   uint8_t h_border;
-   uint8_t v_border;
-   uint8_t flags;
-} __attribute__ ((packed));
-struct lvds_dvo_timing2 {
uint16_t clock; /**< In 10khz */
uint8_t hactive_lo;
uint8_t hblank_lo;
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index 2984a11e9012..0cf9183e4fcb 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -935,7 +935,7 @@ static void dump_psr(struct context *context,
 }
 
 static void
-print_detail_timing_data(const struct lvds_dvo_timing2 *dvo_timing)
+print_detail_timing_data(const struct lvds_dvo_timing *dvo_timing)
 {
int display, sync_start, sync_end, total;
 
@@ -966,10 +966,10 @@ print_detail_timing_data(const struct lvds_dvo_timing2 
*dvo_timing)
 static void dump_sdvo_panel_dtds(struct context *context,
 const struct bdb_block *block)
 {
-   const struct lvds_dvo_timing2 *dvo_timing = block->data;
+   const struct lvds_dvo_timing *dvo_timing = block->data;
int n, count;
 
-   count = block->size / sizeof(struct lvds_dvo_timing2);
+   count = block->size / sizeof(struct lvds_dvo_timing);
for (n = 0; n < count; n++) {
printf("%d:\n", n);
print_detail_timing_data(dvo_timing++);
-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 05/10] tools/intel_vbt_decode: migrate timing dumping to kernel struct

[Jani Nikula]

Adapt the dumping according to the changes, and do what the kernel does.

Signed-off-by: Jani Nikula 
---
 tools/intel_bios.h   | 28 
 tools/intel_vbt_decode.c |  9 ++---
 tools/intel_vbt_defs.h   | 31 +++
 3 files changed, 37 insertions(+), 31 deletions(-)

diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 65e64ccb41ef..8d1bf7ae0c81 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -155,34 +155,6 @@ struct bdb_child_devices {
struct child_device_config children[DEVICE_CHILD_SIZE];
 } __attribute__ ((packed));
 
-struct lvds_dvo_timing {
-   uint16_t clock; /**< In 10khz */
-   uint8_t hactive_lo;
-   uint8_t hblank_lo;
-   uint8_t hblank_hi:4;
-   uint8_t hactive_hi:4;
-   uint8_t vactive_lo;
-   uint8_t vblank_lo;
-   uint8_t vblank_hi:4;
-   uint8_t vactive_hi:4;
-   uint8_t hsync_off_lo;
-   uint8_t hsync_pulse_width;
-   uint8_t vsync_pulse_width:4;
-   uint8_t vsync_off:4;
-   uint8_t rsvd0:6;
-   uint8_t hsync_off_hi:2;
-   uint8_t h_image;
-   uint8_t v_image;
-   uint8_t max_hv;
-   uint8_t h_border;
-   uint8_t v_border;
-   uint8_t rsvd1:3;
-   uint8_t digital:2;
-   uint8_t vsync_positive:1;
-   uint8_t hsync_positive:1;
-   uint8_t rsvd2:1;
-} __attribute__((packed));
-
 struct blc_struct {
uint8_t inverter_type:2;
uint8_t inverter_polarity:1;/* 1 means inverted (0 = max 
brightness) */
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index 836a9783d54e..beb33672835e 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -950,7 +950,8 @@ print_detail_timing_data(const struct lvds_dvo_timing 
*dvo_timing)
display = (dvo_timing->hactive_hi << 8) | dvo_timing->hactive_lo;
sync_start = display +
((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
-   sync_end = sync_start + dvo_timing->hsync_pulse_width;
+   sync_end = sync_start + ((dvo_timing->hsync_pulse_width_hi) << 8 |
+dvo_timing->hsync_pulse_width_lo);
total = display +
((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
printf("\thdisplay: %d\n", display);
@@ -959,8 +960,10 @@ print_detail_timing_data(const struct lvds_dvo_timing 
*dvo_timing)
printf("\thtotal: %d\n", total);
 
display = (dvo_timing->vactive_hi << 8) | dvo_timing->vactive_lo;
-   sync_start = display + dvo_timing->vsync_off;
-   sync_end = sync_start + dvo_timing->vsync_pulse_width;
+   sync_start = display + ((dvo_timing->vsync_off_hi << 8) |
+   dvo_timing->vsync_off_lo);
+   sync_end = sync_start + ((dvo_timing->vsync_pulse_width_hi << 8) |
+dvo_timing->vsync_pulse_width_lo);
total = display +
((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
printf("\tvdisplay: %d\n", display);
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index 5481304d2ac2..8bdb2292747b 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -379,6 +379,37 @@ struct lvds_fp_timing {
u16 terminator;
 } __packed;
 
+struct lvds_dvo_timing {
+   u16 clock;  /**< In 10khz */
+   u8 hactive_lo;
+   u8 hblank_lo;
+   u8 hblank_hi:4;
+   u8 hactive_hi:4;
+   u8 vactive_lo;
+   u8 vblank_lo;
+   u8 vblank_hi:4;
+   u8 vactive_hi:4;
+   u8 hsync_off_lo;
+   u8 hsync_pulse_width_lo;
+   u8 vsync_pulse_width_lo:4;
+   u8 vsync_off_lo:4;
+   u8 vsync_pulse_width_hi:2;
+   u8 vsync_off_hi:2;
+   u8 hsync_pulse_width_hi:2;
+   u8 hsync_off_hi:2;
+   u8 himage_lo;
+   u8 vimage_lo;
+   u8 vimage_hi:4;
+   u8 himage_hi:4;
+   u8 h_border;
+   u8 v_border;
+   u8 rsvd1:3;
+   u8 digital:2;
+   u8 vsync_positive:1;
+   u8 hsync_positive:1;
+   u8 non_interlaced:1;
+} __packed;
+
 struct lvds_pnp_id {
u16 mfg_name;
u16 product_code;
-- 
2.11.0

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[Intel-gfx] [i-g-t PATCH 01/10] tools/intel_lid: use local register definition

[Jani Nikula]

This makes the future intel_vbt_decode refactoring easier.

Signed-off-by: Jani Nikula 
---
 tools/intel_lid.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/intel_lid.c b/tools/intel_lid.c
index 0703e2e1e14e..37c6ba5e443f 100644
--- a/tools/intel_lid.c
+++ b/tools/intel_lid.c
@@ -39,9 +39,10 @@
 
 #include "intel_io.h"
 #include "intel_reg.h"
-#include "intel_bios.h"
 #include "intel_chipset.h"
 
+#define SWF14_LID_STATUS_CLOSED(1<<29) /* 0 here means open */
+
 enum lid_status {
LID_UNKNOWN = -1,
LID_OPEN,
@@ -125,7 +126,7 @@ int main(int argc, char **argv)
 
printf("Intel LVDS Lid status:\n");
printf("\tSWF14(0x%x) : %s\n", swf14,
-  swf14 & SWF14_LID_SWITCH_EN ? "close" : "open");
+  swf14 & SWF14_LID_STATUS_CLOSED ? "close" : "open");
 
acpi_lid = i830_lvds_acpi_lid_state();
switch (acpi_lid) {
-- 
2.11.0

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[Intel-gfx] [PATCH v2] drm/i915: Beef up of Beef up the IPS vs. CRC workaround

[Marta Lofstedt]

Commit 6e644626945c7c1a7f4d4f83b806b898297846d0 was
supposed to solve below bug. However, the patch I tested
is not the same as the one that got merged.
With this addition the test pass.

V2: removed unused: "struct intel_crtc *intel_crtc"

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101664

Signed-off-by: Marta Lofstedt 
---
 drivers/gpu/drm/i915/intel_pipe_crc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 4e22bb927fed..96043a51c1bf 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -919,7 +919,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const 
char *source_name,
 {
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_pipe_crc *pipe_crc = _priv->pipe_crc[crtc->index];
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum intel_display_power_domain power_domain;
enum intel_pipe_crc_source source;
u32 val = 0; /* shut up gcc */
@@ -951,8 +950,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const 
char *source_name,
else if ((IS_HASWELL(dev_priv) ||
  IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
hsw_pipe_A_crc_wa(dev_priv, false);
-
-   hsw_enable_ips(intel_crtc);
}
 
pipe_crc->skipped = 0;
-- 
2.11.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Patchwork]

== Series Details ==

Series: series starting with [1/1] igt/dapc: Test Driver Assisted Performance 
Capture (DAPC)
URL   : https://patchwork.freedesktop.org/series/29418/
State : failure

== Summary ==

IGT patchset build failed on latest successful build
60f6a12195395934f179d5ecc080353190d19a6c tests: chamelium: Eliminate reset when 
preparing output

make  all-recursive
Making all in lib
make  all-recursive
Making all in .
Making all in tests
make[4]: Nothing to be done for 'all'.
Making all in man
make[2]: Nothing to be done for 'all'.
Making all in tools
Making all in null_state_gen
make[3]: Nothing to be done for 'all'.
Making all in registers
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all-am'.
Making all in scripts
make[2]: Nothing to be done for 'all'.
Making all in benchmarks
make[2]: Nothing to be done for 'all'.
Making all in tests
Making all in intel-ci
make[3]: Nothing to be done for 'all'.
  CCLD gem_bad_batch
  CCLD gem_hang
  CCLD gem_bad_blit
  CCLD gem_bad_address
  CCLD gem_non_secure_batch
  CCLD gem_stress
  CCLD core_auth
  CCLD core_get_client_auth
  CCLD core_getclient
  CCLD core_getstats
  CCLD core_getversion
  CCLD core_prop_blob
  CCLD core_setmaster_vs_auth
  CC   dapc.o
dapc.c:176:3: error: ‘I915_OA_FORMAT_A12’ undeclared here (not in a function)
  [I915_OA_FORMAT_A12]  = { 0, 64 },
   ^~
dapc.c:176:3: error: array index in initializer not of integer type
dapc.c:176:3: note: (near initialization for ‘gen8_plus_oa_formats’)
dapc.c:177:3: error: ‘I915_OA_FORMAT_A12_B8_C8’ undeclared here (not in a 
function)
  [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
   ^~~~
dapc.c:177:3: error: array index in initializer not of integer type
dapc.c:177:3: note: (near initialization for ‘gen8_plus_oa_formats’)
dapc.c:178:3: error: ‘I915_OA_FORMAT_A32u40_A4u32_B8_C8’ undeclared here (not 
in a function)
  [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
   ^
dapc.c:178:3: error: array index in initializer not of integer type
dapc.c:178:3: note: (near initialization for ‘gen8_plus_oa_formats’)
dapc.c: In function ‘get_card_for_fd’:
dapc.c:284:2: warning: ‘readdir_r’ is deprecated [-Wdeprecated-declarations]
  while ((readdir_r(drm_dir, entry1, ) == 0) && entry2 != NULL)
  ^
In file included from /usr/include/glib-2.0/glib/gdir.h:32:0,
 from /usr/include/glib-2.0/glib.h:45,
 from ./../lib/igt_core.h:43,
 from dapc.c:37:
/usr/include/dirent.h:183:12: note: declared here
 extern int readdir_r (DIR *__restrict __dirp,
^
dapc.c: At top level:
dapc.c:340:5: warning: no previous prototype for ‘read_perf_dapc_samples’ 
[-Wmissing-prototypes]
 int read_perf_dapc_samples(uint8_t *temp_buf, uint8_t *out_data,
 ^~
dapc.c: In function ‘read_perf_dapc_samples’:
dapc.c:81:8: error: ‘I915_PERF_MMIO_NUM_MAX’ undeclared (first use in this 
function)
  4*I915_PERF_MMIO_NUM_MAX) /* MMIO reg */
^
dapc.c:94:40: note: in expansion of macro ‘TS_MMIO_SAMPLE_SIZE_MAX’
 #define READ_TS_MMIO_BUF_SIZE_MAX (100*TS_MMIO_SAMPLE_SIZE_MAX)
^~~
dapc.c:350:19: note: in expansion of macro ‘READ_TS_MMIO_BUF_SIZE_MAX’
   max_read_size = READ_TS_MMIO_BUF_SIZE_MAX;
   ^
dapc.c:81:8: note: each undeclared identifier is reported only once for each 
function it appears in
  4*I915_PERF_MMIO_NUM_MAX) /* MMIO reg */
^
dapc.c:94:40: note: in expansion of macro ‘TS_MMIO_SAMPLE_SIZE_MAX’
 #define READ_TS_MMIO_BUF_SIZE_MAX (100*TS_MMIO_SAMPLE_SIZE_MAX)
^~~
dapc.c:350:19: note: in expansion of macro ‘READ_TS_MMIO_BUF_SIZE_MAX’
   max_read_size = READ_TS_MMIO_BUF_SIZE_MAX;
   ^
dapc.c:394:9: error: ‘I915_PERF_SAMPLE_OA_SOURCE_RCS’ undeclared (first use in 
this function)
 I915_PERF_SAMPLE_OA_SOURCE_RCS) {
 ^~
dapc.c: At top level:
dapc.c:415:6: warning: no previous prototype for ‘read_metrics_id_from_sysfs’ 
[-Wmissing-prototypes]
 bool read_metrics_id_from_sysfs(int *metrics_id)
  ^~
dapc.c: In function ‘open_i915_rcs_oa_stream’:
dapc.c:456:3: error: ‘DRM_I915_PERF_PROP_ENGINE’ undeclared (first use in this 
function)
   DRM_I915_PERF_PROP_ENGINE, ring_id,
   ^
dapc.c:457:3: error: ‘DRM_I915_PERF_PROP_SAMPLE_OA_SOURCE’ undeclared (first 
use in this function)
   DRM_I915_PERF_PROP_SAMPLE_OA_SOURCE, true,
   ^~~
dapc.c:458:3: error: ‘DRM_I915_PERF_PROP_SAMPLE_CTX_ID’ undeclared (first use 
in this function)
   DRM_I915_PERF_PROP_SAMPLE_CTX_ID, true,
   ^~~~
dapc.c:459:3: error: ‘DRM_I915_PERF_PROP_SAMPLE_PID’ undeclared 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Beef up of Beef up the IPS vs. CRC workaround

[Patchwork]

== Series Details ==

Series: drm/i915: Beef up of Beef up the IPS vs. CRC workaround
URL   : https://patchwork.freedesktop.org/series/29425/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_pipe_crc.o
drivers/gpu/drm/i915/intel_pipe_crc.c: In function ‘intel_crtc_set_crc_source’:
drivers/gpu/drm/i915/intel_pipe_crc.c:922:21: error: unused variable 
‘intel_crtc’ [-Werror=unused-variable]
  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 ^~
cc1: all warnings being treated as errors
scripts/Makefile.build:302: recipe for target 
'drivers/gpu/drm/i915/intel_pipe_crc.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_pipe_crc.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Recreate vmapping even when the object is pinned (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Recreate vmapping even when the object is pinned (rev2)
URL   : https://patchwork.freedesktop.org/series/29388/
State : success

== Summary ==

Series 29388v2 drm/i915: Recreate vmapping even when the object is pinned
https://patchwork.freedesktop.org/api/1.0/series/29388/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:458s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:437s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:554s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:512s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:261  dwarn:0   dfail:0   fail:2   skip:16  
time:464s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:427s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:471s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:603s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:526s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:468s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:476s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:438s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:487s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:406s

00b77f621f835bc114b79ec897b9aa277ea5726b drm-tip: 2017y-08m-28d-10h-25m-08s UTC 
integration manifest
1dad816b4277 drm/i915: Recreate vmapping even when the object is pinned

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5507/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove excess indent in intel_finish_reset() caught by sparse

[Patchwork]

== Series Details ==

Series: drm/i915: Remove excess indent in intel_finish_reset() caught by sparse
URL   : https://patchwork.freedesktop.org/series/29424/
State : success

== Summary ==

Series 29424v1 drm/i915: Remove excess indent in intel_finish_reset() caught by 
sparse
https://patchwork.freedesktop.org/api/1.0/series/29424/revisions/1/mbox/

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:446s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:560s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:256s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:523s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:516s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:612s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:456s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:418s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:497s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:609s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:594s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:527s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:502s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:502s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:401s

00b77f621f835bc114b79ec897b9aa277ea5726b drm-tip: 2017y-08m-28d-10h-25m-08s UTC 
integration manifest
1403c89af085 drm/i915: Remove excess indent in intel_finish_reset() caught by 
sparse

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5506/
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[Intel-gfx] [PATCH] drm/i915: Beef up of Beef up the IPS vs. CRC workaround

[Marta Lofstedt]

Commit 6e644626945c7c1a7f4d4f83b806b898297846d0 was
supposed to solve below bug. However, the patch I tested
is not the same as the one that got merged.
With this addition the test pass.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101664

Signed-off-by: Marta Lofstedt 
---
 drivers/gpu/drm/i915/intel_pipe_crc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 4e22bb927fed..f79f9a42798d 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -951,8 +951,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const 
char *source_name,
else if ((IS_HASWELL(dev_priv) ||
  IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
hsw_pipe_A_crc_wa(dev_priv, false);
-
-   hsw_enable_ips(intel_crtc);
}
 
pipe_crc->skipped = 0;
-- 
2.11.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for Adding NV12 support (rev2)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev2)
URL   : https://patchwork.freedesktop.org/series/28103/
State : failure

== Summary ==

Series 28103v2 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/2/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-kbl-7500u)

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:452s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:435s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:368s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:556s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:234s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:516s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:440s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:453s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:502s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7500u total:238  pass:222  dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:595s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:595s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:525s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:462s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:500s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s

00b77f621f835bc114b79ec897b9aa277ea5726b drm-tip: 2017y-08m-28d-10h-25m-08s UTC 
integration manifest
149fc1e88a51 drm/i915: Add NV12 support to intel_framebuffer_init
26135eea1a26 drm/i915: Add NV12 as supported format for sprite plane
2083ffe043b7 drm/i915: Add NV12 as supported format for primary plane
93ab85476653 drm/i915: Upscale scaler max scale for NV12
d291f3965561 drm/i915: Update format_is_yuv() to include NV12
b6c629b41415 drm/i915: Set scaler mode for NV12

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5505/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for i915 perf support for command stream based OA, GPU and workload metrics capture (rev2)

[Patchwork]

== Series Details ==

Series: i915 perf support for command stream based OA, GPU and workload metrics 
capture (rev2)
URL   : https://patchwork.freedesktop.org/series/28104/
State : failure

== Summary ==

Test perf:
Subgroup short-reads:
pass   -> FAIL   (shard-hsw)
Subgroup disabled-read-error:
pass   -> FAIL   (shard-hsw)
Subgroup buffer-fill:
pass   -> INCOMPLETE (shard-hsw)
Subgroup missing-sample-flags:
pass   -> INCOMPLETE (shard-hsw)
Subgroup blocking:
pass   -> INCOMPLETE (shard-hsw) fdo#102252
Test kms_plane_multiple:
Subgroup atomic-pipe-A-tiling-x:
pass   -> SKIP   (shard-hsw)
Test gem_ctx_param:
Subgroup invalid-param-get:
pass   -> FAIL   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2133 pass:1176 dwarn:0   dfail:0   fail:19  skip:935 
time:9259s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5503/shards.html
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[Intel-gfx] [PATCH v2] drm/i915: Recreate vmapping even when the object is pinned

[Chris Wilson]

Sometimes we know we are the only user of the bo, but since we take a
protective pin_pages early on, an attempt to change the vmap on the
object is denied because it is busy. i915_gem_object_pin_map() cannot
tell from our single pin_count if the operation is safe. Instead we must
pass that information down from the caller in the manner of
I915_MAP_OVERRIDE.

This issue has existed from the introduction of the mapping, but was
never noticed as the only place where this conflict might happen is for
cached kernel buffers (such as allocated by i915_gem_batch_pool_get()).
Until recently there was only a single user (the cmdparser) so no
conflicts ever occurred. However, we now use it to allocate batches for
different operations (using MAP_WC on !llc for writes) in addition to the
existing shadow batch (using MAP_WB for reads).

We could either keep both mappings cached, or use a different write
mechanism if we detect a MAP_WB already exists (i.e. clflush
afterwards), but as we haven't seen this issue in the wild (it requires
hitting the GPU reloc path in addition to the cmdparser) for simplicity
just allow the mappings to be recreated.

v2: Include the i915_MAP_OVERRIDE bit in the enum so the compiler knows
about all the valid values.

Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
Testcase: igt/gem_lut_handle # byt, completely by accident
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 3 +++
 drivers/gpu/drm/i915/i915_gem.c| 7 ++-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +++-
 4 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index f0cb22cc0dd6..8ba932b22f7c 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1073,7 +1073,7 @@ static u32 *copy_batch(struct drm_i915_gem_object 
*dst_obj,
goto unpin_src;
}
 
-   dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
+   dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);
if (IS_ERR(dst))
goto unpin_dst;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8352cbe0c444..0383e879a315 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3485,6 +3485,9 @@ void __i915_gem_object_invalidate(struct 
drm_i915_gem_object *obj);
 enum i915_map_type {
I915_MAP_WB = 0,
I915_MAP_WC,
+#define I915_MAP_OVERRIDE BIT(31)
+   I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
+   I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 37fbc64d9ffe..43834dee4e8d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2553,6 +2553,9 @@ static void *i915_gem_object_map(const struct 
drm_i915_gem_object *obj,
GEM_BUG_ON(i != n_pages);
 
switch (type) {
+   default:
+   MISSING_CASE(type);
+   /* fallthrough to use PAGE_KERNEL anyway */
case I915_MAP_WB:
pgprot = PAGE_KERNEL;
break;
@@ -2583,7 +2586,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object 
*obj,
if (ret)
return ERR_PTR(ret);
 
-   pinned = true;
+   pinned = !(type & I915_MAP_OVERRIDE);
+   type &= ~I915_MAP_OVERRIDE;
+
if (!atomic_inc_not_zero(>mm.pages_pin_count)) {
if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
ret = i915_gem_object_get_pages(obj);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1c4fac032329..dcce69a23309 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1071,7 +1071,9 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
return PTR_ERR(obj);
 
cmd = i915_gem_object_pin_map(obj,
- cache->has_llc ? I915_MAP_WB : 
I915_MAP_WC);
+ cache->has_llc ?
+ I915_MAP_FORCE_WB :
+ I915_MAP_FORCE_WC);
i915_gem_object_unpin_pages(obj);
if (IS_ERR(cmd))
return PTR_ERR(cmd);
-- 
2.14.1

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[Intel-gfx] [PATCH] drm/i915: Remove excess indent in intel_finish_reset() caught by sparse

[Chris Wilson]

  CHECK   drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_display.c:3753 intel_finish_reset() warn: 
inconsistent indenting

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f2cd94..7317e1d1c1e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3750,8 +3750,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
if (!gpu_reset_clobbers_display(dev_priv)) {
/* for testing only restore the display */
ret = __intel_display_resume(dev, state, ctx);
-   if (ret)
-   DRM_ERROR("Restoring old state failed with 
%i\n", ret);
+   if (ret)
+   DRM_ERROR("Restoring old state failed with %i\n", ret);
} else {
/*
 * The display has been reset as well,
-- 
2.14.1

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[Intel-gfx] [PATCH 5/6] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 47e5ba9..5b49e4e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1197,6 +1197,19 @@ static bool 
intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
 .format_mod_supported = intel_sprite_plane_format_mod_supported,
 };
 
+static uint32_t nv12_plane_formats[] = {
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_YUYV,
+   DRM_FORMAT_YVYU,
+   DRM_FORMAT_UYVY,
+   DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
+};
+
 struct intel_plane *
 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
  enum pipe pipe, int plane)
@@ -1239,9 +1252,14 @@ struct intel_plane *
 
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
-
-   plane_formats = skl_plane_formats;
-   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+   if (IS_BROXTON(dev_priv) &&
+   (pipe == PIPE_A || pipe == PIPE_B)) {
+   plane_formats = nv12_plane_formats;
+   num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
+   } else {
+   plane_formats = skl_plane_formats;
+   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+   }
modifiers = skl_plane_format_modifiers;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_plane->can_scale = false;
-- 
1.9.1

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[Intel-gfx] [PATCH 3/6] drm/i915: Upscale scaler max scale for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 33 +++--
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f..4e73d88 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3451,6 +3451,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4707,7 +4709,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
 {
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4723,7 +4726,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 * the 90/270 degree plane rotation cases (to match the
 * GTT mapping), hence no need to account for rotation here.
 */
-   need_scaling = src_w != dst_w || src_h != dst_h;
+   need_scaling = src_w != dst_w || src_h != dst_h ||
+   (pixel_format == DRM_FORMAT_NV12);
 
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4802,7 +4806,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
 }
 
 /**
@@ -4832,7 +4836,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(_state->base.src) >> 16,
drm_rect_height(_state->base.src) >> 16,
drm_rect_width(_state->base.dst),
-   drm_rect_height(_state->base.dst));
+   drm_rect_height(_state->base.dst),
+   fb ? fb->format->format : 0);
 
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4858,6 +4863,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
@@ -12836,11 +12842,12 @@ static void add_rps_boost_after_vblank(struct 
drm_crtc *crtc,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+   struct intel_crtc_state *crtc_state, uint32_t pixel_format)
 {
struct drm_i915_private *dev_priv;
-   int max_scale;
-   int crtc_clock, max_dotclk;
+   int max_scale, mult;
+   int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12862,8 +12869,10 @@ static void add_rps_boost_after_vblank(struct drm_crtc 
*crtc,
 *or
 *cdclk/crtc_clock
 */
-   max_scale = min((1 << 16) * 3 - 1,
-   (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+   mult 

[Intel-gfx] [PATCH 1/6] drm/i915: Set scaler mode for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_atomic.c | 8 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae..ac61135 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6582,6 +6582,7 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..808f8e6 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
 
/* set scaler mode */
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   if (plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   DRM_ERROR("NV12 format setting scaler mode\n");
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_NV12;
+   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
scaler_state->scalers[*scaler_id].mode = 0;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
-- 
1.9.1

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[Intel-gfx] [PATCH 6/6] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 6cf8806..615c7cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14095,6 +14095,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (!IS_BROXTON(dev_priv)) {
+   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+   _name));
+   goto err;
+   }
+   break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));
-- 
1.9.1

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[Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 4e73d88..6cf8806 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -106,6 +106,22 @@
DRM_FORMAT_MOD_INVALID
 };
 
+static const uint32_t nv12_primary_formats[] = {
+   DRM_FORMAT_C8,
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_XRGB2101010,
+   DRM_FORMAT_XBGR2101010,
+   DRM_FORMAT_YUYV,
+   DRM_FORMAT_YVYU,
+   DRM_FORMAT_UYVY,
+   DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
+};
+
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13280,8 +13296,14 @@ static bool 
intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
primary->update_plane = skylake_update_primary_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
-   intel_primary_formats = skl_primary_formats;
-   num_formats = ARRAY_SIZE(skl_primary_formats);
+   if (IS_BROXTON(dev_priv) &&
+   ((pipe == PIPE_A || pipe == PIPE_B))) {
+   intel_primary_formats = nv12_primary_formats;
+   num_formats = ARRAY_SIZE(nv12_primary_formats);
+   } else {
+   intel_primary_formats = skl_primary_formats;
+   num_formats = ARRAY_SIZE(skl_primary_formats);
+   }
if (pipe < PIPE_C)
modifiers = skl_format_modifiers_ccs;
else
-- 
1.9.1

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[Intel-gfx] [PATCH 2/6] drm/i915: Update format_is_yuv() to include NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 524933b..54f876e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -42,13 +42,14 @@
 #include "i915_drv.h"
 
 static bool
-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -331,7 +332,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc)
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
 
/*
@@ -895,7 +896,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state 
*crtc_state,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
 
-   if (format_is_yuv(fb->format->format)) {
+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
 
-- 
1.9.1

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[Intel-gfx] [PATCH 0/6] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after
rebasing on latest drm-intel-nightly. Initial series of the patches
can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
Patches were initial reviewed last when floated but
currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Rebase of the current NV12 patch series has been done as per the
current changes on drm-intel-nightly.
Review comments from Ville (12th June 2017) have been addressed
Review comments from Clinton A Taylor (7th July 2017) have been
addressed
Review comments from Clinton A Taylor (10th July 2017) have been
addressed. Had missed out tested-by/reviewed-by in the patches.
Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from last rev:
Rebased the series as Ville's patches are merged. Previously,
this series included those floating patches.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_atomic.c  |  8 -
 drivers/gpu/drm/i915/intel_display.c | 67 +---
 drivers/gpu/drm/i915/intel_drv.h |  3 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 34 ++
 5 files changed, 92 insertions(+), 21 deletions(-)

-- 
1.9.1

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Re: [Intel-gfx] [PATCH i-g-t] pm_rps: Extended testcases with checking PMINTRMSK register value

[Dec, Katarzyna]

On Wed, 2017-08-23 at 17:04 +0200, Daniel Vetter wrote:
> On Tue, Aug 22, 2017 at 01:14:19PM +, Szwichtenberg, Radoslaw
> wrote:
> > On Tue, 2017-08-22 at 13:33 +0100, Chris Wilson wrote:
> > > Quoting Szwichtenberg, Radoslaw (2017-08-22 12:56:00)
> > > > On Tue, 2017-08-22 at 01:31 +0300, Arkadiusz Hiler wrote:
> > > > > On Mon, Aug 21, 2017 at 09:39:24PM +0200, Daniel Vetter
> > > > > wrote:
> > > > > > On Mon, Aug 21, 2017 at 11:21:49AM +0100, Chris Wilson
> > > > > > wrote:
> > > > > > > Quoting Chris Wilson (2017-08-21 10:53:36)
> > > > > > > > Quoting Arkadiusz Hiler (2017-08-21 10:42:25)
> > > > > > > > > On Mon, Aug 21, 2017 at 08:05:58AM +, Dec,
> > > > > > > > > Katarzyna wrote:
> > > > > > > > > > I understand we do not want to check registers in
> > > > > > > > > > IGT tests.
> > > > > > > > > > What
> > > > > > > > > > about reading interrupt masks from debugfs
> > > > > > > > > > (i915_frequency_info).
> > > > > > > > > 
> > > > > > > > > Hey Kasia
> > > > > > > > > 
> > > > > > > > > It would be pretty much the same thing, but instead
> > > > > > > > > of us reading
> > > > > > > > > the
> > > > > > > > > PMINTRMASK directly we would ask the kernel to do
> > > > > > > > > that on our
> > > > > > > > > behalf.
> > > > > > > > > 
> > > > > > > > > That would just hide register read, not get rid of
> > > > > > > > > it.
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > I think you are missing the point. The idea is that
> > > > > > > > > we do not want
> > > > > > > > > to
> > > > > > > > > test details of in-kernel implementation, not ban the
> > > > > > > > > register
> > > > > > > > > reads
> > > > > > > > > completely.
> > > > > > > > > 
> > > > > > > > > Reading register directly, especially just to make
> > > > > > > > > sure that the
> > > > > > > > > kernel
> > > > > > > > > set something correctly is a good indicator that we
> > > > > > > > > are trying to
> > > > > > > > > do
> > > > > > > > > just that - test the internal details.
> > > > > > > > > 
> > > > > > > > > > Would that be better approach? You guys suggested
> > > > > > > > > > to get
> > > > > > > > > > interested
> > > > > > > > > > in
> > > > > > > > > > kselftests for having such checks, but I am afraid
> > > > > > > > > > that it could
> > > > > > > > > > be
> > > > > > > > > > too much job and we have too few hands to work.
> > > > > > > > > 
> > > > > > > > > How much of an effort would the kselftest be, since
> > > > > > > > > it seems that
> > > > > > > > > you
> > > > > > > > > did some
> > > > > > > > > investigation already?
> > > > > > > > 
> > > > > > > > It doesn't even require a whole selftest, just
> > > > > > > > something like
> > > > > > > > 
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > index 448e71af4772..e83b67fe0354 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > @@ -7733,7 +7733,8 @@ void
> > > > > > > > intel_suspend_gt_powersave(struct
> > > > > > > > drm_i915_private *dev_priv)
> > > > > > > > if (cancel_delayed_work_sync(_priv-
> > > > > > > > > rps.autoenable_work))
> > > > > > > > 
> > > > > > > > intel_runtime_pm_put(dev_priv);
> > > > > > > >  
> > > > > > > > -   /* gen6_rps_idle() will be called later to
> > > > > > > > disable
> > > > > > > > interrupts */
> > > > > > > > +   WARN_ON(I915_READ(GEN6_PMINTRMSK) !=
> > > > > > > > +   gen6_sanitize_rps_pm_mask(dev_priv,
> > > > > > > > ~0));
> > > > > > > >  }
> > > > > > > 
> > > > > > > Wrong spot. We actually need a call from
> > > > > > > intel_runtime_pm_disable_interrupts.
> > > > > > 
> > > > > > Yeah, for consistency checks which are very closely tied to
> > > > > > the
> > > > > > implementation we tend to sprinkle WARN_ON all over the
> > > > > > place. In some
> > > > > > cases those checks are too expensive for production, then
> > > > > > we add a
> > > > > > compile-time-option to hide them (e.g. GEM_BUG_ON).
> > > > > > 
> > > > > > I chatted with Radek, and if I understand things correctly,
> > > > > > the main
> > > > > > value
> > > > > > you derive from these is making sure a frankenstein port to
> > > > > > an older
> > > > > > kernel doesn't miss or miss-apply any critical patches. In-
> > > > > > kernel
> > > > > > consistency checks unfortunately don't really help with
> > > > > > that, but we
> > > > > > heavily rely on these for validation.
> > > > > 
> > > > > Having that stated on the mailing list from the beginning
> > > > > (e.g. in the
> > > > > commit message or as one of the first replies) would help
> > > > > directing the
> > > > > whole discussion on the right track and make us understand
> > > > > your needs
> > > > > better.
> > > > > 
> > > > > I agree with Daniel's earlier statement that we should be
> > > > > very
> > > > > (over)verbose about the changes we are making and purpose
> 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc

[Patchwork]

== Series Details ==

Series: series starting with [1/8] drm/i915: Separate GuC/HuC specific 
functionality from intel_uc
URL   : https://patchwork.freedesktop.org/series/29420/
State : failure

== Summary ==

Series 29420v1 series starting with [1/8] drm/i915: Separate GuC/HuC specific 
functionality from intel_uc
https://patchwork.freedesktop.org/api/1.0/series/29420/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_sync:
Subgroup basic-store-each:
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-skl-x1585l)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-2a)
Subgroup basic-no-display:
pass   -> DMESG-WARN (fi-glk-2a)
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-glk-2a)

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:563s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:506s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:519s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:514s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:257  dwarn:3   dfail:0   fail:0   skip:19  
time:615s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:449s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:494s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:470s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:580s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:584s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:520s
fi-skl-6260u total:279  pass:268  dwarn:0   dfail:0   fail:1   skip:10  
time:459s
fi-skl-6700k total:279  pass:260  dwarn:0   dfail:0   fail:1   skip:18  
time:470s
fi-skl-6770hqtotal:279  pass:268  dwarn:0   dfail:0   fail:1   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:1   skip:13  
time:434s
fi-skl-x1585ltotal:279  pass:267  dwarn:0   dfail:0   fail:1   skip:11  
time:473s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:546s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:402s
fi-bdw-gvtdvm failed to connect after reboot

c52f5322612a688655751c4dd44baa43e39d4dec drm-tip: 2017y-08m-26d-11h-41m-06s UTC 
integration manifest
3c3e0c1856da HAX enable guc submission for CI
eea7658646db drm/i915/guc: Change default GuC FW for KBL to v9.39
c333427db680 drm/i915/guc: Change default GuC FW for BXT to v9.29
301e32c4fc6f drm/i915/guc: Change default GuC FW for SKL to v9.33
f6bb0d1cb2c7 drm/i915/guc: Disable critical logging in GuC by default from GuC 
v9
a59f7ca55717 drm/i915/guc: Fix GuC HW/SW state cleanup in unload path
9074d00deb1f drm/i915/guc: Fix GuC interaction in reset/suspend scenarios
d4191b2e5cf2 drm/i915: Separate GuC/HuC specific functionality from intel_uc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5504/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for pm_rps: Changes in waitboost scenario (rev6)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev6)
URL   : https://patchwork.freedesktop.org/series/28966/
State : warning

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test tools_test:
Subgroup tools_test:
pass   -> DMESG-WARN (shard-hsw)
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test vgem_basic:
Subgroup unload:
pass   -> SKIP   (shard-hsw) fdo#102453
Test pm_rps:
Subgroup reset:
fail   -> PASS   (shard-hsw) fdo#102250 +1
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453
fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250

shard-hswtotal:2230 pass:1229 dwarn:2   dfail:0   fail:17  skip:982 
time:9552s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_109/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for i915 perf support for command stream based OA, GPU and workload metrics capture (rev2)

[Patchwork]

== Series Details ==

Series: i915 perf support for command stream based OA, GPU and workload metrics 
capture (rev2)
URL   : https://patchwork.freedesktop.org/series/28104/
State : success

== Summary ==

Series 28104v2 i915 perf support for command stream based OA, GPU and workload 
metrics capture
https://patchwork.freedesktop.org/api/1.0/series/28104/revisions/2/mbox/

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:441s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:364s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:559s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:525s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:526s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:514s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:505s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:484s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:601s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:468s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:483s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:496s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:477s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:412s

c52f5322612a688655751c4dd44baa43e39d4dec drm-tip: 2017y-08m-26d-11h-41m-06s UTC 
integration manifest
a419e5fcb12f drm/i915: Support for capturing MMIO register values
1b48288a71cf drm/i915: Async check for streams data availability with hrtimer 
rescheduling
f168e3fa2f06 drm/i915: Extract raw GPU timestamps from OA reports to forward in 
perf samples
bde0d0d6eb4e drm/i915: Add support for collecting timestamps on all gpu engines
8b0fab464e1a drm/i915: Link perf stream structures with Engines
b4e368066fb1 drm/i915: Add support for emitting execbuffer tags through OA 
counter reports
0b79f744a467 drm/i915: Add support for having pid output with OA report
4d197fda9cac drm/i915: Populate ctx ID for periodic OA reports
f923eda48bc8 drm/i915: Inform userspace about command stream OA buf overflow
6490dde322c2 drm/i915: Flush periodic samples, in case of no pending CS sample 
requests
3aab294733f8 drm/i915: Define CTX_ID property for perf sampling
a2d5a39d29bb drm/i915: Framework for capturing command stream based OA reports.
bf3d4fd72084 drm/i915: Expose OA sample source to userspace
27302bb9bfd3 drm/i915: Add ctx getparam ioctl parameter to retrieve ctx unique 
id

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5503/
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Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33

[Daniel Stone]

Hi Sagar,

On 28 August 2017 at 10:56, Sagar Arun Kamble  wrote:
> This patch makes v9.33 firmware as default firmware for SKL.
> This update includes (since v6.1):

https://01.org/linuxgraphics/downloads/firmware does not include
v9.33, only 6.1.

Please do not push this patch until it has at least made it out for
public release, and preferably into a linux-firmware tree as well.

Cheers,
Daniel
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[Intel-gfx] [PATCH 8/8] HAX enable guc submission for CI

[Sagar Arun Kamble]

From: Chris Wilson 

---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 38dd283..d16dc39 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
-   .enable_guc_loading = 0,
-   .enable_guc_submission = 0,
+   .enable_guc_loading = 1,
+   .enable_guc_submission = 1,
.guc_log_level = -1,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
-- 
1.9.1

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[Intel-gfx] [PATCH 3/8] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

[Sagar Arun Kamble]

Teardown of GuC HW/SW state was not properly done in unload path.
During unload, we can rely on intel_guc_reset_prepare being done
as part of i915_gem_suspend for disabling GuC interfaces.
We will have to disable GuC submission prior to suspend as that involves
communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
be called as part of i915_gem_suspend during unload as that really
takes care of finishing the GuC operations. Created new parameter for
i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.

v2: Prepared i915_gem_unload. (Michal)

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c|  6 +--
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_gem.c| 79 ++
 drivers/gpu/drm/i915/intel_guc.c   | 13 ++
 drivers/gpu/drm/i915/intel_guc.h   |  1 +
 drivers/gpu/drm/i915/intel_uc.c| 14 +++---
 drivers/gpu/drm/i915/intel_uc_common.h |  1 +
 7 files changed, 103 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b2e8f95..b6cc2fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -601,7 +601,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
 
mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
+   intel_uc_cleanup_hw(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
@@ -682,7 +682,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
 
 cleanup_gem:
-   if (i915_gem_suspend(dev_priv))
+   if (i915_gem_unload(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
 cleanup_uc:
@@ -1375,7 +1375,7 @@ void i915_driver_unload(struct drm_device *dev)
 
i915_driver_unregister(dev_priv);
 
-   if (i915_gem_suspend(dev_priv))
+   if (i915_gem_unload(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8352cbe..d273096 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3606,6 +3606,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_unload(struct drm_i915_private *dev_priv);
 void i915_gem_resume(struct drm_i915_private *dev_priv);
 int i915_gem_fault(struct vm_fault *vmf);
 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 24bed2d..be12358 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4624,6 +4624,85 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
return ret;
 }
 
+int i915_gem_unload(struct drm_i915_private *dev_priv)
+{
+   struct drm_device *dev = _priv->drm;
+   int ret;
+
+   intel_runtime_pm_get(dev_priv);
+   intel_suspend_gt_powersave(dev_priv);
+
+   mutex_lock(>struct_mutex);
+
+   /* We have to flush all the executing contexts to main memory so
+* that they can saved in the hibernation image. To ensure the last
+* context image is coherent, we have to switch away from it. That
+* leaves the dev_priv->kernel_context still active when
+* we actually suspend, and its image in memory may not match the GPU
+* state. Fortunately, the kernel_context is disposable and we do
+* not rely on its state.
+*/
+   ret = i915_gem_switch_to_kernel_context(dev_priv);
+   if (ret)
+   goto err_unlock;
+
+   ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
+   if (ret)
+   goto err_unlock;
+
+   assert_kernel_context_is_current(dev_priv);
+   i915_gem_contexts_lost(dev_priv);
+   mutex_unlock(>struct_mutex);
+
+   cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
+   cancel_delayed_work_sync(_priv->gt.retire_work);
+
+   /* As the idle_work is rearming if it detects a race, play safe and
+* repeat the flush until it is definitely idle.
+*/
+   while 

[Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9

[Sagar Arun Kamble]

critical logging in GuC to enable capturing minimal important logs in
production systems.
i915.guc_log_level controls the verbosity and logging in GuC for logs other
than critical logs. By default, logging in GuC is disabled through
i915.guc_log_level.
This patch introduces new kernel param i915.enable_guc_critical_logging.
For Linux release builds, if needed critical GuC logs can be enabled
separately through this parameter. GuC log snapshot captured in error state
will have these minimal critical events logged.
Default value for this parameter is currently set to false.
This patch updates the initialization parameter sent during GuC load to
disable critical logging unless i915.guc_log_level is set to enable logging
and ensures it is enabled/disabling while enabling/disabling through
debugfs based on i915.enable_guc_critical_logging.

v2: Emulating GuC critical logging through i915.guc_log_level. Setting
this to 0 will make GuC critical logging ON and setting it to 1-4 will
communicate log level of 0-3 to GuC.

Cc: Arkadiusz Hiler 
Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Signed-off-by: Jeff McGee 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_params.c  |  3 ++-
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 24 +---
 drivers/gpu/drm/i915/intel_guc_loader.c | 31 +++
 drivers/gpu/drm/i915/intel_guc_log.c| 26 +++---
 4 files changed, 73 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 8ab003d..38dd283 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -234,7 +234,8 @@ struct i915_params i915 __read_mostly = {
 
 module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
 MODULE_PARM_DESC(guc_log_level,
-   "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+   "GuC firmware logging level (-1:disabled (default), "
+   "0: Critical Logging enabled, 1-4:Normal Logging enabled)");
 
 module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp, 
0400);
 MODULE_PARM_DESC(guc_firmware_path,
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5fa2860..0aac8e8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -122,9 +122,15 @@
 #define   GUC_LOG_VERBOSITY_MED(1 << GUC_LOG_VERBOSITY_SHIFT)
 #define   GUC_LOG_VERBOSITY_HIGH   (2 << GUC_LOG_VERBOSITY_SHIFT)
 #define   GUC_LOG_VERBOSITY_ULTRA  (3 << GUC_LOG_VERBOSITY_SHIFT)
-/* Verbosity range-check limits, without the shift */
+/*
+ * Verbosity range-check limits, without the shift.
+ * GuC log verbosity supported by firmware are 0 to 3.
+ * However, in order to treat the critical GuC logging similar to
+ * other logging levels we have incresed GuC verbosity levels by 1
+ * with Level 0 corresponding to critical GuC logging.
+ */
 #define  GUC_LOG_VERBOSITY_MIN 0
-#define  GUC_LOG_VERBOSITY_MAX 3
+#define  GUC_LOG_VERBOSITY_MAX 4
 #define  GUC_LOG_VERBOSITY_MASK0x000f
 #define  GUC_LOG_DESTINATION_MASK  (3 << 4)
 #define   GUC_LOG_DISABLED (1 << 6)
@@ -132,6 +138,7 @@
 #define   GUC_WQ_TRACK_ENABLED (1 << 8)
 #define   GUC_ADS_ENABLED  (1 << 9)
 #define   GUC_DEBUG_RESERVED   (1 << 10)
+#define   GUC_V9_CRITICAL_LOGGING_DISABLED (1 << 10)
 #define   GUC_ADS_ADDR_SHIFT   11
 #define   GUC_ADS_ADDR_MASK0xf800
 
@@ -139,6 +146,16 @@
 
 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw)   \
+   (((IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && \
+   guc_fw->major_ver_found >= 9) || \
+ (IS_KABYLAKE(dev_priv) && guc_fw->major_ver_found >= 9 && \
+   guc_fw->minor_ver_found >= 39))
+
 /**
  * DOC: GuC Firmware Layout
  *
@@ -539,7 +556,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
-   u32 reserved2:24;
+   u32 critical_logging_enabled:1;
+   u32 reserved2:23;
};
u32 value;
 } __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 81e03a6..0b8d7b2 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -106,6 +106,8 @@ static u32 get_core_family(struct drm_i915_private 
*dev_priv)
 static void guc_params_init(struct drm_i915_private 

[Intel-gfx] [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39

[Sagar Arun Kamble]

This patch makes v9.39 firmware as default firmware for KBL.
This update includes (since v9.14):

- DCC spec changes for BXT + DCT enabling
- Bug Fix for power conservation feature SLPC_DCC
- Scheduler 1-element submission during DCC cycles.
- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Media engine Reset fix.  Correctly marking context for resubmission in
  Media Reset case.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- Async FW in Engine Schedule feature (not enabled from KMD)
- GuC clean up to align developer build in line to production build.
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low
  during CPD flow.
- Fix for submit queue over flow issue
- Enabling IBC on KBL GT3 15W, GT4 45W
- Disabling wrong device ID WA in production signed kernel
- Enabling WA for MSGCH hang issue upto required KBL stepping
- Clear forcewake in CSB when SQ is empty.
- 3Tries of GuC2CSME wake request
- During reset one parameter was not getting accounted
- Disable DCC 1-elem mode submission
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change.No functional change done as part of this
  check in.
- Enabling Guc Log changes for ultra low logging for OCA
- Enabling Dynamic Render Power Well Hysteresis Programming for Compute
  Worklaods
- Enabling build failure check to catch critical section overflow.
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
  Bit
- Aggressive DCC implementation for supported platforms.

Cc: Arkadiusz Hiler 
Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Signed-off-by: Jeff McGee 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3e4dec5..515f6b3 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -58,7 +58,7 @@
 #define BXT_FW_MINOR 29
 
 #define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 14
+#define KBL_FW_MINOR 39
 
 #define GLK_FW_MAJOR 10
 #define GLK_FW_MINOR 56
-- 
1.9.1

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[Intel-gfx] [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33

[Sagar Arun Kamble]

This patch makes v9.33 firmware as default firmware for SKL.
This update includes (since v6.1):

- HuC RSA Keys updated.
- Adding per engine preemption support in GuC scheduler
- Minor bug fixes.
- Added support to log media reset count for host to read it
- Sub-feature level control for power management features.
- Minor clean-up for power management interface.
- Unified power management interface and scheduler interface into
  1 file using same version.
- Bug Fix for multi context scheduler flag.
- DCC spec changes for BXT + DCT enabling
- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Media engine Reset fix.  Correctly marking context for resubmission in
  Media Reset case.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- Async FW in Engine Schedule feature (not enabled from KMD)
- GuC clean up to align developer build in line to production build.
- DCC consistency fix for SKL
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- Enabled WA for MSGCH hang issue
- Clear forcewake in CSB when SQ is empty.
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change.No functional change done as part of this
  check in.
- Enable decoupled freq for SKL GT4
- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request
  has come from ME spec
- During reset one parameter was not getting accounted
- Enabling Guc Log changes for ultra low logging for OCA
- Enabling build failure check to catch critical section overflow.
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
  Bit

Cc: Arkadiusz Hiler 
Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Signed-off-by: Jeff McGee 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 0b8d7b2..2aff3c2 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -51,8 +51,8 @@
  *
  */
 
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 33
 
 #define BXT_FW_MAJOR 8
 #define BXT_FW_MINOR 7
-- 
1.9.1

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[Intel-gfx] [PATCH 2/8] drm/i915/guc: Fix GuC interaction in reset/suspend scenarios

[Sagar Arun Kamble]

Tearing down of guc_ggtt_invalidate/guc_interrupts/guc_communication
setup should happen towards end of reset/suspend as these are
setup back again during recovery/resume.

Prepared helpers intel_guc_pause and intel_guc_unpause that will do
teardown/bringup of this setup along with suspension/resumption of GuC if
loaded. Moved intel_guc_suspend, intel_guc_resume to intel_guc.c.

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c|   6 +-
 drivers/gpu/drm/i915/i915_gem.c|   6 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  52 --
 drivers/gpu/drm/i915/intel_guc.c   | 152 +
 drivers/gpu/drm/i915/intel_guc.h   |   9 +-
 drivers/gpu/drm/i915/intel_uc.c|  29 +-
 6 files changed, 169 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2ae730c..b2e8f95 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1690,8 +1690,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
 
-   intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
 
spin_lock_irq(_priv->irq_lock);
@@ -2486,7 +2484,7 @@ static int intel_runtime_suspend(struct device *kdev)
 */
i915_gem_runtime_suspend(dev_priv);
 
-   intel_guc_suspend(dev_priv);
+   intel_guc_runtime_suspend(_priv->guc);
 
intel_runtime_pm_disable_interrupts(dev_priv);
 
@@ -2571,7 +2569,7 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   intel_guc_resume(dev_priv);
+   intel_guc_runtime_resume(_priv->guc);
 
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ac02785..24bed2d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2842,6 +2842,8 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
 
i915_gem_revoke_fences(dev_priv);
 
+   intel_guc_reset_prepare(_priv->guc);
+
return err;
 }
 
@@ -4576,8 +4578,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
-   intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->gt.retire_work);
 
@@ -4593,6 +4593,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->gt.awake);
WARN_ON(!intel_engines_are_idle(dev_priv));
 
+   intel_guc_system_suspend(_priv->guc);
+
/*
 * Neither the BIOS, ourselves or any other kernel
 * expects the system to be in execlists mode on startup,
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 602ae8a..2f977ab 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1287,55 +1287,3 @@ void i915_guc_submission_disable(struct drm_i915_private 
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
 }
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv:  i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
-   struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
-   u32 data[3];
-
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   gen9_disable_guc_interrupts(dev_priv);
-
-   ctx = dev_priv->kernel_context;
-
-   data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
-   /* any value greater than GUC_POWER_D0 */
-   data[1] = GUC_POWER_D1;
-   /* first page is shared data with GuC */
-   data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv:  i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
-   struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
-   u32 data[3];
-
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   if (i915.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(dev_priv);
-
-   ctx = dev_priv->kernel_context;
-
-   data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
-   data[1] = GUC_POWER_D0;
-   /* first page is shared data with GuC */
-   data[2] = 

[Intel-gfx] [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29

[Sagar Arun Kamble]

This patch makes v9.29 firmware as default firmware for BXT.
This update includes (since v8.7):

- Added support to log media reset count for host to read it
- BXT WA for fixing MTP hangs. WaDisableDOPRenderClkGatingAtSubmit
- Sub-feature level control for power management features.
- Minor clean-up for power management interface.
- Unified power management interface and scheduler interface into
  1 file using same version.
- Bug Fix for multi context scheduler flag.
- DCC spec changes for BXT + DCT enabling
- Springboard based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Enabled IBC for BXT
- Media engine Reset fix.  Correctly marking context for resubmission in
  Media Reset case.
- SLPC Dynamic RPe fix to resolve issues where incorrect frequency was set.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- GuC clean up to align developer build in line to production build.
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- Clear forcewake in CSB when SQ is empty.
- SLPC IBC 1.6 for APL to ensure multiplier does not cap IA below Pe.
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change. No functional change done as part of this
  check in.
- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request
  has come from ME spec
- During reset one parameter was not getting accounted
- Enabling Guc Log changes for ultra low logging for OCA
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Fixing Issue with Default Guc Log changes for OCA using special Control
  Bit

Cc: Arkadiusz Hiler 
Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Signed-off-by: Jeff McGee 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2aff3c2..3e4dec5 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -54,8 +54,8 @@
 #define SKL_FW_MAJOR 9
 #define SKL_FW_MINOR 33
 
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 29
 
 #define KBL_FW_MAJOR 9
 #define KBL_FW_MINOR 14
-- 
1.9.1

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[Intel-gfx] [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc

[Sagar Arun Kamble]

Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
Created intel_guc.c and intel_guc.h for placing GuC specific code.
Created intel_huc.h to refer to HuC specific functions.

v2: Prepared intel_uc_common.h. huc_auth code declaration adjusted.
Moved enable/disable_communication to intel_uc.c (Michal)

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.c|   1 -
 drivers/gpu/drm/i915/i915_guc_submission.c |   1 -
 drivers/gpu/drm/i915/intel_guc.c   | 193 ++
 drivers/gpu/drm/i915/intel_guc.h   | 200 +++
 drivers/gpu/drm/i915/intel_guc_loader.c|   1 -
 drivers/gpu/drm/i915/intel_huc.c   |  50 +-
 drivers/gpu/drm/i915/intel_huc.h   |  38 +
 drivers/gpu/drm/i915/intel_uc.c| 128 +--
 drivers/gpu/drm/i915/intel_uc.h| 254 +
 drivers/gpu/drm/i915/intel_uc_common.h | 101 
 11 files changed, 545 insertions(+), 423 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_uc_common.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b..efc5b30 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -59,6 +59,7 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
+ intel_guc.o \
  intel_guc_ct.o \
  intel_guc_log.o \
  intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f10a078..2ae730c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -50,7 +50,6 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
-#include "intel_uc.h"
 
 static struct drm_driver driver;
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..602ae8a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -23,7 +23,6 @@
  */
 #include 
 #include "i915_drv.h"
-#include "intel_uc.h"
 
 #include 
 
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 000..978a0e3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
+{
+   WARN(1, "Unexpected send: action=%#x\n", *action);
+   return -ENODEV;
+}
+
+static void gen8_guc_raise_irq(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+}
+
+void intel_guc_init_early(struct intel_guc *guc)
+{
+   intel_guc_ct_init_early(>ct);
+
+   mutex_init(>send_mutex);
+   guc->send = intel_guc_send_nop;
+   guc->notify = gen8_guc_raise_irq;
+}
+
+static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
+{
+   GEM_BUG_ON(!guc->send_regs.base);
+   GEM_BUG_ON(!guc->send_regs.count);
+   GEM_BUG_ON(i >= guc->send_regs.count);
+
+   return _MMIO(guc->send_regs.base + 4 * i);
+}
+
+void intel_guc_init_send_regs(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   enum forcewake_domains fw_domains = 0;
+   unsigned int i;
+
+   

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for igt/gem_exec_nop: Headless requires DRM_MASTER for modesetting

[Petri Latvala]

On Sat, Aug 26, 2017 at 02:17:40PM +, Patchwork wrote:
>   CC   gem_exec_nop.o
> Makefile:3922: recipe for target 'gem_exec_nop.o' failed
> Makefile:4407: recipe for target 'all-recursive' failed
> Makefile:530: recipe for target 'all-recursive' failed
> Makefile:462: recipe for target 'all' failed


The missing output is:

In file included from ./../lib/intel_batchbuffer.h:8:0,
 from ./../lib/drmtest.h:39,
 from ./../lib/igt.h:27,
 from gem_exec_nop.c:28:
gem_exec_nop.c: In function ‘__real_main614’:
gem_exec_nop.c:673:28: error: ‘fd’ undeclared (first use in this function)
   igt_require(drmSetMaster(fd) == 0);
^
./../lib/igt_core.h:617:8: note: in definition of macro ‘igt_require’
  if (!(expr)) igt_skip_check(#expr , NULL); \
^~~~
gem_exec_nop.c:673:28: note: each undeclared identifier is reported only once 
for each function it appears in
   igt_require(drmSetMaster(fd) == 0);
^
./../lib/igt_core.h:617:8: note: in definition of macro ‘igt_require’
  if (!(expr)) igt_skip_check(#expr , NULL); \
^~~~

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[Intel-gfx] [PATCH 12/14] drm/i915: Extract raw GPU timestamps from OA reports to forward in perf samples

[Sagar Arun Kamble]

From: Sourab Gupta 

The OA reports contain the least significant 32 bits of the gpu timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu timestamps in the perf samples.

Signed-off-by: Sourab Gupta 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 48 ++--
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 3 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5515e3b..b5e8d95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2720,6 +2720,7 @@ struct drm_i915_private {
u32 ctx_flexeu0_offset;
u32 n_pending_periodic_samples;
u32 pending_periodic_ts;
+   u64 last_gpu_ts;
 
/**
 * The RPT_ID/reason field for Gen8+ includes a bit
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index af33fcd..33842fc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1121,6 +1121,26 @@ static int append_perf_sample(struct i915_perf_stream 
*stream,
 }
 
 /**
+ * get_gpu_ts_from_oa_report - Retrieve absolute gpu timestamp from OA report
+ *
+ * Note: We are assuming that we're updating last_gpu_ts frequently enough so
+ * that it's never possible to see multiple overflows before we compare
+ * sample_ts to last_gpu_ts. Since this is significantly large duration
+ * (~6min for 80ns ts base), we can safely assume so.
+ */
+static u64 get_gpu_ts_from_oa_report(struct drm_i915_private *dev_priv,
+   const u8 *report)
+{
+   u32 sample_ts = *(u32 *)(report + 4);
+   u32 delta;
+
+   delta = sample_ts - (u32)dev_priv->perf.oa.last_gpu_ts;
+   dev_priv->perf.oa.last_gpu_ts += delta;
+
+   return dev_priv->perf.oa.last_gpu_ts;
+}
+
+/**
  * append_oa_buffer_sample - Copies single periodic OA report into userspace
  * read() buffer.
  * @stream: An i915-perf stream opened for OA metrics
@@ -1152,11 +1172,8 @@ static int append_oa_buffer_sample(struct 
i915_perf_stream *stream,
if (sample_flags & SAMPLE_TAG)
data.tag = stream->last_tag;
 
-   /* TODO: Derive timestamp from OA report,
-* after scaling with the ts base
-*/
if (sample_flags & SAMPLE_TS)
-   data.ts = 0;
+   data.ts = get_gpu_ts_from_oa_report(dev_priv, report);
 
if (sample_flags & SAMPLE_OA_REPORT)
data.report = report;
@@ -1730,6 +1747,7 @@ static int append_cs_buffer_sample(struct 
i915_perf_stream *stream,
struct drm_i915_private *dev_priv = stream->dev_priv;
struct i915_perf_sample_data data = { 0 };
u32 sample_flags = stream->sample_flags;
+   u64 gpu_ts = 0;
int ret = 0;
 
if (sample_flags & SAMPLE_OA_REPORT) {
@@ -1745,6 +1763,9 @@ static int append_cs_buffer_sample(struct 
i915_perf_stream *stream,
 sample_ts, U32_MAX);
if (ret)
return ret;
+
+   if (sample_flags & SAMPLE_TS)
+   gpu_ts = get_gpu_ts_from_oa_report(dev_priv, report);
}
 
if (sample_flags & SAMPLE_OA_SOURCE)
@@ -1783,16 +1804,13 @@ static int append_cs_buffer_sample(struct 
i915_perf_stream *stream,
}
 
if (sample_flags & SAMPLE_TS) {
-   /* For RCS, if OA samples are also being collected, derive the
-* timestamp from OA report, after scaling with the TS base.
+   /* If OA sampling is enabled, derive the ts from OA report.
 * Else, forward the timestamp collected via command stream.
 */
-   /* TODO: derive the timestamp from OA report */
-   if (sample_flags & SAMPLE_OA_REPORT)
-   data.ts = 0;
-   else
-   data.ts = *(u64 *) (stream->cs_buffer.vaddr +
+   if (!(sample_flags & SAMPLE_OA_REPORT))
+   gpu_ts = *(u64 *) (stream->cs_buffer.vaddr +
   node->ts_offset);
+   data.ts = gpu_ts;
}
 
return append_perf_sample(stream, buf, count, offset, );
@@ -2960,9 +2978,15 @@ static void i915_perf_stream_enable(struct 
i915_perf_stream *stream)
 {
struct drm_i915_private *dev_priv = stream->dev_priv;
 
-   if (stream->sample_flags & SAMPLE_OA_REPORT)
+   if (stream->sample_flags & SAMPLE_OA_REPORT) {
dev_priv->perf.oa.ops.oa_enable(dev_priv);
 
+   if (stream->sample_flags & SAMPLE_TS)
+   

[Intel-gfx] [PATCH 11/14] drm/i915: Add support for collecting timestamps on all gpu engines

[Sagar Arun Kamble]

From: Sourab Gupta 

With this patch, for RCS, timestamps and OA reports can be collected
together, and provided to userspace in separate sample fields. For other
engines, the capabilility to collect timestamps is added.

The thing to note is that, still only a single stream instance can be
opened at any particular time. Though that stream may now be opened for any
gpu engine, for collection of timestamp samples.

So, this patch doesn't add the support to open multiple concurrent streams,
as yet.

v2: Patching the offsets for TS capture similar to OA.

Signed-off-by: Sourab Gupta 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.h |  18 ++-
 drivers/gpu/drm/i915/i915_gem_request.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c| 223 +---
 drivers/gpu/drm/i915/i915_reg.h |   2 +
 include/uapi/drm/i915_drm.h |   7 +
 5 files changed, 230 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 554f84fb..5515e3b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2242,12 +2242,24 @@ struct i915_perf_cs_sample {
struct drm_i915_gem_request *request;
 
/**
-* @oa_offset: Offset into ``>cs_buffer``
-* where the perf metrics will be collected, when the commands inserted
-* into the command stream are executed by GPU.
+* @oa_offset: Offset into ``>cs_buffer
+* where the OA report will be collected (if the stream is configured
+* for collection of OA samples).
 */
u32 oa_offset;
 
+   /**
+* @ts_offset: Offset into ``>cs_buffer
+* where the timestamps will be collected (if the stream is configured
+* for collection of timestamp data)
+*/
+   u32 ts_offset;
+
+   /**
+* @size: buffer size corresponding to this perf sample
+*/
+   u32 size;
+
/* Is this sample prior to request start or post request end */
enum request_sample_id id;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h 
b/drivers/gpu/drm/i915/i915_gem_request.h
index a2535c6..691a0eb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -200,6 +200,8 @@ struct drm_i915_gem_request {
u32 *post_oa_offset;
u64 pid;
u32 tag;
+   u32 *pre_ts_offset;
+   u32 *post_ts_offset;
 };
 
 extern const struct dma_fence_ops i915_fence_ops;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b6bd730..af33fcd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -292,12 +292,17 @@
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
-/* Data common to periodic and RCS based OA samples */
+#define OA_ADDR_ALIGN 64
+#define TS_ADDR_ALIGN 8
+#define I915_PERF_TS_SAMPLE_SIZE 8
+
+/*Data common to perf samples (periodic OA / CS based OA / Timestamps)*/
 struct i915_perf_sample_data {
u64 source;
u64 ctx_id;
u64 pid;
u64 tag;
+   u64 ts;
const u8 *report;
 };
 
@@ -355,6 +360,7 @@ struct i915_perf_sample_data {
 #define SAMPLE_CTX_ID(1<<2)
 #define SAMPLE_PID   (1<<3)
 #define SAMPLE_TAG   (1<<4)
+#define SAMPLE_TS(1<<5)
 
 /**
  * struct perf_open_properties - for validated properties given to open a 
stream
@@ -498,6 +504,86 @@ static int i915_emit_oa_report_capture(struct 
drm_i915_gem_request *request,
 }
 
 /**
+ * i915_emit_ts_capture - Insert the commands to capture timestamp
+ * data into the GPU command stream
+ * @request: request in whose context the timestamps are being collected.
+ * @preallocate: allocate space in ring for related sample.
+ */
+static int i915_emit_ts_capture(struct drm_i915_gem_request *request,
+   bool preallocate)
+{
+   struct drm_i915_private *dev_priv = request->i915;
+   u32 cmd, len = 6, *cs;
+
+   if (preallocate)
+   request->reserved_space += len;
+   else
+   request->reserved_space -= len;
+
+   cs = intel_ring_begin(request, 6);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   if (request->engine->id == RCS) {
+   if (INTEL_GEN(dev_priv) >= 8)
+   cmd = GFX_OP_PIPE_CONTROL(6);
+   else
+   cmd = GFX_OP_PIPE_CONTROL(5);
+
+   *cs++ = cmd;
+   *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB |
+   PIPE_CONTROL_TIMESTAMP_WRITE;
+   /*
+* Save the address in the ringbuffer where offset for OA report
+* capture is to be placed during __i915_gem_request_submit.
+*/
+   if (preallocate)
+  

[Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Sagar Arun Kamble]

This test verifies different i915 perf sampling options for fields like
PID, CTX ID, Timestamp, OA Report, TAG, MMIO.

Cc: Lionel Landwerlin 
Signed-off-by: Sourab Gupta 
Signed-off-by: Sagar Arun Kamble 
---
 tests/Makefile.sources |1 +
 tests/dapc.c   | 1017 
 2 files changed, 1018 insertions(+)
 create mode 100644 tests/dapc.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..61feb0d 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -26,6 +26,7 @@ TESTS_progs = \
core_getversion \
core_prop_blob \
core_setmaster_vs_auth \
+   dapc \
debugfs_test \
drm_import_export \
drm_mm \
diff --git a/tests/dapc.c b/tests/dapc.c
new file mode 100644
index 000..f49b1cd
--- /dev/null
+++ b/tests/dapc.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright ?? 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * dapc: Driver Assisted Performance Capture
+ *  This tests the i915 perf functionality to sample various metrics by
+ *  associating with the CS stream or just standalone periodic OA samples.
+ *  Verifies fields like PID, CTX ID, Timestamp, OA Report, MMIO, Tags are
+ *  generated properly for each sample.
+ *
+ * Authors:
+ *   Sourab Gupta 
+ *   Sagar Arun Kamble 
+ *
+ */
+#define _GNU_SOURCE
+#include "xf86drm.h"
+#include "i915_drm.h"
+#include "igt_core.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define COLLECT_DATA { \
+   printf("(%s) Collecting data. ", __func__); \
+   printf("Press enter to continue...\n"); \
+   getc(stdin); \
+}
+
+#define OA_SAMPLE_SIZE_MAX (8 +/* drm_i915_perf_record_header */ \
+8 +/* source info */ \
+8 +/* ctx ID */ \
+8 +/* Pid */ \
+8 +/* Tag */ \
+256) /* raw OA counter snapshot */
+
+#define TS_SAMPLE_SIZE_MAX (8 +/* drm_i915_perf_record_header */ \
+8 +/* ctx ID */ \
+8 +/* Pid */ \
+8 +/* Tag */ \
+8) /* Timestamp */ \
+
+#define TS_MMIO_SAMPLE_SIZE_MAX(8 +   /* drm_i915_perf_record_header 
*/ \
+8 +   /* ctx ID */ \
+8 +   /* Pid */ \
+8 +   /* Tag */ \
+8 +   /* Timestamp */ \
+4*I915_PERF_MMIO_NUM_MAX)  /* MMIO reg */
+
+#define OA_TS_MMIO_SAMPLE_SIZE_MAX (8 +   /* drm_i915_perf_record_header */ \
+   8 +   /* source info */ \
+   8 +   /* ctx ID */ \
+   8 +   /* Pid */ \
+   8 +   /* Tag */ \
+   8 +   /* Timestamp */ \
+   (4*I915_PERF_MMIO_NUM_MAX) + /* MMIO reg*/ \
+   256) /* raw OA counter snapshot */
+
+#define READ_OA_BUF_SIZE_MAX   (100*OA_SAMPLE_SIZE_MAX)
+#define READ_TS_BUF_SIZE_MAX   (100*TS_SAMPLE_SIZE_MAX)
+#define READ_TS_MMIO_BUF_SIZE_MAX  (100*TS_MMIO_SAMPLE_SIZE_MAX)
+#define READ_OA_TS_MMIO_BUF_SIZE_MAX   (100*OA_TS_MMIO_SAMPLE_SIZE_MAX)
+
+#define SAMPLE_OA  (1<<0)
+#define SAMPLE_TS  (1<<1)
+#define SAMPLE_MMIO(1<<2)
+
+struct intel_device {
+