[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level.

[Patchwork]

== Series Details ==

Series: series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level.
URL   : https://patchwork.freedesktop.org/series/29508/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1231 dwarn:0   dfail:0   fail:17  skip:982 
time:9671s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5534/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (rev2)
URL   : https://patchwork.freedesktop.org/series/28702/
State : warning

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test kms_fbcon_fbt:
Subgroup fbc:
pass   -> SKIP   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252 +1

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:18  skip:983 
time:9595s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5533/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaFbcSkipSegments
URL   : https://patchwork.freedesktop.org/series/29507/
State : failure

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw)
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:19  skip:982 
time:9540s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5532/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: WaDisableI2mCycleOnWRPort

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaDisableI2mCycleOnWRPort
URL   : https://patchwork.freedesktop.org/series/29506/
State : success

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2230 pass:1230 dwarn:0   dfail:0   fail:18  skip:982 
time:9610s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5531/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
URL   : https://patchwork.freedesktop.org/series/29505/
State : success

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1232 dwarn:0   dfail:0   fail:16  skip:982 
time:9675s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5530/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/gem_flink_basic: Add documentation for subtests

[Patchwork]

== Series Details ==

Series: tests/gem_flink_basic: Add documentation for subtests
URL   : https://patchwork.freedesktop.org/series/29499/
State : success

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2185 pass:1203 dwarn:0   dfail:0   fail:18  skip:964 
time:9426s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_121/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level.

[Patchwork]

== Series Details ==

Series: series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level.
URL   : https://patchwork.freedesktop.org/series/29508/
State : success

== Summary ==

Series 29508v1 series starting with [1/8] drm/i915: Introduce 
intel_ddi_dp_level.
https://patchwork.freedesktop.org/api/1.0/series/29508/revisions/1/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:442s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:561s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:254s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:518s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:510s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:440s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:607s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:442s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:429s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:489s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:597s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:586s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:527s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:491s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:477s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:551s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
b866ac4a3412 drm/i915/cnl: Fix DP max voltage
ca4a613265e9 drm/i915/cnl: Fix DDI hdmi level selection.
0c42dd5b2cf1 drm/i915/cnl: Move ddi buf trans related functions up.
b1cfb8242e86 drm/i915/cnl: Move voltage check into ddi buf trans functions.
1f0aea39bf70 drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
bd7fcd99ee83 drm/i915: Align vswing sequences with old ddi buffer registers.
d652d935d01a drm/i915: decouple gen9 and gen10 dp signal levels.
38d9face694c drm/i915: Introduce intel_ddi_dp_level.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5534/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (rev2)
URL   : https://patchwork.freedesktop.org/series/28702/
State : success

== Summary ==

Series 28702v2 drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
https://patchwork.freedesktop.org/api/1.0/series/28702/revisions/2/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:444s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:553s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:516s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:448s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:495s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:482s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:600s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:527s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:486s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:451s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:494s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:550s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:402s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
d2d16811f053 drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5533/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: add perf support for Coffeelake (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake (rev3)
URL   : https://patchwork.freedesktop.org/series/29489/
State : failure

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2186 pass:1203 dwarn:0   dfail:0   fail:16  skip:967 
time:9481s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5529/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaFbcSkipSegments
URL   : https://patchwork.freedesktop.org/series/29507/
State : success

== Summary ==

Series 29507v1 drm/i915/cnl: WaFbcSkipSegments
https://patchwork.freedesktop.org/api/1.0/series/29507/revisions/1/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:448s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:561s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:522s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:516s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:441s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:430s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:493s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:600s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:594s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:519s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:483s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:404s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
5b3a4809fc72 drm/i915/cnl: WaFbcSkipSegments

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5532/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: WaDisableI2mCycleOnWRPort

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaDisableI2mCycleOnWRPort
URL   : https://patchwork.freedesktop.org/series/29506/
State : success

== Summary ==

Series 29506v1 drm/i915/cnl: WaDisableI2mCycleOnWRPort
https://patchwork.freedesktop.org/api/1.0/series/29506/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:548s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:255s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:518s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:501s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:471s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:591s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:484s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:482s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:409s
fi-bdw-gvtdvm failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
a1d60281b605 drm/i915/cnl: WaDisableI2mCycleOnWRPort

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5531/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
URL   : https://patchwork.freedesktop.org/series/29505/
State : success

== Summary ==

Series 29505v1 drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
https://patchwork.freedesktop.org/api/1.0/series/29505/revisions/1/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:460s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:445s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:561s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:523s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:443s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:615s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:444s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:422s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:511s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:599s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:600s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:528s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:480s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:495s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:452s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:493s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
7f164562d87a drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5530/
___
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[Intel-gfx] [PATCH 4/8] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.

[Rodrigo Vivi]

Sequences for DisplayPort asks us to
" Configure voltage swing and related IO settings.
Refer to DDI Buffer section."

before "Configure and enable DDI_BUF_CTL"

On BXT and CNL this means to execute the ddi vswing sequences.

At this point these sequences calls are getting duplicated for DP
because they are all called from DP link trainning sequences.

However this patch is not yet removing it before a futher discussion
since spec also allows that during link training without disabling
anything:

"
Notes
Changing voltage swing during link training:
Change the swing setting following the DDI Buffer section.
The port does not need to be disabled.
"

Cc: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index eedd29487e0b..506782c1a62a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2136,6 +2136,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_ddi_get_encoder_port(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+   uint32_t level = intel_ddi_dp_level(intel_dp);
 
WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
 
@@ -2148,7 +2149,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
 
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
 
-   if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
+   if (IS_CANNONLAKE(dev_priv))
+   cnl_ddi_vswing_sequence(encoder, level);
+   else if (IS_GEN9_LP(dev_priv))
+   bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+   else
intel_prepare_dp_ddi_buffers(encoder);
 
intel_ddi_init_dp_buf_reg(encoder);
-- 
2.13.2

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[Intel-gfx] [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection.

[Rodrigo Vivi]

Let's get a proper HDMI DDI entry level for vswing programming
sequences on CNL.

Spec doesn't specify any default for HDMI tables,
so let's pick the last entry as the default for now.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3ce02cbd4483..f1757a8e481a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -660,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private 
*dev_priv, enum port por
if (IS_GEN9_LP(dev_priv))
return hdmi_level;
 
-   if (IS_GEN9_BC(dev_priv)) {
+   if (IS_CANNONLAKE(dev_priv)) {
+   cnl_get_buf_trans_hdmi(dev_priv, _hdmi_entries);
+   hdmi_default_entry = n_hdmi_entries - 1;
+   } else if (IS_GEN9_BC(dev_priv)) {
skl_get_buf_trans_hdmi(dev_priv, _hdmi_entries);
hdmi_default_entry = 8;
} else if (IS_BROADWELL(dev_priv)) {
-- 
2.13.2

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[Intel-gfx] [PATCH 8/8] drm/i915/cnl: Fix DP max voltage

[Rodrigo Vivi]

On clock recovery this function is called to find out
the max voltage swing level that we could go.

However gen 9 functions use the old buffer translation tables
to figure that out. That table is not valid for CNL
causing an invalid number of entries and an invalid selection
on the max voltage swing level.

v2: Let's use same approach that previous platforms.

Cc: Ville Syrjälä 
Cc: Clint Taylor 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 35 +++
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f1757a8e481a..97ff082c28a7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
int *n_entries)
}
 }
 
+static int cnl_max_level(struct drm_i915_private *dev_priv,
+enum intel_output_type type)
+{
+   int n_entries = 0;
+
+   switch (type) {
+   case INTEL_OUTPUT_DP:
+   cnl_get_buf_trans_dp(dev_priv, _entries);
+   break;
+   case INTEL_OUTPUT_EDP:
+   cnl_get_buf_trans_edp(dev_priv, _entries);
+   break;
+   case INTEL_OUTPUT_HDMI:
+   cnl_get_buf_trans_hdmi(dev_priv, _entries);
+   break;
+   default:
+   MISSING_CASE(type);
+   return 0;
+   }
+
+   return n_entries - 1;
+}
+
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
port)
 {
int n_hdmi_entries;
@@ -1879,10 +1902,14 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int n_entries;
 
-   if (encoder->type == INTEL_OUTPUT_EDP)
-   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
-   else
-   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   if (IS_CANNONLAKE(dev_priv)) {
+   cnl_max_level(dev_priv, encoder->type);
+   } else {
+   if (encoder->type == INTEL_OUTPUT_EDP)
+   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
+   else
+   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   }
 
if (WARN_ON(n_entries < 1))
n_entries = 1;
-- 
2.13.2

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[Intel-gfx] [PATCH 6/8] drm/i915/cnl: Move ddi buf trans related functions up.

[Rodrigo Vivi]

No functional changes. But those functions will be needed
to get max level for HDMI and DP, so let's move those
up closer to other similar functions existent for previous
platforms.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 122 +++
 1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7b547a7f6c2b..3ce02cbd4483 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 
int *n_entries)
}
 }
 
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
+{
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+   if (voltage == VOLTAGE_INFO_0_85V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
+   return cnl_ddi_translations_hdmi_0_85V;
+   } else if (voltage == VOLTAGE_INFO_0_95V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
+   return cnl_ddi_translations_hdmi_0_95V;
+   } else if (voltage == VOLTAGE_INFO_1_05V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
+   return cnl_ddi_translations_hdmi_1_05V;
+   } else
+   MISSING_CASE(voltage);
+   return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+{
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+   if (voltage == VOLTAGE_INFO_0_85V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
+   return cnl_ddi_translations_dp_0_85V;
+   } else if (voltage == VOLTAGE_INFO_0_95V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
+   return cnl_ddi_translations_dp_0_95V;
+   } else if (voltage == VOLTAGE_INFO_1_05V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
+   return cnl_ddi_translations_dp_1_05V;
+   } else
+   MISSING_CASE(voltage);
+   return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+{
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+   if (dev_priv->vbt.edp.low_vswing) {
+   if (voltage == VOLTAGE_INFO_0_85V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
+   return cnl_ddi_translations_edp_0_85V;
+   } else if (voltage == VOLTAGE_INFO_0_95V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
+   return cnl_ddi_translations_edp_0_95V;
+   } else if (voltage == VOLTAGE_INFO_1_05V) {
+   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
+   return cnl_ddi_translations_edp_1_05V;
+   } else
+   MISSING_CASE(voltage);
+   return NULL;
+   } else {
+   return cnl_get_buf_trans_dp(dev_priv, n_entries);
+   }
+}
+
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
port)
 {
int n_hdmi_entries;
@@ -1829,67 +1890,6 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
-static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
-{
-   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-   if (voltage == VOLTAGE_INFO_0_85V) {
-   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
-   return cnl_ddi_translations_hdmi_0_85V;
-   } else if (voltage == VOLTAGE_INFO_0_95V) {
-   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
-   return cnl_ddi_translations_hdmi_0_95V;
-   } else if (voltage == VOLTAGE_INFO_1_05V) {
-   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
-   return cnl_ddi_translations_hdmi_1_05V;
-   } else
-   MISSING_CASE(voltage);
-   return NULL;
-}
-
-static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
-{
-   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-   if (voltage == VOLTAGE_INFO_0_85V) {
-   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
-   return cnl_ddi_translations_dp_0_85V;
-   } else if (voltage == VOLTAGE_INFO_0_95V) {
-   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
-   return cnl_ddi_translations_dp_0_95V;
-   } else if (voltage == VOLTAGE_INFO_1_05V) {
-   

[Intel-gfx] [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels.

[Rodrigo Vivi]

Let's decouple bxt, glk and cnl dp signal levels
from other DDIs to avoid confusion.

No functional change. Only a reorg to avoid messing
with currently working DP signal levels when
moving voltage swing sequences around to match spec.

v2: ddi_signal_levels is also called from other ddi
platforms, so don't remove IS_GEN9_BC check from
skl_ddi_set_iboos. (Ville).

Cc: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 27 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 10 --
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 3 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e875e05d053..9a887780f99f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp 
*intel_dp)
return translate_signal_level(signal_levels);
 }
 
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+u32 bxt_signal_levels(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
struct intel_encoder *encoder = >base;
enum port port = dport->port;
+   u32 level = intel_ddi_dp_level(intel_dp);
+
+   if (IS_CANNONLAKE(dev_priv))
+   cnl_ddi_vswing_sequence(encoder, level);
+   else
+   bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+
+   return 0;
+}
+
+uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+   struct intel_encoder *encoder = >base;
uint32_t level = intel_ddi_dp_level(intel_dp);
 
if (IS_GEN9_BC(dev_priv))
-   skl_ddi_set_iboost(encoder, level);
-   else if (IS_GEN9_LP(dev_priv))
-   bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-   else if (IS_CANNONLAKE(dev_priv)) {
-   cnl_ddi_vswing_sequence(encoder, level);
-   /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
-   return 0;
-   }
+   skl_ddi_set_iboost(encoder, level);
+
return DDI_BUF_TRANS_SELECT(level);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d3e5fdf0d2fa..49a8c339b2b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
uint32_t signal_levels, mask = 0;
uint8_t train_set = intel_dp->train_set[0];
 
-   if (HAS_DDI(dev_priv)) {
+   if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   signal_levels = bxt_signal_levels(intel_dp);
+   } else if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
-
-   if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
-   signal_levels = 0;
-   else
-   mask = DDI_BUF_EMP_MASK;
+   mask = DDI_BUF_EMP_MASK;
} else if (IS_CHERRYVIEW(dev_priv)) {
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f13091c..469c06000774 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state);
+u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
 
-- 
2.13.2

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[Intel-gfx] [PATCH 5/8] drm/i915/cnl: Move voltage check into ddi buf trans functions.

[Rodrigo Vivi]

Let's start converging CNL buf translations to same style
used on previous platforms. So first thing is to use the
standard signature so we don't need to propagate the voltage
check into other parts of the code, but only on the parts
that it is really useful.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 48 ++--
 1 file changed, 21 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 506782c1a62a..7b547a7f6c2b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1830,9 +1830,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
 }
 
 static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
-  u32 voltage, int *n_entries)
+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 {
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
if (voltage == VOLTAGE_INFO_0_85V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
return cnl_ddi_translations_hdmi_0_85V;
@@ -1842,14 +1843,16 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private 
*dev_priv,
} else if (voltage == VOLTAGE_INFO_1_05V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
return cnl_ddi_translations_hdmi_1_05V;
-   }
+   } else
+   MISSING_CASE(voltage);
return NULL;
 }
 
 static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
-u32 voltage, int *n_entries)
+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 {
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
if (voltage == VOLTAGE_INFO_0_85V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
return cnl_ddi_translations_dp_0_85V;
@@ -1859,14 +1862,16 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
} else if (voltage == VOLTAGE_INFO_1_05V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
return cnl_ddi_translations_dp_1_05V;
-   }
+   } else
+   MISSING_CASE(voltage);
return NULL;
 }
 
 static const struct cnl_ddi_buf_trans *
-cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
- u32 voltage, int *n_entries)
+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
if (dev_priv->vbt.edp.low_vswing) {
if (voltage == VOLTAGE_INFO_0_85V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
@@ -1877,10 +1882,11 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
} else if (voltage == VOLTAGE_INFO_1_05V) {
*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
return cnl_ddi_translations_edp_1_05V;
-   }
+   } else
+   MISSING_CASE(voltage);
return NULL;
} else {
-   return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
+   return cnl_get_buf_trans_dp(dev_priv, n_entries);
}
 }
 
@@ -1888,31 +1894,19 @@ static void cnl_ddi_vswing_program(struct 
drm_i915_private *dev_priv,
u32 level, enum port port, int type)
 {
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
-   u32 n_entries, val, voltage;
+   u32 n_entries, val;
int ln;
 
-   /*
-* Values for each port type are listed in
-* voltage swing programming tables.
-* Vccio voltage found in PORT_COMP_DW3.
-*/
-   voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
if (type == INTEL_OUTPUT_HDMI) {
-   ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
- voltage, _entries);
+   ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, _entries);
} else if (type == INTEL_OUTPUT_DP) {
-   ddi_translations = cnl_get_buf_trans_dp(dev_priv,
-   voltage, _entries);
+   ddi_translations = cnl_get_buf_trans_dp(dev_priv, _entries);
} else if (type == INTEL_OUTPUT_EDP) {
-   ddi_translations = cnl_get_buf_trans_edp(dev_priv,
-voltage, _entries);
+   ddi_translations = cnl_get_buf_trans_edp(dev_priv, _entries);
}
 
-   if (ddi_translations == NULL) {
-   MISSING_CASE(voltage);
+   if (WARN_ON(ddi_translations == NULL))
return;
-   }
 
if (level >= 

[Intel-gfx] [PATCH 3/8] drm/i915: Align vswing sequences with old ddi buffer registers.

[Rodrigo Vivi]

Vswing sequences on BXT and CNL are equivalent
to the ddi buffer registers setting on other platforms.

For some reason it got aligned with skl_ddi_set_iboost what
is semantically incorrect. This forced us to keep skipping
ddi buffer translation tables on the platforms that has
the vswing sequences.

v2: Don't mess with DP signal levels on this patch.

Cc: Vandana Kannan 
Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Ander Conselvan de Oliveira 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 22 ++
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9a887780f99f..eedd29487e0b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct 
intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations;
 
-   if (IS_GEN9_LP(dev_priv))
-   return;
-
switch (encoder->type) {
case INTEL_OUTPUT_EDP:
ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
@@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations_hdmi;
 
-   if (IS_GEN9_LP(dev_priv))
-   return;
-
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 
if (IS_GEN9_BC(dev_priv)) {
@@ -2154,7 +2148,9 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
 
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
 
-   intel_prepare_dp_ddi_buffers(encoder);
+   if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
+   intel_prepare_dp_ddi_buffers(encoder);
+
intel_ddi_init_dp_buf_reg(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
@@ -2180,14 +2176,16 @@ static void intel_ddi_pre_enable_hdmi(struct 
intel_encoder *encoder,
 
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
 
-   intel_prepare_hdmi_ddi_buffers(encoder);
-   if (IS_GEN9_BC(dev_priv))
-   skl_ddi_set_iboost(encoder, level);
+   if (IS_CANNONLAKE(dev_priv))
+   cnl_ddi_vswing_sequence(encoder, level);
else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port,
INTEL_OUTPUT_HDMI);
-   else if (IS_CANNONLAKE(dev_priv))
-   cnl_ddi_vswing_sequence(encoder, level);
+   else
+   intel_prepare_hdmi_ddi_buffers(encoder);
+
+   if (IS_GEN9_BC(dev_priv))
+   skl_ddi_set_iboost(encoder, level);
 
intel_dig_port->set_infoframes(>base,
   has_infoframe,
-- 
2.13.2

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[Intel-gfx] [PATCH 1/8] drm/i915: Introduce intel_ddi_dp_level.

[Rodrigo Vivi]

No functional changes. This only moves the DP level
selection to a separated function that will be later
used to organize better the vswing sequences.

Cc: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0a316a6ccb50..7e875e05d053 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2054,18 +2054,22 @@ static uint32_t translate_signal_level(int 
signal_levels)
return 0;
 }
 
+static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
+{
+   uint8_t train_set = intel_dp->train_set[0];
+   int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+DP_TRAIN_PRE_EMPHASIS_MASK);
+
+   return translate_signal_level(signal_levels);
+}
+
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
struct intel_encoder *encoder = >base;
-   uint8_t train_set = intel_dp->train_set[0];
-   int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
-DP_TRAIN_PRE_EMPHASIS_MASK);
enum port port = dport->port;
-   uint32_t level;
-
-   level = translate_signal_level(signal_levels);
+   uint32_t level = intel_ddi_dp_level(intel_dp);
 
if (IS_GEN9_BC(dev_priv))
skl_ddi_set_iboost(encoder, level);
-- 
2.13.2

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Always wake the device to flush the GTT (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT (rev4)
URL   : https://patchwork.freedesktop.org/series/29436/
State : failure

== Summary ==

Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw)

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:19  skip:982 
time:9668s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5528/shards.html
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[Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Rodrigo Vivi]

Driver’s CPU access to GTT is via the GTTMMADR BAR.

The current HW implementation of that BAR is to only
support <= DW (and maybe QW) writes—not 16/32/64B writes
that could occur with WC and/or SSE/AVX moves.

GTTMMADR must be marked uncacheable (UC).
Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).

v2: Get clarification on the reasons and spec is getting
updated to reflect it now.

Cc: Joonas Lahtinen 
Suggested-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 708b95cd8c30..7da9621d2c60 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2790,13 +2790,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
u64 size)
phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
 
/*
-* On BXT writes larger than 64 bit to the GTT pagetable range will be
-* dropped. For WC mappings in general we have 64 byte burst writes
-* when the WC buffer is flushed, so we can't use it, but have to
+* On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
+* will be dropped. For WC mappings in general we have 64 byte burst
+* writes when the WC buffer is flushed, so we can't use it, but have to
 * resort to an uncached mapping. The WC issue is easily caught by the
 * readback check when writing GTT PTE entries.
 */
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
-- 
2.13.2

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[Intel-gfx] [PATCH] drm/i915/cnl: WaFbcSkipSegments

[Rodrigo Vivi]

Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.

Cc: Paulo Zanoni 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..0072ef79bf34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2939,6 +2939,8 @@ enum i915_power_well_id {
 #define ILK_DPFC_CHICKEN   _MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION(1<<23)
+#define   CNL_SKIP_SEG_EN  (1<<12)
+#define   CNL_SKIP_SEG_COUNT   (1<<10)
 #define ILK_FBC_RT_BASE_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ff0b9f999f..acf793256507 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8283,6 +8283,10 @@ static void cannonlake_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
   SARBUNIT_CLKGATE_DIS);
+
+   /* WaFbcSkipSegments:cnl */
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT);
 }
 
 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.13.2

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[Intel-gfx] [PATCH] drm/i915/cnl: WaDisableI2mCycleOnWRPort

[Rodrigo Vivi]

On CNL B0 stepping GAM is not able to detect some deadlock
condition and then rise the rise the gam_coh_flush.

WA database and spec both mentions to set 4AB8[24]=1 as
workaround. Alghouth register offset 0x4AB8 is not
documented for any platform.

Cc: Mika Kuoppala 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..bbacdac5c794 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2373,6 +2373,7 @@ enum i915_power_well_id {
 
 #define GAMT_CHKN_BIT_REG  _MMIO(0x4ab8)
 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
+#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT   (1<<24)
 
 #if 0
 #define PRB0_TAIL  _MMIO(0x2030)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6ac9d0a4156..f087eb6b0134 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,11 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
 
+   /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
+   if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
+   WA_SET_BIT(GAMT_CHKN_BIT_REG,
+  GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
+
/* WaForceContextSaveRestoreNonCoherent:cnl */
WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-- 
2.13.2

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[Intel-gfx] [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Rodrigo Vivi]

WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.

Cc: Mika Kuoppala 
Cc: Oscar Mateo 
Cc: Ben Widawsky 
Cc: Anuj Phogat 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..1ad22a824921 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8072,6 +8072,7 @@ enum {
 #define   HSW_SAMPLE_C_PERFORMANCE (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC  (1<<5)
+#define   CNL_FAST_ANISO_L1_BANKING_FIX(1<<4)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS(1<<1)
 
 #define GEN9_HALF_SLICE_CHICKEN7   _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6ac9d0a4156..4b9b7828802d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 
+   /* FtrEnableFastAnisoL1BankingFix: cnl */
+   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
-- 
2.13.2

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add a default case in gen7 hwsp switch-case

[Patchwork]

== Series Details ==

Series: drm/i915: Add a default case in gen7 hwsp switch-case
URL   : https://patchwork.freedesktop.org/series/29494/
State : success

== Summary ==

Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2230 pass:1231 dwarn:0   dfail:0   fail:17  skip:982 
time:9668s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5527/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/gem_flink_basic: Add documentation for subtests

[Patchwork]

== Series Details ==

Series: tests/gem_flink_basic: Add documentation for subtests
URL   : https://patchwork.freedesktop.org/series/29499/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
bf45d253648250fc402eee02237366c8882b2053 igt: Add gem_close

with latest DRM-Tip kernel build CI_DRM_3016
428ed27345fb drm-tip: 2017y-08m-29d-17h-43m-11s UTC integration manifest

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:436s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:365s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:550s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:534s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:523s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:517s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:616s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:447s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:595s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:602s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:537s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:490s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:500s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:559s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:404s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_121/
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[Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

[Vinay Belgaumkar]

Added the missing IGT_TEST_DESCRIPTION and some subtest
descriptions.

Signed-off-by: Vinay Belgaumkar 
---
 tests/gem_flink_basic.c | 36 
 1 file changed, 36 insertions(+)

diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
index 26ae7d6..8761e0d 100644
--- a/tests/gem_flink_basic.c
+++ b/tests/gem_flink_basic.c
@@ -36,6 +36,8 @@
 #include 
 #include "drm.h"
 
+IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by name");
+
 static void
 test_flink(int fd)
 {
@@ -155,14 +157,48 @@ igt_main
igt_fixture
fd = drm_open_driver(DRIVER_INTEL);
 
+   /* basic:
+   This subtest creates a gem object, and then creates
+   a flink. It tests that we can gain access to the gem
+   object using the flink name.
+
+   Test fails if flink creation/open fails.
+   **/
igt_subtest("basic")
test_flink(fd);
+
+   /* double-flink:
+   This test checks if it is possible to create 2 flinks
+   for the same gem object.
+
+   Test fails if 2 flink objects cannot be created.
+   **/
igt_subtest("double-flink")
test_double_flink(fd);
+
+   /* bad-flink:
+   Use an invalid flink handle.
+
+   DRM_IOCTL_GEM_FLINK ioctl call should return failure.
+   **/
igt_subtest("bad-flink")
test_bad_flink(fd);
+
+   /* bad-open:
+   Try to use an invalid flink name.
+
+   DRM_IOCTL_GEM_FLINK ioctl call should return failure.
+   **/
igt_subtest("bad-open")
test_bad_open(fd);
+
+   /* flink-lifetime:
+   Check if a flink name can be used even after the drm
+   fd used to create it is closed.
+
+   Flink name should remain valid until the gem object
+   it points to has not been freed.
+   **/
igt_subtest("flink-lifetime")
test_flink_lifetime(fd);
 }
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake (rev3)
URL   : https://patchwork.freedesktop.org/series/29489/
State : success

== Summary ==

Series 29489v3 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29489/revisions/3/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:436s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:553s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:523s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:516s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:612s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:444s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:468s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:589s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:523s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:468s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:485s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:483s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:406s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
60919f594bda drm/i915/perf: add support for Coffeelake GT2
60c4ec5214f5 drm/i915: rework IS_*_GT* macros
485230577d3d drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5529/
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[Intel-gfx] [PATCH v3 3/3] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void

[Intel-gfx] [PATCH v3 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 152 +++
 3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..0ac733baa734 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_FEATURES \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_FEATURES,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_FEATURES,
+   .gt = 2,
+};
+
+#define IVB_M_FEATURES \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_FEATURES,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_FEATURES,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct intel_device_info intel_broadwell_info = {
+static const struct intel_device_info intel_broadwell_gt1_info = {
+   BDW_PLATFORM,
+   

[Intel-gfx] [PATCH v3 2/3] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v3 0/3] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Didn't compile the whole kernel and missed some errors :(

Lionel Landwerlin (3):
  drm/i915: add GT number to intel_device_info
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 ++
 drivers/gpu/drm/i915/i915_pci.c   | 193 ++
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 152 --
 7 files changed, 407 insertions(+), 111 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Always wake the device to flush the GTT (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT (rev4)
URL   : https://patchwork.freedesktop.org/series/29436/
State : success

== Summary ==

Series 29436v4 drm/i915: Always wake the device to flush the GTT
https://patchwork.freedesktop.org/api/1.0/series/29436/revisions/4/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:458s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:439s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:548s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:515s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:514s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:476s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:590s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:601s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:532s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:463s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:488s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:470s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:549s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:407s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
26e7bf1f36fb drm/i915: Always wake the device to flush the GTT

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5528/
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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/audio: Add suspend and hibernate tests for HDMI signal integrity

[Patchwork]

== Series Details ==

Series: tests/audio: Add suspend and hibernate tests for HDMI signal integrity
URL   : https://patchwork.freedesktop.org/series/29485/
State : success

== Summary ==

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1231 dwarn:0   dfail:0   fail:17  skip:982 
time:9635s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_120/shards.html
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[Intel-gfx] [Resend for flip-flops] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Since we hold the device wakeref when writing through the GTT (otherwise
the writes would fail), we presumed that before the device sleeps those
writes would naturally be flushed and that we wouldn't need our mmio
read trick. However, that presumption seems false and a sleepy bxt seems
to require us to always manually flush the GTT writes prior to direct
access.

Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before flushing 
GTT writes")
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 44a7cb0e8bad..e4cc08bc518c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -695,12 +695,11 @@ flush_write_domain(struct drm_i915_gem_object *obj, 
unsigned int flush_domains)
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-   if (intel_runtime_pm_get_if_in_use(dev_priv)) {
-   spin_lock_irq(_priv->uncore.lock);
-   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
-   spin_unlock_irq(_priv->uncore.lock);
-   intel_runtime_pm_put(dev_priv);
-   }
+   intel_runtime_pm_get(dev_priv);
+   spin_lock_irq(_priv->uncore.lock);
+   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+   spin_unlock_irq(_priv->uncore.lock);
+   intel_runtime_pm_put(dev_priv);
}
 
intel_fb_obj_flush(obj,
-- 
2.14.1

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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always wake the device to flush the GTT (rev3)

[Chris Wilson]

Quoting Chris Wilson (2017-08-29 20:21:36)
> Quoting Patchwork (2017-08-29 19:50:02)
> > For more details see: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5522/shards.html
> 
> Hmm, bxt pwrite issues still remain in this one. So either the theory is
> bogus or we have a hole...

Most obvious hole being the delay being rpm being not-in-use and
autosuspend.
-Chris
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Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries

[Peter Zijlstra]

On Tue, Aug 29, 2017 at 07:16:31PM +, Rogozhkin, Dmitry V wrote:
> > Pretty strict, people tend to get fairly upset every time we leak stuff.
> > In fact Debian and Android carry a perf_event_paranoid patch that
> > default disables _everything_ :-(
> 
> Can you say more on that for Debian and Android? What exactly they do?
> What is the value of perf_event_paranoid there? They disable everything
> even for root and CAP_SYS_ADMIN? But still they don't remove this from
> kernel on compilation stage, right? So users can explicitly change
> perf_event_paranoid to the desired value?

They introduce (and default to) perf_event_paranoid = 3. Which
disallows everything for unpriv user, root can still do things IIRC, I'd
have to dig out the patch.

This way apps have no access to the syscall, but you can enable it using
ADB by lowering the setting. So developers still have access, but
regular apps do not.

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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always wake the device to flush the GTT (rev3)

[Chris Wilson]

Quoting Patchwork (2017-08-29 19:50:02)
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5522/shards.html

Hmm, bxt pwrite issues still remain in this one. So either the theory is
bogus or we have a hole...
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Add a default case in gen7 hwsp switch-case

[Michel Thierry]

On 29/08/17 12:18, Chris Wilson wrote:

Quoting Michel Thierry (2017-08-29 19:55:45)

Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not-handled-in-switch warnings.

Use a default case instead, otherwise we will need to keep adding extra
cases if changes happen in the future.

Signed-off-by: Michel Thierry 


Left spray paint behind, so
Reviewed-by: Chris Wilson 

(Not really a case of MISSING_CASE, as it is completely impossible, so
GEM_BUG?)


True, GEM_BUG makes more sense here.
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Re: [Intel-gfx] [PATCH] drm/i915: Add a default case in gen7 hwsp switch-case

[Chris Wilson]

Quoting Michel Thierry (2017-08-29 19:55:45)
> Gen7 won't get any new engines, and we already added VCS2 there to just
> silence gcc's not-handled-in-switch warnings.
> 
> Use a default case instead, otherwise we will need to keep adding extra
> cases if changes happen in the future.
> 
> Signed-off-by: Michel Thierry 

Left spray paint behind, so
Reviewed-by: Chris Wilson 

(Not really a case of MISSING_CASE, as it is completely impossible, so
GEM_BUG?)
-Chris
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Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries

[Rogozhkin, Dmitry V]

On Tue, 2017-08-29 at 11:30 +0200, Peter Zijlstra wrote:
> On Mon, Aug 28, 2017 at 10:43:17PM +, Rogozhkin, Dmitry V wrote:
> 
> > Hi Peter,
> >
> > I have updated my fixes to Tvrtko's PMU, they are here:
> > https://patchwork.freedesktop.org/series/28842/, and I started to check
> > whether we will be able to cover all the use cases for this PMU which we
> > had in mind. Here I have some concerns and further questions.
> >
> > So, as soon as I registered PMU with the perf_invalid_context, i.e. as
> > an uncore PMU, I got the effect that metrics from our PMU are available
> > under root only. This happens since we fall to the following case
> > described in 'man perf_event_open': "A pid == -1 and cpu >= 0 setting is
> > per-CPU and measures all processes on the specified CPU.  Per-CPU events
> > need  the  CAP_SYS_ADMIN  capability  or
> > a /proc/sys/kernel/perf_event_paranoid value of less than 1."
> >
> > This a trouble point for us... So, could you, please, clarify:
> > 1. How PMU API is positioned? It is for debug purposes only or it can be
> > used in the end-user release applications to monitor system activity and
> > make some decisions based on that?
> 
> Perf is meant to also be usable for end-users, _however_ by default it
> will only allow users to profile their own userspace (tasks).
> 
> Allowing unpriv users access to kernel data is a clear data leak (you
> instantly void KASLR for instance).
> 
> And since uncore PMUs are not uniquely tied to individual user context,
> unpriv users have no access.
> 

If someone knew how much I don't like to step into such situations:).
Ok, thank you for clarification. This affect how we can use this API,
but it does not make it unusable. Good that it is intended for end-users
as well.

> > 2. How applications can access uncore PMU metrics from non-privileged
> > applications?
> 
> Only by lowering sysctl.kernel.perf_event_paranoid.
> Since uuncore is shared among many users, its events can be used to
> construct side-channel attacks. So from a security pov this is not
> something that can otherwise be done.
> 
> Imagine user A using the GPU to do crypto and user B reading the GPU
> events to infer state or similar things.
> 
> Without privilege separation we cannot allow unpriv access to system
> wide resources.
> 
> > 3. Is that a strong requirement to restrict uncore PMU metrics reporting
> > to privileged applications or this can be relaxed?
> 
> Pretty strict, people tend to get fairly upset every time we leak stuff.
> In fact Debian and Android carry a perf_event_paranoid patch that
> default disables _everything_ :-(

Can you say more on that for Debian and Android? What exactly they do?
What is the value of perf_event_paranoid there? They disable everything
even for root and CAP_SYS_ADMIN? But still they don't remove this from
kernel on compilation stage, right? So users can explicitly change
perf_event_paranoid to the desired value?

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add a default case in gen7 hwsp switch-case

[Patchwork]

== Series Details ==

Series: drm/i915: Add a default case in gen7 hwsp switch-case
URL   : https://patchwork.freedesktop.org/series/29494/
State : success

== Summary ==

Series 29494v1 drm/i915: Add a default case in gen7 hwsp switch-case
https://patchwork.freedesktop.org/api/1.0/series/29494/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-bdw-5557u)

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:357s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:558s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:517s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:614s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:589s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:475s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:446s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:486s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:552s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:407s
fi-skl-6700k failed to connect after reboot

428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC 
integration manifest
5e67d9a66af3 drm/i915: Add a default case in gen7 hwsp switch-case

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5527/
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[Intel-gfx] [PATCH] drm/i915: Add a default case in gen7 hwsp switch-case

[Michel Thierry]

Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not-handled-in-switch warnings.

Use a default case instead, otherwise we will need to keep adding extra
cases if changes happen in the future.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c277a26bbd99..7d57a5971f39 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -409,10 +409,12 @@ static void intel_ring_setup_status_page(struct 
intel_engine_cs *engine)
mmio = BLT_HWS_PGA_GEN7;
break;
/*
-* VCS2 actually doesn't exist on Gen7. Only shut up
+* No more rings exist on Gen7. Only shut up
 * gcc switch check warning
 */
-   case VCS2:
+   default:
+   MISSING_CASE(engine->id);
+   /* fall through */
case VCS:
mmio = BSD_HWS_PGA_GEN7;
break;
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always wake the device to flush the GTT (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT (rev3)
URL   : https://patchwork.freedesktop.org/series/29436/
State : success

== Summary ==

Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)

shard-hswtotal:2230 pass:1230 dwarn:0   dfail:0   fail:18  skip:982 
time:9625s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5522/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RFCv6,1/2] drm/i915: Factor out setup_private_pat()

[Patchwork]

== Series Details ==

Series: series starting with [RFCv6,1/2] drm/i915: Factor out 
setup_private_pat()
URL   : https://patchwork.freedesktop.org/series/29493/
State : failure

== Summary ==

Series 29493v1 series starting with [RFCv6,1/2] drm/i915: Factor out 
setup_private_pat()
https://patchwork.freedesktop.org/api/1.0/series/29493/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> SKIP   (fi-bdw-gvtdvm) fdo#102331
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test core_prop_blob:
Subgroup basic:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test debugfs_test:
Subgroup read_all_entries:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup basic-subslice-total:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test drv_hangman:
Subgroup error-state-basic:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_basic:
Subgroup bad-close:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup create-close:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup create-fd-close:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_busy:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup basic-hang-default:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_close_race:
Subgroup basic-process:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup basic-threads:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_ctx_basic:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Test gem_ctx_create:
Subgroup basic:
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-glk-2a)
Subgroup basic-files:
WARNING: Long output truncated
fi-kbl-r failed to connect after reboot

Re: [Intel-gfx] [RFCv5 2/2] drm/i915: Introduce private PAT management

[Wang, Zhi A]

I see. 

For 1) I can fix it in the next RFC.
For 2) I can find some VPG guys to ask for the details.

Thanks,
Zhi.

-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] 
Sent: Tuesday, August 29, 2017 9:14 PM
To: Wang, Zhi A ; Joonas Lahtinen 
; intel-gfx@lists.freedesktop.org; 
intel-gvt-...@lists.freedesktop.org
Cc: zhen...@linux.intel.com; Widawsky, Benjamin ; 
Vivi, Rodrigo 
Subject: RE: [RFCv5 2/2] drm/i915: Introduce private PAT management

Quoting Wang, Zhi A (2017-08-29 18:54:51)
> Another finding during the re-factoring are:
> 
> a)It looks like that the PPAT_CACHE_INDEX on BDW/SKL is mapped to:
> GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);
> 
> But the PPAT_CACHE_INDEX on CNL is mapped to GEN8_PPAT_LLCELLC | 
> GEN8_PPAT_AGE(0);
> 
> GEN8_PPAT_WB is missing here and by default the cache attribute is UC.
> 
> Is this set intentionally?

That sounds like a nasty little bug.

> b) Looks like all the ages of PPAT in windows driver is AGE(3) because of 
> some performance gains, is there any reason that i915 has to set it to AGE(0)?

Nope, it's never been rigorously tested. On occasion, we've swapped it around 
(at least for the older gen) and never found a significant difference; I 
haven't even heard if anyone has tried such experiments on gen8+. Off the top 
of my head, the age should only matter when you have PTE with different ages 
(unless there's some automatic clock algorithm tracking the age on each page in 
a shadow, the challenge being then when you decide to refresh the age from the 
PTE.) -Chris
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[Intel-gfx] [RFCv6 1/2] drm/i915: Factor out setup_private_pat()

[Zhi Wang]

Factor out setup_private_pat() for introducing the following patches.

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 708b95c..b74fa9d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2915,6 +2915,16 @@ static void gen6_gmch_remove(struct i915_address_space 
*vm)
cleanup_scratch_page(vm);
 }
 
+static void setup_private_pat(struct drm_i915_private *dev_priv)
+{
+   if (INTEL_GEN(dev_priv) >= 10)
+   cnl_setup_private_ppat(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+   chv_setup_private_ppat(dev_priv);
+   else
+   bdw_setup_private_ppat(dev_priv);
+}
+
 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -2947,14 +2957,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
}
 
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-
-   if (INTEL_GEN(dev_priv) >= 10)
-   cnl_setup_private_ppat(dev_priv);
-   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-   chv_setup_private_ppat(dev_priv);
-   else
-   bdw_setup_private_ppat(dev_priv);
-
ggtt->base.cleanup = gen6_gmch_remove;
ggtt->base.bind_vma = ggtt_bind_vma;
ggtt->base.unbind_vma = ggtt_unbind_vma;
@@ -2975,6 +2977,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
ggtt->invalidate = gen6_ggtt_invalidate;
 
+   setup_private_pat(dev_priv);
+
return ggtt_probe_common(ggtt, size);
 }
 
-- 
2.7.4

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Re: [Intel-gfx] [RFCv5 2/2] drm/i915: Introduce private PAT management

[Chris Wilson]

Quoting Wang, Zhi A (2017-08-29 18:54:51)
> Another finding during the re-factoring are:
> 
> a)It looks like that the PPAT_CACHE_INDEX on BDW/SKL is mapped to:
> GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);
> 
> But the PPAT_CACHE_INDEX on CNL is mapped to 
> GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);
> 
> GEN8_PPAT_WB is missing here and by default the cache attribute is UC.
> 
> Is this set intentionally?

That sounds like a nasty little bug.

> b) Looks like all the ages of PPAT in windows driver is AGE(3) because of 
> some performance gains, is there any reason that i915 has to set it to AGE(0)?

Nope, it's never been rigorously tested. On occasion, we've swapped it
around (at least for the older gen) and never found a significant
difference; I haven't even heard if anyone has tried such experiments
on gen8+. Off the top of my head, the age should only matter when you
have PTE with different ages (unless there's some automatic clock
algorithm tracking the age on each page in a shadow, the challenge
being then when you decide to refresh the age from the PTE.)
-Chris
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[Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Zhi Wang]

The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.

intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate or
return a partially matched PPAT entry if there is any available PPAT
indexes or not.

intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.

Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update_hw(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.

v6:

- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html

- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html

v5:

- Add check and warnnings for those platforms which don't have PPAT.

v3:

- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)

v2:

- API re-design. (Chris)

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 273 +---
 drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
 3 files changed, 262 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef5..5ffde10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2312,6 +2312,8 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
 
+   struct intel_ppat ppat;
+
/* Kernel Modesetting */
 
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b74fa9d..3106142 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
u64 size)
return 0;
 }
 
-static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+static struct intel_ppat_entry *
+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
 {
+   struct intel_ppat_entry *entry = >entries[index];
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(test_bit(index, ppat->used));
+
+   entry->ppat = ppat;
+   entry->value = value;
+   kref_init(>ref);
+   set_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+
+   return entry;
+}
+
+static void __free_ppat_entry(struct intel_ppat_entry *entry)
+{
+   struct intel_ppat *ppat = entry->ppat;
+   unsigned int index = entry - ppat->entries;
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(!test_bit(index, ppat->used));
+
+   entry->value = ppat->clear_value;
+   clear_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+}
+
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @i915: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, the partially
+ * matched entry will be used.
+ */
+const struct intel_ppat_entry *
+intel_ppat_get(struct drm_i915_private *i915, u8 value)
+{
+   struct intel_ppat *ppat = >ppat;
+   struct intel_ppat_entry *entry;
+   unsigned int scanned, best_score;
+   int i;
+
+   GEM_BUG_ON(!ppat->max_entries);
+
+   scanned = best_score = 0;
+
+   for_each_set_bit(i, ppat->used, ppat->max_entries) {
+   unsigned int score;
+
+   entry = >entries[i];
+   score = ppat->match(entry->value, value);
+   if (score > best_score) {
+   if (score == INTEL_PPAT_PERFECT_MATCH) {
+   kref_get(>ref);
+   return entry;
+   }
+   best_score = score;
+   }
+   scanned++;
+   }
+
+   if (scanned == ppat->max_entries) {
+   if (!best_score)
+

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: add perf support for Coffeelake (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake (rev2)
URL   : https://patchwork.freedesktop.org/series/29489/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CC  arch/x86/kernel/early-quirks.o
arch/x86/kernel/early-quirks.c:519:2: error: implicit declaration of function 
‘INTEL_SNB_D_IDS’ [-Werror=implicit-function-declaration]
  INTEL_SNB_D_IDS(_early_ops),
  ^~~
arch/x86/kernel/early-quirks.c:519:2: error: initializer element is not constant
arch/x86/kernel/early-quirks.c:519:2: note: (near initialization for 
‘intel_early_ids[37].vendor’)
arch/x86/kernel/early-quirks.c:520:2: error: implicit declaration of function 
‘INTEL_SNB_M_IDS’ [-Werror=implicit-function-declaration]
  INTEL_SNB_M_IDS(_early_ops),
  ^~~
arch/x86/kernel/early-quirks.c:520:2: error: initializer element is not constant
arch/x86/kernel/early-quirks.c:520:2: note: (near initialization for 
‘intel_early_ids[37].device’)
arch/x86/kernel/early-quirks.c:521:2: error: implicit declaration of function 
‘INTEL_IVB_M_IDS’ [-Werror=implicit-function-declaration]
  INTEL_IVB_M_IDS(_early_ops),
  ^~~
arch/x86/kernel/early-quirks.c:521:2: error: initializer element is not constant
arch/x86/kernel/early-quirks.c:521:2: note: (near initialization for 
‘intel_early_ids[37].subvendor’)
arch/x86/kernel/early-quirks.c:522:2: error: implicit declaration of function 
‘INTEL_IVB_D_IDS’ [-Werror=implicit-function-declaration]
  INTEL_IVB_D_IDS(_early_ops),
  ^~~
arch/x86/kernel/early-quirks.c:522:2: error: initializer element is not constant
arch/x86/kernel/early-quirks.c:522:2: note: (near initialization for 
‘intel_early_ids[37].subdevice’)
arch/x86/kernel/early-quirks.c:523:2: warning: braces around scalar initializer
  INTEL_HSW_IDS(_early_ops),
  ^
arch/x86/kernel/early-quirks.c:523:2: note: (near initialization for 
‘intel_early_ids[37].class’)
In file included from ./include/drm/i915_drm.h:29:0,
 from arch/x86/kernel/early-quirks.c:19:
./include/drm/i915_pciids.h:154:19: warning: excess elements in scalar 
initializer
  INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
   ^
./include/drm/i915_pciids.h:39:10: note: in definition of macro 
‘INTEL_VGA_DEVICE’
  0x8086, id,\
  ^~
./include/drm/i915_pciids.h:220:2: note: in expansion of macro 
‘INTEL_HSW_GT1_IDS’
  INTEL_HSW_GT1_IDS(info), \
  ^
arch/x86/kernel/early-quirks.c:523:2: note: in expansion of macro 
‘INTEL_HSW_IDS’
  INTEL_HSW_IDS(_early_ops),
  ^
./include/drm/i915_pciids.h:154:19: note: (near initialization for 
‘intel_early_ids[37].class’)
  INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
   ^
./include/drm/i915_pciids.h:39:10: note: in definition of macro 
‘INTEL_VGA_DEVICE’
  0x8086, id,\
  ^~
./include/drm/i915_pciids.h:220:2: note: in expansion of macro 
‘INTEL_HSW_GT1_IDS’
  INTEL_HSW_GT1_IDS(info), \
  ^
arch/x86/kernel/early-quirks.c:523:2: note: in expansion of macro 
‘INTEL_HSW_IDS’
  INTEL_HSW_IDS(_early_ops),
  ^
./include/drm/i915_pciids.h:40:2: warning: excess elements in scalar initializer
  ~0, ~0, \
  ^
./include/drm/i915_pciids.h:154:2: note: in expansion of macro 
‘INTEL_VGA_DEVICE’
  INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
  ^~~~
./include/drm/i915_pciids.h:220:2: note: in expansion of macro 
‘INTEL_HSW_GT1_IDS’
  INTEL_HSW_GT1_IDS(info), \
  ^
arch/x86/kernel/early-quirks.c:523:2: note: in expansion of macro 
‘INTEL_HSW_IDS’
  INTEL_HSW_IDS(_early_ops),
  ^
./include/drm/i915_pciids.h:40:2: note: (near initialization for 
‘intel_early_ids[37].class’)
  ~0, ~0, \
  ^
./include/drm/i915_pciids.h:154:2: note: in expansion of macro 
‘INTEL_VGA_DEVICE’
  INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
  ^~~~
./include/drm/i915_pciids.h:220:2: note: in expansion of macro 
‘INTEL_HSW_GT1_IDS’
  INTEL_HSW_GT1_IDS(info), \
  ^
arch/x86/kernel/early-quirks.c:523:2: note: in expansion of macro 
‘INTEL_HSW_IDS’
  INTEL_HSW_IDS(_early_ops),
  ^
./include/drm/i915_pciids.h:40:6: warning: excess elements in scalar initializer
  ~0, ~0, \
  ^
./include/drm/i915_pciids.h:154:2: note: in expansion of macro 
‘INTEL_VGA_DEVICE’
  INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
  ^~~~
./include/drm/i915_pciids.h:220:2: note: in expansion of macro 
‘INTEL_HSW_GT1_IDS’
  INTEL_HSW_GT1_IDS(info), \
  ^
arch/x86/kernel/early-quirks.c:523:2: note: in expansion of macro 
‘INTEL_HSW_IDS’
  

Re: [Intel-gfx] [RFCv5 2/2] drm/i915: Introduce private PAT management

[Wang, Zhi A]

Another finding during the re-factoring are:

a)It looks like that the PPAT_CACHE_INDEX on BDW/SKL is mapped to:
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);

But the PPAT_CACHE_INDEX on CNL is mapped to 
GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);

GEN8_PPAT_WB is missing here and by default the cache attribute is UC.

Is this set intentionally?

b) Looks like all the ages of PPAT in windows driver is AGE(3) because of some 
performance gains, is there any reason that i915 has to set it to AGE(0)?

Thanks,
Zhi.

-Original Message-
From: Wang, Zhi A 
Sent: Tuesday, August 29, 2017 2:19 PM
To: 'Joonas Lahtinen' ; 
intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org
Cc: ch...@chris-wilson.co.uk; zhen...@linux.intel.com; Widawsky, Benjamin 
; Vivi, Rodrigo 
Subject: RE: [RFCv5 2/2] drm/i915: Introduce private PAT management

Thanks Joonas! :)

-Original Message-
From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
Sent: Tuesday, August 29, 2017 12:37 PM
To: Wang, Zhi A ; intel-gfx@lists.freedesktop.org; 
intel-gvt-...@lists.freedesktop.org
Cc: ch...@chris-wilson.co.uk; zhen...@linux.intel.com; Widawsky, Benjamin 
; Vivi, Rodrigo 
Subject: Re: [RFCv5 2/2] drm/i915: Introduce private PAT management

On Tue, 2017-08-29 at 16:00 +0800, Zhi Wang wrote:
> The private PAT management is to support PPAT entry manipulation. Two 
> APIs are introduced for dynamically managing PPAT entries:
> intel_ppat_get and intel_ppat_put.
> 
> intel_ppat_get will search for an existing PPAT entry which perfectly 
> matches the required PPAT value. If not, it will try to allocate or 
> return a partially matched PPAT entry if there is any available PPAT 
> indexes or not.
> 
> intel_ppat_put will put back the PPAT entry which comes from 
> intel_ppat_get. If it's dynamically allocated, the reference count 
> will be decreased. If the reference count turns into zero, the PPAT 
> index is freed again.
> 
> Besides, another two callbacks are introduced to support the private 
> PAT management framework. One is ppat->update(), which writes the PPAT 
> configurations in ppat->entries into HW. Another one is ppat->match, 
> which will return a score to show how two PPAT values match with each other.
> 
> v5:
> 
> - Add check and warnnings for those platforms which don't have PPAT.
> 
> v3:
> 
> - Introduce dirty bitmap for PPAT registers. (Chris)
> - Change the name of the pointer "dev_priv" to "i915". (Chris)
> - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. 
> (Chris)
> 
> v2:
> 
> - API re-design. (Chris)
> 
> Cc: Ben Widawsky 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Signed-off-by: Zhi Wang 



> -static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
> +static struct intel_ppat_entry *alloc_ppat_entry(struct intel_ppat *ppat,
> +  unsigned int index,
> +  u8 value)
>  {
> + struct intel_ppat_entry *entry = >entries[index];
> +
> + entry->ppat = ppat;
> + entry->value = value;
> + kref_init(>ref_count);
> + set_bit(index, ppat->used);
> + set_bit(index, ppat->dirty);
> +
> + return entry;
> +}
> +
> +static void free_ppat_entry(struct intel_ppat_entry *entry) {
> + struct intel_ppat *ppat = entry->ppat;
> + int index = entry - ppat->entries;
> +
> + entry->value = ppat->dummy_value;
> + clear_bit(index, ppat->used);
> + set_bit(index, ppat->dirty);
> +}

Above functions should be __ prefixed as they do no checking if they override 
existing data. The suitable names might be __ppat_get and __ppat_put.

> +
> +/**
> + * intel_ppat_get - get a usable PPAT entry
> + * @i915: i915 device instance
> + * @value: the PPAT value required by the caller
> + *
> + * The function tries to search if there is an existing PPAT entry 
> +which
> + * matches with the required value. If perfectly matched, the 
> +existing PPAT
> + * entry will be used. If only partially matched, it will try to 
> +check if
> + * there is any available PPAT index. If yes, it will allocate a new 
> +PPAT
> + * index for the required entry and update the HW. If not, the 
> +partially
> + * matched entry will be used.
> + */
> +const struct intel_ppat_entry *intel_ppat_get(struct drm_i915_private 
> +*i915,

Maybe split the function type and name to avoid exceeding 80 chars on next line.

> +   u8 value)
> +{
> + struct intel_ppat *ppat = >ppat;
> + struct intel_ppat_entry *entry;
> + int i, used;
> + unsigned int score, best_score;
> +
> + if (WARN_ON(!ppat->max_entries))
> + 

[Intel-gfx] ✗ Fi.CI.IGT: warning for docs/chamelium: Explain that the Chamelium should only target one DUT

[Patchwork]

== Series Details ==

Series: docs/chamelium: Explain that the Chamelium should only target one DUT
URL   : https://patchwork.freedesktop.org/series/29482/
State : warning

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1230 dwarn:1   dfail:0   fail:17  skip:982 
time:9572s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_119/shards.html
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[Intel-gfx] [PATCH v2 2/3] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v2 0/3] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Upon Chris' comment, fill the intel_device_info.gt field for SNB & IVB
as well.

Cheers,

Lionel Landwerlin (3):
  drm/i915: add GT number to intel_device_info
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 ++
 drivers/gpu/drm/i915/i915_pci.c   | 193 ++
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 138 ++--
 7 files changed, 392 insertions(+), 112 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] [PATCH v2 3/3] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void

[Intel-gfx] [PATCH v2 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

v2: Add SNB & IVB (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 138 
 3 files changed, 231 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..0ac733baa734 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_FEATURES \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_FEATURES,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_FEATURES,
+   .gt = 2,
+};
+
+#define IVB_M_FEATURES \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_FEATURES,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_FEATURES,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct intel_device_info intel_broadwell_info = {
+static const struct intel_device_info intel_broadwell_gt1_info = {
+   BDW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29489/
State : success

== Summary ==

Series 29489v1 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29489/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:450s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:559s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:255s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:518s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:621s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:444s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:600s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:523s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:463s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:490s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:504s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:546s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:402s
fi-skl-6700k failed to connect after reboot

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
27db0b3ec2de drm/i915/perf: add support for Coffeelake GT2
8f96a48feb6f drm/i915: rework IS_*_GT* macros
aefe22cd3979 drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5524/
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: add GT number to intel_device_info

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 18:17:22)
> On 29/08/17 18:01, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2017-08-29 17:52:49)
> >> Up to Coffeelake we could deduce this GT number from the device ID.
> >> This doesn't seem to be the case anymore. This change reorders pciids
> >> per GT and adds a gt field to intel_device_info. We set this field on
> >> the following platforms :
> > Do we also then want to identify the sub-gts? Without a use that smells
> > of over-engineering -- I wonder if we've snuck one in anyway, just not
> > called it a gt test.
> 
> Hmm I wasn't aware of sub-gts (or maybe I know them under a different name).
> Do you mean things like GT3e?

The variably sized sseu were for different gt1.5 (and I may be imagining
a gt1.2).
-Chris
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

On 29/08/17 18:01, Chris Wilson wrote:

Quoting Lionel Landwerlin (2017-08-29 17:52:49)

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

Do we also then want to identify the sub-gts? Without a use that smells
of over-engineering -- I wonder if we've snuck one in anyway, just not
called it a gt test.


Hmm I wasn't aware of sub-gts (or maybe I know them under a different name).
Do you mean things like GT3e?




- HSW/BDW/SKL/KBL/CFL/CNL

Also should apply retrospectively to ivb, and then snb for completeness.
(We do have a IS_IVB_GT1 that can then be purged.)


Sure!


-Chris



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Re: [Intel-gfx] [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue

[Vivi, Rodrigo]

On Tue, 2017-08-29 at 09:42 +0300, Jani Nikula wrote:
> On Tue, 29 Aug 2017, Rodrigo Vivi  wrote:
> > This workaround fixes a CNL PCH bug when changing
> > backlight from a lower frequency to a higher frequency.
> >
> > During random reboot cycles, display backlight seems to
> > be off/ dim for 2-3 mins.
> >
> > The only functional change on this patch is to
> > set bit 13 of 0xC2020 for CNL PCH.
> >
> > The rest of patch is organizing identation around
> > those bits definitions and re-organizing CFL workarounds.
> >
> > Cc: Arthur J Runyan 
> > Cc: Dhinakaran Pandiyan 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 11 ++-
> >  drivers/gpu/drm/i915/intel_pm.c | 27 +--
> >  2 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index c59c590e45c4..31b1b1dfb754 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7474,11 +7474,12 @@ enum {
> >  #define  FDI_RX_PHASE_SYNC_POINTER_EN  (1<<0)
> >  #define FDI_RX_CHICKEN(pipe)   _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, 
> > _FDI_RXB_CHICKEN)
> >  
> > -#define SOUTH_DSPCLK_GATE_D_MMIO(0xc2020)
> > -#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> > -#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> > -#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> > -#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
> > +#define SOUTH_DSPCLK_GATE_D_MMIO(0xc2020)
> > +#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE(1<<30)
> > +#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE   (1<<29)
> > +#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> > +#define  CNP_PWM_CGE_GATING_DISABLE(1<<13)
> 
> Only add this one line, please don't reshuffle the rest.

yep... my momentary OCD took over and fixed indentation around what I
was touching to avoid extra patch...

> 
> > +#define  PCH_LP_PARTITION_LEVEL_DISABLE(1<<12)
> >  
> >  /* CPU: FDI_TX */
> >  #define _FDI_TXA_CTL0x60100
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 88bbbc44c00d..5a4b41ea0c3a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct 
> > drm_i915_private *dev_priv,
> > I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >  }
> >  
> > +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > +   if (!HAS_PCH_CNP(dev_priv))
> > +   return;
> 
> Is this for CFL without CNP?

Nope. CNP only.

So far we have CFL with KBP and CNP
and we have CNL with CNP but who know what we might have in the future,
so I preferred to skip inside the function instead of adding 2 ifs
outside and/or have to fix it later.

> 
> BR,
> Jani.
> 
> > +
> > +   /* Wa #1181 */
> > +   I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> > +}
> > +
> >  static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > +   cnp_init_clock_gating(dev_priv);
> > +
> > /* This is not an Wa. Enable for better image quality */
> > I915_WRITE(_3D_CHICKEN3,
> >_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > @@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> >SARBUNIT_CLKGATE_DIS);
> >  }
> >  
> > +static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > +   cnp_init_clock_gating(dev_priv);
> > +   gen9_init_clock_gating(dev_priv);
> > +
> > +   /* WaFbcNukeOnHostModify:cfl */
> > +   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > +  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> > +}
> > +
> >  static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > gen9_init_clock_gating(dev_priv);
> > @@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >  
> > -   /* WaFbcNukeOnHostModify:kbl,cfl */
> > +   /* WaFbcNukeOnHostModify:kbl */
> > I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> > @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct 
> > drm_i915_private *dev_priv)
> >  {
> > if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating = 
> > cannonlake_init_clock_gating;
> > +   else if (IS_COFFEELAKE(dev_priv))
> > +   dev_priv->display.init_clock_gating = 
> > coffeelake_init_clock_gating;
> > else if (IS_SKYLAKE(dev_priv))
> > 

Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Jeff McGee]

On Tue, Aug 29, 2017 at 04:17:46PM +0100, Chris Wilson wrote:
> Quoting Jeff McGee (2017-08-29 16:04:17)
> > On Tue, Aug 29, 2017 at 10:07:18AM +0100, Chris Wilson wrote:
> > > Quoting Jeff McGee (2017-08-28 21:18:44)
> > > > On Mon, Aug 28, 2017 at 08:44:48PM +0100, Chris Wilson wrote:
> > > > > Quoting jeff.mc...@intel.com (2017-08-28 20:25:30)
> > > > > > From: Jeff McGee 
> > > > > > 
> > > > > > If someone else is resetting the engine we should clear our own bit 
> > > > > > as
> > > > > > part of skipping that engine. Otherwise we will later believe that 
> > > > > > it
> > > > > > has not been reset successfully and then trigger full gpu reset. If 
> > > > > > the
> > > > > > other guy's reset actually fails, he will trigger the full gpu 
> > > > > > reset.
> > > > > 
> > > > > The reason we did continue on to the global reset was to serialise
> > > > > i915_handle_error() with the other thread. Not a huge issue, but a
> > > > > reasonable property to keep -- and we definitely want a to explain why
> > > > > only one reset at a time is important.
> > > > > 
> > > > > bool intel_engine_lock_reset() {
> > > > >   if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
> > > > > >i915->gpu_error.flags))
> > > > >   return true;
> > > > > 
> > > > >   intel_engine_wait_for_reset(engine);
> > > > The current code doesn't wait for the other thread to finish the reset, 
> > > > but
> > > > this would add that wait. 
> > > 
> > > Pardon? If we can't reset the engine, we go to the full reset which is
> > > serialised, both with individual engine resets and other globals.
> > > 
> > > > Did you intend that as an additional change to
> > > > the current code? I don't think it is necessary. Each thread wants to
> > > > reset some subset of engines, so it seems the thread can safely exit as 
> > > > soon
> > > > as it knows each of those engines has been reset or is being reset as 
> > > > part
> > > > of another thread that got the lock first. If any of the threads fail to
> > > > reset an engine they "own", then full gpu reset is assured.
> > > 
> > > It's unexpected for this function to return before the reset.
> > > -Chris
> > 
> > I'm a bit confused, so let's go back to the original code that I was trying
> > to fix:
> > 
> > 
> > /*
> >  * Try engine reset when available. We fall back to full reset if
> >  * single reset fails.
> >  */
> > if (intel_has_reset_engine(dev_priv)) {
> > for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
> > BUILD_BUG_ON(I915_RESET_MODESET >= 
> > I915_RESET_ENGINE);
> > if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
> >  _priv->gpu_error.flags))
> > continue;
> > 
> > if (i915_reset_engine(engine, 0) == 0)
> > engine_mask &= ~intel_engine_flag(engine);
> > 
> > clear_bit(I915_RESET_ENGINE + engine->id,
> >   _priv->gpu_error.flags);
> > wake_up_bit(_priv->gpu_error.flags,
> > I915_RESET_ENGINE + engine->id);
> > }
> > }
> > 
> > if (!engine_mask)
> > goto out;
> > 
> > /* Full reset needs the mutex, stop any other user trying to do so. 
> > */
> > 
> > Let's say that 2 threads are here intending to reset render. #1 gets the 
> > lock
> > and starts the render engine-only reset. #2 fails to get the lock which 
> > implies
> > that someone else is in the process of resetting the render engine (with 
> > single
> > engine reset or full gpu reset). #2 continues on without waiting but doesn't
> > clear the render bit in engine_mask. So #2 will proceed to initiate a full
> > gpu reset when it may not be necessary. That's the problem I was trying
> > to address with my initial patch. Do you agree that #2 must clear this bit
> > to avoid always triggering full gpu reset? If the engine-only reset done by
> > #1 fails, #1 will do the fallback to full gpu reset, so there is no risk 
> > that
> > we would miss the full gpu reset if it is really needed.
> > 
> > Then there is the question of whether #2 should wait around for the
> > render engine reset by #1 to complete. It doesn't in current code and I 
> > don't
> > see why it needs to. But that can be a separate discussion from the above.
> 
> It very much does in the current code. If we can not do the per-engine
> reset, it falls back to the global reset.

So are you saying that it is by design in this scenario that #2 will resort
to full gpu reset just because it wasn't the thread that actually performed
the engine reset, even though it can clearly infer based on the engine lock
being held that #1 is performing that reset for him?

> The global reset 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Pull wait-for-idle into i915_gem_switch_to_kernel_context()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Pull wait-for-idle into 
i915_gem_switch_to_kernel_context()
URL   : https://patchwork.freedesktop.org/series/29478/
State : failure

== Summary ==

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-B-frame-sequence:
pass   -> FAIL   (shard-hsw)
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:19  skip:982 
time:9626s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5520/shards.html
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: add GT number to intel_device_info

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 17:52:49)
> Up to Coffeelake we could deduce this GT number from the device ID.
> This doesn't seem to be the case anymore. This change reorders pciids
> per GT and adds a gt field to intel_device_info. We set this field on
> the following platforms :

Do we also then want to identify the sub-gts? Without a use that smells
of over-engineering -- I wonder if we've snuck one in anyway, just not
called it a gt test.

>- HSW/BDW/SKL/KBL/CFL/CNL

Also should apply retrospectively to ivb, and then snb for completeness.
(We do have a IS_IVB_GT1 that can then be purged.)
-Chris
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[Intel-gfx] [PATCH 2/3] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..d4ea25b83991 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2893,11 +2893,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2918,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH 3/3] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4ea25b83991..0e76e332f3fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2929,6 +2929,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void

[Intel-gfx] [PATCH 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - HSW/BDW/SKL/KBL/CFL/CNL

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 111 +++-
 include/drm/i915_pciids.h   | 110 ++-
 3 files changed, 151 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..2fa2c0b04432 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -299,10 +299,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +332,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct intel_device_info intel_broadwell_info = {
+static const struct intel_device_info intel_broadwell_gt1_info = {
BDW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_broadwell_gt2_info = {
+   BDW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_broadwell_rsvd_info = {
+   BDW_PLATFORM,
+   .gt = 3,
+   /* According to the device ID those devices are GT3, they were
+* previously treated as not GT3, keep it like that.
+*/
 };
 
 static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
+   .gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -358,13 +387,29 @@ static const struct intel_device_info 
intel_cherryview_info = {
.has_guc = 1, \
.ddb_size = 896
 
-static const struct intel_device_info intel_skylake_info = {
+static const struct intel_device_info intel_skylake_gt1_info = {
SKL_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_skylake_gt3_info = {
+static const struct intel_device_info intel_skylake_gt2_info = {
SKL_PLATFORM,
-   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+   .gt = 2,
+};
+
+#define SKL_GT3_PLUS_PLATFORM \
+   SKL_PLATFORM, \
+   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
+
+
+static const struct intel_device_info intel_skylake_gt3_info = {
+   SKL_GT3_PLUS_PLATFORM,
+   .gt = 3,
+};
+
+static const struct intel_device_info intel_skylake_gt4_info = {
+   SKL_GT3_PLUS_PLATFORM,
+   .gt = 4,
 };
 
 #define GEN9_LP_FEATURES \
@@ -415,12 +460,19 @@ static const struct intel_device_info 
intel_geminilake_info = {
.has_guc = 1, \
.ddb_size = 896
 
-static const struct intel_device_info intel_kabylake_info = {
+static const struct intel_device_info intel_kabylake_gt1_info = {
+   KBL_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_kabylake_gt2_info = {
KBL_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
+   .gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -433,20 +485,28 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.has_guc = 1, \
.ddb_size = 896
 
-static const struct intel_device_info intel_coffeelake_info = {
+static const struct intel_device_info intel_coffeelake_gt1_info = {
+   CFL_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_coffeelake_gt2_info = {
CFL_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info 

[Intel-gfx] [PATCH 0/3] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Hi all,

This series adds support for perf on Coffeelake GT2. This requires
some changes in order to identify GT2s chipsets. It seems the scheme
that was used before in device IDs isn't there anymore.

Cheers,

Lionel Landwerlin (3):
  drm/i915: add GT number to intel_device_info
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  17 +++---
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_pci.c   | 111 +++---
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 include/drm/i915_pciids.h | 110 ++---
 7 files changed, 310 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/audio: Add suspend and hibernate tests for HDMI signal integrity

[Patchwork]

== Series Details ==

Series: tests/audio: Add suspend and hibernate tests for HDMI signal integrity
URL   : https://patchwork.freedesktop.org/series/29485/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
bf45d253648250fc402eee02237366c8882b2053 igt: Add gem_close

with latest DRM-Tip kernel build CI_DRM_3014
627598734e5e drm-tip: 2017y-08m-29d-09h-52m-12s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:439s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:365s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:554s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:251s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:517s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:522s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:517s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:444s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:430s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:482s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:600s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:599s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:521s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:491s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:553s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:403s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_120/
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Skylake plane update/disable unifications [v2]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v2]
URL   : https://patchwork.freedesktop.org/series/29462/
State : warning

== Summary ==

Series 29462v1 drm/i915: Skylake plane update/disable unifications [v2]
https://patchwork.freedesktop.org/api/1.0/series/29462/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> SKIP   (fi-skl-x1585l)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:458s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:548s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:254s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:518s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:516s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:618s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:595s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:525s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:480s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:267  dwarn:0   dfail:0   fail:0   skip:12  
time:475s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:408s
fi-skl-6700k failed to connect after reboot

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
e2421d33d3d1 drm/i915: Unify skylake plane disable
50c7cd3e4795 drm/i915: Unify skylake plane update
6a622aad5fc6 drm/i915: dspaddr_offset doesn't need to be more than local 
variable

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5523/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Always wake the device to flush the GTT (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Always wake the device to flush the GTT (rev3)
URL   : https://patchwork.freedesktop.org/series/29436/
State : success

== Summary ==

Series 29436v3 drm/i915: Always wake the device to flush the GTT
https://patchwork.freedesktop.org/api/1.0/series/29436/revisions/3/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:458s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:445s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:553s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:522s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:527s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:518s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:620s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:442s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:508s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:471s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:591s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:599s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:526s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:483s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:446s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:481s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:403s
fi-skl-6700k failed to connect after reboot

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
aee73c805b40 drm/i915: Flush indirect GTT writes upon runtime-suspend

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5522/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/atomic: Move drm_crtc_commit to drm_crtc_state.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/atomic: Move drm_crtc_commit to 
drm_crtc_state.
URL   : https://patchwork.freedesktop.org/series/29476/
State : failure

== Summary ==

Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_cursor_legacy:
Subgroup nonblocking-modeset-vs-cursor-atomic:
pass   -> INCOMPLETE (shard-hsw)
Subgroup long-nonblocking-modeset-vs-cursor-atomic:
pass   -> INCOMPLETE (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-use-after-nonblocking-unbind:
fail   -> PASS   (shard-hsw) fdo#101847 +1
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-B:
pass   -> INCOMPLETE (shard-hsw)
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101847 https://bugs.freedesktop.org/show_bug.cgi?id=101847
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2105 pass:1158 dwarn:0   dfail:0   fail:16  skip:928 
time:8690s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5519/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: warning for HAX drm/i915: Disable runtime-pm for shard-apl

[Patchwork]

== Series Details ==

Series: HAX drm/i915: Disable runtime-pm for shard-apl
URL   : https://patchwork.freedesktop.org/series/29484/
State : warning

== Summary ==

Series 29484v1 HAX drm/i915: Disable runtime-pm for shard-apl
https://patchwork.freedesktop.org/api/1.0/series/29484/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> SKIP   (fi-bxt-j4205)
Subgroup basic-rte:
pass   -> SKIP   (fi-bxt-j4205)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:463s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:458s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:555s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:258  dwarn:0   dfail:0   fail:0   skip:21  
time:520s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:522s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:514s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:442s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:613s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:503s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:483s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:597s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:520s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:469s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:493s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:446s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:504s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:556s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:403s
fi-skl-6700k failed to connect after reboot

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
531c23a24d7b HAX drm/i915: Disable runtime-pm for shard-apl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5521/
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[Intel-gfx] [PATCH] drm/i915: Flush indirect GTT writes upon runtime-suspend

[Chris Wilson]

Our assumption is that indirect writes via the GTT are naturally flushed
when we enter runtime suspend. However, from the look of bxt in our CI,
this is not true and so we must apply our trick of doing a mmio to
serialise the writes.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 43834dee4e8d..6b9352248925 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2023,6 +2023,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
 {
struct drm_i915_gem_object *obj, *on;
+   unsigned long flags;
int i;
 
/*
@@ -2063,6 +2064,17 @@ void i915_gem_runtime_suspend(struct drm_i915_private 
*dev_priv)
GEM_BUG_ON(!list_empty(>vma->obj->userfault_link));
reg->dirty = true;
}
+
+   spin_lock_irqsave(_priv->uncore.lock, flags);
+   POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+   spin_unlock_irqrestore(_priv->uncore.lock, flags);
+
+   list_for_each_entry(obj, _priv->mm.bound_list, global_link) {
+   if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) {
+   obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
+   obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
+   }
+   }
 }
 
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t] tests/audio: Add suspend and hibernate tests for HDMI signal integrity

[Paul Kocialkowski]

This introduces tests for HDMI signal integrity after suspend and
hibernate. They simply test that signal integrity is ensured before
and after suspend or hibernate.

Signed-off-by: Paul Kocialkowski 
---
 tests/audio.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/tests/audio.c b/tests/audio.c
index 7fb91c97..560876a3 100644
--- a/tests/audio.c
+++ b/tests/audio.c
@@ -167,8 +167,27 @@ static void test_integrity(const char *device_name)
free(data.alsa);
 }
 
+static void test_suspend_resume_integrity(const char *device_name,
+ enum igt_suspend_state state,
+ enum igt_suspend_test test)
+{
+   test_integrity(device_name);
+
+   igt_system_suspend_autoresume(state, test);
+
+   test_integrity(device_name);
+}
+
 igt_main
 {
igt_subtest("hdmi-integrity")
test_integrity("HDMI");
+
+   igt_subtest("hdmi-integrity-after-suspend")
+   test_suspend_resume_integrity("HDMI", SUSPEND_STATE_MEM,
+ SUSPEND_TEST_NONE);
+
+   igt_subtest("hdmi-integrity-after-hibernate")
+   test_suspend_resume_integrity("HDMI", SUSPEND_STATE_DISK,
+ SUSPEND_TEST_DEVICES);
 }
-- 
2.14.0

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[Intel-gfx] [PATCH] HAX drm/i915: Disable runtime-pm for shard-apl

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..9a8a2ec9fbcd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -397,6 +397,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
 static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
.platform = INTEL_BROXTON,
+   .has_runtime_pm = 0,
.ddb_size = 512,
 };
 
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for docs/chamelium: Explain that the Chamelium should only target one DUT

[Patchwork]

== Series Details ==

Series: docs/chamelium: Explain that the Chamelium should only target one DUT
URL   : https://patchwork.freedesktop.org/series/29482/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
bf45d253648250fc402eee02237366c8882b2053 igt: Add gem_close

with latest DRM-Tip kernel build CI_DRM_3014
627598734e5e drm-tip: 2017y-08m-29d-09h-52m-12s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:460s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:447s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:367s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:567s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:523s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:525s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:525s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:438s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:617s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:431s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:601s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:517s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:494s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:502s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:411s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_119/
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Chris Wilson]

Quoting Jeff McGee (2017-08-28 20:46:00)
> On Mon, Aug 28, 2017 at 12:41:58PM -0700, Michel Thierry wrote:
> > On 28/08/17 12:25, jeff.mc...@intel.com wrote:
> > >From: Jeff McGee 
> > >
> > >If someone else is resetting the engine we should clear our own bit as
> > >part of skipping that engine. Otherwise we will later believe that it
> > >has not been reset successfully and then trigger full gpu reset. If the
> > >other guy's reset actually fails, he will trigger the full gpu reset.
> > >
> > 
> > Did you hit this by manually setting wedged to 'x' ring repeatedly?
> > 
> I haven't actually reproduced it. Have just been looking at the code a
> lot to try to develop reset for preemption enforcement. The implementation
> will call i915_handle_error from another work item that can run concurrent
> with hangcheck.

Note to hit it in practice is a nasty bug. The assumption is that between
a pair of resets there was sufficient time for the engine to recover,
and so if we reset too quickly we conclude that the reset/recovery
mechanism is broken.

And if you do start playing with fast resets, you very quickly find that
kthread_park is a livelock waiting to happen.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Chris Wilson]

Quoting Jeff McGee (2017-08-29 16:04:17)
> On Tue, Aug 29, 2017 at 10:07:18AM +0100, Chris Wilson wrote:
> > Quoting Jeff McGee (2017-08-28 21:18:44)
> > > On Mon, Aug 28, 2017 at 08:44:48PM +0100, Chris Wilson wrote:
> > > > Quoting jeff.mc...@intel.com (2017-08-28 20:25:30)
> > > > > From: Jeff McGee 
> > > > > 
> > > > > If someone else is resetting the engine we should clear our own bit as
> > > > > part of skipping that engine. Otherwise we will later believe that it
> > > > > has not been reset successfully and then trigger full gpu reset. If 
> > > > > the
> > > > > other guy's reset actually fails, he will trigger the full gpu reset.
> > > > 
> > > > The reason we did continue on to the global reset was to serialise
> > > > i915_handle_error() with the other thread. Not a huge issue, but a
> > > > reasonable property to keep -- and we definitely want a to explain why
> > > > only one reset at a time is important.
> > > > 
> > > > bool intel_engine_lock_reset() {
> > > >   if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
> > > > >i915->gpu_error.flags))
> > > >   return true;
> > > > 
> > > >   intel_engine_wait_for_reset(engine);
> > > The current code doesn't wait for the other thread to finish the reset, 
> > > but
> > > this would add that wait. 
> > 
> > Pardon? If we can't reset the engine, we go to the full reset which is
> > serialised, both with individual engine resets and other globals.
> > 
> > > Did you intend that as an additional change to
> > > the current code? I don't think it is necessary. Each thread wants to
> > > reset some subset of engines, so it seems the thread can safely exit as 
> > > soon
> > > as it knows each of those engines has been reset or is being reset as part
> > > of another thread that got the lock first. If any of the threads fail to
> > > reset an engine they "own", then full gpu reset is assured.
> > 
> > It's unexpected for this function to return before the reset.
> > -Chris
> 
> I'm a bit confused, so let's go back to the original code that I was trying
> to fix:
> 
> 
> /*
>  * Try engine reset when available. We fall back to full reset if
>  * single reset fails.
>  */
> if (intel_has_reset_engine(dev_priv)) {
> for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
> BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
> if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>  _priv->gpu_error.flags))
> continue;
> 
> if (i915_reset_engine(engine, 0) == 0)
> engine_mask &= ~intel_engine_flag(engine);
> 
> clear_bit(I915_RESET_ENGINE + engine->id,
>   _priv->gpu_error.flags);
> wake_up_bit(_priv->gpu_error.flags,
> I915_RESET_ENGINE + engine->id);
> }
> }
> 
> if (!engine_mask)
> goto out;
> 
> /* Full reset needs the mutex, stop any other user trying to do so. */
> 
> Let's say that 2 threads are here intending to reset render. #1 gets the lock
> and starts the render engine-only reset. #2 fails to get the lock which 
> implies
> that someone else is in the process of resetting the render engine (with 
> single
> engine reset or full gpu reset). #2 continues on without waiting but doesn't
> clear the render bit in engine_mask. So #2 will proceed to initiate a full
> gpu reset when it may not be necessary. That's the problem I was trying
> to address with my initial patch. Do you agree that #2 must clear this bit
> to avoid always triggering full gpu reset? If the engine-only reset done by
> #1 fails, #1 will do the fallback to full gpu reset, so there is no risk that
> we would miss the full gpu reset if it is really needed.
> 
> Then there is the question of whether #2 should wait around for the
> render engine reset by #1 to complete. It doesn't in current code and I don't
> see why it needs to. But that can be a separate discussion from the above.

It very much does in the current code. If we can not do the per-engine
reset, it falls back to the global reset. The global reset is serialised
with itself and the per-engine resets. Ergo it waits, and that was
intentional.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for Improve robustness of the i915 perf tests (rev2)

[Patchwork]

== Series Details ==

Series: Improve robustness of the i915 perf tests (rev2)
URL   : https://patchwork.freedesktop.org/series/28373/
State : success

== Summary ==

Test perf:
Subgroup oa-exponents:
fail   -> PASS   (shard-hsw) fdo#102254
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)

fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2231 pass:1231 dwarn:0   dfail:0   fail:17  skip:983 
time:9558s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_118/shards.html
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[Intel-gfx] [PATCH i-g-t] docs/chamelium: Explain that the Chamelium should only target one DUT

[Paul Kocialkowski]

This adds an explanation about why the Chamelium should only be
connected to one target device at once to the in-tree documentation.

Signed-off-by: Paul Kocialkowski 
---
 docs/chamelium.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/docs/chamelium.txt b/docs/chamelium.txt
index 77594284..ae7ac34a 100644
--- a/docs/chamelium.txt
+++ b/docs/chamelium.txt
@@ -54,6 +54,12 @@ CI system with a shared testlist) to remove the Chamelium 
configuration from the
 hosts that shouldn't connect to the Chamelium so that they can be skipped, 
which
 is faster than a network timeout.
 
+It should also be noted that each Chamelium platform should only be used for
+testing a single target device at a time. This is because the reset call issued
+by the IGT tests is common to all connectors and thus one machine running a 
test
+on a given connector may reset the chamelium while another machine is running
+a test on another connector.
+
 An example fully-featured configuration follows:
 [Common]
 FrameDumpPath=/root/
-- 
2.14.0

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Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

[Jeff McGee]

On Tue, Aug 29, 2017 at 10:07:18AM +0100, Chris Wilson wrote:
> Quoting Jeff McGee (2017-08-28 21:18:44)
> > On Mon, Aug 28, 2017 at 08:44:48PM +0100, Chris Wilson wrote:
> > > Quoting jeff.mc...@intel.com (2017-08-28 20:25:30)
> > > > From: Jeff McGee 
> > > > 
> > > > If someone else is resetting the engine we should clear our own bit as
> > > > part of skipping that engine. Otherwise we will later believe that it
> > > > has not been reset successfully and then trigger full gpu reset. If the
> > > > other guy's reset actually fails, he will trigger the full gpu reset.
> > > 
> > > The reason we did continue on to the global reset was to serialise
> > > i915_handle_error() with the other thread. Not a huge issue, but a
> > > reasonable property to keep -- and we definitely want a to explain why
> > > only one reset at a time is important.
> > > 
> > > bool intel_engine_lock_reset() {
> > >   if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
> > > >i915->gpu_error.flags))
> > >   return true;
> > > 
> > >   intel_engine_wait_for_reset(engine);
> > The current code doesn't wait for the other thread to finish the reset, but
> > this would add that wait. 
> 
> Pardon? If we can't reset the engine, we go to the full reset which is
> serialised, both with individual engine resets and other globals.
> 
> > Did you intend that as an additional change to
> > the current code? I don't think it is necessary. Each thread wants to
> > reset some subset of engines, so it seems the thread can safely exit as soon
> > as it knows each of those engines has been reset or is being reset as part
> > of another thread that got the lock first. If any of the threads fail to
> > reset an engine they "own", then full gpu reset is assured.
> 
> It's unexpected for this function to return before the reset.
> -Chris

I'm a bit confused, so let's go back to the original code that I was trying
to fix:


/*
 * Try engine reset when available. We fall back to full reset if
 * single reset fails.
 */
if (intel_has_reset_engine(dev_priv)) {
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
 _priv->gpu_error.flags))
continue;

if (i915_reset_engine(engine, 0) == 0)
engine_mask &= ~intel_engine_flag(engine);

clear_bit(I915_RESET_ENGINE + engine->id,
  _priv->gpu_error.flags);
wake_up_bit(_priv->gpu_error.flags,
I915_RESET_ENGINE + engine->id);
}
}

if (!engine_mask)
goto out;

/* Full reset needs the mutex, stop any other user trying to do so. */

Let's say that 2 threads are here intending to reset render. #1 gets the lock
and starts the render engine-only reset. #2 fails to get the lock which implies
that someone else is in the process of resetting the render engine (with single
engine reset or full gpu reset). #2 continues on without waiting but doesn't
clear the render bit in engine_mask. So #2 will proceed to initiate a full
gpu reset when it may not be necessary. That's the problem I was trying
to address with my initial patch. Do you agree that #2 must clear this bit
to avoid always triggering full gpu reset? If the engine-only reset done by
#1 fails, #1 will do the fallback to full gpu reset, so there is no risk that
we would miss the full gpu reset if it is really needed.

Then there is the question of whether #2 should wait around for the
render engine reset by #1 to complete. It doesn't in current code and I don't
see why it needs to. But that can be a separate discussion from the above.
-Jeff
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Joonas Lahtinen (2017-08-29 15:54:06)
> On Tue, 2017-08-29 at 11:33 +0100, Chris Wilson wrote:
> > Since we hold the device wakeref when writing through the GTT (otherwise
> > the writes would fail), we presumed that before the device sleeps those
> > writes would naturally be flushed and that we wouldn't need our mmio
> > read trick. However, that presumption seems false and a sleepy bxt seems
> > to require us to always manually flush the GTT writes prior to direct
> > access.
> > 
> > Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before 
> > flushing GTT writes")
> > Signed-off-by: Chris Wilson 
> > Cc: Joonas Lahtinen 
> 
> Got any Bugzilla, Testcase, Tested-by?

Original bugzilla hasn't been reopened, so I its looks like they were
happy enough with the original patches that fixed the problem on my bxt.
The testcase seems to be very system dependent, my suspicion is that it
has to do with the wacky runtime pm exhibited by CI bxt.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Joonas Lahtinen]

On Tue, 2017-08-29 at 11:33 +0100, Chris Wilson wrote:
> Since we hold the device wakeref when writing through the GTT (otherwise
> the writes would fail), we presumed that before the device sleeps those
> writes would naturally be flushed and that we wouldn't need our mmio
> read trick. However, that presumption seems false and a sleepy bxt seems
> to require us to always manually flush the GTT writes prior to direct
> access.
> 
> Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before flushing 
> GTT writes")
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 

Got any Bugzilla, Testcase, Tested-by?

Does what the message describes.

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Pull wait-for-idle into i915_gem_switch_to_kernel_context()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Pull wait-for-idle into 
i915_gem_switch_to_kernel_context()
URL   : https://patchwork.freedesktop.org/series/29478/
State : success

== Summary ==

Series 29478v1 series starting with [1/2] drm/i915: Pull wait-for-idle into 
i915_gem_switch_to_kernel_context()
https://patchwork.freedesktop.org/api/1.0/series/29478/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:439s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:551s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:524s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:522s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:518s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:430s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:448s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:497s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:599s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:522s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:481s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:478s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:414s

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
a4f2c16aa596 drm/i915/perf: Remove open-coding of 
i915_gem_switch_to_kernel_context()
0046c657b34c drm/i915: Pull wait-for-idle into 
i915_gem_switch_to_kernel_context()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5520/
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Re: [Intel-gfx] [PATCH 03/23] drm/i915/gemfs: enable THP

[Joonas Lahtinen]

On Mon, 2017-08-21 at 19:34 +0100, Matthew Auld wrote:
> Enable transparent-huge-pages through gemfs by mounting with
> huge=within_size.
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 



> +++ b/drivers/gpu/drm/i915/i915_gemfs.c
> @@ -24,6 +24,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  #include "i915_drv.h"
>  #include "i915_gemfs.h"
> @@ -41,6 +42,20 @@ int i915_gemfs_init(struct drm_i915_private *i915)
>   if (IS_ERR(gemfs))
>   return PTR_ERR(gemfs);
>  
> + if (has_transparent_hugepage()) {
> + struct super_block *sb = gemfs->mnt_sb;
> + char options[] = "huge=within_size";

char const options[] ?

> + int flags = 0;
> +
> + /* We don't consider failure to remount fatal, since this should
> +  * only ever attempt to modify the mount options of the sb, and
> +  * so should always leave us with a working mount upon failure.
> +  * Hence decoupling this from the actual kern_mount is probably
> +  * advisable.
> +  */
> + WARN_ON(sb->s_op->remount_fs(sb, , options));

Not to have too many fallback paths, would it make sense for any error
in setting up gemfs to result in NULL gemfs and fallback to tmpfs?

With the string constified, this is:

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 05/23] drm/i915: push set_pages down to the callers

[Joonas Lahtinen]

On Mon, 2017-08-21 at 19:34 +0100, Matthew Auld wrote:
> Each backend is now responsible for calling __i915_gem_object_set_pages
> upon successfully gathering its backing storage. This eliminates the
> inconsistency between the async and sync paths, which stands out even
> more when we start throwing around an sg_mask in a later patch.
> 
> Suggested-by: Chris Wilson 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 



> @@ -2485,12 +2490,10 @@ static int i915_gem_object_get_pages(struct 
> drm_i915_gem_object *obj)
>   return -EFAULT;
>   }
>  
> - pages = obj->ops->get_pages(obj);
> - if (unlikely(IS_ERR(pages)))
> - return PTR_ERR(pages);
> + ret = obj->ops->get_pages(obj);
> + GEM_BUG_ON(ret == 0 && IS_ERR_OR_NULL(obj->mm.pages));

!ret should be equally readable. Especially if you call the variable
"err".

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
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Re: [Intel-gfx] [PATCH 02/23] drm/i915: introduce simple gemfs

[Joonas Lahtinen]

On Mon, 2017-08-21 at 19:34 +0100, Matthew Auld wrote:
> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> moves us away from the shmemfs shm_mnt, and gives us the much needed
> flexibility to do things like set our own mount options, namely huge=
> which should allow us to enable the use of transparent-huge-pages for
> our shmem backed objects.
> 
> v2: various improvements suggested by Joonas
> 
> v3: move gemfs instance to i915.mm and simplify now that we have
> file_setup_with_mnt
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Dave Hansen 
> Cc: Kirill A. Shutemov 
> Cc: Hugh Dickins 
> Cc: linux...@kvack.org



> @@ -4288,6 +4289,25 @@ static const struct drm_i915_gem_object_ops 
> i915_gem_object_ops = {
>   .pwrite = i915_gem_object_pwrite_gtt,
>  };
>  
> +static int i915_gem_object_create_shmem(struct drm_device *dev,
> + struct drm_gem_object *obj,
> + size_t size)
> +{
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct file *filp;
> +
> + drm_gem_private_object_init(dev, obj, size);
> +
> + filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
> +  VM_NORESERVE);

Can you double-check that /proc/meminfo is unaffected by this change?
If we stop appearing under "Shemem:" we maybe need to maybe highlight
this somewhere (at least in commit message).



> +int i915_gemfs_init(struct drm_i915_private *i915)
> +{
> + struct file_system_type *type;
> + struct vfsmount *gemfs;
> +
> + type = get_fs_type("tmpfs");
> + if (!type)
> + return -ENODEV;
> +
> + gemfs = kern_mount(type);
> + if (IS_ERR(gemfs))
> + return PTR_ERR(gemfs);

By occasionally checking that "i915->mm.gemfs" might be NULL, could we
continue without our own gemfs mount and just lose the additional
features? Or is it not worth the hassle?

Anyway, this is:

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
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Open Source Technology Center
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Re: [Intel-gfx] [i-g-t PATCH 00/10] tools/intel_vbt_decode: switch to using kernel intel_vbt_defs.h

[Jani Nikula]

On Tue, 29 Aug 2017, Daniel Vetter  wrote:
> On Mon, Aug 28, 2017 at 03:19:52PM +0300, Jani Nikula wrote:
>> There's little point in duplicating the efforts of describing the same
>> data in two places. This series lets us use the verbatim copy of the
>> intel_vbt_defs.h from kernel. Going forward, we should add the changes
>> in kernel first, then copy the header over to igt.
>> 
>> If we need local tweaks, we can still have them in intel_bios.h, and
>> indeed we'll still have some after this series.
>
> I assume the end result matches what we now have in the kernel. Might be
> good practice to reference the sha1 of the kernel commit (needs to be a
> stable sha1, not drm-tip ofc) when resyncing in the future. On the series:
>
> Acked-by: Daniel Vetter 

Pushed, with the kernel commit reference added.

There'd be plenty to tweak and fix here, but the main goal of reducing
duplication was reached, so that'll do for now.

BR,
Jani.


>> 
>> BR,
>> Jani.
>> 
>> Jani Nikula (10):
>>   tools/intel_lid: use local register definition
>>   tools/intel_vbt_decode: remove unused definitions from intel_bios.h
>>   tools/intel_vbt_decode: clean up struct lvds_dvo_timing
>>   tools/intel_vbt_decode: start migrating to kernel intel_vbt_defs.h
>>   tools/intel_vbt_decode: migrate timing dumping to kernel struct
>>   tools/intel_vbt_decode: migrate child device dumping to kernel struct
>>   tools/intel_vbt_decode: migrate psr dumping to kernel struct
>>   tools/intel_vbt_decode: migrate edp dumping to kernel struct
>>   tools/intel_vbt_decode: migrate child device type bits decoding to
>> kernel defs
>>   tools/intel_vbt_defs: migrate backlight dumping to kernel struct
>> 
>>  tools/intel_bios.h   | 760 +--
>>  tools/intel_lid.c|   5 +-
>>  tools/intel_vbt_decode.c | 180 +-
>>  tools/intel_vbt_defs.h   | 897 
>> +++
>>  4 files changed, 996 insertions(+), 846 deletions(-)
>>  create mode 100644 tools/intel_vbt_defs.h
>> 
>> -- 
>> 2.11.0
>> 
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/atomic: Move drm_crtc_commit to drm_crtc_state.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/atomic: Move drm_crtc_commit to 
drm_crtc_state.
URL   : https://patchwork.freedesktop.org/series/29476/
State : success

== Summary ==

Series 29476v1 series starting with [1/2] drm/atomic: Move drm_crtc_commit to 
drm_crtc_state.
https://patchwork.freedesktop.org/api/1.0/series/29476/revisions/1/mbox/

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:444s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:365s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:573s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:529s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:526s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:436s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:618s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:448s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:516s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:601s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:482s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:493s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:484s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:410s
fi-pnv-d510 failed to connect after reboot

627598734e5ed449b1173ff8158126c57c361a40 drm-tip: 2017y-08m-29d-09h-52m-12s UTC 
integration manifest
73a398a3ba87 drm/atomic: Fix freeing connector/plane state too early by 
tracking commits
23c240dcae13 drm/atomic: Move drm_crtc_commit to drm_crtc_state.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5519/
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[Intel-gfx] ✓ Fi.CI.BAT: success for Improve robustness of the i915 perf tests (rev2)

[Patchwork]

== Series Details ==

Series: Improve robustness of the i915 perf tests (rev2)
URL   : https://patchwork.freedesktop.org/series/28373/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
bf45d253648250fc402eee02237366c8882b2053 igt: Add gem_close

with latest DRM-Tip kernel build CI_DRM_3014
627598734e5e drm-tip: 2017y-08m-29d-09h-52m-12s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:456s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:440s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:557s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:526s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:518s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:444s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:618s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:601s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:523s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6700k total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:482s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:490s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:439s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:506s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:405s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_118/
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Re: [Intel-gfx] [PATCH 01/23] mm/shmem: introduce shmem_file_setup_with_mnt

[Joonas Lahtinen]

On Fri, 2017-08-25 at 13:49 -0700, Andrew Morton wrote:
> On Thu, 24 Aug 2017 13:04:09 +0100 Matthew Auld 
>  wrote:
> 
> > On 23 August 2017 at 23:34, Andrew Morton  wrote:
> > > On Wed, 23 Aug 2017 12:31:28 +0300 Joonas Lahtinen 
> > >  wrote:
> > > 
> > > > This patch has been floating around for a while now Acked and without
> > > > further comments. It is blocking us from merging huge page support to
> > > > drm/i915.
> > > > 
> > > > Would you mind merging it, or prodding the right people to get it in?
> > > > 
> > > > Regards, Joonas
> > > > 
> > > > On Mon, 2017-08-21 at 19:34 +0100, Matthew Auld wrote:
> > > > > We are planning to use our own tmpfs mnt in i915 in place of the
> > > > > shm_mnt, such that we can control the mount options, in particular
> > > > > huge=, which we require to support huge-gtt-pages. So rather than roll
> > > > > our own version of __shmem_file_setup, it would be preferred if we 
> > > > > could
> > > > > just give shmem our mnt, and let it do the rest.
> > > 
> > > hm, it's a bit odd.  I'm having trouble locating the code which handles
> > > huge=within_size (and any other options?).
> > 
> > See here https://patchwork.freedesktop.org/patch/172771/, currently we
> > only care about huge=within_size.
> > 
> > > What other approaches were considered?
> > 
> > We also tried https://patchwork.freedesktop.org/patch/156528/, where
> > it was suggested that we mount our own tmpfs instance.
> > 
> > Following from that we now have our own tmps mnt mounted with
> > huge=within_size. With this patch we avoid having to roll our own
> > __shmem_file_setup like in
> > https://patchwork.freedesktop.org/patch/163024/.
> > 
> > > Was it not feasible to add i915-specific mount options to
> > > mm/shmem.c (for example?).
> > 
> > Hmm, I think within_size should suffice for our needs.
> 
> hm, ok, well, unless someone can think of something cleaner, please add
> my ack and include it in the appropriate drm tree.

Thanks, I will do that. It'll first get incorporated into drm-tip (
https://cgit.freedesktop.org/drm-tip) once the kselftests are finalized
(now that we know we're not facing third rewrite for core MM
dependency). And eventually into drm-next through a pull request to
Dave Airlie.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✓ Fi.CI.IGT: success for lib/igt_debugfs: Open DRM driver without master for hpd storm exit

[Patchwork]

== Series Details ==

Series: lib/igt_debugfs: Open DRM driver without master for hpd storm exit
URL   : https://patchwork.freedesktop.org/series/29470/
State : success

== Summary ==

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453

shard-hswtotal:2230 pass:1232 dwarn:0   dfail:0   fail:17  skip:981 
time:9575s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_117/shards.html
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[Intel-gfx] [PATCH 1/2] drm/i915: Pull wait-for-idle into i915_gem_switch_to_kernel_context()

[Chris Wilson]

All callers do want a synchronous switch to the kernel context, that is
by the time the call returns, the GPU has evicted all user contexts and
now has the kernel context pinned. As all callers want this behaviour,
refactor the common wait-for-idle into the switch.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c |  6 --
 drivers/gpu/drm/i915/i915_gem_context.c |  4 +++-
 drivers/gpu/drm/i915/i915_gem_evict.c   | 14 +-
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 890fe2802973..18ba74be286c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4564,12 +4564,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
if (ret)
goto err_unlock;
 
-   ret = i915_gem_wait_for_idle(dev_priv,
-I915_WAIT_INTERRUPTIBLE |
-I915_WAIT_LOCKED);
-   if (ret)
-   goto err_unlock;
-
assert_kernel_context_is_current(dev_priv);
i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 58a2a44f88bd..f70b05e682ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -924,7 +924,9 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
return ret;
}
 
-   return 0;
+   return i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
 }
 
 static bool client_is_banned(struct drm_i915_file_private *file_priv)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c 
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 4df039ef2ce3..5cf73ad4801a 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -52,25 +52,13 @@ static bool ggtt_is_idle(struct drm_i915_private *dev_priv)
 
 static int ggtt_flush(struct drm_i915_private *i915)
 {
-   int err;
-
/* Not everything in the GGTT is tracked via vma (otherwise we
 * could evict as required with minimal stalling) so we are forced
 * to idle the GPU and explicitly retire outstanding requests in
 * the hopes that we can then remove contexts and the like only
 * bound by their active reference.
 */
-   err = i915_gem_switch_to_kernel_context(i915);
-   if (err)
-   return err;
-
-   err = i915_gem_wait_for_idle(i915,
-I915_WAIT_INTERRUPTIBLE |
-I915_WAIT_LOCKED);
-   if (err)
-   return err;
-
-   return 0;
+   return i915_gem_switch_to_kernel_context(i915);
 }
 
 static bool
-- 
2.14.1

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[Intel-gfx] [PATCH 2/2] drm/i915/perf: Remove open-coding of i915_gem_switch_to_kernel_context()

[Chris Wilson]

The kernel context does not need to be updated for the oa config, since
it is *never* used for anything but idling the device; it should never
be required to emit OA samples. As such we can forgo tweaking the
context image, and just do a plain switch to enforce the GPU barrier so
that we can then update all other context images.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Lionel Landwerlin 
Cc: Matthew Auld  \o/
---
 drivers/gpu/drm/i915/i915_perf.c | 113 +--
 1 file changed, 1 insertion(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..b44199726897 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1623,112 +1623,6 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
}
 }
 
-/*
- * Same as gen8_update_reg_state_unlocked only through the batchbuffer. This
- * is only used by the kernel context.
- */
-static int gen8_emit_oa_config(struct drm_i915_gem_request *req,
-  const struct i915_oa_config *oa_config)
-{
-   struct drm_i915_private *dev_priv = req->i915;
-   /* The MMIO offsets for Flex EU registers aren't contiguous */
-   u32 flex_mmio[] = {
-   i915_mmio_reg_offset(EU_PERF_CNTL0),
-   i915_mmio_reg_offset(EU_PERF_CNTL1),
-   i915_mmio_reg_offset(EU_PERF_CNTL2),
-   i915_mmio_reg_offset(EU_PERF_CNTL3),
-   i915_mmio_reg_offset(EU_PERF_CNTL4),
-   i915_mmio_reg_offset(EU_PERF_CNTL5),
-   i915_mmio_reg_offset(EU_PERF_CNTL6),
-   };
-   u32 *cs;
-   int i;
-
-   cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   *cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1);
-
-   *cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
-   *cs++ = (dev_priv->perf.oa.period_exponent << 
GEN8_OA_TIMER_PERIOD_SHIFT) |
-   (dev_priv->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
-   GEN8_OA_COUNTER_RESUME;
-
-   for (i = 0; i < ARRAY_SIZE(flex_mmio); i++) {
-   u32 mmio = flex_mmio[i];
-
-   /*
-* This arbitrary default will select the 'EU FPU0 Pipeline
-* Active' event. In the future it's anticipated that there
-* will be an explicit 'No Event' we can select, but not
-* yet...
-*/
-   u32 value = 0;
-
-   if (oa_config) {
-   u32 j;
-
-   for (j = 0; j < oa_config->flex_regs_len; j++) {
-   if 
(i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
-   value = oa_config->flex_regs[j].value;
-   break;
-   }
-   }
-   }
-
-   *cs++ = mmio;
-   *cs++ = value;
-   }
-
-   *cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-static int gen8_switch_to_updated_kernel_context(struct drm_i915_private 
*dev_priv,
-const struct i915_oa_config 
*oa_config)
-{
-   struct intel_engine_cs *engine = dev_priv->engine[RCS];
-   struct i915_gem_timeline *timeline;
-   struct drm_i915_gem_request *req;
-   int ret;
-
-   lockdep_assert_held(_priv->drm.struct_mutex);
-
-   i915_gem_retire_requests(dev_priv);
-
-   req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
-   if (IS_ERR(req))
-   return PTR_ERR(req);
-
-   ret = gen8_emit_oa_config(req, oa_config);
-   if (ret) {
-   i915_add_request(req);
-   return ret;
-   }
-
-   /* Queue this switch after all other activity */
-   list_for_each_entry(timeline, _priv->gt.timelines, link) {
-   struct drm_i915_gem_request *prev;
-   struct intel_timeline *tl;
-
-   tl = >engine[engine->id];
-   prev = i915_gem_active_raw(>last_request,
-  _priv->drm.struct_mutex);
-   if (prev)
-   i915_sw_fence_await_sw_fence_gfp(>submit,
->submit,
-GFP_KERNEL);
-   }
-
-   ret = i915_switch_context(req);
-   i915_add_request(req);
-
-   return ret;
-}
-
 /*
  * Manages updating the per-context aspects of the OA stream
  * configuration across all contexts.
@@ -1771,11 +1665,6 @@ static int gen8_configure_all_contexts(struct 

[Intel-gfx] [PATCH 2/2] drm/atomic: Fix freeing connector/plane state too early by tracking commits

[Maarten Lankhorst]

Currently we neatly track the crtc state, but forget to look at
plane/connector state.

When doing a nonblocking modeset, immediately followed by a setprop
before the modeset completes, the setprop will see the modesets new
state as the old state and free it.

This has to be solved by waiting for hw_done on the connector, even
if it's not assigned to a crtc. When a connector is unbound we take
the last crtc commit, and when it stays unbound we create a new
crtc commit for the connector that gets signaled on hw_done.

We wait for it the same way as we do for crtc's, which will make
sure we never run into a use-after-free situation.

Signed-off-by: Maarten Lankhorst 
Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
Cc: Laurent Pinchart 
---
 drivers/gpu/drm/drm_atomic_helper.c | 171 ++--
 include/drm/drm_connector.h |   7 ++
 include/drm/drm_plane.h |   7 ++
 3 files changed, 179 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 9c2888cb4081..a4fd500d6200 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1644,6 +1644,39 @@ static void release_crtc_commit(struct completion 
*completion)
drm_crtc_commit_put(commit);
 }
 
+static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc *crtc)
+{
+   init_completion(>flip_done);
+   init_completion(>hw_done);
+   init_completion(>cleanup_done);
+   INIT_LIST_HEAD(>commit_entry);
+   kref_init(>ref);
+   commit->crtc = crtc;
+}
+
+static struct drm_crtc_commit *
+init_or_ref_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+   struct drm_crtc_commit *commit;
+
+   if (crtc) {
+   struct drm_crtc_state *new_crtc_state;
+
+   new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+
+   commit = new_crtc_state->commit;
+   drm_crtc_commit_get(commit);
+   } else {
+   commit = kzalloc(sizeof(*commit), GFP_KERNEL);
+   if (!commit)
+   return NULL;
+
+   init_commit(commit, NULL);
+   }
+
+   return commit;
+}
+
 /**
  * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
  * @state: new modeset state to be committed
@@ -1692,6 +1725,10 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
 {
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+   struct drm_connector *conn;
+   struct drm_connector_state *old_conn_state, *new_conn_state;
+   struct drm_plane *plane;
+   struct drm_plane_state *old_plane_state, *new_plane_state;
struct drm_crtc_commit *commit;
int i, ret;
 
@@ -1700,12 +1737,7 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
if (!commit)
return -ENOMEM;
 
-   init_completion(>flip_done);
-   init_completion(>hw_done);
-   init_completion(>cleanup_done);
-   INIT_LIST_HEAD(>commit_entry);
-   kref_init(>ref);
-   commit->crtc = crtc;
+   init_commit(commit, crtc);
 
new_crtc_state->commit = commit;
 
@@ -1741,6 +1773,36 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
drm_crtc_commit_get(commit);
}
 
+   for_each_oldnew_connector_in_state(state, conn, old_conn_state, 
new_conn_state, i) {
+   if (new_conn_state->crtc)
+   continue;
+
+   if (nonblock && old_conn_state->commit &&
+   
!try_wait_for_completion(_conn_state->commit->flip_done))
+   return -EBUSY;
+
+   commit = init_or_ref_crtc_commit(state, old_conn_state->crtc);
+   if (!commit)
+   return -ENOMEM;
+
+   new_conn_state->commit = commit;
+   }
+
+   for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
new_plane_state, i) {
+   if (new_plane_state->crtc)
+   continue;
+
+   if (nonblock && old_plane_state->commit &&
+   
!try_wait_for_completion(_plane_state->commit->flip_done))
+   return -EBUSY;
+
+   commit = init_or_ref_crtc_commit(state, old_plane_state->crtc);
+   if (!commit)
+   return -ENOMEM;
+
+   new_plane_state->commit = commit;
+   }
+
return 0;
 }
 EXPORT_SYMBOL(drm_atomic_helper_setup_commit);
@@ -1761,6 +1823,10 @@ void drm_atomic_helper_wait_for_dependencies(struct 
drm_atomic_state *old_state)
 {
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state;
+   struct drm_plane *plane;
+   

[Intel-gfx] [PATCH 1/2] drm/atomic: Move drm_crtc_commit to drm_crtc_state.

[Maarten Lankhorst]

Most code only cares about the current commit or previous commit.
Fortunately we already have a place to track those. Move it to
drm_crtc_state where it belongs. :)

The per-crtc commit_list is kept for places where we have to look
deeper than the current or previous commit for checking whether to stall
on unpin. This is used in drm_atomic_helper_setup_commit and
intel_has_pending_fb_unpin.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/drm_atomic.c|  7 ---
 drivers/gpu/drm/drm_atomic_helper.c | 92 ++---
 include/drm/drm_atomic.h|  1 -
 include/drm/drm_crtc.h  |  9 
 4 files changed, 32 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 2fd383d7253a..2cce48f203e0 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
crtc->funcs->atomic_destroy_state(crtc,
  state->crtcs[i].state);
 
-   if (state->crtcs[i].commit) {
-   kfree(state->crtcs[i].commit->event);
-   state->crtcs[i].commit->event = NULL;
-   drm_crtc_commit_put(state->crtcs[i].commit);
-   }
-
-   state->crtcs[i].commit = NULL;
state->crtcs[i].ptr = NULL;
state->crtcs[i].state = NULL;
}
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 4e53aae9a1fb..9c2888cb4081 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
 void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
  struct drm_atomic_state *old_state)
 {
-   struct drm_crtc_state *unused;
+   struct drm_crtc_state *new_crtc_state;
struct drm_crtc *crtc;
int i;
 
-   for_each_new_crtc_in_state(old_state, crtc, unused, i) {
-   struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
+   for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
+   struct drm_crtc_commit *commit = new_crtc_state->commit;
int ret;
 
if (!commit)
@@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device 
*dev,
 {
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
-   struct drm_crtc_commit *commit;
struct drm_plane *__plane, *plane = NULL;
struct drm_plane_state *__plane_state, *plane_state = NULL;
const struct drm_plane_helper_funcs *funcs;
-   int i, j, n_planes = 0;
+   int i, n_planes = 0;
 
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
if (drm_atomic_crtc_needs_modeset(crtc_state))
@@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device 
*dev,
return -EINVAL;
 
/*
-* Don't do an async update if there is an outstanding commit modifying
+* XXX: Don't do an async update if there is an outstanding commit 
modifying
 * the plane.  This prevents our async update's changes from getting
 * overridden by a previous synchronous update's state.
 */
-   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
-   if (plane->crtc != crtc)
-   continue;
-
-   spin_lock(>commit_lock);
-   commit = list_first_entry_or_null(>commit_list,
- struct drm_crtc_commit,
- commit_entry);
-   if (!commit) {
-   spin_unlock(>commit_lock);
-   continue;
-   }
-   spin_unlock(>commit_lock);
-
-   if (!crtc->state->state)
-   continue;
-
-   for_each_plane_in_state(crtc->state->state, __plane,
-   __plane_state, j) {
-   if (__plane == plane)
-   return -EINVAL;
-   }
-   }
 
return funcs->atomic_async_check(plane, plane_state);
 }
@@ -1731,7 +1707,7 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
kref_init(>ref);
commit->crtc = crtc;
 
-   state->crtcs[i].commit = commit;
+   new_crtc_state->commit = commit;
 
ret = stall_checks(crtc, nonblock);
if (ret)
@@ -1769,22 +1745,6 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
 }
 EXPORT_SYMBOL(drm_atomic_helper_setup_commit);
 
-
-static struct drm_crtc_commit *preceeding_commit(struct drm_crtc *crtc)
-{
-   

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Discard the request queue if we fail to sleep before suspend

[Mika Kuoppala]

Chris Wilson  writes:

> If we fail to clear the outstanding request queue before suspending,
> mark those requests as lost.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102037
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Joonas Lahtinen 
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9dc24b915aa7..37fbc64d9ffe 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4585,7 +4585,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
>* reset the GPU back to its idle, low power state.
>*/
>   WARN_ON(dev_priv->gt.awake);
> - WARN_ON(!intel_engines_are_idle(dev_priv));
> + if (WARN_ON(!intel_engines_are_idle(dev_priv)))
> + i915_gem_set_wedged(dev_priv); /* no hope, so reset everthing */

s/ever/every

Reviewed-by: Mika Kuoppala 

>  
>   /*
>* Neither the BIOS, ourselves or any other kernel
> -- 
> 2.14.1
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[Intel-gfx] [PATCH i-g-t v4 06/12] tests/perf: rework oa-exponent test

[Lionel Landwerlin]

New issues that were discovered while making the tests work on Gen8+ :

 - we need to measure timings between periodic reports and discard all
   other kind of reports

 - it seems periodicity of the reports can be affected outside of RC6
   (frequency change), we can detect this by looking at the amount of
   clock cycles per timestamp deltas

v2: Drop some unused variables (Matthew)

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 733 ---
 1 file changed, 599 insertions(+), 134 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index ca69440d..efaa4a06 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -306,6 +307,25 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static bool
+timestamp_delta_within(uint32_t delta,
+  uint32_t expected_delta,
+  uint32_t margin)
+{
+   return delta >= (expected_delta - margin) &&
+  delta <= (expected_delta + margin);
+}
+
+static bool
+double_value_within(double value,
+   double expected,
+   double percent_margin)
+{
+   return value >= (expected - expected * percent_margin / 100.0) &&
+  value <= (expected + expected * percent_margin / 100.0);
+
+}
+
 static void
 __perf_close(int fd)
 {
@@ -472,6 +492,20 @@ gen8_read_report_ticks(uint32_t *report, enum 
drm_i915_oa_format format)
return report[3];
 }
 
+static void
+gen8_read_report_clock_ratios(uint32_t *report,
+ uint32_t *slice_freq_mhz,
+ uint32_t *unslice_freq_mhz)
+{
+   uint32_t unslice_freq = report[0] & 0x1ff;
+   uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+   uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+   uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+   *slice_freq_mhz = (slice_freq * 1) / 1000;
+   *unslice_freq_mhz = (unslice_freq * 1) / 1000;
+}
+
 static const char *
 gen8_read_report_reason(const uint32_t *report)
 {
@@ -494,29 +528,6 @@ gen8_read_report_reason(const uint32_t *report)
return "unknown";
 }
 
-static bool
-oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
-{
-   if (IS_HASWELL(devid)) {
-   /* For Haswell we don't have a documented report reason field
-* (though empirically report[0] bit 10 does seem to correlate
-* with a timer trigger reason) so we instead infer which
-* reports are timer triggered by checking if the least
-* significant bits are zero and the exponent bit is set.
-*/
-   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
-
-   if ((report[1] & oa_exponent_mask) != (1 << oa_exponent))
-   return true;
-   } else {
-   if ((report[0] >> OAREPORT_REASON_SHIFT) &
-   OAREPORT_REASON_TIMER)
-   return true;
-   }
-
-   return false;
-}
-
 static uint64_t
 timebase_scale(uint32_t u32_delta)
 {
@@ -563,6 +574,29 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   /* For Haswell we don't have a documented report reason field
+* (though empirically report[0] bit 10 does seem to correlate
+* with a timer trigger reason) so we instead infer which
+* reports are timer triggered by checking if the least
+* significant bits are zero and the exponent bit is set.
+*/
+   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
+
+   if ((report[1] & oa_exponent_mask) == (1 << oa_exponent))
+   return true;
+   } else {
+   if ((report[0] >> OAREPORT_REASON_SHIFT) &
+   OAREPORT_REASON_TIMER)
+   return true;
+   }
+
+   return false;
+}
+
 static bool
 oa_report_ctx_is_valid(uint32_t *report)
 {
@@ -578,6 +612,128 @@ oa_report_ctx_is_valid(uint32_t *report)
igt_assert(!"reached");
 }
 
+static uint32_t
+oa_report_get_ctx_id(uint32_t *report)
+{
+   if (!oa_report_ctx_is_valid(report))
+   return 0x;
+   return report[2];
+}
+
+static double
+oa_reports_tick_per_period(uint32_t *report0, uint32_t *report1)
+{
+   if (intel_gen(devid) < 8)
+   return 0.0;
+
+   /* Measure the number GPU tick delta to timestamp delta. */
+   return (double) 

[Intel-gfx] [PATCH i-g-t v4 09/12] tests/perf: add Kabylake support

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matthew Auld 
---
 tests/perf.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index 32d53ea1..32f34ec4 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -,8 +,23 @@ init_sys_info(void)
} else if (IS_BROXTON(devid)) {
test_set_uuid = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
timestamp_frequency = 1920;
-   } else
+   } else if (IS_KABYLAKE(devid)) {
+   switch (intel_gt(devid)) {
+   case 1:
+   test_set_uuid = 
"baa3c7e4-52b6-4b85-801e-465a94b746dd";
+   break;
+   case 2:
+   test_set_uuid = 
"f1792f32-6db2-4b50-b4b2-557128f1688d";
+   break;
+   default:
+   igt_debug("unsupported Kabylake GT size\n");
+   return false;
+   }
+   timestamp_frequency = 1200;
+   } else {
+   igt_debug("unsupported GT\n");
return false;
+   }
 
gp.param = I915_PARAM_EU_TOTAL;
gp.value = _eus;
-- 
2.14.1

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