Re: [Intel-gfx] [PATCH i-g-t] tests/kms_atomic: subtest atomic_invalid_params requires CRTC

[Arkadiusz Hiler]

On Tue, Aug 29, 2017 at 01:49:18PM +0300, Mika Kahola wrote:
> In my view, this is a valid check.
> 
> Reviewed-by: Mika Kahola 
> 
> On Tue, 2017-08-29 at 13:32 +0300, Marta Lofstedt wrote:
> > Check for valid crtc is missing in igt@kms_atomic@atomic_invalid_para
> > ms.
> > This leads to segfault on machines where the subtest should be
> > skipped.
> > 
> > Signed-off-by: Marta Lofstedt 

pushed

thanks for the patch and the review :-)

-- 
Cheers,
Arek
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Re: [Intel-gfx] [PATCH 1/2] drm/atomic: Move drm_crtc_commit to drm_crtc_state.

[Daniel Vetter]

On Tue, Aug 29, 2017 at 04:02:02PM +0200, Maarten Lankhorst wrote:
> Most code only cares about the current commit or previous commit.
> Fortunately we already have a place to track those. Move it to
> drm_crtc_state where it belongs. :)
> 
> The per-crtc commit_list is kept for places where we have to look
> deeper than the current or previous commit for checking whether to stall
> on unpin. This is used in drm_atomic_helper_setup_commit and
> intel_has_pending_fb_unpin.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/drm_atomic.c|  7 ---
>  drivers/gpu/drm/drm_atomic_helper.c | 92 
> ++---
>  include/drm/drm_atomic.h|  1 -
>  include/drm/drm_crtc.h  |  9 
>  4 files changed, 32 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2fd383d7253a..2cce48f203e0 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct 
> drm_atomic_state *state)
>   crtc->funcs->atomic_destroy_state(crtc,
> state->crtcs[i].state);
>  
> - if (state->crtcs[i].commit) {
> - kfree(state->crtcs[i].commit->event);
> - state->crtcs[i].commit->event = NULL;
> - drm_crtc_commit_put(state->crtcs[i].commit);
> - }
> -
> - state->crtcs[i].commit = NULL;
>   state->crtcs[i].ptr = NULL;
>   state->crtcs[i].state = NULL;
>   }
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4e53aae9a1fb..9c2888cb4081 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
>  void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
> struct drm_atomic_state *old_state)
>  {
> - struct drm_crtc_state *unused;
> + struct drm_crtc_state *new_crtc_state;
>   struct drm_crtc *crtc;
>   int i;
>  
> - for_each_new_crtc_in_state(old_state, crtc, unused, i) {
> - struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
> + for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
> + struct drm_crtc_commit *commit = new_crtc_state->commit;
>   int ret;
>  
>   if (!commit)
> @@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device 
> *dev,
>  {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *crtc_state;
> - struct drm_crtc_commit *commit;
>   struct drm_plane *__plane, *plane = NULL;
>   struct drm_plane_state *__plane_state, *plane_state = NULL;
>   const struct drm_plane_helper_funcs *funcs;
> - int i, j, n_planes = 0;
> + int i, n_planes = 0;
>  
>   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
>   if (drm_atomic_crtc_needs_modeset(crtc_state))
> @@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device 
> *dev,
>   return -EINVAL;
>  
>   /*
> -  * Don't do an async update if there is an outstanding commit modifying
> +  * XXX: Don't do an async update if there is an outstanding commit 
> modifying
>* the plane.  This prevents our async update's changes from getting
>* overridden by a previous synchronous update's state.
>*/
> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - if (plane->crtc != crtc)
> - continue;
> -
> - spin_lock(&crtc->commit_lock);
> - commit = list_first_entry_or_null(&crtc->commit_list,
> -   struct drm_crtc_commit,
> -   commit_entry);
> - if (!commit) {
> - spin_unlock(&crtc->commit_lock);
> - continue;
> - }
> - spin_unlock(&crtc->commit_lock);
> -
> - if (!crtc->state->state)
> - continue;
> -
> - for_each_plane_in_state(crtc->state->state, __plane,
> - __plane_state, j) {
> - if (__plane == plane)
> - return -EINVAL;
> - }
> - }
>  
>   return funcs->atomic_async_check(plane, plane_state);
>  }
> @@ -1731,7 +1707,7 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   kref_init(&commit->ref);
>   commit->crtc = crtc;
>  
> - state->crtcs[i].commit = commit;
> + new_crtc_state->commit = commit;
>  
>   ret = stall_checks(crtc, nonblock);
>   if (ret)
> @@ -1769,22 +1745,6 @@ int drm_atomic_helper_setup_commit

Re: [Intel-gfx] [Resend for flip-flops] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Chris Wilson (2017-08-29 20:25:46)
> Since we hold the device wakeref when writing through the GTT (otherwise
> the writes would fail), we presumed that before the device sleeps those
> writes would naturally be flushed and that we wouldn't need our mmio
> read trick. However, that presumption seems false and a sleepy bxt seems
> to require us to always manually flush the GTT writes prior to direct
> access.
> 
> Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before flushing 
> GTT writes")
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Reviewed-by: Joonas Lahtinen 

On the basis of two samples, this seems to fix the pwrite flip-flops,
so pushed for a wider sampling.
-Chris
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Re: [Intel-gfx] [PATCH 00/12] drm/i915: Fix up the CCS code

[Jani Nikula]

On Mon, 28 Aug 2017, Ville Syrjälä  wrote:
> On Mon, Aug 28, 2017 at 02:35:54PM +0100, Daniel Stone wrote:
>> Hi Daniel,
>> 
>> On 25 August 2017 at 18:17, Daniel Vetter  wrote:
>> > Which of these do we need to cherry-pick over to -next-fixes? There's no
>> > annotations about that. If the answer is "most" I'm leaning towards
>> > disabling CCS for 4.14, minimal set would be ideal (and first in the patch
>> > series).
>> 
>> My opinion below; tl;dr is that I don't think most of them are
>> super-critical. Ville obviously has a far stronger opinion than me on
>> the shape of the code, so I'm fine with this series, which seems to
>> mostly be a merge back of the delta between whatever Ville's latest
>> branch was, and whatever the last patchset Ben sent out was.
>> 
>> >> Ville Syrjälä (12):
>> >>   drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear
>> >> offset
>> 
>> This should land into -fixes. I trust Ville that it has no UABI
>> impact, but seems like something to be very consistent on.
>
> It does change the uabi. That's the whole point. What was merged doesn't
> agree with what userspace wants. So this we want in definitely so that
> we don't end up exposing the wrong uabi in any released kernel.
>
>> 
>> >>   drm/i915: Skip fence alignemnt check for the CCS plane
>> 
>> Not sure if this is -fixes material really, just a cleanup?
>
> It makes the kernel less likely to reject the fb entirely. So
> without this userspace has to be rather careful where it places
> the aux surface. I would include this as well.
>
>> 
>> >>   drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for
>> >> CCS
>> 
>> Not -fixes, performance optimisation.
>
> We hope. It does change the layout of the compressed data though so if
> our testcases try to generate compressed data with the CPU it'll not go
> well if the test assumes the wrong hash mode. I would include this as
> well so that we don't end up in any kind of a mess later when we try to
> change it.
>
> So the patches were more or less sorted in priority order, and we want
> at least 01,02 and maybe 03.

When you decide what to apply, please *please* add the appropriate
Fixes: tags for the ones you want to show up in v4.14.

BR,
Jani.


>
>> 
>> >>   drm/i915: Add a comment exlaining CCS hsub/vsub
>> 
>> Seems harmless to land to -fixes.
>> 
>> >>   drm/i915: Nuke a pointless unreachable()
>> 
>> Ditto.
>> 
>> >>   drm/i915: Add the missing Y/Yf modifiers for SKL+ sprites
>> 
>> Per my previous reply, NAK to landing at all, since DDB/WM allocation
>> seems too broken for it to work.
>> 
>> >>   drm/i915: Clean up the sprite modifier checks
>> 
>> Fine with this, but doesn't seem like -fixes material.
>> 
>> >>   drm/i915: Add CCS capability for sprites
>> 
>> NAK, same reason as Y/Yf.
>> 
>> >>   drm/i915: Allow up to 32KB stride on SKL+ "sprites"
>> 
>> Again doesn't seem like -fixes necessarily?
>> 
>> >>   drm: Fix modifiers_property kernel doc
>> 
>> Good for -fixes.
>> 
>> >>   drm: Check that the plane supports the request format+modifier combo
>> 
>> Good for core (not Intel) -fixes.
>> 
>> >>   drm/i915: Remove the pipe/plane ID checks from
>> >> skl_check_ccs_aux_surface()
>> 
>> Seems fine but probably not -fixes material; land in Intel after a merge?
>> 
>> Cheers,
>> Daniel

-- 
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaDisableI2mCycleOnWRPort

[Mika Kuoppala]

Rodrigo Vivi  writes:

> On CNL B0 stepping GAM is not able to detect some deadlock
> condition and then rise the rise the gam_coh_flush.
>
> WA database and spec both mentions to set 4AB8[24]=1 as
> workaround. Alghouth register offset 0x4AB8 is not
s/Alghouth/Although

> documented for any platform.
>

References: HSD#1945815, BSID#1112

> Cc: Mika Kuoppala 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_reg.h| 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..bbacdac5c794 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2373,6 +2373,7 @@ enum i915_power_well_id {
>  
>  #define GAMT_CHKN_BIT_REG_MMIO(0x4ab8)
>  #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING   (1<<28)
> +#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
>  
>  #if 0
>  #define PRB0_TAIL_MMIO(0x2030)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..f087eb6b0134 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,11 @@ static int cnl_init_workarounds(struct intel_engine_cs 
> *engine)
>   struct drm_i915_private *dev_priv = engine->i915;
>   int ret;
>  
> + /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
> + if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> + WA_SET_BIT(GAMT_CHKN_BIT_REG,
> +GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
> +
>   /* WaForceContextSaveRestoreNonCoherent:cnl */
>   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> -- 
> 2.13.2
>
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Mika Kuoppala]

Rodrigo Vivi  writes:

> WA to enable HW L1 Banking fix that allows aniso to operate
> at full sample rate.
>

References: HSD#1937670

> Cc: Mika Kuoppala 
> Cc: Oscar Mateo 
> Cc: Ben Widawsky 
> Cc: Anuj Phogat 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_reg.h| 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..1ad22a824921 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8072,6 +8072,7 @@ enum {
>  #define   HSW_SAMPLE_C_PERFORMANCE   (1<<9)
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS(1<<8)
>  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC(1<<5)
> +#define   CNL_FAST_ANISO_L1_BANKING_FIX  (1<<4)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS  (1<<1)
>  
>  #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..4b9b7828802d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
> *engine)
>   /* WaPushConstantDereferenceHoldDisable:cnl */
>   WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
>  
> + /* FtrEnableFastAnisoL1BankingFix: cnl */
> + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> +
>   /* WaEnablePreemptionGranularityControlByUMD:cnl */
>   ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
>   if (ret)
> -- 
> 2.13.2
>
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[Intel-gfx] [PATCH] drm/i915: Add interface to reserve fence registers for vGPU

[changbin . du]

From: Changbin Du 

In the past, vGPU alloc fence registers by walking through mm.fence_list
to find fence which pin_count = 0 and vma is empty. vGPU may not find
enough fence registers this way. Because a fence can be bind to vma even
though it is not in using. We have found such failure many times these
days.

An option to resolve this issue is that we can force-remove fence from
vma in this case.

This patch added two new api to the fence management code:
 - i915_reserve_one_fence() will try to find a free fence from fence_list
   and force-remove vma if need.
 - i915_giveback_reserved_fence() reclaim a reserved fence after vGPU has
   finished.

With this change, the fence management is more clear to work with vGPU.
GVTg do not need remove fence from fence_list in private.

Signed-off-by: Changbin Du 
---
 drivers/gpu/drm/i915/gvt/aperture_gm.c| 26 +
 drivers/gpu/drm/i915/i915_drv.h   |  3 +++
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 39 +++
 3 files changed, 53 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c 
b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index ca3d192..29f1bf7 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
_clear_vgpu_fence(vgpu);
for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
reg = vgpu->fence.regs[i];
-   list_add_tail(®->link,
- &dev_priv->mm.fence_list);
+   i915_giveback_reserved_fence(reg);
+   vgpu->fence.regs[i] = NULL;
}
mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
struct drm_i915_private *dev_priv = gvt->dev_priv;
struct drm_i915_fence_reg *reg;
int i;
-   struct list_head *pos, *q;
 
intel_runtime_pm_get(dev_priv);
 
/* Request fences from host */
mutex_lock(&dev_priv->drm.struct_mutex);
-   i = 0;
-   list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
-   reg = list_entry(pos, struct drm_i915_fence_reg, link);
-   if (reg->pin_count || reg->vma)
-   continue;
-   list_del(pos);
+
+   for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
+   reg = i915_reserve_one_fence(dev_priv);
+   if (IS_ERR(reg))
+   goto out_free_fence;
+
vgpu->fence.regs[i] = reg;
-   if (++i == vgpu_fence_sz(vgpu))
-   break;
}
-   if (i != vgpu_fence_sz(vgpu))
-   goto out_free_fence;
 
_clear_vgpu_fence(vgpu);
 
@@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
intel_runtime_pm_put(dev_priv);
return 0;
 out_free_fence:
+   gvt_vgpu_err("Failed to alloc fences\n");
/* Return fences to host, if fail */
for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
reg = vgpu->fence.regs[i];
if (!reg)
continue;
-   list_add_tail(®->link,
- &dev_priv->mm.fence_list);
+   i915_giveback_reserved_fence(reg);
+   vgpu->fence.regs[i] = NULL;
}
mutex_unlock(&dev_priv->drm.struct_mutex);
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef5..c505b44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3650,6 +3650,9 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
 /* i915_gem_fence_reg.c */
 int __must_check i915_vma_get_fence(struct i915_vma *vma);
 int __must_check i915_vma_put_fence(struct i915_vma *vma);
+struct drm_i915_fence_reg *
+i915_reserve_one_fence(struct drm_i915_private *dev_priv);
+void i915_giveback_reserved_fence(struct drm_i915_fence_reg *fence);
 
 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c 
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 5fe2cd8..63e4e94 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -360,6 +360,45 @@ i915_vma_get_fence(struct i915_vma *vma)
 }
 
 /**
+ * i915_reserve_one_fence - Reserve a fence for vGPU
+ * @dev_priv: i915 device private
+ *
+ * This function walks the fence regs looking for a free one and remove
+ * it from the fence_list. It is used to reserve fence for vGPU to use.
+ */
+struct drm_i915_fence_reg *
+i915_reserve_one_fence(struct drm_i915_private *dev_priv)
+{
+   struct drm_i915_fence_reg *fence;
+   int ret;
+
+   fence = fence_find(dev_priv);
+   if (IS_ERR(fence))
+   return fence;
+
+   if (fence->vma)

Re: [Intel-gfx] [PATCH 2/2] drm/atomic: Fix freeing connector/plane state too early by tracking commits

[Daniel Vetter]

Onnkhorst> that would be the right thing to do
 chickens didn't want to audit 20+ drivers :-)
 neither, could we just break them? :pTue, Aug 29, 2017 at 
04:02:03PM +0200, Maarten Lankhorst wrote:
> Currently we neatly track the crtc state, but forget to look at
> plane/connector state.
> 
> When doing a nonblocking modeset, immediately followed by a setprop
> before the modeset completes, the setprop will see the modesets new
> state as the old state and free it.
> 
> This has to be solved by waiting for hw_done on the connector, even
> if it's not assigned to a crtc. When a connector is unbound we take
> the last crtc commit, and when it stays unbound we create a new
> crtc commit for the connector that gets signaled on hw_done.
> 
> We wait for it the same way as we do for crtc's, which will make
> sure we never run into a use-after-free situation.
> 
> Signed-off-by: Maarten Lankhorst 
> Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> Cc: Laurent Pinchart 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c | 171 
> ++--
>  include/drm/drm_connector.h |   7 ++
>  include/drm/drm_plane.h |   7 ++
>  3 files changed, 179 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 9c2888cb4081..a4fd500d6200 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1644,6 +1644,39 @@ static void release_crtc_commit(struct completion 
> *completion)
>   drm_crtc_commit_put(commit);
>  }
>  
> +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc 
> *crtc)
> +{
> + init_completion(&commit->flip_done);
> + init_completion(&commit->hw_done);
> + init_completion(&commit->cleanup_done);
> + INIT_LIST_HEAD(&commit->commit_entry);
> + kref_init(&commit->ref);
> + commit->crtc = crtc;
> +}
> +
> +static struct drm_crtc_commit *
> +init_or_ref_crtc_commit(struct drm_atomic_state *state, struct drm_crtc 
> *crtc)
> +{
> + struct drm_crtc_commit *commit;
> +
> + if (crtc) {
> + struct drm_crtc_state *new_crtc_state;
> +
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> +
> + commit = new_crtc_state->commit;
> + drm_crtc_commit_get(commit);
> + } else {
> + commit = kzalloc(sizeof(*commit), GFP_KERNEL);
> + if (!commit)
> + return NULL;
> +
> + init_commit(commit, NULL);
> + }
> +
> + return commit;
> +}
> +
>  /**
>   * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
>   * @state: new modeset state to be committed
> @@ -1692,6 +1725,10 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>  {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> + struct drm_connector *conn;
> + struct drm_connector_state *old_conn_state, *new_conn_state;
> + struct drm_plane *plane;
> + struct drm_plane_state *old_plane_state, *new_plane_state;
>   struct drm_crtc_commit *commit;
>   int i, ret;
>  
> @@ -1700,12 +1737,7 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   if (!commit)
>   return -ENOMEM;
>  
> - init_completion(&commit->flip_done);
> - init_completion(&commit->hw_done);
> - init_completion(&commit->cleanup_done);
> - INIT_LIST_HEAD(&commit->commit_entry);
> - kref_init(&commit->ref);
> - commit->crtc = crtc;
> + init_commit(commit, crtc);
>  
>   new_crtc_state->commit = commit;
>  
> @@ -1741,6 +1773,36 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   drm_crtc_commit_get(commit);
>   }
>  
> + for_each_oldnew_connector_in_state(state, conn, old_conn_state, 
> new_conn_state, i) {
> + if (new_conn_state->crtc)
> + continue;
> +
> + if (nonblock && old_conn_state->commit &&
> + 
> !try_wait_for_completion(&old_conn_state->commit->flip_done))
> + return -EBUSY;
> +
> + commit = init_or_ref_crtc_commit(state, old_conn_state->crtc);
> + if (!commit)
> + return -ENOMEM;
> +
> + new_conn_state->commit = commit;
> + }
> +
> + for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
> new_plane_state, i) {
> + if (new_plane_state->crtc)
> + continue;
> +
> + if (nonblock && old_plane_state->commit &&
> + 
> !try_wait_for_completion(&old_plane_state->commit->flip_done))
> + return -EBUSY;
> +
> + commit = init_or_ref_crtc_commit(state, old_plane_state->crtc);
> + if (!commit)
> + return -ENOM

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add interface to reserve fence registers for vGPU

[Patchwork]

== Series Details ==

Series: drm/i915: Add interface to reserve fence registers for vGPU
URL   : https://patchwork.freedesktop.org/series/29523/
State : success

== Summary ==

Series 29523v1 drm/i915: Add interface to reserve fence registers for vGPU
https://patchwork.freedesktop.org/api/1.0/series/29523/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:440s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:542s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:257s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:523s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:522s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:613s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:447s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:428s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:499s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:483s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:593s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:596s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:523s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:463s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:492s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:479s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:401s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
26b12b402e67 drm/i915: Add interface to reserve fence registers for vGPU

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5535/
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Re: [Intel-gfx] [PATCH] drm/i915: Add interface to reserve fence registers for vGPU

[Chris Wilson]

Quoting changbin...@intel.com (2017-08-30 09:54:21)
> This patch added two new api to the fence management code:
>  - i915_reserve_one_fence() will try to find a free fence from fence_list
>and force-remove vma if need.
>  - i915_giveback_reserved_fence() reclaim a reserved fence after vGPU has
>finished.

Symmetry: reserve_fence, unreserve_fence.

We need a safeguard here so that the host is able to always able allocate
to allocate a fence for the display engine. (That requirement should be
quite soft for modern hw, nevertheless it should be in the design to
prevent overuse from leading to an unusable system.)
-Chris
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Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Daniel Vetter]

One more on top of Lionel's coments.

On Mon, Aug 28, 2017 at 03:23:03PM +0530, Sagar Arun Kamble wrote:
> +int main(int argc, char **argv)
> +{
> + bool ret;
> + int option;
> + int platform;
> +
> + if (argc != 3) {
> + printf("Usage: \n./dapc  \
> + \nPlatform: 0-HSW, 1-BDW, 2-SKL\n\
> + \nTest_mode:\n\
> + \t0 - RCS OA mode\n\
> + \t1 - RCS TS mode\n\
> + \t2 - RCS TS+MMIO mode\n\
> + \t3 - RCS OA+TS+MMIO mode\n\
> + \t4 - Periodic OA mode\n");
> + return 0;
> + }
> +
> + ret = initialize();
> + if (!ret)
> + return -1;
> +
> + platform = atoi(argv[1]);
> + switch (platform) {
> + case 0:
> + arch = ARCH_HSW;
> + break;
> + case 1:
> + arch = ARCH_BDW;
> + break;
> + case 2:
> + arch = ARCH_SKL;
> + break;
> + default:
> + fprintf(stderr, "Invalid platform:%d\n", platform);
> + return -1;
> + }
> +
> + option = atoi(argv[2]);

Please convert this into a proper igt testcase that enumrates subtests
like all the others. Otherwise CI won't pick it up, which makes this
wasted effort. This means using igt_main, igt_subtest, igt_fixture and all
the various igt_assert/require macros we have to check results.

Also dapc is not a good testcase name, needs some proper prefixing.
-Daniel

> + switch (option) {
> + case 0:
> + test_perf_dapc_rcs_oa();
> + break;
> + case 1:
> + test_perf_dapc_rcs_ts();
> + break;
> + case 2:
> + test_perf_dapc_rcs_ts_mmio();
> + break;
> + case 3:
> + test_perf_dapc_rcs_oa_ts_mmio();
> + break;
> + case 4:
> + test_perf_dapc_periodic_oa();
> + break;
> + default:
> + fprintf(stderr, "Invalid Option:%d\n", option);
> + return -1;
> + }
> +
> + return 0;
> +}
> -- 
> 1.9.1
> 

> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Lionel Landwerlin]

On 30/08/17 10:39, Daniel Vetter wrote:

Also dapc is not a good testcase name, needs some proper prefixing.



Reminds me perf.c should probably be renamed too.
What would be an appropriate name? intel_perf.c?
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Re: [Intel-gfx] [PATCH 1/2] drm/atomic: Move drm_crtc_commit to drm_crtc_state.

[Laurent Pinchart]

On Tuesday, 29 August 2017 17:02:02 EEST Maarten Lankhorst wrote:
> Most code only cares about the current commit or previous commit.
> Fortunately we already have a place to track those. Move it to
> drm_crtc_state where it belongs. :)
> 
> The per-crtc commit_list is kept for places where we have to look
> deeper than the current or previous commit for checking whether to stall
> on unpin. This is used in drm_atomic_helper_setup_commit and
> intel_has_pending_fb_unpin.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/drm_atomic.c|  7 ---
>  drivers/gpu/drm/drm_atomic_helper.c | 92 --
>  include/drm/drm_atomic.h|  1 -
>  include/drm/drm_crtc.h  |  9 
>  4 files changed, 32 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2fd383d7253a..2cce48f203e0 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct
> drm_atomic_state *state) crtc->funcs->atomic_destroy_state(crtc,
> state->crtcs[i].state);
> 
> - if (state->crtcs[i].commit) {
> - kfree(state->crtcs[i].commit->event);
> - state->crtcs[i].commit->event = NULL;
> - drm_crtc_commit_put(state->crtcs[i].commit);
> - }
> -
> - state->crtcs[i].commit = NULL;
>   state->crtcs[i].ptr = NULL;
>   state->crtcs[i].state = NULL;
>   }
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index 4e53aae9a1fb..9c2888cb4081
> 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
>  void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
> struct drm_atomic_state *old_state)
>  {
> - struct drm_crtc_state *unused;
> + struct drm_crtc_state *new_crtc_state;
>   struct drm_crtc *crtc;
>   int i;
> 
> - for_each_new_crtc_in_state(old_state, crtc, unused, i) {
> - struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
> + for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
> + struct drm_crtc_commit *commit = new_crtc_state->commit;
>   int ret;
> 
>   if (!commit)
> @@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device
> *dev, {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *crtc_state;
> - struct drm_crtc_commit *commit;
>   struct drm_plane *__plane, *plane = NULL;
>   struct drm_plane_state *__plane_state, *plane_state = NULL;
>   const struct drm_plane_helper_funcs *funcs;
> - int i, j, n_planes = 0;
> + int i, n_planes = 0;
> 
>   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
>   if (drm_atomic_crtc_needs_modeset(crtc_state))
> @@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device
> *dev, return -EINVAL;
> 
>   /*
> -  * Don't do an async update if there is an outstanding commit modifying
> +  * XXX: Don't do an async update if there is an outstanding commit
> modifying
>* the plane.  This prevents our async update's changes from getting
>* overridden by a previous synchronous update's state.
>*/

This looks like work in progress. The code is gone and the comment left. I'm 
not sure what 'XXX' means. If it's a TODO, patch 2/2 doesn't address it. And 
if you really meant to drop this check permanently, the reason should be 
explained in the commit message.

> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - if (plane->crtc != crtc)
> - continue;
> -
> - spin_lock(&crtc->commit_lock);
> - commit = list_first_entry_or_null(&crtc->commit_list,
> -   struct drm_crtc_commit,
> -   commit_entry);
> - if (!commit) {
> - spin_unlock(&crtc->commit_lock);
> - continue;
> - }
> - spin_unlock(&crtc->commit_lock);
> -
> - if (!crtc->state->state)
> - continue;
> -
> - for_each_plane_in_state(crtc->state->state, __plane,
> - __plane_state, j) {
> - if (__plane == plane)
> - return -EINVAL;
> - }
> - }
> 
>   return funcs->atomic_async_check(plane, plane_state);
>  }
> @@ -1731,7 +1707,7 @@ int drm_atomic_helper_setup_commit(struct
> drm_atomic_state *state, kref_init(&commit->ref);
>   commit->crtc = crtc;
> 
> - state->crtcs[i].commit = com

[Intel-gfx] [PATCH igt] igt/gem_flink_race: Limit name subtest to 5s

[Chris Wilson]

At present, we try to do 1,000,000 cycles, which may be a reasonable
estimate for detecting the race, takes 6 minutes in practice on bxt on a
good day (as it spends more time doing rpm suspend/resume than actual work,
and that accounts for more of the relative difference in performance
between bxt and big core than the difference in clocks+ipc).

An ideal solution would be to have a data-race detector in the kernel
combined with a short test to exercise the different paths. Lacking the
DRD, use a shorter test anyway. 5s is chosen simply on the basis that
the other race subtest is also run over a 5s interval.

Signed-off-by: Chris Wilson 
---
 tests/gem_flink_race.c | 35 +--
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/tests/gem_flink_race.c b/tests/gem_flink_race.c
index 30e33f65..baee285f 100644
--- a/tests/gem_flink_race.c
+++ b/tests/gem_flink_race.c
@@ -49,8 +49,14 @@ IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close 
races.");
 volatile int pls_die = 0;
 int fd;
 
+struct flink_name {
+   pthread_t thread;
+   unsigned long count;
+};
+
 static void *thread_fn_flink_name(void *p)
 {
+   struct flink_name *t = p;
struct drm_gem_open open_struct;
int ret;
 
@@ -65,6 +71,7 @@ static void *thread_fn_flink_name(void *p)
igt_assert(name == 1);
 
gem_close(fd, open_struct.handle);
+   t->count++;
} else
igt_assert(errno == ENOENT);
}
@@ -72,42 +79,50 @@ static void *thread_fn_flink_name(void *p)
return (void *)0;
 }
 
-static void test_flink_name(void)
+static void test_flink_name(int timeout)
 {
-   pthread_t *threads;
+   struct flink_name *threads;
int r, i, num_threads;
+   unsigned long count;
+   char buf[256];
void *status;
+   int len;
 
num_threads = sysconf(_SC_NPROCESSORS_ONLN) - 1;
if (!num_threads)
num_threads = 1;
 
-   threads = calloc(num_threads, sizeof(pthread_t));
+   threads = calloc(num_threads, sizeof(*threads));
 
fd = drm_open_driver(DRIVER_INTEL);
 
for (i = 0; i < num_threads; i++) {
-   r = pthread_create(&threads[i], NULL,
-  thread_fn_flink_name, NULL);
+   r = pthread_create(&threads[i].thread, NULL,
+  thread_fn_flink_name, &threads[i]);
igt_assert_eq(r, 0);
}
 
-   for (i = 0; i < 100; i++) {
+   count = 0;
+   igt_until_timeout(timeout) {
uint32_t handle;
 
handle = gem_create(fd, 4096);
-
gem_flink(fd, handle);
-
gem_close(fd, handle);
+
+   count++;
}
 
pls_die = 1;
 
+   len = snprintf(buf, sizeof(buf), "Completed %lu cycles with [", count);
for (i = 0;  i < num_threads; i++) {
-   pthread_join(threads[i], &status);
+   pthread_join(threads[i].thread, &status);
igt_assert(status == 0);
+   len += snprintf(buf + len, sizeof(buf) - len, "%lu, ", 
threads[i].count);
}
+   snprintf(buf + len - 2, sizeof(buf) - len + 2, "] races");
+   igt_info("%s\n", buf);
 
close(fd);
 }
@@ -186,7 +201,7 @@ igt_main
igt_skip_on_simulation();
 
igt_subtest("flink_name")
-   test_flink_name();
+   test_flink_name(5);
 
igt_subtest("flink_close")
test_flink_close();
-- 
2.14.1

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Re: [Intel-gfx] [PATCH i-g-t] tests/chamelium: Let the Chamelium itself wait for a stable video input

[Paul Kocialkowski]

On Tue, 2017-08-29 at 15:08 +0300, Paul Kocialkowski wrote:
> On Mon, 2017-08-28 at 17:55 +0300, Paul Kocialkowski wrote:
> > Before capturing video, the Chamelium will always wait for the video
> > input to be stable (and perform the FSM if it was not). This means
> > that
> > there is no need to explicitly do it beforehand.
> > 
> > When the receiver needs to be reset, the call will result in a
> > timeout,
> > after which the follow-up call to capture the video will perform the
> > FSM
> > that resets it. Skipping the explicit wait for video input stable
> > allows
> > the Chamelium to perform the FSM directly, which saves valuable
> > time.
> > 
> > Removing the associated call does not negatively impact the
> > execution
> > of
> > the CRC and frame comparison tests either.
> 
> I got an email from the mailer daemon indicating that this patch could
> not be delivered to Lyude.
> 
> Lyude: did you receive the patch or should I resend it?

Either way, it's up at: https://patchwork.freedesktop.org/series/29432/

> > Signed-off-by: Paul Kocialkowski 
> > ---
> >  tests/chamelium.c | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> > diff --git a/tests/chamelium.c b/tests/chamelium.c
> > index 484bb537..e3d81357 100644
> > --- a/tests/chamelium.c
> > +++ b/tests/chamelium.c
> > @@ -474,9 +474,6 @@ enable_output(data_t *data,
> > if (chamelium_port_get_type(port) ==
> > DRM_MODE_CONNECTOR_VGA)
> > usleep(25);
> >  
> > -   chamelium_port_wait_video_input_stable(data->chamelium,
> > port,
> > -  HOTPLUG_TIMEOUT);
> > -
> > drmModeFreeConnector(connector);
> >  }
> >  
-- 
Paul Kocialkowski 
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo, Finland
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[Intel-gfx] [PATCH i-g-t] tools: Add intel_vbt_defs.h to Makefile.sources

[Arkadiusz Hiler]

So is will be picked up for the distributable tarball.

Fixes: 09f35ea4dc06 ("tools/intel_vbt_decode: start migrating to kernel 
intel_vbt_defs.h")
Signed-off-by: Arkadiusz Hiler 
---
 tools/Makefile.sources | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 6d9a6ace..c49ab8f0 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -50,6 +50,7 @@ intel_reg_SOURCES =   \
 
 intel_vbt_decode_SOURCES = \
intel_vbt_decode.c  \
+   intel_vbt_defs.h \
intel_bios.h
 
 intel_l3_parity_SOURCES =  \
-- 
2.13.5

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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_flink_race: Limit name subtest to 5s

[Patchwork]

== Series Details ==

Series: igt/gem_flink_race: Limit name subtest to 5s
URL   : https://patchwork.freedesktop.org/series/29528/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
bf45d253648250fc402eee02237366c8882b2053 igt: Add gem_close

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:560s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:518s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:514s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:614s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:448s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:599s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:599s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:442s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:487s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:558s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:413s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_122/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add interface to reserve fence registers for vGPU

[Patchwork]

== Series Details ==

Series: drm/i915: Add interface to reserve fence registers for vGPU
URL   : https://patchwork.freedesktop.org/series/29523/
State : failure

== Summary ==

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-B-planes:
pass   -> SKIP   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw)
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)

shard-hswtotal:2230 pass:1228 dwarn:0   dfail:0   fail:19  skip:983 
time:9597s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5535/shards.html
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Re: [Intel-gfx] [PATCH i-g-t] tools: Add intel_vbt_defs.h to Makefile.sources

[Arkadiusz Hiler]

On Wed, Aug 30, 2017 at 01:30:16PM +0300, Arkadiusz Hiler wrote:
> So is will be picked up for the distributable tarball.
> 
> Fixes: 09f35ea4dc06 ("tools/intel_vbt_decode: start migrating to kernel 
> intel_vbt_defs.h")
> Signed-off-by: Arkadiusz Hiler 

Pushed with Jani's ack from the IRC to stop post-merge CI failing on
distcheck.

-- 
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Arek
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Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Kamble, Sagar A]

On 8/30/2017 3:09 PM, Daniel Vetter wrote:

One more on top of Lionel's coments.

On Mon, Aug 28, 2017 at 03:23:03PM +0530, Sagar Arun Kamble wrote:

+int main(int argc, char **argv)
+{
+   bool ret;
+   int option;
+   int platform;
+
+   if (argc != 3) {
+   printf("Usage: \n./dapc  \
+   \nPlatform: 0-HSW, 1-BDW, 2-SKL\n\
+   \nTest_mode:\n\
+   \t0 - RCS OA mode\n\
+   \t1 - RCS TS mode\n\
+   \t2 - RCS TS+MMIO mode\n\
+   \t3 - RCS OA+TS+MMIO mode\n\
+   \t4 - Periodic OA mode\n");
+   return 0;
+   }
+
+   ret = initialize();
+   if (!ret)
+   return -1;
+
+   platform = atoi(argv[1]);
+   switch (platform) {
+   case 0:
+   arch = ARCH_HSW;
+   break;
+   case 1:
+   arch = ARCH_BDW;
+   break;
+   case 2:
+   arch = ARCH_SKL;
+   break;
+   default:
+   fprintf(stderr, "Invalid platform:%d\n", platform);
+   return -1;
+   }
+
+   option = atoi(argv[2]);

Please convert this into a proper igt testcase that enumrates subtests
like all the others. Otherwise CI won't pick it up, which makes this
wasted effort. This means using igt_main, igt_subtest, igt_fixture and all
the various igt_assert/require macros we have to check results.

Also dapc is not a good testcase name, needs some proper prefixing.
-Daniel

Yes. Will update the testcase. Thank you Daniel.



+   switch (option) {
+   case 0:
+   test_perf_dapc_rcs_oa();
+   break;
+   case 1:
+   test_perf_dapc_rcs_ts();
+   break;
+   case 2:
+   test_perf_dapc_rcs_ts_mmio();
+   break;
+   case 3:
+   test_perf_dapc_rcs_oa_ts_mmio();
+   break;
+   case 4:
+   test_perf_dapc_periodic_oa();
+   break;
+   default:
+   fprintf(stderr, "Invalid Option:%d\n", option);
+   return -1;
+   }
+
+   return 0;
+}
--
1.9.1

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT

[Joonas Lahtinen]

On Wed, 2017-08-23 at 11:20 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-23 11:05:18)
> > On Tue, 2017-08-22 at 12:05 +0100, Chris Wilson wrote:
> > > By using drm_gem_flink/drm_gem_open on an object using the same fd, it
> > > is possible for a client to create multiple handles pointing to the same
> > > object (tied to the same contexts and VMA), as exemplified by
> > > igt::gem_handle_to_libdrm_bo(). Since this duplication has been possible
> > > since forever, we cannot assume that the handle:(fpriv, object) is
> > > unique and so must handle the multiple users of a single VMA.
> > > 
> > > Testcase: igt/gem_close
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
> > > Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> > > Signed-off-by: Chris Wilson 
> > > Cc: Tvrtko Ursulin 
> > > Cc: Joonas Lahtinen 
> > 
> > 
> > 
> > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > @@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
> > >   goto err_obj;
> > >   }
> > >  
> > > + vma->open_count++;
> > >   list_add(&lut->obj_link, &obj->lut_list);
> > 
> > This code maybe should be in i915_gem.c as "i915_gem_object_add_lut" or
> > something.
> 
> I disagree. It's very much tied to being an execbuf only interaction,
> that obj/ctx/handle.

So how are we going to proceed here? The current proposed solution is
very unintuitive, one counter spread over multiple files.

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [RFCv5 2/2] drm/i915: Introduce private PAT management

[Joonas Lahtinen]

On Tue, 2017-08-29 at 18:19 +, Wang, Zhi A wrote:
> I see. 
> 
> For 1) I can fix it in the next RFC.

Please send a separate bugfix for this so we can proceed to test and
merge immediately.

Regards, Joonas

> For 2) I can find some VPG guys to ask for the details.
> 
> Thanks,
> Zhi.
> 
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] 
> Sent: Tuesday, August 29, 2017 9:14 PM
> To: Wang, Zhi A ; Joonas Lahtinen 
> ; intel-gfx@lists.freedesktop.org; 
> intel-gvt-...@lists.freedesktop.org
> Cc: zhen...@linux.intel.com; Widawsky, Benjamin 
> ; Vivi, Rodrigo 
> Subject: RE: [RFCv5 2/2] drm/i915: Introduce private PAT management
> 
> Quoting Wang, Zhi A (2017-08-29 18:54:51)
> > Another finding during the re-factoring are:
> > 
> > a)It looks like that the PPAT_CACHE_INDEX on BDW/SKL is mapped to:
> > GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0);
> > 
> > But the PPAT_CACHE_INDEX on CNL is mapped to GEN8_PPAT_LLCELLC | 
> > GEN8_PPAT_AGE(0);
> > 
> > GEN8_PPAT_WB is missing here and by default the cache attribute is UC.
> > 
> > Is this set intentionally?
> 
> That sounds like a nasty little bug.
> 
> > b) Looks like all the ages of PPAT in windows driver is AGE(3) because of 
> > some performance gains, is there any reason that i915 has to set it to 
> > AGE(0)?
> 
> Nope, it's never been rigorously tested. On occasion, we've swapped it around 
> (at least for the older gen) and never found a significant difference; I 
> haven't even heard if anyone has tried such experiments on gen8+. Off the top 
> of my head, the age should only matter when you have PTE with different ages 
> (unless there's some automatic clock algorithm tracking the age on each page 
> in a shadow, the challenge being then when you decide to refresh the age from 
> the PTE.) -Chris
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

[Michał Winiarski]

On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote:
> Added the missing IGT_TEST_DESCRIPTION and some subtest
> descriptions.
> 
> Signed-off-by: Vinay Belgaumkar 
> ---
>  tests/gem_flink_basic.c | 36 
>  1 file changed, 36 insertions(+)
> 
> diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
> index 26ae7d6..8761e0d 100644
> --- a/tests/gem_flink_basic.c
> +++ b/tests/gem_flink_basic.c
> @@ -36,6 +36,8 @@
>  #include 
>  #include "drm.h"
>  
> +IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by 
> name");
> +
>  static void
>  test_flink(int fd)
>  {
> @@ -155,14 +157,48 @@ igt_main
>   igt_fixture
>   fd = drm_open_driver(DRIVER_INTEL);
>  
> + /* basic:
> + This subtest creates a gem object, and then creates
> + a flink. It tests that we can gain access to the gem
> + object using the flink name.
> +
> + Test fails if flink creation/open fails.
> + **/

Please use kernel coding style.
This is not the format we're using for multiline comments.

/*
 *
 */
^^^ This is the format we're using.

And on the documentation itself, let's take a quote from the kernel coding
style:
"Comments are good, but there is also a danger of over-commenting.  NEVER
try to explain HOW your code works in a comment: it's much better to
write the code so that the **working** is obvious, and it's a waste of
time to explain badly written code."

Now, let's try to match the tests with the comments:
/* This subtest creates a gem object */ 
ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
igt_assert_eq(ret, 0);

/* and then creates a flink */
flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
igt_assert_eq(ret, 0);

/* It tests that we can gain access to the gem object using the flink
 * name
 */
Well... not really, we're not accessing the object in any way.

/* Test fails if flink creation/open fails. */
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, &open_struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);

>   igt_subtest("basic")
>   test_flink(fd);
> +
> + /* double-flink:
> + This test checks if it is possible to create 2 flinks
> + for the same gem object.
> +
> + Test fails if 2 flink objects cannot be created.
> + **/

/* This test checks if it is possible to create 2 flinks for the same
 * gem object
 */

flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
igt_assert_eq(ret, 0);

flink2.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink2);
igt_assert_eq(ret, 0);

/* Test fails if 2 flink objects cannot be created. */
Well - this is handled by the asserts above.
You ignored this assumption in your description for some reason though:
igt_assert(flink2.name == flink.name);

>   igt_subtest("double-flink")
>   test_double_flink(fd);
> +
> + /* bad-flink:
> + Use an invalid flink handle.
> +
> + DRM_IOCTL_GEM_FLINK ioctl call should return failure.
> + **/

ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
igt_assert(ret == -1 && errno == ENOENT);

There is also an igt_info message:
igt_info("Testing error return on bad flink ioctl.\n");


>   igt_subtest("bad-flink")
>   test_bad_flink(fd);
> +
> + /* bad-open:
> + Try to use an invalid flink name.
> +
> + DRM_IOCTL_GEM_FLINK ioctl call should return failure.
> + **/

open_struct.name = 0x10101010;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, &open_struct);

igt_assert(ret == -1 && errno == ENOENT);

Same as for bad flink:
igt_info("Testing error return on bad open ioctl.\n");

>   igt_subtest("bad-open")
>   test_bad_open(fd);
> +
> + /* flink-lifetime:
> + Check if a flink name can be used even after the drm
> + fd used to create it is closed.
> +
> + Flink name should remain valid until the gem object
> + it points to has not been freed.
> + **/

That's better, however...
Why wasn't the object freed when we closed the drm fd (fd2) used to create it?
(hint, it wasn't freed because we're doing OPEN using a different fd before
closing fd2, and that changes the lifetime of an object since we're bumping the
refcount this way, which perhaps could use a comment, not in the description
but in the testcase itself).
As for a one-line description, perhaps something more general would work better?
Check if a flink name is valid for the whole duration of underlying gem object
lifetime.

Overall - do you believe, that 1:1 from C to English translation is not a
perfect example of "over-commenting"? Do we really need to take an approach
where we're documenting even the simp

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Joonas Lahtinen]

On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> Driver’s CPU access to GTT is via the GTTMMADR BAR.
> 
> The current HW implementation of that BAR is to only
> support <= DW (and maybe QW) writes—not 16/32/64B writes
> that could occur with WC and/or SSE/AVX moves.
> 
> GTTMMADR must be marked uncacheable (UC).
> Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
> 
> v2: Get clarification on the reasons and spec is getting
> updated to reflect it now.
> 
> Cc: Joonas Lahtinen 
> Suggested-by: Ben Widawsky 
> Signed-off-by: Rodrigo Vivi 

Rodrigo, can you double-check how this interacts with the patch from
Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.

If that doesn't help with the problem, this is;

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
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Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Kamble, Sagar A]

Thanks Lionel for the review. Will revamp the testcase.


Thanks

Sagar

On 8/29/2017 2:21 PM, Lionel Landwerlin wrote:

Hi Sagar,

Thanks for writing this test. It looks promising but there are a few 
issues that needs to be addressed for this to run in CI.

Please have a look at the comments below.

Thanks!

On 28/08/17 10:53, Sagar Arun Kamble wrote:

This test verifies different i915 perf sampling options for fields like
PID, CTX ID, Timestamp, OA Report, TAG, MMIO.

Cc: Lionel Landwerlin 
Signed-off-by: Sourab Gupta 
Signed-off-by: Sagar Arun Kamble 
---
  tests/Makefile.sources |1 +
  tests/dapc.c   | 1017 


  2 files changed, 1018 insertions(+)
  create mode 100644 tests/dapc.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..61feb0d 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -26,6 +26,7 @@ TESTS_progs = \
  core_getversion \
  core_prop_blob \
  core_setmaster_vs_auth \
+dapc \
  debugfs_test \
  drm_import_export \
  drm_mm \
diff --git a/tests/dapc.c b/tests/dapc.c
new file mode 100644
index 000..f49b1cd
--- /dev/null
+++ b/tests/dapc.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a
+ * copy of this software and associated documentation files (the 
"Software"),
+ * to deal in the Software without restriction, including without 
limitation
+ * the rights to use, copy, modify, merge, publish, distribute, 
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom 
the

+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including 
the next
+ * paragraph) shall be included in all copies or substantial 
portions of the

+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES 
OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 
OTHER DEALINGS

+ * IN THE SOFTWARE.
+ *
+ * dapc: Driver Assisted Performance Capture
+ * This tests the i915 perf functionality to sample various 
metrics by
+ * associating with the CS stream or just standalone periodic OA 
samples.
+ * Verifies fields like PID, CTX ID, Timestamp, OA Report, MMIO, 
Tags are

+ * generated properly for each sample.
+ *
+ * Authors:
+ *   Sourab Gupta 
+ *   Sagar Arun Kamble 
+ *
+ */
+#define _GNU_SOURCE
+#include "xf86drm.h"
+#include "i915_drm.h"
+#include "igt_core.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+


To be able to run this test in the continuous integration system, we 
need it to be autonomous.
The following macro requires user interaction. Unfortunately that 
won't work.
Please look at the other tests to create subtests and make sure we can 
run this in the CI.

Thanks!

Yes. Will update this.



+#define COLLECT_DATA { \
+printf("(%s) Collecting data. ", __func__); \
+printf("Press enter to continue...\n"); \
+getc(stdin); \
+}
+


It would be good to test stream configurations with different sizes.
For example only Pid, or Tag & Pid or SourceInfo & ctx ID & Tag, etc...
And verify that we get reports with appropriate sizes.

Sure. Will try to add testcases for those combinations too.


+#define OA_SAMPLE_SIZE_MAX(8 +/* drm_i915_perf_record_header 
*/ \

+ 8 +/* source info */ \
+ 8 +/* ctx ID */ \
+ 8 +/* Pid */ \
+ 8 +/* Tag */ \
+ 256) /* raw OA counter snapshot */
+
+#define TS_SAMPLE_SIZE_MAX(8 +/* drm_i915_perf_record_header 
*/ \

+ 8 +/* ctx ID */ \
+ 8 +/* Pid */ \
+ 8 +/* Tag */ \
+ 8)/* Timestamp */ \
+
+#define TS_MMIO_SAMPLE_SIZE_MAX(8 +   /* 
drm_i915_perf_record_header */ \

+ 8 +   /* ctx ID */ \
+ 8 +   /* Pid */ \
+ 8 +   /* Tag */ \
+ 8 +   /* Timestamp */ \
+ 4*I915_PERF_MMIO_NUM_MAX)/* MMIO reg */
+
+#define OA_TS_MMIO_SAMPLE_SIZE_MAX (8 +   /* 
drm_i915_perf_record_header */ \

+8 +   /* source info */ \
+8 +   /* ctx ID */ \
+8 +   /* Pid */ \
+8 +   /* Tag */ \
+8 +   /* Timestamp */ \
+(4*I915_PERF_MMIO_NUM_MAX) + /* MMIO 

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Pull wait-for-idle into i915_gem_switch_to_kernel_context()

[Mika Kuoppala]

Chris Wilson  writes:

> All callers do want a synchronous switch to the kernel context, that is
> by the time the call returns, the GPU has evicted all user contexts and
> now has the kernel context pinned. As all callers want this behaviour,
> refactor the common wait-for-idle into the switch.
>
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_gem.c |  6 --
>  drivers/gpu/drm/i915/i915_gem_context.c |  4 +++-
>  drivers/gpu/drm/i915/i915_gem_evict.c   | 14 +-
>  3 files changed, 4 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 890fe2802973..18ba74be286c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4564,12 +4564,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
>   if (ret)
>   goto err_unlock;
>  
> - ret = i915_gem_wait_for_idle(dev_priv,
> -  I915_WAIT_INTERRUPTIBLE |
> -  I915_WAIT_LOCKED);
> - if (ret)
> - goto err_unlock;
> -
>   assert_kernel_context_is_current(dev_priv);
>   i915_gem_contexts_lost(dev_priv);
>   mutex_unlock(&dev->struct_mutex);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 58a2a44f88bd..f70b05e682ac 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -924,7 +924,9 @@ int i915_gem_switch_to_kernel_context(struct 
> drm_i915_private *dev_priv)
>   return ret;
>   }
>  
> - return 0;
> + return i915_gem_wait_for_idle(dev_priv,
> +  I915_WAIT_INTERRUPTIBLE |
> +  I915_WAIT_LOCKED);

This wont apply due to special case EIO handling the previous
suspend hardening patches introduced. Please explain why the EIO
needs to passthrough and not return.

-Mika

>  }
>  
>  static bool client_is_banned(struct drm_i915_file_private *file_priv)
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c 
> b/drivers/gpu/drm/i915/i915_gem_evict.c
> index 4df039ef2ce3..5cf73ad4801a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -52,25 +52,13 @@ static bool ggtt_is_idle(struct drm_i915_private 
> *dev_priv)
>  
>  static int ggtt_flush(struct drm_i915_private *i915)
>  {
> - int err;
> -
>   /* Not everything in the GGTT is tracked via vma (otherwise we
>* could evict as required with minimal stalling) so we are forced
>* to idle the GPU and explicitly retire outstanding requests in
>* the hopes that we can then remove contexts and the like only
>* bound by their active reference.
>*/
> - err = i915_gem_switch_to_kernel_context(i915);
> - if (err)
> - return err;
> -
> - err = i915_gem_wait_for_idle(i915,
> -  I915_WAIT_INTERRUPTIBLE |
> -  I915_WAIT_LOCKED);
> - if (err)
> - return err;
> -
> - return 0;
> + return i915_gem_switch_to_kernel_context(i915);
>  }
>  
>  static bool
> -- 
> 2.14.1
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Chris Wilson]

Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > 
> > The current HW implementation of that BAR is to only
> > support <= DW (and maybe QW) writes—not 16/32/64B writes
> > that could occur with WC and/or SSE/AVX moves.
> > 
> > GTTMMADR must be marked uncacheable (UC).
> > Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
> > 
> > v2: Get clarification on the reasons and spec is getting
> > updated to reflect it now.
> > 
> > Cc: Joonas Lahtinen 
> > Suggested-by: Ben Widawsky 
> > Signed-off-by: Rodrigo Vivi 
> 
> Rodrigo, can you double-check how this interacts with the patch from
> Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.

Different issue (or should be). The ioremap concerns access through the
PCI BAR, affecting how fast we insert entries into the GGTT (so
establishing new mmaps following frequent runtime pm, loading of new
contexts + rings, as well as the stressful GGTT thrashing). PPAT affects
how the device accesses the physical pages, not the PTE themselves.
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915: Wrap execlist port completion into a function

[Mika Kuoppala]

When execlist entry is processed, we nullify the corresponding port.
Also when we reset the gpu we need to nullify ports. Introduce function
to do this common operation and also use it for cancellation for all ports,
in error handling and recovery paths.

Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c| 11 ++-
 drivers/gpu/drm/i915/i915_guc_submission.c | 10 +-
 drivers/gpu/drm/i915/intel_lrc.c   | 18 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.h| 23 +++
 4 files changed, 37 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6dffab14a3e3..34387abda65b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3046,18 +3046,11 @@ static void engine_set_wedged(struct intel_engine_cs 
*engine)
 */
 
if (i915.enable_execlists) {
-   struct execlist_port *port = engine->execlist.port;
+   struct intel_engine_execlist * const el = &engine->execlist;
unsigned long flags;
-   unsigned int n;
 
spin_lock_irqsave(&engine->timeline->lock, flags);
-
-   for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
-   i915_gem_request_put(port_request(&port[n]));
-   memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
-   engine->execlist.queue = RB_ROOT;
-   engine->execlist.first = NULL;
-
+   execlist_cancel_port_requests(el);
spin_unlock_irqrestore(&engine->timeline->lock, flags);
 
/* The port is checked prior to scheduling a tasklet, but
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index f95defe18885..1056d45d2ac9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -714,20 +714,20 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
 static void i915_guc_irq_handler(unsigned long data)
 {
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
-   struct execlist_port *port = engine->execlist.port;
+   struct intel_engine_execlist * const el = &engine->execlist;
+   struct execlist_port *port = el->port;
struct drm_i915_gem_request *rq;
bool submit;
 
do {
-   rq = port_request(&port[0]);
+   rq = port_request(port);
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
 
-   port[0] = port[1];
-   memset(&port[1], 0, sizeof(port[1]));
+   execlist_port_complete(el);
 
-   rq = port_request(&port[0]);
+   rq = port_request(port);
}
 
submit = false;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2964e7c0a873..7f154601c83d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -412,8 +412,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 */
last->tail = last->wa_tail;
 
-   GEM_BUG_ON(port_isset(&port[1]));
-
/* Hardware submission is through 2 ports. Conceptually each port
 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
 * static for a context, and unique to each, so we only execute
@@ -485,6 +483,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
if (submit)
port_assign(port, last);
port++;
+
+   GEM_BUG_ON(port_isset(port));
}
 
INIT_LIST_HEAD(&rq->priotree.link);
@@ -609,8 +609,7 @@ static void intel_lrc_irq_handler(unsigned long data)
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
 
-   port[0] = port[1];
-   memset(&port[1], 0, sizeof(port[1]));
+   execlist_port_complete(el);
} else {
port_set(port, port_pack(rq, count));
}
@@ -1329,9 +1328,9 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
 static void reset_common_ring(struct intel_engine_cs *engine,
  struct drm_i915_gem_request *request)
 {
-   struct execlist_port *port = engine->execlist.port;
+   struct intel_engine_execlist * const el = &engine->execlist;
+   struct execlist_port *port = el->port;
struct intel_context *ce;
-   unsigned i

[Intel-gfx] [PATCH 1/2] drm/i915: Make own struct for execlist items

[Mika Kuoppala]

Engine's execlist related items have been increasing to
a point where a separate struct is warranted. Carve execlist
specific items to a dedicated struct to add clarity.

v2: add kerneldoc and fix whitespace (Joonas, Chris)

Suggested-by: Chris Wilson 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Mika Kuoppala 
Acked-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  6 +-
 drivers/gpu/drm/i915/i915_gem.c| 16 +++---
 drivers/gpu/drm/i915/i915_gpu_error.c  |  4 +-
 drivers/gpu/drm/i915/i915_guc_submission.c | 19 ---
 drivers/gpu/drm/i915/i915_irq.c|  5 +-
 drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++--
 drivers/gpu/drm/i915/intel_lrc.c   | 64 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.h| 88 +++---
 8 files changed, 134 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 48572b157222..514344e28399 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3341,10 +3341,10 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
}
 
rcu_read_lock();
-   for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); 
idx++) {
+   for (idx = 0; idx < ARRAY_SIZE(engine->execlist.port); 
idx++) {
unsigned int count;
 
-   rq = port_unpack(&engine->execlist_port[idx],
+   rq = port_unpack(&engine->execlist.port[idx],
 &count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
@@ -3358,7 +3358,7 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
rcu_read_unlock();
 
spin_lock_irq(&engine->timeline->lock);
-   for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+   for (rb = engine->execlist.first; rb; rb = rb_next(rb)) 
{
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4cc08bc518c..6dffab14a3e3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2814,8 +2814,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs 
*engine)
 * Turning off the engine->irq_tasklet until the reset is over
 * prevents the race.
 */
-   tasklet_kill(&engine->irq_tasklet);
-   tasklet_disable(&engine->irq_tasklet);
+   tasklet_kill(&engine->execlist.irq_tasklet);
+   tasklet_disable(&engine->execlist.irq_tasklet);
 
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
@@ -2994,7 +2994,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
 {
-   tasklet_enable(&engine->irq_tasklet);
+   tasklet_enable(&engine->execlist.irq_tasklet);
kthread_unpark(engine->breadcrumbs.signaler);
 }
 
@@ -3046,17 +3046,17 @@ static void engine_set_wedged(struct intel_engine_cs 
*engine)
 */
 
if (i915.enable_execlists) {
-   struct execlist_port *port = engine->execlist_port;
+   struct execlist_port *port = engine->execlist.port;
unsigned long flags;
unsigned int n;
 
spin_lock_irqsave(&engine->timeline->lock, flags);
 
-   for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
+   for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
i915_gem_request_put(port_request(&port[n]));
-   memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
-   engine->execlist_queue = RB_ROOT;
-   engine->execlist_first = NULL;
+   memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
+   engine->execlist.queue = RB_ROOT;
+   engine->execlist.first = NULL;
 
spin_unlock_irqrestore(&engine->timeline->lock, flags);
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ed5a1eb839ad..6114bf79219d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1327,10 +1327,10 @@ static void engine_record_requests(struct 
intel_engine_cs *engine,
 static void error_record_engine_execlists(struct intel_engine_cs *engine,
  struct drm_i915_error_engine *ee)
 {
-   const struct execlist_port *port = engine->execlist_port;
+   const struct execlist_port *port = engine->execlist.port;
unsigned int n;
 
-   for 

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/gem_flink_race: Limit name subtest to 5s

[Patchwork]

== Series Details ==

Series: igt/gem_flink_race: Limit name subtest to 5s
URL   : https://patchwork.freedesktop.org/series/29528/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2230 pass:1229 dwarn:0   dfail:0   fail:19  skip:982 
time:9605s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_122/shards.html
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Wrap execlist port completion into a function

[Chris Wilson]

Quoting Mika Kuoppala (2017-08-30 12:32:11)
> +static inline void
> +execlist_port_complete(struct intel_engine_execlist * const el)
> +{
> +   struct execlist_port * const port = el->port;
> +
> +   port[0] = port[1];
> +   memset(&port[1], 0, sizeof(port[1]));
> +}
> +
> +static inline void
> +execlist_cancel_port_requests(struct intel_engine_execlist * const el)
> +{
> +   unsigned int i;
> +
> +   for (i = 0; i < ARRAY_SIZE(el->port); i++) {
> +   i915_gem_request_put(port_request(&el->port[i]));
> +   execlist_port_complete(el);

No. Cancellation is not defined as completion. Iterating over the ports
and then calling complete that only operates on the first port and
doesn't even take the port as implied by its name is horrible.
Just a patch moving the cancellation to its own function that doesn't
need to be inlined since it is called only on reset is what I want to
see.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Joonas Lahtinen]

On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > > 
> > > The current HW implementation of that BAR is to only
> > > support <= DW (and maybe QW) writes—not 16/32/64B writes
> > > that could occur with WC and/or SSE/AVX moves.
> > > 
> > > GTTMMADR must be marked uncacheable (UC).
> > > Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
> > > 
> > > v2: Get clarification on the reasons and spec is getting
> > > updated to reflect it now.
> > > 
> > > Cc: Joonas Lahtinen 
> > > Suggested-by: Ben Widawsky 
> > > Signed-off-by: Rodrigo Vivi 
> > 
> > Rodrigo, can you double-check how this interacts with the patch from
> > Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.
> 
> Different issue (or should be). The ioremap concerns access through the
> PCI BAR, affecting how fast we insert entries into the GGTT (so
> establishing new mmaps following frequent runtime pm, loading of new
> contexts + rings, as well as the stressful GGTT thrashing). PPAT affects
> how the device accesses the physical pages, not the PTE themselves.

Yes, I know it should be :) But Rodrigo also described pretty random
hangs, IIRC not much was pinpointing to either of the issues. With
these two bugs present, device could be operating without write-back on
certain pages, or could be operating on wrong pages altogether.

I'd just like one round of testing to try to avoid this change if we
can.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Pull wait-for-idle into i915_gem_switch_to_kernel_context()

[Chris Wilson]

Quoting Mika Kuoppala (2017-08-30 12:16:08)
> Chris Wilson  writes:
> 
> > All callers do want a synchronous switch to the kernel context, that is
> > by the time the call returns, the GPU has evicted all user contexts and
> > now has the kernel context pinned. As all callers want this behaviour,
> > refactor the common wait-for-idle into the switch.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c |  6 --
> >  drivers/gpu/drm/i915/i915_gem_context.c |  4 +++-
> >  drivers/gpu/drm/i915/i915_gem_evict.c   | 14 +-
> >  3 files changed, 4 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 890fe2802973..18ba74be286c 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4564,12 +4564,6 @@ int i915_gem_suspend(struct drm_i915_private 
> > *dev_priv)
> >   if (ret)
> >   goto err_unlock;
> >  
> > - ret = i915_gem_wait_for_idle(dev_priv,
> > -  I915_WAIT_INTERRUPTIBLE |
> > -  I915_WAIT_LOCKED);
> > - if (ret)
> > - goto err_unlock;
> > -
> >   assert_kernel_context_is_current(dev_priv);
> >   i915_gem_contexts_lost(dev_priv);
> >   mutex_unlock(&dev->struct_mutex);
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 58a2a44f88bd..f70b05e682ac 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -924,7 +924,9 @@ int i915_gem_switch_to_kernel_context(struct 
> > drm_i915_private *dev_priv)
> >   return ret;
> >   }
> >  
> > - return 0;
> > + return i915_gem_wait_for_idle(dev_priv,
> > +  I915_WAIT_INTERRUPTIBLE |
> > +  I915_WAIT_LOCKED);
> 
> This wont apply due to special case EIO handling the previous
> suspend hardening patches introduced. Please explain why the EIO
> needs to passthrough and not return.

Hmm, hopefully my earlier reply turns up...

But as I was writing up an assert for add_request, I realise that we
know allow set-wedged to be unlocked and so we do not have the strict
control over requests-vs-wedging anymore. The idea still remains, if we
set-wedged as we build the request, we do want to cancel it and report
the -EIO.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Make own struct for execlist items

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Make own struct for execlist items
URL   : https://patchwork.freedesktop.org/series/29533/
State : success

== Summary ==

Series 29533v1 series starting with [1/2] drm/i915: Make own struct for 
execlist items
https://patchwork.freedesktop.org/api/1.0/series/29533/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:457s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:550s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:252s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:531s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:430s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:443s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:431s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:598s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:604s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:523s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:447s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:485s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:410s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
8e6eed00e9b5 drm/i915: Wrap execlist port completion into a function
ddebf7ee3b51 drm/i915: Make own struct for execlist items

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5536/
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT

[Chris Wilson]

Quoting Joonas Lahtinen (2017-08-30 12:07:47)
> On Wed, 2017-08-23 at 11:20 +0100, Chris Wilson wrote:
> > Quoting Joonas Lahtinen (2017-08-23 11:05:18)
> > > On Tue, 2017-08-22 at 12:05 +0100, Chris Wilson wrote:
> > > > By using drm_gem_flink/drm_gem_open on an object using the same fd, it
> > > > is possible for a client to create multiple handles pointing to the same
> > > > object (tied to the same contexts and VMA), as exemplified by
> > > > igt::gem_handle_to_libdrm_bo(). Since this duplication has been possible
> > > > since forever, we cannot assume that the handle:(fpriv, object) is
> > > > unique and so must handle the multiple users of a single VMA.
> > > > 
> > > > Testcase: igt/gem_close
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
> > > > Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> > > > Signed-off-by: Chris Wilson 
> > > > Cc: Tvrtko Ursulin 
> > > > Cc: Joonas Lahtinen 
> > > 
> > > 
> > > 
> > > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > > @@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer 
> > > > *eb)
> > > >   goto err_obj;
> > > >   }
> > > >  
> > > > + vma->open_count++;
> > > >   list_add(&lut->obj_link, &obj->lut_list);
> > > 
> > > This code maybe should be in i915_gem.c as "i915_gem_object_add_lut" or
> > > something.
> > 
> > I disagree. It's very much tied to being an execbuf only interaction,
> > that obj/ctx/handle.
> 
> So how are we going to proceed here? The current proposed solution is
> very unintuitive, one counter spread over multiple files.

The table is very much for the entertainment of execbuf (and if you
squint hard, ok not hard at all, so is the rest of GEM), if you were to
push hard that's where I suggest to shove it.

But I'm not yet seeing the issue with one side being clear where the
user opens the vma and the other where it is closed by the user.
-Chris
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[Intel-gfx] [PATCH 3/5] drm/atomic: Move drm_crtc_commit to drm_crtc_state, v2.

[Maarten Lankhorst]

Most code only cares about the current commit or previous commit.
Fortuantely we already have a place to track those. Move it to
drm_crtc_state where it belongs. :)

The per-crtc commit_list is kept for places where we have to look
deeper than the current or previous commit for checking whether to stall
on unpin. This is used in drm_atomic_helper_setup_commit and
intel_has_pending_fb_unpin.

Changes since v1:
- Update kerneldoc for drm_crtc.commit_list. (danvet)

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_atomic.c|  7 ---
 drivers/gpu/drm/drm_atomic_helper.c | 92 ++---
 include/drm/drm_atomic.h|  1 -
 include/drm/drm_crtc.h  | 23 --
 4 files changed, 42 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 2fd383d7253a..2cce48f203e0 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
crtc->funcs->atomic_destroy_state(crtc,
  state->crtcs[i].state);
 
-   if (state->crtcs[i].commit) {
-   kfree(state->crtcs[i].commit->event);
-   state->crtcs[i].commit->event = NULL;
-   drm_crtc_commit_put(state->crtcs[i].commit);
-   }
-
-   state->crtcs[i].commit = NULL;
state->crtcs[i].ptr = NULL;
state->crtcs[i].state = NULL;
}
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 11d0e94a2181..8ccb8b6536c0 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
 void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
  struct drm_atomic_state *old_state)
 {
-   struct drm_crtc_state *unused;
+   struct drm_crtc_state *new_crtc_state;
struct drm_crtc *crtc;
int i;
 
-   for_each_new_crtc_in_state(old_state, crtc, unused, i) {
-   struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
+   for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
+   struct drm_crtc_commit *commit = new_crtc_state->commit;
int ret;
 
if (!commit)
@@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device 
*dev,
 {
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
-   struct drm_crtc_commit *commit;
struct drm_plane *__plane, *plane = NULL;
struct drm_plane_state *__plane_state, *plane_state = NULL;
const struct drm_plane_helper_funcs *funcs;
-   int i, j, n_planes = 0;
+   int i, n_planes = 0;
 
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
if (drm_atomic_crtc_needs_modeset(crtc_state))
@@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device 
*dev,
return -EINVAL;
 
/*
-* Don't do an async update if there is an outstanding commit modifying
+* TODO: Don't do an async update if there is an outstanding commit 
modifying
 * the plane.  This prevents our async update's changes from getting
 * overridden by a previous synchronous update's state.
 */
-   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
-   if (plane->crtc != crtc)
-   continue;
-
-   spin_lock(&crtc->commit_lock);
-   commit = list_first_entry_or_null(&crtc->commit_list,
- struct drm_crtc_commit,
- commit_entry);
-   if (!commit) {
-   spin_unlock(&crtc->commit_lock);
-   continue;
-   }
-   spin_unlock(&crtc->commit_lock);
-
-   if (!crtc->state->state)
-   continue;
-
-   for_each_plane_in_state(crtc->state->state, __plane,
-   __plane_state, j) {
-   if (__plane == plane)
-   return -EINVAL;
-   }
-   }
 
return funcs->atomic_async_check(plane, plane_state);
 }
@@ -1731,7 +1707,7 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
kref_init(&commit->ref);
commit->crtc = crtc;
 
-   state->crtcs[i].commit = commit;
+   new_crtc_state->commit = commit;
 
ret = stall_checks(crtc, nonblock);
if (ret)
@@ -1769,22 +1745,6 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
 }
 EXPORT_SYMBOL(drm_atomic_helpe

[Intel-gfx] [PATCH 2/5] drm/atomic: Remove waits in drm_atomic_helper_commit_cleanup_done

[Maarten Lankhorst]

When commit synchronization through drm_crtc_commit was first
introduced, we tried to solve the problem of the flip_done
needing a reference count by blocking in cleanup_done.

This has been changed by commit 24835e442f28 ("drm: reference count
event->completion") which made the waits here no longer needed.

Signed-off-by: Maarten Lankhorst 
Suggested-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_atomic_helper.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 4e53aae9a1fb..11d0e94a2181 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1885,7 +1885,6 @@ void drm_atomic_helper_commit_cleanup_done(struct 
drm_atomic_state *old_state)
struct drm_crtc_state *new_crtc_state;
struct drm_crtc_commit *commit;
int i;
-   long ret;
 
for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
commit = old_state->crtcs[i].commit;
@@ -1895,22 +1894,6 @@ void drm_atomic_helper_commit_cleanup_done(struct 
drm_atomic_state *old_state)
complete_all(&commit->cleanup_done);
WARN_ON(!try_wait_for_completion(&commit->hw_done));
 
-   /* commit_list borrows our reference, need to remove before we
-* clean up our drm_atomic_state. But only after it actually
-* completed, otherwise subsequent commits won't stall 
properly. */
-   if (try_wait_for_completion(&commit->flip_done))
-   goto del_commit;
-
-   /* We must wait for the vblank event to signal our completion
-* before releasing our reference, since the vblank work does
-* not hold a reference of its own. */
-   ret = wait_for_completion_timeout(&commit->flip_done,
- 10*HZ);
-   if (ret == 0)
-   DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
- crtc->base.id, crtc->name);
-
-del_commit:
spin_lock(&crtc->commit_lock);
list_del(&commit->commit_entry);
spin_unlock(&crtc->commit_lock);
-- 
2.11.0

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[Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Maarten Lankhorst]

Currently we neatly track the crtc state, but forget to look at
plane/connector state.

When doing a nonblocking modeset, immediately followed by a setprop
before the modeset completes, the setprop will see the modesets new
state as the old state and free it.

This has to be solved by waiting for hw_done on the connector, even
if it's not assigned to a crtc. When a connector is unbound we take
the last crtc commit, and when it stays unbound we create a new
fake crtc commit for that gets signaled on hw_done for all the
planes/connectors.

We wait for it the same way as we do for crtc's, which will make
sure we never run into a use-after-free situation.

Changes since v1:
- Only create a single disable commit. (danvet)
- Fix leak in intel_legacy_cursor_update.

Signed-off-by: Maarten Lankhorst 
Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
Cc: Laurent Pinchart 
---
 drivers/gpu/drm/drm_atomic.c |   4 +
 drivers/gpu/drm/drm_atomic_helper.c  | 156 +--
 drivers/gpu/drm/i915/intel_display.c |   2 +
 include/drm/drm_atomic.h |  12 +++
 include/drm/drm_connector.h  |   7 ++
 include/drm/drm_plane.h  |   7 ++
 6 files changed, 182 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 2cce48f203e0..75f5f74de9bf 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
}
state->num_private_objs = 0;
 
+   if (state->fake_commit) {
+   drm_crtc_commit_put(state->fake_commit);
+   state->fake_commit = NULL;
+   }
 }
 EXPORT_SYMBOL(drm_atomic_state_default_clear);
 
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 8ccb8b6536c0..034f563fb130 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion 
*completion)
drm_crtc_commit_put(commit);
 }
 
+static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc *crtc)
+{
+   init_completion(&commit->flip_done);
+   init_completion(&commit->hw_done);
+   init_completion(&commit->cleanup_done);
+   INIT_LIST_HEAD(&commit->commit_entry);
+   kref_init(&commit->ref);
+   commit->crtc = crtc;
+}
+
+static struct drm_crtc_commit *
+fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+   struct drm_crtc_commit *commit;
+
+   if (crtc) {
+   struct drm_crtc_state *new_crtc_state;
+
+   new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+
+   commit = new_crtc_state->commit;
+   } else if (!state->fake_commit) {
+   state->fake_commit = commit = kzalloc(sizeof(*commit), 
GFP_KERNEL);
+   if (!commit)
+   return NULL;
+
+   init_commit(commit, NULL);
+   } else
+   commit = state->fake_commit;
+
+   drm_crtc_commit_get(commit);
+   return commit;
+}
+
 /**
  * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
  * @state: new modeset state to be committed
@@ -1692,6 +1726,10 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
 {
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+   struct drm_connector *conn;
+   struct drm_connector_state *old_conn_state, *new_conn_state;
+   struct drm_plane *plane;
+   struct drm_plane_state *old_plane_state, *new_plane_state;
struct drm_crtc_commit *commit;
int i, ret;
 
@@ -1700,12 +1738,7 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
if (!commit)
return -ENOMEM;
 
-   init_completion(&commit->flip_done);
-   init_completion(&commit->hw_done);
-   init_completion(&commit->cleanup_done);
-   INIT_LIST_HEAD(&commit->commit_entry);
-   kref_init(&commit->ref);
-   commit->crtc = crtc;
+   init_commit(commit, crtc);
 
new_crtc_state->commit = commit;
 
@@ -1741,6 +1774,36 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
drm_crtc_commit_get(commit);
}
 
+   for_each_oldnew_connector_in_state(state, conn, old_conn_state, 
new_conn_state, i) {
+   if (new_conn_state->crtc)
+   continue;
+
+   if (nonblock && old_conn_state->commit &&
+   
!try_wait_for_completion(&old_conn_state->commit->flip_done))
+   return -EBUSY;
+
+   commit = fake_or_crtc_commit(state, old_conn_state->crtc);
+   if (!commit)
+   return -ENOMEM;
+
+   new_conn_state->commit =

[Intel-gfx] [RFC PATCH 1/5] drm/i915: Always wait for flip_done

[Maarten Lankhorst]

The next commit removes the wait for flip_done in in
drm_atomic_helper_commit_cleanup_done, but we need it for the tests
to pass. Instead of using complicated vblank tracking which ends
up being ignored anyway, call the correct atomic helper. :)

RFC because I'm not completely sure what we want to do with the vblank waiting,
I think for now this patch is the right way to go until we decide because it
preserves the status quo when drm_crtc_commit was introduced.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 83 +++-
 2 files changed, 8 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cbbafbfb0a55..de19621864a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -707,8 +707,7 @@ struct drm_i915_display_funcs {
struct drm_atomic_state *old_state);
void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 struct drm_atomic_state *old_state);
-   void (*update_crtcs)(struct drm_atomic_state *state,
-unsigned int *crtc_vblank_mask);
+   void (*update_crtcs)(struct drm_atomic_state *state);
void (*audio_codec_enable)(struct drm_connector *connector,
   struct intel_encoder *encoder,
   const struct drm_display_mode 
*adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 52c73b4dabaa..3f3cb96aa11e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12114,73 +12114,10 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc 
*crtc)
return dev->driver->get_vblank_counter(dev, crtc->pipe);
 }
 
-static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
- struct drm_i915_private *dev_priv,
- unsigned crtc_mask)
-{
-   unsigned last_vblank_count[I915_MAX_PIPES];
-   enum pipe pipe;
-   int ret;
-
-   if (!crtc_mask)
-   return;
-
-   for_each_pipe(dev_priv, pipe) {
-   struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
- pipe);
-
-   if (!((1 << pipe) & crtc_mask))
-   continue;
-
-   ret = drm_crtc_vblank_get(&crtc->base);
-   if (WARN_ON(ret != 0)) {
-   crtc_mask &= ~(1 << pipe);
-   continue;
-   }
-
-   last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
-   }
-
-   for_each_pipe(dev_priv, pipe) {
-   struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
- pipe);
-   long lret;
-
-   if (!((1 << pipe) & crtc_mask))
-   continue;
-
-   lret = wait_event_timeout(dev->vblank[pipe].queue,
-   last_vblank_count[pipe] !=
-   drm_crtc_vblank_count(&crtc->base),
-   msecs_to_jiffies(50));
-
-   WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
-
-   drm_crtc_vblank_put(&crtc->base);
-   }
-}
-
-static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
-{
-   /* fb updated, need to unpin old fb */
-   if (crtc_state->fb_changed)
-   return true;
-
-   /* wm changes, need vblank before final wm's */
-   if (crtc_state->update_wm_post)
-   return true;
-
-   if (crtc_state->wm.need_postvbl_update)
-   return true;
-
-   return false;
-}
-
 static void intel_update_crtc(struct drm_crtc *crtc,
  struct drm_atomic_state *state,
  struct drm_crtc_state *old_crtc_state,
- struct drm_crtc_state *new_crtc_state,
- unsigned int *crtc_vblank_mask)
+ struct drm_crtc_state *new_crtc_state)
 {
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -12203,13 +12140,9 @@ static void intel_update_crtc(struct drm_crtc *crtc,
}
 
drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
-
-   if (needs_vblank_wait(pipe_config))
-   *crtc_vblank_mask |= drm_crtc_mask(crtc);
 }
 
-static void intel_update_crtcs(struct drm_atomic_state *state,
-  unsigned int *crtc_vblank_mask)
+static void intel_update_crtcs(struct drm_atomic_state *state)
 {
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
@@ 

[Intel-gfx] [RFC PATCH 5/5] drm/atomic: Make async plane update checks work as intended.

[Maarten Lankhorst]

By always keeping track of the last commit in plane_state, we know
whether there is an active update on the plane or not. With that
information we can reject the fast update, and force the slowpath
to be used as was originally intended.

Cc: Gustavo Padovan 
Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/drm_atomic_helper.c  | 25 +++--
 drivers/gpu/drm/i915/intel_display.c |  8 
 include/drm/drm_plane.h  |  5 +++--
 3 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 034f563fb130..384d99347bb3 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1388,8 +1388,8 @@ int drm_atomic_helper_async_check(struct drm_device *dev,
 {
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
-   struct drm_plane *__plane, *plane = NULL;
-   struct drm_plane_state *__plane_state, *plane_state = NULL;
+   struct drm_plane *plane;
+   struct drm_plane_state *old_plane_state, *new_plane_state;
const struct drm_plane_helper_funcs *funcs;
int i, n_planes = 0;
 
@@ -1398,33 +1398,33 @@ int drm_atomic_helper_async_check(struct drm_device 
*dev,
return -EINVAL;
}
 
-   for_each_new_plane_in_state(state, __plane, __plane_state, i) {
+   for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
new_plane_state, i)
n_planes++;
-   plane = __plane;
-   plane_state = __plane_state;
-   }
 
/* FIXME: we support only single plane updates for now */
-   if (!plane || n_planes != 1)
+   if (n_planes != 1)
return -EINVAL;
 
-   if (!plane_state->crtc)
+   if (!new_plane_state->crtc)
return -EINVAL;
 
funcs = plane->helper_private;
if (!funcs->atomic_async_update)
return -EINVAL;
 
-   if (plane_state->fence)
+   if (new_plane_state->fence)
return -EINVAL;
 
/*
-* TODO: Don't do an async update if there is an outstanding commit 
modifying
+* Don't do an async update if there is an outstanding commit modifying
 * the plane.  This prevents our async update's changes from getting
 * overridden by a previous synchronous update's state.
 */
+   if (old_plane_state->commit &&
+   !try_wait_for_completion(&old_plane_state->commit->hw_done))
+   return -EBUSY;
 
-   return funcs->atomic_async_check(plane, plane_state);
+   return funcs->atomic_async_check(plane, new_plane_state);
 }
 EXPORT_SYMBOL(drm_atomic_helper_async_check);
 
@@ -1790,9 +1790,6 @@ int drm_atomic_helper_setup_commit(struct 
drm_atomic_state *state,
}
 
for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
new_plane_state, i) {
-   if (new_plane_state->crtc)
-   continue;
-
if (nonblock && old_plane_state->commit &&

!try_wait_for_completion(&old_plane_state->commit->flip_done))
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 70ce02753177..cf21ec4ce920 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13043,6 +13043,14 @@ intel_legacy_cursor_update(struct drm_plane *plane,
goto slow;
 
old_plane_state = plane->state;
+   /*
+* Don't do an async update if there is an outstanding commit modifying
+* the plane.  This prevents our async update's changes from getting
+* overridden by a previous synchronous update's state.
+*/
+   if (old_plane_state->commit &&
+   !try_wait_for_completion(&old_plane_state->commit->hw_done))
+   goto slow;
 
/*
 * If any parameters change that may affect watermarks,
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 7d96116fd4c4..feb9941d0cdb 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -124,9 +124,10 @@ struct drm_plane_state {
bool visible;
 
/**
-* @commit: Tracks the pending commit to prevent use-after-free 
conditions.
+* @commit: Tracks the pending commit to prevent use-after-free 
conditions,
+* and for async plane updates.
 *
-* Is only set when @crtc is NULL.
+* May be NULL.
 */
struct drm_crtc_commit *commit;
 
-- 
2.11.0

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[Intel-gfx] [PATCH 0/5] drm/atomic: Fix use-after-free with unbound connectors/planes.

[Maarten Lankhorst]

This started out as a small set of 2 patches, but feedback made it 5. :(

Maarten Lankhorst (5):
  drm/i915: Always wait for flip_done
  drm/atomic: Remove waits in drm_atomic_helper_commit_cleanup_done
  drm/atomic: Move drm_crtc_commit to drm_crtc_state, v2.
  drm/atomic: Fix freeing connector/plane state too early by tracking
commits, v2.
  drm/atomic: Make async plane update checks work as intended.

 drivers/gpu/drm/drm_atomic.c |  11 +-
 drivers/gpu/drm/drm_atomic_helper.c  | 270 ++-
 drivers/gpu/drm/i915/i915_drv.h  |   3 +-
 drivers/gpu/drm/i915/intel_display.c |  93 +++-
 include/drm/drm_atomic.h |  13 +-
 include/drm/drm_connector.h  |   7 +
 include/drm/drm_crtc.h   |  23 ++-
 include/drm/drm_plane.h  |   8 ++
 8 files changed, 242 insertions(+), 186 deletions(-)

-- 
2.11.0

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Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

[Daniel Vetter]

On Wed, Aug 30, 2017 at 10:43:47AM +0100, Lionel Landwerlin wrote:
> On 30/08/17 10:39, Daniel Vetter wrote:
> > Also dapc is not a good testcase name, needs some proper prefixing.
> 
> 
> Reminds me perf.c should probably be renamed too.
> What would be an appropriate name? intel_perf.c?

I think at least a common prefix for all the perf related stuff would be
good. Atm we don't have a consistent rule for prefixing intel-specific
tests, so perf and perf_dapc sound ok to me. If you want, add an intel_
prefix for fun.
-Daniel
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Daniel Vetter]

On Tue, Aug 29, 2017 at 03:59:36PM +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-29 15:54:06)
> > On Tue, 2017-08-29 at 11:33 +0100, Chris Wilson wrote:
> > > Since we hold the device wakeref when writing through the GTT (otherwise
> > > the writes would fail), we presumed that before the device sleeps those
> > > writes would naturally be flushed and that we wouldn't need our mmio
> > > read trick. However, that presumption seems false and a sleepy bxt seems
> > > to require us to always manually flush the GTT writes prior to direct
> > > access.
> > > 
> > > Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before 
> > > flushing GTT writes")
> > > Signed-off-by: Chris Wilson 
> > > Cc: Joonas Lahtinen 
> > 
> > Got any Bugzilla, Testcase, Tested-by?
> 
> Original bugzilla hasn't been reopened, so I its looks like they were
> happy enough with the original patches that fixed the problem on my bxt.
> The testcase seems to be very system dependent, my suspicion is that it
> has to do with the wacky runtime pm exhibited by CI bxt.

CI bxt doesn't have displays, which means we shut down a lot more when
it's running. Does this indicate a huge gem test gap where we should run
plenty of gem testcases with all the outputs shut down?

Or just the need to add a pile more tests to pm_rpm?

Would be good if testcase review is a part of review, and not just "code
does what the commit message says" ... The latter should be the
trivial-most part of review really.
-Daniel
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[Intel-gfx] [PATCH 2/2] drm/i915: Wrap port cancellation into a function

[Mika Kuoppala]

On reset and wedged path, we want to release the requests
that are tied to ports and then mark the ports to be unset.
Introduce a function for this.

Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 10 ++
 drivers/gpu/drm/i915/intel_lrc.c|  5 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 ++
 4 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6dffab14a3e3..e63721a1253f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3046,17 +3046,14 @@ static void engine_set_wedged(struct intel_engine_cs 
*engine)
 */
 
if (i915.enable_execlists) {
-   struct execlist_port *port = engine->execlist.port;
+   struct intel_engine_execlist * const el = &engine->execlist;
unsigned long flags;
-   unsigned int n;
 
spin_lock_irqsave(&engine->timeline->lock, flags);
 
-   for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
-   i915_gem_request_put(port_request(&port[n]));
-   memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
-   engine->execlist.queue = RB_ROOT;
-   engine->execlist.first = NULL;
+   execlist_cancel_port_requests(el);
+   el->queue = RB_ROOT;
+   el->first = NULL;
 
spin_unlock_irqrestore(&engine->timeline->lock, flags);
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 253d2f501ef3..65a9a53f7495 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1370,6 +1370,16 @@ void intel_engines_mark_idle(struct drm_i915_private 
*i915)
}
 }
 
+void execlist_cancel_port_requests(struct intel_engine_execlist * const el)
+{
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(el->port); i++)
+   i915_gem_request_put(port_request(&el->port[i]));
+
+   memset(el->port, 0, sizeof(el->port));
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_engine.c"
 #endif
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2964e7c0a873..7dc893806b43 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1331,7 +1331,6 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
 {
struct execlist_port *port = engine->execlist.port;
struct intel_context *ce;
-   unsigned int n;
 
/*
 * Catch up with any missed context-switch interrupts.
@@ -1343,9 +1342,7 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
 * requests were completed.
 */
if (!request) {
-   for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
-   i915_gem_request_put(port_request(&port[n]));
-   memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
+   execlist_cancel_port_requests(&engine->execlist);
return;
}
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 5788bf713e27..7e6b0b997c16 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -493,6 +493,8 @@ struct intel_engine_cs {
u32 (*get_cmd_length_mask)(u32 cmd_header);
 };
 
+void execlist_cancel_port_requests(struct intel_engine_execlist * const el);
+
 static inline unsigned int
 intel_engine_flag(const struct intel_engine_cs *engine)
 {
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 2/5] drm/atomic: Remove waits in drm_atomic_helper_commit_cleanup_done

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:17:49PM +0200, Maarten Lankhorst wrote:
> When commit synchronization through drm_crtc_commit was first
> introduced, we tried to solve the problem of the flip_done
> needing a reference count by blocking in cleanup_done.
> 
> This has been changed by commit 24835e442f28 ("drm: reference count
> event->completion") which made the waits here no longer needed.

This is wrong. Your next patch makes this no longer necessary.
> 
> Signed-off-by: Maarten Lankhorst 
> Suggested-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c | 17 -
>  1 file changed, 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4e53aae9a1fb..11d0e94a2181 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1885,7 +1885,6 @@ void drm_atomic_helper_commit_cleanup_done(struct 
> drm_atomic_state *old_state)
>   struct drm_crtc_state *new_crtc_state;
>   struct drm_crtc_commit *commit;
>   int i;
> - long ret;
>  
>   for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
>   commit = old_state->crtcs[i].commit;
> @@ -1895,22 +1894,6 @@ void drm_atomic_helper_commit_cleanup_done(struct 
> drm_atomic_state *old_state)
>   complete_all(&commit->cleanup_done);
>   WARN_ON(!try_wait_for_completion(&commit->hw_done));
>  
> - /* commit_list borrows our reference, need to remove before we
> -  * clean up our drm_atomic_state. But only after it actually
> -  * completed, otherwise subsequent commits won't stall 
> properly. */

This comment here is the clue: "... otherwise subsequent commits wont
stall properly". When we remove the drm_crtc_commit from commit_list, the
next commit won't be able to properly stall for flip_done. Hence we must
wait for flip_done before removing it.

But with your new patch we wait for flip_done using
old_crtc_state->commit, and this is indeed no longer necessary.

With the commit message and patch ordering fixed up:

Reviewed-by: Daniel Vetter 

> - if (try_wait_for_completion(&commit->flip_done))
> - goto del_commit;
> -
> - /* We must wait for the vblank event to signal our completion
> -  * before releasing our reference, since the vblank work does
> -  * not hold a reference of its own. */
> - ret = wait_for_completion_timeout(&commit->flip_done,
> -   10*HZ);
> - if (ret == 0)
> - DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
> -   crtc->base.id, crtc->name);
> -
> -del_commit:
>   spin_lock(&crtc->commit_lock);
>   list_del(&commit->commit_entry);
>   spin_unlock(&crtc->commit_lock);
> -- 
> 2.11.0
> 
> ___
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Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:17:51PM +0200, Maarten Lankhorst wrote:
> Currently we neatly track the crtc state, but forget to look at
> plane/connector state.
> 
> When doing a nonblocking modeset, immediately followed by a setprop
> before the modeset completes, the setprop will see the modesets new
> state as the old state and free it.
> 
> This has to be solved by waiting for hw_done on the connector, even
> if it's not assigned to a crtc. When a connector is unbound we take
> the last crtc commit, and when it stays unbound we create a new
> fake crtc commit for that gets signaled on hw_done for all the
> planes/connectors.
> 
> We wait for it the same way as we do for crtc's, which will make
> sure we never run into a use-after-free situation.
> 
> Changes since v1:
> - Only create a single disable commit. (danvet)
> - Fix leak in intel_legacy_cursor_update.
> 
> Signed-off-by: Maarten Lankhorst 
> Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> Cc: Laurent Pinchart 
> ---
>  drivers/gpu/drm/drm_atomic.c |   4 +
>  drivers/gpu/drm/drm_atomic_helper.c  | 156 
> +--
>  drivers/gpu/drm/i915/intel_display.c |   2 +
>  include/drm/drm_atomic.h |  12 +++
>  include/drm/drm_connector.h  |   7 ++
>  include/drm/drm_plane.h  |   7 ++
>  6 files changed, 182 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2cce48f203e0..75f5f74de9bf 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct 
> drm_atomic_state *state)
>   }
>   state->num_private_objs = 0;
>  
> + if (state->fake_commit) {
> + drm_crtc_commit_put(state->fake_commit);
> + state->fake_commit = NULL;
> + }
>  }
>  EXPORT_SYMBOL(drm_atomic_state_default_clear);
>  
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 8ccb8b6536c0..034f563fb130 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion 
> *completion)
>   drm_crtc_commit_put(commit);
>  }
>  
> +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc 
> *crtc)
> +{
> + init_completion(&commit->flip_done);
> + init_completion(&commit->hw_done);
> + init_completion(&commit->cleanup_done);
> + INIT_LIST_HEAD(&commit->commit_entry);
> + kref_init(&commit->ref);
> + commit->crtc = crtc;
> +}
> +
> +static struct drm_crtc_commit *
> +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> +{
> + struct drm_crtc_commit *commit;
> +
> + if (crtc) {
> + struct drm_crtc_state *new_crtc_state;
> +
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> +
> + commit = new_crtc_state->commit;
> + } else if (!state->fake_commit) {
> + state->fake_commit = commit = kzalloc(sizeof(*commit), 
> GFP_KERNEL);
> + if (!commit)
> + return NULL;
> +
> + init_commit(commit, NULL);
> + } else
> + commit = state->fake_commit;
> +
> + drm_crtc_commit_get(commit);

Double refcount for the case where you call init_commit? Aka I think this
leaks.

> + return commit;
> +}
> +
>  /**
>   * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
>   * @state: new modeset state to be committed
> @@ -1692,6 +1726,10 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>  {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> + struct drm_connector *conn;
> + struct drm_connector_state *old_conn_state, *new_conn_state;
> + struct drm_plane *plane;
> + struct drm_plane_state *old_plane_state, *new_plane_state;
>   struct drm_crtc_commit *commit;
>   int i, ret;
>  
> @@ -1700,12 +1738,7 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   if (!commit)
>   return -ENOMEM;
>  
> - init_completion(&commit->flip_done);
> - init_completion(&commit->hw_done);
> - init_completion(&commit->cleanup_done);
> - INIT_LIST_HEAD(&commit->commit_entry);
> - kref_init(&commit->ref);
> - commit->crtc = crtc;
> + init_commit(commit, crtc);
>  
>   new_crtc_state->commit = commit;
>  
> @@ -1741,6 +1774,36 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   drm_crtc_commit_get(commit);
>   }
>  
> + for_each_oldnew_connector_in_state(state, conn, old_conn_state, 
> new_conn_state, i) {

Maybe a commen there like
/* commit tracked through the crtc_state->commit */
Feels at least a bit non-obviou

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Make own struct for execlist items (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Make own struct for execlist items 
(rev2)
URL   : https://patchwork.freedesktop.org/series/29533/
State : failure

== Summary ==

Series 29533v2 series starting with [1/2] drm/i915: Make own struct for 
execlist items
https://patchwork.freedesktop.org/api/1.0/series/29533/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> INCOMPLETE (fi-bwr-2160)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:449s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:445s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:545s
fi-bwr-2160  total:278  pass:183  dwarn:0   dfail:0   fail:0   skip:94 
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:519s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:513s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:437s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:445s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:429s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:428s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:477s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:595s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:591s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:522s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:488s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:482s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:549s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:404s

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
c21421e1a0e2 drm/i915: Wrap port cancellation into a function
ef321d1c6ab1 drm/i915: Make own struct for execlist items

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5538/
___
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Re: [Intel-gfx] [RFC PATCH 1/5] drm/i915: Always wait for flip_done

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:17:48PM +0200, Maarten Lankhorst wrote:
> The next commit removes the wait for flip_done in in
> drm_atomic_helper_commit_cleanup_done, but we need it for the tests
> to pass. Instead of using complicated vblank tracking which ends
> up being ignored anyway, call the correct atomic helper. :)
> 
> RFC because I'm not completely sure what we want to do with the vblank 
> waiting,
> I think for now this patch is the right way to go until we decide because it
> preserves the status quo when drm_crtc_commit was introduced.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  3 +-
>  drivers/gpu/drm/i915/intel_display.c | 83 
> +++-
>  2 files changed, 8 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cbbafbfb0a55..de19621864a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -707,8 +707,7 @@ struct drm_i915_display_funcs {
>   struct drm_atomic_state *old_state);
>   void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
>struct drm_atomic_state *old_state);
> - void (*update_crtcs)(struct drm_atomic_state *state,
> -  unsigned int *crtc_vblank_mask);
> + void (*update_crtcs)(struct drm_atomic_state *state);
>   void (*audio_codec_enable)(struct drm_connector *connector,
>  struct intel_encoder *encoder,
>  const struct drm_display_mode 
> *adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 52c73b4dabaa..3f3cb96aa11e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12114,73 +12114,10 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc 
> *crtc)
>   return dev->driver->get_vblank_counter(dev, crtc->pipe);
>  }
>  
> -static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
> -   struct drm_i915_private *dev_priv,
> -   unsigned crtc_mask)
> -{
> - unsigned last_vblank_count[I915_MAX_PIPES];
> - enum pipe pipe;
> - int ret;
> -
> - if (!crtc_mask)
> - return;
> -
> - for_each_pipe(dev_priv, pipe) {
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> -   pipe);
> -
> - if (!((1 << pipe) & crtc_mask))
> - continue;
> -
> - ret = drm_crtc_vblank_get(&crtc->base);
> - if (WARN_ON(ret != 0)) {
> - crtc_mask &= ~(1 << pipe);
> - continue;
> - }
> -
> - last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
> - }
> -
> - for_each_pipe(dev_priv, pipe) {
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> -   pipe);
> - long lret;
> -
> - if (!((1 << pipe) & crtc_mask))
> - continue;
> -
> - lret = wait_event_timeout(dev->vblank[pipe].queue,
> - last_vblank_count[pipe] !=
> - drm_crtc_vblank_count(&crtc->base),
> - msecs_to_jiffies(50));
> -
> - WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
> -
> - drm_crtc_vblank_put(&crtc->base);
> - }
> -}
> -
> -static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
> -{
> - /* fb updated, need to unpin old fb */
> - if (crtc_state->fb_changed)
> - return true;
> -
> - /* wm changes, need vblank before final wm's */
> - if (crtc_state->update_wm_post)
> - return true;
> -
> - if (crtc_state->wm.need_postvbl_update)
> - return true;
> -
> - return false;
> -}
> -
>  static void intel_update_crtc(struct drm_crtc *crtc,
> struct drm_atomic_state *state,
> struct drm_crtc_state *old_crtc_state,
> -   struct drm_crtc_state *new_crtc_state,
> -   unsigned int *crtc_vblank_mask)
> +   struct drm_crtc_state *new_crtc_state)
>  {
>   struct drm_device *dev = crtc->dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -12203,13 +12140,9 @@ static void intel_update_crtc(struct drm_crtc *crtc,
>   }
>  
>   drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
> -
> - if (needs_vblank_wait(pipe_config))
> - *crtc_vblank_mask |= drm_crtc_mask(crtc);
>  }
>  
> -static void intel_update_crtcs(struct drm_atomic_state *state,
> -unsign

Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Maarten Lankhorst]

Op 30-08-17 om 14:40 schreef Daniel Vetter:
> On Wed, Aug 30, 2017 at 02:17:51PM +0200, Maarten Lankhorst wrote:
>> Currently we neatly track the crtc state, but forget to look at
>> plane/connector state.
>>
>> When doing a nonblocking modeset, immediately followed by a setprop
>> before the modeset completes, the setprop will see the modesets new
>> state as the old state and free it.
>>
>> This has to be solved by waiting for hw_done on the connector, even
>> if it's not assigned to a crtc. When a connector is unbound we take
>> the last crtc commit, and when it stays unbound we create a new
>> fake crtc commit for that gets signaled on hw_done for all the
>> planes/connectors.
>>
>> We wait for it the same way as we do for crtc's, which will make
>> sure we never run into a use-after-free situation.
>>
>> Changes since v1:
>> - Only create a single disable commit. (danvet)
>> - Fix leak in intel_legacy_cursor_update.
>>
>> Signed-off-by: Maarten Lankhorst 
>> Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
>> Cc: Laurent Pinchart 
>> ---
>>  drivers/gpu/drm/drm_atomic.c |   4 +
>>  drivers/gpu/drm/drm_atomic_helper.c  | 156 
>> +--
>>  drivers/gpu/drm/i915/intel_display.c |   2 +
>>  include/drm/drm_atomic.h |  12 +++
>>  include/drm/drm_connector.h  |   7 ++
>>  include/drm/drm_plane.h  |   7 ++
>>  6 files changed, 182 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
>> index 2cce48f203e0..75f5f74de9bf 100644
>> --- a/drivers/gpu/drm/drm_atomic.c
>> +++ b/drivers/gpu/drm/drm_atomic.c
>> @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct 
>> drm_atomic_state *state)
>>  }
>>  state->num_private_objs = 0;
>>  
>> +if (state->fake_commit) {
>> +drm_crtc_commit_put(state->fake_commit);
>> +state->fake_commit = NULL;
>> +}
>>  }
>>  EXPORT_SYMBOL(drm_atomic_state_default_clear);
>>  
>> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
>> b/drivers/gpu/drm/drm_atomic_helper.c
>> index 8ccb8b6536c0..034f563fb130 100644
>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>> @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion 
>> *completion)
>>  drm_crtc_commit_put(commit);
>>  }
>>  
>> +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc 
>> *crtc)
>> +{
>> +init_completion(&commit->flip_done);
>> +init_completion(&commit->hw_done);
>> +init_completion(&commit->cleanup_done);
>> +INIT_LIST_HEAD(&commit->commit_entry);
>> +kref_init(&commit->ref);
>> +commit->crtc = crtc;
>> +}
>> +
>> +static struct drm_crtc_commit *
>> +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
>> +{
>> +struct drm_crtc_commit *commit;
>> +
>> +if (crtc) {
>> +struct drm_crtc_state *new_crtc_state;
>> +
>> +new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>> +
>> +commit = new_crtc_state->commit;
>> +} else if (!state->fake_commit) {
>> +state->fake_commit = commit = kzalloc(sizeof(*commit), 
>> GFP_KERNEL);
>> +if (!commit)
>> +return NULL;
>> +
>> +init_commit(commit, NULL);
>> +} else
>> +commit = state->fake_commit;
>> +
>> +drm_crtc_commit_get(commit);
> Double refcount for the case where you call init_commit? Aka I think this
> leaks.
>
>> +return commit;
>> +}
>> +
>>  /**
>>   * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
>>   * @state: new modeset state to be committed
>> @@ -1692,6 +1726,10 @@ int drm_atomic_helper_setup_commit(struct 
>> drm_atomic_state *state,
>>  {
>>  struct drm_crtc *crtc;
>>  struct drm_crtc_state *old_crtc_state, *new_crtc_state;
>> +struct drm_connector *conn;
>> +struct drm_connector_state *old_conn_state, *new_conn_state;
>> +struct drm_plane *plane;
>> +struct drm_plane_state *old_plane_state, *new_plane_state;
>>  struct drm_crtc_commit *commit;
>>  int i, ret;
>>  
>> @@ -1700,12 +1738,7 @@ int drm_atomic_helper_setup_commit(struct 
>> drm_atomic_state *state,
>>  if (!commit)
>>  return -ENOMEM;
>>  
>> -init_completion(&commit->flip_done);
>> -init_completion(&commit->hw_done);
>> -init_completion(&commit->cleanup_done);
>> -INIT_LIST_HEAD(&commit->commit_entry);
>> -kref_init(&commit->ref);
>> -commit->crtc = crtc;
>> +init_commit(commit, crtc);
>>  
>>  new_crtc_state->commit = commit;
>>  
>> @@ -1741,6 +1774,36 @@ int drm_atomic_helper_setup_commit(struct 
>> drm_atomic_state *state,
>>  drm_crtc_commit_get(commit);
>>  }
>>  
>> +for_each_oldnew_connector_in_state(state, conn, old_conn_state, 
>> new_conn_state, i) 

Re: [Intel-gfx] [RFC PATCH 5/5] drm/atomic: Make async plane update checks work as intended.

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:17:52PM +0200, Maarten Lankhorst wrote:
> By always keeping track of the last commit in plane_state, we know
> whether there is an active update on the plane or not. With that
> information we can reject the fast update, and force the slowpath
> to be used as was originally intended.
> 
> Cc: Gustavo Padovan 
> Signed-off-by: Maarten Lankhorst 

Makes sense, but I think like patch 1 it would be better to do this in a
separate series. Which would then include a patch to move i915 over to the
async plane support.

One more comment below.

> ---
>  drivers/gpu/drm/drm_atomic_helper.c  | 25 +++--
>  drivers/gpu/drm/i915/intel_display.c |  8 
>  include/drm/drm_plane.h  |  5 +++--
>  3 files changed, 22 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 034f563fb130..384d99347bb3 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1388,8 +1388,8 @@ int drm_atomic_helper_async_check(struct drm_device 
> *dev,
>  {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *crtc_state;
> - struct drm_plane *__plane, *plane = NULL;
> - struct drm_plane_state *__plane_state, *plane_state = NULL;
> + struct drm_plane *plane;
> + struct drm_plane_state *old_plane_state, *new_plane_state;
>   const struct drm_plane_helper_funcs *funcs;
>   int i, n_planes = 0;
>  
> @@ -1398,33 +1398,33 @@ int drm_atomic_helper_async_check(struct drm_device 
> *dev,
>   return -EINVAL;
>   }
>  
> - for_each_new_plane_in_state(state, __plane, __plane_state, i) {
> + for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
> new_plane_state, i)
>   n_planes++;
> - plane = __plane;
> - plane_state = __plane_state;
> - }
>  
>   /* FIXME: we support only single plane updates for now */
> - if (!plane || n_planes != 1)
> + if (n_planes != 1)
>   return -EINVAL;
>  
> - if (!plane_state->crtc)
> + if (!new_plane_state->crtc)
>   return -EINVAL;
>  
>   funcs = plane->helper_private;
>   if (!funcs->atomic_async_update)
>   return -EINVAL;
>  
> - if (plane_state->fence)
> + if (new_plane_state->fence)
>   return -EINVAL;
>  
>   /*
> -  * TODO: Don't do an async update if there is an outstanding commit 
> modifying
> +  * Don't do an async update if there is an outstanding commit modifying
>* the plane.  This prevents our async update's changes from getting
>* overridden by a previous synchronous update's state.
>*/
> + if (old_plane_state->commit &&
> + !try_wait_for_completion(&old_plane_state->commit->hw_done))
> + return -EBUSY;

Instead of forcing us to always set the plane_state->commit pointer (bunch
of pointles refcounting), perhaps just check
plane_state->crtc->state->commit? We do hold the necessary locks to at
least look at that.
-Daniel

>  
> - return funcs->atomic_async_check(plane, plane_state);
> + return funcs->atomic_async_check(plane, new_plane_state);
>  }
>  EXPORT_SYMBOL(drm_atomic_helper_async_check);
>  
> @@ -1790,9 +1790,6 @@ int drm_atomic_helper_setup_commit(struct 
> drm_atomic_state *state,
>   }
>  
>   for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
> new_plane_state, i) {
> - if (new_plane_state->crtc)
> - continue;
> -
>   if (nonblock && old_plane_state->commit &&
>   
> !try_wait_for_completion(&old_plane_state->commit->flip_done))
>   return -EBUSY;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 70ce02753177..cf21ec4ce920 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13043,6 +13043,14 @@ intel_legacy_cursor_update(struct drm_plane *plane,
>   goto slow;
>  
>   old_plane_state = plane->state;
> + /*
> +  * Don't do an async update if there is an outstanding commit modifying
> +  * the plane.  This prevents our async update's changes from getting
> +  * overridden by a previous synchronous update's state.
> +  */
> + if (old_plane_state->commit &&
> + !try_wait_for_completion(&old_plane_state->commit->hw_done))
> + goto slow;
>  
>   /*
>* If any parameters change that may affect watermarks,
> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
> index 7d96116fd4c4..feb9941d0cdb 100644
> --- a/include/drm/drm_plane.h
> +++ b/include/drm/drm_plane.h
> @@ -124,9 +124,10 @@ struct drm_plane_state {
>   bool visible;
>  
>   /**
> -  * @commit: Tracks the pending commit to prevent use-after-free 
> conditions.
> +  * @commit: Tracks the pending commit to

Re: [Intel-gfx] [RFC PATCH 5/5] drm/atomic: Make async plane update checks work as intended.

[Maarten Lankhorst]

Op 30-08-17 om 14:46 schreef Daniel Vetter:
> On Wed, Aug 30, 2017 at 02:17:52PM +0200, Maarten Lankhorst wrote:
>> By always keeping track of the last commit in plane_state, we know
>> whether there is an active update on the plane or not. With that
>> information we can reject the fast update, and force the slowpath
>> to be used as was originally intended.
>>
>> Cc: Gustavo Padovan 
>> Signed-off-by: Maarten Lankhorst 
> Makes sense, but I think like patch 1 it would be better to do this in a
> separate series. Which would then include a patch to move i915 over to the
> async plane support.
>
> One more comment below.
>
>> ---
>>  drivers/gpu/drm/drm_atomic_helper.c  | 25 +++--
>>  drivers/gpu/drm/i915/intel_display.c |  8 
>>  include/drm/drm_plane.h  |  5 +++--
>>  3 files changed, 22 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
>> b/drivers/gpu/drm/drm_atomic_helper.c
>> index 034f563fb130..384d99347bb3 100644
>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>> @@ -1388,8 +1388,8 @@ int drm_atomic_helper_async_check(struct drm_device 
>> *dev,
>>  {
>>  struct drm_crtc *crtc;
>>  struct drm_crtc_state *crtc_state;
>> -struct drm_plane *__plane, *plane = NULL;
>> -struct drm_plane_state *__plane_state, *plane_state = NULL;
>> +struct drm_plane *plane;
>> +struct drm_plane_state *old_plane_state, *new_plane_state;
>>  const struct drm_plane_helper_funcs *funcs;
>>  int i, n_planes = 0;
>>  
>> @@ -1398,33 +1398,33 @@ int drm_atomic_helper_async_check(struct drm_device 
>> *dev,
>>  return -EINVAL;
>>  }
>>  
>> -for_each_new_plane_in_state(state, __plane, __plane_state, i) {
>> +for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
>> new_plane_state, i)
>>  n_planes++;
>> -plane = __plane;
>> -plane_state = __plane_state;
>> -}
>>  
>>  /* FIXME: we support only single plane updates for now */
>> -if (!plane || n_planes != 1)
>> +if (n_planes != 1)
>>  return -EINVAL;
>>  
>> -if (!plane_state->crtc)
>> +if (!new_plane_state->crtc)
>>  return -EINVAL;
>>  
>>  funcs = plane->helper_private;
>>  if (!funcs->atomic_async_update)
>>  return -EINVAL;
>>  
>> -if (plane_state->fence)
>> +if (new_plane_state->fence)
>>  return -EINVAL;
>>  
>>  /*
>> - * TODO: Don't do an async update if there is an outstanding commit 
>> modifying
>> + * Don't do an async update if there is an outstanding commit modifying
>>   * the plane.  This prevents our async update's changes from getting
>>   * overridden by a previous synchronous update's state.
>>   */
>> +if (old_plane_state->commit &&
>> +!try_wait_for_completion(&old_plane_state->commit->hw_done))
>> +return -EBUSY;
> Instead of forcing us to always set the plane_state->commit pointer (bunch
> of pointles refcounting), perhaps just check
> plane_state->crtc->state->commit? We do hold the necessary locks to at
> least look at that.
Then we'd always take the slowpath?

The point here was to check whether the current plane was part of the most 
recent commit, to know this we must either add a flip_planes mask member to 
drm_crtc_commit, or add a pointer in plane_state to the most recent commit it 
was part of.
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Re: [Intel-gfx] [RFC PATCH 1/5] drm/i915: Always wait for flip_done

[Maarten Lankhorst]

Op 30-08-17 om 14:43 schreef Daniel Vetter:
> On Wed, Aug 30, 2017 at 02:17:48PM +0200, Maarten Lankhorst wrote:
>> The next commit removes the wait for flip_done in in
>> drm_atomic_helper_commit_cleanup_done, but we need it for the tests
>> to pass. Instead of using complicated vblank tracking which ends
>> up being ignored anyway, call the correct atomic helper. :)
>>
>> RFC because I'm not completely sure what we want to do with the vblank 
>> waiting,
>> I think for now this patch is the right way to go until we decide because it
>> preserves the status quo when drm_crtc_commit was introduced.
>>
>> Signed-off-by: Maarten Lankhorst 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h  |  3 +-
>>  drivers/gpu/drm/i915/intel_display.c | 83 
>> +++-
>>  2 files changed, 8 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index cbbafbfb0a55..de19621864a9 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -707,8 +707,7 @@ struct drm_i915_display_funcs {
>>  struct drm_atomic_state *old_state);
>>  void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
>>   struct drm_atomic_state *old_state);
>> -void (*update_crtcs)(struct drm_atomic_state *state,
>> - unsigned int *crtc_vblank_mask);
>> +void (*update_crtcs)(struct drm_atomic_state *state);
>>  void (*audio_codec_enable)(struct drm_connector *connector,
>> struct intel_encoder *encoder,
>> const struct drm_display_mode 
>> *adjusted_mode);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 52c73b4dabaa..3f3cb96aa11e 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -12114,73 +12114,10 @@ u32 intel_crtc_get_vblank_counter(struct 
>> intel_crtc *crtc)
>>  return dev->driver->get_vblank_counter(dev, crtc->pipe);
>>  }
>>  
>> -static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
>> -  struct drm_i915_private *dev_priv,
>> -  unsigned crtc_mask)
>> -{
>> -unsigned last_vblank_count[I915_MAX_PIPES];
>> -enum pipe pipe;
>> -int ret;
>> -
>> -if (!crtc_mask)
>> -return;
>> -
>> -for_each_pipe(dev_priv, pipe) {
>> -struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
>> -  pipe);
>> -
>> -if (!((1 << pipe) & crtc_mask))
>> -continue;
>> -
>> -ret = drm_crtc_vblank_get(&crtc->base);
>> -if (WARN_ON(ret != 0)) {
>> -crtc_mask &= ~(1 << pipe);
>> -continue;
>> -}
>> -
>> -last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
>> -}
>> -
>> -for_each_pipe(dev_priv, pipe) {
>> -struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
>> -  pipe);
>> -long lret;
>> -
>> -if (!((1 << pipe) & crtc_mask))
>> -continue;
>> -
>> -lret = wait_event_timeout(dev->vblank[pipe].queue,
>> -last_vblank_count[pipe] !=
>> -drm_crtc_vblank_count(&crtc->base),
>> -msecs_to_jiffies(50));
>> -
>> -WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
>> -
>> -drm_crtc_vblank_put(&crtc->base);
>> -}
>> -}
>> -
>> -static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
>> -{
>> -/* fb updated, need to unpin old fb */
>> -if (crtc_state->fb_changed)
>> -return true;
>> -
>> -/* wm changes, need vblank before final wm's */
>> -if (crtc_state->update_wm_post)
>> -return true;
>> -
>> -if (crtc_state->wm.need_postvbl_update)
>> -return true;
>> -
>> -return false;
>> -}
>> -
>>  static void intel_update_crtc(struct drm_crtc *crtc,
>>struct drm_atomic_state *state,
>>struct drm_crtc_state *old_crtc_state,
>> -  struct drm_crtc_state *new_crtc_state,
>> -  unsigned int *crtc_vblank_mask)
>> +  struct drm_crtc_state *new_crtc_state)
>>  {
>>  struct drm_device *dev = crtc->dev;
>>  struct drm_i915_private *dev_priv = to_i915(dev);
>> @@ -12203,13 +12140,9 @@ static void intel_update_crtc(struct drm_crtc *crtc,
>>  }
>>  
>>  drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
>> -
>> -if (needs_vblank_wait(pipe_config))
>> -*crtc_vblank_mask |= drm_crtc_mask(crtc);
>>  }
>

Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Daniel Vetter (2017-08-30 13:23:56)
> On Tue, Aug 29, 2017 at 03:59:36PM +0100, Chris Wilson wrote:
> > Quoting Joonas Lahtinen (2017-08-29 15:54:06)
> > > On Tue, 2017-08-29 at 11:33 +0100, Chris Wilson wrote:
> > > > Since we hold the device wakeref when writing through the GTT (otherwise
> > > > the writes would fail), we presumed that before the device sleeps those
> > > > writes would naturally be flushed and that we wouldn't need our mmio
> > > > read trick. However, that presumption seems false and a sleepy bxt seems
> > > > to require us to always manually flush the GTT writes prior to direct
> > > > access.
> > > > 
> > > > Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before 
> > > > flushing GTT writes")
> > > > Signed-off-by: Chris Wilson 
> > > > Cc: Joonas Lahtinen 
> > > 
> > > Got any Bugzilla, Testcase, Tested-by?
> > 
> > Original bugzilla hasn't been reopened, so I its looks like they were
> > happy enough with the original patches that fixed the problem on my bxt.
> > The testcase seems to be very system dependent, my suspicion is that it
> > has to do with the wacky runtime pm exhibited by CI bxt.
> 
> CI bxt doesn't have displays, which means we shut down a lot more when
> it's running. Does this indicate a huge gem test gap where we should run
> plenty of gem testcases with all the outputs shut down?

This one is hard to tell since we are guessing at how the hw actually
works. Strong PCI ordering it is not.

If we take this example at face value, the key point of failure was
rpm_get_if_in_use, so we could simply say that we need to ensure that
all such branches are exercised, with varying amounts of stress since we
are looking for a random hw delay.

At the moment that boils down to the shrinker being avoiding unbinding
anything whilst the device is idle, pushing us closer to oom (with
kswapd hopefully riding to the rescue, and we all know how unreliable
kswapd is).

The wacky part of CI suspend seems to be that there's no reason for the
device to wake at times, quite a few of the tests are just burning
cycles without touching the hw and we still have the constant stream of
suspend/resume. I'm very suspicious that we are waking up too often (and
that it takes too long, about 28ms including the hpd of a headless
machine).

> Or just the need to add a pile more tests to pm_rpm?

No. It's just your regular combinatorial explosion. The approach I would
take here would be to register a sysenter callback that attempted to do a
rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
via the faultinjection framework) and then run the minimal test set that
exercises all ioctl paths, and then expand to all driver branches.

First we need coverage feedback.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Make own struct for execlist items

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Make own struct for execlist items
URL   : https://patchwork.freedesktop.org/series/29533/
State : failure

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252 +1

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1230 dwarn:0   dfail:0   fail:18  skip:982 
time:9620s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5536/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Chris Wilson (2017-08-30 13:56:40)
> Quoting Daniel Vetter (2017-08-30 13:23:56)
> > Or just the need to add a pile more tests to pm_rpm?
> 
> No. It's just your regular combinatorial explosion. The approach I would
> take here would be to register a sysenter callback that attempted to do a
> rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> via the faultinjection framework) and then run the minimal test set that
> exercises all ioctl paths, and then expand to all driver branches.

We also need the corollary that without rpm it works.
-Chris
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[Intel-gfx] [PATCH i-g-t v6] pm_rps: Changes in waitboost scenario

[Katarzyna Dec]

CI is observing sporadical failures in pm_rps subtests.
There are a couple of reasons. One of them is the fact that
on gen6, gen7 and gen7.5, max frequency (as in the HW limit)
is not set to RP0, but the value obtaind from PCODE (which
may be different from RP0). Thus the test is operating under
wrong assumptions (SOFTMAX == RP0 == BOOST which is simply
not the case). Let's compare current frequency with BOOST
frequency rather than SOFTMAX to get the test behaviour under control.
In boost_freq function I set MAX freq to midium freqency, which ensures
that we for sure reach BOOST frequency. This could help with failures
with boost frequency failing to drop down.
GPU reset needs to be modified so we are not dependent on kernel's low
priority retire worker. Reset method was replaced by igt_force_gpu_reset()
and in reset testcase we make sure that we can recover from hang.

v2: Commit message, simplified waiting for boost to finish, drop
noisy whitespace cleanup.

v3: Removed reading from i915_rps_boost_info debugfs because it not
the same on every kernel. Removed function waiting for boost.
Instead of that I made sure we will reach in boost by setting MAX freq to fmid.

v4: Moved proposal with making test drm master to other patch

v5: Used igt_force_gpu_reset() to reset GPU. Modified "reset" testcase.

v6: Comments changes and update.

Cc: Chris Wilson 
Cc: Jeff Mcgee 
Cc: Petri Latvala 
Cc: Jani Saarinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Radoslaw Szwichtenberg 
Acked-by: Daniel Vetter 
Signed-off-by: Katarzyna Dec 
---
 tests/pm_rps.c | 67 --
 1 file changed, 42 insertions(+), 25 deletions(-)

diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index f0455e78..f821c210 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -50,6 +50,7 @@ enum {
RP0,
RP1,
RPn,
+   BOOST,
NUMFREQ
 };
 
@@ -60,7 +61,7 @@ struct junk {
const char *mode;
FILE *filp;
 } stuff[] = {
-   { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { 
"RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, 
NULL }
+   { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { 
"RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { "boost", 
"rb+", NULL }, { NULL, NULL, NULL }
 };
 
 static int readval(FILE *filp)
@@ -167,7 +168,7 @@ static void dump(const int *freqs)
 }
 
 enum load {
-   LOW,
+   LOW = 0,
HIGH
 };
 
@@ -185,9 +186,10 @@ static struct load_helper {
 
 static void load_helper_signal_handler(int sig)
 {
-   if (sig == SIGUSR2)
-   lh.load = lh.load == LOW ? HIGH : LOW;
-   else
+   if (sig == SIGUSR2) {
+   lh.load = !lh.load;
+   igt_debug("Switching background load to %s\n", lh.load ? "high" 
: "low");
+   } else
lh.exit = true;
 }
 
@@ -238,6 +240,7 @@ static void load_helper_run(enum load load)
return;
}
 
+   lh.exit = false;
lh.load = load;
 
igt_fork_helper(&lh.igt_proc) {
@@ -263,6 +266,8 @@ static void load_helper_run(enum load load)
if (intel_gen(lh.devid) >= 6)
execbuf.flags = I915_EXEC_BLT;
 
+   igt_debug("Applying %s load...\n", lh.load ? "high" : "low");
+
while (!lh.exit) {
memset(&object, 0, sizeof(object));
object.handle = fences[val%3];
@@ -296,6 +301,12 @@ static void load_helper_run(enum load load)
gem_close(drm_fd, fences[0]);
gem_close(drm_fd, fences[1]);
gem_close(drm_fd, fences[2]);
+
+   /* Idle/boost logic is tide with request requirement.
+* Speed up detection of idle state and ensure deboost
+* after removing load.
+*/
+   igt_drop_caches_set(drm_fd, DROP_RETIRE);
}
 }
 
@@ -553,38 +564,43 @@ static void stabilize_check(int *out)
igt_debug("Waited %d msec to stabilize cur\n", wait);
 }
 
-static void reset_gpu(void)
-{
-   int fd = drm_open_driver(DRIVER_INTEL);
-   igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
-   close(fd);
-}
-
 static void boost_freq(int fd, int *boost_freqs)
 {
int64_t timeout = 1;
-   int ring = -1;
igt_spin_t *load;
+   unsigned int engine;
+   int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
 
-   load = igt_spin_batch_new(fd, ring, 0);
+   fmid = get_hw_rounded_freq(fmid);
+   /* set max freq to less then boost freq */
+   writeval(stuff[MAX].filp, fmid);
 
+   /* put boost on the same engine as low load */
+   engine = I915_EXEC_RENDER;
+   if (intel_gen(lh.devid) >= 6)
+   engine = I915_EXEC_BLT;
+   load = igt_spin_batch_new(fd, engine, 0);
/* Waiting will grant us a boost to maximum */
gem_wait(fd, load->ha

Re: [Intel-gfx] [PATCH 3/5] drm/atomic: Move drm_crtc_commit to drm_crtc_state, v2.

[Laurent Pinchart]

Hi Maarten,

Thank you for the patch.

On Wednesday, 30 August 2017 15:17:50 EEST Maarten Lankhorst wrote:
> Most code only cares about the current commit or previous commit.
> Fortuantely we already have a place to track those. Move it to
> drm_crtc_state where it belongs. :)
> 
> The per-crtc commit_list is kept for places where we have to look
> deeper than the current or previous commit for checking whether to stall
> on unpin. This is used in drm_atomic_helper_setup_commit and
> intel_has_pending_fb_unpin.
> 
> Changes since v1:
> - Update kerneldoc for drm_crtc.commit_list. (danvet)
> 
> Signed-off-by: Maarten Lankhorst 
> Reviewed-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/drm_atomic.c|  7 ---
>  drivers/gpu/drm/drm_atomic_helper.c | 92 +-
>  include/drm/drm_atomic.h|  1 -
>  include/drm/drm_crtc.h  | 23 --
>  4 files changed, 42 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2fd383d7253a..2cce48f203e0 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct
> drm_atomic_state *state) crtc->funcs->atomic_destroy_state(crtc,
> state->crtcs[i].state);
> 
> - if (state->crtcs[i].commit) {
> - kfree(state->crtcs[i].commit->event);
> - state->crtcs[i].commit->event = NULL;
> - drm_crtc_commit_put(state->crtcs[i].commit);
> - }
> -
> - state->crtcs[i].commit = NULL;
>   state->crtcs[i].ptr = NULL;
>   state->crtcs[i].state = NULL;
>   }
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index 11d0e94a2181..8ccb8b6536c0
> 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
>  void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
> struct drm_atomic_state *old_state)
>  {
> - struct drm_crtc_state *unused;
> + struct drm_crtc_state *new_crtc_state;
>   struct drm_crtc *crtc;
>   int i;
> 
> - for_each_new_crtc_in_state(old_state, crtc, unused, i) {
> - struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
> + for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
> + struct drm_crtc_commit *commit = new_crtc_state->commit;
>   int ret;
> 
>   if (!commit)
> @@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device
> *dev, {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *crtc_state;
> - struct drm_crtc_commit *commit;
>   struct drm_plane *__plane, *plane = NULL;
>   struct drm_plane_state *__plane_state, *plane_state = NULL;
>   const struct drm_plane_helper_funcs *funcs;
> - int i, j, n_planes = 0;
> + int i, n_planes = 0;
> 
>   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
>   if (drm_atomic_crtc_needs_modeset(crtc_state))
> @@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device
> *dev, return -EINVAL;
> 
>   /*
> -  * Don't do an async update if there is an outstanding commit modifying
> +  * TODO: Don't do an async update if there is an outstanding commit
> modifying
>* the plane.  This prevents our async update's changes from getting
>* overridden by a previous synchronous update's state.
>*/

As mentioned in a comment to your previous patch, this is unrelated to 
$SUBJECT. You should mention and explain this change in the commit message 
(possibly splitting it out in a separate commit if you think that would make 
more sense, up to you).

> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - if (plane->crtc != crtc)
> - continue;
> -
> - spin_lock(&crtc->commit_lock);
> - commit = list_first_entry_or_null(&crtc->commit_list,
> -   struct drm_crtc_commit,
> -   commit_entry);
> - if (!commit) {
> - spin_unlock(&crtc->commit_lock);
> - continue;
> - }
> - spin_unlock(&crtc->commit_lock);
> -
> - if (!crtc->state->state)
> - continue;
> -
> - for_each_plane_in_state(crtc->state->state, __plane,
> - __plane_state, j) {
> - if (__plane == plane)
> - return -EINVAL;
> - }
> - }
> 
>   return funcs->atomic_async_check(plane, plane_state);
>  }
> @@ -1731,7 +1707,7 @@ int drm_atomic_helper_setup_commit

Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Chris Wilson (2017-08-30 13:56:40)
> No. It's just your regular combinatorial explosion. The approach I would
> take here would be to register a sysenter callback that attempted to do a
> rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> via the faultinjection framework) and then run the minimal test set that
> exercises all ioctl paths, and then expand to all driver branches.

The simpler option is to apply the faultinjection to the rpm_put.
-Chris
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[Intel-gfx] [PATCH i-g-t v7] pm_rps: Changes in waitboost scenario

[Katarzyna Dec]

CI is observing sporadical failures in pm_rps subtests.
There are a couple of reasons. One of them is the fact that
on gen6, gen7 and gen7.5, max frequency (as in the HW limit)
is not set to RP0, but the value obtaind from PCODE (which
may be different from RP0). Thus the test is operating under
wrong assumptions (SOFTMAX == RP0 == BOOST which is simply
not the case). Let's compare current frequency with BOOST
frequency rather than SOFTMAX to get the test behaviour under control.
In boost_freq function I set MAX freq to midium freqency, which ensures
that we for sure reach BOOST frequency. This could help with failures
with boost frequency failing to drop down.
GPU reset needs to be modified so we are not dependent on kernel's low
priority retire worker. Reset method was replaced by igt_force_gpu_reset()
and in reset testcase we make sure that we can recover from hang.

v2: Commit message, simplified waiting for boost to finish, drop
noisy whitespace cleanup.

v3: Removed reading from i915_rps_boost_info debugfs because it not
the same on every kernel. Removed function waiting for boost.
Instead of that I made sure we will reach in boost by setting MAX freq to fmid.

v4: Moved proposal with making test drm master to other patch

v5: Used igt_force_gpu_reset() to reset GPU. Modified "reset" testcase.

v6: Comments changes and update.

v7: Fixing typos

Cc: Chris Wilson 
Cc: Jeff Mcgee 
Cc: Petri Latvala 
Cc: Jani Saarinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Radoslaw Szwichtenberg 
Acked-by: Daniel Vetter 
Signed-off-by: Katarzyna Dec 
---
 tests/pm_rps.c | 67 --
 1 file changed, 42 insertions(+), 25 deletions(-)

diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index f0455e78..7b5ab94f 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -50,6 +50,7 @@ enum {
RP0,
RP1,
RPn,
+   BOOST,
NUMFREQ
 };
 
@@ -60,7 +61,7 @@ struct junk {
const char *mode;
FILE *filp;
 } stuff[] = {
-   { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { 
"RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, 
NULL }
+   { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { 
"RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { "boost", 
"rb+", NULL }, { NULL, NULL, NULL }
 };
 
 static int readval(FILE *filp)
@@ -167,7 +168,7 @@ static void dump(const int *freqs)
 }
 
 enum load {
-   LOW,
+   LOW = 0,
HIGH
 };
 
@@ -185,9 +186,10 @@ static struct load_helper {
 
 static void load_helper_signal_handler(int sig)
 {
-   if (sig == SIGUSR2)
-   lh.load = lh.load == LOW ? HIGH : LOW;
-   else
+   if (sig == SIGUSR2) {
+   lh.load = !lh.load;
+   igt_debug("Switching background load to %s\n", lh.load ? "high" 
: "low");
+   } else
lh.exit = true;
 }
 
@@ -238,6 +240,7 @@ static void load_helper_run(enum load load)
return;
}
 
+   lh.exit = false;
lh.load = load;
 
igt_fork_helper(&lh.igt_proc) {
@@ -263,6 +266,8 @@ static void load_helper_run(enum load load)
if (intel_gen(lh.devid) >= 6)
execbuf.flags = I915_EXEC_BLT;
 
+   igt_debug("Applying %s load...\n", lh.load ? "high" : "low");
+
while (!lh.exit) {
memset(&object, 0, sizeof(object));
object.handle = fences[val%3];
@@ -296,6 +301,12 @@ static void load_helper_run(enum load load)
gem_close(drm_fd, fences[0]);
gem_close(drm_fd, fences[1]);
gem_close(drm_fd, fences[2]);
+
+   /* Idle/boost logic is tided with request retirement.
+* Speed up detection of idle state and ensure deboost
+* after removing load.
+*/
+   igt_drop_caches_set(drm_fd, DROP_RETIRE);
}
 }
 
@@ -553,38 +564,43 @@ static void stabilize_check(int *out)
igt_debug("Waited %d msec to stabilize cur\n", wait);
 }
 
-static void reset_gpu(void)
-{
-   int fd = drm_open_driver(DRIVER_INTEL);
-   igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
-   close(fd);
-}
-
 static void boost_freq(int fd, int *boost_freqs)
 {
int64_t timeout = 1;
-   int ring = -1;
igt_spin_t *load;
+   unsigned int engine;
+   int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
 
-   load = igt_spin_batch_new(fd, ring, 0);
+   fmid = get_hw_rounded_freq(fmid);
+   /* set max freq to less then boost freq */
+   writeval(stuff[MAX].filp, fmid);
 
+   /* put boost on the same engine as low load */
+   engine = I915_EXEC_RENDER;
+   if (intel_gen(lh.devid) >= 6)
+   engine = I915_EXEC_BLT;
+   load = igt_spin_batch_new(fd, engine, 0);
/* Waiting will grant us a boost to maximum */
gem

[Intel-gfx] ✓ Fi.CI.BAT: success for pm_rps: Changes in waitboost scenario (rev8)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev8)
URL   : https://patchwork.freedesktop.org/series/28966/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:365s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:551s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:525s
fi-byt-j1900 total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:529s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:517s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:437s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:447s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:428s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:432s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:480s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:525s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:470s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:483s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:446s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:507s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:555s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:406s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_124/
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Re: [Intel-gfx] [RFC PATCH 1/5] drm/i915: Always wait for flip_done

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:54:28PM +0200, Maarten Lankhorst wrote:
> Op 30-08-17 om 14:43 schreef Daniel Vetter:
> > On Wed, Aug 30, 2017 at 02:17:48PM +0200, Maarten Lankhorst wrote:
> >> The next commit removes the wait for flip_done in in
> >> drm_atomic_helper_commit_cleanup_done, but we need it for the tests
> >> to pass. Instead of using complicated vblank tracking which ends
> >> up being ignored anyway, call the correct atomic helper. :)
> >>
> >> RFC because I'm not completely sure what we want to do with the vblank 
> >> waiting,
> >> I think for now this patch is the right way to go until we decide because 
> >> it
> >> preserves the status quo when drm_crtc_commit was introduced.
> >>
> >> Signed-off-by: Maarten Lankhorst 
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h  |  3 +-
> >>  drivers/gpu/drm/i915/intel_display.c | 83 
> >> +++-
> >>  2 files changed, 8 insertions(+), 78 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> >> b/drivers/gpu/drm/i915/i915_drv.h
> >> index cbbafbfb0a55..de19621864a9 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -707,8 +707,7 @@ struct drm_i915_display_funcs {
> >>struct drm_atomic_state *old_state);
> >>void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
> >> struct drm_atomic_state *old_state);
> >> -  void (*update_crtcs)(struct drm_atomic_state *state,
> >> -   unsigned int *crtc_vblank_mask);
> >> +  void (*update_crtcs)(struct drm_atomic_state *state);
> >>void (*audio_codec_enable)(struct drm_connector *connector,
> >>   struct intel_encoder *encoder,
> >>   const struct drm_display_mode 
> >> *adjusted_mode);
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 52c73b4dabaa..3f3cb96aa11e 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -12114,73 +12114,10 @@ u32 intel_crtc_get_vblank_counter(struct 
> >> intel_crtc *crtc)
> >>return dev->driver->get_vblank_counter(dev, crtc->pipe);
> >>  }
> >>  
> >> -static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
> >> -struct drm_i915_private *dev_priv,
> >> -unsigned crtc_mask)
> >> -{
> >> -  unsigned last_vblank_count[I915_MAX_PIPES];
> >> -  enum pipe pipe;
> >> -  int ret;
> >> -
> >> -  if (!crtc_mask)
> >> -  return;
> >> -
> >> -  for_each_pipe(dev_priv, pipe) {
> >> -  struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> >> -pipe);
> >> -
> >> -  if (!((1 << pipe) & crtc_mask))
> >> -  continue;
> >> -
> >> -  ret = drm_crtc_vblank_get(&crtc->base);
> >> -  if (WARN_ON(ret != 0)) {
> >> -  crtc_mask &= ~(1 << pipe);
> >> -  continue;
> >> -  }
> >> -
> >> -  last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
> >> -  }
> >> -
> >> -  for_each_pipe(dev_priv, pipe) {
> >> -  struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> >> -pipe);
> >> -  long lret;
> >> -
> >> -  if (!((1 << pipe) & crtc_mask))
> >> -  continue;
> >> -
> >> -  lret = wait_event_timeout(dev->vblank[pipe].queue,
> >> -  last_vblank_count[pipe] !=
> >> -  drm_crtc_vblank_count(&crtc->base),
> >> -  msecs_to_jiffies(50));
> >> -
> >> -  WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
> >> -
> >> -  drm_crtc_vblank_put(&crtc->base);
> >> -  }
> >> -}
> >> -
> >> -static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
> >> -{
> >> -  /* fb updated, need to unpin old fb */
> >> -  if (crtc_state->fb_changed)
> >> -  return true;
> >> -
> >> -  /* wm changes, need vblank before final wm's */
> >> -  if (crtc_state->update_wm_post)
> >> -  return true;
> >> -
> >> -  if (crtc_state->wm.need_postvbl_update)
> >> -  return true;
> >> -
> >> -  return false;
> >> -}
> >> -
> >>  static void intel_update_crtc(struct drm_crtc *crtc,
> >>  struct drm_atomic_state *state,
> >>  struct drm_crtc_state *old_crtc_state,
> >> -struct drm_crtc_state *new_crtc_state,
> >> -unsigned int *crtc_vblank_mask)
> >> +struct drm_crtc_state *new_crtc_state)
> >>  {
> >>struct drm_device *dev = crtc->dev;
> >>struct drm_i915_private *dev_priv = to_i915(dev);
> >> @@ -12203,13 +12140,9 @@ static void intel_update_crtc(struct drm_crtc 
> >> *crt

Re: [Intel-gfx] [RFC PATCH 5/5] drm/atomic: Make async plane update checks work as intended.

[Daniel Vetter]

On Wed, Aug 30, 2017 at 02:53:43PM +0200, Maarten Lankhorst wrote:
> Op 30-08-17 om 14:46 schreef Daniel Vetter:
> > On Wed, Aug 30, 2017 at 02:17:52PM +0200, Maarten Lankhorst wrote:
> >> By always keeping track of the last commit in plane_state, we know
> >> whether there is an active update on the plane or not. With that
> >> information we can reject the fast update, and force the slowpath
> >> to be used as was originally intended.
> >>
> >> Cc: Gustavo Padovan 
> >> Signed-off-by: Maarten Lankhorst 
> > Makes sense, but I think like patch 1 it would be better to do this in a
> > separate series. Which would then include a patch to move i915 over to the
> > async plane support.
> >
> > One more comment below.
> >
> >> ---
> >>  drivers/gpu/drm/drm_atomic_helper.c  | 25 +++--
> >>  drivers/gpu/drm/i915/intel_display.c |  8 
> >>  include/drm/drm_plane.h  |  5 +++--
> >>  3 files changed, 22 insertions(+), 16 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> >> b/drivers/gpu/drm/drm_atomic_helper.c
> >> index 034f563fb130..384d99347bb3 100644
> >> --- a/drivers/gpu/drm/drm_atomic_helper.c
> >> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> >> @@ -1388,8 +1388,8 @@ int drm_atomic_helper_async_check(struct drm_device 
> >> *dev,
> >>  {
> >>struct drm_crtc *crtc;
> >>struct drm_crtc_state *crtc_state;
> >> -  struct drm_plane *__plane, *plane = NULL;
> >> -  struct drm_plane_state *__plane_state, *plane_state = NULL;
> >> +  struct drm_plane *plane;
> >> +  struct drm_plane_state *old_plane_state, *new_plane_state;
> >>const struct drm_plane_helper_funcs *funcs;
> >>int i, n_planes = 0;
> >>  
> >> @@ -1398,33 +1398,33 @@ int drm_atomic_helper_async_check(struct 
> >> drm_device *dev,
> >>return -EINVAL;
> >>}
> >>  
> >> -  for_each_new_plane_in_state(state, __plane, __plane_state, i) {
> >> +  for_each_oldnew_plane_in_state(state, plane, old_plane_state, 
> >> new_plane_state, i)
> >>n_planes++;
> >> -  plane = __plane;
> >> -  plane_state = __plane_state;
> >> -  }
> >>  
> >>/* FIXME: we support only single plane updates for now */
> >> -  if (!plane || n_planes != 1)
> >> +  if (n_planes != 1)
> >>return -EINVAL;
> >>  
> >> -  if (!plane_state->crtc)
> >> +  if (!new_plane_state->crtc)
> >>return -EINVAL;
> >>  
> >>funcs = plane->helper_private;
> >>if (!funcs->atomic_async_update)
> >>return -EINVAL;
> >>  
> >> -  if (plane_state->fence)
> >> +  if (new_plane_state->fence)
> >>return -EINVAL;
> >>  
> >>/*
> >> -   * TODO: Don't do an async update if there is an outstanding commit 
> >> modifying
> >> +   * Don't do an async update if there is an outstanding commit modifying
> >> * the plane.  This prevents our async update's changes from getting
> >> * overridden by a previous synchronous update's state.
> >> */
> >> +  if (old_plane_state->commit &&
> >> +  !try_wait_for_completion(&old_plane_state->commit->hw_done))
> >> +  return -EBUSY;
> > Instead of forcing us to always set the plane_state->commit pointer (bunch
> > of pointles refcounting), perhaps just check
> > plane_state->crtc->state->commit? We do hold the necessary locks to at
> > least look at that.
> Then we'd always take the slowpath?
> 
> The point here was to check whether the current plane was part of the
> most recent commit, to know this we must either add a flip_planes mask
> member to drm_crtc_commit, or add a pointer in plane_state to the most
> recent commit it was part of.

Hm right, that would block us against ongoing page_flips ... I guess
tracking commits at the plane level makes sense. If you can add that to
the commit message please, since otherwise I'll forget again?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: add GT number to intel_device_info

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 09:42:02PM +0100, Lionel Landwerlin wrote:
> Up to Coffeelake we could deduce this GT number from the device ID.
> This doesn't seem to be the case anymore. This change reorders pciids
> per GT and adds a gt field to intel_device_info. We set this field on
> the following platforms :
> 
>- SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL
> 
> v2: Add SNB & IVB (Chris)
> 
> v3: Fix compilation error in early-quirks (Lionel)
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |   1 +
>  drivers/gpu/drm/i915/i915_pci.c | 193 
> +++-
>  include/drm/i915_pciids.h   | 152 +++
>  3 files changed, 246 insertions(+), 100 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0383e879a315..3d417537bd59 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -842,6 +842,7 @@ struct intel_device_info {
>   u8 gen;
>   u16 gen_mask;
>   enum intel_platform platform;
> + u8 gt; /* GT number, 0 if undefined */
>   u8 ring_mask; /* Rings supported by the HW */
>   u8 num_rings;
>  #define DEFINE_FLAG(name) u8 name:1
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a1e6b696bcfa..0ac733baa734 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -224,15 +224,34 @@ static const struct intel_device_info 
> intel_ironlake_m_info = {
>   GEN_DEFAULT_PIPEOFFSETS, \
>   CURSOR_OFFSETS
>  
> -static const struct intel_device_info intel_sandybridge_d_info = {
> - GEN6_FEATURES,
> - .platform = INTEL_SANDYBRIDGE,
> +#define SNB_D_PLATFORM \
> + GEN6_FEATURES, \
> + .platform = INTEL_SANDYBRIDGE
> +
> +static const struct intel_device_info intel_sandybridge_d_gt1_info = {
> + SNB_D_PLATFORM,
> + .gt = 1,
>  };
>  
> -static const struct intel_device_info intel_sandybridge_m_info = {
> - GEN6_FEATURES,
> - .platform = INTEL_SANDYBRIDGE,
> - .is_mobile = 1,
> +static const struct intel_device_info intel_sandybridge_d_gt2_info = {
> + SNB_D_PLATFORM,
> + .gt = 2,
> +};
> +
> +#define SNB_M_PLATFORM \
> + GEN6_FEATURES, \
> + .platform = INTEL_SANDYBRIDGE, \
> + .is_mobile = 1
> +
> +
> +static const struct intel_device_info intel_sandybridge_m_gt1_info = {
> + SNB_M_PLATFORM,
> + .gt = 1,
> +};
> +
> +static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> + SNB_M_PLATFORM,
> + .gt = 2,
>  };
>  
>  #define GEN7_FEATURES  \
> @@ -249,22 +268,41 @@ static const struct intel_device_info 
> intel_sandybridge_m_info = {
>   GEN_DEFAULT_PIPEOFFSETS, \
>   IVB_CURSOR_OFFSETS
>  
> -static const struct intel_device_info intel_ivybridge_d_info = {
> - GEN7_FEATURES,
> - .platform = INTEL_IVYBRIDGE,
> - .has_l3_dpf = 1,
> +#define IVB_D_FEATURES \

FEATURES vs. PLATFORM seem to be used in an inconsistent manner.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 3/5] drm/atomic: Move drm_crtc_commit to drm_crtc_state, v2.

[Maarten Lankhorst]

Op 30-08-17 om 15:09 schreef Laurent Pinchart:
> Hi Maarten,
>
> Thank you for the patch.
>
> On Wednesday, 30 August 2017 15:17:50 EEST Maarten Lankhorst wrote:
>> Most code only cares about the current commit or previous commit.
>> Fortuantely we already have a place to track those. Move it to
>> drm_crtc_state where it belongs. :)
>>
>> The per-crtc commit_list is kept for places where we have to look
>> deeper than the current or previous commit for checking whether to stall
>> on unpin. This is used in drm_atomic_helper_setup_commit and
>> intel_has_pending_fb_unpin.
>>
>> Changes since v1:
>> - Update kerneldoc for drm_crtc.commit_list. (danvet)
>>
>> Signed-off-by: Maarten Lankhorst 
>> Reviewed-by: Daniel Vetter 
>> ---
>>  drivers/gpu/drm/drm_atomic.c|  7 ---
>>  drivers/gpu/drm/drm_atomic_helper.c | 92 +-
>>  include/drm/drm_atomic.h|  1 -
>>  include/drm/drm_crtc.h  | 23 --
>>  4 files changed, 42 insertions(+), 81 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
>> index 2fd383d7253a..2cce48f203e0 100644
>> --- a/drivers/gpu/drm/drm_atomic.c
>> +++ b/drivers/gpu/drm/drm_atomic.c
>> @@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(struct
>> drm_atomic_state *state) crtc->funcs->atomic_destroy_state(crtc,
>>state->crtcs[i].state);
>>
>> -if (state->crtcs[i].commit) {
>> -kfree(state->crtcs[i].commit->event);
>> -state->crtcs[i].commit->event = NULL;
>> -drm_crtc_commit_put(state->crtcs[i].commit);
>> -}
>> -
>> -state->crtcs[i].commit = NULL;
>>  state->crtcs[i].ptr = NULL;
>>  state->crtcs[i].state = NULL;
>>  }
>> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
>> b/drivers/gpu/drm/drm_atomic_helper.c index 11d0e94a2181..8ccb8b6536c0
>> 100644
>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>> @@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
>>  void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
>>struct drm_atomic_state *old_state)
>>  {
>> -struct drm_crtc_state *unused;
>> +struct drm_crtc_state *new_crtc_state;
>>  struct drm_crtc *crtc;
>>  int i;
>>
>> -for_each_new_crtc_in_state(old_state, crtc, unused, i) {
>> -struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
>> +for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
>> +struct drm_crtc_commit *commit = new_crtc_state->commit;
>>  int ret;
>>
>>  if (!commit)
>> @@ -1388,11 +1388,10 @@ int drm_atomic_helper_async_check(struct drm_device
>> *dev, {
>>  struct drm_crtc *crtc;
>>  struct drm_crtc_state *crtc_state;
>> -struct drm_crtc_commit *commit;
>>  struct drm_plane *__plane, *plane = NULL;
>>  struct drm_plane_state *__plane_state, *plane_state = NULL;
>>  const struct drm_plane_helper_funcs *funcs;
>> -int i, j, n_planes = 0;
>> +int i, n_planes = 0;
>>
>>  for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
>>  if (drm_atomic_crtc_needs_modeset(crtc_state))
>> @@ -1420,33 +1419,10 @@ int drm_atomic_helper_async_check(struct drm_device
>> *dev, return -EINVAL;
>>
>>  /*
>> - * Don't do an async update if there is an outstanding commit modifying
>> + * TODO: Don't do an async update if there is an outstanding commit
>> modifying
>>   * the plane.  This prevents our async update's changes from getting
>>   * overridden by a previous synchronous update's state.
>>   */
> As mentioned in a comment to your previous patch, this is unrelated to 
> $SUBJECT. You should mention and explain this change in the commit message 
> (possibly splitting it out in a separate commit if you think that would make 
> more sense, up to you).
I'm all for removing this, it doesn't work.. But I g uess it can be kept in for 
now and I'll drop this hunk.
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

On 30/08/17 14:41, Ville Syrjälä wrote:

On Tue, Aug 29, 2017 at 09:42:02PM +0100, Lionel Landwerlin wrote:

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

- SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_drv.h |   1 +
  drivers/gpu/drm/i915/i915_pci.c | 193 +++-
  include/drm/i915_pciids.h   | 152 +++
  3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
  #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..0ac733baa734 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
  
-static const struct intel_device_info intel_sandybridge_d_info = {

-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
  };
  
-static const struct intel_device_info intel_sandybridge_m_info = {

-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
  };
  
  #define GEN7_FEATURES  \

@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
  
-static const struct intel_device_info intel_ivybridge_d_info = {

-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_FEATURES \

FEATURES vs. PLATFORM seem to be used in an inconsistent manner.


Thanks, fixing it up.

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[Intel-gfx] ✓ Fi.CI.BAT: success for pm_rps: Changes in waitboost scenario (rev9)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev9)
URL   : https://patchwork.freedesktop.org/series/28966/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> INCOMPLETE (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:365s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:566s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:527s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:528s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:527s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:434s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:624s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:451s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:427s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:472s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:483s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:601s
fi-pnv-d510  total:156  pass:113  dwarn:0   dfail:0   fail:0   skip:42 
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:474s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:567s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:439s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:553s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:411s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_125/
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[Intel-gfx] [PATCH v4 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 152 +++
 3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..f56aa8e3890b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define IVB_M_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct intel_device_info intel_broadwell_info = {
+static const struct intel_device_info intel_broadwell_gt1_info = {

[Intel-gfx] [PATCH v4 0/3] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Inconsistencies noticed by Ville in patch 1.

Cheers,

Lionel Landwerlin (3):
  drm/i915: add GT number to intel_device_info
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 ++
 drivers/gpu/drm/i915/i915_pci.c   | 193 ++
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 152 --
 7 files changed, 407 insertions(+), 111 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] [PATCH v4 2/3] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v4 3/3] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_test_config_cflgt2(struct d

[Intel-gfx] [PATCH i-g-t] lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Paul Kocialkowski]

This removes the igt_require condition on the sysfs open call used to
write the suspend/resume delay so that it is allowed to fail. Intsead,
the code that depends on it is put in a conditional block.

This allows running test binaries as a non-privileged user for e.g.
listing the available tests with the SuspendResumeDelay parameter set
in igtrc configuration. Sysfs access would otherwise cause it to fail.

Signed-off-by: Paul Kocialkowski 
---
 lib/igt_aux.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index f428f159..d808fe3e 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -883,19 +883,21 @@ void igt_set_autoresume_delay(int delay_secs)
 
igt_skip_on_simulation();
 
-   igt_require((delay_fd = 
open("/sys/module/suspend/parameters/pm_test_delay",
-   O_RDWR)) >= 0);
+   delay_fd = open("/sys/module/suspend/parameters/pm_test_delay", O_RDWR);
+
+   if (delay_fd >= 0) {
+   if (!original_autoresume_delay) {
+   igt_require(read(delay_fd, delay_str,
+sizeof(delay_str)));
+   original_autoresume_delay = atoi(delay_str);
+   igt_install_exit_handler(igt_restore_autoresume_delay);
+   }
 
-   if (!original_autoresume_delay) {
-   igt_require(read(delay_fd, delay_str, sizeof(delay_str)));
-   original_autoresume_delay = atoi(delay_str);
-   igt_install_exit_handler(igt_restore_autoresume_delay);
-   }
+   snprintf(delay_str, sizeof(delay_str), "%d", delay_secs);
+   igt_require(write(delay_fd, delay_str, strlen(delay_str)));
 
-   snprintf(delay_str, sizeof(delay_str), "%d", delay_secs);
-   igt_require(write(delay_fd, delay_str, strlen(delay_str)));
-
-   close(delay_fd);
+   close(delay_fd);
+   }
 
autoresume_delay = delay_secs;
 }
-- 
2.14.0

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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Daniel Vetter]

On Wed, Aug 30, 2017 at 01:56:40PM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2017-08-30 13:23:56)
> > Or just the need to add a pile more tests to pm_rpm?
> 
> No. It's just your regular combinatorial explosion. The approach I would
> take here would be to register a sysenter callback that attempted to do a
> rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> via the faultinjection framework) and then run the minimal test set that
> exercises all ioctl paths, and then expand to all driver branches.
> 
> First we need coverage feedback.

What I meant to imply: As long as any display is on we will never rpm
suspend. Mostly this is the case for CI machines.

The new testcases I've had in mind would explicitly dpms off the display
before running a set of gem testcases. We don't want to do that everywhere
though, because a dpms on/off is very costly.

I guess once we switch (eventually, hopefully) to a binary-at-time model
for full igt CI we could amortize that over a pile of substests and do it
almost everywhere.

So I think adding a force rpm suspend won't help, because under normal CI
runs we can't ever get there becaus of the active display. And that's why
we're not hitting all these tons of problems anywhere else.

This might also be good reason for more server chips, or at least fake
server chips, where we disable the display entirely.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:24PM -0700, Rodrigo Vivi wrote:
> Let's decouple bxt, glk and cnl dp signal levels
> from other DDIs to avoid confusion.
> 
> No functional change. Only a reorg to avoid messing
> with currently working DP signal levels when
> moving voltage swing sequences around to match spec.
> 
> v2: ddi_signal_levels is also called from other ddi
> platforms, so don't remove IS_GEN9_BC check from
> skl_ddi_set_iboos. (Ville).
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 27 ++-
>  drivers/gpu/drm/i915/intel_dp.c  | 10 --
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  3 files changed, 23 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7e875e05d053..9a887780f99f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp 
> *intel_dp)
>   return translate_signal_level(signal_levels);
>  }
>  
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 bxt_signal_levels(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>   struct intel_encoder *encoder = &dport->base;
>   enum port port = dport->port;
> + u32 level = intel_ddi_dp_level(intel_dp);
> +
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
> + else
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +
> + return 0;
> +}
> +
> +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> + struct intel_encoder *encoder = &dport->base;
>   uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, level);
> - else if (IS_GEN9_LP(dev_priv))
> - bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> - else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_ddi_vswing_sequence(encoder, level);
> - /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> - return 0;
> - }
> + skl_ddi_set_iboost(encoder, level);

Tab got changed into spaces somehow.

With that fixed
Reviewed-by: Ville Syrjälä 

> +
>   return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d3e5fdf0d2fa..49a8c339b2b0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>   uint32_t signal_levels, mask = 0;
>   uint8_t train_set = intel_dp->train_set[0];
>  
> - if (HAS_DDI(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + signal_levels = bxt_signal_levels(intel_dp);
> + } else if (HAS_DDI(dev_priv)) {
>   signal_levels = ddi_signal_levels(intel_dp);
> -
> - if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> - signal_levels = 0;
> - else
> - mask = DDI_BUF_EMP_MASK;
> + mask = DDI_BUF_EMP_MASK;
>   } else if (IS_CHERRYVIEW(dev_priv)) {
>   signal_levels = chv_signal_levels(intel_dp);
>   } else if (IS_VALLEYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 17649f13091c..469c06000774 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state 
> *crtc_state,
>   bool state);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
>  
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Laurent Pinchart]

Hi Maarten,

Thank you for the patch.

On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> Currently we neatly track the crtc state, but forget to look at
> plane/connector state.
> 
> When doing a nonblocking modeset, immediately followed by a setprop
> before the modeset completes, the setprop will see the modesets new
> state as the old state and free it.
> 
> This has to be solved by waiting for hw_done on the connector, even
> if it's not assigned to a crtc. When a connector is unbound we take
> the last crtc commit, and when it stays unbound we create a new
> fake crtc commit for that gets signaled on hw_done for all the
> planes/connectors.
> 
> We wait for it the same way as we do for crtc's, which will make
> sure we never run into a use-after-free situation.
> 
> Changes since v1:
> - Only create a single disable commit. (danvet)
> - Fix leak in intel_legacy_cursor_update.
> 
> Signed-off-by: Maarten Lankhorst 
> Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> Cc: Laurent Pinchart 
> ---
>  drivers/gpu/drm/drm_atomic.c |   4 +
>  drivers/gpu/drm/drm_atomic_helper.c  | 156 ++--
>  drivers/gpu/drm/i915/intel_display.c |   2 +
>  include/drm/drm_atomic.h |  12 +++
>  include/drm/drm_connector.h  |   7 ++
>  include/drm/drm_plane.h  |   7 ++
>  6 files changed, 182 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2cce48f203e0..75f5f74de9bf 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> drm_atomic_state *state) }
>   state->num_private_objs = 0;
> 
> + if (state->fake_commit) {
> + drm_crtc_commit_put(state->fake_commit);
> + state->fake_commit = NULL;
> + }
>  }
>  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> *completion) drm_crtc_commit_put(commit);
>  }
> 
> +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> *crtc)
> +{

You could allocate the commit in this function too, the kzalloc() is currently 
duplicated. The function should probably be called alloc_commit() then.

> + init_completion(&commit->flip_done);
> + init_completion(&commit->hw_done);
> + init_completion(&commit->cleanup_done);
> + INIT_LIST_HEAD(&commit->commit_entry);
> + kref_init(&commit->ref);
> + commit->crtc = crtc;
> +}
> +
> +static struct drm_crtc_commit *
> +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> +{
> + struct drm_crtc_commit *commit;
> +
> + if (crtc) {
> + struct drm_crtc_state *new_crtc_state;
> +
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> +
> + commit = new_crtc_state->commit;
> + } else if (!state->fake_commit) {
> + state->fake_commit = commit = kzalloc(sizeof(*commit), 
> GFP_KERNEL);
> + if (!commit)
> + return NULL;
> +
> + init_commit(commit, NULL);
> + } else
> + commit = state->fake_commit;
> +
> + drm_crtc_commit_get(commit);

I believe the reference counting is right. The double reference in the second 
case (kref_init() when initializing the commit and drm_crtc_commit_get()) 
should not cause a leak. The kref_init() takes a reference to store the commit 
in state->fake_commit, released in drm_atomic_state_default_clear(), and the 
drm_crtc_commit_get() takes a reference returned by the function, stored in 
new_*_state->commit by the caller.

This being said, I think the reference counting is confusing, as proved by 
Daniel thinking there was a leak here (or by me thinking there's no leak while 
there's one :-)). To make the implementation clearer, I propose turning the 
definition of drm_crtc_commit_get() to

static inline struct drm_crtc_commit *
drm_crtc_commit_get(struct drm_crtc_commit *commit)
{
kref_get(&commit->ref);
return commit;
}

and writing this function as

/* Return a new reference to the commit object */
static struct drm_crtc_commit *
fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
struct drm_crtc_commit *commit;

if (crtc) {
struct drm_crtc_state *new_crtc_state;

new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

commit = new_crtc_state->commit;
} else {
if (!state->fake_commit)
state->fake_commit = alloc_commit(NULL);

commit = state->fake_commit;
}

return d

Re: [Intel-gfx] [PATCH 5/8] drm/i915/cnl: Move voltage check into ddi buf trans functions.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:27PM -0700, Rodrigo Vivi wrote:
> Let's start converging CNL buf translations to same style
> used on previous platforms. So first thing is to use the
> standard signature so we don't need to propagate the voltage
> check into other parts of the code, but only on the parts
> that it is really useful.
> 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 48 
> ++--
>  1 file changed, 21 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 506782c1a62a..7b547a7f6c2b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1830,9 +1830,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> -u32 voltage, int *n_entries)
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

I wonder if we should just cache that somewhere. My main worry is
whether the device is always awake when we call this code.

> +
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
>   return cnl_ddi_translations_hdmi_0_85V;
> @@ -1842,14 +1843,16 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
>   return cnl_ddi_translations_hdmi_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);

nit: Looks like these if ladders could be turned into switch statements.


Anyways, patch lgtm
Reviewed-by: Ville Syrjälä 

>   return NULL;
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> -  u32 voltage, int *n_entries)
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
>   return cnl_ddi_translations_dp_0_85V;
> @@ -1859,14 +1862,16 @@ cnl_get_buf_trans_dp(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
>   return cnl_ddi_translations_dp_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);
>   return NULL;
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> -   u32 voltage, int *n_entries)
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
>   if (dev_priv->vbt.edp.low_vswing) {
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> @@ -1877,10 +1882,11 @@ cnl_get_buf_trans_edp(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
>   return cnl_ddi_translations_edp_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);
>   return NULL;
>   } else {
> - return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
> + return cnl_get_buf_trans_dp(dev_priv, n_entries);
>   }
>  }
>  
> @@ -1888,31 +1894,19 @@ static void cnl_ddi_vswing_program(struct 
> drm_i915_private *dev_priv,
>   u32 level, enum port port, int type)
>  {
>   const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> - u32 n_entries, val, voltage;
> + u32 n_entries, val;
>   int ln;
>  
> - /*
> -  * Values for each port type are listed in
> -  * voltage swing programming tables.
> -  * Vccio voltage found in PORT_COMP_DW3.
> -  */
> - voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
>   if (type == INTEL_OUTPUT_HDMI) {
> - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
> -   voltage, &n_entries);
> + ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
>   } else if (type == INTEL_OUTPUT_DP) {
> - ddi_translations = cnl_get_buf_trans_dp(dev_priv,
> - voltage, &n_entries);
> + ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
>   } else if (type == INTEL_OUTPUT_EDP) {
> -   

Re: [Intel-gfx] [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:29PM -0700, Rodrigo Vivi wrote:
> Let's get a proper HDMI DDI entry level for vswing programming
> sequences on CNL.
> 
> Spec doesn't specify any default for HDMI tables,
> so let's pick the last entry as the default for now.
> 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 3ce02cbd4483..f1757a8e481a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -660,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private 
> *dev_priv, enum port por
>   if (IS_GEN9_LP(dev_priv))
>   return hdmi_level;
>  
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
> + hdmi_default_entry = n_hdmi_entries - 1;

Hmm. I guess we might try to do the same thing for BXT, for extra
consistency. But that's a separate issue.

Reviewed-by: Ville Syrjälä 

> + } else if (IS_GEN9_BC(dev_priv)) {
>   skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
>   hdmi_default_entry = 8;
>   } else if (IS_BROADWELL(dev_priv)) {
> -- 
> 2.13.2
> 
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:30PM -0700, Rodrigo Vivi wrote:
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 35 +++
>  1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f1757a8e481a..97ff082c28a7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static int cnl_max_level(struct drm_i915_private *dev_priv,
> +  enum intel_output_type type)
> +{
> + int n_entries = 0;
> +
> + switch (type) {
> + case INTEL_OUTPUT_DP:
> + cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + break;
> + case INTEL_OUTPUT_EDP:
> + cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + break;
> + case INTEL_OUTPUT_HDMI:
> + cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + break;
> + default:
> + MISSING_CASE(type);
> + return 0;
> + }
> +
> + return n_entries - 1;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1879,10 +1902,14 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   int n_entries;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_max_level(dev_priv, encoder->type);

You're not actually using the return value. Also the return value has -1
already applied, whereas here we just need the n_entries w/o -1.

> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> + }
>  
>   if (WARN_ON(n_entries < 1))
>   n_entries = 1;
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce intel_ddi_dp_level.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:23PM -0700, Rodrigo Vivi wrote:
> No functional changes. This only moves the DP level
> selection to a separated function that will be later
> used to organize better the vswing sequences.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0a316a6ccb50..7e875e05d053 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2054,18 +2054,22 @@ static uint32_t translate_signal_level(int 
> signal_levels)
>   return 0;
>  }
>  
> +static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
> +{
> + uint8_t train_set = intel_dp->train_set[0];
> + int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> +  DP_TRAIN_PRE_EMPHASIS_MASK);
> +
> + return translate_signal_level(signal_levels);
> +}
> +
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>   struct intel_encoder *encoder = &dport->base;
> - uint8_t train_set = intel_dp->train_set[0];
> - int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> -  DP_TRAIN_PRE_EMPHASIS_MASK);
>   enum port port = dport->port;
> - uint32_t level;
> -
> - level = translate_signal_level(signal_levels);
> + uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   if (IS_GEN9_BC(dev_priv))
>   skl_ddi_set_iboost(encoder, level);
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Align vswing sequences with old ddi buffer registers.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:25PM -0700, Rodrigo Vivi wrote:
> Vswing sequences on BXT and CNL are equivalent
> to the ddi buffer registers setting on other platforms.
> 
> For some reason it got aligned with skl_ddi_set_iboost what
> is semantically incorrect. This forced us to keep skipping
> ddi buffer translation tables on the platforms that has
> the vswing sequences.
> 
> v2: Don't mess with DP signal levels on this patch.
> 
> Cc: Vandana Kannan 
> Cc: Imre Deak 
> Cc: Ville Syrjälä 
> Cc: Ander Conselvan de Oliveira 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 22 ++
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a887780f99f..eedd29487e0b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct 
> intel_encoder *encoder)
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   const struct ddi_buf_trans *ddi_translations;
>  
> - if (IS_GEN9_LP(dev_priv))
> - return;
> -
>   switch (encoder->type) {
>   case INTEL_OUTPUT_EDP:
>   ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
> @@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
> intel_encoder *encoder)
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   const struct ddi_buf_trans *ddi_translations_hdmi;
>  
> - if (IS_GEN9_LP(dev_priv))
> - return;
> -
>   hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
>  
>   if (IS_GEN9_BC(dev_priv)) {
> @@ -2154,7 +2148,9 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - intel_prepare_dp_ddi_buffers(encoder);
> + if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
> + intel_prepare_dp_ddi_buffers(encoder);
> +
>   intel_ddi_init_dp_buf_reg(encoder);
>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
> @@ -2180,14 +2176,16 @@ static void intel_ddi_pre_enable_hdmi(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - intel_prepare_hdmi_ddi_buffers(encoder);
> - if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, level);
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
>   else if (IS_GEN9_LP(dev_priv))
>   bxt_ddi_vswing_sequence(dev_priv, level, port,
>   INTEL_OUTPUT_HDMI);
> - else if (IS_CANNONLAKE(dev_priv))
> - cnl_ddi_vswing_sequence(encoder, level);
> + else
> + intel_prepare_hdmi_ddi_buffers(encoder);
> +
> + if (IS_GEN9_BC(dev_priv))
> + skl_ddi_set_iboost(encoder, level);
>  
>   intel_dig_port->set_infoframes(&encoder->base,
>  has_infoframe,
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Daniel Vetter]

On Wed, Aug 30, 2017 at 05:10:43PM +0300, Laurent Pinchart wrote:
> Hi Maarten,
> 
> Thank you for the patch.
> 
> On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> > Currently we neatly track the crtc state, but forget to look at
> > plane/connector state.
> > 
> > When doing a nonblocking modeset, immediately followed by a setprop
> > before the modeset completes, the setprop will see the modesets new
> > state as the old state and free it.
> > 
> > This has to be solved by waiting for hw_done on the connector, even
> > if it's not assigned to a crtc. When a connector is unbound we take
> > the last crtc commit, and when it stays unbound we create a new
> > fake crtc commit for that gets signaled on hw_done for all the
> > planes/connectors.
> > 
> > We wait for it the same way as we do for crtc's, which will make
> > sure we never run into a use-after-free situation.
> > 
> > Changes since v1:
> > - Only create a single disable commit. (danvet)
> > - Fix leak in intel_legacy_cursor_update.
> > 
> > Signed-off-by: Maarten Lankhorst 
> > Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> > Cc: Laurent Pinchart 
> > ---
> >  drivers/gpu/drm/drm_atomic.c |   4 +
> >  drivers/gpu/drm/drm_atomic_helper.c  | 156 ++--
> >  drivers/gpu/drm/i915/intel_display.c |   2 +
> >  include/drm/drm_atomic.h |  12 +++
> >  include/drm/drm_connector.h  |   7 ++
> >  include/drm/drm_plane.h  |   7 ++
> >  6 files changed, 182 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 2cce48f203e0..75f5f74de9bf 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> > drm_atomic_state *state) }
> > state->num_private_objs = 0;
> > 
> > +   if (state->fake_commit) {
> > +   drm_crtc_commit_put(state->fake_commit);
> > +   state->fake_commit = NULL;
> > +   }
> >  }
> >  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> > 
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> > 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> > *completion) drm_crtc_commit_put(commit);
> >  }
> > 
> > +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> > *crtc)
> > +{
> 
> You could allocate the commit in this function too, the kzalloc() is 
> currently 
> duplicated. The function should probably be called alloc_commit() then.
> 
> > +   init_completion(&commit->flip_done);
> > +   init_completion(&commit->hw_done);
> > +   init_completion(&commit->cleanup_done);
> > +   INIT_LIST_HEAD(&commit->commit_entry);
> > +   kref_init(&commit->ref);
> > +   commit->crtc = crtc;
> > +}
> > +
> > +static struct drm_crtc_commit *
> > +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> > +{
> > +   struct drm_crtc_commit *commit;
> > +
> > +   if (crtc) {
> > +   struct drm_crtc_state *new_crtc_state;
> > +
> > +   new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > +
> > +   commit = new_crtc_state->commit;
> > +   } else if (!state->fake_commit) {
> > +   state->fake_commit = commit = kzalloc(sizeof(*commit), 
> > GFP_KERNEL);
> > +   if (!commit)
> > +   return NULL;
> > +
> > +   init_commit(commit, NULL);
> > +   } else
> > +   commit = state->fake_commit;
> > +
> > +   drm_crtc_commit_get(commit);
> 
> I believe the reference counting is right. The double reference in the second 
> case (kref_init() when initializing the commit and drm_crtc_commit_get()) 
> should not cause a leak. The kref_init() takes a reference to store the 
> commit 
> in state->fake_commit, released in drm_atomic_state_default_clear(), and the 
> drm_crtc_commit_get() takes a reference returned by the function, stored in 
> new_*_state->commit by the caller.
> 
> This being said, I think the reference counting is confusing, as proved by 
> Daniel thinking there was a leak here (or by me thinking there's no leak 
> while 
> there's one :-)). To make the implementation clearer, I propose turning the 
> definition of drm_crtc_commit_get() to
> 
> static inline struct drm_crtc_commit *
> drm_crtc_commit_get(struct drm_crtc_commit *commit)
> {
>   kref_get(&commit->ref);
>   return commit;
> }
> 
> and writing this function as
> 
> /* Return a new reference to the commit object */
> static struct drm_crtc_commit *
> fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> {
>   struct drm_crtc_commit *commit;
> 
>   if (crtc) {
>   struct drm_crtc_state *new_crtc_state;
> 
>   new_crtc_state = drm_atomic_get_

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:26PM -0700, Rodrigo Vivi wrote:
> Sequences for DisplayPort asks us to
> " Configure voltage swing and related IO settings.
> Refer to DDI Buffer section."
> 
> before "Configure and enable DDI_BUF_CTL"
> 
> On BXT and CNL this means to execute the ddi vswing sequences.
> 
> At this point these sequences calls are getting duplicated for DP
> because they are all called from DP link trainning sequences.
> 
> However this patch is not yet removing it before a futher discussion
> since spec also allows that during link training without disabling
> anything:
> 
> "
> Notes
> Changing voltage swing during link training:
> Change the swing setting following the DDI Buffer section.
> The port does not need to be disabled.
> "
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 

Imre is out atm so we didn't get his opinion, but I'm fine with this so
Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index eedd29487e0b..506782c1a62a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2136,6 +2136,7 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
>  
> @@ -2148,7 +2149,11 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
> + else if (IS_GEN9_LP(dev_priv))
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> + else
>   intel_prepare_dp_ddi_buffers(encoder);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 6/8] drm/i915/cnl: Move ddi buf trans related functions up.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:28PM -0700, Rodrigo Vivi wrote:
> No functional changes. But those functions will be needed
> to get max level for HDMI and DP, so let's move those
> up closer to other similar functions existent for previous
> platforms.
> 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 122 
> +++
>  1 file changed, 61 insertions(+), 61 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7b547a7f6c2b..3ce02cbd4483 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_private 
> *dev_priv, int *n_entries)
>   }
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> + return cnl_ddi_translations_hdmi_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> + return cnl_ddi_translations_hdmi_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> + return cnl_ddi_translations_hdmi_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> + return cnl_ddi_translations_dp_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
> + return cnl_ddi_translations_dp_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
> + return cnl_ddi_translations_dp_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (dev_priv->vbt.edp.low_vswing) {
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> + return cnl_ddi_translations_edp_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
> + return cnl_ddi_translations_edp_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
> + return cnl_ddi_translations_edp_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> + } else {
> + return cnl_get_buf_trans_dp(dev_priv, n_entries);
> + }
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1829,67 +1890,6 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> -static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> -{
> - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> - if (voltage == VOLTAGE_INFO_0_85V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> - return cnl_ddi_translations_hdmi_0_85V;
> - } else if (voltage == VOLTAGE_INFO_0_95V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> - return cnl_ddi_translations_hdmi_0_95V;
> - } else if (voltage == VOLTAGE_INFO_1_05V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> - return cnl_ddi_translations_hdmi_1_05V;
> - } else
> - MISSING_CASE(voltage);
> - return NULL;
> -}
> -
> -static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> -{
> - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> - if (voltage == VOLTAGE_INFO_0_85V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> - return cnl_ddi_translations_dp_0_85V;
> - } else if (voltage == VOLTAGE_INFO_0_95V) {
> -   

Re: [Intel-gfx] [PATCH 8/8] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:30PM -0700, Rodrigo Vivi wrote:
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 35 +++
>  1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f1757a8e481a..97ff082c28a7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static int cnl_max_level(struct drm_i915_private *dev_priv,
> +  enum intel_output_type type)
> +{
> + int n_entries = 0;
> +
> + switch (type) {
> + case INTEL_OUTPUT_DP:

These encoder->type checks are a bit problematic due to the DDI encoder
type changing dynamically. But to fix that I thunk I'll just need to
resurrect my old patches to get rid of that type changing. But I'll
wait until you cand land these since I need to rebase my stuff anyway.

> + cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + break;
> + case INTEL_OUTPUT_EDP:
> + cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + break;
> + case INTEL_OUTPUT_HDMI:
> + cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + break;
> + default:
> + MISSING_CASE(type);
> + return 0;
> + }
> +
> + return n_entries - 1;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1879,10 +1902,14 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   int n_entries;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_max_level(dev_priv, encoder->type);
> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> + }
>  
>   if (WARN_ON(n_entries < 1))
>   n_entries = 1;
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29547/
State : success

== Summary ==

Series 29547v1 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29547/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:550s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:251s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:521s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:484s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:483s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
fe9806b8b6e4 drm/i915/perf: add support for Coffeelake GT2
53483bc14c61 drm/i915: rework IS_*_GT* macros
72dd9b082ec1 drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5539/
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Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Laurent Pinchart]

On Wednesday, 30 August 2017 17:17:36 EEST Daniel Vetter wrote:
> On Wed, Aug 30, 2017 at 05:10:43PM +0300, Laurent Pinchart wrote:
> > Hi Maarten,
> > 
> > Thank you for the patch.
> > 
> > On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> > > Currently we neatly track the crtc state, but forget to look at
> > > plane/connector state.
> > > 
> > > When doing a nonblocking modeset, immediately followed by a setprop
> > > before the modeset completes, the setprop will see the modesets new
> > > state as the old state and free it.
> > > 
> > > This has to be solved by waiting for hw_done on the connector, even
> > > if it's not assigned to a crtc. When a connector is unbound we take
> > > the last crtc commit, and when it stays unbound we create a new
> > > fake crtc commit for that gets signaled on hw_done for all the
> > > planes/connectors.
> > > 
> > > We wait for it the same way as we do for crtc's, which will make
> > > sure we never run into a use-after-free situation.
> > > 
> > > Changes since v1:
> > > - Only create a single disable commit. (danvet)
> > > - Fix leak in intel_legacy_cursor_update.
> > > 
> > > Signed-off-by: Maarten Lankhorst 
> > > Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> > > Cc: Laurent Pinchart 
> > > ---
> > > 
> > >  drivers/gpu/drm/drm_atomic.c |   4 +
> > >  drivers/gpu/drm/drm_atomic_helper.c  | 156
> > >  ++--
> > >  drivers/gpu/drm/i915/intel_display.c |   2 +
> > >  include/drm/drm_atomic.h |  12 +++
> > >  include/drm/drm_connector.h  |   7 ++
> > >  include/drm/drm_plane.h  |   7 ++
> > >  6 files changed, 182 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > > index 2cce48f203e0..75f5f74de9bf 100644
> > > --- a/drivers/gpu/drm/drm_atomic.c
> > > +++ b/drivers/gpu/drm/drm_atomic.c
> > > @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> > > drm_atomic_state *state) }
> > > 
> > >   state->num_private_objs = 0;
> > > 
> > > + if (state->fake_commit) {
> > > + drm_crtc_commit_put(state->fake_commit);
> > > + state->fake_commit = NULL;
> > > + }
> > > 
> > >  }
> > >  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> > > 
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> > > 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> > > *completion) drm_crtc_commit_put(commit);
> > > 
> > >  }
> > > 
> > > +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> > > *crtc)
> > > +{
> > 
> > You could allocate the commit in this function too, the kzalloc() is
> > currently duplicated. The function should probably be called
> > alloc_commit() then.> 
> > > + init_completion(&commit->flip_done);
> > > + init_completion(&commit->hw_done);
> > > + init_completion(&commit->cleanup_done);
> > > + INIT_LIST_HEAD(&commit->commit_entry);
> > > + kref_init(&commit->ref);
> > > + commit->crtc = crtc;
> > > +}
> > > +
> > > +static struct drm_crtc_commit *
> > > +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc
> > > *crtc)
> > > +{
> > > + struct drm_crtc_commit *commit;
> > > +
> > > + if (crtc) {
> > > + struct drm_crtc_state *new_crtc_state;
> > > +
> > > + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > > +
> > > + commit = new_crtc_state->commit;
> > > + } else if (!state->fake_commit) {
> > > + state->fake_commit = commit = kzalloc(sizeof(*commit), 
GFP_KERNEL);
> > > + if (!commit)
> > > + return NULL;
> > > +
> > > + init_commit(commit, NULL);
> > > + } else
> > > + commit = state->fake_commit;
> > > +
> > > + drm_crtc_commit_get(commit);
> > 
> > I believe the reference counting is right. The double reference in the
> > second case (kref_init() when initializing the commit and
> > drm_crtc_commit_get()) should not cause a leak. The kref_init() takes a
> > reference to store the commit in state->fake_commit, released in
> > drm_atomic_state_default_clear(), and the drm_crtc_commit_get() takes a
> > reference returned by the function, stored in new_*_state->commit by the
> > caller.
> > 
> > This being said, I think the reference counting is confusing, as proved by
> > Daniel thinking there was a leak here (or by me thinking there's no leak
> > while there's one :-)). To make the implementation clearer, I propose
> > turning the definition of drm_crtc_commit_get() to
> > 
> > static inline struct drm_crtc_commit *
> > drm_crtc_commit_get(struct drm_crtc_commit *commit)
> > {
> > 
> > kref_get(&commit->ref);
> > return commit;
> > 
> > }
> > 
> > and writing this function as
> > 
> > /* Return a new reference to the commit object

[Intel-gfx] [PATCH i-g-t] lib/tests: Add audio selftest

[Paul Kocialkowski]

This introduces a selftest for the audio library.

It consists of generating a signal from a list of frequencies and
ensuring that the integrity checking function does detect these
frequencies (and only these frequencies).

Signed-off-by: Paul Kocialkowski 
---
 lib/tests/Makefile.am  |  2 +-
 lib/tests/Makefile.sources |  5 
 lib/tests/igt_audio.c  | 57 ++
 3 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 lib/tests/igt_audio.c

diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
index 5d14194a..b1caa628 100644
--- a/lib/tests/Makefile.am
+++ b/lib/tests/Makefile.am
@@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
-DIGT_DATADIR=\""$(abs_srcdir)"\" \
$(NULL)
 
-LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
$(TIMER_LIBS)
+LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(GSL_CFLAGS) 
$(LIBUNWIND_LIBS) $(TIMER_LIBS)
 
 LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) -lm
 AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
diff --git a/lib/tests/Makefile.sources b/lib/tests/Makefile.sources
index 8d1a8dea..eb702844 100644
--- a/lib/tests/Makefile.sources
+++ b/lib/tests/Makefile.sources
@@ -18,6 +18,11 @@ check_prog_list = \
igt_can_fail_simple \
$(NULL)
 
+#if HAVE_GSL
+check_prog_list += \
+   igt_audio
+#endif
+
 TESTS = \
$(check_prog_list) \
$(check_script_list) \
diff --git a/lib/tests/igt_audio.c b/lib/tests/igt_audio.c
new file mode 100644
index ..2354d5a0
--- /dev/null
+++ b/lib/tests/igt_audio.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt_core.h"
+#include "igt_audio.h"
+
+static int test_frequencies[] = {
+   300,
+   600,
+   1200,
+   8,
+   1,
+};
+
+static int test_frequencies_count = sizeof(test_frequencies) / sizeof(int);
+
+igt_simple_main
+{
+   short buffer[2 * 1024];
+   struct audio_signal *signal;
+   int i;
+
+   signal = audio_signal_init(2, 44800);
+   igt_assert(signal);
+
+   for (i = 0; i < test_frequencies_count; i++)
+   audio_signal_add_frequency(signal, test_frequencies[i]);
+
+   audio_signal_synthesize(signal);
+   audio_signal_fill(signal, buffer, 1024);
+
+   igt_assert(audio_signal_detect(signal, 2, 44800, buffer, 1024));
+
+   audio_signal_clean(signal);
+   free(signal);
+}
-- 
2.14.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Patchwork]

== Series Details ==

Series: lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay
URL   : https://patchwork.freedesktop.org/series/29549/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:565s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:527s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:524s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:519s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:438s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:617s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:447s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:482s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:595s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:532s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:482s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:543s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:448s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:407s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_126/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for pm_rps: Changes in waitboost scenario (rev9)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev9)
URL   : https://patchwork.freedesktop.org/series/28966/
State : warning

== Summary ==

Test pm_rps:
Subgroup reset:
fail   -> PASS   (shard-hsw) fdo#102250 +1
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw) fdo#102249
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-B-planes:
pass   -> SKIP   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_plane_lowres:
Subgroup pipe-A-tiling-none:
pass   -> SKIP   (shard-hsw)
Test kms_fbc_crc:
Subgroup page_flip_and_mmap_cpu:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453

fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453

shard-hswtotal:2265 pass:1227 dwarn:1   dfail:0   fail:17  skip:1020 
time:9512s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_125/shards.html
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Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: rework IS_*_GT* macros

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 21:42:03)
> We can now make use of the intel_device_info.gt field.
> 
> Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/tests: Add audio selftest

[Patchwork]

== Series Details ==

Series: lib/tests: Add audio selftest
URL   : https://patchwork.freedesktop.org/series/29550/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:362s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:567s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:534s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:529s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:513s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:439s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:616s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:448s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:429s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:428s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:497s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:477s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:599s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:603s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:528s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:472s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:452s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:544s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:410s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_127/
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: add GT number to intel_device_info

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 21:42:02)
> Up to Coffeelake we could deduce this GT number from the device ID.
> This doesn't seem to be the case anymore. This change reorders pciids
> per GT and adds a gt field to intel_device_info. We set this field on
> the following platforms :
> 
>- SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL
> 
> v2: Add SNB & IVB (Chris)
> 
> v3: Fix compilation error in early-quirks (Lionel)
> 
> Signed-off-by: Lionel Landwerlin 

The pci ids and tables motions looks ok, so
Reviewed-by: Chris Wilson 
on that part.

Can you do a
/sbin/modinfo drivers/gpu/drm/i915/i915.ko  | grep ^alias: | wc -l
before/after just to make sure.

Bonus points for marking up all the structs with __initdata
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Daniel Vetter (2017-08-30 14:59:32)
> On Wed, Aug 30, 2017 at 01:56:40PM +0100, Chris Wilson wrote:
> > Quoting Daniel Vetter (2017-08-30 13:23:56)
> > > Or just the need to add a pile more tests to pm_rpm?
> > 
> > No. It's just your regular combinatorial explosion. The approach I would
> > take here would be to register a sysenter callback that attempted to do a
> > rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> > via the faultinjection framework) and then run the minimal test set that
> > exercises all ioctl paths, and then expand to all driver branches.
> > 
> > First we need coverage feedback.
> 
> What I meant to imply: As long as any display is on we will never rpm
> suspend. Mostly this is the case for CI machines.
> 
> The new testcases I've had in mind would explicitly dpms off the display
> before running a set of gem testcases. We don't want to do that everywhere
> though, because a dpms on/off is very costly.

If no userspace is using the display and we remove fbcon, shouldn't the
kernel be disabling the outputs anyway? There's literally nothing there
to provide display continuity.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29547/
State : warning

== Summary ==

Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_mmio_vs_cs_flip:
Subgroup setcrtc_vs_cs_flip:
pass   -> SKIP   (shard-hsw)
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
pass   -> SKIP   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1228 dwarn:0   dfail:0   fail:18  skip:984 
time:9635s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5539/shards.html
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Re: [Intel-gfx] [PATCH i-g-t] lib/tests: Add audio selftest

[Chris Wilson]

Quoting Paul Kocialkowski (2017-08-30 15:45:14)
> This introduces a selftest for the audio library.
> 
> It consists of generating a signal from a list of frequencies and
> ensuring that the integrity checking function does detect these
> frequencies (and only these frequencies).
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/tests/Makefile.am  |  2 +-
>  lib/tests/Makefile.sources |  5 
>  lib/tests/igt_audio.c  | 57 
> ++
>  3 files changed, 63 insertions(+), 1 deletion(-)
>  create mode 100644 lib/tests/igt_audio.c
> 
> diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
> index 5d14194a..b1caa628 100644
> --- a/lib/tests/Makefile.am
> +++ b/lib/tests/Makefile.am
> @@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
> -DIGT_DATADIR=\""$(abs_srcdir)"\" \
> $(NULL)
>  
> -LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
> $(TIMER_LIBS)
> +LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(GSL_CFLAGS) 
> $(LIBUNWIND_LIBS) $(TIMER_LIBS)

Let's play spot the odd one out.
-Chris
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[Intel-gfx] [PATCH v5 3/4] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v5 2/4] drm/i915: mark all device info struct with __initdata

[Lionel Landwerlin]

As recommended by Chris.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_pci.c | 94 -
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f56aa8e3890b..2aeaf4855feb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -66,19 +66,19 @@
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i830_info = {
+static const struct intel_device_info intel_i830_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I830,
.is_mobile = 1, .cursor_needs_physical = 1,
.num_pipes = 2, /* legal, last one wins */
 };
 
-static const struct intel_device_info intel_i845g_info = {
+static const struct intel_device_info intel_i845g_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I845G,
 };
 
-static const struct intel_device_info intel_i85x_info = {
+static const struct intel_device_info intel_i85x_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I85X, .is_mobile = 1,
.num_pipes = 2, /* legal, last one wins */
@@ -86,7 +86,7 @@ static const struct intel_device_info intel_i85x_info = {
.has_fbc = 1,
 };
 
-static const struct intel_device_info intel_i865g_info = {
+static const struct intel_device_info intel_i865g_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I865G,
 };
@@ -98,7 +98,7 @@ static const struct intel_device_info intel_i865g_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i915g_info = {
+static const struct intel_device_info intel_i915g_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I915G, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -106,7 +106,7 @@ static const struct intel_device_info intel_i915g_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i915gm_info = {
+static const struct intel_device_info intel_i915gm_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I915GM,
.is_mobile = 1,
@@ -118,7 +118,7 @@ static const struct intel_device_info intel_i915gm_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i945g_info = {
+static const struct intel_device_info intel_i945g_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I945G,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -127,7 +127,7 @@ static const struct intel_device_info intel_i945g_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i945gm_info = {
+static const struct intel_device_info intel_i945gm_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I945GM, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -138,14 +138,14 @@ static const struct intel_device_info intel_i945gm_info = 
{
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_g33_info = {
+static const struct intel_device_info intel_g33_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_G33,
.has_hotplug = 1,
.has_overlay = 1,
 };
 
-static const struct intel_device_info intel_pineview_info = {
+static const struct intel_device_info intel_pineview_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_PINEVIEW, .is_mobile = 1,
.has_hotplug = 1,
@@ -160,14 +160,14 @@ static const struct intel_device_info intel_pineview_info 
= {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i965g_info = {
+static const struct intel_device_info intel_i965g_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_I965G,
.has_overlay = 1,
.hws_needs_physical = 1,
 };
 
-static const struct intel_device_info intel_i965gm_info = {
+static const struct intel_device_info intel_i965gm_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_I965GM,
.is_mobile = 1, .has_fbc = 1,
@@ -176,14 +176,14 @@ static const struct intel_device_info intel_i965gm_info = 
{
.hws_needs_physical = 1,
 };
 
-static const struct intel_device_info intel_g45_info = {
+static const struct intel_device_info intel_g45_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_G45,
.has_pipe_cxsr = 1,
.ring_mask = RENDER_RING | BSD_RING,
 };
 
-static const struct intel_device_info intel_gm45_info = {
+static const struct intel_device_info intel_gm45_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_GM45,
.is_mobile = 1, .has_fbc = 1,
@@ -200,12 +200,12 @@ static const struct intel_device_info intel_gm45_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_

[Intel-gfx] [PATCH v5 1/4] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

Before & After :

$ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l
209

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 152 +++
 3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..f56aa8e3890b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define IVB_M_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct 

[Intel-gfx] [PATCH v5 0/4] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Hi,

Adding one commit to mark device info structs with __initdata.

Cheers,

Lionel Landwerlin (4):
  drm/i915: add GT number to intel_device_info
  drm/i915: mark all device info struct with __initdata
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +
 drivers/gpu/drm/i915/i915_pci.c   | 241 --
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 152 +
 7 files changed, 431 insertions(+), 135 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] [PATCH v5 4/4] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_test_config_cflgt2(struct d

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29557/
State : success

== Summary ==

Series 29557v1 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29557/revisions/1/mbox/

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:462s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:552s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:439s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:450s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:599s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:404s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
12ba957a6601 drm/i915/perf: add support for Coffeelake GT2
59a09d151126 drm/i915: rework IS_*_GT* macros
d49b0dd08fef drm/i915: mark all device info struct with __initdata
4506125731ce drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5540/
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