[Intel-gfx] [PATCH v2 5/7] tests/kms_ccs: Test case where CCS and main buffer overlaps

[Gabriel Krisman Bertazi]

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index cc41c85c4964..06d34a80b108 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -34,10 +34,11 @@ enum test_flags {
TEST_BAD_PIXEL_FORMAT   = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER  = 1 << 5,
+   TEST_BAD_CCS_OFFSET = 1 << 6,
 };
 
 #define TEST_FAIL_ON_ADDFB2 \
-   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_OFFSET)
 
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
@@ -321,7 +322,13 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
int ccs_height = ALIGN(height, 16) / 16;
f.pitches[1] = ALIGN(ccs_width * 1, 128);
f.modifier[1] = modifier;
-   f.offsets[1] = size[0];
+
+   if (data->flags & TEST_BAD_CCS_OFFSET) {
+   /* Overlap CCS buffer with the color buffer. */
+   f.offsets[1] = 0;
+   } else
+   f.offsets[1] = size[0];
+
size[1] = f.pitches[1] * ALIGN(ccs_height, 32);
 
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
@@ -454,7 +461,8 @@ static void test_output(data_t *data)
 
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
data->flags & TEST_BAD_ROTATION_90 ||
-   data->flags & TEST_NO_AUX_BUFFER) {
+   data->flags & TEST_NO_AUX_BUFFER ||
+   data->flags & TEST_BAD_CCS_OFFSET) {
try_config(data, fb_flags | FB_COMPRESSED);
}
 
@@ -528,6 +536,10 @@ igt_main
igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
test_output();
 
+   data.flags = TEST_BAD_CCS_OFFSET;
+   igt_subtest_f("pipe-%s-invalid-ccs-offset", pipe_name)
+   test_output();
+
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH v2 6/7] tests/kms_ccs: Test case where CCS is on a different BO

[Gabriel Krisman Bertazi]

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 24 
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 06d34a80b108..95de6963226d 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -35,10 +35,12 @@ enum test_flags {
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER  = 1 << 5,
TEST_BAD_CCS_OFFSET = 1 << 6,
+   TEST_BAD_CCS_HANDLE = 1 << 7,
 };
 
 #define TEST_FAIL_ON_ADDFB2 \
-   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_OFFSET)
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_OFFSET | \
+TEST_BAD_CCS_HANDLE)
 
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
@@ -276,6 +278,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
unsigned int size[2];
uint64_t modifier;
int ret;
+   uint32_t ccs_handle;
 
/* Use either compressed or Y-tiled to test. However, given the lack of
 * available bandwidth, we use linear for the primary plane when
@@ -331,10 +334,18 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
 
size[1] = f.pitches[1] * ALIGN(ccs_height, 32);
 
-   f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
+   if (data->flags & TEST_BAD_CCS_HANDLE) {
+   /* Put the CCS buffer on a different BO. */
+   f.handles[0] = gem_create(data->drm_fd, size[0]);
+   ccs_handle = gem_create(data->drm_fd, size[1]);
+   f.offsets[1] = 0;
+   } else {
+   f.handles[0] = gem_create(data->drm_fd, size[0] + 
size[1]);
+   ccs_handle = f.handles[0];
+   }
 
if (!(data->flags & TEST_NO_AUX_BUFFER)) {
-   f.handles[1] = f.handles[0];
+   f.handles[1] = ccs_handle;
render_ccs(data, f.handles[1], f.offsets[1], size[1],
   height, f.pitches[1]);
}
@@ -462,7 +473,8 @@ static void test_output(data_t *data)
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
data->flags & TEST_BAD_ROTATION_90 ||
data->flags & TEST_NO_AUX_BUFFER ||
-   data->flags & TEST_BAD_CCS_OFFSET) {
+   data->flags & TEST_BAD_CCS_OFFSET ||
+   data->flags & TEST_BAD_CCS_HANDLE) {
try_config(data, fb_flags | FB_COMPRESSED);
}
 
@@ -540,6 +552,10 @@ igt_main
igt_subtest_f("pipe-%s-invalid-ccs-offset", pipe_name)
test_output();
 
+   data.flags = TEST_BAD_CCS_HANDLE;
+   igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
+   test_output();
+
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH v2 7/7] tests/kms_ccs: Test case for wrong aux buffer stripe size

[Gabriel Krisman Bertazi]

Two scenarios tested:
  - unaligned stripe
  - Stripe too small

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 95de6963226d..2e6efe95ffca 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -36,15 +36,18 @@ enum test_flags {
TEST_NO_AUX_BUFFER  = 1 << 5,
TEST_BAD_CCS_OFFSET = 1 << 6,
TEST_BAD_CCS_HANDLE = 1 << 7,
+   TEST_BAD_AUX_STRIDE = 1 << 8,
 };
 
 #define TEST_FAIL_ON_ADDFB2 \
(TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_OFFSET | \
-TEST_BAD_CCS_HANDLE)
+TEST_BAD_CCS_HANDLE | TEST_BAD_AUX_STRIDE)
 
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
FB_HAS_PLANE= 1 << 1,
+   FB_MISALIGN_AUX_STRIDE  = 1 << 2,
+   FB_SMALL_AUX_STRIDE = 1 << 3,
 };
 
 typedef struct {
@@ -323,7 +326,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
 */
int ccs_width = ALIGN(width * 4, 32) / 32;
int ccs_height = ALIGN(height, 16) / 16;
-   f.pitches[1] = ALIGN(ccs_width * 1, 128);
+   int aux_stride = ALIGN(ccs_width * 1, 128);
+
+   if (fb_flags & FB_MISALIGN_AUX_STRIDE)
+   aux_stride = ccs_width;
+   else if (fb_flags & FB_SMALL_AUX_STRIDE)
+   aux_stride = ALIGN(ccs_width/2, 128);
+
+   f.pitches[1] = aux_stride;
f.modifier[1] = modifier;
 
if (data->flags & TEST_BAD_CCS_OFFSET) {
@@ -478,6 +488,11 @@ static void test_output(data_t *data)
try_config(data, fb_flags | FB_COMPRESSED);
}
 
+   if (data->flags & TEST_BAD_AUX_STRIDE) {
+   try_config(data, fb_flags | FB_COMPRESSED | 
FB_MISALIGN_AUX_STRIDE);
+   try_config(data, fb_flags | FB_COMPRESSED | 
FB_SMALL_AUX_STRIDE);
+   }
+
primary = igt_output_get_plane_type(data->output, 
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
igt_plane_set_rotation(primary, IGT_ROTATION_0);
@@ -556,6 +571,9 @@ igt_main
igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
test_output();
 
+   data.flags = TEST_BAD_AUX_STRIDE;
+   igt_subtest_f("pipe-%s-bad-aux-stride", pipe_name)
+   test_output();
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH v2 4/7] tests/kms_ccs: Test case where the CCS buffer was not provided

[Gabriel Krisman Bertazi]

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 73025a1e019f..cc41c85c4964 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -33,8 +33,12 @@ enum test_flags {
TEST_ROTATE_180 = 1 << 2,
TEST_BAD_PIXEL_FORMAT   = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
+   TEST_NO_AUX_BUFFER  = 1 << 5,
 };
 
+#define TEST_FAIL_ON_ADDFB2 \
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
FB_HAS_PLANE= 1 << 1,
@@ -321,16 +325,19 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
size[1] = f.pitches[1] * ALIGN(ccs_height, 32);
 
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
-   f.handles[1] = f.handles[0];
-   render_ccs(data, f.handles[1], f.offsets[1], size[1],
-  height, f.pitches[1]);
+
+   if (!(data->flags & TEST_NO_AUX_BUFFER)) {
+   f.handles[1] = f.handles[0];
+   render_ccs(data, f.handles[1], f.offsets[1], size[1],
+  height, f.pitches[1]);
+   }
} else
f.handles[0] = gem_create(data->drm_fd, size[0]);
 
render_fb(data, f.handles[0], size[0], fb_flags, height, f.pitches[0]);
 
ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, );
-   if (data->flags & TEST_BAD_PIXEL_FORMAT) {
+   if (data->flags & TEST_FAIL_ON_ADDFB2) {
igt_assert_eq(ret, -1);
igt_assert_eq(errno, EINVAL);
return;
@@ -379,7 +386,7 @@ static void try_config(data_t *data, enum test_fb_flags 
fb_flags)
drm_mode->vdisplay, fb_flags);
}
 
-   if (data->flags & TEST_BAD_PIXEL_FORMAT)
+   if (data->flags & TEST_FAIL_ON_ADDFB2)
return;
 
igt_plane_set_position(primary, 0, 0);
@@ -446,7 +453,8 @@ static void test_output(data_t *data)
}
 
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
-   data->flags & TEST_BAD_ROTATION_90) {
+   data->flags & TEST_BAD_ROTATION_90 ||
+   data->flags & TEST_NO_AUX_BUFFER) {
try_config(data, fb_flags | FB_COMPRESSED);
}
 
@@ -515,6 +523,11 @@ igt_main
}
 
data.plane = NULL;
+
+   data.flags = TEST_NO_AUX_BUFFER;
+   igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
+   test_output();
+
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH v2 1/7] tests/kms_ccs: Test pipes other than pipe A

[Gabriel Krisman Bertazi]

Commit d41c4ccbd2f9 ("tests/kms_ccs: Fix subtest enumeration")
accidently removed the update of data.pipe, causing kms_ccs to silently
only test PIPE_A.

This fixes the behavior reported by Daniel Vetter where tests would
succeed even on nonexistent pipes.

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index ab9325d14991..775c6999699f 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -483,6 +483,8 @@ igt_main
const char *pipe_name = kmstest_pipe_name(pipe);
int sprite_idx = 0;
 
+   data.pipe = pipe;
+
data.flags = TEST_BAD_PIXEL_FORMAT;
igt_subtest_f("pipe-%s-bad-pixel-format", pipe_name)
test_output();
-- 
2.11.0

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[Intel-gfx] [PATCH v2 0/7] kms_ccs testcase improvements

[Gabriel Krisman Bertazi]

Hey,

Here is a v2 including other testcases for kms_ccs as well as random
fixes to that test and one to igt_kms.

I have two other testcases that I wanted to share together with this set
for kms_ccs, but they will come later.

Please notice that the testcase for the overlapping buffers will hit a
failure because linux fails to detect the overlapping buffers in
add_fb2.  I'll submit on another thread with a patch to linux fixing the
ioctl, which will make this test suceed. 

Please, let me know your feedback,

Gabriel Krisman Bertazi (7):
  tests/kms_ccs: Test pipes other than pipe A
  lib/igt_kms: Fix off-by-one bug on skip of missing pipe
  tests/kms_ccs: Prevent segfault if pipe is not supported
  tests/kms_ccs: Test case where the CCS buffer was not provided
  tests/kms_ccs: Test case where CCS and main buffer overlaps
  tests/kms_ccs: Test case where CCS is on a different BO
  tests/kms_ccs: Test case for wrong aux buffer stripe size

 lib/igt_kms.c   |  2 +-
 tests/kms_ccs.c | 82 ++---
 2 files changed, 74 insertions(+), 10 deletions(-)

-- 
2.11.0

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[Intel-gfx] [PATCH v2 3/7] tests/kms_ccs: Prevent segfault if pipe is not supported

[Gabriel Krisman Bertazi]

for_each_plane_on_pipe() indexes bad memory when iterating over an invalid
pipe.  Make sure the pipe exists before trying to use it.  This prevents
the crash below:

root@ideacentre:~# igt-gpu-tools/tests/kms_ccs --r 
pipe-D-crc-sprite-planes-basic
IGT-Version: 1.19-g59f0e3d182a8 (x86_64) (Linux: 4.13.0-rc6.intel-boxes+x86_64)
Received signal SIGSEGV.
Stack trace:
 #0 [fatal_sig_handler+0x185]
 #1 [killpg+0x40]
 #2 [__real_main485+0x2de]
 #3 [main+0x3f]
 #4 [__libc_start_main+0xf1]
 #5 [_start+0x2a]
 #6 [+0x2a]
Subtest pipe-D-crc-sprite-planes-basic: CRASH (0.004s)

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 775c6999699f..73025a1e019f 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -503,6 +503,9 @@ igt_main
 
data.flags = TEST_CRC;
igt_subtest_f("pipe-%s-crc-sprite-planes-basic", pipe_name) {
+
+   igt_display_require_output_on_pipe(, 
data.pipe);
+
for_each_plane_on_pipe(, data.pipe, 
data.plane) {
if (data.plane->type == DRM_PLANE_TYPE_PRIMARY)
continue;
-- 
2.11.0

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[Intel-gfx] [PATCH v2 2/7] lib/igt_kms: Fix off-by-one bug on skip of missing pipe

[Gabriel Krisman Bertazi]

display->n_pipes is zero-indexed, so N returned in
igt_display_get_n_pipes is already not a valid pipe.  This patch
prevents kms_ccs from going nuts when testing the first unxesting pipe.

Signed-off-by: Gabriel Krisman Bertazi 
---
 lib/igt_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 14e2701c3afd..ce07fcc1fc73 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1864,7 +1864,7 @@ void igt_display_require_output_on_pipe(igt_display_t 
*display, enum pipe pipe)
 {
igt_output_t *output;
 
-   igt_skip_on_f(igt_display_get_n_pipes(display) < pipe,
+   igt_skip_on_f(igt_display_get_n_pipes(display) <= pipe,
  "Pipe %s does not exist.\n", kmstest_pipe_name(pipe));
 
for_each_valid_output_on_pipe(display, pipe, output)
-- 
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Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Vivi, Rodrigo]

On Thu, 2017-08-31 at 13:24 +0800, Zhi Wang wrote:
> Also I should send a register diff at that time (RFC -> PATCH). Suppose 
> these two patches should keep the used PPAT registers unchanged like before.

I knew you were going to ask this and logs :)
I will check tomorrow carefully since right now I don't have access to
the machine.

Sorry about that.

> 
> On 08/31/17 13:22, Wang, Zhi A wrote:
> > Thanks for the test! Sorry I didn't have an CNL on my hand.
> >
> > This is only RFC now. after collecting all the comments, I will start full 
> > test. :)
> >
> > Thanks,
> > Zhi.
> >
> > -Original Message-
> > From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
> > Sent: Thursday, August 31, 2017 8:15 AM
> > To: Wang, Zhi A 
> > Cc: Vivi, Rodrigo ; 
> > intel-gfx@lists.freedesktop.org; Widawsky, Benjamin 
> > ; intel-gvt-...@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT 
> > management
> >
> > On Wed, Aug 30, 2017 at 9:49 PM, Zhi Wang  wrote:
> >> Hi Vivi:
> >>  Thanks for the reply! The register are written in ppat->update_hw() 
> >> now.
> > oh, I saw now...
> > I hadden noticed that interation.
> >
> > But something seems really odd yet...
> > My CNL with these 2 patches applied hangs on any execution...
> >
> >>
> >> +static void cnl_private_pat_update_hw(struct drm_i915_private
> >> +*dev_priv) {
> >> +   struct intel_ppat *ppat = _priv->ppat;
> >> +   int i;
> >> +
> >> +   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
> >> +   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
> >> +   clear_bit(i, ppat->dirty);
> >> +   }
> >> +}
> >> +
> >> +static void bdw_private_pat_update_hw(struct drm_i915_private
> >> +*dev_priv) {
> >> +   struct intel_ppat *ppat = _priv->ppat;
> >> +   u64 pat = 0;
> >> +   int i;
> >> +
> >> +   for (i = 0; i < ppat->max_entries; i++)
> >> +   pat |= GEN8_PPAT(i, ppat->entries[i].value);
> >> +
> >> +   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
> >> +
> >> +   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
> >> +   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); }
> >>
> >> On 08/31/17 06:00, Vivi, Rodrigo wrote:
> >>> On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:
>  The private PAT management is to support PPAT entry manipulation.
>  Two APIs are introduced for dynamically managing PPAT entries:
>  intel_ppat_get and intel_ppat_put.
> 
>  intel_ppat_get will search for an existing PPAT entry which
>  perfectly matches the required PPAT value. If not, it will try to
>  allocate or return a partially matched PPAT entry if there is any
>  available PPAT indexes or not.
> 
>  intel_ppat_put will put back the PPAT entry which comes from
>  intel_ppat_get. If it's dynamically allocated, the reference count
>  will be decreased. If the reference count turns into zero, the PPAT
>  index is freed again.
> 
>  Besides, another two callbacks are introduced to support the private
>  PAT management framework. One is ppat->update_hw(), which writes the
>  PPAT configurations in ppat->entries into HW. Another one is
>  ppat->match, which will return a score to show how two PPAT values
>  match with each other.
> 
>  v6:
> 
>  - Address all comments from Chris:
>  http://www.spinics.net/lists/intel-gfx/msg136850.html
> 
>  - Address all comments from Joonas:
>  http://www.spinics.net/lists/intel-gfx/msg136845.html
> 
>  v5:
> 
>  - Add check and warnnings for those platforms which don't have PPAT.
> 
>  v3:
> 
>  - Introduce dirty bitmap for PPAT registers. (Chris)
>  - Change the name of the pointer "dev_priv" to "i915". (Chris)
>  - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *.
>  (Chris)
> 
>  v2:
> 
>  - API re-design. (Chris)
> 
>  Cc: Ben Widawsky 
>  Cc: Rodrigo Vivi 
>  Cc: Chris Wilson 
>  Cc: Joonas Lahtinen 
>  Signed-off-by: Zhi Wang 
>  ---
> drivers/gpu/drm/i915/i915_drv.h |   2 +
> drivers/gpu/drm/i915/i915_gem_gtt.c | 273
>  +---
> drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
> 3 files changed, 262 insertions(+), 49 deletions(-)
> 
>  diff --git a/drivers/gpu/drm/i915/i915_drv.h
>  b/drivers/gpu/drm/i915/i915_drv.h index 7587ef5..5ffde10 100644
>  --- a/drivers/gpu/drm/i915/i915_drv.h
>  +++ b/drivers/gpu/drm/i915/i915_drv.h
>  @@ -2312,6 +2312,8 @@ struct drm_i915_private {
>   DECLARE_HASHTABLE(mm_structs, 7);
>   struct mutex mm_lock;
> 

Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Zhi Wang]

Also I should send a register diff at that time (RFC -> PATCH). Suppose 
these two patches should keep the used PPAT registers unchanged like before.



On 08/31/17 13:22, Wang, Zhi A wrote:

Thanks for the test! Sorry I didn't have an CNL on my hand.

This is only RFC now. after collecting all the comments, I will start full 
test. :)

Thanks,
Zhi.

-Original Message-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
Sent: Thursday, August 31, 2017 8:15 AM
To: Wang, Zhi A 
Cc: Vivi, Rodrigo ; intel-gfx@lists.freedesktop.org; 
Widawsky, Benjamin ; intel-gvt-...@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

On Wed, Aug 30, 2017 at 9:49 PM, Zhi Wang  wrote:

Hi Vivi:
 Thanks for the reply! The register are written in ppat->update_hw() now.

oh, I saw now...
I hadden noticed that interation.

But something seems really odd yet...
My CNL with these 2 patches applied hangs on any execution...



+static void cnl_private_pat_update_hw(struct drm_i915_private
+*dev_priv) {
+   struct intel_ppat *ppat = _priv->ppat;
+   int i;
+
+   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
+   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
+   clear_bit(i, ppat->dirty);
+   }
+}
+
+static void bdw_private_pat_update_hw(struct drm_i915_private
+*dev_priv) {
+   struct intel_ppat *ppat = _priv->ppat;
+   u64 pat = 0;
+   int i;
+
+   for (i = 0; i < ppat->max_entries; i++)
+   pat |= GEN8_PPAT(i, ppat->entries[i].value);
+
+   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
+
+   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
+   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); }

On 08/31/17 06:00, Vivi, Rodrigo wrote:

On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:

The private PAT management is to support PPAT entry manipulation.
Two APIs are introduced for dynamically managing PPAT entries:
intel_ppat_get and intel_ppat_put.

intel_ppat_get will search for an existing PPAT entry which
perfectly matches the required PPAT value. If not, it will try to
allocate or return a partially matched PPAT entry if there is any
available PPAT indexes or not.

intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count
will be decreased. If the reference count turns into zero, the PPAT
index is freed again.

Besides, another two callbacks are introduced to support the private
PAT management framework. One is ppat->update_hw(), which writes the
PPAT configurations in ppat->entries into HW. Another one is
ppat->match, which will return a score to show how two PPAT values
match with each other.

v6:

- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html

- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html

v5:

- Add check and warnnings for those platforms which don't have PPAT.

v3:

- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *.
(Chris)

v2:

- API re-design. (Chris)

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
   drivers/gpu/drm/i915/i915_drv.h |   2 +
   drivers/gpu/drm/i915/i915_gem_gtt.c | 273
+---
   drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
   3 files changed, 262 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h index 7587ef5..5ffde10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2312,6 +2312,8 @@ struct drm_i915_private {
 DECLARE_HASHTABLE(mm_structs, 7);
 struct mutex mm_lock;
   + struct intel_ppat ppat;
+
 /* Kernel Modesetting */
 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b74fa9d..3106142 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct
i915_ggtt *ggtt, u64 size)
 return 0;
   }
   -static void cnl_setup_private_ppat(struct drm_i915_private
*dev_priv)
+static struct intel_ppat_entry *
+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8
value)
   {
+   struct intel_ppat_entry *entry = >entries[index];
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(test_bit(index, ppat->used));
+
+   entry->ppat = ppat;
+   entry->value = value;
+   

Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Wang, Zhi A]

Thanks for the test! Sorry I didn't have an CNL on my hand.

This is only RFC now. after collecting all the comments, I will start full 
test. :)

Thanks,
Zhi.

-Original Message-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] 
Sent: Thursday, August 31, 2017 8:15 AM
To: Wang, Zhi A 
Cc: Vivi, Rodrigo ; intel-gfx@lists.freedesktop.org; 
Widawsky, Benjamin ; 
intel-gvt-...@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

On Wed, Aug 30, 2017 at 9:49 PM, Zhi Wang  wrote:
> Hi Vivi:
> Thanks for the reply! The register are written in ppat->update_hw() now.

oh, I saw now...
I hadden noticed that interation.

But something seems really odd yet...
My CNL with these 2 patches applied hangs on any execution...

>
>
> +static void cnl_private_pat_update_hw(struct drm_i915_private 
> +*dev_priv) {
> +   struct intel_ppat *ppat = _priv->ppat;
> +   int i;
> +
> +   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
> +   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
> +   clear_bit(i, ppat->dirty);
> +   }
> +}
> +
> +static void bdw_private_pat_update_hw(struct drm_i915_private 
> +*dev_priv) {
> +   struct intel_ppat *ppat = _priv->ppat;
> +   u64 pat = 0;
> +   int i;
> +
> +   for (i = 0; i < ppat->max_entries; i++)
> +   pat |= GEN8_PPAT(i, ppat->entries[i].value);
> +
> +   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
> +
> +   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
> +   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); }
>
> On 08/31/17 06:00, Vivi, Rodrigo wrote:
>>
>> On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:
>>>
>>> The private PAT management is to support PPAT entry manipulation. 
>>> Two APIs are introduced for dynamically managing PPAT entries: 
>>> intel_ppat_get and intel_ppat_put.
>>>
>>> intel_ppat_get will search for an existing PPAT entry which 
>>> perfectly matches the required PPAT value. If not, it will try to 
>>> allocate or return a partially matched PPAT entry if there is any 
>>> available PPAT indexes or not.
>>>
>>> intel_ppat_put will put back the PPAT entry which comes from 
>>> intel_ppat_get. If it's dynamically allocated, the reference count 
>>> will be decreased. If the reference count turns into zero, the PPAT 
>>> index is freed again.
>>>
>>> Besides, another two callbacks are introduced to support the private 
>>> PAT management framework. One is ppat->update_hw(), which writes the 
>>> PPAT configurations in ppat->entries into HW. Another one is 
>>> ppat->match, which will return a score to show how two PPAT values 
>>> match with each other.
>>>
>>> v6:
>>>
>>> - Address all comments from Chris:
>>> http://www.spinics.net/lists/intel-gfx/msg136850.html
>>>
>>> - Address all comments from Joonas:
>>> http://www.spinics.net/lists/intel-gfx/msg136845.html
>>>
>>> v5:
>>>
>>> - Add check and warnnings for those platforms which don't have PPAT.
>>>
>>> v3:
>>>
>>> - Introduce dirty bitmap for PPAT registers. (Chris)
>>> - Change the name of the pointer "dev_priv" to "i915". (Chris)
>>> - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. 
>>> (Chris)
>>>
>>> v2:
>>>
>>> - API re-design. (Chris)
>>>
>>> Cc: Ben Widawsky 
>>> Cc: Rodrigo Vivi 
>>> Cc: Chris Wilson 
>>> Cc: Joonas Lahtinen 
>>> Signed-off-by: Zhi Wang 
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h |   2 +
>>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 273
>>> +---
>>>   drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
>>>   3 files changed, 262 insertions(+), 49 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>>> b/drivers/gpu/drm/i915/i915_drv.h index 7587ef5..5ffde10 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2312,6 +2312,8 @@ struct drm_i915_private {
>>> DECLARE_HASHTABLE(mm_structs, 7);
>>> struct mutex mm_lock;
>>>   + struct intel_ppat ppat;
>>> +
>>> /* Kernel Modesetting */
>>> struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> index b74fa9d..3106142 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> @@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct 
>>> i915_ggtt *ggtt, u64 size)
>>> return 0;
>>>   }
>>>   -static void cnl_setup_private_ppat(struct drm_i915_private 
>>> *dev_priv)
>>> +static struct intel_ppat_entry *
>>> +__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8
>>> value)
>>>   {
>>> +   struct intel_ppat_entry *entry = 

Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Rodrigo Vivi]

On Wed, Aug 30, 2017 at 9:49 PM, Zhi Wang  wrote:
> Hi Vivi:
> Thanks for the reply! The register are written in ppat->update_hw() now.

oh, I saw now...
I hadden noticed that interation.

But something seems really odd yet...
My CNL with these 2 patches applied hangs on any execution...

>
>
> +static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
> +{
> +   struct intel_ppat *ppat = _priv->ppat;
> +   int i;
> +
> +   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
> +   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
> +   clear_bit(i, ppat->dirty);
> +   }
> +}
> +
> +static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
> +{
> +   struct intel_ppat *ppat = _priv->ppat;
> +   u64 pat = 0;
> +   int i;
> +
> +   for (i = 0; i < ppat->max_entries; i++)
> +   pat |= GEN8_PPAT(i, ppat->entries[i].value);
> +
> +   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
> +
> +   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
> +   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
> +}
>
> On 08/31/17 06:00, Vivi, Rodrigo wrote:
>>
>> On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:
>>>
>>> The private PAT management is to support PPAT entry manipulation. Two
>>> APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
>>> and intel_ppat_put.
>>>
>>> intel_ppat_get will search for an existing PPAT entry which perfectly
>>> matches the required PPAT value. If not, it will try to allocate or
>>> return a partially matched PPAT entry if there is any available PPAT
>>> indexes or not.
>>>
>>> intel_ppat_put will put back the PPAT entry which comes from
>>> intel_ppat_get. If it's dynamically allocated, the reference count will
>>> be decreased. If the reference count turns into zero, the PPAT index is
>>> freed again.
>>>
>>> Besides, another two callbacks are introduced to support the private PAT
>>> management framework. One is ppat->update_hw(), which writes the PPAT
>>> configurations in ppat->entries into HW. Another one is ppat->match,
>>> which
>>> will return a score to show how two PPAT values match with each other.
>>>
>>> v6:
>>>
>>> - Address all comments from Chris:
>>> http://www.spinics.net/lists/intel-gfx/msg136850.html
>>>
>>> - Address all comments from Joonas:
>>> http://www.spinics.net/lists/intel-gfx/msg136845.html
>>>
>>> v5:
>>>
>>> - Add check and warnnings for those platforms which don't have PPAT.
>>>
>>> v3:
>>>
>>> - Introduce dirty bitmap for PPAT registers. (Chris)
>>> - Change the name of the pointer "dev_priv" to "i915". (Chris)
>>> - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)
>>>
>>> v2:
>>>
>>> - API re-design. (Chris)
>>>
>>> Cc: Ben Widawsky 
>>> Cc: Rodrigo Vivi 
>>> Cc: Chris Wilson 
>>> Cc: Joonas Lahtinen 
>>> Signed-off-by: Zhi Wang 
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h |   2 +
>>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 273
>>> +---
>>>   drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
>>>   3 files changed, 262 insertions(+), 49 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 7587ef5..5ffde10 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2312,6 +2312,8 @@ struct drm_i915_private {
>>> DECLARE_HASHTABLE(mm_structs, 7);
>>> struct mutex mm_lock;
>>>   + struct intel_ppat ppat;
>>> +
>>> /* Kernel Modesetting */
>>> struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> index b74fa9d..3106142 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> @@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct i915_ggtt
>>> *ggtt, u64 size)
>>> return 0;
>>>   }
>>>   -static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
>>> +static struct intel_ppat_entry *
>>> +__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8
>>> value)
>>>   {
>>> +   struct intel_ppat_entry *entry = >entries[index];
>>> +
>>> +   GEM_BUG_ON(index >= ppat->max_entries);
>>> +   GEM_BUG_ON(test_bit(index, ppat->used));
>>> +
>>> +   entry->ppat = ppat;
>>> +   entry->value = value;
>>> +   kref_init(>ref);
>>> +   set_bit(index, ppat->used);
>>> +   set_bit(index, ppat->dirty);
>>> +
>>> +   return entry;
>>> +}
>>> +
>>> +static void __free_ppat_entry(struct intel_ppat_entry *entry)
>>> +{
>>> +   struct intel_ppat *ppat = entry->ppat;
>>> +   unsigned int index = entry - ppat->entries;
>>> +
>>> +   GEM_BUG_ON(index >= 

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaDisableI2mCycleOnWRPort

[Vivi, Rodrigo]

merged to dinq. thanks for the review

On Wed, 2017-08-30 at 11:45 +0300, Mika Kuoppala wrote:
> Rodrigo Vivi  writes:
> 
> > On CNL B0 stepping GAM is not able to detect some deadlock
> > condition and then rise the rise the gam_coh_flush.
> >
> > WA database and spec both mentions to set 4AB8[24]=1 as
> > workaround. Alghouth register offset 0x4AB8 is not
> s/Alghouth/Although
> 
> > documented for any platform.
> >
> 
> References: HSD#1945815, BSID#1112
> 
> > Cc: Mika Kuoppala 
> > Signed-off-by: Rodrigo Vivi 
> 
> Reviewed-by: Mika Kuoppala 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h| 1 +
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index e2908ae34004..bbacdac5c794 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2373,6 +2373,7 @@ enum i915_power_well_id {
> >  
> >  #define GAMT_CHKN_BIT_REG  _MMIO(0x4ab8)
> >  #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
> > +#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT   (1<<24)
> >  
> >  #if 0
> >  #define PRB0_TAIL  _MMIO(0x2030)
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index a6ac9d0a4156..f087eb6b0134 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1070,6 +1070,11 @@ static int cnl_init_workarounds(struct 
> > intel_engine_cs *engine)
> > struct drm_i915_private *dev_priv = engine->i915;
> > int ret;
> >  
> > +   /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
> > +   if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> > +   WA_SET_BIT(GAMT_CHKN_BIT_REG,
> > +  GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
> > +
> > /* WaForceContextSaveRestoreNonCoherent:cnl */
> > WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> >   HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> > -- 
> > 2.13.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

___
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Vivi, Rodrigo]

merged to dinq. thanks for the review


On Wed, 2017-08-30 at 11:55 +0300, Mika Kuoppala wrote:
> Rodrigo Vivi  writes:
> 
> > WA to enable HW L1 Banking fix that allows aniso to operate
> > at full sample rate.
> >
> 
> References: HSD#1937670
> 
> > Cc: Mika Kuoppala 
> > Cc: Oscar Mateo 
> > Cc: Ben Widawsky 
> > Cc: Anuj Phogat 
> > Signed-off-by: Rodrigo Vivi 
> 
> Reviewed-by: Mika Kuoppala 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h| 1 +
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index e2908ae34004..1ad22a824921 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8072,6 +8072,7 @@ enum {
> >  #define   HSW_SAMPLE_C_PERFORMANCE (1<<9)
> >  #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
> >  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC  (1<<5)
> > +#define   CNL_FAST_ANISO_L1_BANKING_FIX(1<<4)
> >  #define   GEN8_SAMPLER_POWER_BYPASS_DIS(1<<1)
> >  
> >  #define GEN9_HALF_SLICE_CHICKEN7   _MMIO(0xe194)
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index a6ac9d0a4156..4b9b7828802d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct 
> > intel_engine_cs *engine)
> > /* WaPushConstantDereferenceHoldDisable:cnl */
> > WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
> >  
> > +   /* FtrEnableFastAnisoL1BankingFix: cnl */
> > +   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> > +
> > /* WaEnablePreemptionGranularityControlByUMD:cnl */
> > ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> > if (ret)
> > -- 
> > 2.13.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue

[Rodrigo Vivi]

From: "Vivi, Rodrigo" 

This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.

During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.

The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.

The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.

v2: Only add the bit that matters without touching others
around (Jani).
Rebase on top of clock gating functions rename.

Cc: Jani Nikula 
Cc: Arthur J Runyan 
Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 27 +--
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..bb3df56e447f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7482,6 +7482,7 @@ enum {
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1<<13)
 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4bdf1fb1df7e..3473b327519d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+   if (!HAS_PCH_CNP(dev_priv))
+   return;
+
+   /* Wa #1181 */
+   I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+}
+
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+   cnp_init_clock_gating(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8285,6 +8296,16 @@ static void cnl_init_clock_gating(struct 
drm_i915_private *dev_priv)
   SARBUNIT_CLKGATE_DIS);
 }
 
+static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+   cnp_init_clock_gating(dev_priv);
+   gen9_init_clock_gating(dev_priv);
+
+   /* WaFbcNukeOnHostModify:cfl */
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+}
+
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
gen9_init_clock_gating(dev_priv);
@@ -8299,7 +8320,7 @@ static void kbl_init_clock_gating(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-   /* WaFbcNukeOnHostModify:kbl,cfl */
+   /* WaFbcNukeOnHostModify:kbl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
@@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+   else if (IS_COFFEELAKE(dev_priv))
+   dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
-   else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+   else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-- 
2.13.2

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Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Zhi Wang]

Hi Vivi:
Thanks for the reply! The register are written in ppat->update_hw() 
now.


+static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
+{
+   struct intel_ppat *ppat = _priv->ppat;
+   int i;
+
+   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
+   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
+   clear_bit(i, ppat->dirty);
+   }
+}
+
+static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
+{
+   struct intel_ppat *ppat = _priv->ppat;
+   u64 pat = 0;
+   int i;
+
+   for (i = 0; i < ppat->max_entries; i++)
+   pat |= GEN8_PPAT(i, ppat->entries[i].value);
+
+   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
+
+   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
+   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
+}

On 08/31/17 06:00, Vivi, Rodrigo wrote:

On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:

The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.

intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate or
return a partially matched PPAT entry if there is any available PPAT
indexes or not.

intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.

Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update_hw(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.

v6:

- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html

- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html

v5:

- Add check and warnnings for those platforms which don't have PPAT.

v3:

- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)

v2:

- API re-design. (Chris)

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
  drivers/gpu/drm/i915/i915_drv.h |   2 +
  drivers/gpu/drm/i915/i915_gem_gtt.c | 273 +---
  drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
  3 files changed, 262 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef5..5ffde10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2312,6 +2312,8 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
  
+	struct intel_ppat ppat;

+
/* Kernel Modesetting */
  
  	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b74fa9d..3106142 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
u64 size)
return 0;
  }
  
-static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)

+static struct intel_ppat_entry *
+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
  {
+   struct intel_ppat_entry *entry = >entries[index];
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(test_bit(index, ppat->used));
+
+   entry->ppat = ppat;
+   entry->value = value;
+   kref_init(>ref);
+   set_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+
+   return entry;
+}
+
+static void __free_ppat_entry(struct intel_ppat_entry *entry)
+{
+   struct intel_ppat *ppat = entry->ppat;
+   unsigned int index = entry - ppat->entries;
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(!test_bit(index, ppat->used));
+
+   entry->value = ppat->clear_value;
+   clear_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+}
+
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @i915: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, 

Re: [Intel-gfx] [PATCH] drm/i915: Stop using long platform names on clock gating functions.

[Rodrigo Vivi]

On Tue, Aug 29, 2017 at 09:43:41AM +0300, Jani Nikula wrote:
> On Tue, 29 Aug 2017, Rodrigo Vivi  wrote:
> > No functional changes.
> >
> > Our code was only a bit messy with mixed style there so
> > let's clean up a bit using the short codenames for the platforms.
> >
> > Cc: Dhinakaran Pandiyan 
> > Signed-off-by: Rodrigo Vivi 
> 
> Acked-by: Jani Nikula 

thanks. merged to dinq.

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 44 
> > -
> >  1 file changed, 22 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index d5ff0b9f999f..4bdf1fb1df7e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7981,7 +7981,7 @@ static void ilk_init_lp_watermarks(struct 
> > drm_i915_private *dev_priv)
> >  */
> >  }
> >  
> > -static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> >  
> > @@ -8264,7 +8264,7 @@ static void gen8_set_l3sqc_credits(struct 
> > drm_i915_private *dev_priv,
> > I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >  }
> >  
> > -static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > /* This is not an Wa. Enable for better image quality */
> > I915_WRITE(_3D_CHICKEN3,
> > @@ -8285,7 +8285,7 @@ static void cannonlake_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> >SARBUNIT_CLKGATE_DIS);
> >  }
> >  
> > -static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > gen9_init_clock_gating(dev_priv);
> >  
> > @@ -8304,7 +8304,7 @@ static void kabylake_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> >ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> >  
> > -static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > gen9_init_clock_gating(dev_priv);
> >  
> > @@ -8317,7 +8317,7 @@ static void skylake_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> >ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> >  
> > -static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > enum pipe pipe;
> >  
> > @@ -8375,7 +8375,7 @@ static void broadwell_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> >I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >  }
> >  
> > -static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > ilk_init_lp_watermarks(dev_priv);
> >  
> > @@ -8429,7 +8429,7 @@ static void haswell_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > lpt_init_clock_gating(dev_priv);
> >  }
> >  
> > -static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > uint32_t snpcr;
> >  
> > @@ -8526,7 +8526,7 @@ static void ivybridge_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > gen6_check_mch_setup(dev_priv);
> >  }
> >  
> > -static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > /* WaDisableEarlyCull:vlv */
> > I915_WRITE(_3D_CHICKEN3,
> > @@ -8606,7 +8606,7 @@ static void valleyview_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> >  }
> >  
> > -static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > /* WaVSRefCountFullforceMissDisable:chv */
> > /* WaDSRefCountFullforceMissDisable:chv */
> > @@ -8666,7 +8666,7 @@ static void g4x_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > g4x_disable_trickle_feed(dev_priv);
> >  }
> >  
> > -static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
> > I915_WRITE(RENCLK_GATE_D2, 0);
> > @@ -8680,7 +8680,7 @@ static void crestline_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> >  }
> >  
> > -static void 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Introduce HAS_2PPC.

[Rodrigo Vivi]

On Wed, Aug 30, 2017 at 7:58 PM, Pandiyan, Dhinakaran
 wrote:
> On Wed, 2017-08-30 at 20:32 +0100, Chris Wilson wrote:
>> Quoting Pandiyan, Dhinakaran (2017-08-30 20:12:52)
>> > On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
>> > > Let's make it easier to add platforms that supports 2 pixel per
>> > > clock.
>> > >
>> > > With spread checks per platform it was easy to miss one or
>> > > another spot leading to loose some time on debug.
>> > >
>> > > Hopefully this check would save some cases in the future.
>> > >
>> > > No functional change.
>> > >
>> > > Cc: Paulo Zanoni 
>> > > Cc: Dhinakaran Pandiyan 
>> > > Cc: Ville Syrjälä 
>> > > Signed-off-by: Rodrigo Vivi 
>> > > ---
>> > >  drivers/gpu/drm/i915/i915_drv.h| 4 
>> > >  drivers/gpu/drm/i915/i915_pci.c| 2 ++
>> > >  drivers/gpu/drm/i915/intel_cdclk.c | 8 
>> > >  drivers/gpu/drm/i915/intel_pm.c| 3 +--
>> > >  4 files changed, 11 insertions(+), 6 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> > > b/drivers/gpu/drm/i915/i915_drv.h
>> > > index 6c25c8520c87..94f5e6522e5e 100644
>> > > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > > @@ -748,6 +748,7 @@ struct intel_csr {
>> > >   func(is_lp); \
>> > >   func(is_alpha_support); \
>> > >   /* Keep has_* in alphabetical order */ \
>> > > + func(has_2ppc); \
>> > >   func(has_64bit_reloc); \
>> > >   func(has_aliasing_ppgtt); \
>> > >   func(has_csr); \
>> > > @@ -3025,6 +3026,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>> > >  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
>> > >   (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>> > >
>> > > +/* Supports 2 pixel per clock */
>> > > +#define HAS_2PPC(dev_priv) ((dev_priv)->info.has_2ppc)
>> > > +
>> >
>> > How about
>> > #define HAS_2PPC(dev_priv) (IS_GEMINILAKE(dev_priv) ||
>> > INTEL_GEN(dev_priv) >= 10) ?
>> >
>> > I am not clear on what qualifies for a place in device_info, but
>> > defining it this way let's me go to the definition and quickly check
>> > which platform has 2 pixels per clock.

One thing I always wanted was to avoid 2 places to declare features &
capabilities.
Here or on the platform.

>>
>> A couple of rules of thumb for starting with:
>>
>> Use device_info if:
>>
>>  - it fundamentally changes how the device operates, such that knowing
>>about it in debug logs is a key means of triage

I think on this one 2ppc qualifies

>>
>>  - number of branches x callsites > 8

2 * 5 > 8 in this case?
or I'm getting the number of "branches" incorrectly?

What I was trying to save as well is the addition of any next platform.
When adding the feature it would be easier to search for HAS_2PPC instead of
searching for glk or cnl and analising that individually to see if it
is 2pp before
 see if it applies to that platform.

But the reason that I put this patch on top is that I don't have
strong opinion here so
t would be fine for me to move on without ht.

Thanks,
Rodrigo.

>>(some estimate of the cost of inclusion inside device_info vs
>>savings in object code, for a more realistic estimate a branch will
>>~12 bytes (depending on the phase of the moon) and cost for device
>>info will be the addition of a few strings, and a couple of calls
>>to use those string, so at a guess 100 bytes.)
>
> That's an interesting back-of-the-envelope calculation. I suppose the
> compiler is also more likely to load device_info->gen into a register
> than device_info->has_2ppc.
>
>
>>
>> -Chris
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-- 
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Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH] drm/i915: Add interface to reserve fence registers for vGPU

[Du, Changbin]

Hi chris,

On Wed, Aug 30, 2017 at 10:27:18AM +0100, Chris Wilson wrote:
> Quoting changbin...@intel.com (2017-08-30 09:54:21)
> > This patch added two new api to the fence management code:
> >  - i915_reserve_one_fence() will try to find a free fence from fence_list
> >and force-remove vma if need.
> >  - i915_giveback_reserved_fence() reclaim a reserved fence after vGPU has
> >finished.
> 
> Symmetry: reserve_fence, unreserve_fence.
>
ok, I will rename the functions.

> We need a safeguard here so that the host is able to always able allocate
> to allocate a fence for the display engine. (That requirement should be
> quite soft for modern hw, nevertheless it should be in the design to
> prevent overuse from leading to an unusable system.)
> -Chris
Yes, agree. Is there any other components always need a fence ready? otherwise,
I will add a safeguard to ensure at least 1 fence register remained for host.

-- 
Thanks,
Changbin Du


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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Introduce HAS_2PPC.

[Pandiyan, Dhinakaran]

On Wed, 2017-08-30 at 20:32 +0100, Chris Wilson wrote:
> Quoting Pandiyan, Dhinakaran (2017-08-30 20:12:52)
> > On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> > > Let's make it easier to add platforms that supports 2 pixel per
> > > clock.
> > > 
> > > With spread checks per platform it was easy to miss one or
> > > another spot leading to loose some time on debug.
> > > 
> > > Hopefully this check would save some cases in the future.
> > > 
> > > No functional change.
> > > 
> > > Cc: Paulo Zanoni 
> > > Cc: Dhinakaran Pandiyan 
> > > Cc: Ville Syrjälä 
> > > Signed-off-by: Rodrigo Vivi 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h| 4 
> > >  drivers/gpu/drm/i915/i915_pci.c| 2 ++
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 8 
> > >  drivers/gpu/drm/i915/intel_pm.c| 3 +--
> > >  4 files changed, 11 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 6c25c8520c87..94f5e6522e5e 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -748,6 +748,7 @@ struct intel_csr {
> > >   func(is_lp); \
> > >   func(is_alpha_support); \
> > >   /* Keep has_* in alphabetical order */ \
> > > + func(has_2ppc); \
> > >   func(has_64bit_reloc); \
> > >   func(has_aliasing_ppgtt); \
> > >   func(has_csr); \
> > > @@ -3025,6 +3026,9 @@ intel_info(const struct drm_i915_private *dev_priv)
> > >  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> > >   (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> > >  
> > > +/* Supports 2 pixel per clock */
> > > +#define HAS_2PPC(dev_priv) ((dev_priv)->info.has_2ppc)
> > > +
> > 
> > How about
> > #define HAS_2PPC(dev_priv) (IS_GEMINILAKE(dev_priv) ||
> > INTEL_GEN(dev_priv) >= 10) ?
> > 
> > I am not clear on what qualifies for a place in device_info, but
> > defining it this way let's me go to the definition and quickly check
> > which platform has 2 pixels per clock.
> 
> A couple of rules of thumb for starting with:
> 
> Use device_info if:
> 
>  - it fundamentally changes how the device operates, such that knowing
>about it in debug logs is a key means of triage
>  
>  - number of branches x callsites > 8
>(some estimate of the cost of inclusion inside device_info vs
>savings in object code, for a more realistic estimate a branch will
>~12 bytes (depending on the phase of the moon) and cost for device
>info will be the addition of a few strings, and a couple of calls
>to use those string, so at a guess 100 bytes.)

That's an interesting back-of-the-envelope calculation. I suppose the
compiler is also more likely to load device_info->gen into a register
than device_info->has_2ppc.


> 
> -Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Disable DRRS when PSR is enabled

[Vivi, Rodrigo]

On Wed, 2017-08-30 at 17:32 -0700, Radhakrishna Sripada wrote:
> Some platforms donot support PSR and DRRS simultaneously. Deferring
> to PSR when both PSR and DRRS are supported by the panel.
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=10

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10

"Fixes: " is only used to -fixes cherry-picks. Not a case for
this patch.

> Cc: Nicholas Stommel 
> Cc: Dhinakaran Pandiyan 
> Cc: Jani Nikula 
> Cc: Clinton Taylor 
> Cc: Rodrigo Vivi 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d3e5fdf0d2fa..dc7a6721e0dd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5469,11 +5469,6 @@ static void intel_dp_set_drrs_state(struct 
> drm_i915_private *dev_priv,
>   return;
>   }
>  
> - /*
> -  * FIXME: This needs proper synchronization with psr state for some
> -  * platforms that cannot have PSR and DRRS enabled at the same time.
> -  */
> -
>   dig_port = dp_to_dig_port(intel_dp);
>   encoder = _port->base;
>   intel_crtc = to_intel_crtc(encoder->base.crtc);
> @@ -5557,6 +5552,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
>   return;
>   }
>  
> + if (dev_priv->psr.enabled != NULL) {

if (dev_priv->psr.enabled) {
?

> + DRM_DEBUG_KMS("PSR active. Disabling DRRS.\n");
> + return;
> + }
> +
>   mutex_lock(_priv->drrs.mutex);
>   if (WARN_ON(dev_priv->drrs.dp)) {
>   DRM_ERROR("DRRS already enabled\n");

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[Intel-gfx] [PATCH] drm/i915: Disable DRRS when PSR is enabled

[Radhakrishna Sripada]

Some platforms donot support PSR and DRRS simultaneously. Deferring
to PSR when both PSR and DRRS are supported by the panel.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=10
Cc: Nicholas Stommel 
Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Cc: Clinton Taylor 
Cc: Rodrigo Vivi 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d3e5fdf0d2fa..dc7a6721e0dd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5469,11 +5469,6 @@ static void intel_dp_set_drrs_state(struct 
drm_i915_private *dev_priv,
return;
}
 
-   /*
-* FIXME: This needs proper synchronization with psr state for some
-* platforms that cannot have PSR and DRRS enabled at the same time.
-*/
-
dig_port = dp_to_dig_port(intel_dp);
encoder = _port->base;
intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -5557,6 +5552,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
return;
}
 
+   if (dev_priv->psr.enabled != NULL) {
+   DRM_DEBUG_KMS("PSR active. Disabling DRRS.\n");
+   return;
+   }
+
mutex_lock(_priv->drrs.mutex);
if (WARN_ON(dev_priv->drrs.dp)) {
DRM_ERROR("DRRS already enabled\n");
-- 
2.9.3

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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

[Belgaumkar, Vinay]

On 8/30/2017 12:39 PM, Michał Winiarski wrote:

On Wed, Aug 30, 2017 at 10:49:20AM -0700, Belgaumkar, Vinay wrote:



On 8/30/2017 4:12 AM, Michał Winiarski wrote:

On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote:

Added the missing IGT_TEST_DESCRIPTION and some subtest
descriptions.

Signed-off-by: Vinay Belgaumkar 
---
  tests/gem_flink_basic.c | 36 
  1 file changed, 36 insertions(+)

diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
index 26ae7d6..8761e0d 100644
--- a/tests/gem_flink_basic.c
+++ b/tests/gem_flink_basic.c
@@ -36,6 +36,8 @@
  #include 
  #include "drm.h"
+IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by name");
+
  static void
  test_flink(int fd)
  {
@@ -155,14 +157,48 @@ igt_main
igt_fixture
fd = drm_open_driver(DRIVER_INTEL);
+   /* basic:
+   This subtest creates a gem object, and then creates
+   a flink. It tests that we can gain access to the gem
+   object using the flink name.
+
+   Test fails if flink creation/open fails.
+   **/

Please use kernel coding style.
This is not the format we're using for multiline comments.

/*
  *
  */
^^^ This is the format we're using.


Agreed. Will change it to match that style. The multi-line comments in /lib
directory actually use this-
/**
 * 
 */



And on the documentation itself, let's take a quote from the kernel coding
style:
"Comments are good, but there is also a danger of over-commenting.  NEVER
try to explain HOW your code works in a comment: it's much better to
write the code so that the **working** is obvious, and it's a waste of
time to explain badly written code."

Now, let's try to match the tests with the comments:
/* This subtest creates a gem object */
ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, );
igt_assert_eq(ret, 0);

/* and then creates a flink */
flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

/* It tests that we can gain access to the gem object using the flink
 * name
 */
Well... not really, we're not accessing the object in any way.


Yes, but we are trying to open the flink in this line of the test-
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);

I will change it to "open the flink" instead of "access the gem object".



/* Test fails if flink creation/open fails. */
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);


igt_subtest("basic")
test_flink(fd);
+
+   /* double-flink:
+   This test checks if it is possible to create 2 flinks
+   for the same gem object.
+
+   Test fails if 2 flink objects cannot be created.
+   **/

/* This test checks if it is possible to create 2 flinks for the same
 * gem object
 */

flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

flink2.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

/* Test fails if 2 flink objects cannot be created. */
Well - this is handled by the asserts above.
You ignored this assumption in your description for some reason though:
igt_assert(flink2.name == flink.name);


Agreed. Also need to add that comment saying the name remains the same
across the two
applications opening the same gem object.




igt_subtest("double-flink")
test_double_flink(fd);
+
+   /* bad-flink:
+   Use an invalid flink handle.
+
+   DRM_IOCTL_GEM_FLINK ioctl call should return failure.
+   **/

ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert(ret == -1 && errno == ENOENT);

There is also an igt_info message:
igt_info("Testing error return on bad flink ioctl.\n");


True, there is some duplication in the comments at this point.

The documentation that I am adding before the subtest call will be rolled up
by gtkdoc/Sphinx/doxygen, it likely
will not look at the text documentation in the actual code. When we look at
the rolled up documentation, it
is good to have an idea of when a particular test will pass/fail without
having to dig into code.

So, yes, there will be some duplication for existing tests. But if we start
following this method for new tests,
we can have one place to describe what the test does/when does it fail, and
then expand on anything that is
not very clear in the code itself.





igt_subtest("bad-flink")
test_bad_flink(fd);
+
+   /* bad-open:
+   Try to use an invalid flink name.
+
+   DRM_IOCTL_GEM_FLINK ioctl call 

[Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max voltage

[Rodrigo Vivi]

From: "Vivi, Rodrigo" 

On clock recovery this function is called to find out
the max voltage swing level that we could go.

However gen 9 functions use the old buffer translation tables
to figure that out. That table is not valid for CNL
causing an invalid number of entries and an invalid selection
on the max voltage swing level.

v2: Let's use same approach that previous platforms.
v3: Actually use n_entries and avoid duplicated -1.

Cc: Ville Syrjälä 
Cc: Clint Taylor 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 48 +++-
 1 file changed, 38 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d962552e2ccc..9aa508616284 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
int *n_entries)
}
 }
 
+static int cnl_max_level(struct drm_i915_private *dev_priv,
+enum intel_output_type type)
+{
+   int n_entries = 0;
+
+   switch (type) {
+   case INTEL_OUTPUT_DP:
+   cnl_get_buf_trans_dp(dev_priv, _entries);
+   break;
+   case INTEL_OUTPUT_EDP:
+   cnl_get_buf_trans_edp(dev_priv, _entries);
+   break;
+   case INTEL_OUTPUT_HDMI:
+   cnl_get_buf_trans_hdmi(dev_priv, _entries);
+   break;
+   default:
+   MISSING_CASE(type);
+   return 0;
+   }
+
+   return n_entries;
+}
+
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
port)
 {
int n_hdmi_entries;
@@ -1877,19 +1900,24 @@ static void bxt_ddi_vswing_sequence(struct 
drm_i915_private *dev_priv,
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   int n_entries;
+   int n_entries, level;
 
-   if (encoder->type == INTEL_OUTPUT_EDP)
-   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
-   else
-   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   if (IS_CANNONLAKE(dev_priv)) {
+   level = cnl_max_level(dev_priv, encoder->type);
+   } else {
+   if (encoder->type == INTEL_OUTPUT_EDP)
+   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
+   else
+   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   level = n_entries - 1;
+   }
 
-   if (WARN_ON(n_entries < 1))
-   n_entries = 1;
-   if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
-   n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
+   if (WARN_ON(level < 0))
+   level = 0;
+   if (WARN_ON(level > ARRAY_SIZE(index_to_dp_signal_levels) - 1))
+   level = ARRAY_SIZE(index_to_dp_signal_levels) - 1;
 
-   return index_to_dp_signal_levels[n_entries - 1] &
+   return index_to_dp_signal_levels[level] &
DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
-- 
2.13.2

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Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Vivi, Rodrigo]

On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:
> The private PAT management is to support PPAT entry manipulation. Two
> APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
> and intel_ppat_put.
> 
> intel_ppat_get will search for an existing PPAT entry which perfectly
> matches the required PPAT value. If not, it will try to allocate or
> return a partially matched PPAT entry if there is any available PPAT
> indexes or not.
> 
> intel_ppat_put will put back the PPAT entry which comes from
> intel_ppat_get. If it's dynamically allocated, the reference count will
> be decreased. If the reference count turns into zero, the PPAT index is
> freed again.
> 
> Besides, another two callbacks are introduced to support the private PAT
> management framework. One is ppat->update_hw(), which writes the PPAT
> configurations in ppat->entries into HW. Another one is ppat->match, which
> will return a score to show how two PPAT values match with each other.
> 
> v6:
> 
> - Address all comments from Chris:
> http://www.spinics.net/lists/intel-gfx/msg136850.html
> 
> - Address all comments from Joonas:
> http://www.spinics.net/lists/intel-gfx/msg136845.html
> 
> v5:
> 
> - Add check and warnnings for those platforms which don't have PPAT.
> 
> v3:
> 
> - Introduce dirty bitmap for PPAT registers. (Chris)
> - Change the name of the pointer "dev_priv" to "i915". (Chris)
> - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)
> 
> v2:
> 
> - API re-design. (Chris)
> 
> Cc: Ben Widawsky 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Signed-off-by: Zhi Wang 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |   2 +
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 273 
> +---
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
>  3 files changed, 262 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7587ef5..5ffde10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2312,6 +2312,8 @@ struct drm_i915_private {
>   DECLARE_HASHTABLE(mm_structs, 7);
>   struct mutex mm_lock;
>  
> + struct intel_ppat ppat;
> +
>   /* Kernel Modesetting */
>  
>   struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b74fa9d..3106142 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
> u64 size)
>   return 0;
>  }
>  
> -static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
> +static struct intel_ppat_entry *
> +__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
>  {
> + struct intel_ppat_entry *entry = >entries[index];
> +
> + GEM_BUG_ON(index >= ppat->max_entries);
> + GEM_BUG_ON(test_bit(index, ppat->used));
> +
> + entry->ppat = ppat;
> + entry->value = value;
> + kref_init(>ref);
> + set_bit(index, ppat->used);
> + set_bit(index, ppat->dirty);
> +
> + return entry;
> +}
> +
> +static void __free_ppat_entry(struct intel_ppat_entry *entry)
> +{
> + struct intel_ppat *ppat = entry->ppat;
> + unsigned int index = entry - ppat->entries;
> +
> + GEM_BUG_ON(index >= ppat->max_entries);
> + GEM_BUG_ON(!test_bit(index, ppat->used));
> +
> + entry->value = ppat->clear_value;
> + clear_bit(index, ppat->used);
> + set_bit(index, ppat->dirty);
> +}
> +
> +/**
> + * intel_ppat_get - get a usable PPAT entry
> + * @i915: i915 device instance
> + * @value: the PPAT value required by the caller
> + *
> + * The function tries to search if there is an existing PPAT entry which
> + * matches with the required value. If perfectly matched, the existing PPAT
> + * entry will be used. If only partially matched, it will try to check if
> + * there is any available PPAT index. If yes, it will allocate a new PPAT
> + * index for the required entry and update the HW. If not, the partially
> + * matched entry will be used.
> + */
> +const struct intel_ppat_entry *
> +intel_ppat_get(struct drm_i915_private *i915, u8 value)
> +{
> + struct intel_ppat *ppat = >ppat;
> + struct intel_ppat_entry *entry;
> + unsigned int scanned, best_score;
> + int i;
> +
> + GEM_BUG_ON(!ppat->max_entries);
> +
> + scanned = best_score = 0;
> +
> + for_each_set_bit(i, ppat->used, ppat->max_entries) {
> + unsigned int score;
> +
> + entry = >entries[i];
> + score = ppat->match(entry->value, value);
> + if (score > best_score) {
> + if (score == INTEL_PPAT_PERFECT_MATCH) {
> + kref_get(>ref);
> +

[Intel-gfx] [RFC i-g-t v1] tests/perf_pmu: test i915 RFC PMU

[Dmitry Rogozhkin]

i915 RFC PMU:
* https://patchwork.freedesktop.org/series/27488/
* https://patchwork.freedesktop.org/series/28842/

Tests:
* init: try to initialize all possible metrics exposed in i915 PMU
  (limit to 0-instance of engines)
* invalid_init: verify that i915 PMU correctly error out on invalid
  initialization
* single: verify that BUSY metrics work for each engine
* parallel: verify that parallel requests for metrics do not conflict
* cpu_online: verify PMU context migration on CPUs going online/offline

v1: add cpu_online test

Signed-off-by: Dmitry Rogozhkin 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
---
 tests/Makefile.sources |   1 +
 tests/perf_pmu.c   | 629 +
 2 files changed, 630 insertions(+)
 create mode 100644 tests/perf_pmu.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..51b684b 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -215,6 +215,7 @@ TESTS_progs = \
kms_vblank \
meta_test \
perf \
+   perf_pmu \
pm_backlight \
pm_lpsp \
pm_rc6_residency \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
new file mode 100644
index 000..428b2f9
--- /dev/null
+++ b/tests/perf_pmu.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "igt_sysfs.h"
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "drm.h"
+
+#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
+#define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
+
+#define USAGE_TOLERANCE 0.02
+
+
+// This is a copy of perf.h from intel-gpu-tools/overlay
+// because I am lazy enough to move it to some common library
+
+
+#include 
+
+enum drm_i915_gem_engine_class {
+   I915_ENGINE_CLASS_OTHER = 0,
+   I915_ENGINE_CLASS_RENDER = 1,
+   I915_ENGINE_CLASS_COPY = 2,
+   I915_ENGINE_CLASS_VIDEO = 3,
+   I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+   I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
+enum drm_i915_pmu_engine_sample {
+   I915_SAMPLE_QUEUED = 0,
+   I915_SAMPLE_BUSY = 1,
+   I915_SAMPLE_WAIT = 2,
+   I915_SAMPLE_SEMA = 3
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+   (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
+
+#define __I915_PMU_ENGINE(class, instance, sample) \
+   ((class) << I915_PMU_CLASS_SHIFT | \
+   (instance) << I915_PMU_SAMPLE_BITS | \
+   (sample))
+
+#define I915_PMU_ENGINE_QUEUED(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED)
+
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
+
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
+
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+
+#define I915_PMU_ACTUAL_FREQUENCY  __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY   __I915_PMU_OTHER(1)
+#define I915_PMU_ENERGY__I915_PMU_OTHER(2)
+#define I915_PMU_INTERRUPTS__I915_PMU_OTHER(3)
+
+#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(4)
+#define I915_PMU_RC6p_RESIDENCY__I915_PMU_OTHER(5)
+#define I915_PMU_RC6pp_RESIDENCY   __I915_PMU_OTHER(6)
+
+static inline int
+perf_event_open(struct perf_event_attr *attr,
+ 

[Intel-gfx] [RFC v3 0/3] Support perf stat with i915 PMU

[Dmitry Rogozhkin]

These patches depend on the RFC patches enabling i915 PMU from Tvrtko:
  https://patchwork.freedesktop.org/series/27488/
Thus, CI failure to build them is expected. I think that my patches should
be squeashed in Tvrtko's one actually.

The first patch simply reorders functions and does nothing comparing to
Tvrtko's patches. Next patches add fixes according to PMU API comments
and clarifications from PMU aware engineers.

v1: Make busy_stats refcounted instead of the whole pmu.

v2: Expose cpumask for the i915 pmu to prevent creation of multiple events
of the same type. Remove perf-driver level sampling.

v3: Add CPUs online/offline tracking to form cpumask.

Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Peter Zijlstra 

Dmitry Rogozhkin (3):
  drm/i915/pmu: reorder function to suite next patch
  drm/i915/pmu: serve global events and support perf stat
  drm/i915/pmu: deny perf driver level sampling of i915 PMU

 drivers/gpu/drm/i915/i915_drv.h |  19 +-
 drivers/gpu/drm/i915/i915_pmu.c | 368 
 drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +-
 3 files changed, 196 insertions(+), 193 deletions(-)

-- 
1.8.3.1

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[Intel-gfx] [RFC v3 3/3] drm/i915/pmu: deny perf driver level sampling of i915 PMU

[Dmitry Rogozhkin]

This patch should probably be squashed with Tvrtko's PMU enabling patch...

As per discussion with Peter, i915 PMU is an example of uncore PMU which
are prohibited to support perf driver level sampling. This patch removes
hrtimer which we expose to perf core and denies events creation with
non-zero event->attr.sampling_period.

Mind that this patch does _not_ remove i915 PMU _internal_ sampling timer.
So, sampling metrics are still gathered, but can be accessed only by
explicit request to get metric counter, i.e. by sys_read().

Change-Id: I33f345f679f0a5a8ecc9867f9e7c1bfb357e708d
Signed-off-by: Dmitry Rogozhkin 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Peter Zijlstra 
---
 drivers/gpu/drm/i915/i915_pmu.c | 89 ++---
 1 file changed, 4 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7bfedb7..edd1e27 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -239,50 +239,6 @@ static int engine_event_init(struct perf_event *event)
return 0;
 }
 
-static DEFINE_PER_CPU(struct pt_regs, i915_pmu_pt_regs);
-
-static enum hrtimer_restart hrtimer_sample(struct hrtimer *hrtimer)
-{
-   struct pt_regs *regs = this_cpu_ptr(_pmu_pt_regs);
-   struct perf_sample_data data;
-   struct perf_event *event;
-   u64 period;
-
-   event = container_of(hrtimer, struct perf_event, hw.hrtimer);
-   if (event->state != PERF_EVENT_STATE_ACTIVE)
-   return HRTIMER_NORESTART;
-
-   event->pmu->read(event);
-
-   perf_sample_data_init(, 0, event->hw.last_period);
-   perf_event_overflow(event, , regs);
-
-   period = max_t(u64, 1, event->hw.sample_period);
-   hrtimer_forward_now(hrtimer, ns_to_ktime(period));
-   return HRTIMER_RESTART;
-}
-
-static void init_hrtimer(struct perf_event *event)
-{
-   struct hw_perf_event *hwc = >hw;
-
-   if (!is_sampling_event(event))
-   return;
-
-   hrtimer_init(>hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
-   hwc->hrtimer.function = hrtimer_sample;
-
-   if (event->attr.freq) {
-   long freq = event->attr.sample_freq;
-
-   event->attr.sample_period = NSEC_PER_SEC / freq;
-   hwc->sample_period = event->attr.sample_period;
-   local64_set(>period_left, hwc->sample_period);
-   hwc->last_period = hwc->sample_period;
-   event->attr.freq = 0;
-   }
-}
-
 static int i915_pmu_event_init(struct perf_event *event)
 {
struct drm_i915_private *i915 =
@@ -293,6 +249,10 @@ static int i915_pmu_event_init(struct perf_event *event)
if (event->attr.type != event->pmu->type)
return -ENOENT;
 
+   /* unsupported modes and filters */
+   if (event->attr.sample_period) /* no sampling */
+   return -EINVAL;
+
if (has_branch_stack(event))
return -EOPNOTSUPP;
 
@@ -328,46 +288,9 @@ static int i915_pmu_event_init(struct perf_event *event)
if (!event->parent)
event->destroy = i915_pmu_event_destroy;
 
-   init_hrtimer(event);
-
return 0;
 }
 
-static void i915_pmu_timer_start(struct perf_event *event)
-{
-   struct hw_perf_event *hwc = >hw;
-   s64 period;
-
-   if (!is_sampling_event(event))
-   return;
-
-   period = local64_read(>period_left);
-   if (period) {
-   if (period < 0)
-   period = 1;
-
-   local64_set(>period_left, 0);
-   } else {
-   period = max_t(u64, 1, hwc->sample_period);
-   }
-
-   hrtimer_start_range_ns(>hrtimer,
-  ns_to_ktime(period), 0,
-  HRTIMER_MODE_REL_PINNED);
-}
-
-static void i915_pmu_timer_cancel(struct perf_event *event)
-{
-   struct hw_perf_event *hwc = >hw;
-
-   if (!is_sampling_event(event))
-   return;
-
-   local64_set(>period_left,
-   ktime_to_ns(hrtimer_get_remaining(>hrtimer)));
-   hrtimer_cancel(>hrtimer);
-}
-
 static bool engine_needs_busy_stats(struct intel_engine_cs *engine)
 {
return supports_busy_stats() &&
@@ -493,8 +416,6 @@ static void i915_pmu_enable(struct perf_event *event)
}
 
spin_unlock_irqrestore(>pmu.lock, flags);
-
-   i915_pmu_timer_start(event);
 }
 
 static void i915_pmu_disable(struct perf_event *event)
@@ -534,8 +455,6 @@ static void i915_pmu_disable(struct perf_event *event)
i915->pmu.timer_enabled &= pmu_needs_timer(i915, true);
 
spin_unlock_irqrestore(>pmu.lock, flags);
-
-   i915_pmu_timer_cancel(event);
 }
 
 static void i915_pmu_event_start(struct perf_event *event, int flags)
-- 
1.8.3.1

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[Intel-gfx] [RFC v3 1/3] drm/i915/pmu: reorder function to suite next patch

[Dmitry Rogozhkin]

This patch is doing nover except reordering functions to highlight
changes in the next patch.

Change-Id: I0cd298780503ae8f6f8035b86c59fc8b5191356b
Signed-off-by: Dmitry Rogozhkin 
Cc: Tvrtko Ursulin 
Cc: Peter Zijlstra 
---
 drivers/gpu/drm/i915/i915_pmu.c | 180 
 1 file changed, 90 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 3272ec0..bcdf2bc 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -363,6 +363,88 @@ static bool engine_needs_busy_stats(struct intel_engine_cs 
*engine)
   (engine->pmu.enable & BIT(I915_SAMPLE_BUSY));
 }
 
+static u64 count_interrupts(struct drm_i915_private *i915)
+{
+   /* open-coded kstat_irqs() */
+   struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
+   u64 sum = 0;
+   int cpu;
+
+   if (!desc || !desc->kstat_irqs)
+   return 0;
+
+   for_each_possible_cpu(cpu)
+   sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
+
+   return sum;
+}
+
+static void i915_pmu_event_read(struct perf_event *event)
+{
+   struct drm_i915_private *i915 =
+   container_of(event->pmu, typeof(*i915), pmu.base);
+   u64 val = 0;
+
+   if (is_engine_event(event)) {
+   u8 sample = engine_event_sample(event);
+   struct intel_engine_cs *engine;
+
+   engine = intel_engine_lookup_user(i915,
+ engine_event_class(event),
+ engine_event_instance(event));
+
+   if (WARN_ON_ONCE(!engine)) {
+   /* Do nothing */
+   } else if (sample == I915_SAMPLE_BUSY &&
+  engine->pmu.busy_stats) {
+   val = ktime_to_ns(intel_engine_get_busy_time(engine));
+   } else {
+   val = engine->pmu.sample[sample];
+   }
+   } else switch (event->attr.config) {
+   case I915_PMU_ACTUAL_FREQUENCY:
+   val = i915->pmu.sample[__I915_SAMPLE_FREQ_ACT];
+   break;
+   case I915_PMU_REQUESTED_FREQUENCY:
+   val = i915->pmu.sample[__I915_SAMPLE_FREQ_REQ];
+   break;
+   case I915_PMU_ENERGY:
+   val = intel_energy_uJ(i915);
+   break;
+   case I915_PMU_INTERRUPTS:
+   val = count_interrupts(i915);
+   break;
+
+   case I915_PMU_RC6_RESIDENCY:
+   if (!i915->gt.awake)
+   return;
+
+   val = intel_rc6_residency_ns(i915,
+IS_VALLEYVIEW(i915) ?
+VLV_GT_RENDER_RC6 :
+GEN6_GT_GFX_RC6);
+   break;
+
+   case I915_PMU_RC6p_RESIDENCY:
+   if (!i915->gt.awake)
+   return;
+
+   if (!IS_VALLEYVIEW(i915))
+   val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+   break;
+
+   case I915_PMU_RC6pp_RESIDENCY:
+   if (!i915->gt.awake)
+   return;
+
+   if (!IS_VALLEYVIEW(i915))
+   val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+   break;
+   }
+
+   local64_set(>count, val);
+}
+
 static void i915_pmu_enable(struct perf_event *event)
 {
struct drm_i915_private *i915 =
@@ -440,23 +522,6 @@ static void i915_pmu_disable(struct perf_event *event)
i915_pmu_timer_cancel(event);
 }
 
-static int i915_pmu_event_add(struct perf_event *event, int flags)
-{
-   struct hw_perf_event *hwc = >hw;
-
-   if (flags & PERF_EF_START)
-   i915_pmu_enable(event);
-
-   hwc->state = !(flags & PERF_EF_START);
-
-   return 0;
-}
-
-static void i915_pmu_event_del(struct perf_event *event, int flags)
-{
-   i915_pmu_disable(event);
-}
-
 static void i915_pmu_event_start(struct perf_event *event, int flags)
 {
i915_pmu_enable(event);
@@ -467,86 +532,21 @@ static void i915_pmu_event_stop(struct perf_event *event, 
int flags)
i915_pmu_disable(event);
 }
 
-static u64 count_interrupts(struct drm_i915_private *i915)
+static int i915_pmu_event_add(struct perf_event *event, int flags)
 {
-   /* open-coded kstat_irqs() */
-   struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
-   u64 sum = 0;
-   int cpu;
+   struct hw_perf_event *hwc = >hw;
 
-   if (!desc || !desc->kstat_irqs)
-   return 0;
+   if (flags & PERF_EF_START)
+   i915_pmu_enable(event);
 
-   for_each_possible_cpu(cpu)
-   sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
+   hwc->state = !(flags & PERF_EF_START);
 
-   return sum;
+ 

[Intel-gfx] [RFC v3 2/3] drm/i915/pmu: serve global events and support perf stat

[Dmitry Rogozhkin]

This patch should probably be squashed with Tvrtko's PMU enabling
patch...

Making perf-stat workable with i915 PMU. The major point is that
current implementation of i915 PMU exposes global counter rather
thatn per-task counters. Thus, required changes are:
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)

Examples:
perf stat -e i915/rcs0-busy/ workload.sh
   This should error out with "failed to read counter" because the
requested counter can't be queried in per-task mode (which is the case).

perf stat -e i915/rcs0-busy/ -a workload.sh
perf stat -e i915/rcs0-busy/ -a -C0 workload.sh
   These 2 commands should give the same result with the correct counter
values. Counter value will be queried once in the end of the wrokload.
The example output would be:

 Performance counter stats for 'system wide':
   649,547,987  i915/rcs0-busy/

   1.895530680 seconds time elapsed

perf stat -e i915/rcs0-busy/ -a -I 100 workload.sh
   This will query counter perdiodically (each 100ms) and dump output:

 0.100108369  4,137,438  i915/rcs0-busy/
i915/rcs0-busy/: 37037414 100149071 100149071
 0.200249024 37,037,414  i915/rcs0-busy/
i915/rcs0-busy/: 36935429 100145077 100145077
 0.300391916 36,935,429  i915/rcs0-busy/
i915/rcs0-busy/: 34262017 100126136 100126136
 0.400518037 34,262,017  i915/rcs0-busy/
i915/rcs0-busy/: 34539960 100126217 100126217

v1: Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.

v2: Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.

v3: Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.

Change-Id: I7d1abe747a4399196e72253f7b66441a6528dbee
Signed-off-by: Dmitry Rogozhkin 
Cc: Tvrtko Ursulin 
Cc: Peter Zijlstra 

cpumask

Change-Id: I145f59240b75f2b703e0531ec81af6cd05aae95c
Signed-off-by: Dmitry Rogozhkin 
---
 drivers/gpu/drm/i915/i915_drv.h |  19 +++---
 drivers/gpu/drm/i915/i915_pmu.c | 115 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +-
 3 files changed, 110 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b59da2c..e629e5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2153,6 +2153,16 @@ enum {
__I915_NUM_PMU_SAMPLERS
 };
 
+struct i915_pmu {
+   struct hlist_node node;
+   struct pmu base;
+   spinlock_t lock;
+   struct hrtimer timer;
+   bool timer_enabled;
+   u64 enable;
+   u64 sample[__I915_NUM_PMU_SAMPLERS];
+};
+
 struct drm_i915_private {
struct drm_device drm;
 
@@ -2660,14 +2670,7 @@ struct drm_i915_private {
int irq;
} lpe_audio;
 
-   struct {
-   struct pmu base;
-   spinlock_t lock;
-   struct hrtimer timer;
-   bool timer_enabled;
-   u64 enable;
-   u64 sample[__I915_NUM_PMU_SAMPLERS];
-   } pmu;
+   struct i915_pmu pmu;
 
/*
 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index bcdf2bc..7bfedb7 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -15,6 +15,8 @@
 
 #define ENGINE_SAMPLE_BITS (16)
 
+static cpumask_t i915_pmu_cpumask = CPU_MASK_NONE;
+
 static u8 engine_config_sample(u64 config)
 {
return config & I915_PMU_SAMPLE_MASK;
@@ -285,16 +287,24 @@ static int i915_pmu_event_init(struct perf_event *event)
 {
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+   int cpu;
int ret;
 
-   /* XXX ideally only want pid == -1 && cpu == -1 */
-
if (event->attr.type != event->pmu->type)
return -ENOENT;
 
if (has_branch_stack(event))
return -EOPNOTSUPP;
 
+   if (event->cpu < 0)
+   return -EINVAL;
+
+   cpu = cpumask_any_and(_pmu_cpumask,
+   topology_sibling_cpumask(event->cpu));
+
+   if (cpu >= nr_cpu_ids)
+   return -ENODEV;
+
ret = 0;
if (is_engine_event(event)) {
ret = engine_event_init(event);
@@ -314,6 +324,7 @@ static int i915_pmu_event_init(struct perf_event *event)
if (ret)
return ret;
 
+   event->cpu = cpu;
if (!event->parent)
 

[Intel-gfx] [PATCH] dim: filter thisimage files

[Daniel Vetter]

They're just temporary files used by git. From rerere.c in the git
sources:

/*
 * Normalize the conflicts in path and write it out to
 * "thisimage" temporary file.
 */

Reported by Rodrigo.

v2: use find, not grep (Jani).

v3: Don't piss of shellcheck (Rodrigo).

Signed-off-by: Daniel Vetter 
---
 dim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dim b/dim
index 11aa675cc3bc..940bc89104f7 100755
--- a/dim
+++ b/dim
@@ -545,7 +545,7 @@ function commit_rerere_cache
git rm $file &> /dev/null
fi
done
-   find rr-cache/ -mtime -1 -type f -print0 | xargs -0 git add > 
/dev/null
+   find rr-cache/ -mtime -1 -type f -not -name "thisimage*" 
-print0 | xargs -0 git add > /dev/null
git rm rr-cache/rr-cache &> /dev/null || true
if git commit -m "$time: $integration_branch rerere cache 
update" >& /dev/null; then
echo -n "New commit. "
-- 
2.14.1

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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

[Michał Winiarski]

On Wed, Aug 30, 2017 at 10:49:20AM -0700, Belgaumkar, Vinay wrote:
> 
> 
> On 8/30/2017 4:12 AM, Michał Winiarski wrote:
> > On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote:
> > > Added the missing IGT_TEST_DESCRIPTION and some subtest
> > > descriptions.
> > > 
> > > Signed-off-by: Vinay Belgaumkar 
> > > ---
> > >   tests/gem_flink_basic.c | 36 
> > >   1 file changed, 36 insertions(+)
> > > 
> > > diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
> > > index 26ae7d6..8761e0d 100644
> > > --- a/tests/gem_flink_basic.c
> > > +++ b/tests/gem_flink_basic.c
> > > @@ -36,6 +36,8 @@
> > >   #include 
> > >   #include "drm.h"
> > > +IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by 
> > > name");
> > > +
> > >   static void
> > >   test_flink(int fd)
> > >   {
> > > @@ -155,14 +157,48 @@ igt_main
> > >   igt_fixture
> > >   fd = drm_open_driver(DRIVER_INTEL);
> > > + /* basic:
> > > + This subtest creates a gem object, and then creates
> > > + a flink. It tests that we can gain access to the gem
> > > + object using the flink name.
> > > +
> > > + Test fails if flink creation/open fails.
> > > + **/
> > Please use kernel coding style.
> > This is not the format we're using for multiline comments.
> > 
> > /*
> >   *
> >   */
> > ^^^ This is the format we're using.
> 
> Agreed. Will change it to match that style. The multi-line comments in /lib
> directory actually use this-
> /**
>  * 
>  */
> 
> > 
> > And on the documentation itself, let's take a quote from the kernel coding
> > style:
> > "Comments are good, but there is also a danger of over-commenting.  NEVER
> > try to explain HOW your code works in a comment: it's much better to
> > write the code so that the **working** is obvious, and it's a waste of
> > time to explain badly written code."
> > 
> > Now, let's try to match the tests with the comments:
> > /* This subtest creates a gem object */
> > ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, );
> > igt_assert_eq(ret, 0);
> > 
> > /* and then creates a flink */
> > flink.handle = create.handle;
> > ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
> > igt_assert_eq(ret, 0);
> > 
> > /* It tests that we can gain access to the gem object using the flink
> >  * name
> >  */
> > Well... not really, we're not accessing the object in any way.
> 
> Yes, but we are trying to open the flink in this line of the test-
> open_struct.name = flink.name;
> ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
> igt_assert_eq(ret, 0);
> igt_assert(open_struct.handle != 0);
> 
> I will change it to "open the flink" instead of "access the gem object".
> 
> > 
> > /* Test fails if flink creation/open fails. */
> > open_struct.name = flink.name;
> > ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
> > igt_assert_eq(ret, 0);
> > igt_assert(open_struct.handle != 0);
> > 
> > >   igt_subtest("basic")
> > >   test_flink(fd);
> > > +
> > > + /* double-flink:
> > > + This test checks if it is possible to create 2 flinks
> > > + for the same gem object.
> > > +
> > > + Test fails if 2 flink objects cannot be created.
> > > + **/
> > /* This test checks if it is possible to create 2 flinks for the same
> >  * gem object
> >  */
> > 
> > flink.handle = create.handle;
> > ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
> > igt_assert_eq(ret, 0);
> > 
> > flink2.handle = create.handle;
> > ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
> > igt_assert_eq(ret, 0);
> > 
> > /* Test fails if 2 flink objects cannot be created. */
> > Well - this is handled by the asserts above.
> > You ignored this assumption in your description for some reason though:
> > igt_assert(flink2.name == flink.name);
> 
> Agreed. Also need to add that comment saying the name remains the same
> across the two
> applications opening the same gem object.
> 
> > 
> > >   igt_subtest("double-flink")
> > >   test_double_flink(fd);
> > > +
> > > + /* bad-flink:
> > > + Use an invalid flink handle.
> > > +
> > > + DRM_IOCTL_GEM_FLINK ioctl call should return failure.
> > > + **/
> > ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
> > igt_assert(ret == -1 && errno == ENOENT);
> > 
> > There is also an igt_info message:
> > igt_info("Testing error return on bad flink ioctl.\n");
> 
> True, there is some duplication in the comments at this point.
> 
> The documentation that I am adding before the subtest call will be rolled up
> by gtkdoc/Sphinx/doxygen, it likely
> will not look at the text documentation in the actual code. When we look at
> the rolled up documentation, it
> is good to have an idea of when a particular test will pass/fail without
> having to dig into code.
> 
> So, yes, there will be some duplication for existing tests. But if we start
> following this method for 

Re: [Intel-gfx] [RFC PATCH 4/4] drm/i915: reprogram NOA muxes on context switch when using perf

[Lionel Landwerlin]

On 30/08/17 20:15, Chris Wilson wrote:

Quoting Lionel Landwerlin (2017-08-30 19:20:06)

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram then at
context switch.

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
  drivers/gpu/drm/i915/i915_perf.c | 77 
  drivers/gpu/drm/i915/intel_lrc.c | 64 ++---
  drivers/gpu/drm/i915/intel_lrc.h |  1 +
  4 files changed, 140 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0003b46b6840..d4b3e5da9009 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3685,6 +3685,8 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, 
void *data,
  void i915_oa_init_reg_state(struct intel_engine_cs *engine,
 struct i915_gem_context *ctx,
 uint32_t *reg_state);
+u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv);
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch);
  
  /* i915_gem_evict.c */

  int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..b74ffbb47879 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1687,6 +1687,74 @@ static int gen8_emit_oa_config(struct 
drm_i915_gem_request *req,
 return 0;
  }
  
+#define MAX_LRI_SIZE (125U)

+
+u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv)
+{
+   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+
+   lockdep_assert_held(_priv->drm.struct_mutex);

Still not happy by this coupling to struct_mutex. :-p

Missed RCS check.


+
+   /* Perf not supported. */
+   if (!dev_priv->perf.initialized)
+   return 0;
+
+   /* OA not currently configured. */
+   if (!stream)
+   return 0;
+
+   /* Very unlikely but possible that we have no muxes to configure. */
+   if (!stream->oa_config->mux_regs_len)
+   return 0;
+
+   /* Return the size of MI_LOAD_REGISTER_IMMs. */
+   return (stream->oa_config->mux_regs_len / MAX_LRI_SIZE) * 4 + 4 +
+   stream->oa_config->mux_regs_len * 8;
+}
+
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+   u32 n_lri, n_mux_regs;
+   u32 i;
+
+   lockdep_assert_held(_priv->drm.struct_mutex);
+
+   /* We only care about RCS. */
+   if (engine->id != RCS)
+   return batch;
+
+   /* Perf not supported. */
+   if (!dev_priv->perf.initialized)
+   return batch;
+
+   /* OA not currently configured. */
+   if (!stream)
+   return batch;
+
+   /* It's very unlikely, but possible that we're dealing with a config
+* with no mux to configure.
+*/
+   if (!stream->oa_config->mux_regs_len)
+   return batch;

The above could be condensed into
if (i915_oa_get_perctx_bb_size() == 0)
return;


+
+   n_mux_regs = stream->oa_config->mux_regs_len;
+   n_lri = (n_mux_regs / MAX_LRI_SIZE) + (n_mux_regs % MAX_LRI_SIZE) != 0;
+
+   for (i = 0; i < n_mux_regs; i++) {
+   if ((i % MAX_LRI_SIZE) == 0) {
+   n_lri = min(n_mux_regs - i, MAX_LRI_SIZE);
+   *batch++ = MI_LOAD_REGISTER_IMM(n_lri);
+   }
+
+   *batch++ = 
i915_mmio_reg_offset(stream->oa_config->mux_regs[i].addr);
+   *batch++ = stream->oa_config->mux_regs[i].value;
+   }

I would have personally used a double loop. But at least kill that first
n_lri, that was a moment of confusion spent trying to work out what you
were using it for.


+
+   return batch;
+}
  /**
   * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
@@ -1055,6 +1057,8 @@ static u32 *gen8_init_indirectctx_bb(struct 
intel_engine_cs *engine, u32 *batch)
   */
  static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
  {
+   batch = i915_oa_emit_perctx_bb(engine, batch);
+
 /* WaDisableCtxRestoreArbitration:bdw,chv */
 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
 *batch++ = MI_BATCH_BUFFER_END;
@@ -1118,21 +1122,27 @@ static u32 *gen9_init_indirectctx_bb(struct 
intel_engine_cs *engine, u32 *batch)
  
  static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)

  {
+   batch = i915_oa_emit_perctx_bb(engine, batch);

Wrong wa_bb. This is emitted at the start of every bb, you want
indirectctx_bb which is 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Introduce HAS_2PPC.

[Chris Wilson]

Quoting Pandiyan, Dhinakaran (2017-08-30 20:12:52)
> On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> > Let's make it easier to add platforms that supports 2 pixel per
> > clock.
> > 
> > With spread checks per platform it was easy to miss one or
> > another spot leading to loose some time on debug.
> > 
> > Hopefully this check would save some cases in the future.
> > 
> > No functional change.
> > 
> > Cc: Paulo Zanoni 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h| 4 
> >  drivers/gpu/drm/i915/i915_pci.c| 2 ++
> >  drivers/gpu/drm/i915/intel_cdclk.c | 8 
> >  drivers/gpu/drm/i915/intel_pm.c| 3 +--
> >  4 files changed, 11 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 6c25c8520c87..94f5e6522e5e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -748,6 +748,7 @@ struct intel_csr {
> >   func(is_lp); \
> >   func(is_alpha_support); \
> >   /* Keep has_* in alphabetical order */ \
> > + func(has_2ppc); \
> >   func(has_64bit_reloc); \
> >   func(has_aliasing_ppgtt); \
> >   func(has_csr); \
> > @@ -3025,6 +3026,9 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> >   (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> >  
> > +/* Supports 2 pixel per clock */
> > +#define HAS_2PPC(dev_priv) ((dev_priv)->info.has_2ppc)
> > +
> 
> How about
> #define HAS_2PPC(dev_priv) (IS_GEMINILAKE(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10) ?
> 
> I am not clear on what qualifies for a place in device_info, but
> defining it this way let's me go to the definition and quickly check
> which platform has 2 pixels per clock.

A couple of rules of thumb for starting with:

Use device_info if:

 - it fundamentally changes how the device operates, such that knowing
   about it in debug logs is a key means of triage
 
 - number of branches x callsites > 8
   (some estimate of the cost of inclusion inside device_info vs
   savings in object code, for a more realistic estimate a branch will
   ~12 bytes (depending on the phase of the moon) and cost for device
   info will be the addition of a few strings, and a couple of calls
   to use those string, so at a guess 100 bytes.)

-Chris
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Re: [Intel-gfx] [RFC PATCH 4/4] drm/i915: reprogram NOA muxes on context switch when using perf

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-30 19:20:06)
> If some of the contexts submitting workloads to the GPU have been
> configured to shutdown slices/subslices, we might loose the NOA
> configurations written in the NOA muxes. We need to reprogram then at
> context switch.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
>  drivers/gpu/drm/i915/i915_perf.c | 77 
> 
>  drivers/gpu/drm/i915/intel_lrc.c | 64 ++---
>  drivers/gpu/drm/i915/intel_lrc.h |  1 +
>  4 files changed, 140 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0003b46b6840..d4b3e5da9009 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3685,6 +3685,8 @@ int i915_perf_remove_config_ioctl(struct drm_device 
> *dev, void *data,
>  void i915_oa_init_reg_state(struct intel_engine_cs *engine,
> struct i915_gem_context *ctx,
> uint32_t *reg_state);
> +u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv);
> +u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch);
>  
>  /* i915_gem_evict.c */
>  int __must_check i915_gem_evict_something(struct i915_address_space *vm,
> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
> b/drivers/gpu/drm/i915/i915_perf.c
> index 94185d610673..b74ffbb47879 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1687,6 +1687,74 @@ static int gen8_emit_oa_config(struct 
> drm_i915_gem_request *req,
> return 0;
>  }
>  
> +#define MAX_LRI_SIZE (125U)
> +
> +u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv)
> +{
> +   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
> +
> +   lockdep_assert_held(_priv->drm.struct_mutex);

Still not happy by this coupling to struct_mutex. :-p

Missed RCS check.

> +
> +   /* Perf not supported. */
> +   if (!dev_priv->perf.initialized)
> +   return 0;
> +
> +   /* OA not currently configured. */
> +   if (!stream)
> +   return 0;
> +
> +   /* Very unlikely but possible that we have no muxes to configure. */
> +   if (!stream->oa_config->mux_regs_len)
> +   return 0;
> +
> +   /* Return the size of MI_LOAD_REGISTER_IMMs. */
> +   return (stream->oa_config->mux_regs_len / MAX_LRI_SIZE) * 4 + 4 +
> +   stream->oa_config->mux_regs_len * 8;
> +}
> +
> +u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
> +{
> +   struct drm_i915_private *dev_priv = engine->i915;
> +   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
> +   u32 n_lri, n_mux_regs;
> +   u32 i;
> +
> +   lockdep_assert_held(_priv->drm.struct_mutex);
> +
> +   /* We only care about RCS. */
> +   if (engine->id != RCS)
> +   return batch;
> +
> +   /* Perf not supported. */
> +   if (!dev_priv->perf.initialized)
> +   return batch;
> +
> +   /* OA not currently configured. */
> +   if (!stream)
> +   return batch;
> +
> +   /* It's very unlikely, but possible that we're dealing with a config
> +* with no mux to configure.
> +*/
> +   if (!stream->oa_config->mux_regs_len)
> +   return batch;

The above could be condensed into
if (i915_oa_get_perctx_bb_size() == 0)
return;

> +
> +   n_mux_regs = stream->oa_config->mux_regs_len;
> +   n_lri = (n_mux_regs / MAX_LRI_SIZE) + (n_mux_regs % MAX_LRI_SIZE) != 
> 0;
> +
> +   for (i = 0; i < n_mux_regs; i++) {
> +   if ((i % MAX_LRI_SIZE) == 0) {
> +   n_lri = min(n_mux_regs - i, MAX_LRI_SIZE);
> +   *batch++ = MI_LOAD_REGISTER_IMM(n_lri);
> +   }
> +
> +   *batch++ = 
> i915_mmio_reg_offset(stream->oa_config->mux_regs[i].addr);
> +   *batch++ = stream->oa_config->mux_regs[i].value;
> +   }

I would have personally used a double loop. But at least kill that first
n_lri, that was a moment of confusion spent trying to work out what you
were using it for.

> +
> +   return batch;
> +}

>  /**
>   * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
> @@ -1055,6 +1057,8 @@ static u32 *gen8_init_indirectctx_bb(struct 
> intel_engine_cs *engine, u32 *batch)
>   */
>  static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
>  {
> +   batch = i915_oa_emit_perctx_bb(engine, batch);
> +
> /* WaDisableCtxRestoreArbitration:bdw,chv */
> *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> *batch++ = MI_BATCH_BUFFER_END;
> @@ -1118,21 +1122,27 @@ static u32 *gen9_init_indirectctx_bb(struct 
> intel_engine_cs *engine, u32 *batch)
>  
>  static u32 *gen9_init_perctx_bb(struct 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Introduce HAS_2PPC.

[Pandiyan, Dhinakaran]

On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> Let's make it easier to add platforms that supports 2 pixel per
> clock.
> 
> With spread checks per platform it was easy to miss one or
> another spot leading to loose some time on debug.
> 
> Hopefully this check would save some cases in the future.
> 
> No functional change.
> 
> Cc: Paulo Zanoni 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_drv.h| 4 
>  drivers/gpu/drm/i915/i915_pci.c| 2 ++
>  drivers/gpu/drm/i915/intel_cdclk.c | 8 
>  drivers/gpu/drm/i915/intel_pm.c| 3 +--
>  4 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6c25c8520c87..94f5e6522e5e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -748,6 +748,7 @@ struct intel_csr {
>   func(is_lp); \
>   func(is_alpha_support); \
>   /* Keep has_* in alphabetical order */ \
> + func(has_2ppc); \
>   func(has_64bit_reloc); \
>   func(has_aliasing_ppgtt); \
>   func(has_csr); \
> @@ -3025,6 +3026,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
>   (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>  
> +/* Supports 2 pixel per clock */
> +#define HAS_2PPC(dev_priv) ((dev_priv)->info.has_2ppc)
> +

How about
#define HAS_2PPC(dev_priv) (IS_GEMINILAKE(dev_priv) ||
INTEL_GEN(dev_priv) >= 10) ?

I am not clear on what qualifies for a place in device_info, but
defining it this way let's me go to the definition and quickly check
which platform has 2 pixels per clock.

But again, iirc we won't need this with Ville's changes merged.


>  /*
>   * dp aux and gmbus irq on gen4 seems to be able to generate legacy 
> interrupts
>   * even when in MSI mode. This results in spurious interrupt warnings if the
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 09d97e0990b7..df84025579cf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -405,6 +405,7 @@ static const struct intel_device_info 
> intel_geminilake_info = {
>   GEN9_LP_FEATURES,
>   .platform = INTEL_GEMINILAKE,
>   .ddb_size = 1024,
> + .has_2ppc = 1,
>   .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>  };
>  
> @@ -450,6 +451,7 @@ static const struct intel_device_info 
> intel_cannonlake_info = {
>   .gen = 10,
>   .ddb_size = 1024,
>   .has_csr = 1,
> + .has_2ppc = 1,
>   .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 6b1d805fb755..edbccda40f0c 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1752,7 +1752,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> intel_crtc_state *crtc_state,
>   crtc_state->has_audio &&
>   crtc_state->port_clock >= 54 &&
>   crtc_state->lane_count == 4) {
> - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (HAS_2PPC(dev_priv))
>   pixel_rate = max(2 * 316800, pixel_rate);
>   else
>   pixel_rate = max(432000, pixel_rate);
> @@ -1764,7 +1764,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> intel_crtc_state *crtc_state,
>* two pixels per clock.
>*/
>   if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> + if (HAS_2PPC(dev_priv))
>   pixel_rate = max(2 * 2 * 96000, pixel_rate);
>   else
>   pixel_rate = max(2 * 96000, pixel_rate);
> @@ -1997,14 +1997,14 @@ static int intel_compute_max_dotclk(struct 
> drm_i915_private *dev_priv)
>  {
>   int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
> - if (IS_CANNONLAKE(dev_priv))
> - return 2 * max_cdclk_freq;
>   if (IS_GEMINILAKE(dev_priv))
>   /*
>* FIXME: Limiting to 99% as a temporary workaround. See
>* glk_calc_cdclk() for details.
>*/
>   return 2 * max_cdclk_freq * 99 / 100;
> + else if (HAS_2PPC(dev_priv))
> + return 2 * max_cdclk_freq;
>   else if (INTEL_INFO(dev_priv)->gen >= 9 ||
>IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>   return max_cdclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 42f753df30cb..c8da6ca4e8df 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3969,8 +3969,7 @@ int 

Re: [Intel-gfx] [RFC PATCH 2/4] drm/i915: extract per-ctx/indirect bb programming

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-30 19:20:04)
> Let's put this in its own function to reuse it later.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 33 +++--
>  1 file changed, 19 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 5b96b1e2353d..6da2b4f0c5a5 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1906,6 +1906,23 @@ static u32 intel_lr_indirect_ctx_offset(struct 
> intel_engine_cs *engine)
> return indirect_ctx_offset;
>  }
>  
> +static void execlists_init_reg_state_wa_bb(u32 *regs,
> +  struct intel_engine_cs *engine)
> +{
> +   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
> +   u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

You are going to repeat the !wa_ctx->vma so you might as well pull it
in.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Ville Syrjälä]

On Wed, Aug 30, 2017 at 06:14:03PM +, Pandiyan, Dhinakaran wrote:
> 
> On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> > This is heavily based on a initial patch provided by Ville
> > plus all changes provided later by Ander.
> > 
> 
> Ville abandoned this change last time stating - "Assume 1 pixel per
> clock for the purposes of max pixel rate calculation until DDI clock
> voltage scaling is handled"
> 
> If you can confirm that change was implemented, this patch is
> Reviewed-by: Dhinakaran Pandiyan 
> 
> 
> Also, I see that Ville's patch to change the pixel rate checks to use
> cdclk has not been merged

I totally forgot about that one TBH. I've just reposted first patch to
get a fresh CI run for it.

I think this CNL thing might look cleaner if redone on top of my stuff,
but if people want this in ASAP I can rebase my stuff as well.

> 
> 
> 
> > As Geminilake, Cannonlake also supports 2 pixels per clock.
> > 
> > Different from Geminilake we are not implementing the 99% Wa.
> > But we can revisit that decision later if we find out
> > any limitation on later CNL SKUs.
> > 
> > Cc: Ville Syrjälä 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Jani Nikula 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++--
> >  drivers/gpu/drm/i915/intel_pm.c|  3 ++-
> >  2 files changed, 8 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 1241e5891b29..6b1d805fb755 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1422,9 +1422,9 @@ void bxt_uninit_cdclk(struct drm_i915_private 
> > *dev_priv)
> >  
> >  static int cnl_calc_cdclk(int max_pixclk)
> >  {
> > -   if (max_pixclk > 336000)
> > +   if (max_pixclk > 2 * 336000)
> > return 528000;
> > -   else if (max_pixclk > 168000)
> > +   else if (max_pixclk > 2 * 168000)
> > return 336000;
> > else
> > return 168000;
> > @@ -1752,9 +1752,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> > intel_crtc_state *crtc_state,
> > crtc_state->has_audio &&
> > crtc_state->port_clock >= 54 &&
> > crtc_state->lane_count == 4) {
> > -   if (IS_CANNONLAKE(dev_priv))
> > -   pixel_rate = max(316800, pixel_rate);
> > -   else if (IS_GEMINILAKE(dev_priv))
> > +   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> > pixel_rate = max(2 * 316800, pixel_rate);
> > else
> > pixel_rate = max(432000, pixel_rate);
> > @@ -1766,7 +1764,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> > intel_crtc_state *crtc_state,
> >  * two pixels per clock.
> >  */
> > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> > -   if (IS_GEMINILAKE(dev_priv))
> > +   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> > pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > else
> > pixel_rate = max(2 * 96000, pixel_rate);
> > @@ -1999,6 +1997,8 @@ static int intel_compute_max_dotclk(struct 
> > drm_i915_private *dev_priv)
> >  {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >  
> > +   if (IS_CANNONLAKE(dev_priv))
> > +   return 2 * max_cdclk_freq;
> > if (IS_GEMINILAKE(dev_priv))
> > /*
> >  * FIXME: Limiting to 99% as a temporary workaround. See
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index ed662937ec3c..42f753df30cb 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3969,7 +3969,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
> > *intel_crtc,
> > crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> > dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> >  
> > -   if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> > +   if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)) ||
> > +   IS_CANNONLAKE(to_i915(intel_crtc->base.dev)))
> > dotclk *= 2;
> >  
> > pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH v4 1/2] drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"

[ville . syrjala]

From: Ville Syrjälä 

Make the min_pixclk thing less confusing by changing it to track
the minimum acceptable cdclk frequency instead. This means moving
the application of the guardbands to a slightly higher level from
the low level platform specific calc_cdclk() functions.

The immediate benefit is elimination of the confusing 2x factors
on GLK/CNL+ in the audio workarounds (which stems from the fact
that the pipes produce two pixels per clock).

v2: Keep cdclk higher on CNL to workaround missing DDI clock voltage handling
v3: Squash with the CNL cdclk limits patch (DK)
v4: s/intel_min_cdclk/intel_pixel_rate_to_cdclk/ (DK)

Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 
Cc: Maarten Lankhorst 
Reviewed-by: Dhinakaran Pandiyan 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  12 ++-
 drivers/gpu/drm/i915/intel_cdclk.c   | 202 ++-
 drivers/gpu/drm/i915/intel_display.c |  21 ++--
 drivers/gpu/drm/i915/intel_drv.h |   4 +-
 4 files changed, 125 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..7a20f58e711a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -569,6 +569,15 @@ struct i915_hotplug {
 (__i)++) \
for_each_if (plane_state)
 
+#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
+   for ((__i) = 0; \
+(__i) < (__state)->base.dev->mode_config.num_crtc && \
+((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (new_crtc_state) = 
to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+(__i)++) \
+   for_each_if (crtc)
+
+
 struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
@@ -2335,7 +2344,8 @@ struct drm_i915_private {
struct mutex dpll_lock;
 
unsigned int active_crtcs;
-   unsigned int min_pixclk[I915_MAX_PIPES];
+   /* minimum acceptable cdclk for each pipe */
+   int min_cdclk[I915_MAX_PIPES];
 
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 1241e5891b29..fafffb04b447 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -417,24 +417,21 @@ static void hsw_get_cdclk(struct drm_i915_private 
*dev_priv,
cdclk_state->cdclk = 54;
 }
 
-static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
- int max_pixclk)
+static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
int freq_320 = (dev_priv->hpll_freq <<  1) % 32 != 0 ?
33 : 32;
-   int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 
/*
 * We seem to get an unstable or solid color picture at 200MHz.
 * Not sure what's wrong. For now use 200MHz only when all pipes
 * are off.
 */
-   if (!IS_CHERRYVIEW(dev_priv) &&
-   max_pixclk > freq_320*limit/100)
+   if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
return 40;
-   else if (max_pixclk > 27*limit/100)
+   else if (min_cdclk > 27)
return freq_320;
-   else if (max_pixclk > 0)
+   else if (min_cdclk > 0)
return 27;
else
return 20;
@@ -612,13 +609,13 @@ static void chv_set_cdclk(struct drm_i915_private 
*dev_priv,
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
-static int bdw_calc_cdclk(int max_pixclk)
+static int bdw_calc_cdclk(int min_cdclk)
 {
-   if (max_pixclk > 54)
+   if (min_cdclk > 54)
return 675000;
-   else if (max_pixclk > 45)
+   else if (min_cdclk > 45)
return 54;
-   else if (max_pixclk > 337500)
+   else if (min_cdclk > 337500)
return 45;
else
return 337500;
@@ -724,23 +721,23 @@ static void bdw_set_cdclk(struct drm_i915_private 
*dev_priv,
 cdclk, dev_priv->cdclk.hw.cdclk);
 }
 
-static int skl_calc_cdclk(int max_pixclk, int vco)
+static int skl_calc_cdclk(int min_cdclk, int vco)
 {
if (vco == 864) {
-   if (max_pixclk > 54)
+   if (min_cdclk > 54)
return 617143;
-   else if (max_pixclk > 432000)
+   else if (min_cdclk > 432000)
return 54;
-   else if (max_pixclk > 308571)
+   else if (min_cdclk > 308571)
return 432000;
else
return 

Re: [Intel-gfx] [RFC PATCH 1/4] drm/i915: use same define size for wa_bb pin/allocation

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-30 19:20:03)
> If we have CTX_WA_BB_OBJ_SIZE we should use it everywhere we want to
> refer to the workaround batchbuffer object rather than using
> PAGE_SIZE.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 3758ff81928d..5b96b1e2353d 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1141,7 +1141,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs 
> *engine)
> goto err;
> }
>  
> -   err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
> +   err = i915_vma_pin(vma, 0, CTX_WA_BB_OBJ_SIZE, PIN_GLOBAL | PIN_HIGH);

It shouldn't be passed there at all; that parameter is for overriding
the vma->size.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] lib/tests: Add audio selftest

[Lyude Paul]

On Wed, 2017-08-30 at 17:45 +0300, Paul Kocialkowski wrote:
> This introduces a selftest for the audio library.
> 
> It consists of generating a signal from a list of frequencies and
> ensuring that the integrity checking function does detect these
> frequencies (and only these frequencies).
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/tests/Makefile.am  |  2 +-
>  lib/tests/Makefile.sources |  5 
>  lib/tests/igt_audio.c  | 57
> ++
>  3 files changed, 63 insertions(+), 1 deletion(-)
>  create mode 100644 lib/tests/igt_audio.c
> 
> diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
> index 5d14194a..b1caa628 100644
> --- a/lib/tests/Makefile.am
> +++ b/lib/tests/Makefile.am
> @@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
>   -DIGT_DATADIR=\""$(abs_srcdir)"\" \
>   $(NULL)
>  
> -LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS)
> $(TIMER_LIBS)
> +LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(GSL_CFLAGS)
> $(LIBUNWIND_LIBS) $(TIMER_LIBS)
>  
>  LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) -lm
>  AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
> diff --git a/lib/tests/Makefile.sources b/lib/tests/Makefile.sources
> index 8d1a8dea..eb702844 100644
> --- a/lib/tests/Makefile.sources
> +++ b/lib/tests/Makefile.sources
> @@ -18,6 +18,11 @@ check_prog_list = \
>   igt_can_fail_simple \
>   $(NULL)
>  
> +#if HAVE_GSL
> +check_prog_list += \
> + igt_audio
> +#endif
> +
>  TESTS = \
>   $(check_prog_list) \
>   $(check_script_list) \
> diff --git a/lib/tests/igt_audio.c b/lib/tests/igt_audio.c
> new file mode 100644
> index ..2354d5a0
> --- /dev/null
> +++ b/lib/tests/igt_audio.c
> @@ -0,0 +1,57 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "igt_core.h"
> +#include "igt_audio.h"
> +
> +static int test_frequencies[] = {
> + 300,
> + 600,
> + 1200,
> + 8,
> + 1,
> +};
> +
> +static int test_frequencies_count = sizeof(test_frequencies) / sizeof(int);
> +
> +igt_simple_main
> +{
> + short buffer[2 * 1024];
And just specify the size here explicitly, no need to present it in units of
1024
> + struct audio_signal *signal;
> + int i;
> +
> + signal = audio_signal_init(2, 44800);
> + igt_assert(signal);
> +
> + for (i = 0; i < test_frequencies_count; i++)
Just use ARRAY_SIZE(test_frequencies), no need for test_frequencies_count
> + audio_signal_add_frequency(signal, test_frequencies[i]);
> +
> + audio_signal_synthesize(signal);
> + audio_signal_fill(signal, buffer, 1024);
> +
> + igt_assert(audio_signal_detect(signal, 2, 44800, buffer, 1024));
> +
> + audio_signal_clean(signal);
> + free(signal);
> +}
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t] tests/chamelium: Let the Chamelium itself wait for a stable video input

[Lyude Paul]

On Wed, 2017-08-30 at 13:24 +0300, Paul Kocialkowski wrote:
> On Tue, 2017-08-29 at 15:08 +0300, Paul Kocialkowski wrote:
> > On Mon, 2017-08-28 at 17:55 +0300, Paul Kocialkowski wrote:
> > > Before capturing video, the Chamelium will always wait for the
> > > video
> > > input to be stable (and perform the FSM if it was not). This
> > > means
> > > that
> > > there is no need to explicitly do it beforehand.
> > > 
> > > When the receiver needs to be reset, the call will result in a
> > > timeout,
> > > after which the follow-up call to capture the video will perform
> > > the
> > > FSM
> > > that resets it. Skipping the explicit wait for video input stable
> > > allows
> > > the Chamelium to perform the FSM directly, which saves valuable
> > > time.
> > > 
> > > Removing the associated call does not negatively impact the
> > > execution
> > > of
> > > the CRC and frame comparison tests either.
> > 
> > I got an email from the mailer daemon indicating that this patch
> > could
> > not be delivered to Lyude.
> > 
> > Lyude: did you receive the patch or should I resend it?
> 
> Either way, it's up at: https://patchwork.freedesktop.org/series/2943
> 2/
> 
Yeah I didn't get it the first time but that's ok, weird though...

Anyway, R-B'd and pushed, thanks
> > > Signed-off-by: Paul Kocialkowski
> > > 
> > > ---
> > >  tests/chamelium.c | 3 ---
> > >  1 file changed, 3 deletions(-)
> > > 
> > > diff --git a/tests/chamelium.c b/tests/chamelium.c
> > > index 484bb537..e3d81357 100644
> > > --- a/tests/chamelium.c
> > > +++ b/tests/chamelium.c
> > > @@ -474,9 +474,6 @@ enable_output(data_t *data,
> > >   if (chamelium_port_get_type(port) ==
> > > DRM_MODE_CONNECTOR_VGA)
> > >   usleep(25);
> > >  
> > > - chamelium_port_wait_video_input_stable(data->chamelium,
> > > port,
> > > -HOTPLUG_TIMEOUT);
> > > -
> > >   drmModeFreeConnector(connector);
> > >  }
> > >  
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t] tests/audio: Add suspend and hibernate tests for HDMI signal integrity

[Lyude Paul]

R-B'd and pushed, thanks!

On Tue, 2017-08-29 at 18:35 +0300, Paul Kocialkowski wrote:
> This introduces tests for HDMI signal integrity after suspend and
> hibernate. They simply test that signal integrity is ensured before
> and after suspend or hibernate.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  tests/audio.c | 19 +++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/tests/audio.c b/tests/audio.c
> index 7fb91c97..560876a3 100644
> --- a/tests/audio.c
> +++ b/tests/audio.c
> @@ -167,8 +167,27 @@ static void test_integrity(const char
> *device_name)
>   free(data.alsa);
>  }
>  
> +static void test_suspend_resume_integrity(const char *device_name,
> +   enum igt_suspend_state
> state,
> +   enum igt_suspend_test
> test)
> +{
> + test_integrity(device_name);
> +
> + igt_system_suspend_autoresume(state, test);
> +
> + test_integrity(device_name);
> +}
> +
>  igt_main
>  {
>   igt_subtest("hdmi-integrity")
>   test_integrity("HDMI");
> +
> + igt_subtest("hdmi-integrity-after-suspend")
> + test_suspend_resume_integrity("HDMI",
> SUSPEND_STATE_MEM,
> +   SUSPEND_TEST_NONE);
> +
> + igt_subtest("hdmi-integrity-after-hibernate")
> + test_suspend_resume_integrity("HDMI",
> SUSPEND_STATE_DISK,
> +   SUSPEND_TEST_DEVICES);
>  }
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t] docs/chamelium: Explain that the Chamelium should only target one DUT

[Lyude Paul]

R-B'd and pushed, thanks!

On Tue, 2017-08-29 at 18:11 +0300, Paul Kocialkowski wrote:
> This adds an explanation about why the Chamelium should only be
> connected to one target device at once to the in-tree documentation.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  docs/chamelium.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/docs/chamelium.txt b/docs/chamelium.txt
> index 77594284..ae7ac34a 100644
> --- a/docs/chamelium.txt
> +++ b/docs/chamelium.txt
> @@ -54,6 +54,12 @@ CI system with a shared testlist) to remove the
> Chamelium configuration from the
>  hosts that shouldn't connect to the Chamelium so that they can be
> skipped, which
>  is faster than a network timeout.
>  
> +It should also be noted that each Chamelium platform should only be
> used for
> +testing a single target device at a time. This is because the reset
> call issued
> +by the IGT tests is common to all connectors and thus one machine
> running a test
> +on a given connector may reset the chamelium while another machine
> is running
> +a test on another connector.
> +
>  An example fully-featured configuration follows:
>  [Common]
>  FrameDumpPath=/root/
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t] lib/igt_debugfs: Open DRM driver without master for hpd storm exit

[Lyude Paul]

R-B'd and pushed, thanks!

On Tue, 2017-08-29 at 15:53 +0300, Paul Kocialkowski wrote:
> When running the full chamelium test binary, it occurs that the hpd
> storm exit handler (that restores its initial value) will fail when
> trying to acquire DRM master.
> 
> This happens even though the previously-held DRM file descriptor was
> closed already.
> 
> Since there is no need to get DRM master for debugfs access purposes,
> open the DRM node without requesting master to fix the issue.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/igt_debugfs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> index ee1f0f54..090b56e0 100644
> --- a/lib/igt_debugfs.c
> +++ b/lib/igt_debugfs.c
> @@ -579,7 +579,7 @@ void igt_require_pipe_crc(int fd)
>  
>  static void igt_hpd_storm_exit_handler(int sig)
>  {
> - int fd = drm_open_driver_master(DRIVER_INTEL);
> + int fd = drm_open_driver(DRIVER_INTEL);
>  
>   /* Here we assume that only one i915 device will be ever
> present */
>   igt_hpd_storm_reset(fd);
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [RFC PATCH 0/4] drm/i915: implement NOA mux reprogramming at ctx-switch

[Lionel Landwerlin]

I forgot to mentioned this was tested on SKL GT4 using 2 OA/NOA 
configurations that exposes :


 1. signals of the state of power on each slice/subslice
 2. signals of the number of sampler cache misses on each slice

We verified that the counters incrementing on those signals return to 
normal values when you switch between 2 different context with 2 
different RPCS configurations (as opposed to running the same 
configurations without this series).
We used Chris's series to expose RPCS configuration to userspace : 
https://github.com/djdeath/linux/commit/b2ea9b16ef1377f808be4d4c60f5f23596517f49
You can pull the branch with those changes here : 
https://github.com/djdeath/linux/commits/wip/djdeath/oa-next-slice-control


Cheers,

-
Lionel

On 30/08/17 19:20, Lionel Landwerlin wrote:

Hi all,

This little series implements NOA muxes reprogramming on context
switch through the per context batch buffer.

NOA muxes resides in slices & subslices, which makes their
configuration subject to loss when a slice or subslice is shutdown.
The goal of this series is to restore the configuration on context
switch. It currently reloads all configurations on context switch but
we may be able to be a bit more clever by copying the last RPCS
configuration in memory and compare the current configuration before
executing all the MI_LRIs using a MI_PREDICATE.

Looking forward to comments!

Cheers,

Lionel Landwerlin (4):
   drm/i915: use same define size for wa_bb pin/allocation
   drm/i915: extract per-ctx/indirect bb programming
   drm/i915: pass wa_ctx as argument
   drm/i915: reprogram NOA muxes on context switch when using perf

  drivers/gpu/drm/i915/i915_drv.h  |   2 +
  drivers/gpu/drm/i915/i915_perf.c |  77 +++
  drivers/gpu/drm/i915/intel_lrc.c | 110 ++-
  drivers/gpu/drm/i915/intel_lrc.h |   1 +
  4 files changed, 166 insertions(+), 24 deletions(-)

--
2.14.1



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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add a default case in gen7 hwsp switch-case (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add a default case in gen7 hwsp switch-case (rev2)
URL   : https://patchwork.freedesktop.org/series/29494/
State : success

== Summary ==

Series 29494v2 drm/i915: Add a default case in gen7 hwsp switch-case
https://patchwork.freedesktop.org/api/1.0/series/29494/revisions/2/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:439s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:549s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:257s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:523s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:519s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:513s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:439s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:447s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:475s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:479s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:532s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:468s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:448s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:545s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:406s
fi-skl-6700k failed to connect after reboot

14d5b307c691a24460b991756dc2d501f853e0b3 drm-tip: 2017y-08m-30d-17h-07m-37s UTC 
integration manifest
1be04ad10820 drm/i915: Add a default case in gen7 hwsp switch-case

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5542/
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[Intel-gfx] [RFC PATCH 3/4] drm/i915: pass wa_ctx as argument

[Lionel Landwerlin]

Rather than accessing it from the engine structure. This will be used
for reprogramming later.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6da2b4f0c5a5..c7e7c355b0a7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1125,7 +1125,8 @@ static u32 *gen9_init_perctx_bb(struct intel_engine_cs 
*engine, u32 *batch)
 
 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
 
-static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
+static int lrc_setup_wa_ctx(struct intel_engine_cs *engine,
+   struct i915_ctx_workarounds *wa_ctx)
 {
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -1145,7 +1146,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs 
*engine)
if (err)
goto err;
 
-   engine->wa_ctx.vma = vma;
+   wa_ctx->vma = vma;
return 0;
 
 err:
@@ -1160,9 +1161,9 @@ static void lrc_destroy_wa_ctx(struct intel_engine_cs 
*engine)
 
 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
 
-static int intel_init_workaround_bb(struct intel_engine_cs *engine)
+static int intel_init_workaround_bb(struct intel_engine_cs *engine,
+   struct i915_ctx_workarounds *wa_ctx)
 {
-   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
struct i915_wa_ctx_bb *wa_bb[2] = { _ctx->indirect_ctx,
_ctx->per_ctx };
wa_bb_func_t wa_bb_fn[2];
@@ -1190,7 +1191,7 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return 0;
}
 
-   ret = lrc_setup_wa_ctx(engine);
+   ret = lrc_setup_wa_ctx(engine, wa_ctx);
if (ret) {
DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
return ret;
@@ -1829,7 +1830,7 @@ int logical_render_ring_init(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   ret = intel_init_workaround_bb(engine);
+   ret = intel_init_workaround_bb(engine, >wa_ctx);
if (ret) {
/*
 * We continue even if we fail to initialize WA batch
-- 
2.14.1

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[Intel-gfx] [RFC PATCH 1/4] drm/i915: use same define size for wa_bb pin/allocation

[Lionel Landwerlin]

If we have CTX_WA_BB_OBJ_SIZE we should use it everywhere we want to
refer to the workaround batchbuffer object rather than using
PAGE_SIZE.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3758ff81928d..5b96b1e2353d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1141,7 +1141,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs 
*engine)
goto err;
}
 
-   err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
+   err = i915_vma_pin(vma, 0, CTX_WA_BB_OBJ_SIZE, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err;
 
-- 
2.14.1

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[Intel-gfx] [RFC PATCH 0/4] drm/i915: implement NOA mux reprogramming at ctx-switch

[Lionel Landwerlin]

Hi all,

This little series implements NOA muxes reprogramming on context
switch through the per context batch buffer.

NOA muxes resides in slices & subslices, which makes their
configuration subject to loss when a slice or subslice is shutdown.
The goal of this series is to restore the configuration on context
switch. It currently reloads all configurations on context switch but
we may be able to be a bit more clever by copying the last RPCS
configuration in memory and compare the current configuration before
executing all the MI_LRIs using a MI_PREDICATE.

Looking forward to comments!

Cheers,

Lionel Landwerlin (4):
  drm/i915: use same define size for wa_bb pin/allocation
  drm/i915: extract per-ctx/indirect bb programming
  drm/i915: pass wa_ctx as argument
  drm/i915: reprogram NOA muxes on context switch when using perf

 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_perf.c |  77 +++
 drivers/gpu/drm/i915/intel_lrc.c | 110 ++-
 drivers/gpu/drm/i915/intel_lrc.h |   1 +
 4 files changed, 166 insertions(+), 24 deletions(-)

--
2.14.1
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[Intel-gfx] [RFC PATCH 2/4] drm/i915: extract per-ctx/indirect bb programming

[Lionel Landwerlin]

Let's put this in its own function to reuse it later.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 33 +++--
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5b96b1e2353d..6da2b4f0c5a5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1906,6 +1906,23 @@ static u32 intel_lr_indirect_ctx_offset(struct 
intel_engine_cs *engine)
return indirect_ctx_offset;
 }
 
+static void execlists_init_reg_state_wa_bb(u32 *regs,
+  struct intel_engine_cs *engine)
+{
+   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
+   u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+
+   regs[CTX_RCS_INDIRECT_CTX + 1] =
+   (ggtt_offset + wa_ctx->indirect_ctx.offset) |
+   (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+
+   regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
+   intel_lr_indirect_ctx_offset(engine) << 6;
+
+   regs[CTX_BB_PER_CTX_PTR + 1] =
+   (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
+}
+
 static void execlists_init_reg_state(u32 *regs,
 struct i915_gem_context *ctx,
 struct intel_engine_cs *engine,
@@ -1948,20 +1965,8 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
RING_INDIRECT_CTX_OFFSET(base), 0);
 
-   if (engine->wa_ctx.vma) {
-   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
-   u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
-
-   regs[CTX_RCS_INDIRECT_CTX + 1] =
-   (ggtt_offset + wa_ctx->indirect_ctx.offset) |
-   (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
-
-   regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
-   intel_lr_indirect_ctx_offset(engine) << 6;
-
-   regs[CTX_BB_PER_CTX_PTR + 1] =
-   (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
-   }
+   if (engine->wa_ctx.vma)
+   execlists_init_reg_state_wa_bb(regs, engine);
}
 
regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
-- 
2.14.1

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[Intel-gfx] [RFC PATCH 4/4] drm/i915: reprogram NOA muxes on context switch when using perf

[Lionel Landwerlin]

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram then at
context switch.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_perf.c | 77 
 drivers/gpu/drm/i915/intel_lrc.c | 64 ++---
 drivers/gpu/drm/i915/intel_lrc.h |  1 +
 4 files changed, 140 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0003b46b6840..d4b3e5da9009 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3685,6 +3685,8 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, 
void *data,
 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
uint32_t *reg_state);
+u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv);
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch);
 
 /* i915_gem_evict.c */
 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..b74ffbb47879 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1687,6 +1687,74 @@ static int gen8_emit_oa_config(struct 
drm_i915_gem_request *req,
return 0;
 }
 
+#define MAX_LRI_SIZE (125U)
+
+u32 i915_oa_get_perctx_bb_size(struct drm_i915_private *dev_priv)
+{
+   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+
+   lockdep_assert_held(_priv->drm.struct_mutex);
+
+   /* Perf not supported. */
+   if (!dev_priv->perf.initialized)
+   return 0;
+
+   /* OA not currently configured. */
+   if (!stream)
+   return 0;
+
+   /* Very unlikely but possible that we have no muxes to configure. */
+   if (!stream->oa_config->mux_regs_len)
+   return 0;
+
+   /* Return the size of MI_LOAD_REGISTER_IMMs. */
+   return (stream->oa_config->mux_regs_len / MAX_LRI_SIZE) * 4 + 4 +
+   stream->oa_config->mux_regs_len * 8;
+}
+
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+   u32 n_lri, n_mux_regs;
+   u32 i;
+
+   lockdep_assert_held(_priv->drm.struct_mutex);
+
+   /* We only care about RCS. */
+   if (engine->id != RCS)
+   return batch;
+
+   /* Perf not supported. */
+   if (!dev_priv->perf.initialized)
+   return batch;
+
+   /* OA not currently configured. */
+   if (!stream)
+   return batch;
+
+   /* It's very unlikely, but possible that we're dealing with a config
+* with no mux to configure.
+*/
+   if (!stream->oa_config->mux_regs_len)
+   return batch;
+
+   n_mux_regs = stream->oa_config->mux_regs_len;
+   n_lri = (n_mux_regs / MAX_LRI_SIZE) + (n_mux_regs % MAX_LRI_SIZE) != 0;
+
+   for (i = 0; i < n_mux_regs; i++) {
+   if ((i % MAX_LRI_SIZE) == 0) {
+   n_lri = min(n_mux_regs - i, MAX_LRI_SIZE);
+   *batch++ = MI_LOAD_REGISTER_IMM(n_lri);
+   }
+
+   *batch++ = 
i915_mmio_reg_offset(stream->oa_config->mux_regs[i].addr);
+   *batch++ = stream->oa_config->mux_regs[i].value;
+   }
+
+   return batch;
+}
+
 static int gen8_switch_to_updated_kernel_context(struct drm_i915_private 
*dev_priv,
 const struct i915_oa_config 
*oa_config)
 {
@@ -1793,6 +1861,15 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
if (ret)
goto out;
 
+   /*
+* Reload the workaround batchbuffer to include NOA muxes
+* reprogramming on context-switch, so we don't loose configurations
+* after switch-from a context with disabled slices/subslices.
+*/
+   ret = logical_render_ring_reload_wa_bb(dev_priv->engine[RCS]);
+   if (ret)
+   return ret;
+
/* Update all contexts now that we've stalled the submission. */
list_for_each_entry(ctx, _priv->contexts.list, link) {
struct intel_context *ce = >engine[RCS];
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7e7c355b0a7..60639624045b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -217,6 +217,8 @@ static void execlists_init_reg_state(u32 *reg_state,
 struct i915_gem_context *ctx,
 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29557/
State : success

== Summary ==

Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2185 pass:1212 dwarn:0   dfail:0   fail:17  skip:956 
time:9601s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5540/shards.html
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Re: [Intel-gfx] [PATCH i-g-t] lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Arkadiusz Hiler]

On Wed, Aug 30, 2017 at 04:56:09PM +0300, Paul Kocialkowski wrote:
> This removes the igt_require condition on the sysfs open call used to
> write the suspend/resume delay so that it is allowed to fail. Intsead,
> the code that depends on it is put in a conditional block.
> 
> This allows running test binaries as a non-privileged user for e.g.
> listing the available tests with the SuspendResumeDelay parameter set
> in igtrc configuration. Sysfs access would otherwise cause it to fail.
> 
> Signed-off-by: Paul Kocialkowski 
Reviewed-by: Arkadiusz Hiler 

and pushed

thanks for fixing it on a short notice!

-- 
Cheers,
Arek
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Pandiyan, Dhinakaran]

On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
> 

Ville abandoned this change last time stating - "Assume 1 pixel per
clock for the purposes of max pixel rate calculation until DDI clock
voltage scaling is handled"

If you can confirm that change was implemented, this patch is
Reviewed-by: Dhinakaran Pandiyan 


Also, I see that Ville's patch to change the pixel rate checks to use
cdclk has not been merged



> As Geminilake, Cannonlake also supports 2 pixels per clock.
> 
> Different from Geminilake we are not implementing the 99% Wa.
> But we can revisit that decision later if we find out
> any limitation on later CNL SKUs.
> 
> Cc: Ville Syrjälä 
> Cc: Dhinakaran Pandiyan 
> Cc: Jani Nikula 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++--
>  drivers/gpu/drm/i915/intel_pm.c|  3 ++-
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 1241e5891b29..6b1d805fb755 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1422,9 +1422,9 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  static int cnl_calc_cdclk(int max_pixclk)
>  {
> - if (max_pixclk > 336000)
> + if (max_pixclk > 2 * 336000)
>   return 528000;
> - else if (max_pixclk > 168000)
> + else if (max_pixclk > 2 * 168000)
>   return 336000;
>   else
>   return 168000;
> @@ -1752,9 +1752,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> intel_crtc_state *crtc_state,
>   crtc_state->has_audio &&
>   crtc_state->port_clock >= 54 &&
>   crtc_state->lane_count == 4) {
> - if (IS_CANNONLAKE(dev_priv))
> - pixel_rate = max(316800, pixel_rate);
> - else if (IS_GEMINILAKE(dev_priv))
> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
>   pixel_rate = max(2 * 316800, pixel_rate);
>   else
>   pixel_rate = max(432000, pixel_rate);
> @@ -1766,7 +1764,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct 
> intel_crtc_state *crtc_state,
>* two pixels per clock.
>*/
>   if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> - if (IS_GEMINILAKE(dev_priv))
> + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
>   pixel_rate = max(2 * 2 * 96000, pixel_rate);
>   else
>   pixel_rate = max(2 * 96000, pixel_rate);
> @@ -1999,6 +1997,8 @@ static int intel_compute_max_dotclk(struct 
> drm_i915_private *dev_priv)
>  {
>   int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
> + if (IS_CANNONLAKE(dev_priv))
> + return 2 * max_cdclk_freq;
>   if (IS_GEMINILAKE(dev_priv))
>   /*
>* FIXME: Limiting to 99% as a temporary workaround. See
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ed662937ec3c..42f753df30cb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3969,7 +3969,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
> *intel_crtc,
>   crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>   dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>  
> - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> + if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)) ||
> + IS_CANNONLAKE(to_i915(intel_crtc->base.dev)))
>   dotclk *= 2;
>  
>   pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip waking the device to service pwrite

[Patchwork]

== Series Details ==

Series: drm/i915: Skip waking the device to service pwrite
URL   : https://patchwork.freedesktop.org/series/29560/
State : success

== Summary ==

Series 29560v1 drm/i915: Skip waking the device to service pwrite
https://patchwork.freedesktop.org/api/1.0/series/29560/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:437s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:362s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:560s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:519s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:524s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:436s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:609s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:445s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:435s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:479s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:597s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:525s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:467s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:449s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:486s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:548s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:405s
fi-byt-n2820 failed to connect after reboot

14d5b307c691a24460b991756dc2d501f853e0b3 drm-tip: 2017y-08m-30d-17h-07m-37s UTC 
integration manifest
e24a0b1b6b51 drm/i915: Skip waking the device to service pwrite

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5541/
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[Intel-gfx] [PATCH v2] drm/i915: Add a default case in gen7 hwsp switch-case

[Michel Thierry]

Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not handled in switch warnings.

Use a default case instead, otherwise we will need to keep adding extra
cases if changes happen in the future.

v2: Since reaching the default case is impossible, use GEM_BUG_ON (Chris).

Cc: Chris Wilson 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c277a26bbd99..8af8871a8594 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -402,17 +402,18 @@ static void intel_ring_setup_status_page(struct 
intel_engine_cs *engine)
 */
if (IS_GEN7(dev_priv)) {
switch (engine->id) {
+   /*
+* No more rings exist on Gen7. Default case is only to shut up
+* gcc switch check warning.
+*/
+   default:
+   GEM_BUG_ON(engine->id);
case RCS:
mmio = RENDER_HWS_PGA_GEN7;
break;
case BCS:
mmio = BLT_HWS_PGA_GEN7;
break;
-   /*
-* VCS2 actually doesn't exist on Gen7. Only shut up
-* gcc switch check warning
-*/
-   case VCS2:
case VCS:
mmio = BSD_HWS_PGA_GEN7;
break;
-- 
2.14.1

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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Vivi, Rodrigo]

On Wed, 2017-08-30 at 14:38 +0300, Joonas Lahtinen wrote:
> On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> > Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > > > 
> > > > The current HW implementation of that BAR is to only
> > > > support <= DW (and maybe QW) writes—not 16/32/64B writes
> > > > that could occur with WC and/or SSE/AVX moves.
> > > > 
> > > > GTTMMADR must be marked uncacheable (UC).
> > > > Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
> > > > 
> > > > v2: Get clarification on the reasons and spec is getting
> > > > updated to reflect it now.
> > > > 
> > > > Cc: Joonas Lahtinen 
> > > > Suggested-by: Ben Widawsky 
> > > > Signed-off-by: Rodrigo Vivi 
> > > 
> > > Rodrigo, can you double-check how this interacts with the patch from
> > > Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.
> > 
> > Different issue (or should be). The ioremap concerns access through the
> > PCI BAR, affecting how fast we insert entries into the GGTT (so
> > establishing new mmaps following frequent runtime pm, loading of new
> > contexts + rings, as well as the stressful GGTT thrashing). PPAT affects
> > how the device accesses the physical pages, not the PTE themselves.
> 
> Yes, I know it should be :) But Rodrigo also described pretty random
> hangs, IIRC not much was pinpointing to either of the issues. With
> these two bugs present, device could be operating without write-back on
> certain pages, or could be operating on wrong pages altogether.
> 
> I'd just like one round of testing to try to avoid this change if we
> can.

I had tried already put PAT to non-cached, but I will double check Zhi's
work just in case.

I wish we could avoid this patch here, but it seems by definition this
BAR should be uncached. By BAR's non-Prefetchable attribute.

So probably the ioremap_wc should check that attribute and fail to
allocate that with wc so we would try wc and fallback to uncached.

But since we know this is uncached only for this case and this handle
don't exist yet the best is to move along with this patch.

> 
> Regards, Joonas

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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

[Belgaumkar, Vinay]

On 8/30/2017 4:12 AM, Michał Winiarski wrote:

On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote:

Added the missing IGT_TEST_DESCRIPTION and some subtest
descriptions.

Signed-off-by: Vinay Belgaumkar 
---
  tests/gem_flink_basic.c | 36 
  1 file changed, 36 insertions(+)

diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
index 26ae7d6..8761e0d 100644
--- a/tests/gem_flink_basic.c
+++ b/tests/gem_flink_basic.c
@@ -36,6 +36,8 @@
  #include 
  #include "drm.h"
  
+IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by name");

+
  static void
  test_flink(int fd)
  {
@@ -155,14 +157,48 @@ igt_main
igt_fixture
fd = drm_open_driver(DRIVER_INTEL);
  
+	/* basic:

+   This subtest creates a gem object, and then creates
+   a flink. It tests that we can gain access to the gem
+   object using the flink name.
+
+   Test fails if flink creation/open fails.
+   **/

Please use kernel coding style.
This is not the format we're using for multiline comments.

/*
  *
  */
^^^ This is the format we're using.


Agreed. Will change it to match that style. The multi-line comments in 
/lib directory actually use this-

/**
 * 
 */



And on the documentation itself, let's take a quote from the kernel coding
style:
"Comments are good, but there is also a danger of over-commenting.  NEVER
try to explain HOW your code works in a comment: it's much better to
write the code so that the **working** is obvious, and it's a waste of
time to explain badly written code."

Now, let's try to match the tests with the comments:
/* This subtest creates a gem object */
ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, );
igt_assert_eq(ret, 0);

/* and then creates a flink */
flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

/* It tests that we can gain access to the gem object using the flink
 * name
 */
Well... not really, we're not accessing the object in any way.


Yes, but we are trying to open the flink in this line of the test-
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);

I will change it to "open the flink" instead of "access the gem object".



/* Test fails if flink creation/open fails. */
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);


igt_subtest("basic")
test_flink(fd);
+
+   /* double-flink:
+   This test checks if it is possible to create 2 flinks
+   for the same gem object.
+
+   Test fails if 2 flink objects cannot be created.
+   **/

/* This test checks if it is possible to create 2 flinks for the same
 * gem object
 */

flink.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

flink2.handle = create.handle;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);

/* Test fails if 2 flink objects cannot be created. */
Well - this is handled by the asserts above.
You ignored this assumption in your description for some reason though:
igt_assert(flink2.name == flink.name);


Agreed. Also need to add that comment saying the name remains the same 
across the two

applications opening the same gem object.




igt_subtest("double-flink")
test_double_flink(fd);
+
+   /* bad-flink:
+   Use an invalid flink handle.
+
+   DRM_IOCTL_GEM_FLINK ioctl call should return failure.
+   **/

ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert(ret == -1 && errno == ENOENT);

There is also an igt_info message:
igt_info("Testing error return on bad flink ioctl.\n");


True, there is some duplication in the comments at this point.

The documentation that I am adding before the subtest call will be 
rolled up by gtkdoc/Sphinx/doxygen, it likely
will not look at the text documentation in the actual code. When we look 
at the rolled up documentation, it
is good to have an idea of when a particular test will pass/fail without 
having to dig into code.


So, yes, there will be some duplication for existing tests. But if we 
start following this method for new tests,
we can have one place to describe what the test does/when does it fail, 
and then expand on anything that is

not very clear in the code itself.





igt_subtest("bad-flink")
test_bad_flink(fd);
+
+   /* bad-open:
+   Try to use an invalid flink name.
+
+   DRM_IOCTL_GEM_FLINK ioctl call should return failure.
+   **/

open_struct.name = 0x10101010;
ret = ioctl(fd, 

[Intel-gfx] [PATCH] drm/i915: Skip waking the device to service pwrite

[Chris Wilson]

If the device is in runtime suspend, resuming takes time and reduces our
powersaving. If this was for a small write into an object, that resume
will take longer than any savings in using the indirect GGTT access to
avoid the cpu cache.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 93dfa793975a..8940a6873ca5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1229,7 +1229,21 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
if (ret)
return ret;
 
-   intel_runtime_pm_get(i915);
+   if (i915_gem_object_has_struct_page(obj)) {
+   /* Avoid waking the device up if we can fallback, as
+* waking/resuming is very slow (10-100 ms depending
+* on PCI sleeps and our own resume time). This easily
+* dwarfs any performance advantage from using the
+* cache bypass of indirect GGTT access.
+*/
+   if (!intel_runtime_pm_get_if_in_use(i915)) {
+   ret = -EFAULT;
+   goto out_unlock;
+   }
+   } else {
+   intel_runtime_pm_get(i915);
+   }
+
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
   PIN_MAPPABLE | PIN_NONBLOCK);
if (!IS_ERR(vma)) {
@@ -1244,7 +1258,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
if (IS_ERR(vma)) {
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
-   goto out_unlock;
+   goto out_rpm;
GEM_BUG_ON(!node.allocated);
}
 
@@ -1307,8 +1321,9 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
} else {
i915_vma_unpin(vma);
}
-out_unlock:
+out_rpm:
intel_runtime_pm_put(i915);
+out_unlock:
mutex_unlock(>drm.struct_mutex);
return ret;
 }
-- 
2.14.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/tests: Add audio selftest

[Patchwork]

== Series Details ==

Series: lib/tests: Add audio selftest
URL   : https://patchwork.freedesktop.org/series/29550/
State : failure

== Summary ==

Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)

fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2265 pass:1230 dwarn:0   dfail:0   fail:19  skip:1016 
time:9604s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_127/shards.html
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Re: [Intel-gfx] [RFC v2 2/3] drm/i915/pmu: serve global events and support perf stat

[Rogozhkin, Dmitry V]

On Tue, 2017-08-29 at 11:28 +0200, Peter Zijlstra wrote:
> On Wed, Aug 23, 2017 at 11:38:43PM +, Rogozhkin, Dmitry V wrote:
> > On Wed, 2017-08-23 at 08:26 -0700, Dmitry Rogozhkin wrote:
> > > +static cpumask_t i915_pmu_cpumask = CPU_MASK_CPU0;
> > 
> > Peter, this hardcoding of cpumask to use CPU0 works, but should I
> > implement something smarter or this will be sufficient? I see that
> > cstate.c you have pointed me to tries to track CPUs going online/offline
> > and migrates PMU context to another CPU if selected one went offline.
> > Should I follow this way?
> 
> Yes.. x86 used to not allow hotplug of CPU0, but they 'fixed' that :/
> 
> And the perf core needs _a_ valid CPU to run things from, which leaves
> you having to track online/offline things.
> 
> Now, I suppose its all fairly similar for a lot of uncore PMUs, so maybe
> you can pull some of this into a library and avoid the endless
> duplication between all (most?) uncore driveres.
> 
> > If I should track CPUs going online/offline, then I have questions:
> > 1. How I should register tracking callbacks? I see that cstate.c
> > registers CPUHP_AP_PERF_X86_CSTATE_STARTING and
> > CPUHP_AP_PERF_X86_CSTATE_ONLINE, uncore.c registers
> > CPUHP_AP_PERF_X86_UNCORE_ONLINE. What I should use? I incline to UNCORE.
> 
> Egads, what a mess :/ Clearly I didn't pay too much attention there.
> 
> So ideally we'd not hate a state per PMU, and
> __cpuhp_setup_state_cpuslocked() has a .multi_instance argument that
> allows reuse of a state.
> 
> So yes, please use the PERF_X86_UNCORE ones if possible.
> 
> > 2. If I will register for, say UNCORE, then how double registrations
> > will be handled if both uncore.c and i915.c will register callbacks? Any
> > conflict here?
> 
> Should work with .multi_instance I _think_, I've not had the pleasure of
> using the new and improved CPU hotplug infrastructure much.
> 
> > 3. What I should pass as 2nd argument? Will "perf/x86/intel/i915:online"
> > be ok?
> 
> Yeah, whatever I think.. something unique. Someone or something will
> eventually yell if its no good I suppose ;-)


I figured out how to track cpus online/offline status in PMU. Here is a
question however. What is the reason for uncore PMUs (cstate.c for
example) to register for cpus other than cpu0? I see it registers for
first thread of each cpu, on my 8 logical-core systems it registers for
cpu0-3 it seems. If they register for few cpus then perf-stat will
aggregate counters which can be disabled with '-A, --no-aggr' option.
Ok... but they could register for just cpu0. Besides, it looks like on
Linux cpu0 can't go offline at all at least of x86 architecture. Peter,
could you, please, clarify the reasoning to register designated readers
of uncore PMU for few CPUs?

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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Redo old gmch irq handling (rev2)

[Ville Syrjälä]

On Mon, Aug 21, 2017 at 03:15:39PM +0300, Tomi Sarvela wrote:
> On 21/08/17 15:09, Ville Syrjälä wrote:
> > On Fri, Aug 18, 2017 at 09:19:23PM +0100, Chris Wilson wrote:
> >> Quoting Patchwork (2017-08-18 20:41:45)
> >>> == Series Details ==
> >>>
> >>> Series: drm/i915: Redo old gmch irq handling (rev2)
> >>> URL   : https://patchwork.freedesktop.org/series/26215/
> >>> State : success
> >>>
> >>> == Summary ==
> >>>
> >>> Series 26215v2 drm/i915: Redo old gmch irq handling
> >>> https://patchwork.freedesktop.org/api/1.0/series/26215/revisions/2/mbox/
> >>>
> >>> Test gem_exec_flush:
> >>>  Subgroup basic-batch-kernel-default-uc:
> >>>  fail   -> PASS   (fi-snb-2600) fdo#17
> >>> Test kms_flip:
> >>>  Subgroup basic-flip-vs-modeset:
> >>>  skip   -> PASS   (fi-skl-x1585l) fdo#101781
> >>>
> >>> fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
> >>> fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
> >>>
> >>> fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   
> >>> skip:54  time:365s
> >>> fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   
> >>> skip:50  time:419s
> >>> fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   
> >>> skip:55  time:527s
> >>
> >> That's a reasonably intensive workout of the interrupt handler. Ironlake
> >> in particular is pretty bad at seqno coherency. Would like to have had
> >> the gdg and elk/ctg results, what happened to those?
> > 
> > That's a good question. bwr seems to be missing as well. Tomi?
> 
> For hang reasons, BWR and ELK haven't been part of the Patchwork runs. 
> Added tag to both of them now when the issue is fixed.
> 
> CTG is a laptop, and occasionally stops answering to AC boot. Causes 
> noise, so this hasn't been participating Trybot/Patchwork runs.
> 
> GDG is usually (=always) hanging to igt@drv_hangman@error-state-basic 
> which is one of the first tests run. There hasn't been a reason to keep 
> it in Patchwork/Trybot.
> 
> I can re-run the tests through Patchwork if you want, and you'll get 
> results to at least BWR and ELK.

Please do. More results on affected machines wouldn't hurt.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 00/12] drm/i915: Fix up the CCS code

[Ville Syrjälä]

On Wed, Aug 30, 2017 at 11:31:16AM +0300, Jani Nikula wrote:
> On Mon, 28 Aug 2017, Ville Syrjälä  wrote:
> > On Mon, Aug 28, 2017 at 02:35:54PM +0100, Daniel Stone wrote:
> >> Hi Daniel,
> >> 
> >> On 25 August 2017 at 18:17, Daniel Vetter  wrote:
> >> > Which of these do we need to cherry-pick over to -next-fixes? There's no
> >> > annotations about that. If the answer is "most" I'm leaning towards
> >> > disabling CCS for 4.14, minimal set would be ideal (and first in the 
> >> > patch
> >> > series).
> >> 
> >> My opinion below; tl;dr is that I don't think most of them are
> >> super-critical. Ville obviously has a far stronger opinion than me on
> >> the shape of the code, so I'm fine with this series, which seems to
> >> mostly be a merge back of the delta between whatever Ville's latest
> >> branch was, and whatever the last patchset Ben sent out was.
> >> 
> >> >> Ville Syrjälä (12):
> >> >>   drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear
> >> >> offset
> >> 
> >> This should land into -fixes. I trust Ville that it has no UABI
> >> impact, but seems like something to be very consistent on.
> >
> > It does change the uabi. That's the whole point. What was merged doesn't
> > agree with what userspace wants. So this we want in definitely so that
> > we don't end up exposing the wrong uabi in any released kernel.
> >
> >> 
> >> >>   drm/i915: Skip fence alignemnt check for the CCS plane
> >> 
> >> Not sure if this is -fixes material really, just a cleanup?
> >
> > It makes the kernel less likely to reject the fb entirely. So
> > without this userspace has to be rather careful where it places
> > the aux surface. I would include this as well.
> >
> >> 
> >> >>   drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for
> >> >> CCS
> >> 
> >> Not -fixes, performance optimisation.
> >
> > We hope. It does change the layout of the compressed data though so if
> > our testcases try to generate compressed data with the CPU it'll not go
> > well if the test assumes the wrong hash mode. I would include this as
> > well so that we don't end up in any kind of a mess later when we try to
> > change it.
> >
> > So the patches were more or less sorted in priority order, and we want
> > at least 01,02 and maybe 03.
> 
> When you decide what to apply, please *please* add the appropriate
> Fixes: tags for the ones you want to show up in v4.14.

I just pushed 01 and 02 to dinq with the approriage Fixes: tags.
I'd still prefer to get 03 in as well, but that would need an
r-b/ack.

> 
> BR,
> Jani.
> 
> 
> >
> >> 
> >> >>   drm/i915: Add a comment exlaining CCS hsub/vsub
> >> 
> >> Seems harmless to land to -fixes.
> >> 
> >> >>   drm/i915: Nuke a pointless unreachable()
> >> 
> >> Ditto.
> >> 
> >> >>   drm/i915: Add the missing Y/Yf modifiers for SKL+ sprites
> >> 
> >> Per my previous reply, NAK to landing at all, since DDB/WM allocation
> >> seems too broken for it to work.
> >> 
> >> >>   drm/i915: Clean up the sprite modifier checks
> >> 
> >> Fine with this, but doesn't seem like -fixes material.
> >> 
> >> >>   drm/i915: Add CCS capability for sprites
> >> 
> >> NAK, same reason as Y/Yf.
> >> 
> >> >>   drm/i915: Allow up to 32KB stride on SKL+ "sprites"
> >> 
> >> Again doesn't seem like -fixes necessarily?
> >> 
> >> >>   drm: Fix modifiers_property kernel doc
> >> 
> >> Good for -fixes.
> >> 
> >> >>   drm: Check that the plane supports the request format+modifier combo
> >> 
> >> Good for core (not Intel) -fixes.
> >> 
> >> >>   drm/i915: Remove the pipe/plane ID checks from
> >> >> skl_check_ccs_aux_surface()
> >> 
> >> Seems fine but probably not -fixes material; land in Intel after a merge?
> >> 
> >> Cheers,
> >> Daniel
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
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Intel OTC
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[Intel-gfx] ✓ Fi.CI.IGT: success for lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Patchwork]

== Series Details ==

Series: lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay
URL   : https://patchwork.freedesktop.org/series/29549/
State : success

== Summary ==

Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453

shard-hswtotal:2265 pass:1231 dwarn:0   dfail:0   fail:18  skip:1016 
time:9676s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_126/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29557/
State : success

== Summary ==

Series 29557v1 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29557/revisions/1/mbox/

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:462s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:358s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:552s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:253s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:520s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:439s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:611s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:450s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:426s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:599s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:598s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:524s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:489s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:444s
fi-skl-x1585ltotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:548s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:404s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
12ba957a6601 drm/i915/perf: add support for Coffeelake GT2
59a09d151126 drm/i915: rework IS_*_GT* macros
d49b0dd08fef drm/i915: mark all device info struct with __initdata
4506125731ce drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5540/
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[Intel-gfx] [PATCH v5 4/4] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void

[Intel-gfx] [PATCH v5 0/4] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Hi,

Adding one commit to mark device info structs with __initdata.

Cheers,

Lionel Landwerlin (4):
  drm/i915: add GT number to intel_device_info
  drm/i915: mark all device info struct with __initdata
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +
 drivers/gpu/drm/i915/i915_pci.c   | 241 --
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 152 +
 7 files changed, 431 insertions(+), 135 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] [PATCH v5 3/4] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v5 2/4] drm/i915: mark all device info struct with __initdata

[Lionel Landwerlin]

As recommended by Chris.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_pci.c | 94 -
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f56aa8e3890b..2aeaf4855feb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -66,19 +66,19 @@
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i830_info = {
+static const struct intel_device_info intel_i830_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I830,
.is_mobile = 1, .cursor_needs_physical = 1,
.num_pipes = 2, /* legal, last one wins */
 };
 
-static const struct intel_device_info intel_i845g_info = {
+static const struct intel_device_info intel_i845g_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I845G,
 };
 
-static const struct intel_device_info intel_i85x_info = {
+static const struct intel_device_info intel_i85x_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I85X, .is_mobile = 1,
.num_pipes = 2, /* legal, last one wins */
@@ -86,7 +86,7 @@ static const struct intel_device_info intel_i85x_info = {
.has_fbc = 1,
 };
 
-static const struct intel_device_info intel_i865g_info = {
+static const struct intel_device_info intel_i865g_info __initdata = {
GEN2_FEATURES,
.platform = INTEL_I865G,
 };
@@ -98,7 +98,7 @@ static const struct intel_device_info intel_i865g_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i915g_info = {
+static const struct intel_device_info intel_i915g_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I915G, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -106,7 +106,7 @@ static const struct intel_device_info intel_i915g_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i915gm_info = {
+static const struct intel_device_info intel_i915gm_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I915GM,
.is_mobile = 1,
@@ -118,7 +118,7 @@ static const struct intel_device_info intel_i915gm_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i945g_info = {
+static const struct intel_device_info intel_i945g_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I945G,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -127,7 +127,7 @@ static const struct intel_device_info intel_i945g_info = {
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_i945gm_info = {
+static const struct intel_device_info intel_i945gm_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_I945GM, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
@@ -138,14 +138,14 @@ static const struct intel_device_info intel_i945gm_info = 
{
.unfenced_needs_alignment = 1,
 };
 
-static const struct intel_device_info intel_g33_info = {
+static const struct intel_device_info intel_g33_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_G33,
.has_hotplug = 1,
.has_overlay = 1,
 };
 
-static const struct intel_device_info intel_pineview_info = {
+static const struct intel_device_info intel_pineview_info __initdata = {
GEN3_FEATURES,
.platform = INTEL_PINEVIEW, .is_mobile = 1,
.has_hotplug = 1,
@@ -160,14 +160,14 @@ static const struct intel_device_info intel_pineview_info 
= {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_i965g_info = {
+static const struct intel_device_info intel_i965g_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_I965G,
.has_overlay = 1,
.hws_needs_physical = 1,
 };
 
-static const struct intel_device_info intel_i965gm_info = {
+static const struct intel_device_info intel_i965gm_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_I965GM,
.is_mobile = 1, .has_fbc = 1,
@@ -176,14 +176,14 @@ static const struct intel_device_info intel_i965gm_info = 
{
.hws_needs_physical = 1,
 };
 
-static const struct intel_device_info intel_g45_info = {
+static const struct intel_device_info intel_g45_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_G45,
.has_pipe_cxsr = 1,
.ring_mask = RENDER_RING | BSD_RING,
 };
 
-static const struct intel_device_info intel_gm45_info = {
+static const struct intel_device_info intel_gm45_info __initdata = {
GEN4_FEATURES,
.platform = INTEL_GM45,
.is_mobile = 1, .has_fbc = 1,
@@ -200,12 +200,12 @@ static const struct intel_device_info intel_gm45_info = {
GEN_DEFAULT_PIPEOFFSETS, \

[Intel-gfx] [PATCH v5 1/4] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

Before & After :

$ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l
209

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 152 +++
 3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..f56aa8e3890b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define IVB_M_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
  

Re: [Intel-gfx] [PATCH i-g-t] lib/tests: Add audio selftest

[Chris Wilson]

Quoting Paul Kocialkowski (2017-08-30 15:45:14)
> This introduces a selftest for the audio library.
> 
> It consists of generating a signal from a list of frequencies and
> ensuring that the integrity checking function does detect these
> frequencies (and only these frequencies).
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/tests/Makefile.am  |  2 +-
>  lib/tests/Makefile.sources |  5 
>  lib/tests/igt_audio.c  | 57 
> ++
>  3 files changed, 63 insertions(+), 1 deletion(-)
>  create mode 100644 lib/tests/igt_audio.c
> 
> diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
> index 5d14194a..b1caa628 100644
> --- a/lib/tests/Makefile.am
> +++ b/lib/tests/Makefile.am
> @@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
> -DIGT_DATADIR=\""$(abs_srcdir)"\" \
> $(NULL)
>  
> -LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
> $(TIMER_LIBS)
> +LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(GSL_CFLAGS) 
> $(LIBUNWIND_LIBS) $(TIMER_LIBS)

Let's play spot the odd one out.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29547/
State : warning

== Summary ==

Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_mmio_vs_cs_flip:
Subgroup setcrtc_vs_cs_flip:
pass   -> SKIP   (shard-hsw)
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
pass   -> SKIP   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2230 pass:1228 dwarn:0   dfail:0   fail:18  skip:984 
time:9635s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5539/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Chris Wilson]

Quoting Daniel Vetter (2017-08-30 14:59:32)
> On Wed, Aug 30, 2017 at 01:56:40PM +0100, Chris Wilson wrote:
> > Quoting Daniel Vetter (2017-08-30 13:23:56)
> > > Or just the need to add a pile more tests to pm_rpm?
> > 
> > No. It's just your regular combinatorial explosion. The approach I would
> > take here would be to register a sysenter callback that attempted to do a
> > rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> > via the faultinjection framework) and then run the minimal test set that
> > exercises all ioctl paths, and then expand to all driver branches.
> > 
> > First we need coverage feedback.
> 
> What I meant to imply: As long as any display is on we will never rpm
> suspend. Mostly this is the case for CI machines.
> 
> The new testcases I've had in mind would explicitly dpms off the display
> before running a set of gem testcases. We don't want to do that everywhere
> though, because a dpms on/off is very costly.

If no userspace is using the display and we remove fbcon, shouldn't the
kernel be disabling the outputs anyway? There's literally nothing there
to provide display continuity.
-Chris
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: add GT number to intel_device_info

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 21:42:02)
> Up to Coffeelake we could deduce this GT number from the device ID.
> This doesn't seem to be the case anymore. This change reorders pciids
> per GT and adds a gt field to intel_device_info. We set this field on
> the following platforms :
> 
>- SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL
> 
> v2: Add SNB & IVB (Chris)
> 
> v3: Fix compilation error in early-quirks (Lionel)
> 
> Signed-off-by: Lionel Landwerlin 

The pci ids and tables motions looks ok, so
Reviewed-by: Chris Wilson 
on that part.

Can you do a
/sbin/modinfo drivers/gpu/drm/i915/i915.ko  | grep ^alias: | wc -l
before/after just to make sure.

Bonus points for marking up all the structs with __initdata
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/tests: Add audio selftest

[Patchwork]

== Series Details ==

Series: lib/tests: Add audio selftest
URL   : https://patchwork.freedesktop.org/series/29550/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:362s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:567s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:534s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:529s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:513s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:439s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:616s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:448s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:429s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:428s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:497s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:477s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:599s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:603s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:528s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:472s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:452s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:544s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:410s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_127/
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Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: rework IS_*_GT* macros

[Chris Wilson]

Quoting Lionel Landwerlin (2017-08-29 21:42:03)
> We can now make use of the intel_device_info.gt field.
> 
> Signed-off-by: Lionel Landwerlin 
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: warning for pm_rps: Changes in waitboost scenario (rev9)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev9)
URL   : https://patchwork.freedesktop.org/series/28966/
State : warning

== Summary ==

Test pm_rps:
Subgroup reset:
fail   -> PASS   (shard-hsw) fdo#102250 +1
Test kms_plane_multiple:
Subgroup legacy-pipe-E-tiling-y:
incomplete -> SKIP   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw) fdo#102249
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-C-planes:
skip   -> PASS   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-B-planes:
pass   -> SKIP   (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_plane_lowres:
Subgroup pipe-A-tiling-none:
pass   -> SKIP   (shard-hsw)
Test kms_fbc_crc:
Subgroup page_flip_and_mmap_cpu:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
skip   -> PASS   (shard-hsw)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (shard-hsw) fdo#102453

fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102453 https://bugs.freedesktop.org/show_bug.cgi?id=102453

shard-hswtotal:2265 pass:1227 dwarn:1   dfail:0   fail:17  skip:1020 
time:9512s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_125/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Patchwork]

== Series Details ==

Series: lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay
URL   : https://patchwork.freedesktop.org/series/29549/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:565s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:527s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:524s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:519s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:438s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:617s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:447s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:482s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:595s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:532s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:482s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:543s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:448s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:407s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_126/
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[Intel-gfx] [PATCH i-g-t] lib/tests: Add audio selftest

[Paul Kocialkowski]

This introduces a selftest for the audio library.

It consists of generating a signal from a list of frequencies and
ensuring that the integrity checking function does detect these
frequencies (and only these frequencies).

Signed-off-by: Paul Kocialkowski 
---
 lib/tests/Makefile.am  |  2 +-
 lib/tests/Makefile.sources |  5 
 lib/tests/igt_audio.c  | 57 ++
 3 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 lib/tests/igt_audio.c

diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
index 5d14194a..b1caa628 100644
--- a/lib/tests/Makefile.am
+++ b/lib/tests/Makefile.am
@@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
-DIGT_DATADIR=\""$(abs_srcdir)"\" \
$(NULL)
 
-LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
$(TIMER_LIBS)
+LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(GSL_CFLAGS) 
$(LIBUNWIND_LIBS) $(TIMER_LIBS)
 
 LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) -lm
 AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
diff --git a/lib/tests/Makefile.sources b/lib/tests/Makefile.sources
index 8d1a8dea..eb702844 100644
--- a/lib/tests/Makefile.sources
+++ b/lib/tests/Makefile.sources
@@ -18,6 +18,11 @@ check_prog_list = \
igt_can_fail_simple \
$(NULL)
 
+#if HAVE_GSL
+check_prog_list += \
+   igt_audio
+#endif
+
 TESTS = \
$(check_prog_list) \
$(check_script_list) \
diff --git a/lib/tests/igt_audio.c b/lib/tests/igt_audio.c
new file mode 100644
index ..2354d5a0
--- /dev/null
+++ b/lib/tests/igt_audio.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt_core.h"
+#include "igt_audio.h"
+
+static int test_frequencies[] = {
+   300,
+   600,
+   1200,
+   8,
+   1,
+};
+
+static int test_frequencies_count = sizeof(test_frequencies) / sizeof(int);
+
+igt_simple_main
+{
+   short buffer[2 * 1024];
+   struct audio_signal *signal;
+   int i;
+
+   signal = audio_signal_init(2, 44800);
+   igt_assert(signal);
+
+   for (i = 0; i < test_frequencies_count; i++)
+   audio_signal_add_frequency(signal, test_frequencies[i]);
+
+   audio_signal_synthesize(signal);
+   audio_signal_fill(signal, buffer, 1024);
+
+   igt_assert(audio_signal_detect(signal, 2, 44800, buffer, 1024));
+
+   audio_signal_clean(signal);
+   free(signal);
+}
-- 
2.14.0

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Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Laurent Pinchart]

On Wednesday, 30 August 2017 17:17:36 EEST Daniel Vetter wrote:
> On Wed, Aug 30, 2017 at 05:10:43PM +0300, Laurent Pinchart wrote:
> > Hi Maarten,
> > 
> > Thank you for the patch.
> > 
> > On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> > > Currently we neatly track the crtc state, but forget to look at
> > > plane/connector state.
> > > 
> > > When doing a nonblocking modeset, immediately followed by a setprop
> > > before the modeset completes, the setprop will see the modesets new
> > > state as the old state and free it.
> > > 
> > > This has to be solved by waiting for hw_done on the connector, even
> > > if it's not assigned to a crtc. When a connector is unbound we take
> > > the last crtc commit, and when it stays unbound we create a new
> > > fake crtc commit for that gets signaled on hw_done for all the
> > > planes/connectors.
> > > 
> > > We wait for it the same way as we do for crtc's, which will make
> > > sure we never run into a use-after-free situation.
> > > 
> > > Changes since v1:
> > > - Only create a single disable commit. (danvet)
> > > - Fix leak in intel_legacy_cursor_update.
> > > 
> > > Signed-off-by: Maarten Lankhorst 
> > > Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> > > Cc: Laurent Pinchart 
> > > ---
> > > 
> > >  drivers/gpu/drm/drm_atomic.c |   4 +
> > >  drivers/gpu/drm/drm_atomic_helper.c  | 156
> > >  ++--
> > >  drivers/gpu/drm/i915/intel_display.c |   2 +
> > >  include/drm/drm_atomic.h |  12 +++
> > >  include/drm/drm_connector.h  |   7 ++
> > >  include/drm/drm_plane.h  |   7 ++
> > >  6 files changed, 182 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > > index 2cce48f203e0..75f5f74de9bf 100644
> > > --- a/drivers/gpu/drm/drm_atomic.c
> > > +++ b/drivers/gpu/drm/drm_atomic.c
> > > @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> > > drm_atomic_state *state) }
> > > 
> > >   state->num_private_objs = 0;
> > > 
> > > + if (state->fake_commit) {
> > > + drm_crtc_commit_put(state->fake_commit);
> > > + state->fake_commit = NULL;
> > > + }
> > > 
> > >  }
> > >  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> > > 
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> > > 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> > > *completion) drm_crtc_commit_put(commit);
> > > 
> > >  }
> > > 
> > > +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> > > *crtc)
> > > +{
> > 
> > You could allocate the commit in this function too, the kzalloc() is
> > currently duplicated. The function should probably be called
> > alloc_commit() then.> 
> > > + init_completion(>flip_done);
> > > + init_completion(>hw_done);
> > > + init_completion(>cleanup_done);
> > > + INIT_LIST_HEAD(>commit_entry);
> > > + kref_init(>ref);
> > > + commit->crtc = crtc;
> > > +}
> > > +
> > > +static struct drm_crtc_commit *
> > > +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc
> > > *crtc)
> > > +{
> > > + struct drm_crtc_commit *commit;
> > > +
> > > + if (crtc) {
> > > + struct drm_crtc_state *new_crtc_state;
> > > +
> > > + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > > +
> > > + commit = new_crtc_state->commit;
> > > + } else if (!state->fake_commit) {
> > > + state->fake_commit = commit = kzalloc(sizeof(*commit), 
GFP_KERNEL);
> > > + if (!commit)
> > > + return NULL;
> > > +
> > > + init_commit(commit, NULL);
> > > + } else
> > > + commit = state->fake_commit;
> > > +
> > > + drm_crtc_commit_get(commit);
> > 
> > I believe the reference counting is right. The double reference in the
> > second case (kref_init() when initializing the commit and
> > drm_crtc_commit_get()) should not cause a leak. The kref_init() takes a
> > reference to store the commit in state->fake_commit, released in
> > drm_atomic_state_default_clear(), and the drm_crtc_commit_get() takes a
> > reference returned by the function, stored in new_*_state->commit by the
> > caller.
> > 
> > This being said, I think the reference counting is confusing, as proved by
> > Daniel thinking there was a leak here (or by me thinking there's no leak
> > while there's one :-)). To make the implementation clearer, I propose
> > turning the definition of drm_crtc_commit_get() to
> > 
> > static inline struct drm_crtc_commit *
> > drm_crtc_commit_get(struct drm_crtc_commit *commit)
> > {
> > 
> > kref_get(>ref);
> > return commit;
> > 
> > }
> > 
> > and writing this function as
> > 
> > /* Return a new 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake

[Patchwork]

== Series Details ==

Series: drm/i915: add perf support for Coffeelake
URL   : https://patchwork.freedesktop.org/series/29547/
State : success

== Summary ==

Series 29547v1 drm/i915: add perf support for Coffeelake
https://patchwork.freedesktop.org/api/1.0/series/29547/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:443s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:359s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:550s
fi-bwr-2160  total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  
time:251s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:521s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:515s
fi-elk-e7500 total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  
time:435s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:610s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:446s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:424s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:596s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:597s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:521s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:484s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:445s
fi-skl-x1585ltotal:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:483s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:405s
fi-skl-6700k failed to connect after reboot

6a305b78140aedc9008bdb7e78e70417a8413bbf drm-tip: 2017y-08m-30d-08h-12m-34s UTC 
integration manifest
fe9806b8b6e4 drm/i915/perf: add support for Coffeelake GT2
53483bc14c61 drm/i915: rework IS_*_GT* macros
72dd9b082ec1 drm/i915: add GT number to intel_device_info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5539/
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:30PM -0700, Rodrigo Vivi wrote:
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 35 +++
>  1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f1757a8e481a..97ff082c28a7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static int cnl_max_level(struct drm_i915_private *dev_priv,
> +  enum intel_output_type type)
> +{
> + int n_entries = 0;
> +
> + switch (type) {
> + case INTEL_OUTPUT_DP:

These encoder->type checks are a bit problematic due to the DDI encoder
type changing dynamically. But to fix that I thunk I'll just need to
resurrect my old patches to get rid of that type changing. But I'll
wait until you cand land these since I need to rebase my stuff anyway.

> + cnl_get_buf_trans_dp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_EDP:
> + cnl_get_buf_trans_edp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_HDMI:
> + cnl_get_buf_trans_hdmi(dev_priv, _entries);
> + break;
> + default:
> + MISSING_CASE(type);
> + return 0;
> + }
> +
> + return n_entries - 1;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1879,10 +1902,14 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   int n_entries;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_max_level(dev_priv, encoder->type);
> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + }
>  
>   if (WARN_ON(n_entries < 1))
>   n_entries = 1;
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/cnl: Move ddi buf trans related functions up.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:28PM -0700, Rodrigo Vivi wrote:
> No functional changes. But those functions will be needed
> to get max level for HDMI and DP, so let's move those
> up closer to other similar functions existent for previous
> platforms.
> 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 122 
> +++
>  1 file changed, 61 insertions(+), 61 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7b547a7f6c2b..3ce02cbd4483 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_private 
> *dev_priv, int *n_entries)
>   }
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> + return cnl_ddi_translations_hdmi_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> + return cnl_ddi_translations_hdmi_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> + return cnl_ddi_translations_hdmi_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> + return cnl_ddi_translations_dp_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
> + return cnl_ddi_translations_dp_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
> + return cnl_ddi_translations_dp_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +{
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + if (dev_priv->vbt.edp.low_vswing) {
> + if (voltage == VOLTAGE_INFO_0_85V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> + return cnl_ddi_translations_edp_0_85V;
> + } else if (voltage == VOLTAGE_INFO_0_95V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
> + return cnl_ddi_translations_edp_0_95V;
> + } else if (voltage == VOLTAGE_INFO_1_05V) {
> + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
> + return cnl_ddi_translations_edp_1_05V;
> + } else
> + MISSING_CASE(voltage);
> + return NULL;
> + } else {
> + return cnl_get_buf_trans_dp(dev_priv, n_entries);
> + }
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1829,67 +1890,6 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> -static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> -{
> - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> - if (voltage == VOLTAGE_INFO_0_85V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> - return cnl_ddi_translations_hdmi_0_85V;
> - } else if (voltage == VOLTAGE_INFO_0_95V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> - return cnl_ddi_translations_hdmi_0_95V;
> - } else if (voltage == VOLTAGE_INFO_1_05V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> - return cnl_ddi_translations_hdmi_1_05V;
> - } else
> - MISSING_CASE(voltage);
> - return NULL;
> -}
> -
> -static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> -{
> - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> - if (voltage == VOLTAGE_INFO_0_85V) {
> - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> - return cnl_ddi_translations_dp_0_85V;
> - } 

Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Daniel Vetter]

On Wed, Aug 30, 2017 at 05:10:43PM +0300, Laurent Pinchart wrote:
> Hi Maarten,
> 
> Thank you for the patch.
> 
> On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> > Currently we neatly track the crtc state, but forget to look at
> > plane/connector state.
> > 
> > When doing a nonblocking modeset, immediately followed by a setprop
> > before the modeset completes, the setprop will see the modesets new
> > state as the old state and free it.
> > 
> > This has to be solved by waiting for hw_done on the connector, even
> > if it's not assigned to a crtc. When a connector is unbound we take
> > the last crtc commit, and when it stays unbound we create a new
> > fake crtc commit for that gets signaled on hw_done for all the
> > planes/connectors.
> > 
> > We wait for it the same way as we do for crtc's, which will make
> > sure we never run into a use-after-free situation.
> > 
> > Changes since v1:
> > - Only create a single disable commit. (danvet)
> > - Fix leak in intel_legacy_cursor_update.
> > 
> > Signed-off-by: Maarten Lankhorst 
> > Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> > Cc: Laurent Pinchart 
> > ---
> >  drivers/gpu/drm/drm_atomic.c |   4 +
> >  drivers/gpu/drm/drm_atomic_helper.c  | 156 ++--
> >  drivers/gpu/drm/i915/intel_display.c |   2 +
> >  include/drm/drm_atomic.h |  12 +++
> >  include/drm/drm_connector.h  |   7 ++
> >  include/drm/drm_plane.h  |   7 ++
> >  6 files changed, 182 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 2cce48f203e0..75f5f74de9bf 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> > drm_atomic_state *state) }
> > state->num_private_objs = 0;
> > 
> > +   if (state->fake_commit) {
> > +   drm_crtc_commit_put(state->fake_commit);
> > +   state->fake_commit = NULL;
> > +   }
> >  }
> >  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> > 
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> > 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> > *completion) drm_crtc_commit_put(commit);
> >  }
> > 
> > +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> > *crtc)
> > +{
> 
> You could allocate the commit in this function too, the kzalloc() is 
> currently 
> duplicated. The function should probably be called alloc_commit() then.
> 
> > +   init_completion(>flip_done);
> > +   init_completion(>hw_done);
> > +   init_completion(>cleanup_done);
> > +   INIT_LIST_HEAD(>commit_entry);
> > +   kref_init(>ref);
> > +   commit->crtc = crtc;
> > +}
> > +
> > +static struct drm_crtc_commit *
> > +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> > +{
> > +   struct drm_crtc_commit *commit;
> > +
> > +   if (crtc) {
> > +   struct drm_crtc_state *new_crtc_state;
> > +
> > +   new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > +
> > +   commit = new_crtc_state->commit;
> > +   } else if (!state->fake_commit) {
> > +   state->fake_commit = commit = kzalloc(sizeof(*commit), 
> > GFP_KERNEL);
> > +   if (!commit)
> > +   return NULL;
> > +
> > +   init_commit(commit, NULL);
> > +   } else
> > +   commit = state->fake_commit;
> > +
> > +   drm_crtc_commit_get(commit);
> 
> I believe the reference counting is right. The double reference in the second 
> case (kref_init() when initializing the commit and drm_crtc_commit_get()) 
> should not cause a leak. The kref_init() takes a reference to store the 
> commit 
> in state->fake_commit, released in drm_atomic_state_default_clear(), and the 
> drm_crtc_commit_get() takes a reference returned by the function, stored in 
> new_*_state->commit by the caller.
> 
> This being said, I think the reference counting is confusing, as proved by 
> Daniel thinking there was a leak here (or by me thinking there's no leak 
> while 
> there's one :-)). To make the implementation clearer, I propose turning the 
> definition of drm_crtc_commit_get() to
> 
> static inline struct drm_crtc_commit *
> drm_crtc_commit_get(struct drm_crtc_commit *commit)
> {
>   kref_get(>ref);
>   return commit;
> }
> 
> and writing this function as
> 
> /* Return a new reference to the commit object */
> static struct drm_crtc_commit *
> fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> {
>   struct drm_crtc_commit *commit;
> 
>   if (crtc) {
>   struct drm_crtc_state *new_crtc_state;
> 
>   

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:26PM -0700, Rodrigo Vivi wrote:
> Sequences for DisplayPort asks us to
> " Configure voltage swing and related IO settings.
> Refer to DDI Buffer section."
> 
> before "Configure and enable DDI_BUF_CTL"
> 
> On BXT and CNL this means to execute the ddi vswing sequences.
> 
> At this point these sequences calls are getting duplicated for DP
> because they are all called from DP link trainning sequences.
> 
> However this patch is not yet removing it before a futher discussion
> since spec also allows that during link training without disabling
> anything:
> 
> "
> Notes
> Changing voltage swing during link training:
> Change the swing setting following the DDI Buffer section.
> The port does not need to be disabled.
> "
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 

Imre is out atm so we didn't get his opinion, but I'm fine with this so
Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index eedd29487e0b..506782c1a62a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2136,6 +2136,7 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> + uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
>  
> @@ -2148,7 +2149,11 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
> + else if (IS_GEN9_LP(dev_priv))
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> + else
>   intel_prepare_dp_ddi_buffers(encoder);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Align vswing sequences with old ddi buffer registers.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:25PM -0700, Rodrigo Vivi wrote:
> Vswing sequences on BXT and CNL are equivalent
> to the ddi buffer registers setting on other platforms.
> 
> For some reason it got aligned with skl_ddi_set_iboost what
> is semantically incorrect. This forced us to keep skipping
> ddi buffer translation tables on the platforms that has
> the vswing sequences.
> 
> v2: Don't mess with DP signal levels on this patch.
> 
> Cc: Vandana Kannan 
> Cc: Imre Deak 
> Cc: Ville Syrjälä 
> Cc: Ander Conselvan de Oliveira 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 22 ++
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a887780f99f..eedd29487e0b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct 
> intel_encoder *encoder)
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   const struct ddi_buf_trans *ddi_translations;
>  
> - if (IS_GEN9_LP(dev_priv))
> - return;
> -
>   switch (encoder->type) {
>   case INTEL_OUTPUT_EDP:
>   ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
> @@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
> intel_encoder *encoder)
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   const struct ddi_buf_trans *ddi_translations_hdmi;
>  
> - if (IS_GEN9_LP(dev_priv))
> - return;
> -
>   hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
>  
>   if (IS_GEN9_BC(dev_priv)) {
> @@ -2154,7 +2148,9 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - intel_prepare_dp_ddi_buffers(encoder);
> + if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
> + intel_prepare_dp_ddi_buffers(encoder);
> +
>   intel_ddi_init_dp_buf_reg(encoder);
>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
> @@ -2180,14 +2176,16 @@ static void intel_ddi_pre_enable_hdmi(struct 
> intel_encoder *encoder,
>  
>   intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>  
> - intel_prepare_hdmi_ddi_buffers(encoder);
> - if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, level);
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
>   else if (IS_GEN9_LP(dev_priv))
>   bxt_ddi_vswing_sequence(dev_priv, level, port,
>   INTEL_OUTPUT_HDMI);
> - else if (IS_CANNONLAKE(dev_priv))
> - cnl_ddi_vswing_sequence(encoder, level);
> + else
> + intel_prepare_hdmi_ddi_buffers(encoder);
> +
> + if (IS_GEN9_BC(dev_priv))
> + skl_ddi_set_iboost(encoder, level);
>  
>   intel_dig_port->set_infoframes(>base,
>  has_infoframe,
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce intel_ddi_dp_level.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:23PM -0700, Rodrigo Vivi wrote:
> No functional changes. This only moves the DP level
> selection to a separated function that will be later
> used to organize better the vswing sequences.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0a316a6ccb50..7e875e05d053 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2054,18 +2054,22 @@ static uint32_t translate_signal_level(int 
> signal_levels)
>   return 0;
>  }
>  
> +static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
> +{
> + uint8_t train_set = intel_dp->train_set[0];
> + int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> +  DP_TRAIN_PRE_EMPHASIS_MASK);
> +
> + return translate_signal_level(signal_levels);
> +}
> +
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>   struct intel_encoder *encoder = >base;
> - uint8_t train_set = intel_dp->train_set[0];
> - int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> -  DP_TRAIN_PRE_EMPHASIS_MASK);
>   enum port port = dport->port;
> - uint32_t level;
> -
> - level = translate_signal_level(signal_levels);
> + uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   if (IS_GEN9_BC(dev_priv))
>   skl_ddi_set_iboost(encoder, level);
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 8/8] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:30PM -0700, Rodrigo Vivi wrote:
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 35 +++
>  1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f1757a8e481a..97ff082c28a7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static int cnl_max_level(struct drm_i915_private *dev_priv,
> +  enum intel_output_type type)
> +{
> + int n_entries = 0;
> +
> + switch (type) {
> + case INTEL_OUTPUT_DP:
> + cnl_get_buf_trans_dp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_EDP:
> + cnl_get_buf_trans_edp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_HDMI:
> + cnl_get_buf_trans_hdmi(dev_priv, _entries);
> + break;
> + default:
> + MISSING_CASE(type);
> + return 0;
> + }
> +
> + return n_entries - 1;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1879,10 +1902,14 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   int n_entries;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_max_level(dev_priv, encoder->type);

You're not actually using the return value. Also the return value has -1
already applied, whereas here we just need the n_entries w/o -1.

> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + }
>  
>   if (WARN_ON(n_entries < 1))
>   n_entries = 1;
> -- 
> 2.13.2

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Re: [Intel-gfx] [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:29PM -0700, Rodrigo Vivi wrote:
> Let's get a proper HDMI DDI entry level for vswing programming
> sequences on CNL.
> 
> Spec doesn't specify any default for HDMI tables,
> so let's pick the last entry as the default for now.
> 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 3ce02cbd4483..f1757a8e481a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -660,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private 
> *dev_priv, enum port por
>   if (IS_GEN9_LP(dev_priv))
>   return hdmi_level;
>  
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_get_buf_trans_hdmi(dev_priv, _hdmi_entries);
> + hdmi_default_entry = n_hdmi_entries - 1;

Hmm. I guess we might try to do the same thing for BXT, for extra
consistency. But that's a separate issue.

Reviewed-by: Ville Syrjälä 

> + } else if (IS_GEN9_BC(dev_priv)) {
>   skl_get_buf_trans_hdmi(dev_priv, _hdmi_entries);
>   hdmi_default_entry = 8;
>   } else if (IS_BROADWELL(dev_priv)) {
> -- 
> 2.13.2
> 
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Re: [Intel-gfx] [PATCH 5/8] drm/i915/cnl: Move voltage check into ddi buf trans functions.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:27PM -0700, Rodrigo Vivi wrote:
> Let's start converging CNL buf translations to same style
> used on previous platforms. So first thing is to use the
> standard signature so we don't need to propagate the voltage
> check into other parts of the code, but only on the parts
> that it is really useful.
> 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 48 
> ++--
>  1 file changed, 21 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 506782c1a62a..7b547a7f6c2b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1830,9 +1830,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> -u32 voltage, int *n_entries)
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

I wonder if we should just cache that somewhere. My main worry is
whether the device is always awake when we call this code.

> +
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
>   return cnl_ddi_translations_hdmi_0_85V;
> @@ -1842,14 +1843,16 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
>   return cnl_ddi_translations_hdmi_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);

nit: Looks like these if ladders could be turned into switch statements.


Anyways, patch lgtm
Reviewed-by: Ville Syrjälä 

>   return NULL;
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> -  u32 voltage, int *n_entries)
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
>   return cnl_ddi_translations_dp_0_85V;
> @@ -1859,14 +1862,16 @@ cnl_get_buf_trans_dp(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
>   return cnl_ddi_translations_dp_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);
>   return NULL;
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> -   u32 voltage, int *n_entries)
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
>   if (dev_priv->vbt.edp.low_vswing) {
>   if (voltage == VOLTAGE_INFO_0_85V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> @@ -1877,10 +1882,11 @@ cnl_get_buf_trans_edp(struct drm_i915_private 
> *dev_priv,
>   } else if (voltage == VOLTAGE_INFO_1_05V) {
>   *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
>   return cnl_ddi_translations_edp_1_05V;
> - }
> + } else
> + MISSING_CASE(voltage);
>   return NULL;
>   } else {
> - return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
> + return cnl_get_buf_trans_dp(dev_priv, n_entries);
>   }
>  }
>  
> @@ -1888,31 +1894,19 @@ static void cnl_ddi_vswing_program(struct 
> drm_i915_private *dev_priv,
>   u32 level, enum port port, int type)
>  {
>   const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> - u32 n_entries, val, voltage;
> + u32 n_entries, val;
>   int ln;
>  
> - /*
> -  * Values for each port type are listed in
> -  * voltage swing programming tables.
> -  * Vccio voltage found in PORT_COMP_DW3.
> -  */
> - voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
>   if (type == INTEL_OUTPUT_HDMI) {
> - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
> -   voltage, _entries);
> + ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, _entries);
>   } else if (type == INTEL_OUTPUT_DP) {
> - ddi_translations = cnl_get_buf_trans_dp(dev_priv,
> - voltage, _entries);
> + ddi_translations = cnl_get_buf_trans_dp(dev_priv, _entries);
>   } 

Re: [Intel-gfx] [PATCH 4/5] drm/atomic: Fix freeing connector/plane state too early by tracking commits, v2.

[Laurent Pinchart]

Hi Maarten,

Thank you for the patch.

On Wednesday, 30 August 2017 15:17:51 EEST Maarten Lankhorst wrote:
> Currently we neatly track the crtc state, but forget to look at
> plane/connector state.
> 
> When doing a nonblocking modeset, immediately followed by a setprop
> before the modeset completes, the setprop will see the modesets new
> state as the old state and free it.
> 
> This has to be solved by waiting for hw_done on the connector, even
> if it's not assigned to a crtc. When a connector is unbound we take
> the last crtc commit, and when it stays unbound we create a new
> fake crtc commit for that gets signaled on hw_done for all the
> planes/connectors.
> 
> We wait for it the same way as we do for crtc's, which will make
> sure we never run into a use-after-free situation.
> 
> Changes since v1:
> - Only create a single disable commit. (danvet)
> - Fix leak in intel_legacy_cursor_update.
> 
> Signed-off-by: Maarten Lankhorst 
> Testcase: kms_atomic_transition.plane-use-after-nonblocking-unbind*
> Cc: Laurent Pinchart 
> ---
>  drivers/gpu/drm/drm_atomic.c |   4 +
>  drivers/gpu/drm/drm_atomic_helper.c  | 156 ++--
>  drivers/gpu/drm/i915/intel_display.c |   2 +
>  include/drm/drm_atomic.h |  12 +++
>  include/drm/drm_connector.h  |   7 ++
>  include/drm/drm_plane.h  |   7 ++
>  6 files changed, 182 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 2cce48f203e0..75f5f74de9bf 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -192,6 +192,10 @@ void drm_atomic_state_default_clear(struct
> drm_atomic_state *state) }
>   state->num_private_objs = 0;
> 
> + if (state->fake_commit) {
> + drm_crtc_commit_put(state->fake_commit);
> + state->fake_commit = NULL;
> + }
>  }
>  EXPORT_SYMBOL(drm_atomic_state_default_clear);
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index 8ccb8b6536c0..034f563fb130
> 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1644,6 +1644,40 @@ static void release_crtc_commit(struct completion
> *completion) drm_crtc_commit_put(commit);
>  }
> 
> +static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc
> *crtc)
> +{

You could allocate the commit in this function too, the kzalloc() is currently 
duplicated. The function should probably be called alloc_commit() then.

> + init_completion(>flip_done);
> + init_completion(>hw_done);
> + init_completion(>cleanup_done);
> + INIT_LIST_HEAD(>commit_entry);
> + kref_init(>ref);
> + commit->crtc = crtc;
> +}
> +
> +static struct drm_crtc_commit *
> +fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
> +{
> + struct drm_crtc_commit *commit;
> +
> + if (crtc) {
> + struct drm_crtc_state *new_crtc_state;
> +
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> +
> + commit = new_crtc_state->commit;
> + } else if (!state->fake_commit) {
> + state->fake_commit = commit = kzalloc(sizeof(*commit), 
> GFP_KERNEL);
> + if (!commit)
> + return NULL;
> +
> + init_commit(commit, NULL);
> + } else
> + commit = state->fake_commit;
> +
> + drm_crtc_commit_get(commit);

I believe the reference counting is right. The double reference in the second 
case (kref_init() when initializing the commit and drm_crtc_commit_get()) 
should not cause a leak. The kref_init() takes a reference to store the commit 
in state->fake_commit, released in drm_atomic_state_default_clear(), and the 
drm_crtc_commit_get() takes a reference returned by the function, stored in 
new_*_state->commit by the caller.

This being said, I think the reference counting is confusing, as proved by 
Daniel thinking there was a leak here (or by me thinking there's no leak while 
there's one :-)). To make the implementation clearer, I propose turning the 
definition of drm_crtc_commit_get() to

static inline struct drm_crtc_commit *
drm_crtc_commit_get(struct drm_crtc_commit *commit)
{
kref_get(>ref);
return commit;
}

and writing this function as

/* Return a new reference to the commit object */
static struct drm_crtc_commit *
fake_or_crtc_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
struct drm_crtc_commit *commit;

if (crtc) {
struct drm_crtc_state *new_crtc_state;

new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

commit = new_crtc_state->commit;
} else {
if (!state->fake_commit)
state->fake_commit = alloc_commit(NULL);

commit = state->fake_commit;
 

Re: [Intel-gfx] [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels.

[Ville Syrjälä]

On Tue, Aug 29, 2017 at 04:22:24PM -0700, Rodrigo Vivi wrote:
> Let's decouple bxt, glk and cnl dp signal levels
> from other DDIs to avoid confusion.
> 
> No functional change. Only a reorg to avoid messing
> with currently working DP signal levels when
> moving voltage swing sequences around to match spec.
> 
> v2: ddi_signal_levels is also called from other ddi
> platforms, so don't remove IS_GEN9_BC check from
> skl_ddi_set_iboos. (Ville).
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 27 ++-
>  drivers/gpu/drm/i915/intel_dp.c  | 10 --
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  3 files changed, 23 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7e875e05d053..9a887780f99f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp 
> *intel_dp)
>   return translate_signal_level(signal_levels);
>  }
>  
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 bxt_signal_levels(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>   struct intel_encoder *encoder = >base;
>   enum port port = dport->port;
> + u32 level = intel_ddi_dp_level(intel_dp);
> +
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
> + else
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +
> + return 0;
> +}
> +
> +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> + struct intel_encoder *encoder = >base;
>   uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>   if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, level);
> - else if (IS_GEN9_LP(dev_priv))
> - bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> - else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_ddi_vswing_sequence(encoder, level);
> - /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> - return 0;
> - }
> + skl_ddi_set_iboost(encoder, level);

Tab got changed into spaces somehow.

With that fixed
Reviewed-by: Ville Syrjälä 

> +
>   return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d3e5fdf0d2fa..49a8c339b2b0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>   uint32_t signal_levels, mask = 0;
>   uint8_t train_set = intel_dp->train_set[0];
>  
> - if (HAS_DDI(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + signal_levels = bxt_signal_levels(intel_dp);
> + } else if (HAS_DDI(dev_priv)) {
>   signal_levels = ddi_signal_levels(intel_dp);
> -
> - if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> - signal_levels = 0;
> - else
> - mask = DDI_BUF_EMP_MASK;
> + mask = DDI_BUF_EMP_MASK;
>   } else if (IS_CHERRYVIEW(dev_priv)) {
>   signal_levels = chv_signal_levels(intel_dp);
>   } else if (IS_VALLEYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 17649f13091c..469c06000774 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state 
> *crtc_state,
>   bool state);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
>  
> -- 
> 2.13.2

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Always wake the device to flush the GTT

[Daniel Vetter]

On Wed, Aug 30, 2017 at 01:56:40PM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2017-08-30 13:23:56)
> > Or just the need to add a pile more tests to pm_rpm?
> 
> No. It's just your regular combinatorial explosion. The approach I would
> take here would be to register a sysenter callback that attempted to do a
> rpm suspend (i.e. so ~every ioctl would start from idle, and controlled
> via the faultinjection framework) and then run the minimal test set that
> exercises all ioctl paths, and then expand to all driver branches.
> 
> First we need coverage feedback.

What I meant to imply: As long as any display is on we will never rpm
suspend. Mostly this is the case for CI machines.

The new testcases I've had in mind would explicitly dpms off the display
before running a set of gem testcases. We don't want to do that everywhere
though, because a dpms on/off is very costly.

I guess once we switch (eventually, hopefully) to a binary-at-time model
for full igt CI we could amortize that over a pile of substests and do it
almost everywhere.

So I think adding a force rpm suspend won't help, because under normal CI
runs we can't ever get there becaus of the active display. And that's why
we're not hitting all these tons of problems anywhere else.

This might also be good reason for more server chips, or at least fake
server chips, where we disable the display entirely.
-Daniel
-- 
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http://blog.ffwll.ch
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[Intel-gfx] [PATCH i-g-t] lib/igt_aux: Allow sysfs open to fail when setting suspend/resume delay

[Paul Kocialkowski]

This removes the igt_require condition on the sysfs open call used to
write the suspend/resume delay so that it is allowed to fail. Intsead,
the code that depends on it is put in a conditional block.

This allows running test binaries as a non-privileged user for e.g.
listing the available tests with the SuspendResumeDelay parameter set
in igtrc configuration. Sysfs access would otherwise cause it to fail.

Signed-off-by: Paul Kocialkowski 
---
 lib/igt_aux.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index f428f159..d808fe3e 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -883,19 +883,21 @@ void igt_set_autoresume_delay(int delay_secs)
 
igt_skip_on_simulation();
 
-   igt_require((delay_fd = 
open("/sys/module/suspend/parameters/pm_test_delay",
-   O_RDWR)) >= 0);
+   delay_fd = open("/sys/module/suspend/parameters/pm_test_delay", O_RDWR);
+
+   if (delay_fd >= 0) {
+   if (!original_autoresume_delay) {
+   igt_require(read(delay_fd, delay_str,
+sizeof(delay_str)));
+   original_autoresume_delay = atoi(delay_str);
+   igt_install_exit_handler(igt_restore_autoresume_delay);
+   }
 
-   if (!original_autoresume_delay) {
-   igt_require(read(delay_fd, delay_str, sizeof(delay_str)));
-   original_autoresume_delay = atoi(delay_str);
-   igt_install_exit_handler(igt_restore_autoresume_delay);
-   }
+   snprintf(delay_str, sizeof(delay_str), "%d", delay_secs);
+   igt_require(write(delay_fd, delay_str, strlen(delay_str)));
 
-   snprintf(delay_str, sizeof(delay_str), "%d", delay_secs);
-   igt_require(write(delay_fd, delay_str, strlen(delay_str)));
-
-   close(delay_fd);
+   close(delay_fd);
+   }
 
autoresume_delay = delay_secs;
 }
-- 
2.14.0

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[Intel-gfx] [PATCH v4 2/3] drm/i915: rework IS_*_GT* macros

[Lionel Landwerlin]

We can now make use of the intel_device_info.gt field.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d417537bd59..51c25b65611c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,9 +2869,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)   ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
-INTEL_DEVID(dev_priv) == 0x0152 || \
-INTEL_DEVID(dev_priv) == 0x015a)
+#define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
+(dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)((dev_priv)->info.platform == 
INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)   ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2893,11 +2892,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)   (IS_BROADWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)   (IS_BROADWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_HSW_ULT(dev_priv)   (IS_HASWELL(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)   (IS_HASWELL(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0A0E || \
 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2918,15 +2917,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 INTEL_DEVID(dev_priv) == 0x5915 || \
 INTEL_DEVID(dev_priv) == 0x591E)
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_SKL_GT4(dev_priv)   (IS_SKYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
+(dev_priv)->info.gt == 4)
 #define IS_KBL_GT2(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
+(dev_priv)->info.gt == 2)
 #define IS_KBL_GT3(dev_priv)   (IS_KABYLAKE(dev_priv) && \
-(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+(dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 
-- 
2.14.1

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[Intel-gfx] [PATCH v4 3/3] drm/i915/perf: add support for Coffeelake GT2

[Lionel Landwerlin]

Add the test configuration & timestamp frequency for Coffeelake GT2.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 +++
 drivers/gpu/drm/i915/i915_perf.c  |   5 ++
 5 files changed, 152 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..a972c770c4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
  i915_oa_bxt.o \
  i915_oa_kblgt2.o \
  i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51c25b65611c..004338f5cdc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2928,6 +2928,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c 
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+   { _MMIO(0x2740), 0x },
+   { _MMIO(0x2744), 0x0080 },
+   { _MMIO(0x2714), 0xf080 },
+   { _MMIO(0x2710), 0x },
+   { _MMIO(0x2724), 0xf080 },
+   { _MMIO(0x2720), 0x },
+   { _MMIO(0x2770), 0x0004 },
+   { _MMIO(0x2774), 0x },
+   { _MMIO(0x2778), 0x0003 },
+   { _MMIO(0x277c), 0x },
+   { _MMIO(0x2780), 0x0007 },
+   { _MMIO(0x2784), 0x },
+   { _MMIO(0x2788), 0x0012 },
+   { _MMIO(0x278c), 0xfff7 },
+   { _MMIO(0x2790), 0x0012 },
+   { _MMIO(0x2794), 0xffcf },
+   { _MMIO(0x2798), 0x00100082 },
+   { _MMIO(0x279c), 0xffef },
+   { _MMIO(0x27a0), 0x001000c2 },
+   { _MMIO(0x27a4), 0xffe7 },
+   { _MMIO(0x27a8), 0x0011 },
+   { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+   { _MMIO(0x9840), 0x0080 },
+   { _MMIO(0x9888), 0x1181 },
+   { _MMIO(0x9888), 0x07810013 },
+   { _MMIO(0x9888), 0x1f81 },
+   { _MMIO(0x9888), 0x1d81 },
+   { _MMIO(0x9888), 0x1b930040 },
+   { _MMIO(0x9888), 0x07e54000 },
+   { _MMIO(0x9888), 0x1f908000 },
+   { _MMIO(0x9888), 0x1190 },
+   { _MMIO(0x9888), 0x3790 },
+   { _MMIO(0x9888), 0x5390 },
+   { _MMIO(0x9888), 0x4590 },
+   { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   return sprintf(buf, "1\n");
+}
+
+void

[Intel-gfx] [PATCH v4 0/3] drm/i915: add perf support for Coffeelake

[Lionel Landwerlin]

Inconsistencies noticed by Ville in patch 1.

Cheers,

Lionel Landwerlin (3):
  drm/i915: add GT number to intel_device_info
  drm/i915: rework IS_*_GT* macros
  drm/i915/perf: add support for Coffeelake GT2

 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  22 ++--
 drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 +++
 drivers/gpu/drm/i915/i915_oa_cflgt2.h |  34 ++
 drivers/gpu/drm/i915/i915_pci.c   | 193 ++
 drivers/gpu/drm/i915/i915_perf.c  |   5 +
 include/drm/i915_pciids.h | 152 --
 7 files changed, 407 insertions(+), 111 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
 create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h

--
2.14.1
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[Intel-gfx] [PATCH v4 1/3] drm/i915: add GT number to intel_device_info

[Lionel Landwerlin]

Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c | 193 +++-
 include/drm/i915_pciids.h   | 152 +++
 3 files changed, 246 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..3d417537bd59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -842,6 +842,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
+   u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
 #define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b696bcfa..f56aa8e3890b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,15 +224,34 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_sandybridge_d_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
+#define SNB_D_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE
+
+static const struct intel_device_info intel_sandybridge_d_gt1_info = {
+   SNB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_sandybridge_m_info = {
-   GEN6_FEATURES,
-   .platform = INTEL_SANDYBRIDGE,
-   .is_mobile = 1,
+static const struct intel_device_info intel_sandybridge_d_gt2_info = {
+   SNB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define SNB_M_PLATFORM \
+   GEN6_FEATURES, \
+   .platform = INTEL_SANDYBRIDGE, \
+   .is_mobile = 1
+
+
+static const struct intel_device_info intel_sandybridge_m_gt1_info = {
+   SNB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_sandybridge_m_gt2_info = {
+   SNB_M_PLATFORM,
+   .gt = 2,
 };
 
 #define GEN7_FEATURES  \
@@ -249,22 +268,41 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
-static const struct intel_device_info intel_ivybridge_d_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .has_l3_dpf = 1,
+#define IVB_D_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_d_gt1_info = {
+   IVB_D_PLATFORM,
+   .gt = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_m_info = {
-   GEN7_FEATURES,
-   .platform = INTEL_IVYBRIDGE,
-   .is_mobile = 1,
-   .has_l3_dpf = 1,
+static const struct intel_device_info intel_ivybridge_d_gt2_info = {
+   IVB_D_PLATFORM,
+   .gt = 2,
+};
+
+#define IVB_M_PLATFORM \
+   GEN7_FEATURES, \
+   .platform = INTEL_IVYBRIDGE, \
+   .is_mobile = 1, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_ivybridge_m_gt1_info = {
+   IVB_M_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_gt2_info = {
+   IVB_M_PLATFORM,
+   .gt = 2,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
+   .gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
 };
@@ -299,10 +337,24 @@ static const struct intel_device_info 
intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
 
-static const struct intel_device_info intel_haswell_info = {
-   HSW_FEATURES,
-   .platform = INTEL_HASWELL,
-   .has_l3_dpf = 1,
+#define HSW_PLATFORM \
+   HSW_FEATURES, \
+   .platform = INTEL_HASWELL, \
+   .has_l3_dpf = 1
+
+static const struct intel_device_info intel_haswell_gt1_info = {
+   HSW_PLATFORM,
+   .gt = 1,
+};
+
+static const struct intel_device_info intel_haswell_gt2_info = {
+   HSW_PLATFORM,
+   .gt = 2,
+};
+
+static const struct intel_device_info intel_haswell_gt3_info = {
+   HSW_PLATFORM,
+   .gt = 3,
 };
 
 #define BDW_FEATURES \
@@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info 
= {
.gen = 8, \
.platform = INTEL_BROADWELL
 
-static const struct intel_device_info intel_broadwell_info = {
+static const struct 

[Intel-gfx] ✓ Fi.CI.BAT: success for pm_rps: Changes in waitboost scenario (rev9)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev9)
URL   : https://patchwork.freedesktop.org/series/28966/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
fc6510887f8f45e18ca267e53eb564de043bd9d6 tools: Add intel_vbt_defs.h to 
Makefile.sources

with latest DRM-Tip kernel build CI_DRM_3018
6a305b78140a drm-tip: 2017y-08m-30d-08h-12m-34s UTC integration manifest

Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> INCOMPLETE (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:365s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:566s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:527s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:528s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:527s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:434s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:624s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:451s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:427s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:472s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:483s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:601s
fi-pnv-d510  total:156  pass:113  dwarn:0   dfail:0   fail:0   skip:42 
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:474s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:567s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:439s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:553s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:411s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_125/
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