[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/9] drm/i915/gvt: Make elsp_dwords in the right order
== Series Details == Series: series starting with [v2,1/9] drm/i915/gvt: Make elsp_dwords in the right order URL : https://patchwork.freedesktop.org/series/30164/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2301 pass:1235 dwarn:0 dfail:0 fail:14 skip:1052 time:9348s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5650/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v13 2/5] drm/i915: Introduce private PAT management
On 09/11/17 16:59, Joonas Lahtinen wrote:
On Mon, 2017-09-11 at 12:26 +0800, Zhi Wang wrote:
The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.
intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate a new
entry if there is any available PPAT indexs, or return a partially
matched PPAT entry if there is no available PPAT indexes.
intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.
Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update_hw(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.
v12:
- Fix a problem "not returning the entry of best score". (Zhenyu)
This change should have resulted in adding an indication that Chris
reviewed only a previous version of the patch.
v7:
- Keep all the register writes unchanged in this patch. (Joonas)
v6:
- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html
- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html
v5:
- Add check and warnnings for those platforms which don't have PPAT.
v3:
- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)
v2:
- API re-design. (Chris)
Reviewed-by: Chris Wilson
Cc: Ben Widawsky
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Zhi Wang
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @i915: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, the partially
+ * matched entry will be used.
+ */
+const struct intel_ppat_entry *
+intel_ppat_get(struct drm_i915_private *i915, u8 value)
+{
+ struct intel_ppat *ppat = &i915->ppat;
+ struct intel_ppat_entry *entry;
+ unsigned int scanned, best_score;
+ int i;
+
+ GEM_BUG_ON(!ppat->max_entries);
+
+ scanned = best_score = 0;
You can drop this extra newline.
+ for_each_set_bit(i, ppat->used, ppat->max_entries) {
+ unsigned int score;
+
+ score = ppat->match(ppat->entries[i].value, value);
+ if (score > best_score) {
If you set "entry = &ppat->entries[i];" here already.
+ if (score == INTEL_PPAT_PERFECT_MATCH) {
+ kref_get(&ppat->entries[i].ref);
+ return &ppat->entries[i];
These become "kref_get(&entry->ref);" and "return entry;"
+static unsigned int bdw_private_pat_match(u8 src, u8 dst)
+{
+ unsigned int score = 0;
+
+ /* Cache attribute has to be matched. */
+ if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
+ return 0;
We're not giving any points for when only cache attribute matches? Does
not this result in ENOSPC when we would have an entry with matching
"cache attribute", but no other matching entries while PPAT is full.
so maybe score += 4 here?
Aiha. cache attribute of src == cache attribute of dst is mandatory
since the mismatch of other attribute only causes performance drop, but
mismatch of cache attribute causes problem of correctness.
+
+ if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
+ score += 2;
+
+ if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
+ score += 1;
+
+ if (score == 3)
(score == 7) respectively.
+ return INTEL_PPAT_PERFECT_MATCH;
+
+ return score;
+}
+
+static unsigned int chv_private_pat_match(u8 src, u8 dst)
+{
+ return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
+ INTEL_PPAT_PERFECT_MATCH : 0;
This handles the situation correctly, when snooping is the only
attribute looked for.
With the BDW attribute fix scoring, this is;
Reviewed-by: Joonas Lahtinen
Remember to add to the end of the tag list ;)
Regards, Joonas
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[Intel-gfx] [PATCH for trybot] drm/i915: Trybot always warn check
---
drivers/gpu/drm/i915/intel_sprite.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b0d6e3e28d07..e14c7c46fcac 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -214,14 +214,12 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state)
crtc->debug.min_vbl, crtc->debug.max_vbl,
crtc->debug.scanline_start, scanline_end);
}
-#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
VBLANK_EVASION_TIME_US)
DRM_WARN("Atomic update on pipe (%c) took %lld us, max time
under evasion is %u us\n",
pipe_name(pipe),
ktime_us_delta(end_vbl_time,
crtc->debug.start_vbl_time),
VBLANK_EVASION_TIME_US);
-#endif
}
static void
--
2.14.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Trybot always warn check
== Series Details == Series: drm/i915: Trybot always warn check URL : https://patchwork.freedesktop.org/series/30170/ State : success == Summary == Series 30170v1 drm/i915: Trybot always warn check https://patchwork.freedesktop.org/api/1.0/series/30170/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102672 Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:455s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:376s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:539s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:272s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:504s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:490s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:455s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:457s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:592s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:488s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:488s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:555s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:460s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:503s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:570s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:423s 3cbfafbde5bb92b6ecdbfd47e189d2742aa6fbec drm-tip: 2017y-09m-11d-23h-04m-21s UTC integration manifest 7b99ea7f8f65 drm/i915: Trybot always warn check == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5651/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm: handle override and firmware EDID at drm_do_get_edid() level
Handle debugfs override edid and firmware edid at the low level to
transparently and completely replace the real edid. Previously, we
practically only used the modes from the override EDID, and none of the
other data, such as audio parameters.
This change also prevents actual EDID reads when the EDID is to be
overridden, but retains the DDC probe. This is useful if the reason for
preferring override EDID are problems with reading the data, or
corruption of the data.
Move firmware EDID loading from helper to core, as the functionality
moves to lower level as well. This will result in a change of module
parameter from drm_kms_helper.edid_firmware to drm.edid_firmware, which
arguably makes more sense anyway.
Some future work remains related to override and firmware EDID
validation. Like before, no validation is done for override EDID. The
firmware EDID is validated separately in the loader. Some unification
and deduplication would be in order, to validate all of them at the
drm_do_get_edid() level, like "real" EDIDs.
v2: move firmware loading to core
v3: rebase, commit message refresh
Cc: Abdiel Janulgue
Cc: Daniel Vetter
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
Documentation/admin-guide/kernel-parameters.txt | 2 +-
drivers/gpu/drm/Kconfig | 2 +-
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/drm_edid.c | 15 +++
drivers/gpu/drm/drm_probe_helper.c | 19 +--
5 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index d9c171ce4190..9b393c29953f 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -854,7 +854,7 @@
The filter can be disabled or changed to another
driver later using sysfs.
- drm_kms_helper.edid_firmware=[:][,[:]]
+ drm.edid_firmware=[:][,[:]]
Broken monitors, graphic adapters, KVMs and EDIDless
panels may send no or incorrect EDID data sets.
This parameter allows to specify an EDID data sets
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index c5e1a8409285..c9f09fc298bb 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -110,7 +110,7 @@ config DRM_FBDEV_OVERALLOC
config DRM_LOAD_EDID_FIRMWARE
bool "Allow to specify an EDID data set instead of probing for it"
- depends on DRM_KMS_HELPER
+ depends on DRM
help
Say Y here, if you want to use EDID data to be loaded from the
/lib/firmware directory or one of the provided built-in
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index df923119ac36..0ee184f56a60 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -28,6 +28,7 @@ drm-$(CONFIG_DRM_PANEL) += drm_panel.o
drm-$(CONFIG_OF) += drm_of.o
drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
+drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
@@ -36,7 +37,6 @@ drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o
drm_probe_helper.o \
drm_scdc_helper.o drm_gem_framebuffer_helper.o
drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o
-drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6bb6337be920..00ddabfbf980 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1533,6 +1533,10 @@ static void connector_bad_edid(struct drm_connector
*connector,
* level, drivers must make all reasonable efforts to expose it as an I2C
* adapter and use drm_get_edid() instead of abusing this function.
*
+ * The EDID may be overridden using debugfs override_edid or firmare EDID
+ * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
+ * order. Having either of them bypasses actual EDID reads.
+ *
* Return: Pointer to valid EDID or NULL if we couldn't find any.
*/
struct edid *drm_do_get_edid(struct drm_connector *connector,
@@ -1542,6 +1546,17 @@ struct edid *drm_do_get_edid(struct drm_connector
*connector,
{
int i, j = 0, valid_extensions = 0;
u8 *edid, *new;
+ struct edid *override = NULL;
+
+ if (connector->override_edid)
+ override = drm_edid_duplicate((const struct edid *)
+ connector->edid_blob_ptr->da
[Intel-gfx] [PATCH v3 0/2] drm/edid: transparent low-level override/firmware EDIDs
Patch 1 is v3 of [1]. There are no functional changes to the previous version, just a rebase and a slight refresh of the commit message and comments. I think the conclusion from the discussion was that this should work just fine. At least one user reported this helped with their audio woes with firmware EDID. Patch 2 is an attempt to mitigate the problem of moving the edid_firmware module parameter from drm_kms_helper to drm. Not sure if it's too much or too little or just right. Need input here. Pedantically it should be part of patch 1, but this division should be easier to grasp in review. BR, Jani. [1] http://patchwork.freedesktop.org/patch/msgid/1487344854-18777-5-git-send-email-jani.nik...@intel.com Cc: Abdiel Janulgue Cc: Daniel Vetter Cc: Ville Syrjälä Jani Nikula (2): drm: handle override and firmware EDID at drm_do_get_edid() level drm: add backwards compatibility support for drm_kms_helper.edid_firmware Documentation/admin-guide/kernel-parameters.txt | 2 +- drivers/gpu/drm/Kconfig | 2 +- drivers/gpu/drm/Makefile| 2 +- drivers/gpu/drm/drm_edid.c | 15 +++ drivers/gpu/drm/drm_edid_load.c | 7 +++ drivers/gpu/drm/drm_kms_helper_common.c | 19 +++ drivers/gpu/drm/drm_probe_helper.c | 19 +-- include/drm/drm_edid.h | 2 ++ 8 files changed, 47 insertions(+), 21 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm: add backwards compatibility support for drm_kms_helper.edid_firmware
If drm_kms_helper.edid_firmware module parameter is set at
drm_kms_helper probe time, update the new drm.edid_firmware parameter
for backwards compatibility.
The drm_kms_helper.edid_firmware is now read-only in sysfs to prevent
runtime updates.
This is a sort of easy middle ground; adding a full runtime support via
/sys/module/drm_kms_helper/parameters/edid_firmware would be possible,
but considerably more and uglier code.
Cc: Abdiel Janulgue
Cc: Daniel Vetter
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
I'm wondering if the change from drm_kms_helper.edid_firmware to
drm.edid_firmware is enough of an ABI breakage to warrant something like
this patch.
---
drivers/gpu/drm/drm_edid_load.c | 7 +++
drivers/gpu/drm/drm_kms_helper_common.c | 19 +++
include/drm/drm_edid.h | 2 ++
3 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index 1c0495acf341..a94005529cd4 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -31,6 +31,13 @@ module_param_string(edid_firmware, edid_firmware,
sizeof(edid_firmware), 0644);
MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob
"
"from built-in data or /lib/firmware instead. ");
+/* Use only for backward compatibility with drm_kms_helper.edid_firmware */
+void __drm_set_edid_firmware_path(const char *path)
+{
+ strlcpy(edid_firmware, path, sizeof(edid_firmware));
+}
+EXPORT_SYMBOL(__drm_set_edid_firmware_path);
+
#define GENERIC_EDIDS 6
static const char * const generic_edid_name[GENERIC_EDIDS] = {
"edid/800x600.bin",
diff --git a/drivers/gpu/drm/drm_kms_helper_common.c
b/drivers/gpu/drm/drm_kms_helper_common.c
index 6e35a56a6102..6130199a83b6 100644
--- a/drivers/gpu/drm/drm_kms_helper_common.c
+++ b/drivers/gpu/drm/drm_kms_helper_common.c
@@ -26,6 +26,7 @@
*/
#include
+#include
#include "drm_crtc_helper_internal.h"
@@ -33,10 +34,28 @@ MODULE_AUTHOR("David Airlie, Jesse Barnes");
MODULE_DESCRIPTION("DRM KMS helper");
MODULE_LICENSE("GPL and additional rights");
+#if IS_ENABLED(CONFIG_DRM_LOAD_EDID_FIRMWARE)
+static char edid_firmware[PATH_MAX];
+module_param_string(edid_firmware, edid_firmware, sizeof(edid_firmware), 0444);
+MODULE_PARM_DESC(edid_firmware, "DEPRECATED. Use drm.edid_firmware instead.");
+static inline void legacy_set_edid_firmare_path(void)
+{
+ if (edid_firmware[0]) {
+ DRM_NOTE("drm_kms_firmware.edid_firmware is deprecated, "
+"please use drm.edid_firmware intead.\n");
+ __drm_set_edid_firmware_path(edid_firmware);
+ }
+}
+#else
+static inline void legacy_set_edid_firmare_path(void) {}
+#endif
+
static int __init drm_kms_helper_init(void)
{
int ret;
+ legacy_set_edid_firmare_path();
+
/* Call init functions from specific kms helpers here */
ret = drm_fb_helper_modinit();
if (ret < 0)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 1e1908a6b1d6..cdfb793255f0 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -341,12 +341,14 @@ int drm_av_sync_delay(struct drm_connector *connector,
#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
struct edid *drm_load_edid_firmware(struct drm_connector *connector);
+void __drm_set_edid_firmware_path(const char *path);
#else
static inline struct edid *
drm_load_edid_firmware(struct drm_connector *connector)
{
return ERR_PTR(-ENOENT);
}
+static inline void __drm_set_edid_firmware_path(const char *path) {}
#endif
int
--
2.11.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: transparent low-level override/firmware EDIDs
== Series Details == Series: drm/edid: transparent low-level override/firmware EDIDs URL : https://patchwork.freedesktop.org/series/30182/ State : success == Summary == Series 30182v1 drm/edid: transparent low-level override/firmware EDIDs https://patchwork.freedesktop.org/api/1.0/series/30182/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102672 Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:461s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:377s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:542s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:503s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:487s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:448s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:451s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:596s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:411s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:435s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:458s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:490s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:552s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:500s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:464s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:479s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:569s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:427s 3cbfafbde5bb92b6ecdbfd47e189d2742aa6fbec drm-tip: 2017y-09m-11d-23h-04m-21s UTC integration manifest 0c51d38eadf2 drm: add backwards compatibility support for drm_kms_helper.edid_firmware cb109b29bd40 drm: handle override and firmware EDID at drm_do_get_edid() level == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5652/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/20] Add support for GuC-based SLPC
On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote: > SLPC (Single Loop Power Controller) is a replacement for some host-based > power management features. The SLPC implementation runs in GuC firmware. > This series has been tested with SKL/APL/KBL GuC firmware v9 and v10 > which are yet to be released on 01.org. > > The graphics power management features in SLPC are called GTPERF, > BALANCER, and DCC. > 1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts > requested graphics frequency to maintain target framerate. Turbo adjusts > requested graphics frequency to maintain target GT busyness. > 2. BALANCER adjusts balance between power budgets for IA and GT in power > limited scenarios. > 3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls > guc-scheduler to maintain actual graphics frequency in efficient range. > > This series activates GTPERF Turbo and BALANCER in GuC SLPC. > Patch to enable SLPC by default on platforms having support is removed > from this series as there are following new changes to be added in future > before we enable GuC/SLPC by default: > 1. Link waitboost with SLPC. > 2. Handle CPG as part of SLPC. > 3. IA p-state logic update with GuC submission. > > In order to enable CI/PnP testing of SLPC and to avoid frequent > rebase, this series should be safe for merge with feature in disabled > state. > > v2: Addressed review comments on v1. Removed patch to enable SLPC by > default. > > v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT. > Added change for sanitizing GT PM during reset. Added separate patch > for sysfs interface to know HW requested frequency. Also, earlier > patches did not go as series hence were not correctly picked up by BAT. > > v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL > GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC > improves performance when GuC is enabled compared to Host Turbo. > This series keeps only support of 9.18 firmware for better readability. > If needed, other SLPC interfaces for different GuC version will be > added later. > > v5: This series incorporates feedback from code reviews on earlier series > and adds following new changes: > 1. More changes for separation of RPS and RC6 handling for Gen9. > 2. Tied up SLPC enabling with GuC load/GuC submission sequence. > 3. SLPC structures are defined explicitly for event input/output. > 4. Definition of SLPC parameter control and task control functions > agnostic to the underlying param definitions as they might > change with GuC versions and prepared helpers for common tasks. > 5. Transition of i915 overrides done through host to guc events > to shared data and single reset event. > 6. Handling SLPC status post reset through shared memory. > 7. Derived helpers for setting frequency limits. > 8. Removed sysfs interface to know RPNSWREQ as it is available in > debugfs interface i915_frequency_info. > 9. Simple igt test to verify SLPC configuration by i915 in various > driver scenarios is prepared. > > v6: This series adds following new changes: > 1. Updated intel_guc_send for SLPC to receive output data from GuC. > 2. Added task overrides and min frequency overrides in intel_slpc_init. > min frequency is set to Rpe. > 3. New debugfs interface added to set/unset/read SLPC parameters > other than tasks and frequencies. SLPC reset post parameter update > added. > 4. SLPC parameters persist as part of i915-GuC shared data hence not > overriding frequency limits while re-enabling SLPC. > 5. Other minor fixes to clear pm_rps_events, clflush the shared data. > > v7: This series adds following new changes: > 1. Reordered patches. SLPC communication interfaces (structures and > functions) are pulled into patches earlier in the series. > 2. Eliminated dependency on i915.enable_slpc at various functions where > rps_enabled is available. > 3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter > in intel_uc_sanitize_options. > > v8: Activated Balancer. Changed prototype of SLPC functions to accept > struct intel_slpc as parameter instead of drm_i915_private. > > VIZ-6889, VIZ-6890 > > Cc: Chris Wilson > Cc: Daniel Vetter > Cc: Beuchat, Marc > Cc: Radoslaw Szwichtenberg > Cc: Jeff McGee > Cc: Arkadiusz Hiler > Cc: Oscar Mateo > Cc: Michał Winiarski I did enable SLPC on my machine and looks like everything is working fine. I will be spending more time reviewing whole series and also running some tests on my KBL to see if there are no functional problems. -Radek Acked-by: Radoslaw Szwichtenberg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.fre
[Intel-gfx] [PATCH 0/8] Support for more than two execlist ports
Hi, Here is a patchset to allow power-of-two number of execlist ports configurable at init time. The purpose is to support more than two ports (contexts) for guc submission. I did few runs of gem_exec_nop and gem_exec_ctx on non guc paths to verify that these don't regress the hw submission path. I expected a neutral or minor negative effect but there is an improvement. These needs to be rebased on top of Michał Winiarski's coalesced requests patch, but to get comments on the native side of handling and general approach, here it is. -Mika Mika Kuoppala (8): drm/i915: Make own struct for execlist items drm/i915: Wrap port cancellation into a function drm/i915: Add execlist_port_complete drm/i915: Make execlist port count variable drm/i915: Introduce iterators for execlist ports drm/i915: Introduce execlist_port_* accessors drm/i915: Move execlist initialization into intel_engine_cs.c drm/i915: Keep track of reserved execlist ports drivers/gpu/drm/i915/i915_debugfs.c| 9 +- drivers/gpu/drm/i915/i915_drv.h| 3 +- drivers/gpu/drm/i915/i915_gem.c| 17 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++- drivers/gpu/drm/i915/i915_guc_submission.c | 59 ++ drivers/gpu/drm/i915/i915_irq.c| 5 +- drivers/gpu/drm/i915/intel_engine_cs.c | 39 +-- drivers/gpu/drm/i915/intel_lrc.c | 159 ++ drivers/gpu/drm/i915/intel_ringbuffer.h| 173 + 9 files changed, 339 insertions(+), 143 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: Make execlist port count variable
GuC can handle more than two submission ports. Make port count
variable to prepare supporting more than 2 ports.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c| 8
drivers/gpu/drm/i915/i915_drv.h| 3 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 17 -
drivers/gpu/drm/i915/i915_guc_submission.c | 8 ++--
drivers/gpu/drm/i915/intel_lrc.c | 24
drivers/gpu/drm/i915/intel_ringbuffer.h| 23 ++-
6 files changed, 58 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index cc36409936dc..77ac775e312d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3315,6 +3315,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
upper_32_bits(addr), lower_32_bits(addr));
if (i915.enable_execlists) {
+ struct intel_engine_execlist * const el =
&engine->execlist;
u32 ptr, read, write;
unsigned int idx;
@@ -3344,11 +3345,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlist.port);
idx++) {
+ for (idx = 0; idx < execlist_num_ports(el); idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlist.port[idx],
-&count);
+ rq = port_unpack(&el->port[idx], &count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
idx, count);
@@ -3361,7 +3361,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist.first; rb; rb = rb_next(rb))
{
+ for (rb = el->first; rb; rb = rb_next(rb)) {
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cc31a5b049f..fd068ac66388 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1001,7 +1001,8 @@ struct i915_gpu_state {
u32 seqno;
u32 head;
u32 tail;
- } *requests, execlist[2];
+ } *requests, execlist[EXECLIST_MAX_PORTS];
+ unsigned int num_ports;
struct drm_i915_error_waiter {
char comm[TASK_COMM_LEN];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6114bf79219d..e048d713f72c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -396,6 +396,8 @@ static void error_print_context(struct
drm_i915_error_state_buf *m,
static void error_print_engine(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ int n;
+
err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
err_printf(m, " START: 0x%08x\n", ee->start);
err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -465,8 +467,11 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
err_printf(m, " engine reset count: %u\n", ee->reset_count);
- error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
- error_print_request(m, " ELSP[1]: ", &ee->execlist[1]);
+ for (n = 0; n < ee->num_ports; n++) {
+ err_printf(m, " ELSP[%d]:", n);
+ error_print_request(m, " ", &ee->execlist[n]);
+ }
+
error_print_context(m, " Active context: ", &ee->context);
}
@@ -1327,17 +1332,19 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct execlist_port *port = engine->execlist.port;
+ const struct intel_engine_execlist * const el = &engine->execlist;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++) {
- struct drm_i915_gem_request *rq = port_request(&port[n]);
+ for (n = 0; n < execlist_num_ports(el); n++) {
+ struct drm_i915_gem_request *rq = port_request(&el->port[n]);
if (!r
[Intel-gfx] [PATCH 6/8] drm/i915: Introduce execlist_port_* accessors
Instead of trusting that first available port is at index 0,
use accessor to hide this. This allows us to just move the head
on port completion instead of memmoving the array.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 15 ++-
drivers/gpu/drm/i915/i915_irq.c| 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 29 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 40 --
5 files changed, 57 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c38a3e71e285..0dfb03a0cee4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -662,9 +662,8 @@ static void port_assign(struct execlist_port *port,
static bool i915_guc_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
- const struct execlist_port * const last_port =
- &el->port[el->port_mask];
+ struct execlist_port *port = execlist_port_head(el);
+ const struct execlist_port * const last_port = execlist_port_tail(el);
struct drm_i915_gem_request *last = port_request(port);
struct rb_node *rb;
bool submit = false;
@@ -686,7 +685,8 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
if (submit)
port_assign(port, last);
- port++;
+
+ port = execlist_port_next(el, port);
}
INIT_LIST_HEAD(&rq->priotree.link);
@@ -717,9 +717,8 @@ static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
- const struct execlist_port * const last_port =
- &el->port[el->port_mask];
+ struct execlist_port *port = execlist_port_head(el);
+ const struct execlist_port * const last_port = execlist_port_tail(el);
struct drm_i915_gem_request *rq;
bool submit;
@@ -729,7 +728,7 @@ static void i915_guc_irq_handler(unsigned long data)
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
- execlist_port_complete(el, port);
+ port = execlist_port_complete(el, port);
rq = port_request(port);
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e16fbea03823..1919ac0b7b0f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1312,7 +1312,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir, int test_shift)
bool tasklet = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
- if (port_count(&el->port[0])) {
+ if (port_count(execlist_port_head(el))) {
__set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
tasklet = true;
}
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 192ecc26f432..0fb5a1f99349 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1334,7 +1334,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
return false;
/* Both ports drained, no more ELSP submission? */
- if (port_request(&engine->execlist.port[0]))
+ if (port_request(execlist_port_head(&engine->execlist)))
return false;
/* ELSP is empty, but there are ready requests? */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cfa21731b9c7..0bc42a3f9528 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -400,9 +400,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
{
struct drm_i915_gem_request *last;
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
- const struct execlist_port * const last_port =
- &el->port[el->port_mask];
+ struct execlist_port *port = execlist_port_head(el);
+ const struct execlist_port * const last_port = execlist_port_tail(el);
struct rb_node *rb;
bool submit = false;
@@ -486,7 +485,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (submit)
port_assign(port, last);
- port++;
+
+
[Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
To further enchance port processing, keep track of
reserved ports. This way we can iterate only the used subset
of port space. Note that we lift the responsibility of
execlists_submit_request() to inspect hw availability and
always do dequeuing. This is to ensure that only the irq
handler will be responsible for keeping track of available ports.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 43 ---
drivers/gpu/drm/i915/i915_irq.c| 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +-
drivers/gpu/drm/i915/intel_lrc.c | 84 ++
drivers/gpu/drm/i915/intel_ringbuffer.h| 50 +-
5 files changed, 117 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 0dfb03a0cee4..fdda3a1835ad 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -662,12 +662,19 @@ static void port_assign(struct execlist_port *port,
static bool i915_guc_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = execlist_port_head(el);
- const struct execlist_port * const last_port = execlist_port_tail(el);
- struct drm_i915_gem_request *last = port_request(port);
+ struct execlist_port *port;
+ struct drm_i915_gem_request *last;
struct rb_node *rb;
bool submit = false;
+ if (execlist_active_ports(el)) {
+ port = execlist_port_tail(el);
+ last = port_request(port);
+ } else {
+ port = NULL;
+ last = NULL;
+ }
+
spin_lock_irq(&engine->timeline->lock);
rb = el->first;
GEM_BUG_ON(rb_first(&el->queue) != rb);
@@ -675,9 +682,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs
*engine)
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
struct drm_i915_gem_request *rq, *rn;
+ if (!port)
+ port = execlist_request_port(el);
+
list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
if (last && rq->ctx != last->ctx) {
- if (port == last_port) {
+ if (!execlist_inactive_ports(el)) {
__list_del_many(&p->requests,
&rq->priotree.link);
goto done;
@@ -686,7 +696,8 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
if (submit)
port_assign(port, last);
- port = execlist_port_next(el, port);
+ port = execlist_request_port(el);
+ GEM_BUG_ON(port_isset(port));
}
INIT_LIST_HEAD(&rq->priotree.link);
@@ -717,26 +728,22 @@ static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = execlist_port_head(el);
- const struct execlist_port * const last_port = execlist_port_tail(el);
- struct drm_i915_gem_request *rq;
- bool submit;
do {
- rq = port_request(port);
- while (rq && i915_gem_request_completed(rq)) {
+ while (execlist_active_ports(el)) {
+ struct execlist_port *port = execlist_port_head(el);
+ struct drm_i915_gem_request *rq = port_request(port);
+
+ if (!i915_gem_request_completed(rq))
+ break;
+
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
- port = execlist_port_complete(el, port);
-
- rq = port_request(port);
+ execlist_release_port(el, port);
}
- submit = false;
- if (!port_count(last_port))
- submit = i915_guc_dequeue(engine);
- } while (submit);
+ } while (execlist_inactive_ports(el) && i915_guc_dequeue(engine));
}
/*
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1919ac0b7b0f..de4e608786a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1312,7 +1312,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir, int test_shift)
bool tasklet = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
- if (port_count(execlist_port_head(el))) {
+ if (ex
[Intel-gfx] [PATCH 7/8] drm/i915: Move execlist initialization into intel_engine_cs.c
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_engine_cs.c | 18 +++---
drivers/gpu/drm/i915/intel_lrc.c | 4
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0fb5a1f99349..4b9eaec50070 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -380,6 +380,20 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
}
+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlist * const el = &engine->execlist;
+
+ el->port_mask = 1;
+ BUILD_BUG_ON_NOT_POWER_OF_2(el->port_mask + 1);
+ GEM_BUG_ON(el->port_mask >= EXECLIST_MAX_PORTS);
+
+ el->port_head = 0;
+
+ el->queue = RB_ROOT;
+ el->first = NULL;
+}
+
/**
* intel_engines_setup_common - setup engine state not requiring hw access
* @engine: Engine to setup.
@@ -391,9 +405,7 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
*/
void intel_engine_setup_common(struct intel_engine_cs *engine)
{
- engine->execlist.queue = RB_ROOT;
- engine->execlist.first = NULL;
-
+ intel_engine_init_execlist(engine);
intel_engine_init_timeline(engine);
intel_engine_init_hangcheck(engine);
i915_gem_batch_pool_init(engine, &engine->batch_pool);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0bc42a3f9528..1a1c68c53fbd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1763,10 +1763,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
/* Intentionally left blank. */
engine->buffer = NULL;
- engine->execlist.port_mask = 1;
- BUILD_BUG_ON_NOT_POWER_OF_2(engine->execlist.port_mask + 1);
- GEM_BUG_ON(engine->execlist.port_mask >= EXECLIST_MAX_PORTS);
-
fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
RING_ELSP(engine),
FW_REG_WRITE);
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915: Introduce iterators for execlist ports
Switch to iterators for execlist_port access. This is
a preparation for indexing ports from arbitrary location. Which
in turn allows us to handle ports in ring like fashion.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++--
drivers/gpu/drm/i915/i915_gpu_error.c | 7 ---
drivers/gpu/drm/i915/intel_lrc.c| 23 +++
drivers/gpu/drm/i915/intel_ringbuffer.h | 16 +++-
4 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 77ac775e312d..6bff702a5fc6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,6 +3254,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
for_each_engine(engine, dev_priv, id) {
struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ struct execlist_port *port;
struct drm_i915_gem_request *rq;
struct rb_node *rb;
u64 addr;
@@ -3345,10 +3346,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < execlist_num_ports(el); idx++) {
+ for_each_execlist_port(el, port, idx) {
unsigned int count;
- rq = port_unpack(&el->port[idx], &count);
+ rq = port_unpack(port, &count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
idx, count);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index e048d713f72c..966f00de53aa 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1332,11 +1332,12 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct intel_engine_execlist * const el = &engine->execlist;
+ struct intel_engine_execlist * const el = &engine->execlist;
+ const struct execlist_port *port;
unsigned int n;
- for (n = 0; n < execlist_num_ports(el); n++) {
- struct drm_i915_gem_request *rq = port_request(&el->port[n]);
+ for_each_execlist_port(el, port, n) {
+ struct drm_i915_gem_request *rq = port_request(port);
if (!rq)
break;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4752d71dd644..cfa21731b9c7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -338,24 +338,25 @@ static u64 execlists_update_context(struct
drm_i915_gem_request *rq)
static void execlists_submit_ports(struct intel_engine_cs *engine)
{
- struct execlist_port *port = engine->execlist.port;
- u32 __iomem *elsp =
+ u32 __iomem * const elsp =
engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+ struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port;
unsigned int n;
- for (n = execlist_num_ports(&engine->execlist); n--; ) {
+ for_each_execlist_port_reverse(el, port, n) {
struct drm_i915_gem_request *rq;
unsigned int count;
u64 desc;
- rq = port_unpack(&port[n], &count);
+ rq = port_unpack(port, &count);
if (rq) {
GEM_BUG_ON(count > !n);
if (!count++)
execlists_context_status_change(rq,
INTEL_CONTEXT_SCHEDULE_IN);
- port_set(&port[n], port_pack(rq, count));
+ port_set(port, port_pack(rq, count));
desc = execlists_update_context(rq);
- GEM_DEBUG_EXEC(port[n].context_id =
upper_32_bits(desc));
+ GEM_DEBUG_EXEC(port->context_id = upper_32_bits(desc));
} else {
GEM_BUG_ON(!n);
desc = 0;
@@ -1238,7 +1239,7 @@ static u8 gtiir[] = {
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port;
unsigned int n;
bool submit;
int ret;
@@ -1276,9 +1277,7 @@ static int gen8_init_common_ring(struct intel_engine_cs
*engine)
/* After a GPU reset, we may have requests to replay */
submit = false;
- for (n = 0; n < execlist_num_ports(el); n++) {
-
[Intel-gfx] [PATCH 1/8] drm/i915: Make own struct for execlist items
Engine's execlist related items have been increasing to
a point where a separate struct is warranted. Carve execlist
specific items to a dedicated struct to add clarity.
v2: add kerneldoc and fix whitespace (Joonas, Chris)
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Mika Kuoppala
Acked-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 6 +-
drivers/gpu/drm/i915/i915_gem.c| 16 +++---
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 19 ---
drivers/gpu/drm/i915/i915_irq.c| 5 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++--
drivers/gpu/drm/i915/intel_lrc.c | 64 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 88 +++---
8 files changed, 134 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6338018f655d..cc36409936dc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3344,10 +3344,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port);
idx++) {
+ for (idx = 0; idx < ARRAY_SIZE(engine->execlist.port);
idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlist_port[idx],
+ rq = port_unpack(&engine->execlist.port[idx],
&count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
@@ -3361,7 +3361,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+ for (rb = engine->execlist.first; rb; rb = rb_next(rb))
{
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f445587c1a4b..7d0263e9c220 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2815,8 +2815,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine)
* Turning off the engine->irq_tasklet until the reset is over
* prevents the race.
*/
- tasklet_kill(&engine->irq_tasklet);
- tasklet_disable(&engine->irq_tasklet);
+ tasklet_kill(&engine->execlist.irq_tasklet);
+ tasklet_disable(&engine->execlist.irq_tasklet);
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
@@ -2995,7 +2995,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
{
- tasklet_enable(&engine->irq_tasklet);
+ tasklet_enable(&engine->execlist.irq_tasklet);
kthread_unpark(engine->breadcrumbs.signaler);
}
@@ -3047,17 +3047,17 @@ static void engine_set_wedged(struct intel_engine_cs
*engine)
*/
if (i915.enable_execlists) {
- struct execlist_port *port = engine->execlist_port;
+ struct execlist_port *port = engine->execlist.port;
unsigned long flags;
unsigned int n;
spin_lock_irqsave(&engine->timeline->lock, flags);
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
+ for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
i915_gem_request_put(port_request(&port[n]));
- memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
- engine->execlist_queue = RB_ROOT;
- engine->execlist_first = NULL;
+ memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
+ engine->execlist.queue = RB_ROOT;
+ engine->execlist.first = NULL;
spin_unlock_irqrestore(&engine->timeline->lock, flags);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ed5a1eb839ad..6114bf79219d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1327,10 +1327,10 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct execlist_port *port = engine->execlist_port;
+ const struct execlist_port *port = engine->execlist.port;
unsigned int n;
- for
[Intel-gfx] [PATCH 3/8] drm/i915: Add execlist_port_complete
When first execlist entry is processed, we move the port (contents).
Introduce function for this as execlist, guc and reset handling
use this common operation.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 12 ++--
drivers/gpu/drm/i915/intel_lrc.c | 28 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 14 +-
3 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index f95defe18885..336d22ea5216 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -691,7 +691,7 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
rq->priotree.priority = INT_MAX;
i915_guc_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port, el));
last = rq;
submit = true;
}
@@ -714,20 +714,20 @@ static bool i915_guc_dequeue(struct intel_engine_cs
*engine)
static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
- struct execlist_port *port = engine->execlist.port;
+ struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port = el->port;
struct drm_i915_gem_request *rq;
bool submit;
do {
- rq = port_request(&port[0]);
+ rq = port_request(port);
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
- port[0] = port[1];
- memset(&port[1], 0, sizeof(port[1]));
+ execlist_port_complete(el, port);
- rq = port_request(&port[0]);
+ rq = port_request(port);
}
submit = false;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7dc893806b43..73626dbcef50 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -398,7 +398,8 @@ static void port_assign(struct execlist_port *port,
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *last;
- struct execlist_port *port = engine->execlist.port;
+ struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port = el->port;
struct rb_node *rb;
bool submit = false;
@@ -412,8 +413,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
last->tail = last->wa_tail;
- GEM_BUG_ON(port_isset(&port[1]));
-
/* Hardware submission is through 2 ports. Conceptually each port
* has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
* static for a context, and unique to each, so we only execute
@@ -436,8 +435,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
spin_lock_irq(&engine->timeline->lock);
- rb = engine->execlist.first;
- GEM_BUG_ON(rb_first(&engine->execlist.queue) != rb);
+ rb = el->first;
+ GEM_BUG_ON(rb_first(&el->queue) != rb);
while (rb) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
struct drm_i915_gem_request *rq, *rn;
@@ -460,7 +459,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* combine this request with the last, then we
* are done.
*/
- if (port != engine->execlist.port) {
+ if (port != el->port) {
__list_del_many(&p->requests,
&rq->priotree.link);
goto done;
@@ -485,25 +484,27 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (submit)
port_assign(port, last);
port++;
+
+ GEM_BUG_ON(port_isset(port));
}
INIT_LIST_HEAD(&rq->priotree.link);
rq->priotree.priority = INT_MAX;
__i915_gem_request_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port, el));
last = rq;
submit = true;
}
[Intel-gfx] [PATCH 2/8] drm/i915: Wrap port cancellation into a function
On reset and wedged path, we want to release the requests
that are tied to ports and then mark the ports to be unset.
Introduce a function for this.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/intel_engine_cs.c | 10 ++
drivers/gpu/drm/i915/intel_lrc.c| 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7d0263e9c220..d65f654821cb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3047,17 +3047,14 @@ static void engine_set_wedged(struct intel_engine_cs
*engine)
*/
if (i915.enable_execlists) {
- struct execlist_port *port = engine->execlist.port;
+ struct intel_engine_execlist * const el = &engine->execlist;
unsigned long flags;
- unsigned int n;
spin_lock_irqsave(&engine->timeline->lock, flags);
- for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
- engine->execlist.queue = RB_ROOT;
- engine->execlist.first = NULL;
+ execlist_cancel_port_requests(el);
+ el->queue = RB_ROOT;
+ el->first = NULL;
spin_unlock_irqrestore(&engine->timeline->lock, flags);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6197df0de3fe..192ecc26f432 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1407,6 +1407,16 @@ bool intel_engine_can_store_dword(struct intel_engine_cs
*engine)
}
}
+void execlist_cancel_port_requests(struct intel_engine_execlist * const el)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(el->port); i++)
+ i915_gem_request_put(port_request(&el->port[i]));
+
+ memset(el->port, 0, sizeof(el->port));
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_engine.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2964e7c0a873..7dc893806b43 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1331,7 +1331,6 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
{
struct execlist_port *port = engine->execlist.port;
struct intel_context *ce;
- unsigned int n;
/*
* Catch up with any missed context-switch interrupts.
@@ -1343,9 +1342,7 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
* requests were completed.
*/
if (!request) {
- for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(engine->execlist.port, 0, sizeof(engine->execlist.port));
+ execlist_cancel_port_requests(&engine->execlist);
return;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 326ca1453e91..ae921f916c89 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -493,6 +493,8 @@ struct intel_engine_cs {
u32 (*get_cmd_length_mask)(u32 cmd_header);
};
+void execlist_cancel_port_requests(struct intel_engine_execlist * const el);
+
static inline unsigned int
intel_engine_flag(const struct intel_engine_cs *engine)
{
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4] kms_rotation_crc: 90 degree flip test is not a stress test
On Mon, Sep 11, 2017 at 06:14:57PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> To the best of my recollection the page flipping test was added
> simply to start exercising page flips with 90/270 rotation.
>
> There is no need to do 60 flips which can take quite some time,
> because we do 60 flips against each pipe and each fb geometry.
>
> Also, calling this a stress test is also not matching the
> original idea of the test.
>
> v2:
>
> Several changes:
>
> 1. Remove the stress from the name and reduce the number of
> flips to one only.
>
> 2. Move the page flip before CRC collection for a more useful
> test.
>
> 3. Add more flipping tests, for different rotation and sprite
> planes.
>
> 4. Convert to table driven subtest generation.
>
> v3: Remove extended.testlist from the patch.
>
> v4:
>
> Collect a flip fb crc and check it after flip. This way we test
> not only the flip succeeded but the right image is displayed.
For now it looks like sprite-rotation-X-flip tests are failing
by this assert.
Otherwise:
Reviewed-by: Katarzyna Dec
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Cc: Katarzyna Dec
> Reviewed-by: Chris Wilson (v3)
> ---
> tests/kms_rotation_crc.c | 194
> +--
> 1 file changed, 122 insertions(+), 72 deletions(-)
>
> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
> index 83e37f126f40..21e264addc09 100644
> --- a/tests/kms_rotation_crc.c
> +++ b/tests/kms_rotation_crc.c
> @@ -35,13 +35,14 @@ typedef struct {
> struct igt_fb fb_modeset;
> struct igt_fb fb_flip;
> igt_crc_t ref_crc;
> + igt_crc_t flip_crc;
> igt_pipe_crc_t *pipe_crc;
> igt_rotation_t rotation;
> int pos_x;
> int pos_y;
> uint32_t override_fmt;
> uint64_t override_tiling;
> - unsigned int flip_stress;
> + bool flips;
> } data_t;
>
> static void
> @@ -163,6 +164,7 @@ static void prepare_fbs(data_t *data, igt_output_t
> *output,
> unsigned int w, h, ref_w, ref_h, min_w, min_h;
> uint64_t tiling = data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE;
> uint32_t pixel_format = data->override_fmt ?: DRM_FORMAT_XRGB;
> + const float flip_opacity = 0.75;
>
> if (data->fb.fb_id) {
> igt_plane_set_fb(plane, NULL);
> @@ -219,12 +221,28 @@ static void prepare_fbs(data_t *data, igt_output_t
> *output,
>
> igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling, &data->fb);
>
> - if (data->flip_stress) {
> - igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
> &data->fb_flip);
> - paint_squares(data, IGT_ROTATION_0, &data->fb_flip, 0.92);
> + igt_plane_set_rotation(plane, IGT_ROTATION_0);
> +
> + /*
> + * Create a reference software rotated flip framebuffer.
> + */
> + if (data->flips) {
> + igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
> + &data->fb_flip);
> + paint_squares(data, data->rotation, &data->fb_flip,
> + flip_opacity);
> + igt_plane_set_fb(plane, &data->fb_flip);
> + if (plane->type != DRM_PLANE_TYPE_CURSOR)
> + igt_plane_set_position(plane, data->pos_x, data->pos_y);
> + igt_display_commit2(display,
> + display->is_atomic ?
> + COMMIT_ATOMIC : COMMIT_UNIVERSAL);
> + igt_pipe_crc_collect_crc(data->pipe_crc, &data->flip_crc);
> }
>
> - /* Step 1: create a reference CRC for a software-rotated fb */
> + /*
> + * Create a reference CRC for a software-rotated fb.
> + */
> igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
> data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE,
> &data->fb_reference);
> paint_squares(data, data->rotation, &data->fb_reference, 1.0);
> @@ -232,20 +250,30 @@ static void prepare_fbs(data_t *data, igt_output_t
> *output,
> igt_plane_set_fb(plane, &data->fb_reference);
> if (plane->type != DRM_PLANE_TYPE_CURSOR)
> igt_plane_set_position(plane, data->pos_x, data->pos_y);
> - igt_plane_set_rotation(plane, IGT_ROTATION_0);
> igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC :
> COMMIT_UNIVERSAL);
>
> igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
>
> /*
> - * Step 2: prepare the plane with an non-rotated fb let the hw
> - * rotate it.
> + * Prepare the plane with an non-rotated fb let the hw rotate it.
>*/
> paint_squares(data, IGT_ROTATION_0, &data->fb, 1.0);
> igt_plane_set_fb(plane, &data->fb);
>
> if (plane->type != DRM_PLANE_TYPE_CURSOR)
> igt_plane_set_position(plane, data->pos_x, data->pos_y);
> +
> + /*
> + * Prepare the non-rotated flip fb.
> + */
> + if (data->flips
Re: [Intel-gfx] [PATCH 4/8] drm/i915: Make execlist port count variable
Quoting Mika Kuoppala (2017-09-12 09:36:14)
> static inline void
> execlist_port_complete(struct intel_engine_execlist * const el,
>struct execlist_port * const port)
> {
> - struct execlist_port * const port1 = &el->port[1];
> + const unsigned int m = el->port_mask;
>
> GEM_DEBUG_BUG_ON(port_index(port, el) != 0);
>
> - *port = *port1;
> - memset(port1, 0, sizeof(struct execlist_port));
> + memmove(port, port + 1, m * sizeof(struct execlist_port));
> + memset(port + m, 0, sizeof(struct execlist_port));
Ah I was going to suggest you keep the port[0] = port[1] in the earlier
patch, then remember there will be magic later on. But if we go through
this step, we may as not cut out the meander.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for Support for more than two execlist ports
== Series Details == Series: Support for more than two execlist ports URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Series 30183v1 Support for more than two execlist ports https://patchwork.freedesktop.org/api/1.0/series/30183/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102672 Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:380s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:538s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:269s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:502s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:500s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:452s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:447s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:594s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:408s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:491s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:463s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:486s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:549s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:460s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:504s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:479s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:564s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:421s 3cbfafbde5bb92b6ecdbfd47e189d2742aa6fbec drm-tip: 2017y-09m-11d-23h-04m-21s UTC integration manifest 92a4d479b91f drm/i915: Keep track of reserved execlist ports 68c571c9f0fb drm/i915: Move execlist initialization into intel_engine_cs.c f960067d8174 drm/i915: Introduce execlist_port_* accessors 8378cd04c0e3 drm/i915: Introduce iterators for execlist ports f54ccbc16ae8 drm/i915: Make execlist port count variable 3069386bf94e drm/i915: Add execlist_port_complete ddfca3322990 drm/i915: Wrap port cancellation into a function 809bf696eded drm/i915: Make own struct for execlist items == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5653/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Trybot always warn check
== Series Details == Series: drm/i915: Trybot always warn check URL : https://patchwork.freedesktop.org/series/30170/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 Test kms_cursor_legacy: Subgroup flip-vs-cursor-atomic: fail -> PASS (shard-hsw) fdo#102402 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2301 pass:1237 dwarn:0 dfail:0 fail:12 skip:1052 time:9398s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5651/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 0/2] drm/edid: transparent low-level override/firmware EDIDs
On 09/12/2017 11:19 AM, Jani Nikula wrote: > Patch 1 is v3 of [1]. There are no functional changes to the previous > version, just a rebase and a slight refresh of the commit message and > comments. I think the conclusion from the discussion was that this > should work just fine. At least one user reported this helped with their > audio woes with firmware EDID. > > Patch 2 is an attempt to mitigate the problem of moving the > edid_firmware module parameter from drm_kms_helper to drm. Not sure if > it's too much or too little or just right. Need input here. Pedantically > it should be part of patch 1, but this division should be easier to > grasp in review. > > BR, > Jani. > > > [1] > http://patchwork.freedesktop.org/patch/msgid/1487344854-18777-5-git-send-email-jani.nik...@intel.com > > Cc: Abdiel Janulgue > Cc: Daniel Vetter > Cc: Ville Syrjälä Tested-by: Abdiel Janulgue ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18)
> +execlist_request_port(struct intel_engine_execlist * const el)
> +{
> + GEM_DEBUG_BUG_ON(el->port_count == el->port_mask + 1);
> +
> + el->port_count++;
> +
> + GEM_DEBUG_BUG_ON(port_isset(execlist_port_tail(el)));
> +
> + return execlist_port_tail(el);
> +}
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 0dfb03a0cee4..fdda3a1835ad 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -662,12 +662,19 @@ static void port_assign(struct execlist_port *port,
> static bool i915_guc_dequeue(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlist * const el = &engine->execlist;
> - struct execlist_port *port = execlist_port_head(el);
> - const struct execlist_port * const last_port = execlist_port_tail(el);
> - struct drm_i915_gem_request *last = port_request(port);
> + struct execlist_port *port;
> + struct drm_i915_gem_request *last;
> struct rb_node *rb;
> bool submit = false;
>
> + if (execlist_active_ports(el)) {
> + port = execlist_port_tail(el);
> + last = port_request(port);
> + } else {
> + port = NULL;
> + last = NULL;
> + }
> +
> spin_lock_irq(&engine->timeline->lock);
> rb = el->first;
> GEM_BUG_ON(rb_first(&el->queue) != rb);
> @@ -675,9 +682,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs
> *engine)
> struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> struct drm_i915_gem_request *rq, *rn;
>
> + if (!port)
> + port = execlist_request_port(el);
> +
I can't see port becoming NULL inside the loop, so why can't we do it
during the init above? What did I miss?
-Chris
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18)
> static void execlists_dequeue(struct intel_engine_cs *engine)
> {
> - struct drm_i915_gem_request *last;
> struct intel_engine_execlist * const el = &engine->execlist;
> - struct execlist_port *port = execlist_port_head(el);
> - const struct execlist_port * const last_port = execlist_port_tail(el);
> + struct execlist_port *port;
> + struct drm_i915_gem_request *last;
> struct rb_node *rb;
> bool submit = false;
>
> - last = port_request(port);
> - if (last)
> + if (execlist_active_ports(el)) {
> + port = execlist_port_tail(el);
> + last = port_request(port);
> +
> /* WaIdleLiteRestore:bdw,skl
> * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
> * as we resubmit the request. See gen8_emit_breadcrumb()
> @@ -414,6 +419,10 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> * request.
> */
> last->tail = last->wa_tail;
> + } else {
> + port = NULL;
> + last = NULL;
> + }
>
> /* Hardware submission is through 2 ports. Conceptually each port
> * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
> @@ -443,6 +452,9 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> struct drm_i915_gem_request *rq, *rn;
>
> + if (!port)
> + port = execlist_request_port(el);
> +
> list_for_each_entry_safe(rq, rn, &p->requests, priotree.link)
> {
> /*
> * Can we combine this request with the current port?
> @@ -461,7 +473,7 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> * combine this request with the last, then we
> * are done.
> */
The comment above is now confused, so
/*
* If we are on the last port and cannot combine
* this request with the previous, then we are
* done.
*/
-Chris
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[Intel-gfx] [PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable
Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 11 ++-
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0871807..0dd0e2a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3307,13 +3307,14 @@ static void i9xx_update_primary_plane(struct
intel_plane *primary,
int x = plane_state->main.x;
int y = plane_state->main.y;
unsigned long irqflags;
+ u32 dspaddr_offset;
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
- crtc->dspaddr_offset = plane_state->main.offset;
+ dspaddr_offset = plane_state->main.offset;
else
- crtc->dspaddr_offset = linear_offset;
+ dspaddr_offset = linear_offset;
crtc->adjusted_x = x;
crtc->adjusted_y = y;
@@ -3342,18 +3343,18 @@ static void i9xx_update_primary_plane(struct
intel_plane *primary,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
}
POSTING_READ_FW(reg);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3078076..d58cd10 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -806,7 +806,6 @@ struct intel_crtc {
/* Display surface base address adjustement for pageflips. Note that on
* gen4+ this only adjusts up to a tile, offsets within a tile are
* handled in the hw itself (with the TILEOFF register). */
- u32 dspaddr_offset;
int adjusted_x;
int adjusted_y;
--
2.7.4
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[Intel-gfx] [PATCH 2/3] drm/i915: Unify skylake plane update
Don't handle skylake primary plane separately as it is similar
plane as the others.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/intel_display.c | 85 +---
drivers/gpu/drm/i915/intel_drv.h | 9 ++--
drivers/gpu/drm/i915/intel_fbc.c | 11 +++--
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
5 files changed, 22 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d07d110..24d52d70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1096,6 +1096,14 @@ struct intel_fbc {
int src_w;
int src_h;
bool visible;
+ /*
+* Display surface base address adjustement for
+* pageflips. Note that on gen4+ this only adjusts up
+* to a tile, offsets within a tile are handled in
+* the hw itself (with the TILEOFF register).
+*/
+ int adjusted_x;
+ int adjusted_y;
} plane;
struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0dd0e2a..739003d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3298,7 +3298,6 @@ static void i9xx_update_primary_plane(struct intel_plane
*primary,
const struct intel_plane_state
*plane_state)
{
struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum plane plane = primary->plane;
u32 linear_offset;
@@ -3316,9 +3315,6 @@ static void i9xx_update_primary_plane(struct intel_plane
*primary,
else
dspaddr_offset = linear_offset;
- crtc->adjusted_x = x;
- crtc->adjusted_y = y;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (INTEL_GEN(dev_priv) < 4) {
@@ -3554,83 +3550,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state
*crtc_state,
return plane_ctl;
}
-static void skylake_update_primary_plane(struct intel_plane *plane,
-const struct intel_crtc_state
*crtc_state,
-const struct intel_plane_state
*plane_state)
-{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- enum plane_id plane_id = plane->id;
- enum pipe pipe = plane->pipe;
- u32 plane_ctl = plane_state->ctl;
- unsigned int rotation = plane_state->base.rotation;
- u32 stride = skl_plane_stride(fb, 0, rotation);
- u32 aux_stride = skl_plane_stride(fb, 1, rotation);
- u32 surf_addr = plane_state->main.offset;
- int scaler_id = plane_state->scaler_id;
- int src_x = plane_state->main.x;
- int src_y = plane_state->main.y;
- int src_w = drm_rect_width(&plane_state->base.src) >> 16;
- int src_h = drm_rect_height(&plane_state->base.src) >> 16;
- int dst_x = plane_state->base.dst.x1;
- int dst_y = plane_state->base.dst.y1;
- int dst_w = drm_rect_width(&plane_state->base.dst);
- int dst_h = drm_rect_height(&plane_state->base.dst);
- unsigned long irqflags;
-
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- dst_w--;
- dst_h--;
-
- crtc->dspaddr_offset = surf_addr;
-
- crtc->adjusted_x = src_x;
- crtc->adjusted_y = src_y;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
- I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
- PLANE_COLOR_PIPE_GAMMA_ENABLE |
- PLANE_COLOR_PIPE_CSC_ENABLE |
- PLANE_COLOR_PLANE_GAMMA_DISABLE);
- }
-
- I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
- I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
- I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
- I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->aux.offset - surf_addr) | aux_stride);
- I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->aux.y << 16) | plane_state->aux.x);
-
- if (scaler_id >= 0) {
- uint32_t ps_ctrl = 0;
-
- WARN_ON(!dst_w || !dst_h);
- ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18)
> To further enchance port processing, keep track of
> reserved ports. This way we can iterate only the used subset
> of port space. Note that we lift the responsibility of
> execlists_submit_request() to inspect hw availability and
> always do dequeuing. This is to ensure that only the irq
> handler will be responsible for keeping track of available ports.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 43 ---
> drivers/gpu/drm/i915/i915_irq.c| 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 5 +-
> drivers/gpu/drm/i915/intel_lrc.c | 84
> ++
> drivers/gpu/drm/i915/intel_ringbuffer.h| 50 +-
> 5 files changed, 117 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 0dfb03a0cee4..fdda3a1835ad 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -662,12 +662,19 @@ static void port_assign(struct execlist_port *port,
> static bool i915_guc_dequeue(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlist * const el = &engine->execlist;
> - struct execlist_port *port = execlist_port_head(el);
> - const struct execlist_port * const last_port = execlist_port_tail(el);
> - struct drm_i915_gem_request *last = port_request(port);
> + struct execlist_port *port;
> + struct drm_i915_gem_request *last;
> struct rb_node *rb;
> bool submit = false;
>
> + if (execlist_active_ports(el)) {
> + port = execlist_port_tail(el);
> + last = port_request(port);
> + } else {
> + port = NULL;
> + last = NULL;
> + }
> +
> spin_lock_irq(&engine->timeline->lock);
> rb = el->first;
> GEM_BUG_ON(rb_first(&el->queue) != rb);
> @@ -675,9 +682,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs
> *engine)
> struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> struct drm_i915_gem_request *rq, *rn;
>
> + if (!port)
> + port = execlist_request_port(el);
> +
> list_for_each_entry_safe(rq, rn, &p->requests, priotree.link)
> {
> if (last && rq->ctx != last->ctx) {
> - if (port == last_port) {
> + if (!execlist_inactive_ports(el)) {
> __list_del_many(&p->requests,
> &rq->priotree.link);
> goto done;
> @@ -686,7 +696,8 @@ static bool i915_guc_dequeue(struct intel_engine_cs
> *engine)
> if (submit)
> port_assign(port, last);
>
> - port = execlist_port_next(el, port);
> + port = execlist_request_port(el);
> + GEM_BUG_ON(port_isset(port));
> }
>
> INIT_LIST_HEAD(&rq->priotree.link);
> @@ -717,26 +728,22 @@ static void i915_guc_irq_handler(unsigned long data)
> {
> struct intel_engine_cs * const engine = (struct intel_engine_cs
> *)data;
> struct intel_engine_execlist * const el = &engine->execlist;
> - struct execlist_port *port = execlist_port_head(el);
> - const struct execlist_port * const last_port = execlist_port_tail(el);
> - struct drm_i915_gem_request *rq;
> - bool submit;
>
> do {
> - rq = port_request(port);
> - while (rq && i915_gem_request_completed(rq)) {
> + while (execlist_active_ports(el)) {
> + struct execlist_port *port = execlist_port_head(el);
> + struct drm_i915_gem_request *rq = port_request(port);
> +
> + if (!i915_gem_request_completed(rq))
> + break;
> +
> trace_i915_gem_request_out(rq);
> i915_gem_request_put(rq);
>
> - port = execlist_port_complete(el, port);
> -
> - rq = port_request(port);
> + execlist_release_port(el, port);
> }
>
> - submit = false;
> - if (!port_count(last_port))
> - submit = i915_guc_dequeue(engine);
> - } while (submit);
> + } while (execlist_inactive_ports(el) && i915_guc_dequeue(engine));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1919ac0b7b0f..de4e608786a8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @
[Intel-gfx] [PATCH 0/3] drm/i915: Skylake plane update/disable unifications [v4]
[v4] rebase [v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä) [v2] Fixed missed references which were brough on rebase. /Juha-Pekka Juha-Pekka Heikkila (3): drm/i915: dspaddr_offset doesn't need to be more than local variable drm/i915: Unify skylake plane update drm/i915: Unify skylake plane disable drivers/gpu/drm/i915/i915_drv.h | 8 +++ drivers/gpu/drm/i915/intel_display.c | 117 +++ drivers/gpu/drm/i915/intel_drv.h | 11 ++-- drivers/gpu/drm/i915/intel_fbc.c | 11 +++- drivers/gpu/drm/i915/intel_sprite.c | 4 +- 5 files changed, 32 insertions(+), 119 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Unify skylake plane disable
Don't handle skylake primary plane separately as it is similar
plane as the others.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 21 ++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
3 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 739003d..afead21 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3550,23 +3550,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state
*crtc_state,
return plane_ctl;
}
-static void skylake_disable_primary_plane(struct intel_plane *primary,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
- enum plane_id plane_id = primary->id;
- enum pipe pipe = primary->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
- I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
- I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
- POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
static int
__intel_display_resume(struct drm_device *dev,
struct drm_atomic_state *state,
@@ -13150,7 +13133,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
modifiers = skl_format_modifiers_ccs;
primary->update_plane = skl_update_plane;
- primary->disable_plane = skylake_disable_primary_plane;
+ primary->disable_plane = skl_disable_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13160,7 +13143,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
modifiers = skl_format_modifiers_noccs;
primary->update_plane = skl_update_plane;
- primary->disable_plane = skylake_disable_primary_plane;
+ primary->disable_plane = skl_disable_plane;
} else if (INTEL_GEN(dev_priv) >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a690cc5..a92c2e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1915,6 +1915,7 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state);
void skl_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
/* intel_tv.c */
void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 2ec4108..22598c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -305,7 +305,7 @@ skl_update_plane(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void
+void
skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
--
2.7.4
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18)
> +static inline unsigned int
> +execlist_active_ports(const struct intel_engine_execlist * const el)
> {
> - const unsigned int i = port_index(port, el);
> + return READ_ONCE(el->port_count);
READ_ONCE? Could we separate the racy check from the serialized uses
inside the tasklet where we do want the compiler to go to town?
-Chris
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Increase poll time for BDW FCLK_DONE (rev2)
On Mon, Sep 11, 2017 at 12:15:21PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Increase poll time for BDW FCLK_DONE (rev2) > URL : https://patchwork.freedesktop.org/series/30006/ > State : success Thanks for the patch and review, pushed it to -dinq. For the future please check the preferred multi-line comment format. Fixed this up now while applying. > > == Summary == > > Series 30006v2 drm/i915: Increase poll time for BDW FCLK_DONE > https://patchwork.freedesktop.org/api/1.0/series/30006/revisions/2/mbox/ > > Test kms_cursor_legacy: > Subgroup basic-busy-flip-before-cursor-legacy: > fail -> PASS (fi-snb-2600) fdo#100215 > > fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 > > fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 > time:445s > fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:456s > fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 > time:377s > fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 > time:535s > fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 > time:271s > fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 > time:505s > fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 > time:502s > fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 > time:496s > fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 > time:447s > fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 > time:452s > fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 > time:590s > fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:427s > fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:405s > fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 > time:439s > fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:496s > fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:467s > fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 > time:488s > fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 > time:587s > fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 > time:589s > fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 > time:554s > fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:459s > fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:521s > fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:503s > fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 > time:457s > fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 > time:480s > fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 > time:565s > fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 > time:426s > > b8ed44bfbb7cf1dd40a5b5c15da77053fdc0e0d0 drm-tip: 2017y-09m-11d-11h-22m-27s > UTC integration manifest > 4df9d5006ad9 drm/i915: Increase poll time for BDW FCLK_DONE > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5639/ > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Monday, September 11, 2017 11:51 PM
>To: Shankar, Uma
>Cc: Daniel Vetter ; intel-gfx@lists.freedesktop.org; Srinivas,
>Vidya
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Mon, Sep 11, 2017 at 01:19:15PM +, Shankar, Uma wrote:
>>
>>
>> >-Original Message-
>> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> >Behalf Of Daniel Vetter
>> >Sent: Saturday, September 9, 2017 1:15 AM
>> >To: Ville Syrjälä
>> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>> >
>> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for
>> >gen9 dsi
>> >
>> >On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
>> >> On Fri, Sep 08, 2017 at 05:47:59PM +0300, Ville Syrjälä wrote:
>> >> > On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
>> >> > > From: Uma Shankar
>> >> > >
>> >> > > For gen9 platforms, dsi timings are driven from port instead of
>> >> > > pipe (unlike ddi). Thus, we can't rely on pipe registers to get
>> >> > > the timing information. Even scanline register read will not be
>> >> > > functional.
>> >> > > This is causing vblank evasion logic to fail since it relies on
>> >> > > scanline, causing atomic update failure warnings.
>> >> > >
>> >> > > This patch uses pipe framestamp and current timestamp registers
>> >> > > to calculate scanline. This is an indirect way to get the scanline.
>> >> > > It helps resolve atomic update failure for gen9 dsi platforms.
>> >> > >
>> >> > > Signed-off-by: Uma Shankar
>> >> > > Signed-off-by: Chandra Konduru
>> >> > > Signed-off-by: Vidya Srinivas
>> >> > > ---
>> >> > > drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> >> > > drivers/gpu/drm/i915/i915_irq.c | 5 +
>> >> > > drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> >> > > drivers/gpu/drm/i915/intel_dsi.c | 46
>> >> > >
>> >> > > 4 files changed, 56 insertions(+)
>> >> > >
>> >> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >> > > b/drivers/gpu/drm/i915/i915_drv.h index d07d110..4213b54 100644
>> >> > > --- a/drivers/gpu/drm/i915/i915_drv.h
>> >> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >> > > @@ -4077,6 +4077,8 @@ void intel_sbi_write(struct
>> >> > > drm_i915_private *dev_priv, u16 reg, u32 value,
>> >> > > u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32
>> >> > > reg); void vlv_flisdsi_write(struct drm_i915_private *dev_priv,
>> >> > > u32 reg,
>> >> > > u32 val);
>> >> > >
>> >> > > +u32 bxt_dsi_get_scanline(struct intel_crtc *crtc);
>> >> > > +
>> >> > > /* intel_dpio_phy.c */
>> >> > > void bxt_port_to_phy_channel(struct drm_i915_private
>> >> > > *dev_priv, enum
>> >port port,
>> >> > >enum dpio_phy *phy, enum dpio_channel
>*ch); diff --
>> >git
>> >> > > a/drivers/gpu/drm/i915/i915_irq.c
>> >> > > b/drivers/gpu/drm/i915/i915_irq.c index 5d391e6..31aa7f0 100644
>> >> > > --- a/drivers/gpu/drm/i915/i915_irq.c
>> >> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> >> > > @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct
>> >> > > intel_crtc
>> >*crtc)
>> >> > > struct drm_vblank_crtc *vblank;
>> >> > > enum pipe pipe = crtc->pipe;
>> >> > > int position, vtotal;
>> >> > > + enum transcoder cpu_transcoder;
>> >> > >
>> >> > > if (!crtc->active)
>> >> > > return -1;
>> >> > > @@ -792,6 +793,10 @@ static int
>> >> > > __intel_get_crtc_scanline(struct
>> >intel_crtc *crtc)
>> >> > > if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>> >> > > vtotal /= 2;
>> >> > >
>> >> > > + cpu_transcoder = crtc->config->cpu_transcoder;
>> >> >
>> >> > Humm. Would be nice to be able to do this without adding more
>> >> > crtc->config uses. We're pretty much trying to get rid of that guy.
>> >> >
>> >> > > + if (IS_BROXTON(dev_priv) && transcoder_is_dsi(cpu_transcoder))
>> >> > > + return bxt_dsi_get_scanline(crtc);
>> >> > > +
>> >> > > if (IS_GEN2(dev_priv))
>> >> > > position = I915_READ_FW(PIPEDSL(pipe)) &
>> >DSL_LINEMASK_GEN2;
>> >> > > else
>> >> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >> > > b/drivers/gpu/drm/i915/i915_reg.h index 9a73ea0..54582de 100644
>> >> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> > > @@ -8802,6 +8802,9 @@ enum skl_power_gate {
>> >> > > #define MIPIO_TXESC_CLK_DIV2
> _MMIO(0x160008)
>> >> > > #define GLK_TX_ESC_CLK_DIV2_MASK0x3FF
>> >> > >
>> >> > > +#define BXT_TIMESTAMP_CTR_MMIO(0x44070)
>> >> > > +#define BXT_PIPE_FRMTMSTMP_A _MMIO(0x70048)
>> >> >
>> >> > Please add proper parametrized define that works for all pipes.
>> >>
>> >> Oh, and these shouldn't be called BXT_something. I don't recall
>> >> when they got added to the hardware, but I'm pretty sure it was way
>> >> before BXT came out.
>>
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18)
> @@ -1351,12 +1363,16 @@ static void reset_common_ring(struct intel_engine_cs
> *engine,
> return;
> }
>
> - if (request->ctx != port_request(port)->ctx) {
> - i915_gem_request_put(port_request(port));
> - execlist_port_complete(el, port);
> - }
> + if (execlist_active_ports(el)) {
> + struct execlist_port *port = execlist_port_head(el);
>
> - GEM_BUG_ON(request->ctx != port_request(port)->ctx);
This needs a FIXME at least.
For starters we need to drop requests until the ctx match (i.e. while
(rq->ctx != port_request(port)->ctx)) and then we have the issue that we
may have the same ctx multiple times in an N slot elsp. So
while (rq->ctx != port_rquest(port)->ctx ||
i915_gem_request_completed(port_request(port)))
?
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Re: [Intel-gfx] [PATCH] drm/i915/bxt: set min brightness from VBT
On Tue, 12 Sep 2017, "Lee, Shawn C" wrote:
> Min brightness value from vbt was missing for BXT platform.
> This setting have to refer backlight ic spec to restrict
> min backlight output. Without this restriction, driver would
> allow to configure lower brightness value and violate
> backlight ic requirement.
>
> Fixes: 0fb890c01349 ("drm/i915/bxt: BLC implementation")
> Cc: Jani Nikula
> Cc: Cooper Chiou
> Cc: Gary C Wang
> Signed-off-by: Shawn Lee
Pushed to drm-intel-next-queued, thanks for the patch.
Care to send a similar patch for cnp_setup_backlight, please?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_panel.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index a17b1de7d7e0..d4dd248ac9a8 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1699,6 +1699,8 @@ bxt_setup_backlight(struct intel_connector *connector,
> enum pipe unused)
> if (!panel->backlight.max)
> return -ENODEV;
>
> + panel->backlight.min = get_backlight_min_vbt(connector);
> +
> val = bxt_get_backlight(connector);
> val = intel_panel_compute_brightness(connector, val);
> panel->backlight.level = clamp(val, panel->backlight.min,
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] drm/i915/bxt: set min brightness from VBT
No problem! I will commit a patch for CNP later.
On Tue, 12 Sep 2017, "Lee, Shawn C" wrote:
> Min brightness value from vbt was missing for BXT platform.
> This setting have to refer backlight ic spec to restrict min backlight
> output. Without this restriction, driver would allow to configure
> lower brightness value and violate backlight ic requirement.
>
> Fixes: 0fb890c01349 ("drm/i915/bxt: BLC implementation")
> Cc: Jani Nikula
> Cc: Cooper Chiou
> Cc: Gary C Wang
> Signed-off-by: Shawn Lee
Pushed to drm-intel-next-queued, thanks for the patch.
Care to send a similar patch for cnp_setup_backlight, please?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_panel.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index a17b1de7d7e0..d4dd248ac9a8 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1699,6 +1699,8 @@ bxt_setup_backlight(struct intel_connector *connector,
> enum pipe unused)
> if (!panel->backlight.max)
> return -ENODEV;
>
> + panel->backlight.min = get_backlight_min_vbt(connector);
> +
> val = bxt_get_backlight(connector);
> val = intel_panel_compute_brightness(connector, val);
> panel->backlight.level = clamp(val, panel->backlight.min,
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Skylake plane update/disable unifications [v4]
== Series Details == Series: drm/i915: Skylake plane update/disable unifications [v4] URL : https://patchwork.freedesktop.org/series/30185/ State : warning == Summary == Series 30185v1 drm/i915: Skylake plane update/disable unifications [v4] https://patchwork.freedesktop.org/api/1.0/series/30185/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102672 Test gem_ringfill: Subgroup basic-default: pass -> SKIP (fi-bsw-n3050) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 +1 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-n2820) fdo#101705 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:447s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:377s fi-bsw-n3050 total:289 pass:242 dwarn:0 dfail:0 fail:0 skip:47 time:522s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:269s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:498s fi-byt-n2820 total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:496s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:457s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:451s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:600s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:413s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:469s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:491s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:573s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:584s fi-pnv-d510 total:156 pass:113 dwarn:0 dfail:0 fail:0 skip:42 fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:528s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:464s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:424s 3cbfafbde5bb92b6ecdbfd47e189d2742aa6fbec drm-tip: 2017y-09m-11d-23h-04m-21s UTC integration manifest 5ef8e43e70de drm/i915: Unify skylake plane disable 4e3958f66205 drm/i915: Unify skylake plane update 816933d27463 drm/i915: dspaddr_offset doesn't need to be more than local variable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5654/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Monday, September 11, 2017 11:20 PM
>To: Shankar, Uma
>Cc: Srinivas, Vidya ;
>intel-gfx@lists.freedesktop.org;
>Kahola, Mika ; Kamath, Sunil
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Mon, Sep 11, 2017 at 01:04:18PM +, Shankar, Uma wrote:
>>
>>
>> >-Original Message-
>> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>> >Sent: Friday, September 8, 2017 8:18 PM
>> >To: Srinivas, Vidya
>> >Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika
>> >; Kamath, Sunil ;
>> >Shankar, Uma ; Konduru, Chandra
>> >
>> >Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>> >
>> >On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
>> >> From: Uma Shankar
>> >>
>> >> For gen9 platforms, dsi timings are driven from port instead of
>> >> pipe (unlike ddi). Thus, we can't rely on pipe registers to get the
>> >> timing information. Even scanline register read will not be functional.
>> >> This is causing vblank evasion logic to fail since it relies on
>> >> scanline, causing atomic update failure warnings.
>> >>
>> >> This patch uses pipe framestamp and current timestamp registers to
>> >> calculate scanline. This is an indirect way to get the scanline.
>> >> It helps resolve atomic update failure for gen9 dsi platforms.
>> >>
>> >> Signed-off-by: Uma Shankar
>> >> Signed-off-by: Chandra Konduru
>> >> Signed-off-by: Vidya Srinivas
>> >> ---
>> >> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> >> drivers/gpu/drm/i915/i915_irq.c | 5 +
>> >> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> >> drivers/gpu/drm/i915/intel_dsi.c | 46
>> >>
>> >> 4 files changed, 56 insertions(+)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >> b/drivers/gpu/drm/i915/i915_drv.h index d07d110..4213b54 100644
>> >> --- a/drivers/gpu/drm/i915/i915_drv.h
>> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >> @@ -4077,6 +4077,8 @@ void intel_sbi_write(struct drm_i915_private
>> >> *dev_priv, u16 reg, u32 value,
>> >> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>> >> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg,
>> >> u32 val);
>> >>
>> >> +u32 bxt_dsi_get_scanline(struct intel_crtc *crtc);
>> >> +
>> >> /* intel_dpio_phy.c */
>> >> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv,
>> >> enum port
>> >port,
>> >>enum dpio_phy *phy, enum dpio_channel *ch); diff --
>> >git
>> >> a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> >> index 5d391e6..31aa7f0 100644
>> >> --- a/drivers/gpu/drm/i915/i915_irq.c
>> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> >> @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct
>> >> intel_crtc
>> >*crtc)
>> >> struct drm_vblank_crtc *vblank;
>> >> enum pipe pipe = crtc->pipe;
>> >> int position, vtotal;
>> >> + enum transcoder cpu_transcoder;
>> >>
>> >> if (!crtc->active)
>> >> return -1;
>> >> @@ -792,6 +793,10 @@ static int __intel_get_crtc_scanline(struct
>> >> intel_crtc
>> >*crtc)
>> >> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>> >> vtotal /= 2;
>> >>
>> >> + cpu_transcoder = crtc->config->cpu_transcoder;
>> >
>> >Humm. Would be nice to be able to do this without adding more
>> >crtc->config uses. We're pretty much trying to get rid of that guy.
>> >
>>
>> Will try to find an alternate way to do this.
>>
>> >> + if (IS_BROXTON(dev_priv) && transcoder_is_dsi(cpu_transcoder))
>> >> + return bxt_dsi_get_scanline(crtc);
>> >> +
>> >> if (IS_GEN2(dev_priv))
>> >> position = I915_READ_FW(PIPEDSL(pipe)) &
>> >DSL_LINEMASK_GEN2;
>> >> else
>> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >> b/drivers/gpu/drm/i915/i915_reg.h index 9a73ea0..54582de 100644
>> >> --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> @@ -8802,6 +8802,9 @@ enum skl_power_gate {
>> >> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
>> >> #define GLK_TX_ESC_CLK_DIV2_MASK0x3FF
>> >>
>> >> +#define BXT_TIMESTAMP_CTR_MMIO(0x44070)
>> >> +#define BXT_PIPE_FRMTMSTMP_A _MMIO(0x70048)
>> >
>> >Please add proper parametrized define that works for all pipes.
>> >
>>
>> Will add that.
>>
>> >> +
>> >> /* BXT MIPI clock controls */
>> >> #define BXT_MAX_VAR_OUTPUT_KHZ 39500
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> >> b/drivers/gpu/drm/i915/intel_dsi.c
>> >> index 2a0f5d3..d145ba4 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> >> @@ -1621,6 +1621,52 @@ static int intel_dsi_get_modes(struct
>> >drm_connector *connector)
>> >> return 1;
>> >> }
>> >>
>> >> +/*
>> >> + * For Gen9 DSI, pipe scanline register will not
>> >> + * work to get the scanline since the timings
>>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: transparent low-level override/firmware EDIDs
== Series Details == Series: drm/edid: transparent low-level override/firmware EDIDs URL : https://patchwork.freedesktop.org/series/30182/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test kms_cursor_legacy: Subgroup flip-vs-cursor-atomic: fail -> PASS (shard-hsw) fdo#102402 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402 shard-hswtotal:2301 pass:1236 dwarn:0 dfail:0 fail:13 skip:1052 time:9433s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5652/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v3.
This tests the various parts of atomic that I want to make
interruptible. Running with --debug shows the stats from
__igt_sigiter_continue, which can be used to make sure that
we don't fall over.
The default igt kms helpers use drmIoctl, which is not intercepted
by igt_while_interruptible. Only igt_ioctl is. This means we have
to call the ioctls manually here.
Changes since v1:
- Implement interruptible DPMS checking too.
- Use igt_ioctl + igt_while_interruptible, instead of the signal helper
shotgun.
Changes since v2:
- Bump whitespace to get rid of the weird double } at same indent.
- Use more newlines in the call to the atomic ioctl.
Signed-off-by: Maarten Lankhorst
Cc: Daniel Stone
Acked-by: Daniel Vetter
---
lib/igt_kms.c| 3 +-
lib/igt_kms.h| 1 +
tests/Makefile.sources | 1 +
tests/kms_atomic_interruptible.c | 323 +++
4 files changed, 327 insertions(+), 1 deletion(-)
create mode 100644 tests/kms_atomic_interruptible.c
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 72fde792ba89..7bcafc072f70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
"scaling mode",
- "CRTC_ID"
+ "CRTC_ID",
+ "DPMS"
};
/*
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index e5dc329b161e..3d1061fa08c8 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
enum igt_atomic_connector_properties {
IGT_CONNECTOR_SCALING_MODE = 0,
IGT_CONNECTOR_CRTC_ID,
+ IGT_CONNECTOR_DPMS,
IGT_NUM_CONNECTOR_PROPS
};
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0f4e39af10a1..cf542df181a8 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -172,6 +172,7 @@ TESTS_progs = \
kms_3d \
kms_addfb_basic \
kms_atomic \
+ kms_atomic_interruptible \
kms_atomic_transition \
kms_busy \
kms_ccs \
diff --git a/tests/kms_atomic_interruptible.c b/tests/kms_atomic_interruptible.c
new file mode 100644
index ..dcc60f1c654a
--- /dev/null
+++ b/tests/kms_atomic_interruptible.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include "sw_sync.h"
+
+enum plane_test_type
+{
+ test_legacy_modeset,
+ test_atomic_modeset,
+ test_legacy_dpms,
+ test_setplane,
+ test_setcursor,
+ test_pageflip
+};
+
+static int block_plane(igt_display_t *display, igt_output_t *output, enum
plane_test_type test_type, igt_plane_t *plane)
+{
+ int timeline = sw_sync_timeline_create();
+
+ igt_fork(child, 1) {
+ /* Ignore the signal helper, we need to block indefinitely on
the fence. */
+ signal(SIGCONT, SIG_IGN);
+
+ if (test_type == test_legacy_modeset || test_type ==
test_atomic_modeset) {
+ igt_output_set_pipe(output, PIPE_NONE);
+ igt_plane_set_fb(plane, NULL);
+ }
+ igt_plane_set_fence_fd(plane,
sw_sync_timeline_create_fence(timeline, 1));
+
+ igt_display_commit2(display, COMMIT_ATOMIC);
+ }
+
+ return timeline;
+}
+
+static void unblock(int block)
+{
+ sw_sync_timeline_inc(block, 1);
+ close(block);
+}
+
+static void ev_page_flip(int fd, unsigned seq, unsigned tv_sec, unsigned
tv_usec, void *user_data)
+{
+ igt_debug("Retrieved vblank seq: %u on unk\n", seq);
+}
+
+static drmEventContext drm_events = {
+ .version = 2,
+ .page_flip_handler = ev_page_flip
+};
+
+static void run_plane_test(igt_display_t *display, enum pipe pipe,
igt_output_t *output,
+
Re: [Intel-gfx] [PATCH] Revert "drm/i915/bxt: Disable device ready before shutdown command"
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Vidya Srinivas
> Sent: Tuesday, September 5, 2017 3:15 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srinivas, Vidya
> Subject: [Intel-gfx] [PATCH] Revert "drm/i915/bxt: Disable device ready
> before shutdown command"
>
> From: Uma Shankar
>
> This reverts commit bbdf0b2ff32aa75c7bd167569130e9391d2e6282.
>
> Disable device ready before shutdown command was added previously to
> avoid a split screen issue seen on dual link DSI panels. As of now, dual link
> is
> not supported and will need some rework in the upstream code. For single
> link DSI panels, the change is not required. This will cause failure in
> sending
> SHUTDOWN packet during disable. Hence reverting the change. Will handle
> the change as part of dual link enabling in upstream.
Already there are lot of changes wrt to DSI dual link inside intel_dsi.c.
Can't we keep this change as well under the condition if (dual_link &&
Broxton)??
Might help to fetch dual link changes in future instead of losing it.
Regards,
Madhav
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Vidya Srinivas
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 11 ---
> 1 file changed, 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 2a0f5d3..fc25d7d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -892,8 +892,6 @@ static void intel_dsi_disable(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state
> *old_conn_state) {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
>
> @@ -903,15 +901,6 @@ static void intel_dsi_disable(struct intel_encoder
> *encoder,
> intel_panel_disable_backlight(old_conn_state);
>
> /*
> - * Disable Device ready before the port shutdown in order
> - * to avoid split screen
> - */
> - if (IS_BROXTON(dev_priv)) {
> - for_each_dsi_port(port, intel_dsi->ports)
> - I915_WRITE(MIPI_DEVICE_READY(port), 0);
> - }
> -
> - /*
>* According to the spec we should send SHUTDOWN before
>* MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
>* has shown that the v3 sequence works for v2 VBTs too
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v3.
Quoting Maarten Lankhorst (2017-09-12 10:57:13)
> This tests the various parts of atomic that I want to make
> interruptible. Running with --debug shows the stats from
> __igt_sigiter_continue, which can be used to make sure that
> we don't fall over.
>
> The default igt kms helpers use drmIoctl, which is not intercepted
> by igt_while_interruptible. Only igt_ioctl is. This means we have
> to call the ioctls manually here.
>
> Changes since v1:
> - Implement interruptible DPMS checking too.
> - Use igt_ioctl + igt_while_interruptible, instead of the signal helper
> shotgun.
> Changes since v2:
> - Bump whitespace to get rid of the weird double } at same indent.
> - Use more newlines in the call to the atomic ioctl.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Daniel Stone
> Acked-by: Daniel Vetter
> ---
> lib/igt_kms.c| 3 +-
> lib/igt_kms.h| 1 +
> tests/Makefile.sources | 1 +
> tests/kms_atomic_interruptible.c | 323
> +++
> 4 files changed, 327 insertions(+), 1 deletion(-)
> create mode 100644 tests/kms_atomic_interruptible.c
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 72fde792ba89..7bcafc072f70 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
>
> const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> "scaling mode",
> - "CRTC_ID"
> + "CRTC_ID",
> + "DPMS"
> };
>
> /*
> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> index e5dc329b161e..3d1061fa08c8 100644
> --- a/lib/igt_kms.h
> +++ b/lib/igt_kms.h
> @@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
> enum igt_atomic_connector_properties {
> IGT_CONNECTOR_SCALING_MODE = 0,
> IGT_CONNECTOR_CRTC_ID,
> + IGT_CONNECTOR_DPMS,
> IGT_NUM_CONNECTOR_PROPS
> };
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0f4e39af10a1..cf542df181a8 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -172,6 +172,7 @@ TESTS_progs = \
> kms_3d \
> kms_addfb_basic \
> kms_atomic \
> + kms_atomic_interruptible \
> kms_atomic_transition \
> kms_busy \
> kms_ccs \
> diff --git a/tests/kms_atomic_interruptible.c
> b/tests/kms_atomic_interruptible.c
> new file mode 100644
> index ..dcc60f1c654a
> --- /dev/null
> +++ b/tests/kms_atomic_interruptible.c
> @@ -0,0 +1,323 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include "sw_sync.h"
> +
> +enum plane_test_type
> +{
> + test_legacy_modeset,
> + test_atomic_modeset,
> + test_legacy_dpms,
> + test_setplane,
> + test_setcursor,
> + test_pageflip
> +};
> +
> +static int block_plane(igt_display_t *display, igt_output_t *output, enum
> plane_test_type test_type, igt_plane_t *plane)
> +{
> + int timeline = sw_sync_timeline_create();
> +
> + igt_fork(child, 1) {
> + /* Ignore the signal helper, we need to block indefinitely on
> the fence. */
> + signal(SIGCONT, SIG_IGN);
> +
> + if (test_type == test_legacy_modeset || test_type ==
> test_atomic_modeset) {
> + igt_output_set_pipe(output, PIPE_NONE);
> + igt_plane_set_fb(plane, NULL);
> + }
> + igt_plane_set_fence_fd(plane,
> sw_sync_timeline_create_fence(timeline, 1));
Does igt_plane_set_fence_fd() consume the fd? If it does, that's nasty,
but if it doesn't we have a leak.
From my inspection, igt_plane_set_fence_fd creates a private copy of the
fence fd, and doesn't bother to check if it was successful
> +
> + ig
Re: [Intel-gfx] [PATCH 1/8] drm/i915: Make own struct for execlist items
Quoting Mika Kuoppala (2017-09-12 09:36:11) > Engine's execlist related items have been increasing to > a point where a separate struct is warranted. Carve execlist > specific items to a dedicated struct to add clarity. > > v2: add kerneldoc and fix whitespace (Joonas, Chris) > > Suggested-by: Chris Wilson > Cc: Chris Wilson > Cc: Joonas Lahtinen > Signed-off-by: Mika Kuoppala > Acked-by: Joonas Lahtinen Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/8] drm/i915: Wrap port cancellation into a function
Quoting Mika Kuoppala (2017-09-12 09:36:12) > On reset and wedged path, we want to release the requests > that are tied to ports and then mark the ports to be unset. > Introduce a function for this. > > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915: Add execlist_port_complete
Quoting Mika Kuoppala (2017-09-12 09:36:13)
> @@ -412,8 +413,6 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> */
> last->tail = last->wa_tail;
>
> - GEM_BUG_ON(port_isset(&port[1]));
* Raises eyebrow
> -
> /* Hardware submission is through 2 ports. Conceptually each port
> * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
> * static for a context, and unique to each, so we only execute
> @@ -485,25 +484,27 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> if (submit)
> port_assign(port, last);
> port++;
> +
> + GEM_BUG_ON(port_isset(port));
* and relax
You had me worried there, but that looks like a neat generalisation.
> @@ -495,6 +495,18 @@ struct intel_engine_cs {
>
> void execlist_cancel_port_requests(struct intel_engine_execlist * const el);
>
> +static inline void
> +execlist_port_complete(struct intel_engine_execlist * const el,
> + struct execlist_port * const port)
> +{
> + struct execlist_port * const port1 = &el->port[1];
> +
> + GEM_DEBUG_BUG_ON(port_index(port, el) != 0);
Just GEM_BUG_ON().
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 4/8] drm/i915: Make execlist port count variable
Quoting Mika Kuoppala (2017-09-12 09:36:14) > GuC can handle more than two submission ports. I know why you want this, but this is a little too wishy-washy. Something along the lines, "As we emulate execlists on top of the GuC workqueue, it is not restricted to just 2 ports and we can increase that number arbitrarily to trade-off queue depth (i.e. scheduling latency) against pipeline bubbles." Not that we have any evidence to suggest we need more than 2 ports ;) > Make port count variable to prepare supporting more than 2 ports. > > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Chris Wilson writes:
> Quoting Mika Kuoppala (2017-09-12 09:36:18)
>> +execlist_request_port(struct intel_engine_execlist * const el)
>> +{
>> + GEM_DEBUG_BUG_ON(el->port_count == el->port_mask + 1);
>> +
>> + el->port_count++;
>> +
>> + GEM_DEBUG_BUG_ON(port_isset(execlist_port_tail(el)));
>> +
>> + return execlist_port_tail(el);
>> +}
>>
>> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
>> b/drivers/gpu/drm/i915/i915_guc_submission.c
>> index 0dfb03a0cee4..fdda3a1835ad 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
>> @@ -662,12 +662,19 @@ static void port_assign(struct execlist_port *port,
>> static bool i915_guc_dequeue(struct intel_engine_cs *engine)
>> {
>> struct intel_engine_execlist * const el = &engine->execlist;
>> - struct execlist_port *port = execlist_port_head(el);
>> - const struct execlist_port * const last_port =
>> execlist_port_tail(el);
>> - struct drm_i915_gem_request *last = port_request(port);
>> + struct execlist_port *port;
>> + struct drm_i915_gem_request *last;
>> struct rb_node *rb;
>> bool submit = false;
>>
>> + if (execlist_active_ports(el)) {
>> + port = execlist_port_tail(el);
>> + last = port_request(port);
>> + } else {
>> + port = NULL;
>> + last = NULL;
>> + }
>> +
>> spin_lock_irq(&engine->timeline->lock);
>> rb = el->first;
>> GEM_BUG_ON(rb_first(&el->queue) != rb);
>> @@ -675,9 +682,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs
>> *engine)
>> struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
>> struct drm_i915_gem_request *rq, *rn;
>>
>> + if (!port)
>> + port = execlist_request_port(el);
>> +
>
> I can't see port becoming NULL inside the loop, so why can't we do it
> during the init above? What did I miss?
Hmm this might have warranted a comment. I wanted to avoid requesting
a port if there is nothing to dequeue, that is why it inside while (rb).
We could allocate early and let the port linger if nothing to dequeue,
but then the GEM_DEBUG's need to be relaxed more.
-Mika
> -Chris
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Re: [Intel-gfx] [PATCH 5/8] drm/i915: Introduce iterators for execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:15)
> Switch to iterators for execlist_port access. This is
> a preparation for indexing ports from arbitrary location. Which
> in turn allows us to handle ports in ring like fashion.
>
> Signed-off-by: Mika Kuoppala
Something we want to keep an eye as we switch to these macros is code
generation. As a quick guide, check object size, i.e. run
scripts/bloat-o-meter.
> -static inline unsigned int
> -execlist_num_ports(const struct intel_engine_execlist * const el)
> -{
> - return el->port_mask + 1;
> -}
> +/* Iterators over elsp ports */
> +#define __port_idx(start, i, m) (((start) + (i)) & (m))
> +
> +#define for_each_execlist_port(el__, port__, n__) \
> + for ((n__) = 0; \
> +(port__) = &(el__)->port[__port_idx(0, (n__),
> (el__)->port_mask)], (n__) < (el__)->port_mask + 1; \
> +(n__)++)
Using (n__) is misleading. It can't be anything other than a lhv (i.e.
plain variable and not an expr). checkpatch can complain all it wants.
Probably should keep execlist_num_ports() for another patch.
That x < y + 1 just keeps on triggering me everytime I see it.
> +
> +#define for_each_execlist_port_reverse(el__, port__, n__) \
> + for ((n__) = (el__)->port_mask + 1; \
> +(port__) = &(el__)->port[__port_idx((el__)->port_mask, (n__),
> (el__)->port_mask)], (n__)--;)
>
> static inline void
> execlist_port_complete(struct intel_engine_execlist * const el,
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Chris Wilson writes:
> Quoting Mika Kuoppala (2017-09-12 09:36:18)
>> +static inline unsigned int
>> +execlist_active_ports(const struct intel_engine_execlist * const el)
>> {
>> - const unsigned int i = port_index(port, el);
>> + return READ_ONCE(el->port_count);
>
> READ_ONCE? Could we separate the racy check from the serialized uses
> inside the tasklet where we do want the compiler to go to town?
Hmm so substitute execlist_active_ports() in i915_irq.c with
READ_ONCE(el->port_count) and remove it in this function?
-Mika
> -Chris
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Re: [Intel-gfx] [PATCH 6/8] drm/i915: Introduce execlist_port_* accessors
Quoting Mika Kuoppala (2017-09-12 09:36:16)
> Instead of trusting that first available port is at index 0,
> use accessor to hide this. This allows us to just move the head
> on port completion instead of memmoving the array.
Ah. Even after a re-read, I wasn't expecting to see the advance in this
path. "This allows" is too passive, sounds like you are describing a
future optimisation.
> -static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
> +static bool execlists_elsp_ready(struct intel_engine_execlist * const el)
> {
> - const struct execlist_port *port = engine->execlist.port;
> + struct execlist_port * const port = execlist_port_head(el);
For readability
struct execlist_port * const port0 = execlist_port_head(el);
struct execlist_port * const port1 = execlist_port_next(el, port0);
> - return port_count(&port[0]) + port_count(&port[1]) < 2;
> + return port_count(port) + port_count(execlist_port_next(el, port)) <
> 2;
return port_count(port0) + port_count(port1) < 2;
-Chris
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Re: [Intel-gfx] [PATCH 5/8] drm/i915: Introduce iterators for execlist ports
Chris Wilson writes:
> Quoting Mika Kuoppala (2017-09-12 09:36:15)
>> Switch to iterators for execlist_port access. This is
>> a preparation for indexing ports from arbitrary location. Which
>> in turn allows us to handle ports in ring like fashion.
>>
>> Signed-off-by: Mika Kuoppala
>
> Something we want to keep an eye as we switch to these macros is code
> generation. As a quick guide, check object size, i.e. run
> scripts/bloat-o-meter.
>
>> -static inline unsigned int
>> -execlist_num_ports(const struct intel_engine_execlist * const el)
>> -{
>> - return el->port_mask + 1;
>> -}
>> +/* Iterators over elsp ports */
>> +#define __port_idx(start, i, m) (((start) + (i)) & (m))
>> +
>> +#define for_each_execlist_port(el__, port__, n__) \
>> + for ((n__) = 0; \
>> +(port__) = &(el__)->port[__port_idx(0, (n__),
>> (el__)->port_mask)], (n__) < (el__)->port_mask + 1; \
>> +(n__)++)
>
> Using (n__) is misleading. It can't be anything other than a lhv (i.e.
> plain variable and not an expr). checkpatch can complain all it wants.
>
> Probably should keep execlist_num_ports() for another patch.
> That x < y + 1 just keeps on triggering me everytime I see it.
There is only a once callsite per macro if I recall right. We could
just drop these macros and live happier life as no-one really is a fan.
-Mika
>
>> +
>> +#define for_each_execlist_port_reverse(el__, port__, n__) \
>> + for ((n__) = (el__)->port_mask + 1; \
>> +(port__) = &(el__)->port[__port_idx((el__)->port_mask, (n__),
>> (el__)->port_mask)], (n__)--;)
>>
>> static inline void
>> execlist_port_complete(struct intel_engine_execlist * const el,
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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Move execlist initialization into intel_engine_cs.c
Quoting Mika Kuoppala (2017-09-12 09:36:17) > Move execlist init into a common engine setup. As it is > common to both guc and hw execlists. "Move execlist init into the commone engine setup for simplicity. At present, it is split between the common setup and lrc for no real reason. As we always inspect the execlists for debugging, we should make sure that it is always initialised (and empty at start). Plus now that we have a common substruct for execlists, having a common initialiser makes our setup more self-descriptive." > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson I would bump this to just after introduction of struct engine->execlist -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skylake plane update/disable unifications [v4]
== Series Details == Series: drm/i915: Skylake plane update/disable unifications [v4] URL : https://patchwork.freedesktop.org/series/30185/ State : success == Summary == Series 30185v1 drm/i915: Skylake plane update/disable unifications [v4] https://patchwork.freedesktop.org/api/1.0/series/30185/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> FAIL (fi-skl-6700k) fdo#100367 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:374s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:533s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:269s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:504s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:496s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:450s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:454s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:594s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:479s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:555s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:454s fi-skl-6700k total:289 pass:264 dwarn:0 dfail:0 fail:1 skip:24 time:514s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:454s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:466s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:425s fi-bdw-gvtdvm failed to connect after reboot 694f07d3df18c02da3f526ae0e1238eb12534e1e drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest cf8eed1a327c drm/i915: Unify skylake plane disable 1fd6d5a0a554 drm/i915: Unify skylake plane update 442d1197df5f drm/i915: dspaddr_offset doesn't need to be more than local variable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5655/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 09:36:18) > To further enchance port processing, keep track of > reserved ports. This way we can iterate only the used subset > of port space. Note that we lift the responsibility of > execlists_submit_request() to inspect hw availability and > always do dequeuing. This is to ensure that only the irq > handler will be responsible for keeping track of available ports. Hmm, gut feeling is that tracking the tail instead of count is more intuitive, especially for dequeue. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Support for more than two execlist ports
== Series Details == Series: Support for more than two execlist ports URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Test kms_cursor_legacy: Subgroup flip-vs-cursor-atomic: fail -> PASS (shard-hsw) fdo#102402 fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402 shard-hswtotal:2301 pass:1237 dwarn:0 dfail:0 fail:12 skip:1052 time:9452s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5653/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 11:27:53)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2017-09-12 09:36:18)
> >> +execlist_request_port(struct intel_engine_execlist * const el)
> >> +{
> >> + GEM_DEBUG_BUG_ON(el->port_count == el->port_mask + 1);
> >> +
> >> + el->port_count++;
> >> +
> >> + GEM_DEBUG_BUG_ON(port_isset(execlist_port_tail(el)));
> >> +
> >> + return execlist_port_tail(el);
> >> +}
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> >> b/drivers/gpu/drm/i915/i915_guc_submission.c
> >> index 0dfb03a0cee4..fdda3a1835ad 100644
> >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> >> @@ -662,12 +662,19 @@ static void port_assign(struct execlist_port *port,
> >> static bool i915_guc_dequeue(struct intel_engine_cs *engine)
> >> {
> >> struct intel_engine_execlist * const el = &engine->execlist;
> >> - struct execlist_port *port = execlist_port_head(el);
> >> - const struct execlist_port * const last_port =
> >> execlist_port_tail(el);
> >> - struct drm_i915_gem_request *last = port_request(port);
> >> + struct execlist_port *port;
> >> + struct drm_i915_gem_request *last;
> >> struct rb_node *rb;
> >> bool submit = false;
> >>
> >> + if (execlist_active_ports(el)) {
> >> + port = execlist_port_tail(el);
> >> + last = port_request(port);
> >> + } else {
> >> + port = NULL;
> >> + last = NULL;
> >> + }
> >> +
> >> spin_lock_irq(&engine->timeline->lock);
> >> rb = el->first;
> >> GEM_BUG_ON(rb_first(&el->queue) != rb);
> >> @@ -675,9 +682,12 @@ static bool i915_guc_dequeue(struct intel_engine_cs
> >> *engine)
> >> struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> >> struct drm_i915_gem_request *rq, *rn;
> >>
> >> + if (!port)
> >> + port = execlist_request_port(el);
> >> +
> >
> > I can't see port becoming NULL inside the loop, so why can't we do it
> > during the init above? What did I miss?
>
> Hmm this might have warranted a comment. I wanted to avoid requesting
> a port if there is nothing to dequeue, that is why it inside while (rb).
> We could allocate early and let the port linger if nothing to dequeue,
> but then the GEM_DEBUG's need to be relaxed more.
Ah, that's where only advancing at the end comes into play. Would also
help not to call it request_port... Or just not hiding the mechanics.
-Chris
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep track of reserved execlist ports
Quoting Mika Kuoppala (2017-09-12 11:29:48)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2017-09-12 09:36:18)
> >> +static inline unsigned int
> >> +execlist_active_ports(const struct intel_engine_execlist * const el)
> >> {
> >> - const unsigned int i = port_index(port, el);
> >> + return READ_ONCE(el->port_count);
> >
> > READ_ONCE? Could we separate the racy check from the serialized uses
> > inside the tasklet where we do want the compiler to go to town?
>
> Hmm so substitute execlist_active_ports() in i915_irq.c with
> READ_ONCE(el->port_count) and remove it in this function?
The elsp_ready outside of the tasklet also need to take special care (or
at least document that they are outside of the serialized section).
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests: Add kms_atomic_interruptible test, v3.
== Series Details == Series: tests: Add kms_atomic_interruptible test, v3. URL : https://patchwork.freedesktop.org/series/30187/ State : success == Summary == IGT patchset tested on top of latest successful build f9e0154630766b63617c64255a68e5129e233a4b igt/gem_evict_(alignment,everything): Limit to low 4G with latest DRM-Tip kernel build CI_DRM_3077 694f07d3df18 drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest Test chamelium: Subgroup dp-crc-fast: fail -> PASS (fi-kbl-7500u) fdo#102514 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:446s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:382s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:538s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:270s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:514s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:512s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:501s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:449s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:447s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:600s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:432s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:417s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:442s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:491s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:556s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:464s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:488s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:580s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:424s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_173/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v3.
Op 12-09-17 om 12:09 schreef Chris Wilson:
> Quoting Maarten Lankhorst (2017-09-12 10:57:13)
>> This tests the various parts of atomic that I want to make
>> interruptible. Running with --debug shows the stats from
>> __igt_sigiter_continue, which can be used to make sure that
>> we don't fall over.
>>
>> The default igt kms helpers use drmIoctl, which is not intercepted
>> by igt_while_interruptible. Only igt_ioctl is. This means we have
>> to call the ioctls manually here.
>>
>> Changes since v1:
>> - Implement interruptible DPMS checking too.
>> - Use igt_ioctl + igt_while_interruptible, instead of the signal helper
>> shotgun.
>> Changes since v2:
>> - Bump whitespace to get rid of the weird double } at same indent.
>> - Use more newlines in the call to the atomic ioctl.
>>
>> Signed-off-by: Maarten Lankhorst
>> Cc: Daniel Stone
>> Acked-by: Daniel Vetter
>> ---
>> lib/igt_kms.c| 3 +-
>> lib/igt_kms.h| 1 +
>> tests/Makefile.sources | 1 +
>> tests/kms_atomic_interruptible.c | 323
>> +++
>> 4 files changed, 327 insertions(+), 1 deletion(-)
>> create mode 100644 tests/kms_atomic_interruptible.c
>>
>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
>> index 72fde792ba89..7bcafc072f70 100644
>> --- a/lib/igt_kms.c
>> +++ b/lib/igt_kms.c
>> @@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
>>
>> const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
>> "scaling mode",
>> - "CRTC_ID"
>> + "CRTC_ID",
>> + "DPMS"
>> };
>>
>> /*
>> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
>> index e5dc329b161e..3d1061fa08c8 100644
>> --- a/lib/igt_kms.h
>> +++ b/lib/igt_kms.h
>> @@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
>> enum igt_atomic_connector_properties {
>> IGT_CONNECTOR_SCALING_MODE = 0,
>> IGT_CONNECTOR_CRTC_ID,
>> + IGT_CONNECTOR_DPMS,
>> IGT_NUM_CONNECTOR_PROPS
>> };
>>
>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>> index 0f4e39af10a1..cf542df181a8 100644
>> --- a/tests/Makefile.sources
>> +++ b/tests/Makefile.sources
>> @@ -172,6 +172,7 @@ TESTS_progs = \
>> kms_3d \
>> kms_addfb_basic \
>> kms_atomic \
>> + kms_atomic_interruptible \
>> kms_atomic_transition \
>> kms_busy \
>> kms_ccs \
>> diff --git a/tests/kms_atomic_interruptible.c
>> b/tests/kms_atomic_interruptible.c
>> new file mode 100644
>> index ..dcc60f1c654a
>> --- /dev/null
>> +++ b/tests/kms_atomic_interruptible.c
>> @@ -0,0 +1,323 @@
>> +/*
>> + * Copyright © 2016 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "igt.h"
>> +#include "drmtest.h"
>> +#include "sw_sync.h"
>> +
>> +enum plane_test_type
>> +{
>> + test_legacy_modeset,
>> + test_atomic_modeset,
>> + test_legacy_dpms,
>> + test_setplane,
>> + test_setcursor,
>> + test_pageflip
>> +};
>> +
>> +static int block_plane(igt_display_t *display, igt_output_t *output, enum
>> plane_test_type test_type, igt_plane_t *plane)
>> +{
>> + int timeline = sw_sync_timeline_create();
>> +
>> + igt_fork(child, 1) {
>> + /* Ignore the signal helper, we need to block indefinitely
>> on the fence. */
>> + signal(SIGCONT, SIG_IGN);
>> +
>> + if (test_type == test_legacy_modeset || test_type ==
>> test_atomic_modeset) {
>> + igt_output_set_pipe(output, PIPE_NONE);
>> + igt_plane_set_fb(plane, NULL);
>> + }
>> + igt_plane_set_fence_fd(plane,
>> sw_sync_timeline_create_fence(timeline, 1));
> Does igt_plane_set_fence_fd() consume the fd? If it does, that's nasty,
> but if it d
Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update
On Fri, Sep 08, 2017 at 09:48:17AM -0700, Belgaumkar, Vinay wrote:
[SNIP]
> > > >
> > > > + /* Checks if we achieve boost using gem_wait */
> > >
> > > We should mention this is doing gem_wait on a spinning batch, hence the
> > > boost.
> > I think that additional information is not needed here. I got 2 reasons:
> > - we assume that subtest comment will be oneliner
> > - do we need such details here?
>
> This current form gives the idea that we can get turbo boost by simply doing
> a gem_wait, which is incorrect. We either say "Checks if we can achieve
> boost" or then give the complete info - "Checks if we can achieve boost
> using gem_wait on a spinning batch". Either ways, it is still single line.
Yes, the request needs to be incomplete to grant boost.
No, stating that we're granting boost on spinning batches is confusing because
of terminology overload (spinbatch is a specific type of GPU load that we're
using).
-Michał
>
> >
> > Thanks,
> > Kasia
> > >
> > > Other than this and the above comment, LGTM.
> > >
> > > Acked-by: Vinay Belgaumkar
> > >
> > >
> > > > igt_subtest("waitboost")
> > > > waitboost(drm_fd, false);
> > > >
> > > > + /* Test boost frequency after GPU reset */
> > > > igt_subtest("reset") {
> > > > igt_hang_t hang = igt_allow_hang(drm_fd, 0, 0);
> > > > waitboost(drm_fd, true);
> > > >
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[Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v4.
This tests the various parts of atomic that I want to make
interruptible. Running with --debug shows the stats from
__igt_sigiter_continue, which can be used to make sure that
we don't fall over.
The default igt kms helpers use drmIoctl, which is not intercepted
by igt_while_interruptible. Only igt_ioctl is. This means we have
to call the ioctls manually here.
Changes since v1:
- Implement interruptible DPMS checking too.
- Use igt_ioctl + igt_while_interruptible, instead of the signal helper
shotgun.
Changes since v2:
- Bump whitespace to get rid of the weird double } at same indent.
- Use more newlines in the call to the atomic ioctl.
Changes since v3:
- Fix copyright on year. (Adrinael)
- Use do_ioctl instead of do_or_die(igt_ioctl) (ickle).
- Add test description. (Adrinael)
Signed-off-by: Maarten Lankhorst
Cc: Daniel Stone
Acked-by: Daniel Vetter
---
lib/igt_kms.c| 3 +-
lib/igt_kms.h| 1 +
tests/Makefile.sources | 1 +
tests/kms_atomic_interruptible.c | 325 +++
4 files changed, 329 insertions(+), 1 deletion(-)
create mode 100644 tests/kms_atomic_interruptible.c
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 72fde792ba89..7bcafc072f70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
"scaling mode",
- "CRTC_ID"
+ "CRTC_ID",
+ "DPMS"
};
/*
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index e5dc329b161e..3d1061fa08c8 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
enum igt_atomic_connector_properties {
IGT_CONNECTOR_SCALING_MODE = 0,
IGT_CONNECTOR_CRTC_ID,
+ IGT_CONNECTOR_DPMS,
IGT_NUM_CONNECTOR_PROPS
};
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0f4e39af10a1..cf542df181a8 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -172,6 +172,7 @@ TESTS_progs = \
kms_3d \
kms_addfb_basic \
kms_atomic \
+ kms_atomic_interruptible \
kms_atomic_transition \
kms_busy \
kms_ccs \
diff --git a/tests/kms_atomic_interruptible.c b/tests/kms_atomic_interruptible.c
new file mode 100644
index ..4e39019c72de
--- /dev/null
+++ b/tests/kms_atomic_interruptible.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Tests that interrupt various atomic ioctls.");
+
+enum plane_test_type
+{
+ test_legacy_modeset,
+ test_atomic_modeset,
+ test_legacy_dpms,
+ test_setplane,
+ test_setcursor,
+ test_pageflip
+};
+
+static int block_plane(igt_display_t *display, igt_output_t *output, enum
plane_test_type test_type, igt_plane_t *plane)
+{
+ int timeline = sw_sync_timeline_create();
+
+ igt_fork(child, 1) {
+ /* Ignore the signal helper, we need to block indefinitely on
the fence. */
+ signal(SIGCONT, SIG_IGN);
+
+ if (test_type == test_legacy_modeset || test_type ==
test_atomic_modeset) {
+ igt_output_set_pipe(output, PIPE_NONE);
+ igt_plane_set_fb(plane, NULL);
+ }
+ igt_plane_set_fence_fd(plane,
sw_sync_timeline_create_fence(timeline, 1));
+
+ igt_display_commit2(display, COMMIT_ATOMIC);
+ }
+
+ return timeline;
+}
+
+static void unblock(int block)
+{
+ sw_sync_timeline_inc(block, 1);
+ close(block);
+}
+
+static void ev_page_flip(int fd, unsigned seq, unsigned tv_sec, unsigned
tv_usec, void *user_data)
+{
+ igt_debug("Retrieved vblank seq: %u on unk
Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update
On Thu, Sep 07, 2017 at 02:15:14PM +0200, Katarzyna Dec wrote:
> Added comments in tricky places for better feature understanding.
> Added IGT_TEST_DESCRIPTION and short description for non-obvious
> subtests.
> Changed name of 'magic' checkit() function to something meaningfull.
> Changed junk struct and stuff array names.
> Made some minor coding style changes.
>
> Cc: Vinay Belgaumkar
> Cc: Petri Latvala
> Cc: Arkadiusz Hiler
> Cc: Daniel Vetter
>
> Signed-off: Katarzyna Dec
LGTM. I especially like changing the identifiers for more
self-explanatory forms.
Acked-by: Petri Latvala
> ---
> tests/pm_rps.c | 108
> ++---
> 1 file changed, 64 insertions(+), 44 deletions(-)
>
> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
> index e79f0ea7..1eeb6c6a 100644
> --- a/tests/pm_rps.c
> +++ b/tests/pm_rps.c
> @@ -40,6 +40,8 @@
>
> #include "intel_bufmgr.h"
>
> +IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
> +
> static int drm_fd;
>
> static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
> @@ -56,12 +58,19 @@ enum {
>
> static int origfreqs[NUMFREQ];
>
> -struct junk {
> +struct sysfs_file {
> const char *name;
> const char *mode;
> FILE *filp;
> -} stuff[] = {
> - { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, {
> "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { "boost",
> "rb+", NULL }, { NULL, NULL, NULL }
> +} sysfs_files[] = {
> + { "cur", "r", NULL },
> + { "min", "rb+", NULL },
> + { "max", "rb+", NULL },
> + { "RP0", "r", NULL },
> + { "RP1", "r", NULL },
> + { "RPn", "r", NULL },
> + { "boost", "rb+", NULL },
> + { NULL, NULL, NULL }
> };
>
> static int readval(FILE *filp)
> @@ -81,7 +90,7 @@ static void read_freqs(int *freqs)
> int i;
>
> for (i = 0; i < NUMFREQ; i++)
> - freqs[i] = readval(stuff[i].filp);
> + freqs[i] = readval(sysfs_files[i].filp);
> }
>
> static void nsleep(unsigned long ns)
> @@ -143,7 +152,7 @@ static int do_writeval(FILE *filp, int val, int lerrno,
> bool readback_check)
> #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL, true)
> #define writeval_nocheck(filp, val) do_writeval(filp, val, 0, false)
>
> -static void checkit(const int *freqs)
> +static void check_freq_constraints(const int *freqs)
> {
> igt_assert_lte(freqs[MIN], freqs[MAX]);
> igt_assert_lte(freqs[CUR], freqs[MAX]);
> @@ -162,7 +171,7 @@ static void dump(const int *freqs)
>
> igt_debug("gt freq (MHz):");
> for (i = 0; i < NUMFREQ; i++)
> - igt_debug(" %s=%d", stuff[i].name, freqs[i]);
> + igt_debug(" %s=%d", sysfs_files[i].name, freqs[i]);
>
> igt_debug("\n");
> }
> @@ -387,14 +396,18 @@ static int get_hw_rounded_freq(int target)
> idx = MAX;
>
> old_freq = freqs[idx];
> - writeval_nocheck(stuff[idx].filp, target);
> + writeval_nocheck(sysfs_files[idx].filp, target);
> read_freqs(freqs);
> ret = freqs[idx];
> - writeval_nocheck(stuff[idx].filp, old_freq);
> + writeval_nocheck(sysfs_files[idx].filp, old_freq);
>
> return ret;
> }
>
> +/*
> + * Modify softlimit MIN and MAX freqs to valid and invalid levels. Depending
> + * on subtest run different check after each modification.
> + */
> static void min_max_config(void (*check)(void), bool load_gpu)
> {
> int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
> @@ -411,78 +424,78 @@ static void min_max_config(void (*check)(void), bool
> load_gpu)
> check();
>
> igt_debug("\nSet min=RPn and max=RP0...\n");
> - writeval(stuff[MIN].filp, origfreqs[RPn]);
> - writeval(stuff[MAX].filp, origfreqs[RP0]);
> + writeval(sysfs_files[MIN].filp, origfreqs[RPn]);
> + writeval(sysfs_files[MAX].filp, origfreqs[RP0]);
> if (load_gpu)
> do_load_gpu();
> check();
>
> igt_debug("\nIncrease min to midpoint...\n");
> - writeval(stuff[MIN].filp, fmid);
> + writeval(sysfs_files[MIN].filp, fmid);
> if (load_gpu)
> do_load_gpu();
> check();
>
> igt_debug("\nIncrease min to RP0...\n");
> - writeval(stuff[MIN].filp, origfreqs[RP0]);
> + writeval(sysfs_files[MIN].filp, origfreqs[RP0]);
> if (load_gpu)
> do_load_gpu();
> check();
>
> igt_debug("\nIncrease min above RP0 (invalid)...\n");
> - writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
> + writeval_inval(sysfs_files[MIN].filp, origfreqs[RP0] + 1000);
> check();
>
> igt_debug("\nDecrease max to RPn (invalid)...\n");
> - writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
> + writeval_inval(sysfs_files[MAX].filp, origfreqs[RPn]);
> check();
>
> igt_debug("\nDecrease min to midpoint...\n");
> - writeval(stuff[MIN].filp, fmid);
> +
[Intel-gfx] ✓ Fi.CI.BAT: success for tests: Add kms_atomic_interruptible test, v4.
== Series Details == Series: tests: Add kms_atomic_interruptible test, v4. URL : https://patchwork.freedesktop.org/series/30193/ State : success == Summary == IGT patchset tested on top of latest successful build f9e0154630766b63617c64255a68e5129e233a4b igt/gem_evict_(alignment,everything): Limit to low 4G with latest DRM-Tip kernel build CI_DRM_3077 694f07d3df18 drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest Test kms_flip: Subgroup basic-flip-vs-modeset: skip -> PASS (fi-skl-x1585l) fdo#101781 fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:379s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:532s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:274s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:519s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:505s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:457s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:458s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:599s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:435s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:495s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:470s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:487s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:584s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:548s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:457s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:523s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:511s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s fi-skl-x1585ltotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:508s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:581s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:428s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_174/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update
On Thu, Sep 07, 2017 at 02:15:14PM +0200, Katarzyna Dec wrote: > Added comments in tricky places for better feature understanding. > Added IGT_TEST_DESCRIPTION and short description for non-obvious > subtests. > Changed name of 'magic' checkit() function to something meaningfull. > Changed junk struct and stuff array names. > Made some minor coding style changes. > > Cc: Vinay Belgaumkar > Cc: Petri Latvala > Cc: Arkadiusz Hiler > Cc: Daniel Vetter > > Signed-off: Katarzyna Dec Gathered all Acks here and pushed, as there is no use in further bikesheeding the wording ;-) It can be fine-tuned in the following patches if it proves necessary anyway. Even if it's not perfect it makes pm_rps a really good, real-world example how things should look like. Thanks for the patch and the reviews! -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v4.
On Tue, Sep 12, 2017 at 01:27:30PM +0200, Maarten Lankhorst wrote:
> This tests the various parts of atomic that I want to make
> interruptible. Running with --debug shows the stats from
> __igt_sigiter_continue, which can be used to make sure that
> we don't fall over.
>
> The default igt kms helpers use drmIoctl, which is not intercepted
> by igt_while_interruptible. Only igt_ioctl is. This means we have
> to call the ioctls manually here.
>
> Changes since v1:
> - Implement interruptible DPMS checking too.
> - Use igt_ioctl + igt_while_interruptible, instead of the signal helper
> shotgun.
> Changes since v2:
> - Bump whitespace to get rid of the weird double } at same indent.
> - Use more newlines in the call to the atomic ioctl.
> Changes since v3:
> - Fix copyright on year. (Adrinael)
> - Use do_ioctl instead of do_or_die(igt_ioctl) (ickle).
> - Add test description. (Adrinael)
>
> Signed-off-by: Maarten Lankhorst
> Cc: Daniel Stone
> Acked-by: Daniel Vetter
I'd still prefer the sleep() calls to have their number selection
documented to avoid cases like the number hunting Marta had to do for
the fbc bug, but meh. Either way,
Reviewed-by: Petri Latvala
> ---
> lib/igt_kms.c| 3 +-
> lib/igt_kms.h| 1 +
> tests/Makefile.sources | 1 +
> tests/kms_atomic_interruptible.c | 325
> +++
> 4 files changed, 329 insertions(+), 1 deletion(-)
> create mode 100644 tests/kms_atomic_interruptible.c
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 72fde792ba89..7bcafc072f70 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
>
> const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> "scaling mode",
> - "CRTC_ID"
> + "CRTC_ID",
> + "DPMS"
> };
>
> /*
> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> index e5dc329b161e..3d1061fa08c8 100644
> --- a/lib/igt_kms.h
> +++ b/lib/igt_kms.h
> @@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
> enum igt_atomic_connector_properties {
> IGT_CONNECTOR_SCALING_MODE = 0,
> IGT_CONNECTOR_CRTC_ID,
> + IGT_CONNECTOR_DPMS,
> IGT_NUM_CONNECTOR_PROPS
> };
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0f4e39af10a1..cf542df181a8 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -172,6 +172,7 @@ TESTS_progs = \
> kms_3d \
> kms_addfb_basic \
> kms_atomic \
> + kms_atomic_interruptible \
> kms_atomic_transition \
> kms_busy \
> kms_ccs \
> diff --git a/tests/kms_atomic_interruptible.c
> b/tests/kms_atomic_interruptible.c
> new file mode 100644
> index ..4e39019c72de
> --- /dev/null
> +++ b/tests/kms_atomic_interruptible.c
> @@ -0,0 +1,325 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include "sw_sync.h"
> +
> +IGT_TEST_DESCRIPTION("Tests that interrupt various atomic ioctls.");
> +
> +enum plane_test_type
> +{
> + test_legacy_modeset,
> + test_atomic_modeset,
> + test_legacy_dpms,
> + test_setplane,
> + test_setcursor,
> + test_pageflip
> +};
> +
> +static int block_plane(igt_display_t *display, igt_output_t *output, enum
> plane_test_type test_type, igt_plane_t *plane)
> +{
> + int timeline = sw_sync_timeline_create();
> +
> + igt_fork(child, 1) {
> + /* Ignore the signal helper, we need to block indefinitely on
> the fence. */
> + signal(SIGCONT, SIG_IGN);
> +
> + if (test_type == test_legacy_modeset || test_type ==
> test_atomic_modeset) {
> + igt_output_set_pipe(output, PIPE_NONE);
> + igt_plane
[Intel-gfx] ✓ Fi.CI.BAT: success for igt/sw_sync: Fix up close(timeline) tests for unsignaled fences
== Series Details == Series: igt/sw_sync: Fix up close(timeline) tests for unsignaled fences URL : https://patchwork.freedesktop.org/series/30126/ State : success == Summary == IGT patchset tested on top of latest successful build 1c6e20deb30e4fc059183f1cf3f832b500b89464 pm_rps: [RFC] RPS tests documentation update with latest DRM-Tip kernel build CI_DRM_3077 694f07d3df18 drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest Test chamelium: Subgroup dp-crc-fast: fail -> PASS (fi-kbl-7500u) fdo#102514 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:377s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:538s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:508s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:501s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:459s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:460s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:597s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:429s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:412s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:493s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:460s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:493s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:594s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:554s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:464s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:525s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:509s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:461s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:489s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:572s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:432s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_175/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] igt/sw_sync: Fix up close(timeline) tests for unsignaled fences
On Mon, Sep 11, 2017 at 01:35:10PM +0100, Chris Wilson wrote: > Following > > kernel commit ea4d5a270b57fa8d4871f372ca9b97b7697fdfda > Author: Dominik Behr > Date: Thu Sep 7 16:02:46 2017 -0300 > > dma-buf/sw_sync: force signal all unsignaled fences on dying timeline > > To avoid hanging userspace components that might have been waiting on the > active fences of the destroyed timeline we need to signal with error all > remaining fences on such timeline. > > This restore the default behaviour of the Android sw_sync framework, which > Android still relies on. It was broken on the dma fence conversion a few > years ago and never fixed. > > unsignaled fences are now signaled and flagged with ENOENT when the > timeline is closed. Fixup timeline_closed_signaled to match. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102650 > Signed-off-by: Chris Wilson Reviewed-by: Michał Winiarski -Michał > --- > tests/sw_sync.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/tests/sw_sync.c b/tests/sw_sync.c > index 946592e8..20dfbbb9 100644 > --- a/tests/sw_sync.c > +++ b/tests/sw_sync.c > @@ -82,8 +82,10 @@ static void test_timeline_closed(void) > fence = sw_sync_timeline_create_fence(timeline, 1); > > close(timeline); > - igt_assert_f(sync_fence_wait(fence, 0) == -ETIME, > + igt_assert_f(sync_fence_wait(fence, 0) == 0, >"Failure waiting on unsignaled fence on closed > timeline\n"); > + igt_assert_f(sync_fence_status(fence) == -ENOENT, > + "Failure in marking up an unsignaled fence on closed > timeline\n"); > } > > static void test_timeline_closed_signaled(void) > -- > 2.14.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Disable DMC powersaving during GT operations
The DMC typifies the worst example of firmware: it overrides system behaviour and is fubar. When no displays are active, the DMC appears to continually toggle its control register trying to change display power states. This in turn has the side effect of slowing down the GT by a few orders of magntidue, making headless operations intolerably slow. This seems to affect all machines with dmc (so a byproduct of the dmc code itself being shared) and severely limits throughput on the CI bxt and triggers the watchdog for incomplete tests. Altenative suggestion is to blacklist all DMC firmware until it is fixed. References: https://bugs.freedesktop.org/show_bug.cgi?id=100572 Testcase: igt/gem_exec_nop/headless Suggested-by: Tvrtko Ursulin Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Imre Deak --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ drivers/gpu/drm/i915/i915_gem_request.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ba72a4bdaa78..e3236c1d44f0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3331,6 +3331,9 @@ i915_gem_idle_work_handler(struct work_struct *work) intel_engines_mark_idle(dev_priv); i915_gem_timelines_mark_idle(dev_priv); + if (dev_priv->csr.dmc_payload) + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); + GEM_BUG_ON(!dev_priv->gt.awake); dev_priv->gt.awake = false; rearm_hangcheck = false; diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 813a3b546d6e..3c8ebdb5b0b4 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915) intel_runtime_pm_get_noresume(i915); i915->gt.awake = true; + if (i915->csr.dmc_payload) + intel_display_power_get(i915, POWER_DOMAIN_MODESET); + intel_enable_gt_powersave(i915); i915_update_gfx_val(i915); if (INTEL_GEN(i915) >= 6) -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] eb-uninit
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 0cd6869c8fc3..91c2830acac1 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -681,7 +681,7 @@ static int eb_select_context(struct i915_execbuffer *eb)
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
- struct drm_i915_gem_object *uninitialized_var(obj);
+ struct drm_i915_gem_object *obj;
unsigned int i;
int err;
@@ -727,19 +727,17 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
goto err_obj;
}
+ /* transfer ref to ctx */
vma->open_count++;
list_add(&lut->obj_link, &obj->lut_list);
list_add(&lut->ctx_link, &eb->ctx->handles_list);
lut->ctx = eb->ctx;
lut->handle = handle;
- /* transfer ref to ctx */
- obj = NULL;
-
add_vma:
err = eb_add_vma(eb, i, vma);
if (unlikely(err))
- goto err_obj;
+ goto err_vma;
GEM_BUG_ON(vma != eb->vma[i]);
GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
@@ -768,8 +766,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
return eb_reserve(eb);
err_obj:
- if (obj)
- i915_gem_object_put(obj);
+ i915_gem_object_put(obj);
err_vma:
eb->vma[i] = NULL;
return err;
--
2.14.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable DMC powersaving during GT operations
On 12/09/2017 13:37, Chris Wilson wrote: The DMC typifies the worst example of firmware: it overrides system behaviour and is fubar. When no displays are active, the DMC appears to continually toggle its control register trying to change display power states. This in turn has the side effect of slowing down the GT by a few orders of magntidue, making headless operations intolerably slow. This seems to affect all machines with dmc (so a byproduct of the dmc code itself being shared) and severely limits throughput on the CI bxt and triggers the watchdog for incomplete tests. Altenative suggestion is to blacklist all DMC firmware until it is fixed. I've sent this as https://patchwork.freedesktop.org/patch/154942/ some time ago. You asked for a long code comment back then. :) Anyway, I don't mind we merge one of the two since it is taking an eternity to get this fixes in the firmware. So: Reviewed-by: Tvrtko Ursulin Regards, Tvrtko References: https://bugs.freedesktop.org/show_bug.cgi?id=100572 Testcase: igt/gem_exec_nop/headless Suggested-by: Tvrtko Ursulin Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Imre Deak --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ drivers/gpu/drm/i915/i915_gem_request.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ba72a4bdaa78..e3236c1d44f0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3331,6 +3331,9 @@ i915_gem_idle_work_handler(struct work_struct *work) intel_engines_mark_idle(dev_priv); i915_gem_timelines_mark_idle(dev_priv); + if (dev_priv->csr.dmc_payload) + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); + GEM_BUG_ON(!dev_priv->gt.awake); dev_priv->gt.awake = false; rearm_hangcheck = false; diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 813a3b546d6e..3c8ebdb5b0b4 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915) intel_runtime_pm_get_noresume(i915); i915->gt.awake = true; + if (i915->csr.dmc_payload) + intel_display_power_get(i915, POWER_DOMAIN_MODESET); + intel_enable_gt_powersave(i915); i915_update_gfx_val(i915); if (INTEL_GEN(i915) >= 6) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/6] drm/atomic: Interruptible locks for everyone!
drm_atomic_commit could previous have always failed when waits failed, but locking was always done uninterruptibly. Add infrastructure to make it possible for callers to choose interruptible locking, and convert the 5 most common ioctl's to use it. All other atomic helpers can be converted when additional tests are added to kms_atomic_interruptible. Changes since last version: - Small fixes to the preparation patch - Convert setcrtc as well. Maarten Lankhorst (6): drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible waiting, v2. drm/atomic: Convert atomic ioctl locking to interruptible. drm/legacy: Convert cursor ioctl locking to interruptible. drm/legacy: Convert setplane ioctl locking to interruptible. drm/atomic: Convert pageflip ioctl locking to interruptible. drm/crtc: Convert setcrtc ioctl locking to interruptible. drivers/gpu/drm/drm_atomic.c | 7 +-- drivers/gpu/drm/drm_crtc.c | 7 +-- drivers/gpu/drm/drm_debugfs_crc.c | 2 +- drivers/gpu/drm/drm_modeset_lock.c | 96 +++--- drivers/gpu/drm/drm_plane.c| 21 + include/drm/drm_modeset_lock.h | 12 +++-- 6 files changed, 77 insertions(+), 68 deletions(-) -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/6] drm/legacy: Convert cursor ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_plane.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 7a00351d5b5d..eef58595101c 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -834,7 +834,7 @@ static int drm_mode_cursor_common(struct drm_device *dev,
return -ENOENT;
}
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock(&crtc->mutex, &ctx);
if (ret)
@@ -876,8 +876,9 @@ static int drm_mode_cursor_common(struct drm_device *dev,
}
out:
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
--
2.14.1
___
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[Intel-gfx] [PATCH v2 4/6] drm/legacy: Convert setplane ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_plane.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index eef58595101c..803d67c22da2 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -667,7 +667,7 @@ static int setplane_internal(struct drm_plane *plane,
struct drm_modeset_acquire_ctx ctx;
int ret;
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock_all_ctx(plane->dev, &ctx);
if (ret)
@@ -678,8 +678,9 @@ static int setplane_internal(struct drm_plane *plane,
fail:
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
--
2.14.1
___
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[Intel-gfx] [PATCH v2 2/6] drm/atomic: Convert atomic ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and
handle drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 75f5f74de9bf..366c56fe5f58 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -2234,7 +2234,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
(arg->flags & DRM_MODE_PAGE_FLIP_EVENT))
return -EINVAL;
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
state = drm_atomic_state_alloc(dev);
if (!state)
@@ -2347,8 +2347,9 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
if (ret == -EDEADLK) {
drm_atomic_state_clear(state);
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_atomic_state_put(state);
--
2.14.1
___
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[Intel-gfx] [PATCH v2 5/6] drm/atomic: Convert pageflip ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_plane.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 803d67c22da2..72cba9805edc 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -987,7 +987,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
return -EINVAL;
}
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock(&crtc->mutex, &ctx);
if (ret)
@@ -1076,8 +1076,9 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
crtc->primary->old_fb = NULL;
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
--
2.14.1
___
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Re: [Intel-gfx] [PATCH] drm/i915: Disable DMC powersaving during GT operations
Quoting Chris Wilson (2017-09-12 13:37:32) > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c > b/drivers/gpu/drm/i915/i915_gem_request.c > index 813a3b546d6e..3c8ebdb5b0b4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_request.c > +++ b/drivers/gpu/drm/i915/i915_gem_request.c > @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915) > intel_runtime_pm_get_noresume(i915); > i915->gt.awake = true; > /* * The DMC doesn't behave well when it is active (i.e the system is * idle). It continually tries to toggle DC_STATE_EN causing a * severe slow down of the rest of the system (severe enough to trigger * watchdogs and reboot the machine under CI testing). * * Known affected firmware: * - skl_dmc_ver1_26.bin * - bxt_dmc_ver1_07.bin */ > + if (i915->csr.dmc_payload) > + intel_display_power_get(i915, POWER_DOMAIN_MODESET); > + ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/6] drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible waiting, v2.
When we want to make drm_atomic_commit interruptible, there are a lot of
places that call the lock function, which we don't have control over.
Rather than trying to convert every single one, it's easier to toggle
interruptible waiting per acquire_ctx. If drm_modeset_acquire_init is
called with DRM_MODESET_ACQUIRE_INTERRUPTIBLE, then we will perform
interruptible waits in drm_modeset_lock and drm_modeset_backoff.
Changes since v1:
- Fix locking example in drm_modeset_lock.c to be compatible
with interruptible waiting (xexaxo) and make it default.
Uninterruptible waiting shouldn't happen except in corner cases,
but the example will still apply if the flag is removed.
- Add drm_modeset_lock_single_interruptible() to documentation.
- Fix dead link to removed drm_modeset_lock_interruptible() in
drm_modeset_lock().
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter #v1
Cc: Emil Velikov
---
drivers/gpu/drm/drm_debugfs_crc.c | 2 +-
drivers/gpu/drm/drm_modeset_lock.c | 96 +++---
include/drm/drm_modeset_lock.h | 12 +++--
3 files changed, 57 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs_crc.c
b/drivers/gpu/drm/drm_debugfs_crc.c
index f9e26dda56d6..9dd879589a2c 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -155,7 +155,7 @@ static int crtc_crc_open(struct inode *inode, struct file
*filep)
int ret = 0;
if (drm_drv_uses_atomic_modeset(crtc->dev)) {
- ret = drm_modeset_lock_interruptible(&crtc->mutex, NULL);
+ ret = drm_modeset_lock_single_interruptible(&crtc->mutex);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/drm_modeset_lock.c
b/drivers/gpu/drm/drm_modeset_lock.c
index af4e906c630d..e123497da0ca 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -39,23 +39,28 @@
*
* The basic usage pattern is to::
*
- * drm_modeset_acquire_init(&ctx)
+ * drm_modeset_acquire_init(ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
* retry:
* foreach (lock in random_ordered_set_of_locks) {
- * ret = drm_modeset_lock(lock, &ctx)
+ * ret = drm_modeset_lock(lock, ctx)
* if (ret == -EDEADLK) {
- * drm_modeset_backoff(&ctx);
- * goto retry;
+ * ret = drm_modeset_backoff(ctx);
+ * if (!ret)
+ * goto retry;
* }
+ * if (ret)
+ * goto out;
* }
* ... do stuff ...
- * drm_modeset_drop_locks(&ctx);
- * drm_modeset_acquire_fini(&ctx);
+ * out:
+ * drm_modeset_drop_locks(ctx);
+ * drm_modeset_acquire_fini(ctx);
*
* If all that is needed is a single modeset lock, then the &struct
* drm_modeset_acquire_ctx is not needed and the locking can be simplified
- * by passing a NULL instead of ctx in the drm_modeset_lock()
- * call and, when done, by calling drm_modeset_unlock().
+ * by passing a NULL instead of ctx in the drm_modeset_lock() call or
+ * calling drm_modeset_lock_single_interruptible(). To unlock afterwards
+ * call drm_modeset_unlock().
*
* On top of these per-object locks using &ww_mutex there's also an overall
* &drm_mode_config.mutex, for protecting everything else. Mostly this means
@@ -178,7 +183,11 @@ EXPORT_SYMBOL(drm_warn_on_modeset_not_all_locked);
/**
* drm_modeset_acquire_init - initialize acquire context
* @ctx: the acquire context
- * @flags: for future
+ * @flags: 0 or %DRM_MODESET_ACQUIRE_INTERRUPTIBLE
+ *
+ * When passing %DRM_MODESET_ACQUIRE_INTERRUPTIBLE to @flags,
+ * all calls to drm_modeset_lock() will perform an interruptible
+ * wait.
*/
void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
uint32_t flags)
@@ -186,6 +195,9 @@ void drm_modeset_acquire_init(struct
drm_modeset_acquire_ctx *ctx,
memset(ctx, 0, sizeof(*ctx));
ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
INIT_LIST_HEAD(&ctx->locked);
+
+ if (flags & DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
+ ctx->interruptible = true;
}
EXPORT_SYMBOL(drm_modeset_acquire_init);
@@ -261,8 +273,19 @@ static inline int modeset_lock(struct drm_modeset_lock
*lock,
return ret;
}
-static int modeset_backoff(struct drm_modeset_acquire_ctx *ctx,
- bool interruptible)
+/**
+ * drm_modeset_backoff - deadlock avoidance backoff
+ * @ctx: the acquire context
+ *
+ * If deadlock is detected (ie. drm_modeset_lock() returns -EDEADLK),
+ * you must call this function to drop all currently held locks and
+ * block until the contended lock becomes available.
+ *
+ * This function returns 0 on success, or -ERESTARTSYS if this context
+ * is initialized with %DRM_MODESET_ACQUIRE_INTERRUPTIBLE and the
+ * wait has been interrupted.
+ */
+int drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
{
struct drm_modeset_lock *contended = ctx->co
[Intel-gfx] [PATCH v2 6/6] drm/crtc: Convert setcrtc ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_crtc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 5af25ce5bf7c..68b4e976d5e0 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -577,7 +577,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
mutex_lock(&crtc->dev->mode_config.mutex);
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock_all_ctx(crtc->dev, &ctx);
if (ret)
@@ -717,8 +717,9 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
kfree(connector_set);
drm_mode_destroy(dev, mode);
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
--
2.14.1
___
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[Intel-gfx] [PATCH 2/4] drm/i915/guc: Submit GuC workitems containing coalesced requests
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition). This allows us to completely
remove the reservation, replacing it with a compile time check.
v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)
v4: Squash removing wq_resv
References: https://bugs.freedesktop.org/show_bug.cgi?id=101873
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Jeff McGee
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 -
drivers/gpu/drm/i915/i915_guc_submission.c | 179 ++---
drivers/gpu/drm/i915/intel_lrc.c | 25 +---
drivers/gpu/drm/i915/intel_uc.h| 11 --
4 files changed, 62 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6338018f655d..f5fd00cfb3b0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2450,8 +2450,6 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
- seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
tot += submissions;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 8a550785b257..6f0adcd2a058 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -406,63 +406,6 @@ static void guc_stage_desc_fini(struct intel_guc *guc,
memset(desc, 0, sizeof(*desc));
}
-/**
- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
- * @request: request associated with the commands
- *
- * Return: 0 if space is available
- * -EAGAIN if space is not currently available
- *
- * This function must be called (and must return 0) before a request
- * is submitted to the GuC via i915_guc_submit() below. Once a result
- * of 0 has been returned, it must be balanced by a corresponding
- * call to submit().
- *
- * Reservation allows the caller to determine in advance that space
- * will be available for the next submission before committing resources
- * to it, and helps avoid late failures with complicated recovery paths.
- */
-int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
-{
- const size_t wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
- struct guc_process_desc *desc = __get_process_desc(client);
- u32 freespace;
- int ret;
-
- spin_lock_irq(&client->wq_lock);
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- freespace -= client->wq_rsvd;
- if (likely(freespace >= wqi_size)) {
- client->wq_rsvd += wqi_size;
- ret = 0;
- } else {
- client->no_wq_space++;
- ret = -EAGAIN;
- }
- spin_unlock_irq(&client->wq_lock);
-
- return ret;
-}
-
-static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&client->wq_lock, flags);
- client->wq_rsvd += size;
- spin_unlock_irqrestore(&client->wq_lock, flags);
-}
-
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
-{
- const int wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
-
- GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
- guc_client_update_wq_rsvd(client, -wqi_size);
-}
-
/* Construct a Work Item and append it to the GuC's Work Queue */
static void guc_wq_item_append(struct i915_guc_client *client,
struct drm_i915_gem_request *rq)
@@ -475,7 +418,7 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct guc_wq_item *wqi;
u32 freespace, tail, wq_off;
- /* Free space is guaranteed, see i915_guc_wq_reserve() above */
+ /* Free space is guaranteed */
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
GEM_BUG_ON(freespace < wqi_size);
@@ -491,14 +434,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
* workqueue buffer dw by dw.
*/
BUILD_BUG_ON(wqi_size != 16);
- GEM_BUG_ON(client->wq_rsvd < wqi_size);
/* postincrement WQ tail for next time */
[Intel-gfx] [PATCH 1/4] drm/i915/guc: Remove obsolete comments and remove unused variable
Originally removed in:
c1adab970348 ("drm/i915/guc: Remove failed doorbell stat from debugfs")
f1448a62a103 ("drm/i915/guc: Remove last submission result from debugfs")
Were accidentaly restored in:
925344ccc91d ("BackMerge tag 'v4.12-rc5' into drm-next")
We can also remove unused variable and replace it with a WARN.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 +--
drivers/gpu/drm/i915/intel_uc.h| 4
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e9349a2c..8a550785b257 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -602,7 +602,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
struct intel_guc *guc = &rq->i915->guc;
struct i915_guc_client *client = guc->execbuf_client;
unsigned long flags;
- int b_ret;
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
@@ -611,7 +610,7 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
spin_lock_irqsave(&client->wq_lock, flags);
guc_wq_item_append(client, rq);
- b_ret = guc_ring_doorbell(client);
+ WARN_ON(guc_ring_doorbell(client));
client->submissions[engine_id] += 1;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b17b0f..69daf4c01cd0 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -59,10 +59,6 @@ struct drm_i915_gem_request;
*available in the work queue (note, the queue is shared,
*not per-engine). It is OK for this to be nonzero, but
*it should not be huge!
- * b_fail: failed to ring the doorbell. This should never happen, unless
- * somehow the hardware misbehaves, or maybe if the GuC firmware
- * crashes? We probably need to reset the GPU to recover.
- * retcode: errno from last guc_submit()
*/
struct i915_guc_client {
struct i915_vma *vma;
--
2.13.5
___
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[Intel-gfx] [PATCH 3/4] drm/i915/guc: Make adding GuC work items lockless
We can get rid of a spinlock by updating the tail directly using
cmpxchg. We can also put guc client on a diet by removing some constants
from the struct.
This causes a small change in one of GuC debugfs files.
We're no longer reporting constant values (which I don't think is a
problem), but we're also no longer reporting the tail (does anyone care?).
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Suggested-by: Chris Wilson
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 --
drivers/gpu/drm/i915/i915_guc_submission.c | 39 ++
drivers/gpu/drm/i915/intel_uc.h| 5
3 files changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f5fd00cfb3b0..e124e91aefcf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2447,8 +2447,6 @@ static void i915_guc_client_info(struct seq_file *m,
client->priority, client->stage_id, client->proc_desc_offset);
seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
client->doorbell_id, client->doorbell_offset,
client->doorbell_cookie);
- seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
- client->wq_size, client->wq_offset, client->wq_tail);
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 6f0adcd2a058..3a8a77ae2af8 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -306,7 +306,7 @@ static void guc_proc_desc_init(struct intel_guc *guc,
desc->db_base_addr = 0;
desc->stage_id = client->stage_id;
- desc->wq_size_bytes = client->wq_size;
+ desc->wq_size_bytes = GUC_WQ_SIZE;
desc->wq_status = WQ_STATUS_ACTIVE;
desc->priority = client->priority;
}
@@ -391,8 +391,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
desc->process_desc = gfx_addr + client->proc_desc_offset;
- desc->wq_addr = gfx_addr + client->wq_offset;
- desc->wq_size = client->wq_size;
+ desc->wq_addr = gfx_addr + GUC_DB_SIZE;
+ desc->wq_size = GUC_WQ_SIZE;
desc->desc_private = (uintptr_t)client;
}
@@ -416,15 +416,15 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct intel_engine_cs *engine = rq->engine;
struct guc_process_desc *desc = __get_process_desc(client);
struct guc_wq_item *wqi;
- u32 freespace, tail, wq_off;
+ u32 freespace, ring_tail, wq_off, wq_next;
/* Free space is guaranteed */
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
+ freespace = CIRC_SPACE(desc->tail, desc->head, GUC_WQ_SIZE);
GEM_BUG_ON(freespace < wqi_size);
/* The GuC firmware wants the tail index in QWords, not bytes */
- tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3;
- GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
+ ring_tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3;
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
* should not have the case where structure wqi is across page, neither
@@ -435,11 +435,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
- /* postincrement WQ tail for next time */
- wq_off = client->wq_tail;
+ /* Find our offset and postincrement WQ tail for next time */
+ do {
+ wq_off = desc->tail;
+ wq_next = (wq_off + wqi_size) & (GUC_WQ_SIZE - 1);
+ } while (cmpxchg(&desc->tail, wq_off, wq_next) != wq_off);
GEM_BUG_ON(wq_off & (wqi_size - 1));
- client->wq_tail += wqi_size;
- client->wq_tail &= client->wq_size - 1;
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -453,7 +454,7 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
/* The GuC wants only the low-order word of the context descriptor */
wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
- wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
wqi->fence_id = rq->global_seqno;
}
@@ -463,20 +464,14 @@ static void guc_reset_wq(struct i915_guc_client *client)
desc->head = 0;
desc->tail = 0;
-
- client->wq_tail = 0;
}
static int guc_ring_doorbell(struct i915_guc_client *client)
{
- struct
[Intel-gfx] [PATCH 4/4] HAX Enable GuC Submission for CI
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8ab003dca113..c9d72f1b8383 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_loading = 0,
- .enable_guc_submission = 0,
+ .enable_guc_loading = 2,
+ .enable_guc_submission = 2,
.guc_log_level = -1,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
--
2.13.5
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Re: [Intel-gfx] [PATCH] eb-uninit
Quoting Chris Wilson (2017-09-12 13:37:22) Wrong branch... On noes, I thought I had squashed this in... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable DMC powersaving during GT operations
On 12/09/2017 13:45, Tvrtko Ursulin wrote: On 12/09/2017 13:37, Chris Wilson wrote: The DMC typifies the worst example of firmware: it overrides system behaviour and is fubar. When no displays are active, the DMC appears to continually toggle its control register trying to change display power states. This in turn has the side effect of slowing down the GT by a few orders of magntidue, making headless operations intolerably slow. This seems to affect all machines with dmc (so a byproduct of the dmc code itself being shared) and severely limits throughput on the CI bxt and triggers the watchdog for incomplete tests. Altenative suggestion is to blacklist all DMC firmware until it is fixed. I've sent this as https://patchwork.freedesktop.org/patch/154942/ some time ago. You asked for a long code comment back then. :) Anyway, I don't mind we merge one of the two since it is taking an eternity to get this fixes in the firmware. So: Reviewed-by: Tvrtko Ursulin I take it back, there was a reason in shape of another firmware bug which made us put this patch on hold. Imre might know the status of that one. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable DMC powersaving during GT operations
== Series Details == Series: drm/i915: Disable DMC powersaving during GT operations URL : https://patchwork.freedesktop.org/series/30196/ State : success == Summary == Series 30196v1 drm/i915: Disable DMC powersaving during GT operations https://patchwork.freedesktop.org/api/1.0/series/30196/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: fail -> PASS (fi-kbl-7500u) fdo#102514 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:449s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:457s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:384s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:546s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:506s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:506s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:459s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:460s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:600s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:414s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:583s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:550s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:464s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:507s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:465s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:480s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:575s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:427s 694f07d3df18c02da3f526ae0e1238eb12534e1e drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest 64ca6b9d82b4 drm/i915: Disable DMC powersaving during GT operations == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5656/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] HAX Enable GuC Submission for CI
Preface with a revert of 04f7b24eccdfae680a36e9825fe0d61dcd5ed528 -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/4] HAX Enable GuC Submission for CI
Also:
Revert "drm/i915/guc: Assert that we switch between known ggtt->invalidate
functions"
This reverts commit 04f7b24eccdfae680a36e9825fe0d61dcd5ed528.
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/gpu/drm/i915/i915_params.c | 4 ++--
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 09e524dbc090..478a8d42aeb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3189,17 +3189,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv)
void i915_ggtt_enable_guc(struct drm_i915_private *i915)
{
- GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
}
void i915_ggtt_disable_guc(struct drm_i915_private *i915)
{
- /* We should only be called after i915_ggtt_enable_guc() */
- GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
- i915->ggtt.invalidate = gen6_ggtt_invalidate;
+ if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+ i915->ggtt.invalidate = gen6_ggtt_invalidate;
}
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8ab003dca113..c9d72f1b8383 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_loading = 0,
- .enable_guc_submission = 0,
+ .enable_guc_loading = 2,
+ .enable_guc_submission = 2,
.guc_log_level = -1,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
--
2.13.5
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Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Shankar, Uma
>Sent: Tuesday, September 12, 2017 3:20 PM
>To: Ville Syrjälä
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>
>
>>-Original Message-
>>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>>Sent: Monday, September 11, 2017 11:20 PM
>>To: Shankar, Uma
>>Cc: Srinivas, Vidya ;
>>intel-gfx@lists.freedesktop.org; Kahola, Mika ;
>>Kamath, Sunil ; Konduru, Chandra
>>
>>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>>
>>On Mon, Sep 11, 2017 at 01:04:18PM +, Shankar, Uma wrote:
>>>
>>>
>>> >-Original Message-
>>> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>>> >Sent: Friday, September 8, 2017 8:18 PM
>>> >To: Srinivas, Vidya
>>> >Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika
>>> >; Kamath, Sunil ;
>>> >Shankar, Uma ; Konduru, Chandra
>>> >
>>> >Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>>> >
>>> >On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
>>> >> From: Uma Shankar
>>> >>
>>> >> For gen9 platforms, dsi timings are driven from port instead of
>>> >> pipe (unlike ddi). Thus, we can't rely on pipe registers to get
>>> >> the timing information. Even scanline register read will not be
>>> >> functional.
>>> >> This is causing vblank evasion logic to fail since it relies on
>>> >> scanline, causing atomic update failure warnings.
>>> >>
>>> >> This patch uses pipe framestamp and current timestamp registers to
>>> >> calculate scanline. This is an indirect way to get the scanline.
>>> >> It helps resolve atomic update failure for gen9 dsi platforms.
>>> >>
>>> >> Signed-off-by: Uma Shankar
>>> >> Signed-off-by: Chandra Konduru
>>> >> Signed-off-by: Vidya Srinivas
>>> >> ---
>>> >> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>>> >> drivers/gpu/drm/i915/i915_irq.c | 5 +
>>> >> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>> >> drivers/gpu/drm/i915/intel_dsi.c | 46
>>> >>
>>> >> 4 files changed, 56 insertions(+)
>>> >>
>>> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> >> b/drivers/gpu/drm/i915/i915_drv.h index d07d110..4213b54 100644
>>> >> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> >> @@ -4077,6 +4077,8 @@ void intel_sbi_write(struct drm_i915_private
>>> >> *dev_priv, u16 reg, u32 value,
>>> >> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>>> >> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg,
>>> >> u32 val);
>>> >>
>>> >> +u32 bxt_dsi_get_scanline(struct intel_crtc *crtc);
>>> >> +
>>> >> /* intel_dpio_phy.c */
>>> >> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv,
>>> >> enum port
>>> >port,
>>> >> enum dpio_phy *phy, enum dpio_channel
>>> >> *ch); diff --
>>> >git
>>> >> a/drivers/gpu/drm/i915/i915_irq.c
>>> >> b/drivers/gpu/drm/i915/i915_irq.c index 5d391e6..31aa7f0 100644
>>> >> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> >> @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct
>>> >> intel_crtc
>>> >*crtc)
>>> >> struct drm_vblank_crtc *vblank;
>>> >> enum pipe pipe = crtc->pipe;
>>> >> int position, vtotal;
>>> >> +enum transcoder cpu_transcoder;
>>> >>
>>> >> if (!crtc->active)
>>> >> return -1;
>>> >> @@ -792,6 +793,10 @@ static int __intel_get_crtc_scanline(struct
>>> >> intel_crtc
>>> >*crtc)
>>> >> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>>> >> vtotal /= 2;
>>> >>
>>> >> +cpu_transcoder = crtc->config->cpu_transcoder;
>>> >
>>> >Humm. Would be nice to be able to do this without adding more
>>> >crtc->config uses. We're pretty much trying to get rid of that guy.
>>> >
>>>
>>> Will try to find an alternate way to do this.
>>>
>>> >> +if (IS_BROXTON(dev_priv) && transcoder_is_dsi(cpu_transcoder))
>>> >> +return bxt_dsi_get_scanline(crtc);
>>> >> +
>>> >> if (IS_GEN2(dev_priv))
>>> >> position = I915_READ_FW(PIPEDSL(pipe)) &
>>> >DSL_LINEMASK_GEN2;
>>> >> else
>>> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> >> b/drivers/gpu/drm/i915/i915_reg.h index 9a73ea0..54582de 100644
>>> >> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> >> @@ -8802,6 +8802,9 @@ enum skl_power_gate {
>>> >> #define MIPIO_TXESC_CLK_DIV2_MMIO(0x160008)
>>> >> #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
>>> >>
>>> >> +#define BXT_TIMESTAMP_CTR _MMIO(0x44070)
>>> >> +#define BXT_PIPE_FRMTMSTMP_A_MMIO(0x70048)
>>> >
>>> >Please add proper parametrized define that works for all pipes.
>>> >
>>>
>>> Will add that.
>>>
>>> >> +
>>> >> /* BXT MIPI
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skylake plane update/disable unifications [v4]
== Series Details == Series: drm/i915: Skylake plane update/disable unifications [v4] URL : https://patchwork.freedesktop.org/series/30185/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2301 pass:1237 dwarn:0 dfail:0 fail:12 skip:1052 time:9421s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5655/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
On Tue, Sep 12, 2017 at 01:23:39PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> >Shankar, Uma
> >Sent: Tuesday, September 12, 2017 3:20 PM
> >To: Ville Syrjälä
> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >
> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
> >
> >
> >
> >>-Original Message-
> >>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >>Sent: Monday, September 11, 2017 11:20 PM
> >>To: Shankar, Uma
> >>Cc: Srinivas, Vidya ;
> >>intel-gfx@lists.freedesktop.org; Kahola, Mika ;
> >>Kamath, Sunil ; Konduru, Chandra
> >>
> >>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
> >>
> >>On Mon, Sep 11, 2017 at 01:04:18PM +, Shankar, Uma wrote:
> >>>
> >>>
> >>> >-Original Message-
> >>> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >>> >Sent: Friday, September 8, 2017 8:18 PM
> >>> >To: Srinivas, Vidya
> >>> >Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika
> >>> >; Kamath, Sunil ;
> >>> >Shankar, Uma ; Konduru, Chandra
> >>> >
> >>> >Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
> >>> >
> >>> >On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
> >>> >> From: Uma Shankar
> >>> >>
> >>> >> For gen9 platforms, dsi timings are driven from port instead of
> >>> >> pipe (unlike ddi). Thus, we can't rely on pipe registers to get
> >>> >> the timing information. Even scanline register read will not be
> >>> >> functional.
> >>> >> This is causing vblank evasion logic to fail since it relies on
> >>> >> scanline, causing atomic update failure warnings.
> >>> >>
> >>> >> This patch uses pipe framestamp and current timestamp registers to
> >>> >> calculate scanline. This is an indirect way to get the scanline.
> >>> >> It helps resolve atomic update failure for gen9 dsi platforms.
> >>> >>
> >>> >> Signed-off-by: Uma Shankar
> >>> >> Signed-off-by: Chandra Konduru
> >>> >> Signed-off-by: Vidya Srinivas
> >>> >> ---
> >>> >> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> >>> >> drivers/gpu/drm/i915/i915_irq.c | 5 +
> >>> >> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >>> >> drivers/gpu/drm/i915/intel_dsi.c | 46
> >>> >>
> >>> >> 4 files changed, 56 insertions(+)
> >>> >>
> >>> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>> >> b/drivers/gpu/drm/i915/i915_drv.h index d07d110..4213b54 100644
> >>> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>> >> @@ -4077,6 +4077,8 @@ void intel_sbi_write(struct drm_i915_private
> >>> >> *dev_priv, u16 reg, u32 value,
> >>> >> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> >>> >> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg,
> >>> >> u32 val);
> >>> >>
> >>> >> +u32 bxt_dsi_get_scanline(struct intel_crtc *crtc);
> >>> >> +
> >>> >> /* intel_dpio_phy.c */
> >>> >> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv,
> >>> >> enum port
> >>> >port,
> >>> >> enum dpio_phy *phy, enum dpio_channel
> >>> >> *ch); diff --
> >>> >git
> >>> >> a/drivers/gpu/drm/i915/i915_irq.c
> >>> >> b/drivers/gpu/drm/i915/i915_irq.c index 5d391e6..31aa7f0 100644
> >>> >> --- a/drivers/gpu/drm/i915/i915_irq.c
> >>> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> >>> >> @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct
> >>> >> intel_crtc
> >>> >*crtc)
> >>> >>struct drm_vblank_crtc *vblank;
> >>> >>enum pipe pipe = crtc->pipe;
> >>> >>int position, vtotal;
> >>> >> + enum transcoder cpu_transcoder;
> >>> >>
> >>> >>if (!crtc->active)
> >>> >>return -1;
> >>> >> @@ -792,6 +793,10 @@ static int __intel_get_crtc_scanline(struct
> >>> >> intel_crtc
> >>> >*crtc)
> >>> >>if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> >>> >>vtotal /= 2;
> >>> >>
> >>> >> + cpu_transcoder = crtc->config->cpu_transcoder;
> >>> >
> >>> >Humm. Would be nice to be able to do this without adding more
> >>> >crtc->config uses. We're pretty much trying to get rid of that guy.
> >>> >
> >>>
> >>> Will try to find an alternate way to do this.
> >>>
> >>> >> + if (IS_BROXTON(dev_priv) && transcoder_is_dsi(cpu_transcoder))
> >>> >> + return bxt_dsi_get_scanline(crtc);
> >>> >> +
> >>> >>if (IS_GEN2(dev_priv))
> >>> >>position = I915_READ_FW(PIPEDSL(pipe)) &
> >>> >DSL_LINEMASK_GEN2;
> >>> >>else
> >>> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>> >> b/drivers/gpu/drm/i915/i915_reg.h index 9a73ea0..54582de 100644
> >>> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> >> @@ -8802,6 +8802,9 @@ enum skl_power_gate {
> >>> >> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> >>> >> #define GLK_TX_ESC_CLK_DIV2_MASK
Re: [Intel-gfx] [PATCH v13 2/5] drm/i915: Introduce private PAT management
On Tue, 2017-09-12 at 15:20 +0800, Zhi Wang wrote:
> On 09/11/17 16:59, Joonas Lahtinen wrote:
> > On Mon, 2017-09-11 at 12:26 +0800, Zhi Wang wrote:
> > > The private PAT management is to support PPAT entry manipulation. Two
> > > +static unsigned int bdw_private_pat_match(u8 src, u8 dst)
> > > +{
> > > + unsigned int score = 0;
> > > +
> > > + /* Cache attribute has to be matched. */
> > > + if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
> > > + return 0;
> >
> > We're not giving any points for when only cache attribute matches? Does
> > not this result in ENOSPC when we would have an entry with matching
> > "cache attribute", but no other matching entries while PPAT is full.
> >
> > so maybe score += 4 here?
> >
>
> Aiha. cache attribute of src == cache attribute of dst is mandatory
> since the mismatch of other attribute only causes performance drop, but
> mismatch of cache attribute causes problem of correctness.
Yes, that's why I suggested;
if (CA(src) != CA(dst))
return 0;
score += 4;
if (...)
score += ...
Because currently, if only the cache attribute matches (which is enough
for correctness), the score is returned as zero which is then rejected
just like if cache attribute did not match. If only cache attribute
matches, we should return non-zero, like my example above.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✓ Fi.CI.BAT: success for eb-uninit
== Series Details == Series: eb-uninit URL : https://patchwork.freedesktop.org/series/30197/ State : success == Summary == Series 30197v1 eb-uninit https://patchwork.freedesktop.org/api/1.0/series/30197/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: fail -> PASS (fi-kbl-7500u) fdo#102514 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:452s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:452s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:375s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:532s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:503s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:494s fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:452s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:450s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:603s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:429s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:436s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:487s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:552s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:448s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:504s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:463s fi-skl-x1585ltotal:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:480s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:421s 694f07d3df18c02da3f526ae0e1238eb12534e1e drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest a40e1048d670 eb-uninit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5657/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Submit GuC workitems containing coalesced requests
Quoting Michał Winiarski (2017-09-12 13:47:24) > To create an upper bound on number of GuC workitems, we need to change > the way that requests are being submitted. Rather than submitting each > request as an individual workitem, we can do coalescing in a similar way > we're handlig execlist submission ports. We also need to stop pretending > that we're doing "lite-restore" in GuC submission (we would create a > workitem each time we hit this condition). This allows us to completely > remove the reservation, replacing it with a compile time check. > > v2: Also coalesce when replaying on reset (Daniele) > v3: Consistent wq_resv - per-request (Daniele) > v4: Squash removing wq_resv > > References: https://bugs.freedesktop.org/show_bug.cgi?id=101873 > Cc: Chris Wilson > Cc: Daniele Ceraolo Spurio > Cc: Jeff McGee > Cc: Michal Wajdeczko > Cc: Oscar Mateo > Signed-off-by: Michał Winiarski Matches my expectations, Reviewed-by: Chris Wilson Just pondering the interaction with gen8_cs_irq_handler(). Since we are now tweaking port_count(), it is theoretically possible that we get a cs-interrupt. That seems entirely harmless as the guc tasklet checks the breadcrumb anyway. Just something to keep in the back of the mind when reviewing the interactions between execlist.port[] and guc. But I'm wondering if we should be masking the cs-interrupt on switching to guc... I don't believe we are in gen9_enable_guc_interrupts(). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v4.
This tests the various parts of atomic that I want to make
interruptible. Running with --debug shows the stats from
__igt_sigiter_continue, which can be used to make sure that
we don't fall over.
The default igt kms helpers use drmIoctl, which is not intercepted
by igt_while_interruptible. Only igt_ioctl is. This means we have
to call the ioctls manually here.
Changes since v1:
- Implement interruptible DPMS checking too.
- Use igt_ioctl + igt_while_interruptible, instead of the signal helper
shotgun.
Changes since v2:
- Bump whitespace to get rid of the weird double } at same indent.
- Use more newlines in the call to the atomic ioctl.
Changes since v3:
- Fix copyright on year. (Adrinael)
- Use do_ioctl instead of do_or_die(igt_ioctl) (ickle).
- Add test description. (Adrinael)
Signed-off-by: Maarten Lankhorst
Cc: Daniel Stone
Acked-by: Daniel Vetter #v1
Reviewed-by: Petri Latvala
[mlankhorst: Document sleep values (Adrinael)]
---
lib/igt_kms.c| 3 +-
lib/igt_kms.h| 1 +
tests/Makefile.sources | 1 +
tests/kms_atomic_interruptible.c | 331 +++
4 files changed, 335 insertions(+), 1 deletion(-)
create mode 100644 tests/kms_atomic_interruptible.c
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 72fde792ba89..7bcafc072f70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -186,7 +186,8 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
"scaling mode",
- "CRTC_ID"
+ "CRTC_ID",
+ "DPMS"
};
/*
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index e5dc329b161e..3d1061fa08c8 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -114,6 +114,7 @@ extern const char *igt_crtc_prop_names[];
enum igt_atomic_connector_properties {
IGT_CONNECTOR_SCALING_MODE = 0,
IGT_CONNECTOR_CRTC_ID,
+ IGT_CONNECTOR_DPMS,
IGT_NUM_CONNECTOR_PROPS
};
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0f4e39af10a1..cf542df181a8 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -172,6 +172,7 @@ TESTS_progs = \
kms_3d \
kms_addfb_basic \
kms_atomic \
+ kms_atomic_interruptible \
kms_atomic_transition \
kms_busy \
kms_ccs \
diff --git a/tests/kms_atomic_interruptible.c b/tests/kms_atomic_interruptible.c
new file mode 100644
index ..4e06ee4e2d6b
--- /dev/null
+++ b/tests/kms_atomic_interruptible.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Tests that interrupt various atomic ioctls.");
+
+enum plane_test_type
+{
+ test_legacy_modeset,
+ test_atomic_modeset,
+ test_legacy_dpms,
+ test_setplane,
+ test_setcursor,
+ test_pageflip
+};
+
+static int block_plane(igt_display_t *display, igt_output_t *output, enum
plane_test_type test_type, igt_plane_t *plane)
+{
+ int timeline = sw_sync_timeline_create();
+
+ igt_fork(child, 1) {
+ /* Ignore the signal helper, we need to block indefinitely on
the fence. */
+ signal(SIGCONT, SIG_IGN);
+
+ if (test_type == test_legacy_modeset || test_type ==
test_atomic_modeset) {
+ igt_output_set_pipe(output, PIPE_NONE);
+ igt_plane_set_fb(plane, NULL);
+ }
+ igt_plane_set_fence_fd(plane,
sw_sync_timeline_create_fence(timeline, 1));
+
+ igt_display_commit2(display, COMMIT_ATOMIC);
+ }
+
+ return timeline;
+}
+
+static void unblock(int block)
+{
+ sw_sync_timeline_inc(block, 1);
+ close(block);
+}
+
+static void ev_page_flip(int fd, unsigned seq, unsigned tv_sec, unsigned
Re: [Intel-gfx] [PATCH v13 2/5] drm/i915: Introduce private PAT management
Thanks! :) I see.
-Original Message-
From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
Sent: Tuesday, September 12, 2017 4:34 PM
To: Wang, Zhi A ; intel-gfx@lists.freedesktop.org;
intel-gvt-...@lists.freedesktop.org
Cc: Vivi, Rodrigo ; Widawsky, Benjamin
; zhen...@linux.intel.com; ch...@chris-wilson.co.uk
Subject: Re: [PATCH v13 2/5] drm/i915: Introduce private PAT management
On Tue, 2017-09-12 at 15:20 +0800, Zhi Wang wrote:
> On 09/11/17 16:59, Joonas Lahtinen wrote:
> > On Mon, 2017-09-11 at 12:26 +0800, Zhi Wang wrote:
> > > The private PAT management is to support PPAT entry manipulation.
> > > Two
> > > +static unsigned int bdw_private_pat_match(u8 src, u8 dst) {
> > > + unsigned int score = 0;
> > > +
> > > + /* Cache attribute has to be matched. */
> > > + if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
> > > + return 0;
> >
> > We're not giving any points for when only cache attribute matches?
> > Does not this result in ENOSPC when we would have an entry with
> > matching "cache attribute", but no other matching entries while PPAT is
> > full.
> >
> > so maybe score += 4 here?
> >
>
> Aiha. cache attribute of src == cache attribute of dst is mandatory
> since the mismatch of other attribute only causes performance drop,
> but mismatch of cache attribute causes problem of correctness.
Yes, that's why I suggested;
if (CA(src) != CA(dst))
return 0;
score += 4;
if (...)
score += ...
Because currently, if only the cache attribute matches (which is enough for
correctness), the score is returned as zero which is then rejected just like if
cache attribute did not match. If only cache attribute matches, we should
return non-zero, like my example above.
Regards, Joonas
--
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH v2 0/6] drm/atomic: Interruptible locks for everyone!
Op 12-09-17 om 14:41 schreef Maarten Lankhorst: > drm_atomic_commit could previous have always failed when waits failed, > but locking was always done uninterruptibly. Add infrastructure to make > it possible for callers to choose interruptible locking, and convert the > 5 most common ioctl's to use it. > > All other atomic helpers can be converted when additional tests are added > to kms_atomic_interruptible. > > Changes since last version: > - Small fixes to the preparation patch > - Convert setcrtc as well. > > Maarten Lankhorst (6): > drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible > waiting, v2. > drm/atomic: Convert atomic ioctl locking to interruptible. > drm/legacy: Convert cursor ioctl locking to interruptible. > drm/legacy: Convert setplane ioctl locking to interruptible. > drm/atomic: Convert pageflip ioctl locking to interruptible. > drm/crtc: Convert setcrtc ioctl locking to interruptible. > > drivers/gpu/drm/drm_atomic.c | 7 +-- > drivers/gpu/drm/drm_crtc.c | 7 +-- > drivers/gpu/drm/drm_debugfs_crc.c | 2 +- > drivers/gpu/drm/drm_modeset_lock.c | 96 > +++--- > drivers/gpu/drm/drm_plane.c| 21 + > include/drm/drm_modeset_lock.h | 12 +++-- > 6 files changed, 77 insertions(+), 68 deletions(-) > Please ignore this series, should have been sent to dri-devel with intel-gfx to cc. I'm resending. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/6] drm/legacy: Convert cursor ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_plane.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 7a00351d5b5d..eef58595101c 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -834,7 +834,7 @@ static int drm_mode_cursor_common(struct drm_device *dev,
return -ENOENT;
}
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock(&crtc->mutex, &ctx);
if (ret)
@@ -876,8 +876,9 @@ static int drm_mode_cursor_common(struct drm_device *dev,
}
out:
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
--
2.14.1
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[Intel-gfx] [PATCH v2 0/6] drm/atomic: Interruptible locks for everyone!
drm_atomic_commit could previous have always failed when waits failed, but locking was always done uninterruptibly. Add infrastructure to make it possible for callers to choose interruptible locking, and convert the 5 most common ioctl's to use it. All other atomic helpers can be converted when additional tests are added to kms_atomic_interruptible. Changes since last version: - Small fixes to the preparation patch - Convert setcrtc as well. Maarten Lankhorst (6): drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible waiting, v2. drm/atomic: Convert atomic ioctl locking to interruptible. drm/legacy: Convert cursor ioctl locking to interruptible. drm/legacy: Convert setplane ioctl locking to interruptible. drm/atomic: Convert pageflip ioctl locking to interruptible. drm/crtc: Convert setcrtc ioctl locking to interruptible. drivers/gpu/drm/drm_atomic.c | 7 +-- drivers/gpu/drm/drm_crtc.c | 7 +-- drivers/gpu/drm/drm_debugfs_crc.c | 2 +- drivers/gpu/drm/drm_modeset_lock.c | 96 +++--- drivers/gpu/drm/drm_plane.c| 21 + include/drm/drm_modeset_lock.h | 12 +++-- 6 files changed, 77 insertions(+), 68 deletions(-) -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/6] drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible waiting, v2.
When we want to make drm_atomic_commit interruptible, there are a lot of
places that call the lock function, which we don't have control over.
Rather than trying to convert every single one, it's easier to toggle
interruptible waiting per acquire_ctx. If drm_modeset_acquire_init is
called with DRM_MODESET_ACQUIRE_INTERRUPTIBLE, then we will perform
interruptible waits in drm_modeset_lock and drm_modeset_backoff.
Changes since v1:
- Fix locking example in drm_modeset_lock.c to be compatible
with interruptible waiting (xexaxo) and make it default.
Uninterruptible waiting shouldn't happen except in corner cases,
but the example will still apply if the flag is removed.
- Add drm_modeset_lock_single_interruptible() to documentation.
- Fix dead link to removed drm_modeset_lock_interruptible() in
drm_modeset_lock().
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter #v1
Cc: Emil Velikov
---
drivers/gpu/drm/drm_debugfs_crc.c | 2 +-
drivers/gpu/drm/drm_modeset_lock.c | 96 +++---
include/drm/drm_modeset_lock.h | 12 +++--
3 files changed, 57 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs_crc.c
b/drivers/gpu/drm/drm_debugfs_crc.c
index f9e26dda56d6..9dd879589a2c 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -155,7 +155,7 @@ static int crtc_crc_open(struct inode *inode, struct file
*filep)
int ret = 0;
if (drm_drv_uses_atomic_modeset(crtc->dev)) {
- ret = drm_modeset_lock_interruptible(&crtc->mutex, NULL);
+ ret = drm_modeset_lock_single_interruptible(&crtc->mutex);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/drm_modeset_lock.c
b/drivers/gpu/drm/drm_modeset_lock.c
index af4e906c630d..e123497da0ca 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -39,23 +39,28 @@
*
* The basic usage pattern is to::
*
- * drm_modeset_acquire_init(&ctx)
+ * drm_modeset_acquire_init(ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
* retry:
* foreach (lock in random_ordered_set_of_locks) {
- * ret = drm_modeset_lock(lock, &ctx)
+ * ret = drm_modeset_lock(lock, ctx)
* if (ret == -EDEADLK) {
- * drm_modeset_backoff(&ctx);
- * goto retry;
+ * ret = drm_modeset_backoff(ctx);
+ * if (!ret)
+ * goto retry;
* }
+ * if (ret)
+ * goto out;
* }
* ... do stuff ...
- * drm_modeset_drop_locks(&ctx);
- * drm_modeset_acquire_fini(&ctx);
+ * out:
+ * drm_modeset_drop_locks(ctx);
+ * drm_modeset_acquire_fini(ctx);
*
* If all that is needed is a single modeset lock, then the &struct
* drm_modeset_acquire_ctx is not needed and the locking can be simplified
- * by passing a NULL instead of ctx in the drm_modeset_lock()
- * call and, when done, by calling drm_modeset_unlock().
+ * by passing a NULL instead of ctx in the drm_modeset_lock() call or
+ * calling drm_modeset_lock_single_interruptible(). To unlock afterwards
+ * call drm_modeset_unlock().
*
* On top of these per-object locks using &ww_mutex there's also an overall
* &drm_mode_config.mutex, for protecting everything else. Mostly this means
@@ -178,7 +183,11 @@ EXPORT_SYMBOL(drm_warn_on_modeset_not_all_locked);
/**
* drm_modeset_acquire_init - initialize acquire context
* @ctx: the acquire context
- * @flags: for future
+ * @flags: 0 or %DRM_MODESET_ACQUIRE_INTERRUPTIBLE
+ *
+ * When passing %DRM_MODESET_ACQUIRE_INTERRUPTIBLE to @flags,
+ * all calls to drm_modeset_lock() will perform an interruptible
+ * wait.
*/
void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
uint32_t flags)
@@ -186,6 +195,9 @@ void drm_modeset_acquire_init(struct
drm_modeset_acquire_ctx *ctx,
memset(ctx, 0, sizeof(*ctx));
ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
INIT_LIST_HEAD(&ctx->locked);
+
+ if (flags & DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
+ ctx->interruptible = true;
}
EXPORT_SYMBOL(drm_modeset_acquire_init);
@@ -261,8 +273,19 @@ static inline int modeset_lock(struct drm_modeset_lock
*lock,
return ret;
}
-static int modeset_backoff(struct drm_modeset_acquire_ctx *ctx,
- bool interruptible)
+/**
+ * drm_modeset_backoff - deadlock avoidance backoff
+ * @ctx: the acquire context
+ *
+ * If deadlock is detected (ie. drm_modeset_lock() returns -EDEADLK),
+ * you must call this function to drop all currently held locks and
+ * block until the contended lock becomes available.
+ *
+ * This function returns 0 on success, or -ERESTARTSYS if this context
+ * is initialized with %DRM_MODESET_ACQUIRE_INTERRUPTIBLE and the
+ * wait has been interrupted.
+ */
+int drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
{
struct drm_modeset_lock *contended = ctx->co
[Intel-gfx] [PATCH v2 4/6] drm/legacy: Convert setplane ioctl locking to interruptible.
Pass DRM_MODESET_ACQUIRE_INTERRUPTIBLE to acquire_init, and handle
drm_modeset_backoff which can now fail by returning the error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_plane.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index eef58595101c..803d67c22da2 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -667,7 +667,7 @@ static int setplane_internal(struct drm_plane *plane,
struct drm_modeset_acquire_ctx ctx;
int ret;
- drm_modeset_acquire_init(&ctx, 0);
+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
retry:
ret = drm_modeset_lock_all_ctx(plane->dev, &ctx);
if (ret)
@@ -678,8 +678,9 @@ static int setplane_internal(struct drm_plane *plane,
fail:
if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- goto retry;
+ ret = drm_modeset_backoff(&ctx);
+ if (!ret)
+ goto retry;
}
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
--
2.14.1
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