[Intel-gfx] Issues withddcutils/ddccontorl remote control of an monitor with Skylake/Kabylake GPU
I have a Kabylake GPU (i7700K) and I can't control my monitor with it using ddcutil. It only sometimes work and most of the time spews i2c errors. I also tested on my laptop which has Skylake GPU and I see the same issue. The same monitor works with my nvidia GPU and when connected via VGA<->DP adapter to the notebook. I will soon provide all the debug logs i could gather, but meanwhile maybe this is known issue? For reference I used 4.12 kernel on the Kabylake GPU. Best regards, Maxim Levitsky ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [01/10] drm/i915/guc: Create intel_guc.c for defining GuC specific functionality
== Series Details == Series: series starting with [01/10] drm/i915/guc: Create intel_guc.c for defining GuC specific functionality URL : https://patchwork.freedesktop.org/series/30486/ State : warning == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-2p-pri-indfb-multidraw: pass -> SKIP (shard-hsw) Subgroup fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-spr-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: pass -> SKIP (shard-hsw) Subgroup psr-2p-primscrn-pri-shrfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-pri-shrfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc: pass -> SKIP (shard-hsw) Subgroup psr-2p-scndscrn-shrfb-plflip-blt: pass -> SKIP (shard-hsw) Subgroup fbc-2p-primscrn-spr-indfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) Subgroup psr-1p-rte: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup psr-2p-scndscrn-spr-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-cur-indfb-draw-pwrite: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: pass -> SKIP (shard-hsw) Subgroup psr-1p-primscrn-spr-indfb-fullscreen: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-cur-indfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbc-1p-indfb-fliptrack: skip -> PASS (shard-hsw) Subgroup psr-rgb101010-draw-blt: pass -> SKIP (shard-hsw) Subgroup psr-1p-offscren-pri-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-pri-shrfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt: pass -> SKIP (shard-hsw) Subgroup psr-1p-primscrn-spr-indfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-spr-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc: pass -> SKIP (shard-hsw) Subgroup psr-1p-primscrn-spr-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu: skip -> PASS (shard-hsw) Subgroup psr-2p-primscrn-cur-indfb-draw-render: pass -> SKIP (shard-hsw) Subgroup psr-rgb565-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-spr-indfb-onoff: pass -> SKIP (shard-hsw) Subgroup psr-1p-primscrn-pri-shrfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-pri-indfb-multidraw: pass -> SKIP (shard-hsw) Subgroup fbc-2p-scndscrn-pri-indfb-draw-pwrite: pass -> SKIP (shard-hsw) Subgroup fbc-2p-primscrn-cur-indfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-primscrn-indfb-msflip-blt: pass -> SKIP (shard-hsw) Subgroup psr-2p-scndscrn-cur-indfb-move: pass -> SKIP (shard-hsw) Subgroup psr-2p-primscrn-pri-shrfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbc-2p-primscrn-cur-indfb-draw-blt: pass -> SKIP (shard-hsw) Subgroup psr-2p-scndscrn-pri-indfb-draw-render: pass -> SKIP (shard-hsw) Subgroup fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbcpsr-2p-scndscrn-indfb-msflip-blt: pass -> SKIP (shard-hsw) Subgroup fbcpsr-rgb565-draw-mmap-cpu: pass -> SKIP (shard-hsw) Subgroup fbc-1p-primscrn-cur-indfb-onoff: skip -> PASS (shard-hsw) Subgroup psr-1p-offscren-pri
Re: [Intel-gfx] [PATCH v2] drm/dp: DPCD register defines for link status within ESI field
On Wed, 13 Sep 2017, Dhinakaran Pandiyan wrote: > Link status is available in the ESI field on devices with DPCD r1.2 or > higher. DP spec also says "An MST upstream device shall use this field > instead of the Link/Sink Device Status field registers, starting from DPCD > Address 00200h." > > v2: Prefixed DP_ (Jani) > Rewrote commment to stay within 80 cols. > Cc: Jani Nikula > Reviewed-by: Jani Nikula > Signed-off-by: Dhinakaran Pandiyan Thanks, pushed to drm-misc-next. BR, Jani. > --- > include/drm/drm_dp_helper.h | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 2c412a15cfa1..11c39f15f1b3 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -738,6 +738,11 @@ > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) > > +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as > 0x202 */ > +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as > 0x203 */ > +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as > 0x204 */ > +#define DP_SINK_STATUS_ESI 0x200f /* status same as > 0x205 */ > + > #define DP_DPRX_FEATURE_ENUMERATION_LIST0x2210 /* DP 1.3 */ > # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ > # define DP_SST_SPLIT_SDP_CAP(1 << 1) /* DP > 1.4 */ -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gen9+: Set same power state before hibernation image save/restore
On Fri, Sep 15, 2017 at 06:02:33PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 16, 2017 at 05:46:07PM +0300, Imre Deak wrote:
> > Atm, on GEN9 big core platforms before saving the hibernation image we
> > uninitialize the display, disabling power wells manually, while before
> > restoring the image we keep things powered (letting HW/DMC power down
> > things as needed). The state mismatch will trigger the following error:
> >
> > DC state mismatch (0x0 -> 0x2)
> >
> > While the restore handler knows how to initialize the display from an
> > unknown state (due to a different loader kernel or not having i915
> > loaded in the loader kernel) we should still use the same state for
> > consistency before image saving and restoring. Do this by uniniting the
> > display before restoring the image too.
> >
> > Bugzilla: https://bugs.freedesktop.org/attachment.cgi?id=133376
> > Reported-and-tested-by: Wang Wendy
> > Reported-and-tested-by: Joonas Lahtinen
> > Cc: Wang Wendy
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjala
> > Signed-off-by: Imre Deak
> >
> > ---
> >
> > [ No Fixes: line, since I'm not aware of any other issues caused by this
> > besides the error message. ]
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 20 +---
> > 1 file changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 43100229613c..d816ba715cb6 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1571,7 +1571,7 @@ static int i915_drm_suspend_late(struct drm_device
> > *dev, bool hibernation)
> >
> > intel_display_set_init_power(dev_priv, false);
> >
> > - fw_csr = !IS_GEN9_LP(dev_priv) &&
> > + fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
> > suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
> > /*
> > * In case of firmware assisted context save/restore don't manually
> > @@ -2055,11 +2055,14 @@ static int i915_pm_resume(struct device *kdev)
> > /* freeze: before creating the hibernation_image */
> > static int i915_pm_freeze(struct device *kdev)
> > {
> > + struct drm_device *dev = &kdev_to_i915(kdev)->drm;
> > int ret;
> >
> > - ret = i915_pm_suspend(kdev);
> > - if (ret)
> > - return ret;
> > + if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
> > + ret = i915_drm_suspend(dev);
> > + if (ret)
> > + return ret;
> > + }
>
> Hmm. This hunk is here just for consistentency I take it?
Yes, to make i915_pm_freeze() and i915_pm_freeze_late() similar.
>
> Patch lgtm
> Reviewed-by: Ville Syrjälä
>
> >
> > ret = i915_gem_freeze(kdev_to_i915(kdev));
> > if (ret)
> > @@ -2070,11 +2073,14 @@ static int i915_pm_freeze(struct device *kdev)
> >
> > static int i915_pm_freeze_late(struct device *kdev)
> > {
> > + struct drm_device *dev = &kdev_to_i915(kdev)->drm;
> > int ret;
> >
> > - ret = i915_pm_suspend_late(kdev);
> > - if (ret)
> > - return ret;
> > + if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
> > + ret = i915_drm_suspend_late(dev, true);
> > + if (ret)
> > + return ret;
> > + }
> >
> > ret = i915_gem_freeze_late(kdev_to_i915(kdev));
> > if (ret)
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH v2] drm/i915/mst: Use MST sideband message transactions for dpms control
Op 13-09-17 om 22:06 schreef Dhinakaran Pandiyan:
> Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to
> set power states for downstream sinks. Apart from giving us the ability
> to set power state for individual sinks, this fixes the below test for
> me.
>
> $ xrandr --display :0 --output DP-2-2-8 --off
> $ xrandr --display :0 --output DP-2-2-1 --off
> $ xrandr --display :0 --output DP-2-2-8 --auto #Black screen
> $ xrandr --display :0 --output DP-2-2-1 --auto
>
> v2: Modify and document the dpms and port disable order (Ville)
> Add comment explaining is_mst = !crtc_state equivalence(Ville, Maarten)
>
> Cc: Ville Syrjälä
> Cc: Lyude
> Cc: Maarten Lankhorst
> Signed-off-by: Dhinakaran Pandiyan
Acked-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_ddi.c| 18 ++
> drivers/gpu/drm/i915/intel_dp_mst.c | 13 +
> 2 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 1da3bb2cc4b4..0053d66393f8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2161,7 +2161,8 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> intel_prepare_dp_ddi_buffers(encoder);
>
> intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!link_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> intel_dp_start_link_train(intel_dp);
> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> intel_dp_stop_link_train(intel_dp);
> @@ -2235,12 +2236,21 @@ static void intel_ddi_post_disable(struct
> intel_encoder *intel_encoder,
> uint32_t val;
> bool wait = false;
>
> - /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
> -
> if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + /*
> + * old_crtc_state and old_conn_state are NULL when called from
> + * DP_MST. The main connector associated with this port is never
> + * bound to a crtc for MST.
> + */
> + bool is_mst = !old_crtc_state;
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + /*
> + * Power down sink before disabling the port, otherwise we end
> + * up getting interrupts from the sink on detecting link loss.
> + */
> + if (!is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> }
>
> val = I915_READ(DDI_BUF_CTL(port));
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8e3aad0ea60b..187f3f05a828 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -164,15 +164,19 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder,
>
> drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
>
> + /*
> + * Power down mst path before disabling the port, otherwise we end
> + * up getting interrupts from the sink upon detecting link loss.
> + */
> + drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
> + false);
> +
> intel_dp->active_mst_links--;
>
> intel_mst->connector = NULL;
> - if (intel_dp->active_mst_links == 0) {
> + if (intel_dp->active_mst_links == 0)
> intel_dig_port->base.post_disable(&intel_dig_port->base,
> NULL, NULL);
> -
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> - }
> }
>
> static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> @@ -197,6 +201,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
>
> DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>
> + drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
> if (intel_dp->active_mst_links == 0)
> intel_dig_port->base.pre_enable(&intel_dig_port->base,
> pipe_config, NULL);
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[Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Cleanup adding GuC work items
We can just operate on the wq_tail directly (in the process descriptor).
This allows us to remove the duplicated tail from the client. While I'm
here let's also remove the constants kept in the client and document our
locking requirements. This causes a small change in one of GuC debugfs
files. We're no longer reporting constant values (which I don't think
is a problem), but we're also no longer reporting the tail (does anyone
care?).
v2: Update tail after wqi contents. (Chris)
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 --
drivers/gpu/drm/i915/i915_guc_submission.c | 35 --
drivers/gpu/drm/i915/intel_uc.h| 4
3 files changed, 14 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 46ac6091772e..2518bdf95eef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2447,8 +2447,6 @@ static void i915_guc_client_info(struct seq_file *m,
client->priority, client->stage_id, client->proc_desc_offset);
seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
client->doorbell_id, client->doorbell_offset);
- seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
- client->wq_size, client->wq_offset, client->wq_tail);
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 16ce570a0b74..954bd183591b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -305,7 +305,7 @@ static void guc_proc_desc_init(struct intel_guc *guc,
desc->db_base_addr = 0;
desc->stage_id = client->stage_id;
- desc->wq_size_bytes = client->wq_size;
+ desc->wq_size_bytes = GUC_WQ_SIZE;
desc->wq_status = WQ_STATUS_ACTIVE;
desc->priority = client->priority;
}
@@ -390,8 +390,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
desc->process_desc = gfx_addr + client->proc_desc_offset;
- desc->wq_addr = gfx_addr + client->wq_offset;
- desc->wq_size = client->wq_size;
+ desc->wq_addr = gfx_addr + GUC_DB_SIZE;
+ desc->wq_size = GUC_WQ_SIZE;
desc->desc_private = (uintptr_t)client;
}
@@ -416,14 +416,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct i915_gem_context *ctx = rq->ctx;
struct guc_process_desc *desc = __get_process_desc(client);
struct guc_wq_item *wqi;
- u32 freespace, tail, wq_off;
+ u32 ring_tail, wq_off;
- /* Free space is guaranteed */
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- GEM_BUG_ON(freespace < wqi_size);
+ lockdep_assert_held(&client->wq_lock);
- tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
- GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
+ ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
* should not have the case where structure wqi is across page, neither
@@ -434,11 +432,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
- /* postincrement WQ tail for next time */
- wq_off = client->wq_tail;
+ /* Postincrement WQ tail for next time, free space is guaranteed. */
+ wq_off = READ_ONCE(desc->tail);
+ GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
+ GUC_WQ_SIZE) < wqi_size);
+ WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
GEM_BUG_ON(wq_off & (wqi_size - 1));
- client->wq_tail += wqi_size;
- client->wq_tail &= client->wq_size - 1;
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -451,7 +450,7 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx,
engine));
- wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
wqi->fence_id = rq->global_seqno;
}
@@ -461,18 +460,14 @@ static void guc_reset_wq(struct i915_guc_client *client)
desc->head = 0;
desc->tail = 0;
-
- client->wq_tail = 0;
}
static void guc_ring_doorbell(struct i915_guc_client *client)
{
- struct guc_process_desc *desc = _
Re: [Intel-gfx] Issues withddcutils/ddccontorl remote control of an monitor with Skylake/Kabylake GPU
On Mon, 18 Sep 2017, Maxim Levitsky wrote: > I have a Kabylake GPU (i7700K) and I can't control my monitor with it using > ddcutil. > It only sometimes work and most of the time spews i2c errors. > I also tested on my laptop which has Skylake GPU and I see the same issue. > The same monitor works with my nvidia GPU and when connected via VGA<->DP > adapter to the notebook. > > I will soon provide all the debug logs i could gather, but meanwhile maybe > this is known issue? > > For reference I used 4.12 kernel on the Kabylake GPU. Please file bugs at [1], and attach the logs there. ISTR there have been bugs reported about this before, but I couldn't find any. It certainly has never been a high priority thing. BR, Jani. [1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/execlists: Kick start request processing after a reset
On Sat, Sep 16, 2017 at 09:44:11PM +0100, Chris Wilson wrote:
> During a reset, we may skip over completed requests and lost
> context-switch interrupts. Following the reset, we may then may end up
> with no active requests in the ELSP (and so do not resubmit to restart
> the engine), but have a queue of requests ready for execution. This is
> unlikely, it requires the last request to complete after the hang is
> detected, but not impossible. The outcome of this is that the engine
> stalls, possibly leading to full ring and indefinite wait under
> struct_mutex, eventually leading to a full driver hang.
>
> Alternatively, we can solve this by unsubmitting the incomplete requests
> and just kickstarting the tasklet. Michał has patches for that, which I
> initially disliked due to the extra complexity, but the complexity of
> this "simple" restart is growing...
You are doing exactly that in 4/4.
Perhaps squash the two together to avoid moving code around, although this one
is a genuine fix, so I guess it's also fine on its own.
If you rebase the whole thing on top of coalesced GuC requests (which now is all
reviewed and ready to be merged), we'll have uniform reset handling for GuC
and execlists.
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
Reviewed-by: Michał Winiarski
-Michał
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 2f9ebd32025c..d960611692de 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1340,8 +1340,12 @@ static int gen8_init_common_ring(struct
> intel_engine_cs *engine)
> submit = true;
> }
>
> - if (submit && !i915.enable_guc_submission)
> - execlists_submit_ports(engine);
> + if (!i915.enable_guc_submission) {
> + if (submit)
> + execlists_submit_ports(engine);
> + else if (engine->execlist_first)
> + tasklet_hi_schedule(&engine->irq_tasklet);
> + }
>
> return 0;
> }
> --
> 2.14.1
>
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable (rev3)
== Series Details == Series: series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable (rev3) URL : https://patchwork.freedesktop.org/series/30345/ State : failure == Summary == Series 30345v3 series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable https://patchwork.freedesktop.org/api/1.0/series/30345/revisions/3/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> SKIP (fi-glk-2a) Test drv_hangman: Subgroup error-state-basic: pass -> SKIP (fi-glk-2a) Test gem_busy: Subgroup basic-busy-default: pass -> SKIP (fi-glk-2a) Subgroup basic-hang-default: pass -> SKIP (fi-glk-2a) Test gem_close_race: Subgroup basic-process: pass -> SKIP (fi-glk-2a) Subgroup basic-threads: pass -> SKIP (fi-glk-2a) Test gem_cpu_reloc: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_cs_tlb: Subgroup basic-default: pass -> SKIP (fi-glk-2a) Test gem_ctx_create: Subgroup basic: pass -> SKIP (fi-glk-2a) Subgroup basic-files: pass -> SKIP (fi-glk-2a) Test gem_ctx_exec: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_ctx_switch: Subgroup basic-default: pass -> SKIP (fi-glk-2a) Subgroup basic-default-heavy: pass -> SKIP (fi-glk-2a) Test gem_exec_basic: Subgroup basic-blt: pass -> SKIP (fi-glk-2a) Subgroup basic-bsd: pass -> SKIP (fi-glk-2a) Subgroup basic-default: pass -> SKIP (fi-glk-2a) Subgroup basic-render: pass -> SKIP (fi-glk-2a) Subgroup basic-vebox: pass -> SKIP (fi-glk-2a) Subgroup gtt-blt: pass -> SKIP (fi-glk-2a) Subgroup gtt-bsd: pass -> SKIP (fi-glk-2a) Subgroup gtt-default: pass -> SKIP (fi-glk-2a) Subgroup gtt-render: pass -> SKIP (fi-glk-2a) Subgroup gtt-vebox: pass -> SKIP (fi-glk-2a) Subgroup readonly-blt: pass -> SKIP (fi-glk-2a) Subgroup readonly-bsd: pass -> SKIP (fi-glk-2a) Subgroup readonly-default: pass -> SKIP (fi-glk-2a) Subgroup readonly-render: pass -> SKIP (fi-glk-2a) Subgroup readonly-vebox: pass -> SKIP (fi-glk-2a) Test gem_exec_create: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_exec_fence: Subgroup basic-busy-default: pass -> SKIP (fi-glk-2a) Subgroup basic-wait-default: pass -> SKIP (fi-glk-2a) Subgroup basic-await-default: pass -> SKIP (fi-glk-2a) Subgroup await-hang-default: pass -> SKIP (fi-glk-2a) Subgroup nb-await-default: pass -> SKIP (fi-glk-2a) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> SKIP (fi-glk-2a) Subgroup basic-batch-kernel-default-wb: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-pro-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-prw-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-ro-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-rw-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-set-default: pass -> SKIP (fi-glk-2a) Subgroup basic-wb-pro-default: pass -> SKIP (fi-glk-2a) WARNING: Long output truncated 7fb202bddcf81e23028f9aadcf82b732699bd527 drm-tip: 2017y-09m-16d-10h-04m-01s UTC integration manifest 08d95e829f52 HAX Enable GuC Submission for CI e2b3b402316a drm/i915/guc: Cleanup adding GuC work items 17825246e8e0 drm/i915/guc: Simplify GuC doorbell logic ee856fbc1bdd drm/i915/guc: Submit GuC workitems containing coalesced requests a65869bb678b drm/i915/guc: Remove obsolete comments and remove unused variable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5722/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/execlists: Kick start request processing after a reset
Quoting Michał Winiarski (2017-09-18 09:53:50) > On Sat, Sep 16, 2017 at 09:44:11PM +0100, Chris Wilson wrote: > > During a reset, we may skip over completed requests and lost > > context-switch interrupts. Following the reset, we may then may end up > > with no active requests in the ELSP (and so do not resubmit to restart > > the engine), but have a queue of requests ready for execution. This is > > unlikely, it requires the last request to complete after the hang is > > detected, but not impossible. The outcome of this is that the engine > > stalls, possibly leading to full ring and indefinite wait under > > struct_mutex, eventually leading to a full driver hang. > > > > Alternatively, we can solve this by unsubmitting the incomplete requests > > and just kickstarting the tasklet. Michał has patches for that, which I > > initially disliked due to the extra complexity, but the complexity of > > this "simple" restart is growing... > > You are doing exactly that in 4/4. > Perhaps squash the two together to avoid moving code around, although this one > is a genuine fix, so I guess it's also fine on its own. It was a fix that introduced the concept of calling tasklet_schedule during restart, which is then expanded on by 4/4 to do everything. I liked the progression. > If you rebase the whole thing on top of coalesced GuC requests (which now is > all > reviewed and ready to be merged), we'll have uniform reset handling for GuC > and execlists. Bugfix wins :-p Are you happy if I pull in the coalesced guc requests with this amendment: @@ -1181,7 +1182,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) */ engine->irq_tasklet.func = i915_guc_irq_handler; clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); - i915_guc_submit(engine); + tasklet_schedule(&engine->irq_tasklet); } return 0; with the desc->tail fix, guc has been stable for a day of mixed hang testing. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 4/5] drm/i915/guc: Cleanup adding GuC work items
We can just operate on the wq_tail directly (in the process descriptor).
This allows us to remove the duplicated tail from the client. While I'm
here let's also remove the constants kept in the client and document our
locking requirements. This causes a small change in one of GuC debugfs
files. We're no longer reporting constant values (which I don't think
is a problem), but we're also no longer reporting the tail (does anyone
care?).
v2: Update tail after wqi contents. (Chris)
v3: Really update tail after wqi contents.
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 --
drivers/gpu/drm/i915/i915_guc_submission.c | 37 +-
drivers/gpu/drm/i915/intel_uc.h| 4
3 files changed, 16 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 46ac6091772e..2518bdf95eef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2447,8 +2447,6 @@ static void i915_guc_client_info(struct seq_file *m,
client->priority, client->stage_id, client->proc_desc_offset);
seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
client->doorbell_id, client->doorbell_offset);
- seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
- client->wq_size, client->wq_offset, client->wq_tail);
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 16ce570a0b74..18fefc11b8d7 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -305,7 +305,7 @@ static void guc_proc_desc_init(struct intel_guc *guc,
desc->db_base_addr = 0;
desc->stage_id = client->stage_id;
- desc->wq_size_bytes = client->wq_size;
+ desc->wq_size_bytes = GUC_WQ_SIZE;
desc->wq_status = WQ_STATUS_ACTIVE;
desc->priority = client->priority;
}
@@ -390,8 +390,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
desc->process_desc = gfx_addr + client->proc_desc_offset;
- desc->wq_addr = gfx_addr + client->wq_offset;
- desc->wq_size = client->wq_size;
+ desc->wq_addr = gfx_addr + GUC_DB_SIZE;
+ desc->wq_size = GUC_WQ_SIZE;
desc->desc_private = (uintptr_t)client;
}
@@ -416,14 +416,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct i915_gem_context *ctx = rq->ctx;
struct guc_process_desc *desc = __get_process_desc(client);
struct guc_wq_item *wqi;
- u32 freespace, tail, wq_off;
+ u32 ring_tail, wq_off;
- /* Free space is guaranteed */
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- GEM_BUG_ON(freespace < wqi_size);
+ lockdep_assert_held(&client->wq_lock);
- tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
- GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
+ ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
* should not have the case where structure wqi is across page, neither
@@ -434,11 +432,11 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
- /* postincrement WQ tail for next time */
- wq_off = client->wq_tail;
+ /* Free space is guaranteed. */
+ wq_off = READ_ONCE(desc->tail);
+ GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
+ GUC_WQ_SIZE) < wqi_size);
GEM_BUG_ON(wq_off & (wqi_size - 1));
- client->wq_tail += wqi_size;
- client->wq_tail &= client->wq_size - 1;
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -451,8 +449,11 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx,
engine));
- wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
wqi->fence_id = rq->global_seqno;
+
+ /* Postincrement WQ tail for next time. */
+ WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
}
static void guc_reset_wq(struct i915_guc_client *client)
@@ -461,18 +462,14 @@ static void guc_reset_wq(struct i915_guc_client *client)
desc->head = 0;
desc->tail = 0;
-
- client->wq_tail
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable (rev4)
== Series Details == Series: series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable (rev4) URL : https://patchwork.freedesktop.org/series/30345/ State : failure == Summary == Series 30345v4 series starting with [1/5] drm/i915/guc: Remove obsolete comments and remove unused variable https://patchwork.freedesktop.org/api/1.0/series/30345/revisions/4/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> SKIP (fi-glk-2a) Test drv_hangman: Subgroup error-state-basic: pass -> SKIP (fi-glk-2a) Test gem_busy: Subgroup basic-busy-default: pass -> SKIP (fi-glk-2a) Subgroup basic-hang-default: pass -> SKIP (fi-glk-2a) Test gem_close_race: Subgroup basic-process: pass -> SKIP (fi-glk-2a) Subgroup basic-threads: pass -> SKIP (fi-glk-2a) Test gem_cpu_reloc: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_cs_tlb: Subgroup basic-default: pass -> SKIP (fi-glk-2a) Test gem_ctx_create: Subgroup basic: pass -> SKIP (fi-glk-2a) Subgroup basic-files: pass -> SKIP (fi-glk-2a) Test gem_ctx_exec: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_ctx_switch: Subgroup basic-default: pass -> SKIP (fi-glk-2a) Subgroup basic-default-heavy: pass -> SKIP (fi-glk-2a) Test gem_exec_basic: Subgroup basic-blt: pass -> SKIP (fi-glk-2a) Subgroup basic-bsd: pass -> SKIP (fi-glk-2a) Subgroup basic-default: pass -> SKIP (fi-glk-2a) Subgroup basic-render: pass -> SKIP (fi-glk-2a) Subgroup basic-vebox: pass -> SKIP (fi-glk-2a) Subgroup gtt-blt: pass -> SKIP (fi-glk-2a) Subgroup gtt-bsd: pass -> SKIP (fi-glk-2a) Subgroup gtt-default: pass -> SKIP (fi-glk-2a) Subgroup gtt-render: pass -> SKIP (fi-glk-2a) Subgroup gtt-vebox: pass -> SKIP (fi-glk-2a) Subgroup readonly-blt: pass -> SKIP (fi-glk-2a) Subgroup readonly-bsd: pass -> SKIP (fi-glk-2a) Subgroup readonly-default: pass -> SKIP (fi-glk-2a) Subgroup readonly-render: pass -> SKIP (fi-glk-2a) Subgroup readonly-vebox: pass -> SKIP (fi-glk-2a) Test gem_exec_create: Subgroup basic: pass -> SKIP (fi-glk-2a) Test gem_exec_fence: Subgroup basic-busy-default: pass -> SKIP (fi-glk-2a) Subgroup basic-wait-default: pass -> SKIP (fi-glk-2a) Subgroup basic-await-default: pass -> SKIP (fi-glk-2a) Subgroup await-hang-default: pass -> SKIP (fi-glk-2a) Subgroup nb-await-default: pass -> SKIP (fi-glk-2a) Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> SKIP (fi-glk-2a) Subgroup basic-batch-kernel-default-wb: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-pro-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-prw-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-ro-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-rw-default: pass -> SKIP (fi-glk-2a) Subgroup basic-uc-set-default: pass -> SKIP (fi-glk-2a) Subgroup basic-wb-pro-default: pass -> SKIP (fi-glk-2a) WARNING: Long output truncated 5299e24e48f3c24e612bcdb997d0dc477cdde0d0 drm-tip: 2017y-09m-18d-08h-44m-15s UTC integration manifest 64c3ff54acc4 HAX Enable GuC Submission for CI 014245b3bc97 drm/i915/guc: Cleanup adding GuC work items 081c491cce12 drm/i915/guc: Simplify GuC doorbell logic dcc489641106 drm/i915/guc: Submit GuC workitems containing coalesced requests acde6ebc373d drm/i915/guc: Remove obsolete comments and remove unused variable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5723/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/9] drm/i915/execlists: Move insert_request()
Move insert_request() earlier to avoid a forward declaration in a later
patch.
Signed-off-by: Chris Wilson
Reviewed-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20170916204414.32762-2-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 128 +++
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0f578f76f79f..7c709530b422 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -286,6 +286,70 @@ intel_lr_context_descriptor_update(struct i915_gem_context
*ctx,
ce->lrc_desc = desc;
}
+static bool
+insert_request(struct intel_engine_cs *engine,
+ struct i915_priotree *pt,
+ int prio)
+{
+ struct i915_priolist *p;
+ struct rb_node **parent, *rb;
+ bool first = true;
+
+ if (unlikely(engine->no_priolist))
+ prio = I915_PRIORITY_NORMAL;
+
+find_priolist:
+ /* most positive priority is scheduled first, equal priorities fifo */
+ rb = NULL;
+ parent = &engine->execlist_queue.rb_node;
+ while (*parent) {
+ rb = *parent;
+ p = rb_entry(rb, typeof(*p), node);
+ if (prio > p->priority) {
+ parent = &rb->rb_left;
+ } else if (prio < p->priority) {
+ parent = &rb->rb_right;
+ first = false;
+ } else {
+ list_add_tail(&pt->link, &p->requests);
+ return false;
+ }
+ }
+
+ if (prio == I915_PRIORITY_NORMAL) {
+ p = &engine->default_priolist;
+ } else {
+ p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
+ /* Convert an allocation failure to a priority bump */
+ if (unlikely(!p)) {
+ prio = I915_PRIORITY_NORMAL; /* recurses just once */
+
+ /* To maintain ordering with all rendering, after an
+* allocation failure we have to disable all scheduling.
+* Requests will then be executed in fifo, and schedule
+* will ensure that dependencies are emitted in fifo.
+* There will be still some reordering with existing
+* requests, so if userspace lied about their
+* dependencies that reordering may be visible.
+*/
+ engine->no_priolist = true;
+ goto find_priolist;
+ }
+ }
+
+ p->priority = prio;
+ rb_link_node(&p->node, rb, parent);
+ rb_insert_color(&p->node, &engine->execlist_queue);
+
+ INIT_LIST_HEAD(&p->requests);
+ list_add_tail(&pt->link, &p->requests);
+
+ if (first)
+ engine->execlist_first = &p->node;
+
+ return first;
+}
+
static inline void
execlists_context_status_change(struct drm_i915_gem_request *rq,
unsigned long status)
@@ -700,70 +764,6 @@ static void intel_lrc_irq_handler(unsigned long data)
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
}
-static bool
-insert_request(struct intel_engine_cs *engine,
- struct i915_priotree *pt,
- int prio)
-{
- struct i915_priolist *p;
- struct rb_node **parent, *rb;
- bool first = true;
-
- if (unlikely(engine->no_priolist))
- prio = I915_PRIORITY_NORMAL;
-
-find_priolist:
- /* most positive priority is scheduled first, equal priorities fifo */
- rb = NULL;
- parent = &engine->execlist_queue.rb_node;
- while (*parent) {
- rb = *parent;
- p = rb_entry(rb, typeof(*p), node);
- if (prio > p->priority) {
- parent = &rb->rb_left;
- } else if (prio < p->priority) {
- parent = &rb->rb_right;
- first = false;
- } else {
- list_add_tail(&pt->link, &p->requests);
- return false;
- }
- }
-
- if (prio == I915_PRIORITY_NORMAL) {
- p = &engine->default_priolist;
- } else {
- p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
- /* Convert an allocation failure to a priority bump */
- if (unlikely(!p)) {
- prio = I915_PRIORITY_NORMAL; /* recurses just once */
-
- /* To maintain ordering with all rendering, after an
-* allocation failure we have to disable all scheduling.
-* Requests will then be executed in fifo, and schedule
-* will ensure that dependencies are emitted in fifo.
[Intel-gfx] [CI 5/9] drm/i915/execlists: Unwind incomplete requests on resets
Given the mechanism to unwind and replay requests (designed to support
preemption), we have an alternative to the current method of
resubmitting the ELSP upon reset. Resubmitting ELSP turns out to be more
complicated than expected, due to having to handle lost context-switch
interrupts and so guessing what ELSP we need to resubmit later. Instead,
by unwinding the requests and clearing the ELSP tracking entirely, we
can then just dequeue the first pair of ready requests after resetting,
using the normal submission procedure.
Currently, the unwound requests have maximum priority and so are
guaranteed to be resubmitted upon resume. If we are lucky, we may be
able to coalesce a new request on top!
Suggested-by: Michał Winiarski
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Link:
https://patchwork.freedesktop.org/patch/msgid/20170916204414.32762-4-ch...@chris-wilson.co.uk
Reviewed-by: Michał Winiarski
---
drivers/gpu/drm/i915/intel_lrc.c | 61 +---
1 file changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be2cba6b36d1..94a89eff4dbd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1308,9 +1308,6 @@ static u8 gtiir[] = {
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- struct execlist_port *port = engine->execlist_port;
- unsigned int n;
- bool submit;
int ret;
ret = intel_mocs_init_engine(engine);
@@ -1346,26 +1343,8 @@ static int gen8_init_common_ring(struct intel_engine_cs
*engine)
engine->csb_head = -1;
/* After a GPU reset, we may have requests to replay */
- submit = false;
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
- if (!port_isset(&port[n]))
- break;
-
- DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
-engine->name, n,
-port_request(&port[n])->global_seqno);
-
- /* Discard the current inflight count */
- port_set(&port[n], port_request(&port[n]));
- submit = true;
- }
-
- if (!i915.enable_guc_submission) {
- if (submit)
- execlists_submit_ports(engine);
- else if (engine->execlist_first)
- tasklet_schedule(&engine->irq_tasklet);
- }
+ if (!i915.enable_guc_submission && engine->execlist_first)
+ tasklet_schedule(&engine->irq_tasklet);
return 0;
}
@@ -1407,9 +1386,13 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
struct drm_i915_gem_request *request)
{
struct execlist_port *port = engine->execlist_port;
+ struct drm_i915_gem_request *rq, *rn;
struct intel_context *ce;
+ unsigned long flags;
unsigned int n;
+ spin_lock_irqsave(&engine->timeline->lock, flags);
+
/*
* Catch up with any missed context-switch interrupts.
*
@@ -1419,20 +1402,28 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
* guessing the missed context-switch events by looking at what
* requests were completed.
*/
- if (!request) {
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
- return;
- }
+ for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
+ i915_gem_request_put(port_request(&port[n]));
+ memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
- if (request->ctx != port_request(port)->ctx) {
- i915_gem_request_put(port_request(port));
- port[0] = port[1];
- memset(&port[1], 0, sizeof(port[1]));
+ /* Push back any incomplete requests for replay after the reset. */
+ list_for_each_entry_safe_reverse(rq, rn,
+&engine->timeline->requests, link) {
+ struct i915_priolist *p;
+
+ if (i915_gem_request_completed(rq))
+ break;
+
+ __i915_gem_request_unsubmit(rq);
+
+ p = lookup_priolist(engine,
+ &rq->priotree,
+ rq->priotree.priority);
+ list_add(&rq->priotree.link,
+&ptr_mask_bits(p, 1)->requests);
}
- GEM_BUG_ON(request->ctx != port_request(port)->ctx);
+ spin_unlock_irqrestore(&engine->timeline->lock, flags);
/* If the request was innocent, we leave the request in the ELSP
* and will try to
[Intel-gfx] [CI 9/9] drm/i915/guc: Cleanup adding GuC work items
From: Michał Winiarski
We can just operate on the wq_tail directly (in the process descriptor).
This allows us to remove the duplicated tail from the client. While I'm
here let's also remove the constants kept in the client and document our
locking requirements. This causes a small change in one of GuC debugfs
files. We're no longer reporting constant values (which I don't think
is a problem), but we're also no longer reporting the tail (does anyone
care?).
v2: Update tail after wqi contents. (Chris)
v3: Really update tail after wqi contents.
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20170918092536.12287-1-michal.winiar...@intel.com
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 --
drivers/gpu/drm/i915/i915_guc_submission.c | 37 +-
drivers/gpu/drm/i915/intel_uc.h| 4
3 files changed, 16 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 57821dcd2001..ca6fa6d122c6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2448,8 +2448,6 @@ static void i915_guc_client_info(struct seq_file *m,
client->priority, client->stage_id, client->proc_desc_offset);
seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
client->doorbell_id, client->doorbell_offset);
- seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
- client->wq_size, client->wq_offset, client->wq_tail);
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 065832413a26..6cc33a2aab0c 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -305,7 +305,7 @@ static void guc_proc_desc_init(struct intel_guc *guc,
desc->db_base_addr = 0;
desc->stage_id = client->stage_id;
- desc->wq_size_bytes = client->wq_size;
+ desc->wq_size_bytes = GUC_WQ_SIZE;
desc->wq_status = WQ_STATUS_ACTIVE;
desc->priority = client->priority;
}
@@ -390,8 +390,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
desc->process_desc = gfx_addr + client->proc_desc_offset;
- desc->wq_addr = gfx_addr + client->wq_offset;
- desc->wq_size = client->wq_size;
+ desc->wq_addr = gfx_addr + GUC_DB_SIZE;
+ desc->wq_size = GUC_WQ_SIZE;
desc->desc_private = (uintptr_t)client;
}
@@ -416,14 +416,12 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct i915_gem_context *ctx = rq->ctx;
struct guc_process_desc *desc = __get_process_desc(client);
struct guc_wq_item *wqi;
- u32 freespace, tail, wq_off;
+ u32 ring_tail, wq_off;
- /* Free space is guaranteed */
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- GEM_BUG_ON(freespace < wqi_size);
+ lockdep_assert_held(&client->wq_lock);
- tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
- GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
+ ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
* should not have the case where structure wqi is across page, neither
@@ -434,11 +432,11 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
- /* postincrement WQ tail for next time */
- wq_off = client->wq_tail;
+ /* Free space is guaranteed. */
+ wq_off = READ_ONCE(desc->tail);
+ GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
+ GUC_WQ_SIZE) < wqi_size);
GEM_BUG_ON(wq_off & (wqi_size - 1));
- client->wq_tail += wqi_size;
- client->wq_tail &= client->wq_size - 1;
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -451,8 +449,11 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx,
engine));
- wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
wqi->fence_id = rq->global_seqno;
+
+ /* Postincrement WQ tail for next time. */
+ WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
}
static void guc_reset_wq(struct i915_guc_client *clien
[Intel-gfx] [CI 4/9] drm/i915/execlists: Split insert_request()
In the next patch we will want to reinsert a request not at the end of
the priority queue, but at the front. Here we split insert_request()
into two, the first function retrieves the priority list (for reuse for
unsubmit later) and a wrapper function to insert at the end of that list
and to schedule the tasklet if we were first.
Signed-off-by: Chris Wilson
Reviewed-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20170916204414.32762-3-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 35 +++
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7c709530b422..be2cba6b36d1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -286,10 +286,10 @@ intel_lr_context_descriptor_update(struct
i915_gem_context *ctx,
ce->lrc_desc = desc;
}
-static bool
-insert_request(struct intel_engine_cs *engine,
- struct i915_priotree *pt,
- int prio)
+static struct i915_priolist *
+lookup_priolist(struct intel_engine_cs *engine,
+ struct i915_priotree *pt,
+ int prio)
{
struct i915_priolist *p;
struct rb_node **parent, *rb;
@@ -311,8 +311,7 @@ insert_request(struct intel_engine_cs *engine,
parent = &rb->rb_right;
first = false;
} else {
- list_add_tail(&pt->link, &p->requests);
- return false;
+ return p;
}
}
@@ -338,16 +337,14 @@ insert_request(struct intel_engine_cs *engine,
}
p->priority = prio;
+ INIT_LIST_HEAD(&p->requests);
rb_link_node(&p->node, rb, parent);
rb_insert_color(&p->node, &engine->execlist_queue);
- INIT_LIST_HEAD(&p->requests);
- list_add_tail(&pt->link, &p->requests);
-
if (first)
engine->execlist_first = &p->node;
- return first;
+ return ptr_pack_bits(p, first, 1);
}
static inline void
@@ -764,6 +761,17 @@ static void intel_lrc_irq_handler(unsigned long data)
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
}
+static void insert_request(struct intel_engine_cs *engine,
+ struct i915_priotree *pt,
+ int prio)
+{
+ struct i915_priolist *p = lookup_priolist(engine, pt, prio);
+
+ list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
+ if (ptr_unmask_bits(p, 1) && execlists_elsp_ready(engine))
+ tasklet_hi_schedule(&engine->irq_tasklet);
+}
+
static void execlists_submit_request(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
@@ -772,12 +780,7 @@ static void execlists_submit_request(struct
drm_i915_gem_request *request)
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(&engine->timeline->lock, flags);
- if (insert_request(engine,
- &request->priotree,
- request->priotree.priority)) {
- if (execlists_elsp_ready(engine))
- tasklet_hi_schedule(&engine->irq_tasklet);
- }
+ insert_request(engine, &request->priotree, request->priotree.priority);
GEM_BUG_ON(!engine->execlist_first);
GEM_BUG_ON(list_empty(&request->priotree.link));
--
2.14.1
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[Intel-gfx] [CI 7/9] drm/i915/guc: Submit GuC workitems containing coalesced requests
From: Michał Winiarski
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition). This allows us to completely
remove the reservation, replacing it with a compile time check.
v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)
v4: Squash removing wq_resv
v5: Reflect i915_guc_submit argument changes in doc
v6: Rebase on top of execlists reset/restart fix (Chris)
References: https://bugs.freedesktop.org/show_bug.cgi?id=101873
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Jeff McGee
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20170914083216.10192-2-michal.winiar...@intel.com
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 -
drivers/gpu/drm/i915/i915_guc_submission.c | 181 ++---
drivers/gpu/drm/i915/intel_lrc.c | 25 +---
drivers/gpu/drm/i915/intel_uc.h| 11 --
4 files changed, 63 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 62133dd303ac..0364f0d2d76e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2451,8 +2451,6 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
- seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
tot += submissions;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c180ff1423fd..16b31f70114e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -406,63 +406,6 @@ static void guc_stage_desc_fini(struct intel_guc *guc,
memset(desc, 0, sizeof(*desc));
}
-/**
- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
- * @request: request associated with the commands
- *
- * Return: 0 if space is available
- * -EAGAIN if space is not currently available
- *
- * This function must be called (and must return 0) before a request
- * is submitted to the GuC via i915_guc_submit() below. Once a result
- * of 0 has been returned, it must be balanced by a corresponding
- * call to submit().
- *
- * Reservation allows the caller to determine in advance that space
- * will be available for the next submission before committing resources
- * to it, and helps avoid late failures with complicated recovery paths.
- */
-int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
-{
- const size_t wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
- struct guc_process_desc *desc = __get_process_desc(client);
- u32 freespace;
- int ret;
-
- spin_lock_irq(&client->wq_lock);
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- freespace -= client->wq_rsvd;
- if (likely(freespace >= wqi_size)) {
- client->wq_rsvd += wqi_size;
- ret = 0;
- } else {
- client->no_wq_space++;
- ret = -EAGAIN;
- }
- spin_unlock_irq(&client->wq_lock);
-
- return ret;
-}
-
-static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&client->wq_lock, flags);
- client->wq_rsvd += size;
- spin_unlock_irqrestore(&client->wq_lock, flags);
-}
-
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
-{
- const int wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
-
- GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
- guc_client_update_wq_rsvd(client, -wqi_size);
-}
-
/* Construct a Work Item and append it to the GuC's Work Queue */
static void guc_wq_item_append(struct i915_guc_client *client,
struct drm_i915_gem_request *rq)
@@ -476,7 +419,7 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct guc_wq_item *wqi;
u32 freespace, tail, wq_off;
- /* Free space is guaranteed, see i915_guc_wq_reserve() above */
+ /* Free space is guaranteed */
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
GEM_BUG_ON(freespac
[Intel-gfx] [CI 1/9] drm/i915: Cancel all ready but queued requests when wedging
When wedging the hw, we want to mark all in-flight requests as -EIO.
This is made slightly more complex by execlists who store the ready but
not yet submitted-to-hw requests on a private queue (an rbtree
priolist). Call into execlists to cancel not only the ELSP tracking for
the submitted requests, but also the queue of unsubmitted requests.
v2: Move the majority of engine_set_wedged to the backends (both legacy
ringbuffer and execlists handling their own lists).
Reported-by: Michał Winiarski
Testcase: igt/gem_eio/in-flight-contexts
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Link:
https://patchwork.freedesktop.org/patch/msgid/20170915173100.26470-1-ch...@chris-wilson.co.uk
Reviewed-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem.c | 38 +
drivers/gpu/drm/i915/intel_lrc.c| 60 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 +++
drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +
4 files changed, 89 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3250dfaa192b..c4bf34865fa3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3022,9 +3022,6 @@ static void nop_submit_request(struct
drm_i915_gem_request *request)
static void engine_set_wedged(struct intel_engine_cs *engine)
{
- struct drm_i915_gem_request *request;
- unsigned long flags;
-
/* We need to be sure that no thread is running the old callback as
* we install the nop handler (otherwise we would submit a request
* to hardware that will never complete). In order to prevent this
@@ -3034,40 +3031,7 @@ static void engine_set_wedged(struct intel_engine_cs
*engine)
engine->submit_request = nop_submit_request;
/* Mark all executing requests as skipped */
- spin_lock_irqsave(&engine->timeline->lock, flags);
- list_for_each_entry(request, &engine->timeline->requests, link)
- if (!i915_gem_request_completed(request))
- dma_fence_set_error(&request->fence, -EIO);
- spin_unlock_irqrestore(&engine->timeline->lock, flags);
-
- /*
-* Clear the execlists queue up before freeing the requests, as those
-* are the ones that keep the context and ringbuffer backing objects
-* pinned in place.
-*/
-
- if (i915.enable_execlists) {
- struct execlist_port *port = engine->execlist_port;
- unsigned long flags;
- unsigned int n;
-
- spin_lock_irqsave(&engine->timeline->lock, flags);
-
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
- engine->execlist_queue = RB_ROOT;
- engine->execlist_first = NULL;
-
- spin_unlock_irqrestore(&engine->timeline->lock, flags);
-
- /* The port is checked prior to scheduling a tasklet, but
-* just in case we have suspended the tasklet to do the
-* wedging make sure that when it wakes, it decides there
-* is no work to do by clearing the irq_posted bit.
-*/
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- }
+ engine->cancel_requests(engine);
/* Mark all pending requests as complete so that any concurrent
* (lockless) lookup doesn't try and wait upon the request as we
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1960ba5ff9e4..8e5caa5d3973 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -506,6 +506,65 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists_submit_ports(engine);
}
+static void execlists_cancel_requests(struct intel_engine_cs *engine)
+{
+ struct execlist_port *port = engine->execlist_port;
+ struct drm_i915_gem_request *rq, *rn;
+ struct rb_node *rb;
+ unsigned long flags;
+ unsigned long n;
+
+ spin_lock_irqsave(&engine->timeline->lock, flags);
+
+ /* Cancel the requests on the HW and clear the ELSP tracker. */
+ for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
+ i915_gem_request_put(port_request(&port[n]));
+ memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
+
+ /* Mark all executing requests as skipped. */
+ list_for_each_entry(rq, &engine->timeline->requests, link) {
+ GEM_BUG_ON(!rq->global_seqno);
+ if (!i915_gem_request_completed(rq))
+ dma_fence_set_error(&rq->fence, -EIO);
+ }
+
+ /* Flush the queued requests to the timeline list (for retiring). */
+ rb =
[Intel-gfx] [CI 2/9] drm/i915/execlists: Kick start request processing after a reset
During a reset, we may skip over completed requests and lost
context-switch interrupts. Following the reset, we may then may end up
with no active requests in the ELSP (and so do not resubmit to restart
the engine), but have a queue of requests ready for execution. This is
unlikely, it requires the last request to complete after the hang is
detected, but not impossible. The outcome of this is that the engine
stalls, possibly leading to full ring and indefinite wait under
struct_mutex, eventually leading to a full driver hang.
Alternatively, we can solve this by unsubmitting the incomplete requests
and just kickstarting the tasklet. Michał has patches for that, which I
initially disliked due to the extra complexity, but the complexity of
this "simple" restart is growing...
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Link:
https://patchwork.freedesktop.org/patch/msgid/20170916204414.32762-1-ch...@chris-wilson.co.uk
Reviewed-by: Michał Winiarski
---
drivers/gpu/drm/i915/intel_lrc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8e5caa5d3973..0f578f76f79f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1357,8 +1357,12 @@ static int gen8_init_common_ring(struct intel_engine_cs
*engine)
submit = true;
}
- if (submit && !i915.enable_guc_submission)
- execlists_submit_ports(engine);
+ if (!i915.enable_guc_submission) {
+ if (submit)
+ execlists_submit_ports(engine);
+ else if (engine->execlist_first)
+ tasklet_schedule(&engine->irq_tasklet);
+ }
return 0;
}
--
2.14.1
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[Intel-gfx] [CI 6/9] drm/i915/guc: Remove obsolete comments and remove unused variable
From: Michał Winiarski
Originally removed in:
c1adab970348 ("drm/i915/guc: Remove failed doorbell stat from debugfs")
f1448a62a103 ("drm/i915/guc: Remove last submission result from debugfs")
Were accidentally restored in:
925344ccc91d ("BackMerge tag 'v4.12-rc5' into drm-next")
We can also remove unused variable and replace it with a WARN.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20170914083216.10192-1-michal.winiar...@intel.com
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 +--
drivers/gpu/drm/i915/intel_uc.h| 4
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index b28677e5a4f2..c180ff1423fd 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -601,7 +601,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
struct intel_guc *guc = &rq->i915->guc;
struct i915_guc_client *client = guc->execbuf_client;
unsigned long flags;
- int b_ret;
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
@@ -610,7 +609,7 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
spin_lock_irqsave(&client->wq_lock, flags);
guc_wq_item_append(client, rq);
- b_ret = guc_ring_doorbell(client);
+ WARN_ON(guc_ring_doorbell(client));
client->submissions[engine_id] += 1;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b17b0f..69daf4c01cd0 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -59,10 +59,6 @@ struct drm_i915_gem_request;
*available in the work queue (note, the queue is shared,
*not per-engine). It is OK for this to be nonzero, but
*it should not be huge!
- * b_fail: failed to ring the doorbell. This should never happen, unless
- * somehow the hardware misbehaves, or maybe if the GuC firmware
- * crashes? We probably need to reset the GPU to recover.
- * retcode: errno from last guc_submit()
*/
struct i915_guc_client {
struct i915_vma *vma;
--
2.14.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 8/9] drm/i915/guc: Simplify GuC doorbell logic
From: Michał Winiarski
All we're really doing is incrementing a simple counter in a
doorbell_info struct. We can do without extra variables and a separate
counter kept in guc_client. Since it's gone, we're also removing its
debugfs.
The only functional change here, is that we're no longer treating 0 as a
special value. GuC doesn't seem to care, why should we?
v2: Restore desc->tail update.
v3: Drop the retry loop, assert that doorbell cookie doesn't change
behind our back.
v4: WARN rather than BUG, use xchg. (Chris)
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Suggested-by: Chris Wilson
Signed-off-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20170914105125.3031-1-michal.winiar...@intel.com
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 60 +++---
drivers/gpu/drm/i915/intel_uc.h| 1 -
3 files changed, 15 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0364f0d2d76e..57821dcd2001 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2446,8 +2446,8 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
client->priority, client->stage_id, client->proc_desc_offset);
- seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
- client->doorbell_id, client->doorbell_offset,
client->doorbell_cookie);
+ seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
+ client->doorbell_id, client->doorbell_offset);
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 16b31f70114e..065832413a26 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -192,13 +192,12 @@ static int __create_doorbell(struct i915_guc_client
*client)
doorbell = __get_doorbell(client);
doorbell->db_status = GUC_DOORBELL_ENABLED;
- doorbell->cookie = client->doorbell_cookie;
+ doorbell->cookie = 0;
err = __guc_allocate_doorbell(client->guc, client->stage_id);
- if (err) {
+ if (err)
doorbell->db_status = GUC_DOORBELL_DISABLED;
- doorbell->cookie = 0;
- }
+
return err;
}
@@ -466,57 +465,24 @@ static void guc_reset_wq(struct i915_guc_client *client)
client->wq_tail = 0;
}
-static int guc_ring_doorbell(struct i915_guc_client *client)
+static void guc_ring_doorbell(struct i915_guc_client *client)
{
struct guc_process_desc *desc = __get_process_desc(client);
- union guc_doorbell_qw db_cmp, db_exc, db_ret;
- union guc_doorbell_qw *db;
- int attempt = 2, ret = -EAGAIN;
+ struct guc_doorbell_info *db;
+ u32 cookie;
/* Update the tail so it is visible to GuC */
desc->tail = client->wq_tail;
- /* current cookie */
- db_cmp.db_status = GUC_DOORBELL_ENABLED;
- db_cmp.cookie = client->doorbell_cookie;
-
- /* cookie to be updated */
- db_exc.db_status = GUC_DOORBELL_ENABLED;
- db_exc.cookie = client->doorbell_cookie + 1;
- if (db_exc.cookie == 0)
- db_exc.cookie = 1;
-
/* pointer of current doorbell cacheline */
- db = (union guc_doorbell_qw *)__get_doorbell(client);
-
- while (attempt--) {
- /* lets ring the doorbell */
- db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
- db_cmp.value_qw, db_exc.value_qw);
-
- /* if the exchange was successfully executed */
- if (db_ret.value_qw == db_cmp.value_qw) {
- /* db was successfully rung */
- client->doorbell_cookie = db_exc.cookie;
- ret = 0;
- break;
- }
-
- /* XXX: doorbell was lost and need to acquire it again */
- if (db_ret.db_status == GUC_DOORBELL_DISABLED)
- break;
+ db = __get_doorbell(client);
- DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
-db_cmp.cookie, db_ret.cookie);
+ /* we're not expecting the doorbell cookie to change behind our back */
+ cookie = READ_ONCE(db->cookie);
+ WARN_ON_ONCE(xchg(&db->cookie, cookie + 1) != cookie);
- /* update the cookie to newly read cookie from GuC */
- db_cmp.cookie = db_ret.cookie;
- db_exc.cookie = db_ret.cookie + 1;
- if (db_exc.cookie == 0)
-
[Intel-gfx] [PATCH 2/8] drm/i915/guc: Create intel_guc_init_early
Prepared intel_guc_init_early for GuC Specific early
initialization to be done from intel_uc_init_early.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 499ecf3..af4bc3b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -101,10 +101,8 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
-void intel_uc_init_early(struct drm_i915_private *dev_priv)
+static void intel_guc_init_early(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
-
intel_guc_ct_init_early(&guc->ct);
mutex_init(&guc->send_mutex);
@@ -112,6 +110,11 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
guc->notify = gen8_guc_raise_irq;
}
+void intel_uc_init_early(struct drm_i915_private *dev_priv)
+{
+ intel_guc_init_early(&dev_priv->guc);
+}
+
static void fetch_uc_fw(struct drm_i915_private *dev_priv,
struct intel_uc_fw *uc_fw)
{
--
1.9.1
___
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[Intel-gfx] [PATCH 5/8] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path
Teardown of GuC HW/SW state was not properly done in unload path.
guc_submission_disable was called as part of intel_uc_fini_hw which
happens post gem_unload in the i915_driver_unload path.
s/i915_gem_fini/i915_gem_cleanup as it looks more suitable as that
function does cleanup.
To differentiate the tasks during suspend and unload w.r.t GuC this
patch introduces new function i915_gem_fini which in addition to
disabling GuC interfaces also disables GuC submission during which
communication with GuC is needed for destroying doorbell.
i915_gem_fini is copy of i915_gem_suspend with difference w.r.t
GuC operations. To achieve this, new helpers i915_gem_context_suspend
and i915_gem_suspend_complete are prepared.
This patch updates the functions responsibilities as follows:
1. intel_uc_fini_hw: Disable all things that involve communication with
GuC and internal operation of GuC firmware, currently submission.
Post this disable all other state like guc_ggtt_invalidate,
guc_communication and guc_interrupts.
2. intel_uc_cleanup: Free up all UC related memory and other data.
v2: Prepared i915_gem_unload. (Michal)
v3: Moved guc_free_load_err_log past i915.enable_guc_loading check in
intel_uc_cleanup_hw. Prepared i915_gem_contexts_suspend and
i915_gem_suspend_complete that are used in the two paths
i915_gem_suspend and i915_gem_unload. Unload specific actions like
disabling GuC submission and GuC communication are being done in
i915_gem_unload. Commit message update. (Michał Winiarski)
v4: prepared i915_gem_cleanup and intel_uc_cleanup.
v5: Rebase as intel_guc.h is removed. Kept guc_capture_load_err_log in
intel_uc.c as it is not needed anywhere else. (Sagar)
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 52
drivers/gpu/drm/i915/intel_guc.c | 32 +
drivers/gpu/drm/i915/intel_uc.c | 28 --
drivers/gpu/drm/i915/intel_uc.h | 3 +++
6 files changed, 94 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f41f0e0..ac1f92a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -596,13 +596,13 @@ static bool i915_switcheroo_can_switch(struct pci_dev
*pdev)
.can_switch = i915_switcheroo_can_switch,
};
-static void i915_gem_fini(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup(struct drm_i915_private *dev_priv)
{
/* Flush any outstanding unpin_work. */
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
+ intel_uc_cleanup(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
@@ -683,9 +683,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_fini(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
- i915_gem_fini(dev_priv);
+ i915_gem_cleanup(dev_priv);
cleanup_uc:
intel_uc_fini_fw(dev_priv);
cleanup_irq:
@@ -1376,7 +1376,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_fini(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -1410,7 +1410,7 @@ void i915_driver_unload(struct drm_device *dev)
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
i915_reset_error_state(dev_priv);
- i915_gem_fini(dev_priv);
+ i915_gem_cleanup(dev_priv);
intel_uc_fini_fw(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b735b6..3806e63 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3669,6 +3669,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags);
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_fini(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_fault(struct vm_fault *vmf);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ae97a6f..19f3da2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4545,12 +4545,11 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
}
}
-int i915_
[Intel-gfx] [PATCH 3/8] drm/i915/guc: Create intel_guc.c for defining GuC specific functionality
Create intel_guc.c and added GuC specific functionality from
intel_uc.c. Moved below functions to intel_guc.c.
1. intel_guc_send_nop
2. gen8_guc_raise_irq
3. intel_guc_init_early
4. guc_send_regs
5. intel_guc_init_send_regs
6. intel_guc_send_mmio
7. intel_guc_sample_forcewake
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/intel_guc.c | 146 +++
drivers/gpu/drm/i915/intel_uc.c | 121
drivers/gpu/drm/i915/intel_uc.h | 11 +--
4 files changed, 154 insertions(+), 125 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1cb8059..e13fc19 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -59,6 +59,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
+ intel_guc.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 000..d8b3559
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
+{
+ WARN(1, "Unexpected send: action=%#x\n", *action);
+ return -ENODEV;
+}
+
+static void gen8_guc_raise_irq(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+}
+
+void intel_guc_init_early(struct intel_guc *guc)
+{
+ intel_guc_ct_init_early(&guc->ct);
+
+ mutex_init(&guc->send_mutex);
+ guc->send = intel_guc_send_nop;
+ guc->notify = gen8_guc_raise_irq;
+}
+
+static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
+{
+ GEM_BUG_ON(!guc->send_regs.base);
+ GEM_BUG_ON(!guc->send_regs.count);
+ GEM_BUG_ON(i >= guc->send_regs.count);
+
+ return _MMIO(guc->send_regs.base + 4 * i);
+}
+
+void intel_guc_init_send_regs(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ enum forcewake_domains fw_domains = 0;
+ unsigned int i;
+
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
+
+ for (i = 0; i < guc->send_regs.count; i++) {
+ fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+ guc_send_reg(guc, i),
+ FW_REG_READ | FW_REG_WRITE);
+ }
+ guc->send_regs.fw_domains = fw_domains;
+}
+
+/*
+ * This function implements the MMIO based host to GuC interface.
+ */
+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ u32 status;
+ int i;
+ int ret;
+
+ GEM_BUG_ON(!len);
+ GEM_BUG_ON(len > guc->send_regs.count);
+
+ /* If CT is available, we expect to use MMIO only during init/fini */
+ GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
+ *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
+ *action !=
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
+
+ mutex_lock(&guc->send_mutex);
+ intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
+
+ for (i = 0; i < len; i++)
+ I915_WRITE(guc_send_reg(guc, i), action[i]);
+
+ POSTING_READ(guc_send_reg(guc, i - 1));
+
+ intel_guc_notify(guc);
+
+ /*
+* No GuC command should ever take longer than 10ms.
+
[Intel-gfx] [PATCH 4/8] drm/i915/guc: Fix GuC interaction in reset/suspend scenarios
Pass intel_guc to intel_guc_suspend/resume instead of drm_i915_private.
guc_ggtt_invalidate/guc_interrupts should be disabled towards
end of reset/suspend post GuC suspension as these are setup back again
during recovery/resume.
Prepared helpers intel_guc_pause and intel_guc_unpause that will do
teardown/bringup of this setup along with suspension/resumption of GuC if
loaded. These helpers can then be used along the system or runtime
suspend/resume paths as applicable. Currently post system resume, since
GuC is loaded completely system_resume function for GuC is doing
nothing. We rely on the setup happening in intel_uc_init_hw path.
During runtime_suspend we will call intel_guc_pause helper.
Another helper added is intel_guc_reset_prepare, this will make sure that
disabling of ggtt_invalidate and GuC interrupts happens prior to reset and
updates the firmware load status to PENDING.
v2: Updated commit message. Added note about skipped call to
intel_guc_system_resume. guc_enable/disable_communication was moved to
earlier patch so corresponding rebase. (Michal Wajdeczko)
v3: Introduction of intel_uc_runtime/system_suspend/resume. Updated
changes for enable/disable_communication.
v4: Squashed change to update parameters of intel_guc_suspend/resume from
earlier patch.
v5: Rebase as intel_guc.h is removed. Updated intel_uc_runtime_resume and
intel_uc_system_resume as guc_enable_communication should happen prior to
resuming the uc. Thanks to trybot for catching this. (Sagar)
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c| 15 +++-
drivers/gpu/drm/i915/i915_gem.c| 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 52
drivers/gpu/drm/i915/intel_guc.c | 129 +
drivers/gpu/drm/i915/intel_uc.c| 53
drivers/gpu/drm/i915/intel_uc.h| 12 ++-
6 files changed, 206 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5c111ea..f41f0e0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1684,6 +1684,11 @@ static int i915_drm_resume(struct drm_device *dev)
drm_mode_config_reset(dev);
+ /*
+* NB: Full gem reinitialization is being done during i915_drm_resume,
+* hence intel_guc_system_resume will be of no use. If full
+* reinitialization is avoided, need to call intel_guc_system_resume.
+*/
mutex_lock(&dev->struct_mutex);
if (i915_gem_init_hw(dev_priv)) {
DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
@@ -1691,8 +1696,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(&dev->struct_mutex);
- intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
spin_lock_irq(&dev_priv->irq_lock);
@@ -2493,7 +2496,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ intel_uc_runtime_suspend(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2578,7 +2581,11 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
- intel_guc_resume(dev_priv);
+ ret = intel_uc_runtime_resume(dev_priv);
+ if (ret) {
+ DRM_ERROR("uc runtime resume failed (%d)\n", ret);
+ return ret;
+ }
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3250dfa..ae97a6f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2847,6 +2847,8 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
i915_gem_revoke_fences(dev_priv);
+ intel_uc_reset_prepare(dev_priv);
+
return err;
}
@@ -4575,7 +4577,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
+ intel_uc_system_suspend(dev_priv);
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 3f9d227..f527963 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1205,55 +1205,3 @@ void i915_guc_submission_disable(struct drm_i915_private
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device priva
[Intel-gfx] [PATCH 7/8] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default always. It should
be noted that streaming support with half-full interrupt mechanism
that is present for normal logging is not present for this type of
logging.
v2: Emulated GuC critical logging through i915.guc_log_level.
v3: Commit message update. Enable default/critical logging in GuC always.
Fixed RPM wake during guc_log_unregister in the unload path.
v4: Moved RPM wake change to separate patch. Removed GUC_DEBUG_RESERVED
and updated name of new bit to be version agnostic. Updated parameter to
struct intel_guc * and name of macro NEEDS_GUC_CRITICAL_LOGGING.
Removed explicit clearing of GUC_CRITICAL_LOGGING_DISABLED from
params[GUC_CTL_DEBUG] as it is unnecessary. (Michal Wajdeczko)
v5: Removed GUC_CRITICAL_LOGGING_DISABLED. Added HAS_GUC check to
GUC_NEEDS_CRITICAL_LOGGING. (Michal Wajdeczko)
v6: More refined version of GUC_NEEDS_CRITICAL_LOGGING. Commit message
update. (Michal Wajdeczko)
Cc: Chheda Harsh J
Cc: Fry Gregory P
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 4 ++--
drivers/gpu/drm/i915/intel_guc_log.c | 13 -
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 7eb6b4f..fed875a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -127,7 +127,6 @@
#define GUC_PROFILE_ENABLED (1 << 7)
#define GUC_WQ_TRACK_ENABLED (1 << 8)
#define GUC_ADS_ENABLED (1 << 9)
-#define GUC_DEBUG_RESERVED (1 << 10)
#define GUC_ADS_ADDR_SHIFT 11
#define GUC_ADS_ADDR_MASK0xf800
@@ -539,7 +538,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
- u32 reserved2:24;
+ u32 critical_logging_enabled:1;
+ u32 reserved2:23;
};
u32 value;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 3c45681..b820175 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -586,10 +586,18 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(&guc->log.vma);
}
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define GUC_NEEDS_CRITICAL_LOGGING(guc)\
+ (HAS_GUC(guc_to_i915(guc)) && \
+(guc->fw.major_ver_found >= 9) && \
+(guc->fw.minor_ver_found >= (IS_KABYLAKE(guc_to_i915(guc)) ? 39 : 0)))
+
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
{
struct intel_guc *guc = &dev_priv->guc;
-
union guc_log_control log_param;
int ret;
@@ -603,6 +611,9 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;
+ if (GUC_NEEDS_CRITICAL_LOGGING(guc))
+ log_param.critical_logging_enabled = 1;
+
ret = guc_log_control(guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw
s/guc_init_send_regs/intel_guc_init_send_regs.
Added declaration in intel_uc.h. Calling it from intel_uc_init_hw as it
is one time setup.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/intel_uc.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..499ecf3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -271,7 +271,7 @@ static inline i915_reg_t guc_send_reg(struct intel_guc
*guc, u32 i)
return _MMIO(guc->send_regs.base + 4 * i);
}
-static void guc_init_send_regs(struct intel_guc *guc)
+void intel_guc_init_send_regs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
enum forcewake_domains fw_domains = 0;
@@ -309,8 +309,6 @@ static int guc_enable_communication(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- guc_init_send_regs(guc);
-
if (HAS_GUC_CT(dev_priv))
return intel_guc_enable_ct(guc);
@@ -386,6 +384,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_log_capture;
+ intel_guc_init_send_regs(guc);
+
ret = guc_enable_communication(guc);
if (ret)
goto err_log_capture;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 7703c9a..77e6d83 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -211,6 +211,7 @@ struct intel_huc {
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+void intel_guc_init_send_regs(struct intel_guc *guc);
static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32
len)
{
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: Reorganize HuC authentication
Prepared intel_auth_huc to separate HuC specific functionality
from GuC send action. Created new header intel_huc.h to group
HuC specific declarations.
v2: Changed argument preparation for AUTHENTICATE_HUC.
s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h
to later patch.
v3: Rebase as intel_guc.h is removed. Added param description to
intel_huc_auth. (Michal)
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc.c | 18 ++
drivers/gpu/drm/i915/intel_huc.c | 22 +++---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
drivers/gpu/drm/i915/intel_uc.h | 3 ++-
4 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 273b18b..f147fdd 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -305,3 +305,21 @@ void intel_guc_cleanup(struct intel_guc *guc)
if (i915.enable_guc_submission)
i915_guc_submission_fini(dev_priv);
}
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @guc: struct intel_guc*
+ * @offset: rsa offset w.r.t ggtt base of huc vma
+ *
+ * triggers a huc fw authentication request to the guc via intel_guc_send
+ * authenticate_huc interface.
+ */
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_AUTHENTICATE_HUC,
+ rsa_offset
+ };
+
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+}
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0..d3da4d3 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -225,19 +225,16 @@ void intel_huc_init_hw(struct intel_huc *huc)
}
/**
- * intel_guc_auth_huc() - authenticate ucode
- * @dev_priv: the drm_i915_device
- *
- * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
- * authenticate_huc interface.
+ * intel_huc_auth() - authenticate ucode
+ * @huc: intel_huc structure
*/
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+void intel_huc_auth(struct intel_huc *huc)
{
+ struct drm_i915_private *dev_priv = huc_to_i915(huc);
struct intel_guc *guc = &dev_priv->guc;
- struct intel_huc *huc = &dev_priv->huc;
struct i915_vma *vma;
+ u32 offset;
int ret;
- u32 data[2];
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return;
@@ -250,11 +247,8 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
return;
}
- /* Specify auth action and where public signature is. */
- data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
- data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
-
- ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+ offset = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
+ ret = intel_guc_auth_huc(guc, offset);
if (ret) {
DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
goto out;
@@ -266,7 +260,6 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
HUC_FW_VERIFIED,
HUC_FW_VERIFIED,
50);
-
if (ret) {
DRM_ERROR("HuC: Authentication failed %d\n", ret);
goto out;
@@ -275,4 +268,3 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
out:
i915_vma_unpin(vma);
}
-
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index a06719c..1c5ba7c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -343,7 +343,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_log_capture;
- intel_guc_auth_huc(dev_priv);
+ intel_huc_auth(&dev_priv->huc);
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 7bdab01..87176a6 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -238,6 +238,7 @@ static inline void intel_guc_notify(struct intel_guc *guc)
int intel_guc_system_resume(struct intel_guc *guc);
void intel_guc_fini_hw(struct intel_guc *guc);
void intel_guc_cleanup(struct intel_guc *guc);
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
/* intel_guc_loader.c */
int intel_guc_select_fw(struct intel_guc *guc);
@@ -268,6 +269,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
/* intel_huc.c */
void intel_huc_select_fw(struct intel_huc *huc);
void intel_huc_init_hw(struct intel_huc *huc);
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
+void intel_huc_auth(struct intel_hu
[Intel-gfx] [PATCH 6/8] drm/i915/guc: Remove i915_guc_log_unregister
Functionality needed to disable GuC interrupts and cleanup the
runtime/relay data structures is already covered in the unload path
via intel_guc_fini_hw and intel_guc_cleanup hence remove
i915_guc_log_unregister
v2: Removed the function i915_guc_log_unregister.
v3: Rebase as intel_guc.h is removed.
Cc: Michal Wajdeczko
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/intel_guc_log.c | 12
drivers/gpu/drm/i915/intel_uc.h | 1 -
3 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ac1f92a..7bd9756 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1252,7 +1252,6 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
i915_perf_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
- i915_guc_log_unregister(dev_priv);
drm_dev_unregister(&dev_priv->drm);
i915_gem_shrinker_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..3c45681 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -648,15 +648,3 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
guc_log_late_setup(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
-
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
-{
- if (!i915.enable_guc_submission)
- return;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
- /* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
- guc_log_runtime_destroy(&dev_priv->guc);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 46a7d7a..7bdab01 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -256,7 +256,6 @@ static inline void intel_guc_notify(struct intel_guc *guc)
void intel_guc_log_destroy(struct intel_guc *guc);
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
void i915_guc_log_register(struct drm_i915_private *dev_priv);
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2.
Commit b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.") removed
the call to wait_for_vblanks and replaced it with flip_done.
Unfortunately legacy_cursor_update was unset too late, and the
replacement call drm_atomic_helper_wait_for_flip_done() was
a noop. Make sure that its unset before setup_commit() is
called to fix this issue.
Changes since v1:
- Force vblank wait for watermarks not yet converted to atomic too. (Ville)
- Use for_each_new_intel_crtc_in_state. (Ville)
Signed-off-by: Maarten Lankhorst
Fixes: b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102675
Testcase: kms_cursor_crc
Cc: Daniel Vetter
Cc: Jani Nikula
Reported-by: Marta Löfstedt
Cc: Marta Löfstedt
Tested-by: Marta Löfstedt
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 45 +---
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8599e425abb1..8d051256da1e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12517,21 +12517,10 @@ static int intel_atomic_commit(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
- ret = drm_atomic_helper_setup_commit(state, nonblock);
- if (ret)
- return ret;
-
drm_atomic_state_get(state);
i915_sw_fence_init(&intel_state->commit_ready,
intel_atomic_commit_ready);
- ret = intel_atomic_prepare_commit(dev, state);
- if (ret) {
- DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
- i915_sw_fence_commit(&intel_state->commit_ready);
- return ret;
- }
-
/*
* The intel_legacy_cursor_update() fast path takes care
* of avoiding the vblank waits for simple cursor
@@ -12540,19 +12529,37 @@ static int intel_atomic_commit(struct drm_device *dev,
* updates happen during the correct frames. Gen9+ have
* double buffered watermarks and so shouldn't need this.
*
-* Do this after drm_atomic_helper_setup_commit() and
-* intel_atomic_prepare_commit() because we still want
-* to skip the flip and fb cleanup waits. Although that
-* does risk yanking the mapping from under the display
-* engine.
+* Unset state->legacy_cursor_update before the call to
+* drm_atomic_helper_setup_commit() because otherwise
+* drm_atomic_helper_wait_for_flip_done() is a noop and
+* we get FIFO underruns because we didn't wait
+* for vblank.
*
* FIXME doing watermarks and fb cleanup from a vblank worker
* (assuming we had any) would solve these problems.
*/
- if (INTEL_GEN(dev_priv) < 9)
- state->legacy_cursor_update = false;
+ if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(intel_state, crtc,
new_crtc_state, i)
+ if (new_crtc_state->wm.need_postvbl_update ||
+ new_crtc_state->update_wm_post)
+ state->legacy_cursor_update = false;
+ }
+
+ ret = intel_atomic_prepare_commit(dev, state);
+ if (ret) {
+ DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
+ i915_sw_fence_commit(&intel_state->commit_ready);
+ return ret;
+ }
+
+ ret = drm_atomic_helper_setup_commit(state, nonblock);
+ if (!ret)
+ ret = drm_atomic_helper_swap_state(state, true);
- ret = drm_atomic_helper_swap_state(state, true);
if (ret) {
i915_sw_fence_commit(&intel_state->commit_ready);
--
2.14.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw
On Mon, 18 Sep 2017 12:11:24 +0200, Sagar Arun Kamble
wrote:
s/guc_init_send_regs/intel_guc_init_send_regs.
Added declaration in intel_uc.h. Calling it from intel_uc_init_hw as it
is one time setup.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/intel_uc.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..499ecf3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -271,7 +271,7 @@ static inline i915_reg_t guc_send_reg(struct
intel_guc *guc, u32 i)
return _MMIO(guc->send_regs.base + 4 * i);
}
-static void guc_init_send_regs(struct intel_guc *guc)
+void intel_guc_init_send_regs(struct intel_guc *guc)
Hmm, there is no reason to export this function now, as it called
by the function defined below.
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
enum forcewake_domains fw_domains = 0;
@@ -309,8 +309,6 @@ static int guc_enable_communication(struct intel_guc
*guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- guc_init_send_regs(guc);
-
if (HAS_GUC_CT(dev_priv))
return intel_guc_enable_ct(guc);
@@ -386,6 +384,8 @@ int intel_uc_init_hw(struct drm_i915_private
*dev_priv)
if (ret)
goto err_log_capture;
+ intel_guc_init_send_regs(guc);
+
Hmm, if you want to make it 'one-time-setup' then this is still
wrong place as intel_uc_init_hw() can be called several times
during driver life cycle. Maybe all we need is new function
intel_uc_init(dev_priv) as existing intel_uc_init_early() may
be too early ;)
Michal
ret = guc_enable_communication(guc);
if (ret)
goto err_log_capture;
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 7703c9a..77e6d83 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -211,6 +211,7 @@ struct intel_huc {
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32
len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32
len);
+void intel_guc_init_send_regs(struct intel_guc *guc);
static inline int intel_guc_send(struct intel_guc *guc, const u32
*action, u32 len)
{
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw
On 9/18/2017 3:49 PM, Michal Wajdeczko wrote:
On Mon, 18 Sep 2017 12:11:24 +0200, Sagar Arun Kamble
wrote:
s/guc_init_send_regs/intel_guc_init_send_regs.
Added declaration in intel_uc.h. Calling it from intel_uc_init_hw as it
is one time setup.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/intel_uc.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..499ecf3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -271,7 +271,7 @@ static inline i915_reg_t guc_send_reg(struct
intel_guc *guc, u32 i)
return _MMIO(guc->send_regs.base + 4 * i);
}
-static void guc_init_send_regs(struct intel_guc *guc)
+void intel_guc_init_send_regs(struct intel_guc *guc)
Hmm, there is no reason to export this function now, as it called
by the function defined below.
Yeah :) ... I was probably thinking this to be defined in intel_guc.c
which is changed with this series.
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
enum forcewake_domains fw_domains = 0;
@@ -309,8 +309,6 @@ static int guc_enable_communication(struct
intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-guc_init_send_regs(guc);
-
if (HAS_GUC_CT(dev_priv))
return intel_guc_enable_ct(guc);
@@ -386,6 +384,8 @@ int intel_uc_init_hw(struct drm_i915_private
*dev_priv)
if (ret)
goto err_log_capture;
+intel_guc_init_send_regs(guc);
+
Hmm, if you want to make it 'one-time-setup' then this is still
wrong place as intel_uc_init_hw() can be called several times
during driver life cycle. Maybe all we need is new function
intel_uc_init(dev_priv) as existing intel_uc_init_early() may
be too early ;)
Michal
Right. Will move this in i915_driver_init_mmio after intel_uncore_init.
ret = guc_enable_communication(guc);
if (ret)
goto err_log_capture;
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 7703c9a..77e6d83 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -211,6 +211,7 @@ struct intel_huc {
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32
len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action,
u32 len);
+void intel_guc_init_send_regs(struct intel_guc *guc);
static inline int intel_guc_send(struct intel_guc *guc, const u32
*action, u32 len)
{
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging
== Series Details == Series: series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging URL : https://patchwork.freedesktop.org/series/30501/ State : success == Summary == Series 30501v1 series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging https://patchwork.freedesktop.org/api/1.0/series/30501/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:419s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:520s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:501s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:502s fi-cfl-s total:286 pass:223 dwarn:31 dfail:0 fail:0 skip:31 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:415s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:595s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:426s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:475s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:753s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:488s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:564s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:413s fi-bxt-j4205 failed to connect after reboot 5299e24e48f3c24e612bcdb997d0dc477cdde0d0 drm-tip: 2017y-09m-18d-08h-44m-15s UTC integration manifest 3bddf86faa88 drm/i915/guc: Cleanup adding GuC work items 90187e53e2ab drm/i915/guc: Simplify GuC doorbell logic ddacf24a003a drm/i915/guc: Submit GuC workitems containing coalesced requests 26a2d2dc68d9 drm/i915/guc: Remove obsolete comments and remove unused variable 86c6359e0a27 drm/i915/execlists: Unwind incomplete requests on resets 7254e9a3210e drm/i915/execlists: Split insert_request() 7992c464edbe drm/i915/execlists: Move insert_request() dd7393ced3ae drm/i915/execlists: Kick start request processing after a reset b45f40bca4d6 drm/i915: Cancel all ready but queued requests when wedging == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5724/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/8] drm/i915/guc: Create intel_guc_init_early
On Mon, 18 Sep 2017 12:11:25 +0200, Sagar Arun Kamble
wrote:
Prepared intel_guc_init_early for GuC Specific early
initialization to be done from intel_uc_init_early.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 499ecf3..af4bc3b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -101,10 +101,8 @@ static void gen8_guc_raise_irq(struct intel_guc
*guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
-void intel_uc_init_early(struct drm_i915_private *dev_priv)
+static void intel_guc_init_early(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
-
intel_guc_ct_init_early(&guc->ct);
mutex_init(&guc->send_mutex);
@@ -112,6 +110,11 @@ void intel_uc_init_early(struct drm_i915_private
*dev_priv)
guc->notify = gen8_guc_raise_irq;
}
+void intel_uc_init_early(struct drm_i915_private *dev_priv)
+{
+ intel_guc_init_early(&dev_priv->guc);
+}
+
static void fetch_uc_fw(struct drm_i915_private *dev_priv,
struct intel_uc_fw *uc_fw)
{
hmm, maybe this patch can be squashed with next one as signature
of the intel_guc_init_early() is changed there again
Michal
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[Intel-gfx] [PATCH v2 0/2] drm/i915: add perf support for Coffeelake
Hi, Just a follow up with refactoring in patch 1. Cheers, Lionel Landwerlin (2): drm/i915/perf: disable clk ratio reports on gen9 drm/i915/perf: add support for Coffeelake GT2 drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++ drivers/gpu/drm/i915/i915_oa_cflgt2.h | 34 +++ drivers/gpu/drm/i915/i915_perf.c | 8 ++- 5 files changed, 153 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/perf: add support for Coffeelake GT2
Add the test configuration & timestamp frequency for Coffeelake GT2.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
drivers/gpu/drm/i915/i915_oa_cflgt2.h | 34 +++
drivers/gpu/drm/i915/i915_perf.c | 5 ++
5 files changed, 152 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1cb8059a3a16..5182e3d5557d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
i915_oa_bxt.o \
i915_oa_kblgt2.o \
i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b735b69f6ed..6d7d871b32ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2983,6 +2983,8 @@ intel_info(const struct drm_i915_private *dev_priv)
(dev_priv)->info.gt == 3)
#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x },
+ { _MMIO(0x2744), 0x0080 },
+ { _MMIO(0x2714), 0xf080 },
+ { _MMIO(0x2710), 0x },
+ { _MMIO(0x2724), 0xf080 },
+ { _MMIO(0x2720), 0x },
+ { _MMIO(0x2770), 0x0004 },
+ { _MMIO(0x2774), 0x },
+ { _MMIO(0x2778), 0x0003 },
+ { _MMIO(0x277c), 0x },
+ { _MMIO(0x2780), 0x0007 },
+ { _MMIO(0x2784), 0x },
+ { _MMIO(0x2788), 0x0012 },
+ { _MMIO(0x278c), 0xfff7 },
+ { _MMIO(0x2790), 0x0012 },
+ { _MMIO(0x2794), 0xffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0xffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0xffe7 },
+ { _MMIO(0x27a8), 0x0011 },
+ { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9840), 0x0080 },
+ { _MMIO(0x9888), 0x1181 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f81 },
+ { _MMIO(0x9888), 0x1d81 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x1190 },
+ { _MMIO(0x9888), 0x3790 },
+ { _MMIO(0x9888), 0x5390 },
+ { _MMIO(0x9888), 0x4590 },
+ { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_test_config_cflgt2(struct d
[Intel-gfx] [PATCH v2 1/2] drm/i915/perf: disable clk ratio reports on gen9
We're doing this on all Gen9 based platforms, let's just check the gen
rather than listing every single platforms.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..1b40ac6d1400 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1850,8 +1850,7 @@ static int gen8_enable_metric_set(struct drm_i915_private
*dev_priv,
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
- IS_KABYLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ if (IS_GEN9(dev_priv)) {
I915_WRITE(GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
--
2.14.1
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/perf: add support for Coffeelake GT2
Quoting Lionel Landwerlin (2017-09-18 12:00:45) > Add the test configuration & timestamp frequency for Coffeelake GT2. > > Signed-off-by: Lionel Landwerlin What changed from the one that Matthew reviewed? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw
== Series Details == Series: series starting with [1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw URL : https://patchwork.freedesktop.org/series/30502/ State : success == Summary == Series 30502v1 series starting with [1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw https://patchwork.freedesktop.org/api/1.0/series/30502/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:447s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:471s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:420s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:514s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:511s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:497s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s fi-cfl-s total:286 pass:222 dwarn:32 dfail:0 fail:0 skip:31 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:417s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:592s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:431s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:410s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:493s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:463s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:476s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:594s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:751s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:479s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:569s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:425s fi-pnv-d510 failed to connect after reboot 5299e24e48f3c24e612bcdb997d0dc477cdde0d0 drm-tip: 2017y-09m-18d-08h-44m-15s UTC integration manifest 53c49956930b drm/i915: Reorganize HuC authentication ef00b76aa0ed drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9 5906c0b4e8bc drm/i915/guc: Remove i915_guc_log_unregister 2e42ce116c18 drm/i915/guc: Fix GuC HW/SW state cleanup in unload path 64e86399 drm/i915/guc: Fix GuC interaction in reset/suspend scenarios 54c1c4d674df drm/i915/guc: Create intel_guc.c for defining GuC specific functionality e36b9ffa4c53 drm/i915/guc: Create intel_guc_init_early 0b442d5e2362 drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5725/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/perf: add support for Coffeelake GT2
On 18/09/17 12:04, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-09-18 12:00:45) Add the test configuration & timestamp frequency for Coffeelake GT2. Signed-off-by: Lionel Landwerlin What changed from the one that Matthew reviewed? -Chris Nothing, I forgot to add his Rb :/ His comment about disabling clk-ratio reports is addressed in patch 1. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: document field usage of drm_i915_perf_oa_config
Document the expected length register config pointers (tuple of u32 values). Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 3d34c6a4313d..4409cea57607 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3200,6 +3200,11 @@ static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, * Validates the submitted OA register to be saved into a new OA config that * can then be used for programming the OA unit and its NOA network. * + * drm_i915_perf_oa_config has 3 pointers fields (mux_regs_ptr, + * boolean_regs_ptr, flex_regs_ptr) to buffers of tuples (register address, + * value) of u32 values. The number of tuples is given respectively by + * n_mux_regs, n_boolean_regs and n_flex_regs fields. + * * Returns: A new allocated config number to be used with the perf open ioctl * or a negative error code on failure. */ -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 0/2] drm/i915: add perf support for Coffeelake
Missing Rb on patch 2 :/ Sorry for the noise. Cheers, Lionel Landwerlin (2): drm/i915/perf: disable clk ratio reports on gen9 drm/i915/perf: add support for Coffeelake GT2 drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++ drivers/gpu/drm/i915/i915_oa_cflgt2.h | 34 +++ drivers/gpu/drm/i915/i915_perf.c | 8 ++- 5 files changed, 153 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm/i915/perf: add support for Coffeelake GT2
Add the test configuration & timestamp frequency for Coffeelake GT2.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_oa_cflgt2.c | 109 ++
drivers/gpu/drm/i915/i915_oa_cflgt2.h | 34 +++
drivers/gpu/drm/i915/i915_perf.c | 5 ++
5 files changed, 152 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_cflgt2.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1cb8059a3a16..5182e3d5557d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
i915_oa_bxt.o \
i915_oa_kblgt2.o \
i915_oa_kblgt3.o \
- i915_oa_glk.o
+ i915_oa_glk.o \
+ i915_oa_cflgt2.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b735b69f6ed..6d7d871b32ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2983,6 +2983,8 @@ intel_info(const struct drm_i915_private *dev_priv)
(dev_priv)->info.gt == 3)
#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
+(dev_priv)->info.gt == 2)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c
b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index ..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x },
+ { _MMIO(0x2744), 0x0080 },
+ { _MMIO(0x2714), 0xf080 },
+ { _MMIO(0x2710), 0x },
+ { _MMIO(0x2724), 0xf080 },
+ { _MMIO(0x2720), 0x },
+ { _MMIO(0x2770), 0x0004 },
+ { _MMIO(0x2774), 0x },
+ { _MMIO(0x2778), 0x0003 },
+ { _MMIO(0x277c), 0x },
+ { _MMIO(0x2780), 0x0007 },
+ { _MMIO(0x2784), 0x },
+ { _MMIO(0x2788), 0x0012 },
+ { _MMIO(0x278c), 0xfff7 },
+ { _MMIO(0x2790), 0x0012 },
+ { _MMIO(0x2794), 0xffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0xffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0xffe7 },
+ { _MMIO(0x27a8), 0x0011 },
+ { _MMIO(0x27ac), 0xffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9840), 0x0080 },
+ { _MMIO(0x9888), 0x1181 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f81 },
+ { _MMIO(0x9888), 0x1d81 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x1190 },
+ { _MMIO(0x9888), 0x3790 },
+ { _MMIO(0x9888), 0x5390 },
+ { _MMIO(0x9888), 0x4590 },
+ { _MMIO(0x9888), 0x3390 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_
[Intel-gfx] [PATCH v3 1/2] drm/i915/perf: disable clk ratio reports on gen9
We're doing this on all Gen9 based platforms, let's just check the gen
rather than listing every single platforms.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..1b40ac6d1400 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1850,8 +1850,7 @@ static int gen8_enable_metric_set(struct drm_i915_private
*dev_priv,
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
- IS_KABYLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ if (IS_GEN9(dev_priv)) {
I915_WRITE(GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
--
2.14.1
___
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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH] drm/i915/perf: document field usage of drm_i915_perf_oa_config
Quoting Lionel Landwerlin (2017-09-18 12:10:38) > Document the expected length register config pointers (tuple of u32 > values). > > Signed-off-by: Lionel Landwerlin > --- > drivers/gpu/drm/i915/i915_perf.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c > b/drivers/gpu/drm/i915/i915_perf.c > index 3d34c6a4313d..4409cea57607 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3200,6 +3200,11 @@ static int create_dynamic_oa_sysfs_entry(struct > drm_i915_private *dev_priv, > * Validates the submitted OA register to be saved into a new OA config that > * can then be used for programming the OA unit and its NOA network. > * > + * drm_i915_perf_oa_config has 3 pointers fields (mux_regs_ptr, s/pointers/pointer/ > + * boolean_regs_ptr, flex_regs_ptr) to buffers of tuples (register address, > + * value) of u32 values. The number of tuples is given respectively by > + * n_mux_regs, n_boolean_regs and n_flex_regs fields. Reviewed-by: Chris Wilson But I would suggest this would better for describing the uabi in i915_drm.h. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [request] bugfix patch for inclusion in the Linux 4.9 LTS series
On Mon, 18 Sep 2017, Aaditya Bagga wrote: > Hi there! > > With the Linux 4.9 series (upto 4.9.50), the GPU hangs upon resume from > disk (hibernation) on a laptop with Intel Broadwell graphics. > > I filed a bug [1] and got to know that it has been already fixed [2]. > > Would it be possible to have this patch included in the Linux 4.9 LTS > series? > > Thanks, > Aaditya > > [1]: https://bugs.freedesktop.org/show_bug.cgi?id=102831 > [2]: https://patchwork.freedesktop.org/patch/111587/ Chris? BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2.
== Series Details == Series: drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. URL : https://patchwork.freedesktop.org/series/30503/ State : failure == Summary == Series 30503v1 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. https://patchwork.freedesktop.org/api/1.0/series/30503/revisions/1/mbox/ Test gem_exec_reloc: Subgroup basic-cpu-gtt-noreloc: pass -> DMESG-WARN (fi-kbl-7500u) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:418s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:514s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:496s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:488s fi-cfl-s total:286 pass:223 dwarn:31 dfail:0 fail:0 skip:31 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:412s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:604s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:410s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s fi-kbl-7500u total:118 pass:99 dwarn:2 dfail:0 fail:0 skip:16 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:599s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:544s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:496s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:474s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:564s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:417s 5299e24e48f3c24e612bcdb997d0dc477cdde0d0 drm-tip: 2017y-09m-18d-08h-44m-15s UTC integration manifest 52dcc46ca752 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5726/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: document field usage of drm_i915_perf_oa_config
On 18/09/17 12:27, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-09-18 12:10:38) Document the expected length register config pointers (tuple of u32 values). Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 3d34c6a4313d..4409cea57607 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3200,6 +3200,11 @@ static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, * Validates the submitted OA register to be saved into a new OA config that * can then be used for programming the OA unit and its NOA network. * + * drm_i915_perf_oa_config has 3 pointers fields (mux_regs_ptr, s/pointers/pointer/ + * boolean_regs_ptr, flex_regs_ptr) to buffers of tuples (register address, + * value) of u32 values. The number of tuples is given respectively by + * n_mux_regs, n_boolean_regs and n_flex_regs fields. Reviewed-by: Chris Wilson But I would suggest this would better for describing the uabi in i915_drm.h. I was wondering about put it in i915_drm.h, I think it's better. Let's me just send another patch for the uapi instead. Thanks! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915: Convert intel_rc6_residency_us to ns
From: Tvrtko Ursulin
Will be used for exposing the PMU counters.
v2:
* Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
* Restore full unit conversion precision.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
drivers/gpu/drm/i915/i915_sysfs.c | 9 +++--
drivers/gpu/drm/i915/intel_pm.c | 27 +--
3 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b735b69f6ed..4571cbff13a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4125,9 +4125,15 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
-u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
+u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
const i915_reg_t reg);
+static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
+const i915_reg_t reg)
+{
+ return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
+}
+
#define I915_READ8(reg)
dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv,
(reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index d61c8727f756..1a34d32d0092 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -42,8 +42,13 @@ static inline struct drm_i915_private
*kdev_minor_to_i915(struct device *kdev)
static u32 calc_residency(struct drm_i915_private *dev_priv,
i915_reg_t reg)
{
- return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg),
-1000);
+ u64 res;
+
+ intel_runtime_pm_get(dev_priv);
+ res = intel_rc6_residency_us(dev_priv, reg);
+ intel_runtime_pm_put(dev_priv);
+
+ return DIV_ROUND_CLOSEST_ULL(res, 1000);
}
static ssize_t
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94624ede3479..9c4588369452 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9342,34 +9342,33 @@ static u64 vlv_residency_raw(struct drm_i915_private
*dev_priv,
return lower | (u64)upper << 8;
}
-u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
+u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
const i915_reg_t reg)
{
- u64 time_hw, units, div;
+ u64 time_hw;
+ u32 mul, div;
if (!intel_enable_rc6())
return 0;
- intel_runtime_pm_get(dev_priv);
-
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- units = 1000;
+ mul = 100;
div = dev_priv->czclk_freq;
-
time_hw = vlv_residency_raw(dev_priv, reg);
- } else if (IS_GEN9_LP(dev_priv)) {
- units = 1000;
- div = 1200; /* 833.33ns */
- time_hw = I915_READ(reg);
} else {
- units = 128000; /* 1.28us */
- div = 10;
+ /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
+ if (IS_GEN9_LP(dev_priv)) {
+ mul = 1;
+ div = 12;
+ } else {
+ mul = 1280;
+ div = 1;
+ }
time_hw = I915_READ(reg);
}
- intel_runtime_pm_put(dev_priv);
- return DIV_ROUND_UP_ULL(time_hw * units, div);
+ return DIV_ROUND_UP_ULL(time_hw * mul, div);
}
--
2.9.5
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[Intel-gfx] [PATCH 3/8] drm/i915/pmu: Expose a PMU interface for perf queries
From: Tvrtko Ursulin From: Chris Wilson From: Tvrtko Ursulin From: Dmitry Rogozhkin The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll registers from userspace. (Which not only incurs holding the forcewake lock indefinitely, perturbing the system, but also runs the risk of hanging the machine.) As an alternative we can use the perf event counter interface to sample the ring registers periodically and send those results to userspace. To be able to do so, we need to export the two symbols from kernel/events/core.c to register and unregister a PMU device. v1-v2 (Chris Wilson): v2: Use a common timer for the ring sampling. v3: (Tvrtko Ursulin) * Decouple uAPI from i915 engine ids. * Complete uAPI defines. * Refactor some code to helpers for clarity. * Skip sampling disabled engines. * Expose counters in sysfs. * Pass in fake regs to avoid null ptr deref in perf core. * Convert to class/instance uAPI. * Use shared driver code for rc6 residency, power and frequency. v4: (Dmitry Rogozhkin) * Register PMU with .task_ctx_nr=perf_invalid_context * Expose cpumask for the PMU with the single CPU in the mask * Properly support pmu->stop(): it should call pmu->read() * Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE) * Introduce refcounting of event subscriptions. * Make pmu.busy_stats a refcounter to avoid busy stats going away with some deleted event. * Expose cpumask for i915 PMU to avoid multiple events creation of the same type followed by counter aggregation by perf-stat. * Track CPUs getting online/offline to migrate perf context. If (likely) cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be needed to see effect of CPU status tracking. * End result is that only global events are supported and perf stat works correctly. * Deny perf driver level sampling - it is prohibited for uncore PMU. v5: (Tvrtko Ursulin) * Don't hardcode number of engine samplers. * Rewrite event ref-counting for correctness and simplicity. * Store initial counter value when starting already enabled events to correctly report values to all listeners. * Fix RC6 residency readout. * Comments, GPL header. v6: * Add missing entry to v4 changelog. * Fix accounting in CPU hotplug case by copying the approach from arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin) v7: * Log failure message only on failure. * Remove CPU hotplug notification state on unregister. v8: * Fix error unwind on failed registration. * Checkpatch cleanup. v9: * Drop the energy metric, it is available via intel_rapl_perf. (Ville Syrjälä) * Use HAS_RC6(p). (Chris Wilson) * Handle unsupported non-engine events. (Dmitry Rogozhkin) * Rebase for intel_rc6_residency_ns needing caller managed runtime pm. * Drop HAS_RC6 checks from the read callback since creating those events will be rejected at init time already. * Add counter units to sysfs so perf stat output is nicer. * Cleanup the attribute tables for brevity and readability. Signed-off-by: Chris Wilson Signed-off-by: Tvrtko Ursulin Signed-off-by: Dmitry Rogozhkin Cc: Tvrtko Ursulin Cc: Chris Wilson Cc: Dmitry Rogozhkin Cc: Peter Zijlstra --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 78 drivers/gpu/drm/i915/i915_pmu.c | 705 drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_engine_cs.c | 10 + drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 25 ++ include/uapi/drm/i915_drm.h | 57 +++ 9 files changed, 906 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_pmu.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 1cb8059a3a16..7b3a0eca62b6 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -26,6 +26,7 @@ i915-y := i915_drv.o \ i915-$(CONFIG_COMPAT) += i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o +i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o # GEM code i915-y += i915_cmd_parser.o \ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5c111ea96e80..b1f96eb1be16 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1196,6 +1196,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; i915_gem_shrinker_init(dev_priv); + i915_pmu_register(dev_priv); /* * Notify a valid surface after modesetting, @@ -1250,6 +1251,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) intel_opregion_unregister(dev_priv); i915_perf_unregister(dev_priv); + i915_pmu_unregister(dev_priv); i915_teardown_sysfs(dev_priv); i915_guc_
[Intel-gfx] [PATCH v4 00/8] i915 PMU and engine busy stats
From: Tvrtko Ursulin Fourth spin of the i915 PMU series. Now with the RFC tag removed. This is a cleaned up and bugfixed version with incorporated inital review feedback. Some patches have been dropped for time being. Patches 1-2 are small refactors to make the following work easier. Patch 3 is the main bit. Patch 4 is a small optimisation on top, to only run the sampling timer when it is required. (Depending on GPU awake status and active PMU counters.) Patches 5-7 add software engine busyness tracking, which is then used from the PMU in patch 7. This allows more efficient and more accurate engine busyness metric. And finally patch 8 is an additional optimisation which hides the whole cost of the software engine busyness tracking behind a single nop instruction in the off case. Tvrtko Ursulin (8): drm/i915: Convert intel_rc6_residency_us to ns drm/i915: Extract intel_get_cagf drm/i915/pmu: Expose a PMU interface for perf queries drm/i915/pmu: Suspend sampling when GPU is idle drm/i915: Wrap context schedule notification drm/i915: Engine busy time tracking drm/i915/pmu: Wire up engine busy stats to PMU drm/i915: Gate engine stats collection with a static key drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 9 +- drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 96 +++- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gem_request.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 853 drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/i915_sysfs.c | 20 +- drivers/gpu/drm/i915/intel_engine_cs.c | 111 + drivers/gpu/drm/i915/intel_lrc.c| 19 +- drivers/gpu/drm/i915/intel_pm.c | 41 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 25 + drivers/gpu/drm/i915/intel_ringbuffer.h | 147 ++ include/uapi/drm/i915_drm.h | 57 +++ 15 files changed, 1351 insertions(+), 35 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_pmu.c -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915: Extract intel_get_cagf
From: Tvrtko Ursulin
Code to be shared between debugfs and the PMU implementation.
v2: Checkpatch cleanup.
v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson (v2)
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_sysfs.c | 11 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ++
4 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 62133dd303ac..98a735ecaeaf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1113,13 +1113,8 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) &
GEN6_CURBSYTAVG_MASK;
- if (INTEL_GEN(dev_priv) >= 9)
- cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
- else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
- else
- cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
- cagf = intel_gpu_freq(dev_priv, cagf);
+ cagf = intel_gpu_freq(dev_priv,
+ intel_get_cagf(dev_priv, rpstat));
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4571cbff13a9..7d3f5a5c2454 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4134,6 +4134,8 @@ static inline u64 intel_rc6_residency_us(struct
drm_i915_private *dev_priv,
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+
#define I915_READ8(reg)
dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv,
(reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 1a34d32d0092..2f74ae55332d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -257,14 +257,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
} else {
- u32 rpstat = I915_READ(GEN6_RPSTAT1);
- if (INTEL_GEN(dev_priv) >= 9)
- ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
- else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
- else
- ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
- ret = intel_gpu_freq(dev_priv, ret);
+ ret = intel_gpu_freq(dev_priv,
+intel_get_cagf(dev_priv,
+ I915_READ(GEN6_RPSTAT1)));
}
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9c4588369452..97a7fd74da3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9372,3 +9372,17 @@ u64 intel_rc6_residency_ns(struct drm_i915_private
*dev_priv,
return DIV_ROUND_UP_ULL(time_hw * mul, div);
}
+
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
+{
+ u32 cagf;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+ else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+ else
+ cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+
+ return cagf;
+}
--
2.9.5
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[Intel-gfx] [PATCH 6/8] drm/i915: Engine busy time tracking
From: Tvrtko Ursulin
Track total time requests have been executing on the hardware.
We add new kernel API to allow software tracking of time GPU
engines are spending executing requests.
Both per-engine and global API is added with the latter also
being exported for use by external users.
v2:
* Squashed with the internal API.
* Dropped static key.
* Made per-engine.
* Store time in monotonic ktime.
v3: Moved stats clearing to disable.
v4:
* Comments.
* Don't export the API just yet.
v5: Whitespace cleanup.
v6:
* Rename ref to active.
* Drop engine aggregate stats for now.
* Account initial busy period after enabling stats.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 84 ++
drivers/gpu/drm/i915/intel_lrc.c| 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 92 +
3 files changed, 178 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 82510d971c7d..cbf978d39052 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -232,6 +232,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
/* Nothing to do here, execute in order of dependencies */
engine->schedule = NULL;
+ spin_lock_init(&engine->stats.lock);
+
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
dev_priv->engine_class[info->class][info->instance] = engine;
@@ -1556,6 +1558,88 @@ bool intel_engine_can_store_dword(struct intel_engine_cs
*engine)
}
}
+/**
+ * intel_enable_engine_stats() - Enable engine busy tracking on engine
+ * @engine: engine to enable stats collection
+ *
+ * Start collecting the engine busyness data for @engine.
+ *
+ * Returns 0 on success or a negative error code.
+ */
+int intel_enable_engine_stats(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ if (!i915.enable_execlists)
+ return -ENODEV;
+
+ spin_lock_irqsave(&engine->stats.lock, flags);
+ if (engine->stats.enabled == ~0)
+ goto busy;
+ if (engine->stats.enabled++ == 0)
+ engine->stats.enabled_at = ktime_get();
+ spin_unlock_irqrestore(&engine->stats.lock, flags);
+
+ return 0;
+
+busy:
+ spin_unlock_irqrestore(&engine->stats.lock, flags);
+
+ return -EBUSY;
+}
+
+/**
+ * intel_disable_engine_stats() - Disable engine busy tracking on engine
+ * @engine: engine to disable stats collection
+ *
+ * Stops collecting the engine busyness data for @engine.
+ */
+void intel_disable_engine_stats(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ if (!i915.enable_execlists)
+ return;
+
+ spin_lock_irqsave(&engine->stats.lock, flags);
+ WARN_ON_ONCE(engine->stats.enabled == 0);
+ if (--engine->stats.enabled == 0) {
+ engine->stats.enabled_at = 0;
+ engine->stats.active = 0;
+ engine->stats.start = 0;
+ engine->stats.total = 0;
+ }
+ spin_unlock_irqrestore(&engine->stats.lock, flags);
+}
+
+/**
+ * intel_engine_get_busy_time() - Return current accumulated engine busyness
+ * @engine: engine to report on
+ *
+ * Returns accumulated time @engine was busy since engine stats were enabled.
+ */
+ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
+{
+ ktime_t total;
+ unsigned long flags;
+
+ spin_lock_irqsave(&engine->stats.lock, flags);
+
+ total = engine->stats.total;
+
+ /*
+* If the engine is executing something at the moment
+* add it to the total.
+*/
+ if (engine->stats.active)
+ total = ktime_add(total,
+ ktime_sub(ktime_get(), engine->stats.start));
+
+ spin_unlock_irqrestore(&engine->stats.lock, flags);
+
+ return total;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_engine.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ba91db43f163..7f2861014448 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -304,12 +304,14 @@ execlists_context_status_change(struct
drm_i915_gem_request *rq,
static inline void
execlists_context_schedule_in(struct drm_i915_gem_request *rq)
{
+ intel_engine_context_in(rq->engine);
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
}
static inline void
execlists_context_schedule_out(struct drm_i915_gem_request *rq)
{
+ intel_engine_context_out(rq->engine);
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbd1734759b8..ae0a4c498a0f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -46
[Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU
From: Tvrtko Ursulin
We can use engine busy stats instead of the MMIO sampling timer
for better efficiency.
As minimum this saves period * num_engines / sec mmio reads,
and in a better case, when only engine busy samplers are active,
it enables us to not kick off the sampling timer at all.
v2: Rebase.
v3:
* Rebase, comments.
* Leave engine busyness controls out of workers.
v4: Checkpatch cleanup.
v5: Added comment to pmu_needs_timer change.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 40 ++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
2 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index b7de6fe3cac7..ffba21eeb5d0 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -90,6 +90,11 @@ static unsigned int event_enabled_bit(struct perf_event
*event)
return config_enabled_bit(event->attr.config);
}
+static bool supports_busy_stats(void)
+{
+ return i915.enable_execlists;
+}
+
static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
{
u64 enable;
@@ -115,6 +120,12 @@ static bool pmu_needs_timer(struct drm_i915_private *i915,
bool gpu_active)
*/
if (!gpu_active)
enable &= ~ENGINE_SAMPLE_MASK;
+ /**
+* Also there is software busyness tracking available we do not
+* need the timer for I915_SAMPLE_BUSY counter.
+*/
+ else if (supports_busy_stats())
+ enable &= ~BIT(I915_SAMPLE_BUSY);
/**
* If some bits remain it means we need the sampling timer running.
@@ -192,7 +203,8 @@ static void engines_sample(struct drm_i915_private
*dev_priv)
if (enable & BIT(I915_SAMPLE_QUEUED))
engine->pmu.sample[I915_SAMPLE_QUEUED] += PERIOD;
- if (enable & BIT(I915_SAMPLE_BUSY)) {
+ if ((enable & BIT(I915_SAMPLE_BUSY)) &&
+ !engine->pmu.busy_stats) {
u32 val;
fw = grab_forcewake(dev_priv, fw);
@@ -385,6 +397,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
if (WARN_ON_ONCE(!engine)) {
/* Do nothing */
+ } else if (sample == I915_SAMPLE_BUSY &&
+ engine->pmu.busy_stats) {
+ val = ktime_to_ns(intel_engine_get_busy_time(engine));
} else {
val = engine->pmu.sample[sample];
}
@@ -438,6 +453,12 @@ static void i915_pmu_event_read(struct perf_event *event)
local64_add(new - prev, &event->count);
}
+static bool engine_needs_busy_stats(struct intel_engine_cs *engine)
+{
+ return supports_busy_stats() &&
+ (engine->pmu.enable & BIT(I915_SAMPLE_BUSY));
+}
+
static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
@@ -477,7 +498,14 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
- engine->pmu.enable_count[sample]++;
+ if (engine->pmu.enable_count[sample]++ == 0) {
+ if (engine_needs_busy_stats(engine) &&
+ !engine->pmu.busy_stats) {
+ engine->pmu.busy_stats =
+ intel_enable_engine_stats(engine) == 0;
+ WARN_ON_ONCE(!engine->pmu.busy_stats);
+ }
+ }
}
/*
@@ -513,8 +541,14 @@ static void i915_pmu_disable(struct perf_event *event)
* Decrement the reference count and clear the enabled
* bitmask when the last listener on an event goes away.
*/
- if (--engine->pmu.enable_count[sample] == 0)
+ if (--engine->pmu.enable_count[sample] == 0) {
engine->pmu.enable &= ~BIT(sample);
+ if (!engine_needs_busy_stats(engine) &&
+ engine->pmu.busy_stats) {
+ engine->pmu.busy_stats = false;
+ intel_disable_engine_stats(engine);
+ }
+ }
}
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index ae0a4c498a0f..cb58ce34ab13 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -265,6 +265,11 @@ struct intel_engine_cs {
* Our internal timer stores the current counter in this field.
*/
u64 sample[I915_ENGINE_SAMPLE_MAX];
+ /**
+* @busy_
[Intel-gfx] [PATCH 5/8] drm/i915: Wrap context schedule notification
From: Tvrtko Ursulin
No functional change just something which will be handy in the
following patch.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1960ba5ff9e4..ba91db43f163 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -301,6 +301,18 @@ execlists_context_status_change(struct
drm_i915_gem_request *rq,
status, rq);
}
+static inline void
+execlists_context_schedule_in(struct drm_i915_gem_request *rq)
+{
+ execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+}
+
+static inline void
+execlists_context_schedule_out(struct drm_i915_gem_request *rq)
+{
+ execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
+}
+
static void
execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
{
@@ -346,7 +358,7 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
if (rq) {
GEM_BUG_ON(count > !n);
if (!count++)
- execlists_context_status_change(rq,
INTEL_CONTEXT_SCHEDULE_IN);
+ execlists_context_schedule_in(rq);
port_set(&port[n], port_pack(rq, count));
desc = execlists_update_context(rq);
GEM_DEBUG_EXEC(port[n].context_id =
upper_32_bits(desc));
@@ -612,8 +624,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
GEM_BUG_ON(!i915_gem_request_completed(rq));
- execlists_context_status_change(rq,
INTEL_CONTEXT_SCHEDULE_OUT);
-
+ execlists_context_schedule_out(rq);
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
--
2.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: Gate engine stats collection with a static key
From: Tvrtko Ursulin
This reduces the cost of the software engine busyness tracking
to a single no-op instruction when there are no listeners.
v2: Rebase and some comments.
v3: Rebase.
v4: Checkpatch fixes.
v5: Rebase.
v6: Use system_long_wq to avoid being blocked by struct_mutex
users.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 54 +++--
drivers/gpu/drm/i915/intel_engine_cs.c | 17 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 101
3 files changed, 130 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ffba21eeb5d0..6d22172b8fb0 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -499,11 +499,17 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
if (engine->pmu.enable_count[sample]++ == 0) {
+ /*
+* Enable engine busy stats tracking if needed or
+* alternatively cancel the scheduled disabling of the
+* same.
+*/
if (engine_needs_busy_stats(engine) &&
!engine->pmu.busy_stats) {
- engine->pmu.busy_stats =
- intel_enable_engine_stats(engine) == 0;
- WARN_ON_ONCE(!engine->pmu.busy_stats);
+ engine->pmu.busy_stats = true;
+ if
(!cancel_delayed_work(&engine->pmu.disable_busy_stats))
+ queue_work(system_long_wq,
+
&engine->pmu.enable_busy_stats);
}
}
}
@@ -546,7 +552,15 @@ static void i915_pmu_disable(struct perf_event *event)
if (!engine_needs_busy_stats(engine) &&
engine->pmu.busy_stats) {
engine->pmu.busy_stats = false;
- intel_disable_engine_stats(engine);
+ /*
+* We request a delayed disable to handle the
+* rapid on/off cycles on events which can
+* happen when tools like perf stat start in a
+* nicer way.
+*/
+ queue_delayed_work(system_long_wq,
+
&engine->pmu.disable_busy_stats,
+
round_jiffies_up_relative(HZ));
}
}
}
@@ -737,9 +751,27 @@ static int i915_pmu_cpu_offline(unsigned int cpu, struct
hlist_node *node)
return 0;
}
+static void __enable_busy_stats(struct work_struct *work)
+{
+ struct intel_engine_cs *engine =
+ container_of(work, typeof(*engine), pmu.enable_busy_stats);
+
+ WARN_ON_ONCE(intel_enable_engine_stats(engine));
+}
+
+static void __disable_busy_stats(struct work_struct *work)
+{
+ struct intel_engine_cs *engine =
+ container_of(work, typeof(*engine), pmu.disable_busy_stats.work);
+
+ intel_disable_engine_stats(engine);
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
int ret;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
if (INTEL_GEN(i915) <= 2) {
DRM_INFO("PMU not supported for this GPU.");
@@ -773,6 +805,12 @@ void i915_pmu_register(struct drm_i915_private *i915)
i915->pmu.timer.function = i915_sample;
i915->pmu.enable = 0;
+ for_each_engine(engine, i915, id) {
+ INIT_WORK(&engine->pmu.enable_busy_stats, __enable_busy_stats);
+ INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats,
+ __disable_busy_stats);
+ }
+
ret = perf_pmu_register(&i915->pmu.base, "i915", -1);
if (ret == 0)
return;
@@ -791,6 +829,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
void i915_pmu_unregister(struct drm_i915_private *i915)
{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
if (!i915->pmu.base.event_init)
return;
@@ -802,6 +843,11 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
hrtimer_cancel(&i915->pmu.timer);
+ for_each_engine(engine, i915, id) {
+ flush_work(&engine->pmu.enable_busy_stats);
+ flush_delayed_work(&engine->pmu.disable_busy_stats);
+ }
+
perf_pmu_unregister(&i915->pmu.base);
i915->pmu.base.event_init = NULL;
}
diff --git a/dr
[Intel-gfx] [PATCH i-g-t 1/5] intel-gpu-overlay: Move local perf implementation to a library
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/Makefile.sources | 2 ++
overlay/perf.c => lib/igt_perf.c | 2 +-
overlay/perf.h => lib/igt_perf.h | 2 ++
overlay/Makefile.am | 6 ++
overlay/gem-interrupts.c | 3 ++-
overlay/gpu-freq.c | 3 ++-
overlay/gpu-perf.c | 3 ++-
overlay/gpu-top.c| 3 ++-
overlay/power.c | 3 ++-
overlay/rc6.c| 3 ++-
10 files changed, 19 insertions(+), 11 deletions(-)
rename overlay/perf.c => lib/igt_perf.c (94%)
rename overlay/perf.h => lib/igt_perf.h (99%)
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 53fdb54cbfa5..c031cb502469 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -16,6 +16,8 @@ lib_source_list = \
igt_gt.h\
igt_gvt.c \
igt_gvt.h \
+ igt_perf.c \
+ igt_perf.h \
igt_primes.c\
igt_primes.h\
igt_rand.c \
diff --git a/overlay/perf.c b/lib/igt_perf.c
similarity index 94%
rename from overlay/perf.c
rename to lib/igt_perf.c
index b8fdc675c587..45cccff0ae53 100644
--- a/overlay/perf.c
+++ b/lib/igt_perf.c
@@ -3,7 +3,7 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
uint64_t i915_type_id(void)
{
diff --git a/overlay/perf.h b/lib/igt_perf.h
similarity index 99%
rename from overlay/perf.h
rename to lib/igt_perf.h
index c44e65f9734c..a80b311cd1d1 100644
--- a/overlay/perf.h
+++ b/lib/igt_perf.h
@@ -1,6 +1,8 @@
#ifndef I915_PERF_H
#define I915_PERF_H
+#include
+
#include
#define I915_SAMPLE_BUSY 0
diff --git a/overlay/Makefile.am b/overlay/Makefile.am
index 5472514efc16..c66a80f4e571 100644
--- a/overlay/Makefile.am
+++ b/overlay/Makefile.am
@@ -4,8 +4,8 @@ endif
AM_CPPFLAGS = -I.
AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
- $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS)
-LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS)
+ $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -I$(srcdir)/../lib
+LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS)
$(top_builddir)/lib/libintel_tools.la
intel_gpu_overlay_SOURCES = \
chart.h \
@@ -29,8 +29,6 @@ intel_gpu_overlay_SOURCES = \
igfx.c \
overlay.h \
overlay.c \
- perf.h \
- perf.c \
power.h \
power.c \
rc6.h \
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0150a1d03825..7ba54fcd487d 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -31,9 +31,10 @@
#include
#include
+#include "igt_perf.h"
+
#include "gem-interrupts.h"
#include "debugfs.h"
-#include "perf.h"
static int perf_open(void)
{
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 321c93882238..7f29b1aa986e 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -28,9 +28,10 @@
#include
#include
+#include "igt_perf.h"
+
#include "gpu-freq.h"
#include "debugfs.h"
-#include "perf.h"
static int perf_i915_open(int config, int group)
{
diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c
index f557b9f06a17..3d4a9be91a94 100644
--- a/overlay/gpu-perf.c
+++ b/overlay/gpu-perf.c
@@ -34,7 +34,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "gpu-perf.h"
#include "debugfs.h"
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 891a7ea7c0b1..06f489dfdc83 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -31,7 +31,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "igfx.h"
#include "gpu-top.h"
diff --git a/overlay/power.c b/overlay/power.c
index 2f1521b82cd6..84d860cae40c 100644
--- a/overlay/power.c
+++ b/overlay/power.c
@@ -31,7 +31,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "power.h"
#include "debugfs.h"
diff --git a/overlay/rc6.c b/overlay/rc6.c
index d7047c2f4880..3175bb22308f 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -31,8 +31,9 @@
#include
#include
+#include "igt_perf.h"
+
#include "rc6.h"
-#include "perf.h"
static int perf_i915_open(int config, int group)
{
--
2.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/5] intel-gpu-overlay: Consolidate perf PMU access to library
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 33 +
lib/igt_perf.h | 2 ++
overlay/gem-interrupts.c | 16 +---
overlay/gpu-freq.c | 22 ++
overlay/gpu-top.c| 32
overlay/power.c | 17 +
overlay/rc6.c| 24 +++-
7 files changed, 50 insertions(+), 96 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 45cccff0ae53..0fa5ae3acb66 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -2,6 +2,8 @@
#include
#include
#include
+#include
+#include
#include "igt_perf.h"
@@ -24,3 +26,34 @@ uint64_t i915_type_id(void)
return strtoull(buf, 0, 0);
}
+static int _perf_open(int config, int group, int format)
+{
+ struct perf_event_attr attr;
+
+ memset(&attr, 0, sizeof (attr));
+
+ attr.type = i915_type_id();
+ if (attr.type == 0)
+ return -ENOENT;
+
+ attr.config = config;
+
+ if (group >= 0)
+ format &= ~PERF_FORMAT_GROUP;
+
+ attr.read_format = format;
+
+ return perf_event_open(&attr, -1, 0, group, 0);
+
+}
+
+int perf_i915_open(int config)
+{
+ return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_i915_open_group(int config, int group)
+{
+ return _perf_open(config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index a80b311cd1d1..8e674c3a3755 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -62,5 +62,7 @@ perf_event_open(struct perf_event_attr *attr,
}
uint64_t i915_type_id(void);
+int perf_i915_open(int config);
+int perf_i915_open_group(int config, int group);
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 7ba54fcd487d..a84aef0398a7 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -36,20 +36,6 @@
#include "gem-interrupts.h"
#include "debugfs.h"
-static int perf_open(void)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = I915_PERF_INTERRUPTS;
-
- return perf_event_open(&attr, -1, 0, -1, 0);
-}
-
static long long debugfs_read(void)
{
char buf[8192], *b;
@@ -127,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_open();
+ irqs->fd = perf_i915_open(I915_PERF_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 7f29b1aa986e..76c5ed9acfd1 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -33,30 +33,12 @@
#include "gpu-freq.h"
#include "debugfs.h"
-static int perf_i915_open(int config, int group)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = config;
-
- attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
- if (group == -1)
- attr.read_format |= PERF_FORMAT_GROUP;
-
- return perf_event_open(&attr, -1, 0, group, 0);
-}
-
static int perf_open(void)
{
int fd;
- fd = perf_i915_open(I915_PERF_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open(I915_PERF_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_i915_open_group(I915_PERF_ACTUAL_FREQUENCY, -1);
+ if (perf_i915_open_group(I915_PERF_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 06f489dfdc83..812f47d5aced 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -48,24 +48,6 @@
#define I915_PERF_RING_WAIT(n) (__I915_PERF_RING(n) + 1)
#define I915_PERF_RING_SEMA(n) (__I915_PERF_RING(n) + 2)
-static int perf_i915_open(int config, int group)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = config;
-
- attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
- if (group == -1)
- attr.read_format |= PERF_FORMAT_GROUP;
-
- return perf_event_open(&attr, -1, 0, group, 0);
-}
-
static int perf_init(struct gpu_top *gt)
{
const char *names[] = {
@@ -77,27 +59,29 @@ static int perf_init(struct gpu_top *gt)
};
int n;
- gt->fd = perf_i915_open(I915_PERF_RING_BUSY(0), -1);
+ gt->fd = perf_i915_open_group(I915_PERF_RING_BUSY(0), -1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open(I915_PERF_RING_WAIT(0), gt->fd) >= 0)
+
[Intel-gfx] [PATCH i-g-t 4/5] intel-gpu-overlay: Catch-up to new i915 PMU
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.h | 93 ++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +--
overlay/gpu-top.c| 68 +++
overlay/power.c | 4 +--
overlay/rc6.c| 6 ++--
6 files changed, 111 insertions(+), 66 deletions(-)
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 8e674c3a3755..e29216f0500a 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -1,3 +1,27 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
#ifndef I915_PERF_H
#define I915_PERF_H
@@ -5,41 +29,56 @@
#include
-#define I915_SAMPLE_BUSY 0
-#define I915_SAMPLE_WAIT 1
-#define I915_SAMPLE_SEMA 2
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+ I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
+enum drm_i915_pmu_engine_sample {
+ I915_SAMPLE_QUEUED = 0,
+ I915_SAMPLE_BUSY = 1,
+ I915_SAMPLE_WAIT = 2,
+ I915_SAMPLE_SEMA = 3,
+ I915_ENGINE_SAMPLE_MAX /* non-ABI */
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+ (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
-#define I915_SAMPLE_RCS0
-#define I915_SAMPLE_VCS1
-#define I915_SAMPLE_BCS2
-#define I915_SAMPLE_VECS 3
+#define __I915_PMU_ENGINE(class, instance, sample) \
+ ((class) << I915_PMU_CLASS_SHIFT | \
+ (instance) << I915_PMU_SAMPLE_BITS | \
+ (sample))
-#define __I915_PERF_COUNT(ring, id) ((ring) << 4 | (id))
+#define I915_PMU_ENGINE_QUEUED(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED)
-#define I915_PERF_COUNT_RCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_RCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_RCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_VCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_BCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_BCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_BCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
-#define I915_PERF_COUNT_VECS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VECS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_VECS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_SEMA)
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
-#define I915_PERF_ACTUAL_FREQUENCY 32
-#define I915_PERF_REQUESTED_FREQUENCY 33
-#define I915_PERF_ENERGY 34
-#define I915_PERF_INTERRUPTS 35
+#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS__I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_RC6p_RESIDENCY
[Intel-gfx] [PATCH i-g-t 0/5] IGT PMU support
From: Tvrtko Ursulin 1. Fixes for intel-gpu-overlay to work on top of the proposed i915 PMU perf API. 2. New test to exercise the same API. Tvrtko Ursulin (5): intel-gpu-overlay: Move local perf implementation to a library intel-gpu-overlay: Consolidate perf PMU access to library intel-gpu-overlay: Fix interrupts PMU readout intel-gpu-overlay: Catch-up to new i915 PMU tests/perf_pmu: Tests for i915 PMU API lib/Makefile.sources | 2 + lib/igt_gt.c | 23 +- lib/igt_gt.h | 8 + lib/igt_perf.c | 59 lib/igt_perf.h | 107 +++ overlay/Makefile.am | 6 +- overlay/gem-interrupts.c | 25 +- overlay/gpu-freq.c | 25 +- overlay/gpu-perf.c | 3 +- overlay/gpu-top.c| 87 +++--- overlay/perf.c | 26 -- overlay/perf.h | 64 - overlay/power.c | 22 +- overlay/rc6.c| 27 +- tests/Makefile.sources | 1 + tests/perf_pmu.c | 713 +++ 16 files changed, 970 insertions(+), 228 deletions(-) create mode 100644 lib/igt_perf.c create mode 100644 lib/igt_perf.h delete mode 100644 overlay/perf.c delete mode 100644 overlay/perf.h create mode 100644 tests/perf_pmu.c -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 3/5] intel-gpu-overlay: Fix interrupts PMU readout
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
overlay/gem-interrupts.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index a84aef0398a7..3eda24f4d7eb 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -136,8 +136,12 @@ int gem_interrupts_update(struct gem_interrupts *irqs)
else
val = ret;
} else {
- if (read(irqs->fd, &val, sizeof(val)) < 0)
+ uint64_t data[2];
+
+ if (read(irqs->fd, &data, sizeof(data)) < 0)
return irqs->error = errno;
+
+ val = data[0];
}
update = irqs->last_count == 0;
--
2.9.5
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[Intel-gfx] [PATCH 4/8] drm/i915/pmu: Suspend sampling when GPU is idle
From: Tvrtko Ursulin
If only a subset of events is enabled we can afford to suspend
the sampling timer when the GPU is idle and so save some cycles
and power.
v2: Rebase and limit timer even more.
v3: Rebase.
v4: Rebase.
v5: Skip action if perf PMU failed to register.
v6: Checkpatch cleanup.
v7:
* Add a common helper to start the timer if needed. (Chris Wilson)
* Add comment explaining bitwise logic in pmu_needs_timer.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_request.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 88 +
4 files changed, 88 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 824372037672..0e0df3b72944 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2252,6 +2252,10 @@ struct i915_pmu {
*/
unsigned int enable_count[I915_PMU_MASK_BITS];
/**
+* @timer_enabled: Should the internal sampling timer be running.
+*/
+ bool timer_enabled;
+ /**
* @sample: Current counter value for i915 events which need sampling.
*
* These counters are updated from the i915 PMU sampling timer.
@@ -4002,9 +4006,13 @@ extern void i915_perf_unregister(struct drm_i915_private
*dev_priv);
#ifdef CONFIG_PERF_EVENTS
void i915_pmu_register(struct drm_i915_private *i915);
void i915_pmu_unregister(struct drm_i915_private *i915);
+void i915_pmu_gt_idle(struct drm_i915_private *i915);
+void i915_pmu_gt_active(struct drm_i915_private *i915);
#else
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_idle(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_active(struct drm_i915_private *i915) {}
#endif
/* i915_suspend.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3250dfaa192b..27ae16abed86 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3227,6 +3227,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
intel_engines_mark_idle(dev_priv);
i915_gem_timelines_mark_idle(dev_priv);
+ i915_pmu_gt_idle(dev_priv);
GEM_BUG_ON(!dev_priv->gt.awake);
dev_priv->gt.awake = false;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 813a3b546d6e..18a1e379253e 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -258,6 +258,7 @@ static void mark_busy(struct drm_i915_private *i915)
i915_update_gfx_val(i915);
if (INTEL_GEN(i915) >= 6)
gen6_rps_busy(i915);
+ i915_pmu_gt_active(i915);
queue_delayed_work(i915->wq,
&i915->gt.retire_work,
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index b0a942f8da74..b7de6fe3cac7 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -90,6 +90,75 @@ static unsigned int event_enabled_bit(struct perf_event
*event)
return config_enabled_bit(event->attr.config);
}
+static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
+{
+ u64 enable;
+
+ /**
+* Only some counters need the sampling timer.
+*
+* We start with a bitmask of all currently enabled events.
+*/
+ enable = i915->pmu.enable;
+
+ /**
+* Mask out all the ones which do not need the timer, or in
+* other words keep all the ones that could need the timer.
+*/
+ enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
+ config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) |
+ ENGINE_SAMPLE_MASK;
+
+ /**
+* When the GPU is idle per-engine counters do not need to be
+* running so clear those bits out.
+*/
+ if (!gpu_active)
+ enable &= ~ENGINE_SAMPLE_MASK;
+
+ /**
+* If some bits remain it means we need the sampling timer running.
+*/
+ return enable;
+}
+
+void i915_pmu_gt_idle(struct drm_i915_private *i915)
+{
+ if (!i915->pmu.base.event_init)
+ return;
+
+ spin_lock_irq(&i915->pmu.lock);
+ /*
+* Signal sampling timer to stop if only engine events are enabled and
+* GPU went idle.
+*/
+ i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
+ spin_unlock_irq(&i915->pmu.lock);
+}
+
+static void __i915_pmu_maybe_start_timer(struct drm_i915_private *i915)
+{
+ if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) {
+ i915->pmu.timer_enabled = true;
+ hrtimer_start_range_ns(&i915->pmu.timer,
+
[Intel-gfx] [PATCH i-g-t 5/5] tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Dmitry Rogozhkin
---
lib/igt_gt.c | 23 +-
lib/igt_gt.h | 8 +
tests/Makefile.sources | 1 +
tests/perf_pmu.c | 713 +
4 files changed, 738 insertions(+), 7 deletions(-)
create mode 100644 tests/perf_pmu.c
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b3809eee..102cc2841feb 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -537,14 +537,23 @@ unsigned intel_detect_and_clear_missed_interrupts(int fd)
return missed;
}
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+ I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
const struct intel_execution_engine intel_execution_engines[] = {
- { "default", NULL, 0, 0 },
- { "render", "rcs0", I915_EXEC_RENDER, 0 },
- { "bsd", "vcs0", I915_EXEC_BSD, 0 },
- { "bsd1", "vcs0", I915_EXEC_BSD, 1<<13 /*I915_EXEC_BSD_RING1*/ },
- { "bsd2", "vcs1", I915_EXEC_BSD, 2<<13 /*I915_EXEC_BSD_RING2*/ },
- { "blt", "bcs0", I915_EXEC_BLT, 0 },
- { "vebox", "vecs0", I915_EXEC_VEBOX, 0 },
+ { "default", NULL, -1, -1, 0, 0 },
+ { "render", "rcs0", I915_ENGINE_CLASS_RENDER, 0, I915_EXEC_RENDER, 0 },
+ { "bsd", "vcs0", I915_ENGINE_CLASS_VIDEO, 0, I915_EXEC_BSD, 0 },
+ { "bsd1", "vcs0", I915_ENGINE_CLASS_VIDEO, 0, I915_EXEC_BSD, 1<<13
/*I915_EXEC_BSD_RING1*/ },
+ { "bsd2", "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD, 2<<13
/*I915_EXEC_BSD_RING2*/ },
+ { "blt", "bcs0", I915_ENGINE_CLASS_COPY, 0, I915_EXEC_BLT, 0 },
+ { "vebox", "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0,
I915_EXEC_VEBOX, 0 },
{ NULL, 0, 0 }
};
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 2579cbd37be7..436041ce9cc0 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -66,6 +66,8 @@ unsigned intel_detect_and_clear_missed_interrupts(int fd);
extern const struct intel_execution_engine {
const char *name;
const char *full_name;
+ int class;
+ int instance;
unsigned exec_id;
unsigned flags;
} intel_execution_engines[];
@@ -78,6 +80,12 @@ extern const struct intel_execution_engine {
e__++) \
for_if (gem_has_ring(fd__, flags__ = e__->exec_id | e__->flags))
+#define for_each_engine_class_instance(fd__, e__) \
+ for ((e__) = intel_execution_engines;\
+(e__)->name; \
+(e__)++) \
+ for_if ((e__)->class > 0)
+
bool gem_can_store_dword(int fd, unsigned int engine);
#endif /* IGT_GT_H */
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index cf542df181a8..4bab6247151c 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -217,6 +217,7 @@ TESTS_progs = \
kms_vblank \
meta_test \
perf \
+ perf_pmu \
pm_backlight \
pm_lpsp \
pm_rc6_residency \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
new file mode 100644
index ..2dbee586dacc
--- /dev/null
+++ b/tests/perf_pmu.c
@@ -0,0 +1,713 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+#include "igt_perf.h"
+
+IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
+
+const double tolerance = 0.02f;
+const unsigned long batch_duration_ns = 1000 * 1000 * 1000 / 2;
+
+static void
+init(int gem_fd, const struct intel_execution_engine *e, uint8_t sample)
+{
+
[Intel-gfx] [PATCH] uapi/drm/i915: document field usage of drm_i915_perf_oa_config
Document the expected length register config pointers (tuple of u32
values).
Signed-off-by: Lionel Landwerlin
---
include/uapi/drm/i915_drm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fd5c103fe88d..20062f30c1b1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1523,6 +1523,11 @@ struct drm_i915_perf_oa_config {
__u32 n_boolean_regs;
__u32 n_flex_regs;
+ /**
+* These fields are pointers to tuples of u32 values (register
+* address, value). For example the expected length of the buffer
+* pointed by mux_regs_ptr should be (2 * sizeof(u32) * n_mux_regs).
+*/
__u64 mux_regs_ptr;
__u64 boolean_regs_ptr;
__u64 flex_regs_ptr;
--
2.14.1
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Re: [Intel-gfx] [PATCH] uapi/drm/i915: document field usage of drm_i915_perf_oa_config
Quoting Lionel Landwerlin (2017-09-18 12:42:41)
> Document the expected length register config pointers (tuple of u32
> values).
>
> Signed-off-by: Lionel Landwerlin
> ---
> include/uapi/drm/i915_drm.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index fd5c103fe88d..20062f30c1b1 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1523,6 +1523,11 @@ struct drm_i915_perf_oa_config {
> __u32 n_boolean_regs;
> __u32 n_flex_regs;
>
> + /**
Not kerneldoc, so /*
> +* These fields are pointers to tuples of u32 values (register
> +* address, value). For example the expected length of the buffer
> +* pointed by mux_regs_ptr should be (2 * sizeof(u32) * n_mux_regs).
s/should be/is/
i.e. expected length of the buffer ... is X.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging
== Series Details == Series: series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging URL : https://patchwork.freedesktop.org/series/30501/ State : failure == Summary == Test kms_ccs: Subgroup pipe-D-bad-pixel-format: skip -> INCOMPLETE (shard-hsw) Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test gem_eio: Subgroup in-flight: dmesg-warn -> DMESG-FAIL (shard-hsw) fdo#102616 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102616 https://bugs.freedesktop.org/show_bug.cgi?id=102616 shard-hswtotal:2313 pass:1213 dwarn:0 dfail:1 fail:13 skip:1040 time:8998s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5724/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/9] drm/i915: Cancel all ready but queued requests when wedging
Quoting Patchwork (2017-09-18 12:51:55) > == Series Details == > > Series: series starting with [CI,1/9] drm/i915: Cancel all ready but queued > requests when wedging > URL : https://patchwork.freedesktop.org/series/30501/ > State : failure > > == Summary == > > Test kms_ccs: > Subgroup pipe-D-bad-pixel-format: > skip -> INCOMPLETE (shard-hsw) > Test perf: > Subgroup polling: > pass -> FAIL (shard-hsw) fdo#102252 > Test gem_eio: > Subgroup in-flight: > dmesg-warn -> DMESG-FAIL (shard-hsw) fdo#102616 > > fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 > fdo#102616 https://bugs.freedesktop.org/show_bug.cgi?id=102616 > > shard-hswtotal:2313 pass:1213 dwarn:0 dfail:1 fail:13 skip:1040 > time:8998s For the record, now pushed. Thanks for the patches and review, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake
== Series Details == Series: drm/i915: add perf support for Coffeelake URL : https://patchwork.freedesktop.org/series/30509/ State : success == Summary == Series 30509v1 drm/i915: add perf support for Coffeelake https://patchwork.freedesktop.org/api/1.0/series/30509/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a: dmesg-warn -> INCOMPLETE (fi-cfl-s) fdo#102294 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:473s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:420s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:525s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:516s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:496s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:484s fi-cfl-s total:239 pass:188 dwarn:22 dfail:0 fail:0 skip:28 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:595s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:428s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:482s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:464s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:466s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:458s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:755s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:579s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:414s 5299e24e48f3c24e612bcdb997d0dc477cdde0d0 drm-tip: 2017y-09m-18d-08h-44m-15s UTC integration manifest ff94048ab5f7 drm/i915/perf: add support for Coffeelake GT2 a6121c1c091c drm/i915/perf: disable clk ratio reports on gen9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5727/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
On Fri, 2017-09-15 at 10:58 -0700, Rodrigo Vivi wrote: > On Thu, Sep 14, 2017 at 09:12:50AM +, Patchwork wrote: > > > > == Series Details == > > > > Series: drm/i915: Miscellaneous fixes to reduce dependency for > > I915_MAX_PIPES > > URL : https://patchwork.freedesktop.org/series/30336/ > > State : warning > > > > == Summary == > > > > Test kms_cursor_legacy: > > Subgroup flip-vs-cursor-crc-legacy: > > pass -> SKIP (shard-hsw) > > Subgroup cursor-vs-flip-atomic: > > pass -> SKIP (shard-hsw) > > Test kms_cursor_crc: > > Subgroup cursor-128x128-random: > > pass -> SKIP (shard-hsw) > > Test kms_draw_crc: > > Subgroup draw-method-rgb565-mmap-cpu-xtiled: > > pass -> SKIP (shard-hsw) > I liked the clean-up on this series very much. > And all patches looks good to me. > Only concern I have are this tests here skiping with > > "Test requirement: !(n >= display.n_pipes)" > > So, could you please double check and see if this is > caused by any change in here? The SKIP's are all on HSW. I'll rerun the tests just for comparison and to check if these tests systematically skip. > > Thanks, > Rodrigo. > > > > > Test kms_flip: > > Subgroup wf_vblank-vs-dpms: > > dmesg-warn -> PASS (shard-hsw) fdo#102614 > > Test gem_flink_race: > > Subgroup flink_close: > > fail -> PASS (shard-hsw) fdo#102655 > > Test perf: > > Subgroup polling: > > fail -> PASS (shard-hsw) fdo#102252 > > Test gem_eio: > > Subgroup in-flight: > > fail -> PASS (shard-hsw) fdo#102616 > > > > fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 > > fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 > > fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 > > fdo#102616 https://bugs.freedesktop.org/show_bug.cgi?id=102616 > > > > shard-hswtotal:2313 pass:1242 > > dwarn:0 dfail:0 fail:12 skip:1059 time:9338s > > > > == Logs == > > > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patc > > hwork_5692/shards.html > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Mika Kahola - Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw
== Series Details == Series: series starting with [1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw URL : https://patchwork.freedesktop.org/series/30502/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2313 pass:1244 dwarn:1 dfail:0 fail:13 skip:1055 time:9597s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5725/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/perf: document field usage of drm_i915_perf_oa_config
== Series Details == Series: drm/i915/perf: document field usage of drm_i915_perf_oa_config URL : https://patchwork.freedesktop.org/series/30511/ State : failure == Summary == Series 30511v1 drm/i915/perf: document field usage of drm_i915_perf_oa_config https://patchwork.freedesktop.org/api/1.0/series/30511/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-skl-6260u) pass -> INCOMPLETE (fi-kbl-r) Test gem_ringfill: Subgroup basic-default-hang: dmesg-warn -> INCOMPLETE (fi-pnv-d510) fdo#101600 Test kms_addfb_basic: Subgroup small-bo: pass -> DMESG-WARN (fi-kbl-7500u) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> INCOMPLETE (fi-kbl-7500u) fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:442s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:419s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:494s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:489s fi-cfl-s total:286 pass:222 dwarn:32 dfail:0 fail:0 skip:31 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:418s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:595s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:427s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:491s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:460s fi-kbl-7500u total:245 pass:222 dwarn:2 dfail:0 fail:0 skip:20 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:585s fi-kbl-r total:118 pass:97 dwarn:0 dfail:0 fail:0 skip:20 fi-pnv-d510 total:156 pass:113 dwarn:0 dfail:0 fail:0 skip:42 fi-skl-6260u total:118 pass:105 dwarn:0 dfail:0 fail:0 skip:12 fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:748s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:492s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:573s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:418s 099f750f912b9dc16d15832b8fc048a4c918e384 drm-tip: 2017y-09m-18d-11h-57m-58s UTC integration manifest 80e0f1f0f9f6 drm/i915/perf: document field usage of drm_i915_perf_oa_config == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5728/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix a typo in i915_ppat_get()
On Thu, 2017-09-14 at 17:51 +, Wang, Zhi A wrote: > Thanks for the comments. V2 has been sent. At least I never received V2, so the fix has still not been merged. Please (re-)send it ASAP. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] meson: Fix IGT_GIT_SHA1 handling
On Fri, Sep 15, 2017 at 01:52:39PM -0700, Jordan Justen wrote:
> Reviewed-by: Jordan Justen
Both patches pushed. Thanks for the review.
>
> On 2017-09-15 06:59:54, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Tell meson about the dependency on version.h. Avoids the compiler
> > falling over on account of IGT_GIT_SHA1 not being there.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > lib/meson.build | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/lib/meson.build b/lib/meson.build
> > index 0d379d90d889..203be520fd3f 100644
> > --- a/lib/meson.build
> > +++ b/lib/meson.build
> > @@ -140,9 +140,9 @@ install_headers(lib_headers)
> > pkgdatadir = join_paths(get_option('prefix'), get_option('datadir'),
> > 'intel-gpu-tools')
> > srcdir = join_paths(meson.source_root(), 'tests')
> >
> > -vcs_tag(input : 'version.h.in', output : 'version.h',
> > - fallback : 'NO-GIT',
> > - command : [ 'git', 'log', '-n1', '--pretty=format:g%h' ] )
> > +lib_version = vcs_tag(input : 'version.h.in', output : 'version.h',
> > + fallback : 'NO-GIT',
> > + command : [ 'git', 'log', '-n1',
> > '--pretty=format:g%h' ] )
> >
> > lib_intermediates = []
> > foreach f: lib_sources
> > @@ -154,7 +154,7 @@ foreach f: lib_sources
> > endif
> >
> > lib = static_library('igt-' + name,
> > -f,
> > + [ f, lib_version ],
> > include_directories: inc,
> > dependencies : lib_deps,
> > c_args : [
> > --
> > 2.13.5
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix a typo in i915_ppat_get()
Sorry I changed the tittle of the patch with a fixes line. You have already given an r-b. :) -Original Message- From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] Sent: Monday, September 18, 2017 4:08 PM To: Wang, Zhi A ; Vivi, Rodrigo Cc: intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; ch...@chris-wilson.co.uk; zhen...@linux.intel.com; Widawsky, Benjamin Subject: Re: [PATCH 1/2] drm/i915: Fix a typo in i915_ppat_get() On Thu, 2017-09-14 at 17:51 +, Wang, Zhi A wrote: > Thanks for the comments. V2 has been sent. At least I never received V2, so the fix has still not been merged. Please (re-)send it ASAP. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add perf support for Coffeelake
== Series Details == Series: drm/i915: add perf support for Coffeelake URL : https://patchwork.freedesktop.org/series/30509/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2313 pass:1244 dwarn:1 dfail:0 fail:13 skip:1055 time:9507s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5727/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 5/5] tests/perf_pmu: Tests for i915 PMU API
Quoting Tvrtko Ursulin (2017-09-18 12:38:40)
> From: Tvrtko Ursulin
>
> A bunch of tests for the new i915 PMU feature.
>
> Parts of the code were initialy sketched by Dmitry Rogozhkin.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> Cc: Dmitry Rogozhkin
> ---
> lib/igt_gt.c | 23 +-
> lib/igt_gt.h | 8 +
> tests/Makefile.sources | 1 +
> tests/perf_pmu.c | 713
> +
> 4 files changed, 738 insertions(+), 7 deletions(-)
> create mode 100644 tests/perf_pmu.c
>
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index b3f3b3809eee..102cc2841feb 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -537,14 +537,23 @@ unsigned intel_detect_and_clear_missed_interrupts(int
> fd)
> return missed;
> }
>
> +enum drm_i915_gem_engine_class {
> + I915_ENGINE_CLASS_OTHER = 0,
> + I915_ENGINE_CLASS_RENDER = 1,
> + I915_ENGINE_CLASS_COPY = 2,
> + I915_ENGINE_CLASS_VIDEO = 3,
> + I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
> + I915_ENGINE_CLASS_MAX /* non-ABI */
> +};
> +
> const struct intel_execution_engine intel_execution_engines[] = {
> - { "default", NULL, 0, 0 },
> - { "render", "rcs0", I915_EXEC_RENDER, 0 },
> - { "bsd", "vcs0", I915_EXEC_BSD, 0 },
> - { "bsd1", "vcs0", I915_EXEC_BSD, 1<<13 /*I915_EXEC_BSD_RING1*/ },
> - { "bsd2", "vcs1", I915_EXEC_BSD, 2<<13 /*I915_EXEC_BSD_RING2*/ },
> - { "blt", "bcs0", I915_EXEC_BLT, 0 },
> - { "vebox", "vecs0", I915_EXEC_VEBOX, 0 },
> + { "default", NULL, -1, -1, 0, 0 },
> + { "render", "rcs0", I915_ENGINE_CLASS_RENDER, 0, I915_EXEC_RENDER, 0
> },
> + { "bsd", "vcs0", I915_ENGINE_CLASS_VIDEO, 0, I915_EXEC_BSD, 0 },
> + { "bsd1", "vcs0", I915_ENGINE_CLASS_VIDEO, 0, I915_EXEC_BSD, 1<<13
> /*I915_EXEC_BSD_RING1*/ },
> + { "bsd2", "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD, 2<<13
> /*I915_EXEC_BSD_RING2*/ },
> + { "blt", "bcs0", I915_ENGINE_CLASS_COPY, 0, I915_EXEC_BLT, 0 },
> + { "vebox", "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0,
> I915_EXEC_VEBOX, 0 },
> { NULL, 0, 0 }
I was anticipating a new struct for the explicit interface so that we
can easily phase out the out with its aliasing.
> };
>
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 2579cbd37be7..436041ce9cc0 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -66,6 +66,8 @@ unsigned intel_detect_and_clear_missed_interrupts(int fd);
> extern const struct intel_execution_engine {
> const char *name;
> const char *full_name;
> + int class;
> + int instance;
> unsigned exec_id;
> unsigned flags;
> } intel_execution_engines[];
> @@ -78,6 +80,12 @@ extern const struct intel_execution_engine {
> e__++) \
> for_if (gem_has_ring(fd__, flags__ = e__->exec_id |
> e__->flags))
>
> +#define for_each_engine_class_instance(fd__, e__) \
> + for ((e__) = intel_execution_engines;\
> +(e__)->name; \
> +(e__)++) \
> + for_if ((e__)->class > 0)
> +
> bool gem_can_store_dword(int fd, unsigned int engine);
>
> #endif /* IGT_GT_H */
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index cf542df181a8..4bab6247151c 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -217,6 +217,7 @@ TESTS_progs = \
> kms_vblank \
> meta_test \
> perf \
> + perf_pmu \
> pm_backlight \
> pm_lpsp \
> pm_rc6_residency \
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> new file mode 100644
> index ..2dbee586dacc
> --- /dev/null
> +++ b/tests/perf_pmu.c
> @@ -0,0 +1,713 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include
> +#
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Silence sparse by using gfp_t
On Mon, 2017-09-04 at 12:08 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-09-04 07:50:38)
> > On Fri, 2017-09-01 at 15:57 +0100, Chris Wilson wrote:
> > > Sparse enforces that GFP flags are only manipulated inside gfp_t locals.
> > >
> > > Fixes: 4d470f7359c4 ("drm/i915: Avoid undefined behaviour of "u32 >> 32"")
> > > Signed-off-by: Chris Wilson
> > > Cc: Joonas Lahtinen
> > > Cc: Tvrtko Ursulin
> >
> > Isn't Fixes: bit much for sparse warning?
>
> Impact: None ?
Well, "Impact: Cosmetic" would be more truthful but complex.
"Backport: None" ?
Could also take the value that is currently causing grief in the Cc:
stable line;
"Backport: v4.8+"
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH 1/2] drm/i915: Enable scanline read for gen9 dsi
From: Uma Shankar
For gen9 platforms, dsi timings are driven from port instead of pipe
(unlike ddi). Thus, we can't rely on pipe registers to get the timing
information. Even scanline register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, causing atomic update failure warnings.
This patch uses pipe framestamp and current timestamp registers
to calculate scanline. This is an indirect way to get the scanline.
It helps resolve atomic update failure for gen9 dsi platforms.
v2: Addressed Ville and Daniel's review comments. Updated the
register MACROs, handled race condition for register reads,
extracted timings from the hwmode. Removed the dependency on
crtc->config to get the encoder type.
v3: Made get scanline function generic
Credits-to: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Chandra Konduru
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/intel_display.c | 60
4 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cc31a5..d9efe83 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 gen9_get_scanline(struct intel_crtc *crtc);
+
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..47668dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
struct drm_vblank_crtc *vblank;
enum pipe pipe = crtc->pipe;
int position, vtotal;
+ struct intel_encoder *encoder;
if (!crtc->active)
return -1;
@@ -792,6 +793,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
+ if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder)
+ if (encoder->type == INTEL_OUTPUT_DSI)
+ return gen9_get_scanline(crtc);
+ }
+
if (IS_GEN2(dev_priv))
position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b03260..85168ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8802,6 +8802,17 @@ enum skl_power_gate {
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358)
+#define GEN7_TIMESTAMP_CTR _MMIO(0x44070)
+
+#define _PIPE_FRMTMSTMP_A 0x70048
+#define _PIPE_FRMTMSTMP_B 0x71048
+#define _IVB_PIPE_FRMTMSTMP_C 0x72048
+#define PIPE_FRMTMSTMP(pipe) \
+ _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \
+ _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C)
+
/* BXT MIPI clock controls */
#define BXT_MAX_VAR_OUTPUT_KHZ 39500
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0871807..601032f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10352,6 +10352,66 @@ static bool needs_scaling(const struct
intel_plane_state *state)
return (src_w != dst_w || src_h != dst_h);
}
+/*
+ * For Gen9 DSI, pipe scanline register will not
+ * work to get the scanline since the timings
+ * are driven from the PORT (unlike DDI encoders).
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+u32 gen9_get_scanline(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 crtc_vblank_start = crtc->base.mode.crtc_vblank_start;
+ u32 crtc_vtotal = crtc->base.mode.crtc_vtotal;
+ u32 crtc_htotal = crtc->base.mode.crtc_htotal;
+ u32 crtc_clock = crtc->base.mode.crtc_clock;
+ u64 scanline = 0, scan_prev_time, scan_curr_time, scan_post_time;
+
+ WARN_ON(!crtc_vtotal);
+ if (!crtc_vtotal)
+ return scanline;
+
+ /* To
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add perf support for Coffeelake
== Series Details == Series: drm/i915: add perf support for Coffeelake URL : https://patchwork.freedesktop.org/series/30512/ State : success == Summary == Series 30512v1 drm/i915: add perf support for Coffeelake https://patchwork.freedesktop.org/api/1.0/series/30512/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 +1 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> FAIL (fi-skl-6700k) fdo#100367 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:375s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:528s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:269s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:503s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:502s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:498s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:562s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:452s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:598s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:442s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:484s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:587s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:555s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s fi-skl-6700k total:289 pass:264 dwarn:0 dfail:0 fail:1 skip:24 time:522s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:575s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:423s 2fc9cff0b670ddda64f5de27b137f0ee9b8d3f4b drm-tip: 2017y-09m-18d-12h-26m-04s UTC integration manifest 789a89beab62 drm/i915/perf: add support for Coffeelake GT2 c583c314a7a7 drm/i915/perf: disable clk ratio reports on gen9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5729/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
From: Uma Shankar
For gen9 platforms, dsi timings are driven from port instead of pipe
(unlike ddi). Thus, we can't rely on pipe registers to get the timing
information. Even scanline register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, causing atomic update failure warnings.
This patch uses pipe framestamp and current timestamp registers
to calculate scanline. This is an indirect way to get the scanline.
It helps resolve atomic update failure for gen9 dsi platforms.
v2: Addressed Ville and Daniel's review comments. Updated the
register MACROs, handled race condition for register reads,
extracted timings from the hwmode. Removed the dependency on
crtc->config to get the encoder type.
v3: Made get scanline function generic
Credits-to: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Chandra Konduru
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/intel_display.c | 60
4 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28ad5da..5178330 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 gen9_get_scanline(struct intel_crtc *crtc);
+
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 003a928..bb30711 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -814,6 +814,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
struct drm_vblank_crtc *vblank;
enum pipe pipe = crtc->pipe;
int position, vtotal;
+ struct intel_encoder *encoder;
if (!crtc->active)
return -1;
@@ -825,6 +826,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
+ if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder)
+ if (encoder->type == INTEL_OUTPUT_DSI)
+ return gen9_get_scanline(crtc);
+ }
+
if (IS_GEN2(dev_priv))
position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a4..47d1241 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8806,6 +8806,17 @@ enum skl_power_gate {
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358)
+#define GEN7_TIMESTAMP_CTR _MMIO(0x44070)
+
+#define _PIPE_FRMTMSTMP_A 0x70048
+#define _PIPE_FRMTMSTMP_B 0x71048
+#define _IVB_PIPE_FRMTMSTMP_C 0x72048
+#define PIPE_FRMTMSTMP(pipe) \
+ _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \
+ _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C)
+
/* BXT MIPI clock controls */
#define BXT_MAX_VAR_OUTPUT_KHZ 39500
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8599e42..c14e8bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10353,6 +10353,66 @@ static bool needs_scaling(const struct
intel_plane_state *state)
return (src_w != dst_w || src_h != dst_h);
}
+/*
+ * For Gen9 DSI, pipe scanline register will not
+ * work to get the scanline since the timings
+ * are driven from the PORT (unlike DDI encoders).
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+u32 gen9_get_scanline(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 crtc_vblank_start = crtc->base.mode.crtc_vblank_start;
+ u32 crtc_vtotal = crtc->base.mode.crtc_vtotal;
+ u32 crtc_htotal = crtc->base.mode.crtc_htotal;
+ u32 crtc_clock = crtc->base.mode.crtc_clock;
+ u64 scanline = 0, scan_prev_time, scan_curr_time, scan_post_time;
+
+ WARN_ON(!crtc_vtotal);
+ if (!crtc_vtotal)
+ return scanline;
+
+ /* To
[Intel-gfx] [PATCH] drm/i915: Return the correct score in i915_ppat_get()
The cache attribute of the required entry has to be the same with the
existing value. After this requirement is met, the futher comparison
should be performed. After this fix, the refined test case can pass.
v2:
- Refine the tittle and comments. (Rodrigo)
Fixes: 4395890a4855 ("drm/i915: Introduce private PAT management")
Cc: Chris Wilson
Cc: Ben Widawsky
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Signed-off-by: Zhi Wang
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5923b51..636ad7d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2965,7 +2965,7 @@ static unsigned int bdw_private_pat_match(u8 src, u8 dst)
};
/* Cache attribute has to be matched. */
- if (GEN8_PPAT_GET_CA(src) == GEN8_PPAT_GET_CA(dst))
+ if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
return 0;
score |= CA_MATCH;
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/i915: Disable DMC powersaving during GT operations
+ Jari & Samu On Tue, 2017-09-12 at 13:48 +0100, Chris Wilson wrote: > Quoting Chris Wilson (2017-09-12 13:37:32) > > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c > > b/drivers/gpu/drm/i915/i915_gem_request.c > > index 813a3b546d6e..3c8ebdb5b0b4 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_request.c > > +++ b/drivers/gpu/drm/i915/i915_gem_request.c > > @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915) > > intel_runtime_pm_get_noresume(i915); > > i915->gt.awake = true; > > > > /* > * The DMC doesn't behave well when it is active (i.e the system is > * idle). It continually tries to toggle DC_STATE_EN causing a > * severe slow down of the rest of the system (severe enough to trigger > * watchdogs and reboot the machine under CI testing). > * > * Known affected firmware: > * - skl_dmc_ver1_26.bin > * - bxt_dmc_ver1_07.bin > */ Has this patch been tested more widely, does it have negative performance effects? Regards, Joonas > > + if (i915->csr.dmc_payload) > > + intel_display_power_get(i915, POWER_DOMAIN_MODESET); > > + -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Ignore duplicate VMA stored within the per-object handle LUT
On Wed, 2017-08-30 at 12:56 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-30 12:07:47)
> > On Wed, 2017-08-23 at 11:20 +0100, Chris Wilson wrote:
> > > Quoting Joonas Lahtinen (2017-08-23 11:05:18)
> > > > On Tue, 2017-08-22 at 12:05 +0100, Chris Wilson wrote:
> > > > > By using drm_gem_flink/drm_gem_open on an object using the same fd, it
> > > > > is possible for a client to create multiple handles pointing to the
> > > > > same
> > > > > object (tied to the same contexts and VMA), as exemplified by
> > > > > igt::gem_handle_to_libdrm_bo(). Since this duplication has been
> > > > > possible
> > > > > since forever, we cannot assume that the handle:(fpriv, object) is
> > > > > unique and so must handle the multiple users of a single VMA.
> > > > >
> > > > > Testcase: igt/gem_close
> > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102355
> > > > > Fixes: d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> > > > > Signed-off-by: Chris Wilson
> > > > > Cc: Tvrtko Ursulin
> > > > > Cc: Joonas Lahtinen
> > > >
> > > >
> > > >
> > > > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > > > @@ -720,6 +720,7 @@ static int eb_lookup_vmas(struct i915_execbuffer
> > > > > *eb)
> > > > > goto err_obj;
> > > > > }
> > > > >
> > > > > + vma->open_count++;
> > > > > list_add(&lut->obj_link, &obj->lut_list);
> > > >
> > > > This code maybe should be in i915_gem.c as "i915_gem_object_add_lut" or
> > > > something.
> > >
> > > I disagree. It's very much tied to being an execbuf only interaction,
> > > that obj/ctx/handle.
> >
> > So how are we going to proceed here? The current proposed solution is
> > very unintuitive, one counter spread over multiple files.
>
> The table is very much for the entertainment of execbuf (and if you
> squint hard, ok not hard at all, so is the rest of GEM), if you were to
> push hard that's where I suggest to shove it.
>
> But I'm not yet seeing the issue with one side being clear where the
> user opens the vma and the other where it is closed by the user.
As long as it's in one file, all good, so execbuf is fine.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Enable scanline read for gen9 dsi
Op 18-09-17 om 15:32 schreef Vidya Srinivas:
> From: Uma Shankar
>
> For gen9 platforms, dsi timings are driven from port instead of pipe
> (unlike ddi). Thus, we can't rely on pipe registers to get the timing
> information. Even scanline register read will not be functional.
> This is causing vblank evasion logic to fail since it relies on
> scanline, causing atomic update failure warnings.
>
> This patch uses pipe framestamp and current timestamp registers
> to calculate scanline. This is an indirect way to get the scanline.
> It helps resolve atomic update failure for gen9 dsi platforms.
>
> v2: Addressed Ville and Daniel's review comments. Updated the
> register MACROs, handled race condition for register reads,
> extracted timings from the hwmode. Removed the dependency on
> crtc->config to get the encoder type.
>
> v3: Made get scanline function generic
>
> Credits-to: Ville Syrjälä
> Signed-off-by: Uma Shankar
> Signed-off-by: Chandra Konduru
> Signed-off-by: Vidya Srinivas
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_irq.c | 7 +
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> drivers/gpu/drm/i915/intel_display.c | 60
>
> 4 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1cc31a5..d9efe83 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
> u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> +u32 gen9_get_scanline(struct intel_crtc *crtc);
> +
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port
> port,
>enum dpio_phy *phy, enum dpio_channel *ch);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5d391e6..47668dd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> struct drm_vblank_crtc *vblank;
> enum pipe pipe = crtc->pipe;
> int position, vtotal;
> + struct intel_encoder *encoder;
>
> if (!crtc->active)
> return -1;
> @@ -792,6 +793,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
>
> + if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder)
> + if (encoder->type == INTEL_OUTPUT_DSI)
> + return gen9_get_scanline(crtc);
I really think we shouldn't loop over all encoders for something as critical as
__intel_get_crtc_scanline..
> + }
> +
> if (IS_GEN2(dev_priv))
> position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0b03260..85168ee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8802,6 +8802,17 @@ enum skl_power_gate {
> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> #define GLK_TX_ESC_CLK_DIV2_MASK0x3FF
>
> +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> +#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358)
> +#define GEN7_TIMESTAMP_CTR _MMIO(0x44070)
> +
> +#define _PIPE_FRMTMSTMP_A0x70048
> +#define _PIPE_FRMTMSTMP_B0x71048
> +#define _IVB_PIPE_FRMTMSTMP_C0x72048
> +#define PIPE_FRMTMSTMP(pipe) \
> + _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \
> + _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C)
> +
> /* BXT MIPI clock controls */
> #define BXT_MAX_VAR_OUTPUT_KHZ 39500
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0871807..601032f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10352,6 +10352,66 @@ static bool needs_scaling(const struct
> intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h);
> }
>
> +/*
> + * For Gen9 DSI, pipe scanline register will not
> + * work to get the scanline since the timings
> + * are driven from the PORT (unlike DDI encoders).
> + * This function will use Framestamp and current
> + * timestamp registers to calculate the scanline.
> + */
> +u32 gen9_get_scanline(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + u32 crtc_vblank_start = crtc->base.mode.crtc_vblank_start;
> + u
[Intel-gfx] ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev9)
== Series Details == Series: i915 PMU and engine busy stats (rev9) URL : https://patchwork.freedesktop.org/series/27488/ State : success == Summary == Series 27488v9 i915 PMU and engine busy stats https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/9/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 +1 Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (fi-cfl-s) fdo#102294 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:460s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:377s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:537s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:271s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:506s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:502s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:546s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:449s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:596s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:434s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:469s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:490s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:584s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:591s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:549s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:507s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:574s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:430s 2fc9cff0b670ddda64f5de27b137f0ee9b8d3f4b drm-tip: 2017y-09m-18d-12h-26m-04s UTC integration manifest 8f9cb14934ff drm/i915: Gate engine stats collection with a static key 7e1acab5b0bc drm/i915/pmu: Wire up engine busy stats to PMU 4f8337b50f17 drm/i915: Engine busy time tracking 6023c9cdd7a0 drm/i915: Wrap context schedule notification 8a0f7b93de83 drm/i915/pmu: Suspend sampling when GPU is idle 3f9f41ba111e drm/i915/pmu: Expose a PMU interface for perf queries c928eecdb02b drm/i915: Extract intel_get_cagf 9a324fdc25b8 drm/i915: Convert intel_rc6_residency_us to ns == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5730/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Enable scanline read for gen9 dsi
On Mon, Sep 18, 2017 at 07:02:21PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For gen9 platforms, dsi timings are driven from port instead of pipe
> (unlike ddi). Thus, we can't rely on pipe registers to get the timing
> information. Even scanline register read will not be functional.
> This is causing vblank evasion logic to fail since it relies on
> scanline, causing atomic update failure warnings.
>
> This patch uses pipe framestamp and current timestamp registers
> to calculate scanline. This is an indirect way to get the scanline.
> It helps resolve atomic update failure for gen9 dsi platforms.
>
> v2: Addressed Ville and Daniel's review comments. Updated the
> register MACROs, handled race condition for register reads,
> extracted timings from the hwmode. Removed the dependency on
> crtc->config to get the encoder type.
>
> v3: Made get scanline function generic
>
> Credits-to: Ville Syrjälä
> Signed-off-by: Uma Shankar
> Signed-off-by: Chandra Konduru
> Signed-off-by: Vidya Srinivas
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_irq.c | 7 +
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> drivers/gpu/drm/i915/intel_display.c | 60
>
> 4 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1cc31a5..d9efe83 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
> u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> +u32 gen9_get_scanline(struct intel_crtc *crtc);
> +
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port
> port,
>enum dpio_phy *phy, enum dpio_channel *ch);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5d391e6..47668dd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> struct drm_vblank_crtc *vblank;
> enum pipe pipe = crtc->pipe;
> int position, vtotal;
> + struct intel_encoder *encoder;
>
> if (!crtc->active)
> return -1;
> @@ -792,6 +793,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
>
> + if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder)
> + if (encoder->type == INTEL_OUTPUT_DSI)
> + return gen9_get_scanline(crtc);
> + }
We're going to want a better way to do this. I think what we could so is
stuff some kind of flag into hwmode->private_flags to indicate that we
should use the frame timestamps instead of the scanline counter.
> +
> if (IS_GEN2(dev_priv))
> position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0b03260..85168ee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8802,6 +8802,17 @@ enum skl_power_gate {
> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> #define GLK_TX_ESC_CLK_DIV2_MASK0x3FF
>
> +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> +#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358)
Just 0x2358. Should be called just GEN4_TIMESTAMP.
If we're going to define that, then we should also define
'ILK_TIMESTAMP_HI 0x70070' for completeness. ILK preferred over GEN5
since this one in particular is a display register.
> +#define GEN7_TIMESTAMP_CTR _MMIO(0x44070)
I would call it 'IVB_TIMESTAMP_CTR' since it's a display register
and doesn't apply to VLV/CHV.
> +
> +#define _PIPE_FRMTMSTMP_A0x70048
> +#define _PIPE_FRMTMSTMP_B0x71048
> +#define _IVB_PIPE_FRMTMSTMP_C0x72048
Leave the pipe C out.
> +#define PIPE_FRMTMSTMP(pipe) \
> + _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \
> + _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C)
_MMIO_PIPE2((pipe), _PIPE_FRMTMSTMP_A)
> +
> /* BXT MIPI clock controls */
> #define BXT_MAX_VAR_OUTPUT_KHZ 39500
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0871807..601032f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10352,6 +10352,66 @@ static bool needs_scaling(const struct
> intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Disable iommu for the mock device
Quoting Chris Wilson (2017-09-14 17:22:40) > On some machines, the iommu cannot allocate a domain for the mock device > causing the dma_map_sg() to fail, and the selftest to fail with -ENOMEM. > For the mock selftests, we are using a fake device and do not care about > iommu; so convince intel_iommu to treat us as a dummy device with an > identity mapping (and no iommu domain). > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101080 > Signed-off-by: Chris Wilson Tested-by: Elizabeth De La Torre Mena > --- > drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > index 678723430d78..38ed006be5be 100644 > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > @@ -146,6 +146,9 @@ struct drm_i915_private *mock_gem_device(void) > dev_set_name(&pdev->dev, "mock"); > dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); > > + /* hack to disable iommu for the fake device; force identity mapping > */ > + pdev->dev.archdata.iommu = (void *)-1; > + > dev_pm_domain_set(&pdev->dev, &pm_domain); > pm_runtime_enable(&pdev->dev); > pm_runtime_dont_use_autosuspend(&pdev->dev); > -- > 2.14.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Enable scanline read for gen9 dsi
On Mon, Sep 18, 2017 at 03:57:38PM +0200, Maarten Lankhorst wrote:
> Op 18-09-17 om 15:32 schreef Vidya Srinivas:
> > From: Uma Shankar
> >
> > For gen9 platforms, dsi timings are driven from port instead of pipe
> > (unlike ddi). Thus, we can't rely on pipe registers to get the timing
> > information. Even scanline register read will not be functional.
> > This is causing vblank evasion logic to fail since it relies on
> > scanline, causing atomic update failure warnings.
> >
> > This patch uses pipe framestamp and current timestamp registers
> > to calculate scanline. This is an indirect way to get the scanline.
> > It helps resolve atomic update failure for gen9 dsi platforms.
> >
> > v2: Addressed Ville and Daniel's review comments. Updated the
> > register MACROs, handled race condition for register reads,
> > extracted timings from the hwmode. Removed the dependency on
> > crtc->config to get the encoder type.
> >
> > v3: Made get scanline function generic
> >
> > Credits-to: Ville Syrjälä
> > Signed-off-by: Uma Shankar
> > Signed-off-by: Chandra Konduru
> > Signed-off-by: Vidya Srinivas
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_irq.c | 7 +
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++
> > drivers/gpu/drm/i915/intel_display.c | 60
> >
> > 4 files changed, 80 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1cc31a5..d9efe83 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private
> > *dev_priv, u16 reg, u32 value,
> > u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32
> > val);
> >
> > +u32 gen9_get_scanline(struct intel_crtc *crtc);
> > +
> > /* intel_dpio_phy.c */
> > void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port
> > port,
> > enum dpio_phy *phy, enum dpio_channel *ch);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 5d391e6..47668dd 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> > *crtc)
> > struct drm_vblank_crtc *vblank;
> > enum pipe pipe = crtc->pipe;
> > int position, vtotal;
> > + struct intel_encoder *encoder;
> >
> > if (!crtc->active)
> > return -1;
> > @@ -792,6 +793,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> > *crtc)
> > if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> > vtotal /= 2;
> >
> > + if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> > + for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder)
> > + if (encoder->type == INTEL_OUTPUT_DSI)
> > + return gen9_get_scanline(crtc);
> I really think we shouldn't loop over all encoders for something as critical
> as __intel_get_crtc_scanline..
> > + }
> > +
> > if (IS_GEN2(dev_priv))
> > position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> > else
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 0b03260..85168ee 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8802,6 +8802,17 @@ enum skl_power_gate {
> > #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> > #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
> >
> > +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> > +#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358)
> > +#define GEN7_TIMESTAMP_CTR _MMIO(0x44070)
> > +
> > +#define _PIPE_FRMTMSTMP_A 0x70048
> > +#define _PIPE_FRMTMSTMP_B 0x71048
> > +#define _IVB_PIPE_FRMTMSTMP_C 0x72048
> > +#define PIPE_FRMTMSTMP(pipe) \
> > + _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \
> > + _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C)
> > +
> > /* BXT MIPI clock controls */
> > #define BXT_MAX_VAR_OUTPUT_KHZ 39500
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 0871807..601032f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10352,6 +10352,66 @@ static bool needs_scaling(const struct
> > intel_plane_state *state)
> > return (src_w != dst_w || src_h != dst_h);
> > }
> >
> > +/*
> > + * For Gen9 DSI, pipe scanline register will not
> > + * work to get the scanline since the timings
> > + * are driven from the PORT (unlike DDI encoders).
> > + * This function will use Framestamp and current
> > + * timestamp registers
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Add debug_gvt to classify GVT-g log messages
On Thu, 2017-09-14 at 10:59 +0800, Shuo Liu wrote: > Add a silimar log mechanism as like drm. Classify GVT-g log messages > as different categories by differnt log functions. > > Signed-off-by: Shuo Liu Please split out the i915 related changes to separate patches in the beginning of the series for easier reviewing. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Move the context descriptor to an inline helper
On Tue, 2017-09-12 at 22:49 +0100, Chris Wilson wrote: > The context descriptor is stored inside the per-engine context state, as > we only need to compute it once and access it frequently. However, > currently only intel_lrc.c has easy access, but i915_guc_submission.c > would like to frequently read it as well, and more so only ever needs > the lower 32bits. Make it an inline as the compiler should be able to > retrieve the value in less instructions than it takes to do the function > call: > > add/remove: 0/1 grow/shrink: 1/0 up/down: 8/-45 (-37) > function old new delta > i915_guc_submit 621 629 +8 > intel_lr_context_descriptor 45 - -45 > > Signed-off-by: Chris Wilson > @@ -78,8 +79,14 @@ struct drm_i915_private; > struct i915_gem_context; > > void intel_lr_context_resume(struct drm_i915_private *dev_priv); > -uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, > - struct intel_engine_cs *engine); > + > +static inline uint64_t There was a perfect opportunity for s/uint64_t/u64/ here. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2.
== Series Details == Series: drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. URL : https://patchwork.freedesktop.org/series/30503/ State : success == Summary == Series 30503v1 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. https://patchwork.freedesktop.org/api/1.0/series/30503/revisions/1/mbox/ Test gem_exec_reloc: Subgroup basic-cpu-read: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup basic-gtt-read: dmesg-warn -> PASS (fi-kbl-7500u) Test gem_exec_store: Subgroup basic-all: dmesg-warn -> PASS (fi-kbl-7500u) Test gem_exec_suspend: Subgroup basic-s3: incomplete -> PASS (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 +1 Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:449s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:467s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:422s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:517s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:521s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:491s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:501s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:541s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:417s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:598s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:408s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:427s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:491s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:474s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:588s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:593s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:543s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:746s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:472s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:416s 0bbe2f0d6a1e69d0ee72ea0c1dcdd93269419024 drm-tip: 2017y-09m-18d-13h-52m-45s UTC integration manifest 45883bf694b6 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5731/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU
Quoting Tvrtko Ursulin (2017-09-18 12:38:13)
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index b7de6fe3cac7..ffba21eeb5d0 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -90,6 +90,11 @@ static unsigned int event_enabled_bit(struct perf_event
> *event)
> return config_enabled_bit(event->attr.config);
> }
>
> +static bool supports_busy_stats(void)
> +{
> + return i915.enable_execlists;
> +}
> +
> static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
> {
> u64 enable;
> @@ -115,6 +120,12 @@ static bool pmu_needs_timer(struct drm_i915_private
> *i915, bool gpu_active)
> */
> if (!gpu_active)
> enable &= ~ENGINE_SAMPLE_MASK;
> + /**
/** kerneldoc?
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Return the correct score in i915_ppat_get()
Quoting Zhi Wang (2017-09-18 14:36:34)
> The cache attribute of the required entry has to be the same with the
> existing value. After this requirement is met, the futher comparison
> should be performed. After this fix, the refined test case can pass.
>
> v2:
>
> - Refine the tittle and comments. (Rodrigo)
>
> Fixes: 4395890a4855 ("drm/i915: Introduce private PAT management")
> Cc: Chris Wilson
> Cc: Ben Widawsky
> Cc: Rodrigo Vivi
> Cc: Joonas Lahtinen
> Signed-off-by: Zhi Wang
> Reviewed-by: Joonas Lahtinen
And pushed, thanks for the followup.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v2.
On Mon, Sep 18, 2017 at 12:12:50PM +0200, Maarten Lankhorst wrote:
> Commit b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.") removed
> the call to wait_for_vblanks and replaced it with flip_done.
>
> Unfortunately legacy_cursor_update was unset too late, and the
> replacement call drm_atomic_helper_wait_for_flip_done() was
> a noop. Make sure that its unset before setup_commit() is
> called to fix this issue.
>
> Changes since v1:
> - Force vblank wait for watermarks not yet converted to atomic too. (Ville)
> - Use for_each_new_intel_crtc_in_state. (Ville)
>
> Signed-off-by: Maarten Lankhorst
> Fixes: b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102675
> Testcase: kms_cursor_crc
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Reported-by: Marta Löfstedt
> Cc: Marta Löfstedt
> Tested-by: Marta Löfstedt
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 45
> +---
> 1 file changed, 26 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8599e425abb1..8d051256da1e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12517,21 +12517,10 @@ static int intel_atomic_commit(struct drm_device
> *dev,
> struct drm_i915_private *dev_priv = to_i915(dev);
> int ret = 0;
>
> - ret = drm_atomic_helper_setup_commit(state, nonblock);
> - if (ret)
> - return ret;
> -
> drm_atomic_state_get(state);
> i915_sw_fence_init(&intel_state->commit_ready,
> intel_atomic_commit_ready);
>
> - ret = intel_atomic_prepare_commit(dev, state);
> - if (ret) {
> - DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
> - i915_sw_fence_commit(&intel_state->commit_ready);
> - return ret;
> - }
> -
> /*
>* The intel_legacy_cursor_update() fast path takes care
>* of avoiding the vblank waits for simple cursor
> @@ -12540,19 +12529,37 @@ static int intel_atomic_commit(struct drm_device
> *dev,
>* updates happen during the correct frames. Gen9+ have
>* double buffered watermarks and so shouldn't need this.
>*
> - * Do this after drm_atomic_helper_setup_commit() and
> - * intel_atomic_prepare_commit() because we still want
> - * to skip the flip and fb cleanup waits. Although that
> - * does risk yanking the mapping from under the display
> - * engine.
> + * Unset state->legacy_cursor_update before the call to
> + * drm_atomic_helper_setup_commit() because otherwise
> + * drm_atomic_helper_wait_for_flip_done() is a noop and
> + * we get FIFO underruns because we didn't wait
> + * for vblank.
>*
>* FIXME doing watermarks and fb cleanup from a vblank worker
>* (assuming we had any) would solve these problems.
>*/
> - if (INTEL_GEN(dev_priv) < 9)
> - state->legacy_cursor_update = false;
> + if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + for_each_new_intel_crtc_in_state(intel_state, crtc,
> new_crtc_state, i)
> + if (new_crtc_state->wm.need_postvbl_update ||
> + new_crtc_state->update_wm_post)
> + state->legacy_cursor_update = false;
Hmm. I guess that's better. But I still don't see why you want to change
this bit of code in this patch. AFAICS it's got nothing to do with the fix
itself, and instead it's just trying to optimize some cursor updates
that were kicked over to the slow path. Or am I missing something?
> + }
> +
> + ret = intel_atomic_prepare_commit(dev, state);
> + if (ret) {
> + DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
> + i915_sw_fence_commit(&intel_state->commit_ready);
> + return ret;
> + }
> +
> + ret = drm_atomic_helper_setup_commit(state, nonblock);
> + if (!ret)
> + ret = drm_atomic_helper_swap_state(state, true);
>
> - ret = drm_atomic_helper_swap_state(state, true);
> if (ret) {
> i915_sw_fence_commit(&intel_state->commit_ready);
>
> --
> 2.14.1
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [CI 7/9] drm/i915/guc: Submit GuC workitems containing coalesced requests
Minor change needed: With removal of i915_guc_wq_reserve and void
i915_guc_wq_unreserve, declaration "struct drm_i915_gem_request" can be
removed from intel_uc.h
On 9/18/2017 3:34 PM, Chris Wilson wrote:
From: Michał Winiarski
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition). This allows us to completely
remove the reservation, replacing it with a compile time check.
v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)
v4: Squash removing wq_resv
v5: Reflect i915_guc_submit argument changes in doc
v6: Rebase on top of execlists reset/restart fix (Chris)
References: https://bugs.freedesktop.org/show_bug.cgi?id=101873
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Jeff McGee
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Signed-off-by: Michał Winiarski
Reviewed-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20170914083216.10192-2-michal.winiar...@intel.com
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 -
drivers/gpu/drm/i915/i915_guc_submission.c | 181 ++---
drivers/gpu/drm/i915/intel_lrc.c | 25 +---
drivers/gpu/drm/i915/intel_uc.h| 11 --
4 files changed, 63 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 62133dd303ac..0364f0d2d76e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2451,8 +2451,6 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
- seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
tot += submissions;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c180ff1423fd..16b31f70114e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -406,63 +406,6 @@ static void guc_stage_desc_fini(struct intel_guc *guc,
memset(desc, 0, sizeof(*desc));
}
-/**
- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
- * @request: request associated with the commands
- *
- * Return: 0 if space is available
- * -EAGAIN if space is not currently available
- *
- * This function must be called (and must return 0) before a request
- * is submitted to the GuC via i915_guc_submit() below. Once a result
- * of 0 has been returned, it must be balanced by a corresponding
- * call to submit().
- *
- * Reservation allows the caller to determine in advance that space
- * will be available for the next submission before committing resources
- * to it, and helps avoid late failures with complicated recovery paths.
- */
-int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
-{
- const size_t wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
- struct guc_process_desc *desc = __get_process_desc(client);
- u32 freespace;
- int ret;
-
- spin_lock_irq(&client->wq_lock);
- freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
- freespace -= client->wq_rsvd;
- if (likely(freespace >= wqi_size)) {
- client->wq_rsvd += wqi_size;
- ret = 0;
- } else {
- client->no_wq_space++;
- ret = -EAGAIN;
- }
- spin_unlock_irq(&client->wq_lock);
-
- return ret;
-}
-
-static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&client->wq_lock, flags);
- client->wq_rsvd += size;
- spin_unlock_irqrestore(&client->wq_lock, flags);
-}
-
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
-{
- const int wqi_size = sizeof(struct guc_wq_item);
- struct i915_guc_client *client = request->i915->guc.execbuf_client;
-
- GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
- guc_client_update_wq_rsvd(client, -wqi_size);
-}
-
/* Construct a Work Item and append it to the GuC's Work Queue */
static void guc_wq_item_append(struct i915_guc_client *client,
struct drm_i915_gem_request *rq)
@@ -476,7 +419,7 @@ static void guc_wq_item_append(struct i915_guc_client
*client,
struct guc_wq_item *wqi;
u32 freespace, tail, wq_off;
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
== Series Details == Series: drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES URL : https://patchwork.freedesktop.org/series/30336/ State : failure == Summary == Series 30336v1 drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES https://patchwork.freedesktop.org/api/1.0/series/30336/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: pass -> FAIL (fi-kbl-7500u) fdo#102672 Test gem_exec_reloc: Subgroup basic-cpu-read: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup basic-gtt-read: dmesg-warn -> PASS (fi-kbl-7500u) Test gem_exec_store: Subgroup basic-all: dmesg-warn -> PASS (fi-kbl-7500u) Test gem_exec_suspend: Subgroup basic-s3: incomplete -> PASS (fi-kbl-7500u) Test kms_busy: Subgroup basic-flip-c: pass -> INCOMPLETE (fi-bxt-j4205) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:446s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:422s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:521s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:208 pass:186 dwarn:0 dfail:0 fail:0 skip:21 fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:492s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:489s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:542s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-2atotal:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:599s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:428s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:408s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:470s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:478s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:490s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:474s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:564s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:415s 0bbe2f0d6a1e69d0ee72ea0c1dcdd93269419024 drm-tip: 2017y-09m-18d-13h-52m-45s UTC integration manifest 00a0126699df drm/i915: Cleanup South Error Interrupts 36d4ab76683c drm/i915: Favor for_each_pipe() macro eeb5874d6d9b drm/i915: Fold IRQ pipe masks ed210993826c drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation b25327e73cdf drm/i915: Don't relay on I915_MAX_PIPES == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5733/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/perf: disable clk ratio reports on gen9
On 18 September 2017 at 12:21, Lionel Landwerlin wrote: > We're doing this on all Gen9 based platforms, let's just check the gen > rather than listing every single platforms. > > Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Disable iommu for the mock device
On 18 September 2017 at 15:22, Chris Wilson wrote: > Quoting Chris Wilson (2017-09-14 17:22:40) >> On some machines, the iommu cannot allocate a domain for the mock device >> causing the dma_map_sg() to fail, and the selftest to fail with -ENOMEM. >> For the mock selftests, we are using a fake device and do not care about >> iommu; so convince intel_iommu to treat us as a dummy device with an >> identity mapping (and no iommu domain). >> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101080 >> Signed-off-by: Chris Wilson > Tested-by: Elizabeth De La Torre Mena Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 00/8] i915 PMU and engine busy stats
Quoting Tvrtko Ursulin (2017-09-18 12:38:06) > From: Tvrtko Ursulin > > Fourth spin of the i915 PMU series. Now with the RFC tag removed. Just to dump one idea that I wanted to report in the overlay: rate of object allocation, deallocation; pages pinned, unpinned; vma bind, unbind. They tend to be the other things I find of interest in reading traces. Now the problem with vma is that it would be nice if it were tied to a context/process. Pid filtering might be interesting... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: add perf support for Coffeelake
== Series Details == Series: drm/i915: add perf support for Coffeelake URL : https://patchwork.freedesktop.org/series/30512/ State : warning == Summary == Test kms_atomic_transition: Subgroup plane-all-transition-nonblocking: fail -> PASS (shard-hsw) fdo#102671 Test kms_busy: Subgroup extended-pageflip-modeset-hang-oldfb-render-A: pass -> SKIP (shard-hsw) Test kms_draw_crc: Subgroup draw-method-xrgb-render-xtiled: pass -> SKIP (shard-hsw) Test kms_atomic: Subgroup plane_primary_legacy: pass -> SKIP (shard-hsw) Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 fdo#102671 https://bugs.freedesktop.org/show_bug.cgi?id=102671 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2313 pass:1243 dwarn:0 dfail:0 fail:12 skip:1058 time:9406s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5729/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
