Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/guc : Removing i915_modparams.enable_guc_loading module
Subject is missing "parameter" in the end. Either keep module parameter
or i915_modparams.
On 10/4/2017 4:26 AM, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC: "enable_guc_loading" and
"enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
Need to change the order of the tag to comply with new convention.
Applies to all patches.
should be as below as per chronology
S-o-b:
Cc:
R-b:
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++--
drivers/gpu/drm/i915/intel_huc.c| 4 ++-
drivers/gpu/drm/i915/intel_uc.c | 51 +
drivers/gpu/drm/i915/intel_uc.h | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +--
12 files changed, 52 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 53e40dd..4fde4b2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2336,8 +2336,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2369,8 +2371,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+
+ }
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2465,7 +2470,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61a4be9..6479b72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3141,9 +3141,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
Is this typo? Should be (dev_priv)->huc.fw.path
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee36..0890341 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64d7852..a32935a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b
Re: [Intel-gfx] [PATCH 04/13] drm/i915: Unify and export gen9+ port_clock calculation.
On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> On Cannonlake the DVFS level selection depends on the
> port clock.
>
> So let's re-org in a way that we can easily export without
> duplicating any code.
>
> v2: Rebased on changes on previous patches
>
> Cc: Mika Kahola
> Cc: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 21 ++---
> drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> 2 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 92eabb6cc1ab..ee64b1a50453 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1297,7 +1297,7 @@ static void cnl_ddi_clock_get(struct
> intel_encoder *encoder,
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
>
> - pipe_config->port_clock = cnl_calc_pll_link(dev_priv,
> pll_id);
> + pipe_config->port_clock = intel_ddi_port_clock(dev_priv,
> pll_id);
>
> ddi_dotclock_get(pipe_config);
> }
> @@ -1353,7 +1353,7 @@ static void skl_ddi_clock_get(struct
> intel_encoder *encoder,
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
>
> - pipe_config->port_clock = skl_calc_pll_link(dev_priv,
> pll_id);
> + pipe_config->port_clock = intel_ddi_port_clock(dev_priv,
> pll_id);
>
> ddi_dotclock_get(pipe_config);
> }
> @@ -1437,11 +1437,26 @@ static void bxt_ddi_clock_get(struct
> intel_encoder *encoder,
> enum port port = intel_ddi_get_encoder_port(encoder);
> enum intel_dpll_id pll_id = port;
>
> - pipe_config->port_clock = bxt_calc_pll_link(dev_priv,
> pll_id);
> + pipe_config->port_clock = intel_ddi_port_clock(dev_priv,
> pll_id);
>
> ddi_dotclock_get(pipe_config);
> }
>
> +int intel_ddi_port_clock(struct drm_i915_private *dev_priv,
> + enum intel_dpll_id pll_id)
> +{
> + if (IS_GEN9_BC(dev_priv)) {
> + return skl_calc_pll_link(dev_priv, pll_id);
> + } else if (IS_GEN9_LP(dev_priv)) {
> + return bxt_calc_pll_link(dev_priv, pll_id);
> + } else if (IS_CANNONLAKE(dev_priv)) {
> + return cnl_calc_pll_link(dev_priv, pll_id);
> + } else {
> + MISSING_CASE(INTEL_GEN(dev_priv));
> + return 0;
> + }
> +}
Personally, I feel that we wouldn't need to unify this. We call
platform specific functions from this intel_ddi_port_clock() and this
is called from platform specific *_ddi_clock_get() routine. Why not
just keep all platform specific functions in one place?
Paolo, any opinions on this one?
> +
> void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 0cab667fff57..fe4650d6db03 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1293,7 +1293,8 @@ bool intel_ddi_is_audio_enabled(struct
> drm_i915_private *dev_priv,
> struct intel_crtc *intel_crtc);
> void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> -
> +int intel_ddi_port_clock(struct drm_i915_private *dev_priv,
> + enum intel_dpll_id pll_id);
> void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
> *crtc_state,
--
Mika Kahola - Intel OTC
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Re: [Intel-gfx] [PATCH v5 1/5] drm/i915/guc : Unifying seq_puts messages
On 10/4/2017 4:25 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separated into a separate patch
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 847f8e8..53e40dd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1616,7 +1616,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2654,7 +2654,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2807,7 +2807,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3683,7 +3683,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(&drrs->mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
There is corresponding "Yes" seq_puts above. Please update that as well.
Commit subject looks little ambiguous. can we say unify seq_puts
messages for feature support.
}
seq_puts(m, "\n");
}
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log.
== Series Details == Series: series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log. URL : https://patchwork.freedesktop.org/series/31363/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1314 dwarn:7 dfail:0 fail:25 skip:1083 time:9971s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5892/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off
== Series Details == Series: series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off URL : https://patchwork.freedesktop.org/series/31361/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1314 dwarn:7 dfail:0 fail:25 skip:1083 time:10035s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5891/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1315 dwarn:7 dfail:0 fail:24 skip:1083 time:9997s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5890/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log.
== Series Details == Series: series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log. URL : https://patchwork.freedesktop.org/series/31363/ State : success == Summary == Series 31363v1 series starting with [1/2] drm/i915/guc: Add GuC Load time to dmesg log. https://patchwork.freedesktop.org/api/1.0/series/31363/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:454s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:397s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:569s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:287s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:531s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:542s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:534s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:552s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:615s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:434s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:590s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:437s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:418s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:470s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:510s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:475s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:496s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:489s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:595s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:655s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:534s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:524s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:578s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:432s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest a62859b3af32 drm/i915/huc: Add HuC Load time to dmesg log. 09abcf680851 drm/i915/guc: Add GuC Load time to dmesg log. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5892/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1314 dwarn:7 dfail:0 fail:25 skip:1083 time:10019s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5889/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to dmesg log.
This patch uses jiffies to calculate the huc
load time.This information can be useful for testing
to know how much time huc takes to load.
v2: Remove debugfs entry. Remove local variable
huc_finish_load. (Daniel, Tvrtko)
v3: Use ktime_get() for more accurate timings.
Ensure the load is successful, before load times
is printed. (Tvrtko, Michal)
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: Sujaritha Sundaresan
Cc: Oscar Mateo Lozano
Cc: Michal Wajdeczko
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8b4b535..972ae63 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -90,6 +90,7 @@ static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
unsigned long offset = 0;
u32 size;
int ret;
+ ktime_t start_load;
ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
if (ret) {
@@ -121,11 +122,14 @@ static int huc_ucode_xfer(struct drm_i915_private
*dev_priv)
I915_WRITE(DMA_COPY_SIZE, size);
/* Start the DMA */
+ start_load = ktime_get();
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
/* Wait for DMA to finish */
ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
+ huc_fw->load_time = ktime_ms_delta(ktime_get(), start_load);
+
DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
/* Disable the bits once DMA is over */
@@ -220,6 +224,9 @@ void intel_huc_init_hw(struct intel_huc *huc)
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
DRM_ERROR("Failed to complete HuC uCode load with ret %d\n",
err);
+ else
+ DRM_DEBUG_DRIVER("Time taken to load HuC %lld ms\n",
+huc->fw.load_time);
return;
}
--
2.7.4
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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
Calculate the time that GuC takes to load using
jiffies. This information could be very useful in
determining if GuC is taking unreasonably long time
to load in a certain platforms.
v2: Calculate time before logs are collected.
Move the guc_load_time variable as a part of
intel_uc_fw struct. Store only final result
which is to be exported to debugfs. (Michal)
Add the load time in the print message as well.
v3: Remove debugfs entry. Remove local variable
guc_finish_load. (Daniel, Tvrtko)
v4: Use ktime_get() instead of jiffies. Use DRM_NOTE
if time taken to load is more than the threshold. On
load times within acceptable range, use DRM_DEBUG_DRIVER
(Tvrtko)
Cc: Chris Wilson
Cc: Tvrtko ursulin
Cc: Daniel Vetter
Cc: Sujaritha Sundaresan
Cc: Oscar Mateo
Cc: Michal Wajdeczko
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_loader.c | 10 +-
drivers/gpu/drm/i915/intel_uc.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index c9e25be..a0b562c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -199,6 +199,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
struct sg_table *sg = vma->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
int i, ret = 0;
+ ktime_t start_load;
/* where RSA signature starts */
offset = guc_fw->rsa_offset;
@@ -225,6 +226,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
+ start_load = ktime_get();
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
/*
@@ -237,13 +239,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
*/
ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
+ guc_fw->load_time = ktime_ms_delta(ktime_get(), start_load);
+
DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
I915_READ(DMA_CTRL), status);
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
DRM_ERROR("GuC firmware signature verification failed\n");
ret = -ENOEXEC;
- }
+ } else if (guc_fw->load_time > 20)
+ DRM_NOTE("Time taken to load GuC is more than the acceptable \
+threshold\n");
DRM_DEBUG_DRIVER("returning %d\n", ret);
@@ -373,6 +379,8 @@ int intel_guc_init_hw(struct intel_guc *guc)
guc->fw.path,
guc->fw.major_ver_found, guc->fw.minor_ver_found);
+ DRM_DEBUG_DRIVER("GuC is loaded in: %lld ms\n",guc->fw.load_time);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 6966349..65b9674 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -136,6 +136,7 @@ struct intel_uc_fw {
uint32_t rsa_offset;
uint32_t ucode_size;
uint32_t ucode_offset;
+ unsigned long long load_time;
};
struct intel_guc_log {
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.IGT: warning for Fix HDMI as dual display on CNL.
== Series Details == Series: Fix HDMI as dual display on CNL. URL : https://patchwork.freedesktop.org/series/31352/ State : warning == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test kms_flip: Subgroup flip-vs-rmfb-interruptible: pass -> DMESG-WARN (shard-hsw) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1314 dwarn:8 dfail:0 fail:24 skip:1083 time:10037s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5888/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off
== Series Details == Series: series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off URL : https://patchwork.freedesktop.org/series/31361/ State : success == Summary == Series 31361v1 series starting with [1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off https://patchwork.freedesktop.org/api/1.0/series/31361/revisions/1/mbox/ fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:478s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:569s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:291s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:527s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:531s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:536s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:519s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:629s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:441s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:597s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:441s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:468s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:508s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:475s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:504s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:583s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:498s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:660s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:470s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:532s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:513s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:582s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:428s fi-blb-e6850 failed to connect after reboot 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest 0abb5f54274b drm/i915/edp: Increase the T12 delay quirk to 1300ms 528f70dcb630 drm/i915/edp: Get the Panel Power Off timestamp after panel is off == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5891/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] Fix compilation on some distros
On Thu, Sep 28, 2017 at 1:40 AM, Petri Latvala wrote: > On Wed, Sep 27, 2017 at 04:08:27PM -0700, James Ausmus wrote: >> Some distros (such as Gentoo) are removing the include of >> sys/sysmacros.h from sys/types.h. Explicitly include sysmacros.h in >> files where we use the minor() and major() functions. >> >> Signed-off-by: James Ausmus > > Reviewed-by: Petri Latvala > Thanks for the review! Can you push? I don't have access rights. Thanks! -James > > >> --- >> lib/igt_debugfs.c | 1 + >> lib/igt_sysfs.c | 1 + >> tools/aubdump.c | 1 + >> 3 files changed, 3 insertions(+) >> >> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c >> index 1e8c8cc3cd44..60b29e3a025a 100644 >> --- a/lib/igt_debugfs.c >> +++ b/lib/igt_debugfs.c >> @@ -25,6 +25,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c >> index 817678bc28ed..f4e306003b01 100644 >> --- a/lib/igt_sysfs.c >> +++ b/lib/igt_sysfs.c >> @@ -24,6 +24,7 @@ >> >> #include >> #include >> +#include >> #include >> #include >> #include >> diff --git a/tools/aubdump.c b/tools/aubdump.c >> index 78d183f49adc..ee4d99b06ed1 100644 >> --- a/tools/aubdump.c >> +++ b/tools/aubdump.c >> @@ -30,6 +30,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> -- >> 2.14.1 >> >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- James Ausmus ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. https://patchwork.freedesktop.org/api/1.0/series/30924/revisions/2/mbox/ fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:457s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:399s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:564s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:288s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:531s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:529s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:544s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:529s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:616s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:436s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:591s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:440s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:417s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:468s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:507s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:478s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:501s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:573s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:494s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:587s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:654s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:473s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:536s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:522s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:579s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:430s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest 5bff72096d0d drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5890/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/edp: Increase the T12 delay quirk to 1300ms
For this specific PCI device, the eDP panel requires a higher
panel power cycle delay of 1300ms where the minimum spec
requirement of panel power cycle delay is 500ms.
This fix in combination with correct timestamp at which we get the
panel power off time fixes the dP AUX CH timeouts seen on various IGT tests.
Fixes: c99a259b4b5192ba ("drm/i915/edp: Add a T12 panel delay quirk to fix
DP AUX CH timeouts")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101144,
https://bugs.freedesktop.org/show_bug.cgi?id=101518
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0fd41cd..ca48bce 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5286,7 +5286,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device
*dev,
* seems sufficient to avoid this problem.
*/
if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
- vbt.t11_t12 = max_t(u16, vbt.t11_t12, 900 * 10);
+ vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to
%d\n",
vbt.t11_t12);
}
--
2.1.4
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[Intel-gfx] [PATCH 1/2] drm/i915/edp: Get the Panel Power Off timestamp after panel is off
Kernel stores the time in jiffies at which the eDP panel is turned off. This should be obtained after the panel is off (after the wait_panel_off). When we next attempt to turn the panel on, we use the difference between the timestamp at which we want to turn the panel on and timestamp at which panel was turned off to ensure that this is equal to panel power cycle delay and if not we wait for the remaining time. Not waiting for the panel power cycle delay can cause the panel to not turn on giving rise to AUX timeouts for the attempted AUX transactions. Cc: Daniel Vetter Cc: Jani Nikula Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101518, https://bugs.freedesktop.org/show_bug.cgi?id=101144 Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 90e756c..0fd41cd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2308,8 +2308,8 @@ static void edp_panel_off(struct intel_dp *intel_dp) I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); - intel_dp->panel_power_off_time = ktime_get_boottime(); wait_panel_off(intel_dp); + intel_dp->panel_power_off_time = ktime_get_boottime(); /* We got a reference when we enabled the VDD. */ intel_display_power_put(dev_priv, intel_dp->aux_power_domain); -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2)
== Series Details == Series: series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2) URL : https://patchwork.freedesktop.org/series/31330/ State : warning == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test gem_pwrite: Subgroup huge-cpu-backwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-cpu-random: fail -> PASS (shard-hsw) Subgroup big-gtt-fbr: fail -> PASS (shard-hsw) Subgroup big-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-cpu-forwards: fail -> PASS (shard-hsw) Subgroup huge-cpu-fbr: fail -> PASS (shard-hsw) Subgroup big-cpu-backwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-backwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-random: fail -> PASS (shard-hsw) Subgroup big-gtt-forwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-fbr: fail -> PASS (shard-hsw) Subgroup big-gtt-backwards: fail -> PASS (shard-hsw) Subgroup big-cpu-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-fbr: fail -> PASS (shard-hsw) Test kms_busy: Subgroup extended-modeset-hang-oldfb-with-reset-render-C: pass -> DMESG-WARN (shard-hsw) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1330 dwarn:8 dfail:0 fail:8 skip:1083 time:9983s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_293/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915/guc : Fixing argument type warning.
Reverting argument type (struct intel_guc *guc) to expected type due to warning.
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7 +--
drivers/gpu/drm/i915/intel_uc.h| 4 ++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a351339..0db1291 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -920,8 +920,9 @@ void i915_guc_policies_init(struct guc_policies *policies)
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
+int i915_guc_submission_shared_objects_init(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = &dev_priv->guc;
struct i915_vma *vma;
void *vaddr;
@@ -949,8 +950,10 @@ int i915_guc_submission_shared_objects_init(struct
intel_guc *guc)
return 0;
}
-void i915_guc_submission_shared_objects_fini(struct intel_guc *guc)
+void i915_guc_submission_shared_objects_fini(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = &dev_priv->guc;
+
ida_destroy(&guc->stage_ids);
i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
i915_vma_unpin_and_release(&guc->stage_desc_pool);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 5106046..7a6c9b1 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -230,10 +230,10 @@ static inline void intel_guc_notify(struct intel_guc *guc)
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
-int i915_guc_submission_shared_objects_init(struct intel_guc *guc);
+int i915_guc_submission_shared_objects_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_shared_objects_fini(struct intel_guc *guc);
+void i915_guc_submission_shared_objects_fini(struct drm_i915_private
*dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
void i915_guc_policies_init(struct guc_policies *policies);
--
1.9.1
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[Intel-gfx] [PATCH 4/5] drm/i915/guc: group initialization of GuC objects
The previous patch has split up the initialization of some of the GuC
objects in 2 different functions, let's pull them back together.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs (Daniele)
v3: Rebase
v4: Rebase
v5: Separated from previous patch
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7 ++---
drivers/gpu/drm/i915/intel_uc.c| 41 +-
drivers/gpu/drm/i915/intel_uc.h| 4 +--
3 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c456c55..a351339 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -920,9 +920,8 @@ void i915_guc_policies_init(struct guc_policies *policies)
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
struct i915_vma *vma;
void *vaddr;
@@ -950,10 +949,8 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
return 0;
}
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_shared_objects_fini(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
-
ida_destroy(&guc->stage_ids);
i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
i915_vma_unpin_and_release(&guc->stage_desc_pool);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 732f188..69239e4 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -423,13 +423,33 @@ static int guc_shared_objects_init(struct intel_guc *guc)
ret = guc_ads_create(guc);
if (ret < 0)
- intel_guc_log_destroy(guc);
+ goto err_logs;
+
+ if (i915_modparams.enable_guc_submission) {
+ /*
+* This is stuff we need to have available at fw load time
+* if we are planning to enable submission later
+*/
+ ret = i915_guc_submission_shared_objects_init(guc);
+ if (ret)
+ goto err_ads;
+ }
+
+ return 0;
+
+err_ads:
+ guc_ads_destroy(guc);
+err_logs:
+ intel_guc_log_destroy(guc);
return ret;
}
static void guc_shared_objects_fini(struct intel_guc *guc)
{
+ if (i915_modparams.enable_guc_submission)
+ i915_guc_submission_shared_objects_fini(guc);
+
guc_ads_destroy(guc);
intel_guc_log_destroy(guc);
}
@@ -452,16 +472,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_guc;
- if (i915_modparams.enable_guc_submission) {
- /*
-* This is stuff we need to have available at fw load time
-* if we are planning to enable submission later
-*/
- ret = i915_guc_submission_init(dev_priv);
- if (ret)
- goto err_shared;
- }
-
/* init WOPCM */
I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
I915_WRITE(DMA_GUC_WOPCM_OFFSET,
@@ -481,7 +491,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
*/
ret = __intel_uc_reset_hw(dev_priv);
if (ret)
- goto err_submission;
+ goto err_shared;
intel_huc_init_hw(&dev_priv->huc);
ret = intel_guc_init_hw(&dev_priv->guc);
@@ -526,11 +536,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
gen9_disable_guc_interrupts(dev_priv);
err_log_capture:
guc_capture_load_err_log(guc);
-err_submission:
- if (i915_modparams.enable_guc_submission)
- i915_guc_submission_fini(dev_priv);
err_shared:
- guc_shared_objects_fini(guc);
+ guc_shared_objects_fini(guc);
err_guc:
i915_ggtt_disable_guc(dev_priv);
@@ -567,7 +574,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (i915_modparams.enable_guc_submission) {
gen9_disable_guc_interrupts(dev_priv);
- i915_guc_submission_fini(dev_priv);
+ i915_guc_submission_shared_objects_fini(dev_priv);
}
guc_shared_objects_fini(&dev_priv->guc);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 0d12ff4..5106046 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -230,10 +230,10 @@ static inline void intel_guc_notify(s
[Intel-gfx] [PATCH v5 3/5] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs (Daniele)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 114 +---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 115 -
drivers/gpu/drm/i915/intel_uc.h| 1 +
4 files changed, 121 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 04f1281..c456c55 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -71,13 +71,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -904,7 +897,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -924,88 +917,6 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(&blob->policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it. Note that we have to skip our header (1 page),
-* because our GuC shared data is there.
-*/
- blob->ads.golden_context_lrca =
- guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
skipped_offset;
-
- /*
-* The GuC expects us to exclude the portion of the context image that
-* it skips from the size it is to read. It starts reading from after
-* the execlist context (so skipping the first page [PPHWSP] and 80
-* dwords). Weird guc is weird.
-
[Intel-gfx] [PATCH v5 2/5] drm/i915/guc : Removing i915_modparams.enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++--
drivers/gpu/drm/i915/intel_huc.c| 4 ++-
drivers/gpu/drm/i915/intel_uc.c | 51 +
drivers/gpu/drm/i915/intel_uc.h | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +--
12 files changed, 52 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 53e40dd..4fde4b2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2336,8 +2336,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2369,8 +2371,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+
+ }
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2465,7 +2470,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61a4be9..6479b72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3141,9 +3141,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee36..0890341 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64d7852..a32935a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3292,7 +3292,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
+ if (NEEDS_GUC_LOADING(dev_priv)) {
[Intel-gfx] [PATCH v5 1/5] drm/i915/guc : Unifying seq_puts messages
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separated into a separate patch
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 847f8e8..53e40dd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1616,7 +1616,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2654,7 +2654,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2807,7 +2807,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3683,7 +3683,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(&drrs->mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/5] Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simpily unifies different seq_puts messages found in debugfs. In earlier verions, Patch 1 and 2 were previuosly in one single patch. Patch 2 focuses on replacing the enable_guc_loading module. Patch 3 and 4 deal with decoupling guc logs and ADS from submission. Patch 5 fixes a warning generated as a result of patch 4. Cc: Anusha Srivatsa Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Oscar Mateo Cc: Sagar Arun Kamble Sujaritha Sundaresan (5): drm/i915/guc : Unifying seq_puts messages drm/i915/guc : Removing i915_modparams.enable_guc_loading module drm/i915/guc : Decouple logs and ADS from submission drm/i915/guc : group initialization of GuC objects drm/i915/guc : Fixing argument type warning drivers/gpu/drm/i915/i915_debugfs.c| 21 +-- drivers/gpu/drm/i915/i915_drv.h| 9 +- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 118 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 5 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc_loader.c| 7 +- drivers/gpu/drm/i915/intel_guc_log.c | 6 +- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 199 +++-- drivers/gpu/drm/i915/intel_uc.h| 7 +- drivers/gpu/drm/i915/intel_uncore.c| 4 +- 14 files changed, 202 insertions(+), 185 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/30924/ State : failure == Summary == Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. https://patchwork.freedesktop.org/api/1.0/series/30924/revisions/2/mbox/ Test kms_busy: Subgroup basic-flip-b: pass -> DMESG-WARN (fi-skl-6700k) Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-skl-6700k) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> INCOMPLETE (fi-kbl-7560u) fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:457s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:471s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:401s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:559s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:290s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:532s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:543s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:528s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:558s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:609s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:429s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:598s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:438s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:420s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:464s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:507s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:473s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:502s fi-kbl-7560u total:245 pass:228 dwarn:0 dfail:0 fail:0 skip:16 fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:487s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:663s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:470s fi-skl-6700k total:289 pass:263 dwarn:2 dfail:0 fail:0 skip:24 time:535s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:509s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:580s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:427s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest c879014a35c0 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5889/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix HDMI as dual display on CNL.
== Series Details == Series: Fix HDMI as dual display on CNL. URL : https://patchwork.freedesktop.org/series/31352/ State : success == Summary == Series 31352v1 Fix HDMI as dual display on CNL. https://patchwork.freedesktop.org/api/1.0/series/31352/revisions/1/mbox/ fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:457s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:393s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:565s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:287s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:526s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:530s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:544s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:529s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:555s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:620s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:431s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:592s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:444s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:418s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:467s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:506s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:481s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:504s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:491s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:591s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:656s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:537s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:523s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:481s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:582s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:436s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest aaae0f2562ab drm/i915/cnl: Fix PLL initialization for HDMI. 94b2a3780dfe drm/i915/cnl: Fix PLL mapping. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5888/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
This is heavily based on a initial patch provided by Ville
plus all changes provided later by Ander.
As Geminilake, Cannonlake also supports 2 pixels per clock.
Different from Geminilake we are not implementing the 99% Wa.
But we can revisit that decision later if we find out
any limitation on later CNL SKUs.
v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
minimum acceptable cdclk instead of "minimum dotclock")'
v3: When fixing HDMI on CNL I noticed that I missed to convert
back the doubled pixel rate to cdclk.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c | 14 ++
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
3 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 58ee4dd07cf6..bdb95b75c9d4 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct
drm_i915_private *dev_priv,
int pixel_rate)
{
if (INTEL_GEN(dev_priv) >= 10)
- /*
-* FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
-* once DDI clock voltage requirements are
-* handled correctly.
-*/
- return pixel_rate;
+ return DIV_ROUND_UP(pixel_rate, 2);
else if (IS_GEMINILAKE(dev_priv))
/*
* FIXME: Avoid using a pixel clock that is more than 99% of
the cdclk
@@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
int max_cdclk_freq = dev_priv->max_cdclk_freq;
if (INTEL_GEN(dev_priv) >= 10)
- /*
-* FIXME: Allow '2 * max_cdclk_freq'
-* once DDI clock voltage requirements are
-* handled correctly.
-*/
- return max_cdclk_freq;
+ return 2 * max_cdclk_freq;
else if (IS_GEMINILAKE(dev_priv))
/*
* FIXME: Limiting to 99% as a temporary workaround. See
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b7a6ddc6a66d..644759aff069 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
max_dotclk =
to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
- if (IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
max_dotclk *= 2;
if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 171b21f6c4ad..ede871b7982e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state
*crtc_state)
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
struct intel_crtc_state *cstate)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
struct drm_crtc_state *crtc_state = &cstate->base;
struct drm_atomic_state *state = crtc_state->state;
struct drm_plane *plane;
@@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
crtc_clock = crtc_state->adjusted_mode.crtc_clock;
dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
- if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
dotclk *= 2;
pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
--
2.13.5
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[Intel-gfx] ✓ Fi.CI.IGT: success for lib: Assert that the internal gem_create interface matches the ioctl
== Series Details == Series: lib: Assert that the internal gem_create interface matches the ioctl URL : https://patchwork.freedesktop.org/series/31329/ State : success == Summary == Test gem_pwrite: Subgroup huge-cpu-fbr: fail -> PASS (shard-hsw) Subgroup huge-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-gtt-fbr: fail -> PASS (shard-hsw) Subgroup big-gtt-fbr: fail -> PASS (shard-hsw) Subgroup big-gtt-backwards: fail -> PASS (shard-hsw) Subgroup huge-cpu-random: fail -> PASS (shard-hsw) Subgroup huge-gtt-backwards: fail -> PASS (shard-hsw) Subgroup big-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-cpu-forwards: fail -> PASS (shard-hsw) Subgroup big-gtt-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-backwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-random: fail -> PASS (shard-hsw) Subgroup big-cpu-fbr: fail -> PASS (shard-hsw) Subgroup huge-cpu-backwards: fail -> PASS (shard-hsw) Subgroup big-cpu-forwards: fail -> PASS (shard-hsw) Test gem_eio: Subgroup wait: dmesg-warn -> PASS (shard-hsw) fdo#102886 Test prime_self_import: Subgroup reimport-vs-gem_close-race: pass -> FAIL (shard-hsw) fdo#102655 Test kms_flip: Subgroup flip-vs-expired-vblank-interruptible: pass -> FAIL (shard-hsw) fdo#102887 Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886 fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1330 dwarn:6 dfail:0 fail:10 skip:1083 time:10110s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_292/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Fix PLL mapping.
On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on
the clock for the DDI and map the DPLL to the DDI"
So we first do the map and then we unset DDI_CLK_OFF to turn the clock
on. We do this in 2 separated steps.
However, on this second step where we should only unset the off bit we are
also unmapping the ddi from the pll. So we end up using the pll 0
for almost everything. Consequently breaking cases with more than one
display.
Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
Cc: Paulo Zanoni
Cc: Manasi Navare
Cc: Kahola, Mika
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 55c43b333d3c..bf8ec0bd349f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2144,8 +2144,7 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
* register writes.
*/
val = I915_READ(DPCLKA_CFGCR0);
- val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
-DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
I915_WRITE(DPCLKA_CFGCR0, val);
} else if (IS_GEN9_BC(dev_priv)) {
/* DDI -> PLL mapping */
--
2.13.5
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[Intel-gfx] [PATCH 0/2] Fix HDMI as dual display on CNL.
HDMI + any other display wasn't working on CNL. Luckly in few cases BIOS setup things properly for us so we took a while to catch this bugs here. But with these 2 patches we got multiple display with hot plug working properly on CNL. Thanks, Rodrigo. Rodrigo Vivi (2): drm/i915/cnl: Fix PLL mapping. drm/i915/cnl: Fix PLL initialization for HDMI. drivers/gpu/drm/i915/intel_ddi.c | 3 +-- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix PLL initialization for HDMI.
HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
on in a global CTRL1 as it was on SKL.
The original patch addressed this difference, but leaving behind
this single entry here. So we were checking the wrong bits during
the PLL initialization and consequently avoiding the CFGCR1 setup
during HDMI initialization. Luckly when only HDMI was in use BIOS
had already setup this for us. But the dual display with hot plug
were messed up.
Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs")
Cc: Paulo Zanoni
Cc: Manasi Navare
Cc: Kahola, Mika
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 55997389a29f..032fd915e929 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2000,7 +2000,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private
*dev_priv,
/* 3. Configure DPLL_CFGCR0 */
/* Avoid touch CFGCR1 if HDMI mode is not enabled */
- if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
+ if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
val = pll->state.hw_state.cfgcr1;
I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
/* 4. Reab back to ensure writes completed */
--
2.13.5
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Update the DMC version on CNL
== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : warning == Summary == Test kms_mmio_vs_cs_flip: Subgroup setplane_vs_cs_flip: pass -> SKIP (shard-hsw) Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1312 dwarn:7 dfail:0 fail:26 skip:1084 time:10018s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5885/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD
== Series Details == Series: series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD URL : https://patchwork.freedesktop.org/series/31350/ State : warning == Summary == Series 31350v1 series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD https://patchwork.freedesktop.org/api/1.0/series/31350/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-flip-after-cursor-legacy: pass -> DMESG-WARN (fi-bxt-dsi) fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:467s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:482s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:399s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:569s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:289s fi-bxt-dsi total:289 pass:258 dwarn:1 dfail:0 fail:0 skip:30 time:536s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:537s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:546s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:538s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:571s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:634s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:438s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:598s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:444s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:417s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:470s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:498s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:503s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:583s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:492s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:669s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:479s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:537s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:524s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:474s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:584s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:437s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest 476fa7061ed8 drm/i915/scheduler: Support user-defined priorities fcef1b9da6f5 drm/i915/execlists: Preemption! 80fd5334c8e1 drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask ca9d057a5788 drm/i915/execlists: Keep request->priority for its lifetime 95c67d878d4f drm/i915/execlists: Move bdw GPGPU w/a to emit_bb 3b9484d04dd0 drm/i915: Introduce a preempt context 6f00d4774d40 drm/i915/execlists: Distinguish the incomplete context notifies 27f4e56e982f drm/i915/preempt: Default to disabled mid-command preemption levels 2fe1ac1a5b7c drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5887/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2)
== Series Details == Series: series starting with tests/kms_color: Unset plane fb on teardown, v2. (rev2) URL : https://patchwork.freedesktop.org/series/31330/ State : success == Summary == IGT patchset tested on top of latest successful build 7fd0cae99630f954cfe0089b4b7e91576a353582 lib: Fixup __gem_create() to be 64b safe. with latest DRM-Tip kernel build CI_DRM_3169 654360cf73fe drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest No testlist changes. Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-cfl-s) fdo#103026 fdo#103026 https://bugs.freedesktop.org/show_bug.cgi?id=103026 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:395s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:587s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:291s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:532s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:531s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:548s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:538s fi-cfl-s total:289 pass:257 dwarn:0 dfail:0 fail:0 skip:32 time:573s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:638s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:438s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:592s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:438s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:471s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:513s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:481s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:503s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:469s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:539s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:514s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:479s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:597s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:439s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_293/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Update the DMC version on CNL
== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : warning == Summary == Test kms_cursor_crc: Subgroup cursor-128x128-random: pass -> SKIP (shard-hsw) Test kms_force_connector_basic: Subgroup force-load-detect: skip -> PASS (shard-hsw) Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1314 dwarn:7 dfail:0 fail:25 skip:1083 time:9971s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5884/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU (rev2)
Quoting Patchwork (2017-10-03 17:07:51) > == Series Details == > > Series: lib: Ask the kernel to quiescent the GPU (rev2) > URL : https://patchwork.freedesktop.org/series/30890/ > State : failure > > == Summary == > > IGT patchset tested on top of latest successful build > 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from > __gem_create() > > with latest DRM-Tip kernel build CI_DRM_3167 > 5a0359bf59aa drm-tip: 2017y-10m-03d-13h-34m-56s UTC integration manifest > > No testlist changes. > > Test chamelium: > Subgroup dp-crc-fast: > pass -> FAIL (fi-kbl-7500u) fdo#102514 > Test gem_sync: > Subgroup basic-all: > pass -> DMESG-FAIL (fi-blb-e6850) > pass -> FAIL (fi-pnv-d510) Still all clean on my own pnv n570. Both of those are desktop, whereas mine is a mobile part, but that shouldn't make any difference... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 6/9] drm/i915/execlists: Keep request->priority for its lifetime
With preemption, we will want to "unsubmit" a request, taking it back
from the hw and returning it to the priority sorted execution list. In
order to know where to insert it into that list, we need to remember
its adjust priority (which may change even as it was being executed).
This also affects reset for execlists as we are now unsubmitting the
requests following the reset (rather than directly writing the ELSP for
the inflight contexts). This turns reset into an accidental preemption
point, as after the reset we may choose a different pair of contexts to
submit to hw.
GuC is not updated as this series doesn't add preemption to the GuC
submission, and so it can keep benefiting from the early pruning of the
DFS inside execlists_schedule() for a little longer. We also need to
find a way of reducing the cost of that DFS...
v2: Include priority in error-state
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Reviewed-by: Michał Winiarski
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++
drivers/gpu/drm/i915/intel_lrc.c | 14 ++
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 31292afb961d..1fc7080bfa7b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -982,6 +982,7 @@ struct i915_gpu_state {
pid_t pid;
u32 handle;
u32 hw_id;
+ int priority;
int ban_score;
int active;
int guilty;
@@ -1004,6 +1005,7 @@ struct i915_gpu_state {
long jiffies;
pid_t pid;
u32 context;
+ int priority;
int ban_score;
u32 seqno;
u32 head;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c14552ab270b..dc91b32d699e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -377,9 +377,9 @@ static void error_print_request(struct
drm_i915_error_state_buf *m,
if (!erq->seqno)
return;
- err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms
ago, head %08x, tail %08x\n",
+ err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d,
emitted %dms ago, head %08x, tail %08x\n",
prefix, erq->pid, erq->ban_score,
- erq->context, erq->seqno,
+ erq->context, erq->seqno, erq->priority,
jiffies_to_msecs(jiffies - erq->jiffies),
erq->head, erq->tail);
}
@@ -388,9 +388,9 @@ static void error_print_context(struct
drm_i915_error_state_buf *m,
const char *header,
const struct drm_i915_error_context *ctx)
{
- err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d
active %d\n",
+ err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d
guilty %d active %d\n",
header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
- ctx->ban_score, ctx->guilty, ctx->active);
+ ctx->priority, ctx->ban_score, ctx->guilty, ctx->active);
}
static void error_print_engine(struct drm_i915_error_state_buf *m,
@@ -1271,6 +1271,7 @@ static void record_request(struct drm_i915_gem_request
*request,
struct drm_i915_error_request *erq)
{
erq->context = request->ctx->hw_id;
+ erq->priority = request->priotree.priority;
erq->ban_score = atomic_read(&request->ctx->ban_score);
erq->seqno = request->global_seqno;
erq->jiffies = request->emitted_jiffies;
@@ -1364,6 +1365,7 @@ static void record_context(struct drm_i915_error_context
*e,
e->handle = ctx->user_handle;
e->hw_id = ctx->hw_id;
+ e->priority = ctx->priority;
e->ban_score = atomic_read(&ctx->ban_score);
e->guilty = atomic_read(&ctx->guilty_count);
e->active = atomic_read(&ctx->active_count);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e5b470ce43e8..02ea1e4e098b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -585,8 +585,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
INIT_LIST_HEAD(&rq->priotree.link);
- rq->priotree.priority = INT_MAX;
-
__i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port,
execlists));
last = rq;
@@ -794,6 +792,7 @@ static void intel_lrc_irq_handler(unsigned long data)
[Intel-gfx] [CI 4/9] drm/i915: Introduce a preempt context
Add another perma-pinned context for using for preemption at any time.
We cannot just reuse the existing kernel context, as first and foremost
we need to ensure that we can preempt the kernel context itself, so
require a distinct context id. Similar to the kernel context, we may
want to interrupt execution and switch to the preempt context at any
time, and so it needs to be permanently pinned and available.
To compensate for yet another permanent allocation, we shrink the
existing context and the new context by reducing their ringbuffer to the
minimum.
v2: Assert that we never allocate a request from the preemption context.
v3: Limit perma-pin to engines that may preempt.
v4: Onion cleanup for early driver death
v5: Onion ordering in main driver cleanup as well.
Signed-off-by: Chris Wilson
Reviewed-by: Michał Winiarski
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++-
drivers/gpu/drm/i915/i915_gem_context.c | 76 -
drivers/gpu/drm/i915/i915_gem_request.c | 7 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 22 +-
4 files changed, 87 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ca11318ac69..31292afb961d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -783,6 +783,7 @@ struct intel_csr {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+ func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_pipe_cxsr); \
func(has_pooled_eu); \
@@ -2251,8 +2252,11 @@ struct drm_i915_private {
wait_queue_head_t gmbus_wait_queue;
struct pci_dev *bridge_dev;
- struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
+ /* Context used internally to idle the GPU and setup initial state */
+ struct i915_gem_context *kernel_context;
+ /* Context only to be used for injecting preemption commands */
+ struct i915_gem_context *preempt_context;
struct i915_vma *semaphore;
struct drm_dma_handle *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee369c74d..2bb8e58706ba 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -416,14 +416,43 @@ i915_gem_context_create_gvt(struct drm_device *dev)
return ctx;
}
+static struct i915_gem_context *
+create_kernel_context(struct drm_i915_private *i915, int prio)
+{
+ struct i915_gem_context *ctx;
+
+ ctx = i915_gem_create_context(i915, NULL);
+ if (IS_ERR(ctx))
+ return ctx;
+
+ i915_gem_context_clear_bannable(ctx);
+ ctx->priority = prio;
+ ctx->ring_size = PAGE_SIZE;
+
+ GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+
+ return ctx;
+}
+
+static void
+destroy_kernel_context(struct i915_gem_context **ctxp)
+{
+ struct i915_gem_context *ctx;
+
+ /* Keep the context ref so that we can free it immediately ourselves */
+ ctx = i915_gem_context_get(fetch_and_zero(ctxp));
+ GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+
+ context_close(ctx);
+ i915_gem_context_free(ctx);
+}
+
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
+ int err;
- /* Init should only be called once per module load. Eventually the
-* restriction on the context_disabled check can be loosened. */
- if (WARN_ON(dev_priv->kernel_context))
- return 0;
+ GEM_BUG_ON(dev_priv->kernel_context);
INIT_LIST_HEAD(&dev_priv->contexts.list);
INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
@@ -441,28 +470,38 @@ int i915_gem_contexts_init(struct drm_i915_private
*dev_priv)
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
ida_init(&dev_priv->contexts.hw_ida);
- ctx = i915_gem_create_context(dev_priv, NULL);
+ /* lowest priority; idle task */
+ ctx = create_kernel_context(dev_priv, I915_PRIORITY_MIN);
if (IS_ERR(ctx)) {
- DRM_ERROR("Failed to create default global context (error
%ld)\n",
- PTR_ERR(ctx));
- return PTR_ERR(ctx);
+ DRM_ERROR("Failed to create default global context\n");
+ err = PTR_ERR(ctx);
+ goto err;
}
-
- /* For easy recognisablity, we want the kernel context to be 0 and then
+ /*
+* For easy recognisablity, we want the kernel context to be 0 and then
* all user contexts will have non-zero hw_id.
*/
GEM_BUG_ON(ctx->hw_id);
-
- i915_gem_context_clear_bannable(ctx);
- ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
dev_priv->kernel_context = ctx;
- GEM_BUG_ON(!i915
[Intel-gfx] [CI 3/9] drm/i915/execlists: Distinguish the incomplete context notifies
Let the listener know that the context we just scheduled out was not
complete, and will be scheduled back in at a later point.
v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to
CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference
later.
Signed-off-by: Chris Wilson
Cc: "Zhenyu Wang"
Cc: "Wang, Zhi A"
Cc: Michał Winiarski
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.h | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index d5892d24f0b6..f6ded475bb2c 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -174,6 +174,7 @@ static int shadow_context_status_change(struct
notifier_block *nb,
atomic_set(&workload->shadow_ctx_active, 1);
break;
case INTEL_CONTEXT_SCHEDULE_OUT:
+ case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
atomic_set(&workload->shadow_ctx_active, 0);
break;
default:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7d6da130b184..0f6c839d65a1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -618,7 +618,7 @@ execlist_cancel_port_requests(struct intel_engine_execlists
*execlists)
while (num_ports-- && port_isset(port)) {
struct drm_i915_gem_request *rq = port_request(port);
- execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
+ execlists_context_status_change(rq,
INTEL_CONTEXT_SCHEDULE_PREEMPTED);
i915_gem_request_put(rq);
memset(port, 0, sizeof(*port));
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 314adee7127a..689fde1a63a9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -61,6 +61,7 @@
enum {
INTEL_CONTEXT_SCHEDULE_IN = 0,
INTEL_CONTEXT_SCHEDULE_OUT,
+ INTEL_CONTEXT_SCHEDULE_PREEMPTED,
};
/* Logical Rings */
--
2.14.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 8/9] drm/i915/execlists: Preemption!
When we write to ELSP, it triggers a context preemption at the earliest
arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other
operations and the explicit MI_ARB_CHECK). If this is to the same
context, it triggers a LITE_RESTORE where the RING_TAIL is merely
updated (used currently to chain requests from the same context
together, avoiding bubbles). However, if it is to a different context, a
full context-switch is performed and it will start to execute the new
context saving the image of the old for later execution.
Previously we avoided preemption by only submitting a new context when
the old was idle. But now we wish embrace it, and if the new request has
a higher priority than the currently executing request, we write to the
ELSP regardless, thus triggering preemption, but we tell the GPU to
switch to our special preemption context (not the target). In the
context-switch interrupt handler, we know that the previous contexts
have finished execution and so can unwind all the incomplete requests
and compute the new highest priority request to execute.
It would be feasible to avoid the switch-to-idle intermediate by
programming the ELSP with the target context. The difficulty is in
tracking which request that should be whilst maintaining the dependency
change, the error comes in with coalesced requests. As we only track the
most recent request and its priority, we may run into the issue of being
tricked in preempting a high priority request that was followed by a
low priority request from the same context (e.g. for PI); worse still
that earlier request may be our own dependency and the order then broken
by preemption. By injecting the switch-to-idle and then recomputing the
priority queue, we avoid the issue with tracking in-flight coalesced
requests. Having tried the preempt-to-busy approach, and failed to find
a way around the coalesced priority issue, Michal's original proposal to
inject an idle context (based on handling GuC preemption) succeeds.
The current heuristic for deciding when to preempt are only if the new
request is of higher priority, and has the privileged priority of
greater than 0. Note that the scheduler remains unfair!
v2: Disable for gen8 (bdw/bsw) as we need additional w/a for GPGPU.
Since, the feature is now conditional and not always available when we
have a scheduler, make it known via the HAS_SCHEDULER GETPARAM (now a
capability mask).
v3: Stylistic tweaks.
v4: Appease Joonas with a snippet of kerneldoc, only to fuel to fire of
the preempt vs preempting debate.
Suggested-by: Michal Winiarski
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Tvrtko Ursulin
Cc: Arkadiusz Hiler
Cc: Mika Kuoppala
Cc: Ben Widawsky
Cc: Zhenyu Wang
Cc: Zhi Wang
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/i915_irq.c | 6 +-
drivers/gpu/drm/i915/i915_pci.c | 2 +
drivers/gpu/drm/i915/intel_lrc.c| 157 +---
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
5 files changed, 143 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index efbe5fc3d044..4d5a22485848 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -368,9 +368,16 @@ static int i915_getparam(struct drm_device *dev, void
*data,
break;
case I915_PARAM_HAS_SCHEDULER:
value = 0;
- if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule)
+ if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
value |= I915_SCHEDULER_CAP_ENABLED;
+
+ if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
+ i915_modparams.enable_execlists &&
+ !i915_modparams.enable_guc_submission)
+ value |= I915_SCHEDULER_CAP_PREEMPTION;
+ }
break;
+
case I915_PARAM_MMAP_VERSION:
/* Remember to bump this if the version changes! */
case I915_PARAM_HAS_GEM:
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e5997e818673..de777139f6a1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1382,10 +1382,8 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir, int test_shift)
bool tasklet = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
- if (port_count(&execlists->port[0])) {
- __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- tasklet = true;
- }
+ __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ tasklet = true;
}
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
[Intel-gfx] [CI 2/9] drm/i915/preempt: Default to disabled mid-command preemption levels
From: Michał Winiarski
Supporting fine-granularity preemption levels may require changes in
userspace batch buffer programming. Therefore, we need to fallback to
safe default values, rather that use hardware defaults. Userspace is
still able to enable fine-granularity, since we're whitelisting the
register controlling it in WaEnablePreemptionGranularityControlByUMD.
v2: Extend w/a to cover Cannonlake
v3: Fix commentary to include both fake w/a names.
Signed-off-by: Michał Winiarski
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_reg.h| 6 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 25 +
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39ad9327e2a0..e7dba5539b11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7003,6 +7003,12 @@ enum {
#define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
+#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
+#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
+#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVELGEN9_PREEMPT_GPGPU_LEVEL(0, 0)
+#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
+#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
+#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 040c85e496fa..5615f033c807 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1071,6 +1071,24 @@ static int gen9_init_workarounds(struct intel_engine_cs
*engine)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+ /*
+* Supporting preemption with fine-granularity requires changes in the
+* batch buffer programming. Since we can't break old userspace, we
+* need to set our default preemption level to safe value. Userspace is
+* still able to use more fine-grained preemption levels, since in
+* WaEnablePreemptionGranularityControlByUMD we're whitelisting the
+* per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
+* not real HW workarounds, but merely a way to start using preemption
+* while maintaining old contract with userspace.
+*/
+
+ /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
+
+ /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
if (ret)
@@ -1272,6 +1290,13 @@ static int cnl_init_workarounds(struct intel_engine_cs
*engine)
/* FtrEnableFastAnisoL1BankingFix: cnl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+ /* WaDisable3DMidCmdPreemption:cnl */
+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
+
+ /* WaDisableGPGPUMidCmdPreemption:cnl */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
--
2.14.2
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[Intel-gfx] [CI 9/9] drm/i915/scheduler: Support user-defined priorities
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via I915_CONTEXT_PARAM_PRIORITY, with more positive
values being higher priority (they will be serviced earlier, after their
dependencies have been resolved). Any prerequisite work for an execbuf
will have its priority raised to match the new request as required.
Normal users can specify any value in the range of -1023 to 0 [default],
i.e. they can reduce the priority of their workloads (and temporarily
boost it back to normal if so desired).
Privileged users can specify any value in the range of -1023 to 1023,
[default is 0], i.e. they can raise their priority above all overs and
so potentially starve the system.
Note that the existing schedulers are not fair, nor load balancing, the
execution is strictly by priority on a first-come, first-served basis,
and the driver may choose to boost some requests above the range
available to users.
This priority was originally based around nice(2), but evolved to allow
clients to adjust their priority within a small range, and allow for a
privileged high priority range.
For example, this can be used to implement EGL_IMG_context_priority
https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt
EGL_CONTEXT_PRIORITY_LEVEL_IMG determines the priority level of
the context to be created. This attribute is a hint, as an
implementation may not support multiple contexts at some
priority levels and system policy may limit access to high
priority contexts to appropriate system privilege level. The
default value for EGL_CONTEXT_PRIORITY_LEVEL_IMG is
EGL_CONTEXT_PRIORITY_MEDIUM_IMG."
so we can map
PRIORITY_HIGH -> 1023 [privileged, will failback to 0]
PRIORITY_MED -> 0 [default]
PRIORITY_LOW -> -1023
They also map onto the priorities used by VkQueue (and a VkQueue is
essentially a timeline, our i915_gem_context under full-ppgtt).
v2: s/CAP_SYS_ADMIN/CAP_SYS_NICE/
v3: Report min/max user priorities as defines in the uapi, and rebase
internal priorities on the exposed values.
Testcase: igt/gem_exec_schedule
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 23 +++
drivers/gpu/drm/i915/i915_gem_request.h | 14 ++
include/uapi/drm/i915_drm.h | 7 +++
4 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4d5a22485848..4f9a3d84e194 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -370,6 +370,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 0;
if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
value |= I915_SCHEDULER_CAP_ENABLED;
+ value |= I915_SCHEDULER_CAP_PRIORITY;
if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
i915_modparams.enable_execlists &&
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2bb8e58706ba..5bf96a258509 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1070,6 +1070,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
case I915_CONTEXT_PARAM_BANNABLE:
args->value = i915_gem_context_is_bannable(ctx);
break;
+ case I915_CONTEXT_PARAM_PRIORITY:
+ args->value = ctx->priority;
+ break;
default:
ret = -EINVAL;
break;
@@ -1125,6 +1128,26 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
else
i915_gem_context_clear_bannable(ctx);
break;
+
+ case I915_CONTEXT_PARAM_PRIORITY:
+ {
+ int priority = args->value;
+
+ if (args->size)
+ ret = -EINVAL;
+ else if (!to_i915(dev)->engine[RCS]->schedule)
+ ret = -ENODEV;
+ else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
+priority < I915_CONTEXT_MIN_USER_PRIORITY)
+ ret = -EINVAL;
+ else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
+!capable(CAP_SYS_NICE))
+ ret = -EPERM;
+ else
+
[Intel-gfx] [CI 1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD
From: Jeff McGee The WA applies to all production Gen9 and requires both enabling and whitelisting of the per-context preemption control register. v2: Extend to Cannonlake. Signed-off-by: Jeff McGee Signed-off-by: Michał Winiarski Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_engine_cs.c | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a28e2a864cf1..040c85e496fa 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1076,8 +1076,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */ - ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ + I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, + _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); + ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret) return ret; @@ -1139,14 +1141,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; - /* -* Actual WA is to disable percontext preemption granularity control -* until D0 which is the default case so this is equivalent to -* !WaDisablePerCtxtPreemptionGranularityControl:skl -*/ - I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, - _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); - /* WaEnableGapsTsvCreditFix:skl */ I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE)); @@ -1279,6 +1273,8 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); /* WaEnablePreemptionGranularityControlByUMD:cnl */ + I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, + _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret) return ret; -- 2.14.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 7/9] drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask
In the next few patches, we wish to enable different features for the
scheduler, some which may subtlety change ABI (e.g. allow requests to be
reordered under different circumstances). So we need to make sure
userspace is cognizant of the changes (if they care), by which we employ
the usual method of a GETPARAM. We already have an
I915_PARAM_HAS_SCHEDULER (which notes the existing ability to reorder
requests to avoid bubbles), and now we wish to extend that to be a
bitmask to describe the different capabilities implemented.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++--
include/uapi/drm/i915_drm.h | 9 -
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5cc24344c266..efbe5fc3d044 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -367,8 +367,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = i915_gem_mmap_gtt_version();
break;
case I915_PARAM_HAS_SCHEDULER:
- value = dev_priv->engine[RCS] &&
- dev_priv->engine[RCS]->schedule;
+ value = 0;
+ if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule)
+ value |= I915_SCHEDULER_CAP_ENABLED;
break;
case I915_PARAM_MMAP_VERSION:
/* Remember to bump this if the version changes! */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fe25a01c81f2..aa4a3b20ef6b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -397,10 +397,17 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
-/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
* priorities and the driver will attempt to execute batches in priority order.
+ * The param returns a capability bitmask, nonzero implies that the scheduler
+ * is enabled, with different features present according to the mask.
*/
#define I915_PARAM_HAS_SCHEDULER41
+#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
+#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
+#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
+
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
--
2.14.2
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[Intel-gfx] [CI 5/9] drm/i915/execlists: Move bdw GPGPU w/a to emit_bb
Move the re-enabling of MI arbitration from a per-bb w/a buffer to the
emission of the batch buffer itself.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0f6c839d65a1..e5b470ce43e8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1159,24 +1159,6 @@ static u32 *gen8_init_indirectctx_bb(struct
intel_engine_cs *engine, u32 *batch)
return batch;
}
-/*
- * This batch is started immediately after indirect_ctx batch. Since we ensure
- * that indirect_ctx ends on a cacheline this batch is aligned automatically.
- *
- * The number of DWORDS written are returned using this field.
- *
- * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add
padding
- * to align it with cacheline as padding after MI_BATCH_BUFFER_END is
redundant.
- */
-static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
-{
- /* WaDisableCtxRestoreArbitration:bdw,chv */
- *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- *batch++ = MI_BATCH_BUFFER_END;
-
- return batch;
-}
-
static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32
*batch)
{
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
@@ -1291,7 +1273,7 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
break;
case 8:
wa_bb_fn[0] = gen8_init_indirectctx_bb;
- wa_bb_fn[1] = gen8_init_perctx_bb;
+ wa_bb_fn[1] = NULL;
break;
default:
MISSING_CASE(INTEL_GEN(engine->i915));
@@ -1535,13 +1517,15 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request *req,
if (IS_ERR(cs))
return PTR_ERR(cs);
+ /* WaDisableCtxRestoreArbitration:bdw,chv */
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
/* FIXME(BDW): Address space and security selectors. */
*cs++ = MI_BATCH_BUFFER_START_GEN8 |
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
(flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
- *cs++ = MI_NOOP;
intel_ring_advance(req, cs);
return 0;
--
2.14.2
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib: Assert that the internal gem_create interface matches the ioctl
== Series Details == Series: lib: Assert that the internal gem_create interface matches the ioctl URL : https://patchwork.freedesktop.org/series/31329/ State : success == Summary == IGT patchset tested on top of latest successful build 7fd0cae99630f954cfe0089b4b7e91576a353582 lib: Fixup __gem_create() to be 64b safe. with latest DRM-Tip kernel build CI_DRM_3169 654360cf73fe drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest No testlist changes. Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-cfl-s) fdo#103026 fdo#103026 https://bugs.freedesktop.org/show_bug.cgi?id=103026 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:454s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:480s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:398s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:592s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:292s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:532s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:553s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:541s fi-cfl-s total:289 pass:257 dwarn:0 dfail:0 fail:0 skip:32 time:566s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:646s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:438s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:600s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:439s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:416s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:474s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:515s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:477s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:502s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:585s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:498s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:595s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:657s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:538s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:515s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:596s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:435s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_292/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for DVFS v2
== Series Details ==
Series: DVFS v2
URL : https://patchwork.freedesktop.org/series/31305/
State : success
== Summary ==
Series 31305v1 DVFS v2
https://patchwork.freedesktop.org/api/1.0/series/31305/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21
time:459s
fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24
time:474s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64
time:391s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46
time:580s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105
time:287s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30
time:525s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29
time:534s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34
time:548s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38
time:542s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32
time:554s
fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27
time:635s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59
time:440s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28
time:602s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26
time:443s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26
time:422s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60
time:478s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28
time:501s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28
time:475s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24
time:497s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19
time:580s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20
time:495s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27
time:593s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65
time:655s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20
time:473s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24
time:539s
fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20
time:515s
fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23
time:469s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38
time:591s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39
time:435s
654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC
integration manifest
7591d8ba19b2 drm/i915: Make DVFS more generic and document them.
a14661ddc36c drm/i915/cnl: When disabling pll put dvfs back to cdclk
requirement.
d1e746f1a012 drm/i915/cnl: Only request voltage frequency switching when needed.
4cdec21e68d4 drm/i915/cnl: Unify dvfs level selection.
a0889ddfbbd0 drm/i915/cnl: Invert dvfs default level.
28a003f8593c drm/i915/cnl: DVFS for PLL disabling
d2afef1e0afb drm/i915/cnl: DVFS for PLL enabling
606856932ecc drm/i915/cnl: Expose DVFS change functions
59e5cd287048 drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
6c807b506a37 drm/i915: Unify and export gen9+ port_clock calculation.
3764f058b99f drm/i915/skl: Extract skl_calc_pll_link following bxt, cnl style.
6b3e7fc3549a drm/i915/cnl: Extract cnl_calc_pll_link following bxt style.
03f2869b4f14 drm/i915: Let's use more enum intel_dpll_id pll_id.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5886/
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Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header
Quoting Michal Wajdeczko (2017-10-03 19:28:02) > On Tue, 03 Oct 2017 19:03:58 +0200, Chris Wilson > wrote: > > > Quoting Michal Wajdeczko (2017-10-03 17:36:05) > >> We want to keep component specific code in separate files. > >> > >> Suggested-by: Joonas Lahtinen > >> Signed-off-by: Michal Wajdeczko > >> Cc: Joonas Lahtinen > >> Cc: Chris Wilson > >> Cc: Sagar Arun Kamble > >> --- > >> drivers/gpu/drm/i915/intel_guc_log.c | 1 + > >> drivers/gpu/drm/i915/intel_guc_log.h | 57 > >> > >> drivers/gpu/drm/i915/intel_uc.h | 26 +--- > >> 3 files changed, 59 insertions(+), 25 deletions(-) > >> create mode 100644 drivers/gpu/drm/i915/intel_guc_log.h > >> > >> diff --git a/drivers/gpu/drm/i915/intel_guc_log.c > >> b/drivers/gpu/drm/i915/intel_guc_log.c > >> index 6571d96..bd9b02e 100644 > >> --- a/drivers/gpu/drm/i915/intel_guc_log.c > >> +++ b/drivers/gpu/drm/i915/intel_guc_log.c > >> @@ -23,6 +23,7 @@ > >> */ > >> #include > >> #include > >> +#include "intel_guc_log.h" > >> #include "i915_drv.h" > > > > Can we keep a newline between <> and "", and aim for alphabetical order. > > I'll add newline in next spin, but I'm not sure about alphabetical order. > > Note that Joonas wants all foo.c files to start with "foo.h" (after <>) > and then followed by other headers to make dependencies more explicit. I'm not fussed, though tbh I am more likely to forget which file I'm in and so which special case to apply. 2 blocks of alphabetical includes is simple enough for me to not muck up :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for lib: Fixup __gem_create() to be 64b safe. (rev2)
== Series Details == Series: lib: Fixup __gem_create() to be 64b safe. (rev2) URL : https://patchwork.freedesktop.org/series/31327/ State : success == Summary == Test gem_pwrite: Subgroup huge-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-gtt-fbr: fail -> PASS (shard-hsw) Subgroup huge-cpu-random: fail -> PASS (shard-hsw) Subgroup big-cpu-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-random: fail -> PASS (shard-hsw) Subgroup big-cpu-backwards: fail -> PASS (shard-hsw) Subgroup big-gtt-random: fail -> PASS (shard-hsw) Subgroup huge-cpu-backwards: fail -> PASS (shard-hsw) Subgroup big-gtt-forwards: fail -> PASS (shard-hsw) Subgroup big-cpu-fbr: fail -> PASS (shard-hsw) Subgroup big-gtt-backwards: fail -> PASS (shard-hsw) Subgroup big-gtt-fbr: fail -> PASS (shard-hsw) Subgroup huge-gtt-forwards: fail -> PASS (shard-hsw) Subgroup huge-gtt-backwards: fail -> PASS (shard-hsw) Subgroup huge-cpu-fbr: fail -> PASS (shard-hsw) Subgroup huge-cpu-forwards: fail -> PASS (shard-hsw) Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test gem_eio: Subgroup execbuf: dmesg-warn -> PASS (shard-hsw) fdo#102886 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886 shard-hswtotal:2429 pass:1331 dwarn:6 dfail:0 fail:9 skip:1083 time:10042s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_291/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Update the DMC version on CNL
== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : success == Summary == Series 31345v1 drm/i915/cnl: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31345/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-n2820) fdo#101705 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:460s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:394s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:576s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:288s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:520s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:545s fi-byt-n2820 total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:529s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:560s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:617s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:442s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:595s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:444s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:429s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:463s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:515s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:475s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:505s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:497s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:662s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:469s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:539s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:515s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:583s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:430s 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest b2a277b2dcd2 drm/i915/cnl: Update the DMC version on CNL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5885/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Update the DMC version on CNL
== Series Details == Series: drm/i915/cnl: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31345/ State : success == Summary == Series 31345v1 drm/i915/cnl: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31345/revisions/1/mbox/ fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:455s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:391s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:565s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:287s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:530s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:546s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:531s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:555s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:617s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:435s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:601s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:439s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:416s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:467s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:510s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:505s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:487s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:535s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:586s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:582s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:432s fi-pnv-d510 failed to connect after reboot 654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest 4d11a9a8bcc3 drm/i915/cnl: Update the DMC version on CNL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5884/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Guc code reorg
== Series Details == Series: drm/i915: Guc code reorg URL : https://patchwork.freedesktop.org/series/31340/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1315 dwarn:7 dfail:0 fail:24 skip:1083 time:10047s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5882/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header
On Tue, 03 Oct 2017 19:03:58 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2017-10-03 17:36:05) We want to keep component specific code in separate files. Suggested-by: Joonas Lahtinen Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_guc_log.c | 1 + drivers/gpu/drm/i915/intel_guc_log.h | 57 drivers/gpu/drm/i915/intel_uc.h | 26 +--- 3 files changed, 59 insertions(+), 25 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_log.h diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c index 6571d96..bd9b02e 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.c +++ b/drivers/gpu/drm/i915/intel_guc_log.c @@ -23,6 +23,7 @@ */ #include #include +#include "intel_guc_log.h" #include "i915_drv.h" Can we keep a newline between <> and "", and aim for alphabetical order. I'll add newline in next spin, but I'm not sure about alphabetical order. Note that Joonas wants all foo.c files to start with "foo.h" (after <>) and then followed by other headers to make dependencies more explicit. Michal ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation
On Tue, Oct 03, 2017 at 05:47:50PM +, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote:
> > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > before starting the DMC firmware's DC state handler.
>
> no mention on CNL there?
>
> Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> Our code probably needs deeper changes...
nevermind. I was wrong about this.
The only difference I see on CNL compared with SKL now
is the bit 31 of DC_STATE_EN...
A bit that we should set during modeset and clear after. But there is
no mention about that bit on the main sequences page and also we
leave dc states disabled during modeset anyways besides that
clock gating wa... So I believe we are safe.
Imre, thoughts?
>
> >
> > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > Cc: Anusha Srivatsa
> > Cc: Rodrigo Vivi
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_csr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > b/drivers/gpu/drm/i915/intel_csr.c
> > index cdfb624eb82d..ea5d5c9645a4 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct
> > drm_i915_private *dev_priv)
> >
> > mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > mask |= DC_STATE_DEBUG_MASK_CORES;
>
> I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5
> or DC6"
> So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
>
>
> >
> > /* The below bit doesn't need to be cleared ever afterwards */
> > --
> > 2.13.2
> >
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Update the DMC version on CNL
On Tue, Oct 03, 2017 at 05:59:48PM +, Anusha Srivatsa wrote: > The latest version of DMC on CNL is 1.06. > Update the version so as to load the > latest firmware. > > Release Notes: > Version: 1.06 > 1. DDI and AUX IO related fix. > > v2: Improve the prefixes in commit message. > Add Release Notes directly. (Rodrigo) > > Cc: Rodrigo Vivi > Signed-off-by: Anusha Srivatsa Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_csr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_csr.c > b/drivers/gpu/drm/i915/intel_csr.c > index cdfb624..f417101 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -37,8 +37,8 @@ > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" > #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) > > -#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin" > -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) > +#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" > +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) > > #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" > MODULE_FIRMWARE(I915_CSR_KBL); > -- > 2.7.4 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL
HI, > -Original Message- > From: Vivi, Rodrigo > Sent: tiistai 3. lokakuuta 2017 21.07 > To: intel-gfx@lists.freedesktop.org > Cc: Srivatsa, Anusha ; Saarinen, Jani > > Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the > DMC version on CNL > > On Tue, Oct 03, 2017 at 06:01:30PM +, Patchwork wrote: > > == Series Details == > > > > Series: i915/CNL/DMC: Update the DMC version on CNL > > URL : https://patchwork.freedesktop.org/series/31344/ > > State : failure > > > > == Summary == > > > > Series 31344v1 i915/CNL/DMC: Update the DMC version on CNL > > https://patchwork.freedesktop.org/api/1.0/series/31344/revisions/1/mbo > > x/ > > > > Test gem_exec_suspend: > > Subgroup basic-s3: > > dmesg-warn -> PASS (fi-cnl-y) fdo#103070 > > Test pm_rpm: > > Subgroup basic-pci-d3-state: > > pass -> FAIL (fi-cnl-y) > > Subgroup basic-rte: > > pass -> FAIL (fi-cnl-y) > > This is caused by the lack of dmc 1.06 on CI. > > We need to adjust our process to have the firmware available on CI before > sending the patches. Otherwise the full IGT tests will never be tested on the > firmware. Yep, now added and re-run series to see. > > > > > fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070 > > > > fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 > time:450s > > fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:478s > > fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 > time:393s > > fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 > time:572s > > fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 > time:293s > > fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 > > time:532s > > fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 > time:538s > > fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 > time:557s > > fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 > time:539s > > fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 > > time:555s > > fi-cnl-y total:289 pass:260 dwarn:0 dfail:0 fail:2 skip:27 > > time:659s > > fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 > time:440s > > fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > > time:595s > > fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:442s > > fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:429s > > fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 > > time:462s > > fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:512s > > fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:476s > > fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 > time:511s > > fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 > time:586s > > fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 > time:484s > > fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 > > time:590s > > fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 > time:662s > > fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:476s > > fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:544s > > fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:588s > > fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 > time:475s > > fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 > time:590s > > fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 > time:437s > > > > e7187e87bb3b5ca43194f86d096b9cf974cc54d7 drm-tip: > > 2017y-10m-03d-16h-09m-59s UTC integration manifest 18316009984d > > i915/CNL/DMC: Update the DMC version on CNL > > > > == Logs == > > > > For more details see: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5883/ > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained
On Tue, 03 Oct 2017 19:02:42 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2017-10-03 17:35:59)
We're trying to resolve inter-header dependencies.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uncore.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 03786f9..66eae2c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -25,6 +25,12 @@
#ifndef __INTEL_UNCORE_H__
#define __INTEL_UNCORE_H__
+#include
+#include
+#include
+
+#include "i915_reg.h"
Hmm, what do we pull in directly? Something like i915_mmio_offset()?
In my head I have i915_reg.h == unwieldy list of register defines and
nothing more.
We need this:
typedef struct {
uint32_t reg;
} i915_reg_t;
Reviewed-by: Chris Wilson
Looks sensible but if it's only one small thing for i915_reg.h can you
add a comment and we can try and split it up.
-Chris
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation
On Tue, Oct 03, 2017 at 06:03:20PM +, Imre Deak wrote:
> On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote:
> > > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > > before starting the DMC firmware's DC state handler.
> >
> > no mention on CNL there?
>
> No, this is only needed for BXT and GLK.
>
> > Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> > Our code probably needs deeper changes...
> >
> > >
> > > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > > Cc: Anusha Srivatsa
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/intel_csr.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > > b/drivers/gpu/drm/i915/intel_csr.c
> > > index cdfb624eb82d..ea5d5c9645a4 100644
> > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct
> > > drm_i915_private *dev_priv)
> > >
> > > mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > mask |= DC_STATE_DEBUG_MASK_CORES;
> >
> > I saw in spec for SKL+: "This field must be set to Mask prior to enabling
> > DC5 or DC6"
> > So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
>
> No, only needed for BXT, GLK, see under BSpec "Sequences for Display C5 and
> C6".
Oh yes! It seems we can trust this part better. Really clear and complete.
Reviewed-by: Rodrigo Vivi
>
> > >
> > > /* The below bit doesn't need to be cleared ever afterwards */
> > > --
> > > 2.13.2
> > >
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL
On Tue, Oct 03, 2017 at 06:01:30PM +, Patchwork wrote: > == Series Details == > > Series: i915/CNL/DMC: Update the DMC version on CNL > URL : https://patchwork.freedesktop.org/series/31344/ > State : failure > > == Summary == > > Series 31344v1 i915/CNL/DMC: Update the DMC version on CNL > https://patchwork.freedesktop.org/api/1.0/series/31344/revisions/1/mbox/ > > Test gem_exec_suspend: > Subgroup basic-s3: > dmesg-warn -> PASS (fi-cnl-y) fdo#103070 > Test pm_rpm: > Subgroup basic-pci-d3-state: > pass -> FAIL (fi-cnl-y) > Subgroup basic-rte: > pass -> FAIL (fi-cnl-y) This is caused by the lack of dmc 1.06 on CI. We need to adjust our process to have the firmware available on CI before sending the patches. Otherwise the full IGT tests will never be tested on the firmware. > > fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070 > > fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 > time:450s > fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:478s > fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 > time:393s > fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 > time:572s > fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 > time:293s > fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 > time:532s > fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 > time:538s > fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 > time:557s > fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 > time:539s > fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 > time:555s > fi-cnl-y total:289 pass:260 dwarn:0 dfail:0 fail:2 skip:27 > time:659s > fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 > time:440s > fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:595s > fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:442s > fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 > time:429s > fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 > time:462s > fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:512s > fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 > time:476s > fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 > time:511s > fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 > time:586s > fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 > time:484s > fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 > time:590s > fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 > time:662s > fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:476s > fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 > time:544s > fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 > time:588s > fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 > time:475s > fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 > time:590s > fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 > time:437s > > e7187e87bb3b5ca43194f86d096b9cf974cc54d7 drm-tip: 2017y-10m-03d-16h-09m-59s > UTC integration manifest > 18316009984d i915/CNL/DMC: Update the DMC version on CNL > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5883/ > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation
On Tue, Oct 03, 2017 at 10:47:50AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote:
> > According to BSpec GLK like BXT needs to ignore the idle state of cores
> > before starting the DMC firmware's DC state handler.
>
> no mention on CNL there?
No, this is only needed for BXT and GLK.
> Btw I just saw that CNL DMC seems much more like BXT than like SKL.
> Our code probably needs deeper changes...
>
> >
> > Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> > Cc: Anusha Srivatsa
> > Cc: Rodrigo Vivi
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_csr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > b/drivers/gpu/drm/i915/intel_csr.c
> > index cdfb624eb82d..ea5d5c9645a4 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct
> > drm_i915_private *dev_priv)
> >
> > mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > mask |= DC_STATE_DEBUG_MASK_CORES;
>
> I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5
> or DC6"
> So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
No, only needed for BXT, GLK, see under BSpec "Sequences for Display C5 and C6".
> >
> > /* The below bit doesn't need to be cleared ever afterwards */
> > --
> > 2.13.2
> >
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
On Tue, Oct 03, 2017 at 05:57:11PM +, Imre Deak wrote:
> On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote:
> > > The DMC firmware program memory is lost after S3/S4 system suspend, so
> > > we need to reprogram it during resume.
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> > > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> > > Cc: Anusha Srivatsa
> > > Cc: Animesh Manna
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 7933d1bc6a1c..3791c3f5f56d 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct
> > > drm_i915_private *dev_priv, bool resume
> > >
> > > /* 6. Enable DBUF */
> > > gen9_dbuf_enable(dev_priv);
> > > +
> > > + if (resume && dev_priv->csr.dmc_payload)
> > > + intel_csr_load_program(dev_priv);
> >
> > If this is needed for all platforms, couldn't we move that to
> > intel_power_domains_init_hw()?
> > so we don't forget future platforms?
>
> For GEN9_LP we also need to run the init sequence separately during
> runtime resume, so these functions seem to be still the proper place to
> call intel_csr_load_program().
ohh true...
Reviewed-by: Rodrigo Vivi
>
> >
> > > }
> > >
> > > static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > > --
> > > 2.13.2
> > >
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[Intel-gfx] [PATCH] drm/i915/cnl: Update the DMC version on CNL
The latest version of DMC on CNL is 1.06. Update the version so as to load the latest firmware. Release Notes: Version: 1.06 1. DDI and AUX IO related fix. v2: Improve the prefixes in commit message. Add Release Notes directly. (Rodrigo) Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index cdfb624..f417101 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,8 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/CNL/DMC: Update the DMC version on CNL
== Series Details == Series: i915/CNL/DMC: Update the DMC version on CNL URL : https://patchwork.freedesktop.org/series/31344/ State : failure == Summary == Series 31344v1 i915/CNL/DMC: Update the DMC version on CNL https://patchwork.freedesktop.org/api/1.0/series/31344/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-cnl-y) fdo#103070 Test pm_rpm: Subgroup basic-pci-d3-state: pass -> FAIL (fi-cnl-y) Subgroup basic-rte: pass -> FAIL (fi-cnl-y) fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:478s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:393s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:572s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:293s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:532s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:538s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:557s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:539s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:555s fi-cnl-y total:289 pass:260 dwarn:0 dfail:0 fail:2 skip:27 time:659s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:440s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:595s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:442s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:429s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:462s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:512s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:476s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:511s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:484s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:662s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:544s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:588s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:590s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:437s e7187e87bb3b5ca43194f86d096b9cf974cc54d7 drm-tip: 2017y-10m-03d-16h-09m-59s UTC integration manifest 18316009984d i915/CNL/DMC: Update the DMC version on CNL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5883/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
On Tue, Oct 03, 2017 at 10:40:18AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote:
> > The DMC firmware program memory is lost after S3/S4 system suspend, so
> > we need to reprogram it during resume.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> > Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> > Cc: Anusha Srivatsa
> > Cc: Animesh Manna
> > Cc: Rodrigo Vivi
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 7933d1bc6a1c..3791c3f5f56d 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct
> > drm_i915_private *dev_priv, bool resume
> >
> > /* 6. Enable DBUF */
> > gen9_dbuf_enable(dev_priv);
> > +
> > + if (resume && dev_priv->csr.dmc_payload)
> > + intel_csr_load_program(dev_priv);
>
> If this is needed for all platforms, couldn't we move that to
> intel_power_domains_init_hw()?
> so we don't forget future platforms?
For GEN9_LP we also need to run the init sequence separately during
runtime resume, so these functions seem to be still the proper place to
call intel_csr_load_program().
>
> > }
> >
> > static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > --
> > 2.13.2
> >
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Organize GLK_COLORS.
patches merged to dinq. Thanks for ideas, reviews and comments.
On Tue, Oct 03, 2017 at 06:36:52AM +, Rodrigo Vivi wrote:
> Let's organize this in a way that it gets more obvious
> when looking to the platform colors and in a easier
> way to get inherited.
>
> v2: Add comma at the end (Jani), when possible.
>
> Cc: Jani Nikula
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_pci.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bfec3a7841d0..d3a6fe5e3c10 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -54,6 +54,8 @@
> .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
> #define CHV_COLORS \
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
> +#define GLK_COLORS \
> + .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>
> /* Keep in gen based order, and chronological order within a gen */
> #define GEN2_FEATURES \
> @@ -496,7 +498,7 @@ static const struct intel_device_info
> intel_geminilake_info __initconst = {
> GEN9_LP_FEATURES,
> .platform = INTEL_GEMINILAKE,
> .ddb_size = 1024,
> - .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
> + GLK_COLORS,
> };
>
> #define KBL_PLATFORM \
> @@ -544,7 +546,7 @@ static const struct intel_device_info
> intel_coffeelake_gt3_info __initconst = {
> #define GEN10_FEATURES \
> GEN9_FEATURES, \
> .ddb_size = 1024, \
> - .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
> + GLK_COLORS
>
> static const struct intel_device_info intel_cannonlake_gt2_info __initconst
> = {
> GEN10_FEATURES,
> --
> 2.13.5
>
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Fix DMC/DC state idleness calculation
On Tue, Oct 03, 2017 at 09:51:59AM +, Imre Deak wrote:
> According to BSpec GLK like BXT needs to ignore the idle state of cores
> before starting the DMC firmware's DC state handler.
no mention on CNL there?
Btw I just saw that CNL DMC seems much more like BXT than like SKL.
Our code probably needs deeper changes...
>
> Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
> Cc: Anusha Srivatsa
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index cdfb624eb82d..ea5d5c9645a4 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct
> drm_i915_private *dev_priv)
>
> mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> mask |= DC_STATE_DEBUG_MASK_CORES;
I saw in spec for SKL+: "This field must be set to Mask prior to enabling DC5
or DC6"
So I believe this should be INTEL_GEN(dev_priv) >= 9... :/
>
> /* The below bit doesn't need to be cleared ever afterwards */
> --
> 2.13.2
>
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Re: [Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL
>-Original Message- >From: Vivi, Rodrigo >Sent: Tuesday, October 3, 2017 10:37 AM >To: Srivatsa, Anusha >Cc: intel-gfx@lists.freedesktop.org >Subject: Re: [PATCH] i915/CNL/DMC: Update the DMC version on CNL > > >Please use prefix like: "drm/i915/cnl:". >dmr is needed and dmc is not necessary. Sure. >On Tue, Oct 03, 2017 at 05:32:12PM +, Anusha Srivatsa wrote: >> The latest version of CNL DMC is 1.06. >> Update the version so as to load the >> latest firmware. >> >> According to Release Notes, this version fixes some DDI and AUX >> related issues. > >Could we paste the release notes directly? Sure. Release Notes is "DDI and AUX IO related fix". Which is pretty much the same as the commit message. :-p >Thanks >Rodrigo. > >> >> Cc: Rodrigo Vivi >> Signed-off-by: Anusha Srivatsa >> --- >> drivers/gpu/drm/i915/intel_csr.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_csr.c >> b/drivers/gpu/drm/i915/intel_csr.c >> index 965988f..bf7bdbe 100644 >> --- a/drivers/gpu/drm/i915/intel_csr.c >> +++ b/drivers/gpu/drm/i915/intel_csr.c >> @@ -37,8 +37,8 @@ >> #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" >> #define GLK_CSR_VERSION_REQUIREDCSR_VERSION(1, 4) >> >> -#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin" >> -#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 4) >> +#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" >> +#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 6) >> >> #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" >> MODULE_FIRMWARE(I915_CSR_KBL); >> -- >> 2.7.4 >> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
On Tue, Oct 03, 2017 at 09:51:58AM +, Imre Deak wrote:
> The DMC firmware program memory is lost after S3/S4 system suspend, so
> we need to reprogram it during resume.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070
> Fixes: cebfcead63de ("drm/i915/DMC/CNL: Load DMC on CNL")
> Cc: Anusha Srivatsa
> Cc: Animesh Manna
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7933d1bc6a1c..3791c3f5f56d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2809,6 +2809,9 @@ static void cnl_display_core_init(struct
> drm_i915_private *dev_priv, bool resume
>
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
> +
> + if (resume && dev_priv->csr.dmc_payload)
> + intel_csr_load_program(dev_priv);
If this is needed for all platforms, couldn't we move that to
intel_power_domains_init_hw()?
so we don't forget future platforms?
> }
>
> static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> --
> 2.13.2
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib: Fixup __gem_create() to be 64b safe. (rev2)
== Series Details == Series: lib: Fixup __gem_create() to be 64b safe. (rev2) URL : https://patchwork.freedesktop.org/series/31327/ State : success == Summary == IGT patchset tested on top of latest successful build 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from __gem_create() with latest DRM-Tip kernel build CI_DRM_3168 e7187e87bb3b drm-tip: 2017y-10m-03d-16h-09m-59s UTC integration manifest No testlist changes. Test drv_module_reload: Subgroup basic-reload-inject: pass -> INCOMPLETE (fi-cfl-s) k.org#196765 k.org#196765 https://bugzilla.kernel.org/show_bug.cgi?id=196765 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:468s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:477s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:398s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:584s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:290s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:536s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:532s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:553s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:536s fi-cfl-s total:288 pass:255 dwarn:1 dfail:0 fail:0 skip:31 fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:646s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:433s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:596s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:439s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:419s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:470s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:502s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:479s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:504s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:495s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:662s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:472s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:542s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:523s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:477s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:587s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:439s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_291/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL
Please use prefix like: "drm/i915/cnl:". dmr is needed and dmc is not necessary. On Tue, Oct 03, 2017 at 05:32:12PM +, Anusha Srivatsa wrote: > The latest version of CNL DMC is 1.06. > Update the version so as to load the > latest firmware. > > According to Release Notes, this version > fixes some DDI and AUX related issues. Could we paste the release notes directly? Thanks Rodrigo. > > Cc: Rodrigo Vivi > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/intel_csr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_csr.c > b/drivers/gpu/drm/i915/intel_csr.c > index 965988f..bf7bdbe 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -37,8 +37,8 @@ > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" > #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) > > -#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin" > -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) > +#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" > +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) > > #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" > MODULE_FIRMWARE(I915_CSR_KBL); > -- > 2.7.4 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] i915/CNL/DMC: Update the DMC version on CNL
The latest version of CNL DMC is 1.06. Update the version so as to load the latest firmware. According to Release Notes, this version fixes some DDI and AUX related issues. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 965988f..bf7bdbe 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,8 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Guc code reorg
== Series Details == Series: drm/i915: Guc code reorg URL : https://patchwork.freedesktop.org/series/31340/ State : success == Summary == Series 31340v1 drm/i915: Guc code reorg https://patchwork.freedesktop.org/api/1.0/series/31340/revisions/1/mbox/ fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:457s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:392s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:569s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:286s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:526s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:534s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:540s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:536s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:618s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:439s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:591s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:439s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:417s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:467s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:518s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:478s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:503s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:492s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:657s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:534s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:523s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:584s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:432s e7187e87bb3b5ca43194f86d096b9cf974cc54d7 drm-tip: 2017y-10m-03d-16h-09m-59s UTC integration manifest 075e3af7041e drm/i915/guc: Move GuC core definitions into dedicated files 6376585ec9d0 drm/i915/guc: Move GuC submission declarations into dedicated header 17911cbed040 drm/i915/guc: Move GuC log declarations into dedicated header 4d9fdaddcdeb drm/i915/guc: Move Guc early init into own function 410d58f48040 drm/i915/huc: Move HuC declarations into dedicated header 81ea7a4979de drm/i915/uc: Move uC fw helper code into dedicated files efcc84c34937 drm/i915/uc: Create intel_uc_init_mmio 897166bdaffc drm/i915/uc: Drop unnecessary forward declaration 927791b05913 drm/i915: Make intel_uncore.h header self-contained == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5882/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header
Quoting Michal Wajdeczko (2017-10-03 17:36:05) > We want to keep component specific code in separate files. > > Suggested-by: Joonas Lahtinen > Signed-off-by: Michal Wajdeczko > Cc: Joonas Lahtinen > Cc: Chris Wilson > Cc: Sagar Arun Kamble > --- > drivers/gpu/drm/i915/intel_guc_log.c | 1 + > drivers/gpu/drm/i915/intel_guc_log.h | 57 > > drivers/gpu/drm/i915/intel_uc.h | 26 +--- > 3 files changed, 59 insertions(+), 25 deletions(-) > create mode 100644 drivers/gpu/drm/i915/intel_guc_log.h > > diff --git a/drivers/gpu/drm/i915/intel_guc_log.c > b/drivers/gpu/drm/i915/intel_guc_log.c > index 6571d96..bd9b02e 100644 > --- a/drivers/gpu/drm/i915/intel_guc_log.c > +++ b/drivers/gpu/drm/i915/intel_guc_log.c > @@ -23,6 +23,7 @@ > */ > #include > #include > +#include "intel_guc_log.h" > #include "i915_drv.h" Can we keep a newline between <> and "", and aim for alphabetical order. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained
Quoting Michal Wajdeczko (2017-10-03 17:35:59) > We're trying to resolve inter-header dependencies. > > Signed-off-by: Michal Wajdeczko > Cc: Joonas Lahtinen > Cc: Chris Wilson > --- > drivers/gpu/drm/i915/intel_uncore.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.h > b/drivers/gpu/drm/i915/intel_uncore.h > index 03786f9..66eae2c 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.h > +++ b/drivers/gpu/drm/i915/intel_uncore.h > @@ -25,6 +25,12 @@ > #ifndef __INTEL_UNCORE_H__ > #define __INTEL_UNCORE_H__ > > +#include > +#include > +#include > + > +#include "i915_reg.h" Hmm, what do we pull in directly? Something like i915_mmio_offset()? In my head I have i915_reg.h == unwieldy list of register defines and nothing more. Reviewed-by: Chris Wilson Looks sensible but if it's only one small thing for i915_reg.h can you add a comment and we can try and split it up. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 4/9] drm/i915/uc: Move uC fw helper code into dedicated files
This is a prerequisite to unblock next steps.
v2: correct include order (Joonas)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_uc.c| 159 +---
drivers/gpu/drm/i915/intel_uc.h| 67 +-
drivers/gpu/drm/i915/intel_uc_fw.c | 179 +
drivers/gpu/drm/i915/intel_uc_fw.h | 98
5 files changed, 283 insertions(+), 221 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_uc_fw.c
create mode 100644 drivers/gpu/drm/i915/intel_uc_fw.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5182e3d..4850f26 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -59,6 +59,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
+ intel_uc_fw.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8151a9d..0b6c931 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -26,19 +26,6 @@
#include "intel_uc.h"
#include
-/* Cleans up uC firmware by releasing the firmware GEM obj.
- */
-static void __intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
-{
- struct drm_i915_gem_object *obj;
-
- obj = fetch_and_zero(&uc_fw->obj);
- if (obj)
- i915_gem_object_put(obj);
-
- uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
-}
-
/* Reset GuC providing us with fresh state for both GuC and HuC.
*/
static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
@@ -112,154 +99,16 @@ void intel_uc_init_early(struct drm_i915_private
*dev_priv)
guc->notify = gen8_guc_raise_irq;
}
-static void fetch_uc_fw(struct drm_i915_private *dev_priv,
- struct intel_uc_fw *uc_fw)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
- struct drm_i915_gem_object *obj;
- const struct firmware *fw = NULL;
- struct uc_css_header *css;
- size_t size;
- int err;
-
- if (!uc_fw->path)
- return;
-
- uc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
-
- DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
-intel_uc_fw_status_repr(uc_fw->fetch_status));
-
- err = request_firmware(&fw, uc_fw->path, &pdev->dev);
- if (err)
- goto fail;
- if (!fw)
- goto fail;
-
- DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
-uc_fw->path, fw);
-
- /* Check the size of the blob before examining buffer contents */
- if (fw->size < sizeof(struct uc_css_header)) {
- DRM_NOTE("Firmware header is missing\n");
- goto fail;
- }
-
- css = (struct uc_css_header *)fw->data;
-
- /* Firmware bits always start from header */
- uc_fw->header_offset = 0;
- uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
- css->key_size_dw - css->exponent_size_dw) *
sizeof(u32);
-
- if (uc_fw->header_size != sizeof(struct uc_css_header)) {
- DRM_NOTE("CSS header definition mismatch\n");
- goto fail;
- }
-
- /* then, uCode */
- uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
- uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
-
- /* now RSA */
- if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
- DRM_NOTE("RSA key size is bad\n");
- goto fail;
- }
- uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
- uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
-
- /* At least, it should have header, uCode and RSA. Size of all three. */
- size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
- if (fw->size < size) {
- DRM_NOTE("Missing firmware components\n");
- goto fail;
- }
-
- /*
-* The GuC firmware image has the version number embedded at a
-* well-known offset within the firmware blob; note that major / minor
-* version are TWO bytes each (i.e. u16), although all pointers and
-* offsets are defined in terms of bytes (u8).
-*/
- switch (uc_fw->type) {
- case INTEL_UC_FW_TYPE_GUC:
- /* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = uc_fw->header_size + uc_fw->ucode_size;
-
- /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
- if (size > intel_guc_wopcm_size(dev_priv)) {
- DRM_ERROR("Firmware is too large to fit in WOPCM\n");
Re: [Intel-gfx] [PATCH i-g-t v4 6/6] tests/kms_ccs: Test case for wrong aux buffer stride size
On 17-09-27 15:34:19, Gabriel Krisman Bertazi wrote:
Two scenarios tested:
- unaligned stride
- Stride too small
Signed-off-by: Gabriel Krisman Bertazi
Jason, could you provide your opinion on this? I've always felt the kernel
interface shouldn't be validating stride at all.
---
tests/kms_ccs.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 2d7105eb1323..cb6e69c69ae5 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -35,14 +35,18 @@ enum test_flags {
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER = 1 << 5,
TEST_BAD_CCS_HANDLE = 1 << 6,
+ TEST_BAD_AUX_STRIDE = 1 << 7,
};
#define TEST_FAIL_ON_ADDFB2 \
- (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE)
+ (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE | \
+TEST_BAD_AUX_STRIDE)
enum test_fb_flags {
FB_COMPRESSED = 1 << 0,
FB_HAS_PLANE= 1 << 1,
+ FB_MISALIGN_AUX_STRIDE = 1 << 2,
+ FB_SMALL_AUX_STRIDE = 1 << 3,
};
typedef struct {
@@ -324,6 +328,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
int ccs_pitches = ALIGN(ccs_width * 1, 128);
int ccs_offsets = size[0];
+ if (fb_flags & FB_MISALIGN_AUX_STRIDE)
+ ccs_pitches -= 64;
+ else if (fb_flags & FB_SMALL_AUX_STRIDE) {
+ igt_skip_on_f(width <= 1024,
+ "FB already has the smallest possible
stride\n");
+ ccs_pitches = ALIGN(ccs_width/2, 128);
+ }
+
size[1] = ccs_pitches * ALIGN(ccs_height, 32);
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
@@ -470,6 +482,11 @@ static void test_output(data_t *data)
try_config(data, fb_flags | FB_COMPRESSED);
}
+ if (data->flags & TEST_BAD_AUX_STRIDE) {
+ try_config(data, fb_flags | FB_COMPRESSED |
FB_MISALIGN_AUX_STRIDE);
+ try_config(data, fb_flags | FB_COMPRESSED |
FB_SMALL_AUX_STRIDE);
+ }
+
primary = igt_output_get_plane_type(data->output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
igt_plane_set_rotation(primary, IGT_ROTATION_0);
@@ -543,6 +560,10 @@ igt_main
data.flags = TEST_BAD_CCS_HANDLE;
igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
test_output(&data);
+
+ data.flags = TEST_BAD_AUX_STRIDE;
+ igt_subtest_f("pipe-%s-bad-aux-stride", pipe_name)
+ test_output(&data);
}
igt_fixture
--
2.11.0
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Re: [Intel-gfx] [PATCH i-g-t v4 5/6] tests/kms_ccs: Test case where CCS is on a different BO
On 17-09-27 15:34:18, Gabriel Krisman Bertazi wrote:
Signed-off-by: Gabriel Krisman Bertazi
Did someone recommend this test? While we have some hardware limitations on
current generations that make it difficult to use multiple BOs, it's certainly
not impossible, and future HW might make this limitation go away entirely.
I'd be fine if you wanted to use an invalid handle instead of a valid, but
different handle.
---
tests/kms_ccs.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 35dfcca6be14..2d7105eb1323 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -34,10 +34,11 @@ enum test_flags {
TEST_BAD_PIXEL_FORMAT = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER = 1 << 5,
+ TEST_BAD_CCS_HANDLE = 1 << 6,
};
#define TEST_FAIL_ON_ADDFB2 \
- (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+ (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE)
enum test_fb_flags {
FB_COMPRESSED = 1 << 0,
@@ -275,6 +276,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
unsigned int size[2];
uint64_t modifier;
int ret;
+ uint32_t ccs_handle;
/* Use either compressed or Y-tiled to test. However, given the lack of
* available bandwidth, we use linear for the primary plane when
@@ -325,10 +327,15 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
size[1] = ccs_pitches * ALIGN(ccs_height, 32);
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
+ if (data->flags & TEST_BAD_CCS_HANDLE) {
+ /* Put the CCS buffer on a different BO. */
+ ccs_handle = gem_create(data->drm_fd, size[0] +
size[1]);
+ } else
+ ccs_handle = f.handles[0];
if (!(data->flags & TEST_NO_AUX_BUFFER)) {
f.modifier[1] = modifier;
- f.handles[1] = f.handles[0];
+ f.handles[1] = ccs_handle;
f.pitches[1] = ccs_pitches;
f.offsets[1] = ccs_offsets;
@@ -458,7 +465,8 @@ static void test_output(data_t *data)
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
data->flags & TEST_BAD_ROTATION_90 ||
- data->flags & TEST_NO_AUX_BUFFER) {
+ data->flags & TEST_NO_AUX_BUFFER ||
+ data->flags & TEST_BAD_CCS_HANDLE) {
try_config(data, fb_flags | FB_COMPRESSED);
}
@@ -532,6 +540,9 @@ igt_main
igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
test_output(&data);
+ data.flags = TEST_BAD_CCS_HANDLE;
+ igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
+ test_output(&data);
}
igt_fixture
--
2.11.0
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[Intel-gfx] [PATCH v3 2/9] drm/i915/uc: Drop unnecessary forward declaration
We don't need it here. Signed-off-by: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Joonas Lahtinen Reviewed-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_uc.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 6966349..38ec880 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -30,8 +30,6 @@ #include "intel_guc_ct.h" #include "i915_vma.h" -struct drm_i915_gem_request; - /* * This structure primarily describes the GEM object shared with the GuC. * The specs sometimes refer to this object as a "GuC context", but we use -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/21] drm/i915: introduce page_size members
Quoting Chris Wilson (2017-09-29 22:31:27)
> Quoting Matthew Auld (2017-09-29 17:10:17)
> > diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
> > b/drivers/gpu/drm/i915/i915_gem_userptr.c
> > index 70ad7489827d..ad5abca1f794 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> > @@ -405,6 +405,9 @@ __i915_gem_userptr_alloc_pages(struct
> > drm_i915_gem_object *obj,
> > {
> > unsigned int max_segment = i915_sg_segment_size();
> > struct sg_table *st;
> > + struct scatterlist *sg;
> > + unsigned int sg_mask;
> > + int n;
> > int ret;
> >
> > st = kmalloc(sizeof(*st), GFP_KERNEL);
> > @@ -434,7 +437,11 @@ __i915_gem_userptr_alloc_pages(struct
> > drm_i915_gem_object *obj,
> > return ERR_PTR(ret);
> > }
> >
> > - __i915_gem_object_set_pages(obj, st);
> > + sg_mask = 0;
> > + for_each_sg(st->sgl, sg, num_pages, n)
> > + sg_mask |= sg->length;
>
> No workie as num_pages != nents.
If we do something like
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ea7e1fbd0fd..c92d89ec9d5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2896,6 +2896,21 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
(((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
(__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
+static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
+{
+ unsigned int page_sizes;
+
+ page_sizes = 0;
+ while (sg) {
+ GEM_BUG_ON(sg->offset);
+ GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
+ page_sizes |= sg->length;
+ sg = __sg_next(sg);
+ }
+
+ return page_sizes;
+}
+
static inline unsigned int i915_sg_segment_size(void)
{
unsigned int size = swiotlb_max_segment();
Then we can just write sg_mask = i915_sg_page_sizes(sg); for when we
don't compute them inline. For popular interfaces (userptr being one of
them) we should look at computing page_sizes inline.
-Chris
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[Intel-gfx] [PATCH v3 6/9] drm/i915/guc: Move Guc early init into own function
We don't want to make aggregate uc functions to be too detailed.
This will also make future patch easier.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Joonas Lahtinen
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0b6c931..b1bd4d3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -88,10 +88,8 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
-void intel_uc_init_early(struct drm_i915_private *dev_priv)
+static void guc_init_early(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
-
intel_guc_ct_init_early(&guc->ct);
mutex_init(&guc->send_mutex);
@@ -99,6 +97,11 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
guc->notify = gen8_guc_raise_irq;
}
+void intel_uc_init_early(struct drm_i915_private *dev_priv)
+{
+ guc_init_early(&dev_priv->guc);
+}
+
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
{
i915_fetch_uc_fw(dev_priv, &dev_priv->huc.fw);
--
2.7.4
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 5/9] drm/i915/huc: Move HuC declarations into dedicated header
We want to keep each uC specific code in separate files.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_huc.h | 39 +++
drivers/gpu/drm/i915/intel_uc.h | 13 +
2 files changed, 40 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 000..d58422b
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw fw;
+
+ /* HuC-specific additions */
+};
+
+void intel_huc_select_fw(struct intel_huc *huc);
+void intel_huc_init_hw(struct intel_huc *huc);
+void intel_huc_auth(struct intel_huc *huc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f0d5a3f..4fa091e 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -30,6 +30,7 @@
#include "intel_ringbuffer.h"
#include "intel_guc_ct.h"
#include "i915_vma.h"
+#include "intel_huc.h"
/*
* This structure primarily describes the GEM object shared with the GuC.
@@ -127,13 +128,6 @@ struct intel_guc {
void (*notify)(struct intel_guc *guc);
};
-struct intel_huc {
- /* Generic uC firmware management */
- struct intel_uc_fw fw;
-
- /* HuC-specific additions */
-};
-
/* intel_uc.c */
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
void intel_uc_init_early(struct drm_i915_private *dev_priv);
@@ -186,9 +180,4 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
return offset;
}
-/* intel_huc.c */
-void intel_huc_select_fw(struct intel_huc *huc);
-void intel_huc_init_hw(struct intel_huc *huc);
-void intel_huc_auth(struct intel_huc *huc);
-
#endif
--
2.7.4
___
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[Intel-gfx] [PATCH v3 3/9] drm/i915/uc: Create intel_uc_init_mmio
From: Sagar Arun Kamble
This patch adds new function intel_uc_init_mmio which will initialize
MMIO access related variables prior to uc load/init.
v2: Removed unnecessary export of guc_send_init_regs. Created
intel_uc_init_mmio that currently wraps guc_init_send_regs. (Michal)
v3 (Michal): add kerneldoc (Joonas)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/intel_uc.c | 15 +--
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5cc2434..74a456f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1007,6 +1007,8 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
intel_uncore_init(dev_priv);
+ intel_uc_init_mmio(dev_priv);
+
ret = intel_engines_init_mmio(dev_priv);
if (ret)
goto err_uncore;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2774778..8151a9d 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -288,6 +288,19 @@ static void guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
}
+/**
+ * intel_uc_init_mmio - setup uC MMIO access
+ *
+ * @dev_priv: device private
+ *
+ * Setup minimal state necessary for MMIO accesses later in the
+ * initialization sequence.
+ */
+void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
+{
+ guc_init_send_regs(&dev_priv->guc);
+}
+
static void guc_capture_load_err_log(struct intel_guc *guc)
{
if (!guc->log.vma || i915_modparams.guc_log_level < 0)
@@ -309,8 +322,6 @@ static int guc_enable_communication(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- guc_init_send_regs(guc);
-
if (HAS_GUC_CT(dev_priv))
return intel_guc_enable_ct(guc);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 38ec880..388528f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -202,6 +202,7 @@ struct intel_huc {
/* intel_uc.c */
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
void intel_uc_init_early(struct drm_i915_private *dev_priv);
+void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
void intel_uc_init_fw(struct drm_i915_private *dev_priv);
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
--
2.7.4
___
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[Intel-gfx] [PATCH v3 9/9] drm/i915/guc: Move GuC core definitions into dedicated files
We want to keep GuC specific code in separated files.
v2: move all functions in single patch (Joonas)
fix old checkpatch issues (Sagar)
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble #1
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 94 --
drivers/gpu/drm/i915/intel_guc.c | 264 +
drivers/gpu/drm/i915/intel_guc.h | 110
drivers/gpu/drm/i915/intel_uc.c| 146 +---
drivers/gpu/drm/i915/intel_uc.h| 78 +
6 files changed, 378 insertions(+), 315 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc.c
create mode 100644 drivers/gpu/drm/i915/intel_guc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4850f26..51d0d29 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -60,6 +60,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
intel_uc_fw.o \
+ intel_guc.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 97dfe96..7460ab4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -644,48 +644,6 @@ static void i915_guc_irq_handler(unsigned long data)
* path of i915_guc_submit() above.
*/
-/**
- * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
- * @guc: the guc
- * @size: size of area to allocate (both virtual space and memory)
- *
- * This is a wrapper to create an object for use with the GuC. In order to
- * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
- * both some backing storage and a range inside the Global GTT. We must pin
- * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
- * range is reserved inside GuC.
- *
- * Return: A i915_vma if successful, otherwise an ERR_PTR.
- */
-struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- int ret;
-
- obj = i915_gem_object_create(dev_priv, size);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
- vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
- if (IS_ERR(vma))
- goto err;
-
- ret = i915_vma_pin(vma, 0, PAGE_SIZE,
- PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- return vma;
-
-err:
- i915_gem_object_put(obj);
- return vma;
-}
-
/* Check that a doorbell register is in the expected state */
static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
{
@@ -1213,55 +1171,3 @@ void i915_guc_submission_disable(struct drm_i915_private
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915_modparams.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 000..bbe4c32
--- /dev/
[Intel-gfx] [PATCH v3 8/9] drm/i915/guc: Move GuC submission declarations into dedicated header
We want to keep uC specific code in separate files.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Cc: MichaĹ Winiarski
---
drivers/gpu/drm/i915/i915_debugfs.c| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 7 +--
drivers/gpu/drm/i915/i915_guc_submission.h | 79 ++
drivers/gpu/drm/i915/intel_uc.c| 1 +
drivers/gpu/drm/i915/intel_uc.h| 45 -
5 files changed, 85 insertions(+), 48 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_guc_submission.h
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b4a6ac6..44aae25 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -30,6 +30,7 @@
#include
#include
#include "intel_drv.h"
+#include "i915_guc_submission.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 04f1281..97dfe96 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -21,12 +21,13 @@
* IN THE SOFTWARE.
*
*/
-#include
-#include "i915_drv.h"
-#include "intel_uc.h"
+#include
#include
+#include "i915_guc_submission.h"
+#include "i915_drv.h"
+
/**
* DOC: GuC-based command submission
*
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.h
b/drivers/gpu/drm/i915/i915_guc_submission.h
new file mode 100644
index 000..b43af42
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_guc_submission.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _I915_GUC_SUBMISSION_H_
+#define _I915_GUC_SUBMISSION_H_
+
+#include
+#include "i915_gem.h"
+
+struct drm_i915_private;
+
+/*
+ * This structure primarily describes the GEM object shared with the GuC.
+ * The specs sometimes refer to this object as a "GuC context", but we use
+ * the term "client" to avoid confusion with hardware contexts. This
+ * GEM object is held for the entire lifetime of our interaction with
+ * the GuC, being allocated before the GuC is loaded with its firmware.
+ * Because there's no way to update the address used by the GuC after
+ * initialisation, the shared object must stay pinned into the GGTT as
+ * long as the GuC is in use. We also keep the first page (only) mapped
+ * into kernel address space, as it includes shared data that must be
+ * updated on every request submission.
+ *
+ * The single GEM object described here is actually made up of several
+ * separate areas, as far as the GuC is concerned. The first page (kept
+ * kmap'd) includes the "process descriptor" which holds sequence data for
+ * the doorbell, and one cacheline which actually *is* the doorbell; a
+ * write to this will "ring the doorbell" (i.e. send an interrupt to the
+ * GuC). The subsequent pages of the client object constitute the work
+ * queue (a circular array of work items), again described in the process
+ * descriptor. Work queue pages are mapped momentarily as required.
+ */
+struct i915_guc_client {
+ struct i915_vma *vma;
+ void *vaddr;
+ struct i915_gem_context *owner;
+ struct intel_guc *guc;
+
+ /* bitmap of (host) engine ids */
+ uint32_t engines;
+ uint32_t priority;
+ u32 stage_id;
+ uint32_t proc_desc_offset;
+
+ u16 doorbell_id;
+ unsigned long doorbell_offset;
+
+ spinlock_t wq_lock;
+ /* Per-engine counts of GuC submissions */
+ uint64_t submissions[I915_NUM_ENGINES];
+};
+
+int i915_guc_submission_init(struct drm_i915_private *dev_priv);
+int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
+void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
+void i91
[Intel-gfx] [PATCH v3 1/9] drm/i915: Make intel_uncore.h header self-contained
We're trying to resolve inter-header dependencies.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uncore.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 03786f9..66eae2c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -25,6 +25,12 @@
#ifndef __INTEL_UNCORE_H__
#define __INTEL_UNCORE_H__
+#include
+#include
+#include
+
+#include "i915_reg.h"
+
struct drm_i915_private;
enum forcewake_domain_id {
--
2.7.4
___
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[Intel-gfx] [PATCH v3 7/9] drm/i915/guc: Move GuC log declarations into dedicated header
We want to keep component specific code in separate files.
Suggested-by: Joonas Lahtinen
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_log.c | 1 +
drivers/gpu/drm/i915/intel_guc_log.h | 57
drivers/gpu/drm/i915/intel_uc.h | 26 +---
3 files changed, 59 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_log.h
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 6571d96..bd9b02e 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -23,6 +23,7 @@
*/
#include
#include
+#include "intel_guc_log.h"
#include "i915_drv.h"
static void guc_log_capture_logs(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h
b/drivers/gpu/drm/i915/intel_guc_log.h
new file mode 100644
index 000..099a0c8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_GUC_LOG_H_
+#define _INTEL_GUC_LOG_H_
+
+#include
+#include "intel_guc_fwif.h"
+
+struct drm_i915_private;
+struct intel_guc;
+
+struct intel_guc_log {
+ uint32_t flags;
+ struct i915_vma *vma;
+ /* The runtime stuff gets created only when GuC logging gets enabled */
+ struct {
+ void *buf_addr;
+ struct workqueue_struct *flush_wq;
+ struct work_struct flush_work;
+ struct rchan *relay_chan;
+ } runtime;
+ /* logging related stats */
+ u32 capture_miss_count;
+ u32 flush_interrupt_count;
+ u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
+ u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
+ u32 flush_count[GUC_MAX_LOG_BUFFER];
+};
+
+int intel_guc_log_create(struct intel_guc *guc);
+void intel_guc_log_destroy(struct intel_guc *guc);
+int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
+void i915_guc_log_register(struct drm_i915_private *dev_priv);
+void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 4fa091e..86ae507 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -29,6 +29,7 @@
#include "i915_guc_reg.h"
#include "intel_ringbuffer.h"
#include "intel_guc_ct.h"
+#include "intel_guc_log.h"
#include "i915_vma.h"
#include "intel_huc.h"
@@ -72,24 +73,6 @@ struct i915_guc_client {
uint64_t submissions[I915_NUM_ENGINES];
};
-struct intel_guc_log {
- uint32_t flags;
- struct i915_vma *vma;
- /* The runtime stuff gets created only when GuC logging gets enabled */
- struct {
- void *buf_addr;
- struct workqueue_struct *flush_wq;
- struct work_struct flush_work;
- struct rchan *relay_chan;
- } runtime;
- /* logging related stats */
- u32 capture_miss_count;
- u32 flush_interrupt_count;
- u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
- u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
- u32 flush_count[GUC_MAX_LOG_BUFFER];
-};
-
struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
@@ -165,13 +148,6 @@ void i915_guc_submission_disable(struct drm_i915_private
*dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-/* intel_guc_log.c */
-int intel_guc_log_create(struct intel_guc *guc);
-void intel_guc_log_destroy(struct intel_guc *guc);
-int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
-void i915_guc_log_register(struct drm_i915_private
[Intel-gfx] [PATCH v3 0/9] drm/i915: Guc code reorg
Other pending series will try to fix current GuC code. Lets move some functions to dedicated files now to make place for these changes and preserve history. v2: move guc files in one step (Joonas) don't rename dev_priv (Joonas) uc_init_mmio (Sagar) v3: more dedicated headers (Joonas) Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Sagar Arun Kamble Michal Wajdeczko (8): drm/i915: Make intel_uncore.h header self-contained drm/i915/uc: Drop unnecessary forward declaration drm/i915/uc: Move uC fw helper code into dedicated files drm/i915/huc: Move HuC declarations into dedicated header drm/i915/guc: Move Guc early init into own function drm/i915/guc: Move GuC log declarations into dedicated header drm/i915/guc: Move GuC submission declarations into dedicated header drm/i915/guc: Move GuC core definitions into dedicated files Sagar Arun Kamble (1): drm/i915/uc: Create intel_uc_init_mmio drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/i915_debugfs.c| 1 + drivers/gpu/drm/i915/i915_drv.c| 2 + drivers/gpu/drm/i915/i915_guc_submission.c | 101 +- drivers/gpu/drm/i915/i915_guc_submission.h | 79 drivers/gpu/drm/i915/intel_guc.c | 264 drivers/gpu/drm/i915/intel_guc.h | 110 ++ drivers/gpu/drm/i915/intel_guc_log.c | 1 + drivers/gpu/drm/i915/intel_guc_log.h | 57 ++ drivers/gpu/drm/i915/intel_huc.h | 39 drivers/gpu/drm/i915/intel_uc.c| 310 ++--- drivers/gpu/drm/i915/intel_uc.h| 228 + drivers/gpu/drm/i915/intel_uc_fw.c | 179 + drivers/gpu/drm/i915/intel_uc_fw.h | 98 + drivers/gpu/drm/i915/intel_uncore.h| 6 + 15 files changed, 861 insertions(+), 616 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_guc_submission.h create mode 100644 drivers/gpu/drm/i915/intel_guc.c create mode 100644 drivers/gpu/drm/i915/intel_guc.h create mode 100644 drivers/gpu/drm/i915/intel_guc_log.h create mode 100644 drivers/gpu/drm/i915/intel_huc.h create mode 100644 drivers/gpu/drm/i915/intel_uc_fw.c create mode 100644 drivers/gpu/drm/i915/intel_uc_fw.h -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4 4/6] tests/kms_ccs: Test case where the CCS buffer was not provided
On 17-09-27 15:34:17, Gabriel Krisman Bertazi wrote:
Signed-off-by: Gabriel Krisman Bertazi
---
tests/kms_ccs.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 73025a1e019f..35dfcca6be14 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -33,8 +33,12 @@ enum test_flags {
TEST_ROTATE_180 = 1 << 2,
TEST_BAD_PIXEL_FORMAT = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
+ TEST_NO_AUX_BUFFER = 1 << 5,
};
+#define TEST_FAIL_ON_ADDFB2 \
+ (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+
Adding the define confuses things more than it helps IMO.
enum test_fb_flags {
FB_COMPRESSED = 1 << 0,
FB_HAS_PLANE= 1 << 1,
@@ -315,22 +319,29 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
*/
int ccs_width = ALIGN(width * 4, 32) / 32;
int ccs_height = ALIGN(height, 16) / 16;
- f.pitches[1] = ALIGN(ccs_width * 1, 128);
- f.modifier[1] = modifier;
I think the case you're trying to test should have the modifier set for plane1,
just no handle, size or whatever. If you don't do this, I'm not sure what you're
actually testing.
- f.offsets[1] = size[0];
- size[1] = f.pitches[1] * ALIGN(ccs_height, 32);
+ int ccs_pitches = ALIGN(ccs_width * 1, 128);
+ int ccs_offsets = size[0];
+
+ size[1] = ccs_pitches * ALIGN(ccs_height, 32);
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
- f.handles[1] = f.handles[0];
- render_ccs(data, f.handles[1], f.offsets[1], size[1],
- height, f.pitches[1]);
+
+ if (!(data->flags & TEST_NO_AUX_BUFFER)) {
+ f.modifier[1] = modifier;
+ f.handles[1] = f.handles[0];
+ f.pitches[1] = ccs_pitches;
+ f.offsets[1] = ccs_offsets;
+
+ render_ccs(data, f.handles[1], f.offsets[1], size[1],
+ height, f.pitches[1]);
+ }
} else
f.handles[0] = gem_create(data->drm_fd, size[0]);
render_fb(data, f.handles[0], size[0], fb_flags, height, f.pitches[0]);
ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f);
- if (data->flags & TEST_BAD_PIXEL_FORMAT) {
+ if (data->flags & TEST_FAIL_ON_ADDFB2) {
igt_assert_eq(ret, -1);
igt_assert_eq(errno, EINVAL);
return;
@@ -379,7 +390,7 @@ static void try_config(data_t *data, enum test_fb_flags
fb_flags)
drm_mode->vdisplay, fb_flags);
}
- if (data->flags & TEST_BAD_PIXEL_FORMAT)
+ if (data->flags & TEST_FAIL_ON_ADDFB2)
return;
igt_plane_set_position(primary, 0, 0);
@@ -446,7 +457,8 @@ static void test_output(data_t *data)
}
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
- data->flags & TEST_BAD_ROTATION_90) {
+ data->flags & TEST_BAD_ROTATION_90 ||
+ data->flags & TEST_NO_AUX_BUFFER) {
try_config(data, fb_flags | FB_COMPRESSED);
}
@@ -515,6 +527,11 @@ igt_main
}
data.plane = NULL;
+
+ data.flags = TEST_NO_AUX_BUFFER;
+ igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
+ test_output(&data);
+
}
igt_fixture
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size (rev2)
== Series Details == Series: drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size (rev2) URL : https://patchwork.freedesktop.org/series/31284/ State : warning == Summary == Series 31284v2 drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size https://patchwork.freedesktop.org/api/1.0/series/31284/revisions/2/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 Test prime_vgem: Subgroup basic-fence-flip: pass -> DMESG-WARN (fi-kbl-7500u) fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:468s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:400s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:588s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:291s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:537s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:535s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:553s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:536s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:559s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:634s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:442s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:604s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:443s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:474s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:502s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s fi-kbl-7500u total:289 pass:262 dwarn:2 dfail:0 fail:1 skip:24 time:496s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:483s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:537s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:526s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:585s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:437s 5a0359bf59aa712a9e81ce7f75c3cd3c884cfeee drm-tip: 2017y-10m-03d-13h-34m-56s UTC integration manifest c7d9cef18bca drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5881/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC i-g-t 5/6] tests/gem_concurrent_all: drop stolen memory related subtests
Quoting Daniele Ceraolo Spurio (2017-10-03 17:14:21)
>
>
> On 03/10/17 04:11, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:17)
> >> The feature was never merged and there has been no progress in the
> >> last year. The tests are currently excluded from compilation with and
> >> ifdef.
> >>
> >> Cc: Chris Wilson
> >> Signed-off-by: Daniele Ceraolo Spurio
> >> ---
> >> tests/gem_concurrent_all.c | 35 ---
> >> 1 file changed, 35 deletions(-)
> >>
> >> diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
> >> index 201b491..87f2129 100644
> >> --- a/tests/gem_concurrent_all.c
> >> +++ b/tests/gem_concurrent_all.c
> >> @@ -170,36 +170,6 @@ static void can_create_private(const struct create
> >> *create, unsigned count)
> >> }
> >> #endif
> >>
> >> -#if HAVE_CREATE_STOLEN
> >> -static drm_intel_bo *
> >> -create_stolen_bo(drm_intel_bufmgr *bufmgr, uint64_t size)
> >> -{
> >> - drm_intel_bo *bo;
> >> - uint32_t handle;
> >> -
> >> - /* XXX gem_create_with_flags(fd, size, I915_CREATE_STOLEN); */
> >> -
> >> - handle = gem_create(fd, size);
> >> - bo = gem_handle_to_libdrm_bo(bufmgr, fd, "stolen", handle);
> >> - gem_close(fd, handle);
> >> -
> >> - return bo;
> >> -}
> >> -
> >> -static void can_create_stolen(const struct create *create, unsigned count)
> >> -{
> >> - /* XXX check num_buffers against available stolen */
> >> - igt_require(0);
> >> -}
> >> -#endif
> >> -
> >> -static void create_cpu_require(const struct create *create, unsigned
> >> count)
> >> -{
> >> -#if HAVE_CREATE_STOLEN
> >> - igt_require(create->create != create_stolen_bo);
> >> -#endif
> >> -}
> >> -
> >> static drm_intel_bo *
> >> unmapped_create_bo(const struct buffers *b)
> >> {
> >> @@ -208,7 +178,6 @@ unmapped_create_bo(const struct buffers *b)
> >>
> >> static void create_snoop_require(const struct create *create, unsigned
> >> count)
> >> {
> >> - create_cpu_require(create, count);
> >
> > Pardon? It's about being descriptive of the requirements, for the snooping
> > code paths,
> > the bo must be cpu accessible.
> > -Chris
> >
>
> Would it be ok for you to just leave create_cpu_require() as an empty
> function or do you have something else in mind?
Leave it as empty. It's primary purpose is a placeholder for
restrictions as they come to light.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mst: Use MST sideband message transactions for dpms control (rev2)
== Series Details == Series: drm/i915/mst: Use MST sideband message transactions for dpms control (rev2) URL : https://patchwork.freedesktop.org/series/30314/ State : success == Summary == Test kms_cursor_legacy: Subgroup pipe-B-torture-bo: incomplete -> PASS (shard-hsw) Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1313 dwarn:7 dfail:0 fail:26 skip:1083 time:9979s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5880/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC i-g-t 5/6] tests/gem_concurrent_all: drop stolen memory related subtests
On 03/10/17 04:11, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:17)
The feature was never merged and there has been no progress in the
last year. The tests are currently excluded from compilation with and
ifdef.
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
tests/gem_concurrent_all.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
index 201b491..87f2129 100644
--- a/tests/gem_concurrent_all.c
+++ b/tests/gem_concurrent_all.c
@@ -170,36 +170,6 @@ static void can_create_private(const struct create
*create, unsigned count)
}
#endif
-#if HAVE_CREATE_STOLEN
-static drm_intel_bo *
-create_stolen_bo(drm_intel_bufmgr *bufmgr, uint64_t size)
-{
- drm_intel_bo *bo;
- uint32_t handle;
-
- /* XXX gem_create_with_flags(fd, size, I915_CREATE_STOLEN); */
-
- handle = gem_create(fd, size);
- bo = gem_handle_to_libdrm_bo(bufmgr, fd, "stolen", handle);
- gem_close(fd, handle);
-
- return bo;
-}
-
-static void can_create_stolen(const struct create *create, unsigned count)
-{
- /* XXX check num_buffers against available stolen */
- igt_require(0);
-}
-#endif
-
-static void create_cpu_require(const struct create *create, unsigned count)
-{
-#if HAVE_CREATE_STOLEN
- igt_require(create->create != create_stolen_bo);
-#endif
-}
-
static drm_intel_bo *
unmapped_create_bo(const struct buffers *b)
{
@@ -208,7 +178,6 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
- create_cpu_require(create, count);
Pardon? It's about being descriptive of the requirements, for the snooping code
paths,
the bo must be cpu accessible.
-Chris
Would it be ok for you to just leave create_cpu_require() as an empty
function or do you have something else in mind?
Thanks,
Daniele
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Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests
On 03/10/17 08:49, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2017-10-03 16:36:37)
On 03/10/17 04:08, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13)
The feature was never merged and there has been no progress in the
last year. The subtests are currently skipping on all platforms by
checking a field in the get_aperture ioctl structure that doesn't
exist in the kernel version of the struct.
The interface for this is upstream, fix the test to exercise the kernel
code (hint dmabuf).
-Chris
I'm not very familiar with the dmabuf interface, but looking at it I
couldn't find any way of allocating and/or accessing an object in stolen
memory from userspace. A grep for "create_stolen" also didn't show
anything. Can you point me in the right direction?
It's just that a dmabuf of a e.g. vgem bo will use the same pread paths
that we originally wrote for stolen support. (We need a bo that is not
backed by struct page.)
Something like
static uint32_t create_foreign_bo(int device, uint32_t sz, void *data)
{
struct vgem_bo scratch;
int vgem, dmabuf;
uint32_t handle;
vgem = drm_driver_open(DRIVER_VGEM);
scratch.width = 1024;
scratch.height = sz / 4096;
scratch.bpp = 32;
vgem_create(vgem, &scratch);
igt_assert_eq(sz, scratch.size);
if (data) {
void *ptr;
ptr = vgem_mmap(vgem, &scratch, PROT_WRITE);
memcpy(ptr, data, sz);
munmap(ptr, scratch.size);
}
dmabuf = prime_handle_to_fd(vgem, scratch.handle);
handle = prime_fd_to_handle(device, dmabuf);
close(dmabuf);
close(vgem);
return handle;
}
will create a handle that we can pass to pread to exercise the same
paths. For pwrite, we need to keep the vgem bo around so we can read
back from its mmapping.
We do have coverage in prime_vgem.c, but it's not the first place you
would go to exercise i915_gem_pread_ioctl().
-Chris
Thanks for the clarification. I'll update the patch to replace the
stolen tests with the vgem ones.
Daniele
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[Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU (rev2)
== Series Details == Series: lib: Ask the kernel to quiescent the GPU (rev2) URL : https://patchwork.freedesktop.org/series/30890/ State : failure == Summary == IGT patchset tested on top of latest successful build 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from __gem_create() with latest DRM-Tip kernel build CI_DRM_3167 5a0359bf59aa drm-tip: 2017y-10m-03d-13h-34m-56s UTC integration manifest No testlist changes. Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test gem_sync: Subgroup basic-all: pass -> DMESG-FAIL (fi-blb-e6850) pass -> FAIL (fi-pnv-d510) Test gem_workarounds: Subgroup basic-read: pass -> FAIL (fi-bdw-5557u) pass -> FAIL (fi-bdw-gvtdvm) pass -> FAIL (fi-bsw-n3050) pass -> FAIL (fi-skl-6260u) pass -> FAIL (fi-skl-6700k) pass -> FAIL (fi-skl-gvtdvm) pass -> FAIL (fi-bxt-dsi) pass -> FAIL (fi-bxt-j4205) pass -> FAIL (fi-kbl-7500u) pass -> FAIL (fi-kbl-7560u) pass -> FAIL (fi-kbl-7567u) pass -> FAIL (fi-kbl-r) pass -> FAIL (fi-glk-1) pass -> FAIL (fi-cfl-s) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:267 dwarn:0 dfail:0 fail:1 skip:21 time:460s fi-bdw-gvtdvmtotal:289 pass:264 dwarn:0 dfail:0 fail:1 skip:24 time:468s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:1 fail:0 skip:64 time:408s fi-bsw-n3050 total:289 pass:242 dwarn:0 dfail:0 fail:1 skip:46 time:552s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:289s fi-bxt-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:523s fi-bxt-j4205 total:289 pass:259 dwarn:0 dfail:0 fail:1 skip:29 time:530s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:548s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:527s fi-cfl-s total:289 pass:255 dwarn:1 dfail:0 fail:1 skip:32 time:551s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:626s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:430s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:1 skip:28 time:592s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:438s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:416s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:453s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:509s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:476s fi-kbl-7500u total:289 pass:262 dwarn:1 dfail:0 fail:2 skip:24 time:496s fi-kbl-7560u total:289 pass:269 dwarn:0 dfail:0 fail:1 skip:19 time:572s fi-kbl-7567u total:289 pass:264 dwarn:4 dfail:0 fail:1 skip:20 time:480s fi-kbl-r total:289 pass:261 dwarn:0 dfail:0 fail:1 skip:27 time:587s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:1 skip:65 time:651s fi-skl-6260u total:289 pass:268 dwarn:0 dfail:0 fail:1 skip:20 time:470s fi-skl-6700k total:289 pass:264 dwarn:0 dfail:0 fail:1 skip:24 time:533s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:559s fi-skl-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:1 skip:23 time:471s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:584s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:434s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_290/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4 3/6] tests/kms_ccs: Prevent segfault if pipe is not supported
On 17-09-27 15:34:16, Gabriel Krisman Bertazi wrote:
for_each_plane_on_pipe() indexes bad memory when iterating over an invalid
pipe. Make sure the pipe exists before trying to use it. This prevents
the crash below:
root@ideacentre:~# igt-gpu-tools/tests/kms_ccs --r
pipe-D-crc-sprite-planes-basic
IGT-Version: 1.19-g59f0e3d182a8 (x86_64) (Linux: 4.13.0-rc6.intel-boxes+x86_64)
Received signal SIGSEGV.
Stack trace:
#0 [fatal_sig_handler+0x185]
#1 [killpg+0x40]
#2 [__real_main485+0x2de]
#3 [main+0x3f]
#4 [__libc_start_main+0xf1]
#5 [_start+0x2a]
#6 [+0x2a]
Subtest pipe-D-crc-sprite-planes-basic: CRASH (0.004s)
Signed-off-by: Gabriel Krisman Bertazi
1-3 so far are
Reviewed-by: Ben Widawsky
---
tests/kms_ccs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 775c6999699f..73025a1e019f 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -503,6 +503,9 @@ igt_main
data.flags = TEST_CRC;
igt_subtest_f("pipe-%s-crc-sprite-planes-basic", pipe_name) {
+
+ igt_display_require_output_on_pipe(&data.display,
data.pipe);
+
for_each_plane_on_pipe(&data.display, data.pipe,
data.plane) {
if (data.plane->type == DRM_PLANE_TYPE_PRIMARY)
continue;
--
2.11.0
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Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests
Quoting Daniele Ceraolo Spurio (2017-10-03 16:36:37)
>
>
> On 03/10/17 04:08, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13)
> >> The feature was never merged and there has been no progress in the
> >> last year. The subtests are currently skipping on all platforms by
> >> checking a field in the get_aperture ioctl structure that doesn't
> >> exist in the kernel version of the struct.
> >
> > The interface for this is upstream, fix the test to exercise the kernel
> > code (hint dmabuf).
> > -Chris
> >
>
> I'm not very familiar with the dmabuf interface, but looking at it I
> couldn't find any way of allocating and/or accessing an object in stolen
> memory from userspace. A grep for "create_stolen" also didn't show
> anything. Can you point me in the right direction?
It's just that a dmabuf of a e.g. vgem bo will use the same pread paths
that we originally wrote for stolen support. (We need a bo that is not
backed by struct page.)
Something like
static uint32_t create_foreign_bo(int device, uint32_t sz, void *data)
{
struct vgem_bo scratch;
int vgem, dmabuf;
uint32_t handle;
vgem = drm_driver_open(DRIVER_VGEM);
scratch.width = 1024;
scratch.height = sz / 4096;
scratch.bpp = 32;
vgem_create(vgem, &scratch);
igt_assert_eq(sz, scratch.size);
if (data) {
void *ptr;
ptr = vgem_mmap(vgem, &scratch, PROT_WRITE);
memcpy(ptr, data, sz);
munmap(ptr, scratch.size);
}
dmabuf = prime_handle_to_fd(vgem, scratch.handle);
handle = prime_fd_to_handle(device, dmabuf);
close(dmabuf);
close(vgem);
return handle;
}
will create a handle that we can pass to pread to exercise the same
paths. For pwrite, we need to keep the vgem bo around so we can read
back from its mmapping.
We do have coverage in prime_vgem.c, but it's not the first place you
would go to exercise i915_gem_pread_ioctl().
-Chris
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[Intel-gfx] [PATCH] drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size
BSpec indicates exactly 16752 DWORDs (17 pages), plus one page for PPHWSP.
BSpec: 1383
v2: Update count and add BSpec tag (Joonas)
Suggested-by: Joonas Lahtinen
Fixes: 7fd0b1a ("drm/i915/cnl: Add Gen10 LRC size")
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: Ben Widawsky
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a75f5e8..25ef740 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -39,7 +39,7 @@
#define GEN8_LR_CONTEXT_RENDER_SIZE(20 * PAGE_SIZE)
#define GEN9_LR_CONTEXT_RENDER_SIZE(22 * PAGE_SIZE)
-#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * PAGE_SIZE)
+#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
--
1.9.1
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] igt/gem_workarounds: Read the workaround registers from the active context
== Series Details == Series: series starting with [CI,1/5] igt/gem_workarounds: Read the workaround registers from the active context URL : https://patchwork.freedesktop.org/series/31325/ State : warning == Summary == IGT patchset tested on top of latest successful build 0045085c632a1cf5b4e9272304ee0e61ff9a7e6f lib: Report the error from __gem_create() with latest DRM-Tip kernel build CI_DRM_3167 5a0359bf59aa drm-tip: 2017y-10m-03d-13h-34m-56s UTC integration manifest Testlist changes: +igt@gem_workarounds@basic-read-context +igt@gem_workarounds@basic-read-fd +igt@gem_workarounds@hibernate-resume +igt@gem_workarounds@hibernate-resume-context +igt@gem_workarounds@hibernate-resume-fd +igt@gem_workarounds@reset-context +igt@gem_workarounds@reset-fd +igt@gem_workarounds@suspend-resume-context +igt@gem_workarounds@suspend-resume-fd Test gem_workarounds: Subgroup basic-read: pass -> SKIP (fi-blb-e6850) pass -> SKIP (fi-pnv-d510) pass -> SKIP (fi-bwr-2160) pass -> SKIP (fi-elk-e7500) pass -> SKIP (fi-ilk-650) pass -> SKIP (fi-snb-2520m) pass -> SKIP (fi-snb-2600) pass -> SKIP (fi-ivb-3520m) pass -> SKIP (fi-ivb-3770) pass -> SKIP (fi-byt-j1900) pass -> SKIP (fi-byt-n2820) pass -> SKIP (fi-hsw-4770) pass -> SKIP (fi-hsw-4770r) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 Test drv_module_reload: Subgroup basic-reload-inject: pass -> DMESG-WARN (fi-cfl-s) k.org#196765 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 k.org#196765 https://bugzilla.kernel.org/show_bug.cgi?id=196765 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:458s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:396s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:582s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:289s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:535s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:538s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:553s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:539s fi-cfl-s total:289 pass:255 dwarn:2 dfail:0 fail:0 skip:32 time:552s fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:641s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:596s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:441s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:469s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:479s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:508s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:491s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:653s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:471s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:547s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:519s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:479s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:591s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:440s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_289/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC size
On 10/03/2017 05:25 AM, Joonas Lahtinen wrote: On Mon, 2017-10-02 at 13:31 -0700, Oscar Mateo wrote: BSpec indicates exactly 16750 DWORDs (17 pages), plus one page for PPHWSP. Assuming this is; Bspec: 1383 I'm actually getting 16801 DWORDs by copy-pasting to spreadsheet and summing up. Are we looking from different places? No, we are looking at the same BSpec page, but you need to filter by "CNL" (that will remove some fields). Even then, I'm now getting 16752 instead of 16750 (maybe they have updated some tags?). I'll resend with the BSpec tag, the new count and your RB, if that's OK. Both lead to the same amount of pages, but I'd like the commit message to be correct for easier double-checking :) With commit message corrected and the Bspec: tag added (or more correct Bspec: tag specified), this is; Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC i-g-t 1/6] tests/gem_pread: drop stolen memory related subtests
On 03/10/17 04:08, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2017-10-03 00:00:13) The feature was never merged and there has been no progress in the last year. The subtests are currently skipping on all platforms by checking a field in the get_aperture ioctl structure that doesn't exist in the kernel version of the struct. The interface for this is upstream, fix the test to exercise the kernel code (hint dmabuf). -Chris I'm not very familiar with the dmabuf interface, but looking at it I couldn't find any way of allocating and/or accessing an object in stolen memory from userspace. A grep for "create_stolen" also didn't show anything. Can you point me in the right direction? Thanks, Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/5] igt/gem_workarounds: Read the workaround registers from the active context
Quoting Mika Kuoppala (2017-10-03 16:19:10)
> Chris Wilson writes:
>
> > The workarounds are only valid whilst the GPU is active. To be sure we
> > are reading the registers in the right state, issue the reads from the GPU.
> >
>
> Yay, this is the right way :)
>
> Some comments and findings below...
>
> > v2: Show ignored write-only failures as debug.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > tests/gem_workarounds.c | 147
> > ++--
> > 1 file changed, 81 insertions(+), 66 deletions(-)
> >
> > diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
> > index 5e30a7b8..95ec250a 100644
> > --- a/tests/gem_workarounds.c
> > +++ b/tests/gem_workarounds.c
> > @@ -61,20 +61,6 @@ static struct write_only_list {
> > static struct intel_wa_reg *wa_regs;
> > static int num_wa_regs;
> >
> > -static void wait_gpu(void)
> > -{
> > - int fd = drm_open_driver(DRIVER_INTEL);
> > - gem_quiescent_gpu(fd);
> > - close(fd);
> > -}
> > -
> > -static void test_hang_gpu(void)
> > -{
> > - int fd = drm_open_driver(DRIVER_INTEL);
> > - igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
> > - close(fd);
> > -}
> > -
> > static void test_suspend_resume(void)
> > {
> > igt_info("Suspending the device ...\n");
> > @@ -96,49 +82,95 @@ static bool write_only(const uint32_t addr)
> > return false;
> > }
> >
> > -static int workaround_fail_count(void)
> > -{
> > - int i, fail_count = 0;
> > -
> > - /* There is a small delay after coming ot of rc6 to the correct
> > -render context values will get loaded by hardware (bdw,chv).
> > -This here ensures that we have the correct context loaded before
> > -we start to read values */
> > - wait_gpu();
> > +#define MI_STORE_REGISTER_MEM (0x24 << 23)
> >
> > - igt_debug("Addressvalmaskreadresult\n");
> > +static int workaround_fail_count(int fd)
> > +{
> > + struct drm_i915_gem_exec_object2 obj[2];
> > + struct drm_i915_gem_relocation_entry *reloc;
> > + struct drm_i915_gem_execbuffer2 execbuf;
> > + uint32_t result_sz, batch_sz;
> > + uint32_t *base, *out;
> > + int fail_count = 0;
> > +
> > + reloc = calloc(num_wa_regs, sizeof(*reloc));
> > + igt_assert(reloc);
> > +
> > + result_sz = 4 * num_wa_regs;
> > + result_sz = (result_sz + 4095) & -4096;
>
> Macro for align?
I never remember if we have PAGE_ALIGN() or not. Quicker to write than
grep.
> Further, why do even need it. For
> what I can gather, the mapping should work for smaller
> objects also.
Our mmap interfaces we like to operate on pages and tend to complain for
some interfaces if not, or not whole object. So it is just simpler to
think in pages and not worry about which work on less.
> > -static void check_workarounds(enum operation op)
> > +static void check_workarounds(int fd, enum operation op)
> > {
> > - igt_assert_eq(workaround_fail_count(), 0);
> > + igt_assert_eq(workaround_fail_count(fd), 0);
> >
> > switch (op) {
> > case GPU_RESET:
> > - test_hang_gpu();
> > + igt_force_gpu_reset(fd);
>
> My kbl fails with the tests as you need some mechanism
> to wait that the reset really did happen?
It waits for the reset to complete (double checked, otherwise we have a
number of nasty races around).
> Hmm the kernel should ensure that the next reading batch
> is post reset and everything should be fine.
>
> (gem_workarounds:7286) WARNING: 0x024D0 0x2248 0x
> 0x2094 FAIL
> (gem_workarounds:7286) WARNING: 0x024D4 0x2580 0x
> 0x2094 FAIL
> (gem_workarounds:7286) WARNING: 0x024D8 0x7304 0x
> 0x2094 FAIL
These are RING_FORCE_TO_NONPRIV, hence the thread about moving them from
the WA_WRITE to I915_WRITE as they are not part of the context image.
https://patchwork.freedesktop.org/series/31099/
-Chris
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