[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE 
(rev2)
URL   : https://patchwork.freedesktop.org/series/34044/
State : success

== Summary ==

Warning: bzip CI_DRM_3359/shard-glkb6/results1.json.bz2 wasn't in correct JSON 
format
Test kms_flip:
Subgroup flip-vs-modeset-interruptible:
dmesg-warn -> PASS   (shard-hsw)
Test drv_suspend:
Subgroup sysfs-reader-hibernate:
fail   -> SKIP   (shard-snb) fdo#103375 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2585 pass:1474 dwarn:1   dfail:1   fail:9   skip:1100 
time:9483s
shard-snbtotal:2585 pass:1260 dwarn:1   dfail:1   fail:11  skip:1312 
time:8025s
Blacklisted hosts:
shard-apltotal:2565 pass:1600 dwarn:1   dfail:0   fail:26  skip:936 
time:12997s
shard-kbltotal:2431 pass:1614 dwarn:5   dfail:1   fail:21  skip:786 
time:9174s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7184/shards.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/lrc: Stop writing to ELSP until HW has processed the previous write

[Patchwork]

== Series Details ==

Series: drm/i915/lrc: Stop writing to ELSP until HW has processed the previous 
write
URL   : https://patchwork.freedesktop.org/series/34043/
State : warning

== Summary ==

Warning: bzip CI_DRM_3359/shard-glkb6/results1.json.bz2 wasn't in correct JSON 
format
Test kms_flip:
Subgroup flip-vs-modeset-interruptible:
dmesg-warn -> PASS   (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-128x128-sliding:
pass   -> SKIP   (shard-hsw)
Test pm_rpm:
Subgroup basic-rte:
pass   -> SKIP   (shard-hsw)

shard-hswtotal:2585 pass:1473 dwarn:1   dfail:1   fail:9   skip:1101 
time:9405s
shard-snbtotal:2585 pass:1261 dwarn:1   dfail:1   fail:11  skip:1311 
time:8013s
Blacklisted hosts:
shard-apltotal:2547 pass:1591 dwarn:2   dfail:0   fail:23  skip:929 
time:13018s
shard-kbltotal:2442 pass:1629 dwarn:4   dfail:0   fail:23  skip:783 
time:10521s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7182/shards.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/9] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/9] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34049/
State : warning

== Summary ==

Series 34049v1 series starting with [CI,1/9] drm/i915/execlists: Listen to 
COMPLETE context event not ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34049/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup prune-stale-modes:
pass   -> SKIP   (fi-snb-2600)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:452s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:527s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:499s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:504s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:491s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:434s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:273s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:424s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:490s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:532s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:578s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:543s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:503s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:465s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:566s
fi-snb-2600  total:289  pass:248  dwarn:0   dfail:0   fail:0   skip:41  
time:420s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:612s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:550s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:494s

72ffd011e980c8131f0c63e08c576d09977a2c54 drm-tip: 2017y-11m-17d-18h-38m-47s UTC 
integration manifest
3dd9238c5f6b drm/i915: Unwind incomplete legacy context switches
3860b874cade drm/i915: Remove i915.semaphores modparam
541abe96ec57 drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info
6eaf5e5d7015 drm/i915: Disable semaphores on Sandybridge
9e08bb6cca7d drm/i915: Remove obsolete ringbuffer emission for gen8+
6be56a6eccfa drm/i915: Remove i915.enable_execlists module parameter
2852e69c777f drm/i915: Automatic i915_switch_context for legacy
984f39da4597 drm/i915: Pull the unconditional GPU cache invalidation into 
request construction
8048d3110f91 drm/i915/execlists: Listen to COMPLETE context event not 
ACTIVE_IDLE

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7185/
___
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[Intel-gfx] [CI 5/9] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

ring  execlists
exec continuous nops on all rings:   n/a1.921us
exec sequential nops on each ring:   n/a   44.621us
single nop + sync:   n/a   21.953us

vblank_mode=0 glxgears:  n/a  ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
Once-upon-a-time-Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c   |  36 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  14 --
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 431 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 9 files changed, 94 insertions(+), 551 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e2a6e18771f..9cef1463d411 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a21544b62866..953867d9171e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -942,7 +942,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
 
struct drm_i915_error_engine {

[Intel-gfx] [CI 8/9] drm/i915: Remove i915.semaphores modparam

[Chris Wilson]

Having disabled the broken semaphores on Sandybridge, there is no need
for a modparam any more, so remove it in favour of a simple
HAS_LEGACY_SEMAPHORES() guard.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +--
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
 8 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 779a6f0785c7..36fc99324b9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = USES_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
-   value = i915_modparams.semaphores;
+   value = HAS_LEGACY_SEMAPHORES(dev_priv);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
@@ -1066,11 +1066,6 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915_modparams.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-   DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-yesno(i915_modparams.semaphores));
-
intel_uc_sanitize_options(dev_priv);
 
intel_gvt_sanitize_options(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953867d9171e..24ce5d89e07e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3140,6 +3140,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_BLT(dev_priv)  HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
 
+#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
+
 #define HAS_LLC(dev_priv)  ((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)((dev_priv)->info.has_snoop)
 #define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
@@ -3303,8 +3305,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d53bb8e872ba..792e6dc7e19b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
-{
-   if (!IS_GEN7(dev_priv))
-   return false;
-
-   if (value >= 0)
-   return value;
-
-   return true;
-}
-
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0704d9af261b..6ca56e482d79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
-   (i915_modparams.semaphores && IS_GEN7(dev_priv)) ?
+   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d61c1787c164..3328147b4863 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(semaphores, int, 0400,
-   "Use semaphores for inter-ring sync "
-   "(default: -1 (use per-chip defaults))");
-
 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE 
(rev2)
URL   : https://patchwork.freedesktop.org/series/34044/
State : success

== Summary ==

Series 34044v2 drm/i915/execlists: Listen to COMPLETE context event not 
ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34044/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103163
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:459s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:386s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:280s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:512s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:500s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:486s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:437s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:436s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:425s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:474s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:533s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:576s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:550s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:516s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:465s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:558s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:424s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:610s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:549s
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:501s

72ffd011e980c8131f0c63e08c576d09977a2c54 drm-tip: 2017y-11m-17d-18h-38m-47s UTC 
integration manifest
2f6712f09a72 drm/i915/execlists: Listen to COMPLETE context event not 
ACTIVE_IDLE

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7184/
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[Intel-gfx] [CI 7/9] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Chris Wilson]

As the semaphores is just part of the engine, include it with the
general pretty printer universally used for debugging.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 32 
 drivers/gpu/drm/i915/intel_engine_cs.c |  9 +
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cef1463d411..41d49a4d25d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_semaphore_status(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   int num_rings = INTEL_INFO(dev_priv)->num_rings;
-   enum intel_engine_id id;
-   int j, ret;
-
-   if (!i915_modparams.semaphores) {
-   seq_puts(m, "Semaphores are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-   intel_runtime_pm_get(dev_priv);
-
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
-   return 0;
-}
-
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
-   {"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1fca7ac3b059..ef8e101ebd98 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
   I915_READ(RING_MI_MODE(engine->mmio_base)),
   I915_READ(RING_MI_MODE(engine->mmio_base)) & 
(MODE_IDLE) ? " [idle]" : "");
}
+   if (i915_modparams.semaphores) {
+   drm_printf(m, "\tSYNC_0: 0x%08x\n",
+  I915_READ(RING_SYNC_0(engine->mmio_base)));
+   drm_printf(m, "\tSYNC_1: 0x%08x\n",
+  I915_READ(RING_SYNC_1(engine->mmio_base)));
+   if (HAS_VEBOX(dev_priv))
+   drm_printf(m, "\tSYNC_2: 0x%08x\n",
+  I915_READ(RING_SYNC_2(engine->mmio_base)));
+   }
 
rcu_read_unlock();
 
-- 
2.15.0

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[Intel-gfx] [CI 1/9] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..768946741be5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
-- 
2.15.0

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[Intel-gfx] [CI 4/9] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Lionel Landwerlin  #i915_perf.c
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 70 -
 drivers/gpu/drm/i915/i915_drv.c |  8 +---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++
 drivers/gpu/drm/i915/i915_gem.c | 10 ++---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/i915_perf.c|  8 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/intel_gvt.c|  5 ---
 drivers/gpu/drm/i915/intel_lrc.c| 31 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 14 files changed, 20 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 0672178548ef..dac12c25f349 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915_modparams.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..5e2a6e18771f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915_modparams.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->contexts.list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
-   {"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_forcewake_domains", i915_forcewake_domains, 0},

[Intel-gfx] [CI 6/9] drm/i915: Disable semaphores on Sandybridge

[Chris Wilson]

I should have admitted defeat long ago as there has been a rare but
persistent error on Sandybridge where semaphore signaling did not
propagate to the waiter, leading to a GPU hang.

With the work on fence signaling for v4.9, the impact of using CPU driven
signaling was greatly reduced wrt to the latency of GPU semaphores,
though without logical rings support, the benefit of reordering work to
avoid bubbles is not realised (i.e. as it stands fence signaling is just
a slower, more costly version of HW semaphores; but works more
consistently). As a rough indicator of the difference,

with semaphores:
Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 
4.988us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 
4.923us]

In comparison, v3.4:
with semaphores:
Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 
11.842us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 
11.839us]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen = 0)
return value;
 
-   /* Enable semaphores on SNB when IO remapping is off */
-   if (IS_GEN6(dev_priv) && intel_vtd_active())
-   return false;
-
return true;
 }
 
-- 
2.15.0

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[Intel-gfx] [CI 9/9] drm/i915: Unwind incomplete legacy context switches

[Chris Wilson]

The legacy context switch for ringbuffer submission is multistaged,
where each of those stages may fail. However, we were updating global
state after some stages, and so we had to force the incomplete request
to be submitted because we could not unwind. Save the global state
before performing the switches, and so enable us to unwind back to the
previous global state should any phase fail. We then must cancel the
request instead of submitting it should the construction fail.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 168 ++--
 drivers/gpu/drm/i915/i915_gem_request.c |  18 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 4 files changed, 62 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6ca56e482d79..f63bec08cc85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
for_each_engine(engine, dev_priv, id) {
engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
 
if (!engine->last_retired_context)
continue;
@@ -681,68 +682,48 @@ static int remap_l3(struct drm_i915_gem_request *req, int 
slice)
return 0;
 }
 
-static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
-  struct intel_engine_cs *engine,
-  struct i915_gem_context *to)
-{
-   if (to->remap_slice)
-   return false;
-
-   if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   return to == engine->legacy_active_context;
-}
-
-static bool
-needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
-{
-   struct i915_gem_context *from = engine->legacy_active_context;
-
-   if (!ppgtt)
-   return false;
-
-   /* Always load the ppgtt on first use */
-   if (!from)
-   return true;
-
-   /* Same context without new entries, skip */
-   if ((!from->ppgtt || from->ppgtt == ppgtt) &&
-   !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   if (engine->id != RCS)
-   return true;
-
-   return true;
-}
-
-static int do_rcs_switch(struct drm_i915_gem_request *req)
+/**
+ * i915_switch_context() - perform a GPU context switch.
+ * @rq: request for which we'll execute the context switch
+ *
+ * The context life cycle is simple. The context refcount is incremented and
+ * decremented by 1 and create and destroy. If the context is in use by the 
GPU,
+ * it will have a refcount > 1. This allows us to destroy the context abstract
+ * object while letting the normal object tracking destroy the backing BO.
+ *
+ * This function should not be used in execlists mode.  Instead the context is
+ * switched by writing to the ELSP and requests keep a reference to their
+ * context.
+ */
+int i915_switch_context(struct drm_i915_gem_request *rq)
 {
-   struct i915_gem_context *to = req->ctx;
-   struct intel_engine_cs *engine = req->engine;
-   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
-   struct i915_gem_context *from = engine->legacy_active_context;
-   u32 hw_flags;
+   struct intel_engine_cs *engine = rq->engine;
+   struct i915_gem_context *to = rq->ctx;
+   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
+   struct i915_gem_context *saved_ctx = engine->legacy_active_context;
+   struct i915_hw_ppgtt *saved_mm = engine->legacy_active_ppgtt;
+   u32 hw_flags = 0;
int ret, i;
 
-   GEM_BUG_ON(engine->id != RCS);
-
-   if (skip_rcs_switch(ppgtt, engine, to))
-   return 0;
+   lockdep_assert_held(>i915->drm.struct_mutex);
+   GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
-   if (needs_pd_load_pre(ppgtt, engine)) {
-   /* Older GENs and non render rings still want the load first,
-* "PP_DCLV followed by PP_DIR_BASE register through Load
-* Register Immediate commands in Ring Buffer before submitting
-* a context."*/
+   if (ppgtt != saved_mm ||
+   (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) {
trace_switch_mm(engine, to);
-   ret = ppgtt->switch_mm(ppgtt, req);
+   ret = ppgtt->switch_mm(ppgtt, rq);
if (ret)
-   return ret;
+   goto err;
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   engine->legacy_active_ppgtt = ppgtt;
+   hw_flags = 

[Intel-gfx] [CI 3/9] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 2/9] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34044/
State : success

== Summary ==

Series 34044v1 drm/i915/execlists: Listen to COMPLETE context event not 
ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34044/revisions/1/mbox/

Test gem_exec_reloc:
Subgroup basic-gtt-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +1
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-gdg-551) fdo#102618
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:447s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:505s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:507s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:497s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:488s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:175  dwarn:1   dfail:0   fail:4   skip:109 
time:274s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:427s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:487s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:530s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:574s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:550s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:523s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:462s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:567s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:427s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:613s
fi-cnl-y total:218  pass:197  dwarn:0   dfail:0   fail:0   skip:20 
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:495s

72ffd011e980c8131f0c63e08c576d09977a2c54 drm-tip: 2017y-11m-17d-18h-38m-47s UTC 
integration manifest
9ee54aa8f598 drm/i915/execlists: Listen to COMPLETE context event not 
ACTIVE_IDLE

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7183/
___
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[Intel-gfx] [PATCH v2] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..768946741be5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
-- 
2.15.0

___
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Quoting Michel Thierry (2017-11-18 00:53:57)
> On 11/17/2017 4:31 PM, Chris Wilson wrote:
> > Since its inception, execlists has listened to (ACTIVE_IDLE |
> > ELEMENT_SWITCH) for detecting when one context completed and it either
> > continued onto the next (in port 1) or idled. We would always see
> > COMPLETE | ACTIVE_IDLE on the final context-switch event, but on recent
> > gen it appears that we now get separate ACTIVE_IDLE and COMPLETE events.
> > In particular, the ACTIVE_IDLE events may not be coupled to a context
> > (since it is a general state rather than a specific context completion
> > event).
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > Cc: Tvrtko Ursulin 
> > Cc: Joonas Lahtinen 
> > Cc: Michal Winiarski 
> > Cc: Michel Thierry 
> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index be6c39adebdf..768946741be5 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -154,7 +154,7 @@
> >   #define GEN8_CTX_STATUS_LITE_RESTORE(1 << 15)
> >   
> >   #define GEN8_CTX_STATUS_COMPLETED_MASK \
> > -  (GEN8_CTX_STATUS_ACTIVE_IDLE | \
> > +  (GEN8_CTX_STATUS_COMPLETE | \
> > GEN8_CTX_STATUS_PREEMPTED | \
> > GEN8_CTX_STATUS_ELEMENT_SWITCH)
> >   
> > 
> 
> Long long time ago we also looked at GEN8_CTX_STATUS_COMPLETE.
> I don't know about these 'recent' gens, but this change shouldn't make 
> things worse.

My mistake, yes originally it was COMPLETE then 

commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

did the s/COMPLETE/ACTIVE_IDLE | ELEMENT_SWITCH/
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Michel Thierry]

On 11/17/2017 4:31 PM, Chris Wilson wrote:

Since its inception, execlists has listened to (ACTIVE_IDLE |
ELEMENT_SWITCH) for detecting when one context completed and it either
continued onto the next (in port 1) or idled. We would always see
COMPLETE | ACTIVE_IDLE on the final context-switch event, but on recent
gen it appears that we now get separate ACTIVE_IDLE and COMPLETE events.
In particular, the ACTIVE_IDLE events may not be coupled to a context
(since it is a general state rather than a specific context completion
event).

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
---
  drivers/gpu/drm/i915/intel_lrc.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..768946741be5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
  #define GEN8_CTX_STATUS_LITE_RESTORE  (1 << 15)
  
  #define GEN8_CTX_STATUS_COMPLETED_MASK \

-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
  



Long long time ago we also looked at GEN8_CTX_STATUS_COMPLETE.
I don't know about these 'recent' gens, but this change shouldn't make 
things worse.


Acked-by: Michel Thierry 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lrc: Stop writing to ELSP until HW has processed the previous write

[Patchwork]

== Series Details ==

Series: drm/i915/lrc: Stop writing to ELSP until HW has processed the previous 
write
URL   : https://patchwork.freedesktop.org/series/34043/
State : success

== Summary ==

Series 34043v1 drm/i915/lrc: Stop writing to ELSP until HW has processed the 
previous write
https://patchwork.freedesktop.org/api/1.0/series/34043/revisions/1/mbox/

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:549s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:279s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:542s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:545s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:488s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:581s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:435s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:430s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:495s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:525s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:588s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:531s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:573s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:579s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:605s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:568s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:539s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:513s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:427s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:650s
fi-cnl-y total:241  pass:216  dwarn:0   dfail:0   fail:0   skip:24 
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:533s

72ffd011e980c8131f0c63e08c576d09977a2c54 drm-tip: 2017y-11m-17d-18h-38m-47s UTC 
integration manifest
1012245361ae drm/i915/lrc: Stop writing to ELSP until HW has processed the 
previous write

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7182/
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Re: [Intel-gfx] [PATCH i-g-t 4/4] tests: Rename chamelium to kms_chamelium.

[Lyude Paul]

Reviewed-by: Lyude Paul 

On Thu, 2017-11-16 at 13:45 +0100, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst 
> ---
>  tests/Makefile.am  |  6 +++---
>  tests/intel-ci/fast-feedback.testlist  | 18 +-
>  tests/{chamelium.c => kms_chamelium.c} |  0
>  tests/meson.build  |  2 +-
>  4 files changed, 13 insertions(+), 13 deletions(-)
>  rename tests/{chamelium.c => kms_chamelium.c} (100%)
> 
> diff --git a/tests/Makefile.am b/tests/Makefile.am
> index 89a970153992..db360523dad6 100644
> --- a/tests/Makefile.am
> +++ b/tests/Makefile.am
> @@ -16,7 +16,7 @@ endif
>  
>  if HAVE_CHAMELIUM
>  TESTS_progs += \
> - chamelium \
> + kms_chamelium \
>   $(NULL)
>  endif
>  
> @@ -153,8 +153,8 @@ vc4_wait_bo_LDADD = $(LDADD) $(DRM_VC4_LIBS)
>  vc4_wait_seqno_CFLAGS = $(AM_CFLAGS) $(DRM_VC4_CFLAGS)
>  vc4_wait_seqno_LDADD = $(LDADD) $(DRM_VC4_LIBS)
>  
> -chamelium_CFLAGS = $(AM_CFLAGS) $(XMLRPC_CFLAGS) $(LIBUDEV_CFLAGS)
> -chamelium_LDADD = $(LDADD) $(XMLRPC_LIBS) $(LIBUDEV_LIBS)
> +kms_chamelium_CFLAGS = $(AM_CFLAGS) $(XMLRPC_CFLAGS) $(LIBUDEV_CFLAGS)
> +kms_chamelium_LDADD = $(LDADD) $(XMLRPC_LIBS) $(LIBUDEV_LIBS)
>  
>  audio_CFLAGS = $(AM_CFLAGS) $(ALSA_CFLAGS)
>  audio_LDADD = $(LDADD) $(ALSA_LIBS)
> diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-
> feedback.testlist
> index bf8c1e663801..f74da743ce88 100644
> --- a/tests/intel-ci/fast-feedback.testlist
> +++ b/tests/intel-ci/fast-feedback.testlist
> @@ -1,14 +1,5 @@
>  # Keep alphabetically sorted by default
>  
> -igt@chamelium@dp-hpd-fast
> -igt@chamelium@dp-edid-read
> -igt@chamelium@dp-crc-fast
> -igt@chamelium@hdmi-hpd-fast
> -igt@chamelium@hdmi-edid-read
> -igt@chamelium@hdmi-crc-fast
> -igt@chamelium@vga-hpd-fast
> -igt@chamelium@vga-edid-read
> -igt@chamelium@common-hpd-after-suspend
>  igt@core_auth@basic-auth
>  igt@core_prop_blob@basic
>  igt@debugfs_test@read_all_entries
> @@ -208,6 +199,15 @@ igt@kms_addfb_basic@unused-pitches
>  igt@kms_busy@basic-flip-a
>  igt@kms_busy@basic-flip-b
>  igt@kms_busy@basic-flip-c
> +igt@kms_chamelium@dp-hpd-fast
> +igt@kms_chamelium@dp-edid-read
> +igt@kms_chamelium@dp-crc-fast
> +igt@kms_chamelium@hdmi-hpd-fast
> +igt@kms_chamelium@hdmi-edid-read
> +igt@kms_chamelium@hdmi-crc-fast
> +igt@kms_chamelium@vga-hpd-fast
> +igt@kms_chamelium@vga-edid-read
> +igt@kms_chamelium@common-hpd-after-suspend
>  igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic
>  igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy
>  igt@kms_cursor_legacy@basic-flip-after-cursor-atomic
> diff --git a/tests/chamelium.c b/tests/kms_chamelium.c
> similarity index 100%
> rename from tests/chamelium.c
> rename to tests/kms_chamelium.c
> diff --git a/tests/meson.build b/tests/meson.build
> index c3d5372f78ac..20ff79dcb15f 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -251,7 +251,7 @@ endif
>  
>  if chamelium.found()
>   test_progs += [
> - 'chamelium',
> + 'kms_chamelium',
>   ]
>   test_deps += chamelium
>  endif
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Re: [Intel-gfx] [PATCH] drm/i915/lrc: Stop writing to ELSP until HW has processed the previous write

[Chris Wilson]

Quoting Michel Thierry (2017-11-18 00:30:38)
> The hardware needs some time to process the information received in the
> ExecList Submission Port, and expects us to don't write anything new until
> it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
> PREEMPTED CSB event.
> 
> If we do not follow this, the driver could write new data into the ELSP
> before HW had finishing fetching the previous one, putting us in
> 'undefined behaviour' space.
> 
> This seems to be the problem causing the spurious PREEMPTED & COMPLETE
> events after a COMPLETE like the one below:
> 
> [] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
> [] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
> [] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
> [] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
> [] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
> [] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
> [] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006
> 
> The ELSP writes that lead to this CSB sequence show that the HW hadn't
> started executing the previous execlist (the one with only ctx 0x6) by the
> time the new one was submitted; this is a bit more clear in the data
> show in the EXECLIST_STATUS register at the time of the ELSP write.
> 
> [] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
> [] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302
> 
> [] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
> [] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308
> 
> Note that having to wait for this ack does not disable lite-restores,
> although it may reduce their numbers.
> 
> And take this as a RFC, since there are probably better ways to still
> respect this HW requirement.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
> Signed-off-by: Michel Thierry 
> Cc: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c| 16 +++-
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  6 ++
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index af41165e3da4..10b7eb64f169 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -449,11 +449,16 @@ static inline void elsp_write(u64 desc, u32 __iomem 
> *elsp)
>  
>  static void execlists_submit_ports(struct intel_engine_cs *engine)
>  {
> +   struct intel_engine_execlists * const execlists = >execlists;
> struct execlist_port *port = engine->execlists.port;
> u32 __iomem *elsp =
> engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> unsigned int n;
>  
> +   if (wait_for_atomic(!READ_ONCE(execlists->outstanding_submission), 
> 10))
> +   GEM_TRACE("%s outstanding submission stuck\n",
> + engine->name);

That can never succeed. Processing events and submitting ports is
serialised to the same thread. All the READ_ONCE/WRITE_ONCE are
incorrect.

I actually did try tracking something like this; the problem is that we
do not always get the IDLE_ACTIVE indicator so actually tracking when
the hw is awake is tricky.
-Chris
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[Intel-gfx] [RFC 1/2] drm/i915: Extend GuC action fast spin time

[John . C . Harrison]

From: John Harrison 

The 'request pre-emption' GuC command seems to be slower than other
commands. It typically takes 20-30us on a GP-MRB system (BXT). That
means that the super-fast busy-spin wait in the GuC send action code
hits the 10us time out. It then drops through to the more system
friendly sleeping wait with a 10ms timeout. Unfortunately, the
sleeping wait seems to average a 1.5ms delay. That is almost 100 times
slower than necessary! It also means that the super-high-priority
pre-emption request is getting a significant extra latency. Even
worse, the latency can be upwards of 8ms if the kernel decides not to
reschedule the i915 driver soon beause the system is busy doing other
things.

This patch extends the busy-spin wait timeout specifically for the
case of pre-emtion requests.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 12 ++--
 drivers/gpu/drm/i915/intel_guc_log.c   |  6 +++---
 drivers/gpu/drm/i915/intel_huc.c   |  2 +-
 drivers/gpu/drm/i915/intel_uc.c| 18 ++
 drivers/gpu/drm/i915/intel_uc.h|  2 +-
 5 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 918cedcef104..ff82f0561ec1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,7 +78,7 @@ static int guc_allocate_doorbell(struct intel_guc *guc,
client->ctx_index
};
 
-   return intel_guc_send(guc, action, ARRAY_SIZE(action));
+   return intel_guc_send(guc, action, ARRAY_SIZE(action), false);
 }
 
 static int guc_release_doorbell(struct intel_guc *guc,
@@ -89,7 +89,7 @@ static int guc_release_doorbell(struct intel_guc *guc,
client->ctx_index
};
 
-   return intel_guc_send(guc, action, ARRAY_SIZE(action));
+   return intel_guc_send(guc, action, ARRAY_SIZE(action), false);
 }
 
 static struct guc_context_desc *__get_context_desc(struct i915_guc_client 
*client)
@@ -605,7 +605,7 @@ static int i915_guc_preempt(struct intel_engine_cs *engine)
data[5] = guc->execbuf_client->ctx_index;
data[6] = guc->shared_data_offset;
 
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
+   return intel_guc_send(guc, data, ARRAY_SIZE(data), true);
 }
 
 /**
@@ -1442,7 +1442,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
/* first page of default ctx is shared data with GuC */
data[2] = guc->shared_data_offset;
 
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
+   return intel_guc_send(guc, data, ARRAY_SIZE(data), false);
 }
 
 
@@ -1466,7 +1466,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
/* first page of default ctx is shared data with GuC */
data[2] = guc->shared_data_offset;
 
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
+   return intel_guc_send(guc, data, ARRAY_SIZE(data), false);
 }
 
 int i915_guc_reset_engine(struct intel_engine_cs *engine)
@@ -1493,5 +1493,5 @@ int i915_guc_reset_engine(struct intel_engine_cs *engine)
/* first page is shared data with GuC */
data[6] = guc_ggtt_offset(ctx->engine[RCS].state);
 
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
+   return intel_guc_send(guc, data, ARRAY_SIZE(data), false);
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 0a4dd4454adf..95fd4e1ace41 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -43,7 +43,7 @@ static int guc_log_flush_complete(struct intel_guc *guc)
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
};
 
-   return intel_guc_send(guc, action, ARRAY_SIZE(action));
+   return intel_guc_send(guc, action, ARRAY_SIZE(action), false);
 }
 
 static int guc_log_flush(struct intel_guc *guc)
@@ -53,7 +53,7 @@ static int guc_log_flush(struct intel_guc *guc)
0
};
 
-   return intel_guc_send(guc, action, ARRAY_SIZE(action));
+   return intel_guc_send(guc, action, ARRAY_SIZE(action), false);
 }
 
 static int guc_log_control(struct intel_guc *guc, u32 control_val)
@@ -63,7 +63,7 @@ static int guc_log_control(struct intel_guc *guc, u32 
control_val)
control_val
};
 
-   return intel_guc_send(guc, action, ARRAY_SIZE(action));
+   return intel_guc_send(guc, action, ARRAY_SIZE(action), false);
 }
 
 
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 80c262fd56ab..e78bca7fd074 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -314,7 +314,7 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
 
-  

[Intel-gfx] [RFC 0/2] Excessive latency in GuC send action

[John . C . Harrison]

From: John Harrison 

While working on a customer project, it was noticed that the time
taken to issue a pre-emption request to the GuC would vary quite
significantly. The correct case was low microseconds but the worst
case was tens of milliseconds. Two separate issues were identified as
causing this extra delay. The acquisition of the GuC send mutex lock
and the stall waiting for an ack from the GuC. Both of these are
necessary steps because the access to the send action mechanism must
be serialised. It is not designed for multiple concurrent operations.

Mutex Lock Delay:
The first issue seems to be with the way mutex_lock() itself is
implemented in the linux kernel. Even when the lock is available, it
seems that linux sometimes decides to do a task switch anyway and not
re-schedule the thread that requested the lock for some time. Hence
the time taken to acquire the mutex lock would generally be
essentially zero but in around 0.05% of cases it would be in the
6-10ms range. Note that there was never any actual contention of the
mutex observed. In all cases, the mutex was available.

The workaround implemented for the customer was to first use a
mutex_trylock(). If the try fails then it falls back to the regular
mutex_lock() call instead. As the try lock is not permitted to stall,
it never hits the random linux task switch issue. Running overnight,
3.2 million pre-emption events were logged with not a single mutex
delay over 10 microseconds (which was the granularity of the
measurement being used).

Ack Delay:
The second issue was with the wait for the GuC acknowledgment of the
send action command. In most cases, no delay is required - the
completion flag is set by the time of the first read. However, around
1% of the time the flag was not set and the wait_for() loop then took
in the region of 8-10ms to return. Analysis showed that this delay was
also entirely due to the linux kernel task switching away due to using
a sleeping wait in the polling loop. Using a non-sleeping wait brought
the latency down to the 10-20us range in the majority of 'slow' cases.
Certain tests had a noticeable spike of about 120us, presumably when
the delay was actually due to the GuC being busy. The worse extremes
measured were around 200us, with maybe one or two hits of 300us in an
overnight run.

The polling construct being used was a 'wait_for_us()' of 10
microseconds (spinning poll) followed by a 'wait_for()' of 10ms
(sleeping poll) with the final fall back being to give up and return
an error. As the command quite frequently takes just over 10us to
complete, this meant the code would regularly drop into the second
loop. Despite the sleep time being set for 1ms, it would actually
sleep for an average of 1.5ms and as noted would commonly hit closer
to 10ms.

The workaround was to extend the busy poll period to 100us in the case
of a pre-emption request. In the case of any other GuC send action
command, the original 10us was kept. The reasoning being that a
pre-emption request is a very high priority, urgent thing and is worth
burning the extra CPU cycles on a busy poll in order to guarantee a
suitably small latency. Whereas, the other send action commands are
not performance critical and a longer but more system friendly sleep
is not an issue.


Note that the two patches included here are based against the
customer's 4.11 tree. So they might not apply too well the current
upstream pre-emption implementation. It was noted that a recent update
to the gem_exec_latency IGT showed "additional latency in the mutex
for guc preemption". Which sounds like the same issue that was seen
here. Hence posting what I have to a wider audience.

John Harrison (2):
  drm/i915: Extend GuC action fast spin time
  drm/i915: Avoid stalling on GuC send mutex lock

 drivers/gpu/drm/i915/i915_guc_submission.c | 12 ++--
 drivers/gpu/drm/i915/intel_guc_log.c   |  6 +++---
 drivers/gpu/drm/i915/intel_huc.c   |  2 +-
 drivers/gpu/drm/i915/intel_uc.c| 23 ++-
 drivers/gpu/drm/i915/intel_uc.h|  2 +-
 5 files changed, 29 insertions(+), 16 deletions(-)

-- 
2.13.0

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[Intel-gfx] [RFC 2/2] drm/i915: Avoid stalling on GuC send mutex lock

[John . C . Harrison]

From: John Harrison 

There is a mutex_lock in the GuC send action code path to ensure
serialised access to the host-to-GuC mechanism. Acquiring the lock
apparently sees random stalls of around 6ms. That is even when the
lock is definitely not acquired by any other thread. In the case of
sending pre-emption requests, a 6ms delay can really damage
performance of the high priority task requiring pre-emption.

It seems that using a mutex_trylock call first prevents this delay
from occurring.

Without the trylock, one particular test showed about one stall hit
for every 1,500 pre-emption requests. With the trylock, no stalls in
3,200,000 pre-emptions.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/intel_uc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 680290ac36d6..e38eceb456c5 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -54,7 +54,10 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action, 
u32 len, bool urgen
if (WARN_ON(len < 1 || len > 15))
return -EINVAL;
 
-   mutex_lock(>send_mutex);
+   /* Use a trylock first to avoid a ~6ms random stall when
+* calling mutex_lock() directly!? */
+   if (!mutex_trylock(>send_mutex))
+   mutex_lock(>send_mutex);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
dev_priv->guc.action_count += 1;
-- 
2.13.0

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[Intel-gfx] [PATCH] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since its inception, execlists has listened to (ACTIVE_IDLE |
ELEMENT_SWITCH) for detecting when one context completed and it either
continued onto the next (in port 1) or idled. We would always see
COMPLETE | ACTIVE_IDLE on the final context-switch event, but on recent
gen it appears that we now get separate ACTIVE_IDLE and COMPLETE events.
In particular, the ACTIVE_IDLE events may not be coupled to a context
(since it is a general state rather than a specific context completion
event).

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..768946741be5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
-- 
2.15.0

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[Intel-gfx] [PATCH] drm/i915/lrc: Stop writing to ELSP until HW has processed the previous write

[Michel Thierry]

The hardware needs some time to process the information received in the
ExecList Submission Port, and expects us to don't write anything new until
it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
PREEMPTED CSB event.

If we do not follow this, the driver could write new data into the ELSP
before HW had finishing fetching the previous one, putting us in
'undefined behaviour' space.

This seems to be the problem causing the spurious PREEMPTED & COMPLETE
events after a COMPLETE like the one below:

[] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
[] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
[] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
[] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
[] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
[] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
[] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006

The ELSP writes that lead to this CSB sequence show that the HW hadn't
started executing the previous execlist (the one with only ctx 0x6) by the
time the new one was submitted; this is a bit more clear in the data
show in the EXECLIST_STATUS register at the time of the ELSP write.

[] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
[] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302

[] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
[] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308

Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.

And take this as a RFC, since there are probably better ways to still
respect this HW requirement.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Michel Thierry 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c| 16 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h |  6 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index af41165e3da4..10b7eb64f169 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -449,11 +449,16 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp)
 
 static void execlists_submit_ports(struct intel_engine_cs *engine)
 {
+   struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = engine->execlists.port;
u32 __iomem *elsp =
engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
unsigned int n;
 
+   if (wait_for_atomic(!READ_ONCE(execlists->outstanding_submission), 10))
+   GEM_TRACE("%s outstanding submission stuck\n",
+ engine->name);
+
for (n = execlists_num_ports(>execlists); n--; ) {
struct drm_i915_gem_request *rq;
unsigned int count;
@@ -479,6 +484,8 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
elsp_write(desc, elsp);
}
+
+   WRITE_ONCE(execlists->outstanding_submission, 1);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -889,6 +896,11 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n",
  engine->name, head,
  status, buf[2*head + 1]);
+
+   if ((status & GEN8_CTX_STATUS_IDLE_ACTIVE) ||
+   (status & GEN8_CTX_STATUS_PREEMPTED))
+   WRITE_ONCE(execlists->outstanding_submission, 
0);
+
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
@@ -944,9 +956,11 @@ static void execlists_submission_tasklet(unsigned long 
data)
/* After the final element, the hw should be idle */
GEM_BUG_ON(port_count(port) == 0 &&
   !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
-   if (port_count(port) == 0)
+   if (port_count(port) == 0) {
execlists_clear_active(execlists,
   EXECLISTS_ACTIVE_USER);
+   WRITE_ONCE(execlists->outstanding_submission, 
0);
+   }
}
 
if (head != execlists->csb_head) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e5c62f8ef0da..2c8e1a74c266 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -288,6 +288,12 @@ struct intel_engine_execlists {
 * @csb_use_mmio: access csb through mmio, instead of hwsp
 */
bool csb_use_mmio;
+
+   /**

Re: [Intel-gfx] [PATCH i-g-t 2/4] lib/igt_kms: Make igt_output_from_connector probe all outputs

[Lyude Paul]

Reviewed-by: Lyude Paul 

On Thu, 2017-11-16 at 13:45 +0100, Maarten Lankhorst wrote:
> igt_output_from_connector should be used for disconnected outputs
> too, this is useful for chamelium testing, where disconnected outputs
> may reappear.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  lib/igt_kms.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 239f4f17d22e..fe0ef2bd6f38 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -1884,9 +1884,13 @@ igt_output_t *igt_output_from_connector(igt_display_t
> *display,
>   drmModeConnector *connector)
>  {
>   igt_output_t *output, *found = NULL;
> + int i;
> +
> + for (i = 0; i < display->n_outputs; i++) {
> + output = >outputs[i];
>  
> - for_each_connected_output(display, output) {
> - if (output->config.connector->connector_id ==
> + if (output->config.connector &&
> + output->config.connector->connector_id ==
>   connector->connector_id) {
>   found = output;
>   break;
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Re: [Intel-gfx] [PATCH i-g-t 3/4] tests/chamelium: Only initialize igt_display once

[Lyude Paul]

Reviewed-by: Lyude Paul 

On Thu, 2017-11-16 at 13:45 +0100, Maarten Lankhorst wrote:
> Instead of first calling kmstest_unset_all_crtcs, and calling
> igt_display_init for each test, use igt_display_reset to reset
> igt_display between tests, and use atomic commit to disable all
> unused crtcs in enable_output().
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  tests/chamelium.c | 45 -
>  1 file changed, 12 insertions(+), 33 deletions(-)
> 
> diff --git a/tests/chamelium.c b/tests/chamelium.c
> index d4a185e76873..8855a8300049 100644
> --- a/tests/chamelium.c
> +++ b/tests/chamelium.c
> @@ -33,6 +33,7 @@
>  typedef struct {
>   struct chamelium *chamelium;
>   struct chamelium_port **ports;
> + igt_display_t display;
>   int port_count;
>  
>   int drm_fd;
> @@ -409,9 +410,9 @@ test_suspend_resume_edid_change(data_t *data, struct
> chamelium_port *port,
>  
>  static igt_output_t *
>  prepare_output(data_t *data,
> -igt_display_t *display,
>  struct chamelium_port *port)
>  {
> + igt_display_t *display = >display;
>   igt_output_t *output;
>   drmModeRes *res;
>   drmModeConnector *connector =
> @@ -420,7 +421,6 @@ prepare_output(data_t *data,
>   bool found = false;
>  
>   igt_assert(res = drmModeGetResources(data->drm_fd));
> - kmstest_unset_all_crtcs(data->drm_fd, res);
>  
>   /* The chamelium's default EDID has a lot of resolutions, way more
> then
>* we need to test
> @@ -430,11 +430,9 @@ prepare_output(data_t *data,
>   chamelium_plug(data->chamelium, port);
>   wait_for_connector(data, port, DRM_MODE_CONNECTED);
>  
> - igt_display_init(display, data->drm_fd);
> - output = igt_output_from_connector(display, connector);
> + igt_display_reset(display);
>  
> - igt_assert(kmstest_probe_connector_config(
> - data->drm_fd, connector->connector_id, ~0, 
> >config));
> + output = igt_output_from_connector(display, connector);
>  
>   for_each_pipe(display, pipe) {
>   if (!igt_pipe_connector_valid(pipe, output))
> @@ -477,7 +475,7 @@ enable_output(data_t *data,
>   igt_pipe_obj_replace_prop_blob(primary->pipe, IGT_CRTC_GAMMA_LUT,
> NULL, 0);
>   igt_pipe_obj_replace_prop_blob(primary->pipe, IGT_CRTC_CTM, NULL,
> 0);
>  
> - igt_display_commit(display);
> + igt_display_commit2(display, COMMIT_ATOMIC);
>  
>   if (chamelium_port_get_type(port) == DRM_MODE_CONNECTOR_VGA)
>   usleep(25);
> @@ -485,25 +483,10 @@ enable_output(data_t *data,
>   drmModeFreeConnector(connector);
>  }
>  
> -static void
> -disable_output(data_t *data,
> -struct chamelium_port *port,
> -igt_output_t *output)
> -{
> - igt_display_t *display = output->display;
> - igt_plane_t *primary = igt_output_get_plane_type(output,
> DRM_PLANE_TYPE_PRIMARY);
> - igt_assert(primary);
> -
> - /* Disable the display */
> - igt_plane_set_fb(primary, NULL);
> - igt_display_commit(display);
> -}
> -
>  static void
>  test_display_crc(data_t *data, struct chamelium_port *port, int count,
>bool fast)
>  {
> - igt_display_t display;
>   igt_output_t *output;
>   igt_plane_t *primary;
>   igt_crc_t *crc;
> @@ -517,7 +500,7 @@ test_display_crc(data_t *data, struct chamelium_port
> *port, int count,
>  
>   reset_state(data, port);
>  
> - output = prepare_output(data, , port);
> + output = prepare_output(data, port);
>   connector = chamelium_port_get_connector(data->chamelium, port,
> false);
>   primary = igt_output_get_plane_type(output,
> DRM_PLANE_TYPE_PRIMARY);
>   igt_assert(primary);
> @@ -561,18 +544,15 @@ test_display_crc(data_t *data, struct chamelium_port
> *port, int count,
>   free(expected_crc);
>   free(crc);
>  
> - disable_output(data, port, output);
>   igt_remove_fb(data->drm_fd, );
>   }
>  
>   drmModeFreeConnector(connector);
> - igt_display_fini();
>  }
>  
>  static void
>  test_display_frame_dump(data_t *data, struct chamelium_port *port)
>  {
> - igt_display_t display;
>   igt_output_t *output;
>   igt_plane_t *primary;
>   struct igt_fb fb;
> @@ -583,7 +563,7 @@ test_display_frame_dump(data_t *data, struct
> chamelium_port *port)
>  
>   reset_state(data, port);
>  
> - output = prepare_output(data, , port);
> + output = prepare_output(data, port);
>   connector = chamelium_port_get_connector(data->chamelium, port,
> false);
>   primary = igt_output_get_plane_type(output,
> DRM_PLANE_TYPE_PRIMARY);
>   igt_assert(primary);
> @@ -608,18 +588,15 @@ test_display_frame_dump(data_t *data, struct
> chamelium_port *port)
>   chamelium_destroy_frame_dump(frame);
>   }
>  
> - disable_output(data, port, output);
>

Re: [Intel-gfx] [PATCH i-g-t 1/4] lib/igt_kms: Add igt_display_reset function.

[Lyude Paul]

Reviewed-by: Lyude Paul 

On Thu, 2017-11-16 at 13:45 +0100, Maarten Lankhorst wrote:
> A lot of code duplicates this, but it should be handled in the core.
> Add it and use it after igt_display_init(), the tests have to be
> converted one by one.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  lib/igt_kms.c | 162 +
> -
>  lib/igt_kms.h |   1 +
>  2 files changed, 104 insertions(+), 59 deletions(-)
> 
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 1d26b8ddbf43..239f4f17d22e 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -1549,29 +1549,14 @@ static void igt_output_refresh(igt_output_t *output)
>  -1);
>   }
>  
> - if (output->config.connector) {
> + if (output->config.connector)
>   igt_atomic_fill_connector_props(display, output,
>   IGT_NUM_CONNECTOR_PROPS, igt_connector_prop_names);
>  
> - if (output->props[IGT_CONNECTOR_BROADCAST_RGB])
> - igt_output_set_prop_value(output,
> -   IGT_CONNECTOR_BROADCAST_R
> GB,
> -   BROADCAST_RGB_FULL);
> - }
> -
>   LOG(display, "%s: Selecting pipe %s\n", output->name,
>   kmstest_pipe_name(output->pending_pipe));
>  }
>  
> -static bool
> -get_plane_property(int drm_fd, uint32_t plane_id, const char *name,
> -uint32_t *prop_id /* out */, uint64_t *value /* out */,
> -drmModePropertyPtr *prop /* out */)
> -{
> - return kmstest_get_property(drm_fd, plane_id,
> DRM_MODE_OBJECT_PLANE,
> - name, prop_id, value, prop);
> -}
> -
>  static int
>  igt_plane_set_property(igt_plane_t *plane, uint32_t prop_id, uint64_t
> value)
>  {
> @@ -1582,15 +1567,6 @@ igt_plane_set_property(igt_plane_t *plane, uint32_t
> prop_id, uint64_t value)
>DRM_MODE_OBJECT_PLANE, prop_id, value);
>  }
>  
> -static bool
> -get_crtc_property(int drm_fd, uint32_t crtc_id, const char *name,
> -uint32_t *prop_id /* out */, uint64_t *value /* out */,
> -drmModePropertyPtr *prop /* out */)
> -{
> - return kmstest_get_property(drm_fd, crtc_id, DRM_MODE_OBJECT_CRTC,
> - name, prop_id, value, prop);
> -}
> -
>  /*
>   * Walk a plane's property list to determine its type.  If we don't
>   * find a type property, then the kernel doesn't support universal
> @@ -1601,14 +1577,110 @@ static int get_drm_plane_type(int drm_fd, uint32_t
> plane_id)
>   uint64_t value;
>   bool has_prop;
>  
> - has_prop = get_plane_property(drm_fd, plane_id, "type",
> -   NULL /* prop_id */, , NULL);
> + has_prop = kmstest_get_property(drm_fd, plane_id,
> DRM_MODE_OBJECT_PLANE,
> + "type", NULL, , NULL);
>   if (has_prop)
>   return (int)value;
>  
>   return DRM_PLANE_TYPE_OVERLAY;
>  }
>  
> +static void igt_plane_reset(igt_plane_t *plane)
> +{
> + /* Reset src coordinates. */
> + igt_plane_set_prop_value(plane, IGT_PLANE_SRC_X, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_SRC_Y, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_SRC_W, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_SRC_H, 0);
> +
> + /* Reset crtc coordinates. */
> + igt_plane_set_prop_value(plane, IGT_PLANE_CRTC_X, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_CRTC_Y, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_CRTC_W, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_CRTC_H, 0);
> +
> + /* Reset binding to fb and crtc. */
> + igt_plane_set_prop_value(plane, IGT_PLANE_FB_ID, 0);
> + igt_plane_set_prop_value(plane, IGT_PLANE_CRTC_ID, 0);
> +
> + /* Use default rotation */
> + if (igt_plane_has_prop(plane, IGT_PLANE_ROTATION))
> + igt_plane_set_prop_value(plane, IGT_PLANE_ROTATION,
> +  IGT_ROTATION_0);
> +
> + igt_plane_clear_prop_changed(plane, IGT_PLANE_IN_FENCE_FD);
> + plane->values[IGT_PLANE_IN_FENCE_FD] = ~0ULL;
> +}
> +
> +static void igt_pipe_reset(igt_pipe_t *pipe)
> +{
> + igt_pipe_obj_set_prop_value(pipe, IGT_CRTC_MODE_ID, 0);
> + igt_pipe_obj_set_prop_value(pipe, IGT_CRTC_ACTIVE, 0);
> + igt_pipe_obj_clear_prop_changed(pipe, IGT_CRTC_OUT_FENCE_PTR);
> +
> + pipe->out_fence_fd = -1;
> +}
> +
> +static void igt_output_reset(igt_output_t *output)
> +{
> + output->pending_pipe = PIPE_NONE;
> + output->use_override_mode = false;
> + memset(>override_mode, 0, sizeof(output->override_mode));
> +
> + igt_output_set_prop_value(output, IGT_CONNECTOR_CRTC_ID, 0);
> +
> + if (igt_output_has_prop(output, IGT_CONNECTOR_BROADCAST_RGB))
> + igt_output_set_prop_value(output,
> 

[Intel-gfx] Updated drm-intel-testing

[Rodrigo Vivi]

Hi all,

The following changes tagged drm-intel-testing-2017-11-17-2:

drm-intel-next-2017-11-17-1:

More change sets for 4.16:

- Many improvements for selftests and other igt tests (Chris)
- Forcewake with PUNIT->PMIC bus fixes and robustness (Hans)
- Define an engine class for uABI (Tvrtko)
- Context switch fixes and improvements (Chris)
- GT powersavings and power gating simplification and fixes (Chris)
- Other general driver clean-ups (Chris, Lucas, Ville)
- Removing old, useless and/or bad workarounds (Chris, Oscar, Radhakrishna)
- IPS, pipe config, etc in preparation for another Fast Boot attempt (Maarten)
- OA perf fixes and support to Coffee Lake and Cannonlake (Lionel)
- Fixes around GPU fault registers (Michel)
- GEM Proxy (Tina)
- Refactor of Geminilake and Cannonlake plane color handling (James)
- Generalize transcoder loop (Mika Kahola)
- New HW Workaround for Cannonlake and Geminilake (Rodrigo)
- Resume GuC before using GEM (Chris)
- Stolen Memory handling improvements (Ville)
- Initialize entry in PPAT for older compilers (Chris)
- Other fixes and robustness improvements on execbuf (Chris)
- Improve logs of GEM_BUG_ON (Mika Kuoppala)
- Rework with massive rename of GuC functions and files (Sagar)
- Don't sanitize frame start delay if pipe is off (Ville)
- Cannonlake clock fixes (Rodrigo)
- Cannonlake HDMI 2.0 support (Rodrigo)
- Add a GuC doorbells selftest (Michel)
- Add might_sleep() check to our wait_for() (Chris)

Many GVT changes for 4.16:

- CSB HWSP update support (Weinan)
- GVT debug helpers, dyndbg and debugfs (Chuanxiao, Shuo)
- full virtualized opregion (Xiaolin)
- VM health check for sane fallback (Fred)
- workload submission code refactor for future enabling (Zhi)
- Updated repo URL in MAINTAINERS (Zhenyu)
- other many misc fixes

Thanks,
Rodrigo.
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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 08:32:19PM +, Ville Syrjälä wrote:
> On Fri, Nov 17, 2017 at 12:12:15PM -0800, Rodrigo Vivi wrote:
> > On Fri, Nov 17, 2017 at 07:19:10PM +, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > Rename enum plane to enum i9xx_plane_id to make it clear that it only
> > > applies to pre-SKL platforms.
> > 
> > Oh! I should had read this before commenting on the cover letter... sorry...
> > 
> > Anyway I don't believe it make clear that it is not skl... because it means
> > it started on i9xx, but not that ended on skl... just "plane" was already
> > good enough imho... but it is really just a comment...
> > don't take this as a nack anyhow... ;)
> 
> I think our unwritten rule is that i9xx often refers to
> gen2/3/4, sometimes including g4x sometimes not, and sometimes
> even vlv/chv gets included.
> 
> And sometimes we just call things by the name i915 instead of
> i9xx, meaning gmch. But on other occasions i915 means just gen3,
> and i9xx means anything else gmch not otherwise named more
> specifically.
> 
> Got it? Good :)

hahaha I think so! :)

> 
> In this case that "pattern" is a bit more broken since here
> i9xx extends all the way to bdw.

I was wondering something like that...

> But it does match the fact that
> the primary plane functions are now called i9xx_plane_whatever().

oh! I see...

> 
> I think I need to include the cursor planes in the i9xx_plane_id
> soon enough, which will make it partially extend all the way to cnl
> and beyond. We really need to tell the hw people to redesign the
> cursor planes so that we have an excuse to split the code :P

in the hope that it wouldn't get it more fuzzy! :)

Thanks a lot for the explanation!

> 
> > 
> > > 
> > > enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> > > per-pipe. We need the old global identifier to index the primary plane
> > > (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> > > platforms.
> > > 
> > > v2: Reorder patches
> > > v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> > > Pimp the commit message a bit
> > > Note that i9xx_plane_id doesn't apply to SKL+
> > > v4: Rebase due to power domain handling in plane readout
> > > v5: Rebase due to crtc->dspaddr_offset removal
> > > v6: s/plane/i9xx_plane/ etc. (James)
> > > 
> > > Cc: James Ausmus 
> > > Cc: Daniel Vetter 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
> > >  drivers/gpu/drm/i915/intel_display.c | 98 
> > > ++--
> > >  drivers/gpu/drm/i915/intel_drv.h |  6 +--
> > >  drivers/gpu/drm/i915/intel_fbc.c | 12 ++---
> > >  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
> > >  5 files changed, 62 insertions(+), 62 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 2158a758a17d..55dd602582cb 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> > > transcoder)
> > >  
> > >  /*
> > >   * Global legacy plane identifier. Valid only for primary/sprite
> > > - * planes on pre-g4x, and only for primary planes on g4x+.
> > > + * planes on pre-g4x, and only for primary planes on g4x-bdw.
> > >   */
> > > -enum plane {
> > > +enum i9xx_plane_id {
> > >   PLANE_A,
> > >   PLANE_B,
> > >   PLANE_C,
> > > @@ -1145,7 +1145,7 @@ struct intel_fbc {
> > >  
> > >   struct {
> > >   enum pipe pipe;
> > > - enum plane plane;
> > > + enum i9xx_plane_id i9xx_plane;
> > >   unsigned int fence_y_offset;
> > >   } crtc;
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 91f74c5373b3..16ac86816f28 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct 
> > > intel_plane_state *plane_state)
> > >   return 0;
> > >  }
> > >  
> > > -static void i9xx_update_primary_plane(struct intel_plane *primary,
> > > -   const struct intel_crtc_state *crtc_state,
> > > -   const struct intel_plane_state 
> > > *plane_state)
> > > +static void i9xx_update_plane(struct intel_plane *plane,
> > > +   const struct intel_crtc_state *crtc_state,
> > > +   const struct intel_plane_state *plane_state)
> > >  {
> > > - struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >   const struct drm_framebuffer *fb = plane_state->base.fb;
> > > - enum plane plane = primary->plane;
> > > + enum i9xx_plane_id i9xx_plane = 

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Plane assert/readout cleanups etc. (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc. (rev9)
URL   : https://patchwork.freedesktop.org/series/31758/
State : warning

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test drv_module_reload:
Subgroup basic-no-display:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_plane:
Subgroup plane-panning-top-left-pipe-c-planes:
dmesg-fail -> PASS   (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-64x64-onscreen:
pass   -> SKIP   (shard-snb)
Test kms_flip:
Subgroup vblank-vs-modeset-suspend-interruptible:
pass   -> SKIP   (shard-snb)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707

shard-hswtotal:2585 pass:1472 dwarn:3   dfail:1   fail:10  skip:1099 
time:9406s
shard-snbtotal:2585 pass:1257 dwarn:1   dfail:1   fail:13  skip:1313 
time:7879s
Blacklisted hosts:
shard-apltotal:2563 pass:1601 dwarn:1   dfail:0   fail:24  skip:936 
time:12896s
shard-kbltotal:2565 pass:1701 dwarn:4   dfail:1   fail:26  skip:832 
time:10491s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7181/shards.html
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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[Ville Syrjälä]

On Fri, Nov 17, 2017 at 12:12:15PM -0800, Rodrigo Vivi wrote:
> On Fri, Nov 17, 2017 at 07:19:10PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Rename enum plane to enum i9xx_plane_id to make it clear that it only
> > applies to pre-SKL platforms.
> 
> Oh! I should had read this before commenting on the cover letter... sorry...
> 
> Anyway I don't believe it make clear that it is not skl... because it means
> it started on i9xx, but not that ended on skl... just "plane" was already
> good enough imho... but it is really just a comment...
> don't take this as a nack anyhow... ;)

I think our unwritten rule is that i9xx often refers to
gen2/3/4, sometimes including g4x sometimes not, and sometimes
even vlv/chv gets included.

And sometimes we just call things by the name i915 instead of
i9xx, meaning gmch. But on other occasions i915 means just gen3,
and i9xx means anything else gmch not otherwise named more
specifically.

Got it? Good :)

In this case that "pattern" is a bit more broken since here
i9xx extends all the way to bdw. But it does match the fact that
the primary plane functions are now called i9xx_plane_whatever().

I think I need to include the cursor planes in the i9xx_plane_id
soon enough, which will make it partially extend all the way to cnl
and beyond. We really need to tell the hw people to redesign the
cursor planes so that we have an excuse to split the code :P

> 
> > 
> > enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> > per-pipe. We need the old global identifier to index the primary plane
> > (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> > platforms.
> > 
> > v2: Reorder patches
> > v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> > Pimp the commit message a bit
> > Note that i9xx_plane_id doesn't apply to SKL+
> > v4: Rebase due to power domain handling in plane readout
> > v5: Rebase due to crtc->dspaddr_offset removal
> > v6: s/plane/i9xx_plane/ etc. (James)
> > 
> > Cc: James Ausmus 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
> >  drivers/gpu/drm/i915/intel_display.c | 98 
> > ++--
> >  drivers/gpu/drm/i915/intel_drv.h |  6 +--
> >  drivers/gpu/drm/i915/intel_fbc.c | 12 ++---
> >  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
> >  5 files changed, 62 insertions(+), 62 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 2158a758a17d..55dd602582cb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> > transcoder)
> >  
> >  /*
> >   * Global legacy plane identifier. Valid only for primary/sprite
> > - * planes on pre-g4x, and only for primary planes on g4x+.
> > + * planes on pre-g4x, and only for primary planes on g4x-bdw.
> >   */
> > -enum plane {
> > +enum i9xx_plane_id {
> > PLANE_A,
> > PLANE_B,
> > PLANE_C,
> > @@ -1145,7 +1145,7 @@ struct intel_fbc {
> >  
> > struct {
> > enum pipe pipe;
> > -   enum plane plane;
> > +   enum i9xx_plane_id i9xx_plane;
> > unsigned int fence_y_offset;
> > } crtc;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 91f74c5373b3..16ac86816f28 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct 
> > intel_plane_state *plane_state)
> > return 0;
> >  }
> >  
> > -static void i9xx_update_primary_plane(struct intel_plane *primary,
> > - const struct intel_crtc_state *crtc_state,
> > - const struct intel_plane_state 
> > *plane_state)
> > +static void i9xx_update_plane(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state,
> > + const struct intel_plane_state *plane_state)
> >  {
> > -   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > +   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > -   enum plane plane = primary->plane;
> > +   enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> > u32 linear_offset;
> > u32 dspcntr = plane_state->ctl;
> > -   i915_reg_t reg = DSPCNTR(plane);
> > +   i915_reg_t reg = DSPCNTR(i9xx_plane);
> > int x = plane_state->main.x;
> > int y = plane_state->main.y;
> > unsigned long irqflags;
> > @@ -3248,34 +3248,34 @@ static void i9xx_update_primary_plane(struct 
> > intel_plane *primary,
> > /* pipesrc and dspsize 

Re: [Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 07:19:10PM +, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Rename enum plane to enum i9xx_plane_id to make it clear that it only
> applies to pre-SKL platforms.

Oh! I should had read this before commenting on the cover letter... sorry...

Anyway I don't believe it make clear that it is not skl... because it means
it started on i9xx, but not that ended on skl... just "plane" was already
good enough imho... but it is really just a comment...
don't take this as a nack anyhow... ;)

> 
> enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> per-pipe. We need the old global identifier to index the primary plane
> (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> platforms.
> 
> v2: Reorder patches
> v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> Pimp the commit message a bit
> Note that i9xx_plane_id doesn't apply to SKL+
> v4: Rebase due to power domain handling in plane readout
> v5: Rebase due to crtc->dspaddr_offset removal
> v6: s/plane/i9xx_plane/ etc. (James)
> 
> Cc: James Ausmus 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
>  drivers/gpu/drm/i915/intel_display.c | 98 
> ++--
>  drivers/gpu/drm/i915/intel_drv.h |  6 +--
>  drivers/gpu/drm/i915/intel_fbc.c | 12 ++---
>  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
>  5 files changed, 62 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2158a758a17d..55dd602582cb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> transcoder)
>  
>  /*
>   * Global legacy plane identifier. Valid only for primary/sprite
> - * planes on pre-g4x, and only for primary planes on g4x+.
> + * planes on pre-g4x, and only for primary planes on g4x-bdw.
>   */
> -enum plane {
> +enum i9xx_plane_id {
>   PLANE_A,
>   PLANE_B,
>   PLANE_C,
> @@ -1145,7 +1145,7 @@ struct intel_fbc {
>  
>   struct {
>   enum pipe pipe;
> - enum plane plane;
> + enum i9xx_plane_id i9xx_plane;
>   unsigned int fence_y_offset;
>   } crtc;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 91f74c5373b3..16ac86816f28 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct intel_plane_state 
> *plane_state)
>   return 0;
>  }
>  
> -static void i9xx_update_primary_plane(struct intel_plane *primary,
> -   const struct intel_crtc_state *crtc_state,
> -   const struct intel_plane_state 
> *plane_state)
> +static void i9xx_update_plane(struct intel_plane *plane,
> +   const struct intel_crtc_state *crtc_state,
> +   const struct intel_plane_state *plane_state)
>  {
> - struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
> - enum plane plane = primary->plane;
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>   u32 linear_offset;
>   u32 dspcntr = plane_state->ctl;
> - i915_reg_t reg = DSPCNTR(plane);
> + i915_reg_t reg = DSPCNTR(i9xx_plane);
>   int x = plane_state->main.x;
>   int y = plane_state->main.y;
>   unsigned long irqflags;
> @@ -3248,34 +3248,34 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
>   /* pipesrc and dspsize control the size that is scaled from,
>* which should always be the user's requested size.
>*/
> - I915_WRITE_FW(DSPSIZE(plane),
> + I915_WRITE_FW(DSPSIZE(i9xx_plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> - I915_WRITE_FW(DSPPOS(plane), 0);
> - } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> - I915_WRITE_FW(PRIMSIZE(plane),
> + I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
> + } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + I915_WRITE_FW(PRIMSIZE(i9xx_plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> - I915_WRITE_FW(PRIMPOS(plane), 0);
> - I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
> + I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
> + 

Re: [Intel-gfx] [PATCH v3 00/10] drm/i915: Plane assert/readout cleanups etc.

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 07:19:07PM +, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> OK, one more time. This time with s/plane/i9xx_plane/ etc. all over.

why not intel_plane?!

> Maybe that will make everyone happy? Unlikely, but let's try.

:)

> 
> Patch 3 is the only one missing r-b.
> 
> Ville Syrjälä (10):
>   drm/i915: Add .get_hw_state() method for planes
>   drm/i915: Redo plane sanitation during readout
>   drm/i915: s/enum plane/enum i9xx_plane_id/
>   drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks
>   drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in
> initial fb readout
>   drm/i915: Nuke ironlake_get_initial_plane_config()
>   drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>   drm/i915: Nuke crtc->plane
>   drm/i915: Use plane->get_hw_state() for initial plane fb readout
>   drm/i915: Add rudimentary plane state verification
> 
>  drivers/gpu/drm/i915/i915_drv.h  |  16 +-
>  drivers/gpu/drm/i915/intel_display.c | 519 
> ---
>  drivers/gpu/drm/i915/intel_drv.h |   9 +-
>  drivers/gpu/drm/i915/intel_fbc.c |  35 ++-
>  drivers/gpu/drm/i915/intel_pm.c  |  36 +--
>  drivers/gpu/drm/i915/intel_sprite.c  |  85 +-
>  6 files changed, 373 insertions(+), 327 deletions(-)
> 
> -- 
> 2.13.6
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane assert/readout cleanups etc. (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc. (rev9)
URL   : https://patchwork.freedesktop.org/series/31758/
State : success

== Summary ==

Series 31758v9 drm/i915: Plane assert/readout cleanups etc.
https://patchwork.freedesktop.org/api/1.0/series/31758/revisions/9/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:454s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:379s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:554s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:500s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:497s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:487s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:426s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:482s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:578s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:558s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:416s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:607s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:548s
fi-glk-dsi   total:156  pass:133  dwarn:0   dfail:0   fail:0   skip:22 

74ae8acff97c1739330154fa34bf5a64e28d608f drm-tip: 2017y-11m-17d-17h-53m-01s UTC 
integration manifest
52af1bc14617 drm/i915: Add rudimentary plane state verification
29561aa75bfd drm/i915: Use plane->get_hw_state() for initial plane fb readout
ee2987349d8c drm/i915: Nuke crtc->plane
2aeaf2574af6 drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
d02162cc6092 drm/i915: Nuke ironlake_get_initial_plane_config()
481703c326e8 drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in 
initial fb readout
a2bc7475c85d drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks
a99138d4f433 drm/i915: s/enum plane/enum i9xx_plane_id/
9b752b27b383 drm/i915: Redo plane sanitation during readout
3f6b3bc03e92 drm/i915: Add .get_hw_state() method for planes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7181/
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[Intel-gfx] [PATCH v3 10/10] drm/i915: Add rudimentary plane state verification

[Ville Syrjala]

From: Ville Syrjälä 

Check that the planes are in the state we expect them to be. For
now we can only check whether each plane is correctly enabled or
disabled. In the future we may want to expand the plane state
readout to support a more thorough verification.

v2: Verify all planes part of the state as long as at least
one crtc is doing a modeset (Daniel)
v3: Fix typoes (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Suggested-by: Daniel Vetter 
Reviewed-by: James Ausmus 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ed58311e8da0..5ca7b33554ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11601,6 +11601,18 @@ verify_crtc_state(struct drm_crtc *crtc,
 }
 
 static void
+intel_verify_planes(struct intel_atomic_state *state)
+{
+   struct intel_plane *plane;
+   const struct intel_plane_state *plane_state;
+   int i;
+
+   for_each_new_intel_plane_in_state(state, plane,
+ plane_state, i)
+   assert_plane(plane, plane_state->base.visible);
+}
+
+static void
 verify_single_dpll_state(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll,
 struct drm_crtc *crtc,
@@ -12393,6 +12405,9 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
intel_modeset_verify_crtc(crtc, state, old_crtc_state, 
new_crtc_state);
}
 
+   if (intel_state->modeset)
+   intel_verify_planes(intel_state);
+
if (intel_state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
 
-- 
2.13.6

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[Intel-gfx] [PATCH v3 09/10] drm/i915: Use plane->get_hw_state() for initial plane fb readout

[Ville Syrjala]

From: Ville Syrjälä 

Since we now have a ->get_hw_state() method for planes, let's use
that during the initial plane fb readout.

v2: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Suggested-by: Daniel Vetter 
Reviewed-by: James Ausmus 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 62cc2a600205..ed58311e8da0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7413,8 +7413,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
 
-   val = I915_READ(DSPCNTR(i9xx_plane));
-   if (!(val & DISPLAY_PLANE_ENABLE))
+   if (!plane->get_hw_state(plane))
return;
 
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
@@ -7427,6 +7426,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
fb->dev = dev;
 
+   val = I915_READ(DSPCNTR(i9xx_plane));
+
if (INTEL_GEN(dev_priv) >= 4) {
if (val & DISPPLANE_TILED) {
plane_config->tiling = I915_TILING_X;
@@ -8442,6 +8443,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
 
+   if (!plane->get_hw_state(plane))
+   return;
+
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
if (!intel_fb) {
DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -8453,8 +8457,6 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->dev = dev;
 
val = I915_READ(PLANE_CTL(pipe, plane_id));
-   if (!(val & PLANE_CTL_ENABLE))
-   goto error;
 
pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
-- 
2.13.6

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[Intel-gfx] [PATCH v2 06/10] drm/i915: Nuke ironlake_get_initial_plane_config()

[Ville Syrjala]

From: Ville Syrjälä 

The only relevant difference between i9xx_get_initial_plane_config() and
ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
Add that to i9xx_get_initial_plane_config() and nuke
ironlake_get_initial_plane_config().

v2: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 79 +++-
 1 file changed, 6 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0c407cb0e6aa..c1d7547c1457 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7438,7 +7438,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fourcc = i9xx_format_to_fourcc(pixel_format);
fb->format = drm_format_info(fourcc);
 
-   if (INTEL_GEN(dev_priv) >= 4) {
+   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+   offset = I915_READ(DSPOFFSET(i9xx_plane));
+   base = I915_READ(DSPSURF(i9xx_plane)) & 0xf000;
+   } else if (INTEL_GEN(dev_priv) >= 4) {
if (plane_config->tiling)
offset = I915_READ(DSPTILEOFF(i9xx_plane));
else
@@ -8545,76 +8548,6 @@ static void ironlake_get_pfit_config(struct intel_crtc 
*crtc,
}
 }
 
-static void
-ironlake_get_initial_plane_config(struct intel_crtc *crtc,
- struct intel_initial_plane_config 
*plane_config)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
-   enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
-   enum pipe pipe = crtc->pipe;
-   u32 val, base, offset;
-   int fourcc, pixel_format;
-   unsigned int aligned_height;
-   struct drm_framebuffer *fb;
-   struct intel_framebuffer *intel_fb;
-
-   val = I915_READ(DSPCNTR(i9xx_plane));
-   if (!(val & DISPLAY_PLANE_ENABLE))
-   return;
-
-   intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-   if (!intel_fb) {
-   DRM_DEBUG_KMS("failed to alloc fb\n");
-   return;
-   }
-
-   fb = _fb->base;
-
-   fb->dev = dev;
-
-   if (INTEL_GEN(dev_priv) >= 4) {
-   if (val & DISPPLANE_TILED) {
-   plane_config->tiling = I915_TILING_X;
-   fb->modifier = I915_FORMAT_MOD_X_TILED;
-   }
-   }
-
-   pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
-   fourcc = i9xx_format_to_fourcc(pixel_format);
-   fb->format = drm_format_info(fourcc);
-
-   base = I915_READ(DSPSURF(i9xx_plane)) & 0xf000;
-   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   offset = I915_READ(DSPOFFSET(i9xx_plane));
-   } else {
-   if (plane_config->tiling)
-   offset = I915_READ(DSPTILEOFF(i9xx_plane));
-   else
-   offset = I915_READ(DSPLINOFF(i9xx_plane));
-   }
-   plane_config->base = base;
-
-   val = I915_READ(PIPESRC(pipe));
-   fb->width = ((val >> 16) & 0xfff) + 1;
-   fb->height = ((val >> 0) & 0xfff) + 1;
-
-   val = I915_READ(DSPSTRIDE(i9xx_plane));
-   fb->pitches[0] = val & 0xffc0;
-
-   aligned_height = intel_fb_align_height(fb, 0, fb->height);
-
-   plane_config->size = fb->pitches[0] * aligned_height;
-
-   DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
- crtc->base.name, plane->base.name, fb->width, fb->height,
- fb->format->cpp[0] * 8, base, fb->pitches[0],
- plane_config->size);
-
-   plane_config->fb = intel_fb;
-}
-
 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 struct intel_crtc_state *pipe_config)
 {
@@ -14217,7 +14150,7 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
} else if (HAS_DDI(dev_priv)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
-   ironlake_get_initial_plane_config;
+   i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -14225,7 +14158,7 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
-   

[Intel-gfx] [PATCH v3 00/10] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjala]

From: Ville Syrjälä 

OK, one more time. This time with s/plane/i9xx_plane/ etc. all over.
Maybe that will make everyone happy? Unlikely, but let's try.

Patch 3 is the only one missing r-b.

Ville Syrjälä (10):
  drm/i915: Add .get_hw_state() method for planes
  drm/i915: Redo plane sanitation during readout
  drm/i915: s/enum plane/enum i9xx_plane_id/
  drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks
  drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in
initial fb readout
  drm/i915: Nuke ironlake_get_initial_plane_config()
  drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
  drm/i915: Nuke crtc->plane
  drm/i915: Use plane->get_hw_state() for initial plane fb readout
  drm/i915: Add rudimentary plane state verification

 drivers/gpu/drm/i915/i915_drv.h  |  16 +-
 drivers/gpu/drm/i915/intel_display.c | 519 ---
 drivers/gpu/drm/i915/intel_drv.h |   9 +-
 drivers/gpu/drm/i915/intel_fbc.c |  35 ++-
 drivers/gpu/drm/i915/intel_pm.c  |  36 +--
 drivers/gpu/drm/i915/intel_sprite.c  |  85 +-
 6 files changed, 373 insertions(+), 327 deletions(-)

-- 
2.13.6

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[Intel-gfx] [PATCH v2 07/10] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()

[Ville Syrjala]

From: Ville Syrjälä 

Stop using the old for_each_intel_plane_in_state() type iteration
macro and replace it with for_each_new_intel_plane_in_state().
And similarly replace drm_atomic_get_existing_crtc_state() with
intel_atomic_get_new_crtc_state(). Switch over to intel_ types
as well to make the code less cluttered.

v2: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Maarten Lankhorst 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  7 +++
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_fbc.c | 23 ++-
 4 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bbeefa2c11ba..9b4857096dd2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -560,13 +560,13 @@ struct i915_hotplug {
for_each_power_well_rev(__dev_priv, __power_well)   
\
for_each_if ((__power_well)->domains & (__domain_mask))
 
-#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
+#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, 
__i) \
for ((__i) = 0; \
 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 ((plane) = 
to_intel_plane((__state)->base.planes[__i].ptr), \
- (plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].state), 1); \
+ (new_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 (__i)++) \
-   for_each_if (plane_state)
+   for_each_if (plane)
 
 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
for ((__i) = 0; \
@@ -576,7 +576,6 @@ struct i915_hotplug {
 (__i)++) \
for_each_if (crtc)
 
-
 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, 
new_plane_state, __i) \
for ((__i) = 0; \
 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c1d7547c1457..b1ead3f95cde 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12080,7 +12080,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
return ret;
 
-   intel_fbc_choose_crtc(dev_priv, state);
+   intel_fbc_choose_crtc(dev_priv, intel_state);
return calc_watermark_data(state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1fe7be94b62..3ebe62666108 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1652,7 +1652,7 @@ static inline void intel_fbdev_restore_mode(struct 
drm_device *dev)
 
 /* intel_fbc.c */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-  struct drm_atomic_state *state);
+  struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
 void intel_fbc_pre_update(struct intel_crtc *crtc,
  struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 3133131306a9..474234322b8b 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1054,11 +1054,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
  */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-  struct drm_atomic_state *state)
+  struct intel_atomic_state *state)
 {
struct intel_fbc *fbc = _priv->fbc;
-   struct drm_plane *plane;
-   struct drm_plane_state *plane_state;
+   struct intel_plane *plane;
+   struct intel_plane_state *plane_state;
bool crtc_chosen = false;
int i;
 
@@ -1066,7 +1066,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
 
/* Does this atomic commit involve the CRTC currently tied to FBC? */
if (fbc->crtc &&
-   !drm_atomic_get_existing_crtc_state(state, >crtc->base))
+   !intel_atomic_get_new_crtc_state(state, fbc->crtc))
goto out;
 
if (!intel_fbc_can_enable(dev_priv))
@@ -1076,13 +1076,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
 * plane. We could go for fancier schemes such as checking the plane
 * size, but this would just affect the few platforms that don't tie FBC
 * to pipe or plane A. */
-   

[Intel-gfx] [PATCH v3 02/10] drm/i915: Redo plane sanitation during readout

[Ville Syrjala]

From: Ville Syrjälä 

Unify the plane disabling during state readout by pulling the code into
a new helper intel_plane_disable_noatomic(). We'll also read out the
state of all planes, so that we know which planes really need to be
diabled.

Additonally we change the plane<->pipe mapping sanitation to work by
simply disabling the offending planes instead of entire pipes. And
we do it before we otherwise sanitize the crtcs, which means we don't
have to worry about misassigned planes during crtc sanitation anymore.

v2: Reoder patches to not depend on enum old_plane_id
v3: s/for_each_pipe/for_each_intel_crtc/

Cc: Thierry Reding 
Cc: Alex Villacís Lasso 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103223
Reviewed-by: Daniel Vetter 
Tested-by: Thierry Reding 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 114 ---
 1 file changed, 65 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7bf8290f0343..91f74c5373b3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2726,6 +2726,23 @@ intel_set_plane_visible(struct intel_crtc_state 
*crtc_state,
  crtc_state->active_planes);
 }
 
+static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
+struct intel_plane *plane)
+{
+   struct intel_crtc_state *crtc_state =
+   to_intel_crtc_state(crtc->base.state);
+   struct intel_plane_state *plane_state =
+   to_intel_plane_state(plane->base.state);
+
+   intel_set_plane_visible(crtc_state, plane_state, false);
+
+   if (plane->id == PLANE_PRIMARY)
+   intel_pre_disable_primary_noatomic(>base);
+
+   trace_intel_disable_plane(>base, crtc);
+   plane->disable_plane(plane, crtc);
+}
+
 static void
 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 struct intel_initial_plane_config *plane_config)
@@ -2783,12 +2800,7 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
 * simplest solution is to just disable the primary plane now and
 * pretend the BIOS never had it enabled.
 */
-   intel_set_plane_visible(to_intel_crtc_state(crtc_state),
-   to_intel_plane_state(plane_state),
-   false);
-   intel_pre_disable_primary_noatomic(_crtc->base);
-   trace_intel_disable_plane(primary, intel_crtc);
-   intel_plane->disable_plane(intel_plane, intel_crtc);
+   intel_plane_disable_noatomic(intel_crtc, intel_plane);
 
return;
 
@@ -5869,6 +5881,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc 
*crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum intel_display_power_domain domain;
+   struct intel_plane *plane;
u64 domains;
struct drm_atomic_state *state;
struct intel_crtc_state *crtc_state;
@@ -5877,11 +5890,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc 
*crtc,
if (!intel_crtc->active)
return;
 
-   if (crtc->primary->state->visible) {
-   intel_pre_disable_primary_noatomic(crtc);
+   for_each_intel_plane_on_crtc(_priv->drm, intel_crtc, plane) {
+   const struct intel_plane_state *plane_state =
+   to_intel_plane_state(plane->base.state);
 
-   intel_crtc_disable_planes(crtc, 1 << 
drm_plane_index(crtc->primary));
-   crtc->primary->state->visible = false;
+   if (plane_state->base.visible)
+   intel_plane_disable_noatomic(intel_crtc, plane);
}
 
state = drm_atomic_state_alloc(crtc->dev);
@@ -14773,22 +14787,36 @@ void i830_disable_pipe(struct drm_i915_private 
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
 }
 
-static bool
-intel_check_plane_mapping(struct intel_crtc *crtc)
+static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
+  struct intel_plane *primary)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   u32 val;
+   enum plane plane = primary->plane;
+   u32 val = I915_READ(DSPCNTR(plane));
 
-   if (INTEL_INFO(dev_priv)->num_pipes == 1)
-   return true;
+   return (val & DISPLAY_PLANE_ENABLE) == 0 ||
+   (val & DISPPLANE_SEL_PIPE_MASK) == 
DISPPLANE_SEL_PIPE(crtc->pipe);
+}
 
-   val = I915_READ(DSPCNTR(!crtc->plane));
+static void
+intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+{
+   struct intel_crtc *crtc;
 
-   if ((val & DISPLAY_PLANE_ENABLE) &&
-

[Intel-gfx] [PATCH v3 08/10] drm/i915: Nuke crtc->plane

[Ville Syrjala]

From: Ville Syrjälä 

Eliminate crtc->plane since it's pretty much a layering violation.
We can always get the plane via crtc->primary if we actually need it.

The only ugly thing left is plane_to_crtc_mapping[], but that's
still needed by the pre-g4x watermark code.

v2: Removed a misplaced comment change (Daniel)
v3: Rebase due to fbc crtc->y usage removal
v4: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 drivers/gpu/drm/i915/intel_drv.h | 1 -
 drivers/gpu/drm/i915/intel_fbc.c | 4 ++--
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b1ead3f95cde..62cc2a600205 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13463,14 +13463,13 @@ static int intel_crtc_init(struct drm_i915_private 
*dev_priv, enum pipe pipe)
goto fail;
 
intel_crtc->pipe = pipe;
-   intel_crtc->i9xx_plane = primary->i9xx_plane;
 
/* initialize shared scalers */
intel_crtc_init_scalers(intel_crtc, crtc_state);
 
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
-  dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] != NULL);
-   dev_priv->plane_to_crtc_mapping[intel_crtc->i9xx_plane] = intel_crtc;
+  dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] != NULL);
+   dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] = intel_crtc;
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
 
drm_crtc_helper_add(_crtc->base, _helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3ebe62666108..635a96fcd788 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -799,7 +799,6 @@ struct intel_crtc_state {
 struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
-   enum i9xx_plane_id i9xx_plane;
/*
 * Whether the crtc and the connected output pipeline is active. Implies
 * that crtc->enabled is set, i.e. the current mode configuration has
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 474234322b8b..4aefc658a5cf 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -890,7 +890,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc 
*crtc,
params->vma = cache->vma;
 
params->crtc.pipe = crtc->pipe;
-   params->crtc.i9xx_plane = crtc->i9xx_plane;
+   params->crtc.i9xx_plane = 
to_intel_plane(crtc->base.primary)->i9xx_plane;
params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 
params->fb.format = cache->fb.format;
@@ -1086,7 +1086,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
continue;
 
-   if (fbc_on_plane_a_only(dev_priv) && crtc->i9xx_plane != 
PLANE_A)
+   if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != 
PLANE_A)
continue;
 
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-- 
2.13.6

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[Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[Ville Syrjala]

From: Ville Syrjälä 

Rename enum plane to enum i9xx_plane_id to make it clear that it only
applies to pre-SKL platforms.

enum i9xx_plane_id is a global identifier, whereas enum plane_id is
per-pipe. We need the old global identifier to index the primary plane
(and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
platforms.

v2: Reorder patches
v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
Pimp the commit message a bit
Note that i9xx_plane_id doesn't apply to SKL+
v4: Rebase due to power domain handling in plane readout
v5: Rebase due to crtc->dspaddr_offset removal
v6: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  6 +--
 drivers/gpu/drm/i915/intel_display.c | 98 ++--
 drivers/gpu/drm/i915/intel_drv.h |  6 +--
 drivers/gpu/drm/i915/intel_fbc.c | 12 ++---
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 5 files changed, 62 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2158a758a17d..55dd602582cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
transcoder)
 
 /*
  * Global legacy plane identifier. Valid only for primary/sprite
- * planes on pre-g4x, and only for primary planes on g4x+.
+ * planes on pre-g4x, and only for primary planes on g4x-bdw.
  */
-enum plane {
+enum i9xx_plane_id {
PLANE_A,
PLANE_B,
PLANE_C,
@@ -1145,7 +1145,7 @@ struct intel_fbc {
 
struct {
enum pipe pipe;
-   enum plane plane;
+   enum i9xx_plane_id i9xx_plane;
unsigned int fence_y_offset;
} crtc;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 91f74c5373b3..16ac86816f28 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct intel_plane_state 
*plane_state)
return 0;
 }
 
-static void i9xx_update_primary_plane(struct intel_plane *primary,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state 
*plane_state)
+static void i9xx_update_plane(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
 {
-   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
-   enum plane plane = primary->plane;
+   enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 linear_offset;
u32 dspcntr = plane_state->ctl;
-   i915_reg_t reg = DSPCNTR(plane);
+   i915_reg_t reg = DSPCNTR(i9xx_plane);
int x = plane_state->main.x;
int y = plane_state->main.y;
unsigned long irqflags;
@@ -3248,34 +3248,34 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
/* pipesrc and dspsize control the size that is scaled from,
 * which should always be the user's requested size.
 */
-   I915_WRITE_FW(DSPSIZE(plane),
+   I915_WRITE_FW(DSPSIZE(i9xx_plane),
  ((crtc_state->pipe_src_h - 1) << 16) |
  (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(DSPPOS(plane), 0);
-   } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
-   I915_WRITE_FW(PRIMSIZE(plane),
+   I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
+   } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
+   I915_WRITE_FW(PRIMSIZE(i9xx_plane),
  ((crtc_state->pipe_src_h - 1) << 16) |
  (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(PRIMPOS(plane), 0);
-   I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
+   I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
+   I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
}
 
I915_WRITE_FW(reg, dspcntr);
 
-   I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
+   I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   I915_WRITE_FW(DSPSURF(plane),
+   I915_WRITE_FW(DSPSURF(i9xx_plane),
  intel_plane_ggtt_offset(plane_state) +
  dspaddr_offset);
-   I915_WRITE_FW(DSPOFFSET(plane), (y << 

[Intel-gfx] [PATCH v3 04/10] drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks

[Ville Syrjala]

From: Ville Syrjälä 

Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code.

v2: s/old_plane_id/i9xx_plane_id/ (Daniel)
v3: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_pm.c | 36 +++-
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55dd602582cb..bbeefa2c11ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -698,7 +698,8 @@ struct drm_i915_display_funcs {
  struct intel_cdclk_state *cdclk_state);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_state *cdclk_state);
-   int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
+   int (*get_fifo_size)(struct drm_i915_private *dev_priv,
+enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
int (*compute_intermediate_wm)(struct drm_device *dev,
   struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c55e4026331..f22cc8468cc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -518,38 +518,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state 
*crtc_state)
fifo_state->plane[PLANE_CURSOR] = 63;
 }
 
-static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
 
size = dsparb & 0x7f;
-   if (plane)
+   if (i9xx_plane == PLANE_B)
size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A", size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(i9xx_plane), size);
 
return size;
 }
 
-static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
 
size = dsparb & 0x1ff;
-   if (plane)
+   if (i9xx_plane == PLANE_B)
size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
size >>= 1; /* Convert to cachelines */
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A", size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(i9xx_plane), size);
 
return size;
 }
 
-static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
@@ -557,9 +560,8 @@ static int i845_get_fifo_size(struct drm_i915_private 
*dev_priv, int plane)
size = dsparb & 0x7f;
size >>= 2; /* Convert to cachelines */
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A",
- size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(i9xx_plane), size);
 
return size;
 }
@@ -2283,8 +2285,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = _a_wm_info;
 
-   fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
-   crtc = intel_get_crtc_for_plane(dev_priv, 0);
+   fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
>config->base.adjusted_mode;
@@ -2310,8 +2312,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (IS_GEN2(dev_priv))
wm_info = _bc_wm_info;
 
-   fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
-   crtc = intel_get_crtc_for_plane(dev_priv, 1);
+   fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
>config->base.adjusted_mode;

[Intel-gfx] [PATCH v4 01/10] drm/i915: Add .get_hw_state() method for planes

[Ville Syrjala]

From: Ville Syrjälä 

Add a .get_hw_state() method for planes, returning true or false
depending on whether the plane is enabled. Use it to rewrite the
plane enabled/disabled asserts in platform agnostic fashion.

We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
supposed sanitize that anyway it doesn't really matter.

v2: Reoder patches to not depend on enum old_plane_id
Just call assert_plane_disabled() from assert_planes_disabled()
v3: Deal with disabled power wells in .get_hw_state()
v4: Rebase due skl primary plane code removal

Cc: Thierry Reding 
Cc: Alex Villacís Lasso 
Reviewed-by: Daniel Vetter  #v2
Tested-by: Thierry Reding  #v2
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 188 +--
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 drivers/gpu/drm/i915/intel_sprite.c  |  83 
 3 files changed, 175 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3b3dec1e6640..7bf8290f0343 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1190,23 +1190,6 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
 pipe_name(pipe));
 }
 
-static void assert_cursor(struct drm_i915_private *dev_priv,
- enum pipe pipe, bool state)
-{
-   bool cur_state;
-
-   if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
-   cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
-   else
-   cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
-
-   I915_STATE_WARN(cur_state != state,
-"cursor on pipe %c assertion failure (expected %s, current %s)\n",
-   pipe_name(pipe), onoff(state), onoff(cur_state));
-}
-#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
-#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
-
 void assert_pipe(struct drm_i915_private *dev_priv,
 enum pipe pipe, bool state)
 {
@@ -1234,77 +1217,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
pipe_name(pipe), onoff(state), onoff(cur_state));
 }
 
-static void assert_plane(struct drm_i915_private *dev_priv,
-enum plane plane, bool state)
+static void assert_plane(struct intel_plane *plane, bool state)
 {
-   u32 val;
-   bool cur_state;
+   bool cur_state = plane->get_hw_state(plane);
 
-   val = I915_READ(DSPCNTR(plane));
-   cur_state = !!(val & DISPLAY_PLANE_ENABLE);
I915_STATE_WARN(cur_state != state,
-"plane %c assertion failure (expected %s, current %s)\n",
-   plane_name(plane), onoff(state), onoff(cur_state));
+   "%s assertion failure (expected %s, current %s)\n",
+   plane->base.name, onoff(state), onoff(cur_state));
 }
 
-#define assert_plane_enabled(d, p) assert_plane(d, p, true)
-#define assert_plane_disabled(d, p) assert_plane(d, p, false)
+#define assert_plane_enabled(p) assert_plane(p, true)
+#define assert_plane_disabled(p) assert_plane(p, false)
 
-static void assert_planes_disabled(struct drm_i915_private *dev_priv,
-  enum pipe pipe)
+static void assert_planes_disabled(struct intel_crtc *crtc)
 {
-   int i;
-
-   /* Primary planes are fixed to pipes on gen4+ */
-   if (INTEL_GEN(dev_priv) >= 4) {
-   u32 val = I915_READ(DSPCNTR(pipe));
-   I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
-"plane %c assertion failure, should be disabled but not\n",
-plane_name(pipe));
-   return;
-   }
-
-   /* Need to check both planes against the pipe */
-   for_each_pipe(dev_priv, i) {
-   u32 val = I915_READ(DSPCNTR(i));
-   enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
-   DISPPLANE_SEL_PIPE_SHIFT;
-   I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == 
cur_pipe,
-"plane %c assertion failure, should be off on pipe %c but 
is still active\n",
-plane_name(i), pipe_name(pipe));
-   }
-}
-
-static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
-   enum pipe pipe)
-{
-   int sprite;
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   struct intel_plane *plane;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   for_each_sprite(dev_priv, pipe, sprite) {
-   u32 val = I915_READ(PLANE_CTL(pipe, sprite));
-   I915_STATE_WARN(val & PLANE_CTL_ENABLE,
-"plane %d assertion failure, 

[Intel-gfx] [PATCH v5 05/10] drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in initial fb readout

[Ville Syrjala]

From: Ville Syrjälä 

Use enum pipe, enum plane_id, and enum i9xx_plane_id consistently in the
initial framebuffe readout.

v2: Use old_plane_id in the ilk code
v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
v4: Rebase due to GLK/CNL PLANE_COLOR_CTL alpha stuff
v5: s/plane/i9xx_plane/ etc. (James)

Cc: James Ausmus 
Cc: Daniel Vetter 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 60 
 1 file changed, 33 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 16ac86816f28..0c407cb0e6aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7404,14 +7404,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+   enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+   enum pipe pipe = crtc->pipe;
u32 val, base, offset;
-   int pipe = crtc->pipe, plane = crtc->i9xx_plane;
int fourcc, pixel_format;
unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
 
-   val = I915_READ(DSPCNTR(plane));
+   val = I915_READ(DSPCNTR(i9xx_plane));
if (!(val & DISPLAY_PLANE_ENABLE))
return;
 
@@ -7438,12 +7440,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
if (INTEL_GEN(dev_priv) >= 4) {
if (plane_config->tiling)
-   offset = I915_READ(DSPTILEOFF(plane));
+   offset = I915_READ(DSPTILEOFF(i9xx_plane));
else
-   offset = I915_READ(DSPLINOFF(plane));
-   base = I915_READ(DSPSURF(plane)) & 0xf000;
+   offset = I915_READ(DSPLINOFF(i9xx_plane));
+   base = I915_READ(DSPSURF(i9xx_plane)) & 0xf000;
} else {
-   base = I915_READ(DSPADDR(plane));
+   base = I915_READ(DSPADDR(i9xx_plane));
}
plane_config->base = base;
 
@@ -7451,15 +7453,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = ((val >> 16) & 0xfff) + 1;
fb->height = ((val >> 0) & 0xfff) + 1;
 
-   val = I915_READ(DSPSTRIDE(pipe));
+   val = I915_READ(DSPSTRIDE(i9xx_plane));
fb->pitches[0] = val & 0xffc0;
 
aligned_height = intel_fb_align_height(fb, 0, fb->height);
 
plane_config->size = fb->pitches[0] * aligned_height;
 
-   DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, 
pitch %d, size 0x%x\n",
- pipe_name(pipe), plane, fb->width, fb->height,
+   DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
+ crtc->base.name, plane->base.name, fb->width, fb->height,
  fb->format->cpp[0] * 8, base, fb->pitches[0],
  plane_config->size);
 
@@ -8428,8 +8430,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+   enum plane_id plane_id = plane->id;
+   enum pipe pipe = crtc->pipe;
u32 val, base, offset, stride_mult, tiling, alpha;
-   int pipe = crtc->pipe;
int fourcc, pixel_format;
unsigned int aligned_height;
struct drm_framebuffer *fb;
@@ -8445,14 +8449,14 @@ skylake_get_initial_plane_config(struct intel_crtc 
*crtc,
 
fb->dev = dev;
 
-   val = I915_READ(PLANE_CTL(pipe, 0));
+   val = I915_READ(PLANE_CTL(pipe, plane_id));
if (!(val & PLANE_CTL_ENABLE))
goto error;
 
pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
-   alpha = I915_READ(PLANE_COLOR_CTL(pipe, 0));
+   alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
alpha &= PLANE_COLOR_ALPHA_MASK;
} else {
alpha = val & PLANE_CTL_ALPHA_MASK;
@@ -8488,16 +8492,16 @@ skylake_get_initial_plane_config(struct intel_crtc 
*crtc,
goto error;
}
 
-   base = I915_READ(PLANE_SURF(pipe, 0)) & 0xf000;
+   base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xf000;
plane_config->base = base;
 
-   offset = I915_READ(PLANE_OFFSET(pipe, 0));
+   offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
 
-   val = I915_READ(PLANE_SIZE(pipe, 0));
+   val = I915_READ(PLANE_SIZE(pipe, plane_id));
fb->height = ((val >> 16) & 0xfff) + 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix init_clock_gating for resume (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix init_clock_gating for resume (rev2)
URL   : https://patchwork.freedesktop.org/series/33718/
State : success

== Summary ==

Series 33718v2 drm/i915: Fix init_clock_gating for resume
https://patchwork.freedesktop.org/api/1.0/series/33718/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103163
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:443s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:454s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:508s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:489s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:427s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:476s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:542s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:547s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:517s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:468s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:563s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:423s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:612s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:547s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:501s
fi-pnv-d510 failed to collect. IGT log at Patchwork_7180/fi-pnv-d510/igt.log

74ae8acff97c1739330154fa34bf5a64e28d608f drm-tip: 2017y-11m-17d-17h-53m-01s UTC 
integration manifest
89e3a2006ae6 drm/i915: Fix init_clock_gating for resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7180/
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Re: [Intel-gfx] [PATCH v2 2/2] i915/drrs/debugfs: crtc id and psr status

[Rodrigo Vivi]

On Tue, Nov 07, 2017 at 06:40:08PM +, Ramalingam C wrote:
> From: "C, Ramalingam" 
> 
> Existing debugfs entry i915_drrs_status is updated with crtc id and
> if PSR is cause for DRRS disabled state.
> 
> [v2]: Dropped the module parameter details as ctl moved from module
>   parameter to debugfs. [Rodrigo]
> 
> Signed-off-by: C, Ramalingam 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0c1501fe4c9f..6c2e8346b9a7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3567,7 +3567,10 @@ static void drrs_status_per_crtc(struct seq_file *m,
>  
>   /* disable_drrs() will make drrs->dp NULL */
>   if (!drrs->dp) {
> - seq_puts(m, "Idleness DRRS: Disabled");
> + seq_puts(m, "Idleness DRRS: Disabled\n");
> + if (dev_priv->psr.enabled)
> + seq_puts(m,
> + "\tAs PSR is enabled, DRRS is not enabled\n");

this seems good...

>   mutex_unlock(>mutex);
>   return;
>   }
> @@ -3611,7 +3614,7 @@ static int i915_drrs_status(struct seq_file *m, void 
> *unused)
>   for_each_intel_crtc(dev, intel_crtc) {
>   if (intel_crtc->base.state->active) {
>   active_crtc_cnt++;
> - seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
> + seq_printf(m, "\nCRTC %d: ", intel_crtc->base.base.id);

this seems for a separated patch...
or at least missing an explanation why...

>  
>   drrs_status_per_crtc(m, dev, intel_crtc);
>   }
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Runtime disable for eDP DRRS

[Rodrigo Vivi]

On Tue, Nov 07, 2017 at 06:38:23PM +, Ramalingam C wrote:
> From: "C, Ramalingam" 
> 
> Debugfs called i915_drrs_ctl is added to enable and disable the
> eDP DRRS. Writing 0 will disable the feature, whereas non-zero
> will enable the feature.
> 
> Possibility of disabling the DRRS, enables the testing of the
> frontbuffer tracking based features (FBC, DRRS and PSR) as
> standalone or any combination of the set.
> 
> [v2]: ctl interface is moved from module parameter to debugfs [Rodrigo]

Thanks

> 
> Signed-off-by: C, Ramalingam 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 43 
> -
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0bb6e01121fc..0c1501fe4c9f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4747,6 +4747,46 @@ static const struct file_operations 
> i915_hpd_storm_ctl_fops = {
>   .write = i915_hpd_storm_ctl_write
>  };
>  
> +static int i915_drrs_ctl_set(void *data, u64 val)
> +{
> + struct drm_i915_private *dev_priv = data;
> + struct drm_device *dev = _priv->drm;
> + struct intel_crtc *intel_crtc;
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp;
> +
> + if (INTEL_GEN(dev_priv) < 7)

I believe we need to define a HAS_DRRS(dev_priv)
which based on what is on intel_cpu_transcoder_set_m_n would be
(IS_CHERRYVIEW(dev_priv) || INTEL_GEN(dev_priv) < 8)

> + return -ENODEV;
> +
> + drm_modeset_lock_all(dev);

my first reaction to this was: "why do you need to lock all modeset?!"
But this simplify a lot the logic here...
This assure that drrs is really not getting changed from other places.

> + for_each_intel_crtc(dev, intel_crtc) {
> + if (!intel_crtc->base.state->active ||
> + !intel_crtc->config->has_drrs)

I was going to say that this check already happens inside
enable and disable functions... But I see the reason why to
check before the unecessary noise.

> + continue;
> +
> + for_each_encoder_on_crtc(dev, _crtc->base, encoder) {
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + continue;
> +
> + DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
> + val ? "en" : "dis", val);
> +
> + intel_dp = enc_to_intel_dp(>base);
> + if (val)
> + intel_edp_drrs_enable(intel_dp,
> + intel_crtc->config);
> + else
> + intel_edp_drrs_disable(intel_dp,
> + intel_crtc->config);
> + }
> + }
> + drm_modeset_unlock_all(dev);
> +
> + return 0;
> +}

It seems simple and effective. Simpler than I imagined...
My only question is about that HAS_DRRS and when to skip here...

> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, 
> "%llu\n");
> +
>  static const struct drm_info_list i915_debugfs_list[] = {
>   {"i915_capabilities", i915_capabilities, 0},
>   {"i915_gem_objects", i915_gem_object_info, 0},
> @@ -4828,7 +4868,8 @@ static const struct i915_debugfs_files {
>   {"i915_dp_test_active", _displayport_test_active_fops},
>   {"i915_guc_log_control", _guc_log_control_fops},
>   {"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
> - {"i915_ipc_status", _ipc_status_fops}
> + {"i915_ipc_status", _ipc_status_fops},
> + {"i915_drrs_ctl", _drrs_ctl_fops}
>  };
>  
>  int i915_debugfs_register(struct drm_i915_private *dev_priv)
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3)

[Chris Wilson]

Quoting Patchwork (2017-11-17 18:37:16)
> == Series Details ==
> 
> Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure 
> (rev3)
> URL   : https://patchwork.freedesktop.org/series/33994/
> State : success
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7177/shards.html

Success! Thanks,
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure 
(rev3)
URL   : https://patchwork.freedesktop.org/series/33994/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
pass   -> SKIP   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
skip   -> PASS   (shard-hsw) fdo#103167
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
skip   -> PASS   (shard-hsw) fdo#102249
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-fencing:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-pipe-a-planes:
skip   -> PASS   (shard-hsw)
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS   (shard-hsw) fdo#102707 +1

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707

shard-hswtotal:2585 pass:1471 dwarn:2   dfail:1   fail:12  skip:1099 
time:9394s
shard-snbtotal:2585 pass:1259 dwarn:1   dfail:1   fail:12  skip:1312 
time:8105s
Blacklisted hosts:
shard-apltotal:2585 pass:1625 dwarn:1   dfail:1   fail:22  skip:936 
time:13448s
shard-kbltotal:2565 pass:1695 dwarn:8   dfail:3   fail:24  skip:834 
time:10521s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7177/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)
URL   : https://patchwork.freedesktop.org/series/33608/
State : success

== Summary ==

Series 33608v2 drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+
https://patchwork.freedesktop.org/api/1.0/series/33608/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:459s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:555s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:496s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:493s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:436s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:426s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:466s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:481s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:532s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:571s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:548s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:462s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:561s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:424s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:610s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:493s

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
ba7ea7279621 drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7179/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable fastboot, v2!

[Patchwork]

== Series Details ==

Series: drm/i915: Enable fastboot, v2!
URL   : https://patchwork.freedesktop.org/series/34010/
State : success

== Summary ==

Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-hsw) fdo#103719
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
skip   -> PASS   (shard-hsw) fdo#103167
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
skip   -> PASS   (shard-hsw) fdo#102249
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-fencing:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-pipe-a-planes:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS   (shard-hsw) fdo#102707

fdo#103719 https://bugs.freedesktop.org/show_bug.cgi?id=103719
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707

shard-hswtotal:2585 pass:1473 dwarn:2   dfail:1   fail:10  skip:1099 
time:9448s
shard-snbtotal:2585 pass:1261 dwarn:1   dfail:1   fail:11  skip:1311 
time:8002s
Blacklisted hosts:
shard-apltotal:2563 pass:1600 dwarn:2   dfail:0   fail:23  skip:936 
time:12973s
shard-kbltotal:2492 pass:1659 dwarn:9   dfail:1   fail:21  skip:801 
time:10337s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7175/shards.html
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Re: [Intel-gfx] [PATCH 0/3] drm/i915: Enable fastboot, v2!

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 03:37:53PM +, Maarten Lankhorst wrote:
> Small fixes for IPS, and then we flip the switch! :-)
> 
> Maarten Lankhorst (3):
>   drm/i915: Make ips_enabled a property depending on whether IPS is
> enabled.
>   drm/i915: Enable IPS for sprite plane
>   drm/i915: Re-enable fastboot by default

Just a heads up to DK that this will for sure impact PSR.

PSR is enabled when we enable DDI. With fast boot that path
is usually not executed any longer so PSR will never get enabled.

Not sure about FBC and DRRS though...

Thanks,
Rodrigo.

> 
>  drivers/gpu/drm/i915/i915_params.h|  2 +-
>  drivers/gpu/drm/i915/intel_display.c  | 76 
> ---
>  drivers/gpu/drm/i915/intel_pipe_crc.c |  2 -
>  3 files changed, 36 insertions(+), 44 deletions(-)
> 
> -- 
> 2.15.0
> 
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Re: [Intel-gfx] [PATCH] Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 01:08:25AM +, Radhakrishna Sripada wrote:
> This reverts commit 8f067837c4b713ce2e69be95af7b2a5eb3bd7de8.
> 
> HSD says "WA withdrawn. It was causing corruption with some images.
> WA is not strictly necessary since this bug just causes loss of FBC
> compression with some sizes and images, but doesn't break anything."
> 

Fixes: 8f067837c4b7 ("drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk")
(added when merging)
> Cc: Rodrigo Vivi 
> Signed-off-by: Radhakrishna Sripada 

Reviewed-by: Rodrigo Vivi 
(post fact since I forgot to add this before hit push when merging :()

But I had reviewed yesterday the spec.

merged to dinq.
Thanks for the patch,
Rodrigo.

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 
>  2 files changed, 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 107e2d7c9fba..96c80fa0fcac 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2985,9 +2985,6 @@ enum i915_power_well_id {
>  #define ILK_DPFC_CHICKEN _MMIO(0x43224)
>  #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
>  #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION  (1<<23)
> -#define   GLK_SKIP_SEG_EN(1<<12)
> -#define   GLK_SKIP_SEG_COUNT_MASK(3<<10)
> -#define   GLK_SKIP_SEG_COUNT(x)  ((x)<<10)
>  #define ILK_FBC_RT_BASE  _MMIO(0x2128)
>  #define   ILK_FBC_RT_VALID   (1<<0)
>  #define   SNB_FBC_FRONT_BUFFER   (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8c69ec9eb6ee..4d2a7e4d91a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -121,7 +121,6 @@ static void bxt_init_clock_gating(struct drm_i915_private 
> *dev_priv)
>  
>  static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> - u32 val;
>   gen9_init_clock_gating(dev_priv);
>  
>   /*
> @@ -141,11 +140,6 @@ static void glk_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(CHICKEN_MISC_2, val);
>   }
>  
> - /* Display WA #1133: WaFbcSkipSegments:glk */
> - val = I915_READ(ILK_DPFC_CHICKEN);
> - val &= ~GLK_SKIP_SEG_COUNT_MASK;
> - val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> - I915_WRITE(ILK_DPFC_CHICKEN, val);
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
> @@ -8478,12 +8472,6 @@ static void cnl_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
>   val |= SARBUNIT_CLKGATE_DIS;
>   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
> -
> - /* Display WA #1133: WaFbcSkipSegments:cnl */
> - val = I915_READ(ILK_DPFC_CHICKEN);
> - val &= ~GLK_SKIP_SEG_COUNT_MASK;
> - val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> - I915_WRITE(ILK_DPFC_CHICKEN, val);
>  }
>  
>  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> -- 
> 2.9.3
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Add a policy note for removing workarounds

[Chris Wilson]

Quoting Rodrigo Vivi (2017-11-17 17:33:49)
> On Fri, Nov 17, 2017 at 11:11:28AM +, Jani Nikula wrote:
> > On Fri, 17 Nov 2017, Chris Wilson  wrote:
> > > Rodrigo gave a persuasive argument for keeping workarounds: that they
> > > serve as a good guide for the bring up of the next generation. Not only
> > > do workarounds persist into the early revisions, they show where the
> > > workarounds were previously added to the code flow and sometimes the old
> > > workarounds have an explanation that give insight into their wider
> > > implications.
> 
> Thanks! :)
> 
> > >
> > > Based on his suggestion, document the policy that we want to keep the
> > > workarounds from the current generation to guide the next. Older
> > > preproduction workarounds we still want to remove to keep the code
> > > clean.
> > >
> > > Signed-off-by: Chris Wilson 
> > > Cc: Jani Nikula 
> > > Cc: Rodrigo Vivi 
> > > Cc: Daniel Vetter 
> > 
> > Acked-by: Jani Nikula 
> > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.c | 5 +
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index 57dfaf04d819..fbfa9434c1d1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -833,6 +833,11 @@ static void i915_workqueues_cleanup(struct 
> > > drm_i915_private *dev_priv)
> > >   * We don't keep the workarounds for pre-production hardware, so we 
> > > expect our
> > >   * driver to fail on these machines in one way or another. A little 
> > > warning on
> > >   * dmesg may help both the user and the bug triagers.
> > > + *
> > > + * Our policy for removing pre-production workarounds is to keep the
> > > + * current gen workarounds as a guide to the bring-up of the next gen
> > > + * (workarounds have a habit of persisting!). Anything older than that
> > > + * should be removed along with the complications they introduce.
> > >   */
> 
> Maybe it would be good to mention that they should be at least protected
> by the REVID checks if they stay around.

Not quite sure how we want to word that. Basically it amounts to that
when we have production units and completed alpha-supported, then
sometime later we want to start tainting the pre-production sdp.
Or maybe it should be simply on completion of alpha-support those
pre-production sdp are tainted.

> But with or without this change:
> 
> Reviewed-by: Rodrigo Vivi 

Taken the simple comment, suggestions welcome.
-Chris
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Re: [Intel-gfx] [GIT PULL] gvt-next for 4.16

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 02:02:51AM +, Zhenyu Wang wrote:
> On 2017.11.16 12:20:14 -0800, Rodrigo Vivi wrote:
> > Hi Zhenyu,
> > 
> > On Thu, Nov 16, 2017 at 09:20:07AM +, Zhenyu Wang wrote:
> > > 
> > > Hi,
> > > 
> > > As we missed 4.15 cycle, here's the bigger initial 4.16 gvt-next pull,
> > > which includes many improvements as noted below.
> > > 
> > > thanks
> > > 
> > > --
> > > The following changes since commit 
> > > 34cc9efc27e2623c76a69d2ad1fa2b972e27a2c1:
> > > 
> > >   drm/i915: Remove pre-production pooled-EU w/a for Broxton (2017-11-15 
> > > 18:04:18 +)
> > > 
> > > are available in the Git repository at:
> > 
> > this capital "G" broke dim here... It took me a while to figure out what
> > was going wrong.
> > 
> > How did you generate this pull request? Why this "g" is in capital?
> >
> 
> I'm using git 2.15-rc2, so found below one.
> 
> commit e66d7c37a5f123f1dcede06ac0e11f9254c3ef46
> Author: Ann T Ropea 
> Date:   Tue Oct 3 00:08:38 2017 +
> 
> request-pull: capitalise "Git" to make it a proper noun
> 
> Of the many ways to spell the three-letter word, the variant "Git"
> should be used when referring to a repository in a description; or, in
>   general, when it is used as a proper noun.
> 
> We thus change the pull-request template message so that it reads
> 
>"...in the Git repository at:"
> 
> Besides, this brings us in line with the documentation, see
> Documentation/howto/using-signed-tag-in-pull-request.txt
> 
> Signed-off-by: Ann T Ropea 
> Acked-by: Jonathan Nieder 
> Reviewed-by: Jonathan Nieder 
> Signed-off-by: Junio C Hamano 
> 
> diff --git a/git-request-pull.sh b/git-request-pull.sh
> index eebd33276da9..13c172bd94fc 100755
> --- a/git-request-pull.sh
> +++ b/git-request-pull.sh
> @@ -128,7 +128,7 @@ git show -s --format='The following changes since commit 
> %H:
> 
>%s (%ci)
> 
> -are available in the git repository at:
> +are available in the Git repository at:

Thanks for the explanation and for finding this source.
Jani already to care of dinq so we should be fine now on ;)

Thanks,
Rodrigo.

>  ' $merge_base &&
>   echo "  $url $pretty_remote" &&
>git show -s --format='
> 
> 
> > Anyway I workarounded it here and pulled your changes into dinq.
> >
> 
> thanks!
> 
> -- 
> Open Source Technology Center, Intel ltd.
> 
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Pull the unconditional GPU 
cache invalidation into request construction
URL   : https://patchwork.freedesktop.org/series/34016/
State : warning

== Summary ==

Series 34016v1 series starting with [CI,1/2] drm/i915: Pull the unconditional 
GPU cache invalidation into request construction
https://patchwork.freedesktop.org/api/1.0/series/34016/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass   -> SKIP   (fi-hsw-4770r)

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:501s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:503s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:488s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:436s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:268s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:547s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:439s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:435s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:481s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:537s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:577s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:544s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:518s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:462s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:557s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:420s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:603s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:556s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:494s

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
1ac8466f9123 drm/i915: Automatic i915_switch_context for legacy
1a7baab4fc49 drm/i915: Pull the unconditional GPU cache invalidation into 
request construction

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7178/
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Re: [Intel-gfx] [PATCH] drm/i915: Add a policy note for removing workarounds

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 11:11:28AM +, Jani Nikula wrote:
> On Fri, 17 Nov 2017, Chris Wilson  wrote:
> > Rodrigo gave a persuasive argument for keeping workarounds: that they
> > serve as a good guide for the bring up of the next generation. Not only
> > do workarounds persist into the early revisions, they show where the
> > workarounds were previously added to the code flow and sometimes the old
> > workarounds have an explanation that give insight into their wider
> > implications.

Thanks! :)

> >
> > Based on his suggestion, document the policy that we want to keep the
> > workarounds from the current generation to guide the next. Older
> > preproduction workarounds we still want to remove to keep the code
> > clean.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Jani Nikula 
> > Cc: Rodrigo Vivi 
> > Cc: Daniel Vetter 
> 
> Acked-by: Jani Nikula 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 5 +
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 57dfaf04d819..fbfa9434c1d1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -833,6 +833,11 @@ static void i915_workqueues_cleanup(struct 
> > drm_i915_private *dev_priv)
> >   * We don't keep the workarounds for pre-production hardware, so we expect 
> > our
> >   * driver to fail on these machines in one way or another. A little 
> > warning on
> >   * dmesg may help both the user and the bug triagers.
> > + *
> > + * Our policy for removing pre-production workarounds is to keep the
> > + * current gen workarounds as a guide to the bring-up of the next gen
> > + * (workarounds have a habit of persisting!). Anything older than that
> > + * should be removed along with the complications they introduce.
> >   */

Maybe it would be good to mention that they should be at least protected
by the REVID checks if they stay around.

But with or without this change:

Reviewed-by: Rodrigo Vivi 



> >  static void intel_detect_preproduction_hw(struct drm_i915_private 
> > *dev_priv)
> >  {
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Always pin the fence for scanout on gen2/3 and primary planes

[Rodrigo Vivi]

On Fri, Nov 17, 2017 at 01:21:35PM +, Ville Syrjälä wrote:
> On Thu, Nov 16, 2017 at 12:49:23PM -0800, Rodrigo Vivi wrote:
> > On Thu, Nov 16, 2017 at 07:14:47PM +, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > The current code is trying to be lazy with fences on scanout buffers.
> > > That looks broken for several reasons:
> > > * gen2/3 always need a fence for tiled scanout
> > > * the unpin doesn't know whether we pinned the fence or not so it
> > >   may unpin something we don't own
> > > * FBC GTT tracking needs a fence (not sure we have proper fallback
> > >   for when there is no fence)
> > 
> > Ohh! I wonder if this would also solve few of old PSR cases... PSR re-uses
> > FBC GTT tracking...
> 
> That whole concept seems a bit broken. AFAICS we have no "is FBC enabled
> on the appropriate plane?" checks in the PSR code. I'm not quite sure
> how it would handle multiple planes either. I guess we should be
> disabling PSR when multiple planes are enabled?

Ironically this case is good on PSR afai can remember...
The old problem with PSR that is back to picture is just primary plane with
fbdev/fbcon... :/

> 
> > 
> > And "fallback" for both is the frontbuffer_tracking
> 
> I'm not sure how fronbuffer tracking handles GTT mmaps. I thought it
> didn't even try. If I'm mistaken then I'm thinking we should perhaps
> even stop using the GTT tracking entirely just to make the whole thing
> more consistent. Having two ways to do the same thing doesn't appeal to
> me.

Well... the frontbuffer tracking would kill the benefits of PSR2.
So if we could make that HW tracking really working I would prefer.
Otherwise we will have to have both... at least one for cases where
hw tracking works and other for the cases hw tracking doesn't work... :/

> 
> > 
> > > 
> > > So to fix this always use a fence for gen2/3, and for primary planes on
> > > other platforms (for FBC). For sprites and cursor we never need a fence
> > > so don't even try to get one.  Since we now know whether a fence was
> > > pinned we can safely unpin it too.
> > > 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
> > >  drivers/gpu/drm/i915/i915_gem.c  |  4 +--
> > >  drivers/gpu/drm/i915/intel_display.c | 55 
> > > 
> > >  drivers/gpu/drm/i915/intel_drv.h |  7 +++--
> > >  drivers/gpu/drm/i915/intel_fbdev.c   | 17 +--
> > >  drivers/gpu/drm/i915/intel_overlay.c |  2 +-
> > >  6 files changed, 66 insertions(+), 21 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 2158a758a17d..8c6d0b7ac9a5 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -3783,7 +3783,7 @@ int __must_check
> > >  i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool 
> > > write);
> > >  struct i915_vma * __must_check
> > >  i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> > > -  u32 alignment,
> > > +  u32 alignment, bool needs_fence,
> > >const struct i915_ggtt_view *view);
> > >  void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
> > >  int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > > b/drivers/gpu/drm/i915/i915_gem.c
> > > index 61ba321e9970..af18168e48e3 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -3944,7 +3944,7 @@ int i915_gem_set_caching_ioctl(struct drm_device 
> > > *dev, void *data,
> > >   */
> > >  struct i915_vma *
> > >  i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> > > -  u32 alignment,
> > > +  u32 alignment, bool needs_fence,
> > >const struct i915_ggtt_view *view)
> > >  {
> > >   struct i915_vma *vma;
> > > @@ -3997,7 +3997,7 @@ i915_gem_object_pin_to_display_plane(struct 
> > > drm_i915_gem_object *obj,
> > >* happy to scanout from anywhere within its global aperture.
> > >*/
> > >   flags = 0;
> > > - if (HAS_GMCH_DISPLAY(i915))
> > > + if (HAS_GMCH_DISPLAY(i915) || needs_fence)
> > >   flags = PIN_MAPPABLE;
> > >   vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
> > >   }
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index e6fcbc5abc75..0657e03e871a 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2154,8 +2154,21 @@ static unsigned int intel_surf_alignment(const 
> > > struct drm_framebuffer *fb,
> > >   }
> > >  }
> > >  
> > > +static bool 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure 
(rev3)
URL   : https://patchwork.freedesktop.org/series/33994/
State : success

== Summary ==

Series 33994v3 drm/i915/selftests: Report ENOMEM clearly for an allocation 
failure
https://patchwork.freedesktop.org/api/1.0/series/33994/revisions/3/mbox/

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:384s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:283s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:505s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:505s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:501s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:501s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:269s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:439s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:427s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:476s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:529s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:577s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:549s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:523s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:573s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:426s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:617s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:490s
fi-skl-gvtdvm failed to collect. IGT log at Patchwork_7177/fi-skl-gvtdvm/igt.log

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
4d66c66f8292 drm/i915/selftests: Report ENOMEM clearly for an allocation failure

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7177/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure 
(rev2)
URL   : https://patchwork.freedesktop.org/series/33994/
State : success

== Summary ==

Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
skip   -> PASS   (shard-hsw) fdo#102249
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
skip   -> PASS   (shard-hsw) fdo#103167
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-fencing:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-pipe-a-planes:
skip   -> PASS   (shard-hsw)

fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2585 pass:1473 dwarn:2   dfail:1   fail:10  skip:1099 
time:9501s
shard-snbtotal:2585 pass:1261 dwarn:1   dfail:1   fail:11  skip:1311 
time:7973s
Blacklisted hosts:
shard-apltotal:2585 pass:1624 dwarn:1   dfail:1   fail:23  skip:936 
time:13424s
shard-kbltotal:2565 pass:1702 dwarn:4   dfail:0   fail:24  skip:834 
time:10499s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7174/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Pull the unconditional GPU cache invalidation into request construction (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Pull the unconditional GPU cache invalidation into request 
construction (rev2)
URL   : https://patchwork.freedesktop.org/series/34007/
State : warning

== Summary ==

Series 34007v2 drm/i915: Pull the unconditional GPU cache invalidation into 
request construction
https://patchwork.freedesktop.org/api/1.0/series/34007/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> SKIP   (fi-hsw-4770r)

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:458s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:531s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:509s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:486s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:264s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:439s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:427s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:484s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:532s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:573s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:545s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:501s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:457s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:559s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:423s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:608s
fi-glk-dsi   total:289  pass:165  dwarn:0   dfail:10  fail:2   skip:112 
time:426s
fi-cnl-y failed to connect after reboot

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
6da581cf9624 drm/i915: Pull the unconditional GPU cache invalidation into 
request construction

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7176/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable fastboot, v2!

[Patchwork]

== Series Details ==

Series: drm/i915: Enable fastboot, v2!
URL   : https://patchwork.freedesktop.org/series/34010/
State : success

== Summary ==

Series 34010v1 drm/i915: Enable fastboot, v2!
https://patchwork.freedesktop.org/api/1.0/series/34010/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:457s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:499s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:490s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:426s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:271s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:424s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:487s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:541s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:578s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:541s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:458s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:561s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:419s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:615s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:494s

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
f8d72017605a drm/i915: Re-enable fastboot by default
d8f81e71499f drm/i915: Enable IPS for sprite plane
faa673850459 drm/i915: Make ips_enabled a property depending on whether IPS is 
enabled.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7175/
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[Intel-gfx] [PATCH v5] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

[Chris Wilson]

If we can not run the drunk_hole test because we couldn't allocate the
memory for the permutation array (even after we tried trimming the
size), report a clear ENOMEM. Similary, if we are asked to operate on a
hole too small for ourselves, make it skip quietly.

v2: Avoid malloc(0) since that returns ZERO_SIZE_PTR not NULL.
v3: Fixup similar construction for lowlevel_hole
v4: Use u64 >> 1 to avoid 64b div.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20171117101732.4335-1-ch...@chris-wilson.co.uk
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 36 +++
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 3dcf886a2802..6491cf0a4f46 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -216,13 +216,21 @@ static int lowlevel_hole(struct drm_i915_private *i915,
hole_size = (hole_end - hole_start) >> size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
-   count = hole_size;
+   count = hole_size >> 1;
+   if (!count) {
+   pr_debug("%s: hole is too small [%llx - %llx] >> %d: 
%lld\n",
+__func__, hole_start, hole_end, size, 
hole_size);
+   break;
+   }
+
do {
-   count >>= 1;
order = i915_random_order(count, );
-   } while (!order && count);
-   if (!order)
-   break;
+   if (order)
+   break;
+   } while (count >>= 1);
+   if (!count)
+   return -ENOMEM;
+   GEM_BUG_ON(!order);
 
GEM_BUG_ON(count * BIT_ULL(size) > vm->total);
GEM_BUG_ON(hole_start + count * BIT_ULL(size) > hole_end);
@@ -704,13 +712,21 @@ static int drunk_hole(struct drm_i915_private *i915,
hole_size = (hole_end - hole_start) >> size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
-   count = hole_size;
+   count = hole_size >> 1;
+   if (!count) {
+   pr_debug("%s: hole is too small [%llx - %llx] >> %d: 
%lld\n",
+__func__, hole_start, hole_end, size, 
hole_size);
+   break;
+   }
+
do {
-   count >>= 1;
order = i915_random_order(count, );
-   } while (!order && count);
-   if (!order)
-   break;
+   if (order)
+   break;
+   } while (count >>= 1);
+   if (!count)
+   return -ENOMEM;
+   GEM_BUG_ON(!order);
 
/* Ignore allocation failures (i.e. don't report them as
 * a test failure) as we are purposefully allocating very
-- 
2.15.0

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[Intel-gfx] [CI 2/2] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 1/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure 
(rev2)
URL   : https://patchwork.freedesktop.org/series/33994/
State : success

== Summary ==

Series 33994v2 drm/i915/selftests: Report ENOMEM clearly for an allocation 
failure
https://patchwork.freedesktop.org/api/1.0/series/33994/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:443s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:458s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:531s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:279s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:499s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:490s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:433s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:487s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:536s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:575s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:544s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:495s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:563s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:425s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:615s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:492s

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
4f00ec50a95b drm/i915/selftests: Report ENOMEM clearly for an allocation failure

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7174/
___
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[Intel-gfx] [CI] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Expose more GPU properties through sysfs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Expose more GPU properties through sysfs (rev2)
URL   : https://patchwork.freedesktop.org/series/33950/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
skip   -> PASS   (shard-hsw) fdo#103167
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
skip   -> PASS   (shard-hsw) fdo#102249
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-fencing:
skip   -> PASS   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-pipe-a-planes:
skip   -> PASS   (shard-hsw)
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS   (shard-hsw) fdo#102707

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707

shard-hswtotal:2585 pass:1474 dwarn:1   dfail:1   fail:10  skip:1099 
time:9416s
shard-snbtotal:2585 pass:1261 dwarn:1   dfail:1   fail:11  skip:1311 
time:8006s
Blacklisted hosts:
shard-apltotal:2585 pass:1620 dwarn:1   dfail:2   fail:25  skip:937 
time:13244s
shard-kbltotal:2565 pass:1700 dwarn:3   dfail:1   fail:27  skip:833 
time:10626s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7171/shards.html
___
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Re: [Intel-gfx] [CI] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

Quoting Chris Wilson (2017-11-17 15:23:58)
> @@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
> /* Unconditionally flush any chipset caches (for streaming writes). */
> i915_gem_chipset_flush(eb->i915);
>  
> -   /* Unconditionally invalidate GPU caches and TLBs. */
> -   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
> +   return true;

Oh, idiot at the keyboard again.
-Chris
___
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

[Matthew Auld]

On 17 November 2017 at 15:31, Chris Wilson  wrote:
> If we can not run the drunk_hole test because we couldn't allocate the
> memory for the permutation array (even after we tried trimming the
> size), report a clear ENOMEM. Similary, if we are asked to operate on a
> hole too small for ourselves, make it skip quietly.
>
> v2: Avoid malloc(0) since that returns ZERO_SIZE_PTR not NULL.
> v3: Fixup similar construction for lowlevel_hole
>
> Signed-off-by: Chris Wilson 
> Cc: Matthew Auld 
> Cc: Mika Kuoppala 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20171117101732.4335-1-ch...@chris-wilson.co.uk
> Reviewed-by: Matthew Auld  #v1
> ---
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 36 
> +++
>  1 file changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 3dcf886a2802..ca83c51b8cac 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -216,13 +216,21 @@ static int lowlevel_hole(struct drm_i915_private *i915,
> hole_size = (hole_end - hole_start) >> size;
> if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
> hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
> -   count = hole_size;
> +   count = hole_size / 2;
Oh wait, we need div_u64(), or maybe just hole_size >> 1...
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Pull the unconditional GPU 
cache invalidation into request construction
URL   : https://patchwork.freedesktop.org/series/34008/
State : failure

== Summary ==

Series 34008v1 series starting with [CI,1/2] drm/i915: Pull the unconditional 
GPU cache invalidation into request construction
https://patchwork.freedesktop.org/api/1.0/series/34008/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163 +2
Test gem_busy:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
Subgroup basic-hang-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6600u)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900) fdo#102657 +2
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
Test gem_ctx_exec:
Subgroup basic:
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Test gem_exec_fence:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

[Matthew Auld]

On 17 November 2017 at 15:31, Chris Wilson  wrote:
> If we can not run the drunk_hole test because we couldn't allocate the
> memory for the permutation array (even after we tried trimming the
> size), report a clear ENOMEM. Similary, if we are asked to operate on a
> hole too small for ourselves, make it skip quietly.
>
> v2: Avoid malloc(0) since that returns ZERO_SIZE_PTR not NULL.
> v3: Fixup similar construction for lowlevel_hole
>
> Signed-off-by: Chris Wilson 
> Cc: Matthew Auld 
> Cc: Mika Kuoppala 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20171117101732.4335-1-ch...@chris-wilson.co.uk
Reviewed-by: Matthew Auld 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Enable IPS for sprite plane

[Ville Syrjälä]

On Fri, Nov 17, 2017 at 04:37:55PM +0100, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 8283e80597bd..38a1cdb3dbb2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5044,7 +5044,7 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   intel_fbc_post_update(crtc);
>  
>   if (primary_state->base.visible &&
> - (needs_modeset(_config->base) ||
> + (pipe_config->disable_cxsr ||
>!old_primary_state->base.visible))
>   intel_post_enable_primary(>base, pipe_config);
>   }
> @@ -5064,7 +5064,7 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   struct intel_atomic_state *old_intel_state =
>   to_intel_atomic_state(old_state);
>  
> - if (needs_modeset(_config->base) || !pipe_config->ips_enabled)
> + if (pipe_config->disable_cxsr || !pipe_config->ips_enabled)

What does IPS have to do with cxsr?

>   hsw_disable_ips(old_crtc_state);
>  
>   if (old_pri_state) {
> @@ -6224,12 +6224,11 @@ static bool pipe_config_supports_ips(struct 
> drm_i915_private *dev_priv,
>   visible_planes = pipe_config->active_planes & ~BIT(PLANE_CURSOR);
>  
>   /*
> -  * FIXME IPS should be fine as long as one plane is
> -  * enabled, but in practice it seems to have problems
> -  * when going from primary only to sprite only and vice
> -  * versa.
> +  * IPS should be fine as long as one plane is enabled, but
> +  * temporarily disable it when when going from primary only
> +  * to sprite only and vice versa.
>*/
> - if (visible_planes != BIT(PLANE_PRIMARY))
> + if (hweight32(visible_planes) != 1)
>   return false;

That should just be
if (active_planes == 0)
return false;

assuming we have no problems with the toggling between
primary only and sprite only.

I can't recall how the cursor affecrs IPS. But I think IPS should 
work as long as any plane (including the cursor) is enabled.

>  
>   /* HSW can handle pixel rate up to cdclk? */
> -- 
> 2.15.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Patchwork]

== Series Details ==

Series: drm/i915: Pull the unconditional GPU cache invalidation into request 
construction
URL   : https://patchwork.freedesktop.org/series/34007/
State : failure

== Summary ==

Series 34007v1 drm/i915: Pull the unconditional GPU cache invalidation into 
request construction
https://patchwork.freedesktop.org/api/1.0/series/34007/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163 +2
Test gem_busy:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-bxt-dsi)
Subgroup basic-hang-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900) fdo#102657 +2
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
Test gem_ctx_exec:
Subgroup basic:
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Test gem_exec_fence:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> 

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Make ips_enabled a property depending on whether IPS is enabled.

[Ville Syrjälä]

On Fri, Nov 17, 2017 at 04:37:54PM +0100, Maarten Lankhorst wrote:
> ips_enabled was used as a variable of whether IPS can be enabled or not,
> but should be used to test whether IPS is actually enabled.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_display.c  | 75 
> ---
>  drivers/gpu/drm/i915/intel_pipe_crc.c |  2 -
>  2 files changed, 35 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 3b3dec1e6640..8283e80597bd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4870,7 +4870,7 @@ void hsw_enable_ips(const struct intel_crtc_state 
> *crtc_state)
>   struct drm_device *dev = crtc->base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - if (!crtc->config->ips_enabled)
> + if (!crtc_state->ips_enabled)
>   return;
>  
>   /*
> @@ -4966,14 +4966,6 @@ intel_post_enable_primary(struct drm_crtc *crtc,
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   int pipe = intel_crtc->pipe;
>  
> - /*
> -  * FIXME IPS should be fine as long as one plane is
> -  * enabled, but in practice it seems to have problems
> -  * when going from primary only to sprite only and vice
> -  * versa.
> -  */
> - hsw_enable_ips(new_crtc_state);
> -
>   /*
>* Gen2 reports pipe underruns whenever all planes are disabled.
>* So don't enable underrun reporting before at least some planes
> @@ -4989,10 +4981,9 @@ intel_post_enable_primary(struct drm_crtc *crtc,
>   intel_check_pch_fifo_underruns(dev_priv);
>  }
>  
> -/* FIXME move all this to pre_plane_update() with proper state tracking */
> +/* FIXME get rid of this and use pre_plane_update */
>  static void
> -intel_pre_disable_primary(struct drm_crtc *crtc,
> -   const struct intel_crtc_state *old_crtc_state)
> +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>  {
>   struct drm_device *dev = crtc->dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -5001,32 +4992,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc,
>  
>   /*
>* Gen2 reports pipe underruns whenever all planes are disabled.
> -  * So diasble underrun reporting before all the planes get disabled.
> -  * FIXME: Need to fix the logic to work when we turn off all planes
> -  * but leave the pipe running.
> +  * So disable underrun reporting before all the planes get disabled.
>*/
>   if (IS_GEN2(dev_priv))
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> - /*
> -  * FIXME IPS should be fine as long as one plane is
> -  * enabled, but in practice it seems to have problems
> -  * when going from primary only to sprite only and vice
> -  * versa.
> -  */
> - hsw_disable_ips(old_crtc_state);
> -}
> -
> -/* FIXME get rid of this and use pre_plane_update */
> -static void
> -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> -
> - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));
> + hsw_disable_ips(to_intel_crtc_state(crtc->state));

BTW thinking about the lack of readout on BDW. In case the BIOS ever
enables IPS, I think we should sanitize ips_enabled to true on BDW.
Or maybe just have the redaout code always set ips_enabled=true on BDW?
That way the first modeset will try to turn it off regardless of whether it
was enabled or not.

>  
>   /*
>* Vblank time updates from the shadow to live plane control register
> @@ -5058,6 +5029,11 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   if (pipe_config->update_wm_post && pipe_config->base.active)
>   intel_update_watermarks(crtc);
>  
> + if (!old_crtc_state->ips_enabled ||
> + needs_modeset(_crtc_state->base) ||

Shoudldn't that be needs_modeset(new_crtc_state)?

> + pipe_config->update_pipe)

Why do we have to check that?

> + hsw_enable_ips(pipe_config);
> +
>   if (old_pri_state) {
>   struct intel_plane_state *primary_state =
>   
> intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
> @@ -5088,6 +5064,9 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   struct intel_atomic_state *old_intel_state =
>   to_intel_atomic_state(old_state);
>  
> + if (needs_modeset(_config->base) || !pipe_config->ips_enabled)
> + hsw_disable_ips(old_crtc_state);
> +
>   if (old_pri_state) {
>   struct intel_plane_state *primary_state =
> 

Re: [Intel-gfx] [PATCH v5 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[Ville Syrjälä]

On Thu, Nov 16, 2017 at 03:21:32PM -0800, James Ausmus wrote:
> On Mon, Oct 23, 2017 at 05:50:32PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Rename enum plane to enum i9xx_plane_id to make it clear that it only
> > applies to pre-SKL platforms.
> > 
> > enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> > per-pipe. We need the old global identifier to index the primary plane
> > (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> > platforms.
> > 
> > v2: Reorder patches
> > v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> > Pimp the commit message a bit
> > Note that i9xx_plane_id doesn't apply to SKL+
> > v4: Rebase due to power domain handling in plane readout
> > v5: Rebase due to crtc->dspaddr_offset removal
> > 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
> >  drivers/gpu/drm/i915/intel_display.c | 87 
> > ++--
> >  drivers/gpu/drm/i915/intel_drv.h |  6 +--
> >  3 files changed, 49 insertions(+), 50 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 54b5d4c582b6..a6b912c646f9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -305,9 +305,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> > transcoder)
> >  
> >  /*
> >   * Global legacy plane identifier. Valid only for primary/sprite
> > - * planes on pre-g4x, and only for primary planes on g4x+.
> > + * planes on pre-g4x, and only for primary planes on g4x-bdw.
> >   */
> > -enum plane {
> > +enum i9xx_plane_id {
> > PLANE_A,
> > PLANE_B,
> > PLANE_C,
> > @@ -1137,7 +1137,7 @@ struct intel_fbc {
> >  
> > struct {
> > enum pipe pipe;
> > -   enum plane plane;
> > +   enum i9xx_plane_id plane;
> > unsigned int fence_y_offset;
> > } crtc;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 4ea0f1ef249e..e726b65588aa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3223,16 +3223,16 @@ int i9xx_check_plane_surface(struct 
> > intel_plane_state *plane_state)
> > return 0;
> >  }
> >  
> > -static void i9xx_update_primary_plane(struct intel_plane *primary,
> > - const struct intel_crtc_state *crtc_state,
> > - const struct intel_plane_state 
> > *plane_state)
> > +static void i9xx_update_plane(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state,
> > + const struct intel_plane_state *plane_state)
> >  {
> > -   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > +   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > -   enum plane plane = primary->plane;
> > +   enum i9xx_plane_id plane_id = plane->plane;
> 
> It feels a bit ugly and counter-intuitive to have the two "plane"s in
> "plane->plane"

It's always been like that. Well, ever since we had planes.
Nothing new there. At least I got rid of the magic
'plane->plane + 1' from the sprite code.

> be different types - since i9xx_plane_id is a global id,
> would it make sense to change the member naming to plane_gid or some

"gid" would confuse me more. It makes me think of uid/gid. We could name
it to plane->i9xx_plane[_id] I suppose to match the type.

> such (both in struct intel_plane and in struct intel_fbc->crtc)?

The fbc mess is going away thankfully. At which point the uses of
i9xx_plane_id will be tucked away neatly in platform specific code
instead of leaking too badly to common code.

> It
> feels like struct intel_plane should continue to be "plane", but we need
> something else for enum i9xx_plane_id just for clarity's sake.

This is I think the third attempt at coming up with something.

I might just have to rename plane->plane to plane->bikeshed to more
accurately reflect its role in i915 development ;)

> 
> > u32 linear_offset;
> > u32 dspcntr = plane_state->ctl;
> > -   i915_reg_t reg = DSPCNTR(plane);
> > +   i915_reg_t reg = DSPCNTR(plane_id);
> > int x = plane_state->main.x;
> > int y = plane_state->main.y;
> > unsigned long irqflags;
> > @@ -3251,34 +3251,34 @@ static void i9xx_update_primary_plane(struct 
> > intel_plane *primary,
> > /* pipesrc and dspsize control the size that is scaled from,
> >  * which should always be the user's requested size.
> >  */
> > -   I915_WRITE_FW(DSPSIZE(plane),
> > +   I915_WRITE_FW(DSPSIZE(plane_id),
> >   ((crtc_state->pipe_src_h - 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose more GPU properties through sysfs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Expose more GPU properties through sysfs (rev2)
URL   : https://patchwork.freedesktop.org/series/33950/
State : success

== Summary ==

Series 33950v2 drm/i915: Expose more GPU properties through sysfs
https://patchwork.freedesktop.org/api/1.0/series/33950/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:460s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:379s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:532s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:280s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:498s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:430s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:473s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:535s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:482s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:577s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:541s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:495s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:464s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:422s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:606s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:542s
fi-glk-dsi   total:27   pass:17   dwarn:0   dfail:0   fail:0   skip:9  

ed17259c4b681ddc178c14368f1a3db512016989 drm-tip: 2017y-11m-17d-12h-03m-24s UTC 
integration manifest
5f20cff14741 drm/i915: expose EU topology through sysfs
3d52bbd7f926 drm/i915: expose engine availability through sysfs
93167529e555 drm/i915/debugfs: reuse max slice/subslices already stored in sseu
82458d6ac063 drm/i915: store all subslice masks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7171/
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[Intel-gfx] [PATCH 0/3] drm/i915: Enable fastboot, v2!

[Maarten Lankhorst]

Small fixes for IPS, and then we flip the switch! :-)

Maarten Lankhorst (3):
  drm/i915: Make ips_enabled a property depending on whether IPS is
enabled.
  drm/i915: Enable IPS for sprite plane
  drm/i915: Re-enable fastboot by default

 drivers/gpu/drm/i915/i915_params.h|  2 +-
 drivers/gpu/drm/i915/intel_display.c  | 76 ---
 drivers/gpu/drm/i915/intel_pipe_crc.c |  2 -
 3 files changed, 36 insertions(+), 44 deletions(-)

-- 
2.15.0

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[Intel-gfx] [PATCH 1/3] drm/i915: Make ips_enabled a property depending on whether IPS is enabled.

[Maarten Lankhorst]

ips_enabled was used as a variable of whether IPS can be enabled or not,
but should be used to test whether IPS is actually enabled.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c  | 75 ---
 drivers/gpu/drm/i915/intel_pipe_crc.c |  2 -
 2 files changed, 35 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3b3dec1e6640..8283e80597bd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4870,7 +4870,7 @@ void hsw_enable_ips(const struct intel_crtc_state 
*crtc_state)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
 
-   if (!crtc->config->ips_enabled)
+   if (!crtc_state->ips_enabled)
return;
 
/*
@@ -4966,14 +4966,6 @@ intel_post_enable_primary(struct drm_crtc *crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
 
-   /*
-* FIXME IPS should be fine as long as one plane is
-* enabled, but in practice it seems to have problems
-* when going from primary only to sprite only and vice
-* versa.
-*/
-   hsw_enable_ips(new_crtc_state);
-
/*
 * Gen2 reports pipe underruns whenever all planes are disabled.
 * So don't enable underrun reporting before at least some planes
@@ -4989,10 +4981,9 @@ intel_post_enable_primary(struct drm_crtc *crtc,
intel_check_pch_fifo_underruns(dev_priv);
 }
 
-/* FIXME move all this to pre_plane_update() with proper state tracking */
+/* FIXME get rid of this and use pre_plane_update */
 static void
-intel_pre_disable_primary(struct drm_crtc *crtc,
- const struct intel_crtc_state *old_crtc_state)
+intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
 {
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5001,32 +4992,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc,
 
/*
 * Gen2 reports pipe underruns whenever all planes are disabled.
-* So diasble underrun reporting before all the planes get disabled.
-* FIXME: Need to fix the logic to work when we turn off all planes
-* but leave the pipe running.
+* So disable underrun reporting before all the planes get disabled.
 */
if (IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-   /*
-* FIXME IPS should be fine as long as one plane is
-* enabled, but in practice it seems to have problems
-* when going from primary only to sprite only and vice
-* versa.
-*/
-   hsw_disable_ips(old_crtc_state);
-}
-
-/* FIXME get rid of this and use pre_plane_update */
-static void
-intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
-{
-   struct drm_device *dev = crtc->dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   int pipe = intel_crtc->pipe;
-
-   intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));
+   hsw_disable_ips(to_intel_crtc_state(crtc->state));
 
/*
 * Vblank time updates from the shadow to live plane control register
@@ -5058,6 +5029,11 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
if (pipe_config->update_wm_post && pipe_config->base.active)
intel_update_watermarks(crtc);
 
+   if (!old_crtc_state->ips_enabled ||
+   needs_modeset(_crtc_state->base) ||
+   pipe_config->update_pipe)
+   hsw_enable_ips(pipe_config);
+
if (old_pri_state) {
struct intel_plane_state *primary_state =

intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
@@ -5088,6 +5064,9 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
 
+   if (needs_modeset(_config->base) || !pipe_config->ips_enabled)
+   hsw_disable_ips(old_crtc_state);
+
if (old_pri_state) {
struct intel_plane_state *primary_state =
intel_atomic_get_new_plane_state(old_intel_state,
@@ -5096,10 +5075,13 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
to_intel_plane_state(old_pri_state);
 
intel_fbc_pre_update(crtc, pipe_config, primary_state);
-
-   if (old_primary_state->base.visible &&
+   /*
+* Gen2 reports pipe underruns whenever all planes are disabled.
+* So disable underrun reporting before all the planes get 
disabled.
+ 

[Intel-gfx] [PATCH 2/3] drm/i915: Enable IPS for sprite plane

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8283e80597bd..38a1cdb3dbb2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5044,7 +5044,7 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
intel_fbc_post_update(crtc);
 
if (primary_state->base.visible &&
-   (needs_modeset(_config->base) ||
+   (pipe_config->disable_cxsr ||
 !old_primary_state->base.visible))
intel_post_enable_primary(>base, pipe_config);
}
@@ -5064,7 +5064,7 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
 
-   if (needs_modeset(_config->base) || !pipe_config->ips_enabled)
+   if (pipe_config->disable_cxsr || !pipe_config->ips_enabled)
hsw_disable_ips(old_crtc_state);
 
if (old_pri_state) {
@@ -6224,12 +6224,11 @@ static bool pipe_config_supports_ips(struct 
drm_i915_private *dev_priv,
visible_planes = pipe_config->active_planes & ~BIT(PLANE_CURSOR);
 
/*
-* FIXME IPS should be fine as long as one plane is
-* enabled, but in practice it seems to have problems
-* when going from primary only to sprite only and vice
-* versa.
+* IPS should be fine as long as one plane is enabled, but
+* temporarily disable it when when going from primary only
+* to sprite only and vice versa.
 */
-   if (visible_planes != BIT(PLANE_PRIMARY))
+   if (hweight32(visible_planes) != 1)
return false;
 
/* HSW can handle pixel rate up to cdclk? */
-- 
2.15.0

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[Intel-gfx] [(resend) PATCH 3/3] drm/i915: Re-enable fastboot by default

[Maarten Lankhorst]

This fix was originally reverted because it left a chromebook pixel
black, and no immediate fix was available. This has been fixed in the
meantime.

Rather than trying to remove the parameter, set it to default to true
for now, so we can always back out if required.

Signed-off-by: Maarten Lankhorst 
Cc: Jani Nikula 
Cc: Daniel Vetter 
Testcase: kms_panel_fitting
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c7292268ed43..b99cb58801e6 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -57,7 +57,7 @@
param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
param(bool, enable_cmd_parser, true) \
param(bool, enable_hangcheck, true) \
-   param(bool, fastboot, false) \
+   param(bool, fastboot, true) \
param(bool, prefault_disable, false) \
param(bool, load_detect_test, false) \
param(bool, force_reset_modeset_test, false) \
-- 
2.15.0

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[Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

[Chris Wilson]

If we can not run the drunk_hole test because we couldn't allocate the
memory for the permutation array (even after we tried trimming the
size), report a clear ENOMEM. Similary, if we are asked to operate on a
hole too small for ourselves, make it skip quietly.

v2: Avoid malloc(0) since that returns ZERO_SIZE_PTR not NULL.
v3: Fixup similar construction for lowlevel_hole

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Mika Kuoppala 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20171117101732.4335-1-ch...@chris-wilson.co.uk
Reviewed-by: Matthew Auld  #v1
---
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 36 +++
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 3dcf886a2802..ca83c51b8cac 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -216,13 +216,21 @@ static int lowlevel_hole(struct drm_i915_private *i915,
hole_size = (hole_end - hole_start) >> size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
-   count = hole_size;
+   count = hole_size / 2;
+   if (!count) {
+   pr_debug("%s: hole is too small [%llx - %llx] >> %d: 
%lld\n",
+__func__, hole_start, hole_end, size, 
hole_size);
+   break;
+   }
+
do {
-   count >>= 1;
order = i915_random_order(count, );
-   } while (!order && count);
-   if (!order)
-   break;
+   if (order)
+   break;
+   } while (count >>= 1);
+   if (!count)
+   return -ENOMEM;
+   GEM_BUG_ON(!order);
 
GEM_BUG_ON(count * BIT_ULL(size) > vm->total);
GEM_BUG_ON(hole_start + count * BIT_ULL(size) > hole_end);
@@ -704,13 +712,21 @@ static int drunk_hole(struct drm_i915_private *i915,
hole_size = (hole_end - hole_start) >> size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
-   count = hole_size;
+   count = hole_size / 2;
+   if (!count) {
+   pr_debug("%s: hole is too small [%llx - %llx] >> %d: 
%lld\n",
+__func__, hole_start, hole_end, size, 
hole_size);
+   break;
+   }
+
do {
-   count >>= 1;
order = i915_random_order(count, );
-   } while (!order && count);
-   if (!order)
-   break;
+   if (order)
+   break;
+   } while (count >>= 1);
+   if (!count)
+   return -ENOMEM;
+   GEM_BUG_ON(!order);
 
/* Ignore allocation failures (i.e. don't report them as
 * a test failure) as we are purposefully allocating very
-- 
2.15.0

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[Intel-gfx] [CI 2/2] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 87a8dabd770a..28e647042908 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 1/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..87a8dabd770a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return true;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] [CI] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..87a8dabd770a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return true;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

[Lionel Landwerlin]

On 17/11/17 10:53, Chris Wilson wrote:

Quoting Lionel Landwerlin (2017-11-16 16:00:03)

With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because signals need to be accounted properly based on whether part of
the GPU has been fused off. The current aggregated numbers like
EU_TOTAL do not gives us sufficient information.

Here is the sysfs layout on a Skylake GT4 :

/sys/devices/pci:00/:00:02.0/drm/card0/topology/

Ok, bikeshedding time!

We already use topology in conjunction with DP-MST, so at a toplevel
this would be confusing.

I would start with a gt/ dir for all of this info.

Is this subslicing only for the render unit; are all platforms going to
have the same fusing across all units? At the least, I thought we would
be able to configure the powergating of the different slices on the
different units. It seems a logical extension that fusing would be
similar.
-Chris


I just realized that 'enabled_mask' might not be future proof enough.
We might want to expose other fusing information in the slices/subslices...
I might rename that to enabled_slices/enabled_subslices/enabled_eus in a v3.

-
Lionel
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[Intel-gfx] [PATCH v2 4/4] drm/i915: expose EU topology through sysfs

[Lionel Landwerlin]

With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because signals need to be accounted properly based on whether part of
the GPU has been fused off. The current aggregated numbers like
EU_TOTAL do not gives us sufficient information.

Here is the sysfs layout on a Skylake GT4 :

/sys/devices/pci:00/:00:02.0/drm/card0/gt/rcs/0/
├── capabilities
├── class
├── enabled_mask
├── id
├── max_eus_per_subslice
├── max_slices
├── max_subslices_per_slice
├── slice0
│   ├── enabled_mask
│   ├── subslice0
│   │   └── enabled_mask
│   ├── subslice1
│   │   └── enabled_mask
│   ├── subslice2
│   │   └── enabled_mask
│   └── subslice3
│   └── enabled_mask
├── slice1
│   ├── enabled_mask
│   ├── subslice0
│   │   └── enabled_mask
│   ├── subslice1
│   │   └── enabled_mask
│   ├── subslice2
│   │   └── enabled_mask
│   └── subslice3
│   └── enabled_mask
└── slice2
├── enabled_mask
├── subslice0
│   └── enabled_mask
├── subslice1
│   └── enabled_mask
├── subslice2
│   └── enabled_mask
└── subslice3
└── enabled_mask

Each enabled_mask file gives us a mask of the enabled units :

$ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/rcs/0/enabled_mask
0x7

$ cat 
/sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/rcs/0/slice0/subslice2/enabled_mask
0xff

v2: Move topology below rcs engine (Chris)
Add max_eus_per_subslice (Lionel)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h   |  26 ++
 drivers/gpu/drm/i915/i915_sysfs.c | 175 ++
 2 files changed, 201 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22ac96d2ef42..8591c4f7cca3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2259,6 +2259,24 @@ struct intel_cdclk_state {
u8 voltage_level;
 };
 
+struct intel_topology_kobject {
+   struct kobject kobj;
+   struct drm_i915_private *dev_priv;
+};
+
+struct intel_slice_kobject {
+   struct kobject kobj;
+   struct drm_i915_private *dev_priv;
+   u8 slice_index;
+};
+
+struct intel_subslice_kobject {
+   struct kobject kobj;
+   struct drm_i915_private *dev_priv;
+   u8 slice_index;
+   u8 subslice_index;
+};
+
 struct drm_i915_private {
struct drm_device drm;
 
@@ -2732,6 +2750,14 @@ struct drm_i915_private {
struct {
struct kobject kobj;
struct kobject classes_kobjs[MAX_ENGINE_CLASS];
+
+   struct sysfs_slice {
+   struct intel_slice_kobject kobj;
+
+   struct sysfs_subslice {
+   struct intel_subslice_kobject kobj;
+   } subslices[GEN_MAX_SUBSLICES];
+   } slices[GEN_MAX_SLICES];
} gt_topology;
 
/* Abstract the submission mechanism (legacy ringbuffer or execlists) 
away */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index fd04d0b93eaf..1ce5bf19 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -559,6 +559,161 @@ static void i915_setup_error_capture(struct device *kdev) 
{}
 static void i915_teardown_error_capture(struct device *kdev) {}
 #endif
 
+static struct attribute mask_attr = {
+   .name = "enabled_mask",
+   .mode = 0444,
+};
+
+static struct attribute max_slices_attr = {
+   .name = "max_slices",
+   .mode = 0444,
+};
+
+static struct attribute max_subslices_per_slice_attr = {
+   .name = "max_subslices_per_slice",
+   .mode = 0444,
+};
+
+static struct attribute max_eus_per_subslice_attr = {
+   .name = "max_eus_per_subslice",
+   .mode = 0444,
+};
+
+static ssize_t
+show_slice_attr(struct kobject *kobj, struct attribute *attr, char *buf)
+{
+   struct intel_slice_kobject *kobj_wrapper =
+   container_of(kobj, struct intel_slice_kobject, kobj);
+   struct drm_i915_private *dev_priv = kobj_wrapper->dev_priv;
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+
+   if (attr == _attr) {
+   return sprintf(buf, "0x%hhx\n",
+  sseu->subslices_mask[kobj_wrapper->slice_index]);
+   }
+
+   return sprintf(buf, "0x0\n");
+}
+
+static const struct sysfs_ops slice_ops = {
+   .show = show_slice_attr,
+};
+
+static struct kobj_type slice_type = {
+   .sysfs_ops = _ops,
+};
+
+static ssize_t
+show_subslice_attr(struct kobject *kobj, struct attribute *attr, char *buf)
+{
+   struct intel_subslice_kobject *kobj_wrapper =
+   container_of(kobj, struct intel_subslice_kobject, kobj);
+   struct drm_i915_private *dev_priv = 

[Intel-gfx] [PATCH v2 2/4] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

[Lionel Landwerlin]

Now that we have that information in topology fields, let's just reused it.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3cc0f383b058..4dea1829c4d4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4492,11 +4492,11 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 struct sseu_dev_info *sseu)
 {
const struct intel_device_info *info = INTEL_INFO(dev_priv);
-   int s_max = 6, ss_max = 4;
int s, ss;
-   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+   u32 s_reg[info->sseu.max_slices],
+   eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
/*
 * FIXME: Valid SS Mask respects the spec and read
 * only valid bits for those registers, excluding reserverd
@@ -4518,7 +4518,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4526,7 +4526,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
sseu->subslices_mask[s] = info->sseu.subslices_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
@@ -4546,17 +4546,11 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
-   int s_max = 3, ss_max = 4;
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
int s, ss;
-   u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
-   /* BXT has a single slice and at most 3 subslices. */
-   if (IS_GEN9_LP(dev_priv)) {
-   s_max = 1;
-   ss_max = 3;
-   }
+   u32 s_reg[info->sseu.max_slices], eu_reg[2*info->sseu.max_subslices], 
eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4571,7 +4565,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4582,7 +4576,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->subslices_mask[s] =
INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (IS_GEN9_LP(dev_priv)) {
-- 
2.15.0

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[Intel-gfx] [PATCH v2 3/4] drm/i915: expose engine availability through sysfs

[Lionel Landwerlin]

This enables userspace to discover the engines available on the GPU.
Here is the layout on a Skylake GT4:

/sys/devices/pci:00/:00:02.0/drm/card0/gt
├── bcs
│   └── 0
│   ├── capabilities
│   ├── class
│   └── id
├── rcs
│   └── 0
│   ├── capabilities
│   ├── class
│   └── id
├── vcs
│   ├── 0
│   │   ├── capabilities
│   │   │   └── hevc
│   │   ├── class
│   │   └── id
│   └── 1
│   ├── capabilities
│   ├── class
│   └── id
└── vecs
└── 0
├── capabilities
├── class
└── id

Further capabilities can be added later as attributes of each engine.

v2: Add capabilities sub directory (Tvrtko)
Move engines directory to drm/card/gt (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |   5 +
 drivers/gpu/drm/i915/i915_reg.h |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c   | 160 
 drivers/gpu/drm/i915/intel_engine_cs.c  |  12 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h |   4 +
 5 files changed, 182 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8d239d8bfab..22ac96d2ef42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2729,6 +2729,11 @@ struct drm_i915_private {
} oa;
} perf;
 
+   struct {
+   struct kobject kobj;
+   struct kobject classes_kobjs[MAX_ENGINE_CLASS];
+   } gt_topology;
+
/* Abstract the submission mechanism (legacy ringbuffer or execlists) 
away */
struct {
void (*resume)(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 107e2d7c9fba..5d1ef1314547 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -186,6 +186,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VIDEO_ENHANCEMENT_CLASS2
 #define COPY_ENGINE_CLASS  3
 #define OTHER_CLASS4
+#define MAX_ENGINE_CLASS   5
 
 /* PCI config space */
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 791759f632e1..fd04d0b93eaf 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -559,6 +559,160 @@ static void i915_setup_error_capture(struct device *kdev) 
{}
 static void i915_teardown_error_capture(struct device *kdev) {}
 #endif
 
+static struct attribute engine_id_attr = {
+   .name = "id",
+   .mode = 0444,
+};
+
+static struct attribute engine_class_attr = {
+   .name = "class",
+   .mode = 0444,
+};
+
+static ssize_t
+show_engine_attr(struct kobject *kobj, struct attribute *attr, char *buf)
+{
+   struct intel_engine_cs *engine =
+   container_of(kobj, struct intel_engine_cs, instance_kobj);
+
+   if (attr == _id_attr)
+   return sprintf(buf, "%hhu\n", engine->uabi_id);
+   if (attr == _class_attr)
+   return sprintf(buf, "%hhu\n", engine->uabi_class);
+   return sprintf(buf, "\n");
+}
+
+static const struct sysfs_ops engine_ops = {
+   .show = show_engine_attr,
+};
+
+static struct kobj_type engine_type = {
+   .sysfs_ops = _ops,
+};
+
+static struct attribute engine_capability_hevc_attr = {
+   .name = "hevc",
+   .mode = 0444,
+};
+
+static ssize_t
+show_engine_capabilities_attr(struct kobject *kobj, struct attribute *attr, 
char *buf)
+{
+   struct intel_engine_cs *engine =
+   container_of(kobj, struct intel_engine_cs, capabilities_kobj);
+
+   if (attr == _capability_hevc_attr)
+   return sprintf(buf, "%i\n", INTEL_GEN(engine->i915) >= 8);
+   return sprintf(buf, "\n");
+}
+
+static const struct sysfs_ops engine_capabilities_ops = {
+   .show = show_engine_capabilities_attr,
+};
+
+static struct kobj_type engine_capabilities_type = {
+   .sysfs_ops = _capabilities_ops,
+};
+
+static int i915_setup_engines_sysfs(struct drm_i915_private *dev_priv,
+   struct kobject *gt_kobj)
+{
+   struct intel_engine_cs *engine_for_class, *engine;
+   enum intel_engine_id id_for_class, id;
+   bool registred[MAX_ENGINE_CLASS] = { false, };
+   int ret;
+
+   for_each_engine(engine_for_class, dev_priv, id_for_class) {
+   struct kobject *engine_class_kobj =
+   
_priv->gt_topology.classes_kobjs[engine_for_class->class];
+
+   if (registred[engine_for_class->class])
+   continue;
+
+   registred[engine_for_class->class] = true;
+
+   ret = kobject_init_and_add(engine_class_kobj,
+  gt_kobj->ktype,
+  gt_kobj,
+  
intel_engine_get_class_name(engine_for_class));
+   if (ret)
+   

[Intel-gfx] [PATCH v2 1/4] drm/i915: store all subslice masks

[Lionel Landwerlin]

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  24 +++--
 drivers/gpu/drm/i915/i915_drv.c  |   2 +-
 drivers/gpu/drm/i915/i915_drv.h  |  23 -
 drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 6 files changed, 161 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..3cc0f383b058 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4477,7 +4477,7 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask = BIT(0);
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslices_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4524,7 +4524,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask = info->sseu.subslice_mask;
+   sseu->subslices_mask[s] = info->sseu.subslices_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4579,8 +4579,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask =
-   INTEL_INFO(dev_priv)->sseu.subslice_mask;
+   sseu->subslices_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4590,7 +4590,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
 
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslices_mask[s] |= BIT(ss);
}
 
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4612,9 +4612,12 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
if (sseu->slice_mask) {
-   sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   sseu->subslices_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslices_mask[s];
+   }
sseu->eu_total = sseu->eu_per_subslice *
 sseu_subslice_total(sseu);
 
@@ -4633,6 +4636,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool 
is_available_info,
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+   int s;
 
seq_printf(m, "  %s Slice Mask: %04x\n", type,
   sseu->slice_mask);
@@ -4640,10 +4644,10 @@ static void i915_print_sseu_info(struct seq_file *m, 
bool is_available_info,
   hweight8(sseu->slice_mask));
seq_printf(m, "  %s Subslice Total: %u\n", type,
   sseu_subslice_total(sseu));
-   seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-  sseu->subslice_mask);
-   seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-  hweight8(sseu->subslice_mask));
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   seq_printf(m, "  %s Slice%i Subslice Mask: %04x\n", type,
+  s, sseu->subslices_mask[s]);
+   }
seq_printf(m, "  %s EU Total: %u\n", type,
   sseu->eu_total);
seq_printf(m, "  %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 11f73b69259b..52f3567de525 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -415,7 +415,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
 

[Intel-gfx] [PATCH v2 0/4] drm/i915: Expose more GPU properties through sysfs

[Lionel Landwerlin]

Hi,

An update based on Chris & Tvrtko's feedback.

Cheers,

Lionel Landwerlin (4):
  drm/i915: store all subslice masks
  drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  drm/i915: expose engine availability through sysfs
  drm/i915: expose EU topology through sysfs

 drivers/gpu/drm/i915/i915_debugfs.c  |  50 +++--
 drivers/gpu/drm/i915/i915_drv.c  |   2 +-
 drivers/gpu/drm/i915/i915_drv.h  |  54 -
 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c| 335 +++
 drivers/gpu/drm/i915/intel_device_info.c | 169 +++-
 drivers/gpu/drm/i915/intel_engine_cs.c   |  12 ++
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   6 +-
 9 files changed, 554 insertions(+), 77 deletions(-)

--
2.15.0
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Automatic i915_switch_context for legacy

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Automatic i915_switch_context 
for legacy
URL   : https://patchwork.freedesktop.org/series/34005/
State : failure

== Summary ==

Series 34005v1 series starting with [CI,1/2] drm/i915: Automatic 
i915_switch_context for legacy
https://patchwork.freedesktop.org/api/1.0/series/34005/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#103163 +2
Test gem_busy:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-hang-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900) fdo#102657 +2
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
Test gem_ctx_exec:
Subgroup basic:
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Test gem_exec_fence:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-blb-e6850)
pass   -> FAIL   (fi-pnv-d510)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   

Re: [Intel-gfx] [(resend) PATCH 1/2] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.

[Maarten Lankhorst]

Op 17-11-17 om 15:53 schreef Ville Syrjälä:
> On Fri, Nov 17, 2017 at 03:47:58PM +0100, Maarten Lankhorst wrote:
>> Op 17-11-17 om 14:31 schreef Ville Syrjälä:
>>> On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
 The watermarks it should calculate against are the old optimal watermarks.
 The currently active crtc watermarks are pure fiction, and are invalid in
 case of a nonblocking modeset, page flip enabling/disabling planes or any
 other reason.

 When the crtc is disabled or during a modeset the intermediate watermarks
 don't need to be programmed separately, and could be directly assigned
 to the optimal watermarks.

 CXSR must always be disabled in the intermediate case for modesets, else
 we get a WARN for vblank wait timeout.

 Also rename crtc_state to new_crtc_state, to distinguish it from the old 
 state.

 Changes since v1:
 - Use intel_atomic_get_old_crtc_state. (ville)
 Changes since v2:
 - Always unset cxsr during modeset.

 Signed-off-by: Maarten Lankhorst 
>>> I was going to try and figure out how/if these get rid of the unclaimed
>>> reg warns, but I didn't quite get that far. I did spot a few other
>>> buglets in the wm code though (I'll send fixes for those at some point).
>>>
>>> Anyways, these patches make sense to me, so for the series
>>> Reviewed-by: Ville Syrjälä 
>> Seems Chris Wilson already beat us to it..
>>
>> https://intel-gfx-ci.01.org/tree/drm-tip/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
>> was gone with
>>
>> commit 1a1f12872edcd5e425b668a35fb23548cfa918ef
>> Author: Chris Wilson > >
>> Date:   Tue Nov 7 14:03:38 2017 +
>>
>> drm/i915: Prevent unbounded wm results in g4x_compute_wm()
> That patch should be nop. So this is a very surprising result.
>
Oh well maybe the watermarks initially read out were being garbage. Garbage in, 
garbage out. :-)
___
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[Intel-gfx] [CI 2/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   |  5 +
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 7 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index af49da64ff3a..28e647042908 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1814,8 +1810,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return true;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 445495f9893c..2c68a2bbe244 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -718,6 +718,11 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_ctx;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index eb142bd4c9e1..8e6ad64aba91 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = rq->engine->emit_bb_start(rq,
batch->node.start, batch->node.size,
flags);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 664d1b4f8c69..09340b3c1156 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -158,10 +158,6 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
goto err_batch;
}
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
flags = 0;
if (INTEL_GEN(vm->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
index e3871db78beb..647bf2bbd799 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -459,10 +459,6 @@ 

[Intel-gfx] [CI 1/2] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   | 18 +-
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 10 files changed, 20 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..af49da64ff3a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1115,10 +1115,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1965,10 +1961,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..445495f9893c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
@@ -703,10 +707,6 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto 

Re: [Intel-gfx] [(resend) PATCH 1/2] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.

[Ville Syrjälä]

On Fri, Nov 17, 2017 at 03:47:58PM +0100, Maarten Lankhorst wrote:
> Op 17-11-17 om 14:31 schreef Ville Syrjälä:
> > On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
> >> The watermarks it should calculate against are the old optimal watermarks.
> >> The currently active crtc watermarks are pure fiction, and are invalid in
> >> case of a nonblocking modeset, page flip enabling/disabling planes or any
> >> other reason.
> >>
> >> When the crtc is disabled or during a modeset the intermediate watermarks
> >> don't need to be programmed separately, and could be directly assigned
> >> to the optimal watermarks.
> >>
> >> CXSR must always be disabled in the intermediate case for modesets, else
> >> we get a WARN for vblank wait timeout.
> >>
> >> Also rename crtc_state to new_crtc_state, to distinguish it from the old 
> >> state.
> >>
> >> Changes since v1:
> >> - Use intel_atomic_get_old_crtc_state. (ville)
> >> Changes since v2:
> >> - Always unset cxsr during modeset.
> >>
> >> Signed-off-by: Maarten Lankhorst 
> > I was going to try and figure out how/if these get rid of the unclaimed
> > reg warns, but I didn't quite get that far. I did spot a few other
> > buglets in the wm code though (I'll send fixes for those at some point).
> >
> > Anyways, these patches make sense to me, so for the series
> > Reviewed-by: Ville Syrjälä 
> Seems Chris Wilson already beat us to it..
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
> was gone with
> 
> commit 1a1f12872edcd5e425b668a35fb23548cfa918ef
> Author: Chris Wilson  >
> Date:   Tue Nov 7 14:03:38 2017 +
> 
> drm/i915: Prevent unbounded wm results in g4x_compute_wm()

That patch should be nop. So this is a very surprising result.

> 
> But I think this patch also fixes it in a slightly different way, never using 
> garbage for intermediaries. :-)
> 
> Thanks for review, pushed.
> 
> Cheers,
> ~Maarten

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [(resend) PATCH 1/2] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.

[Maarten Lankhorst]

Op 17-11-17 om 14:31 schreef Ville Syrjälä:
> On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
>> The watermarks it should calculate against are the old optimal watermarks.
>> The currently active crtc watermarks are pure fiction, and are invalid in
>> case of a nonblocking modeset, page flip enabling/disabling planes or any
>> other reason.
>>
>> When the crtc is disabled or during a modeset the intermediate watermarks
>> don't need to be programmed separately, and could be directly assigned
>> to the optimal watermarks.
>>
>> CXSR must always be disabled in the intermediate case for modesets, else
>> we get a WARN for vblank wait timeout.
>>
>> Also rename crtc_state to new_crtc_state, to distinguish it from the old 
>> state.
>>
>> Changes since v1:
>> - Use intel_atomic_get_old_crtc_state. (ville)
>> Changes since v2:
>> - Always unset cxsr during modeset.
>>
>> Signed-off-by: Maarten Lankhorst 
> I was going to try and figure out how/if these get rid of the unclaimed
> reg warns, but I didn't quite get that far. I did spot a few other
> buglets in the wm code though (I'll send fixes for those at some point).
>
> Anyways, these patches make sense to me, so for the series
> Reviewed-by: Ville Syrjälä 
Seems Chris Wilson already beat us to it..

https://intel-gfx-ci.01.org/tree/drm-tip/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html
was gone with

commit 1a1f12872edcd5e425b668a35fb23548cfa918ef
Author: Chris Wilson >
Date:   Tue Nov 7 14:03:38 2017 +

drm/i915: Prevent unbounded wm results in g4x_compute_wm()

But I think this patch also fixes it in a slightly different way, never using 
garbage for intermediaries. :-)

Thanks for review, pushed.

Cheers,
~Maarten

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Automatic i915_switch_context for legacy

[Patchwork]

== Series Details ==

Series: drm/i915: Automatic i915_switch_context for legacy
URL   : https://patchwork.freedesktop.org/series/34002/
State : failure

== Summary ==

Test gem_exec_reloc:
Subgroup basic-range:
pass   -> INCOMPLETE (shard-snb)
Subgroup basic-range-active:
pass   -> INCOMPLETE (shard-snb)
Test drv_module_reload:
Subgroup basic-no-display:
pass   -> DMESG-WARN (shard-hsw) fdo#102707 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-shrfb-plflip-blt:
pass   -> SKIP   (shard-hsw) fdo#103167
Test kms_flip:
Subgroup vblank-vs-modeset-suspend-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup blt-wf_vblank-vs-dpms-interruptible:
skip   -> PASS   (shard-hsw) fdo#102614
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-varying-size:
fail   -> PASS   (shard-hsw) fdo#102670
Test kms_chv_cursor_fail:
Subgroup pipe-c-256x256-left-edge:
pass   -> SKIP   (shard-hsw)

fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670

shard-hswtotal:2585 pass:1466 dwarn:3   dfail:1   fail:10  skip:1105 
time:9265s
shard-snbtotal:2477 pass:1202 dwarn:1   dfail:1   fail:12  skip:1259 
time:7786s
Blacklisted hosts:
shard-apltotal:2563 pass:1601 dwarn:2   dfail:0   fail:23  skip:936 
time:12966s
shard-kbltotal:2511 pass:1657 dwarn:6   dfail:3   fail:24  skip:819 
time:10080s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7169/shards.html
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