Re: [Intel-gfx] [PATCH 2/3] i965: define stuff for scratch page checking in intel_screen
Sighs, I do not know why git send-email made this into two threads, but there it is. Worse, the second patch was from an older version; the one posted lacks the write to the scratch page with noise. At any rate, the thing is also on github at https://github.com/krogueintel/asem/tree/out-of-bounds-write-detect which has the initialization of the scratch page with noise. -Kevin -Original Message- From: Rogovin, Kevin Sent: Tuesday, December 5, 2017 9:48 AM To: intel-gfx@lists.freedesktop.org Cc: Rogovin, Kevin Subject: [PATCH 2/3] i965: define stuff for scratch page checking in intel_screen From: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + src/mesa/drivers/dri/i965/intel_screen.c | 26 ++ src/mesa/drivers/dri/i965/intel_screen.h | 12 4 files changed, 40 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index f58c593c44..7bd6723311 100644 --- a/src/intel/common/gen_debug.c +++ b/src/intel/common/gen_debug.c @@ -84,6 +84,7 @@ static const struct debug_control debug_control[] = { { "nohiz", DEBUG_NO_HIZ }, { "color", DEBUG_COLOR }, { "reemit", DEBUG_REEMIT }, + { "check_scratch", DEBUG_CHECK_SCRATH }, { NULL,0 } }; diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h index e418e3fb16..5e224a45f0 100644 --- a/src/intel/common/gen_debug.h +++ b/src/intel/common/gen_debug.h @@ -83,6 +83,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_NO_HIZ (1ull << 39) #define DEBUG_COLOR (1ull << 40) #define DEBUG_REEMIT (1ull << 41) +#define DEBUG_CHECK_SCRATH(1ull << 42) #ifdef HAVE_ANDROID_PLATFORM #define LOG_TAG "INTEL-MESA" diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 38769babf0..044be8fe85 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1557,6 +1557,12 @@ intelDestroyScreen(__DRIscreen * sPriv) brw_bufmgr_destroy(screen->bufmgr); driDestroyOptionInfo(&screen->optionCache); + if (screen->debug_batchbuffer.enabled) { + simple_mtx_destroy(&screen->debug_batchbuffer.mutex); + free(screen->debug_batchbuffer.noise_values); + free(screen->debug_batchbuffer.tmp); + } + ralloc_free(screen); sPriv->driverPrivate = NULL; } @@ -2610,6 +2616,26 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) } } + screen->debug_batchbuffer.enabled = false; + if (INTEL_DEBUG & DEBUG_CHECK_SCRATH) { + struct drm_i915_scratch_page sc; + int err; + + sc.buffer_size = 0; + sc.buffer_ptr = 0; + err = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_READ_SCRATCH_PAGE, &sc); + if (err == 0) { + screen->debug_batchbuffer.enabled = true; + simple_mtx_init(&screen->debug_batchbuffer.mutex, mtx_plain); + screen->debug_batchbuffer.buffer_size = sc.buffer_size; + screen->debug_batchbuffer.noise_values = calloc(screen->debug_batchbuffer.buffer_size, 1); + screen->debug_batchbuffer.tmp = calloc(screen->debug_batchbuffer.buffer_size, 1); + for (uint64_t i = 0; i < screen->debug_batchbuffer.buffer_size; ++i) { +screen->debug_batchbuffer.noise_values[i] = rand() & 0xFF; + } + } + } + return (const __DRIconfig**) intel_screen_make_configs(dri_screen); } diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h index 7948617b7f..7d56106aa2 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.h +++ b/src/mesa/drivers/dri/i965/intel_screen.h @@ -37,6 +37,7 @@ #include "common/gen_device_info.h" #include "i915_drm.h" #include "util/xmlconfig.h" +#include "util/simple_mtx.h" #include "isl/isl.h" @@ -114,6 +115,17 @@ struct intel_screen */ int eu_total; + /** +* Struct to perform out-of-bound GEM BO write checking +*/ + struct { + bool enabled; + simple_mtx_t mutex; + uint32_t buffer_size; + uint8_t *noise_values; + uint8_t *tmp; + } debug_batchbuffer; + bool mesa_format_supports_texture[MESA_FORMAT_COUNT]; bool mesa_format_supports_render[MESA_FORMAT_COUNT]; enum isl_format mesa_to_isl_render_format[MESA_FORMAT_COUNT]; -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm-uapi: define interface to kernel for scratch page read
Sighs, I do not know why git send-email made this into two threads, but there it is. Worse, the second patch was from an older version; the one posted lacks the write to the scratch page with noise. At any rate, the thing is also on github at https://github.com/krogueintel/asem/tree/out-of-bounds-write-detect which has the initialization of the scratch page with noise. -Kevin -Original Message- From: Rogovin, Kevin Sent: Tuesday, December 5, 2017 9:48 AM To: intel-gfx@lists.freedesktop.org Cc: Rogovin, Kevin Subject: [PATCH 1/3] drm-uapi: define interface to kernel for scratch page read From: Kevin Rogovin --- include/drm-uapi/i915_drm.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 890df227ae..3a9c3a2d0c 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -262,6 +262,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_PERF_OPEN 0x36 #define DRM_I915_PERF_ADD_CONFIG 0x37 #define DRM_I915_PERF_REMOVE_CONFIG0x38 +#define DRM_I915_READ_SCRATCH_PAGE 0x39 +#define DRM_I915_WRITE_SCRATCH_PAGE 0x40 #define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -319,6 +321,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) +#define DRM_IOCTL_I915_READ_SCRATCH_PAGEDRM_IOWR (DRM_COMMAND_BASE + DRM_I915_READ_SCRATCH_PAGE, struct drm_i915_scratch_page) +#define DRM_IOCTL_I915_WRITE_SCRATCH_PAGE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_WRITE_SCRATCH_PAGE, struct drm_i915_scratch_page) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -1535,6 +1539,33 @@ struct drm_i915_perf_oa_config { __u64 flex_regs_ptr; }; +/** + * Structure to read/write scratch page of PPGTT. Read and writing + * values are not reliable unless the calling application guarantees + * that no batchbuffer that could read or write the scratch is in + * flight using the PPGTT between the time the ioctl is issued and + * it returns. + */ +struct drm_i915_scratch_page { + /** +* size in bytes of the backing store pointed to by buffer_ptr; +* kernel will return the actual size of the scratch page in +* this field as well. +*/ + __u32 buffer_size; + + /** +* Pointer data with which to upload to or download from the +* scratch page; if the buffer size behind buffer_ptr is +* smaller than the scratch page size, then only the first +* buffer_size bytes are read or written. If the scratch +* page size is greater than buffer_size, then the bytes +* past the scratch page size in buffer behind bufer_ptr +* are not read or writte. +*/ + __u64 buffer_ptr; +}; + #if defined(__cplusplus) } #endif -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/3] RFC: Scratch page checking
From: Kevin Rogovin This patch series proposes a new kernel interface for user space to read and write the values of the scratch page for a PPGTT. The user space is expected to guarantee (via its own locking mechanism) that nothing shall read or write to the scratch page for the duration of the ioctl's to read or write the scratch page values. The purpose for user space to read and write the scratch page values is to help see if an out-of-bound write was done to the scratch page by the GPU; from the point of view of GL, this can be used to help detect if an application performs an out-of-bounds write to an SSBO. Patch 1 defines the kernel interface Patches 2-3 implement the debug option in i965 to check for inadvertent scratch page writes by the GPU. Kevin Rogovin (3): drm-uapi: define interface to kernel for scratch page read i965: define stuff for scratch page checking in intel_screen i965: check scratch page in a locked fashion on each ioctl include/drm-uapi/i915_drm.h | 31 +++ src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + src/mesa/drivers/dri/i965/intel_batchbuffer.c | 27 ++- src/mesa/drivers/dri/i965/intel_screen.c | 26 ++ src/mesa/drivers/dri/i965/intel_screen.h | 12 +++ 6 files changed, 97 insertions(+), 1 deletion(-) -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] i965: define stuff for scratch page checking in intel_screen
From: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + src/mesa/drivers/dri/i965/intel_screen.c | 26 ++ src/mesa/drivers/dri/i965/intel_screen.h | 12 4 files changed, 40 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index f58c593c44..7bd6723311 100644 --- a/src/intel/common/gen_debug.c +++ b/src/intel/common/gen_debug.c @@ -84,6 +84,7 @@ static const struct debug_control debug_control[] = { { "nohiz", DEBUG_NO_HIZ }, { "color", DEBUG_COLOR }, { "reemit", DEBUG_REEMIT }, + { "check_scratch", DEBUG_CHECK_SCRATH }, { NULL,0 } }; diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h index e418e3fb16..5e224a45f0 100644 --- a/src/intel/common/gen_debug.h +++ b/src/intel/common/gen_debug.h @@ -83,6 +83,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_NO_HIZ (1ull << 39) #define DEBUG_COLOR (1ull << 40) #define DEBUG_REEMIT (1ull << 41) +#define DEBUG_CHECK_SCRATH(1ull << 42) #ifdef HAVE_ANDROID_PLATFORM #define LOG_TAG "INTEL-MESA" diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 38769babf0..044be8fe85 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1557,6 +1557,12 @@ intelDestroyScreen(__DRIscreen * sPriv) brw_bufmgr_destroy(screen->bufmgr); driDestroyOptionInfo(&screen->optionCache); + if (screen->debug_batchbuffer.enabled) { + simple_mtx_destroy(&screen->debug_batchbuffer.mutex); + free(screen->debug_batchbuffer.noise_values); + free(screen->debug_batchbuffer.tmp); + } + ralloc_free(screen); sPriv->driverPrivate = NULL; } @@ -2610,6 +2616,26 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) } } + screen->debug_batchbuffer.enabled = false; + if (INTEL_DEBUG & DEBUG_CHECK_SCRATH) { + struct drm_i915_scratch_page sc; + int err; + + sc.buffer_size = 0; + sc.buffer_ptr = 0; + err = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_READ_SCRATCH_PAGE, &sc); + if (err == 0) { + screen->debug_batchbuffer.enabled = true; + simple_mtx_init(&screen->debug_batchbuffer.mutex, mtx_plain); + screen->debug_batchbuffer.buffer_size = sc.buffer_size; + screen->debug_batchbuffer.noise_values = calloc(screen->debug_batchbuffer.buffer_size, 1); + screen->debug_batchbuffer.tmp = calloc(screen->debug_batchbuffer.buffer_size, 1); + for (uint64_t i = 0; i < screen->debug_batchbuffer.buffer_size; ++i) { +screen->debug_batchbuffer.noise_values[i] = rand() & 0xFF; + } + } + } + return (const __DRIconfig**) intel_screen_make_configs(dri_screen); } diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h index 7948617b7f..7d56106aa2 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.h +++ b/src/mesa/drivers/dri/i965/intel_screen.h @@ -37,6 +37,7 @@ #include "common/gen_device_info.h" #include "i915_drm.h" #include "util/xmlconfig.h" +#include "util/simple_mtx.h" #include "isl/isl.h" @@ -114,6 +115,17 @@ struct intel_screen */ int eu_total; + /** +* Struct to perform out-of-bound GEM BO write checking +*/ + struct { + bool enabled; + simple_mtx_t mutex; + uint32_t buffer_size; + uint8_t *noise_values; + uint8_t *tmp; + } debug_batchbuffer; + bool mesa_format_supports_texture[MESA_FORMAT_COUNT]; bool mesa_format_supports_render[MESA_FORMAT_COUNT]; enum isl_format mesa_to_isl_render_format[MESA_FORMAT_COUNT]; -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm-uapi: define interface to kernel for scratch page read
From: Kevin Rogovin --- include/drm-uapi/i915_drm.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 890df227ae..3a9c3a2d0c 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -262,6 +262,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_PERF_OPEN 0x36 #define DRM_I915_PERF_ADD_CONFIG 0x37 #define DRM_I915_PERF_REMOVE_CONFIG0x38 +#define DRM_I915_READ_SCRATCH_PAGE 0x39 +#define DRM_I915_WRITE_SCRATCH_PAGE 0x40 #define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -319,6 +321,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) +#define DRM_IOCTL_I915_READ_SCRATCH_PAGEDRM_IOWR (DRM_COMMAND_BASE + DRM_I915_READ_SCRATCH_PAGE, struct drm_i915_scratch_page) +#define DRM_IOCTL_I915_WRITE_SCRATCH_PAGE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_WRITE_SCRATCH_PAGE, struct drm_i915_scratch_page) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -1535,6 +1539,33 @@ struct drm_i915_perf_oa_config { __u64 flex_regs_ptr; }; +/** + * Structure to read/write scratch page of PPGTT. Read and writing + * values are not reliable unless the calling application guarantees + * that no batchbuffer that could read or write the scratch is in + * flight using the PPGTT between the time the ioctl is issued and + * it returns. + */ +struct drm_i915_scratch_page { + /** +* size in bytes of the backing store pointed to by buffer_ptr; +* kernel will return the actual size of the scratch page in +* this field as well. +*/ + __u32 buffer_size; + + /** +* Pointer data with which to upload to or download from the +* scratch page; if the buffer size behind buffer_ptr is +* smaller than the scratch page size, then only the first +* buffer_size bytes are read or written. If the scratch +* page size is greater than buffer_size, then the bytes +* past the scratch page size in buffer behind bufer_ptr +* are not read or writte. +*/ + __u64 buffer_ptr; +}; + #if defined(__cplusplus) } #endif -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] i965: check scratch page in a locked fashion on each ioctl
From: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 216073129b..53b3eaf49b 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -804,7 +804,8 @@ static int submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) { const struct gen_device_info *devinfo = &brw->screen->devinfo; - __DRIscreen *dri_screen = brw->screen->driScrnPriv; + struct intel_screen *screen = brw->screen; + __DRIscreen *dri_screen = screen->driScrnPriv; struct intel_batchbuffer *batch = &brw->batch; int ret = 0; @@ -875,10 +876,34 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) batch->validation_list[index] = tmp; } + if (unlikely(screen->debug_batchbuffer.enabled)) { + simple_mtx_lock(&screen->debug_batchbuffer.mutex); + } + ret = execbuffer(dri_screen->fd, batch, hw_ctx, 4 * USED_BATCH(*batch), in_fence_fd, out_fence_fd, flags); + if (unlikely(screen->debug_batchbuffer.enabled)) { + struct drm_i915_scratch_page sc; + int ret; + + while (brw_bo_busy(batch->bo)) { +usleep(10); + } + + sc.buffer_size = screen->debug_batchbuffer.buffer_size; + sc.buffer_ptr = (__u64)(uintptr_t) screen->debug_batchbuffer.tmp; + + ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_READ_SCRATCH_PAGE, &sc); + assert(ret == 0); + assert(sc.buffer_size == screen->debug_batchbuffer.buffer_size); + assert(memcmp(screen->debug_batchbuffer.tmp, + screen->debug_batchbuffer.noise_values, + screen->debug_batchbuffer.buffer_size) == 0); + simple_mtx_unlock(&screen->debug_batchbuffer.mutex); + } + throttle(brw); } -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] CONTRIBUTING: Fix spelling mistake and line length
== Series Details == Series: series starting with [1/2] CONTRIBUTING: Fix spelling mistake and line length URL : https://patchwork.freedesktop.org/series/34881/ State : warning == Summary == Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-hsw) fdo#104009 Test kms_flip: Subgroup flip-vs-modeset-vs-hang-interruptible: pass -> DMESG-WARN (shard-snb) Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 +1 Test drv_selftest: Subgroup mock_sanitycheck: pass -> DMESG-WARN (shard-snb) fdo#102707 +1 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 shard-hswtotal:2623 pass:1499 dwarn:2 dfail:0 fail:9 skip:1112 time:9330s shard-snbtotal:2681 pass:1306 dwarn:3 dfail:0 fail:12 skip:1360 time:8164s Blacklisted hosts: shard-apltotal:2659 pass:1657 dwarn:1 dfail:0 fail:23 skip:977 time:13252s shard-kbltotal:2681 pass:1797 dwarn:1 dfail:0 fail:24 skip:859 time:10805s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_596/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] CONTRIBUTING: Fix spelling mistake and line length
== Series Details == Series: series starting with [1/2] CONTRIBUTING: Fix spelling mistake and line length URL : https://patchwork.freedesktop.org/series/34881/ State : success == Summary == IGT patchset tested on top of latest successful build 88b01d822be1e9ab429ef1085f6754a47dae3487 igt/pm_rc6_residency: Measure residency after checking for applicability with latest DRM-Tip kernel build CI_DRM_3452 cee3f135bf4e drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest Testlist changes: +igt@kms_content_protection@atomic +igt@kms_content_protection@legacy Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 pass -> DMESG-WARN (fi-bdw-gvtdvm) fdo#103938 +1 Test gem_exec_reloc: Subgroup basic-gtt-read-active: pass -> FAIL (fi-gdg-551) fdo#102582 +1 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#103938 https://bugs.freedesktop.org/show_bug.cgi?id=103938 fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:288 pass:262 dwarn:2 dfail:0 fail:0 skip:24 time:442s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:390s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:533s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:507s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:492s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:476s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:176 dwarn:1 dfail:0 fail:3 skip:108 time:269s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:373s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:268s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:400s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:487s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:491s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:524s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:479s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:536s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:539s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:569s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:521s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:549s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:422s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:613s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:612s fi-glk-dsi total:205 pass:184 dwarn:0 dfail:0 fail:1 skip:19 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_596/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] CONTRIBUTING: Fix spelling mistake and line length
Noticed while I was reading it. Makes for a good first contribution, I guess. Signed-off-by: Sean Paul --- CONTRIBUTING | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CONTRIBUTING b/CONTRIBUTING index 561c5dd8..ca2ed8a5 100644 --- a/CONTRIBUTING +++ b/CONTRIBUTING @@ -18,13 +18,13 @@ A short list of contribution guidelines: on its first invocation. -- intel-gpu-tools is MIT lincensed and we require contributions to follow the +- intel-gpu-tools is MIT licensed and we require contributions to follow the developer's certificate of origin: http://developercertificate.org/ - When submitting new testcases please follow the naming conventions documented - in the generated documentation. Also please make full use of all the helpers and - convenience macros provided by the igt library. The semantic patch lib/igt.cocci - can help with the more automatic conversions. + in the generated documentation. Also please make full use of all the helpers + and convenience macros provided by the igt library. The semantic patch + lib/igt.cocci can help with the more automatic conversions. - Patches need to be reviewed on the mailing list. Exceptions only apply for testcases and tooling for drivers with just a single contributor (e.g. vc4). -- 2.15.0.531.g2ccb3012c9-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] kms_content_protection: Add Content Protection test
Pretty simple test: - initializes the output - clears the content protection property - verifies that it clears - sets the content protection property to desired - verifies that it transitions to enabled Does this for both legacy and atomic. Signed-off-by: Sean Paul --- lib/igt_kms.c | 3 +- lib/igt_kms.h | 1 + tests/Makefile.sources | 1 + tests/kms_content_protection.c | 128 + tests/meson.build | 1 + 5 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 tests/kms_content_protection.c diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 125ecb19..907db694 100644 --- a/lib/igt_kms.c +++ b/lib/igt_kms.c @@ -190,7 +190,8 @@ const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = { "scaling mode", "CRTC_ID", "DPMS", - "Broadcast RGB" + "Broadcast RGB", + "Content Protection" }; /* diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 2a480bf3..93e59dc7 100644 --- a/lib/igt_kms.h +++ b/lib/igt_kms.h @@ -118,6 +118,7 @@ enum igt_atomic_connector_properties { IGT_CONNECTOR_CRTC_ID, IGT_CONNECTOR_DPMS, IGT_CONNECTOR_BROADCAST_RGB, + IGT_CONNECTOR_CONTENT_PROTECTION, IGT_NUM_CONNECTOR_PROPS }; diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 34ca71a0..e0466411 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -179,6 +179,7 @@ TESTS_progs = \ kms_chv_cursor_fail \ kms_color \ kms_concurrent \ + kms_content_protection\ kms_crtc_background_color \ kms_cursor_crc \ kms_cursor_legacy \ diff --git a/tests/kms_content_protection.c b/tests/kms_content_protection.c new file mode 100644 index ..7bfe9a69 --- /dev/null +++ b/tests/kms_content_protection.c @@ -0,0 +1,128 @@ +/* + * Copyright © 2017 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "igt.h" + +IGT_TEST_DESCRIPTION("Test content protection (HDCP)"); + +typedef struct { + int drm_fd; + igt_display_t display; +} data_t; + +static bool +wait_for_prop_value(igt_output_t *output, uint64_t expected) +{ + uint64_t val; + int i; + + for (i = 0; i < 2000; i++) { + val = igt_output_get_prop(output, + IGT_CONNECTOR_CONTENT_PROTECTION); + if (val == expected) + return true; + usleep(1000); + } + igt_info("prop_value mismatch %ld != %ld\n", val, expected); + return false; +} + +static void +test_pipe_output(igt_display_t *display, const enum pipe pipe, +igt_output_t *output, enum igt_commit_style s) +{ + drmModeModeInfo mode; + igt_plane_t *primary; + struct igt_fb red; + bool ret; + + igt_assert(kmstest_get_connector_default_mode( + display->drm_fd, output->config.connector, &mode)); + + igt_output_override_mode(output, &mode); + igt_output_set_pipe(output, pipe); + + igt_create_color_fb(display->drm_fd, mode.hdisplay, mode.vdisplay, + DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE, + 1.f, 0.f, 0.f, &red); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); + igt_plane_set_fb(primary, &red); + igt_display_commit2(display, s); + + igt_output_set_prop_value(output, IGT_CONNECTOR_CONTENT_PROTECTION, 0); + igt_display_commit2(display, s); + + ret = wait_for_prop_value(output, 0); + igt_require_f(ret, "Content Protection not cleared\n"); + + igt_output_set_prop_value(output, IGT_CONNECTOR_CONTENT_PROTECTION, 1); + igt_display_commit2(display, s); + + ret = wait_for_prop_value(output, 2); + igt_require_f(ret, "Conte
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP (rev3)
== Series Details == Series: drm/i915: Implement HDCP (rev3) URL : https://patchwork.freedesktop.org/series/34671/ State : failure == Summary == Applying: drm: Fix link-status kerneldoc line lengths error: Failed to merge in the changes. Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_connector.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_connector.c CONFLICT (content): Merge conflict in drivers/gpu/drm/drm_connector.c Patch failed at 0001 drm: Fix link-status kerneldoc line lengths The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/9] drm: Add Content Protection property
This patch adds a new optional connector property to allow userspace to enable protection over the content it is displaying. This will typically be implemented by the driver using HDCP. The property is a tri-state with the following values: - OFF: Self explanatory, no content protection - DESIRED: Userspace requests that the driver enable protection - ENABLED: Once the driver has authenticated the link, it sets this value The driver is responsible for downgrading ENABLED to DESIRED if the link becomes unprotected. The driver should also maintain the desiredness of protection across hotplug/dpms/suspend. If this looks familiar, I posted [1] this 3 years ago. We have been using this in ChromeOS across exynos, mediatek, and rockchip over that time. Changes in v2: - Pimp kerneldoc for content_protection_property (Daniel) - Drop sysfs attribute Changes in v3: - None Cc: Daniel Vetter Signed-off-by: Sean Paul [1] https://lists.freedesktop.org/archives/dri-devel/2014-December/073336.html --- drivers/gpu/drm/drm_atomic.c| 8 + drivers/gpu/drm/drm_connector.c | 71 + drivers/gpu/drm/drm_sysfs.c | 1 + include/drm/drm_connector.h | 16 ++ include/uapi/drm/drm_mode.h | 4 +++ 5 files changed, 100 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index c2da5585e201..676025d755b2 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -1196,6 +1196,12 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, state->picture_aspect_ratio = val; } else if (property == connector->scaling_mode_property) { state->scaling_mode = val; + } else if (property == connector->content_protection_property) { + if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) { + DRM_DEBUG_KMS("only drivers can set CP Enabled\n"); + return -EINVAL; + } + state->content_protection = val; } else if (connector->funcs->atomic_set_property) { return connector->funcs->atomic_set_property(connector, state, property, val); @@ -1275,6 +1281,8 @@ drm_atomic_connector_get_property(struct drm_connector *connector, *val = state->picture_aspect_ratio; } else if (property == connector->scaling_mode_property) { *val = state->scaling_mode; + } else if (property == connector->content_protection_property) { + *val = state->content_protection; } else if (connector->funcs->atomic_get_property) { return connector->funcs->atomic_get_property(connector, state, property, val); diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index f14b48e6e839..8626aa8f485e 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -698,6 +698,13 @@ static const struct drm_prop_enum_list drm_tv_subconnector_enum_list[] = { DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, drm_tv_subconnector_enum_list) +static struct drm_prop_enum_list drm_cp_enum_list[] = { +{ DRM_MODE_CONTENT_PROTECTION_OFF, "Off" }, +{ DRM_MODE_CONTENT_PROTECTION_DESIRED, "Desired" }, +{ DRM_MODE_CONTENT_PROTECTION_ENABLED, "Enabled" }, +}; +DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list) + /** * DOC: standard connector properties * @@ -764,6 +771,34 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, * after modeset, the kernel driver may set this to "BAD" and issue a * hotplug uevent. Drivers should update this value using * drm_mode_connector_set_link_status_property(). + * Content Protection: + * This property is used by userspace to request the kernel protect future + * content communicated over the link. When requested, kernel will apply + * the appropriate means of protection (most often HDCP), and use the + * property to tell userspace the protection is active. + * + * The value of this property can be one of the following: + * + * - DRM_MODE_CONTENT_PROTECTION_OFF = 0 + * The link is not protected, content is transmitted in the clear. + * - DRM_MODE_CONTENT_PROTECTION_DESIRED = 1 + * Userspace has requested content protection, but the link is not + * currently protected. When in this state, kernel should enable + * Content Protection as soon as possible. + * - DRM_MODE_CONTENT_PROTECTION_ENABLED = 2 + * Userspace has requested content protection, and the link is + * protected. Only the driver can set the property to this value. + * If userspace attempts to set to ENABLED, kernel will return + * -EINVAL. + * + * A few guidelines: + * + * - DESIRED state should be preserved until
[Intel-gfx] [PATCH v3 8/9] drm/i915: Implement HDCP for HDMI
This patch adds HDCP support for HDMI connectors by implementing the intel_hdcp_shim. Nothing too special, just a bunch of DDC reads/writes. Changes in v2: - Rebased on drm-intel-next Changes in v3: - Initialize new worker Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 50 drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_hdmi.c | 257 ++ 4 files changed, 310 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 107e16392710..79944ab4218a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8450,6 +8450,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) +#define TRANS_DDI_HDCP_SIGNALLING (1<<9) #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index eff3b51872eb..a179fd9968a5 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1615,6 +1615,56 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, I915_WRITE(reg, val); } +int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder) +{ + struct drm_device *dev = intel_encoder->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = 0; + int ret = 0; + uint32_t tmp; + + if (!intel_display_power_get_if_enabled(dev_priv, + intel_encoder->power_domain)) + return -ENXIO; + + if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { + ret = -EIO; + goto out; + } + + tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); + tmp &= ~TRANS_DDI_HDCP_SIGNALLING; + I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); +out: + intel_display_power_put(dev_priv, intel_encoder->power_domain); + return ret; +} + +int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder) +{ + struct drm_device *dev = intel_encoder->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = 0; + int ret = 0; + uint32_t tmp; + + if (!intel_display_power_get_if_enabled(dev_priv, + intel_encoder->power_domain)) + return -ENXIO; + + if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { + ret = -EIO; + goto out; + } + + tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); + tmp |= TRANS_DDI_HDCP_SIGNALLING; + I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); +out: + intel_display_power_put(dev_priv, intel_encoder->power_domain); + return ret; +} + bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) { struct drm_device *dev = intel_connector->base.dev; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6f47a4227f5f..0b4405f3e988 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1379,6 +1379,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, u32 bxt_signal_levels(struct intel_dp *intel_dp); uint32_t ddi_signal_levels(struct intel_dp *intel_dp); u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); +int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder); +int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int plane, unsigned int height); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9d5e72728475..17a525b9fcf9 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include "intel_drv.h" #include @@ -873,6 +874,252 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) adapter, enable); } +static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, + unsigned int offset, void *buffer, size_t size) +{ + struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *dev_priv = + intel_dig_port->base.base.dev->dev_private; + struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, + hdmi->ddc_bus); + int ret; + u8 start = offset & 0xff; + struct i2c_msg msgs[] = { +
[Intel-gfx] [PATCH v3 9/9] drm/i915: Implement HDCP for DisplayPort
This patch adds HDCP support for DisplayPort connectors by implementing the intel_hdcp_shim. Most of this is straightforward read/write from/to DPCD registers. One thing worth pointing out is the Aksv output bit. It wasn't easily separable like it's HDMI counterpart, so it's crammed in with the rest of it. Changes in v2: - Moved intel_hdcp_check_link out of intel_dp_check_link and only call it on short pulse. Since intel_hdcp_check_link does its own locking, this ensures we don't deadlock when intel_dp_check_link is called holding connection_mutex. - Rebased on drm-intel-next Changes in v3: - Initialize new worker - Move intel_hdcp_check_link further out to avoid calling it while holding _any_ locks Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/intel_dp.c | 248 ++-- 1 file changed, 241 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c603d4c903e1..dc303e18c1dd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -36,7 +36,9 @@ #include #include #include +#include #include +#include #include "intel_drv.h" #include #include "i915_drv.h" @@ -1025,10 +1027,29 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); } +static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp, + bool has_aux_irq, + int send_bytes, + uint32_t aux_clock_divider, + bool aksv_write) +{ + uint32_t val = 0; + + if (aksv_write) { + send_bytes += 5; + val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT; + } + + return val | intel_dp->get_aux_send_ctl(intel_dp, + has_aux_irq, + send_bytes, + aux_clock_divider); +} + static int intel_dp_aux_ch(struct intel_dp *intel_dp, const uint8_t *send, int send_bytes, - uint8_t *recv, int recv_size) + uint8_t *recv, int recv_size, bool aksv_write) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = @@ -1088,10 +1109,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, } while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { - u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, - has_aux_irq, - send_bytes, - aux_clock_divider); + u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp, +has_aux_irq, +send_bytes, +aux_clock_divider, +aksv_write); /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) { @@ -1228,7 +1250,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) if (msg->buffer) memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); - ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); + ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize, + false); if (ret > 0) { msg->reply = rxbuf[0] >> 4; @@ -1250,7 +1273,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) if (WARN_ON(rxsize > 20)) return -E2BIG; - ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); + ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize, + false); if (ret > 0) { msg->reply = rxbuf[0] >> 4; /* @@ -4981,6 +5005,203 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) pps_unlock(intel_dp); } +static +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, + u8 *an) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base); + uint8_t txbuf[4], rxbuf[2], reply = 0; + ssize_t dpcd_ret; + int ret; + + /* Output An first, that's easy */ + dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, +an, DRM_HDCP_AN_LEN); + if (dpcd_ret != DRM_HDCP_AN_LEN) {
[Intel-gfx] [PATCH v3 5/9] drm/i915: Add HDCP framework + base implementation
This patch adds the framework required to add HDCP support to intel connectors. It implements Aksv loading from fuse, and parts 1/2/3 of the HDCP authentication scheme. Note that without shim implementations, this does not actually implement HDCP. That will come in subsequent patches. Changes in v2: - Don't open code wait_fors (Chris) - drm_hdcp.c under MIT license (Daniel) - Move intel_hdcp_disable() call above ddi_disable (Ram) - Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel) - Justify intel_hdcp_shim with comments (Daniel) - Fixed async locking issues by adding hdcp_mutex (Daniel) - Don't alter connector_state in enable/disable (Daniel) Changes in v3: - Added hdcp_mutex/hdcp_value to make async reasonable - Added hdcp_prop_work to separate link checking & property setting - Added new helper for atomic_check state tracking (Daniel) - Moved enable/disable into atomic_commit with matching helpers - Moved intel_hdcp_check_link out of all locks when called from dp - Bumped up ksv_fifo timeout (noticed failure on one of my dongles) Cc: Chris Wilson Cc: Daniel Vetter Cc: Ramalingam C Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_reg.h | 83 drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_display.c | 14 + drivers/gpu/drm/i915/intel_drv.h | 88 + drivers/gpu/drm/i915/intel_hdcp.c| 731 +++ 6 files changed, 919 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 42bc8bd4ff06..3facea4eefdb 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -107,6 +107,7 @@ i915-y += intel_audio.o \ intel_fbc.o \ intel_fifo_underrun.o \ intel_frontbuffer.o \ + intel_hdcp.o \ intel_hotplug.o \ intel_modes.o \ intel_overlay.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bf043c1c2e..2bd2cc8441d4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8034,6 +8034,7 @@ enum { #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 +#define SKL_PCODE_LOAD_HDCP_KEYS 0x5 #define SKL_PCODE_CDCLK_CONTROL 0x7 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 @@ -8335,6 +8336,88 @@ enum skl_power_gate { #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) + +/* HDCP Key Registers */ +#define SKL_HDCP_KEY_CONF _MMIO(0x66c00) +#define SKL_HDCP_AKSV_SEND_TRIGGER BIT(31) +#define SKL_HDCP_CLEAR_KEYS_TRIGGER BIT(30) +#define SKL_HDCP_KEY_STATUS_MMIO(0x66c04) +#define SKL_HDCP_FUSE_IN_PROGRESS BIT(7) +#define SKL_HDCP_FUSE_ERROR BIT(6) +#define SKL_HDCP_FUSE_DONEBIT(5) +#define SKL_HDCP_KEY_LOAD_STATUS BIT(1) +#define SKL_HDCP_KEY_LOAD_DONEBIT(0) +#define SKL_HDCP_AKSV_LO _MMIO(0x66c10) +#define SKL_HDCP_AKSV_HI _MMIO(0x66c14) + +/* HDCP Repeater Registers */ +#define SKL_HDCP_REP_CTL _MMIO(0x66d00) +#define SKL_HDCP_DDIB_REP_PRESENT BIT(30) +#define SKL_HDCP_DDIA_REP_PRESENT BIT(29) +#define SKL_HDCP_DDIC_REP_PRESENT BIT(28) +#define SKL_HDCP_DDID_REP_PRESENT BIT(27) +#define SKL_HDCP_DDIF_REP_PRESENT BIT(26) +#define SKL_HDCP_DDIE_REP_PRESENT BIT(25) +#define SKL_HDCP_DDIB_SHA1_M0 (1 << 20) +#define SKL_HDCP_DDIA_SHA1_M0 (2 << 20) +#define SKL_HDCP_DDIC_SHA1_M0 (3 << 20) +#define SKL_HDCP_DDID_SHA1_M0 (4 << 20) +#define SKL_HDCP_DDIF_SHA1_M0 (5 << 20) +#define SKL_HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ +#define SKL_HDCP_SHA1_BUSYBIT(16) +#define SKL_HDCP_SHA1_READY BIT(17) +#define SKL_HDCP_SHA1_COMPLETEBIT(18) +#define SKL_HDCP_SHA1_V_MATCH BIT(19) +#define SKL_HDCP_SHA1_TEXT_32 (1 << 1) +#define SKL_HDCP_SHA1_COMPLETE_HASH (2 << 1) +#define SKL_HDCP_SHA1_TEXT_24 (4 << 1) +#define SKL_HDCP_SHA1_TEXT_16 (5 << 1) +#define SKL_HDCP_SHA1_TEXT_8 (6 << 1) +#define SKL_HDCP_SHA1_TEXT_0 (7 << 1) +#define SKL_HDCP_SHA_V_PRIME_H0_MMIO(0x66d04) +#define SKL_HDCP_SHA_V_PRIME_H1_MMIO(0x66d08) +#define SKL_HDCP_SHA_V_PRIME_H2_MMIO(0x66d0C) +#define SKL_HDCP_SHA_V_PRIME_H3_MMIO(0x66d10) +#define SKL_HDCP_SHA_V_PRIME_H4_MMIO(0x66d14) +#define SKL_HDCP_SHA_V_PRIME(h)_MMIO((0x66d04 + h * 4)) +#define SKL_HDCP_SHA_TEXT _MMIO(0x66d
[Intel-gfx] [PATCH v3 7/9] drm/i915: Add function to output Aksv over GMBUS
Once the Aksv is available in the PCH, we need to get it on the wire to the receiver via DDC. The hardware doesn't allow us to read the value directly, so we need to tell GMBUS to source the Aksv internally and send it to the right offset on the receiver. The way we do this is to initiate an indexed write where the index is the Aksv register offset. We write dummy values to GMBUS3 as if we were sending the key, and the hardware slips in the "real" values when it goes out. Changes in v2: - None Changes in v3: - Uses new index write feature (Ville) Cc: Ville Syrjälä Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_i2c.c | 47 +--- 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bddd65839f60..6b39081c5e53 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4049,6 +4049,7 @@ extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, unsigned int pin); +extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter); extern struct i2c_adapter * intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2bd2cc8441d4..107e16392710 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3043,6 +3043,7 @@ enum i915_power_well_id { # define GPIO_DATA_PULLUP_DISABLE (1 << 13) #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ +#define GMBUS_AKSV_SELECT(1<<11) #define GMBUS_RATE_100KHZ(0<<8) #define GMBUS_RATE_50KHZ (1<<8) #define GMBUS_RATE_400KHZ(2<<8) /* reserved on Pineview */ diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 7399009aee0a..0a4c7486fc7b 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "intel_drv.h" #include #include "i915_drv.h" @@ -497,7 +498,8 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) } static int -do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) +do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, + u32 gmbus0_source) { struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, @@ -507,7 +509,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) int ret = 0; retry: - I915_WRITE_FW(GMBUS0, bus->reg0); + I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); for (; i < num; i += inc) { inc = 1; @@ -629,7 +631,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) if (ret < 0) bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; } else { - ret = do_gmbus_xfer(adapter, msgs, num); + ret = do_gmbus_xfer(adapter, msgs, num, 0); if (ret == -EAGAIN) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } @@ -639,6 +641,45 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) return ret; } +int intel_gmbus_output_aksv(struct i2c_adapter *adapter) +{ + struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, + adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + int ret; + u8 cmd = DRM_HDCP_DDC_AKSV ; + u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; + struct i2c_msg msgs[] = { + { + .addr = DRM_HDCP_DDC_ADDR, + .flags = 0, + .len = sizeof(cmd), + .buf = &cmd, + }, + { + .addr = DRM_HDCP_DDC_ADDR, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + + intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); + mutex_lock(&dev_priv->gmbus_mutex); + + /* +* In order to output Aksv to the receiver, use an indexed write to +* pass the i2c command, and tell GMBUS to use the HW-provided value +* instead of sourcing GMBUS3 for the data. +*/ + ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); + + mutex_unlock(&dev_priv->gmbus_mutex); + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); + + return ret; +} +
[Intel-gfx] [PATCH v3 4/9] drm: Add some HDCP related #defines
In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff will get stuffed in drm_hdcp.h, which is new. Changes in v2: - drm_hdcp.h gets MIT license (Daniel) Changes in v3: - None Cc: Daniel Vetter Signed-off-by: Sean Paul --- include/drm/drm_dp_helper.h | 17 ++ include/drm/drm_hdcp.h | 56 + 2 files changed, 73 insertions(+) create mode 100644 include/drm/drm_hdcp.h diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8b9ac321c3bd..4b2640d54c70 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -815,6 +815,23 @@ #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE0x0 diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h new file mode 100644 index ..c9b2484240d4 --- /dev/null +++ b/include/drm/drm_hdcp.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sean Paul + */ + +#ifndef _DRM_HDCP_H_INCLUDED_ +#define _DRM_HDCP_H_INCLUDED_ + +/* Period of hdcp checks (to ensure we're still authenticated) */ +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +/* Shared lengths/masks between HDMI/DVI/DisplayPort */ +#define DRM_HDCP_AN_LEN8 +#define DRM_HDCP_BSTATUS_LEN 2 +#define DRM_HDCP_KSV_LEN 5 +#define DRM_HDCP_RI_LEN2 +#define DRM_HDCP_V_PRIME_PART_LEN 4 +#define DRM_HDCP_V_PRIME_NUM_PARTS 5 +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f) + +/* Slave address for the HDCP registers in the receiver */ +#define DRM_HDCP_DDC_ADDR 0x3A + +/* HDCP register offsets for HDMI/DVI devices */ +#define DRM_HDCP_DDC_BKSV 0x00 +#define DRM_HDCP_DDC_RI_PRIME 0x08 +#define DRM_HDCP_DDC_AKSV 0x10 +#define DRM_HDCP_DDC_AN0x18 +#define DRM_HDCP_DDC_V_PRIME(h)(0x20 + h * 4) +#define DRM_HDCP_DDC_BCAPS 0x40 +#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) +#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) +#define DRM_HDCP_DDC_BSTATUS 0x41 +#define DRM_HDCP_DDC_KSV_FIFO 0x43 + +#endif -- 2.15.0.531.g2ccb3012c9-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 6/9] drm/i915: Make use of indexed write GMBUS feature
This patch enables the indexed write feature of the GMBUS to concatenate 2 consecutive messages into one. The criteria for an indexed write is that both messages are writes, the first is length == 1, and the second is length > 0. The first message is sent out by the GMBUS as the slave command, and the second one is sent via the GMBUS FIFO as usual. Changes in v3: - Added to series Suggested-by: Ville Syrjälä Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/intel_i2c.c | 39 ++- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 49fdf09f9919..7399009aee0a 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, static int gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, - unsigned short addr, u8 *buf, unsigned int len) + unsigned short addr, u8 *buf, unsigned int len, + u32 gmbus1_index) { unsigned int chunk_size = len; u32 val, loop; @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, I915_WRITE_FW(GMBUS3, val); I915_WRITE_FW(GMBUS1, - GMBUS_CYCLE_WAIT | + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, } static int -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, +u32 gmbus1_index) { u8 *buf = msg->buf; unsigned int tx_size = msg->len; @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) do { len = min(tx_size, GMBUS_BYTE_COUNT_MAX); - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, +gmbus1_index); if (ret) return ret; @@ -430,6 +433,14 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) return 0; } +static int +gmbus_xfer_index_write(struct drm_i915_private *dev_priv, u8 cmd, + struct i2c_msg *msg) +{ + u8 gmbus1_index = GMBUS_CYCLE_INDEX | (cmd << GMBUS_SLAVE_INDEX_SHIFT); + return gmbus_xfer_write(dev_priv, msg, gmbus1_index); +} + /* * The gmbus controller can combine a 1 or 2 byte write with a read that * immediately follows it by using an "INDEX" cycle. @@ -444,6 +455,20 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) (msgs[i + 1].flags & I2C_M_RD)); } +/* + * The gmbus controller can combine a 2-msg write into a single write that + * immediately follows it by using an "INDEX" cycle. + */ +static bool +gmbus_is_index_write(struct i2c_msg *msgs, int i, int num) +{ + return (i + 1 < num && + msgs[i].addr == msgs[i + 1].addr && + !(msgs[i].flags & I2C_M_RD) && + !(msgs[i + 1].flags & I2C_M_RD) && + (msgs[i].len == 1 || msgs[i + 1].len > 0)); +} + static int gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) { @@ -489,10 +514,14 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) if (gmbus_is_index_read(msgs, i, num)) { ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); inc = 2; /* an index read is two msgs */ + } else if (gmbus_is_index_write(msgs, i, num)) { + ret = gmbus_xfer_index_write(dev_priv, msgs[i].buf[0], + &msgs[i + 1]); + inc = 2; /* an index write is two msgs */ } else if (msgs[i].flags & I2C_M_RD) { ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); } else { - ret = gmbus_xfer_write(dev_priv, &msgs[i]); + ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); } if (!ret) -- 2.15.0.531.g2ccb3012c9-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/9] drm: Fix link-status kerneldoc line lengths
I'm adding some stuff below it and it's killing my editor's vibe. Changes in v2: - Added to the series Changes in v3: - None Cc: Manasi Navare Acked-by: Daniel Vetter Signed-off-by: Sean Paul --- drivers/gpu/drm/drm_connector.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 704fc8934616..f14b48e6e839 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -759,10 +759,11 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, * should update this value using drm_mode_connector_set_tile_property(). * Userspace cannot change this property. * link-status: - * Connector link-status property to indicate the status of link. The default - * value of link-status is "GOOD". If something fails during or after modeset, - * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers - * should update this value using drm_mode_connector_set_link_status_property(). + * Connector link-status property to indicate the status of link. The + * default value of link-status is "GOOD". If something fails during or + * after modeset, the kernel driver may set this to "BAD" and issue a + * hotplug uevent. Drivers should update this value using + * drm_mode_connector_set_link_status_property(). * * Connectors also have one standardized atomic property: * -- 2.15.0.531.g2ccb3012c9-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 0/9] drm/i915: Implement HDCP
Oh, hello there. Here's v3 of the HDCP patchset. Highlights of v3 are: - Add atomic_check/commit helpers to intel_hdcp to handle state transitions and call enable/disable at the right time. - intel_hdcp_check_link() gets moved again to avoid being called with locks held - Split out setting the property from the check worker into its own dedicated worker. This avoids deadlock when doing a synchronous cancel with mode_config lock(s) held. - Add internal connector->hdcp_value to track actual state of hardware - Add "indexed writes" to GMBUS driver - Rebase on drm-tip to pick up new wait_for - Tested with igt patch Thanks! Sean Sean Paul (9): drm: Fix link-status kerneldoc line lengths drm/i915: Add more control to wait_for routines drm: Add Content Protection property drm: Add some HDCP related #defines drm/i915: Add HDCP framework + base implementation drm/i915: Make use of indexed write GMBUS feature drm/i915: Add function to output Aksv over GMBUS drm/i915: Implement HDCP for HDMI drm/i915: Implement HDCP for DisplayPort drivers/gpu/drm/drm_atomic.c | 8 + drivers/gpu/drm/drm_connector.c | 80 +++- drivers/gpu/drm/drm_sysfs.c | 1 + drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 85 drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_ddi.c | 50 +++ drivers/gpu/drm/i915/intel_display.c | 14 + drivers/gpu/drm/i915/intel_dp.c | 248 +++- drivers/gpu/drm/i915/intel_drv.h | 107 - drivers/gpu/drm/i915/intel_hdcp.c| 731 +++ drivers/gpu/drm/i915/intel_hdmi.c| 257 drivers/gpu/drm/i915/intel_i2c.c | 86 - drivers/gpu/drm/i915/intel_uncore.c | 23 +- drivers/gpu/drm/i915/intel_uncore.h | 14 +- include/drm/drm_connector.h | 16 + include/drm/drm_dp_helper.h | 17 + include/drm/drm_hdcp.h | 56 +++ include/uapi/drm/drm_mode.h | 4 + 20 files changed, 1767 insertions(+), 34 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c create mode 100644 include/drm/drm_hdcp.h -- 2.15.0.531.g2ccb3012c9-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/9] drm/i915: Add more control to wait_for routines
This patch adds a little more control to a couple wait_for routines such that we can avoid open-coding read/wait/timeout patterns which: - need the value of the register after the wait_for - run arbitrary operation for the read portion This patch also chooses the correct sleep function (based on timers-howto.txt) for the polling interval the caller specifies. Changes in v2: - Added to the series Changes in v3: - Rebased on drm-intel-next-queued and the new Wmin/max _wait_for - Removed msleep option Suggested-by: Chris Wilson Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/intel_drv.h| 17 ++--- drivers/gpu/drm/i915/intel_uncore.c | 23 --- drivers/gpu/drm/i915/intel_uncore.h | 14 +- 3 files changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 64426d3e078e..852b3d161754 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -41,20 +41,21 @@ #include /** - * _wait_for - magic (register) wait macro + * __wait_for - magic wait macro * - * Does the right thing for modeset paths when run under kdgb or similar atomic - * contexts. Note that it's important that we check the condition again after - * having timed out, since the timeout could be due to preemption or similar and - * we've never had a chance to check the condition before the timeout. + * Macro to help avoid open coding check/wait/timeout patterns. Note that it's + * important that we check the condition again after having timed out, since the + * timeout could be due to preemption or similar and we've never had a chance to + * check the condition before the timeout. */ -#define _wait_for(COND, US, Wmin, Wmax) ({ \ +#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ int ret__; \ might_sleep(); \ for (;;) { \ bool expired__ = time_after(jiffies, timeout__);\ + OP; \ if (COND) { \ ret__ = 0; \ break; \ @@ -70,7 +71,9 @@ ret__; \ }) -#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) +#define _wait_for(COND, US, Wmin, Wmax)__wait_for(;, (COND), (US), (Wmin), \ + (Wmax)) +#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index b4621271e7a2..9c7d07151f16 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1770,12 +1770,14 @@ int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv, } /** - * intel_wait_for_register - wait until register matches expected state + * __intel_wait_for_register - wait until register matches expected state * @dev_priv: the i915 device * @reg: the register to read * @mask: mask to apply to register value * @value: expected value - * @timeout_ms: timeout in millisecond + * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait + * @slow_timeout_ms: slow timeout in millisecond + * @out_value: optional placeholder to hold registry value * * This routine waits until the target register @reg contains the expected * @value after applying the @mask, i.e. it waits until :: @@ -1786,15 +1788,18 @@ int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv, * * Returns 0 if the register matches the desired condition, or -ETIMEOUT. */ -int intel_wait_for_register(struct drm_i915_private *dev_priv, +int __intel_wait_for_register(struct drm_i915_private *dev_priv, i915_reg_t reg, u32 mask, u32 value, - unsigned int timeout_ms) + unsigned int fast_timeout_us, + unsigned int slow_timeout_ms, + u32 *out_value) { unsigned fw = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); int ret; + u32 reg_value; might_sleep(); @@ -1803,14 +1808,18 @@ int intel_wait_for_register(struct drm_i915_private *dev_priv, ret = __intel_wait_
[Intel-gfx] [GIT PULL] more gvt-next for 4.16
Hi, Here's more gvt-next updates for 4.16. Mostly for final VFIO mdev display dmabuf interface and gvt implementation which have been reviewed by VFIO maintainer and acked to push through gvt merge path. User space qemu support was sent as https://lists.nongnu.org/archive/html/qemu-devel/2017-10/msg02213.html, and tracked at https://www.kraxel.org/cgit/qemu/log/?h=work/intel-vgpu Others include VFIO opregion support, scheduler optimization and preemption fix, etc. thanks -- The following changes since commit f2880e04f3a5419366926182fc97a3c2e4fd8f2a: drm/i915/gvt: Move request alloc to dispatch_workload path only (2017-11-16 11:51:55 +0800) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-next-2017-12-05 for you to fetch changes up to 1603660b3342269c95fcafee1945790342a8c28e: drm/i915/gvt: set max priority for gvt context (2017-12-04 11:24:35 +0800) gvt-next-2017-12-05 - VFIO mdev display dmabuf interface and gvt support (Tina) - VFIO mdev opregion support/fixes (Tina/Xiong/Chris) - workload scheduling optimization (Changbin) - preemption fix and temporal workaround (Zhenyu) - and misc fixes after refactor (Chris) Changbin Du (2): drm/i915/gvt: Convert macro queue_workload to a function drm/i915/gvt: Kick scheduler when new workload queued Chris Wilson (2): drm/i915/gvt: Cleanup unwanted public symbols drm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[] Tina Zhang (7): drm/i915/gvt: Add opregion support drm/i915/gvt: Add framebuffer decoder support vfio: ABI for mdev display dma-buf operation drm/i915/gvt: Dmabuf support for GVT-g drm/i915/gvt: Handle orphan dmabuf_objs drm/i915/gvt: Introduce KBL to dma-buf on Gvt-g drm/i915/gvt: Free dmabuf_obj list in intel_vgpu_dmabuf_cleanup Xiong Zhang (1): drm/i915/gvt: Alloc and Init guest opregion at vgpu creation Zhenyu Wang (2): drm/i915/gvt: Don't mark vgpu context as inactive when preempted drm/i915/gvt: set max priority for gvt context drivers/gpu/drm/i915/gvt/Makefile | 3 +- drivers/gpu/drm/i915/gvt/cfg_space.c| 3 +- drivers/gpu/drm/i915/gvt/display.c | 2 +- drivers/gpu/drm/i915/gvt/display.h | 2 + drivers/gpu/drm/i915/gvt/dmabuf.c | 538 drivers/gpu/drm/i915/gvt/dmabuf.h | 67 drivers/gpu/drm/i915/gvt/execlist.c | 8 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 508 ++ drivers/gpu/drm/i915/gvt/fb_decoder.h | 169 ++ drivers/gpu/drm/i915/gvt/gvt.c | 2 + drivers/gpu/drm/i915/gvt/gvt.h | 17 +- drivers/gpu/drm/i915/gvt/hypercall.h| 3 + drivers/gpu/drm/i915/gvt/kvmgt.c| 161 +- drivers/gpu/drm/i915/gvt/mpt.h | 45 +++ drivers/gpu/drm/i915/gvt/opregion.c | 137 +--- drivers/gpu/drm/i915/gvt/sched_policy.c | 5 + drivers/gpu/drm/i915/gvt/sched_policy.h | 2 + drivers/gpu/drm/i915/gvt/scheduler.c| 21 +- drivers/gpu/drm/i915/gvt/scheduler.h| 7 +- drivers/gpu/drm/i915/gvt/vgpu.c | 17 +- drivers/gpu/drm/i915/i915_gem_object.h | 2 + include/uapi/linux/vfio.h | 62 22 files changed, 1709 insertions(+), 72 deletions(-) create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i915/gvt: make release_shadow_wa_ctx static.
On 2017.12.04 15:15:28 +0200, Joonas Lahtinen wrote: > + GVT-g list > > Zhenyu, please pick this up. > I've queued fixes from Chris for this and will just send for next pull. thanks. > > On Mon, 2017-12-04 at 09:42 +1000, Dave Airlie wrote: > > From: Dave Airlie > > > > This was removed from the header file in > > d0d51282b8 drm/i915/gvt: Remove one extra declaration in scheduler.h > > > > Make it static then. > > > > Signed-off-by: Dave Airlie > > --- > > drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c > > b/drivers/gpu/drm/i915/gvt/scheduler.c > > index d6177a0..41bccbc 100644 > > --- a/drivers/gpu/drm/i915/gvt/scheduler.c > > +++ b/drivers/gpu/drm/i915/gvt/scheduler.c > > @@ -246,7 +246,7 @@ static int copy_workload_to_ring_buffer(struct > > intel_vgpu_workload *workload) > > return 0; > > } > > > > -void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) > > +static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) > > { > > if (!wa_ctx->indirect_ctx.obj) > > return; > -- > Joonas Lahtinen > Open Source Technology Center > Intel Corporation -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-tip:drm-tip 8/11] drivers/gpu/drm/i915/intel_dsi.c:1673:13: error: storage size of 'plane' isn't known
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip head: da94f258bbf0786f7578d4804a77ce75cf58777f commit: b41c97d7270b82207c5edc7c2d67337b15918462 [8/11] Merge remote-tracking branch 'drm-intel/drm-intel-next-queued' into drm-tip config: i386-randconfig-x007-12041112 (attached as .config) compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025 reproduce: git checkout b41c97d7270b82207c5edc7c2d67337b15918462 # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_dsi.c: In function 'intel_dsi_get_panel_orientation': >> drivers/gpu/drm/i915/intel_dsi.c:1673:13: error: storage size of 'plane' >> isn't known enum plane plane; ^ drivers/gpu/drm/i915/intel_dsi.c:1673:13: warning: unused variable 'plane' [-Wunused-variable] vim +1673 drivers/gpu/drm/i915/intel_dsi.c 4e646495 Jani Nikula 2013-08-27 1668 82daca29 Hans de Goede 2017-11-25 1669 static int intel_dsi_get_panel_orientation(struct intel_connector *connector) 82daca29 Hans de Goede 2017-11-25 1670 { 82daca29 Hans de Goede 2017-11-25 1671 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 82daca29 Hans de Goede 2017-11-25 1672 int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; 82daca29 Hans de Goede 2017-11-25 @1673 enum plane plane; 82daca29 Hans de Goede 2017-11-25 1674 u32 val; 82daca29 Hans de Goede 2017-11-25 1675 82daca29 Hans de Goede 2017-11-25 1676 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 82daca29 Hans de Goede 2017-11-25 1677 if (connector->encoder->crtc_mask == BIT(PIPE_B)) 82daca29 Hans de Goede 2017-11-25 1678 plane = PLANE_B; 82daca29 Hans de Goede 2017-11-25 1679 else 82daca29 Hans de Goede 2017-11-25 1680 plane = PLANE_A; 82daca29 Hans de Goede 2017-11-25 1681 82daca29 Hans de Goede 2017-11-25 1682 val = I915_READ(DSPCNTR(plane)); 82daca29 Hans de Goede 2017-11-25 1683 if (val & DISPPLANE_ROTATE_180) 82daca29 Hans de Goede 2017-11-25 1684 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 82daca29 Hans de Goede 2017-11-25 1685 } 82daca29 Hans de Goede 2017-11-25 1686 82daca29 Hans de Goede 2017-11-25 1687 return orientation; 82daca29 Hans de Goede 2017-11-25 1688 } 82daca29 Hans de Goede 2017-11-25 1689 :: The code at line 1673 was first introduced by commit :: 82daca297506a93354a532f7a08654ef3a646924 drm/i915: Add "panel orientation" property to the panel connector, v6. :: TO: Hans de Goede :: CC: Hans de Goede --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] tests/gem_exec_schedule: Add reset on failed preemption test.
== Series Details == Series: series starting with [v2,1/2] tests/gem_exec_schedule: Add reset on failed preemption test. URL : https://patchwork.freedesktop.org/series/34874/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test kms_frontbuffer_tracking: Subgroup fbc-rgb101010-draw-render: pass -> DMESG-FAIL (shard-hsw) fdo#103167 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 shard-hswtotal:2691 pass:1535 dwarn:1 dfail:1 fail:10 skip:1144 time:9519s shard-snbtotal:2691 pass:1308 dwarn:1 dfail:0 fail:12 skip:1370 time:8104s Blacklisted hosts: shard-apltotal:2691 pass:1687 dwarn:1 dfail:0 fail:22 skip:981 time:13783s shard-kbltotal:2691 pass:1807 dwarn:1 dfail:0 fail:23 skip:860 time:11053s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_595/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix compilation (panel orientation x enum plane rename).
On Tue, Dec 05, 2017 at 12:09:35AM +, Michel Thierry wrote: > On 12/4/2017 4:04 PM, Rodrigo Vivi wrote: > > When commit '82daca297506 ("drm/i915: Add "panel orientation" > > property to the panel connector, v6.")' was done and tested > > by CI, commit 'ed15030d7ab0 ("drm/i915: s/enum plane/enum > > i9xx_plane_id/")' wasn't there already. Ops, the biggest issue now is that one patch is on drm-misc-next while the other one is on drm-intel-next-queued. I would just revert this from drm-misc-next and apply it to dinq with a new fixed version or with this patch on top. But I'm not taking any harsh decision without ack from drm-misc maintainers. I will check to see if I get some ack or better ideas tonight before going to bed or in a hope that someone in Europe timezone get this in the morning and fix it. Thanks, Rodrigo. > > > > On this race the second patch got merged first so the first one > > broke i915 compilation. Thanks to Michel this was found quickly. > > > > Cc: Michel Thierry > > Cc: Daniel Vetter > > Cc: Hans de Goede > > Suggested-by: Michel Thierry > > Fixes: 82daca297506 ("drm/i915: Add "panel orientation" property to the > > panel connector, v6.") > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/intel_dsi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c > > b/drivers/gpu/drm/i915/intel_dsi.c > > index 1b60df3c14a0..f67d321376e4 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -1670,7 +1670,7 @@ static int intel_dsi_get_panel_orientation(struct > > intel_connector *connector) > > { > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > > int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; > > - enum plane plane; > > + enum i9xx_plane_id plane; > > u32 val; > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > > > > Reviewed-by: Michel Thierry ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix compilation (panel orientation x enum plane rename).
On Tue, Dec 05, 2017 at 12:14:22AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix compilation (panel orientation x enum plane rename). > URL : https://patchwork.freedesktop.org/series/34876/ > State : failure > > == Summary == > > Applying: drm/i915: Fix compilation (panel orientation x enum plane rename). > error: Failed to merge in the changes. > Using index info to reconstruct a base tree... > M drivers/gpu/drm/i915/intel_dsi.c > Falling back to patching base and 3-way merge... > Auto-merging drivers/gpu/drm/i915/intel_dsi.c > CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_dsi.c > Patch failed at 0001 drm/i915: Fix compilation (panel orientation x enum > plane rename). > The copy of the patch that failed is found in: .git/rebase-apply/patch > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". > Ouch! commit '82daca297506 ("drm/i915: Add "panel orientation" property to the panel connector, v6.")' is merged on drm-misc, not on drm-intel-next-queued. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
== Series Details == Series: drm/i915: Apply Display WA #1183 on skl, kbl, and cfl URL : https://patchwork.freedesktop.org/series/34873/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 +1 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104009 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2679 pass:1536 dwarn:1 dfail:0 fail:10 skip:1132 time:9464s shard-snbtotal:2663 pass:1297 dwarn:1 dfail:0 fail:12 skip:1352 time:7915s Blacklisted hosts: shard-apltotal:2679 pass:1676 dwarn:1 dfail:0 fail:23 skip:978 time:13623s shard-kbltotal:2679 pass:1795 dwarn:1 dfail:0 fail:23 skip:860 time:10813s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7402/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix compilation (panel orientation x enum plane rename).
== Series Details == Series: drm/i915: Fix compilation (panel orientation x enum plane rename). URL : https://patchwork.freedesktop.org/series/34876/ State : failure == Summary == Applying: drm/i915: Fix compilation (panel orientation x enum plane rename). error: Failed to merge in the changes. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_dsi.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_dsi.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_dsi.c Patch failed at 0001 drm/i915: Fix compilation (panel orientation x enum plane rename). The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] tests/gem_exec_schedule: Add reset on failed preemption test.
== Series Details == Series: series starting with [v2,1/2] tests/gem_exec_schedule: Add reset on failed preemption test. URL : https://patchwork.freedesktop.org/series/34874/ State : success == Summary == IGT patchset tested on top of latest successful build 88b01d822be1e9ab429ef1085f6754a47dae3487 igt/pm_rc6_residency: Measure residency after checking for applicability with latest DRM-Tip kernel build CI_DRM_3452 cee3f135bf4e drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest Testlist changes: +igt@gem_exec_schedule@preemptive-hang-blt +igt@gem_exec_schedule@preemptive-hang-bsd +igt@gem_exec_schedule@preemptive-hang-bsd1 +igt@gem_exec_schedule@preemptive-hang-bsd2 +igt@gem_exec_schedule@preemptive-hang-render +igt@gem_exec_schedule@preemptive-hang-vebox +igt@gem_exec_schedule@preempt-hang-blt +igt@gem_exec_schedule@preempt-hang-bsd +igt@gem_exec_schedule@preempt-hang-bsd1 +igt@gem_exec_schedule@preempt-hang-bsd2 +igt@gem_exec_schedule@preempt-hang-render +igt@gem_exec_schedule@preempt-hang-vebox Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:443s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:450s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:506s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:496s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:478s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:277s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:375s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:261s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:399s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:450s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:488s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:532s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:536s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:541s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:450s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:549s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:421s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:604s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:625s fi-glk-dsi total:288 pass:257 dwarn:0 dfail:0 fail:1 skip:30 time:485s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_595/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: add platform tag to WA
On Mon, Dec 04, 2017 at 09:51:47PM +, Lucas De Marchi wrote: > v2: add more missing platform tags > > Cc: Ville Syrjälä > Cc: Rodrigo Vivi > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index 691600ce48c4..c42a6c672b73 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct > intel_crtc_state *crtc_state) > } > } > > - /* Display WA #1139 */ > + /* Display WA #1139: glk */ > if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && > crtc_state->base.adjusted_mode.htotal > 5460) > return false; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 07ee5ad5a13f..f3384e5f5c49 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct > drm_i915_private *dev_priv) > if (!HAS_PCH_CNP(dev_priv)) > return; > > - /* Display WA #1181 */ > + /* Display WA #1181: gen9,gen10 */ This one here should be "cnp" instead of gen actually. That covers both gen9 and gen10 on this path because it actually depends on pch and not on gen itself. But I just saw on spec it mentions "skl" what is strange since this bit was introduced with CNP PCH... If you resend as cnp feel free to add my rv-b ;) Thanks, Rodrigo. > I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | > CNP_PWM_CGE_GATING_DISABLE); > } > -- > 2.14.3 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix compilation (panel orientation x enum plane rename).
On 12/4/2017 4:04 PM, Rodrigo Vivi wrote: When commit '82daca297506 ("drm/i915: Add "panel orientation" property to the panel connector, v6.")' was done and tested by CI, commit 'ed15030d7ab0 ("drm/i915: s/enum plane/enum i9xx_plane_id/")' wasn't there already. On this race the second patch got merged first so the first one broke i915 compilation. Thanks to Michel this was found quickly. Cc: Michel Thierry Cc: Daniel Vetter Cc: Hans de Goede Suggested-by: Michel Thierry Fixes: 82daca297506 ("drm/i915: Add "panel orientation" property to the panel connector, v6.") Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 1b60df3c14a0..f67d321376e4 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -1670,7 +1670,7 @@ static int intel_dsi_get_panel_orientation(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; - enum plane plane; + enum i9xx_plane_id plane; u32 val; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { Reviewed-by: Michel Thierry ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: follow single notation for workaround number
On Mon, Dec 04, 2017 at 09:51:46PM +, Lucas De Marchi wrote: > v2: Allow to have or omit space before platform > > Cc: Ville Syrjälä > Cc: Rodrigo Vivi > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index 9d5e72728475..691600ce48c4 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct > intel_crtc_state *crtc_state) > } > } > > - /* Display Wa #1139 */ > + /* Display WA #1139 */ > if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && > crtc_state->base.adjusted_mode.htotal > 5460) > return false; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 67f326230a7e..07ee5ad5a13f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -58,7 +58,7 @@ static void gen9_init_clock_gating(struct drm_i915_private > *dev_priv) > if (HAS_LLC(dev_priv)) { > /* >* WaCompressedResourceDisplayNewHashMode:skl,kbl > - * Display WA#0390: skl,kbl > + * Display WA #0390: skl,kbl >* >* Must match Sampler, Pixel Back End, and Media. See >* WaCompressedResourceSamplerPbeMediaNewHashMode. > @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct > drm_i915_private *dev_priv) > if (!HAS_PCH_CNP(dev_priv)) > return; > > - /* Wa #1181 */ > + /* Display WA #1181 */ > I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | > CNP_PWM_CGE_GATING_DISABLE); > } > -- > 2.14.3 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix compilation (panel orientation x enum plane rename).
When commit '82daca297506 ("drm/i915: Add "panel orientation" property to the panel connector, v6.")' was done and tested by CI, commit 'ed15030d7ab0 ("drm/i915: s/enum plane/enum i9xx_plane_id/")' wasn't there already. On this race the second patch got merged first so the first one broke i915 compilation. Thanks to Michel this was found quickly. Cc: Michel Thierry Cc: Daniel Vetter Cc: Hans de Goede Suggested-by: Michel Thierry Fixes: 82daca297506 ("drm/i915: Add "panel orientation" property to the panel connector, v6.") Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 1b60df3c14a0..f67d321376e4 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -1670,7 +1670,7 @@ static int intel_dsi_get_panel_orientation(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; - enum plane plane; + enum i9xx_plane_id plane; u32 val; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { -- 2.13.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v2,1/2] drm/i915: follow single notation for workaround number
== Series Details == Series: series starting with [v2,1/2] drm/i915: follow single notation for workaround number URL : https://patchwork.freedesktop.org/series/34869/ State : warning == Summary == Test kms_cursor_crc: Subgroup cursor-64x21-sliding: pass -> SKIP (shard-hsw) Test kms_plane: Subgroup plane-panning-bottom-right-pipe-b-planes: pass -> SKIP (shard-hsw) Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104009 Test gem_softpin: Subgroup noreloc-s4: fail -> SKIP (shard-snb) fdo#103375 Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) fdo#103060 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 shard-hswtotal:2679 pass:1534 dwarn:1 dfail:0 fail:10 skip:1134 time:9379s shard-snbtotal:2663 pass:1297 dwarn:1 dfail:0 fail:11 skip:1353 time:7912s Blacklisted hosts: shard-apltotal:2679 pass:1677 dwarn:1 dfail:0 fail:22 skip:978 time:13600s shard-kbltotal:2663 pass:1783 dwarn:1 dfail:0 fail:24 skip:854 time:10615s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7401/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_exec_schedule: Add test for resetting preemptive batch
This patch adds a test that will trigger a preemption of a low priority batch by a 'bad' batch buffer which will hang. The test aims at making sure that a hanging high priority batch will not disrupt the submission flow of low priority contexts. -v2: - Rename subtest (Chris) - Use igt_hang_ctx to hang ring (Chris) - Add comment on execution order checks (Chris) Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 37 + 1 file changed, 37 insertions(+) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index d0f85b3e..0c2efaa2 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -515,6 +515,40 @@ static void preempt_self(int fd, unsigned ring) gem_close(fd, result); } +static void preemptive_hang(int fd, unsigned ring) +{ + igt_spin_t *spin[16]; + igt_hang_t hang; + uint32_t ctx[2]; + + ctx[HI] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + + for (int n = 0; n < 16; n++) { + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0); + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); + + gem_context_destroy(fd, ctx[LO]); + } + + hang = igt_hang_ctx(fd, ctx[HI], ring, 0, NULL); + gem_wait(fd, hang.handle, NULL); + + for (int n = 0; n < 16; n++) { + /* Current behavior is to execute requests in order of submission. +* This is subject to change as the scheduler evolve. The test should +* be updated to reflect such changes. +*/ + igt_assert(gem_bo_busy(fd, spin[n]->handle)); + igt_spin_batch_free(fd, spin[n]); + } + + gem_context_destroy(fd, ctx[HI]); +} + static void deep(int fd, unsigned ring) { #define XS 8 @@ -1044,6 +1078,9 @@ igt_main preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); } + igt_subtest_f("preemptive-hang-%s", e->name) + preemptive_hang(fd, e->exec_id | e->flags); + igt_fixture { igt_disallow_hang(fd, hang); igt_fork_hang_detector(fd); -- 2.14.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 1/2] tests/gem_exec_schedule: Add reset on failed preemption test.
This patch adds a test where a low priority batch is going to be declared hung while a preemption is pending. The test wants to verify that a 'hanging' low priority batch will not disrupt the execution of a high priority context and that the driver does due diligence in managing a reset while a preemption is pending. -v2: - Use igt_hang_ctx to hang the engine (Chris) - Enable/Process engine reset using IGT libs (Chris) - Create new subtest_group for the test (Chris) Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index a2f4419a..d0f85b3e 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -356,13 +356,15 @@ static void promotion(int fd, unsigned ring) munmap(ptr, 4096); } -#define NEW_CTX 0x1 +#define NEW_CTX (0x1 << 0) +#define HANG_LP (0x1 << 1) static void preempt(int fd, unsigned ring, unsigned flags) { uint32_t result = gem_create(fd, 4096); uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ); igt_spin_t *spin[16]; uint32_t ctx[2]; + igt_hang_t hang; ctx[LO] = gem_context_create(fd); gem_context_set_priority(fd, ctx[LO], MIN_PRIO); @@ -370,6 +372,9 @@ static void preempt(int fd, unsigned ring, unsigned flags) ctx[HI] = gem_context_create(fd); gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + if (flags & HANG_LP) + hang = igt_hang_ctx(fd, ctx[LO], ring, 0, NULL); + for (int n = 0; n < 16; n++) { if (flags & NEW_CTX) { gem_context_destroy(fd, ctx[LO]); @@ -389,6 +394,9 @@ static void preempt(int fd, unsigned ring, unsigned flags) for (int n = 0; n < 16; n++) igt_spin_batch_free(fd, spin[n]); + if (flags & HANG_LP) + igt_post_hang_ring(fd, hang); + gem_context_destroy(fd, ctx[LO]); gem_context_destroy(fd, ctx[HI]); @@ -1023,6 +1031,24 @@ igt_main igt_subtest_f("preempt-self-%s", e->name) preempt_self(fd, e->exec_id | e->flags); + + igt_subtest_group { + igt_hang_t hang; + + igt_fixture { + igt_stop_hang_detector(); + hang = igt_allow_hang(fd, 0, 0); + } + + igt_subtest_f("preempt-hang-%s", e->name) { + preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); + } + + igt_fixture { + igt_disallow_hang(fd, hang); + igt_fork_hang_detector(fd); + } + } } igt_subtest_f("deep-%s", e->name) -- 2.14.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
== Series Details == Series: drm/i915: Apply Display WA #1183 on skl, kbl, and cfl URL : https://patchwork.freedesktop.org/series/34873/ State : success == Summary == Series 34873v1 drm/i915: Apply Display WA #1183 on skl, kbl, and cfl https://patchwork.freedesktop.org/api/1.0/series/34873/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> FAIL (fi-skl-6700k) fdo#103191 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:443s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:445s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:387s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:516s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:500s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:491s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:477s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:372s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:395s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:450s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:484s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:532s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:531s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:538s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s fi-skl-6700k total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:517s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:447s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:549s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:415s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:606s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:641s fi-glk-dsi total:288 pass:245 dwarn:1 dfail:4 fail:0 skip:38 time:535s cee3f135bf4e95188222d7a5ffaeb1e4f0185fc9 drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest 06bdc16eade0 drm/i915: Apply Display WA #1183 on skl, kbl, and cfl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7402/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-tip:drm-tip 8/11] drivers/gpu//drm/i915/intel_dsi.c:1673:13: error: unused variable 'plane'
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip head: da94f258bbf0786f7578d4804a77ce75cf58777f commit: b41c97d7270b82207c5edc7c2d67337b15918462 [8/11] Merge remote-tracking branch 'drm-intel/drm-intel-next-queued' into drm-tip config: x86_64-randconfig-x009-201749 (attached as .config) compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025 reproduce: git checkout b41c97d7270b82207c5edc7c2d67337b15918462 # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/gpu//drm/i915/intel_dsi.c: In function 'intel_dsi_get_panel_orientation': drivers/gpu//drm/i915/intel_dsi.c:1673:13: error: storage size of 'plane' isn't known enum plane plane; ^ >> drivers/gpu//drm/i915/intel_dsi.c:1673:13: error: unused variable 'plane' >> [-Werror=unused-variable] cc1: all warnings being treated as errors vim +/plane +1673 drivers/gpu//drm/i915/intel_dsi.c 4e646495 Jani Nikula 2013-08-27 1668 82daca29 Hans de Goede 2017-11-25 1669 static int intel_dsi_get_panel_orientation(struct intel_connector *connector) 82daca29 Hans de Goede 2017-11-25 1670 { 82daca29 Hans de Goede 2017-11-25 1671 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 82daca29 Hans de Goede 2017-11-25 1672 int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; 82daca29 Hans de Goede 2017-11-25 @1673 enum plane plane; 82daca29 Hans de Goede 2017-11-25 1674 u32 val; 82daca29 Hans de Goede 2017-11-25 1675 82daca29 Hans de Goede 2017-11-25 1676 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 82daca29 Hans de Goede 2017-11-25 1677 if (connector->encoder->crtc_mask == BIT(PIPE_B)) 82daca29 Hans de Goede 2017-11-25 1678 plane = PLANE_B; 82daca29 Hans de Goede 2017-11-25 1679 else 82daca29 Hans de Goede 2017-11-25 1680 plane = PLANE_A; 82daca29 Hans de Goede 2017-11-25 1681 82daca29 Hans de Goede 2017-11-25 1682 val = I915_READ(DSPCNTR(plane)); 82daca29 Hans de Goede 2017-11-25 1683 if (val & DISPPLANE_ROTATE_180) 82daca29 Hans de Goede 2017-11-25 1684 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 82daca29 Hans de Goede 2017-11-25 1685 } 82daca29 Hans de Goede 2017-11-25 1686 82daca29 Hans de Goede 2017-11-25 1687 return orientation; 82daca29 Hans de Goede 2017-11-25 1688 } 82daca29 Hans de Goede 2017-11-25 1689 :: The code at line 1673 was first introduced by commit :: 82daca297506a93354a532f7a08654ef3a646924 drm/i915: Add "panel orientation" property to the panel connector, v6. :: TO: Hans de Goede :: CC: Hans de Goede --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
Display WA #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." This workaround was designed to minimize the impact only to save the bad case with that link rates. But HW engineers indicated that it should be safe to apply broadly, although they were expecting the DPLL0 link rate to be unchanged on runtime. We need to cover 2 cases: when we are in fact enabling DPLL0 and when we are just changing the frequency with small differences. This is based on previous patch by Rodrigo Vivi with suggestions from Ville Syrjälä. Cc: Arthur J Runyan Cc: Ville Syrjälä Cc: Rodrigo Vivi Cc: sta...@vger.kernel.org Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_cdclk.c | 35 - drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++ 3 files changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bf043c1c2e..73335e709ed6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7021,6 +7021,7 @@ enum { #define RESET_PCH_HANDSHAKE_ENABLE(1<<4) #define GEN8_CHICKEN_DCPR_1_MMIO(0x46430) +#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30) #define MASK_WAKEMEM (1<<13) #define SKL_DFSM _MMIO(0x51000) @@ -8575,6 +8576,7 @@ enum skl_power_gate { #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) +#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19) #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) #define BXT_CDCLK_SSA_PRECHARGE_ENABLE(1<<16) #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 9c5ceb98d48f..d77e2bec1e29 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -931,16 +931,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { - int min_cdclk = skl_calc_cdclk(0, vco); u32 val; WARN_ON(vco != 810 && vco != 864); - /* select the minimum CDCLK before enabling DPLL 0 */ - val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); - I915_WRITE(CDCLK_CTL, val); - POSTING_READ(CDCLK_CTL); - /* * We always enable DPLL0 with the lowest link rate possible, but still * taking into account the VCO required to operate the eDP panel at the @@ -994,7 +988,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, { int cdclk = cdclk_state->cdclk; int vco = cdclk_state->vco; - u32 freq_select; + u32 freq_select, cdclk_ctl; int ret; mutex_lock(&dev_priv->pcu_lock); @@ -1009,7 +1003,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, return; } - /* set CDCLK_CTL */ + /* Choose frequency for this cdclk */ switch (cdclk) { default: WARN_ON(cdclk != dev_priv->cdclk.hw.ref); @@ -1036,10 +1030,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv->cdclk.hw.vco != vco) skl_dpll0_disable(dev_priv); + cdclk_ctl = I915_READ(CDCLK_CTL); + + if (dev_priv->cdclk.hw.vco != vco) { + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + } + + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, cdclk_ctl); + POSTING_READ(CDCLK_CTL); + if (dev_priv->cdclk.hw.vco != vco) skl_dpll0_enable(dev_priv, vco); - I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, cdclk_ctl); POSTING_READ(CDCLK_CTL); /* inform PCU of the change */ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8315499452dc..35796fa8e6b4 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -598,6 +598,11 @@ void g
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: savely free connectors from connector_iter
== Series Details == Series: drm: savely free connectors from connector_iter URL : https://patchwork.freedesktop.org/series/34863/ State : success == Summary == Test kms_flip: Subgroup dpms-vs-vblank-race-interruptible: pass -> FAIL (shard-hsw) fdo#103060 Subgroup plain-flip-ts-check-interruptible: pass -> FAIL (shard-hsw) fdo#100368 +1 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 +1 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104009 +1 Test gem_softpin: Subgroup noreloc-s4: fail -> SKIP (shard-snb) fdo#103375 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 shard-hswtotal:2663 pass:1521 dwarn:1 dfail:0 fail:13 skip:1127 time:9210s shard-snbtotal:2663 pass:1297 dwarn:1 dfail:0 fail:11 skip:1353 time:7898s Blacklisted hosts: shard-apltotal:2679 pass:1677 dwarn:2 dfail:0 fail:21 skip:978 time:13577s shard-kbltotal:2679 pass:1795 dwarn:1 dfail:0 fail:23 skip:860 time:10283s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7400/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: follow single notation for workaround number
== Series Details == Series: series starting with [v2,1/2] drm/i915: follow single notation for workaround number URL : https://patchwork.freedesktop.org/series/34869/ State : success == Summary == Series 34869v1 series starting with [v2,1/2] drm/i915: follow single notation for workaround number https://patchwork.freedesktop.org/api/1.0/series/34869/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:437s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:441s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:386s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:526s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:507s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:517s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:493s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:477s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:288s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:373s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:261s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:395s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:457s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:492s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:532s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:484s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:535s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:544s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:566s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:519s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:503s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:453s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:553s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:421s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:610s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:615s fi-glk-dsi total:288 pass:257 dwarn:1 dfail:0 fail:0 skip:30 time:478s cee3f135bf4e95188222d7a5ffaeb1e4f0185fc9 drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest 6612bb11742a drm/i915: add platform tag to WA 05d7792236ca drm/i915: follow single notation for workaround number == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7401/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-firmware pull request(SKL:DMC)
>-Original Message- >From: Josh Boyer [mailto:jwbo...@kernel.org] >Sent: Monday, December 4, 2017 6:37 AM >To: Srivatsa, Anusha >Cc: linux-firmw...@kernel.org; Intel Graphics Development g...@lists.freedesktop.org>; Ben Hutchings ; Kyle >McMartin >Subject: Re: linux-firmware pull request(SKL:DMC) > >On Mon, Nov 27, 2017 at 6:13 PM, Anusha Srivatsa >wrote: >> Hi Ben, Kyle, >> >> Please consider pulling i915 updates to linux-firmware.git. >> >> i915-firmware-2017-11-27 >> The following changes since commit >17e6288135d4500f9fe60224dce2b46d850c346b: >> >> brcm: update firmware for bcm4358 (2017-11-25 10:15:53 -0500) >> >> are available in the git repository at: >> >> ssh://git.freedesktop.org/git/drm/drm-firmware.git master >> >> for you to fetch changes up to 02d857ee316f6f611b6622ef78892d38d0909700: >> >> linux-firmware: DMC firmware for skylake v1.27 (2017-11-27 14:36:28 >> -0800) >> >> >> Anusha Srivatsa (1): >> linux-firmware: DMC firmware for skylake v1.27 >> >> WHENCE | 3 ++- >> i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes >> 2 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 >> i915/skl_dmc_ver1_27.bin > >Merged. Thanks! Thanks a lot Josh! Anusha >josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 0/7] drm/fbdev: Panel orientation connector property support
Hi, On 01-12-17 19:02, Bartlomiej Zolnierkiewicz wrote: On Saturday, November 25, 2017 08:35:46 PM Hans de Goede wrote: Here is v7 of my series to add a "panel orientation" property to the drm-connector for the LCD panel to let userspace know about LCD panels which are not mounted upright, as well as detecting upside-down panels without needing quirks (like we do for 90 degree rotated screens). Bartlomiej, can we please have your Acked-by for merging patches 1, 6 and 7 through the drm tree? Acked-by: Bartlomiej Zolnierkiewicz Thank you. Given that you add (can be in a incremental patch) a comment to: drivers/gpu/drm/drm_panel_orientation_quirks.c [ at the top ] I've fixed this up before merging, adding this comment: * Note the quirks in this file are shared with fbdev/efifb and as such * must not depend on other drm code. and drivers/gpu/drm/Kconfig [ to config DRM_PANEL_ORIENTATION_QUIRKS ] Not everyone likes adding comments to Kconfig files I've had push-back against that in the past. So I will post a follow-up patch for this and then we will see from there. explaining that the code in question is shared with fbdev/efifb (so hopefully people will be careful and not try to make this code DRM specific at some point in a future). Regards, Hans New in v7: -Fix embarrassing build error in efifb due to me only rebuilding modules after cleanups from v6 New in v6: -Fix / reference kernel-doc comments -Don't export the DRM_MODE_PANEL_ORIENTATION_* defines in the UAPI -Move i915 dsi hardware rotation state read-out to intel_dsi_init() New in v5: -Add kernel-doc comment documenting drm_get_panel_orientation_quirk() -drm_fb_helper: Only use hardware (crtc primary plane) rotation for 180 degrees for now as 9-/270 degrees rotation requires special handling New in v4: -Fix drm_fb_helper code setting an invalid rotation value on the primary plane of disabled/unused crtcs (caught by Fi.CI) New in v3: -As requested by Daniel v3 moves the quirks over from the fbdev subsys to the drm subsys. I've done this by simpy starting with a copy of the quirk table and eventually removing the fbdev version. The 1st patch in this series is a small fbdev/fbcon patch, patches 2-5 are all drm patches and patches 6-7 are fbdev/fbcon patches again. As discussed previously the plan is to merge all 7 patches through the drm tree. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/3] lib: avoid < in gtkdoc comments
== Series Details == Series: series starting with [1/3] lib: avoid < in gtkdoc comments URL : https://patchwork.freedesktop.org/series/34865/ State : warning == Summary == IGT patchset tested on top of latest successful build 88b01d822be1e9ab429ef1085f6754a47dae3487 igt/pm_rc6_residency: Measure residency after checking for applicability with latest DRM-Tip kernel build CI_DRM_3452 cee3f135bf4e drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest No testlist changes. Test kms_force_connector_basic: Subgroup force-connector-state: pass -> SKIP (fi-ivb-3520m) Subgroup force-edid: pass -> SKIP (fi-ivb-3520m) Subgroup force-load-detect: pass -> SKIP (fi-ivb-3520m) Subgroup prune-stale-modes: pass -> SKIP (fi-ivb-3520m) fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:450s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:526s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:509s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:491s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:476s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:273s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:542s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:374s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:263s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:402s fi-ivb-3520m total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:485s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:451s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:489s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:528s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:473s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:531s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:543s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:518s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:498s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:550s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:425s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:606s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:627s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:493s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_594/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915: add platform tag to WA
v2: add more missing platform tags Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 691600ce48c4..c42a6c672b73 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) } } - /* Display WA #1139 */ + /* Display WA #1139: glk */ if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && crtc_state->base.adjusted_mode.htotal > 5460) return false; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 07ee5ad5a13f..f3384e5f5c49 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) if (!HAS_PCH_CNP(dev_priv)) return; - /* Display WA #1181 */ + /* Display WA #1181: gen9,gen10 */ I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | CNP_PWM_CGE_GATING_DISABLE); } -- 2.14.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915: follow single notation for workaround number
v2: Allow to have or omit space before platform Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9d5e72728475..691600ce48c4 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) } } - /* Display Wa #1139 */ + /* Display WA #1139 */ if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && crtc_state->base.adjusted_mode.htotal > 5460) return false; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 67f326230a7e..07ee5ad5a13f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -58,7 +58,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) if (HAS_LLC(dev_priv)) { /* * WaCompressedResourceDisplayNewHashMode:skl,kbl -* Display WA#0390: skl,kbl +* Display WA #0390: skl,kbl * * Must match Sampler, Pixel Back End, and Media. See * WaCompressedResourceSamplerPbeMediaNewHashMode. @@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) if (!HAS_PCH_CNP(dev_priv)) return; - /* Wa #1181 */ + /* Display WA #1181 */ I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | CNP_PWM_CGE_GATING_DISABLE); } -- 2.14.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Use exponential backoff for wait_for()
On 11/29/2017 11:55 PM, Sagar Arun Kamble wrote: On 11/30/2017 12:45 PM, John Harrison wrote: On 11/29/2017 10:19 PM, Sagar Arun Kamble wrote: On 11/30/2017 8:34 AM, John Harrison wrote: On 11/24/2017 6:12 AM, Chris Wilson wrote: Quoting Michał Winiarski (2017-11-24 12:37:56) Since we see the effects for GuC preeption, let's gather some evidence. (SKL) intel_guc_send_mmio latency: 100 rounds of gem_exec_latency --r '*-preemption' drm-tip: usecs : count distribution 0 -> 1 : 0|| 2 -> 3 : 0|| 4 -> 7 : 0|| 8 -> 15 : 44 || 16 -> 31 : 1088 || 32 -> 63 : 832 || 64 -> 127: 0|| 128 -> 255: 0|| 256 -> 511: 12 || 512 -> 1023 : 0|| 1024 -> 2047 : 29899|* | 2048 -> 4095 : 131033 || Such pretty graphs. Reminds me of the bpf hist output, I wonder if we could create a tracepoint/kprobe that would output a histogram for each waiter (filterable ofc). Benefit? Just thinking of tuning the spin/sleep, in which case overall metrics are best (intel_eait_for_register needs to be optimised for the typical case). I am wondering if we could tune the spin period down to 5us, 2us? And then have the 10us sleep. We would also need a typical workload to run, it's profile-guided optimisation after all. Hmm. -Chris It took me a while to get back to this but I've now had chance to run with this exponential backoff scheme on the original system that showed the problem. It was a slightly messy back port due to the customer tree being much older than current nightly. I'm pretty sure I got it correct though. However, I'm not sure what the recommendation is for the two timeout values. Using the default of '10, 10' in the patch, I still get lots of very long delays. Recommended setting currently is Wmin=10, Wmax=10 for wait_for_us and Wmin=10, Wmax=1000 for wait_for. Exponential backoff is more helpful inside wait_for if wait_for_us prior to wait_for is smaller. Setting Wmax less than Wmin is effectively changing the backoff strategy to just linear waits of Wmin. I have to up the Wmin value to at least 140 to get a stall free result. Which is plausible given that the big spike in the results of any fast version is at 110-150us. Also of note is that a Wmin between 10 and 110 actually makes things worse. Changing Wmax has no effect. In the following table, 'original' is the original driver before any changes and 'retry loop' is the version using the first workaround of just running the busy poll wait in a 10x loop. The other columns are using the backoff patch with the given Wmin/Wmax values. Note that the times are bucketed to 10us up to 500us and then in 500us lumps thereafter. The value listed is the lower limit, i.e. there were no times of <10us measured. Each case was run for 1000 samples. Below setting like in current nightly will suit this workload and as you have found this will also likely complete most waits in <150us. If many samples had been beyond 160us and less than 300us we might have been needed to change Wmin to may be 15 or 20 to ensure the exponential rise caps around 300us. wait_for_us(10, 10) wait_for() #define wait_for _wait_for(10, 1000) But as shown in the table, a setting of 10/10 does not work well for this workload. The best results possible are a large spike of waits in the 120-130us bucket with a small tail out to 150us. Whereas, the 10/10 setting produces a spike from 150-170us with the tail extending to 240us and an appreciable number of samples stretching all the way out to the 1-10ms range. A regular delay of multiple milliseconds is not acceptable when this path is supposed to be a low latency pre-emption to switch to some super high priority time critical task. And as noted, I did try a bunch of different settings for Wmax but nothing seemed to make much of a difference. E.g. 10/10 vs 10/1000 produced pretty much identical results. Hence it didn't seem worth including those in the table. Wmin = 10us leads us to total delay of 150us in 3 loops (this might be tight to catch most conditions) Wmin = 25us can lead us to total delay of 175us in 3 loops Since most conditions are likely to complete around 140us-160us, Looks like Wmin of 25 to 30 (25,1000 or 30, 1000) will suit this workload but sinc
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: savely free connectors from connector_iter
== Series Details == Series: drm: savely free connectors from connector_iter URL : https://patchwork.freedesktop.org/series/34863/ State : success == Summary == Series 34863v1 drm: savely free connectors from connector_iter https://patchwork.freedesktop.org/api/1.0/series/34863/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:437s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:440s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:384s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:524s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:509s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:486s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:474s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:539s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:369s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:260s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:396s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:479s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:449s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:486s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:524s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:487s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:540s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:543s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:562s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:518s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:443s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:550s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:411s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:615s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:633s fi-glk-dsi total:288 pass:186 dwarn:1 dfail:4 fail:1 skip:96 time:381s cee3f135bf4e95188222d7a5ffaeb1e4f0185fc9 drm-tip: 2017y-12m-04d-21h-06m-29s UTC integration manifest 05169ac37cea drm: savely free connectors from connector_iter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7400/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] HDCP as a Kconfig option
Hi, I understand there there's concerns about the content protection stuff, but please note: - The patches under discussion enforce nothing, they only allow you to enable HDCP if you chose to do so. For real content protection you need a complete system, locked down with secure boot or similar. I think any user concerned about their software freedoms knows to avoid such systems like the plague. - Second, the code doesn't run by default at all. You can try to enable HDCP only by explicitly requesting content protection through a drm property (which I think should be exposed to xrandr by default at least for the modesetting driver). Enterprising users can try out what happens if they want to, but by default nothing at all happens. So no risk of random breakage due to this. Given those two reasons I don't think we need a Kconfig option to disable the code even harder. I hope that explains the situation, and why the patches don't have a Kconfig option from the start. Also thanks very much for reaching out to developers instead of everyone else who just panics on forums and passes around silly conspiracy theories. We definitely don't want to merge code which would hurt our users, that would kinda defeat the point of doing an open source driver. I don't think this is the case here. Cheers, Daniel On Mon, Dec 4, 2017 at 2:20 AM, A. Wilcox wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA256 > > (Note: I am not subscribed to the list, please cc me with replies.) > > Hello i915 developers, > > I represent Adélie Linux, a Linux distribution that has the goal of > empowering users through the true freedom that only libre software can > provide. This new HDCP support patch for i915 has generated a lot of > talking in our community, because even though it is 'open source' it > implements hardware DRM. We feel this to not be in the spirit of > libre software. Hardware DRM unevenly puts all of the control in the > hands of hardware manufacturers and content producers, instead of with > the people who have paid their hard-earned money to support them. > > In addition, different hardware supports different versions of HDCP, > and in some cases, display panels and hardware cannot even speak the > same version, which ends up being a nightmare for users who do not > understand how video links work and just want to see a picture on > their monitor. > > As such, we, the Adélie Linux distribution, respectfully request that > the HDCP support – if added to the i915 driver (and if this is later > factored out to generic code, then the generic framework itself) – be > controllable via a CONFIG_ option in Kconfig, so that we may remove > the entire feature from the module in our kernel package. > > Thank you very much for your time and consideration. > > Regards, > - --arw > > - -- > A. Wilcox (awilfox) > Project Lead, Adélie Linux > http://adelielinux.org > -BEGIN PGP SIGNATURE- > Version: GnuPG v2 > > iQIcBAEBCAAGBQJaJKLIAAoJEMspy1GSK50UMoEP/js0Jex7ToozGriWfzBxPClG > Q0j8IMpDtKPrcktCTdp4Oo5pIYJcu33p3MG+LYmc/CNIKJ2WZIEPDoY5h2CoXLUg > T9KhqiiqCMDeHqzuMpeb0C6dWhuzIJOYo3Q8+pDQLAtslWorLExZCN2vm5l2LeZO > Xa1PG7wwjYGpTCU94e+Z3frBpIVFRb8IYO2N3CvcEu0G06nhQzHSyP+FplITiHpW > 7G0vOs6Vg0UXyRvhgORr6XYLpWOHBcUwhzkJRAxnUbUOGNKihpy+8cWRuHqmt2bc > MjfRQD5F3gqQJfG4GcksuAzJ8woUA/t+URRx/b3QXw1chY4CGnADYqtOAx5iAnIf > Kbgx4RssABypFOXrOCOzdQhS9b21HogvBwLmwgaHxTGGtUi8m3K65XSyEnN3ZSqw > PU1pVbBma/uh3REUXZmT5GskJckIjJngyjMJnfq77YZVYxIC9sPiA4rTmLL4Z2D3 > s5sTaBd5cdIcDOnlcF0P+rUJSLEos6A2DNu8S/T4AwS3tYg4AtceduHVA9m2Sl71 > XsyKp3KsWAh3A4oLXuPKWJWgJDG3M4MBp/vWg1+ORopnhMz62Gt3mX2GcE3jmLQt > GRxXwpodyeSGTq/PxwQpr+7gpGm2Wb14wru0kSB2hgeP8V5cUy+7I9hvBY8YTj7F > aIsMmPkww8F2ge3KJbU0 > =9mDI > -END PGP SIGNATURE- > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] HDCP as a Kconfig option
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 (Note: I am not subscribed to the list, please cc me with replies.) Hello i915 developers, I represent Adélie Linux, a Linux distribution that has the goal of empowering users through the true freedom that only libre software can provide. This new HDCP support patch for i915 has generated a lot of talking in our community, because even though it is 'open source' it implements hardware DRM. We feel this to not be in the spirit of libre software. Hardware DRM unevenly puts all of the control in the hands of hardware manufacturers and content producers, instead of with the people who have paid their hard-earned money to support them. In addition, different hardware supports different versions of HDCP, and in some cases, display panels and hardware cannot even speak the same version, which ends up being a nightmare for users who do not understand how video links work and just want to see a picture on their monitor. As such, we, the Adélie Linux distribution, respectfully request that the HDCP support – if added to the i915 driver (and if this is later factored out to generic code, then the generic framework itself) – be controllable via a CONFIG_ option in Kconfig, so that we may remove the entire feature from the module in our kernel package. Thank you very much for your time and consideration. Regards, - --arw - -- A. Wilcox (awilfox) Project Lead, Adélie Linux http://adelielinux.org -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQIcBAEBCAAGBQJaJKLIAAoJEMspy1GSK50UMoEP/js0Jex7ToozGriWfzBxPClG Q0j8IMpDtKPrcktCTdp4Oo5pIYJcu33p3MG+LYmc/CNIKJ2WZIEPDoY5h2CoXLUg T9KhqiiqCMDeHqzuMpeb0C6dWhuzIJOYo3Q8+pDQLAtslWorLExZCN2vm5l2LeZO Xa1PG7wwjYGpTCU94e+Z3frBpIVFRb8IYO2N3CvcEu0G06nhQzHSyP+FplITiHpW 7G0vOs6Vg0UXyRvhgORr6XYLpWOHBcUwhzkJRAxnUbUOGNKihpy+8cWRuHqmt2bc MjfRQD5F3gqQJfG4GcksuAzJ8woUA/t+URRx/b3QXw1chY4CGnADYqtOAx5iAnIf Kbgx4RssABypFOXrOCOzdQhS9b21HogvBwLmwgaHxTGGtUi8m3K65XSyEnN3ZSqw PU1pVbBma/uh3REUXZmT5GskJckIjJngyjMJnfq77YZVYxIC9sPiA4rTmLL4Z2D3 s5sTaBd5cdIcDOnlcF0P+rUJSLEos6A2DNu8S/T4AwS3tYg4AtceduHVA9m2Sl71 XsyKp3KsWAh3A4oLXuPKWJWgJDG3M4MBp/vWg1+ORopnhMz62Gt3mX2GcE3jmLQt GRxXwpodyeSGTq/PxwQpr+7gpGm2Wb14wru0kSB2hgeP8V5cUy+7I9hvBY8YTj7F aIsMmPkww8F2ge3KJbU0 =9mDI -END PGP SIGNATURE- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-firmware pull request(SKL:DMC)
On Mon, Nov 27, 2017 at 6:13 PM, Anusha Srivatsa wrote: > Hi Ben, Kyle, > > Please consider pulling i915 updates to linux-firmware.git. > > i915-firmware-2017-11-27 > The following changes since commit 17e6288135d4500f9fe60224dce2b46d850c346b: > > brcm: update firmware for bcm4358 (2017-11-25 10:15:53 -0500) > > are available in the git repository at: > > ssh://git.freedesktop.org/git/drm/drm-firmware.git master > > for you to fetch changes up to 02d857ee316f6f611b6622ef78892d38d0909700: > > linux-firmware: DMC firmware for skylake v1.27 (2017-11-27 14:36:28 -0800) > > > Anusha Srivatsa (1): > linux-firmware: DMC firmware for skylake v1.27 > > WHENCE | 3 ++- > i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes > 2 files changed, 2 insertions(+), 1 deletion(-) > create mode 100644 i915/skl_dmc_ver1_27.bin Merged. Thanks! josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3 09/29] drm/i915: deprecate pci_get_bus_and_slot()
On 11/28/2017 11:29 AM, Sinan Kaya wrote: > On 11/28/2017 10:30 AM, Ville Syrjälä wrote: >>> + dev_priv->bridge_dev = >>> + pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); >> Maybe just pci_get_slot(pdev->bus, PCI_DEVFN(0, 0)) ? >> >> I guess if we want to be pedantic we could go for: >> >> bus = pci_find_host_bridge(pdev->bus)->bus; >> pci_get_slot(bus, PCI_DEVFN(0, 0)) >> >> but I think the GPU should always be on the root bus, so the simpler >> form should be fine. >> > > All three of these should be correct. > > I'll use pci_get_slot(pdev->bus, PCI_DEVFN(0, 0)) as you suggested. > Now that I think about this more, I think my version is a simpler change and does not introduce "new features" by assuming GPU and host to be on the same bus similar to the original code. Original code could have used pci_get_slot() too. Since all of them are correct, mine is slightly more correct; I'd like to keep mine. -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Implement WaDisableEarlyEOT.
On Fri, Dec 1, 2017 at 3:40 PM, Rafael Antognolli wrote: > There seems to be another clock gating issue which the workaround is > described as: > >"WA: Set 0xE4F0[1] = 1 to disable Early EOT of thread." > > Signed-off-by: Rafael Antognolli Reviewed-by: Lucas De Marchi Lucas De Marchi > --- > drivers/gpu/drm/i915/i915_reg.h| 1 + > drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1358ce1513f6..0f07f5900a6f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8145,6 +8145,7 @@ enum { > #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE(1<<8) > #define STALL_DOP_GATING_DISABLE (1<<5) > #define THROTTLE_12_5(7<<2) > +#define DISABLE_EARLY_EOT(1<<1) > > #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) > #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c > b/drivers/gpu/drm/i915/intel_engine_cs.c > index 86d4c85c8725..bf581a0bb789 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1272,6 +1272,9 @@ static int cnl_init_workarounds(struct intel_engine_cs > *engine) > if (ret) > return ret; > > + /* WaDisableEarlyEOT:cnl */ > + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); > + > return 0; > } > > -- > 2.13.6 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/3] lib: avoid < in gtkdoc comments
For reasons entirely not clear to me meson gtkdoc runs in strict xml parsing mode, whereas automake gtkdoc doesn't. And gtkdoc itself is to dense to correctly escape this stuff. Paper around this. v2: {foo} instead of of tripy(Joonas) Cc: Joonas Lahtinen Signed-off-by: Daniel Vetter --- lib/igt_aux.c | 4 ++-- lib/igt_core.c| 4 ++-- lib/igt_debugfs.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/igt_aux.c b/lib/igt_aux.c index e2424109ef20..8ca0b60d0925 100644 --- a/lib/igt_aux.c +++ b/lib/igt_aux.c @@ -998,7 +998,7 @@ void igt_drop_root(void) * @var: var lookup to to enable this wait * * Waits for a key press when run interactively and when the corresponding debug - * var is set in the --interactive-debug= variable. Multiple keys + * var is set in the --interactive-debug=$var variable. Multiple keys * can be specified as a comma-separated list or alternatively "all" if a wait * should happen for all cases. * @@ -1039,7 +1039,7 @@ void igt_debug_wait_for_keypress(const char *var) * @expected: message to be printed as expected behaviour before wait for keys Y/n * * Waits for a key press when run interactively and when the corresponding debug - * var is set in the --interactive-debug= variable. Multiple vars + * var is set in the --interactive-debug=$var variable. Multiple vars * can be specified as a comma-separated list or alternatively "all" if a wait * should happen for all cases. * diff --git a/lib/igt_core.c b/lib/igt_core.c index 03fa6e4e836b..cc94350874fc 100644 --- a/lib/igt_core.c +++ b/lib/igt_core.c @@ -167,10 +167,10 @@ * test logic. * * - When adding a new feature test function which uses igt_skip() internally, - * use the _require_ naming scheme. When you + * use the {prefix}_require_{feature_name} naming scheme. When you * instead add a feature test function which returns a boolean, because your * main test logic must take different actions depending upon the feature's - * availability, then instead use the _has_. + * availability, then instead use the {prefix}_has_ . * * - As already mentioned eschew explicit error handling logic as much as * possible. If your test absolutely has to handle the error of some function diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c index 9af8a5933480..49b68dfed0aa 100644 --- a/lib/igt_debugfs.c +++ b/lib/igt_debugfs.c @@ -231,7 +231,7 @@ int igt_debugfs_dir(int device) * @mode: mode bits as used by open() * * This opens a debugfs file as a Unix file descriptor. The filename should be - * relative to the drm device's root, i.e. without "drm/". + * relative to the drm device's root, i.e. without "drm/$minor". * * Returns: * The Unix file descriptor for the debugfs file or -1 if that didn't work out. -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/3] meson: gtkdoc support
Bunch of neat improvements: - xml generates correctly depend upon the test binaries - no need to re-run autogen.sh when new chapters/functions get added, all handed by meson Still one issue: - the gtkdoc target doesn't depend upon the custom_target yet, hacked around using build_by_default: true This is an issue known to upstream already: https://github.com/mesonbuild/meson/issues/2148 v2: Bump meson version to 0.42, since that's the first release which adds the build dir when running the gtkdoc tools, and hence allows including generated files. v2: - Undo the bump, it's only needed for generated source files. Other generated files as input should work with 0.40 already. - Generate version.xml from version.xml.in, which allows us to keep the &version; entity. v3: Add github issue link. Signed-off-by: Daniel Vetter --- docs/meson.build | 1 + .../intel-gpu-tools/generate_description_xml.sh| 44 .../intel-gpu-tools/generate_programs_xml.sh | 22 ++ docs/reference/intel-gpu-tools/meson.build | 80 ++ docs/reference/meson.build | 1 + meson.build| 3 + meson.sh | 2 +- tests/meson.build | 6 +- 8 files changed, 157 insertions(+), 2 deletions(-) create mode 100644 docs/meson.build create mode 100644 docs/reference/intel-gpu-tools/generate_description_xml.sh create mode 100755 docs/reference/intel-gpu-tools/generate_programs_xml.sh create mode 100644 docs/reference/intel-gpu-tools/meson.build create mode 100644 docs/reference/meson.build diff --git a/docs/meson.build b/docs/meson.build new file mode 100644 index ..ead14c4015d9 --- /dev/null +++ b/docs/meson.build @@ -0,0 +1 @@ +subdir('reference') diff --git a/docs/reference/intel-gpu-tools/generate_description_xml.sh b/docs/reference/intel-gpu-tools/generate_description_xml.sh new file mode 100644 index ..8e39e0c4c289 --- /dev/null +++ b/docs/reference/intel-gpu-tools/generate_description_xml.sh @@ -0,0 +1,44 @@ +#!/bin/sh + +output=$1 +filter=$2 +testlist=$3 +testdir=$(dirname $testlist) + +echo "" > $output +echo "> $output +echo " \"http://www.oasis-open.org/docbook/xml/4.3/docbookx.dtd\""; >> $output +echo "[" >> $output +echo " http://www.w3.org/2003/XInclude'\">" >> $output +echo " " >> $output +echo "]>" >> $output +echo "" >> $output +echo "Description" >> $output +for test in `cat $testlist | tr ' ' '\n' | grep "^$filter" | sort`; do + echo "" >> $output; + echo "$test" | perl -pe 's/(?<=_)$(KEYWORDS)(?=(_|\W))/\1<\/acronym>/g' >> $output; + echo "" >> $output; + if ./$testprog --list-subtests > /dev/null ; then + echo "Subtests" >> $output; + subtest_list=`./$testprog --list-subtests`; + subtest_count=`echo $subtest_list | wc -w`; + if [ $subtest_count -gt 100 ]; then + echo "This test has over 100 subtests. " >> $output; + echo "Run $test --list-subtests to list them." >> $output; + else + echo "" >> $output; + for subtest in $subtest_list; do + echo "" >> $output; + echo "$subtest" | perl -pe 's/\b$(KEYWORDS)\b/\1<\/acronym>/g' >> $output; + echo "" >> $output; + done; + echo "" >> $output; + fi; + echo "" >> $output; + fi; + echo "" >> $output; +done; +echo "" >> $output diff --git a/docs/reference/intel-gpu-tools/generate_programs_xml.sh b/docs/reference/intel-gpu-tools/generate_programs_xml.sh new file mode 100755 index ..73adc8cc7bfc --- /dev/null +++ b/docs/reference/intel-gpu-tools/generate_programs_xml.sh @@ -0,0 +1,22 @@ +#!/bin/sh + +output=$1 +filter=$2 +testlist=$3 + +echo "" > $output +echo "> $output +echo " \"http://www.oasis-open.org/docbook/xml/4.3/docbookx.dtd\""; >> $output +echo "[" >> $output +echo " http://www.w3.org/2003/XInclude'\">" >> $output +echo " " >> $output +echo "]>" >> $output +echo "" >> $output +echo "Programs" >> $output +echo "" >> $output +for test in `cat $testlist | tr ' ' '\n' | grep "^$filter" | sort`; do + echo "" >> $output; + echo "$test" >> $output; +done; +echo "" >> $output +echo "" >> $output diff --git a/docs/reference/intel-gpu-tools/meson.build b/docs/reference/intel-gpu-tools/meson.build new file mode 100644 index ..1c009229aae2 --- /dev/null +++ b/docs/reference/intel-gpu-tools/meson.build @@ -0,0 +1,80 @@ +gnome = import('gnome') + +ignore_headers = [ + 'gen6_render.h', + 'gen7_media.h', + 'gen7_render.h', + 'gen8_media.h', + 'gen8_render.h', + 'gpgpu
[Intel-gfx] [PATCH i-g-t 3/3] meson: build a full dependency for lib_igt_perf
meson prefers packages dependencies over passing arount static libraries, because those also include linker flags, include dirs and everything else. While at it pull the special cases out from the common build stanzas like we do with other special cases. Just a bit of ocd to keep everything polished. Cc: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- benchmarks/meson.build | 9 +++-- lib/meson.build| 5 - overlay/meson.build| 4 ++-- tests/meson.build | 11 +-- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/benchmarks/meson.build b/benchmarks/meson.build index fa7f07643a97..4afd204f82b2 100644 --- a/benchmarks/meson.build +++ b/benchmarks/meson.build @@ -12,7 +12,6 @@ benchmark_progs = [ 'gem_prw', 'gem_set_domain', 'gem_syslatency', - 'gem_wsim', 'kms_vblank', 'prime_lookup', 'vgem_mmap', @@ -31,11 +30,9 @@ endif foreach prog : benchmark_progs # FIXME meson doesn't like binaries with the same name # meanwhile just suffix with _bench - link = [] - if prog == 'gem_wsim' - link += lib_igt_perf - endif executable(prog + '_bench', prog + '.c', - link_with : link, dependencies : test_deps) endforeach + +executable('gem_wsim_bench', 'gem_wsim.c', + dependencies : test_deps + [ lib_igt_perf ]) diff --git a/lib/meson.build b/lib/meson.build index 29d89cf09b58..d06d85b438b2 100644 --- a/lib/meson.build +++ b/lib/meson.build @@ -180,8 +180,11 @@ lib_igt = declare_dependency(link_with : lib_igt_build, igt_deps = [ lib_igt ] + lib_deps -lib_igt_perf = static_library('igt_perf', +lib_igt_perf_build = static_library('igt_perf', ['igt_perf.c'] ) +lib_igt_perf = declare_dependency(link_with : lib_igt_perf_build, + include_directories : inc) + subdir('tests') diff --git a/overlay/meson.build b/overlay/meson.build index 6b479eb89890..afacff5ecf60 100644 --- a/overlay/meson.build +++ b/overlay/meson.build @@ -21,7 +21,8 @@ dri2proto = dependency('dri2proto', version : '>= 2.6', required : false) cairo_xlib = dependency('cairo-xlib', required : false) xrandr = dependency('xrandr', version : '>=1.3', required : false) -gpu_overlay_deps = [ realtime, math, cairo, pciaccess, libdrm, libdrm_intel ] +gpu_overlay_deps = [ realtime, math, cairo, pciaccess, libdrm, + libdrm_intel, lib_igt_perf ] both_x11_src = '' @@ -55,6 +56,5 @@ if xrandr.found() and cairo.found() include_directories : inc, c_args : gpu_overlay_cflags, dependencies : gpu_overlay_deps, - link_with : lib_igt_perf, install : true) endif diff --git a/tests/meson.build b/tests/meson.build index 088c37ec9b15..58fe0b0557a3 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -193,7 +193,6 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', - 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency', @@ -263,17 +262,17 @@ libexecdir = join_paths(get_option('prefix'), get_option('libexecdir'), 'intel-g test_executables = [] foreach prog : test_progs - link = [] - if prog == 'perf_pmu' - link += lib_igt_perf - endif test_executables += executable(prog, prog + '.c', dependencies : test_deps, install_dir : libexecdir, - link_with : link, install : true) endforeach +test_executables += executable('perf_pmu', 'perf_pmu.c', + dependencies : test_deps + [ lib_igt_perf ], + install_dir : libexecdir, + install : true) + executable('testdisplay', ['testdisplay.c', 'testdisplay_hotplug.c'], dependencies : test_deps, install_dir : libexecdir, -- 2.15.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: savely free connectors from connector_iter
In commit 613051dac40da1751ab269572766d3348d45a197 Author: Daniel Vetter Date: Wed Dec 14 00:08:06 2016 +0100 drm: locking&new iterators for connector_list we've went to extreme lengths to make sure connector iterations works in any context, without introducing any additional locking context. This worked, except for a small fumble in the implementation: When we actually race with a concurrent connector unplug event, and our temporary connector reference turns out to be the final one, then everything breaks: We call the connector release function from whatever context we happen to be in, which can be an irq/atomic context. And connector freeing grabs all kinds of locks and stuff. Fix this by creating a specially safe put function for connetor_iter, which (in this rare case) punts the cleanup to a worker. Reported-by: Ben Widawsky Cc: Ben Widawsky Fixes: 613051dac40d ("drm: locking&new iterators for connector_list") Cc: Dave Airlie Cc: Chris Wilson Cc: Sean Paul Cc: # v4.11+ Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_connector.c | 28 ++-- drivers/gpu/drm/drm_mode_config.c | 2 ++ include/drm/drm_connector.h | 8 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 25f4b2e9a44f..482014137953 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -152,6 +152,16 @@ static void drm_connector_free(struct kref *kref) connector->funcs->destroy(connector); } +static void drm_connector_free_work_fn(struct work_struct *work) +{ + struct drm_connector *connector = + container_of(work, struct drm_connector, free_work); + struct drm_device *dev = connector->dev; + + drm_mode_object_unregister(dev, &connector->base); + connector->funcs->destroy(connector); +} + /** * drm_connector_init - Init a preallocated connector * @dev: DRM device @@ -181,6 +191,8 @@ int drm_connector_init(struct drm_device *dev, if (ret) return ret; + INIT_WORK(&connector->free_work, drm_connector_free_work_fn); + connector->base.properties = &connector->properties; connector->dev = dev; connector->funcs = funcs; @@ -529,6 +541,18 @@ void drm_connector_list_iter_begin(struct drm_device *dev, } EXPORT_SYMBOL(drm_connector_list_iter_begin); +/* + * Extra-safe connector put function that works in any context. Should only be + * used from the connector_iter functions, where we never really expect to + * actually release the connector when dropping our final reference. + */ +static void +drm_connector_put_safe(struct drm_connector *conn) +{ + if (refcount_dec_and_test(&conn->base.refcount.refcount)) + schedule_work(&conn->free_work); +} + /** * drm_connector_list_iter_next - return next connector * @iter: connectr_list iterator @@ -561,7 +585,7 @@ drm_connector_list_iter_next(struct drm_connector_list_iter *iter) spin_unlock_irqrestore(&config->connector_list_lock, flags); if (old_conn) - drm_connector_put(old_conn); + drm_connector_put_safe(old_conn); return iter->conn; } @@ -580,7 +604,7 @@ void drm_connector_list_iter_end(struct drm_connector_list_iter *iter) { iter->dev = NULL; if (iter->conn) - drm_connector_put(iter->conn); + drm_connector_put_safe(iter->conn); lock_release(&connector_list_iter_dep_map, 0, _RET_IP_); } EXPORT_SYMBOL(drm_connector_list_iter_end); diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index 7623607c0f1e..346c19c6ce01 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -431,6 +431,8 @@ void drm_mode_config_cleanup(struct drm_device *dev) drm_connector_put(connector); } drm_connector_list_iter_end(&conn_iter); + /* connector_iter drops references in a work item. */ + flush_scheduled_work(); if (WARN_ON(!list_empty(&dev->mode_config.connector_list))) { drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 66d6c99d15e5..c5c753a1be85 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -926,6 +926,14 @@ struct drm_connector { uint8_t num_h_tile, num_v_tile; uint8_t tile_h_loc, tile_v_loc; uint16_t tile_h_size, tile_v_size; + + /** +* @free_work: +* +* Work used only by &drm_connector_iter to be able to clean up a +* connector from any context. +*/ + struct work_struct free_work; }; #define obj_to_connector(x) container_of(x, struct drm_connector, base) -- 2.15.0 ___ Intel-
Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_exec_schedule: Add test for resetting preemptive batch
Quoting Antonio Argenziano (2017-12-04 18:25:16) > > > On 04/12/17 09:42, Chris Wilson wrote: > > Quoting Antonio Argenziano (2017-12-04 17:23:15) > >> This patch adds a test that will trigger a preemption of a low priority > >> batch by a 'bad' batch buffer which will hang. The test aims at making > >> sure that a hanging high priority batch will not disrupt the submission > >> flow of low priority contexts. > >> > >> Cc: Chris Wilson > >> Cc: Michal Winiarski > >> Signed-off-by: Antonio Argenziano > >> --- > >> tests/gem_exec_schedule.c | 39 +++ > >> 1 file changed, 39 insertions(+) > >> > >> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c > >> index ae44a6c0..5a4d63f9 100644 > >> --- a/tests/gem_exec_schedule.c > >> +++ b/tests/gem_exec_schedule.c > >> @@ -511,6 +511,39 @@ static void preempt_self(int fd, unsigned ring) > >> gem_close(fd, result); > >> } > >> > >> +static void bad_preemptive(int fd, unsigned ring) > >> +{ > >> + igt_spin_t *spin[16]; > >> + igt_spin_t *bad; > >> + uint32_t ctx[2]; > >> + > >> + ctx[LO] = gem_context_create(fd); > >> + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); > >> + > >> + ctx[HI] = gem_context_create(fd); > >> + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); > >> + > >> + for (int n = 0; n < 16; n++) { > >> + gem_context_destroy(fd, ctx[LO]); > >> + ctx[LO] = gem_context_create(fd); > >> + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); > >> + > >> + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0, true); > >> + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); > >> + } > >> + > >> + bad = igt_spin_batch_new(fd, ctx[HI], ring, 0, false); > >> + gem_wait(fd, bad->handle, NULL); > >> + > >> + for (int n = 0; n < 16; n++) { > >> + igt_assert(gem_bo_busy(fd, spin[n]->handle)); > >> + igt_spin_batch_free(fd, spin[n]); > >> + } > > > > Is this really policy you want to enforce? I certainly don't intend to > > mandate that the kernel isn't allowed to use RT throttling. > > Yeah, I wasn't sure about that. Is a gem_wait on each of them enough or > should I put a write at the end of each low priority batch to make sure > they actually executed? Just a comment that this is what happens right now, but we may enact a different policy when we have a real scheduler. Part of the trick is remembering which tests are allowed to be broken, because on the whole igt define the behaviour which is expected/relied on by clients. (The converse is also true in that we may scope out the limits of user behaviour in igt and then fix the kernel to suite.) As regards gem_wait(), this here is gem_sync(), and you can neaten up ctx[LO] by scoping the context to the loop. And call this something like preemptive_hang; bad* brings bad memories of tests that were deliberately broken as opposed to demonstrating that the code survives abuse. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Implement WaDisableVFclkgate.
Hi, On Fri, Dec 1, 2017 at 3:40 PM, Rafael Antognolli wrote: > This workaround supposedly fixes some hangs in the VF unit. > > Signed-off-by: Rafael Antognolli > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 5 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 09bf043c1c2e..1358ce1513f6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3875,6 +3875,9 @@ enum { > #define SARBUNIT_CLKGATE_DIS (1 << 5) > #define RCCUNIT_CLKGATE_DIS (1 << 7) > > +#define UNSLICE_UNIT_LEVEL_CLOCK _MMIO(0x9434) I think this should follow the other names (UNSLICE_UNIT_LEVEL_CLKGATE). Otherwise it LGTM. Lucas De Marchi > +#define VFUNIT_CLKGATE_DIS(1 << 20) > + > /* > * Display engine regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 67f326230a7e..87b9bdee48e5 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -8446,6 +8446,11 @@ static void cnl_init_clock_gating(struct > drm_i915_private *dev_priv) > if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) > val |= SARBUNIT_CLKGATE_DIS; > I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); > + > + /* WaDisableVFclkgate:cnl */ > + val = I915_READ(UNSLICE_UNIT_LEVEL_CLOCK); > + val |= VFUNIT_CLKGATE_DIS; > + I915_WRITE(UNSLICE_UNIT_LEVEL_CLOCK, val); > } > > static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) > -- > 2.13.6 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix off-by-one comparison of ring_id
== Series Details == Series: drm/i915/gvt: fix off-by-one comparison of ring_id URL : https://patchwork.freedesktop.org/series/34858/ State : success == Summary == Test kms_flip: Subgroup rcs-wf_vblank-vs-modeset: skip -> PASS (shard-hsw) Test kms_atomic_interruptible: Subgroup atomic-setmode: skip -> PASS (shard-hsw) Test kms_draw_crc: Subgroup draw-method-xrgb2101010-blt-untiled: skip -> PASS (shard-hsw) Subgroup draw-method-xrgb2101010-blt-xtiled: skip -> PASS (shard-hsw) Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (shard-snb) fdo#102707 +2 Subgroup basic-reload-inject: pass -> DMESG-WARN (shard-hsw) fdo#103706 Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-bottom-edge: skip -> PASS (shard-snb) Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-snb) Subgroup fbc-suspend: incomplete -> PASS (shard-hsw) fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#103706 https://bugs.freedesktop.org/show_bug.cgi?id=103706 shard-hswtotal:2680 pass:1533 dwarn:3 dfail:0 fail:10 skip:1133 time:9164s shard-snbtotal:2680 pass:1308 dwarn:2 dfail:0 fail:11 skip:1358 time:7844s Blacklisted hosts: shard-kbltotal:2605 pass:1744 dwarn:1 dfail:0 fail:23 skip:837 time:10512s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7399/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] igt_dummyload: Add preemptible parameter to spinning batch.
== Series Details == Series: series starting with [1/3] igt_dummyload: Add preemptible parameter to spinning batch. URL : https://patchwork.freedesktop.org/series/34860/ State : failure == Summary == IGT patchset build failed on latest successful build c7b20c950276a41badd994324e1983760e44842b igt/perf_pmu: Tighten semaphore-wait measurement CCLD drm_import_export CCLD drm_mm CCLD drm_read CCLD drm_vma_limiter CCLD drm_vma_limiter_cached CCLD drm_vma_limiter_cpu CCLD drm_vma_limiter_gtt CCLD drv_getparams_basic CCLD drv_hangman CCLD drv_missed_irq CCLD drv_module_reload CCLD drv_selftest CCLD drv_suspend CCLD gem_bad_reloc CCLD gem_basic CC gem_busy.o gem_busy.c: In function ‘semaphore’: gem_busy.c:116:9: error: too few arguments to function ‘igt_spin_batch_new’ spin = igt_spin_batch_new(fd, 0, ring, handle[BUSY]); ^~ In file included from ./../lib/igt.h:35:0, from gem_busy.c:28: ./../lib/igt_dummyload.h:45:13: note: declared here igt_spin_t *igt_spin_batch_new(int fd, ^~ gem_busy.c: In function ‘close_race’: gem_busy.c:462:14: error: too few arguments to function ‘igt_spin_batch_new’ spin[i] = igt_spin_batch_new(fd, 0, ^~ In file included from ./../lib/igt.h:35:0, from gem_busy.c:28: ./../lib/igt_dummyload.h:45:13: note: declared here igt_spin_t *igt_spin_batch_new(int fd, ^~ gem_busy.c:470:15: error: too few arguments to function ‘igt_spin_batch_new’ spin[i] = igt_spin_batch_new(fd, 0, ^~ In file included from ./../lib/igt.h:35:0, from gem_busy.c:28: ./../lib/igt_dummyload.h:45:13: note: declared here igt_spin_t *igt_spin_batch_new(int fd, ^~ Makefile:3947: recipe for target 'gem_busy.o' failed make[3]: *** [gem_busy.o] Error 1 Makefile:4348: recipe for target 'all-recursive' failed make[2]: *** [all-recursive] Error 1 Makefile:531: recipe for target 'all-recursive' failed make[1]: *** [all-recursive] Error 1 Makefile:463: recipe for target 'all' failed make: *** [all] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/gvt: Add missing breaks in switch statement
== Series Details == Series: drm/i915/gvt: Add missing breaks in switch statement URL : https://patchwork.freedesktop.org/series/34856/ State : warning == Summary == Test gem_eio: Subgroup in-flight: pass -> DMESG-WARN (shard-snb) Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (shard-hsw) fdo#102707 +1 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: fail -> PASS (shard-snb) fdo#101623 +1 Test kms_cursor_crc: Subgroup cursor-256x256-suspend: pass -> INCOMPLETE (shard-snb) fdo#103375 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-hsw) fdo#104009 Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) fdo#103060 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 shard-hswtotal:2680 pass:1532 dwarn:3 dfail:0 fail:11 skip:1133 time:9197s shard-snbtotal:2631 pass:1277 dwarn:3 dfail:0 fail:12 skip:1338 time:7797s Blacklisted hosts: shard-apltotal:2681 pass:1675 dwarn:2 dfail:0 fail:24 skip:979 time:13638s shard-kbltotal:2681 pass:1796 dwarn:2 dfail:0 fail:24 skip:859 time:10919s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7398/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for igt/pm_rc6_residency: Measure residency after checking for applicability (rev4)
== Series Details == Series: igt/pm_rc6_residency: Measure residency after checking for applicability (rev4) URL : https://patchwork.freedesktop.org/series/32097/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 +1 Test gem_eio: Subgroup in-flight-contexts: pass -> DMESG-WARN (shard-snb) fdo#104058 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104009 Test kms_flip: Subgroup busy-flip-interruptible: pass -> FAIL (shard-hsw) fdo#103257 Subgroup dpms-vs-vblank-race-interruptible: pass -> FAIL (shard-hsw) fdo#103060 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (shard-snb) fdo#102848 pass -> DMESG-WARN (shard-hsw) fdo#102707 +1 Test kms_cursor_legacy: Subgroup flip-vs-cursor-legacy: pass -> FAIL (shard-hsw) fdo#102670 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103257 https://bugs.freedesktop.org/show_bug.cgi?id=103257 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 shard-hswtotal:2679 pass:1532 dwarn:2 dfail:0 fail:13 skip:1132 time:9441s shard-snbtotal:2674 pass:1304 dwarn:3 dfail:0 fail:12 skip:1354 time:7742s Blacklisted hosts: shard-apltotal:2679 pass:1676 dwarn:1 dfail:0 fail:25 skip:977 time:13613s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_592/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Expose more GPU properties through sysfs (rev6)
== Series Details == Series: drm/i915: Expose more GPU properties through sysfs (rev6) URL : https://patchwork.freedesktop.org/series/33950/ State : failure == Summary == Test gem_eio: Subgroup in-flight-contexts: pass -> DMESG-WARN (shard-snb) fdo#104058 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: pass -> FAIL (shard-snb) Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 Test drv_module_reload: Subgroup basic-reload-inject: pass -> DMESG-WARN (shard-snb) fdo#102707 +2 fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 shard-hswtotal:2681 pass:1535 dwarn:2 dfail:0 fail:10 skip:1134 time:9503s shard-snbtotal:2681 pass:1305 dwarn:3 dfail:0 fail:14 skip:1359 time:8159s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7397/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/cnl: only divide up base frequency with crystal source
Em Seg, 2017-12-04 às 15:50 -0200, Paulo Zanoni escreveu: > Em Seg, 2017-11-13 às 23:34 +, Lionel Landwerlin escreveu: > > We apply this logic to Gen9 as well. We didn't notice this issue as > > most part we've encountered so far only use the crystal as source > > for > > their timestamp registers. > > > > Fixes: dab9178333 ("drm/i915: expose command stream timestamp > > frequency to userspace") > > Signed-off-by: Lionel Landwerlin > > Reviewed-by: Paulo Zanoni I also merged this since I need it. Patch 3 still needs a check from the people who were reviewing its previous versions. > > > --- > > drivers/gpu/drm/i915/intel_device_info.c | 16 > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > > b/drivers/gpu/drm/i915/intel_device_info.c > > index f3e4940fed49..039f8ec7ad27 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -413,15 +413,15 @@ static u32 read_timestamp_frequency(struct > > drm_i915_private *dev_priv) > > freq = f24_mhz; > > break; > > } > > - } > > > > - /* Now figure out how the command stream's > > timestamp > > register > > - * increments from this frequency (it might > > increment only > > - * every few clock cycle). > > - */ > > - freq >>= 3 - ((rpm_config_reg & > > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMET > > ER > > _MASK) >> > > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETE > > R_ > > SHIFT); > > + /* Now figure out how the command stream's > > timestamp > > + * register increments from this frequency > > (it might > > + * increment only every few clock cycle). > > + */ > > + freq >>= 3 - ((rpm_config_reg & > > + GEN10_RPM_CONFIG0_CTC_SHIFT > > _P > > ARAMETER_MASK) >> > > + GEN10_RPM_CONFIG0_CTC_SHIFT_ > > PA > > RAMETER_SHIFT); > > + } > > > > return freq; > > } > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 2/3] tests/gem_exec_schedule: Add reset on failed preemption test.
On 04/12/17 09:37, Chris Wilson wrote: Quoting Antonio Argenziano (2017-12-04 17:23:14) This patch adds a test where a low priority batch is going to be declared hung while a preemption is pending. The test wants to verify that a 'bad' low priority batch will not disrupt the execution of a high priority context and that the driver does due diligence in managing a reset while a preemption is pending. Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index 1e6b0ae7..ae44a6c0 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -356,7 +356,8 @@ static void promotion(int fd, unsigned ring) munmap(ptr, 4096); } -#define NEW_CTX 0x1 +#define NEW_CTX (0x1 << 0) +#define HANG_LP (0x1 << 1) static void preempt(int fd, unsigned ring, unsigned flags) { uint32_t result = gem_create(fd, 4096); @@ -370,6 +371,9 @@ static void preempt(int fd, unsigned ring, unsigned flags) ctx[HI] = gem_context_create(fd); gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + if (flags & HANG_LP) + igt_spin_batch_new(fd, ctx[LO], ring, 0, false); Both of the hanging batch usecases fit into igt_hang_t batch, which doesn't allow preempting atm. (Though I'd be quite happy to see patches towards unifying the two interfaces, probably with an opts struct rather than continuing to add new params ad nauseam.) Before injecting a hang, you must check with igt_allow_hang etc that hangs/resets are allowed by igt, and to clean up afterwards. I'll re-spin using igt_hang and send an RFC to put the two things together afterwards. Is that OK with you? -Antonio -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_exec_schedule: Add test for resetting preemptive batch
On 04/12/17 09:42, Chris Wilson wrote: Quoting Antonio Argenziano (2017-12-04 17:23:15) This patch adds a test that will trigger a preemption of a low priority batch by a 'bad' batch buffer which will hang. The test aims at making sure that a hanging high priority batch will not disrupt the submission flow of low priority contexts. Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 39 +++ 1 file changed, 39 insertions(+) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index ae44a6c0..5a4d63f9 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -511,6 +511,39 @@ static void preempt_self(int fd, unsigned ring) gem_close(fd, result); } +static void bad_preemptive(int fd, unsigned ring) +{ + igt_spin_t *spin[16]; + igt_spin_t *bad; + uint32_t ctx[2]; + + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + ctx[HI] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + + for (int n = 0; n < 16; n++) { + gem_context_destroy(fd, ctx[LO]); + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0, true); + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); + } + + bad = igt_spin_batch_new(fd, ctx[HI], ring, 0, false); + gem_wait(fd, bad->handle, NULL); + + for (int n = 0; n < 16; n++) { + igt_assert(gem_bo_busy(fd, spin[n]->handle)); + igt_spin_batch_free(fd, spin[n]); + } Is this really policy you want to enforce? I certainly don't intend to mandate that the kernel isn't allowed to use RT throttling. Yeah, I wasn't sure about that. Is a gem_wait on each of them enough or should I put a write at the end of each low priority batch to make sure they actually executed? + + gem_context_destroy(fd, ctx[LO]); + gem_context_destroy(fd, ctx[HI]); +} + static void deep(int fd, unsigned ring) { #define XS 8 @@ -1033,6 +1066,12 @@ igt_main preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); igt_fork_hang_detector(fd); } + + igt_subtest_f("bad-preemptive-%s", e->name) { + igt_stop_hang_detector(); + bad_preemptive(fd, e->exec_id | e->flags); + igt_fork_hang_detector(fd); + } Split into non-hang/hang portions and use igt_subtest_group + igt_fixture. OK, will do. -Antonio -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: fix off-by-one comparison of ring_id
== Series Details == Series: drm/i915/gvt: fix off-by-one comparison of ring_id URL : https://patchwork.freedesktop.org/series/34858/ State : success == Summary == Series 34858v1 drm/i915/gvt: fix off-by-one comparison of ring_id https://patchwork.freedesktop.org/api/1.0/series/34858/revisions/1/mbox/ fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:438s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:442s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:381s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:527s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:503s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:514s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:489s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:478s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:269s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:369s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:261s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:397s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:475s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:449s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:492s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:529s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:533s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:595s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:448s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:542s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:567s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:514s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:502s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:450s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:551s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:420s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:613s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:489s 8d5a56edbf6830c8f170bae7ebfef2aac2afdc5c drm-tip: 2017y-12m-04d-17h-26m-10s UTC integration manifest 4aa4f75d0901 drm/i915/gvt: fix off-by-one comparison of ring_id == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7399/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Mark expected switch fall-throughs
On Mon, Dec 4, 2017 at 4:20 PM, Gustavo A. R. Silva wrote: > Hi Joonas, > > Quoting Joonas Lahtinen : > >> On Mon, 2017-11-27 at 16:17 -0600, Gustavo A. R. Silva wrote: >>> >>> In preparation to enabling -Wimplicit-fallthrough, mark switch cases >>> where we are expecting to fall through. >> >> >> I have to say I'm totally not sold on regexps matching comment >> contents. Was something more explicit ever considered? Like: >> >> #define FALLTHROUGH __attribute__((fallthrough)); >> >> With the appropriate version checks, of course. >> > > One of the arguments is that comments lets us leverage the existing static > analyzers. > > We've been discussing this during the last week, feel free to join the > discussion: > > http://www.spinics.net/lists/kernel/msg2659908.html > http://www.spinics.net/lists/kernel/msg2659906.html If we go with existing rules, then either pls patch coding style, or be a bit more liberal in what you accept. E.g. fallthrough vs fall through seems a bit a bikeshed (and will be an endless source of work for you). I'd also claim that "this shouldn't happen, dump a backtrace and hope for the best" style macros like i915's MISSING_CASE or WARN_ON (as the only thing) should count as an auto-fallthrough annotation. From a quick look, that would cover everything in your patch. -Daniel > > Thanks! > -- > Gustavo A. R. Silva > > > > > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/cnl: only divide up base frequency with crystal source
Em Seg, 2017-11-13 às 23:34 +, Lionel Landwerlin escreveu: > We apply this logic to Gen9 as well. We didn't notice this issue as > most part we've encountered so far only use the crystal as source for > their timestamp registers. > > Fixes: dab9178333 ("drm/i915: expose command stream timestamp > frequency to userspace") > Signed-off-by: Lionel Landwerlin Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_device_info.c | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index f3e4940fed49..039f8ec7ad27 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -413,15 +413,15 @@ static u32 read_timestamp_frequency(struct > drm_i915_private *dev_priv) > freq = f24_mhz; > break; > } > - } > > - /* Now figure out how the command stream's timestamp > register > - * increments from this frequency (it might > increment only > - * every few clock cycle). > - */ > - freq >>= 3 - ((rpm_config_reg & > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER > _MASK) >> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_ > SHIFT); > + /* Now figure out how the command stream's > timestamp > + * register increments from this frequency > (it might > + * increment only every few clock cycle). > + */ > + freq >>= 3 - ((rpm_config_reg & > + GEN10_RPM_CONFIG0_CTC_SHIFT_P > ARAMETER_MASK) >> > + GEN10_RPM_CONFIG0_CTC_SHIFT_PA > RAMETER_SHIFT); > + } > > return freq; > } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt 01/10] igt/perf_pmu: Tighten semaphore-wait measurement
On 04/12/2017 09:27, Chris Wilson wrote: Record the before/after semaphore-wait values around the sleep to try to reduce the inaccuracy from scheduler delays. Previously, the samples were taken before submitting the batch and then after synchronising its completion. The measurement will then be the total that the semaphore was being sampled, but with the extra syscalls intervening may have drifted from the sleep duration. To further reduce the disparity, wait for the batch to start executing before taking our samples. References: https://bugs.freedesktop.org/show_bug.cgi?id=104013 Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- tests/perf_pmu.c | 54 -- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c index cb59bf5d..e872f4e5 100644 --- a/tests/perf_pmu.c +++ b/tests/perf_pmu.c @@ -355,13 +355,13 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, bool busy) static void sema_wait(int gem_fd, const struct intel_execution_engine2 *e) { - struct drm_i915_gem_relocation_entry reloc = { }; - struct drm_i915_gem_execbuffer2 eb = { }; - struct drm_i915_gem_exec_object2 obj[2]; + struct drm_i915_gem_relocation_entry reloc[2] = {}; + struct drm_i915_gem_exec_object2 obj[2] = {}; + struct drm_i915_gem_execbuffer2 eb = {}; uint32_t bb_handle, obj_handle; unsigned long slept; uint32_t *obj_ptr; - uint32_t batch[6]; + uint32_t batch[16]; uint64_t val[2]; int fd; @@ -378,28 +378,35 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e) obj_ptr = gem_mmap__wc(gem_fd, obj_handle, 0, 4096, PROT_WRITE); - batch[0] = MI_SEMAPHORE_WAIT | + batch[0] = MI_STORE_DWORD_IMM; + batch[1] = sizeof(*obj_ptr); + batch[2] = 0; + batch[3] = 1; + batch[4] = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_GTE_SDD; - batch[1] = 1; - batch[2] = 0x0; - batch[3] = 0x0; - batch[4] = MI_NOOP; - batch[5] = MI_BATCH_BUFFER_END; + batch[5] = 1; + batch[6] = 0x0; + batch[7] = 0x0; + batch[8] = MI_BATCH_BUFFER_END; gem_write(gem_fd, bb_handle, 0, batch, sizeof(batch)); - reloc.target_handle = obj_handle; - reloc.offset = 2 * sizeof(uint32_t); - reloc.read_domains = I915_GEM_DOMAIN_RENDER; + reloc[0].target_handle = obj_handle; + reloc[0].offset = 1 * sizeof(uint32_t); + reloc[0].read_domains = I915_GEM_DOMAIN_RENDER; + reloc[0].write_domain = I915_GEM_DOMAIN_RENDER; + reloc[0].delta = sizeof(*obj_ptr); - memset(obj, 0, sizeof(obj)); + reloc[1].target_handle = obj_handle; + reloc[1].offset = 6 * sizeof(uint32_t); + reloc[1].read_domains = I915_GEM_DOMAIN_RENDER; obj[0].handle = obj_handle; obj[1].handle = bb_handle; - obj[1].relocation_count = 1; - obj[1].relocs_ptr = to_user_pointer(&reloc); + obj[1].relocation_count = 2; + obj[1].relocs_ptr = to_user_pointer(reloc); eb.buffer_count = 2; eb.buffers_ptr = to_user_pointer(obj); @@ -413,18 +420,21 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e) fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance)); - val[0] = pmu_read_single(fd); - gem_execbuf(gem_fd, &eb); + do { /* wait for the batch to start executing */ + usleep(5e3); + } while (!obj_ptr[1]); + usleep(5e3); /* wait for the register sampling */ + val[0] = pmu_read_single(fd); slept = measured_usleep(batch_duration_ns / 1000); + val[1] = pmu_read_single(fd); + igt_debug("slept %.3fms, sampled %.3fms\n", + slept*1e-6, (val[1] - val[0])*1e-6); - *obj_ptr = 1; - + obj_ptr[0] = 1; gem_sync(gem_fd, bb_handle); - val[1] = pmu_read_single(fd); - munmap(obj_ptr, 4096); gem_close(gem_fd, obj_handle); gem_close(gem_fd, bb_handle); My first try would be to just sample around usleep, but not complaints on the more involved solution either. Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_exec_schedule: Add test for resetting preemptive batch
Quoting Antonio Argenziano (2017-12-04 17:23:15) > This patch adds a test that will trigger a preemption of a low priority > batch by a 'bad' batch buffer which will hang. The test aims at making > sure that a hanging high priority batch will not disrupt the submission > flow of low priority contexts. > > Cc: Chris Wilson > Cc: Michal Winiarski > Signed-off-by: Antonio Argenziano > --- > tests/gem_exec_schedule.c | 39 +++ > 1 file changed, 39 insertions(+) > > diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c > index ae44a6c0..5a4d63f9 100644 > --- a/tests/gem_exec_schedule.c > +++ b/tests/gem_exec_schedule.c > @@ -511,6 +511,39 @@ static void preempt_self(int fd, unsigned ring) > gem_close(fd, result); > } > > +static void bad_preemptive(int fd, unsigned ring) > +{ > + igt_spin_t *spin[16]; > + igt_spin_t *bad; > + uint32_t ctx[2]; > + > + ctx[LO] = gem_context_create(fd); > + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); > + > + ctx[HI] = gem_context_create(fd); > + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); > + > + for (int n = 0; n < 16; n++) { > + gem_context_destroy(fd, ctx[LO]); > + ctx[LO] = gem_context_create(fd); > + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); > + > + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0, true); > + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); > + } > + > + bad = igt_spin_batch_new(fd, ctx[HI], ring, 0, false); > + gem_wait(fd, bad->handle, NULL); > + > + for (int n = 0; n < 16; n++) { > + igt_assert(gem_bo_busy(fd, spin[n]->handle)); > + igt_spin_batch_free(fd, spin[n]); > + } Is this really policy you want to enforce? I certainly don't intend to mandate that the kernel isn't allowed to use RT throttling. > + > + gem_context_destroy(fd, ctx[LO]); > + gem_context_destroy(fd, ctx[HI]); > +} > + > static void deep(int fd, unsigned ring) > { > #define XS 8 > @@ -1033,6 +1066,12 @@ igt_main > preempt(fd, e->exec_id | > e->flags, NEW_CTX | HANG_LP); > igt_fork_hang_detector(fd); > } > + > + igt_subtest_f("bad-preemptive-%s", > e->name) { > + igt_stop_hang_detector(); > + bad_preemptive(fd, e->exec_id > | e->flags); > + igt_fork_hang_detector(fd); > + } Split into non-hang/hang portions and use igt_subtest_group + igt_fixture. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 2/3] tests/gem_exec_schedule: Add reset on failed preemption test.
Quoting Antonio Argenziano (2017-12-04 17:23:14) > This patch adds a test where a low priority batch is going to be > declared hung while a preemption is pending. The test wants to verify > that a 'bad' low priority batch will not disrupt the execution of a high > priority context and that the driver does due diligence in managing a > reset while a preemption is pending. > > Cc: Chris Wilson > Cc: Michal Winiarski > Signed-off-by: Antonio Argenziano > --- > tests/gem_exec_schedule.c | 12 +++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c > index 1e6b0ae7..ae44a6c0 100644 > --- a/tests/gem_exec_schedule.c > +++ b/tests/gem_exec_schedule.c > @@ -356,7 +356,8 @@ static void promotion(int fd, unsigned ring) > munmap(ptr, 4096); > } > > -#define NEW_CTX 0x1 > +#define NEW_CTX (0x1 << 0) > +#define HANG_LP (0x1 << 1) > static void preempt(int fd, unsigned ring, unsigned flags) > { > uint32_t result = gem_create(fd, 4096); > @@ -370,6 +371,9 @@ static void preempt(int fd, unsigned ring, unsigned flags) > ctx[HI] = gem_context_create(fd); > gem_context_set_priority(fd, ctx[HI], MAX_PRIO); > > + if (flags & HANG_LP) > + igt_spin_batch_new(fd, ctx[LO], ring, 0, false); Both of the hanging batch usecases fit into igt_hang_t batch, which doesn't allow preempting atm. (Though I'd be quite happy to see patches towards unifying the two interfaces, probably with an opts struct rather than continuing to add new params ad nauseam.) Before injecting a hang, you must check with igt_allow_hang etc that hangs/resets are allowed by igt, and to clean up afterwards. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/3] tests/gem_exec_schedule: Add reset on failed preemption test.
This patch adds a test where a low priority batch is going to be declared hung while a preemption is pending. The test wants to verify that a 'bad' low priority batch will not disrupt the execution of a high priority context and that the driver does due diligence in managing a reset while a preemption is pending. Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index 1e6b0ae7..ae44a6c0 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -356,7 +356,8 @@ static void promotion(int fd, unsigned ring) munmap(ptr, 4096); } -#define NEW_CTX 0x1 +#define NEW_CTX (0x1 << 0) +#define HANG_LP (0x1 << 1) static void preempt(int fd, unsigned ring, unsigned flags) { uint32_t result = gem_create(fd, 4096); @@ -370,6 +371,9 @@ static void preempt(int fd, unsigned ring, unsigned flags) ctx[HI] = gem_context_create(fd); gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + if (flags & HANG_LP) + igt_spin_batch_new(fd, ctx[LO], ring, 0, false); + for (int n = 0; n < 16; n++) { if (flags & NEW_CTX) { gem_context_destroy(fd, ctx[LO]); @@ -1023,6 +1027,12 @@ igt_main igt_subtest_f("preempt-self-%s", e->name) preempt_self(fd, e->exec_id | e->flags); + + igt_subtest_f("preempt-bad-%s", e->name) { + igt_stop_hang_detector(); + preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); + igt_fork_hang_detector(fd); + } } igt_subtest_f("deep-%s", e->name) -- 2.14.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 3/3] tests/gem_exec_schedule: Add test for resetting preemptive batch
This patch adds a test that will trigger a preemption of a low priority batch by a 'bad' batch buffer which will hang. The test aims at making sure that a hanging high priority batch will not disrupt the submission flow of low priority contexts. Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- tests/gem_exec_schedule.c | 39 +++ 1 file changed, 39 insertions(+) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index ae44a6c0..5a4d63f9 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -511,6 +511,39 @@ static void preempt_self(int fd, unsigned ring) gem_close(fd, result); } +static void bad_preemptive(int fd, unsigned ring) +{ + igt_spin_t *spin[16]; + igt_spin_t *bad; + uint32_t ctx[2]; + + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + ctx[HI] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + + for (int n = 0; n < 16; n++) { + gem_context_destroy(fd, ctx[LO]); + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0, true); + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); + } + + bad = igt_spin_batch_new(fd, ctx[HI], ring, 0, false); + gem_wait(fd, bad->handle, NULL); + + for (int n = 0; n < 16; n++) { + igt_assert(gem_bo_busy(fd, spin[n]->handle)); + igt_spin_batch_free(fd, spin[n]); + } + + gem_context_destroy(fd, ctx[LO]); + gem_context_destroy(fd, ctx[HI]); +} + static void deep(int fd, unsigned ring) { #define XS 8 @@ -1033,6 +1066,12 @@ igt_main preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); igt_fork_hang_detector(fd); } + + igt_subtest_f("bad-preemptive-%s", e->name) { + igt_stop_hang_detector(); + bad_preemptive(fd, e->exec_id | e->flags); + igt_fork_hang_detector(fd); + } } igt_subtest_f("deep-%s", e->name) -- 2.14.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/3] igt_dummyload: Add preemptible parameter to spinning batch.
The recursive batch emitted in the dummyload library is always pre-emptible. This patch adds a parameter to make it conditionally pre-emptible. The batch can now be used in tests where we still want a spinning batch while not being able to preempt it. Note: The behavior preceding this patch has been kept. All the places that used a spin batch are still using a pre-emptible spin batch. Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano --- lib/igt_dummyload.c | 18 +++--- lib/igt_dummyload.h | 6 -- tests/drv_missed_irq.c| 2 +- tests/gem_busy.c | 4 ++-- tests/gem_exec_fence.c| 14 +++--- tests/gem_exec_latency.c | 2 +- tests/gem_exec_nop.c | 2 +- tests/gem_exec_reloc.c| 8 +--- tests/gem_exec_schedule.c | 8 tests/gem_exec_suspend.c | 2 +- tests/gem_shrink.c| 4 ++-- tests/gem_spin_batch.c| 4 ++-- tests/gem_sync.c | 3 ++- tests/gem_wait.c | 2 +- tests/kms_busy.c | 6 +++--- tests/kms_cursor_legacy.c | 5 +++-- tests/kms_flip.c | 4 ++-- tests/perf_pmu.c | 20 ++-- tests/pm_rps.c| 2 +- 19 files changed, 63 insertions(+), 53 deletions(-) diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index bb2be557..8dd78495 100644 --- a/lib/igt_dummyload.c +++ b/lib/igt_dummyload.c @@ -71,7 +71,7 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc, static void emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t ctx, unsigned engine, -uint32_t dep) +uint32_t dep, bool preemptible) { #define SCRATCH 0 #define BATCH 1 @@ -122,8 +122,8 @@ static void emit_recursive_batch(igt_spin_t *spin, spin->batch = batch; spin->handle = obj[BATCH].handle; - /* Allow ourselves to be preempted */ - *batch++ = MI_ARB_CHK; + if (preemptible) + *batch++ = MI_ARB_CHK; /* Allow ourselves to be preempted */ /* Pad with a few nops so that we do not completely hog the system. * @@ -172,14 +172,15 @@ static void emit_recursive_batch(igt_spin_t *spin, } igt_spin_t * -__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep) +__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, + uint32_t dep, bool preemptible) { igt_spin_t *spin; spin = calloc(1, sizeof(struct igt_spin)); igt_assert(spin); - emit_recursive_batch(spin, fd, ctx, engine, dep); + emit_recursive_batch(spin, fd, ctx, engine, dep, preemptible); igt_assert(gem_bo_busy(fd, spin->handle)); igt_list_add(&spin->link, &spin_list); @@ -194,6 +195,8 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep) * than 0, execute on all available rings. * @dep: handle to a buffer object dependency. If greater than 0, add a * relocation entry to this buffer within the batch. + * @preemptible: Whether spinning batch would execute a preemtible instruction + * or not. * * Start a recursive batch on a ring. Immediately returns a #igt_spin_t that * contains the batch's handle that can be waited upon. The returned structure @@ -203,11 +206,12 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep) * Structure with helper internal state for igt_spin_batch_free(). */ igt_spin_t * -igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep) +igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, + uint32_t dep, bool preemptible) { igt_require_gem(fd); - return __igt_spin_batch_new(fd, ctx, engine, dep); + return __igt_spin_batch_new(fd, ctx, engine, dep, preemptible); } static void notify(union sigval arg) diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h index 215425f7..8660f1b1 100644 --- a/lib/igt_dummyload.h +++ b/lib/igt_dummyload.h @@ -40,11 +40,13 @@ typedef struct igt_spin { igt_spin_t *__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, -uint32_t dep); +uint32_t dep, +bool preemptible); igt_spin_t *igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, - uint32_t dep); + uint32_t dep, + bool preemptible); void igt_spin_batch_set_timeout(igt_spin_t *spin, int64_t ns); void igt_spin_batch_end(igt_spin_t *spin); void igt_spin_batch_free(int fd, igt_spin_t *spin); diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c index 9326a5a6..56220471 100644 --- a/tests/drv_missed_irq.c +++ b/tests/drv_misse
[Intel-gfx] [PATCH][next] drm/i915/gvt: fix off-by-one comparison of ring_id
From: Colin Ian King The ring_id maximum boundary is being compared using the > operator instead of >=, leading to an off-by-one error and an out of bounds write into array vgpu->hws_pga[]. Fix this by simply using the correct comparison operator. Also re-work another comparison that uses the comparison > I915_NUM_ENGINES - 1 to use the >= idiom using to keep this consistent in this code. Detected by CoverityScan, CID#1462404 ("Out-of-bounds write") Fixes: a2ae95af9646 ("drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP") Signed-off-by: Colin Ian King --- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 7354ed816f92..c982867e7c2b 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1398,7 +1398,7 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, * update the VM CSB status correctly. Here listed registers can * support BDW, SKL or other platforms with same HWSP registers. */ - if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) { + if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n", vgpu->id, offset); return -EINVAL; @@ -1473,7 +1473,7 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, u32 data = *(u32 *)p_data; int ret = 0; - if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) + if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) return -EINVAL; execlist = &vgpu->submission.execlist[ring_id]; -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Add missing breaks in switch statement
== Series Details == Series: drm/i915/gvt: Add missing breaks in switch statement URL : https://patchwork.freedesktop.org/series/34856/ State : success == Summary == Series 34856v1 drm/i915/gvt: Add missing breaks in switch statement https://patchwork.freedesktop.org/api/1.0/series/34856/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> DMESG-WARN (fi-elk-e7500) fdo#103989 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:439s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:450s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:379s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:524s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:501s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:487s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:470s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:271s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:536s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:359s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:260s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:390s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:490s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:475s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:540s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:587s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:541s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:520s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:498s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:446s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:553s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:417s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:614s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:628s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:488s a98806aa3e6aad9caff4cf326a6685c90cf8db6b drm-tip: 2017y-12m-04d-14h-34m-55s UTC integration manifest 7619cfa57d3c drm/i915/gvt: Add missing breaks in switch statement == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7398/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH][next] drm/i915/gvt: Add missing breaks in switch statement
From: Colin Ian King The switch statement is missing breaks for the cases of GVT_FAILSAFE_INSUFFICIENT_RESOURCE and GVT_FAILSAFE_GUEST_ERR. Add them in. Detected by CoverityScan, CID#1462416 ("Missing break in switch") Fixes: e011c6ce2b4f ("drm/i915/gvt: Add VM healthy check for workload_thread") Fixes: a33fc7a0482a ("drm/i915/gvt: enter failsafe mode when guest requires more resources") Signed-off-by: Colin Ian King --- drivers/gpu/drm/i915/gvt/handlers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 94fc04210bac..7354ed816f92 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -174,8 +174,10 @@ void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) break; case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: pr_err("Graphics resource is not enough for the guest\n"); + break; case GVT_FAILSAFE_GUEST_ERR: pr_err("GVT Internal error for the guest\n"); + break; default: break; } -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for igt/pm_rc6_residency: Measure residency after checking for applicability (rev4)
== Series Details == Series: igt/pm_rc6_residency: Measure residency after checking for applicability (rev4) URL : https://patchwork.freedesktop.org/series/32097/ State : success == Summary == IGT patchset tested on top of latest successful build 36015334f9ee86b997fc5c0deb4964184f87648f igt: Make dependency on libunwind mandatory with latest DRM-Tip kernel build CI_DRM_3449 a98806aa3e6a drm-tip: 2017y-12m-04d-14h-34m-55s UTC integration manifest Testlist changes: -igt@pm_rc6_residency@rc6pp-accuracy -igt@pm_rc6_residency@rc6p-accuracy Test debugfs_test: Subgroup read_all_entries: pass -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:446s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:384s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:526s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:512s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:488s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:471s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:272s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:360s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:396s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:487s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:487s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:538s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:591s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:459s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:548s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:569s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:520s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:450s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:548s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:419s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:613s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:630s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:490s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_592/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose more GPU properties through sysfs (rev6)
== Series Details == Series: drm/i915: Expose more GPU properties through sysfs (rev6) URL : https://patchwork.freedesktop.org/series/33950/ State : success == Summary == Series 33950v6 drm/i915: Expose more GPU properties through sysfs https://patchwork.freedesktop.org/api/1.0/series/33950/revisions/6/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:437s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:442s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:518s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:501s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:486s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:471s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:544s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:384s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:395s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:492s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:454s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:488s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:529s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:537s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:593s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:449s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:537s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:515s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:546s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:421s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:605s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:622s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:493s fi-bwr-2160 failed to collect. IGT log at Patchwork_7397/fi-bwr-2160/igt.log a98806aa3e6aad9caff4cf326a6685c90cf8db6b drm-tip: 2017y-12m-04d-14h-34m-55s UTC integration manifest 7ff376ded57d drm/i915: expose EU topology through sysfs a6dcc340c365 drm/i915: expose engine availability through sysfs 891c569f0503 drm/i915/debugfs: reuse max slice/subslices already stored in sseu 3f2a55c6484d drm/i915: store all subslice masks 25b08e5552d0 drm: add card symlink in render sysfs directory == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7397/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Mark expected switch fall-throughs
Hi Joonas, Quoting Joonas Lahtinen : On Mon, 2017-11-27 at 16:17 -0600, Gustavo A. R. Silva wrote: In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. I have to say I'm totally not sold on regexps matching comment contents. Was something more explicit ever considered? Like: #define FALLTHROUGH __attribute__((fallthrough)); With the appropriate version checks, of course. One of the arguments is that comments lets us leverage the existing static analyzers. We've been discussing this during the last week, feel free to join the discussion: http://www.spinics.net/lists/kernel/msg2659908.html http://www.spinics.net/lists/kernel/msg2659906.html Thanks! -- Gustavo A. R. Silva ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for test/kms_plane_lowres: Fix display_commit_mode() so it returns the crc
== Series Details == Series: test/kms_plane_lowres: Fix display_commit_mode() so it returns the crc URL : https://patchwork.freedesktop.org/series/34749/ State : failure == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test kms_cursor_crc: Subgroup cursor-256x256-suspend: pass -> SKIP (shard-hsw) fdo#103375 Test kms_plane_lowres: Subgroup pipe-c-tiling-none: pass -> FAIL (shard-hsw) fdo#103181 +2 Subgroup pipe-a-tiling-none: pass -> FAIL (shard-snb) pass -> FAIL (shard-hsw) fdo#102614 Subgroup pipe-c-tiling-x: pass -> FAIL (shard-hsw) Subgroup pipe-b-tiling-x: pass -> FAIL (shard-snb) pass -> FAIL (shard-hsw) Subgroup pipe-b-tiling-none: pass -> FAIL (shard-snb) Subgroup pipe-a-tiling-x: pass -> FAIL (shard-snb) Test kms_flip: Subgroup plain-flip-ts-check-interruptible: pass -> FAIL (shard-hsw) fdo#100368 Test gem_tiled_swapping: Subgroup non-threaded: incomplete -> PASS (shard-snb) fdo#104009 Test drv_module_reload: Subgroup basic-reload-inject: pass -> DMESG-WARN (shard-hsw) fdo#103706 Subgroup basic-no-display: dmesg-warn -> PASS (shard-hsw) fdo#102707 Test kms_frontbuffer_tracking: Subgroup fbc-rgb101010-draw-render: pass -> SKIP (shard-snb) fdo#103167 Test drv_selftest: Subgroup live_hangcheck: incomplete -> PASS (shard-snb) fdo#103880 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103181 https://bugs.freedesktop.org/show_bug.cgi?id=103181 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103706 https://bugs.freedesktop.org/show_bug.cgi?id=103706 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880 shard-hswtotal:2663 pass:1528 dwarn:2 dfail:0 fail:16 skip:1117 time:9424s shard-snbtotal:2663 pass:1304 dwarn:1 dfail:0 fail:16 skip:1342 time:8178s Blacklisted hosts: shard-kbltotal:2603 pass:1748 dwarn:1 dfail:0 fail:35 skip:818 time:10659s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_591/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Flush pending GTT writes before unbinding (rev2)
== Series Details == Series: drm/i915: Flush pending GTT writes before unbinding (rev2) URL : https://patchwork.freedesktop.org/series/34830/ State : failure == Summary == Test testdisplay: pass -> INCOMPLETE (shard-hsw) Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (shard-snb) fdo#102707 Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test gem_busy: Subgroup close-race: pass -> FAIL (shard-snb) fdo#103829 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-hsw) fdo#104009 Test drv_selftest: Subgroup live_hangcheck: incomplete -> PASS (shard-snb) fdo#103880 Test kms_busy: Subgroup extended-modeset-hang-oldfb-with-reset-render-a: pass -> SKIP (shard-hsw) fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880 shard-hswtotal:2629 pass:1511 dwarn:2 dfail:0 fail:9 skip:1105 time:8770s shard-snbtotal:2657 pass:1301 dwarn:2 dfail:0 fail:13 skip:1340 time:7813s Blacklisted hosts: shard-apltotal:2663 pass:1685 dwarn:4 dfail:0 fail:24 skip:950 time:13863s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7396/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 5/5] drm/i915: expose EU topology through sysfs
With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts of the GPU with the OA unit, because signals need to be accounted properly based on whether part of the GPU has been fused off. The current aggregated numbers like EU_TOTAL do not gives us sufficient information. Here is the sysfs layout on a Skylake GT4 : /sys/devices/pci:00/:00:02.0/drm/card0/gt/engines/rcs/topology/ ├── max_eus_per_subslice ├── max_slices ├── max_subslices_per_slice ├── slice0 │ ├── subslice0 │ │ └── eus_enabled_mask │ ├── subslice1 │ │ └── eus_enabled_mask │ ├── subslice2 │ │ └── eus_enabled_mask │ ├── subslice3 │ │ └── eus_enabled_mask │ └── subslices_enabled_mask ├── slice1 │ ├── subslice0 │ │ └── eus_enabled_mask │ ├── subslice1 │ │ └── eus_enabled_mask │ ├── subslice2 │ │ └── eus_enabled_mask │ ├── subslice3 │ │ └── eus_enabled_mask │ └── subslices_enabled_mask ├── slice2 │ ├── subslice0 │ │ └── eus_enabled_mask │ ├── subslice1 │ │ └── eus_enabled_mask │ ├── subslice2 │ │ └── eus_enabled_mask │ ├── subslice3 │ │ └── eus_enabled_mask │ └── subslices_enabled_mask └── slices_enabled_mask Each enabled_mask file gives us a mask of the enabled units : $ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/engines/rcs/topology/slices_enabled_mask 0x7 $ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/engines/rcs/topology/slice2/subslice1/eus_enabled_mask 0xff max_eus_per_subslice/max_slices/max_subslices_per_slice are useful numbers for userspace to build up a n-dimensional representation of the device so that it can allocated upfront and filled up while reading through each of the slices/subslices. v2: Move topology below rcs engine (Chris) Add max_eus_per_subslice/max_slices/max_subslices_per_slice (Lionel) v3: Rename enabled_mask (Lionel) v4: Move slices to drm/card/gt/rcs/topology (Tvrtko) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 27 + drivers/gpu/drm/i915/i915_sysfs.c | 208 ++ 2 files changed, 235 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 893ecb0d4639..fbdfd59ed1bd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2260,6 +2260,24 @@ struct intel_cdclk_state { u8 voltage_level; }; +struct intel_topology_kobject { + struct kobject kobj; + struct drm_i915_private *dev_priv; +}; + +struct intel_slice_kobject { + struct kobject kobj; + struct drm_i915_private *dev_priv; + u8 slice_index; +}; + +struct intel_subslice_kobject { + struct kobject kobj; + struct drm_i915_private *dev_priv; + u8 slice_index; + u8 subslice_index; +}; + struct drm_i915_private { struct drm_device drm; @@ -2735,6 +2753,15 @@ struct drm_i915_private { struct kobject gt_kobj; struct kobject engines_kobj; struct kobject engines_classes_kobjs[MAX_ENGINE_CLASS + 1]; + struct kobject topology_kobj; + + struct sysfs_slice { + struct intel_slice_kobject kobj; + + struct sysfs_subslice { + struct intel_subslice_kobject kobj; + } subslices[GEN_MAX_SUBSLICES]; + } slices[GEN_MAX_SLICES]; } gt_topology; /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index d8ec8ec51cca..b277338ab3fb 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -570,6 +570,205 @@ static void i915_setup_error_capture(struct device *kdev) {} static void i915_teardown_error_capture(struct device *kdev) {} #endif +static struct attribute slices_enabled_mask_attr = { + .name = "slices_enabled_mask", + .mode = 0444, +}; + +static struct attribute subslices_enabled_mask_attr = { + .name = "subslices_enabled_mask", + .mode = 0444, +}; + +static struct attribute eus_enabled_mask_attr = { + .name = "eus_enabled_mask", + .mode = 0444, +}; + +static struct attribute max_slices_attr = { + .name = "max_slices", + .mode = 0444, +}; + +static struct attribute max_subslices_per_slice_attr = { + .name = "max_subslices_per_slice", + .mode = 0444, +}; + +static struct attribute max_eus_per_subslice_attr = { + .name = "max_eus_per_subslice", + .mode = 0444, +}; + +static ssize_t +show_topology_attr(struct kobject *kobj, struct attribute *attr, char *buf) +{ + struct drm_i915_private *dev_priv = + container_of(kobj, struct drm_i91
[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9 (rev4)
== Series Details == Series: igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9 (rev4) URL : https://patchwork.freedesktop.org/series/33132/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: pass -> FAIL (shard-snb) fdo#101623 +1 Test gem_tiled_swapping: Subgroup non-threaded: incomplete -> PASS (shard-snb) fdo#104009 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (shard-hsw) fdo#102707 Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2664 pass:1537 dwarn:1 dfail:0 fail:9 skip:1117 time:9632s shard-snbtotal:2621 pass:1267 dwarn:0 dfail:0 fail:12 skip:1342 time:8065s Blacklisted hosts: shard-apltotal:2613 pass:1648 dwarn:1 dfail:0 fail:22 skip:940 time:12858s shard-kbltotal:2655 pass:1794 dwarn:4 dfail:0 fail:24 skip:832 time:10512s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_590/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 4/5] drm/i915: expose engine availability through sysfs
This enables userspace to discover the engines available on the GPU. Here is the layout on a Skylake GT4: /sys/devices/pci:00/:00:02.0/drm/card0/gt/ └── engines ├── bcs │ └── 0 │ ├── capabilities │ ├── class │ ├── id │ └── instance ├── rcs │ └── 0 │ ├── capabilities │ ├── class │ ├── id │ └── instance ├── vcs │ ├── 0 │ │ ├── capabilities │ │ │ └── hevc │ │ ├── class │ │ ├── id │ │ └── instance │ └── 1 │ ├── capabilities │ ├── class │ ├── id │ └── instance └── vecs └── 0 ├── capabilities ├── class ├── id └── instance Instance is the instance number of the engine for a particular class : $ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/engines/bcs/0/instance 0 Id is a global id used from submitting commands from userspace through execbuf : $ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/engines/bcs/0/id 3 Class maps to enum drm_i915_gem_engine_class in i915_drm.h : $ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/gt/engines/bcs/0/class 1 Further capabilities can be added later as attributes of each engine. v2: Add capabilities sub directory (Tvrtko) Move engines directory to drm/card/gt (Chris) v3: Move engines to drm/card/gt/engines/ (Tvrtko) Add instance attribute to engines (Tvrtko) v4: Fix dev_priv->gt_topology.engines_classes_kobj size (Lionel) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/i915_sysfs.c | 178 drivers/gpu/drm/i915/intel_engine_cs.c | 12 +++ drivers/gpu/drm/i915/intel_ringbuffer.h | 4 + 4 files changed, 200 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0a8e8a3772e5..893ecb0d4639 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2731,6 +2731,12 @@ struct drm_i915_private { } oa; } perf; + struct { + struct kobject gt_kobj; + struct kobject engines_kobj; + struct kobject engines_classes_kobjs[MAX_ENGINE_CLASS + 1]; + } gt_topology; + /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ struct { void (*resume)(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index c74a20b80182..d8ec8ec51cca 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -570,6 +570,178 @@ static void i915_setup_error_capture(struct device *kdev) {} static void i915_teardown_error_capture(struct device *kdev) {} #endif +static struct attribute engine_class_attr = { + .name = "class", + .mode = 0444, +}; + +static struct attribute engine_id_attr = { + .name = "id", + .mode = 0444, +}; + +static struct attribute engine_instance_attr = { + .name = "instance", + .mode = 0444, +}; + +static ssize_t +show_engine_attr(struct kobject *kobj, struct attribute *attr, char *buf) +{ + struct intel_engine_cs *engine = + container_of(kobj, struct intel_engine_cs, instance_kobj); + + if (attr == &engine_class_attr) + return sprintf(buf, "%hhu\n", engine->uabi_class); + if (attr == &engine_id_attr) + return sprintf(buf, "%hhu\n", engine->uabi_id); + if (attr == &engine_instance_attr) + return sprintf(buf, "%hhu\n", engine->instance); + return sprintf(buf, "\n"); +} + +static const struct sysfs_ops engine_ops = { + .show = show_engine_attr, +}; + +static struct kobj_type engine_type = { + .sysfs_ops = &engine_ops, +}; + +static struct attribute engine_capability_hevc_attr = { + .name = "hevc", + .mode = 0444, +}; + +static ssize_t +show_engine_capabilities_attr(struct kobject *kobj, struct attribute *attr, char *buf) +{ + struct intel_engine_cs *engine = + container_of(kobj, struct intel_engine_cs, capabilities_kobj); + + if (attr == &engine_capability_hevc_attr) + return sprintf(buf, "%i\n", INTEL_GEN(engine->i915) >= 8); + return sprintf(buf, "\n"); +} + +static const struct sysfs_ops engine_capabilities_ops = { + .show = show_engine_capabilities_attr, +}; + +static struct kobj_type engine_capabilities_type = { + .sysfs_ops = &engine_capabilities_ops, +}; + +static int i915_setup_engines_sysfs(struct drm_i915_private *dev_priv, + struct kobject *gt_kobj) +{ + struct intel_engine_cs *engine_for_class, *engine; + enum intel_engine_id id_for_class, id; + struct kobject *engines_kobj = &dev_priv->gt_topology.engines_kobj; + bool registred[MA
[Intel-gfx] [PATCH v6 3/5] drm/i915/debugfs: reuse max slice/subslices already stored in sseu
Now that we have that information in topology fields, let's just reused it. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 26 ++ 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ef091a2a6b12..961c5969b223 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4355,11 +4355,11 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { const struct intel_device_info *info = INTEL_INFO(dev_priv); - int s_max = 6, ss_max = 4; int s, ss; - u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2]; + u32 s_reg[info->sseu.max_slices], + eu_reg[2 * info->sseu.max_subslices], eu_mask[2]; - for (s = 0; s < s_max; s++) { + for (s = 0; s < info->sseu.max_slices; s++) { /* * FIXME: Valid SS Mask respects the spec and read * only valid bits for those registers, excluding reserverd @@ -4381,7 +4381,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, GEN9_PGCTL_SSB_EU210_ACK | GEN9_PGCTL_SSB_EU311_ACK; - for (s = 0; s < s_max; s++) { + for (s = 0; s < info->sseu.max_slices; s++) { if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) /* skip disabled slice */ continue; @@ -4389,7 +4389,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); sseu->subslices_mask[s] = info->sseu.subslices_mask[s]; - for (ss = 0; ss < ss_max; ss++) { + for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss @@ -4409,17 +4409,11 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { - int s_max = 3, ss_max = 4; + const struct intel_device_info *info = INTEL_INFO(dev_priv); int s, ss; - u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; - - /* BXT has a single slice and at most 3 subslices. */ - if (IS_GEN9_LP(dev_priv)) { - s_max = 1; - ss_max = 3; - } + u32 s_reg[info->sseu.max_slices], eu_reg[2*info->sseu.max_subslices], eu_mask[2]; - for (s = 0; s < s_max; s++) { + for (s = 0; s < info->sseu.max_slices; s++) { s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); @@ -4434,7 +4428,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, GEN9_PGCTL_SSB_EU210_ACK | GEN9_PGCTL_SSB_EU311_ACK; - for (s = 0; s < s_max; s++) { + for (s = 0; s < info->sseu.max_slices; s++) { if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) /* skip disabled slice */ continue; @@ -4445,7 +4439,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->subslices_mask[s] = INTEL_INFO(dev_priv)->sseu.subslices_mask[s]; - for (ss = 0; ss < ss_max; ss++) { + for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; if (IS_GEN9_LP(dev_priv)) { -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 0/5] drm/i915: Expose more GPU properties through sysfs
Hi, After discussion with Chris, Joonas & Tvrtko, this series adds an additional commit to link the render node back to the card through a symlink. Making it obvious from an application using a render node to know where to get the information it needs. Cheers, Lionel Landwerlin (5): drm: add card symlink in render sysfs directory drm/i915: store all subslice masks drm/i915/debugfs: reuse max slice/subslices already stored in sseu drm/i915: expose engine availability through sysfs drm/i915: expose EU topology through sysfs drivers/gpu/drm/drm_drv.c| 11 + drivers/gpu/drm/i915/i915_debugfs.c | 50 ++-- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 56 - drivers/gpu/drm/i915/i915_sysfs.c| 386 +++ drivers/gpu/drm/i915/intel_device_info.c | 169 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 12 + drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +- 9 files changed, 617 insertions(+), 77 deletions(-) -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 1/5] drm: add card symlink in render sysfs directory
In i915 we would like to expose information about the GPU topology which would be useful mostly to applications making use of the device computational capability (not so much the display part). At the moment we already store information like frequency, etc... into the card directory (/sys/class/drm/card0). It seems natural to add the additional data there too. Unfortunately it's not obvious how to go from the render node back to the sysfs card directory. From the major/minor number it's possible to figure out what device associated with the render node. For example with this render node : $ ls -l /dev/dri/renderD128 crw-rw+ 1 root video 226, 128 Oct 24 16:17 /dev/dri/renderD128 You can rebuild a part to access the associated drm device in : $ ls -l /sys/dev/char/226\:128/device/drm/ total 0 drwxr-xr-x 9 root root 0 Nov 27 16:52 card0 lrwxrwxrwx 1 root root 0 Nov 27 16:52 controlD64 -> card0 drwxr-xr-x 3 root root 0 Nov 27 16:50 renderD128 Right now, most devices have usually only one card. But in order to be future proof, we would like to associate the render node with the card so that you can get access to the card with the following path : /sys/dev/char/226\:128/card/ Signed-off-by: Lionel Landwerlin Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/drm_drv.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 9acc1e157813..a26c0e86778e 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -779,6 +779,14 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) if (drm_core_check_feature(dev, DRIVER_MODESET)) drm_modeset_register_all(dev); + if (drm_core_check_feature(dev, DRIVER_RENDER)) { + ret = sysfs_create_link(&dev->render->kdev->kobj, + &dev->primary->kdev->kobj, + "card"); + if (ret) + goto err_minors; + } + ret = 0; DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", @@ -835,6 +843,9 @@ void drm_dev_unregister(struct drm_device *dev) list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) drm_legacy_rmmap(dev, r_list->map); + if (drm_core_check_feature(dev, DRIVER_RENDER)) + sysfs_remove_link(&dev->render->kdev->kobj, "card"); + remove_compat_control_link(dev); drm_minor_unregister(dev, DRM_MINOR_PRIMARY); drm_minor_unregister(dev, DRM_MINOR_RENDER); -- 2.15.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/5] drm/i915: store all subslice masks
Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymetric (for example slice0 has different number of subslices as slice1+). This change stores all subslices masks for all slices rather than having a single mask that applies to all slices. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 24 +++-- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 23 - drivers/gpu/drm/i915/intel_device_info.c | 169 ++- drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 6 files changed, 161 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 28294470ae31..ef091a2a6b12 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4340,7 +4340,7 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, continue; sseu->slice_mask = BIT(0); - sseu->subslice_mask |= BIT(ss); + sseu->subslices_mask[0] |= BIT(ss); eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + @@ -4387,7 +4387,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, continue; sseu->slice_mask |= BIT(s); - sseu->subslice_mask = info->sseu.subslice_mask; + sseu->subslices_mask[s] = info->sseu.subslices_mask[s]; for (ss = 0; ss < ss_max; ss++) { unsigned int eu_cnt; @@ -4442,8 +4442,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); if (IS_GEN9_BC(dev_priv)) - sseu->subslice_mask = - INTEL_INFO(dev_priv)->sseu.subslice_mask; + sseu->subslices_mask[s] = + INTEL_INFO(dev_priv)->sseu.subslices_mask[s]; for (ss = 0; ss < ss_max; ss++) { unsigned int eu_cnt; @@ -4453,7 +4453,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, /* skip disabled subslice */ continue; - sseu->subslice_mask |= BIT(ss); + sseu->subslices_mask[s] |= BIT(ss); } eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & @@ -4475,9 +4475,12 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; if (sseu->slice_mask) { - sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; sseu->eu_per_subslice = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; + for (s = 0; s < fls(sseu->slice_mask); s++) { + sseu->subslices_mask[s] = + INTEL_INFO(dev_priv)->sseu.subslices_mask[s]; + } sseu->eu_total = sseu->eu_per_subslice * sseu_subslice_total(sseu); @@ -4496,6 +4499,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, { struct drm_i915_private *dev_priv = node_to_i915(m->private); const char *type = is_available_info ? "Available" : "Enabled"; + int s; seq_printf(m, " %s Slice Mask: %04x\n", type, sseu->slice_mask); @@ -4503,10 +4507,10 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, hweight8(sseu->slice_mask)); seq_printf(m, " %s Subslice Total: %u\n", type, sseu_subslice_total(sseu)); - seq_printf(m, " %s Subslice Mask: %04x\n", type, - sseu->subslice_mask); - seq_printf(m, " %s Subslice Per Slice: %u\n", type, - hweight8(sseu->subslice_mask)); + for (s = 0; s < fls(sseu->slice_mask); s++) { + seq_printf(m, " %s Slice%i Subslice Mask: %04x\n", type, + s, sseu->subslices_mask[s]); + } seq_printf(m, " %s EU Total: %u\n", type, sseu->eu_total); seq_printf(m, " %s EU Per Subslice: %u\n", type, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 7faf20aff25a..b9bfc38e6188 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -414,7 +414,7 @@ static int i915_getparam(struct drm_device *dev, void *data, return -
Re: [Intel-gfx] [PATCH i-g-t] igt: Make dependency on libunwind mandatory
On Fri, Dec 01, 2017 at 01:46:39PM +, Chris Wilson wrote: > Quoting Arkadiusz Hiler (2017-12-01 13:19:54) > > With Android support gone there is not much reason for keeping libunwind > > dependency optional. This also deals (cheaply!) with ifdefs covering > > huge portions of code, removing a placement minefield. > > Could also force building with frame-pointers? I'm wonder if that would > help with the less-than-useful stacktraces I get... > -Chris Give it a shot. Spin a series forcing FPs through the CI. Thanks for the review, merged with the unnecessary newline removed. -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] igt/drv_selftests: Disable initialising the display
On Thu, 2017-11-30 at 22:04 +, Chris Wilson wrote: > Many of the selftests try to completely fill global resources; > resources > that are presumed available for bringing up the display. Avoid the > contention by simply not bringing up the display! > > This does limit the effectiveness of selftesting to GEM for the > time being. To exercise KMS from selftests we would essentially have to > always mock the displays. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=103718 > Signed-off-by: Chris Wilson I think it's fair thing to do for now. Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for igt/pm_rc6_residency: Measure residency after checking for applicability (rev3)
== Series Details == Series: igt/pm_rc6_residency: Measure residency after checking for applicability (rev3) URL : https://patchwork.freedesktop.org/series/32097/ State : failure == Summary == Test gem_busy: Subgroup close-race: pass -> FAIL (shard-snb) fdo#103829 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (shard-hsw) fdo#102707 +1 Test drm_read: Subgroup fault-buffer: pass -> SKIP (shard-hsw) Test kms_cursor_legacy: Subgroup flip-vs-cursor-atomic-transitions-varying-size: pass -> SKIP (shard-hsw) fdo#102670 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#101623 +1 Test gem_tiled_swapping: Subgroup non-threaded: incomplete -> PASS (shard-snb) fdo#104009 Test pm_rc6_residency: Subgroup rc6-accuracy: pass -> FAIL (shard-snb) Test drv_selftest: Subgroup live_hangcheck: incomplete -> PASS (shard-snb) fdo#103880 fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880 shard-hswtotal:2663 pass:1534 dwarn:1 dfail:0 fail:10 skip:1118 time:9523s shard-snbtotal:2663 pass:1306 dwarn:2 dfail:0 fail:14 skip:1341 time:8122s Blacklisted hosts: shard-apltotal:2641 pass:1665 dwarn:1 dfail:0 fail:25 skip:949 time:13400s shard-kbltotal:2597 pass:1722 dwarn:28 dfail:1 fail:25 skip:819 time:10559s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_589/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt v3] igt/gem_busy: Replace arbitrary busy batch with indefinite spinbatch
On Sat, 2017-12-02 at 08:47 +, Chris Wilson wrote: > In CI, we were observing situations where the busy blt would complete > before the very next instruction (in userspace) to assert that it was > busy. This is entirely possible if the process was scheduled away and > slept for longer than the arbitrary batch. Instead replace arbitrariness > with a precise infinity. > > v2: Be respectful to UP! > v3: Move spinbatch to owning process to avoid serialisation delays. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103829 > Signed-off-by: Chris Wilson Even the variable names were good. Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for test/kms_plane_lowres: Fix display_commit_mode() so it returns the crc
== Series Details == Series: test/kms_plane_lowres: Fix display_commit_mode() so it returns the crc URL : https://patchwork.freedesktop.org/series/34749/ State : success == Summary == IGT patchset tested on top of latest successful build 476c4b462e0453c70ee81664c0227fdddc26cbd0 igt/gem_eio: Increase wakeup delay for in-flight-suspend with latest DRM-Tip kernel build CI_DRM_3448 b866e173d70a drm-tip: 2017y-12m-04d-09h-19m-02s UTC integration manifest No testlist changes. Test gem_exec_reloc: Subgroup basic-gtt-active: pass -> FAIL (fi-gdg-551) fdo#102582 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:439s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:443s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:388s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:505s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:490s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:479s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:176 dwarn:1 dfail:0 fail:3 skip:108 time:274s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:542s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:360s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:396s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:487s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:449s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:486s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:531s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:475s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:534s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:592s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:462s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:545s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:523s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:500s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:551s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:420s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:606s fi-glk-dsi total:288 pass:257 dwarn:0 dfail:0 fail:1 skip:30 time:488s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_591/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt/pm_rc6_residency: Measure residency after checking for applicability
CI doesn't run in whole-test mode, but runs each subtest individually. Tests that are designed to do a block of work to be shared between many subtests end up running that work multiple times (once per subtest) and worse, that work is wasted if the subtest will be skipped. pm_rc6_residency is one such example that measured all the residencies up front before skipping, each skip was therefore taking in excess of 10s. v2: Put a small delay back before starting measurements as rc6 doesn't start until an evaluation interval after idling. v3: Drop rc6p+ tests; we have no control over the hw whether it decides to use rc6 or deeper (we can enable it, but not dictate it). Signed-off-by: Chris Wilson Reviewed-by: Ewelina Musial #v1 --- tests/pm_rc6_residency.c | 122 +++ 1 file changed, 69 insertions(+), 53 deletions(-) diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c index ad05cca4..3f686019 100644 --- a/tests/pm_rc6_residency.c +++ b/tests/pm_rc6_residency.c @@ -53,11 +53,11 @@ struct residencies { static unsigned long get_rc6_enabled_mask(void) { - unsigned long rc6_mask; + unsigned long enabled; - rc6_mask = 0; - igt_sysfs_scanf(sysfs, "power/rc6_enable", "%lu", &rc6_mask); - return rc6_mask; + enabled = 0; + igt_sysfs_scanf(sysfs, "power/rc6_enable", "%lu", &enabled); + return enabled; } static unsigned long read_rc6_residency(const char *name) @@ -85,63 +85,67 @@ static void residency_accuracy(unsigned int diff, "Sysfs RC6 residency counter is inaccurate.\n"); } -static void read_residencies(int devid, unsigned int rc6_mask, +static unsigned long gettime_ms(void) +{ + struct timespec ts; + + clock_gettime(CLOCK_MONOTONIC, &ts); + + return ts.tv_sec * 1000 + ts.tv_nsec / 100; +} + +static void read_residencies(int devid, unsigned int mask, struct residencies *res) { - if (rc6_mask & RC6_ENABLED) + res->duration = gettime_ms(); + + if (mask & RC6_ENABLED) res->rc6 = read_rc6_residency("rc6"); - if ((rc6_mask & RC6_ENABLED) && + if ((mask & RC6_ENABLED) && (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))) res->media_rc6 = read_rc6_residency("media_rc6"); - if (rc6_mask & RC6P_ENABLED) + if (mask & RC6P_ENABLED) res->rc6p = read_rc6_residency("rc6p"); - if (rc6_mask & RC6PP_ENABLED) + if (mask & RC6PP_ENABLED) res->rc6pp = read_rc6_residency("rc6pp"); -} - -static unsigned long gettime_ms(void) -{ - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC, &ts); - - return ts.tv_sec * 1000 + ts.tv_nsec / 100; + res->duration += (gettime_ms() - res->duration) / 2; } -static void measure_residencies(int devid, unsigned int rc6_mask, +static void measure_residencies(int devid, unsigned int mask, struct residencies *res) { struct residencies start = { }; struct residencies end = { }; int retry; - unsigned long t; - if (!rc6_mask) + if (!mask) return; - /* -* For some reason my ivb isn't idle even after syncing up with the gpu. -* Let's add a sleep just to make it happy. -*/ - sleep(8); - /* * Retry in case of counter wrap-around. We simply re-run the * measurement, since the valid counter range is different on * different platforms and so fixing it up would be non-trivial. */ + read_residencies(devid, mask, &end); + igt_debug("time=%d: rc6=(%d, %d), rc6p=%d, rc6pp=%d\n", +end.duration, end.rc6, end.media_rc6, end.rc6p, end.rc6pp); for (retry = 0; retry < 2; retry++) { - t = gettime_ms(); - read_residencies(devid, rc6_mask, &start); + start = end; sleep(SLEEP_DURATION); - read_residencies(devid, rc6_mask, &end); - t = gettime_ms() - t; + read_residencies(devid, mask, &end); + + igt_debug("time=%d: rc6=(%d, %d), rc6p=%d, rc6pp=%d\n", +end.duration, +end.rc6, end.media_rc6, end.rc6p, end.rc6pp); - if (end.rc6 >= start.rc6 && end.media_rc6 >= start.media_rc6 && - end.rc6p >= start.rc6p && end.rc6pp >= start.rc6pp) + if (end.rc6 >= start.rc6 && + end.media_rc6 >= start.media_rc6 && + end.rc6p >= start.rc6p && + end.rc6pp >= start.rc6pp) break; } igt_assert_f(retry < 2, "residency values are not consistent\n"); @@ -150,7 +154,7 @@ static void measure_residencies(int devid, unsigned int rc6_mask, res->rc6p = end.rc6p - start.rc6p; res->rc6pp = en
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush pending GTT writes before unbinding (rev2)
== Series Details == Series: drm/i915: Flush pending GTT writes before unbinding (rev2) URL : https://patchwork.freedesktop.org/series/34830/ State : success == Summary == Series 34830v2 drm/i915: Flush pending GTT writes before unbinding https://patchwork.freedesktop.org/api/1.0/series/34830/revisions/2/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:441s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:385s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:527s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:506s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:501s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:476s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:275s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:538s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:260s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:393s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:490s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:446s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:490s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:533s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:537s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:593s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:540s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:563s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:517s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:552s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:420s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:616s fi-glk-dsi total:288 pass:257 dwarn:0 dfail:0 fail:1 skip:30 time:505s fi-hsw-4770 failed to collect. IGT log at Patchwork_7396/fi-hsw-4770/igt.log b866e173d70abc9fc308d40141d6bfafd2a8591a drm-tip: 2017y-12m-04d-09h-19m-02s UTC integration manifest 8474aec4f849 drm/i915: Flush pending GTT writes before unbinding == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7396/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] lib: avoid < in gtkdoc comments
On Wed, 2017-11-29 at 12:17 +0100, Daniel Vetter wrote: > For reasons entirely not clear to me meson gtkdoc runs in strict > xml parsing mode, whereas automake gtkdoc doesn't. And gtkdoc itself > is to dense to correctly escape this stuff. > > Paper around this. > > Signed-off-by: Daniel Vetterlooks trippy. As we're not trying to document HTML stuff, maybe simly -> ${foo}. I'm pretty sure everyone will be comfortable with that notation. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx