Re: [Intel-gfx] [PATCH] drm/i915: forward hotplug events again

[Chris Wilson]

Quoting Rodrigo Vivi (2018-01-05 01:42:55)
> As mentioned on commit '88be58be886f ("drm/i915/fbdev:
> Always forward hotplug events") we have real valid cases
> of hotplugs where fbdev is not fully setup yet.
> 
> Unfortunately this remove the checkpoint after the sync point.
> So probably we can live without it. Or we need a more robust
> serialization.

Heh? So you are removing the check as to whether or not the async init
worked. Without the vma, fbdev doesn't exist and the hotplug event will
cause the machine to die (see recent history for examples). I think what
you intend is to always allocate a basic 1024x768 vma if the init config
finds no crtcs to setup.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Vivi, Rodrigo]

On Jan 4, 2018, at 10:07 PM, Kenneth Graunke 
> wrote:

On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote:
On Thu, Jan 04, 2018 at 11:39:23PM +, Kenneth Graunke wrote:
On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
Quoting Kenneth Graunke (2018-01-04 19:38:05)
Geminilake requires the 3D driver to select whether barriers are
intended for compute shaders, or tessellation control shaders, by
whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
switching pipelines.  Failure to do this properly can result in GPU
hangs.

Unfortunately, this means it needs to switch mid-batch, so only
userspace can properly set it.  To facilitate this, the kernel needs
to whitelist the register.

Signed-off-by: Kenneth Graunke 
>
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
2 files changed, 7 insertions(+)

Hello,

We unfortunately need to whitelist an extra register for GPU hang fix
on Geminilake.  Here's the corresponding Mesa patch:

Thankfully it appears to be context saved. Has a w/a name been assigned
for this?
-Chris

There doesn't appear to be one.  The workaround page lists it, but there
is no name.  The register description has a note saying that you need to
set this, but doesn't call it out as a workaround.

It mentions only BXT:ALL, but not mention to GLK.

Should we add to both then?

Well, that's irritating.

Indeed. As always :)

 On the workarounds page, it does indeed say
"BXT" with no mention of GLK.  But the workaround text says to set
"SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)."

Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7
is "Barrier Mode" on [GLK] only, with no mention of BXT.  It's marked
reserved PBC on [SKL+, not GLK, not KBL].  On KBL it's something else.

I have no ways to check this bit right now,
But your explanation makes sense so I agree with you...
Acked-by: Rodrigo Vivi >


I believe Mark saw hangs in tessellation control shader hangs on
Geminilake only, and never saw this issue on Broxton.  So, my guess is
that the workaround really is new on Geminilake, and the BXT tag on the
workarounds page is incorrect.  (Mark, does that sound right to you?)

Probably worth a mention on comment or commit msg?!


That's why I put a generic comment, rather than the name.

On Display side we started using the row name for this case, to help
easily finding this later.

ex: "Display WA #0390: skl,kbl"

The number for this apparently is:
WA #0862

Maybe we could use this one to start
/* GT WA #0862: bxt,glk */

GT? GEM?
Unnamed WA #0862?

Including #0862 seems like a good idea.  I'm happy to change the comment
to whatever you'd prefer.

Leave your comment and add WA #0862...
If later we define a standardized style we come back and change this.

Thanks
Rodrigo


--Ken
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Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Kenneth Graunke]

On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote:
> On Thu, Jan 04, 2018 at 11:39:23PM +, Kenneth Graunke wrote:
> > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
> > > Quoting Kenneth Graunke (2018-01-04 19:38:05)
> > > > Geminilake requires the 3D driver to select whether barriers are
> > > > intended for compute shaders, or tessellation control shaders, by
> > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > > > switching pipelines.  Failure to do this properly can result in GPU
> > > > hangs.
> > > > 
> > > > Unfortunately, this means it needs to switch mid-batch, so only
> > > > userspace can properly set it.  To facilitate this, the kernel needs
> > > > to whitelist the register.
> > > > 
> > > > Signed-off-by: Kenneth Graunke 
> > > > Cc: sta...@vger.kernel.org
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h| 2 ++
> > > >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
> > > >  2 files changed, 7 insertions(+)
> > > > 
> > > > Hello,
> > > > 
> > > > We unfortunately need to whitelist an extra register for GPU hang fix
> > > > on Geminilake.  Here's the corresponding Mesa patch:
> > > 
> > > Thankfully it appears to be context saved. Has a w/a name been assigned
> > > for this?
> > > -Chris
> > 
> > There doesn't appear to be one.  The workaround page lists it, but there
> > is no name.  The register description has a note saying that you need to
> > set this, but doesn't call it out as a workaround.
> 
> It mentions only BXT:ALL, but not mention to GLK.
> 
> Should we add to both then?

Well, that's irritating.  On the workarounds page, it does indeed say
"BXT" with no mention of GLK.  But the workaround text says to set
"SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)."

Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7
is "Barrier Mode" on [GLK] only, with no mention of BXT.  It's marked
reserved PBC on [SKL+, not GLK, not KBL].  On KBL it's something else.

I believe Mark saw hangs in tessellation control shader hangs on
Geminilake only, and never saw this issue on Broxton.  So, my guess is
that the workaround really is new on Geminilake, and the BXT tag on the
workarounds page is incorrect.  (Mark, does that sound right to you?)

> > That's why I put a generic comment, rather than the name.
> 
> On Display side we started using the row name for this case, to help
> easily finding this later.
> 
> ex: "Display WA #0390: skl,kbl"
> 
> The number for this apparently is:
> WA #0862
> 
> Maybe we could use this one to start
> /* GT WA #0862: bxt,glk */
> 
> GT? GEM?
> Unnamed WA #0862?

Including #0862 seems like a good idea.  I'm happy to change the comment
to whatever you'd prefer.

--Ken


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Re: [Intel-gfx] [PATCH v3 11/12] drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled

[Sagar Arun Kamble]

On 1/4/2018 11:19 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:53 +0100, Sagar Arun Kamble 
 wrote:



In order to override the disable/enable control of GuC interrupts during
suspend/reset cycle we are creating two new functions suspend/restore
guc_interrupts which check if interrupts were enabled and disable them
on suspend and enable them on resume. They are used to restore 
interrupts

across reset as well.

Further restructuring of runtime_pm_enable/disable_interrupts and
suspend/restore_guc_interrupts will be done in upcoming patches.

v2: Rebase.

v3: Updated suspend/restore with the new low level get/put functions.
(Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_guc.c | 32 


 drivers/gpu/drm/i915/intel_guc.h |  2 ++
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c

index 0cd3559..2e0db53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3676,8 +3676,10 @@ void intel_finish_reset(struct 
drm_i915_private *dev_priv)

  * The display has been reset as well,
  * so need a full re-initialization.
  */
+    intel_suspend_guc_interrupts(_priv->guc);
 intel_runtime_pm_disable_interrupts(dev_priv);
 intel_runtime_pm_enable_interrupts(dev_priv);
+    intel_restore_guc_interrupts(_priv->guc);
    intel_pps_unlock_regs_wa(dev_priv);
 intel_modeset_init_hw(dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index d356c40..28a418a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,8 +406,7 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)

 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 return 0;
-    if (guc->log.level >= 0)
-    intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+    intel_suspend_guc_interrupts(guc);


Hmm, maybe we should introduce

intel_uc_suspend(struct drm_i915_private *dev_priv)

which will call separately

intel_guc_suspend(guc); /* send suspend action */
intel_guc_suspend_interrupts(guc);

Yes. Ordering was not correct. I have this change as part of 
suspend/resume restructuring from GuC/GEM which will follow

after this. Will keep as it is for now in this patch.

data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 /* any value greater than GUC_POWER_D0 */
@@ -452,8 +451,7 @@ int intel_guc_resume(struct drm_i915_private 
*dev_priv)

 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 return 0;
-    if (guc->log.level >= 0)
-    intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+    intel_restore_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 data[1] = GUC_POWER_D0;
@@ -548,6 +546,16 @@ void intel_get_guc_interrupts(struct intel_guc 
*guc, enum guc_intr_client id)

 spin_unlock_irq(_priv->irq_lock);
 }
+void intel_restore_guc_interrupts(struct intel_guc *guc)
+{
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+    spin_lock_irq(_priv->irq_lock);
+    if (guc->interrupt_clients)
+    __intel_get_guc_interrupts(guc);
+    spin_unlock_irq(_priv->irq_lock);
+}
+
 static void __intel_put_guc_interrupts(struct intel_guc *guc)
 {
 struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,6 +584,22 @@ void intel_put_guc_interrupts(struct intel_guc 
*guc, enum guc_intr_client id)

 intel_reset_guc_interrupts(guc);
 }
+void intel_suspend_guc_interrupts(struct intel_guc *guc)
+{
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+    spin_lock_irq(_priv->irq_lock);
+    if (!guc->interrupt_clients) {
+    spin_unlock_irq(_priv->irq_lock);
+    return;
+    }
+    __intel_put_guc_interrupts(guc);
+    spin_unlock_irq(_priv->irq_lock);
+    synchronize_irq(dev_priv->drm.irq);
+
+    intel_reset_guc_interrupts(guc);
+}
+
 void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
 struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h

index af74392..2c14781 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -140,5 +140,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma 
*vma)
 void intel_get_guc_interrupts(struct intel_guc *guc, enum 
guc_intr_client id);
 void intel_put_guc_interrupts(struct intel_guc *guc, enum 
guc_intr_client id);

 void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);
+void 

Re: [Intel-gfx] [PATCH v3 10/12] drm/i915/guc: Add client support to enable/disable GuC interrupts

[Sagar Arun Kamble]

On 1/4/2018 11:09 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:52 +0100, Sagar Arun Kamble 
 wrote:



This patch adds support to enable/disable GuC interrupts for different
features without impacting other's need. Currently GuC log capture and
CT buffer receive mechanisms use the GuC interrupts. GuC interrupts are
currently enabled and disabled in different logging scenarios all gated
by log level.

v2: Rebase with all GuC interrupt handlers moved to intel_guc.c. 
Handling

multiple clients for GuC interrupts enable/disable.
(Michal Wajdeczko)

v3: Removed spin lock and using test_bit in i915_guc_info. Prepared low
level helpers to get/put GuC interrupts that can be reused during
suspend/resume. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 +
 drivers/gpu/drm/i915/intel_guc.c | 47 
+++-

 drivers/gpu/drm/i915/intel_guc.h | 11 ++---
 drivers/gpu/drm/i915/intel_guc_log.c |  6 ++---
 drivers/gpu/drm/i915/intel_uc.c  |  4 +--
 5 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c

index 16f9a95..eef4c8b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2340,6 +2340,12 @@ static int i915_guc_info(struct seq_file *m, 
void *data)

 GEM_BUG_ON(!guc->execbuf_client);
 GEM_BUG_ON(!guc->preempt_client);
+    seq_puts(m, "GuC Interrupt Clients: ");
+    if (test_bit(GUC_INTR_CLIENT_LOG, >interrupt_clients))
+    seq_puts(m, "GuC Logging\n");
+    else
+    seq_puts(m, "None\n");
+


Maybe this can be done in intel_guc_log.c as part of:

void intel_guc_log_dump(const struct intel_guc_log *log, struct 
drm_printer *p);


Idea is to know as part of GuC global information, which all features 
have enabled GuC to Host Interrupts.
I can add it in the i915_guc_log_dump as to whether interrupt is enabled 
but then I think it will be good to have

it here to know interrupt status together at once we have CTB as well.



 seq_printf(m, "Doorbell map:\n");
 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", 
guc->db_cacheline);
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index 36d1bca..d356c40 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -407,7 +407,7 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)

 return 0;
if (guc->log.level >= 0)
-    intel_disable_guc_interrupts(guc);
+    intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 /* any value greater than GUC_POWER_D0 */
@@ -453,7 +453,7 @@ int intel_guc_resume(struct drm_i915_private 
*dev_priv)

 return 0;
if (guc->log.level >= 0)
-    intel_enable_guc_interrupts(guc);
+    intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 data[1] = GUC_POWER_D0;
@@ -524,28 +524,51 @@ void intel_reset_guc_interrupts(struct 
intel_guc *guc)

 spin_unlock_irq(_priv->irq_lock);
 }
-void intel_enable_guc_interrupts(struct intel_guc *guc)
+static void __intel_get_guc_interrupts(struct intel_guc *guc)
+{
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+    lockdep_assert_held(_priv->irq_lock);
+
+    WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+   dev_priv->pm_guc_events);
+    gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_get_guc_interrupts(struct intel_guc *guc, enum 
guc_intr_client id)


What about intel_guc_interrupts_get(guc, id) ?


 {
 struct drm_i915_private *dev_priv = guc_to_i915(guc);
spin_lock_irq(_priv->irq_lock);
-    if (!dev_priv->guc.interrupts_enabled) {
-    WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-   dev_priv->pm_guc_events);
-    dev_priv->guc.interrupts_enabled = true;
-    gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-    }
+
+    if (!guc->interrupt_clients)
+    __intel_get_guc_interrupts(guc);
+    __set_bit(id, >interrupt_clients);


Do we care about scenarios when we call "get" more than once?
Maybe we need GEM_WARN_ON at the minimum ?

Then I'm wondering if "get/put" are correct if we don't do any
refcounting... maybe "enable/disable" are more appropriate then?

enabling/disabling more than once should not be a problem. will update 
the names

as suggested as we don't refcount.

+
 spin_unlock_irq(_priv->irq_lock);
 }
-void intel_disable_guc_interrupts(struct intel_guc *guc)

Re: [Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Sagar Arun Kamble]

On 1/4/2018 10:52 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:45 +0100, Sagar Arun Kamble 
 wrote:


GuC interrupts handling functions are GuC specific functions hence 
update

the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 22 +++---
 drivers/gpu/drm/i915/intel_guc.h |  8 
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
 drivers/gpu/drm/i915/intel_uc.c  |  8 
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c 
b/drivers/gpu/drm/i915/i915_irq.c

index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct 
drm_i915_private *dev_priv,

 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
if (gt_iir[2] & dev_priv->pm_guc_events)
-    intel_guc_irq_handler(dev_priv, gt_iir[2]);
+    intel_guc_irq_handler(_priv->guc, gt_iir[2]);
 }
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)

 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 return 0;
-    intel_disable_guc_interrupts(dev_priv);
+    intel_disable_guc_interrupts(guc);


Hmm, if we disable irq here, then we might have problems with
sending this message to GuC if we use CTB as comm mechanism...


Yes. This gets fixed in the later patches in the series.

data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 /* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private 
*dev_priv)

 return 0;
if (i915_modparams.guc_log_level >= 0)
-    intel_enable_guc_interrupts(dev_priv);
+    intel_enable_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct 
drm_i915_private *dev_priv)

 return wopcm_size;
 }
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
 spin_lock_irq(_priv->irq_lock);
 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 spin_unlock_irq(_priv->irq_lock);
 }
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
 spin_lock_irq(_priv->irq_lock);
 if (!dev_priv->guc.interrupts_enabled) {


Just spotted:
as we have "guc" try to use "guc->" instead of "dev_priv->guc."


Ok :)

WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct 
drm_i915_private *dev_priv)

 spin_unlock_irq(_priv->irq_lock);
 }
-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
 spin_lock_irq(_priv->irq_lock);
 dev_priv->guc.interrupts_enabled = false;


same here (and possibly in other places too)


Sure.
@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct 
drm_i915_private *dev_priv)

 spin_unlock_irq(_priv->irq_lock);
 synchronize_irq(dev_priv->drm.irq);
-    intel_reset_guc_interrupts(dev_priv);
+    intel_reset_guc_interrupts(guc);
 }
-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
gt_iir)

+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+    struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
 /* Sample the log buffer flush related bits & clear them out 
now

  * itself from the message identity register to minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h

index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma 
*vma)

 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);

 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-void 

Re: [Intel-gfx] [PATCH v3 09/12] drm/i915/guc: Make GuC log related functions depend only on log level

[Sagar Arun Kamble]

On 1/4/2018 10:45 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:51 +0100, Sagar Arun Kamble 
 wrote:


With GuC log level set properly only for cases where GuC is loaded we 
can
remove the GuC submission checks from flush_guc_logs and 
guc_log_register,
unregister and uc_fini_hw functions. It is important to note that GuC 
log

runtime data has to be freed during driver unregister.
Freeing of that data can't be gated by guc_log_level check because if we
free GuC log runtime only when log level >=0 then it will not be 
destroyed

when logging is disabled after enabling before driver unload.

Also, with this patch GuC interrupts are enabled first after GuC load if
logging is enabled. GuC to Host interrupts will be needed for GuC CT
buffer recv mechanism and hence we will be adding support to control 
that
interrupt based on ref. taken by Log or CT recv feature in next 
patch. To

prepare for that all interrupt updates are now gated by GuC log level
checks.

v2: Rebase. Updated check in i915_guc_log_unregister to be based on
guc_log_level. (Michal Wajdeczko)

v3: Rebase. Made all GuC log related functions depend only log level.
Updated uC init w.r.t enabling of GuC interrupts. Commit message update.
Rebase w.r.t guc_log_level immutable changes. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 17 +++--
 drivers/gpu/drm/i915/intel_uc.c  | 15 ---
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index d351642..36d1bca 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,7 +406,8 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)

 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 return 0;
-    intel_disable_guc_interrupts(guc);
+    if (guc->log.level >= 0)
+    intel_disable_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 /* any value greater than GUC_POWER_D0 */
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c

index d979830..7bc0065 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -484,8 +484,7 @@ static void guc_log_capture_logs(struct intel_guc 
*guc)

static void guc_flush_logs(struct intel_guc *guc)
 {
-    if (!USES_GUC_SUBMISSION(dev_priv) ||
-    guc->log.level < 0)
+    if (guc->log.level < 0)
 return;
/* First disable the interrupts, will be renabled afterwards */
@@ -613,8 +612,7 @@ int i915_guc_log_control(struct drm_i915_private 
*dev_priv, u64 control_val)

void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-    if (!USES_GUC_SUBMISSION(dev_priv) ||
-    dev_priv->guc.log.level < 0)
+    if (dev_priv->guc.log.level < 0)
 return;
mutex_lock(_priv->drm.struct_mutex);
@@ -624,14 +622,13 @@ void i915_guc_log_register(struct 
drm_i915_private *dev_priv)

void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-    if (!USES_GUC_SUBMISSION(dev_priv))
-    return;
-
 mutex_lock(_priv->drm.struct_mutex);
 /* GuC logging is currently the only user of Guc2Host interrupts */
-    intel_runtime_pm_get(dev_priv);
-    intel_disable_guc_interrupts(_priv->guc);
-    intel_runtime_pm_put(dev_priv);
+    if (dev_priv->guc.log.level >= 0) {


Can we move "if (guc->log.level >= 0)" condition check to
intel_guc_[disable|enable]_interrupts functions? Then we
should be able to avoid repeating this check over and over
and it will be also easier for use once we add new CTB check.

I will create a new wrapper function for this logging specific check. 
Will not move the check to
guc_enable|disable_intr as it will be low level handler to 
enable/disable interrupts to be used

by logging, CTB.

+    intel_runtime_pm_get(dev_priv);
+    intel_disable_guc_interrupts(_priv->guc);
+    intel_runtime_pm_put(dev_priv);
+    }
intel_guc_log_runtime_destroy(_priv->guc);
 mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index e2e2020..fb5edcc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -318,9 +318,12 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)

 if (ret)
 goto err_log_capture;
+    if (guc->log.level >= 0)
+    intel_enable_guc_interrupts(guc);
+
 ret = guc_enable_communication(guc);
 if (ret)
-    goto err_log_capture;
+    goto err_interrupts;
if (USES_HUC(dev_priv)) {
 ret = 

Re: [Intel-gfx] [PATCH v3 04/12] drm/i915/guc: Add description and comments about guc_log_level parameter

[Sagar Arun Kamble]

On 1/4/2018 10:22 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:46 +0100, Sagar Arun Kamble 
 wrote:



guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info.

^^^
Extra "."


in parameter description and documentation.
Earlier, this patch was added to sanitize guc_log_level like old
GuC parameters enable_guc_loading/submission. With new parameter
enable_guc, sanitization of guc_log_level is no more needed.


Hmm, I think we still need to sanitize log_level if it was wrongly
enabled without enabling GuC first (in intel_uc_sanitize_options).
I think it would not be harmful as all decisions based on it will be 
gated by USES_GUC.




v2: Added documentation to intel_guc_log.c and param description
about GuC loading dependency. (Michal Wajdeczko)

v3: Removed sanitization of module parameter guc_log_level.
Previous review comments not applicable now.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin  #v2
---
 drivers/gpu/drm/i915/i915_params.c   | 3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c

index b5f3eb4..a93a6ca 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -155,7 +155,8 @@ struct i915_params i915_modparams __read_mostly = {
 "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
i915_param_named(guc_log_level, int, 0400,
-    "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+    "GuC firmware logging level. This takes effect only if GuC is to 
be "
+    "loaded (depends on enable_guc) (-1:disabled (default), 
0-3:enabled)");


Btw, I was planing to change above values to follow schema used in 
other modparams:


-1: auto (then it can be controlled by USES_GUC and DRM_I915_DEBUG_GUC)
 0: disabled
 1: enabled (legacy level 0)
 2: enabled (legacy level 1)
 3: enabled (legacy level 2)
 4: enabled (legacy level 3)

So now I'm not sure that I want your patch ;)


Makes sense. Will drop this patch.

Thanks
Sagar

i915_param_named_unsafe(guc_firmware_path, charp, 0400,
 "GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c

index 59a9021..d0131bc 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -34,6 +34,7 @@
  * DOC: GuC firmware log
  *
  * Firmware log is enabled by setting i915.guc_log_level to 
non-negative level.

+ * This takes effect only if GuC is to be loaded based on enable_guc.


... based on i915.enable_guc modparam.

  * Log data is printed out via reading debugfs i915_guc_log_dump. 
Reading from
  * i915_guc_load_status will print out firmware loading status and 
scratch

  * registers value.


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Re: [Intel-gfx] [PATCH v3 12/12] HAX: drm/i915/guc: enable GuC submission/logging for CI

[Sagar Arun Kamble]

On 1/4/2018 9:59 PM, Chris Wilson wrote:

Quoting Sagar Arun Kamble (2018-01-04 16:21:54)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d..c8460c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2659,6 +2659,8 @@ static int intel_runtime_resume(struct device *kdev)
 if (intel_uncore_unclaimed_mmio(dev_priv))
 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
  
+   intel_runtime_pm_enable_interrupts(dev_priv);

+
 intel_guc_resume(dev_priv);
  
 if (IS_GEN9_LP(dev_priv)) {

@@ -2682,8 +2684,6 @@ static int intel_runtime_resume(struct device *kdev)
 i915_gem_init_swizzling(dev_priv);
 i915_gem_restore_fences(dev_priv);
  
-   intel_runtime_pm_enable_interrupts(dev_priv);

Have I missed the pending patch?
There is suspend/resume related restructuring series for GuC/GEM that is 
in queue post this series.

Was reviewed partly some time back.

Thanks
Sagar

-Chris


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Re: [Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Sagar Arun Kamble]

On 1/4/2018 10:01 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:23:05 +0100, Chris Wilson 
 wrote:



Quoting Sagar Arun Kamble (2018-01-04 16:21:45)
GuC interrupts handling functions are GuC specific functions hence 
update

the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 22 +++---
 drivers/gpu/drm/i915/intel_guc.h |  8 
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
 drivers/gpu/drm/i915/intel_uc.c  |  8 
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c 
b/drivers/gpu/drm/i915/i915_irq.c

index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct 
drm_i915_private *dev_priv,

    gen6_rps_irq_handler(dev_priv, gt_iir[2]);

    if (gt_iir[2] & dev_priv->pm_guc_events)
-   intel_guc_irq_handler(dev_priv, gt_iir[2]);
+   intel_guc_irq_handler(_priv->guc, gt_iir[2]);
 }

 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)

    if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
    return 0;

-   intel_disable_guc_interrupts(dev_priv);
+   intel_disable_guc_interrupts(guc);

    data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
    /* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private 
*dev_priv)

    return 0;

    if (i915_modparams.guc_log_level >= 0)
-   intel_enable_guc_interrupts(dev_priv);
+   intel_enable_guc_interrupts(guc);

    data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
    data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct 
drm_i915_private *dev_priv)

    return wopcm_size;
 }

-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
    spin_lock_irq(_priv->irq_lock);
    gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
    spin_unlock_irq(_priv->irq_lock);
 }

-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
    spin_lock_irq(_priv->irq_lock);
    if (!dev_priv->guc.interrupts_enabled) {
    WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct 
drm_i915_private *dev_priv)

    spin_unlock_irq(_priv->irq_lock);
 }

-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
    spin_lock_irq(_priv->irq_lock);
    dev_priv->guc.interrupts_enabled = false;

@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct 
drm_i915_private *dev_priv)

    spin_unlock_irq(_priv->irq_lock);
    synchronize_irq(dev_priv->drm.irq);

-   intel_reset_guc_interrupts(dev_priv);
+   intel_reset_guc_interrupts(guc);
 }

-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
gt_iir)

+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
    if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
    /* Sample the log buffer flush related bits & clear 
them out now
 * itself from the message identity register to 
minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h

index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct 
i915_vma *vma)

 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);

 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_enable_guc_interrupts(struct drm_i915_private 

Re: [Intel-gfx] [PATCH i-g-t 1/6] i-g-t: kms_plane_scaling: Fix basic scaling test

[Srinivas, Vidya]

> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Thursday, January 4, 2018 8:27 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Vetter, Daniel 
> Subject: Re: [Intel-gfx] [PATCH i-g-t 1/6] i-g-t: kms_plane_scaling: Fix basic
> scaling test
> 
> Op 13-12-17 om 10:50 schreef Vidya Srinivas:
> > From: Mahesh Kumar 
> >
> > PIPEC doesnt have 3rd plane in GEN9. So, we skip the 3rd plane related
> > scaling test where 2nd OVERLAY plane is not available.
> >
> > Restricting downscaling to (9/10)x original size of the image to avoid
> > "Max pixel rate limitation" of the hardware.
> >
> > Later patches in this series will cover corner cases of scaling.
> >
> > Signed-off-by: Mahesh Kumar 
> > Signed-off-by: Jyoti Yadav 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >  tests/kms_plane_scaling.c | 234
> > +-
> >  1 file changed, 125 insertions(+), 109 deletions(-)
> >
> > diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
> > index 403df47..a827cb3 100644
> > --- a/tests/kms_plane_scaling.c
> > +++ b/tests/kms_plane_scaling.c
> > @@ -163,144 +163,159 @@ static void iterate_plane_scaling(data_t *d,
> drmModeModeInfo *mode)
> > }
> >  }
> 
> The scaler tests should really require display->is_atomic. Even if there are
> theoretically more limits on the amount of scalers, having a YUV mode or
> interlaced mode may take a scaler, causing this test to fail.
> 
> With try_commit_atomic, it would be possible to test if enough scalers are
> available.
> 
> On top of that, I would really like the test to be more readable, and having
> test_plane_scaling_on_pipe split up in smaller pieces would accomplish
> that.
> 
> I would do some split ups first before doing any fixes, it's hard to read
> what's changed through the whitespace changes, even if the code is correct.
> 
> Also this test needs to be split up into subtests, this is a good start for 
> it.
> 
> Replace igt_simple_main with igt_main, and add subtests for each pipe and
> various tests being performed. See for example kms_color, this test is
> already trying to do too much in one go. :)
> 
> ~Maarten
> 

Thank you. Regarding igt subtests, we have done that in the subsequent patches 
(4th in this series).
https://patchwork.kernel.org/patch/10109581/
Regarding the split up (readability), we have kept it simple for the additional 
tests that we added
in the subsequent patches. In this first patch, we did not want to modify the 
existing code
or make huge changes. We just wanted to fix the existing test case so that it 
runs
without failure. Please do have a check on the other patches and provide your 
feedback.
It would be very helpful.

Regards
Vidya

> >
> > -static void test_plane_scaling(data_t *d)
> > +static void
> > +test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, igt_output_t
> > +*output)
> >  {
> > igt_display_t *display = >display;
> > -   igt_output_t *output;
> > -   enum pipe pipe;
> > -   int valid_tests = 0;
> > +   drmModeModeInfo *mode;
> > int primary_plane_scaling = 0; /* For now */
> >
> > -   igt_require(d->num_scalers);
> > +   igt_output_set_pipe(output, pipe);
> > +   mode = igt_output_get_mode(output);
> > +
> > +   /* allocate fb2 with image size */
> > +   d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
> > +   DRM_FORMAT_XRGB,
> > +   LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
> > +   FILE_NAME, >fb2);
> > +   igt_assert(d->fb_id2);
> > +
> > +   d->fb_id3 = igt_create_pattern_fb(d->drm_fd,
> > +   mode->hdisplay, mode->vdisplay,
> > +   DRM_FORMAT_XRGB,
> > +   LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
> > +   >fb3);
> > +   igt_assert(d->fb_id3);
> > +
> > +   /* Set up display with plane 1 */
> > +   d->plane1 = igt_output_get_plane(output, 0);
> > +   prepare_crtc(d, output, pipe, d->plane1, mode,
> COMMIT_UNIVERSAL);
> > +
> > +   if (primary_plane_scaling) {
> > +   /* Primary plane upscaling */
> > +   igt_fb_set_position(>fb1, d->plane1, 100, 100);
> > +   igt_fb_set_size(>fb1, d->plane1, 500, 500);
> > +   igt_plane_set_position(d->plane1, 0, 0);
> > +   igt_plane_set_size(d->plane1, mode->hdisplay, mode-
> >vdisplay);
> > +   igt_display_commit2(display, COMMIT_UNIVERSAL);
> >
> > -   for_each_pipe_with_valid_output(display, pipe, output) {
> > -   drmModeModeInfo *mode;
> > -
> > -   igt_output_set_pipe(output, pipe);
> > -
> > -   mode = igt_output_get_mode(output);
> > -
> > -   /* allocate fb2 with image size */
> > -   d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
> > -   

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts

[Rodrigo Vivi]

On Wed, Jan 03, 2018 at 08:40:00PM +, Dhinakaran Pandiyan wrote:
> When DC states are enabled and PSR is active, the hardware enters DC5/DC6
> states resulting in the frame counter resetting. The frame counter reset
> mess up the vblank counting logic as the diff between the new frame
> counter value and the previous is negative, and this negative diff gets
> applied as an unsigned value to the vblank count. We cannot reject negative
> diffs altogether because they can arise from legitimate frame counter
> overflows when there is a long period with vblank disabled. So, this
> approach allows for the driver to notice a DC state toggle between a vblank
> disable and enable and fill in the missed vblanks.
> 
> But, in order to disable DC states when vblank interrupts are required,
> the DC_OFF power well has to be disabled in an atomic context. So,
> introduce a new VBLANK power domain that can be acquired and released in
> atomic contexts with these changes -
> 1)  _vblank_get() and _vblank_put() methods skip the power_domain mutex
> and use a spin lock for the DC power well.
> 2) power_domains->domain_use_count is converted to an atomic_t array so
> that it can be updated outside of the power domain mutex.
> 
> v3: Squash domain_use_count atomic_t conversion (Maarten)
> v2: Fix deadlock by switching irqsave spinlock.
> Implement atomic version of get_if_enabled.
> Modify power_domain_verify_state to check power well use count and
> enabled status atomically.
> Rewrite of intel_power_well_{get,put}
> 
> Cc: Maarten Lankhorst 
> Cc: Daniel Vetter 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Vivi 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |   2 +-
>  drivers/gpu/drm/i915/i915_drv.h |  19 +++-
>  drivers/gpu/drm/i915/intel_display.h|   1 +
>  drivers/gpu/drm/i915/intel_drv.h|   3 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 195 
> 
>  5 files changed, 199 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index d81cb2513069..5a7ce734de02 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2746,7 +2746,7 @@ static int i915_power_domain_info(struct seq_file *m, 
> void *unused)
>   for_each_power_domain(power_domain, power_well->domains)
>   seq_printf(m, "  %-23s %d\n",
>intel_display_power_domain_str(power_domain),
> -  power_domains->domain_use_count[power_domain]);
> +  
> atomic_read(_domains->domain_use_count[power_domain]));
>   }
>  
>   mutex_unlock(_domains->lock);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index caebd5825279..61a635f03af7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1032,6 +1032,23 @@ struct i915_power_well {
>   bool has_fuses:1;
>   } hsw;
>   };
> +
> + /* Lock to serialize access to count, hw_enabled and ops, used for
> +  * power wells that have supports_atomix_ctx set to True.
> +  */
> + spinlock_t lock;
> +
> + /* Indicates that the get/put methods for this power well can be called
> +  * in atomic contexts, requires .ops to not sleep. This is valid
> +  * only for the DC_OFF power well currently.
> +  */
> + bool supports_atomic_ctx;
> +
> + /* DC_OFF power well was disabled since the last time vblanks were
> +  * disabled.
> +  */
> + bool dc_off_disabled;
> +
>   const struct i915_power_well_ops *ops;
>  };
>  
> @@ -1045,7 +1062,7 @@ struct i915_power_domains {
>   int power_well_count;
>  
>   struct mutex lock;
> - int domain_use_count[POWER_DOMAIN_NUM];
> + atomic_t domain_use_count[POWER_DOMAIN_NUM];
>   struct i915_power_well *power_wells;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.h 
> b/drivers/gpu/drm/i915/intel_display.h
> index a0d2b6169361..3e9671ff6f79 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -172,6 +172,7 @@ enum intel_display_power_domain {
>   POWER_DOMAIN_AUX_C,
>   POWER_DOMAIN_AUX_D,
>   POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_VBLANK,

Maybe we could start a new category of atomic domains and on interations that 
makes sense go over both
or making the domains in an array with is_atomic bool in case we can transform 
the atomic get,put to
be really generic or into .enable .disable function pointers.

>   POWER_DOMAIN_MODESET,
>   POWER_DOMAIN_GT_IRQ,
>   POWER_DOMAIN_INIT,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: forward hotplug events again

[Patchwork]

== Series Details ==

Series: drm/i915: forward hotplug events again
URL   : https://patchwork.freedesktop.org/series/36054/
State : failure

== Summary ==

Series 36054v1 drm/i915: forward hotplug events again
https://patchwork.freedesktop.org/api/1.0/series/36054/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> INCOMPLETE (fi-bdw-5557u)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#104260

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:109  pass:105  dwarn:0   dfail:0   fail:0   skip:3  
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:368s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:479s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:451s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:269s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:396s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:453s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:498s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:523s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:484s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:428s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:529s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-glk-dsi   total:288  pass:178  dwarn:1   dfail:4   fail:1   skip:104 
time:347s
fi-pnv-d510 failed to collect. IGT log at Patchwork_7613/fi-pnv-d510/igt.log

3e7d28b655aefefe51f1d7ac6aba46d6ca03b658 drm-tip: 2018y-01m-04d-22h-45m-20s UTC 
integration manifest
67cf2fd0cebe drm/i915: forward hotplug events again

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7613/issues.html
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[Intel-gfx] [PATCH] drm/i915: forward hotplug events again

[Rodrigo Vivi]

As mentioned on commit '88be58be886f ("drm/i915/fbdev:
Always forward hotplug events") we have real valid cases
of hotplugs where fbdev is not fully setup yet.

Unfortunately this remove the checkpoint after the sync point.
So probably we can live without it. Or we need a more robust
serialization.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104158
Fixes: a45b30a6c5db ("drm/i915/fbdev: Serialise early hotplug events with async 
fbdev config")
Cc: Chris Wilson 
Cc: Lukas Wunner 
Cc: jrg2...@gmail.com
Cc: sta...@vger.kernel.org
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_fbdev.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c 
b/drivers/gpu/drm/i915/intel_fbdev.c
index da48af11eb6b..7a6069b389f2 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -801,8 +801,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
return;
 
intel_fbdev_sync(ifbdev);
-   if (ifbdev->vma)
-   drm_fb_helper_hotplug_event(>helper);
+   drm_fb_helper_hotplug_event(>helper);
 }
 
 void intel_fbdev_restore_mode(struct drm_device *dev)
-- 
2.13.6

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[Intel-gfx] linux-next: manual merge of the drm tree with the drm-intel-fixes tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the drm tree got a conflict in:

  drivers/gpu/drm/i915/intel_cdclk.c

between commit:

  30414f3010af ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl")

from the drm-intel-fixes tree and commit:

  2aa97491da8a ("drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL")

from the drm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/intel_cdclk.c
index 60cf4e58389a,9c5ceb98d48f..
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@@ -917,11 -994,9 +988,9 @@@ static void skl_set_cdclk(struct drm_i9
  {
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
-   u32 freq_select, pcu_ack, cdclk_ctl;
 -  u32 freq_select;
++  u32 freq_select, cdclk_ctl;
int ret;
  
-   WARN_ON((cdclk == 24000) != (vco == 0));
- 
mutex_lock(_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
@@@ -934,8 -1009,16 +1003,16 @@@
return;
}
  
 -  /* set CDCLK_CTL */
 +  /* Choose frequency for this cdclk */
switch (cdclk) {
+   default:
+   WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+   WARN_ON(vco != 0);
+   /* fall through */
+   case 308571:
+   case 337500:
+   freq_select = CDCLK_FREQ_337_308;
+   break;
case 45:
case 432000:
freq_select = CDCLK_FREQ_450_432;
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: DMC 1.07 for Cannonlake (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: DMC 1.07 for Cannonlake (rev5)
URL   : https://patchwork.freedesktop.org/series/35651/
State : success

== Summary ==

Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
incomplete -> PASS   (shard-hsw) fdo#103540 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-cur-indfb-onoff:
skip   -> PASS   (shard-snb)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2679 pass:1513 dwarn:1   dfail:0   fail:10  skip:1154 
time:8747s
shard-snbtotal:2713 pass:1310 dwarn:1   dfail:0   fail:11  skip:1391 
time:7871s
Blacklisted hosts:
shard-apltotal:2713 pass:1686 dwarn:1   dfail:0   fail:24  skip:1001 
time:13357s
shard-kbltotal:2695 pass:1788 dwarn:1   dfail:0   fail:27  skip:878 
time:10277s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7612/shards.html
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Re: [Intel-gfx] [PATCH] drm/dp: Power cycle display if LINK_ADDRESS fails.

[Pandiyan, Dhinakaran]

On Thu, 2018-01-04 at 23:46 +, Pandiyan, Dhinakaran wrote:
> On Thu, 2018-01-04 at 18:21 -0500, Lyude Paul wrote:
> > Sorry for the late reply, I've been having very similar issues on my own 
> > MST hub
> > and I wanted to make sure that they were the same issue, although it seems 
> > like
> > they aren't.
> > 
> > So; I've been doing a lot of MST debugging this week and last and something 
> > I've
> > discovered needs to be taken into account sometimes with MST hubs is the 
> > actual
> > state that they're in at the point that the DRM driver detects them. I've
> > managed to on multiple occasions, get my hub into a weird state by:
> > 
> > - Plugging in MST displays into the hub
> > - Turning on the machine
> > - Unplugging MST displays from the hub (while still in the BIOS)
> > - Booting into linux
> > - Plugging MST displays into the hub
> > - Everything times out, the world explodes, the economy collapses, etc.
> > 
> > I think maybe, especially since this should be perfectly valid behavior and 
> > not
> > break well or poor behaving hubs, we should do a power cycle with the 
> > display
> > like this when the DP port initially detects an MST hub and before we start
> > doing any serious communication with it. Could you see if this fixes your 
> > issue
> > instead of the patch you've got here?
> > 
> 
> Well, my reasoning to power cycle after a failure was to not affect hubs
> that work. Besides that I also saw an odd cycle of timeouts and late
> replies when I did this.
> 
> 1. Detect hub
> 2. Toggle power state and send LINK_ADDRESS req.
> 3. LINK_ADDRESS req times out.
> 4. Toggle power state and send LINK_ADDRESS req.
> 5. Get late response for the first (and expired) LINK_ADDRESS req.
> 6. Go to step 3
> 
> It seems like toggling the power states flushes out some message buffers
> in the MST hub.
> 
> But, in the retry approach, power cycling resulted in getting the
> response for the current LINK_ADDRESS request along with the previous
> one that timed out.
> 
> I could not come up with an explanation for all the behavior. So, I
> decided to get back to this later.
> 
> 
> > As well, mind attaching your full dmesg with drm.debug=0x6?
> 
> I don't have the old logs anymore, will try to get something for you.
Here you go

Setup: Laptop -> ThinkPad dock -> Dell MST monitor -> Dell monitor
Hotplugged display to dock[passed] - https://pastebin.com/CemRGsCb
Connected boot[failed] - https://pastebin.com/jjXP6HzB

> 
> -DK
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Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Rodrigo Vivi]

On Thu, Jan 04, 2018 at 11:39:23PM +, Kenneth Graunke wrote:
> On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
> > Quoting Kenneth Graunke (2018-01-04 19:38:05)
> > > Geminilake requires the 3D driver to select whether barriers are
> > > intended for compute shaders, or tessellation control shaders, by
> > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > > switching pipelines.  Failure to do this properly can result in GPU
> > > hangs.
> > > 
> > > Unfortunately, this means it needs to switch mid-batch, so only
> > > userspace can properly set it.  To facilitate this, the kernel needs
> > > to whitelist the register.
> > > 
> > > Signed-off-by: Kenneth Graunke 
> > > Cc: sta...@vger.kernel.org
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h| 2 ++
> > >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
> > >  2 files changed, 7 insertions(+)
> > > 
> > > Hello,
> > > 
> > > We unfortunately need to whitelist an extra register for GPU hang fix
> > > on Geminilake.  Here's the corresponding Mesa patch:
> > 
> > Thankfully it appears to be context saved. Has a w/a name been assigned
> > for this?
> > -Chris
> 
> There doesn't appear to be one.  The workaround page lists it, but there
> is no name.  The register description has a note saying that you need to
> set this, but doesn't call it out as a workaround.

It mentions only BXT:ALL, but not mention to GLK.

Should we add to both then?

> 
> That's why I put a generic comment, rather than the name.

On Display side we started using the row name for this case, to help
easily finding this later.

ex: "Display WA #0390: skl,kbl"

The number for this apparently is:
WA #0862

Maybe we could use this one to start
/* GT WA #0862: bxt,glk */

GT? GEM?
Unnamed WA #0862?


Thanks,
Rodrigo.

> 
> --Ken



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Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake

[Rodrigo Vivi]

On Thu, Jan 04, 2018 at 11:51:42PM +, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" 
> 
> There is a new version of DMC available for CNL.
> 
> The release notes mentions:
> 1. Fix for the issue where DC_STATE was getting enabled
> even when disabled by driver causing data corruption
> 
> v2: Since the firmware is  merged to linux-firmware.git,
> add MODULE_FIRMWARE.
> 
> v3: rebased. Correct commit message(Jani)
> 
> Cc: Jani Saarinen 
> Cc: Rodrigo Vivi 
> Signed-off-by: Anusha Srivatsa 
> Reviewed-by: Rodrigo Vivi 

merged, thanks!

> ---
>  drivers/gpu/drm/i915/intel_csr.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c 
> b/drivers/gpu/drm/i915/intel_csr.c
> index 7fe4aac0..41e6c75 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -37,8 +37,9 @@
>  #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
>  #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>  
> -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin"
> -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6)
> +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
> +MODULE_FIRMWARE(I915_CSR_CNL);
> +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>  
>  #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
>  MODULE_FIRMWARE(I915_CSR_KBL);
> -- 
> 2.7.4
> 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: DMC 1.07 for Cannonlake (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: DMC 1.07 for Cannonlake (rev5)
URL   : https://patchwork.freedesktop.org/series/35651/
State : success

== Summary ==

Series 35651v5 drm/i915/dmc: DMC 1.07 for Cannonlake
https://patchwork.freedesktop.org/api/1.0/series/35651/revisions/5/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +1
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:431s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:369s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:479s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:274s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:462s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:450s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:261s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:516s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:389s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:407s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:419s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:463s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:567s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:502s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:523s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:518s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

3e7d28b655aefefe51f1d7ac6aba46d6ca03b658 drm-tip: 2018y-01m-04d-22h-45m-20s UTC 
integration manifest
c9059885aea8 drm/i915/dmc: DMC 1.07 for Cannonlake

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7612/issues.html
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[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake

[Anusha Srivatsa]

From: "Srivatsa, Anusha" 

There is a new version of DMC available for CNL.

The release notes mentions:
1. Fix for the issue where DC_STATE was getting enabled
even when disabled by driver causing data corruption

v2: Since the firmware is  merged to linux-firmware.git,
add MODULE_FIRMWARE.

v3: rebased. Correct commit message(Jani)

Cc: Jani Saarinen 
Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_csr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 7fe4aac0..41e6c75 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -37,8 +37,9 @@
 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
 #define GLK_CSR_VERSION_REQUIRED   CSR_VERSION(1, 4)
 
-#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin"
-#define CNL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 6)
+#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
+MODULE_FIRMWARE(I915_CSR_CNL);
+#define CNL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 7)
 
 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
 MODULE_FIRMWARE(I915_CSR_KBL);
-- 
2.7.4

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Re: [Intel-gfx] [PATCH] drm/dp: Power cycle display if LINK_ADDRESS fails.

[Pandiyan, Dhinakaran]

On Thu, 2018-01-04 at 18:21 -0500, Lyude Paul wrote:
> Sorry for the late reply, I've been having very similar issues on my own MST 
> hub
> and I wanted to make sure that they were the same issue, although it seems 
> like
> they aren't.
> 
> So; I've been doing a lot of MST debugging this week and last and something 
> I've
> discovered needs to be taken into account sometimes with MST hubs is the 
> actual
> state that they're in at the point that the DRM driver detects them. I've
> managed to on multiple occasions, get my hub into a weird state by:
> 
> - Plugging in MST displays into the hub
> - Turning on the machine
> - Unplugging MST displays from the hub (while still in the BIOS)
> - Booting into linux
> - Plugging MST displays into the hub
> - Everything times out, the world explodes, the economy collapses, etc.
> 
> I think maybe, especially since this should be perfectly valid behavior and 
> not
> break well or poor behaving hubs, we should do a power cycle with the display
> like this when the DP port initially detects an MST hub and before we start
> doing any serious communication with it. Could you see if this fixes your 
> issue
> instead of the patch you've got here?
> 

Well, my reasoning to power cycle after a failure was to not affect hubs
that work. Besides that I also saw an odd cycle of timeouts and late
replies when I did this.

1. Detect hub
2. Toggle power state and send LINK_ADDRESS req.
3. LINK_ADDRESS req times out.
4. Toggle power state and send LINK_ADDRESS req.
5. Get late response for the first (and expired) LINK_ADDRESS req.
6. Go to step 3

It seems like toggling the power states flushes out some message buffers
in the MST hub.

But, in the retry approach, power cycling resulted in getting the
response for the current LINK_ADDRESS request along with the previous
one that timed out.

I could not come up with an explanation for all the behavior. So, I
decided to get back to this later.


> As well, mind attaching your full dmesg with drm.debug=0x6?

I don't have the old logs anymore, will try to get something for you.

-DK
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Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Kenneth Graunke]

On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-01-04 19:38:05)
> > Geminilake requires the 3D driver to select whether barriers are
> > intended for compute shaders, or tessellation control shaders, by
> > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > switching pipelines.  Failure to do this properly can result in GPU
> > hangs.
> > 
> > Unfortunately, this means it needs to switch mid-batch, so only
> > userspace can properly set it.  To facilitate this, the kernel needs
> > to whitelist the register.
> > 
> > Signed-off-by: Kenneth Graunke 
> > Cc: sta...@vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h| 2 ++
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
> >  2 files changed, 7 insertions(+)
> > 
> > Hello,
> > 
> > We unfortunately need to whitelist an extra register for GPU hang fix
> > on Geminilake.  Here's the corresponding Mesa patch:
> 
> Thankfully it appears to be context saved. Has a w/a name been assigned
> for this?
> -Chris

There doesn't appear to be one.  The workaround page lists it, but there
is no name.  The register description has a note saying that you need to
set this, but doesn't call it out as a workaround.

That's why I put a generic comment, rather than the name.

--Ken


signature.asc
Description: This is a digitally signed message part.
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Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake

[Srivatsa, Anusha]

>-Original Message-
>From: Saarinen, Jani
>Sent: Wednesday, January 3, 2018 11:52 PM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Cc: Vivi, Rodrigo 
>Subject: RE: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
>
>HI,
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> Behalf Of Anusha Srivatsa
>> Sent: keskiviikko 3. tammikuuta 2018 23.22
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Vivi, Rodrigo 
>> Subject: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
>>
>> There is a new version of DMC available for CNL.
>>
>> The release notes mentions:
>> 1. Fix for the issue where DC_STATE was getting enabled even when
>> disabled by driver causing data corruption
>>
>> v2: Since the firmware is  merged to linux-firmware.git, add
>> MODUE_FIRMWARE.
>Minor typo s/MODUE_/MODULE_

Thanks for noticing Jani.

Anusha 
>> Cc: Rodrigo Vivi 
>> Signed-off-by: Anusha Srivatsa 
>> Reviewed-by: Rodrigo Vivi 
>> ---
>>  drivers/gpu/drm/i915/intel_csr.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> b/drivers/gpu/drm/i915/intel_csr.c
>> index f417101..0d7b3b6 100644
>> --- a/drivers/gpu/drm/i915/intel_csr.c
>> +++ b/drivers/gpu/drm/i915/intel_csr.c
>> @@ -37,8 +37,9 @@
>>  #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
>>  #define GLK_CSR_VERSION_REQUIREDCSR_VERSION(1, 4)
>>
>> -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin"
>> -#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 6)
>> +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
>> +MODULE_FIRMWARE(I915_CSR_CNL);
>> +#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 7)
>>
>>  #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
>>  MODULE_FIRMWARE(I915_CSR_KBL);
>> --
>> 2.7.4
>>
>
>Br,
>
>Jani Saarinen
>Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
>

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Re: [Intel-gfx] [PATCH i-g-t 1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Pandiyan, Dhinakaran]

Including a line about the atomic update failure in the commit message
would be nice.

Reviewed-by: Dhinakaran Pandiyan 

On Thu, 2018-01-04 at 16:07 +0200, Marta Lofstedt wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260
> 
> Signed-off-by: Marta Lofstedt 
> ---
>  tests/kms_psr_sink_crc.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
> index 83a69f0b..26cf434a 100644
> --- a/tests/kms_psr_sink_crc.c
> +++ b/tests/kms_psr_sink_crc.c
> @@ -532,11 +532,13 @@ int main(int argc, char *argv[])
>   igt_subtest("psr_basic") {
>   setup_test_plane();
>   igt_assert(wait_psr_entry());
> + test_cleanup();
>   }
>  
>   igt_subtest("psr_drrs") {
>   setup_test_plane();
>   igt_assert(drrs_disabled());
> + test_cleanup();
>   }
>  
>   for (op = PAGE_FLIP; op <= RENDER; op++) {
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Re: [Intel-gfx] [PATCH] drm/dp: Power cycle display if LINK_ADDRESS fails.

[Lyude Paul]

Sorry for the late reply, I've been having very similar issues on my own MST hub
and I wanted to make sure that they were the same issue, although it seems like
they aren't.

So; I've been doing a lot of MST debugging this week and last and something I've
discovered needs to be taken into account sometimes with MST hubs is the actual
state that they're in at the point that the DRM driver detects them. I've
managed to on multiple occasions, get my hub into a weird state by:

- Plugging in MST displays into the hub
- Turning on the machine
- Unplugging MST displays from the hub (while still in the BIOS)
- Booting into linux
- Plugging MST displays into the hub
- Everything times out, the world explodes, the economy collapses, etc.

I think maybe, especially since this should be perfectly valid behavior and not
break well or poor behaving hubs, we should do a power cycle with the display
like this when the DP port initially detects an MST hub and before we start
doing any serious communication with it. Could you see if this fixes your issue
instead of the patch you've got here?

As well, mind attaching your full dmesg with drm.debug=0x6?

On Wed, 2017-12-20 at 22:36 -0800, Dhinakaran Pandiyan wrote:
> Occasionally there are LINK_ADDRESS sideband messages timing out with the
> Lenovo MST dock + Dell MST monitor(w/ in-built branch) setup I have. These
> failures lead to the display not coming up on boot. Power cycling the port
> corresponding to the MST monitor's branch device and resending the message
> fixes the issue. I am not entirely sure if this is specific to my setup.
> However, as the power state is toggled conditionally on LINK_ADDRESS
> timeouts, this should not affect the working cases.
> 
> Cc: Lyude 
> Cc: Dave Airlie 
> Cc: Jani Nikula 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 13 +++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 70dcfa58d3c2..e06defcdcf18 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -1596,8 +1596,9 @@ static void drm_dp_send_link_address(struct
> drm_dp_mst_topology_mgr *mgr,
>   int len;
>   struct drm_dp_sideband_msg_tx *txmsg;
>   int ret;
> + int attempts = 5;
>  
> - txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
> +retry:   txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
>   if (!txmsg)
>   return;
>  
> @@ -1635,9 +1636,17 @@ static void drm_dp_send_link_address(struct
> drm_dp_mst_topology_mgr *mgr,
>   }
>   (*mgr->cbs->hotplug)(mgr);
>   }
> + } else if (attempts--) {
> + kfree(txmsg);
> + drm_dp_send_power_updown_phy(mstb->mgr, mstb->port_parent,
> +  false);
> + drm_dp_send_power_updown_phy(mstb->mgr, mstb->port_parent,
> +  true);
> + DRM_DEBUG_KMS("link address failed %d, retrying\n", ret);
> + goto retry;
>   } else {
>   mstb->link_address_sent = false;
> - DRM_DEBUG_KMS("link address failed %d\n", ret);
> + DRM_DEBUG_KMS("link address failed %d, giving up\n", ret);
>   }
>  
>   kfree(txmsg);
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Re: [Intel-gfx] Review https://patchwork.freedesktop.org/patch/160274/

[Pandiyan, Dhinakaran]

On Thu, 2018-01-04 at 06:36 +, Mustaffa, Mustamin B wrote:
> Hi all, 
> 
>  
> 
> Please help to review a patch
> https://patchwork.freedesktop.org/patch/160274/
> 
>  

That patch is several months old now, please resubmit the patch to the
mailing list. I see that there were comments from Jani and Imre on your
patch, so Cc them too.

Also provide information about what changed since the patch was
submitted last time.

-DK

> 
> Best regard 
> 
>  
> 
> Mustamin
> 
>  
> 
> 
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[Intel-gfx] ✗ Fi.CI.IGT: failure for meson: use message() rather than warning()

[Patchwork]

== Series Details ==

Series: meson: use message() rather than warning()
URL   : https://patchwork.freedesktop.org/series/36040/
State : failure

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623 +3
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#103167
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
pass   -> INCOMPLETE (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup modeset-vs-vblank-race:
dmesg-warn -> PASS   (shard-hsw) fdo#103060
Subgroup rcs-wf_vblank-vs-dpms:
pass   -> DMESG-WARN (shard-hsw) fdo#102614
Test gem_exec_whisper:
Subgroup normal:
pass   -> FAIL   (shard-hsw)

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2617 pass:1477 dwarn:2   dfail:0   fail:10  skip:1127 
time:8291s
shard-snbtotal:2713 pass:1311 dwarn:1   dfail:0   fail:10  skip:1391 
time:7877s
Blacklisted hosts:
shard-apltotal:2713 pass:1685 dwarn:1   dfail:0   fail:26  skip:1001 
time:13456s
shard-kbltotal:2637 pass:1725 dwarn:26  dfail:2   fail:28  skip:856 
time:10197s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_747/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK

[Rodrigo Vivi]

On Wed, Jan 03, 2018 at 07:03:45PM +, Anusha Srivatsa wrote:
> Since the firmwares are not yet released to public repo,
> disable them on Geminilake.
> 
> v2: Remove the firmware versions (Michal)
> 
> v3: Remove unwanted defines (Rodrigo)
> Correct commit message (Michal)
> 
> Cc: Michal Wajdeczko 
> Cc: Rodrigo Vivi 
> Cc: 
> Signed-off-by: Anusha Srivatsa 
> Fixes: 90f192c8241e ("drm/i915/GuC/GLK: Load GuC on GLK")
> Fixes: db5ba0d8931e ("drm/i915/GLK/HuC: Load HuC on GLK")
> Reviewed-by: Michal Wajdeczko 

Now merged. Thanks for the patch.

> ---
>  drivers/gpu/drm/i915/intel_guc_fw.c |  9 -
>  drivers/gpu/drm/i915/intel_huc.c| 11 ---
>  2 files changed, 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
> b/drivers/gpu/drm/i915/intel_guc_fw.c
> index cbc51c9..3b09329 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -39,9 +39,6 @@
>  #define KBL_FW_MAJOR 9
>  #define KBL_FW_MINOR 39
>  
> -#define GLK_FW_MAJOR 10
> -#define GLK_FW_MINOR 56
> -
>  #define GUC_FW_PATH(platform, major, minor) \
> "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" 
> __stringify(minor) ".bin"
>  
> @@ -54,8 +51,6 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>  #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
>  MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>  
> -#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
> -
>  static void guc_fw_select(struct intel_uc_fw *guc_fw)
>  {
>   struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
> @@ -82,10 +77,6 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
>   guc_fw->path = I915_KBL_GUC_UCODE;
>   guc_fw->major_ver_wanted = KBL_FW_MAJOR;
>   guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> - } else if (IS_GEMINILAKE(dev_priv)) {
> - guc_fw->path = I915_GLK_GUC_UCODE;
> - guc_fw->major_ver_wanted = GLK_FW_MAJOR;
> - guc_fw->minor_ver_wanted = GLK_FW_MINOR;
>   } else {
>   DRM_WARN("%s: No firmware known for this platform!\n",
>intel_uc_fw_type_repr(guc_fw->type));
> diff --git a/drivers/gpu/drm/i915/intel_huc.c 
> b/drivers/gpu/drm/i915/intel_huc.c
> index 974be3d..8ed0518 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -54,10 +54,6 @@
>  #define KBL_HUC_FW_MINOR 00
>  #define KBL_BLD_NUM 1810
>  
> -#define GLK_HUC_FW_MAJOR 02
> -#define GLK_HUC_FW_MINOR 00
> -#define GLK_BLD_NUM 1748
> -
>  #define HUC_FW_PATH(platform, major, minor, bld_num) \
>   "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>   __stringify(minor) "_" __stringify(bld_num) ".bin"
> @@ -74,9 +70,6 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
>   KBL_HUC_FW_MINOR, KBL_BLD_NUM)
>  MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
>  
> -#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
> - GLK_HUC_FW_MINOR, GLK_BLD_NUM)
> -
>  static void huc_fw_select(struct intel_uc_fw *huc_fw)
>  {
>   struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
> @@ -103,10 +96,6 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
>   huc_fw->path = I915_KBL_HUC_UCODE;
>   huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
>   huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
> - } else if (IS_GEMINILAKE(dev_priv)) {
> - huc_fw->path = I915_GLK_HUC_UCODE;
> - huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
> - huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
>   } else {
>   DRM_WARN("%s: No firmware known for this platform!\n",
>intel_uc_fw_type_repr(huc_fw->type));
> -- 
> 2.7.4
> 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: DMC 1.07 for Cannonlake (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: DMC 1.07 for Cannonlake (rev4)
URL   : https://patchwork.freedesktop.org/series/35651/
State : failure

== Summary ==

Applying: drm/i915/dmc: DMC 1.07 for Cannonlake
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_csr.c).
error: could not build fake ancestor
Patch failed at 0001 drm/i915/dmc: DMC 1.07 for Cannonlake
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Rename some shorthand lock classes

[Patchwork]

== Series Details ==

Series: drm/i915: Rename some shorthand lock classes
URL   : https://patchwork.freedesktop.org/series/36047/
State : success

== Summary ==

Series 36047v1 drm/i915: Rename some shorthand lock classes
https://patchwork.freedesktop.org/api/1.0/series/36047/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bdw-5557u) fdo#104162
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:367s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:483s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:447s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:259s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:573s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:531s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y total:218  pass:197  dwarn:0   dfail:0   fail:0   skip:20 
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

8ed3b7257f4b193f702d8c3db3be40494dc6283c drm-tip: 2018y-01m-04d-20h-11m-09s UTC 
integration manifest
7f18a02accd3 drm/i915: Rename some shorthand lock classes

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7610/issues.html
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Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

[Yaodong Li]

On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote:
Since ring frequency programming needs consideration of both IA and GT 
frequency requests I think keeping the logic
to program the ring frequency table in driver that monitors both IA/GT 
busyness and power budgets like intel_ips
will be more appropriate. intel_ips is relying on global load derived 
from all CPUs.
I understand that power awareness and busyness based policy might be 
trickier but having that as tunable will give better flexibility.


By just looking into the current code, the way intel_ips checks gpu 
busyness cannot reflect the actual workload of GT
(e.g. gpu busy is true even if there's only one pending request), in 
this case, we shall not increase the ring freq if we
want to use a "workload monitoring" based solution. so we need a more 
accurate way to monitor the current GT workload

(e.g.  when the pending request count reaches a center tunable threshold??).


On 1/3/2018 11:51 PM, Yaodong Li wrote:


You are thinking of plugging into intel_pstate to make it smarter 
for ia freq transitions?
Yep. This seems a correct step to give some automatic support 
instead of parameter/hardcoded multiplier.


Does this mean we should use cpufreq/intel_pstate based approach 
instead of the current modparam solution for Gen9?


Some concerns and questions about intel_pstate approach:
a) Currently, we cannot get the accurate pstate/target freq value 
from cpufreq in intel_pstate active mode since
 these values won't be exported to cpufreq layer, so if we won't 
change intel_pstate code then we only can get

 the max cpu freq of a new policy.
b) intel_pstate policy is attached to each logic cpu, which means we 
will receive policy/freq transition notification
    for each logic cpu freq change. One question is how we are going 
to decide the freq of the ring? just use the max

    cpu freq reported?
c) With the intel_pstate approach we may still run into thermal 
throttling, in this case, can a certain cooling device

    be triggered to lower the cpu freq?

Thanks and Regards,
-Jackie





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Re: [Intel-gfx] [PATCH] drm: i915: Fix audio issue on BXT

[Pandiyan, Dhinakaran]

+Art

On Thu, 2018-01-04 at 22:13 +0530, Singh, Gaurav K wrote:
> 
> On 1/4/2018 2:48 AM, Rodrigo Vivi wrote:
> > On Wed, Jan 03, 2018 at 08:31:10PM +, Pandiyan, Dhinakaran wrote:
> >> On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:
> >>> From: Gaurav Singh 
> >>>
> >>> On Apollolake, with stress test warm reboot, audio card
> >>> was not getting enumerated after reboot. This was a
> >> The problem looks similar to
> >> https://lists.freedesktop.org/archives/intel-gfx/2017-October/144495.html
> >>
> >> although the proposed solutions are vastly different. I have Cc'd some
> >> more people.
> >>
> >>> spurious issue happening on Apollolake. HW codec and
> >>> HD audio controller link was going out of sync for which
> >>> there was a fix in i915 driver but was not getting invoked
> >>> for BXT. Extending this fix to BXT as well.
> >>>
> >>> Tested on apollolake chromebook by stress test warm reboot
> >>> with 2500 iterations.
> >>>
> >>> Signed-off-by: Gaurav K Singh 
> >>> ---
> >>>   drivers/gpu/drm/i915/intel_audio.c | 2 +-
> >>>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> >>> b/drivers/gpu/drm/i915/intel_audio.c
> >>> index f1502a0188eb..c71c04e1c3f6 100644
> >>> --- a/drivers/gpu/drm/i915/intel_audio.c
> >>> +++ b/drivers/gpu/drm/i915/intel_audio.c
> >>> @@ -729,7 +729,7 @@ static void 
> >>> i915_audio_component_codec_wake_override(struct device *kdev,
> >>>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> >>>   u32 tmp;
> >>>   
> >>> - if (!IS_GEN9_BC(dev_priv))
> >>> + if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
> >> IS_GEN9()? GLK might need this too.
> > I think this is applicable for all Gen9 platforms.
> 
> > if GLK need there is the possibility of CNL also needing it...
> > So not sure where to stop.
> >
> > Also looking to the original patch that introduced this function,
> > commit '632f3ab95fe2 ("drm/i915/audio: add codec wakeup override
> > enabled/disable callback")'
> >
> > it tells that the reason was:
> > "In SKL, HDMI/DP codec and PCH HD Audio Controller are in different p$
> > wells, so it's necessary to reset display audio codecs when power we$
> > otherwise display audio codecs will disappear when resume from low p$
> > state."
> >
> > Is this the case here on BXT?
> Yes, its the same case with BXT.
> >
> > Another interesting thing I noticed on Spec when searching for this bit
> > was that this bit is related to an workaround on SKL/KBL/CFL... no mention
> > to BXT.
> >
> > "This workaround is needed for an HW issue in SKL and KBL in which HW codec
> > and HD audio controller link was going out of sync."
> Yes, in Bspec it has been mentioned only for SKL and KBL. But without 
> this fix, sound card was not getting enumerated for BXT.


Art,

Can you please help us here? To summarize, the question is what
platforms need the AUD_CHICKENBIT_REG:15 bit to be set to avoid code
enumeration failures?

-DK

> >
> > Thanks,
> > Rodrigo.
> >
> >>
> >>>   return;
> >>>   
> >>>   i915_audio_component_get_power(kdev);
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Patchwork]

== Series Details ==

Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
URL   : https://patchwork.freedesktop.org/series/36039/
State : warning

== Summary ==

Test kms_flip:
Subgroup vblank-vs-modeset-suspend-interruptible:
pass   -> SKIP   (shard-snb)
Subgroup flip-vs-modeset-vs-hang-interruptible:
dmesg-warn -> PASS   (shard-snb) fdo#104311
Subgroup nonexisting-fb:
pass   -> SKIP   (shard-hsw)
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#103167 +1
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-crc-atomic:
pass   -> SKIP   (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-left-edge:
pass   -> SKIP   (shard-hsw)
Subgroup pipe-c-128x128-bottom-edge:
pass   -> SKIP   (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
incomplete -> PASS   (shard-hsw) fdo#103375

fdo#104311 https://bugs.freedesktop.org/show_bug.cgi?id=104311
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2636 pass:1486 dwarn:1   dfail:0   fail:10  skip:1139 
time:8647s
shard-snbtotal:2713 pass:1309 dwarn:1   dfail:0   fail:11  skip:1392 
time:7744s
Blacklisted hosts:
shard-apltotal:2713 pass:1686 dwarn:1   dfail:0   fail:25  skip:1001 
time:13296s
shard-kbltotal:2713 pass:1804 dwarn:1   dfail:0   fail:30  skip:878 
time:10383s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7609/shards.html
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable vblanks after verifying power domain states.

[Pandiyan, Dhinakaran]

On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
> Wouldn't it be better to make intel_power_domains_verify_state work
> correctly with the vblank irq?

I tried to :) Since I changed the domain_use_count to atomic_t and moved
it outside of the locks, verify_state became racy. Let me take another
look.

-DK
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Re: [Intel-gfx] [PATCH] drm/i915: Rename some shorthand lock classes

[Chris Wilson]

Quoting Chris Wilson (2018-01-04 21:45:28)
> +#define lockdep_rename(lock, name) \
> +   lockdep_set_class_and_name(lock, (lock)->dep_map.key, name)

Maybe lockdep_set_name() for similarity to the others.
-Chris
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[Intel-gfx] [PATCH] drm/i915: Rename some shorthand lock classes

[Chris Wilson]

By default, lockdep takes the stringified variable as the name for the
lock class. Quite often, these are constructed from local variables that
are chosen for their brevity resulting in less than distinct class
names. Rename some of the worst offenders encountered in recent reports.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 drivers/gpu/drm/i915/i915_gem_request.c | 2 ++
 drivers/gpu/drm/i915/i915_gem_timeline.c| 4 ++--
 drivers/gpu/drm/i915/i915_gem_userptr.c | 2 ++
 drivers/gpu/drm/i915/i915_utils.h   | 3 +++
 drivers/gpu/drm/i915/intel_breadcrumbs.c| 3 +++
 drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
 7 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ba9f67c256f4..0276ac53dff1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4459,6 +4459,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
  const struct drm_i915_gem_object_ops *ops)
 {
mutex_init(>mm.lock);
+   lockdep_rename(>mm.lock, "i915_gem_object->mm");
 
INIT_LIST_HEAD(>vma_list);
INIT_LIST_HEAD(>lut_list);
@@ -4475,6 +4476,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
obj->mm.madv = I915_MADV_WILLNEED;
INIT_RADIX_TREE(>mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(>mm.get_page.lock);
+   lockdep_rename(>mm.get_page.lock, "i915_gem_object->mm.get_page");
 
i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 72bdc203716f..2b25652517be 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -707,6 +707,8 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
GEM_BUG_ON(req->timeline == engine->timeline);
 
spin_lock_init(>lock);
+   lockdep_rename(>lock, "i915_request");
+
dma_fence_init(>fence,
   _fence_ops,
   >lock,
diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c 
b/drivers/gpu/drm/i915/i915_gem_timeline.c
index e9fd87604067..82da881e52ae 100644
--- a/drivers/gpu/drm/i915/i915_gem_timeline.c
+++ b/drivers/gpu/drm/i915/i915_gem_timeline.c
@@ -90,7 +90,7 @@ int i915_gem_timeline_init(struct drm_i915_private *i915,
static struct lock_class_key class;
 
return __i915_gem_timeline_init(i915, timeline, name,
-   , ">lock");
+   , "i915_user_timeline");
 }
 
 int i915_gem_timeline_init__global(struct drm_i915_private *i915)
@@ -100,7 +100,7 @@ int i915_gem_timeline_init__global(struct drm_i915_private 
*i915)
return __i915_gem_timeline_init(i915,
>gt.global_timeline,
"[execution]",
-   , "_timeline->lock");
+   , "i915_global_timeline");
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 382a77a1097e..23b31b588830 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -170,6 +170,8 @@ i915_mmu_notifier_create(struct mm_struct *mm)
return ERR_PTR(-ENOMEM);
 
spin_lock_init(>lock);
+   lockdep_rename(>lock, "i915_mmu_notifier");
+
mn->mn.ops = _gem_userptr_notifier;
mn->objects = RB_ROOT_CACHED;
mn->wq = alloc_workqueue("i915-userptr-release",
diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index 51dbfe5bb418..18219f1fd98e 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -118,6 +118,9 @@ static inline u64 ptr_to_u64(const void *ptr)
__idx;  \
 })
 
+#define lockdep_rename(lock, name) \
+   lockdep_set_class_and_name(lock, (lock)->dep_map.key, name)
+
 #include 
 
 static inline void __list_del_many(struct list_head *head,
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 86acac010bb8..ede7879c25f6 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -843,7 +843,10 @@ int intel_engine_init_breadcrumbs(struct intel_engine_cs 
*engine)
struct task_struct *tsk;
 
spin_lock_init(>rb_lock);
+   lockdep_rename(>rb_lock, "intel_breadcrumbs->rb");
+
spin_lock_init(>irq_lock);
+   lockdep_rename(>irq_lock, "intel_breadcrumbs->irq");
 
timer_setup(>fake_irq, intel_breadcrumbs_fake_irq, 0);
timer_setup(>hangcheck, intel_breadcrumbs_hangcheck, 0);
diff 

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable vblanks after verifying power domain states.

[Pandiyan, Dhinakaran]

On Wed, 2018-01-03 at 20:57 +, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-01-03 20:39:59)
> > Since we want to allow for a non-blocking power domain for vblanks,
> > the power domain use count and power well use count will not be updated
> > atomically inside the power domain mutex (see next patch). This affects
> > verifying if sum(power_domain_use_count) == power_well_use_count at
> > init time. So do not enable vblanks until this verification is done.
> > 
> > Cc: Daniel Vetter 
> > Cc: Ville Syrjälä 
> > Cc: Rodrigo Vivi 
> > Cc: Maarten Lankhorst 
> > Signed-off-by: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 24 
> >  1 file changed, 20 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 0cd355978ab4..7bc874b8dac7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -14739,6 +14739,24 @@ static bool has_pch_trancoder(struct 
> > drm_i915_private *dev_priv,
> > (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
> >  }
> >  
> > +static void modeset_enable_vblanks(struct drm_i915_private *dev_priv)
> > +{
> > +   enum pipe pipe;
> > +
> > +   for_each_pipe(dev_priv, pipe) {
> 
> for_each_intel_crtc()
> -Chris



Thanks for you comments, I'll fix them up in the next version if the
overall approach (disabling DC off) is Acked.
-DK



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Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Chris Wilson]

Quoting Kenneth Graunke (2018-01-04 19:38:05)
> Geminilake requires the 3D driver to select whether barriers are
> intended for compute shaders, or tessellation control shaders, by
> whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> switching pipelines.  Failure to do this properly can result in GPU
> hangs.
> 
> Unfortunately, this means it needs to switch mid-batch, so only
> userspace can properly set it.  To facilitate this, the kernel needs
> to whitelist the register.
> 
> Signed-off-by: Kenneth Graunke 
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/i915_reg.h| 2 ++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
>  2 files changed, 7 insertions(+)
> 
> Hello,
> 
> We unfortunately need to whitelist an extra register for GPU hang fix
> on Geminilake.  Here's the corresponding Mesa patch:

Thankfully it appears to be context saved. Has a w/a name been assigned
for this?
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] meson: use message() rather than warning()

[Rhys Kidd]

On 4 January 2018 at 15:29, Lucas De Marchi 
wrote:

> warning() was only added to the meson interpreter in 0.44 which is
> currently the last version. Let's use message() as we are currently
> requiring meson > 0.40. Otherwise we get the following error:
>
> Meson encountered an error in file overlay/meson.build, line 62,
> column 1:
> Unknown function "warning".
>
> Fixes: 865a47ca ("overlay: parse tracepoints from sysfs to figure out
> fields' location")
> Signed-off-by: Lucas De Marchi 
>

Reviewed-by: Rhys Kidd 


> Cc: Rhys Kidd 
> Cc: Daniel Vetter 
> Cc: Petri Latvala 
> ---
>  overlay/meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/overlay/meson.build b/overlay/meson.build
> index 8b5c52b4..546c8377 100644
> --- a/overlay/meson.build
> +++ b/overlay/meson.build
> @@ -59,7 +59,7 @@ if leg.found()
> command: [leg, '-P', '-o', '@OUTPUT@', '@INPUT@'])
> gpu_overlay_src += leg_file
>  else
> -   warning('leg command not found, disabling overlay; try : apt-get
> install peg')
> +   message('WARNING: leg command not found, disabling overlay; try :
> apt-get install peg')
>  endif
>
>  if leg.found() and xrandr.found() and cairo.found()
> --
> 2.14.3
>
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for meson: use message() rather than warning()

[Patchwork]

== Series Details ==

Series: meson: use message() rather than warning()
URL   : https://patchwork.freedesktop.org/series/36040/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3602
8ed3b7257f4b drm-tip: 2018y-01m-04d-20h-11m-09s UTC integration manifest

No testlist changes.

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_busy:
Subgroup basic-flip-a:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bdw-5557u) fdo#104162

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:481s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-elk-e7500 total:224  pass:169  dwarn:9   dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:267s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:509s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:468s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:582s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:405s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_747/issues.html
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[Intel-gfx] [PATCH i-g-t] meson: use message() rather than warning()

[Lucas De Marchi]

warning() was only added to the meson interpreter in 0.44 which is
currently the last version. Let's use message() as we are currently
requiring meson > 0.40. Otherwise we get the following error:

Meson encountered an error in file overlay/meson.build, line 62, column 
1:
Unknown function "warning".

Fixes: 865a47ca ("overlay: parse tracepoints from sysfs to figure out fields' 
location")
Signed-off-by: Lucas De Marchi 
Cc: Rhys Kidd 
Cc: Daniel Vetter 
Cc: Petri Latvala 
---
 overlay/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/overlay/meson.build b/overlay/meson.build
index 8b5c52b4..546c8377 100644
--- a/overlay/meson.build
+++ b/overlay/meson.build
@@ -59,7 +59,7 @@ if leg.found()
command: [leg, '-P', '-o', '@OUTPUT@', '@INPUT@'])
gpu_overlay_src += leg_file
 else
-   warning('leg command not found, disabling overlay; try : apt-get 
install peg')
+   message('WARNING: leg command not found, disabling overlay; try : 
apt-get install peg')
 endif
 
 if leg.found() and xrandr.found() and cairo.found()
-- 
2.14.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Patchwork]

== Series Details ==

Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
URL   : https://patchwork.freedesktop.org/series/36039/
State : success

== Summary ==

Series 36039v1 drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
https://patchwork.freedesktop.org/api/1.0/series/36039/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:427s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:369s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:477s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:484s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:465s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:451s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:263s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:408s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:497s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:570s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:435s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:522s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:427s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:596s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:463s

1902822a64e3140b0d89ee7042ec4aa89c81afa6 drm-tip: 2018y-01m-04d-19h-38m-27s UTC 
integration manifest
abab48d0ad38 drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7609/issues.html
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[Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Kenneth Graunke]

Geminilake requires the 3D driver to select whether barriers are
intended for compute shaders, or tessellation control shaders, by
whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
switching pipelines.  Failure to do this properly can result in GPU
hangs.

Unfortunately, this means it needs to switch mid-batch, so only
userspace can properly set it.  To facilitate this, the kernel needs
to whitelist the register.

Signed-off-by: Kenneth Graunke 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_reg.h| 2 ++
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 2 files changed, 7 insertions(+)

Hello,

We unfortunately need to whitelist an extra register for GPU hang fix
on Geminilake.  Here's the corresponding Mesa patch:

https://patchwork.freedesktop.org/patch/196047/

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 966e4df9700e..505c605eff98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7079,6 +7079,8 @@ enum {
 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
+#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ebdcbcbacb3c..d64a9f907550 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* Userspace needs to toggle "Barrier Mode" to avoid GPU hangs */
+   ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+   if (ret)
+   return ret;
+
/* WaToEnableHwFixForPushConstHWBug:glk */
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-- 
2.15.1

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Re: [Intel-gfx] [PATCH] drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

[Chris Wilson]

Quoting Matthew Auld (2018-01-04 17:20:16)
> On 4 January 2018 at 16:38, Chris Wilson  wrote:
> > In some iommu, e.g. swiotlb, the available space can be quite limited.
> > So we employ a trial-and-error approach to seeing if our large
> > contiguous chunks can fit, and if that fails we try again with smaller
> > chunks after trying to free our own lazily allocated blobs. As we use a
> > trial-and-error approach, we do not want dma_map_sg() to emit a WARN of
> > its own accord, we want to gracefully report the error back to the caller
> > instead.
> >
> > Note that our noisy culprit, swiotlb, doesn't honour the flag, yet.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Joonas Lahtinen 
> > Cc: Matthew Auld 
> Reviewed-by: Matthew Auld 

Thanks, pushed the small tweak for a silent future.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

[Patchwork]

== Series Details ==

Series: drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()
URL   : https://patchwork.freedesktop.org/series/36025/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
fail   -> PASS   (shard-hsw) fdo#103167 +1
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_flip:
Subgroup flip-vs-panning-vs-hang-interruptible:
pass   -> DMESG-WARN (shard-snb) fdo#103821
Subgroup vblank-vs-modeset-suspend-interruptible:
skip   -> PASS   (shard-snb)
incomplete -> PASS   (shard-hsw) fdo#103540
Subgroup modeset-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060

shard-hswtotal:2636 pass:1491 dwarn:1   dfail:0   fail:10  skip:1134 
time:8724s
shard-snbtotal:2713 pass:1308 dwarn:2   dfail:0   fail:12  skip:1391 
time:7785s
Blacklisted hosts:
shard-apltotal:2636 pass:1635 dwarn:1   dfail:0   fail:26  skip:974 
time:12926s
shard-kbltotal:2713 pass:1791 dwarn:14  dfail:0   fail:29  skip:879 
time:10541s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7608/shards.html
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Re: [Intel-gfx] linux-firmware Pull Request (CNL:DMC)

[Srivatsa, Anusha]

>-Original Message-
>From: Josh Boyer [mailto:jwbo...@kernel.org]
>Sent: Wednesday, January 3, 2018 12:27 PM
>To: Srivatsa, Anusha 
>Cc: linux-firmw...@kernel.org; Intel Graphics Development g...@lists.freedesktop.org>; Ben Hutchings ; Kyle
>McMartin 
>Subject: Re: linux-firmware Pull Request (CNL:DMC)
>
>On Tue, Jan 2, 2018 at 2:10 PM, Anusha Srivatsa 
>wrote:
>> Hi Josh, Ben, Kyle,
>>
>> Please consider pulling i915 updates to linux-firmware.git.
>> The following changes since commit
>2567e092339cd3403d697dc2e0967c31b7acb989:
>>
>>   nvidia: add GP108 signed firmware (2017-12-21 08:08:05 -0500)
>>
>> are available in the git repository at:
>>
>>   https://cgit.freedesktop.org/drm/drm-firmware/ master
>>
>> for you to fetch changes up to 4a77cab4a02712fc7b37b55c120eec61fe7e3f32:
>>
>>   linux-firmware: DMC firmware for cannonlake v1.07 (2018-01-02
>> 10:52:43 -0800)
>>
>> 
>> Anusha Srivatsa (1):
>>   linux-firmware: DMC firmware for cannonlake v1.07
>>
>>  WHENCE   |   2 ++
>>  i915/cnl_dmc_ver1_07.bin | Bin 0 -> 11268 bytes
>>  2 files changed, 2 insertions(+)
>>  create mode 100644 i915/cnl_dmc_ver1_07.bin
>
>Merged and pushed out.  Thanks.

Thanks a lot Josh.

Anusha 
>josh
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Re: [Intel-gfx] [PATCH v3 11/12] drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:21:53 +0100, Sagar Arun Kamble  
 wrote:



In order to override the disable/enable control of GuC interrupts during
suspend/reset cycle we are creating two new functions suspend/restore
guc_interrupts which check if interrupts were enabled and disable them
on suspend and enable them on resume. They are used to restore interrupts
across reset as well.

Further restructuring of runtime_pm_enable/disable_interrupts and
suspend/restore_guc_interrupts will be done in upcoming patches.

v2: Rebase.

v3: Updated suspend/restore with the new low level get/put functions.
(Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_guc.c | 32  


 drivers/gpu/drm/i915/intel_guc.h |  2 ++
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c  
b/drivers/gpu/drm/i915/intel_display.c

index 0cd3559..2e0db53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3676,8 +3676,10 @@ void intel_finish_reset(struct drm_i915_private  
*dev_priv)

 * The display has been reset as well,
 * so need a full re-initialization.
 */
+   intel_suspend_guc_interrupts(_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_restore_guc_interrupts(_priv->guc);
intel_pps_unlock_regs_wa(dev_priv);
intel_modeset_init_hw(dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index d356c40..28a418a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,8 +406,7 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
-   if (guc->log.level >= 0)
-   intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+   intel_suspend_guc_interrupts(guc);


Hmm, maybe we should introduce

intel_uc_suspend(struct drm_i915_private *dev_priv)

which will call separately

intel_guc_suspend(guc); /* send suspend action */
intel_guc_suspend_interrupts(guc);


data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -452,8 +451,7 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
-   if (guc->log.level >= 0)
-   intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+   intel_restore_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -548,6 +546,16 @@ void intel_get_guc_interrupts(struct intel_guc  
*guc, enum guc_intr_client id)

spin_unlock_irq(_priv->irq_lock);
 }
+void intel_restore_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (guc->interrupt_clients)
+   __intel_get_guc_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+}
+
 static void __intel_put_guc_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,6 +584,22 @@ void intel_put_guc_interrupts(struct intel_guc  
*guc, enum guc_intr_client id)

intel_reset_guc_interrupts(guc);
 }
+void intel_suspend_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (!guc->interrupt_clients) {
+   spin_unlock_irq(_priv->irq_lock);
+   return;
+   }
+   __intel_put_guc_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+   synchronize_irq(dev_priv->drm.irq);
+
+   intel_reset_guc_interrupts(guc);
+}
+
 void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index af74392..2c14781 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -140,5 +140,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma  
*vma)
 void intel_get_guc_interrupts(struct intel_guc *guc, enum  
guc_intr_client id);
 void intel_put_guc_interrupts(struct intel_guc *guc, enum  
guc_intr_client id);

 void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);
+void 

Re: [Intel-gfx] [PATCH v3 10/12] drm/i915/guc: Add client support to enable/disable GuC interrupts

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:21:52 +0100, Sagar Arun Kamble  
 wrote:



This patch adds support to enable/disable GuC interrupts for different
features without impacting other's need. Currently GuC log capture and
CT buffer receive mechanisms use the GuC interrupts. GuC interrupts are
currently enabled and disabled in different logging scenarios all gated
by log level.

v2: Rebase with all GuC interrupt handlers moved to intel_guc.c. Handling
multiple clients for GuC interrupts enable/disable.
(Michal Wajdeczko)

v3: Removed spin lock and using test_bit in i915_guc_info. Prepared low
level helpers to get/put GuC interrupts that can be reused during
suspend/resume. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 +
 drivers/gpu/drm/i915/intel_guc.c | 47  
+++-

 drivers/gpu/drm/i915/intel_guc.h | 11 ++---
 drivers/gpu/drm/i915/intel_guc_log.c |  6 ++---
 drivers/gpu/drm/i915/intel_uc.c  |  4 +--
 5 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
b/drivers/gpu/drm/i915/i915_debugfs.c

index 16f9a95..eef4c8b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2340,6 +2340,12 @@ static int i915_guc_info(struct seq_file *m, void  
*data)

GEM_BUG_ON(!guc->execbuf_client);
GEM_BUG_ON(!guc->preempt_client);
+   seq_puts(m, "GuC Interrupt Clients: ");
+   if (test_bit(GUC_INTR_CLIENT_LOG, >interrupt_clients))
+   seq_puts(m, "GuC Logging\n");
+   else
+   seq_puts(m, "None\n");
+


Maybe this can be done in intel_guc_log.c as part of:

void intel_guc_log_dump(const struct intel_guc_log *log, struct  
drm_printer *p);




seq_printf(m, "Doorbell map:\n");
seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index 36d1bca..d356c40 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -407,7 +407,7 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

return 0;
if (guc->log.level >= 0)
-   intel_disable_guc_interrupts(guc);
+   intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -453,7 +453,7 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

return 0;
if (guc->log.level >= 0)
-   intel_enable_guc_interrupts(guc);
+   intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -524,28 +524,51 @@ void intel_reset_guc_interrupts(struct intel_guc  
*guc)

spin_unlock_irq(_priv->irq_lock);
 }
-void intel_enable_guc_interrupts(struct intel_guc *guc)
+static void __intel_get_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   lockdep_assert_held(_priv->irq_lock);
+
+   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+  dev_priv->pm_guc_events);
+   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_get_guc_interrupts(struct intel_guc *guc, enum  
guc_intr_client id)


What about intel_guc_interrupts_get(guc, id) ?


 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
spin_lock_irq(_priv->irq_lock);
-   if (!dev_priv->guc.interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   dev_priv->guc.interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
+
+   if (!guc->interrupt_clients)
+   __intel_get_guc_interrupts(guc);
+   __set_bit(id, >interrupt_clients);


Do we care about scenarios when we call "get" more than once?
Maybe we need GEM_WARN_ON at the minimum ?

Then I'm wondering if "get/put" are correct if we don't do any
refcounting... maybe "enable/disable" are more appropriate then?


+
spin_unlock_irq(_priv->irq_lock);
 }
-void intel_disable_guc_interrupts(struct intel_guc *guc)
+static void __intel_put_guc_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   spin_lock_irq(_priv->irq_lock);
-   dev_priv->guc.interrupts_enabled = false;
+   lockdep_assert_held(_priv->irq_lock);

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

[Patchwork]

== Series Details ==

Series: drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()
URL   : https://patchwork.freedesktop.org/series/36025/
State : success

== Summary ==

Series 36025v1 drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()
https://patchwork.freedesktop.org/api/1.0/series/36025/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:425s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:367s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:481s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:261s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:516s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:388s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:572s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:437s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:263  dwarn:0   dfail:0   fail:1   skip:24  
time:480s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:400s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:556s
fi-cnl-y total:249  pass:224  dwarn:0   dfail:0   fail:0   skip:24 
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:466s

eb3dae33ff20a9460034bbfa8a95c1c56c173116 drm-tip: 2018y-01m-04d-13h-53m-17s UTC 
integration manifest
f668d8cdecde drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7608/issues.html
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Re: [Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:21:45 +0100, Sagar Arun Kamble  
 wrote:



GuC interrupts handling functions are GuC specific functions hence update
the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 22 +++---
 drivers/gpu/drm/i915/intel_guc.h |  8 
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
 drivers/gpu/drm/i915/intel_uc.c  |  8 
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c  
b/drivers/gpu/drm/i915/i915_irq.c

index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct  
drm_i915_private *dev_priv,

gen6_rps_irq_handler(dev_priv, gt_iir[2]);
if (gt_iir[2] & dev_priv->pm_guc_events)
-   intel_guc_irq_handler(dev_priv, gt_iir[2]);
+   intel_guc_irq_handler(_priv->guc, gt_iir[2]);
 }
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
-   intel_disable_guc_interrupts(dev_priv);
+   intel_disable_guc_interrupts(guc);


Hmm, if we disable irq here, then we might have problems with
sending this message to GuC if we use CTB as comm mechanism...


data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

return 0;
if (i915_modparams.guc_log_level >= 0)
-   intel_enable_guc_interrupts(dev_priv);
+   intel_enable_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct drm_i915_private  
*dev_priv)

return wopcm_size;
 }
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
 }
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {


Just spotted:
as we have "guc" try to use "guc->" instead of "dev_priv->guc."


WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct  
drm_i915_private *dev_priv)

spin_unlock_irq(_priv->irq_lock);
 }
-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;


same here (and possibly in other places too)

@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct  
drm_i915_private *dev_priv)

spin_unlock_irq(_priv->irq_lock);
synchronize_irq(dev_priv->drm.irq);
-   intel_reset_guc_interrupts(dev_priv);
+   intel_reset_guc_interrupts(guc);
 }
-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32  
gt_iir)

+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
/* Sample the log buffer flush related bits & clear them out now
 * itself from the message identity register to minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma  
*vma)

 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
size);

 u32 

Re: [Intel-gfx] [PATCH] drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

[Matthew Auld]

On 4 January 2018 at 16:38, Chris Wilson  wrote:
> In some iommu, e.g. swiotlb, the available space can be quite limited.
> So we employ a trial-and-error approach to seeing if our large
> contiguous chunks can fit, and if that fails we try again with smaller
> chunks after trying to free our own lazily allocated blobs. As we use a
> trial-and-error approach, we do not want dma_map_sg() to emit a WARN of
> its own accord, we want to gracefully report the error back to the caller
> instead.
>
> Note that our noisy culprit, swiotlb, doesn't honour the flag, yet.
>
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Matthew Auld 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH v3 09/12] drm/i915/guc: Make GuC log related functions depend only on log level

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:21:51 +0100, Sagar Arun Kamble  
 wrote:



With GuC log level set properly only for cases where GuC is loaded we can
remove the GuC submission checks from flush_guc_logs and  
guc_log_register,

unregister and uc_fini_hw functions. It is important to note that GuC log
runtime data has to be freed during driver unregister.
Freeing of that data can't be gated by guc_log_level check because if we
free GuC log runtime only when log level >=0 then it will not be  
destroyed

when logging is disabled after enabling before driver unload.

Also, with this patch GuC interrupts are enabled first after GuC load if
logging is enabled. GuC to Host interrupts will be needed for GuC CT
buffer recv mechanism and hence we will be adding support to control that
interrupt based on ref. taken by Log or CT recv feature in next patch. To
prepare for that all interrupt updates are now gated by GuC log level
checks.

v2: Rebase. Updated check in i915_guc_log_unregister to be based on
guc_log_level. (Michal Wajdeczko)

v3: Rebase. Made all GuC log related functions depend only log level.
Updated uC init w.r.t enabling of GuC interrupts. Commit message update.
Rebase w.r.t guc_log_level immutable changes. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 17 +++--
 drivers/gpu/drm/i915/intel_uc.c  | 15 ---
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index d351642..36d1bca 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,7 +406,8 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
-   intel_disable_guc_interrupts(guc);
+   if (guc->log.level >= 0)
+   intel_disable_guc_interrupts(guc);
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c  
b/drivers/gpu/drm/i915/intel_guc_log.c

index d979830..7bc0065 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -484,8 +484,7 @@ static void guc_log_capture_logs(struct intel_guc  
*guc)

static void guc_flush_logs(struct intel_guc *guc)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   guc->log.level < 0)
+   if (guc->log.level < 0)
return;
/* First disable the interrupts, will be renabled afterwards */
@@ -613,8 +612,7 @@ int i915_guc_log_control(struct drm_i915_private  
*dev_priv, u64 control_val)

void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   dev_priv->guc.log.level < 0)
+   if (dev_priv->guc.log.level < 0)
return;
mutex_lock(_priv->drm.struct_mutex);
@@ -624,14 +622,13 @@ void i915_guc_log_register(struct drm_i915_private  
*dev_priv)

void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv))
-   return;
-
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
-   intel_runtime_pm_get(dev_priv);
-   intel_disable_guc_interrupts(_priv->guc);
-   intel_runtime_pm_put(dev_priv);
+   if (dev_priv->guc.log.level >= 0) {


Can we move "if (guc->log.level >= 0)" condition check to
intel_guc_[disable|enable]_interrupts functions? Then we
should be able to avoid repeating this check over and over
and it will be also easier for use once we add new CTB check.


+   intel_runtime_pm_get(dev_priv);
+   intel_disable_guc_interrupts(_priv->guc);
+   intel_runtime_pm_put(dev_priv);
+   }
intel_guc_log_runtime_destroy(_priv->guc);
mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index e2e2020..fb5edcc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -318,9 +318,12 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

if (ret)
goto err_log_capture;
+   if (guc->log.level >= 0)
+   intel_enable_guc_interrupts(guc);
+
ret = guc_enable_communication(guc);
if (ret)
-   goto err_log_capture;
+   goto err_interrupts;
if (USES_HUC(dev_priv)) {
ret = intel_huc_auth(huc);
@@ -329,12 +332,9 @@ int intel_uc_init_hw(struct 

[Intel-gfx] [PATCH] drm/i915: Pass DMA_ATTR_NO_WARN to dma_map_sg()

[Chris Wilson]

In some iommu, e.g. swiotlb, the available space can be quite limited.
So we employ a trial-and-error approach to seeing if our large
contiguous chunks can fit, and if that fails we try again with smaller
chunks after trying to free our own lazily allocated blobs. As we use a
trial-and-error approach, we do not want dma_map_sg() to emit a WARN of
its own accord, we want to gracefully report the error back to the caller
instead.

Note that our noisy culprit, swiotlb, doesn't honour the flag, yet.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5f393870532..f2a0f556da21 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2335,9 +2335,10 @@ int i915_gem_gtt_prepare_pages(struct 
drm_i915_gem_object *obj,
   struct sg_table *pages)
 {
do {
-   if (dma_map_sg(>base.dev->pdev->dev,
-  pages->sgl, pages->nents,
-  PCI_DMA_BIDIRECTIONAL))
+   if (dma_map_sg_attrs(>base.dev->pdev->dev,
+pages->sgl, pages->nents,
+PCI_DMA_BIDIRECTIONAL,
+DMA_ATTR_NO_WARN))
return 0;
 
/* If the DMA remap fails, one cause can be that we have
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for kms_vblank: Move tests over from kms_flip. (rev2)

[Patchwork]

== Series Details ==

Series: kms_vblank: Move tests over from kms_flip. (rev2)
URL   : https://patchwork.freedesktop.org/series/36006/
State : success

== Summary ==

Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
fail   -> PASS   (shard-hsw) fdo#103167
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2804 pass:1576 dwarn:1   dfail:0   fail:11  skip:1216 
time:7620s
shard-snbtotal:2804 pass:1321 dwarn:1   dfail:0   fail:13  skip:1469 
time:6530s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_746/shards.html
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Re: [Intel-gfx] [PATCH v3 04/12] drm/i915/guc: Add description and comments about guc_log_level parameter

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:21:46 +0100, Sagar Arun Kamble  
 wrote:



guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info.

 ^^^
Extra "."


in parameter description and documentation.
Earlier, this patch was added to sanitize guc_log_level like old
GuC parameters enable_guc_loading/submission. With new parameter
enable_guc, sanitization of guc_log_level is no more needed.


Hmm, I think we still need to sanitize log_level if it was wrongly
enabled without enabling GuC first (in intel_uc_sanitize_options).



v2: Added documentation to intel_guc_log.c and param description
about GuC loading dependency. (Michal Wajdeczko)

v3: Removed sanitization of module parameter guc_log_level.
Previous review comments not applicable now.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin  #v2
---
 drivers/gpu/drm/i915/i915_params.c   | 3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c  
b/drivers/gpu/drm/i915/i915_params.c

index b5f3eb4..a93a6ca 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -155,7 +155,8 @@ struct i915_params i915_modparams __read_mostly = {
"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
i915_param_named(guc_log_level, int, 0400,
-   "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+   "GuC firmware logging level. This takes effect only if GuC is to be "
+   "loaded (depends on enable_guc) (-1:disabled (default), 0-3:enabled)");


Btw, I was planing to change above values to follow schema used in other  
modparams:


-1: auto (then it can be controlled by USES_GUC and DRM_I915_DEBUG_GUC)
 0: disabled
 1: enabled (legacy level 0)
 2: enabled (legacy level 1)
 3: enabled (legacy level 2)
 4: enabled (legacy level 3)

So now I'm not sure that I want your patch ;)


i915_param_named_unsafe(guc_firmware_path, charp, 0400,
"GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c  
b/drivers/gpu/drm/i915/intel_guc_log.c

index 59a9021..d0131bc 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -34,6 +34,7 @@
  * DOC: GuC firmware log
  *
  * Firmware log is enabled by setting i915.guc_log_level to  
non-negative level.

+ * This takes effect only if GuC is to be loaded based on enable_guc.


... based on i915.enable_guc modparam.

  * Log data is printed out via reading debugfs i915_guc_log_dump.  
Reading from
  * i915_guc_load_status will print out firmware loading status and  
scratch

  * registers value.

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[Intel-gfx] ✗ Fi.CI.BAT: failure for GuC Interrupts/Log updates (rev2)

[Patchwork]

== Series Details ==

Series: GuC Interrupts/Log updates (rev2)
URL   : https://patchwork.freedesktop.org/series/32179/
State : failure

== Summary ==

Series 32179v2 GuC Interrupts/Log updates
https://patchwork.freedesktop.org/api/1.0/series/32179/revisions/2/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-gdg-551)
pass   -> INCOMPLETE (fi-blb-e6850)
pass   -> INCOMPLETE (fi-pnv-d510)
pass   -> INCOMPLETE (fi-bwr-2160)
pass   -> INCOMPLETE (fi-elk-e7500)
pass   -> INCOMPLETE (fi-ilk-650)
pass   -> INCOMPLETE (fi-snb-2520m)
pass   -> INCOMPLETE (fi-snb-2600)
pass   -> INCOMPLETE (fi-ivb-3520m)
pass   -> INCOMPLETE (fi-ivb-3770)
pass   -> INCOMPLETE (fi-byt-j1900)
pass   -> INCOMPLETE (fi-byt-n2820)
pass   -> INCOMPLETE (fi-hsw-4770)
pass   -> INCOMPLETE (fi-hsw-4770r)
pass   -> INCOMPLETE (fi-bdw-5557u)
pass   -> INCOMPLETE (fi-bdw-gvtdvm)
pass   -> INCOMPLETE (fi-bsw-n3050)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test core_prop_blob:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test debugfs_test:
Subgroup read_all_entries:
pass   -> DMESG-WARN (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6600u)
pass   -> DMESG-WARN (fi-skl-6700hq)
pass   -> DMESG-WARN (fi-skl-6700k2)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-bxt-dsi)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-kbl-7500u) fdo#103285
pass   -> DMESG-WARN (fi-kbl-7560u)
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r)
pass   -> SKIP   (fi-glk-1)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup basic-subslice-total:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test drv_hangman:
Subgroup error-state-basic:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test gem_basic:
Subgroup bad-close:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup create-close:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup create-fd-close:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test gem_busy:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup basic-hang-default:
pass   -> SKIP   (fi-skl-gvtdvm) fdo#104108 +4
pass   -> SKIP   (fi-glk-1)
Test gem_close_race:
Subgroup basic-process:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup basic-threads:
pass   -> DMESG-WARN (fi-skl-6600u)
pass   -> DMESG-WARN (fi-skl-6700k2)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-kbl-7500u)
pass   -> DMESG-WARN (fi-kbl-7560u)
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r)
pass   -> SKIP   (fi-glk-1)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Test gem_ctx_create:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
Subgroup basic-files:
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-glk-1)
WARNING: Long output truncated

eb3dae33ff20a9460034bbfa8a95c1c56c173116 drm-tip: 2018y-01m-04d-13h-53m-17s UTC 
integration manifest
6049e29e65e7 HAX: 

Re: [Intel-gfx] [PATCH] drm: i915: Fix audio issue on BXT

[Singh, Gaurav K]

On 1/4/2018 2:48 AM, Rodrigo Vivi wrote:

On Wed, Jan 03, 2018 at 08:31:10PM +, Pandiyan, Dhinakaran wrote:

On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:

From: Gaurav Singh 

On Apollolake, with stress test warm reboot, audio card
was not getting enumerated after reboot. This was a

The problem looks similar to
https://lists.freedesktop.org/archives/intel-gfx/2017-October/144495.html

although the proposed solutions are vastly different. I have Cc'd some
more people.


spurious issue happening on Apollolake. HW codec and
HD audio controller link was going out of sync for which
there was a fix in i915 driver but was not getting invoked
for BXT. Extending this fix to BXT as well.

Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.

Signed-off-by: Gaurav K Singh 
---
  drivers/gpu/drm/i915/intel_audio.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index f1502a0188eb..c71c04e1c3f6 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -729,7 +729,7 @@ static void i915_audio_component_codec_wake_override(struct 
device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
  
-	if (!IS_GEN9_BC(dev_priv))

+   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))

IS_GEN9()? GLK might need this too.

I think this is applicable for all Gen9 platforms.



if GLK need there is the possibility of CNL also needing it...
So not sure where to stop.

Also looking to the original patch that introduced this function,
commit '632f3ab95fe2 ("drm/i915/audio: add codec wakeup override
enabled/disable callback")'

it tells that the reason was:
"In SKL, HDMI/DP codec and PCH HD Audio Controller are in different p$
wells, so it's necessary to reset display audio codecs when power we$
otherwise display audio codecs will disappear when resume from low p$
state."

Is this the case here on BXT?

Yes, its the same case with BXT.


Another interesting thing I noticed on Spec when searching for this bit
was that this bit is related to an workaround on SKL/KBL/CFL... no mention
to BXT.

"This workaround is needed for an HW issue in SKL and KBL in which HW codec
and HD audio controller link was going out of sync."
Yes, in Bspec it has been mentioned only for SKL and KBL. But without 
this fix, sound card was not getting enumerated for BXT.


Thanks,
Rodrigo.




return;
  
  	i915_audio_component_get_power(kdev);

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Re: [Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Michal Wajdeczko]

On Thu, 04 Jan 2018 17:23:05 +0100, Chris Wilson  
 wrote:



Quoting Sagar Arun Kamble (2018-01-04 16:21:45)
GuC interrupts handling functions are GuC specific functions hence  
update

the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 22 +++---
 drivers/gpu/drm/i915/intel_guc.h |  8 
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
 drivers/gpu/drm/i915/intel_uc.c  |  8 
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c  
b/drivers/gpu/drm/i915/i915_irq.c

index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct  
drm_i915_private *dev_priv,

gen6_rps_irq_handler(dev_priv, gt_iir[2]);

if (gt_iir[2] & dev_priv->pm_guc_events)
-   intel_guc_irq_handler(dev_priv, gt_iir[2]);
+   intel_guc_irq_handler(_priv->guc, gt_iir[2]);
 }

 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;

-   intel_disable_guc_interrupts(dev_priv);
+   intel_disable_guc_interrupts(guc);

data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

return 0;

if (i915_modparams.guc_log_level >= 0)
-   intel_enable_guc_interrupts(dev_priv);
+   intel_enable_guc_interrupts(guc);

data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct drm_i915_private  
*dev_priv)

return wopcm_size;
 }

-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
 }

-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct  
drm_i915_private *dev_priv)

spin_unlock_irq(_priv->irq_lock);
 }

-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;

@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct  
drm_i915_private *dev_priv)

spin_unlock_irq(_priv->irq_lock);
synchronize_irq(dev_priv->drm.irq);

-   intel_reset_guc_interrupts(dev_priv);
+   intel_reset_guc_interrupts(guc);
 }

-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32  
gt_iir)

+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
/* Sample the log buffer flush related bits & clear  
them out now
 * itself from the message identity register to  
minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma  
*vma)

 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
size);

 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void 

Re: [Intel-gfx] [PATCH v3 12/12] HAX: drm/i915/guc: enable GuC submission/logging for CI

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-01-04 16:21:54)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6c8da9d..c8460c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2659,6 +2659,8 @@ static int intel_runtime_resume(struct device *kdev)
> if (intel_uncore_unclaimed_mmio(dev_priv))
> DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>  
> +   intel_runtime_pm_enable_interrupts(dev_priv);
> +
> intel_guc_resume(dev_priv);
>  
> if (IS_GEN9_LP(dev_priv)) {
> @@ -2682,8 +2684,6 @@ static int intel_runtime_resume(struct device *kdev)
> i915_gem_init_swizzling(dev_priv);
> i915_gem_restore_fences(dev_priv);
>  
> -   intel_runtime_pm_enable_interrupts(dev_priv);

Have I missed the pending patch?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-01-04 16:21:45)
> GuC interrupts handling functions are GuC specific functions hence update
> the parameter from dev_priv to intel_guc struct.
> 
> v2-v3: Rebase.
> 
> Signed-off-by: Sagar Arun Kamble 
> Cc: Michal Wajdeczko 
> Cc: Daniele Ceraolo Spurio 
> Cc: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Reviewed-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_irq.c  |  2 +-
>  drivers/gpu/drm/i915/intel_guc.c | 22 +++---
>  drivers/gpu/drm/i915/intel_guc.h |  8 
>  drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
>  drivers/gpu/drm/i915/intel_uc.c  |  8 
>  5 files changed, 27 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3f4eff9..a1ae057 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private 
> *dev_priv,
> gen6_rps_irq_handler(dev_priv, gt_iir[2]);
>  
> if (gt_iir[2] & dev_priv->pm_guc_events)
> -   intel_guc_irq_handler(dev_priv, gt_iir[2]);
> +   intel_guc_irq_handler(_priv->guc, gt_iir[2]);
>  }
>  
>  static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> diff --git a/drivers/gpu/drm/i915/intel_guc.c 
> b/drivers/gpu/drm/i915/intel_guc.c
> index e95ff2d..14bf508d 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
> if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> return 0;
>  
> -   intel_disable_guc_interrupts(dev_priv);
> +   intel_disable_guc_interrupts(guc);
>  
> data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
> /* any value greater than GUC_POWER_D0 */
> @@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
> return 0;
>  
> if (i915_modparams.guc_log_level >= 0)
> -   intel_enable_guc_interrupts(dev_priv);
> +   intel_enable_guc_interrupts(guc);
>  
> data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
> data[1] = GUC_POWER_D0;
> @@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct drm_i915_private 
> *dev_priv)
> return wopcm_size;
>  }
>  
> -void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +void intel_reset_guc_interrupts(struct intel_guc *guc)
>  {
> +   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> spin_lock_irq(_priv->irq_lock);
> gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
> spin_unlock_irq(_priv->irq_lock);
>  }
>  
> -void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> +void intel_enable_guc_interrupts(struct intel_guc *guc)
>  {
> +   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> spin_lock_irq(_priv->irq_lock);
> if (!dev_priv->guc.interrupts_enabled) {
> WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
> @@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct drm_i915_private 
> *dev_priv)
> spin_unlock_irq(_priv->irq_lock);
>  }
>  
> -void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> +void intel_disable_guc_interrupts(struct intel_guc *guc)
>  {
> +   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> spin_lock_irq(_priv->irq_lock);
> dev_priv->guc.interrupts_enabled = false;
>  
> @@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct 
> drm_i915_private *dev_priv)
> spin_unlock_irq(_priv->irq_lock);
> synchronize_irq(dev_priv->drm.irq);
>  
> -   intel_reset_guc_interrupts(dev_priv);
> +   intel_reset_guc_interrupts(guc);
>  }
>  
> -void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
> +void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
>  {
> +   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
> /* Sample the log buffer flush related bits & clear them out 
> now
>  * itself from the message identity register to minimize the
> diff --git a/drivers/gpu/drm/i915/intel_guc.h 
> b/drivers/gpu/drm/i915/intel_guc.h
> index c37d34d..49f33b9 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
>  int intel_guc_resume(struct drm_i915_private *dev_priv);
>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
>  u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> -void 

Re: [Intel-gfx] [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12

[Maarten Lankhorst]

Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar 
>
> Current code calculates DDB for planar formats in such a way that we
> store DDB of plane-0 in plane 1 & vice-versa.
> In order to make this clean this patch refactors WM/DDB calculation for
> NV12 planar formats.
>
> Signed-off-by: Mahesh Kumar 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |   2 +-
>  drivers/gpu/drm/i915/intel_drv.h |   1 +
>  drivers/gpu/drm/i915/intel_pm.c  | 120 
> +++
>  3 files changed, 62 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 56047f8..962717d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1434,7 +1434,7 @@ static inline bool skl_ddb_entry_equal(const struct 
> skl_ddb_entry *e1,
>  
>  struct skl_ddb_allocation {
>   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
> packed/uv */
^Should this be changed to packed/y?
> - struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> + struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
>  };
>  
>  struct skl_ddb_values {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9c8aef9..5f5e070 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -513,6 +513,7 @@ struct intel_pipe_wm {
>  struct skl_plane_wm {
>   struct skl_wm_level wm[8];
>   struct skl_wm_level trans_wm;
> + bool is_nv12;
>  };
>  
>  struct skl_pipe_wm {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e2598cf..15edb9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4004,9 +4004,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
> *intel_crtc,
>  static unsigned int
>  skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>const struct drm_plane_state *pstate,
> -  int y)
> +  const int plane)
>  {
> - struct intel_plane *plane = to_intel_plane(pstate->plane);
> + struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
>   struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
>   uint32_t data_rate;
>   uint32_t width = 0, height = 0;
> @@ -4020,9 +4020,9 @@ skl_plane_relative_data_rate(const struct 
> intel_crtc_state *cstate,
>   fb = pstate->fb;
>   format = fb->format->format;
>  
> - if (plane->id == PLANE_CURSOR)
> + if (intel_plane->id == PLANE_CURSOR)
>   return 0;
> - if (y && format != DRM_FORMAT_NV12)
> + if (plane == 1 && format != DRM_FORMAT_NV12)
>   return 0;
>  
>   /*
> @@ -4033,19 +4033,14 @@ skl_plane_relative_data_rate(const struct 
> intel_crtc_state *cstate,
>   width = drm_rect_width(_pstate->base.src) >> 16;
>   height = drm_rect_height(_pstate->base.src) >> 16;
>  
> - /* for planar format */
> - if (format == DRM_FORMAT_NV12) {
> - if (y)  /* y-plane data rate */
> - data_rate = width * height *
> - fb->format->cpp[0];
> - else/* uv-plane data rate */
> - data_rate = (width / 2) * (height / 2) *
> - fb->format->cpp[1];
> - } else {
> - /* for packed formats */
> - data_rate = width * height * fb->format->cpp[0];
> + /* UV plane does 1/2 pixel sub-sampling */
> + if (plane == 1 && format == DRM_FORMAT_NV12) {
> + width /= 2;
> + height /= 2;
>   }
>  
> + data_rate = width * height * fb->format->cpp[plane];
> +
>   down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
>  
>   return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
> @@ -4058,8 +4053,8 @@ skl_plane_relative_data_rate(const struct 
> intel_crtc_state *cstate,
>   */
>  static unsigned int
>  skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> -  unsigned *plane_data_rate,
> -  unsigned *plane_y_data_rate)
> +  unsigned int *plane_data_rate,
> +  unsigned int *uv_plane_data_rate)
>  {
>   struct drm_crtc_state *cstate = _cstate->base;
>   struct drm_atomic_state *state = cstate->state;
> @@ -4075,17 +4070,16 @@ skl_get_total_relative_data_rate(struct 
> intel_crtc_state *intel_cstate,
>   enum plane_id plane_id = to_intel_plane(plane)->id;
>   unsigned int rate;
>  
> - /* packed/uv */
packed/y?
>   rate = skl_plane_relative_data_rate(intel_cstate,
>   pstate, 0);
>   plane_data_rate[plane_id] = rate;
>  
> 

[Intel-gfx] [PATCH v3 10/12] drm/i915/guc: Add client support to enable/disable GuC interrupts

[Sagar Arun Kamble]

This patch adds support to enable/disable GuC interrupts for different
features without impacting other's need. Currently GuC log capture and
CT buffer receive mechanisms use the GuC interrupts. GuC interrupts are
currently enabled and disabled in different logging scenarios all gated
by log level.

v2: Rebase with all GuC interrupt handlers moved to intel_guc.c. Handling
multiple clients for GuC interrupts enable/disable.
(Michal Wajdeczko)

v3: Removed spin lock and using test_bit in i915_guc_info. Prepared low
level helpers to get/put GuC interrupts that can be reused during
suspend/resume. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 +
 drivers/gpu/drm/i915/intel_guc.c | 47 +++-
 drivers/gpu/drm/i915/intel_guc.h | 11 ++---
 drivers/gpu/drm/i915/intel_guc_log.c |  6 ++---
 drivers/gpu/drm/i915/intel_uc.c  |  4 +--
 5 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 16f9a95..eef4c8b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2340,6 +2340,12 @@ static int i915_guc_info(struct seq_file *m, void *data)
GEM_BUG_ON(!guc->execbuf_client);
GEM_BUG_ON(!guc->preempt_client);
 
+   seq_puts(m, "GuC Interrupt Clients: ");
+   if (test_bit(GUC_INTR_CLIENT_LOG, >interrupt_clients))
+   seq_puts(m, "GuC Logging\n");
+   else
+   seq_puts(m, "None\n");
+
seq_printf(m, "Doorbell map:\n");
seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 36d1bca..d356c40 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -407,7 +407,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
return 0;
 
if (guc->log.level >= 0)
-   intel_disable_guc_interrupts(guc);
+   intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -453,7 +453,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
return 0;
 
if (guc->log.level >= 0)
-   intel_enable_guc_interrupts(guc);
+   intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -524,28 +524,51 @@ void intel_reset_guc_interrupts(struct intel_guc *guc)
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_enable_guc_interrupts(struct intel_guc *guc)
+static void __intel_get_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   lockdep_assert_held(_priv->irq_lock);
+
+   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+  dev_priv->pm_guc_events);
+   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_get_guc_interrupts(struct intel_guc *guc, enum guc_intr_client id)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
spin_lock_irq(_priv->irq_lock);
-   if (!dev_priv->guc.interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   dev_priv->guc.interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
+
+   if (!guc->interrupt_clients)
+   __intel_get_guc_interrupts(guc);
+   __set_bit(id, >interrupt_clients);
+
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_disable_guc_interrupts(struct intel_guc *guc)
+static void __intel_put_guc_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
-   spin_lock_irq(_priv->irq_lock);
-   dev_priv->guc.interrupts_enabled = false;
+   lockdep_assert_held(_priv->irq_lock);
 
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_put_guc_interrupts(struct intel_guc *guc, enum guc_intr_client id)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+
+   __clear_bit(id, >interrupt_clients);
+   if (guc->interrupt_clients) {
+   spin_unlock_irq(_priv->irq_lock);
+   return;
+   }
+   __intel_put_guc_interrupts(guc);
 
spin_unlock_irq(_priv->irq_lock);

[Intel-gfx] [PATCH v3 09/12] drm/i915/guc: Make GuC log related functions depend only on log level

[Sagar Arun Kamble]

With GuC log level set properly only for cases where GuC is loaded we can
remove the GuC submission checks from flush_guc_logs and guc_log_register,
unregister and uc_fini_hw functions. It is important to note that GuC log
runtime data has to be freed during driver unregister.
Freeing of that data can't be gated by guc_log_level check because if we
free GuC log runtime only when log level >=0 then it will not be destroyed
when logging is disabled after enabling before driver unload.

Also, with this patch GuC interrupts are enabled first after GuC load if
logging is enabled. GuC to Host interrupts will be needed for GuC CT
buffer recv mechanism and hence we will be adding support to control that
interrupt based on ref. taken by Log or CT recv feature in next patch. To
prepare for that all interrupt updates are now gated by GuC log level
checks.

v2: Rebase. Updated check in i915_guc_log_unregister to be based on
guc_log_level. (Michal Wajdeczko)

v3: Rebase. Made all GuC log related functions depend only log level.
Updated uC init w.r.t enabling of GuC interrupts. Commit message update.
Rebase w.r.t guc_log_level immutable changes. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 17 +++--
 drivers/gpu/drm/i915/intel_uc.c  | 15 ---
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index d351642..36d1bca 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,7 +406,8 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   intel_disable_guc_interrupts(guc);
+   if (guc->log.level >= 0)
+   intel_disable_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index d979830..7bc0065 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -484,8 +484,7 @@ static void guc_log_capture_logs(struct intel_guc *guc)
 
 static void guc_flush_logs(struct intel_guc *guc)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   guc->log.level < 0)
+   if (guc->log.level < 0)
return;
 
/* First disable the interrupts, will be renabled afterwards */
@@ -613,8 +612,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, 
u64 control_val)
 
 void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   dev_priv->guc.log.level < 0)
+   if (dev_priv->guc.log.level < 0)
return;
 
mutex_lock(_priv->drm.struct_mutex);
@@ -624,14 +622,13 @@ void i915_guc_log_register(struct drm_i915_private 
*dev_priv)
 
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv))
-   return;
-
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
-   intel_runtime_pm_get(dev_priv);
-   intel_disable_guc_interrupts(_priv->guc);
-   intel_runtime_pm_put(dev_priv);
+   if (dev_priv->guc.log.level >= 0) {
+   intel_runtime_pm_get(dev_priv);
+   intel_disable_guc_interrupts(_priv->guc);
+   intel_runtime_pm_put(dev_priv);
+   }
 
intel_guc_log_runtime_destroy(_priv->guc);
mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e2e2020..fb5edcc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -318,9 +318,12 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_log_capture;
 
+   if (guc->log.level >= 0)
+   intel_enable_guc_interrupts(guc);
+
ret = guc_enable_communication(guc);
if (ret)
-   goto err_log_capture;
+   goto err_interrupts;
 
if (USES_HUC(dev_priv)) {
ret = intel_huc_auth(huc);
@@ -329,12 +332,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
}
 
if (USES_GUC_SUBMISSION(dev_priv)) {
-   if (guc->log.level >= 0)
-   intel_enable_guc_interrupts(guc);
-
ret = intel_guc_submission_enable(guc);
if (ret)
-   goto err_interrupts;
+   goto 

[Intel-gfx] [PATCH v3 11/12] drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled

[Sagar Arun Kamble]

In order to override the disable/enable control of GuC interrupts during
suspend/reset cycle we are creating two new functions suspend/restore
guc_interrupts which check if interrupts were enabled and disable them
on suspend and enable them on resume. They are used to restore interrupts
across reset as well.

Further restructuring of runtime_pm_enable/disable_interrupts and
suspend/restore_guc_interrupts will be done in upcoming patches.

v2: Rebase.

v3: Updated suspend/restore with the new low level get/put functions.
(Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_guc.c | 32 
 drivers/gpu/drm/i915/intel_guc.h |  2 ++
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0cd3559..2e0db53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3676,8 +3676,10 @@ void intel_finish_reset(struct drm_i915_private 
*dev_priv)
 * The display has been reset as well,
 * so need a full re-initialization.
 */
+   intel_suspend_guc_interrupts(_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_restore_guc_interrupts(_priv->guc);
 
intel_pps_unlock_regs_wa(dev_priv);
intel_modeset_init_hw(dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index d356c40..28a418a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,8 +406,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (guc->log.level >= 0)
-   intel_put_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+   intel_suspend_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -452,8 +451,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (guc->log.level >= 0)
-   intel_get_guc_interrupts(guc, GUC_INTR_CLIENT_LOG);
+   intel_restore_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -548,6 +546,16 @@ void intel_get_guc_interrupts(struct intel_guc *guc, enum 
guc_intr_client id)
spin_unlock_irq(_priv->irq_lock);
 }
 
+void intel_restore_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (guc->interrupt_clients)
+   __intel_get_guc_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+}
+
 static void __intel_put_guc_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,6 +584,22 @@ void intel_put_guc_interrupts(struct intel_guc *guc, enum 
guc_intr_client id)
intel_reset_guc_interrupts(guc);
 }
 
+void intel_suspend_guc_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (!guc->interrupt_clients) {
+   spin_unlock_irq(_priv->irq_lock);
+   return;
+   }
+   __intel_put_guc_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+   synchronize_irq(dev_priv->drm.irq);
+
+   intel_reset_guc_interrupts(guc);
+}
+
 void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index af74392..2c14781 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -140,5 +140,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 void intel_get_guc_interrupts(struct intel_guc *guc, enum guc_intr_client id);
 void intel_put_guc_interrupts(struct intel_guc *guc, enum guc_intr_client id);
 void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);
+void intel_suspend_guc_interrupts(struct intel_guc *guc);
+void intel_restore_guc_interrupts(struct intel_guc *guc);
 
 #endif
-- 
1.9.1

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[Intel-gfx] [PATCH v3 08/12] drm/i915/guc: Make guc_log_level parameter immutable

[Sagar Arun Kamble]

This patch introduces i915 internal state variable in GuC log struct,
"level" which will be copied from guc_log_level modparam during i915
load and thereafter be available for user updates. This will make
guc_log_level parameter immutable.

Suggested-by: Tvrtko Ursulin 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c |  6 +++---
 drivers/gpu/drm/i915/intel_guc_log.c | 23 ++-
 drivers/gpu/drm/i915/intel_guc_log.h |  6 ++
 drivers/gpu/drm/i915/intel_uc.c  | 11 +--
 5 files changed, 29 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bb6307..16f9a95 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2459,7 +2459,7 @@ static int i915_guc_log_control_get(void *data, u64 *val)
if (!dev_priv->guc.log.vma)
return -EINVAL;
 
-   *val = i915_modparams.guc_log_level;
+   *val = dev_priv->guc.log.level;
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 0184c86..d351642 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -253,9 +253,9 @@ void intel_guc_init_params(struct intel_guc *guc)
 
params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
-   if (i915_modparams.guc_log_level >= 0) {
+   if (guc->log.level >= 0) {
params[GUC_CTL_DEBUG] =
-   i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
+   guc->log.level << GUC_LOG_VERBOSITY_SHIFT;
} else {
params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
}
@@ -451,7 +451,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (i915_modparams.guc_log_level >= 0)
+   if (guc->log.level >= 0)
intel_enable_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 3a895a3..d979830 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -148,7 +148,7 @@ static int guc_log_relay_file_create(struct intel_guc *guc)
struct dentry *log_dir;
int ret;
 
-   if (i915_modparams.guc_log_level < 0)
+   if (guc->log.level < 0)
return 0;
 
/* For now create the log file in /sys/kernel/debug/dri/0 dir */
@@ -365,7 +365,7 @@ int intel_guc_log_runtime_create(struct intel_guc *guc)
size_t n_subbufs, subbuf_size;
int ret;
 
-   if (i915_modparams.guc_log_level < 0)
+   if (guc->log.level < 0)
return 0;
 
lockdep_assert_held(_priv->drm.struct_mutex);
@@ -427,7 +427,7 @@ void intel_guc_log_runtime_destroy(struct intel_guc *guc)
 {
/*
 * It's possible that the runtime stuff was never allocated because
-* guc_log_level was < 0 at the time
+* guc->log.level was < 0 at the time
 **/
if (!guc_log_has_runtime(guc))
return;
@@ -464,7 +464,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
intel_guc_log_runtime_destroy(guc);
 err:
/* logging will remain off */
-   i915_modparams.guc_log_level = -1;
+   guc->log.level = -1;
return ret;
 }
 
@@ -485,7 +485,7 @@ static void guc_log_capture_logs(struct intel_guc *guc)
 static void guc_flush_logs(struct intel_guc *guc)
 {
if (!USES_GUC_SUBMISSION(dev_priv) ||
-   (i915_modparams.guc_log_level < 0))
+   guc->log.level < 0)
return;
 
/* First disable the interrupts, will be renabled afterwards */
@@ -513,9 +513,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
GEM_BUG_ON(guc->log.vma);
 
-   if (i915_modparams.guc_log_level > GUC_LOG_VERBOSITY_MAX)
-   i915_modparams.guc_log_level = GUC_LOG_VERBOSITY_MAX;
-
/* The first page is to save log buffer state. Allocate one
 * extra page for others in case for overlap */
size = (1 + GUC_LOG_DPC_PAGES + 1 +
@@ -552,7 +549,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 
 err:
/* logging will be off */
-   i915_modparams.guc_log_level = -1;
+   guc->log.level = -1;
return ret;
 }
 
@@ -575,7 +572,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, 
u64 control_val)
return -EINVAL;
 
/* This combination doesn't make sense & won't have any effect */

[Intel-gfx] [PATCH v3 12/12] HAX: drm/i915/guc: enable GuC submission/logging for CI

[Sagar Arun Kamble]

Also 1) revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
2) fix RPM resume interrupt enabling w.r.t GuC resume
3) disable guc log streaming DRM logs
---
 drivers/gpu/drm/i915/i915_drv.c  | 4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 8 ++--
 drivers/gpu/drm/i915/i915_params.h   | 4 ++--
 drivers/gpu/drm/i915/intel_guc_log.c | 2 +-
 4 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d..c8460c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2659,6 +2659,8 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
+   intel_runtime_pm_enable_interrupts(dev_priv);
+
intel_guc_resume(dev_priv);
 
if (IS_GEN9_LP(dev_priv)) {
@@ -2682,8 +2684,6 @@ static int intel_runtime_resume(struct device *kdev)
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
 
-   intel_runtime_pm_enable_interrupts(dev_priv);
-
/*
 * On VLV/CHV display interrupts are part of the display
 * power well, so hpd is reinitialized from there. For
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5f3938..fdd3345 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3549,8 +3549,6 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 
i915_ggtt_invalidate(i915);
@@ -3558,10 +3556,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 
i915_ggtt_invalidate(i915);
 }
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..25b7e88 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,8 +47,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
-   param(int, guc_log_level, -1) \
+   param(int, enable_guc, -1) \
+   param(int, guc_log_level, 1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index ddd4f6d..da0554c 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -339,7 +339,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
/* Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
}
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v3 07/12] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Sagar Arun Kamble]

Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.

v2: Add comment about need to synchronize flush work and log runtime
destroy

v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 18d1b49..3a895a3 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -632,7 +632,10 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
+   intel_runtime_pm_get(dev_priv);
intel_disable_guc_interrupts(_priv->guc);
+   intel_runtime_pm_put(dev_priv);
+
intel_guc_log_runtime_destroy(_priv->guc);
mutex_unlock(_priv->drm.struct_mutex);
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v3 05/12] drm/i915/guc: Fix GuC interrupts disabling with logging

[Sagar Arun Kamble]

With guc_log_unregister disabling runtime logging and interrupts, there
is no need to disable interrupts during uc_fini_hw hence it is removed.
With GuC CT buffer mechanism, interrupt disabling can be added later at
a point where CT mechanism ceases.

v2: Rebase.

v3: Moved this patch earlier in the series. (Tvrtko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index f82453b..bc7f549 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -377,7 +377,4 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
intel_guc_submission_disable(guc);
 
guc_disable_communication(guc);
-
-   if (USES_GUC_SUBMISSION(dev_priv))
-   intel_disable_guc_interrupts(guc);
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v3 02/12] drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to intel_guc.c

[Sagar Arun Kamble]

GuC interrupts handling is core GuC functionality. Better to keep it
with other core functions in intel_guc.c. Since they are used from
uC functions, GuC logging and i915 irq handling keeping them grouped in
intel_guc.c instead of intel_uc.c.

v2-v3: Rebase.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  | 70 +--
 drivers/gpu/drm/i915/intel_drv.h |  3 --
 drivers/gpu/drm/i915/intel_guc.c | 71 +++-
 drivers/gpu/drm/i915/intel_guc.h |  4 ++
 drivers/gpu/drm/i915/intel_guc_log.c |  6 +--
 drivers/gpu/drm/i915/intel_uc.c  |  8 ++--
 6 files changed, 81 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a9e1a7..3f4eff9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -203,7 +203,6 @@ static void gen2_assert_iir_is_zero(struct drm_i915_private 
*dev_priv,
 } while (0)
 
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
 
 /* For display hotplug interrupt */
 static inline void
@@ -450,38 +449,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private 
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
 }
 
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
-   spin_unlock_irq(_priv->irq_lock);
-}
-
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   if (!dev_priv->guc.interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   dev_priv->guc.interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
-   spin_unlock_irq(_priv->irq_lock);
-}
-
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   dev_priv->guc.interrupts_enabled = false;
-
-   gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-
-   spin_unlock_irq(_priv->irq_lock);
-   synchronize_irq(dev_priv->drm.irq);
-
-   gen9_reset_guc_interrupts(dev_priv);
-}
-
 /**
  * bdw_update_port_irq - update DE port interrupt
  * @dev_priv: driver private
@@ -1480,7 +1447,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private 
*dev_priv,
gen6_rps_irq_handler(dev_priv, gt_iir[2]);
 
if (gt_iir[2] & dev_priv->pm_guc_events)
-   gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+   intel_guc_irq_handler(dev_priv, gt_iir[2]);
 }
 
 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
@@ -1757,41 +1724,6 @@ static void gen6_rps_irq_handler(struct drm_i915_private 
*dev_priv, u32 pm_iir)
}
 }
 
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
-{
-   if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
-   /* Sample the log buffer flush related bits & clear them out now
-* itself from the message identity register to minimize the
-* probability of losing a flush interrupt, when there are back
-* to back flush interrupts.
-* There can be a new flush interrupt, for different log buffer
-* type (like for ISR), whilst Host is handling one (for DPC).
-* Since same bit is used in message register for ISR & DPC, it
-* could happen that GuC sets the bit for 2nd interrupt but Host
-* clears out the bit on handling the 1st interrupt.
-*/
-   u32 msg, flush;
-
-   msg = I915_READ(SOFT_SCRATCH(15));
-   flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
-  INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
-   if (flush) {
-   /* Clear the message bits that are handled */
-   I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
-   /* Handle flush interrupt in bottom half */
-   queue_work(dev_priv->guc.log.runtime.flush_wq,
-  _priv->guc.log.runtime.flush_work);
-
-   dev_priv->guc.log.flush_interrupt_count++;
-   } else {
-   /* Not clearing of unhandled event bits 

[Intel-gfx] [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

[Sagar Arun Kamble]

GuC interrupts handling functions are GuC specific functions hence update
the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 22 +++---
 drivers/gpu/drm/i915/intel_guc.h |  8 
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-
 drivers/gpu/drm/i915/intel_uc.c  |  8 
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private 
*dev_priv,
gen6_rps_irq_handler(dev_priv, gt_iir[2]);
 
if (gt_iir[2] & dev_priv->pm_guc_events)
-   intel_guc_irq_handler(dev_priv, gt_iir[2]);
+   intel_guc_irq_handler(_priv->guc, gt_iir[2]);
 }
 
 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   intel_disable_guc_interrupts(dev_priv);
+   intel_disable_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
return 0;
 
if (i915_modparams.guc_log_level >= 0)
-   intel_enable_guc_interrupts(dev_priv);
+   intel_enable_guc_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct drm_i915_private 
*dev_priv)
return wopcm_size;
 }
 
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct drm_i915_private 
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;
 
@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct drm_i915_private 
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
synchronize_irq(dev_priv->drm.irq);
 
-   intel_reset_guc_interrupts(dev_priv);
+   intel_reset_guc_interrupts(guc);
 }
 
-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
/* Sample the log buffer flush related bits & clear them out now
 * itself from the message identity register to minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
+void 

[Intel-gfx] [PATCH v3 04/12] drm/i915/guc: Add description and comments about guc_log_level parameter

[Sagar Arun Kamble]

guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info.
in parameter description and documentation.
Earlier, this patch was added to sanitize guc_log_level like old
GuC parameters enable_guc_loading/submission. With new parameter
enable_guc, sanitization of guc_log_level is no more needed.

v2: Added documentation to intel_guc_log.c and param description
about GuC loading dependency. (Michal Wajdeczko)

v3: Removed sanitization of module parameter guc_log_level.
Previous review comments not applicable now.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin  #v2
---
 drivers/gpu/drm/i915/i915_params.c   | 3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b5f3eb4..a93a6ca 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -155,7 +155,8 @@ struct i915_params i915_modparams __read_mostly = {
"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
 
 i915_param_named(guc_log_level, int, 0400,
-   "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+   "GuC firmware logging level. This takes effect only if GuC is to be "
+   "loaded (depends on enable_guc) (-1:disabled (default), 0-3:enabled)");
 
 i915_param_named_unsafe(guc_firmware_path, charp, 0400,
"GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 59a9021..d0131bc 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -34,6 +34,7 @@
  * DOC: GuC firmware log
  *
  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
+ * This takes effect only if GuC is to be loaded based on enable_guc.
  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  * i915_guc_load_status will print out firmware loading status and scratch
  * registers value.
-- 
1.9.1

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[Intel-gfx] [PATCH v3 06/12] drm/i915/guc: Separate creation/release of runtime logging data from base logging data

[Sagar Arun Kamble]

GuC log runtime/relay channel data will get released during i915
unregister, and only GuC log vma needs to be released during fini. To
achieve this, prepare separate helpers to create/destroy base and runtime
logging.
This separation is also needed to couple runtime log data and interrupts
handling together. In future we might not want to consider runtime data
creation failure as catastrophic to abort GuC load. Then we can ignore
the return error codes from intel_guc_log_runtime_create().

v2: Rebase.

v3: Refined usage of intel_guc_log_destroy and created new function
intel_guc_log_runtime_destroy. (Tvrtko)
Added intel_guc_log_runtime_create to separate the creation part as well.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  8 +++-
 drivers/gpu/drm/i915/intel_guc_log.c | 22 --
 drivers/gpu/drm/i915/intel_guc_log.h |  2 ++
 3 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 14bf508d..0184c86 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -168,9 +168,13 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_shared;
 
-   ret = intel_guc_ads_create(guc);
+   ret = intel_guc_log_runtime_create(guc);
if (ret)
goto err_log;
+
+   ret = intel_guc_ads_create(guc);
+   if (ret)
+   goto err_log_runtime;
GEM_BUG_ON(!guc->ads_vma);
 
/* We need to notify the guc whenever we change the GGTT */
@@ -178,6 +182,8 @@ int intel_guc_init(struct intel_guc *guc)
 
return 0;
 
+err_log_runtime:
+   intel_guc_log_runtime_destroy(guc);
 err_log:
intel_guc_log_destroy(guc);
 err_shared:
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index d0131bc..18d1b49 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -357,7 +357,7 @@ static bool guc_log_has_runtime(struct intel_guc *guc)
return guc->log.runtime.buf_addr != NULL;
 }
 
-static int guc_log_runtime_create(struct intel_guc *guc)
+int intel_guc_log_runtime_create(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
void *vaddr;
@@ -365,6 +365,9 @@ static int guc_log_runtime_create(struct intel_guc *guc)
size_t n_subbufs, subbuf_size;
int ret;
 
+   if (i915_modparams.guc_log_level < 0)
+   return 0;
+
lockdep_assert_held(_priv->drm.struct_mutex);
 
GEM_BUG_ON(guc_log_has_runtime(guc));
@@ -420,7 +423,7 @@ static int guc_log_runtime_create(struct intel_guc *guc)
return ret;
 }
 
-static void guc_log_runtime_destroy(struct intel_guc *guc)
+void intel_guc_log_runtime_destroy(struct intel_guc *guc)
 {
/*
 * It's possible that the runtime stuff was never allocated because
@@ -446,7 +449,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
 * handle log buffer flush interrupts would not have been done 
yet,
 * so do that now.
 */
-   ret = guc_log_runtime_create(guc);
+   ret = intel_guc_log_runtime_create(guc);
if (ret)
goto err;
}
@@ -458,7 +461,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
return 0;
 
 err_runtime:
-   guc_log_runtime_destroy(guc);
+   intel_guc_log_runtime_destroy(guc);
 err:
/* logging will remain off */
i915_modparams.guc_log_level = -1;
@@ -536,12 +539,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
guc->log.vma = vma;
 
-   if (i915_modparams.guc_log_level >= 0) {
-   ret = guc_log_runtime_create(guc);
-   if (ret < 0)
-   goto err_vma;
-   }
-
/* each allocated unit is a page */
flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
(GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
@@ -553,8 +550,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
return 0;
 
-err_vma:
-   i915_vma_unpin_and_release(>log.vma);
 err:
/* logging will be off */
i915_modparams.guc_log_level = -1;
@@ -563,7 +558,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
 void intel_guc_log_destroy(struct intel_guc *guc)
 {
-   guc_log_runtime_destroy(guc);
i915_vma_unpin_and_release(>log.vma);
 }
 
@@ -639,6 +633,6 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */

[Intel-gfx] [PATCH v3 01/12] drm/i915: Export low level PM IRQ functions to use from GuC functions

[Sagar Arun Kamble]

In order to separate GuC IRQ handling functions from i915_irq.c we need
to export the low level pm irq handlers. Export pm_iir, reset_pm_iir and
enable/disable_pm_irq functions.

v2-v3: Rebase.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  | 8 
 drivers/gpu/drm/i915/intel_drv.h | 4 
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c65..7a9e1a7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -306,7 +306,7 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, 
uint32_t mask)
ilk_update_gt_irq(dev_priv, mask, 0);
 }
 
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
+i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
@@ -369,7 +369,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, 
u32 mask)
__gen6_mask_pm_irq(dev_priv, mask);
 }
 
-static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 
reset_mask)
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 {
i915_reg_t reg = gen6_pm_iir(dev_priv);
 
@@ -380,7 +380,7 @@ static void gen6_reset_pm_iir(struct drm_i915_private 
*dev_priv, u32 reset_mask)
POSTING_READ(reg);
 }
 
-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 
enable_mask)
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 {
lockdep_assert_held(_priv->irq_lock);
 
@@ -390,7 +390,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private 
*dev_priv, u32 enable_mas
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 }
 
-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 
disable_mask)
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 {
lockdep_assert_held(_priv->irq_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f..3a7e18c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1234,8 +1234,12 @@ void intel_pch_fifo_underrun_irq_handler(struct 
drm_i915_private *dev_priv,
 /* i915_irq.c */
 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv);
 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask);
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask);
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask);
 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH v3 00/12] GuC Interrupts/Log updates

[Sagar Arun Kamble]

This series addresses following features/fixes:
1. Restructuring to move GuC interrupts related functions to guc.c
2. Making GuC interrupts enable/disable reference based and tying up with
   logging at all places.
3. Handle suspend/resume/reset for GuC interrupts.
4. Logging fixes about RPM wakeref and skipping relay release during
   uc_fini.

Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Radoslaw Szwichtenberg 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 

Sagar Arun Kamble (12):
  drm/i915: Export low level PM IRQ functions to use from GuC functions
  drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to
intel_guc.c
  drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts
functions
  drm/i915/guc: Add description and comments about guc_log_level
parameter
  drm/i915/guc: Fix GuC interrupts disabling with logging
  drm/i915/guc: Separate creation/release of runtime logging data from
base logging data
  drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts
  drm/i915/guc: Make guc_log_level parameter immutable
  drm/i915/guc: Make GuC log related functions depend only on log level
  drm/i915/guc: Add client support to enable/disable GuC interrupts
  drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled
  HAX: drm/i915/guc: enable GuC submission/logging for CI

 drivers/gpu/drm/i915/i915_debugfs.c  |   8 +-
 drivers/gpu/drm/i915/i915_drv.c  |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  |   8 +-
 drivers/gpu/drm/i915/i915_irq.c  |  78 ++-
 drivers/gpu/drm/i915/i915_params.c   |   3 +-
 drivers/gpu/drm/i915/i915_params.h   |   4 +-
 drivers/gpu/drm/i915/intel_display.c |   2 +
 drivers/gpu/drm/i915/intel_drv.h |   7 +-
 drivers/gpu/drm/i915/intel_guc.c | 141 +--
 drivers/gpu/drm/i915/intel_guc.h |  13 +++-
 drivers/gpu/drm/i915/intel_guc_log.c |  64 +++-
 drivers/gpu/drm/i915/intel_guc_log.h |   8 ++
 drivers/gpu/drm/i915/intel_uc.c  |  29 ---
 13 files changed, 225 insertions(+), 144 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PULL] drm-intel-fixes

[Jani Nikula]

Hi Dave, some more i915 fixes for the new year.

drm-intel-fixes-2018-01-04:
drm/i915 fixes for v4.15-rc7
- couple of documentation build fixes
- serialize non-blocking modesets
- prevent DMC from messing up GMBUS transfers
- PSR regression fix

BR,
Jani.

The following changes since commit 30a7acd573899fd8b8ac39236eff6468b195ac7d:

  Linux 4.15-rc6 (2017-12-31 14:47:43 -0800)

are available in the git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-01-04

for you to fetch changes up to 30414f3010aff95ffdb6bed7b9dce62cde94fdc7:

  drm/i915: Apply Display WA #1183 on skl, kbl, and cfl (2018-01-04 14:39:08 
+0200)


drm/i915 fixes for v4.15-rc7
- couple of documentation build fixes
- serialize non-blocking modesets
- prevent DMC from messing up GMBUS transfers
- PSR regression fix


Dhinakaran Pandiyan (1):
  drm/i915/psr: Fix register name mess up.

Lucas De Marchi (1):
  drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

Markus Heiser (1):
  docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c

Randy Dunlap (1):
  documentation/gpu/i915: fix docs build error after file rename

Ville Syrjälä (2):
  drm/i915: Disable DC states around GMBUS on GLK
  drm/i915: Put all non-blocking modesets onto an ordered wq

 Documentation/gpu/i915.rst  |  5 +
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 drivers/gpu/drm/i915/intel_cdclk.c  | 35 -
 drivers/gpu/drm/i915/intel_display.c| 14 ++---
 drivers/gpu/drm/i915/intel_psr.c| 16 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++
 7 files changed, 62 insertions(+), 24 deletions(-)

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] linux-firmware Pull Request (CNL:DMC)

[Josh Boyer]

On Tue, Jan 2, 2018 at 2:10 PM, Anusha Srivatsa
 wrote:
> Hi Josh, Ben, Kyle,
>
> Please consider pulling i915 updates to linux-firmware.git.
> The following changes since commit 2567e092339cd3403d697dc2e0967c31b7acb989:
>
>   nvidia: add GP108 signed firmware (2017-12-21 08:08:05 -0500)
>
> are available in the git repository at:
>
>   https://cgit.freedesktop.org/drm/drm-firmware/ master
>
> for you to fetch changes up to 4a77cab4a02712fc7b37b55c120eec61fe7e3f32:
>
>   linux-firmware: DMC firmware for cannonlake v1.07 (2018-01-02 10:52:43 
> -0800)
>
> 
> Anusha Srivatsa (1):
>   linux-firmware: DMC firmware for cannonlake v1.07
>
>  WHENCE   |   2 ++
>  i915/cnl_dmc_ver1_07.bin | Bin 0 -> 11268 bytes
>  2 files changed, 2 insertions(+)
>  create mode 100644 i915/cnl_dmc_ver1_07.bin

Merged and pushed out.  Thanks.

josh
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[Intel-gfx] ✓ Fi.CI.IGT: success for test/kms_psr_sink : HACK test if psr_drrs also need test_cleanup

[Patchwork]

== Series Details ==

Series: test/kms_psr_sink : HACK test if psr_drrs also need test_cleanup
URL   : https://patchwork.freedesktop.org/series/36004/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb) fdo#101623
Subgroup fbc-2p-primscrn-pri-shrfb-draw-pwrite:
incomplete -> SKIP   (shard-hsw) fdo#104218
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> INCOMPLETE (shard-hsw) fdo#103990

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103990 https://bugs.freedesktop.org/show_bug.cgi?id=103990

shard-hswtotal:2692 pass:1527 dwarn:1   dfail:0   fail:11  skip:1152 
time:8895s
shard-snbtotal:2713 pass:1309 dwarn:1   dfail:0   fail:12  skip:1391 
time:7863s
Blacklisted hosts:
shard-apltotal:2713 pass:1685 dwarn:1   dfail:0   fail:26  skip:1001 
time:13380s
shard-kbltotal:2713 pass:1797 dwarn:7   dfail:1   fail:28  skip:880 
time:10508s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_744/shards.html
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Re: [Intel-gfx] [PATCH i-g-t 1/6] i-g-t: kms_plane_scaling: Fix basic scaling test

[Maarten Lankhorst]

Op 13-12-17 om 10:50 schreef Vidya Srinivas:
> From: Mahesh Kumar 
>
> PIPEC doesnt have 3rd plane in GEN9. So, we skip the
> 3rd plane related scaling test where 2nd OVERLAY
> plane is not available.
>
> Restricting downscaling to (9/10)x original size of the
> image to avoid "Max pixel rate limitation" of the hardware.
>
> Later patches in this series will cover corner cases of
> scaling.
>
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Jyoti Yadav 
> Signed-off-by: Vidya Srinivas 
> ---
>  tests/kms_plane_scaling.c | 234 
> +-
>  1 file changed, 125 insertions(+), 109 deletions(-)
>
> diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
> index 403df47..a827cb3 100644
> --- a/tests/kms_plane_scaling.c
> +++ b/tests/kms_plane_scaling.c
> @@ -163,144 +163,159 @@ static void iterate_plane_scaling(data_t *d, 
> drmModeModeInfo *mode)
>   }
>  }

The scaler tests should really require display->is_atomic. Even if there are
theoretically more limits on the amount of scalers, having a YUV mode or 
interlaced
mode may take a scaler, causing this test to fail.

With try_commit_atomic, it would be possible to test if enough scalers are 
available.

On top of that, I would really like the test to be more readable, and having
test_plane_scaling_on_pipe split up in smaller pieces would accomplish that.

I would do some split ups first before doing any fixes, it's hard to read what's
changed through the whitespace changes, even if the code is correct.

Also this test needs to be split up into subtests, this is a good start for it.

Replace igt_simple_main with igt_main, and add subtests for each pipe and 
various
tests being performed. See for example kms_color, this test is already trying 
to do too
much in one go. :)

~Maarten

>  
> -static void test_plane_scaling(data_t *d)
> +static void
> +test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, igt_output_t *output)
>  {
>   igt_display_t *display = >display;
> - igt_output_t *output;
> - enum pipe pipe;
> - int valid_tests = 0;
> + drmModeModeInfo *mode;
>   int primary_plane_scaling = 0; /* For now */
>  
> - igt_require(d->num_scalers);
> + igt_output_set_pipe(output, pipe);
> + mode = igt_output_get_mode(output);
> +
> + /* allocate fb2 with image size */
> + d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
> + DRM_FORMAT_XRGB,
> + LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
> + FILE_NAME, >fb2);
> + igt_assert(d->fb_id2);
> +
> + d->fb_id3 = igt_create_pattern_fb(d->drm_fd,
> + mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB,
> + LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
> + >fb3);
> + igt_assert(d->fb_id3);
> +
> + /* Set up display with plane 1 */
> + d->plane1 = igt_output_get_plane(output, 0);
> + prepare_crtc(d, output, pipe, d->plane1, mode, COMMIT_UNIVERSAL);
> +
> + if (primary_plane_scaling) {
> + /* Primary plane upscaling */
> + igt_fb_set_position(>fb1, d->plane1, 100, 100);
> + igt_fb_set_size(>fb1, d->plane1, 500, 500);
> + igt_plane_set_position(d->plane1, 0, 0);
> + igt_plane_set_size(d->plane1, mode->hdisplay, mode->vdisplay);
> + igt_display_commit2(display, COMMIT_UNIVERSAL);
>  
> - for_each_pipe_with_valid_output(display, pipe, output) {
> - drmModeModeInfo *mode;
> -
> - igt_output_set_pipe(output, pipe);
> -
> - mode = igt_output_get_mode(output);
> -
> - /* allocate fb2 with image size */
> - d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
> - DRM_FORMAT_XRGB,
> - LOCAL_I915_FORMAT_MOD_X_TILED, 
> /* tiled */
> - FILE_NAME, >fb2);
> - igt_assert(d->fb_id2);
> -
> - d->fb_id3 = igt_create_pattern_fb(d->drm_fd,
> -   mode->hdisplay, 
> mode->vdisplay,
> -   DRM_FORMAT_XRGB,
> -   
> LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
> -   >fb3);
> - igt_assert(d->fb_id3);
> -
> - /* Set up display with plane 1 */
> - d->plane1 = igt_output_get_plane(output, 0);
> - prepare_crtc(d, output, pipe, d->plane1, mode, 
> COMMIT_UNIVERSAL);
> -
> - if (primary_plane_scaling) {
> - /* Primary plane upscaling */
> - igt_fb_set_position(>fb1, d->plane1, 100, 100);
> - igt_fb_set_size(>fb1, 

[Intel-gfx] ✓ Fi.CI.BAT: success for kms_vblank: Move tests over from kms_flip. (rev2)

[Patchwork]

== Series Details ==

Series: kms_vblank: Move tests over from kms_flip. (rev2)
URL   : https://patchwork.freedesktop.org/series/36006/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3598
eb3dae33ff20 drm-tip: 2018y-01m-04d-13h-53m-17s UTC integration manifest

Testlist changes:
+++ 156 lines
--- 65 lines

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:432s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:477s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:264s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:577s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:517s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:609s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:475s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_746/issues.html
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[Intel-gfx] [PATCH i-g-t v2 0/6] kms_vblank: Move tests over from kms_flip.

[Maarten Lankhorst]

kms_flip is meant for finding issues with page flip, but was used for
finding bugs in the vblank ioctl too. Move over some tests from kms_flip
to kms_vblank, and reduce their runtime to a minimum.

Changes since v1:
- Rebase on top of current head so the changes to kms_flip apply.
- Move hang test moving until after kms_vblank reorganization, for clarity.

Maarten Lankhorst (6):
  tests/kms_flip: Remove blt/rcs flip tests.
  kms_vblank: Reorganize subtests by pipe
  tests/kms_flip: Move kms_flip.vblank-vs-hang to kms_vblank, v2.
  kms_vblank: Add tests implemented in kms_flip
  kms_flip: Remove redundant vblank tests.
  kms_vblank: Remove teardown code from cleanup_crtc

 tests/kms_flip.c   |  58 +--
 tests/kms_vblank.c | 205 +++--
 2 files changed, 152 insertions(+), 111 deletions(-)

-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 2/6] kms_vblank: Reorganize subtests by pipe

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 93 --
 1 file changed, 49 insertions(+), 44 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 342e4ef23b97..e51e96c7f061 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -118,49 +118,41 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
int nchildren =
data->flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
igt_display_t *display = >display;
-   igt_output_t *output;
-   enum pipe p;
+   igt_output_t *output = data->output;
 
-   for_each_pipe_with_valid_output(display, p, output) {
-   data->pipe = p;
-   prepare_crtc(data, fd, output);
+   prepare_crtc(data, fd, output);
 
-   igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
-igt_subtest_name(),
-kmstest_pipe_name(data->pipe),
-igt_output_name(output),
-nchildren);
-
-   if (data->flags & BUSY) {
-   union drm_wait_vblank vbl;
-
-   memset(, 0, sizeof(vbl));
-   vbl.request.type =
-   DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
-   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
-   vbl.request.sequence = 120 + 12;
-   igt_assert_eq(wait_vblank(fd, ), 0);
-   }
+   igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
+igt_subtest_name(), kmstest_pipe_name(data->pipe),
+igt_output_name(output), nchildren);
 
-   igt_fork(child, nchildren)
-   testfunc(data, fd, nchildren);
-   igt_waitchildren();
-
-   if (data->flags & BUSY) {
-   struct drm_event_vblank buf;
-   igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
-   }
+   if (data->flags & BUSY) {
+   union drm_wait_vblank vbl;
 
-   igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
+   memset(, 0, sizeof(vbl));
+   vbl.request.type =
+   DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
+   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
+   vbl.request.sequence = 120 + 12;
+   igt_assert_eq(wait_vblank(fd, ), 0);
+   }
 
-   igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
-igt_subtest_name(),
-kmstest_pipe_name(data->pipe),
-igt_output_name(output));
+   igt_fork(child, nchildren)
+   testfunc(data, fd, nchildren);
+   igt_waitchildren();
 
-   /* cleanup what prepare_crtc() has done */
-   cleanup_crtc(data, fd, output);
+   if (data->flags & BUSY) {
+   struct drm_event_vblank buf;
+   igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
}
+
+   igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
+
+   igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
+igt_subtest_name(), kmstest_pipe_name(data->pipe), 
igt_output_name(output));
+
+   /* cleanup what prepare_crtc() has done */
+   cleanup_crtc(data, fd, output);
 }
 
 static void crtc_id_subtest(data_t *data, int fd)
@@ -329,6 +321,8 @@ igt_main
{ "wait", vblank_wait, IDLE | FORKED | BUSY },
{ }
}, *f;
+   enum pipe p;
+
const struct {
const char *name;
unsigned int flags;
@@ -352,14 +346,25 @@ igt_main
igt_subtest("crtc-id")
crtc_id_subtest(, fd);
 
-   for (f = funcs; f->name; f++) {
-   for (m = modes; m->name; m++) {
-   if (m->flags & ~f->valid)
-   continue;
-
-   igt_subtest_f("%s-%s", f->name, m->name) {
-   data.flags = m->flags;
-   run_test(, fd, f->func);
+   for_each_pipe_static(p) igt_subtest_group {
+   igt_fixture
+   igt_display_require_output_on_pipe(, p);
+
+   data.pipe = p;
+
+   for (f = funcs; f->name; f++) {
+   for (m = modes; m->name; m++) {
+   if (m->flags & ~f->valid)
+   continue;
+
+   igt_subtest_f("pipe-%s-%s-%s",
+ kmstest_pipe_name(data.pipe),
+ f->name, m->name) {
+   
for_each_valid_output_on_pipe(, data.pipe, 

[Intel-gfx] [PATCH i-g-t v2 4/6] kms_vblank: Add tests implemented in kms_flip

[Maarten Lankhorst]

In kms_flip there are some tests for testing whether the
vblank counter is monotonically increasing. Add these subtests
to kms_vblank, where they belong.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 84 +++---
 1 file changed, 80 insertions(+), 4 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 959ba46ca30f..362221c03677 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -51,10 +51,14 @@ typedef struct {
igt_output_t *output;
enum pipe pipe;
unsigned int flags;
-#define IDLE 1
-#define BUSY 2
-#define FORKED 4
-#define NOHANG 8
+#define IDLE   0x1
+#define BUSY   0x2
+#define FORKED 0x4
+#define NOHANG 0x8
+#define MODESET 0x10
+#define DPMS   0x20
+#define SUSPEND 0x40
+#define RPM0x80
 } data_t;
 
 static double elapsed(const struct timespec *start,
@@ -124,6 +128,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 
prepare_crtc(data, fd, output);
 
+   if (data->flags & RPM)
+   igt_require(igt_setup_runtime_pm());
+
igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
 igt_subtest_name(), kmstest_pipe_name(data->pipe),
 igt_output_name(output), nchildren);
@@ -315,6 +322,69 @@ static void vblank_wait(data_t *data, int fd, int 
nchildren)
 elapsed(, , count));
 }
 
+static int get_vblank(int fd, enum pipe pipe, unsigned flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | kmstest_get_vbl_flag(pipe) | 
flags;
+   do_or_die(igt_ioctl(fd, DRM_IOCTL_WAIT_VBLANK, ));
+
+   return vbl.reply.sequence;
+}
+
+static void vblank_ts_cont(data_t *data, int fd, int nchildren)
+{
+   igt_display_t *display = >display;
+   igt_output_t *output = data->output;
+   int seq1, seq2;
+   union drm_wait_vblank vbl;
+
+   seq1 = get_vblank(fd, data->pipe, 0);
+
+   if (data->flags & DPMS) {
+   igt_output_set_prop_value(output, IGT_CONNECTOR_DPMS, 
DRM_MODE_DPMS_OFF);
+   igt_display_commit(display);
+   }
+
+   if (data->flags & MODESET) {
+   igt_output_set_pipe(output, PIPE_NONE);
+   igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+   }
+
+   if (data->flags & RPM)
+   
igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED));
+
+   if (data->flags & SUSPEND)
+   igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_NONE);
+
+   if (data->flags & (MODESET | DPMS)) {
+   /* Attempting to do a vblank while disabled should return 
-EINVAL */
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE;
+   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
+   igt_assert_eq(wait_vblank(fd, ), -EINVAL);
+   }
+
+   if (data->flags & DPMS) {
+   igt_output_set_prop_value(output, IGT_CONNECTOR_DPMS, 
DRM_MODE_DPMS_ON);
+   igt_display_commit(display);
+   }
+
+   if (data->flags & MODESET) {
+   igt_output_set_pipe(output, data->pipe);
+   igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+   }
+
+   seq2 = get_vblank(fd, data->pipe, 0);
+
+   igt_debug("testing ts continuity: Current frame %u, old frame %u\n", 
seq2, seq1);
+
+   igt_assert_f(seq2 - seq1 >= 0, "unexpected vblank seq %u, should be >= 
%u\n", seq2, seq1);
+   igt_assert_f(seq2 - seq1 <= 150, "unexpected vblank seq %u, should be < 
%u\n", seq2, seq1 + 150);
+}
+
 igt_main
 {
int fd;
@@ -327,6 +397,7 @@ igt_main
{ "accuracy", accuracy, IDLE },
{ "query", vblank_query, IDLE | FORKED | BUSY },
{ "wait", vblank_wait, IDLE | FORKED | BUSY },
+   { "ts-continuation", vblank_ts_cont, IDLE | SUSPEND | MODESET | 
DPMS | RPM },
{ }
}, *f;
enum pipe p;
@@ -339,6 +410,11 @@ igt_main
{ "forked", IDLE | FORKED },
{ "busy", BUSY },
{ "forked-busy", BUSY | FORKED },
+   { "dpms-rpm", DPMS | RPM | NOHANG },
+   { "dpms-suspend", DPMS | SUSPEND | NOHANG},
+   { "suspend", SUSPEND | NOHANG },
+   { "modeset", MODESET },
+   { "modeset-rpm", MODESET | RPM | NOHANG},
{ }
}, *m;
 
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 3/6] tests/kms_flip: Move kms_flip.vblank-vs-hang to kms_vblank, v2.

[Maarten Lankhorst]

There's no need to test this more than once. Add a NOHANG
flag which can be used to specify that a subtest can not
be run when hanging. If it's set on either the subtest or
the mode, the -hang test for this combination will not be
generated.

Changes since v1:
- Merge the patch that renamed HANG to NOHANG.
- Rebase after 'reorganize subtests by type'.
- Allow subtests to specify NOHANG too.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c   | 10 +-
 tests/kms_vblank.c | 23 ++-
 2 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 7689e65b521a..50c16b0debbf 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -72,7 +72,7 @@
 #define TEST_SUSPEND   (1 << 26)
 #define TEST_TS_CONT   (1 << 27)
 #define TEST_BO_TOOBIG (1 << 28)
-#define TEST_HANG_ONCE (1 << 29)
+
 #define TEST_BASIC (1 << 30)
 
 #define EVENT_FLIP (1 << 0)
@@ -1071,13 +1071,8 @@ static unsigned int wait_for_events(struct test_output 
*o)
 static unsigned event_loop(struct test_output *o, unsigned duration_ms)
 {
unsigned long start, end;
-   igt_hang_t hang;
int count = 0;
 
-   memset(, 0, sizeof(hang));
-   if (o->flags & TEST_HANG_ONCE)
-   hang = hang_gpu(drm_fd);
-
start = gettime_us();
 
while (1) {
@@ -1097,8 +1092,6 @@ static unsigned event_loop(struct test_output *o, 
unsigned duration_ms)
 
end = gettime_us();
 
-   unhang_gpu(drm_fd, hang);
-
/* Flush any remaining events */
if (o->pending_events)
wait_for_events(o);
@@ -1565,7 +1558,6 @@ int main(int argc, char **argv)
TEST_CHECK_TS, "flip-vs-blocking-wf-vblank" },
{ 30, TEST_FLIP | TEST_MODESET | TEST_HANG | TEST_NOEVENT, 
"flip-vs-modeset-vs-hang" },
{ 30, TEST_FLIP | TEST_PAN | TEST_HANG, 
"flip-vs-panning-vs-hang" },
-   { 30, TEST_VBLANK | TEST_HANG_ONCE, "vblank-vs-hang" },
{ 1, TEST_FLIP | TEST_EINVAL | TEST_FB_BAD_TILING, 
"flip-vs-bad-tiling" },
 
{ 1, TEST_DPMS_OFF | TEST_MODESET | TEST_FLIP,
diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index e51e96c7f061..959ba46ca30f 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -54,6 +54,7 @@ typedef struct {
 #define IDLE 1
 #define BUSY 2
 #define FORKED 4
+#define NOHANG 8
 } data_t;
 
 static double elapsed(const struct timespec *start,
@@ -119,6 +120,7 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
data->flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
igt_display_t *display = >display;
igt_output_t *output = data->output;
+   igt_hang_t hang;
 
prepare_crtc(data, fd, output);
 
@@ -126,6 +128,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 igt_subtest_name(), kmstest_pipe_name(data->pipe),
 igt_output_name(output), nchildren);
 
+   if (!(data->flags & NOHANG))
+   hang = igt_hang_ring(display->drm_fd, I915_EXEC_DEFAULT);
+
if (data->flags & BUSY) {
union drm_wait_vblank vbl;
 
@@ -148,6 +153,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 
igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
 
+   if (!(data->flags & NOHANG))
+   igt_post_hang_ring(fd, hang);
+
igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
 igt_subtest_name(), kmstest_pipe_name(data->pipe), 
igt_output_name(output));
 
@@ -354,12 +362,25 @@ igt_main
 
for (f = funcs; f->name; f++) {
for (m = modes; m->name; m++) {
-   if (m->flags & ~f->valid)
+   if (m->flags & ~(f->valid | NOHANG))
continue;
 
igt_subtest_f("pipe-%s-%s-%s",
  kmstest_pipe_name(data.pipe),
  f->name, m->name) {
+   
for_each_valid_output_on_pipe(, data.pipe, data.output) {
+   data.flags = m->flags | NOHANG;
+   run_test(, fd, f->func);
+   }
+   }
+
+   /* Skip the -hang version if NOHANG flag is set 
*/
+   if (f->valid & NOHANG || m->flags & NOHANG)
+   continue;
+
+   igt_subtest_f("pipe-%s-%s-%s-hang",
+ kmstest_pipe_name(data.pipe),
+ f->name, m->name) {

[Intel-gfx] [PATCH i-g-t v2 1/6] tests/kms_flip: Remove blt/rcs flip tests.

[Maarten Lankhorst]

With the removal of mmio flips, blt and rcs flips are no longer
different from doing busy testing in kms_busy.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c | 40 +---
 1 file changed, 1 insertion(+), 39 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 2899f20e6c73..7689e65b521a 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -45,8 +45,7 @@
 #include "igt_stats.h"
 
 #define TEST_DPMS  (1 << 0)
-#define TEST_WITH_DUMMY_BCS(1 << 1)
-#define TEST_WITH_DUMMY_RCS(1 << 2)
+
 #define TEST_PAN   (1 << 3)
 #define TEST_MODESET   (1 << 4)
 #define TEST_CHECK_TS  (1 << 5)
@@ -668,8 +667,6 @@ static unsigned int run_test_step(struct test_output *o)
struct vblank_reply vbl_reply;
unsigned int target_seq;
igt_hang_t hang;
-   igt_spin_t *spin_rcs = 0;
-   igt_spin_t *spin_bcs = 0;
 
target_seq = o->vblank_state.seq_step;
/* Absolute waits only works once we have a frame counter. */
@@ -691,20 +688,6 @@ static unsigned int run_test_step(struct test_output *o)
if (!(o->flags & TEST_SINGLE_BUFFER))
o->current_fb_id = !o->current_fb_id;
 
-   if (o->flags & TEST_WITH_DUMMY_BCS) {
-   spin_bcs = __igt_spin_batch_new(drm_fd, 0, I915_EXEC_BLT,
-   
o->fb_info[o->current_fb_id].gem_handle);
-   igt_spin_batch_set_timeout(spin_bcs,
-  NSEC_PER_SEC);
-   }
-
-   if (o->flags & TEST_WITH_DUMMY_RCS) {
-   spin_rcs = __igt_spin_batch_new(drm_fd, 0, I915_EXEC_RENDER,
-   
o->fb_info[o->current_fb_id].gem_handle);
-   igt_spin_batch_set_timeout(spin_rcs,
-  NSEC_PER_SEC);
-   }
-
if (o->flags & TEST_FB_RECREATE)
recreate_fb(o);
new_fb_id = o->fb_ids[o->current_fb_id];
@@ -809,10 +792,6 @@ static unsigned int run_test_step(struct test_output *o)
completed_events = EVENT_VBLANK;
}
}
-   if (spin_rcs)
-   igt_spin_batch_free(drm_fd, spin_rcs);
-   if (spin_bcs)
-   igt_spin_batch_free(drm_fd, spin_bcs);
 
if (do_flip && (o->flags & TEST_EBUSY))
igt_assert(do_page_flip(o, new_fb_id, true) == -EBUSY);
@@ -1065,10 +1044,6 @@ static unsigned int wait_for_events(struct test_output 
*o)
evctx.vblank_handler = vblank_handler;
evctx.page_flip_handler = page_flip_handler;
 
-   /* make timeout lax with the dummy load */
-   if (o->flags & (TEST_WITH_DUMMY_BCS | TEST_WITH_DUMMY_RCS))
-   timeout.tv_sec *= 60;
-
FD_ZERO();
FD_SET(drm_fd, );
do {
@@ -1099,9 +1074,6 @@ static unsigned event_loop(struct test_output *o, 
unsigned duration_ms)
igt_hang_t hang;
int count = 0;
 
-   if (o->flags & (TEST_WITH_DUMMY_BCS | TEST_WITH_DUMMY_RCS))
-   igt_require_gem(drm_fd);
-
memset(, 0, sizeof(hang));
if (o->flags & TEST_HANG_ONCE)
hang = hang_gpu(drm_fd);
@@ -1571,15 +1543,7 @@ int main(int argc, char **argv)
{ 30,  TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_VBLANK_ABSOLUTE,
"blocking-absolute-wf_vblank" },
{ 60,  TEST_VBLANK | TEST_DPMS | TEST_EINVAL, 
"wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_WITH_DUMMY_BCS,
-   "blt-wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_WITH_DUMMY_RCS,
-   "rcs-wf_vblank-vs-dpms" },
{ 60,  TEST_VBLANK | TEST_MODESET | TEST_EINVAL, 
"wf_vblank-vs-modeset" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_WITH_DUMMY_BCS,
-   "blt-wf_vblank-vs-modeset" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_WITH_DUMMY_RCS,
-   "rcs-wf_vblank-vs-modeset" },
{ 10, TEST_FLIP | TEST_BASIC, "plain-flip" },
{ 30, TEST_FLIP | TEST_EBUSY , "busy-flip" },
{ 30, TEST_FLIP | TEST_FENCE_STRESS , "flip-vs-fences" },
@@ -1589,8 +1553,6 @@ int main(int argc, char **argv)
{ 30, TEST_FLIP | TEST_RMFB | TEST_MODESET , "flip-vs-rmfb" },
{ 20, TEST_FLIP | TEST_DPMS | TEST_EINVAL | TEST_BASIC, 
"flip-vs-dpms" },
{ 30,  TEST_FLIP | TEST_PAN, "flip-vs-panning" },
-   { 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_BCS, 
"blt-flip-vs-panning" },
-   { 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_RCS, 
"render-flip-vs-panning" },
{ 20, TEST_FLIP | TEST_MODESET | TEST_EINVAL | TEST_BASIC, 
"flip-vs-modeset" },
  

[Intel-gfx] [PATCH i-g-t v2 5/6] kms_flip: Remove redundant vblank tests.

[Maarten Lankhorst]

wf_vblank is redundant with wf_vblank-ts-check, which also performs
a check but runs in the same way.

The -EINVAL vblank tests are reproduced in kms_vblank, as are the
vblank-vs-* tests.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 50c16b0debbf..710ea52b4a8a 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -1527,7 +1527,6 @@ int main(int argc, char **argv)
int flags;
const char *name;
} tests[] = {
-   { 30, TEST_VBLANK, "wf_vblank" },
{ 30, TEST_VBLANK | TEST_CHECK_TS, "wf_vblank-ts-check" },
{ 30, TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_CHECK_TS,
"blocking-wf_vblank" },
@@ -1535,8 +1534,6 @@ int main(int argc, char **argv)
"absolute-wf_vblank" },
{ 30,  TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_VBLANK_ABSOLUTE,
"blocking-absolute-wf_vblank" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_EINVAL, 
"wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_EINVAL, 
"wf_vblank-vs-modeset" },
{ 10, TEST_FLIP | TEST_BASIC, "plain-flip" },
{ 30, TEST_FLIP | TEST_EBUSY , "busy-flip" },
{ 30, TEST_FLIP | TEST_FENCE_STRESS , "flip-vs-fences" },
@@ -1568,11 +1565,6 @@ int main(int argc, char **argv)
{ 0, TEST_ENOENT | TEST_NOEVENT, "nonexisting-fb" },
{ 10, TEST_DPMS_OFF | TEST_DPMS | TEST_VBLANK_RACE, 
"dpms-vs-vblank-race" },
{ 10, TEST_MODESET | TEST_VBLANK_RACE, "modeset-vs-vblank-race" 
},
-   { 10, TEST_VBLANK | TEST_DPMS | TEST_RPM | TEST_TS_CONT, 
"vblank-vs-dpms-rpm" },
-   { 10, TEST_VBLANK | TEST_MODESET | TEST_RPM | TEST_TS_CONT, 
"vblank-vs-modeset-rpm" },
-   { 0, TEST_VBLANK | TEST_DPMS | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-dpms-suspend" },
-   { 0, TEST_VBLANK | TEST_MODESET | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-modeset-suspend" },
-   { 0, TEST_VBLANK | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-suspend" },
{ 0, TEST_BO_TOOBIG | TEST_NO_2X_OUTPUT, "bo-too-big" },
};
int i;
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 6/6] kms_vblank: Remove teardown code from cleanup_crtc

[Maarten Lankhorst]

New way of doing things is calling igt_display_reset() before any
setup code. This way if the configuration stays the same, the initial
modeset will be a noop.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 362221c03677..d2154f1c7605 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -74,6 +74,8 @@ static void prepare_crtc(data_t *data, int fd, igt_output_t 
*output)
igt_display_t *display = >display;
igt_plane_t *primary;
 
+   igt_display_reset(display);
+
/* select the pipe we want to use */
igt_output_set_pipe(output, data->pipe);
 
@@ -95,16 +97,7 @@ static void prepare_crtc(data_t *data, int fd, igt_output_t 
*output)
 
 static void cleanup_crtc(data_t *data, int fd, igt_output_t *output)
 {
-   igt_display_t *display = >display;
-   igt_plane_t *primary;
-
igt_remove_fb(fd, >primary_fb);
-
-   primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
-   igt_plane_set_fb(primary, NULL);
-
-   igt_output_set_pipe(output, PIPE_ANY);
-   igt_display_commit(display);
 }
 
 static int wait_vblank(int fd, union drm_wait_vblank *vbl)
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Marta Lofstedt]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260

Signed-off-by: Marta Lofstedt 
---
 tests/kms_psr_sink_crc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 83a69f0b..26cf434a 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -532,11 +532,13 @@ int main(int argc, char *argv[])
igt_subtest("psr_basic") {
setup_test_plane();
igt_assert(wait_psr_entry());
+   test_cleanup();
}
 
igt_subtest("psr_drrs") {
setup_test_plane();
igt_assert(drrs_disabled());
+   test_cleanup();
}
 
for (op = PAGE_FLIP; op <= RENDER; op++) {
-- 
2.11.0

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Re: [Intel-gfx] [PATCH i-g-t] test/kms_psr_sink_crc - Hack to test test_cleanup() for psr_basic

[Lofstedt, Marta]

Doesn't look like it is needed for the psr_drrs

https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_744/all.html

From: Lofstedt, Marta
Sent: Thursday, January 04, 2018 1:37 PM
To: Latvala, Petri
Cc: intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH i-g-t] test/kms_psr_sink_crc - Hack to test 
test_cleanup() for psr_basic

> -Original Message-
> From: Latvala, Petri
> Sent: Thursday, January 4, 2018 2:11 PM
> To: Lofstedt, Marta 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH i-g-t] test/kms_psr_sink_crc - Hack to test
> test_cleanup() for psr_basic
>
> On Thu, Jan 04, 2018 at 12:54:34PM +0200, Marta Lofstedt wrote:
> > The "*ERROR* Potential atomic update failure on pipe A"
> > started to occure on some BAT machines with IGT_4063.
> > Looking at the dmesgs the ERROR print come when the subtest is
> > exiting. So, this is just a longshot to test if we may need to do the
> > cleanup on this subtest as well.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260
> >
> > Signed-off-by: Marta Lofstedt 
> > ---
> >  tests/kms_psr_sink_crc.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c index
> > 83a69f0b..7ee4c2f4 100644
> > --- a/tests/kms_psr_sink_crc.c
> > +++ b/tests/kms_psr_sink_crc.c
> > @@ -532,6 +532,7 @@ int main(int argc, char *argv[])
> > igt_subtest("psr_basic") {
> > setup_test_plane();
> > igt_assert(wait_psr_entry());
> > +   test_cleanup();
> > }
>
>
> This looks correct indeed.
>
>
> >
> > igt_subtest("psr_drrs") {
>
>
> But the same is required here, isn't it?

Probably, but it is green on GLK-shards which is the only machine currently 
running it. By the way it's the only green PSR related tests on GLK-shards...
I guess I could do a fastfeedback.testlist hack to BAT to see if it fails there 
on some machine.

>
>
>
> --
> Petri Latvala
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[Intel-gfx] ✗ Fi.CI.BAT: failure for kms_vblank: Move tests over from kms_flip.

[Patchwork]

== Series Details ==

Series: kms_vblank: Move tests over from kms_flip.
URL   : https://patchwork.freedesktop.org/series/36006/
State : failure

== Summary ==

Applying: tests/kms_flip: Remove blt/rcs flip tests.
Using index info to reconstruct a base tree...
M   tests/kms_flip.c
Falling back to patching base and 3-way merge...
Auto-merging tests/kms_flip.c
CONFLICT (content): Merge conflict in tests/kms_flip.c
Patch failed at 0001 tests/kms_flip: Remove blt/rcs flip tests.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for test/kms_psr_sink : HACK test if psr_drrs also need test_cleanup

[Patchwork]

== Series Details ==

Series: test/kms_psr_sink : HACK test if psr_drrs also need test_cleanup
URL   : https://patchwork.freedesktop.org/series/36004/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3597
cad7381fbadc drm-tip: 2018y-01m-04d-12h-56m-43s UTC integration manifest

No testlist changes.

Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260 +1

fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-bdw-gvtdvmtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:6s
fi-blb-e6850 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:7s
fi-bsw-n3050 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:19s
fi-bwr-2160  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:12s
fi-bxt-dsi   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:10s
fi-bxt-j4205 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:10s
fi-byt-j1900 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:16s
fi-byt-n2820 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:15s
fi-elk-e7500 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
fi-gdg-551   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:15s
fi-glk-1 total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:11s
fi-hsw-4770  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-hsw-4770r total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-ilk-650   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
fi-ivb-3520m total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-ivb-3770  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-kbl-7500u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-kbl-7560u total:2pass:1dwarn:1   dfail:0   fail:0   skip:0   
time:7s
fi-kbl-7567u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-kbl-r total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:8s
fi-pnv-d510  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:28s
fi-skl-6260u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-skl-6600u total:2pass:1dwarn:1   dfail:0   fail:0   skip:0   
time:8s
fi-skl-6700hqtotal:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:11s
fi-skl-6700k2total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-skl-6770hqtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-skl-gvtdvmtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-snb-2520m total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:13s
fi-snb-2600  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
Blacklisted hosts:
fi-cfl-s2total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:8s
fi-glk-dsi   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:7s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_744/issues.html
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[Intel-gfx] [PATCH i-g-t 3/7] kms_vblank: Reorganize subtests by pipe

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 102 -
 1 file changed, 53 insertions(+), 49 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 9a5a98743fa6..a83500635976 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -119,57 +119,48 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
int nchildren =
data->flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
igt_display_t *display = >display;
-   igt_output_t *output;
-   enum pipe p;
-
-   for_each_pipe_with_valid_output(display, p, output) {
-   igt_hang_t hang;
+   igt_output_t *output = data->output;
+   igt_hang_t hang;
 
-   data->pipe = p;
-   prepare_crtc(data, fd, output);
+   prepare_crtc(data, fd, output);
 
-   igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
-igt_subtest_name(),
-kmstest_pipe_name(data->pipe),
-igt_output_name(output),
-nchildren);
+   igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
+igt_subtest_name(), kmstest_pipe_name(data->pipe),
+igt_output_name(output), nchildren);
 
-   if (data->flags & HANG)
-   hang = igt_hang_ring(display->drm_fd, 
I915_EXEC_DEFAULT);
+   if (data->flags & HANG)
+   hang = igt_hang_ring(display->drm_fd, I915_EXEC_DEFAULT);
 
-   if (data->flags & BUSY) {
-   union drm_wait_vblank vbl;
+   if (data->flags & BUSY) {
+   union drm_wait_vblank vbl;
 
-   memset(, 0, sizeof(vbl));
-   vbl.request.type =
-   DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
-   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
-   vbl.request.sequence = 120 + 12;
-   igt_assert_eq(wait_vblank(fd, ), 0);
-   }
+   memset(, 0, sizeof(vbl));
+   vbl.request.type =
+   DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
+   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
+   vbl.request.sequence = 120 + 12;
+   igt_assert_eq(wait_vblank(fd, ), 0);
+   }
 
-   igt_fork(child, nchildren)
-   testfunc(data, fd, nchildren);
-   igt_waitchildren();
+   igt_fork(child, nchildren)
+   testfunc(data, fd, nchildren);
+   igt_waitchildren();
 
-   if (data->flags & BUSY) {
-   struct drm_event_vblank buf;
-   igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
-   }
+   if (data->flags & BUSY) {
+   struct drm_event_vblank buf;
+   igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
+   }
 
-   igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
+   igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
 
-   if (data->flags & HANG)
-   igt_post_hang_ring(fd, hang);
+   if (data->flags & HANG)
+   igt_post_hang_ring(fd, hang);
 
-   igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
-igt_subtest_name(),
-kmstest_pipe_name(data->pipe),
-igt_output_name(output));
+   igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
+igt_subtest_name(), kmstest_pipe_name(data->pipe), 
igt_output_name(output));
 
-   /* cleanup what prepare_crtc() has done */
-   cleanup_crtc(data, fd, output);
-   }
+   /* cleanup what prepare_crtc() has done */
+   cleanup_crtc(data, fd, output);
 }
 
 static void crtc_id_subtest(data_t *data, int fd)
@@ -338,6 +329,8 @@ igt_main
{ "wait", vblank_wait, IDLE | FORKED | BUSY | HANG },
{ }
}, *f;
+   enum pipe p;
+
const struct {
const char *name;
unsigned int flags;
@@ -361,15 +354,26 @@ igt_main
igt_subtest("crtc-id")
crtc_id_subtest(, fd);
 
-   for (f = funcs; f->name; f++) {
-   for (m = modes; m->name; m++) {
-   if (m->flags & ~f->valid)
-   continue;
-
-   igt_subtest_f("%s-%s%s", f->name, m->name,
- m->flags & HANG ? "-hang" : "") {
-   data.flags = m->flags;
-   run_test(, fd, f->func);
+   for_each_pipe_static(p) igt_subtest_group {
+   igt_fixture
+   igt_display_require_output_on_pipe(, p);

[Intel-gfx] [PATCH i-g-t 4/7] kms_vblank: Make the -hang tests work as intended

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 31 ++-
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index a83500635976..45301ca5110f 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -54,7 +54,7 @@ typedef struct {
 #define IDLE 1
 #define BUSY 2
 #define FORKED 4
-#define HANG 8
+#define NOHANG 8
 } data_t;
 
 static double elapsed(const struct timespec *start,
@@ -128,7 +128,7 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 igt_subtest_name(), kmstest_pipe_name(data->pipe),
 igt_output_name(output), nchildren);
 
-   if (data->flags & HANG)
+   if (!(data->flags & NOHANG))
hang = igt_hang_ring(display->drm_fd, I915_EXEC_DEFAULT);
 
if (data->flags & BUSY) {
@@ -153,7 +153,7 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 
igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
 
-   if (data->flags & HANG)
+   if (!(data->flags & NOHANG))
igt_post_hang_ring(fd, hang);
 
igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
@@ -324,9 +324,9 @@ igt_main
void (*func)(data_t *, int, int);
unsigned int valid;
} funcs[] = {
-   { "accuracy", accuracy, IDLE | HANG },
-   { "query", vblank_query, IDLE | FORKED | BUSY | HANG },
-   { "wait", vblank_wait, IDLE | FORKED | BUSY | HANG },
+   { "accuracy", accuracy, IDLE },
+   { "query", vblank_query, IDLE | FORKED | BUSY },
+   { "wait", vblank_wait, IDLE | FORKED | BUSY },
{ }
}, *f;
enum pipe p;
@@ -365,15 +365,28 @@ igt_main
if (m->flags & ~f->valid)
continue;
 
-   igt_subtest_f("pipe-%s-%s-%s%s",
+   igt_subtest_f("pipe-%s-%s-%s",
  kmstest_pipe_name(data.pipe),
- f->name, m->name,
- m->flags & HANG ? "-hang" : "") {
+ f->name, m->name) {
+   
for_each_valid_output_on_pipe(, data.pipe, data.output) {
+   data.flags = m->flags | NOHANG;
+   run_test(, fd, f->func);
+   }
+   }
+
+   /* Skip the -hang version if NOHANG flag is set 
*/
+   if (f->valid & NOHANG)
+   continue;
+
+   igt_subtest_f("pipe-%s-%s-%s-hang",
+ kmstest_pipe_name(data.pipe),
+ f->name, m->name) {

for_each_valid_output_on_pipe(, data.pipe, data.output) {
data.flags = m->flags;
run_test(, fd, f->func);
}
}
+
}
}
}
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 2/7] tests/kms_flip: Move kms_flip.vblank-vs-hang to kms_vblank

[Maarten Lankhorst]

There's no need to test this more than once.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c   | 10 +-
 tests/kms_vblank.c | 18 ++
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 7689e65b521a..50c16b0debbf 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -72,7 +72,7 @@
 #define TEST_SUSPEND   (1 << 26)
 #define TEST_TS_CONT   (1 << 27)
 #define TEST_BO_TOOBIG (1 << 28)
-#define TEST_HANG_ONCE (1 << 29)
+
 #define TEST_BASIC (1 << 30)
 
 #define EVENT_FLIP (1 << 0)
@@ -1071,13 +1071,8 @@ static unsigned int wait_for_events(struct test_output 
*o)
 static unsigned event_loop(struct test_output *o, unsigned duration_ms)
 {
unsigned long start, end;
-   igt_hang_t hang;
int count = 0;
 
-   memset(, 0, sizeof(hang));
-   if (o->flags & TEST_HANG_ONCE)
-   hang = hang_gpu(drm_fd);
-
start = gettime_us();
 
while (1) {
@@ -1097,8 +1092,6 @@ static unsigned event_loop(struct test_output *o, 
unsigned duration_ms)
 
end = gettime_us();
 
-   unhang_gpu(drm_fd, hang);
-
/* Flush any remaining events */
if (o->pending_events)
wait_for_events(o);
@@ -1565,7 +1558,6 @@ int main(int argc, char **argv)
TEST_CHECK_TS, "flip-vs-blocking-wf-vblank" },
{ 30, TEST_FLIP | TEST_MODESET | TEST_HANG | TEST_NOEVENT, 
"flip-vs-modeset-vs-hang" },
{ 30, TEST_FLIP | TEST_PAN | TEST_HANG, 
"flip-vs-panning-vs-hang" },
-   { 30, TEST_VBLANK | TEST_HANG_ONCE, "vblank-vs-hang" },
{ 1, TEST_FLIP | TEST_EINVAL | TEST_FB_BAD_TILING, 
"flip-vs-bad-tiling" },
 
{ 1, TEST_DPMS_OFF | TEST_MODESET | TEST_FLIP,
diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 342e4ef23b97..9a5a98743fa6 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -54,6 +54,7 @@ typedef struct {
 #define IDLE 1
 #define BUSY 2
 #define FORKED 4
+#define HANG 8
 } data_t;
 
 static double elapsed(const struct timespec *start,
@@ -122,6 +123,8 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
enum pipe p;
 
for_each_pipe_with_valid_output(display, p, output) {
+   igt_hang_t hang;
+
data->pipe = p;
prepare_crtc(data, fd, output);
 
@@ -131,6 +134,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 igt_output_name(output),
 nchildren);
 
+   if (data->flags & HANG)
+   hang = igt_hang_ring(display->drm_fd, 
I915_EXEC_DEFAULT);
+
if (data->flags & BUSY) {
union drm_wait_vblank vbl;
 
@@ -153,6 +159,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 
igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
 
+   if (data->flags & HANG)
+   igt_post_hang_ring(fd, hang);
+
igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
 igt_subtest_name(),
 kmstest_pipe_name(data->pipe),
@@ -324,9 +333,9 @@ igt_main
void (*func)(data_t *, int, int);
unsigned int valid;
} funcs[] = {
-   { "accuracy", accuracy, IDLE },
-   { "query", vblank_query, IDLE | FORKED | BUSY },
-   { "wait", vblank_wait, IDLE | FORKED | BUSY },
+   { "accuracy", accuracy, IDLE | HANG },
+   { "query", vblank_query, IDLE | FORKED | BUSY | HANG },
+   { "wait", vblank_wait, IDLE | FORKED | BUSY | HANG },
{ }
}, *f;
const struct {
@@ -357,7 +366,8 @@ igt_main
if (m->flags & ~f->valid)
continue;
 
-   igt_subtest_f("%s-%s", f->name, m->name) {
+   igt_subtest_f("%s-%s%s", f->name, m->name,
+ m->flags & HANG ? "-hang" : "") {
data.flags = m->flags;
run_test(, fd, f->func);
}
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 6/7] kms_flip: Remove redundant vblank tests.

[Maarten Lankhorst]

wf_vblank is redundant with wf_vblank-ts-check, which also performs
a check but runs in the same way.

The -EINVAL vblank tests are reproduced in kms_vblank, as are the
vblank-vs-* tests.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 50c16b0debbf..710ea52b4a8a 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -1527,7 +1527,6 @@ int main(int argc, char **argv)
int flags;
const char *name;
} tests[] = {
-   { 30, TEST_VBLANK, "wf_vblank" },
{ 30, TEST_VBLANK | TEST_CHECK_TS, "wf_vblank-ts-check" },
{ 30, TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_CHECK_TS,
"blocking-wf_vblank" },
@@ -1535,8 +1534,6 @@ int main(int argc, char **argv)
"absolute-wf_vblank" },
{ 30,  TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_VBLANK_ABSOLUTE,
"blocking-absolute-wf_vblank" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_EINVAL, 
"wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_EINVAL, 
"wf_vblank-vs-modeset" },
{ 10, TEST_FLIP | TEST_BASIC, "plain-flip" },
{ 30, TEST_FLIP | TEST_EBUSY , "busy-flip" },
{ 30, TEST_FLIP | TEST_FENCE_STRESS , "flip-vs-fences" },
@@ -1568,11 +1565,6 @@ int main(int argc, char **argv)
{ 0, TEST_ENOENT | TEST_NOEVENT, "nonexisting-fb" },
{ 10, TEST_DPMS_OFF | TEST_DPMS | TEST_VBLANK_RACE, 
"dpms-vs-vblank-race" },
{ 10, TEST_MODESET | TEST_VBLANK_RACE, "modeset-vs-vblank-race" 
},
-   { 10, TEST_VBLANK | TEST_DPMS | TEST_RPM | TEST_TS_CONT, 
"vblank-vs-dpms-rpm" },
-   { 10, TEST_VBLANK | TEST_MODESET | TEST_RPM | TEST_TS_CONT, 
"vblank-vs-modeset-rpm" },
-   { 0, TEST_VBLANK | TEST_DPMS | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-dpms-suspend" },
-   { 0, TEST_VBLANK | TEST_MODESET | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-modeset-suspend" },
-   { 0, TEST_VBLANK | TEST_SUSPEND | TEST_TS_CONT, 
"vblank-vs-suspend" },
{ 0, TEST_BO_TOOBIG | TEST_NO_2X_OUTPUT, "bo-too-big" },
};
int i;
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 5/7] kms_vblank: Add tests implemented in kms_flip

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 88 ++
 1 file changed, 82 insertions(+), 6 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 45301ca5110f..f2fa11523d50 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -51,10 +51,14 @@ typedef struct {
igt_output_t *output;
enum pipe pipe;
unsigned int flags;
-#define IDLE 1
-#define BUSY 2
-#define FORKED 4
-#define NOHANG 8
+#define IDLE   0x1
+#define BUSY   0x2
+#define FORKED 0x4
+#define NOHANG 0x8
+#define MODESET 0x10
+#define DPMS   0x20
+#define SUSPEND 0x40
+#define RPM0x80
 } data_t;
 
 static double elapsed(const struct timespec *start,
@@ -124,6 +128,9 @@ static void run_test(data_t *data, int fd, void 
(*testfunc)(data_t *, int, int))
 
prepare_crtc(data, fd, output);
 
+   if (data->flags & RPM)
+   igt_require(igt_setup_runtime_pm());
+
igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
 igt_subtest_name(), kmstest_pipe_name(data->pipe),
 igt_output_name(output), nchildren);
@@ -315,6 +322,69 @@ static void vblank_wait(data_t *data, int fd, int 
nchildren)
 elapsed(, , count));
 }
 
+static int get_vblank(int fd, enum pipe pipe, unsigned flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | kmstest_get_vbl_flag(pipe) | 
flags;
+   do_or_die(igt_ioctl(fd, DRM_IOCTL_WAIT_VBLANK, ));
+
+   return vbl.reply.sequence;
+}
+
+static void vblank_ts_cont(data_t *data, int fd, int nchildren)
+{
+   igt_display_t *display = >display;
+   igt_output_t *output = data->output;
+   int seq1, seq2;
+   union drm_wait_vblank vbl;
+
+   seq1 = get_vblank(fd, data->pipe, 0);
+
+   if (data->flags & DPMS) {
+   igt_output_set_prop_value(output, IGT_CONNECTOR_DPMS, 
DRM_MODE_DPMS_OFF);
+   igt_display_commit(display);
+   }
+
+   if (data->flags & MODESET) {
+   igt_output_set_pipe(output, PIPE_NONE);
+   igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+   }
+
+   if (data->flags & RPM)
+   
igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED));
+
+   if (data->flags & SUSPEND)
+   igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_NONE);
+
+   if (data->flags & (MODESET | DPMS)) {
+   /* Attempting to do a vblank while disabled should return 
-EINVAL */
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE;
+   vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
+   igt_assert_eq(wait_vblank(fd, ), -EINVAL);
+   }
+
+   if (data->flags & DPMS) {
+   igt_output_set_prop_value(output, IGT_CONNECTOR_DPMS, 
DRM_MODE_DPMS_ON);
+   igt_display_commit(display);
+   }
+
+   if (data->flags & MODESET) {
+   igt_output_set_pipe(output, data->pipe);
+   igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+   }
+
+   seq2 = get_vblank(fd, data->pipe, 0);
+
+   igt_debug("testing ts continuity: Current frame %u, old frame %u\n", 
seq2, seq1);
+
+   igt_assert_f(seq2 - seq1 >= 0, "unexpected vblank seq %u, should be >= 
%u\n", seq2, seq1);
+   igt_assert_f(seq2 - seq1 <= 150, "unexpected vblank seq %u, should be < 
%u\n", seq2, seq1 + 150);
+}
+
 igt_main
 {
int fd;
@@ -327,6 +397,7 @@ igt_main
{ "accuracy", accuracy, IDLE },
{ "query", vblank_query, IDLE | FORKED | BUSY },
{ "wait", vblank_wait, IDLE | FORKED | BUSY },
+   { "ts-continuation", vblank_ts_cont, IDLE | SUSPEND | MODESET | 
DPMS | RPM },
{ }
}, *f;
enum pipe p;
@@ -339,6 +410,11 @@ igt_main
{ "forked", IDLE | FORKED },
{ "busy", BUSY },
{ "forked-busy", BUSY | FORKED },
+   { "dpms-rpm", DPMS | RPM },
+   { "dpms-suspend", DPMS | SUSPEND },
+   { "suspend", SUSPEND },
+   { "modeset", MODESET },
+   { "modeset-rpm", MODESET | RPM },
{ }
}, *m;
 
@@ -374,8 +450,8 @@ igt_main
}
}
 
-   /* Skip the -hang version if NOHANG flag is set 
*/
-   if (f->valid & NOHANG)
+   /* Skip the -hang version if NOHANG or RPM flag 
is set */
+   if (f->valid & (NOHANG | RPM))
continue;
 

[Intel-gfx] [PATCH i-g-t 0/7] kms_vblank: Move tests over from kms_flip.

[Maarten Lankhorst]

kms_flip is meant for finding issues with page flip, but was used for
finding bugs in the vblank ioctl too. Move over some tests from kms_flip
to kms_vblank, and reduce their runtime to a minimum.

Maarten Lankhorst (7):
  tests/kms_flip: Remove blt/rcs flip tests.
  tests/kms_flip: Move kms_flip.vblank-vs-hang to kms_vblank
  kms_vblank: Reorganize subtests by pipe
  kms_vblank: Make the -hang tests work as intended
  kms_vblank: Add tests implemented in kms_flip
  kms_flip: Remove redundant vblank tests.
  kms_vblank: Remove teardown code from cleanup_crtc

 tests/kms_flip.c   |  55 +--
 tests/kms_vblank.c | 204 +++--
 2 files changed, 152 insertions(+), 107 deletions(-)

-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 7/7] kms_vblank: Remove teardown code from cleanup_crtc

[Maarten Lankhorst]

New way of doing things is calling igt_display_reset() before any
setup code. This way if the configuration stays the same, the initial
modeset will be a noop.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_vblank.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index f2fa11523d50..3d8004ef6c3f 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -74,6 +74,8 @@ static void prepare_crtc(data_t *data, int fd, igt_output_t 
*output)
igt_display_t *display = >display;
igt_plane_t *primary;
 
+   igt_display_reset(display);
+
/* select the pipe we want to use */
igt_output_set_pipe(output, data->pipe);
 
@@ -95,16 +97,7 @@ static void prepare_crtc(data_t *data, int fd, igt_output_t 
*output)
 
 static void cleanup_crtc(data_t *data, int fd, igt_output_t *output)
 {
-   igt_display_t *display = >display;
-   igt_plane_t *primary;
-
igt_remove_fb(fd, >primary_fb);
-
-   primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
-   igt_plane_set_fb(primary, NULL);
-
-   igt_output_set_pipe(output, PIPE_ANY);
-   igt_display_commit(display);
 }
 
 static int wait_vblank(int fd, union drm_wait_vblank *vbl)
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t 1/7] tests/kms_flip: Remove blt/rcs flip tests.

[Maarten Lankhorst]

With the removal of mmio flips, blt and rcs flips are no longer
different from doing busy testing in kms_busy.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_flip.c | 37 +
 1 file changed, 1 insertion(+), 36 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 39ee68d233e5..7689e65b521a 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -45,8 +45,7 @@
 #include "igt_stats.h"
 
 #define TEST_DPMS  (1 << 0)
-#define TEST_WITH_DUMMY_BCS(1 << 1)
-#define TEST_WITH_DUMMY_RCS(1 << 2)
+
 #define TEST_PAN   (1 << 3)
 #define TEST_MODESET   (1 << 4)
 #define TEST_CHECK_TS  (1 << 5)
@@ -668,8 +667,6 @@ static unsigned int run_test_step(struct test_output *o)
struct vblank_reply vbl_reply;
unsigned int target_seq;
igt_hang_t hang;
-   igt_spin_t *spin_rcs = 0;
-   igt_spin_t *spin_bcs = 0;
 
target_seq = o->vblank_state.seq_step;
/* Absolute waits only works once we have a frame counter. */
@@ -691,20 +688,6 @@ static unsigned int run_test_step(struct test_output *o)
if (!(o->flags & TEST_SINGLE_BUFFER))
o->current_fb_id = !o->current_fb_id;
 
-   if (o->flags & TEST_WITH_DUMMY_BCS) {
-   spin_bcs = igt_spin_batch_new(drm_fd, 0, I915_EXEC_BLT,
- 
o->fb_info[o->current_fb_id].gem_handle);
-   igt_spin_batch_set_timeout(spin_bcs,
-  NSEC_PER_SEC);
-   }
-
-   if (o->flags & TEST_WITH_DUMMY_RCS) {
-   spin_rcs = igt_spin_batch_new(drm_fd, 0, I915_EXEC_RENDER,
- 
o->fb_info[o->current_fb_id].gem_handle);
-   igt_spin_batch_set_timeout(spin_rcs,
-  NSEC_PER_SEC);
-   }
-
if (o->flags & TEST_FB_RECREATE)
recreate_fb(o);
new_fb_id = o->fb_ids[o->current_fb_id];
@@ -809,10 +792,6 @@ static unsigned int run_test_step(struct test_output *o)
completed_events = EVENT_VBLANK;
}
}
-   if (spin_rcs)
-   igt_spin_batch_free(drm_fd, spin_rcs);
-   if (spin_bcs)
-   igt_spin_batch_free(drm_fd, spin_bcs);
 
if (do_flip && (o->flags & TEST_EBUSY))
igt_assert(do_page_flip(o, new_fb_id, true) == -EBUSY);
@@ -1065,10 +1044,6 @@ static unsigned int wait_for_events(struct test_output 
*o)
evctx.vblank_handler = vblank_handler;
evctx.page_flip_handler = page_flip_handler;
 
-   /* make timeout lax with the dummy load */
-   if (o->flags & (TEST_WITH_DUMMY_BCS | TEST_WITH_DUMMY_RCS))
-   timeout.tv_sec *= 60;
-
FD_ZERO();
FD_SET(drm_fd, );
do {
@@ -1568,15 +1543,7 @@ int main(int argc, char **argv)
{ 30,  TEST_VBLANK | TEST_VBLANK_BLOCK | TEST_VBLANK_ABSOLUTE,
"blocking-absolute-wf_vblank" },
{ 60,  TEST_VBLANK | TEST_DPMS | TEST_EINVAL, 
"wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_WITH_DUMMY_BCS,
-   "blt-wf_vblank-vs-dpms" },
-   { 60,  TEST_VBLANK | TEST_DPMS | TEST_WITH_DUMMY_RCS,
-   "rcs-wf_vblank-vs-dpms" },
{ 60,  TEST_VBLANK | TEST_MODESET | TEST_EINVAL, 
"wf_vblank-vs-modeset" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_WITH_DUMMY_BCS,
-   "blt-wf_vblank-vs-modeset" },
-   { 60,  TEST_VBLANK | TEST_MODESET | TEST_WITH_DUMMY_RCS,
-   "rcs-wf_vblank-vs-modeset" },
{ 10, TEST_FLIP | TEST_BASIC, "plain-flip" },
{ 30, TEST_FLIP | TEST_EBUSY , "busy-flip" },
{ 30, TEST_FLIP | TEST_FENCE_STRESS , "flip-vs-fences" },
@@ -1586,8 +1553,6 @@ int main(int argc, char **argv)
{ 30, TEST_FLIP | TEST_RMFB | TEST_MODESET , "flip-vs-rmfb" },
{ 20, TEST_FLIP | TEST_DPMS | TEST_EINVAL | TEST_BASIC, 
"flip-vs-dpms" },
{ 30,  TEST_FLIP | TEST_PAN, "flip-vs-panning" },
-   { 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_BCS, 
"blt-flip-vs-panning" },
-   { 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_RCS, 
"render-flip-vs-panning" },
{ 20, TEST_FLIP | TEST_MODESET | TEST_EINVAL | TEST_BASIC, 
"flip-vs-modeset" },
{ 30,  TEST_FLIP | TEST_VBLANK_EXPIRED_SEQ,
"flip-vs-expired-vblank" },
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t] test/kms_psr_sink : HACK test if psr_drrs also need test_cleanup

[Marta Lofstedt]

See previous PW:
https://patchwork.freedesktop.org/series/36000/

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260

Signed-off-by: Marta Lofstedt 
---
 tests/intel-ci/fast-feedback.testlist | 575 +-
 1 file changed, 288 insertions(+), 287 deletions(-)

diff --git a/tests/intel-ci/fast-feedback.testlist 
b/tests/intel-ci/fast-feedback.testlist
index f71a16bc..34db4706 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,295 +1,296 @@
 # Keep alphabetically sorted by default
 
-igt@core_auth@basic-auth
-igt@core_prop_blob@basic
-igt@debugfs_test@read_all_entries
-igt@drv_getparams_basic@basic-eu-total
-igt@drv_getparams_basic@basic-subslice-total
-igt@drv_hangman@error-state-basic
-igt@gem_basic@bad-close
-igt@gem_basic@create-close
-igt@gem_basic@create-fd-close
-igt@gem_busy@basic-busy-default
-igt@gem_busy@basic-hang-default
-igt@gem_close_race@basic-process
-igt@gem_close_race@basic-threads
-igt@gem_cpu_reloc@basic
-igt@gem_cs_tlb@basic-default
-igt@gem_ctx_create@basic
-igt@gem_ctx_create@basic-files
-igt@gem_ctx_exec@basic
-igt@gem_ctx_param@basic
-igt@gem_ctx_param@basic-default
-igt@gem_ctx_switch@basic-default
-igt@gem_ctx_switch@basic-default-heavy
-igt@gem_exec_basic@basic-blt
-igt@gem_exec_basic@basic-bsd
-igt@gem_exec_basic@basic-bsd1
-igt@gem_exec_basic@basic-bsd2
-igt@gem_exec_basic@basic-default
-igt@gem_exec_basic@basic-render
-igt@gem_exec_basic@basic-vebox
-igt@gem_exec_basic@gtt-blt
-igt@gem_exec_basic@gtt-bsd
-igt@gem_exec_basic@gtt-bsd1
-igt@gem_exec_basic@gtt-bsd2
-igt@gem_exec_basic@gtt-default
-igt@gem_exec_basic@gtt-render
-igt@gem_exec_basic@gtt-vebox
-igt@gem_exec_basic@readonly-blt
-igt@gem_exec_basic@readonly-bsd
-igt@gem_exec_basic@readonly-bsd1
-igt@gem_exec_basic@readonly-bsd2
-igt@gem_exec_basic@readonly-default
-igt@gem_exec_basic@readonly-render
-igt@gem_exec_basic@readonly-vebox
-igt@gem_exec_create@basic
-igt@gem_exec_fence@basic-busy-default
-igt@gem_exec_fence@basic-wait-default
-igt@gem_exec_fence@basic-await-default
-igt@gem_exec_fence@await-hang-default
-igt@gem_exec_fence@nb-await-default
-igt@gem_exec_flush@basic-batch-kernel-default-cmd
-igt@gem_exec_flush@basic-batch-kernel-default-uc
-igt@gem_exec_flush@basic-batch-kernel-default-wb
-igt@gem_exec_flush@basic-uc-pro-default
-igt@gem_exec_flush@basic-uc-prw-default
-igt@gem_exec_flush@basic-uc-ro-default
-igt@gem_exec_flush@basic-uc-rw-default
-igt@gem_exec_flush@basic-uc-set-default
-igt@gem_exec_flush@basic-wb-pro-default
-igt@gem_exec_flush@basic-wb-prw-default
-igt@gem_exec_flush@basic-wb-ro-before-default
-igt@gem_exec_flush@basic-wb-ro-default
-igt@gem_exec_flush@basic-wb-rw-before-default
-igt@gem_exec_flush@basic-wb-rw-default
-igt@gem_exec_flush@basic-wb-set-default
-igt@gem_exec_gttfill@basic
-igt@gem_exec_nop@basic-parallel
-igt@gem_exec_nop@basic-series
-igt@gem_exec_parallel@basic
-igt@gem_exec_parse@basic-allowed
-igt@gem_exec_parse@basic-rejected
-igt@gem_exec_reloc@basic-cpu
-igt@gem_exec_reloc@basic-gtt
-igt@gem_exec_reloc@basic-cpu-gtt
-igt@gem_exec_reloc@basic-gtt-cpu
-igt@gem_exec_reloc@basic-cpu-read
-igt@gem_exec_reloc@basic-gtt-read
-igt@gem_exec_reloc@basic-write-cpu
-igt@gem_exec_reloc@basic-write-gtt
-igt@gem_exec_reloc@basic-write-read
-igt@gem_exec_reloc@basic-cpu-noreloc
-igt@gem_exec_reloc@basic-gtt-noreloc
-igt@gem_exec_reloc@basic-cpu-gtt-noreloc
-igt@gem_exec_reloc@basic-gtt-cpu-noreloc
-igt@gem_exec_reloc@basic-cpu-read-noreloc
-igt@gem_exec_reloc@basic-gtt-read-noreloc
-igt@gem_exec_reloc@basic-write-cpu-noreloc
-igt@gem_exec_reloc@basic-write-gtt-noreloc
-igt@gem_exec_reloc@basic-write-read-noreloc
-igt@gem_exec_reloc@basic-cpu-active
-igt@gem_exec_reloc@basic-gtt-active
-igt@gem_exec_reloc@basic-cpu-gtt-active
-igt@gem_exec_reloc@basic-gtt-cpu-active
-igt@gem_exec_reloc@basic-cpu-read-active
-igt@gem_exec_reloc@basic-gtt-read-active
-igt@gem_exec_reloc@basic-write-cpu-active
-igt@gem_exec_reloc@basic-write-gtt-active
-igt@gem_exec_reloc@basic-write-read-active
-igt@gem_exec_reloc@basic-softpin
-igt@gem_exec_store@basic-all
-igt@gem_exec_store@basic-blt
-igt@gem_exec_store@basic-bsd
-igt@gem_exec_store@basic-bsd1
-igt@gem_exec_store@basic-bsd2
-igt@gem_exec_store@basic-default
-igt@gem_exec_store@basic-render
-igt@gem_exec_store@basic-vebox
-igt@gem_exec_suspend@basic
-igt@gem_exec_suspend@basic-s3
-igt@gem_exec_suspend@basic-s4-devices
-igt@gem_flink_basic@bad-flink
-igt@gem_flink_basic@bad-open
-igt@gem_flink_basic@basic
-igt@gem_flink_basic@double-flink
-igt@gem_flink_basic@flink-lifetime
-igt@gem_linear_blits@basic
-igt@gem_mmap@basic
-igt@gem_mmap@basic-small-bo
-igt@gem_mmap_gtt@basic
-igt@gem_mmap_gtt@basic-copy
-igt@gem_mmap_gtt@basic-read
-igt@gem_mmap_gtt@basic-read-no-prefault
-igt@gem_mmap_gtt@basic-read-write
-igt@gem_mmap_gtt@basic-read-write-distinct
-igt@gem_mmap_gtt@basic-short
-igt@gem_mmap_gtt@basic-small-bo