Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

[Yaodong Li]

On 01/05/2018 02:15 AM, Sagar Arun Kamble wrote:



On 1/5/2018 3:22 AM, Yaodong Li wrote:


On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote:
Since ring frequency programming needs consideration of both IA and 
GT frequency requests I think keeping the logic
to program the ring frequency table in driver that monitors both 
IA/GT busyness and power budgets like intel_ips
will be more appropriate. intel_ips is relying on global load 
derived from all CPUs.
I understand that power awareness and busyness based policy might be 
trickier but having that as tunable will give better flexibility.


By just looking into the current code, the way intel_ips checks gpu 
busyness cannot reflect the actual workload of GT
(e.g. gpu busy is true even if there's only one pending request), in 
this case, we shall not increase the ring freq if we
want to use a "workload monitoring" based solution. so we need a more 
accurate way to monitor the current GT workload
(e.g.  when the pending request count reaches a center tunable 
threshold??).
Yes. May be we can share the PMU data about engine busyness with 
intel_ips.
Thank you Sagar! Can you tell more about how we can get the gpu busyness 
from PMU data?


I think the solution would be to set the ring freq table to use a ring 
freq >= current ia freq (for all possible gpu freq) once we found
gpu workload is high (need to tune the threshold), and we will decrease 
the ring freq (use a 2x multiplier?) once we found the GT
workload is low. The benefit to use the intel_ips is it can tell both 
the cpu & gpu busyness. However, we do need an accurate way

to check at least the busyness of gpu for this issue.


On 1/3/2018 11:51 PM, Yaodong Li wrote:


You are thinking of plugging into intel_pstate to make it 
smarter for ia freq transitions?
Yep. This seems a correct step to give some automatic support 
instead of parameter/hardcoded multiplier.


Does this mean we should use cpufreq/intel_pstate based approach 
instead of the current modparam solution for Gen9?


Some concerns and questions about intel_pstate approach:
a) Currently, we cannot get the accurate pstate/target freq value 
from cpufreq in intel_pstate active mode since
 these values won't be exported to cpufreq layer, so if we 
won't change intel_pstate code then we only can get

 the max cpu freq of a new policy.
b) intel_pstate policy is attached to each logic cpu, which means 
we will receive policy/freq transition notification
    for each logic cpu freq change. One question is how we are 
going to decide the freq of the ring? just use the max

    cpu freq reported?
c) With the intel_pstate approach we may still run into thermal 
throttling, in this case, can a certain cooling device

    be triggered to lower the cpu freq?

Thanks and Regards,
-Jackie









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Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Alexandru Chirvasitu]

Will do. 

On Fri, Jan 05, 2018 at 08:02:48PM +, Chris Wilson wrote:
> Quoting Alexandru Chirvasitu (2018-01-05 19:58:42)
> > OK, I then plan to try with the previous config, plus these
> > modifications:
> > 
> > CONFIG_PAGE_POISONING not set
> > CONFIG_SLUB_STATS=y
> > 
> > I'm a little puzzled about this:
> 
> [snip]
> 
> > > It would be CONFIG_SLUB_STATS and then you would a
> > > /sys/kernel/slab/i915_dependency/ directory with all the details of the
> > > slab, and in particular a poison file showing the status (and allowing
> > > it to modified) of slab poisoning
> > > 
> > > Ok, it looks like poisoning is only available if CONFIG_SLUB_DEBUG is
> > > set. Since it is not set, don't worry about it ;)
> > 
> > I actually do have SLUB_DEBUG set to 'y' in the kernel whose dmesg I
> > last sent you.
> 
> Ah, ok. I was looking at the config attached the first mail. Turn off
> SLUB_DEBUG for now to give ourselves the best chance at getting
> something from kasan. I hope it's worth the effort...

No worries, worth it at my end already. And thanks!

Will get back when I have another crash.
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Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Chris Wilson]

Quoting Alexandru Chirvasitu (2018-01-05 19:58:42)
> OK, I then plan to try with the previous config, plus these
> modifications:
> 
> CONFIG_PAGE_POISONING not set
> CONFIG_SLUB_STATS=y
> 
> I'm a little puzzled about this:

[snip]

> > It would be CONFIG_SLUB_STATS and then you would a
> > /sys/kernel/slab/i915_dependency/ directory with all the details of the
> > slab, and in particular a poison file showing the status (and allowing
> > it to modified) of slab poisoning
> > 
> > Ok, it looks like poisoning is only available if CONFIG_SLUB_DEBUG is
> > set. Since it is not set, don't worry about it ;)
> 
> I actually do have SLUB_DEBUG set to 'y' in the kernel whose dmesg I
> last sent you.

Ah, ok. I was looking at the config attached the first mail. Turn off
SLUB_DEBUG for now to give ourselves the best chance at getting
something from kasan. I hope it's worth the effort...
-Chris
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Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Alexandru Chirvasitu]

OK, I then plan to try with the previous config, plus these
modifications:

CONFIG_PAGE_POISONING not set
CONFIG_SLUB_STATS=y

I'm a little puzzled about this:

On Fri, Jan 05, 2018 at 07:51:01PM +, Chris Wilson wrote:
> Quoting Alexandru Chirvasitu (2018-01-05 19:37:24)
> > I'll try. I need a bit of clarification:
> > 
> > On Fri, Jan 05, 2018 at 05:52:25PM +, Chris Wilson wrote:
> > > Quoting Alexandru Chirvasitu (2018-01-03 21:53:15)
> > > > All right, here's the dmesg from the kernel compiled from drm-tip (in
> > > > sync with upstream at the time of the compilation earlier today), with
> > > > 
> > > > CONFIG_DRM_I915_DEBUG_GEM=y
> > > > 
> > > > I crashed it by opening 20+ xterm windows. Doesn't always do it though
> > > > (tried this before).
> > > 
> > > Sorry, still stumped. It's still the same use-after-free and no asserts
> > > hit. Can you keep KASAN enabled but disable slab/page poisoning? Hmm, I
> > > think it has to be page poisoning doing the 0x6b as SLAB_POISON is
> > > disabled by default.
> > 
> > Would this have to be through a new compilation, or would it do to
> > just remove the poisoning kernel parameter on boot? 
> 
> CONFIG_PAGE_POISONING
> 
> > 
> > > (You could check by enabling slabstats can looking in sysfs.)
> > 
> > Sorry, I was having some trouble parsing this; what do I check again
> > and how?
> > 
> > Does 'slabstats' refer to another kernel config option or something
> > else?
> 
> It would be CONFIG_SLUB_STATS and then you would a
> /sys/kernel/slab/i915_dependency/ directory with all the details of the
> slab, and in particular a poison file showing the status (and allowing
> it to modified) of slab poisoning
> 
> Ok, it looks like poisoning is only available if CONFIG_SLUB_DEBUG is
> set. Since it is not set, don't worry about it ;)

I actually do have SLUB_DEBUG set to 'y' in the kernel whose dmesg I
last sent you.

> -Chris
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Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Chris Wilson]

Quoting Alexandru Chirvasitu (2018-01-05 19:37:24)
> I'll try. I need a bit of clarification:
> 
> On Fri, Jan 05, 2018 at 05:52:25PM +, Chris Wilson wrote:
> > Quoting Alexandru Chirvasitu (2018-01-03 21:53:15)
> > > All right, here's the dmesg from the kernel compiled from drm-tip (in
> > > sync with upstream at the time of the compilation earlier today), with
> > > 
> > > CONFIG_DRM_I915_DEBUG_GEM=y
> > > 
> > > I crashed it by opening 20+ xterm windows. Doesn't always do it though
> > > (tried this before).
> > 
> > Sorry, still stumped. It's still the same use-after-free and no asserts
> > hit. Can you keep KASAN enabled but disable slab/page poisoning? Hmm, I
> > think it has to be page poisoning doing the 0x6b as SLAB_POISON is
> > disabled by default.
> 
> Would this have to be through a new compilation, or would it do to
> just remove the poisoning kernel parameter on boot? 

CONFIG_PAGE_POISONING

> 
> > (You could check by enabling slabstats can looking in sysfs.)
> 
> Sorry, I was having some trouble parsing this; what do I check again
> and how?
> 
> Does 'slabstats' refer to another kernel config option or something
> else?

It would be CONFIG_SLUB_STATS and then you would a
/sys/kernel/slab/i915_dependency/ directory with all the details of the
slab, and in particular a poison file showing the status (and allowing
it to modified) of slab poisoning

Ok, it looks like poisoning is only available if CONFIG_SLUB_DEBUG is
set. Since it is not set, don't worry about it ;)
-Chris
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Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Alexandru Chirvasitu]

I'll try. I need a bit of clarification:

On Fri, Jan 05, 2018 at 05:52:25PM +, Chris Wilson wrote:
> Quoting Alexandru Chirvasitu (2018-01-03 21:53:15)
> > All right, here's the dmesg from the kernel compiled from drm-tip (in
> > sync with upstream at the time of the compilation earlier today), with
> > 
> > CONFIG_DRM_I915_DEBUG_GEM=y
> > 
> > I crashed it by opening 20+ xterm windows. Doesn't always do it though
> > (tried this before).
> 
> Sorry, still stumped. It's still the same use-after-free and no asserts
> hit. Can you keep KASAN enabled but disable slab/page poisoning? Hmm, I
> think it has to be page poisoning doing the 0x6b as SLAB_POISON is
> disabled by default.

Would this have to be through a new compilation, or would it do to
just remove the poisoning kernel parameter on boot? 

> (You could check by enabling slabstats can looking in sysfs.)

Sorry, I was having some trouble parsing this; what do I check again
and how?

Does 'slabstats' refer to another kernel config option or something
else?

I apologize, most of these options I'm fiddling with are not familiar
to me..

> My goal is to get that kasan trace telling me who about the
> freed object.
> -Chris
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Re: [Intel-gfx] [PATCH v2 2/2] kms_content_protection: Add Content Protection test

[Sean Paul]

On Tue, Dec 19, 2017 at 9:28 AM, Ramalingam C  wrote:
> Adding few more findings from the IGT usage with kernel solutions.
>
>
>
> On Wednesday 13 December 2017 04:07 PM, Ramalingam C wrote:
>>
>> Sean,
>>
>> Adding few more observations.
>>
>>
>> On Thursday 07 December 2017 05:47 AM, Sean Paul wrote:
>>>
>>> Pretty simple test:
>>> - initializes the output
>>> - clears the content protection property
>>> - verifies that it clears
>>> - sets the content protection property to desired
>>> - verifies that it transitions to enabled
>>>
>>> Does this for both legacy and atomic.
>>>
>>> Changes in v2:
>>> - Don't check for i915 gen
>>> - Skip test if Content Protection property is absent
>>>
>>> Signed-off-by: Sean Paul 
>>> ---
>>>   lib/igt_kms.c  |   3 +-
>>>   lib/igt_kms.h  |   1 +
>>>   tests/Makefile.sources |   1 +
>>>   tests/kms_content_protection.c | 129
>>> +
>>>   tests/meson.build  |   1 +
>>>   5 files changed, 134 insertions(+), 1 deletion(-)
>>>   create mode 100644 tests/kms_content_protection.c
>>>
>>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
>>> index 125ecb19..907db694 100644
>>> --- a/lib/igt_kms.c
>>> +++ b/lib/igt_kms.c
>>> @@ -190,7 +190,8 @@ const char
>>> *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
>>>   "scaling mode",
>>>   "CRTC_ID",
>>>   "DPMS",
>>> -"Broadcast RGB"
>>> +"Broadcast RGB",
>>> +"Content Protection"
>>>   };
>>> /*
>>> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
>>> index 2a480bf3..93e59dc7 100644
>>> --- a/lib/igt_kms.h
>>> +++ b/lib/igt_kms.h
>>> @@ -118,6 +118,7 @@ enum igt_atomic_connector_properties {
>>>  IGT_CONNECTOR_CRTC_ID,
>>>  IGT_CONNECTOR_DPMS,
>>>  IGT_CONNECTOR_BROADCAST_RGB,
>>> +   IGT_CONNECTOR_CONTENT_PROTECTION,
>>>  IGT_NUM_CONNECTOR_PROPS
>>>   };
>>>   diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>>> index 34ca71a0..e0466411 100644
>>> --- a/tests/Makefile.sources
>>> +++ b/tests/Makefile.sources
>>> @@ -179,6 +179,7 @@ TESTS_progs = \
>>>   kms_chv_cursor_fail \
>>>   kms_color \
>>>   kms_concurrent \
>>> +kms_content_protection\
>>>   kms_crtc_background_color \
>>>   kms_cursor_crc \
>>>   kms_cursor_legacy \
>>> diff --git a/tests/kms_content_protection.c
>>> b/tests/kms_content_protection.c
>>> new file mode 100644
>>> index ..5d61b257
>>> --- /dev/null
>>> +++ b/tests/kms_content_protection.c
>>> @@ -0,0 +1,129 @@
>>> +/*
>>> + * Copyright © 2017 Google, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining
>>> a
>>> + * copy of this software and associated documentation files (the
>>> "Software"),
>>> + * to deal in the Software without restriction, including without
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the
>>> next
>>> + * paragraph) shall be included in all copies or substantial portions of
>>> the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
>>> SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#include "igt.h"
>>> +
>>> +IGT_TEST_DESCRIPTION("Test content protection (HDCP)");
>>> +
>>> +typedef struct {
>>> +int drm_fd;
>>> +igt_display_t display;
>>> +} data_t;
>>> +
>>> +static bool
>>> +wait_for_prop_value(igt_output_t *output, uint64_t expected)
>>> +{
>>> +uint64_t val;
>>> +int i;
>>> +
>>> +for (i = 0; i < 2000; i++) {
>>
>> we need 5+Sec to complete the Second part of authentication, in case of
>> repeater with max downstream topology.
>> So we might need to wait for 6000(6Sec) loops!?
>>>
>>> +val = igt_output_get_prop(output,
>>> +  IGT_CONNECTOR_CONTENT_PROTECTION);
>>> +if (val == expected)
>>> +return true;
>>> +usleep(1000);
>>> +}
>>> +igt_info("prop_value mismatch %ld != %ld\n", val, expected);
>>> +return false;
>>> +}
>>> +
>>> +static void
>>> +test_pipe_output(igt_display_t *display, const enum pipe pipe,
>>> + igt_output_t *output, enum igt_commit_style s)
>>> +{
>>> +drmModeModeInfo mode;
>>> +igt_plane_t *primary;
>>> +

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable vblanks after verifying power domain states.

[Pandiyan, Dhinakaran]

On Fri, 2018-01-05 at 10:09 -0800, Rodrigo Vivi wrote:
> On Fri, Jan 05, 2018 at 11:23:54AM +, Maarten Lankhorst wrote:
> > Op 04-01-18 om 22:51 schreef Pandiyan, Dhinakaran:
> > > On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
> > >> Wouldn't it be better to make intel_power_domains_verify_state work
> > >> correctly with the vblank irq?
> > > I tried to :) Since I changed the domain_use_count to atomic_t and moved
> > > it outside of the locks, verify_state became racy. Let me take another
> > > look.
> > >
> > > -DK
> > 
> > It sucks that we end up with 2 ways to handle power domains..
> 
> I also don't like that, but if we need to go with that I believe
> we need to go with a generic approach.
> 
> > 
> > I'm trying to think of a cleaner way, coming up with none. :(
> 
> me neither :(
> 
> > 
> > It would have been nice if we could do something like a seqlock for
> > the refcounts, but that would prevent us from blocking too..
> 
> reader does't block and writer doesn't wait for the reader so not
> sure we could use this.
> 
> > 
> > Is it only the DC off power well we care about?
> 

Yeah, that is sufficient to deal with frame counter resets.

> It is the only call to any power well that comes from an spin-locked
> region. So we can't sleep.
> 
> I think we looked to the option of changing the entire pw to spin locks
> instead of mutexs, but we concluded it wasn't a viable option as well.
> I just can't remember why right now.

Enable/disable for other power wells have wait_for_register()

> 
> Thanks,
> Rodrigo.
> 
> > 
> > ~Maarten
> > 
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Apply cond_resched() liberally to igt_ggtt_page()

[Chris Wilson]

Quoting Chris Wilson (2018-01-05 17:39:04)
> Still occasionally hitting timeouts on bxt with igt_ggtt_page(), so
> include some cond_resched() to keep the nmi watchdog appeased.

On my bxt with kasan+lockdep, igt_ggtt_page() takes 0.3s. And on cases
where CI passes, igt_ggtt_page() takes 0.1s. It's not a lack of
cond_resched() causing the timeouts.
-Chris
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable vblanks after verifying power domain states.

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 11:23:54AM +, Maarten Lankhorst wrote:
> Op 04-01-18 om 22:51 schreef Pandiyan, Dhinakaran:
> > On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
> >> Wouldn't it be better to make intel_power_domains_verify_state work
> >> correctly with the vblank irq?
> > I tried to :) Since I changed the domain_use_count to atomic_t and moved
> > it outside of the locks, verify_state became racy. Let me take another
> > look.
> >
> > -DK
> 
> It sucks that we end up with 2 ways to handle power domains..

I also don't like that, but if we need to go with that I believe
we need to go with a generic approach.

> 
> I'm trying to think of a cleaner way, coming up with none. :(

me neither :(

> 
> It would have been nice if we could do something like a seqlock for
> the refcounts, but that would prevent us from blocking too..

reader does't block and writer doesn't wait for the reader so not
sure we could use this.

> 
> Is it only the DC off power well we care about?

It is the only call to any power well that comes from an spin-locked
region. So we can't sleep.

I think we looked to the option of changing the entire pw to spin locks
instead of mutexs, but we concluded it wasn't a viable option as well.
I just can't remember why right now.

Thanks,
Rodrigo.

> 
> ~Maarten
> 
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Re: [Intel-gfx] [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 05:48:35PM +, Mark Janes wrote:
> Tested-by: Mark Janes 

Thanks for that and sorry for missing it before merging :(
Also I don't know why patchwork didn't get it automatically.

> 
> Geminilake GPU hangs caused by tesselation tests in VulkanCTS and GLCTS
> are fixed by the Mesa patch that toggles this bit.
> 
> Kenneth Graunke  writes:
> 
> > Geminilake requires the 3D driver to select whether barriers are
> > intended for compute shaders, or tessellation control shaders, by
> > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > switching pipelines.  Failure to do this properly can result in GPU
> > hangs.
> >
> > Unfortunately, this means it needs to switch mid-batch, so only
> > userspace can properly set it.  To facilitate this, the kernel needs
> > to whitelist the register.
> >
> > The workarounds page currently tags this as applying to Broxton only,
> > but that doesn't make sense.  The documentation for the register it
> > references says the bit userspace is supposed to toggle only exists on
> > Geminilake.  Empirically, the Mesa patch to toggle this bit appears to
> > fix intermittent GPU hangs in tessellation control shader barrier tests
> > on Geminilake; we haven't seen those hangs on Broxton.
> >
> > v2: Mention WA #0862 in the comment (it doesn't have a name).
> >
> > Signed-off-by: Kenneth Graunke 
> > Acked-by: Rodrigo Vivi 
> > Cc: sta...@vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h| 2 ++
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
> >  2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 966e4df9700e..505c605eff98 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7079,6 +7079,8 @@ enum {
> >  #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
> >  #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
> >  
> > +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > +
> >  #define GEN7_L3SQCREG1 _MMIO(0xB010)
> >  #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index ebdcbcbacb3c..6bb51a502b8b 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct 
> > intel_engine_cs *engine)
> > if (ret)
> > return ret;
> >  
> > +   /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
> > +   ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> > +   if (ret)
> > +   return ret;
> > +
> > /* WaToEnableHwFixForPushConstHWBug:glk */
> > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> >   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> > -- 
> > 2.15.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Apply cond_resched() liberally to igt_ggtt_page()

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Apply cond_resched() liberally to igt_ggtt_page()
URL   : https://patchwork.freedesktop.org/series/36095/
State : success

== Summary ==

Series 36095v1 drm/i915/selftests: Apply cond_resched() liberally to 
igt_ggtt_page()
https://patchwork.freedesktop.org/api/1.0/series/36095/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:493s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:486s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:479s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:462s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:452s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:264s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:407s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:444s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:410s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:497s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:583s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:396s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:606s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:466s

914d61a8fb5fc53f6b0366167210468147495b3f drm-tip: 2018y-01m-05d-09h-12m-18s UTC 
integration manifest
1818471e8fd1 drm/i915/selftests: Apply cond_resched() liberally to 
igt_ggtt_page()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7620/issues.html
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Re: [Intel-gfx] [PATCH i-g-t v12] tests/kms_frontbuffer_tracking: Including DRRS test coverage

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 11:40:29AM +, Lohith BS wrote:
> Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
> refresh rate to the lowest vrefresh supported by panel, when frame is
> not flipped for more than a Sec.
> 
> In kernel, DRRS uses the front buffer tracking infrastructure.
> Hence DRRS test coverage is added along with other frontbuffer tracking
> based features such as FBC and PSR tests.
> 
> Here, we are testing DRRS with other features in all possible
> combinations, in all required test cases, to capture any possible
> regression.
> 
> v2: Addressed the comments and suggestions from Vlad, Marius.
> The signoff details from the earlier work are also included.
> 
> v3: Modified vblank rate calculation by using reply-sequence,
> provided by drmWaitVBlank, as suggested by Chris Wilson.
> 
> v4: As suggested from Chris Wilson and Daniel Vetter
> 1) Avoided using pthread for calculating vblank refresh rate,
>instead used drmWaitVBlank reply sequence.
> 2) Avoided using kernel-specific info like transitional delays,
>instead polling mechanism with timeout is used.
> 3) Included edp-DRRS as a subtest in kms_frontbuffer_tracking.c,
>instead of having a separate test.
> 
> v5: This patch adds DRRS as a new feature in the
> kms_frontbuffer_tracking IGT.
> DRRS switch to lower vrefresh rate is tested at slow-draw subtest.
> 
> Note:
> 1) Currently kernel doesn't have support to enable and disable
>the DRRS feature dynamically(as in case of PSR). Hence if the
>panel supports DRRS it will be enabled by default.
> 
> This is in continuation of last patch
>   "https://patchwork.freedesktop.org/patch/162726/;
> 
> v6: This patch adds runtime enable and disable feature for testing DRRS
> 
> v7: This patch adds runtime enable and disable feature for testing DRRS
> through debugfs entry "i915_drrs_ctl".
> 
> v8: Commit message is updated to reflect current implementation.
> 
> v9: Addressed Paulo Zanoni comments.
> Check for DRRS_LOW at tests with OFFSCREEN + FBS_INDIVIDUAL.
> 
> v10: Corrected DRRS state expectation in suspend related subtests.
> 
> v11: Removing the global flag is_psr_drrs_combo [Rodrigo].
> 
> v12: Rewriting the DRRS inactive deduction [Rodrigo].
> 
> Signed-off-by: Lohith BS 
> Signed-off-by: aknautiy 

I was almost adding the rv-b here, but I will step back while CI is not
fully happy with the patch:

https://patchwork.freedesktop.org/series/32888/

regressed many sub-tests on snb and hsw...

> ---
>  tests/kms_frontbuffer_tracking.c | 178 
> +--
>  1 file changed, 170 insertions(+), 8 deletions(-)
> 
> diff --git a/tests/kms_frontbuffer_tracking.c 
> b/tests/kms_frontbuffer_tracking.c
> index 1601cab..4b87273 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -34,7 +34,7 @@
>  
>  
>  IGT_TEST_DESCRIPTION("Test the Kernel's frontbuffer tracking mechanism and "
> -  "its related features: FBC and PSR");
> +  "its related features: FBC, PSR and DRRS");
>  
>  /*
>   * One of the aspects of this test is that, for every subtest, we try 
> different
> @@ -105,8 +105,9 @@ struct test_mode {
>   FEATURE_NONE  = 0,
>   FEATURE_FBC   = 1,
>   FEATURE_PSR   = 2,
> - FEATURE_COUNT = 4,
> - FEATURE_DEFAULT = 4,
> + FEATURE_DRRS  = 4,
> + FEATURE_COUNT = 8,
> + FEATURE_DEFAULT = 8,
>   } feature;
>  
>   /* Possible pixel formats. We just use FORMAT_DEFAULT for most tests and
> @@ -156,6 +157,7 @@ struct rect {
>  struct {
>   int fd;
>   int debugfs;
> + int drrs_debugfs_fd;
>   drmModeResPtr res;
>   drmModeConnectorPtr connectors[MAX_CONNECTORS];
>   drmModeEncoderPtr encoders[MAX_ENCODERS];
> @@ -182,6 +184,13 @@ struct {
>   .can_test = false,
>  };
>  
> +#define MAX_DRRS_STATUS_BUF_LEN 256
> +
> +struct {
> + bool can_test;
> +} drrs = {
> + .can_test = false,
> +};
>  
>  #define SINK_CRC_SIZE 12
>  typedef struct {
> @@ -825,6 +834,60 @@ static void psr_print_status(void)
>   igt_info("PSR status:\n%s\n", buf);
>  }
>  
> +void drrs_set(unsigned int val)
> +{
> + char buf[2];
> +
> + igt_debug("Manually %sabling DRRS. %llu\n", val ? "en" : "dis", val);
> + snprintf(buf, sizeof(buf), "%d", val);
> + igt_assert_eq(write(drm.drrs_debugfs_fd,
> +   buf, strlen(buf)), strlen(buf));
> +}
> +
> +static bool is_drrs_high(void)
> +{
> + char buf[MAX_DRRS_STATUS_BUF_LEN];
> +
> + debugfs_read("i915_drrs_status", buf);
> + return strstr(buf, "DRRS_HIGH_RR");
> +}
> +
> +static bool is_drrs_low(void)
> +{
> + char buf[MAX_DRRS_STATUS_BUF_LEN];
> +
> + debugfs_read("i915_drrs_status", buf);
> + return strstr(buf, "DRRS_LOW_RR");
> +}
> +
> 

Re: [Intel-gfx] PROBLEM: i915 causes complete desktop freezes in 4.15-rc5

[Chris Wilson]

Quoting Alexandru Chirvasitu (2018-01-03 21:53:15)
> All right, here's the dmesg from the kernel compiled from drm-tip (in
> sync with upstream at the time of the compilation earlier today), with
> 
> CONFIG_DRM_I915_DEBUG_GEM=y
> 
> I crashed it by opening 20+ xterm windows. Doesn't always do it though
> (tried this before).

Sorry, still stumped. It's still the same use-after-free and no asserts
hit. Can you keep KASAN enabled but disable slab/page poisoning? Hmm, I
think it has to be page poisoning doing the 0x6b as SLAB_POISON is
disabled by default. (You could check by enabling slabstats can looking
in sysfs.) My goal is to get that kasan trace telling me who about the
freed object.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 08:59:05AM +, Kenneth Graunke wrote:
> Geminilake requires the 3D driver to select whether barriers are
> intended for compute shaders, or tessellation control shaders, by
> whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> switching pipelines.  Failure to do this properly can result in GPU
> hangs.
> 
> Unfortunately, this means it needs to switch mid-batch, so only
> userspace can properly set it.  To facilitate this, the kernel needs
> to whitelist the register.
> 
> The workarounds page currently tags this as applying to Broxton only,
> but that doesn't make sense.  The documentation for the register it
> references says the bit userspace is supposed to toggle only exists on
> Geminilake.  Empirically, the Mesa patch to toggle this bit appears to
> fix intermittent GPU hangs in tessellation control shader barrier tests
> on Geminilake; we haven't seen those hangs on Broxton.

I just read the bit definition and fully agree with this.

> 
> v2: Mention WA #0862 in the comment (it doesn't have a name).
> 
> Signed-off-by: Kenneth Graunke 
> Acked-by: Rodrigo Vivi 
> Cc: sta...@vger.kernel.org

Merged, thanks.

> ---
>  drivers/gpu/drm/i915/i915_reg.h| 2 ++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 966e4df9700e..505c605eff98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7079,6 +7079,8 @@ enum {
>  #define GEN9_SLICE_COMMON_ECO_CHICKEN0   _MMIO(0x7308)
>  #define  DISABLE_PIXEL_MASK_CAMMING  (1<<14)
>  
> +#define GEN9_SLICE_COMMON_ECO_CHICKEN1   _MMIO(0x731c)
> +
>  #define GEN7_L3SQCREG1   _MMIO(0xB010)
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index ebdcbcbacb3c..6bb51a502b8b 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs 
> *engine)
>   if (ret)
>   return ret;
>  
> + /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
> + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> + if (ret)
> + return ret;
> +
>   /* WaToEnableHwFixForPushConstHWBug:glk */
>   WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> -- 
> 2.15.1
> 
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Re: [Intel-gfx] [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Mark Janes]

Tested-by: Mark Janes 

Geminilake GPU hangs caused by tesselation tests in VulkanCTS and GLCTS
are fixed by the Mesa patch that toggles this bit.

Kenneth Graunke  writes:

> Geminilake requires the 3D driver to select whether barriers are
> intended for compute shaders, or tessellation control shaders, by
> whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> switching pipelines.  Failure to do this properly can result in GPU
> hangs.
>
> Unfortunately, this means it needs to switch mid-batch, so only
> userspace can properly set it.  To facilitate this, the kernel needs
> to whitelist the register.
>
> The workarounds page currently tags this as applying to Broxton only,
> but that doesn't make sense.  The documentation for the register it
> references says the bit userspace is supposed to toggle only exists on
> Geminilake.  Empirically, the Mesa patch to toggle this bit appears to
> fix intermittent GPU hangs in tessellation control shader barrier tests
> on Geminilake; we haven't seen those hangs on Broxton.
>
> v2: Mention WA #0862 in the comment (it doesn't have a name).
>
> Signed-off-by: Kenneth Graunke 
> Acked-by: Rodrigo Vivi 
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/i915_reg.h| 2 ++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 966e4df9700e..505c605eff98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7079,6 +7079,8 @@ enum {
>  #define GEN9_SLICE_COMMON_ECO_CHICKEN0   _MMIO(0x7308)
>  #define  DISABLE_PIXEL_MASK_CAMMING  (1<<14)
>  
> +#define GEN9_SLICE_COMMON_ECO_CHICKEN1   _MMIO(0x731c)
> +
>  #define GEN7_L3SQCREG1   _MMIO(0xB010)
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index ebdcbcbacb3c..6bb51a502b8b 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs 
> *engine)
>   if (ret)
>   return ret;
>  
> + /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
> + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> + if (ret)
> + return ret;
> +
>   /* WaToEnableHwFixForPushConstHWBug:glk */
>   WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> -- 
> 2.15.1
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Re: [Intel-gfx] [PATCH] drm/i915: Add HAS_NATIVE_HDMI2 macro

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 10:43:12AM +, Shashank Sharma wrote:
> GLK/GEN 10 and higher GEN platfomrs sport native HDMI 2.0 controller.
> This patch adds a macro HAS_NATIVE_HDMI2, and uses it to make checks
> in the code more readable.
> 
> Cc: Vivi Rodrigo 
> Cc: Ville Syrjala 
> Signed-off-by: Shashank Sharma 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   | 2 ++
>  drivers/gpu/drm/i915/intel_hdmi.c | 7 +++
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index caebd58..9a4b68b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2719,6 +2719,8 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define BSD2_RINGENGINE_MASK(VCS2)
>  #define ALL_ENGINES  (~0)
>  
> +#define HAS_HDMI2_NATIVE(dev_priv) \
> + (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  #define HAS_ENGINE(dev_priv, id) \
>   (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index bced7b9..ee4e11c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1238,7 +1238,7 @@ static int intel_hdmi_source_max_tmds_clock(struct 
> intel_encoder *encoder)
>   _priv->vbt.ddi_port_info[encoder->port];
>   int max_tmds_clock;
>  
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (HAS_HDMI2_NATIVE(dev_priv))
>   max_tmds_clock = 594000;

I remember someone, probably Ville, saying that here it should be
a platform check instead of the feature because it is a decision
per platform as documented on our spec.

it is gen>=10 for now, but it can probably change in the future.

So I agree with that view and I believe we need to drop this here.

With this dropped feel free to send next v with:
Reviewed-by: Rodrigo Vivi 

>   else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>   max_tmds_clock = 30;
> @@ -1514,8 +1514,7 @@ bool intel_hdmi_compute_config(struct intel_encoder 
> *encoder,
>  
>   pipe_config->lane_count = 4;
>  
> - if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
> -IS_GEMINILAKE(dev_priv))) {
> + if (scdc->scrambling.supported && HAS_HDMI2_NATIVE(dev_priv)) {
>   if (scdc->scrambling.low_rates)
>   pipe_config->hdmi_scrambling = true;
>  
> @@ -2037,7 +2036,7 @@ void intel_hdmi_init_connector(struct 
> intel_digital_port *intel_dig_port,
>   connector->doublescan_allowed = 0;
>   connector->stereo_allowed = 1;
>  
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (HAS_HDMI2_NATIVE(dev_priv))
>   connector->ycbcr_420_allowed = true;
>  
>   intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
> -- 
> 2.7.4
> 
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[Intel-gfx] [PATCH] drm/i915/selftests: Apply cond_resched() liberally to igt_ggtt_page()

[Chris Wilson]

Still occasionally hitting timeouts on bxt with igt_ggtt_page(), so
include some cond_resched() to keep the nmi watchdog appeased.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index bb7cf998fc65..85c19fb24105 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1067,6 +1067,8 @@ static int igt_ggtt_page(void *arg)
ggtt->base.insert_page(>base,
   i915_gem_object_get_dma_address(obj, 0),
   offset, I915_CACHE_NONE, 0);
+
+   cond_resched();
}
 
order = i915_random_order(count, );
@@ -1082,6 +1084,8 @@ static int igt_ggtt_page(void *arg)
vaddr = io_mapping_map_atomic_wc(>iomap, offset);
iowrite32(n, vaddr + n);
io_mapping_unmap_atomic(vaddr);
+
+   cond_resched();
}
i915_gem_flush_ggtt_writes(i915);
 
@@ -1101,6 +1105,8 @@ static int igt_ggtt_page(void *arg)
err = -EINVAL;
break;
}
+
+   cond_resched();
}
 
kfree(order);
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/scheduler: Assert that we do not have a dep cycle back to request

[Patchwork]

== Series Details ==

Series: drm/i915/scheduler: Assert that we do not have a dep cycle back to 
request
URL   : https://patchwork.freedesktop.org/series/36082/
State : success

== Summary ==

Series 36082v1 drm/i915/scheduler: Assert that we do not have a dep cycle back 
to request
https://patchwork.freedesktop.org/api/1.0/series/36082/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +2
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:423s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:494s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:457s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:264s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:570s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:505s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:527s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:406s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:569s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:601s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:468s

914d61a8fb5fc53f6b0366167210468147495b3f drm-tip: 2018y-01m-05d-09h-12m-18s UTC 
integration manifest
1fc4e0c76021 drm/i915/scheduler: Assert that we do not have a dep cycle back to 
request

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7619/issues.html
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[Intel-gfx] [PATCH] drm/i915/scheduler: Assert that we do not have a dep cycle back to request

[Chris Wilson]

When reprioritising a request, we build a list of its dependencies in
topological order. This should leave our origin request as the first
element in our list, if it moves we have a dependency cycle and severe
breakage. Assert that it doesn't move.

Complete, but expensive checking is done by swfence, this assert is more
about documenting the topologically ordered list.

Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_lrc.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4e150b095a11..42705e3875cd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1050,6 +1050,13 @@ static void execlists_schedule(struct 
drm_i915_gem_request *request, int prio)
}
}
 
+   /*
+* We should never have a dep cycle back to ourselves, leaving
+* the original request as the origin of our topologically sorted
+* list.
+*/
+   GEM_BUG_ON(list_first_entry(, typeof(stack), dfs_link) != );
+
/*
 * If we didn't need to bump any existing priorities, and we haven't
 * yet submitted this request (i.e. there is no potential race with
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev3)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev3)
URL   : https://patchwork.freedesktop.org/series/35699/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3604
914d61a8fb5f drm-tip: 2018y-01m-05d-09h-12m-18s UTC integration manifest

No testlist changes.

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:276s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:467s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:262s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:576s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:524s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:495s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:535s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:595s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_751/issues.html
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[Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 tests/kms_frontbuffer_tracking.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab45..8b440dadc 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -927,6 +927,10 @@ static bool fbc_stride_not_supported(void)
 
 static bool fbc_wait_until_enabled(void)
 {
+   if (fbc_is_enabled())
+   return true;
+
+   fbc_print_status();
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-- 
2.15.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev7)

[Patchwork]

== Series Details ==

Series: tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev7)
URL   : https://patchwork.freedesktop.org/series/32888/
State : failure

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass   -> FAIL   (shard-snb) fdo#103167 +43
Subgroup fbc-stridechange:
pass   -> FAIL   (shard-snb) fdo#101623 +61
Subgroup fbc-tilingchange:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-rgb565-draw-mmap-cpu:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-rgb101010-draw-blt:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-wc:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-onoff:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-suspend:
pass   -> FAIL   (shard-hsw) fdo#103540
Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-spr-indfb-onoff:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-spr-indfb-draw-pwrite:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-rgb101010-draw-pwrite:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-rgb101010-draw-mmap-gtt:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
pass   -> FAIL   (shard-snb)
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-modeset-suspend-interruptible:
skip   -> PASS   (shard-snb)
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-a:
skip   -> PASS   (shard-snb)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
skip   -> PASS   (shard-hsw)

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:3283 pass:1469 dwarn:1   dfail:0   fail:80  skip:1733 
time:8832s
shard-snbtotal:3283 pass:1243 dwarn:1   dfail:0   fail:79  skip:1960 
time:7729s
Blacklisted hosts:
shard-apltotal:3283 pass:1612 dwarn:1   dfail:0   fail:99  skip:1571 
time:13272s
shard-kbltotal:3283 pass:1738 dwarn:1   dfail:0   fail:96  skip:1448 
time:10400s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_749/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev2)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev2)
URL   : https://patchwork.freedesktop.org/series/35699/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3604
914d61a8fb5f drm-tip: 2018y-01m-05d-09h-12m-18s UTC integration manifest

No testlist changes.

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> FAIL   (fi-skl-6700k2)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650)

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:367s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:276s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:265s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:409s
fi-ilk-650   total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:462s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:495s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:576s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:263  dwarn:0   dfail:0   fail:1   skip:24  
time:498s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:531s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y total:218  pass:197  dwarn:0   dfail:0   fail:0   skip:20 

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_750/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/14] drm/i915: Only defer freeing of fence callback when also using the timer

[Patchwork]

== Series Details ==

Series: series starting with [01/14] drm/i915: Only defer freeing of fence 
callback when also using the timer
URL   : https://patchwork.freedesktop.org/series/36077/
State : success

== Summary ==

Series 36077v1 series starting with [01/14] drm/i915: Only defer freeing of 
fence callback when also using the timer
https://patchwork.freedesktop.org/api/1.0/series/36077/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +2
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:433s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:483s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:261s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:501s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:572s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:498s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:536s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:411s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-cnl-y total:288  pass:261  dwarn:0   dfail:0   fail:1   skip:26  
time:594s

914d61a8fb5fc53f6b0366167210468147495b3f drm-tip: 2018y-01m-05d-09h-12m-18s UTC 
integration manifest
9c5ac8c6b3a1 drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list
ef2164c7b9aa drm/i915: Only signal from interrupt when requested
c6f17f0f5777 drm/i915: Move the irq_counter inside the spinlock
ffe4588e23e2 drm/i915: Reduce spinlock hold time during notify_ring() interrupt
cf1c0797fed9 drm/i915/breadcrumbs: Drop request reference for the signaler 
thread
05d51ae9363c drm/i915: Trim the retired request queue after submitting
e6252640baec drm/i915: Shrink the request kmem_cache on allocation error
dfa43e787aa3 drm/i915: Shrink the GEM kmem_caches upon idling
6b10d025df62 drm/i915: Move i915_gem_retire_work_handler
7a90e2520dc4 drm/i915: Only attempt to scan the requested number of shrinker 
slabs
37fe06c7363f drm/i915: Use our singlethreaded wq for freeing objects
f0aafc85f53c drm/i915: Rename some shorthand lock classes
aa51bcad9865 drm/i915/fence: Separate timeout mechanism for awaiting on 
dma-fences

[Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 tests/kms_frontbuffer_tracking.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab45..8b440dadc 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -927,6 +927,10 @@ static bool fbc_stride_not_supported(void)
 
 static bool fbc_wait_until_enabled(void)
 {
+   if (fbc_is_enabled())
+   return true;
+
+   fbc_print_status();
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-- 
2.15.1

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[Intel-gfx] [PATCH 01/14] drm/i915: Only defer freeing of fence callback when also using the timer

[Chris Wilson]

Without an accompanying timer (for internal fences), we can free the
fence callback immediately as we do not need to employ the RCU barrier
to serialise with the timer. By avoiding the RCU delay, we can avoid the
extra mempressure under heavy inter-engine request utilisation.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_sw_fence.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index 3669f5eeb91e..13021326d777 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -398,7 +398,12 @@ static void dma_i915_sw_fence_wake(struct dma_fence *dma,
if (fence)
i915_sw_fence_complete(fence);
 
-   irq_work_queue(>work);
+   if (cb->dma) {
+   irq_work_queue(>work);
+   return;
+   }
+
+   kfree(cb);
 }
 
 static void irq_i915_sw_fence_work(struct irq_work *wrk)
@@ -437,10 +442,12 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
i915_sw_fence_await(fence);
 
cb->dma = NULL;
-   timer_setup(>timer, timer_i915_sw_fence_wake, TIMER_IRQSAFE);
-   init_irq_work(>work, irq_i915_sw_fence_work);
if (timeout) {
cb->dma = dma_fence_get(dma);
+   init_irq_work(>work, irq_i915_sw_fence_work);
+
+   timer_setup(>timer,
+   timer_i915_sw_fence_wake, TIMER_IRQSAFE);
mod_timer(>timer, round_jiffies_up(jiffies + timeout));
}
 
-- 
2.15.1

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[Intel-gfx] [PATCH 02/14] drm/i915/fence: Separate timeout mechanism for awaiting on dma-fences

[Chris Wilson]

As the timeout mechanism has grown more and more complicated, using
multiple deferred tasks and more than doubling the size of our struct,
split the two implementations to streamline the simpler no-timeout
callback variant.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_sw_fence.c | 61 +++-
 1 file changed, 40 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index 13021326d777..1de5173e53a2 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -365,18 +365,31 @@ int i915_sw_fence_await_sw_fence_gfp(struct i915_sw_fence 
*fence,
 struct i915_sw_dma_fence_cb {
struct dma_fence_cb base;
struct i915_sw_fence *fence;
+};
+
+struct i915_sw_dma_fence_cb_timer {
+   struct i915_sw_dma_fence_cb base;
struct dma_fence *dma;
struct timer_list timer;
struct irq_work work;
struct rcu_head rcu;
 };
 
+static void dma_i915_sw_fence_wake(struct dma_fence *dma,
+  struct dma_fence_cb *data)
+{
+   struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base);
+
+   i915_sw_fence_complete(cb->fence);
+   kfree(cb);
+}
+
 static void timer_i915_sw_fence_wake(struct timer_list *t)
 {
-   struct i915_sw_dma_fence_cb *cb = from_timer(cb, t, timer);
+   struct i915_sw_dma_fence_cb_timer *cb = from_timer(cb, t, timer);
struct i915_sw_fence *fence;
 
-   fence = xchg(>fence, NULL);
+   fence = xchg(>base.fence, NULL);
if (!fence)
return;
 
@@ -388,27 +401,24 @@ static void timer_i915_sw_fence_wake(struct timer_list *t)
i915_sw_fence_complete(fence);
 }
 
-static void dma_i915_sw_fence_wake(struct dma_fence *dma,
-  struct dma_fence_cb *data)
+static void dma_i915_sw_fence_wake_timer(struct dma_fence *dma,
+struct dma_fence_cb *data)
 {
-   struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base);
+   struct i915_sw_dma_fence_cb_timer *cb =
+   container_of(data, typeof(*cb), base.base);
struct i915_sw_fence *fence;
 
-   fence = xchg(>fence, NULL);
+   fence = xchg(>base.fence, NULL);
if (fence)
i915_sw_fence_complete(fence);
 
-   if (cb->dma) {
-   irq_work_queue(>work);
-   return;
-   }
-
-   kfree(cb);
+   irq_work_queue(>work);
 }
 
 static void irq_i915_sw_fence_work(struct irq_work *wrk)
 {
-   struct i915_sw_dma_fence_cb *cb = container_of(wrk, typeof(*cb), work);
+   struct i915_sw_dma_fence_cb_timer *cb =
+   container_of(wrk, typeof(*cb), work);
 
del_timer_sync(>timer);
dma_fence_put(cb->dma);
@@ -422,6 +432,7 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
  gfp_t gfp)
 {
struct i915_sw_dma_fence_cb *cb;
+   dma_fence_func_t func;
int ret;
 
debug_fence_assert(fence);
@@ -430,7 +441,10 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
if (dma_fence_is_signaled(dma))
return 0;
 
-   cb = kmalloc(sizeof(*cb), gfp);
+   cb = kmalloc(timeout ?
+sizeof(struct i915_sw_dma_fence_cb_timer) :
+sizeof(struct i915_sw_dma_fence_cb),
+gfp);
if (!cb) {
if (!gfpflags_allow_blocking(gfp))
return -ENOMEM;
@@ -441,21 +455,26 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
cb->fence = fence;
i915_sw_fence_await(fence);
 
-   cb->dma = NULL;
+   func = dma_i915_sw_fence_wake;
if (timeout) {
-   cb->dma = dma_fence_get(dma);
-   init_irq_work(>work, irq_i915_sw_fence_work);
+   struct i915_sw_dma_fence_cb_timer *timer =
+   container_of(cb, typeof(*timer), base);
 
-   timer_setup(>timer,
+   timer->dma = dma_fence_get(dma);
+   init_irq_work(>work, irq_i915_sw_fence_work);
+
+   timer_setup(>timer,
timer_i915_sw_fence_wake, TIMER_IRQSAFE);
-   mod_timer(>timer, round_jiffies_up(jiffies + timeout));
+   mod_timer(>timer, round_jiffies_up(jiffies + timeout));
+
+   func = dma_i915_sw_fence_wake_timer;
}
 
-   ret = dma_fence_add_callback(dma, >base, dma_i915_sw_fence_wake);
+   ret = dma_fence_add_callback(dma, >base, func);
if (ret == 0) {
ret = 1;
} else {
-   dma_i915_sw_fence_wake(dma, >base);
+   func(dma, >base);
if (ret == -ENOENT) /* 

[Intel-gfx] [PATCH 10/14] drm/i915/breadcrumbs: Drop request reference for the signaler thread

[Chris Wilson]

If we remember to cancel the signaler on a request when retiring it
(after we know that the request has been signaled), we do not need to
carry an additional request in the signaler itself. This prevents an
issue whereby the signaler threads may be delayed and hold on to
thousands of request references, causing severe memory fragmentation and
premature oom (most noticeable on 32b snb due to the limited GFP_KERNEL
and frequent use of inter-engine fences).

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c  |   6 +-
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 149 +--
 2 files changed, 85 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 4107ee4afd83..4f4e4f3ff56f 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -441,7 +441,10 @@ static void i915_gem_request_retire(struct 
drm_i915_gem_request *request)
spin_lock_irq(>lock);
if (request->waitboost)
atomic_dec(>i915->gt_pm.rps.num_waiters);
-   dma_fence_signal_locked(>fence);
+   if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+   dma_fence_signal_locked(>fence);
+   if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
+   intel_engine_cancel_signaling(request);
spin_unlock_irq(>lock);
 
i915_priotree_fini(request->i915, >priotree);
@@ -732,6 +735,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
 
/* No zalloc, must clear what we need by hand */
req->global_seqno = 0;
+   req->signaling.wait.seqno = 0;
req->file_priv = NULL;
req->batch = NULL;
req->capture_list = NULL;
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 3b8fff28a7b0..4ee495f7476f 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -235,7 +235,7 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs 
*engine)
struct intel_wait *wait, *n;
 
if (!b->irq_armed)
-   goto wakeup_signaler;
+   return;
 
/*
 * We only disarm the irq when we are idle (all requests completed),
@@ -260,14 +260,6 @@ void intel_engine_disarm_breadcrumbs(struct 
intel_engine_cs *engine)
b->waiters = RB_ROOT;
 
spin_unlock_irq(>rb_lock);
-
-   /*
-* The signaling thread may be asleep holding a reference to a request,
-* that had its signaling cancelled prior to being preempted. We need
-* to kick the signaler, just in case, to release any such reference.
-*/
-wakeup_signaler:
-   wake_up_process(b->signaler);
 }
 
 static bool use_fake_irq(const struct intel_breadcrumbs *b)
@@ -644,6 +636,62 @@ static void signaler_set_rtpriority(void)
 sched_setscheduler_nocheck(current, SCHED_FIFO, );
 }
 
+static void __intel_engine_remove_signal(struct intel_engine_cs *engine,
+struct drm_i915_gem_request *request)
+{
+   struct intel_breadcrumbs *b = >breadcrumbs;
+
+   lockdep_assert_held(>rb_lock);
+
+   /*
+* Wake up all other completed waiters and select the
+* next bottom-half for the next user interrupt.
+*/
+   __intel_engine_remove_wait(engine, >signaling.wait);
+
+   /*
+* Find the next oldest signal. Note that as we have
+* not been holding the lock, another client may
+* have installed an even older signal than the one
+* we just completed - so double check we are still
+* the oldest before picking the next one.
+*/
+   if (request->signaling.wait.seqno) {
+   if (request == rcu_access_pointer(b->first_signal)) {
+   struct rb_node *rb = rb_next(>signaling.node);
+   rcu_assign_pointer(b->first_signal,
+  rb ? to_signaler(rb) : NULL);
+   }
+
+   rb_erase(>signaling.node, >signals);
+   request->signaling.wait.seqno = 0;
+   }
+}
+
+static struct drm_i915_gem_request *first_signal(struct intel_breadcrumbs *b)
+{
+   /*
+* See the big warnings for i915_gem_active_get_rcu() and similarly
+* for dma_fence_get_rcu_safe() that explain the intricacies involved
+* here with defeating CPU/compiler speculation and enforcing
+* the required memory barriers.
+*/
+   do {
+   struct drm_i915_gem_request *request;
+
+   request = rcu_dereference(b->first_signal);
+   if (request)
+   request = i915_gem_request_get_rcu(request);
+
+   barrier();
+
+   if (!request || request == rcu_access_pointer(b->first_signal))
+   return 

[Intel-gfx] [PATCH 08/14] drm/i915: Shrink the request kmem_cache on allocation error

[Chris Wilson]

If we fail to allocate a new request, make sure we recover the pages
that are in the process of being freed by inserting an RCU barrier.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 86c86a17d558..94429405e776 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -696,6 +696,9 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unreserve;
 
+   kmem_cache_shrink(dev_priv->requests);
+   rcu_barrier();
+
req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
if (!req) {
ret = -ENOMEM;
-- 
2.15.1

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[Intel-gfx] [PATCH 13/14] drm/i915: Only signal from interrupt when requested

[Chris Wilson]

Avoid calling dma_fence_signal() from inside the interrupt if we haven't
enabled signaling on the request.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 2 +-
 drivers/gpu/drm/i915/i915_irq.c | 3 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index fef54d9de049..18b9f23dafb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1216,7 +1216,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, );
 
-   intel_wait_init(, req);
+   intel_wait_init();
 
 restart:
do {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e5f76d580010..ea290f102784 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1093,7 +1093,8 @@ static void notify_ring(struct intel_engine_cs *engine)
if (i915_seqno_passed(seqno, wait->seqno)) {
struct drm_i915_gem_request *waiter = wait->request;
 
-   if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+   if (waiter &&
+   !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
  >fence.flags) &&
intel_wait_check_request(wait, waiter))
rq = i915_gem_request_get(waiter);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f406d0ff4612..cea2092d25d9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -874,11 +874,10 @@ static inline u32 intel_hws_preempt_done_address(struct 
intel_engine_cs *engine)
 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
 
-static inline void intel_wait_init(struct intel_wait *wait,
-  struct drm_i915_gem_request *rq)
+static inline void intel_wait_init(struct intel_wait *wait)
 {
wait->tsk = current;
-   wait->request = rq;
+   wait->request = NULL;
 }
 
 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 
seqno)
-- 
2.15.1

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[Intel-gfx] [PATCH 09/14] drm/i915: Trim the retired request queue after submitting

[Chris Wilson]

If we submit a request and see that the previous request on this
timeline was already signaled, we first do not need to add the
dependency tracker for that completed request and secondly we know that
we there is then a large backlog in retiring requests affecting this
timeline. Given that we just submitted more work to the HW, now would be
a good time to catch up on those retirements.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 94429405e776..4107ee4afd83 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1021,7 +1021,7 @@ void __i915_add_request(struct drm_i915_gem_request 
*request, bool flush_caches)
 
prev = i915_gem_active_raw(>last_request,
   >i915->drm.struct_mutex);
-   if (prev) {
+   if (prev && !i915_gem_request_completed(prev)) {
i915_sw_fence_await_sw_fence(>submit, >submit,
 >submitq);
if (engine->schedule)
@@ -1057,6 +1057,9 @@ void __i915_add_request(struct drm_i915_gem_request 
*request, bool flush_caches)
local_bh_disable();
i915_sw_fence_commit(>submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
+
+   if (prev && i915_gem_request_completed(prev))
+   i915_gem_request_retire_upto(prev);
 }
 
 static unsigned long local_clock_us(unsigned int *cpu)
-- 
2.15.1

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[Intel-gfx] [PATCH 11/14] drm/i915: Reduce spinlock hold time during notify_ring() interrupt

[Chris Wilson]

By taking advantage of the RCU protection of the task struct, we can find
the appropriate signaler under the spinlock and then release the spinlock
before waking the task and signaling the fence.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_irq.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..0b272501b738 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1065,21 +1065,24 @@ static void ironlake_rps_change_irq_handler(struct 
drm_i915_private *dev_priv)
 
 static void notify_ring(struct intel_engine_cs *engine)
 {
+   const u32 seqno = intel_engine_get_seqno(engine);
struct drm_i915_gem_request *rq = NULL;
+   struct task_struct *tsk = NULL;
struct intel_wait *wait;
 
-   if (!engine->breadcrumbs.irq_armed)
+   if (unlikely(!engine->breadcrumbs.irq_armed))
return;
 
atomic_inc(>irq_count);
set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
 
+   rcu_read_lock();
+
spin_lock(>breadcrumbs.irq_lock);
wait = engine->breadcrumbs.irq_wait;
if (wait) {
-   bool wakeup = engine->irq_seqno_barrier;
-
-   /* We use a callback from the dma-fence to submit
+   /*
+* We use a callback from the dma-fence to submit
 * requests after waiting on our own requests. To
 * ensure minimum delay in queuing the next request to
 * hardware, signal the fence now rather than wait for
@@ -1090,19 +1093,20 @@ static void notify_ring(struct intel_engine_cs *engine)
 * and to handle coalescing of multiple seqno updates
 * and many waiters.
 */
-   if (i915_seqno_passed(intel_engine_get_seqno(engine),
- wait->seqno)) {
+   if (i915_seqno_passed(seqno, wait->seqno)) {
struct drm_i915_gem_request *waiter = wait->request;
 
-   wakeup = true;
if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
  >fence.flags) &&
intel_wait_check_request(wait, waiter))
rq = i915_gem_request_get(waiter);
-   }
 
-   if (wakeup)
-   wake_up_process(wait->tsk);
+   tsk = wait->tsk;
+   } else {
+   if (engine->irq_seqno_barrier &&
+   i915_seqno_passed(seqno, wait->seqno - 1))
+   tsk = wait->tsk;
+   }
} else {
if (engine->breadcrumbs.irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
@@ -1114,6 +1118,11 @@ static void notify_ring(struct intel_engine_cs *engine)
i915_gem_request_put(rq);
}
 
+   if (tsk && tsk->state != TASK_RUNNING)
+   wake_up_process(tsk);
+
+   rcu_read_unlock();
+
trace_intel_engine_notify(engine, wait);
 }
 
-- 
2.15.1

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[Intel-gfx] [PATCH 12/14] drm/i915: Move the irq_counter inside the spinlock

[Chris Wilson]

Rather than have multiple locked instructions inside the notify_ring()
irq handler, move them inside the spinlock and reduce their intrinsic
locking.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c  |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c  |  6 +++---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 13 -
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  2 +-
 4 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 4f4e4f3ff56f..fef54d9de049 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1130,7 +1130,7 @@ static bool __i915_spin_request(const struct 
drm_i915_gem_request *req,
 * takes to sleep on a request, on the order of a microsecond.
 */
 
-   irq = atomic_read(>irq_count);
+   irq = READ_ONCE(engine->breadcrumbs.irq_count);
timeout_us += local_clock_us();
do {
if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
@@ -1141,7 +1141,7 @@ static bool __i915_spin_request(const struct 
drm_i915_gem_request *req,
 * assume we won't see one in the near future but require
 * the engine->seqno_barrier() to fixup coherency.
 */
-   if (atomic_read(>irq_count) != irq)
+   if (READ_ONCE(engine->breadcrumbs.irq_count) != irq)
break;
 
if (signal_pending_state(state, current))
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b272501b738..e5f76d580010 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1073,9 +1073,6 @@ static void notify_ring(struct intel_engine_cs *engine)
if (unlikely(!engine->breadcrumbs.irq_armed))
return;
 
-   atomic_inc(>irq_count);
-   set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
-
rcu_read_lock();
 
spin_lock(>breadcrumbs.irq_lock);
@@ -1107,6 +1104,9 @@ static void notify_ring(struct intel_engine_cs *engine)
i915_seqno_passed(seqno, wait->seqno - 1))
tsk = wait->tsk;
}
+
+   engine->breadcrumbs.irq_count++;
+   __set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
} else {
if (engine->breadcrumbs.irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ee495f7476f..d5b40208690e 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -98,12 +98,14 @@ static void intel_breadcrumbs_hangcheck(struct timer_list 
*t)
struct intel_engine_cs *engine =
from_timer(engine, t, breadcrumbs.hangcheck);
struct intel_breadcrumbs *b = >breadcrumbs;
+   unsigned int irq_count;
 
if (!b->irq_armed)
return;
 
-   if (b->hangcheck_interrupts != atomic_read(>irq_count)) {
-   b->hangcheck_interrupts = atomic_read(>irq_count);
+   irq_count = READ_ONCE(b->irq_count);
+   if (b->hangcheck_interrupts != irq_count) {
+   b->hangcheck_interrupts = irq_count;
mod_timer(>hangcheck, wait_timeout());
return;
}
@@ -176,7 +178,7 @@ static void irq_enable(struct intel_engine_cs *engine)
 * we still need to force the barrier before reading the seqno,
 * just in case.
 */
-   set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
+   __set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
 
/* Caller disables interrupts */
spin_lock(>i915->irq_lock);
@@ -270,13 +272,14 @@ static bool use_fake_irq(const struct intel_breadcrumbs 
*b)
if (!test_bit(engine->id, >i915->gpu_error.missed_irq_rings))
return false;
 
-   /* Only start with the heavy weight fake irq timer if we have not
+   /*
+* Only start with the heavy weight fake irq timer if we have not
 * seen any interrupts since enabling it the first time. If the
 * interrupts are still arriving, it means we made a mistake in our
 * engine->seqno_barrier(), a timing error that should be transient
 * and unlikely to reoccur.
 */
-   return atomic_read(>irq_count) == b->hangcheck_interrupts;
+   return READ_ONCE(b->irq_count) == b->hangcheck_interrupts;
 }
 
 static void enable_fake_irq(struct intel_breadcrumbs *b)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c5ff203e42d6..f406d0ff4612 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -305,7 +305,6 @@ struct intel_engine_cs {
 
struct drm_i915_gem_object *default_state;
 
- 

[Intel-gfx] [PATCH 14/14] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list

[Chris Wilson]

The goal here is to try and reduce the latency of signaling additional
requests following the wakeup from interrupt by reducing the list of
to-be-signaled requests from an rbtree to a sorted linked list. The
original choice of using an rbtree was to facilitate random insertions
of request into the signaler while maintaining a sorted list. However,
if we assume that most new requests are added when they are submitted,
we see those new requests in execution order making a insertion sort
fast, and the reduction in overhead of each signaler iteration
significant.

Since commit 56299fb7d904 ("drm/i915: Signal first fence from irq handler
if complete"), we signal most fences directly from notify_ring() in the
interrupt handler greatly reducing the amount of work that actually
needs to be done by the signaler kthread. All the thread is then
required to do is operate as the bottom-half, cleaning up after the
interrupt handler and preparing the next waiter. This includes signaling
all later completed fences in a saturated system, but on a mostly idle
system we only have to rebuild the wait rbtree in time for the next
interrupt. With this de-emphasis of the signaler's role, we want to
rejig it's datastructures to reduce the amount of work we require to
both setup the signal tree and maintain it on every interrupt.

References: 56299fb7d904 ("drm/i915: Signal first fence from irq handler if 
complete")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_request.h  |   2 +-
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 277 +--
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   4 +-
 3 files changed, 116 insertions(+), 167 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.h 
b/drivers/gpu/drm/i915/i915_gem_request.h
index 6c607f8dbf92..a2dd3d71c0f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -44,8 +44,8 @@ struct intel_wait {
 };
 
 struct intel_signal_node {
-   struct rb_node node;
struct intel_wait wait;
+   struct list_head link;
 };
 
 struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index d5b40208690e..e978f6828c04 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -350,7 +350,8 @@ static inline void __intel_breadcrumbs_finish(struct 
intel_breadcrumbs *b,
lockdep_assert_held(>rb_lock);
GEM_BUG_ON(b->irq_wait == wait);
 
-   /* This request is completed, so remove it from the tree, mark it as
+   /*
+* This request is completed, so remove it from the tree, mark it as
 * complete, and *then* wake up the associated task. N.B. when the
 * task wakes up, it will find the empty rb_node, discern that it
 * has already been removed from the tree and skip the serialisation
@@ -361,7 +362,8 @@ static inline void __intel_breadcrumbs_finish(struct 
intel_breadcrumbs *b,
rb_erase(>node, >waiters);
RB_CLEAR_NODE(>node);
 
-   wake_up_process(wait->tsk); /* implicit smp_wmb() */
+   if (wait->tsk->state != TASK_RUNNING)
+   wake_up_process(wait->tsk); /* implicit smp_wmb() */
 }
 
 static inline void __intel_breadcrumbs_next(struct intel_engine_cs *engine,
@@ -602,36 +604,6 @@ void intel_engine_remove_wait(struct intel_engine_cs 
*engine,
spin_unlock_irq(>rb_lock);
 }
 
-static bool signal_valid(const struct drm_i915_gem_request *request)
-{
-   return intel_wait_check_request(>signaling.wait, request);
-}
-
-static bool signal_complete(const struct drm_i915_gem_request *request)
-{
-   if (!request)
-   return false;
-
-   /* If another process served as the bottom-half it may have already
-* signalled that this wait is already completed.
-*/
-   if (intel_wait_complete(>signaling.wait))
-   return signal_valid(request);
-
-   /* Carefully check if the request is complete, giving time for the
-* seqno to be visible or if the GPU hung.
-*/
-   if (__i915_request_irq_complete(request))
-   return true;
-
-   return false;
-}
-
-static struct drm_i915_gem_request *to_signaler(struct rb_node *rb)
-{
-   return rb_entry(rb, struct drm_i915_gem_request, signaling.node);
-}
-
 static void signaler_set_rtpriority(void)
 {
 struct sched_param param = { .sched_priority = 1 };
@@ -639,77 +611,25 @@ static void signaler_set_rtpriority(void)
 sched_setscheduler_nocheck(current, SCHED_FIFO, );
 }
 
-static void __intel_engine_remove_signal(struct intel_engine_cs *engine,
-struct drm_i915_gem_request *request)
-{
-   struct intel_breadcrumbs *b = >breadcrumbs;
-
- 

[Intel-gfx] [PATCH 07/14] drm/i915: Shrink the GEM kmem_caches upon idling

[Chris Wilson]

When we finally decide the gpu is idle, that is a good time to shrink
our kmem_caches.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5ef0a18bf52c..8168c7c242a5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4711,6 +4711,21 @@ i915_gem_retire_work_handler(struct work_struct *work)
}
 }
 
+static void shrink_caches(struct drm_i915_private *i915)
+{
+   /*
+* kmem_cache_shrink() discards empty slabs and reorders partially
+* filled slabs to prioritise allocating from the mostly full slabs,
+* with the aim of reducing fragmentation.
+*/
+   kmem_cache_shrink(i915->priorities);
+   kmem_cache_shrink(i915->dependencies);
+   kmem_cache_shrink(i915->requests);
+   kmem_cache_shrink(i915->luts);
+   kmem_cache_shrink(i915->vmas);
+   kmem_cache_shrink(i915->objects);
+}
+
 static inline bool
 new_requests_since_last_retire(const struct drm_i915_private *i915)
 {
@@ -4798,6 +4813,13 @@ i915_gem_idle_work_handler(struct work_struct *work)
GEM_BUG_ON(!dev_priv->gt.awake);
i915_queue_hangcheck(dev_priv);
}
+
+   rcu_barrier();
+
+   if (!new_requests_since_last_retire(dev_priv)) {
+   __i915_gem_free_work(_priv->mm.free_work);
+   shrink_caches(dev_priv);
+   }
 }
 
 int i915_gem_suspend(struct drm_i915_private *dev_priv)
-- 
2.15.1

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[Intel-gfx] [PATCH 06/14] drm/i915: Move i915_gem_retire_work_handler

[Chris Wilson]

In preparation for the next patch, move i915_gem_retire_work_handler()
later to avoid a forward declaration.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 228 
 1 file changed, 114 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a227cc7ea952..5ef0a18bf52c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3310,120 +3310,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private 
*i915)
return true;
 }
 
-static void
-i915_gem_retire_work_handler(struct work_struct *work)
-{
-   struct drm_i915_private *dev_priv =
-   container_of(work, typeof(*dev_priv), gt.retire_work.work);
-   struct drm_device *dev = _priv->drm;
-
-   /* Come back later if the device is busy... */
-   if (mutex_trylock(>struct_mutex)) {
-   i915_gem_retire_requests(dev_priv);
-   mutex_unlock(>struct_mutex);
-   }
-
-   /* Keep the retire handler running until we are finally idle.
-* We do not need to do this test under locking as in the worst-case
-* we queue the retire worker once too often.
-*/
-   if (READ_ONCE(dev_priv->gt.awake)) {
-   i915_queue_hangcheck(dev_priv);
-   queue_delayed_work(dev_priv->wq,
-  _priv->gt.retire_work,
-  round_jiffies_up_relative(HZ));
-   }
-}
-
-static inline bool
-new_requests_since_last_retire(const struct drm_i915_private *i915)
-{
-   return (READ_ONCE(i915->gt.active_requests) ||
-   work_pending(>gt.idle_work.work));
-}
-
-static void
-i915_gem_idle_work_handler(struct work_struct *work)
-{
-   struct drm_i915_private *dev_priv =
-   container_of(work, typeof(*dev_priv), gt.idle_work.work);
-   bool rearm_hangcheck;
-   ktime_t end;
-
-   if (!READ_ONCE(dev_priv->gt.awake))
-   return;
-
-   /*
-* Wait for last execlists context complete, but bail out in case a
-* new request is submitted.
-*/
-   end = ktime_add_ms(ktime_get(), I915_IDLE_ENGINES_TIMEOUT);
-   do {
-   if (new_requests_since_last_retire(dev_priv))
-   return;
-
-   if (intel_engines_are_idle(dev_priv))
-   break;
-
-   usleep_range(100, 500);
-   } while (ktime_before(ktime_get(), end));
-
-   rearm_hangcheck =
-   cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
-
-   if (!mutex_trylock(_priv->drm.struct_mutex)) {
-   /* Currently busy, come back later */
-   mod_delayed_work(dev_priv->wq,
-_priv->gt.idle_work,
-msecs_to_jiffies(50));
-   goto out_rearm;
-   }
-
-   /*
-* New request retired after this work handler started, extend active
-* period until next instance of the work.
-*/
-   if (new_requests_since_last_retire(dev_priv))
-   goto out_unlock;
-
-   /*
-* Be paranoid and flush a concurrent interrupt to make sure
-* we don't reactivate any irq tasklets after parking.
-*
-* FIXME: Note that even though we have waited for execlists to be idle,
-* there may still be an in-flight interrupt even though the CSB
-* is now empty. synchronize_irq() makes sure that a residual interrupt
-* is completed before we continue, but it doesn't prevent the HW from
-* raising a spurious interrupt later. To complete the shield we should
-* coordinate disabling the CS irq with flushing the interrupts.
-*/
-   synchronize_irq(dev_priv->drm.irq);
-
-   intel_engines_park(dev_priv);
-   i915_gem_timelines_park(dev_priv);
-
-   i915_pmu_gt_parked(dev_priv);
-
-   GEM_BUG_ON(!dev_priv->gt.awake);
-   dev_priv->gt.awake = false;
-   rearm_hangcheck = false;
-
-   if (INTEL_GEN(dev_priv) >= 6)
-   gen6_rps_idle(dev_priv);
-
-   intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
-
-   intel_runtime_pm_put(dev_priv);
-out_unlock:
-   mutex_unlock(_priv->drm.struct_mutex);
-
-out_rearm:
-   if (rearm_hangcheck) {
-   GEM_BUG_ON(!dev_priv->gt.awake);
-   i915_queue_hangcheck(dev_priv);
-   }
-}
-
 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
 {
struct drm_i915_private *i915 = to_i915(gem->dev);
@@ -4800,6 +4686,120 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
}
 }
 
+static void
+i915_gem_retire_work_handler(struct work_struct *work)
+{
+   struct drm_i915_private *dev_priv =
+   container_of(work, typeof(*dev_priv), gt.retire_work.work);
+   struct drm_device *dev = _priv->drm;
+

[Intel-gfx] [PATCH 04/14] drm/i915: Use our singlethreaded wq for freeing objects

[Chris Wilson]

As freeing the objects require serialisation on struct_mutex, we should
prefer to use our singlethreaded driver wq that is dedicated to work
requiring struct_mutex (hence serialised).The benefit should be less
clutter on the system wq, allowing it to make progress even when the
driver/struct_mutex is heavily contended.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 51488da373e1..a227cc7ea952 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4734,7 +4734,7 @@ static void __i915_gem_free_object_rcu(struct rcu_head 
*head)
 * detour through a worker.
 */
if (llist_add(>freed, >mm.free_list))
-   schedule_work(>mm.free_work);
+   queue_work(i915->wq, >mm.free_work);
 }
 
 void i915_gem_free_object(struct drm_gem_object *gem_obj)
-- 
2.15.1

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[Intel-gfx] [PATCH 03/14] drm/i915: Rename some shorthand lock classes

[Chris Wilson]

By default, lockdep takes the stringified variable as the name for the
lock class. Quite often, these are constructed from local variables that
are chosen for their brevity resulting in less than distinct class
names. Rename some of the worst offenders encountered in recent reports.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 drivers/gpu/drm/i915/i915_gem_request.c | 2 ++
 drivers/gpu/drm/i915/i915_gem_timeline.c| 4 ++--
 drivers/gpu/drm/i915/i915_gem_userptr.c | 2 ++
 drivers/gpu/drm/i915/i915_utils.h   | 7 +++
 drivers/gpu/drm/i915/intel_breadcrumbs.c| 3 +++
 drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
 7 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ba9f67c256f4..51488da373e1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4459,6 +4459,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
  const struct drm_i915_gem_object_ops *ops)
 {
mutex_init(>mm.lock);
+   lockdep_set_name(>mm.lock, "i915_gem_object->mm");
 
INIT_LIST_HEAD(>vma_list);
INIT_LIST_HEAD(>lut_list);
@@ -4475,6 +4476,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
obj->mm.madv = I915_MADV_WILLNEED;
INIT_RADIX_TREE(>mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(>mm.get_page.lock);
+   lockdep_set_name(>mm.get_page.lock, 
"i915_gem_object->mm.get_page");
 
i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 72bdc203716f..86c86a17d558 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -707,6 +707,8 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
GEM_BUG_ON(req->timeline == engine->timeline);
 
spin_lock_init(>lock);
+   lockdep_set_name(>lock, "i915_request");
+
dma_fence_init(>fence,
   _fence_ops,
   >lock,
diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c 
b/drivers/gpu/drm/i915/i915_gem_timeline.c
index e9fd87604067..82da881e52ae 100644
--- a/drivers/gpu/drm/i915/i915_gem_timeline.c
+++ b/drivers/gpu/drm/i915/i915_gem_timeline.c
@@ -90,7 +90,7 @@ int i915_gem_timeline_init(struct drm_i915_private *i915,
static struct lock_class_key class;
 
return __i915_gem_timeline_init(i915, timeline, name,
-   , ">lock");
+   , "i915_user_timeline");
 }
 
 int i915_gem_timeline_init__global(struct drm_i915_private *i915)
@@ -100,7 +100,7 @@ int i915_gem_timeline_init__global(struct drm_i915_private 
*i915)
return __i915_gem_timeline_init(i915,
>gt.global_timeline,
"[execution]",
-   , "_timeline->lock");
+   , "i915_global_timeline");
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 382a77a1097e..6b08ee481cea 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -170,6 +170,8 @@ i915_mmu_notifier_create(struct mm_struct *mm)
return ERR_PTR(-ENOMEM);
 
spin_lock_init(>lock);
+   lockdep_set_name(>lock, "i915_mmu_notifier");
+
mn->mn.ops = _gem_userptr_notifier;
mn->objects = RB_ROOT_CACHED;
mn->wq = alloc_workqueue("i915-userptr-release",
diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index 51dbfe5bb418..dc6deba519db 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -118,6 +118,13 @@ static inline u64 ptr_to_u64(const void *ptr)
__idx;  \
 })
 
+#ifdef CONFIG_LOCKDEP
+#define lockdep_set_name(lock, name)   \
+   lockdep_set_class_and_name(lock, (lock)->dep_map.key, name)
+#else
+#define lockdep_set_name(lock, name)   do {} while (0)
+#endif
+
 #include 
 
 static inline void __list_del_many(struct list_head *head,
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 86acac010bb8..3b8fff28a7b0 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -843,7 +843,10 @@ int intel_engine_init_breadcrumbs(struct intel_engine_cs 
*engine)
struct task_struct *tsk;
 
spin_lock_init(>rb_lock);
+   lockdep_set_name(>rb_lock, "intel_breadcrumbs->rb");
+
spin_lock_init(>irq_lock);
+   lockdep_set_name(>irq_lock, "intel_breadcrumbs->irq");
 

[Intel-gfx] [PATCH 05/14] drm/i915: Only attempt to scan the requested number of shrinker slabs

[Chris Wilson]

Since commit 4e773c3a8a69 ("drm/i915: Wire up shrinkctl->nr_scanned"),
we track the number of objects we scan and do not wish to exceed that as
it will overly penalise our own slabs under mempressure. Given that we
now know the target number of objects to scan, use that as our guide for
deciding to shrink as opposed to the number of objects we manage to
shrink (which doesn't correspond to the numbers we report to shrinkctl).

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 9029ed04879c..0e158f9287c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -363,13 +363,13 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct 
shrink_control *sc)
I915_SHRINK_BOUND |
I915_SHRINK_UNBOUND |
I915_SHRINK_PURGEABLE);
-   if (freed < sc->nr_to_scan)
+   if (sc->nr_scanned < sc->nr_to_scan)
freed += i915_gem_shrink(i915,
 sc->nr_to_scan - sc->nr_scanned,
 >nr_scanned,
 I915_SHRINK_BOUND |
 I915_SHRINK_UNBOUND);
-   if (freed < sc->nr_to_scan && current_is_kswapd()) {
+   if (sc->nr_scanned < sc->nr_to_scan && current_is_kswapd()) {
intel_runtime_pm_get(i915);
freed += i915_gem_shrink(i915,
 sc->nr_to_scan - sc->nr_scanned,
-- 
2.15.1

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[Intel-gfx] Fun with signals

[Chris Wilson]

Just some fallout with handling signals when the interrupt generation
rate is sufficient to saturate the CPU, leaving no time to clean up. In
particular, it's quite easy to cause oom on snb with a bunch of nops.
Overall though there's a small latency improvement for inter-engine
signaling.
-Chris

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Re: [Intel-gfx] [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12

[Maarten Lankhorst]

In subject: s/varification/verification/

Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar 
>
> NV12 formats have two registers for DDB. verify both the registers for
> NV12 during verify_wm_state.
>
> Signed-off-by: Mahesh Kumar 
> ---
>  drivers/gpu/drm/i915/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c  | 50 
> 
>  3 files changed, 42 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 81aa5f1..af3144d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2607,7 +2607,7 @@ static int i9xx_format_to_fourcc(int format)
>   }
>  }
>  
> -static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  {
>   switch (format) {
>   case PLANE_CTL_FORMAT_RGB_565:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 5f5e070..d245481 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1510,6 +1510,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, 
> int plane,
>unsigned int rotation);
>  int skl_check_plane_surface(struct intel_plane_state *plane_state);
>  int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
>  
>  /* intel_csr.c */
>  void intel_csr_ucode_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 15edb9a..5c268b9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3820,6 +3820,43 @@ static void skl_ddb_entry_init_from_hw(struct 
> skl_ddb_entry *entry, u32 reg)
>   entry->end += 1;
>  }
>  
> +static void
> +skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> +const enum pipe pipe,
> +const enum plane_id plane_id,
> +struct skl_ddb_allocation *ddb /* out */)
> +{
> + u32 val, val2 = 0;
> + int fourcc, pixel_format;
> +
> + /* Cursor doesn't support NV12, so no extra calculation needed */
> + if (plane_id == PLANE_CURSOR) {
> + val = I915_READ(CUR_BUF_CFG(pipe));
> + skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
> + return;
> + }
> +
> + val = I915_READ(PLANE_CTL(pipe, plane_id));
> +
> + /* No DDB allocated for disabled planes */
> + if (!(val & PLANE_CTL_ENABLE))
> + return;
> +
> + pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + fourcc = skl_format_to_fourcc(pixel_format,
> +   val & PLANE_CTL_ORDER_RGBX,
> +   val & PLANE_CTL_ALPHA_MASK);
> +
> + val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> + val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> +
> + if (fourcc == DRM_FORMAT_NV12) {
> + skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val2);
> + skl_ddb_entry_init_from_hw(>uv_plane[pipe][plane_id], val);
> + } else
> + skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
> +}
> +
>  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> struct skl_ddb_allocation *ddb /* out */)
>  {
> @@ -3836,16 +3873,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
> *dev_priv,
>   if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
>   continue;
>  
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - u32 val;
> -
> - if (plane_id != PLANE_CURSOR)
> - val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> - else
> - val = I915_READ(CUR_BUF_CFG(pipe));
> -
> - skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
> val);
> - }
> + for_each_plane_id_on_crtc(crtc, plane_id)
> + skl_ddb_get_hw_plane_state(dev_priv, pipe,
> +plane_id, ddb);
>  
>   intel_display_power_put(dev_priv, power_domain);
>   }


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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev7)

[Patchwork]

== Series Details ==

Series: tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev7)
URL   : https://patchwork.freedesktop.org/series/32888/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3604
914d61a8fb5f drm-tip: 2018y-01m-05d-09h-12m-18s UTC integration manifest

Testlist changes:
+++ 570 lines
--- 0 lines

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-snb-2600) fdo#102365
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:426s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:368s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:492s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:578s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:531s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:521s
fi-snb-2600  total:288  pass:247  dwarn:1   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y total:224  pass:199  dwarn:0   dfail:0   fail:0   skip:24 

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_749/issues.html
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[Intel-gfx] [PATCH i-g-t v12] tests/kms_frontbuffer_tracking: Including DRRS test coverage

[Lohith BS]

Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
refresh rate to the lowest vrefresh supported by panel, when frame is
not flipped for more than a Sec.

In kernel, DRRS uses the front buffer tracking infrastructure.
Hence DRRS test coverage is added along with other frontbuffer tracking
based features such as FBC and PSR tests.

Here, we are testing DRRS with other features in all possible
combinations, in all required test cases, to capture any possible
regression.

v2: Addressed the comments and suggestions from Vlad, Marius.
The signoff details from the earlier work are also included.

v3: Modified vblank rate calculation by using reply-sequence,
provided by drmWaitVBlank, as suggested by Chris Wilson.

v4: As suggested from Chris Wilson and Daniel Vetter
1) Avoided using pthread for calculating vblank refresh rate,
   instead used drmWaitVBlank reply sequence.
2) Avoided using kernel-specific info like transitional delays,
   instead polling mechanism with timeout is used.
3) Included edp-DRRS as a subtest in kms_frontbuffer_tracking.c,
   instead of having a separate test.

v5: This patch adds DRRS as a new feature in the
kms_frontbuffer_tracking IGT.
DRRS switch to lower vrefresh rate is tested at slow-draw subtest.

Note:
1) Currently kernel doesn't have support to enable and disable
   the DRRS feature dynamically(as in case of PSR). Hence if the
   panel supports DRRS it will be enabled by default.

This is in continuation of last patch
"https://patchwork.freedesktop.org/patch/162726/;

v6: This patch adds runtime enable and disable feature for testing DRRS

v7: This patch adds runtime enable and disable feature for testing DRRS
through debugfs entry "i915_drrs_ctl".

v8: Commit message is updated to reflect current implementation.

v9: Addressed Paulo Zanoni comments.
Check for DRRS_LOW at tests with OFFSCREEN + FBS_INDIVIDUAL.

v10: Corrected DRRS state expectation in suspend related subtests.

v11: Removing the global flag is_psr_drrs_combo [Rodrigo].

v12: Rewriting the DRRS inactive deduction [Rodrigo].

Signed-off-by: Lohith BS 
Signed-off-by: aknautiy 
---
 tests/kms_frontbuffer_tracking.c | 178 +--
 1 file changed, 170 insertions(+), 8 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab..4b87273 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -34,7 +34,7 @@
 
 
 IGT_TEST_DESCRIPTION("Test the Kernel's frontbuffer tracking mechanism and "
-"its related features: FBC and PSR");
+"its related features: FBC, PSR and DRRS");
 
 /*
  * One of the aspects of this test is that, for every subtest, we try different
@@ -105,8 +105,9 @@ struct test_mode {
FEATURE_NONE  = 0,
FEATURE_FBC   = 1,
FEATURE_PSR   = 2,
-   FEATURE_COUNT = 4,
-   FEATURE_DEFAULT = 4,
+   FEATURE_DRRS  = 4,
+   FEATURE_COUNT = 8,
+   FEATURE_DEFAULT = 8,
} feature;
 
/* Possible pixel formats. We just use FORMAT_DEFAULT for most tests and
@@ -156,6 +157,7 @@ struct rect {
 struct {
int fd;
int debugfs;
+   int drrs_debugfs_fd;
drmModeResPtr res;
drmModeConnectorPtr connectors[MAX_CONNECTORS];
drmModeEncoderPtr encoders[MAX_ENCODERS];
@@ -182,6 +184,13 @@ struct {
.can_test = false,
 };
 
+#define MAX_DRRS_STATUS_BUF_LEN 256
+
+struct {
+   bool can_test;
+} drrs = {
+   .can_test = false,
+};
 
 #define SINK_CRC_SIZE 12
 typedef struct {
@@ -825,6 +834,60 @@ static void psr_print_status(void)
igt_info("PSR status:\n%s\n", buf);
 }
 
+void drrs_set(unsigned int val)
+{
+   char buf[2];
+
+   igt_debug("Manually %sabling DRRS. %llu\n", val ? "en" : "dis", val);
+   snprintf(buf, sizeof(buf), "%d", val);
+   igt_assert_eq(write(drm.drrs_debugfs_fd,
+ buf, strlen(buf)), strlen(buf));
+}
+
+static bool is_drrs_high(void)
+{
+   char buf[MAX_DRRS_STATUS_BUF_LEN];
+
+   debugfs_read("i915_drrs_status", buf);
+   return strstr(buf, "DRRS_HIGH_RR");
+}
+
+static bool is_drrs_low(void)
+{
+   char buf[MAX_DRRS_STATUS_BUF_LEN];
+
+   debugfs_read("i915_drrs_status", buf);
+   return strstr(buf, "DRRS_LOW_RR");
+}
+
+static bool is_drrs_supported(void)
+{
+   char buf[MAX_DRRS_STATUS_BUF_LEN];
+
+   debugfs_read("i915_drrs_status", buf);
+   return strstr(buf, "DRRS Supported: Yes");
+}
+
+static bool is_drrs_inactive(void)
+{
+   char buf[MAX_DRRS_STATUS_BUF_LEN];
+
+   debugfs_read("i915_drrs_status", buf);
+
+   if (strstr(buf, "DRRS_State: "))
+   return false;
+
+   return true;
+}
+
+static void drrs_print_status(void)
+{
+   char 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] test/kms_psr_sink_crc - subtests psr_basic 
and psr_drrs need test cleanup
URL   : https://patchwork.freedesktop.org/series/36065/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-modeset-suspend-interruptible:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +2
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> SKIP   (shard-hsw) fdo#103375
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-a:
skip   -> PASS   (shard-snb)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2653 pass:1501 dwarn:1   dfail:0   fail:9   skip:1141 
time:8622s
shard-snbtotal:2713 pass:1308 dwarn:1   dfail:0   fail:13  skip:1391 
time:7858s
Blacklisted hosts:
shard-apltotal:2615 pass:1616 dwarn:1   dfail:0   fail:23  skip:974 
time:12549s
shard-kbltotal:2713 pass:1803 dwarn:1   dfail:0   fail:30  skip:879 
time:10471s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_748/shards.html
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable vblanks after verifying power domain states.

[Maarten Lankhorst]

Op 04-01-18 om 22:51 schreef Pandiyan, Dhinakaran:
> On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
>> Wouldn't it be better to make intel_power_domains_verify_state work
>> correctly with the vblank irq?
> I tried to :) Since I changed the domain_use_count to atomic_t and moved
> it outside of the locks, verify_state became racy. Let me take another
> look.
>
> -DK

It sucks that we end up with 2 ways to handle power domains..

I'm trying to think of a cleaner way, coming up with none. :(

It would have been nice if we could do something like a seqlock for
the refcounts, but that would prevent us from blocking too..

Is it only the DC off power well we care about?

~Maarten

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Re: [Intel-gfx] [PATCH v3 1/7] drm/i915: Add CRTC output format YCBCR 4:2:0

[Maarten Lankhorst]

Op 05-01-18 om 10:45 schreef Shashank Sharma:
> Currently, we are using a bool in CRTC state (state->ycbcr420),
> to indicate modeset, that the output format is YCBCR 4:2:0. Now in
> order to support other YCBCR formats, we will need more such flags.
>
> The idea behind this patch is to replace this bool with an enum,
> and plug this in in the existing YCBCR 4:2:0 framework in such a
> way that this can be re-used for YCBCR 4:4:4 and other output formats too.
>
> This patch adds a new enum for CRTC output formats, and then plugs it
> in the existing modeset framework.
>
> V3: Added this patch in the series, to address review comments from
> second patchset.
>
> Cc: Ville Syrjala 
> Cc: Maarten Lankhorst 
> Signed-off-by: Shashank Sharma 
Series looks good to me now, so feel free to add my r-b to where its missing. 
But you still need an ack from Ville I think. :)

Reviewed-by: Maarten Lankhorst 

~Maarten
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add HAS_NATIVE_HDMI2 macro

[Patchwork]

== Series Details ==

Series: drm/i915: Add HAS_NATIVE_HDMI2 macro
URL   : https://patchwork.freedesktop.org/series/36071/
State : success

== Summary ==

Series 36071v1 drm/i915: Add HAS_NATIVE_HDMI2 macro
https://patchwork.freedesktop.org/api/1.0/series/36071/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:367s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:461s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:264s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:388s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:409s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:598s
fi-glk-dsi failed to collect. IGT log at Patchwork_7617/fi-glk-dsi/igt.log
fi-pnv-d510 failed to collect. IGT log at Patchwork_7617/fi-pnv-d510/igt.log

914d61a8fb5fc53f6b0366167210468147495b3f drm-tip: 2018y-01m-05d-09h-12m-18s UTC 
integration manifest
d4b30b22d948 drm/i915: Add HAS_NATIVE_HDMI2 macro

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7617/issues.html
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[Intel-gfx] [PATCH] drm/i915: Add HAS_NATIVE_HDMI2 macro

[Shashank Sharma]

GLK/GEN 10 and higher GEN platfomrs sport native HDMI 2.0 controller.
This patch adds a macro HAS_NATIVE_HDMI2, and uses it to make checks
in the code more readable.

Cc: Vivi Rodrigo 
Cc: Ville Syrjala 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 ++
 drivers/gpu/drm/i915/intel_hdmi.c | 7 +++
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caebd58..9a4b68b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2719,6 +2719,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define BSD2_RING  ENGINE_MASK(VCS2)
 #define ALL_ENGINES(~0)
 
+#define HAS_HDMI2_NATIVE(dev_priv) \
+   (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 #define HAS_ENGINE(dev_priv, id) \
(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index bced7b9..ee4e11c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1238,7 +1238,7 @@ static int intel_hdmi_source_max_tmds_clock(struct 
intel_encoder *encoder)
_priv->vbt.ddi_port_info[encoder->port];
int max_tmds_clock;
 
-   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+   if (HAS_HDMI2_NATIVE(dev_priv))
max_tmds_clock = 594000;
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
@@ -1514,8 +1514,7 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
 
pipe_config->lane_count = 4;
 
-   if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
-  IS_GEMINILAKE(dev_priv))) {
+   if (scdc->scrambling.supported && HAS_HDMI2_NATIVE(dev_priv)) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
 
@@ -2037,7 +2036,7 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
 
-   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+   if (HAS_HDMI2_NATIVE(dev_priv))
connector->ycbcr_420_allowed = true;
 
intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] test/kms_psr_sink_crc - subtests psr_basic 
and psr_drrs need test cleanup
URL   : https://patchwork.freedesktop.org/series/36065/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6db24416fdcdf5571125f9005089241cc6ba2652 lib/gem: Reset the global seqno at the 
start of each test

with latest DRM-Tip kernel build CI_DRM_3604
914d61a8fb5f drm-tip: 2018y-01m-05d-09h-12m-18s UTC integration manifest

No testlist changes.

Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6600u) fdo#104260 +2

fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-bdw-gvtdvmtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:6s
fi-blb-e6850 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:7s
fi-bsw-n3050 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:19s
fi-bwr-2160  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:12s
fi-bxt-dsi   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:10s
fi-bxt-j4205 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:10s
fi-byt-j1900 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:17s
fi-byt-n2820 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:16s
fi-elk-e7500 total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
fi-gdg-551   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:15s
fi-glk-1 total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:14s
fi-hsw-4770  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-hsw-4770r total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-ilk-650   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
fi-ivb-3520m total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-ivb-3770  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-kbl-7500u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-kbl-7560u total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:10s
fi-kbl-7567u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-kbl-r total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:11s
fi-pnv-d510  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:28s
fi-skl-6260u total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-skl-6600u total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:11s
fi-skl-6700hqtotal:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:15s
fi-skl-6700k2total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-skl-6770hqtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:4s
fi-skl-gvtdvmtotal:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:5s
fi-snb-2520m total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:13s
fi-snb-2600  total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s
Blacklisted hosts:
fi-cfl-s2total:2pass:2dwarn:0   dfail:0   fail:0   skip:0   
time:11s
fi-glk-dsi   total:2pass:0dwarn:0   dfail:0   fail:0   skip:2   
time:8s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_748/issues.html
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GuC Interrupts/Log updates (rev3)

[Sagar Arun Kamble]

On 1/5/2018 2:42 PM, Patchwork wrote:

== Series Details ==

Series: GuC Interrupts/Log updates (rev3)
URL   : https://patchwork.freedesktop.org/series/32179/
State : failure

== Summary ==

Series 32179v3 GuC Interrupts/Log updates
https://patchwork.freedesktop.org/api/1.0/series/32179/revisions/3/mbox/

Test core_auth:
 Subgroup basic-auth:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test core_prop_blob:
 Subgroup basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test debugfs_test:
 Subgroup read_all_entries:
 incomplete -> PASS   (fi-snb-2520m) fdo#103713 +1
 pass   -> DMESG-WARN (fi-skl-6260u)
 pass   -> DMESG-WARN (fi-skl-6600u)
 pass   -> DMESG-WARN (fi-skl-6700hq)
 pass   -> DMESG-WARN (fi-skl-6700k2)
 pass   -> DMESG-WARN (fi-skl-6770hq)
 pass   -> SKIP   (fi-skl-gvtdvm)
 pass   -> DMESG-WARN (fi-bxt-dsi)
 pass   -> DMESG-WARN (fi-bxt-j4205)
 pass   -> DMESG-WARN (fi-kbl-7500u) fdo#103285
 pass   -> DMESG-WARN (fi-kbl-7560u)
 pass   -> DMESG-WARN (fi-kbl-7567u)
 pass   -> DMESG-WARN (fi-kbl-r)
These are related to circular locking between struct_mutex, mmap_sem, 
i_mutex_key, relay_channels_mutex.
Separating debugfs and relay channel setup from struct_mutex should 
likely resolve this and will be addressed

in new patch series.

Test drv_getparams_basic:
 Subgroup basic-eu-total:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-subslice-total:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test drv_hangman:
 Subgroup error-state-basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_basic:
 Subgroup bad-close:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup create-close:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup create-fd-close:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_busy:
 Subgroup basic-busy-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-hang-default:
 pass   -> SKIP   (fi-skl-gvtdvm) fdo#104108 +2
Test gem_close_race:
 Subgroup basic-process:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-threads:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_cpu_reloc:
 Subgroup basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_cs_tlb:
 Subgroup basic-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_create:
 Subgroup basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-files:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_exec:
 Subgroup basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_param:
 Subgroup basic:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_switch:
 Subgroup basic-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-default-heavy:
 pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_exec_basic:
 Subgroup basic-blt:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-bsd:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-bsd1:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-bsd2:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-render:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup basic-vebox:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-blt:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-bsd:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-bsd1:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-bsd2:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-default:
 pass   -> SKIP   (fi-skl-gvtdvm)
 Subgroup gtt-render:
 pass   -> SKIP   (fi-skl-gvtdvm)
WARNING: Long output truncated
fi-glk-1 failed to collect. IGT log at Patchwork_7614/fi-glk-1/igt.log

3e7d28b655aefefe51f1d7ac6aba46d6ca03b658 drm-tip: 2018y-01m-04d-22h-45m-20s UTC 
integration manifest
5a97f4912290 HAX: drm/i915/guc: enable GuC submission/logging for CI
728519ffad84 drm/i915/guc: Restore GuC 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. (rev2)
URL   : https://patchwork.freedesktop.org/series/36039/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-cur-indfb-onoff:
skip   -> PASS   (shard-snb)
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
incomplete -> PASS   (shard-hsw) fdo#103540 +1
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218
Test drv_suspend:
Subgroup debugfs-reader-hibernate:
fail   -> SKIP   (shard-hsw) fdo#103375
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2713 pass:1538 dwarn:1   dfail:0   fail:9   skip:1165 
time:8990s
shard-snbtotal:2713 pass:1311 dwarn:1   dfail:0   fail:10  skip:1391 
time:7831s
Blacklisted hosts:
shard-apltotal:2713 pass:1683 dwarn:1   dfail:0   fail:27  skip:1001 
time:13368s
shard-kbltotal:2713 pass:1804 dwarn:2   dfail:0   fail:27  skip:880 
time:10508s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7615/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON

[Patchwork]

== Series Details ==

Series: YCBCR 4:2:0/4:4:4 output support for LSPCON
URL   : https://patchwork.freedesktop.org/series/36068/
State : warning

== Summary ==

Series 36068v1 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +2
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> DMESG-WARN (fi-kbl-7567u)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-7567u)
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (fi-kbl-7567u)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:367s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:478s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:275s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:478s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:463s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:453s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:408s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:463s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:264  dwarn:4   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:572s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:505s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:522s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:484s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:520s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:595s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s
fi-gdg-551 failed to collect. IGT log at Patchwork_7616/fi-gdg-551/igt.log

914d61a8fb5fc53f6b0366167210468147495b3f drm-tip: 2018y-01m-05d-09h-12m-18s UTC 
integration manifest
7e873eeda3c9 drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
493d65ec6f3b drm/i915: Write AVI infoframes for Parade LSPCON
0681b480b514 drm/i915: Write AVI infoframes for MCA LSPCON
7dc583b6251a drm/i915: Add AVI infoframe support for LSPCON
3f657d86adf2 drm/i915: Check LSPCON vendor OUI
be479b386bb5 drm/i915: Add CRTC output format YCBCR 4:4:4
0344c5ac79d0 drm/i915: Add CRTC output format YCBCR 4:2:0

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7616/issues.html
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Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

[Sagar Arun Kamble]

On 1/5/2018 3:22 AM, Yaodong Li wrote:


On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote:
Since ring frequency programming needs consideration of both IA and 
GT frequency requests I think keeping the logic
to program the ring frequency table in driver that monitors both 
IA/GT busyness and power budgets like intel_ips
will be more appropriate. intel_ips is relying on global load derived 
from all CPUs.
I understand that power awareness and busyness based policy might be 
trickier but having that as tunable will give better flexibility.


By just looking into the current code, the way intel_ips checks gpu 
busyness cannot reflect the actual workload of GT
(e.g. gpu busy is true even if there's only one pending request), in 
this case, we shall not increase the ring freq if we
want to use a "workload monitoring" based solution. so we need a more 
accurate way to monitor the current GT workload
(e.g.  when the pending request count reaches a center tunable 
threshold??).

Yes. May be we can share the PMU data about engine busyness with intel_ips.



On 1/3/2018 11:51 PM, Yaodong Li wrote:


You are thinking of plugging into intel_pstate to make it smarter 
for ia freq transitions?
Yep. This seems a correct step to give some automatic support 
instead of parameter/hardcoded multiplier.


Does this mean we should use cpufreq/intel_pstate based approach 
instead of the current modparam solution for Gen9?


Some concerns and questions about intel_pstate approach:
a) Currently, we cannot get the accurate pstate/target freq value 
from cpufreq in intel_pstate active mode since
 these values won't be exported to cpufreq layer, so if we won't 
change intel_pstate code then we only can get

 the max cpu freq of a new policy.
b) intel_pstate policy is attached to each logic cpu, which means we 
will receive policy/freq transition notification
    for each logic cpu freq change. One question is how we are going 
to decide the freq of the ring? just use the max

    cpu freq reported?
c) With the intel_pstate approach we may still run into thermal 
throttling, in this case, can a certain cooling device

    be triggered to lower the cpu freq?

Thanks and Regards,
-Jackie







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[Intel-gfx] [PATCH v3 5/7] drm/i915: Write AVI infoframes for MCA LSPCON

[Shashank Sharma]

As LSPCON is a DP branch device, LSPCON vendors define
specific methods to pass AVI infoframes to the the chip.
This patch adds:
- a generic wrapper function for writing AVI infoframes for
  all LSPCON devices.
- a vendor specific function to wrire AVI infoframes into
  MCA LSPCON devices.

V2: Rebase
V3: Added r-b from Maarten

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_drv.h|  4 ++
 drivers/gpu/drm/i915/intel_hdmi.c   |  2 +
 drivers/gpu/drm/i915/intel_lspcon.c | 80 +
 3 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f2e8752..2de6b41 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2037,6 +2037,10 @@ void intel_color_load_luts(struct drm_crtc_state 
*crtc_state);
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
 void lspcon_resume(struct intel_lspcon *lspcon);
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+enum hdmi_infoframe_type type,
+const void *buf, ssize_t len);
 void lspcon_set_infoframes(struct drm_encoder *encoder,
   bool enable,
   const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 0609f11..7b63889 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2000,6 +2000,8 @@ void intel_infoframe_init(struct intel_digital_port 
*intel_dig_port)
intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
} else if (HAS_DDI(dev_priv)) {
if (intel_dig_port->lspcon.active) {
+   intel_dig_port->write_infoframe =
+   lspcon_write_infoframe;
intel_dig_port->set_infoframes = lspcon_set_infoframes;
intel_dig_port->infoframe_enabled =
lspcon_infoframe_enabled;
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 32d4198..0571108 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -31,6 +31,12 @@
 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
+/* AUX addresses to write MCA AVI IF */
+#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
+#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
+#define  LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
+#define  LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -235,6 +241,80 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon 
*lspcon)
DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
 }
 
+static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
+const uint8_t *buffer, ssize_t len)
+{
+   int ret;
+   uint32_t val = 0;
+   uint16_t reg;
+   const uint8_t *data = buffer;
+
+   reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
+   while (val < len) {
+   ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD write failed, add:0x%x\n", reg);
+   return false;
+   }
+   val++; reg++; data++;
+   }
+
+   val = 0;
+   reg = LSPCON_MCA_AVI_IF_CTRL;
+   ret = drm_dp_dpcd_read(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */
+   val &= ~LSPCON_MCA_AVI_IF_HANDLED;
+   val |= LSPCON_MCA_AVI_IF_KICKOFF;
+
+   ret = drm_dp_dpcd_write(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   val = 0;
+   ret = drm_dp_dpcd_read(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   if (val == LSPCON_MCA_AVI_IF_HANDLED)
+   DRM_DEBUG_KMS("AVI IF handled by FW\n");
+
+   return true;
+}
+
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+enum hdmi_infoframe_type type,
+ 

[Intel-gfx] [PATCH v3 1/7] drm/i915: Add CRTC output format YCBCR 4:2:0

[Shashank Sharma]

Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR formats, we will need more such flags.

The idea behind this patch is to replace this bool with an enum,
and plug this in in the existing YCBCR 4:2:0 framework in such a
way that this can be re-used for YCBCR 4:4:4 and other output formats too.

This patch adds a new enum for CRTC output formats, and then plugs it
in the existing modeset framework.

V3: Added this patch in the series, to address review comments from
second patchset.

Cc: Ville Syrjala 
Cc: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_color.c   |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 66 
 drivers/gpu/drm/i915/intel_drv.h | 10 --
 drivers/gpu/drm/i915/intel_hdmi.c|  6 ++--
 drivers/gpu/drm/i915/intel_panel.c   |  2 +-
 6 files changed, 59 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index aa66e95..99e32cb 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -141,7 +141,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
uint16_t coeffs[9] = { 0, };
struct intel_crtc_state *intel_crtc_state = 
to_intel_crtc_state(crtc_state);
 
-   if (intel_crtc_state->ycbcr420) {
+   if (intel_crtc_state->output_format == CRTC_OUTPUT_YCBCR420) {
i9xx_load_ycbcr_conversion_matrix(intel_crtc);
return;
} else if (crtc_state->ctm) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f51645a..84327e7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1264,7 +1264,7 @@ static void ddi_dotclock_get(struct intel_crtc_state 
*pipe_config)
else
dotclock = pipe_config->port_clock;
 
-   if (pipe_config->ycbcr420)
+   if (pipe_config->output_format == CRTC_OUTPUT_YCBCR420)
dotclock *= 2;
 
if (pipe_config->pixel_multiplier)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0cd3559..69b0aa3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4644,7 +4644,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 */
need_scaling = src_w != dst_w || src_h != dst_h;
 
-   if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
+   if (crtc_state->output_format == CRTC_OUTPUT_YCBCR420 &&
+   scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
 
/*
@@ -6356,7 +6357,8 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
-   if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
+   if (pipe_config->output_format == CRTC_OUTPUT_YCBCR420 &&
+   pipe_config->base.ctm) {
/*
 * There is only one pipe CSC unit per pipe, and we need that
 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -8177,10 +8179,10 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
 
-   if (config->ycbcr420) {
-   val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
-   PIPEMISC_YUV420_ENABLE |
-   PIPEMISC_YUV420_MODE_FULL_BLEND;
+   if (config->output_format == CRTC_OUTPUT_YCBCR420) {
+   val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
+   val |= PIPEMISC_YUV420_ENABLE |
+  PIPEMISC_YUV420_MODE_FULL_BLEND;
}
 
I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
@@ -9156,6 +9158,19 @@ static void haswell_get_ddi_port_state(struct intel_crtc 
*crtc,
}
 }
 
+static const char * const output_format_str[] = {
+   "Invalid",
+   "RGB",
+   "YCBCR4:2:0",
+};
+
+static const char *output_formats(enum crtc_output_format format)
+{
+   if (format < CRTC_OUTPUT_INVALID || format > CRTC_OUTPUT_YCBCR420)
+   format = CRTC_OUTPUT_INVALID;
+   return output_format_str[format + 1];
+}
+
 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
 {
@@ -9196,19 +9211,28 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
 
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
-   bool clrspace_yuv = 

[Intel-gfx] [PATCH v3 3/7] drm/i915: Check LSPCON vendor OUI

[Shashank Sharma]

Intel LSPCON chip is provided by 2 vendors:
- Megachips America (MCA)
- Parade technologies (Parade tech)

Its important to know the vendor of this chip, as the address to
write AVI infoframes is different for those two.

This patch reads the vendor OUI signature, and marks into LSPCON
encoder structure for future usages.

This patch also does a small re-arrangement of the code, by moving
lspcon mode change into probe function.

V2: Use dp->desc for OUI detection, dont add a helper for this
(Ville)
V3: Rebase, Added r-b from Maarten

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_drv.h|  6 
 drivers/gpu/drm/i915/intel_lspcon.c | 69 +
 2 files changed, 61 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a393342..ba6a599 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1055,9 +1055,15 @@ struct intel_dp {
struct intel_dp_compliance compliance;
 };
 
+enum lspcon_vendor {
+   LSPCON_VENDOR_MCA,
+   LSPCON_VENDOR_PARADE
+};
+
 struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
+   enum lspcon_vendor vendor;
 };
 
 struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index dcbc786..946dfd0 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -27,6 +27,10 @@
 #include 
 #include "intel_drv.h"
 
+/* LSPCON OUI Vendor ID(signatures) */
+#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
+#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -50,6 +54,40 @@ static const char *lspcon_mode_name(enum drm_lspcon_mode 
mode)
}
 }
 
+static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
+{
+   struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+   struct drm_dp_dpcd_ident *ident;
+   u32 vendor_oui;
+
+   if (drm_dp_read_desc(>aux, >desc, drm_dp_is_branch(dp->dpcd))) {
+   DRM_ERROR("Can't read description\n");
+   return false;
+   }
+
+   ident = >desc.ident;
+   vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) |
+ ident->oui[2];
+
+   switch (vendor_oui) {
+   case LSPCON_VENDOR_MCA_OUI:
+   lspcon->vendor = LSPCON_VENDOR_MCA;
+   DRM_DEBUG_KMS("Vendor: Mega Chips\n");
+   break;
+
+   case LSPCON_VENDOR_PARADE_OUI:
+   lspcon->vendor = LSPCON_VENDOR_PARADE;
+   DRM_DEBUG_KMS("Vendor: Parade Tech\n");
+   break;
+
+   default:
+   DRM_ERROR("Invalid/Unknown vendor OUI\n");
+   return false;
+   }
+
+   return true;
+}
+
 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon 
*lspcon)
 {
enum drm_lspcon_mode current_mode;
@@ -159,7 +197,18 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
/* Yay ... got a LSPCON device */
DRM_DEBUG_KMS("LSPCON detected\n");
lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
-   lspcon->active = true;
+
+   /*
+* In the SW state machine, lets Put LSPCON in PCON mode only.
+* In this way, it will work with both HDMI 1.4 sinks as well as HDMI
+* 2.0 sinks.
+*/
+   if (lspcon->active && lspcon->mode != DRM_LSPCON_MODE_PCON) {
+   if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
+   DRM_ERROR("LSPCON mode change to PCON failed\n");
+   return false;
+   }
+   }
return true;
 }
 
@@ -231,25 +280,17 @@ bool lspcon_init(struct intel_digital_port 
*intel_dig_port)
return false;
}
 
-   /*
-   * In the SW state machine, lets Put LSPCON in PCON mode only.
-   * In this way, it will work with both HDMI 1.4 sinks as well as HDMI
-   * 2.0 sinks.
-   */
-   if (lspcon->active && lspcon->mode != DRM_LSPCON_MODE_PCON) {
-   if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
-   DRM_ERROR("LSPCON mode change to PCON failed\n");
-   return false;
-   }
-   }
-
if (!intel_dp_read_dpcd(dp)) {
DRM_ERROR("LSPCON DPCD read failed\n");
return false;
}
 
-   drm_dp_read_desc(>aux, >desc, drm_dp_is_branch(dp->dpcd));
+   if (!lspcon_detect_vendor(lspcon)) {
+   DRM_ERROR("LSPCON vendor detection failed\n");
+   return false;
+   }
 
+   lspcon->active = 

[Intel-gfx] [PATCH v3 6/7] drm/i915: Write AVI infoframes for Parade LSPCON

[Shashank Sharma]

Different LSPCON vendors specify their custom methods to pass
AVI infoframes to the LSPCON chip, so does Parade tech.

This patch adds functions to arrange and write AVI infoframes
into Parade LSPCON chips.

V2: rebase
V3: Added r-b from Maarten

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_lspcon.c | 119 +++-
 1 file changed, 118 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 0571108..066ea91 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -37,6 +37,12 @@
 #define  LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
 #define  LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
 
+/* AUX addresses to write Parade AVI IF */
+#define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516
+#define LSPCON_PARADE_AVI_IF_CTRL 0x51E
+#define  LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7)
+#define LSPCON_PARADE_AVI_IF_DATA_SIZE 32
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -241,6 +247,113 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon 
*lspcon)
DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
 }
 
+static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
+{
+   u8 avi_if_ctrl;
+   u8 retry;
+   ssize_t ret;
+
+   /* Check if LSPCON FW is ready for data */
+   for (retry = 0; retry < 5; retry++) {
+
+   if (retry)
+   usleep_range(200, 300);
+
+   ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
+  _if_ctrl, 1);
+   if (ret < 0) {
+   DRM_ERROR("Failed to read AVI IF control\n");
+   return false;
+   }
+
+   if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0)
+   return true;
+   }
+
+   DRM_ERROR("Parade FW not ready to accept AVI IF\n");
+   return false;
+}
+
+static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
+  uint8_t *avi_buf)
+{
+   u8 avi_if_ctrl;
+   u8 block_count = 0;
+   u8 *data;
+   uint16_t reg;
+   ssize_t ret;
+
+   while (block_count < 4) {
+
+   if (!lspcon_parade_fw_ready(aux)) {
+   DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
+  block_count);
+   return false;
+   }
+
+   reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
+   data = avi_buf + block_count * 8;
+   ret = drm_dp_dpcd_write(aux, reg, data, 8);
+   if (ret < 0) {
+   DRM_ERROR("Failed to write AVI IF block %d\n",
+  block_count);
+   return false;
+   }
+
+   /*
+* Once a block of data is written, we have to inform the FW
+* about this by writing into avi infoframe control register:
+* - set the kickoff bit[7] to 1
+* - write the block no. to bits[1:0]
+*/
+   reg = LSPCON_PARADE_AVI_IF_CTRL;
+   avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
+   ret = drm_dp_dpcd_write(aux, reg, _if_ctrl, 1);
+   if (ret < 0) {
+   DRM_ERROR("Failed to update (0x%x), block %d\n",
+   reg, block_count);
+   return false;
+   }
+
+   block_count++;
+   }
+
+   DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
+   return true;
+}
+
+static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
+  const uint8_t *frame,
+  ssize_t len)
+{
+   uint8_t avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
+
+   /*
+* Parade's frames contains 32 bytes of data, divided
+* into 4 frames:
+*  Token byte (first byte of first frame, must be non-zero)
+*  HB0 to HB2   from AVI IF (3 bytes header)
+*  PB0 to PB27 from AVI IF (28 bytes data)
+* So it should look like this
+*  first block: ||
+*  next 3 blocks: 
+*/
+
+   if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
+   DRM_ERROR("Invalid length of infoframes\n");
+   return false;
+   }
+
+   memcpy(_if[1], frame, len);
+
+   if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
+   

[Intel-gfx] [PATCH v3 4/7] drm/i915: Add AVI infoframe support for LSPCON

[Shashank Sharma]

In order to pass AVI infoframes to LSPCON devices, a source has to
write them in a vendor recommended method and location.

This patch series:
- adds generic LSPCON infoframe setup functions.
- registers these functions into existing AVI infoframe framework.
- triggers these functions from modeset sequence.

Next patches in the series will add vendor specific code.

V2: Added new parameter to align with new definition of
drm_hdmi_avi_infoframe_quant_range
V3: Added r-b from Maarten (for V2)
Added new parameter output_format in struct lspcon to accommodate
Ville's review comments on last patch of the series

Cc: Ville Syrjala 
Cc: Imre Deak 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_ddi.c| 19 +++---
 drivers/gpu/drm/i915/intel_drv.h| 14 ++-
 drivers/gpu/drm/i915/intel_hdmi.c   | 13 +++---
 drivers/gpu/drm/i915/intel_lspcon.c | 49 +
 4 files changed, 87 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 84327e7..7b89f2a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2238,10 +2238,22 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*encoder,
 
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
-   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
-   else
+   } else {
+   struct intel_lspcon *lspcon =
+   enc_to_intel_lspcon(>base);
+
intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+   if (lspcon->active) {
+   struct intel_digital_port *dig_port =
+   enc_to_dig_port(>base);
+
+   dig_port->set_infoframes(>base,
+crtc_state->has_infoframe,
+crtc_state, conn_state);
+   }
+   }
 }
 
 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
@@ -2892,8 +2904,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
intel_encoder->cloneable = 0;
 
-   intel_infoframe_init(intel_dig_port);
-
if (init_dp) {
if (!intel_ddi_init_dp_connector(intel_dig_port))
goto err;
@@ -2923,6 +2933,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
port_name(port));
}
 
+   intel_infoframe_init(intel_dig_port);
return;
 
 err:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ba6a599..f2e8752 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1064,6 +1064,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+   enum crtc_output_format output_format;
 };
 
 struct intel_digital_port {
@@ -1189,6 +1190,12 @@ static inline struct intel_dp *enc_to_intel_dp(struct 
drm_encoder *encoder)
return _to_dig_port(encoder)->dp;
 }
 
+static inline struct intel_lspcon *
+enc_to_intel_lspcon(struct drm_encoder *encoder)
+{
+   return _to_dig_port(encoder)->lspcon;
+}
+
 static inline struct intel_digital_port *
 dp_to_dig_port(struct intel_dp *intel_dp)
 {
@@ -1703,7 +1710,6 @@ void intel_hdmi_handle_sink_scrambling(struct 
intel_encoder *intel_encoder,
 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
 
-
 /* intel_lvds.c */
 void intel_lvds_init(struct drm_i915_private *dev_priv);
 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
@@ -2031,6 +2037,12 @@ void intel_color_load_luts(struct drm_crtc_state 
*crtc_state);
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
 void lspcon_resume(struct intel_lspcon *lspcon);
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
+void lspcon_set_infoframes(struct drm_encoder *encoder,
+  bool enable,
+  const struct intel_crtc_state *crtc_state,
+  const struct drm_connector_state *conn_state);
+bool lspcon_infoframe_enabled(struct drm_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
 
 /* intel_pipe_crc.c */
 int intel_pipe_crc_create(struct drm_minor *minor);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 

[Intel-gfx] [PATCH v3 2/7] drm/i915: Add CRTC output format YCBCR 4:4:4

[Shashank Sharma]

This patch adds support for YCBCR 4:4:4 CRTC output format.
To do this, this patch extends the existing YCBCR 4:2:0
framework by:
- Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
- Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
- Adding necessary checks in modeset sequence.

V3: Added this patch in the series

Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_color.c   |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 13 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c|  2 ++
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 99e32cb..5b76de6 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -141,7 +141,8 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
uint16_t coeffs[9] = { 0, };
struct intel_crtc_state *intel_crtc_state = 
to_intel_crtc_state(crtc_state);
 
-   if (intel_crtc_state->output_format == CRTC_OUTPUT_YCBCR420) {
+   if (intel_crtc_state->output_format == CRTC_OUTPUT_YCBCR420 ||
+   intel_crtc_state->output_format == CRTC_OUTPUT_YCBCR444) {
i9xx_load_ycbcr_conversion_matrix(intel_crtc);
return;
} else if (crtc_state->ctm) {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 69b0aa3..6ac5ca6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6357,8 +6357,9 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
-   if (pipe_config->output_format == CRTC_OUTPUT_YCBCR420 &&
-   pipe_config->base.ctm) {
+   if ((pipe_config->output_format == CRTC_OUTPUT_YCBCR420 ||
+pipe_config->output_format == CRTC_OUTPUT_YCBCR444) &&
+pipe_config->base.ctm) {
/*
 * There is only one pipe CSC unit per pipe, and we need that
 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -8179,11 +8180,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
 
-   if (config->output_format == CRTC_OUTPUT_YCBCR420) {
+   if (config->output_format > CRTC_OUTPUT_RGB)
val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
+
+   if (config->output_format == CRTC_OUTPUT_YCBCR420)
val |= PIPEMISC_YUV420_ENABLE |
   PIPEMISC_YUV420_MODE_FULL_BLEND;
-   }
 
I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
}
@@ -9161,6 +9163,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc 
*crtc,
 static const char * const output_format_str[] = {
"Invalid",
"RGB",
+   "YCBCR4:4:4",
"YCBCR4:2:0",
 };
 
@@ -9226,6 +9229,8 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
output_format = CRTC_OUTPUT_INVALID;
else
output_format = CRTC_OUTPUT_YCBCR420;
+   } else {
+   output_format = CRTC_OUTPUT_YCBCR444;
}
 
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 79662650..a393342 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -612,6 +612,7 @@ struct intel_crtc_wm_state {
 enum crtc_output_format {
CRTC_OUTPUT_INVALID = -1,
CRTC_OUTPUT_RGB,
+   CRTC_OUTPUT_YCBCR444,
CRTC_OUTPUT_YCBCR420,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index b266a7f..258bb51 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -480,6 +480,8 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder 
*encoder,
 
if (crtc_state->output_format == CRTC_OUTPUT_YCBCR420)
frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
+   else if (crtc_state->output_format == CRTC_OUTPUT_YCBCR444)
+   frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
else
frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 7/7] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

[Shashank Sharma]

LSPCON chips can generate YCBCR outputs, if asked nicely :).

In order to generate YCBCR 4:2:0 outputs, a source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:2:0 in AVI infoframes

Whereas for YCBCR 4:4:4 outputs, the source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:4:4 in AVI infoframes

So for both 4:2:0 as well as 4:4:4 outputs, we are driving the
pipe for YCBCR 4:4:4 output, but AVI infoframe's color space
information indicates LSPCON FW to start scaling down from YCBCR
4:4:4 and generate YCBCR 4:2:0 output. As the scaling is done by
LSPCON device, we need not to reserve a scaler for 4:2:0 outputs.

V2: rebase
V3: Addressed review comments from Ville
- add enum crtc_output_format instead of bool ycbcr420
- use crtc_output_format=4:4:4 for modeset of LSPCON 4:2:0 output
  cases in this way we will have YCBCR 4:4:4 framework ready (except
  the ABI part)

Cc: Ville Syrjala 
Cc: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c|  7 +++
 drivers/gpu/drm/i915/intel_dp.c | 10 ++
 drivers/gpu/drm/i915/intel_drv.h|  2 ++
 drivers/gpu/drm/i915/intel_lspcon.c | 28 
 5 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 966e4df..45ee264 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8547,6 +8547,8 @@ enum skl_power_gate {
 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
 
 #define  TRANS_MSA_SYNC_CLK(1<<0)
+#define  TRANS_MSA_SAMPLING_444(2<<1)
+#define  TRANS_MSA_CLRSP_YCBCR (2<<3)
 #define  TRANS_MSA_6_BPC   (0<<5)
 #define  TRANS_MSA_8_BPC   (1<<5)
 #define  TRANS_MSA_10_BPC  (2<<5)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7b89f2a..7616f6f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1499,6 +1499,13 @@ void intel_ddi_set_pipe_settings(const struct 
intel_crtc_state *crtc_state)
break;
}
 
+   /*
+* As per DP 1.2 spec section 2.3.4.3 while sending
+* YCBCR 444 signals we should program MSA MISC1/0 fields with
+* colorspace information.
+*/
+   if (crtc_state->output_format == CRTC_OUTPUT_YCBCR444)
+   temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 35c5299..3bf82ea 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1613,6 +1613,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct intel_lspcon *lspcon = enc_to_intel_lspcon(>base);
enum port port = encoder->port;
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
struct intel_connector *intel_connector = intel_dp->attached_connector;
@@ -1642,6 +1643,15 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
 
+   if (lspcon->active) {
+   struct drm_connector *connector = _connector->base;
+
+   if (lspcon_ycbcr420_config(connector, pipe_config)) {
+   pipe_config->output_format = CRTC_OUTPUT_YCBCR444;
+   lspcon->output_format = CRTC_OUTPUT_YCBCR420;
+   }
+   }
+
pipe_config->has_drrs = false;
if (IS_G4X(dev_priv) || port == PORT_A)
pipe_config->has_audio = false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2de6b41..5edba06 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2047,6 +2047,8 @@ void lspcon_set_infoframes(struct drm_encoder *encoder,
   const struct drm_connector_state *conn_state);
 bool lspcon_infoframe_enabled(struct drm_encoder *encoder,
  const struct intel_crtc_state *pipe_config);
+bool lspcon_ycbcr420_config(struct drm_connector *connector,
+struct intel_crtc_state *config);
 
 /* intel_pipe_crc.c */
 int intel_pipe_crc_create(struct drm_minor *minor);
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 066ea91..cb88138 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ 

[Intel-gfx] [PATCH v3 0/7] YCBCR 4:2:0/4:4:4 output support for LSPCON

[Shashank Sharma]

This patch series adds YCBCR 4:2:0 output support for LSPCON displays.
In order to indicate the color format of output, to the LSPCON device,
a source has to set and send proper AVI infoframes to LSPCON. So this
patch series:
- first adds AVI infoframes support for LSPCON
- then adds YCBCR 4:2:0 output support for LSPCON

Previous versions of this series and its review can be found here:
https://patchwork.freedesktop.org/series/28536/
https://patchwork.freedesktop.org/series/33794/

In order to address review comment from V2, I have added 2 new patches
in this series, hence sending V3.

Shashank Sharma (7):
  drm/i915: Add CRTC output format YCBCR 4:2:0
  drm/i915: Add CRTC output format YCBCR 4:4:4
  drm/i915: Check LSPCON vendor OUI
  drm/i915: Add AVI infoframe support for LSPCON
  drm/i915: Write AVI infoframes for MCA LSPCON
  drm/i915: Write AVI infoframes for Parade LSPCON
  drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

 drivers/gpu/drm/i915/i915_reg.h  |   2 +
 drivers/gpu/drm/i915/intel_color.c   |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c |  28 ++-
 drivers/gpu/drm/i915/intel_display.c |  73 +---
 drivers/gpu/drm/i915/intel_dp.c  |  10 +
 drivers/gpu/drm/i915/intel_drv.h |  37 +++-
 drivers/gpu/drm/i915/intel_hdmi.c|  23 ++-
 drivers/gpu/drm/i915/intel_lspcon.c  | 343 +--
 drivers/gpu/drm/i915/intel_panel.c   |   2 +-
 9 files changed, 469 insertions(+), 52 deletions(-)

-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. (rev2)
URL   : https://patchwork.freedesktop.org/series/36039/
State : success

== Summary ==

Series 36039v2 drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
https://patchwork.freedesktop.org/api/1.0/series/36039/revisions/2/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +1
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-hsw-4770) fdo#103375
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#104260

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104260 https://bugs.freedesktop.org/show_bug.cgi?id=104260

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:276s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:476s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:450s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:263s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:407s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:498s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:573s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:524s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:488s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:427s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:603s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:466s

3e7d28b655aefefe51f1d7ac6aba46d6ca03b658 drm-tip: 2018y-01m-04d-22h-45m-20s UTC 
integration manifest
61ff562c5c4b drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7615/issues.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for GuC Interrupts/Log updates (rev3)

[Patchwork]

== Series Details ==

Series: GuC Interrupts/Log updates (rev3)
URL   : https://patchwork.freedesktop.org/series/32179/
State : failure

== Summary ==

Series 32179v3 GuC Interrupts/Log updates
https://patchwork.freedesktop.org/api/1.0/series/32179/revisions/3/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> SKIP   (fi-skl-gvtdvm)
Test core_prop_blob:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713 +1
pass   -> DMESG-WARN (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6600u)
pass   -> DMESG-WARN (fi-skl-6700hq)
pass   -> DMESG-WARN (fi-skl-6700k2)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-bxt-dsi)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-kbl-7500u) fdo#103285
pass   -> DMESG-WARN (fi-kbl-7560u)
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-subslice-total:
pass   -> SKIP   (fi-skl-gvtdvm)
Test drv_hangman:
Subgroup error-state-basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_basic:
Subgroup bad-close:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup create-close:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup create-fd-close:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_busy:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-hang-default:
pass   -> SKIP   (fi-skl-gvtdvm) fdo#104108 +2
Test gem_close_race:
Subgroup basic-process:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-threads:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_create:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-files:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_exec:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_param:
Subgroup basic:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_ctx_switch:
Subgroup basic-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-default-heavy:
pass   -> SKIP   (fi-skl-gvtdvm)
Test gem_exec_basic:
Subgroup basic-blt:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-bsd:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-bsd1:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-bsd2:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-render:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup basic-vebox:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-blt:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-bsd:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-bsd1:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-bsd2:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-default:
pass   -> SKIP   (fi-skl-gvtdvm)
Subgroup gtt-render:
pass   -> SKIP   (fi-skl-gvtdvm)
WARNING: Long output truncated
fi-glk-1 failed to collect. IGT log at Patchwork_7614/fi-glk-1/igt.log

3e7d28b655aefefe51f1d7ac6aba46d6ca03b658 drm-tip: 2018y-01m-04d-22h-45m-20s UTC 
integration manifest
5a97f4912290 HAX: drm/i915/guc: enable GuC submission/logging for CI
728519ffad84 drm/i915/guc: Restore GuC interrupts across suspend/reset if 
enabled
8e98ff385ceb drm/i915/guc: Add client support to enable/disable GuC interrupts
6543e7c34d80 drm/i915/guc: Make GuC log related functions depend only on log 
level
83bce4cea636 drm/i915/guc: Make guc_log_level parameter immutable
c2bae0060358 drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts
2acc300475d4 

[Intel-gfx] [PATCH i-g-t 2/2] test/kms_psr_sink : HACK run psr_drrs on BAT

[Marta Lofstedt]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260

Signed-off-by: Marta Lofstedt 
---
 tests/intel-ci/fast-feedback.testlist | 575 +-
 1 file changed, 288 insertions(+), 287 deletions(-)

diff --git a/tests/intel-ci/fast-feedback.testlist 
b/tests/intel-ci/fast-feedback.testlist
index f71a16bc..34db4706 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,295 +1,296 @@
 # Keep alphabetically sorted by default
 
-igt@core_auth@basic-auth
-igt@core_prop_blob@basic
-igt@debugfs_test@read_all_entries
-igt@drv_getparams_basic@basic-eu-total
-igt@drv_getparams_basic@basic-subslice-total
-igt@drv_hangman@error-state-basic
-igt@gem_basic@bad-close
-igt@gem_basic@create-close
-igt@gem_basic@create-fd-close
-igt@gem_busy@basic-busy-default
-igt@gem_busy@basic-hang-default
-igt@gem_close_race@basic-process
-igt@gem_close_race@basic-threads
-igt@gem_cpu_reloc@basic
-igt@gem_cs_tlb@basic-default
-igt@gem_ctx_create@basic
-igt@gem_ctx_create@basic-files
-igt@gem_ctx_exec@basic
-igt@gem_ctx_param@basic
-igt@gem_ctx_param@basic-default
-igt@gem_ctx_switch@basic-default
-igt@gem_ctx_switch@basic-default-heavy
-igt@gem_exec_basic@basic-blt
-igt@gem_exec_basic@basic-bsd
-igt@gem_exec_basic@basic-bsd1
-igt@gem_exec_basic@basic-bsd2
-igt@gem_exec_basic@basic-default
-igt@gem_exec_basic@basic-render
-igt@gem_exec_basic@basic-vebox
-igt@gem_exec_basic@gtt-blt
-igt@gem_exec_basic@gtt-bsd
-igt@gem_exec_basic@gtt-bsd1
-igt@gem_exec_basic@gtt-bsd2
-igt@gem_exec_basic@gtt-default
-igt@gem_exec_basic@gtt-render
-igt@gem_exec_basic@gtt-vebox
-igt@gem_exec_basic@readonly-blt
-igt@gem_exec_basic@readonly-bsd
-igt@gem_exec_basic@readonly-bsd1
-igt@gem_exec_basic@readonly-bsd2
-igt@gem_exec_basic@readonly-default
-igt@gem_exec_basic@readonly-render
-igt@gem_exec_basic@readonly-vebox
-igt@gem_exec_create@basic
-igt@gem_exec_fence@basic-busy-default
-igt@gem_exec_fence@basic-wait-default
-igt@gem_exec_fence@basic-await-default
-igt@gem_exec_fence@await-hang-default
-igt@gem_exec_fence@nb-await-default
-igt@gem_exec_flush@basic-batch-kernel-default-cmd
-igt@gem_exec_flush@basic-batch-kernel-default-uc
-igt@gem_exec_flush@basic-batch-kernel-default-wb
-igt@gem_exec_flush@basic-uc-pro-default
-igt@gem_exec_flush@basic-uc-prw-default
-igt@gem_exec_flush@basic-uc-ro-default
-igt@gem_exec_flush@basic-uc-rw-default
-igt@gem_exec_flush@basic-uc-set-default
-igt@gem_exec_flush@basic-wb-pro-default
-igt@gem_exec_flush@basic-wb-prw-default
-igt@gem_exec_flush@basic-wb-ro-before-default
-igt@gem_exec_flush@basic-wb-ro-default
-igt@gem_exec_flush@basic-wb-rw-before-default
-igt@gem_exec_flush@basic-wb-rw-default
-igt@gem_exec_flush@basic-wb-set-default
-igt@gem_exec_gttfill@basic
-igt@gem_exec_nop@basic-parallel
-igt@gem_exec_nop@basic-series
-igt@gem_exec_parallel@basic
-igt@gem_exec_parse@basic-allowed
-igt@gem_exec_parse@basic-rejected
-igt@gem_exec_reloc@basic-cpu
-igt@gem_exec_reloc@basic-gtt
-igt@gem_exec_reloc@basic-cpu-gtt
-igt@gem_exec_reloc@basic-gtt-cpu
-igt@gem_exec_reloc@basic-cpu-read
-igt@gem_exec_reloc@basic-gtt-read
-igt@gem_exec_reloc@basic-write-cpu
-igt@gem_exec_reloc@basic-write-gtt
-igt@gem_exec_reloc@basic-write-read
-igt@gem_exec_reloc@basic-cpu-noreloc
-igt@gem_exec_reloc@basic-gtt-noreloc
-igt@gem_exec_reloc@basic-cpu-gtt-noreloc
-igt@gem_exec_reloc@basic-gtt-cpu-noreloc
-igt@gem_exec_reloc@basic-cpu-read-noreloc
-igt@gem_exec_reloc@basic-gtt-read-noreloc
-igt@gem_exec_reloc@basic-write-cpu-noreloc
-igt@gem_exec_reloc@basic-write-gtt-noreloc
-igt@gem_exec_reloc@basic-write-read-noreloc
-igt@gem_exec_reloc@basic-cpu-active
-igt@gem_exec_reloc@basic-gtt-active
-igt@gem_exec_reloc@basic-cpu-gtt-active
-igt@gem_exec_reloc@basic-gtt-cpu-active
-igt@gem_exec_reloc@basic-cpu-read-active
-igt@gem_exec_reloc@basic-gtt-read-active
-igt@gem_exec_reloc@basic-write-cpu-active
-igt@gem_exec_reloc@basic-write-gtt-active
-igt@gem_exec_reloc@basic-write-read-active
-igt@gem_exec_reloc@basic-softpin
-igt@gem_exec_store@basic-all
-igt@gem_exec_store@basic-blt
-igt@gem_exec_store@basic-bsd
-igt@gem_exec_store@basic-bsd1
-igt@gem_exec_store@basic-bsd2
-igt@gem_exec_store@basic-default
-igt@gem_exec_store@basic-render
-igt@gem_exec_store@basic-vebox
-igt@gem_exec_suspend@basic
-igt@gem_exec_suspend@basic-s3
-igt@gem_exec_suspend@basic-s4-devices
-igt@gem_flink_basic@bad-flink
-igt@gem_flink_basic@bad-open
-igt@gem_flink_basic@basic
-igt@gem_flink_basic@double-flink
-igt@gem_flink_basic@flink-lifetime
-igt@gem_linear_blits@basic
-igt@gem_mmap@basic
-igt@gem_mmap@basic-small-bo
-igt@gem_mmap_gtt@basic
-igt@gem_mmap_gtt@basic-copy
-igt@gem_mmap_gtt@basic-read
-igt@gem_mmap_gtt@basic-read-no-prefault
-igt@gem_mmap_gtt@basic-read-write
-igt@gem_mmap_gtt@basic-read-write-distinct
-igt@gem_mmap_gtt@basic-short
-igt@gem_mmap_gtt@basic-small-bo
-igt@gem_mmap_gtt@basic-small-bo-tiledx
-igt@gem_mmap_gtt@basic-small-bo-tiledy

[Intel-gfx] [PATCH i-g-t 1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Marta Lofstedt]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260

Signed-off-by: Marta Lofstedt 
---
 tests/kms_psr_sink_crc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 83a69f0b..26cf434a 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -532,11 +532,13 @@ int main(int argc, char *argv[])
igt_subtest("psr_basic") {
setup_test_plane();
igt_assert(wait_psr_entry());
+   test_cleanup();
}
 
igt_subtest("psr_drrs") {
setup_test_plane();
igt_assert(drrs_disabled());
+   test_cleanup();
}
 
for (op = PAGE_FLIP; op <= RENDER; op++) {
-- 
2.11.0

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[Intel-gfx] [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Kenneth Graunke]

Geminilake requires the 3D driver to select whether barriers are
intended for compute shaders, or tessellation control shaders, by
whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
switching pipelines.  Failure to do this properly can result in GPU
hangs.

Unfortunately, this means it needs to switch mid-batch, so only
userspace can properly set it.  To facilitate this, the kernel needs
to whitelist the register.

The workarounds page currently tags this as applying to Broxton only,
but that doesn't make sense.  The documentation for the register it
references says the bit userspace is supposed to toggle only exists on
Geminilake.  Empirically, the Mesa patch to toggle this bit appears to
fix intermittent GPU hangs in tessellation control shader barrier tests
on Geminilake; we haven't seen those hangs on Broxton.

v2: Mention WA #0862 in the comment (it doesn't have a name).

Signed-off-by: Kenneth Graunke 
Acked-by: Rodrigo Vivi 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_reg.h| 2 ++
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 966e4df9700e..505c605eff98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7079,6 +7079,8 @@ enum {
 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
+#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ebdcbcbacb3c..6bb51a502b8b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
+   ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+   if (ret)
+   return ret;
+
/* WaToEnableHwFixForPushConstHWBug:glk */
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-- 
2.15.1

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Re: [Intel-gfx] [PATCH v3 04/12] drm/i915/guc: Add description and comments about guc_log_level parameter

[Sagar Arun Kamble]

On 1/5/2018 10:24 AM, Sagar Arun Kamble wrote:



On 1/4/2018 10:22 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:46 +0100, Sagar Arun Kamble 
 wrote:



guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info.

^^^
Extra "."


in parameter description and documentation.
Earlier, this patch was added to sanitize guc_log_level like old
GuC parameters enable_guc_loading/submission. With new parameter
enable_guc, sanitization of guc_log_level is no more needed.


Hmm, I think we still need to sanitize log_level if it was wrongly
enabled without enabling GuC first (in intel_uc_sanitize_options).
I think it would not be harmful as all decisions based on it will be 
gated by USES_GUC.
I was wrong. i915_guc_log_register/unregister were changed by my series 
to only rely on guc_log_level.
I have added HAS_GUC check in those function in v4 patch. Is that option 
okay or we should sanitize this parameter?




v2: Added documentation to intel_guc_log.c and param description
about GuC loading dependency. (Michal Wajdeczko)

v3: Removed sanitization of module parameter guc_log_level.
Previous review comments not applicable now.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin  #v2
---
 drivers/gpu/drm/i915/i915_params.c   | 3 ++-
 drivers/gpu/drm/i915/intel_guc_log.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c

index b5f3eb4..a93a6ca 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -155,7 +155,8 @@ struct i915_params i915_modparams __read_mostly = {
 "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
i915_param_named(guc_log_level, int, 0400,
-    "GuC firmware logging level (-1:disabled (default), 
0-3:enabled)");
+    "GuC firmware logging level. This takes effect only if GuC is 
to be "
+    "loaded (depends on enable_guc) (-1:disabled (default), 
0-3:enabled)");


Btw, I was planing to change above values to follow schema used in 
other modparams:


-1: auto (then it can be controlled by USES_GUC and DRM_I915_DEBUG_GUC)
 0: disabled
 1: enabled (legacy level 0)
 2: enabled (legacy level 1)
 3: enabled (legacy level 2)
 4: enabled (legacy level 3)

So now I'm not sure that I want your patch ;)


Makes sense. Will drop this patch.

Thanks
Sagar

i915_param_named_unsafe(guc_firmware_path, charp, 0400,
 "GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c

index 59a9021..d0131bc 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -34,6 +34,7 @@
  * DOC: GuC firmware log
  *
  * Firmware log is enabled by setting i915.guc_log_level to 
non-negative level.

+ * This takes effect only if GuC is to be loaded based on enable_guc.


... based on i915.enable_guc modparam.

  * Log data is printed out via reading debugfs i915_guc_log_dump. 
Reading from
  * i915_guc_load_status will print out firmware loading status and 
scratch

  * registers value.




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[Intel-gfx] [PATCH v4 7/9] drm/i915/guc: Add client support to enable/disable GuC interrupts

[Sagar Arun Kamble]

This patch adds support to enable/disable GuC interrupts for different
features without impacting other's need. Currently GuC log capture and
CT buffer receive mechanisms use the GuC interrupts. GuC interrupts are
currently enabled and disabled in different logging scenarios all gated
by log level.

v2: Rebase with all GuC interrupt handlers moved to intel_guc.c. Handling
multiple clients for GuC interrupts enable/disable.
(Michal Wajdeczko)

v3: Removed spin lock and using test_bit in i915_guc_info. Prepared low
level helpers to get/put GuC interrupts that can be reused during
suspend/resume. (Tvrtko)

v4: Rebase. Removed comments about logging being sole user of interrupts.
s/guc_intr_client/intel_guc_intr_client. Reverted function names to
enable/disable_interrupts from get/put_interrupts as applicable. (Michal)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 +
 drivers/gpu/drm/i915/intel_guc.c | 45 
 drivers/gpu/drm/i915/intel_guc.h | 13 ---
 drivers/gpu/drm/i915/intel_guc_log.c |  6 ++---
 4 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 16f9a95..eef4c8b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2340,6 +2340,12 @@ static int i915_guc_info(struct seq_file *m, void *data)
GEM_BUG_ON(!guc->execbuf_client);
GEM_BUG_ON(!guc->preempt_client);
 
+   seq_puts(m, "GuC Interrupt Clients: ");
+   if (test_bit(GUC_INTR_CLIENT_LOG, >interrupt_clients))
+   seq_puts(m, "GuC Logging\n");
+   else
+   seq_puts(m, "None\n");
+
seq_printf(m, "Doorbell map:\n");
seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 7b06c7b..7d66ee5 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -522,28 +522,53 @@ void intel_guc_reset_interrupts(struct intel_guc *guc)
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_guc_enable_interrupts(struct intel_guc *guc)
+static void __intel_guc_enable_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   lockdep_assert_held(_priv->irq_lock);
+
+   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+  dev_priv->pm_guc_events);
+   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_guc_enable_interrupts(struct intel_guc *guc,
+enum intel_guc_intr_client id)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
spin_lock_irq(_priv->irq_lock);
-   if (!guc->interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   guc->interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
+
+   if (!guc->interrupt_clients)
+   __intel_guc_enable_interrupts(guc);
+   __set_bit(id, >interrupt_clients);
+
spin_unlock_irq(_priv->irq_lock);
 }
 
-void intel_guc_disable_interrupts(struct intel_guc *guc)
+static void __intel_guc_disable_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
-   spin_lock_irq(_priv->irq_lock);
-   guc->interrupts_enabled = false;
+   lockdep_assert_held(_priv->irq_lock);
 
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+}
+
+void intel_guc_disable_interrupts(struct intel_guc *guc,
+ enum intel_guc_intr_client id)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+
+   __clear_bit(id, >interrupt_clients);
+   if (guc->interrupt_clients) {
+   spin_unlock_irq(_priv->irq_lock);
+   return;
+   }
+   __intel_guc_disable_interrupts(guc);
 
spin_unlock_irq(_priv->irq_lock);
synchronize_irq(dev_priv->drm.irq);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 1df9222..f248565 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -34,6 +34,11 @@
 #include "intel_uc_fw.h"
 #include "i915_vma.h"
 
+enum intel_guc_intr_client {
+   GUC_INTR_CLIENT_LOG = 0,
+   GUC_INTR_CLIENT_COUNT
+};
+
 struct guc_preempt_work {
struct work_struct work;

[Intel-gfx] [PATCH v4 8/9] drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled

[Sagar Arun Kamble]

In order to override the disable/enable control of GuC interrupts during
suspend/reset cycle we are creating two new functions suspend/restore
guc_interrupts which check if interrupts were enabled and disable them
on suspend and enable them on resume. They are used to restore interrupts
across reset as well.

Further restructuring of runtime_pm_enable/disable_interrupts and
suspend/restore_guc_interrupts will be done in upcoming patches.

v2: Rebase.

v3: Updated suspend/restore with the new low level get/put functions.
(Tvrtko)

v4: Rebase. s/intel_*_guc_interrupts/intel_guc_*_interrupts (Michal)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_guc.c | 30 --
 drivers/gpu/drm/i915/intel_guc.h |  2 ++
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0cd3559..fe5e71a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3676,8 +3676,10 @@ void intel_finish_reset(struct drm_i915_private 
*dev_priv)
 * The display has been reset as well,
 * so need a full re-initialization.
 */
+   intel_guc_suspend_interrupts(_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_guc_restore_interrupts(_priv->guc);
 
intel_pps_unlock_regs_wa(dev_priv);
intel_modeset_init_hw(dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 7d66ee5..0a33eda 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,7 +406,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   intel_guc_log_disable_interrupts(guc);
+   intel_guc_suspend_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -451,7 +451,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   intel_guc_log_enable_interrupts(guc);
+   intel_guc_restore_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -547,6 +547,16 @@ void intel_guc_enable_interrupts(struct intel_guc *guc,
spin_unlock_irq(_priv->irq_lock);
 }
 
+void intel_guc_restore_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (guc->interrupt_clients)
+   __intel_guc_enable_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+}
+
 static void __intel_guc_disable_interrupts(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,6 +586,22 @@ void intel_guc_disable_interrupts(struct intel_guc *guc,
intel_guc_reset_interrupts(guc);
 }
 
+void intel_guc_suspend_interrupts(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   spin_lock_irq(_priv->irq_lock);
+   if (!guc->interrupt_clients) {
+   spin_unlock_irq(_priv->irq_lock);
+   return;
+   }
+   __intel_guc_disable_interrupts(guc);
+   spin_unlock_irq(_priv->irq_lock);
+   synchronize_irq(dev_priv->drm.irq);
+
+   intel_guc_reset_interrupts(guc);
+}
+
 void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f248565..ef7d2fd 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -142,5 +142,7 @@ void intel_guc_enable_interrupts(struct intel_guc *guc,
 void intel_guc_disable_interrupts(struct intel_guc *guc,
  enum intel_guc_intr_client id);
 void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);
+void intel_guc_suspend_interrupts(struct intel_guc *guc);
+void intel_guc_restore_interrupts(struct intel_guc *guc);
 
 #endif
-- 
1.9.1

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[Intel-gfx] [PATCH v4 6/9] drm/i915/guc: Make GuC log related functions depend only on log level

[Sagar Arun Kamble]

With GuC log level set properly only for cases where GuC is loaded we can
remove the GuC submission checks from flush_guc_logs and guc_log_register,
unregister and uc_fini_hw functions. It is important to note that GuC log
runtime data has to be freed during driver unregister.
Freeing of that data can't be gated by guc_log_level check because if we
free GuC log runtime only when log level >=0 then it will not be destroyed
when logging is disabled after enabling before driver unload.

Also, with this patch GuC interrupts are enabled first after GuC load if
logging is enabled. GuC to Host interrupts will be needed for GuC CTB
mechanism and hence we will be adding client support to control the
interrupt for Log and CTB feature in next patch. To prepare for that all
interrupt updates are now gated by GuC log level checks through new
functions intel_guc_log_*_interrupts.

v2: Rebase. Updated check in i915_guc_log_unregister to be based on
guc_log_level. (Michal Wajdeczko)

v3: Rebase. Made all GuC log related functions depend only log level.
Updated uC init w.r.t enabling of GuC interrupts. Commit message update.
Rebase w.r.t guc_log_level immutable changes. (Tvrtko)

v4: Rebase. Prepared new functions intel_guc_log_*_interrupts to reduce
log level checks. (Michal)
Added HAS_GUC checks to i915_guc_log_register/unregister as the parameter
is not sanitized. (Sagar)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  5 ++---
 drivers/gpu/drm/i915/intel_guc_log.c | 29 +
 drivers/gpu/drm/i915/intel_guc_log.h |  2 ++
 drivers/gpu/drm/i915/intel_uc.c  | 13 ++---
 4 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 710b4c4..7b06c7b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -406,7 +406,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   intel_guc_disable_interrupts(guc);
+   intel_guc_log_disable_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -451,8 +451,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (guc->log.level >= 0)
-   intel_guc_enable_interrupts(guc);
+   intel_guc_log_enable_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index aa6434a..1e535e6 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -483,12 +483,11 @@ static void guc_log_capture_logs(struct intel_guc *guc)
 
 static void guc_flush_logs(struct intel_guc *guc)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   guc->log.level < 0)
+   if (guc->log.level < 0)
return;
 
/* First disable the interrupts, will be renabled afterwards */
-   intel_guc_disable_interrupts(guc);
+   intel_guc_log_disable_interrupts(guc);
 
/* Before initiating the forceful flush, wait for any pending/ongoing
 * flush to complete otherwise forceful flush may not actually happen.
@@ -594,7 +593,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, 
u64 control_val)
}
 
/* GuC logging is currently the only user of Guc2Host 
interrupts */
-   intel_guc_enable_interrupts(guc);
+   intel_guc_log_enable_interrupts(guc);
} else {
/* Once logging is disabled, GuC won't generate logs & send an
 * interrupt. But there could be some data in the log buffer
@@ -612,8 +611,10 @@ int i915_guc_log_control(struct drm_i915_private 
*dev_priv, u64 control_val)
 
 void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv) ||
-   dev_priv->guc.log.level < 0)
+   if (!HAS_GUC(dev_priv))
+   return;
+
+   if (dev_priv->guc.log.level < 0)
return;
 
mutex_lock(_priv->drm.struct_mutex);
@@ -623,15 +624,27 @@ void i915_guc_log_register(struct drm_i915_private 
*dev_priv)
 
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-   if (!USES_GUC_SUBMISSION(dev_priv))
+   if (!HAS_GUC(dev_priv))
return;
 
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */

[Intel-gfx] [PATCH v4 3/9] drm/i915/guc: Separate creation/release of runtime logging data from base logging data

[Sagar Arun Kamble]

GuC log runtime/relay channel data will get released during i915
unregister, and only GuC log vma needs to be released during fini. To
achieve this, prepare separate helpers to create/destroy base and runtime
logging.
This separation is also needed to couple runtime log data and interrupts
handling together. In future we might not want to consider runtime data
creation failure as catastrophic to abort GuC load. Then we can ignore
the return error codes from intel_guc_log_runtime_create().

v2: Rebase.

v3: Refined usage of intel_guc_log_destroy and created new function
intel_guc_log_runtime_destroy. (Tvrtko)
Added intel_guc_log_runtime_create to separate the creation part as well.

v4: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc.c |  8 +++-
 drivers/gpu/drm/i915/intel_guc_log.c | 22 --
 drivers/gpu/drm/i915/intel_guc_log.h |  2 ++
 3 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 7278bde..9dac3ee 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -168,9 +168,13 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_shared;
 
-   ret = intel_guc_ads_create(guc);
+   ret = intel_guc_log_runtime_create(guc);
if (ret)
goto err_log;
+
+   ret = intel_guc_ads_create(guc);
+   if (ret)
+   goto err_log_runtime;
GEM_BUG_ON(!guc->ads_vma);
 
/* We need to notify the guc whenever we change the GGTT */
@@ -178,6 +182,8 @@ int intel_guc_init(struct intel_guc *guc)
 
return 0;
 
+err_log_runtime:
+   intel_guc_log_runtime_destroy(guc);
 err_log:
intel_guc_log_destroy(guc);
 err_shared:
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 84ae6f8..d866645 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -356,7 +356,7 @@ static bool guc_log_has_runtime(struct intel_guc *guc)
return guc->log.runtime.buf_addr != NULL;
 }
 
-static int guc_log_runtime_create(struct intel_guc *guc)
+int intel_guc_log_runtime_create(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
void *vaddr;
@@ -364,6 +364,9 @@ static int guc_log_runtime_create(struct intel_guc *guc)
size_t n_subbufs, subbuf_size;
int ret;
 
+   if (i915_modparams.guc_log_level < 0)
+   return 0;
+
lockdep_assert_held(_priv->drm.struct_mutex);
 
GEM_BUG_ON(guc_log_has_runtime(guc));
@@ -419,7 +422,7 @@ static int guc_log_runtime_create(struct intel_guc *guc)
return ret;
 }
 
-static void guc_log_runtime_destroy(struct intel_guc *guc)
+void intel_guc_log_runtime_destroy(struct intel_guc *guc)
 {
/*
 * It's possible that the runtime stuff was never allocated because
@@ -445,7 +448,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
 * handle log buffer flush interrupts would not have been done 
yet,
 * so do that now.
 */
-   ret = guc_log_runtime_create(guc);
+   ret = intel_guc_log_runtime_create(guc);
if (ret)
goto err;
}
@@ -457,7 +460,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
return 0;
 
 err_runtime:
-   guc_log_runtime_destroy(guc);
+   intel_guc_log_runtime_destroy(guc);
 err:
/* logging will remain off */
i915_modparams.guc_log_level = -1;
@@ -535,12 +538,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
guc->log.vma = vma;
 
-   if (i915_modparams.guc_log_level >= 0) {
-   ret = guc_log_runtime_create(guc);
-   if (ret < 0)
-   goto err_vma;
-   }
-
/* each allocated unit is a page */
flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
(GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
@@ -552,8 +549,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
return 0;
 
-err_vma:
-   i915_vma_unpin_and_release(>log.vma);
 err:
/* logging will be off */
i915_modparams.guc_log_level = -1;
@@ -562,7 +557,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
 void intel_guc_log_destroy(struct intel_guc *guc)
 {
-   guc_log_runtime_destroy(guc);
i915_vma_unpin_and_release(>log.vma);
 }
 
@@ -638,6 +632,6 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host 

[Intel-gfx] [PATCH v4 4/9] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Sagar Arun Kamble]

Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.

v2: Add comment about need to synchronize flush work and log runtime
destroy

v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)

v4: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index d866645..7bae6eb 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -631,7 +631,10 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
+   intel_runtime_pm_get(dev_priv);
intel_guc_disable_interrupts(_priv->guc);
+   intel_runtime_pm_put(dev_priv);
+
intel_guc_log_runtime_destroy(_priv->guc);
mutex_unlock(_priv->drm.struct_mutex);
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v4 1/9] drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to intel_guc.c

[Sagar Arun Kamble]

GuC interrupts handling is core GuC functionality. Better to keep it
with other core functions in intel_guc.c. Since they are used from
uC functions, GuC log and i915 irq handling we are keeping them grouped
in intel_guc.c instead of intel_uc.c. Also update the function parameter
from dev_priv to intel_guc struct while we are at it.

In order to separate GuC IRQ handling functions from i915_irq.c we need
to export the low level pm irq handlers. Export pm_iir, reset_pm_iir and
enable/disable_pm_irq functions.

v2-v3: Rebase.

v4: Squashed patches to change the parameter and move to guc.c. Using
readily available guc struct instead of referencing via dev_priv. (Michal)
s/intel_*_guc_interrupts/intel_guc_*_interrupts. (Chris)

Suggested-by: Michal Wajdeczko 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin  #v3
---
 drivers/gpu/drm/i915/i915_irq.c  | 78 +++---
 drivers/gpu/drm/i915/intel_drv.h |  7 ++--
 drivers/gpu/drm/i915/intel_guc.c | 81 ++--
 drivers/gpu/drm/i915/intel_guc.h |  4 ++
 drivers/gpu/drm/i915/intel_guc_log.c |  8 ++--
 drivers/gpu/drm/i915/intel_uc.c  |  8 ++--
 6 files changed, 98 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c65..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -203,7 +203,6 @@ static void gen2_assert_iir_is_zero(struct drm_i915_private 
*dev_priv,
 } while (0)
 
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
 
 /* For display hotplug interrupt */
 static inline void
@@ -306,7 +305,7 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, 
uint32_t mask)
ilk_update_gt_irq(dev_priv, mask, 0);
 }
 
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
+i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
@@ -369,7 +368,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, 
u32 mask)
__gen6_mask_pm_irq(dev_priv, mask);
 }
 
-static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 
reset_mask)
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 {
i915_reg_t reg = gen6_pm_iir(dev_priv);
 
@@ -380,7 +379,7 @@ static void gen6_reset_pm_iir(struct drm_i915_private 
*dev_priv, u32 reset_mask)
POSTING_READ(reg);
 }
 
-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 
enable_mask)
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 {
lockdep_assert_held(_priv->irq_lock);
 
@@ -390,7 +389,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private 
*dev_priv, u32 enable_mas
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 }
 
-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 
disable_mask)
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 {
lockdep_assert_held(_priv->irq_lock);
 
@@ -450,38 +449,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private 
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
 }
 
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
-   spin_unlock_irq(_priv->irq_lock);
-}
-
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   if (!dev_priv->guc.interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   dev_priv->guc.interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
-   spin_unlock_irq(_priv->irq_lock);
-}
-
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
-   spin_lock_irq(_priv->irq_lock);
-   dev_priv->guc.interrupts_enabled = false;
-
-   gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-
-   spin_unlock_irq(_priv->irq_lock);
-   synchronize_irq(dev_priv->drm.irq);
-
-   gen9_reset_guc_interrupts(dev_priv);
-}
-
 /**
  * bdw_update_port_irq - update DE port interrupt
  * @dev_priv: driver private
@@ -1480,7 +1447,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private 
*dev_priv,
gen6_rps_irq_handler(dev_priv, gt_iir[2]);
 
if (gt_iir[2] & 

[Intel-gfx] [PATCH v4 5/9] drm/i915/guc: Make guc_log_level parameter immutable

[Sagar Arun Kamble]

This patch introduces i915 internal state variable in GuC log struct,
"level" which will be copied from guc_log_level modparam during i915
load and thereafter be available for user updates. This will make
guc_log_level parameter immutable.

v2: Rebase.

Suggested-by: Tvrtko Ursulin 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c |  6 +++---
 drivers/gpu/drm/i915/intel_guc_log.c | 23 ++-
 drivers/gpu/drm/i915/intel_guc_log.h |  6 ++
 drivers/gpu/drm/i915/intel_uc.c  | 11 +--
 5 files changed, 29 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bb6307..16f9a95 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2459,7 +2459,7 @@ static int i915_guc_log_control_get(void *data, u64 *val)
if (!dev_priv->guc.log.vma)
return -EINVAL;
 
-   *val = i915_modparams.guc_log_level;
+   *val = dev_priv->guc.log.level;
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 9dac3ee..710b4c4 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -253,9 +253,9 @@ void intel_guc_init_params(struct intel_guc *guc)
 
params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
-   if (i915_modparams.guc_log_level >= 0) {
+   if (guc->log.level >= 0) {
params[GUC_CTL_DEBUG] =
-   i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
+   guc->log.level << GUC_LOG_VERBOSITY_SHIFT;
} else {
params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
}
@@ -451,7 +451,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (i915_modparams.guc_log_level >= 0)
+   if (guc->log.level >= 0)
intel_guc_enable_interrupts(guc);
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 7bae6eb..aa6434a 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -147,7 +147,7 @@ static int guc_log_relay_file_create(struct intel_guc *guc)
struct dentry *log_dir;
int ret;
 
-   if (i915_modparams.guc_log_level < 0)
+   if (guc->log.level < 0)
return 0;
 
/* For now create the log file in /sys/kernel/debug/dri/0 dir */
@@ -364,7 +364,7 @@ int intel_guc_log_runtime_create(struct intel_guc *guc)
size_t n_subbufs, subbuf_size;
int ret;
 
-   if (i915_modparams.guc_log_level < 0)
+   if (guc->log.level < 0)
return 0;
 
lockdep_assert_held(_priv->drm.struct_mutex);
@@ -426,7 +426,7 @@ void intel_guc_log_runtime_destroy(struct intel_guc *guc)
 {
/*
 * It's possible that the runtime stuff was never allocated because
-* guc_log_level was < 0 at the time
+* guc->log.level was < 0 at the time
 **/
if (!guc_log_has_runtime(guc))
return;
@@ -463,7 +463,7 @@ static int guc_log_late_setup(struct intel_guc *guc)
intel_guc_log_runtime_destroy(guc);
 err:
/* logging will remain off */
-   i915_modparams.guc_log_level = -1;
+   guc->log.level = -1;
return ret;
 }
 
@@ -484,7 +484,7 @@ static void guc_log_capture_logs(struct intel_guc *guc)
 static void guc_flush_logs(struct intel_guc *guc)
 {
if (!USES_GUC_SUBMISSION(dev_priv) ||
-   (i915_modparams.guc_log_level < 0))
+   guc->log.level < 0)
return;
 
/* First disable the interrupts, will be renabled afterwards */
@@ -512,9 +512,6 @@ int intel_guc_log_create(struct intel_guc *guc)
 
GEM_BUG_ON(guc->log.vma);
 
-   if (i915_modparams.guc_log_level > GUC_LOG_VERBOSITY_MAX)
-   i915_modparams.guc_log_level = GUC_LOG_VERBOSITY_MAX;
-
/* The first page is to save log buffer state. Allocate one
 * extra page for others in case for overlap */
size = (1 + GUC_LOG_DPC_PAGES + 1 +
@@ -551,7 +548,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 
 err:
/* logging will be off */
-   i915_modparams.guc_log_level = -1;
+   guc->log.level = -1;
return ret;
 }
 
@@ -574,7 +571,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, 
u64 control_val)
return -EINVAL;
 
/* This combination doesn't make sense & won't have 

[Intel-gfx] [PATCH v4 2/9] drm/i915/guc: Fix GuC interrupts disabling with logging

[Sagar Arun Kamble]

With guc_log_unregister disabling runtime logging and interrupts, there
is no need to disable interrupts during uc_fini_hw hence it is removed.
With GuC CT buffer mechanism, interrupt disabling can be added later at
a point where CT mechanism ceases.

v2: Rebase.

v3: Moved this patch earlier in the series. (Tvrtko)

v4: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 16ed558..0e1227f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -377,7 +377,4 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
intel_guc_submission_disable(guc);
 
guc_disable_communication(guc);
-
-   if (USES_GUC_SUBMISSION(dev_priv))
-   intel_guc_disable_interrupts(guc);
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v4 0/9] GuC Interrupts/Log updates

[Sagar Arun Kamble]

This series addresses following features/fixes:
1. Restructuring to move GuC interrupts related functions to guc.c
2. Making GuC interrupts enable/disable client based and tying up with
   logging at all places.
3. Handle suspend/resume/reset for GuC interrupts.
4. Logging fixes about RPM wakeref and skipping relay release during
   uc_fini.

v2: Rebase.
v3: Made guc_log_level parameter immutable, client support for interrupt
control.
v4: Consolidated patches and addressed reviews. Dropped patch about
guc_log_level sanitization.

Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Radoslaw Szwichtenberg 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 

Sagar Arun Kamble (9):
  drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to
intel_guc.c
  drm/i915/guc: Fix GuC interrupts disabling with logging
  drm/i915/guc: Separate creation/release of runtime logging data from
base logging data
  drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts
  drm/i915/guc: Make guc_log_level parameter immutable
  drm/i915/guc: Make GuC log related functions depend only on log level
  drm/i915/guc: Add client support to enable/disable GuC interrupts
  drm/i915/guc: Restore GuC interrupts across suspend/reset if enabled
  HAX: drm/i915/guc: enable GuC submission/logging for CI

 drivers/gpu/drm/i915/i915_debugfs.c  |   8 +-
 drivers/gpu/drm/i915/i915_drv.c  |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  |   8 +-
 drivers/gpu/drm/i915/i915_irq.c  |  78 ++-
 drivers/gpu/drm/i915/i915_params.h   |   4 +-
 drivers/gpu/drm/i915/intel_display.c |   2 +
 drivers/gpu/drm/i915/intel_drv.h |   7 +-
 drivers/gpu/drm/i915/intel_guc.c | 145 +--
 drivers/gpu/drm/i915/intel_guc.h |  15 +++-
 drivers/gpu/drm/i915/intel_guc_log.c |  79 ++-
 drivers/gpu/drm/i915/intel_guc_log.h |  10 +++
 drivers/gpu/drm/i915/intel_uc.c  |  27 ---
 12 files changed, 242 insertions(+), 145 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v4 9/9] HAX: drm/i915/guc: enable GuC submission/logging for CI

[Sagar Arun Kamble]

Also 1) revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
2) fix RPM resume interrupt enabling w.r.t GuC resume
3) disable guc log streaming DRM logs
---
 drivers/gpu/drm/i915/i915_drv.c  | 4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 8 ++--
 drivers/gpu/drm/i915/i915_params.h   | 4 ++--
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 4 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d..c8460c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2659,6 +2659,8 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
+   intel_runtime_pm_enable_interrupts(dev_priv);
+
intel_guc_resume(dev_priv);
 
if (IS_GEN9_LP(dev_priv)) {
@@ -2682,8 +2684,6 @@ static int intel_runtime_resume(struct device *kdev)
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
 
-   intel_runtime_pm_enable_interrupts(dev_priv);
-
/*
 * On VLV/CHV display interrupts are part of the display
 * power well, so hpd is reinitialized from there. For
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f2a0f55..979709b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3550,8 +3550,6 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 
i915_ggtt_invalidate(i915);
@@ -3559,10 +3557,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 
i915_ggtt_invalidate(i915);
 }
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..25b7e88 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,8 +47,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
-   param(int, guc_log_level, -1) \
+   param(int, enable_guc, -1) \
+   param(int, guc_log_level, 1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index fd2a40e..84c0fc7 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -225,7 +225,7 @@ static bool guc_check_log_buf_overflow(struct intel_guc 
*guc,
/* buffer_full_cnt is a 4 bit counter */
guc->log.total_overflow_count[type] += 16;
}
-   DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+   //DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
}
 
return overflow;
@@ -338,7 +338,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
/* Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
}
 }
-- 
1.9.1

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Re: [Intel-gfx] [PATCH i-g-t 1/2] test/kms_psr_sink_crc - subtests psr_basic and psr_drrs need test cleanup

[Lofstedt, Marta]

Arek,
I didn't get any PW for this maybe because I sent it together with a HACK patch 
to get a test run on BAT.

Should I rename both patches and re-send to the list?

/Marta

> -Original Message-
> From: Lofstedt, Marta
> Sent: Thursday, January 4, 2018 4:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Latvala, Petri ; Lofstedt, Marta
> 
> Subject: [PATCH i-g-t 1/2] test/kms_psr_sink_crc - subtests psr_basic and
> psr_drrs need test cleanup
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260
> 
> Signed-off-by: Marta Lofstedt 
> ---
>  tests/kms_psr_sink_crc.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c index
> 83a69f0b..26cf434a 100644
> --- a/tests/kms_psr_sink_crc.c
> +++ b/tests/kms_psr_sink_crc.c
> @@ -532,11 +532,13 @@ int main(int argc, char *argv[])
>   igt_subtest("psr_basic") {
>   setup_test_plane();
>   igt_assert(wait_psr_entry());
> + test_cleanup();
>   }
> 
>   igt_subtest("psr_drrs") {
>   setup_test_plane();
>   igt_assert(drrs_disabled());
> + test_cleanup();
>   }
> 
>   for (op = PAGE_FLIP; op <= RENDER; op++) {
> --
> 2.11.0

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