[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the 
aux init to use it
URL   : https://patchwork.freedesktop.org/series/38744/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b28837aa5cbe drm/i915: Add enum aux_ch and clean up the aux init to use it
-:31: WARNING: line over 80 characters
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:5350:
+#define DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, 
_DPB_AUX_CH_CTL)

-:32: WARNING: line over 80 characters
#32: FILE: drivers/gpu/drm/i915/i915_reg.h:5351:
+#define DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, 
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

-:42: WARNING: line over 80 characters
#42: FILE: drivers/gpu/drm/i915/i915_reg.h:7878:
+#define PCH_DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)

-:43: WARNING: line over 80 characters
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:7879:
+#define PCH_DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

-:90: CHECK: No space is necessary after a cast
#90: FILE: drivers/gpu/drm/i915/intel_dp.c:1344:
+   aux_ch = (enum aux_ch) port;

-:349: WARNING: line over 80 characters
#349: FILE: drivers/gpu/drm/i915/intel_dp.c:1521:
+   intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, 
aux_ch, i);

total: 0 errors, 5 warnings, 1 checks, 393 lines checked
daf9018b0155 drm/i915/cnl: New power domain for AUX IO.
-:71: WARNING: line over 80 characters
#71: FILE: drivers/gpu/drm/i915/intel_psr.c:62:
+   struct drm_i915_private *dev_priv = 
to_i915(intel_dig_port->base.base.dev);

-:90: WARNING: line over 80 characters
#90: FILE: drivers/gpu/drm/i915/intel_psr.c:81:
+   struct drm_i915_private *dev_priv = 
to_i915(intel_dig_port->base.base.dev);

total: 0 errors, 2 warnings, 0 checks, 92 lines checked

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[Intel-gfx] [PATCH igt v3] Iterate over physical engines

[Chris Wilson]

We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for cases where we want to issue requests
once on each HW ring (avoiding aliasing issues).

v2: Remember can_store_dword for gem_sync
v3: Find more open-coded for_each_physical

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 lib/igt_gt.c   |  23 +
 lib/igt_gt.h   |   9 
 tests/amdgpu/amd_prime.c   |   6 +--
 tests/drv_hangman.c|  20 ++--
 tests/gem_busy.c   |  31 ++--
 tests/gem_concurrent_all.c |   2 +-
 tests/gem_ctx_create.c |   5 +-
 tests/gem_ctx_thrash.c |  37 +++---
 tests/gem_exec_async.c |  15 +++---
 tests/gem_exec_await.c |  17 +--
 tests/gem_exec_capture.c   |   2 +-
 tests/gem_exec_create.c|  17 +--
 tests/gem_exec_fence.c |  16 ++
 tests/gem_exec_gttfill.c   |  16 +-
 tests/gem_exec_latency.c   |  19 +++
 tests/gem_exec_nop.c   |  32 ++--
 tests/gem_exec_parallel.c  |  15 +-
 tests/gem_exec_reloc.c |   2 +-
 tests/gem_exec_schedule.c  |  31 
 tests/gem_exec_store.c |   2 +-
 tests/gem_exec_suspend.c   |  20 ++--
 tests/gem_exec_whisper.c   |  15 +-
 tests/gem_ring_sync_loop.c |   2 +-
 tests/gem_spin_batch.c |   5 +-
 tests/gem_sync.c   | 123 -
 25 files changed, 124 insertions(+), 358 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index f70fcb92..e630550b 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -660,3 +660,26 @@ bool gem_has_engine(int gem_fd,
gem_class_instance_to_eb_flags(gem_fd, class,
   instance));
 }
+
+bool gem_ring_is_physical_engine(int fd, unsigned ring)
+{
+   if (ring == I915_EXEC_DEFAULT)
+   return false;
+
+   /* BSD uses an extra flag to chose between aliasing modes */
+   if ((ring & 63) == I915_EXEC_BSD) {
+   bool explicit_bsd = ring & (3 << 13);
+   bool has_bsd2 = gem_has_bsd2(fd);
+   return explicit_bsd ? has_bsd2 : !has_bsd2;
+   }
+
+   return true;
+}
+
+bool gem_ring_has_physical_engine(int fd, unsigned ring)
+{
+   if (!gem_ring_is_physical_engine(fd, ring))
+   return false;
+
+   return gem_has_ring(fd, ring);
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 68592410..4d9d1aa0 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -81,6 +81,15 @@ extern const struct intel_execution_engine {
 e__++) \
for_if (gem_has_ring(fd__, flags__ = e__->exec_id | e__->flags))
 
+#define for_each_physical_engine(fd__, flags__) \
+   for (const struct intel_execution_engine *e__ = 
intel_execution_engines;\
+e__->name; \
+e__++) \
+   for_if (gem_ring_has_physical_engine(fd__, flags__ = 
e__->exec_id | e__->flags))
+
+bool gem_ring_is_physical_engine(int fd, unsigned int ring);
+bool gem_ring_has_physical_engine(int fd, unsigned int ring);
+
 bool gem_can_store_dword(int fd, unsigned int engine);
 
 extern const struct intel_execution_engine2 {
diff --git a/tests/amdgpu/amd_prime.c b/tests/amdgpu/amd_prime.c
index b2f326b4..bb68ccf3 100644
--- a/tests/amdgpu/amd_prime.c
+++ b/tests/amdgpu/amd_prime.c
@@ -179,12 +179,8 @@ static void i915_to_amd(int i915, int amd, 
amdgpu_device_handle device)
struct cork c;
 
nengine = 0;
-   for_each_engine(i915, engine) {
-   if (engine == 0)
-   continue;
-
+   for_each_physical_engine(i915, engine)
engines[nengine++] = engine;
-   }
igt_require(nengine);
 
memset(obj, 0, sizeof(obj));
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index 40c82257..38cb20c3 100644
--- a/tests/drv_hangman.c
+++ b/tests/drv_hangman.c
@@ -183,8 +183,6 @@ static void test_error_state_capture(unsigned ring_id,
igt_hang_t hang;
uint64_t offset;
 
-   igt_require(gem_has_ring(device, ring_id));
-
clear_error_state();
 
hang = igt_hang_ctx(device, 0, ring_id, HANG_ALLOW_CAPTURE, );
@@ -255,23 +253,11 @@ igt_main
if (e->exec_id == 0)
continue;
 
-   /*
-* If the device has 2 BSD rings then due to obtuse aliasing
-* in the API, we can not determine which ring I915_EXEC_BSD
-* will map to, and so must skip the test; as the matching name
-* may be either bsd or bsd2 depending on the kernel/test
-* ordering.
-*
-* Here we are not checking that executing on every ABI engine
- 

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-22 06:07:32)
> From: Tvrtko Ursulin 
> 
> Place context in/out hooks into the GuC backend, when contexts are
> assigned to ports, and removed from them, in order to be able to
> provide engine busy stats in GuC mode.
> 
> Signed-off-by: Tvrtko Ursulin 
> Testcase: igt/perf_pmu/busy-accuracy-*-*
> ---
>  drivers/gpu/drm/i915/intel_guc_submission.c | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 649113c7a3c2..8e99f8fd6da2 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -673,6 +673,7 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> struct intel_engine_execlists * const execlists = >execlists;
> struct execlist_port *port = execlists->port;
> struct i915_request *last = NULL;
> +   struct i915_gem_context *last_ctx = NULL;
> const struct execlist_port * const last_port =
> >port[execlists->port_mask];
> bool submit = false;
> @@ -718,8 +719,13 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> goto done;
> }
>  
> -   if (submit)
> +   if (submit) {
> port_assign(port, last);
> +   if (last->ctx != last_ctx) {
> +   
> intel_engine_context_in(last->engine);
> +   last_ctx = last->ctx;
> +   }
> +   }
> port++;
> }
>  
> @@ -741,6 +747,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> execlists->first = rb;
> if (submit) {
> port_assign(port, last);
> +   if (last->ctx != last_ctx)
> +   intel_engine_context_in(last->engine);
> execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
> guc_submit(engine);
> }
> @@ -763,6 +771,7 @@ static void guc_submission_tasklet(unsigned long data)
>  
> rq = port_request([0]);
> while (rq && i915_request_completed(rq)) {
> +   intel_engine_context_out(rq->engine);

If we only emit context_in once for 2 consecutive rq with the same
context, we would need to do the same for context_out.

Will be interesting to see if this explodes, or we may need yet another
test :)
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: GuC test run (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: GuC test run (rev4)
URL   : https://patchwork.freedesktop.org/series/38615/
State : failure

== Summary ==

Test kms_flip:
Subgroup modeset-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060 +1
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)
Subgroup oa-exponents:
incomplete -> PASS   (shard-apl) fdo#102254
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-top-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185
Test drv_selftest:
Subgroup live_guc:
pass   -> DMESG-WARN (shard-apl)
Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
pass   -> FAIL   (shard-hsw)
Test gem_exec_schedule:
Subgroup smoketest-all:
pass   -> FAIL   (shard-apl)
Subgroup smoketest-render:
pass   -> FAIL   (shard-apl)
Test drv_missed_irq:
pass   -> SKIP   (shard-apl)

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185

shard-apltotal:3369 pass:1753 dwarn:2   dfail:0   fail:23  skip:1590 
time:12350s
shard-hswtotal:3464 pass:1766 dwarn:1   dfail:0   fail:3   skip:1693 
time:11779s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6669s
Blacklisted hosts:
shard-kbltotal:3344 pass:1841 dwarn:10  dfail:0   fail:33  skip:1456 
time:8517s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8117/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

[Pandiyan, Dhinakaran]

On Wed, 2018-02-21 at 23:28 -0800, Dhinakaran Pandiyan wrote:
> From: Ville Syrjälä 
> 
> Since we no longer have a 1:1 correspondence between ports and AUX
> channels, let's give AUX channels their own enum. Makes it easier
> to tell the apples from the oranges, and we get rid of the
> port E AUX power domain FIXME since we now derive the power domain
> from the actual AUX CH.
> 
> v2: Rebase due to AUX F

Patch 2/2 has a dependency on this patch from Ville, so I have included
this patch for CI to test them together.

-DK
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[Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

[Dhinakaran Pandiyan]

PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain
for AUX-A enables DC_OFF well too. This is not required, so add a new
AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX
channels re-use the existing AUX domains as they do need power well 2.

v2: Add AUX IO domain only for AUX-A
Rebased on top of Ville's AUX series.

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Cc: Ville Syrjälä 
Suggested-by: Imre Deak 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_display.h|  1 +
 drivers/gpu/drm/i915/intel_dp.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h|  1 +
 drivers/gpu/drm/i915/intel_psr.c| 37 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +++
 5 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index f5733a2576e7..4e7418b345bc 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -186,6 +186,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_F,
+   POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eeb8a026fd08..777682a925c9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1331,7 +1331,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct 
drm_dp_aux_msg *msg)
return ret;
 }
 
-static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
+enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
 {
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b70ed154c4ce..725a5b8ab611 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1684,6 +1684,7 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
+enum aux_ch intel_aux_ch(struct intel_dp *intel_dp);
 
 /* intel_dp_aux_backlight.c */
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..ff77b505534c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,39 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+static void psr_power_get(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *dev_priv = 
to_i915(intel_dig_port->base.base.dev);
+   enum intel_display_power_domain aux_domain;
+
+   if (INTEL_GEN(dev_priv) < 10)
+   return;
+
+   /* CNL HW requires corresponding AUX IOs to be powered up for PSR, AUX-A
+* does not require the driver to disable DC states, but the rest do.
+* Although PSR is enabled only on Port A currently, let's do this
+* correctly for other ports too.
+*/
+   aux_domain = intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
+   intel_dp->aux_power_domain;
+   intel_display_power_get(dev_priv, aux_domain);
+}
+
+static void psr_power_put(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *dev_priv = 
to_i915(intel_dig_port->base.base.dev);
+   enum intel_display_power_domain aux_domain;
+
+   if (INTEL_GEN(dev_priv) < 10)
+   return;
+
+   aux_domain = intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
+   intel_dp->aux_power_domain;
+   intel_display_power_put(dev_priv, aux_domain);
+}
+
 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -459,6 +492,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 chicken;
 
+   psr_power_get(intel_dp);
+
if (dev_priv->psr.psr2_support) {
chicken = PSR2_VSC_ENABLE_PROG_HEADER;
if (dev_priv->psr.y_cord_support)
@@ -617,6 +652,8 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
else
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
}
+
+   psr_power_put(intel_dp);
 }
 
 /**
diff 

[Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

[Dhinakaran Pandiyan]

From: Ville Syrjälä 

Since we no longer have a 1:1 correspondence between ports and AUX
channels, let's give AUX channels their own enum. Makes it easier
to tell the apples from the oranges, and we get rid of the
port E AUX power domain FIXME since we now derive the power domain
from the actual AUX CH.

v2: Rebase due to AUX F

Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h  |   8 +-
 drivers/gpu/drm/i915/intel_display.h |  11 ++
 drivers/gpu/drm/i915/intel_dp.c  | 240 +--
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 4 files changed, 131 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abcb27d4..39d624083a17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5347,8 +5347,8 @@ enum {
 #define _DPF_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64520)
 #define _DPF_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64524)
 
-#define DP_AUX_CH_CTL(port)_MMIO_PORT(port, _DPA_AUX_CH_CTL, 
_DPB_AUX_CH_CTL)
-#define DP_AUX_CH_DATA(port, i)_MMIO(_PORT(port, _DPA_AUX_CH_DATA1, 
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, 
_DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, 
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY  (1 << 31)
 #define   DP_AUX_CH_CTL_DONE   (1 << 30)
@@ -7875,8 +7875,8 @@ enum {
 #define _PCH_DPD_AUX_CH_DATA4  0xe4320
 #define _PCH_DPD_AUX_CH_DATA5  0xe4324
 
-#define PCH_DP_AUX_CH_CTL(port)_MMIO_PORT((port) - PORT_B, 
_PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
-#define PCH_DP_AUX_CH_DATA(port, i)_MMIO(_PORT((port) - PORT_B, 
_PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define PCH_DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT((aux_ch) - AUX_CH_B, 
_PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT  0
diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index c4042e342f50..f5733a2576e7 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -139,6 +139,17 @@ enum dpio_phy {
 
 #define I915_NUM_PHYS_VLV 2
 
+enum aux_ch {
+   AUX_CH_A,
+   AUX_CH_B,
+   AUX_CH_C,
+   AUX_CH_D,
+   _AUX_CH_E, /* does not exist */
+   AUX_CH_F,
+};
+
+#define aux_ch_name(a) ((a) + 'A')
+
 enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f20b25f98e5a..eeb8a026fd08 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1331,171 +1331,194 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct 
drm_dp_aux_msg *msg)
return ret;
 }
 
-static enum port intel_aux_port(struct drm_i915_private *dev_priv,
-   enum port port)
+static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
 {
+   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
const struct ddi_vbt_port_info *info =
_priv->vbt.ddi_port_info[port];
-   enum port aux_port;
+   enum aux_ch aux_ch;
 
if (!info->alternate_aux_channel) {
+   aux_ch = (enum aux_ch) port;
+
DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
- port_name(port), port_name(port));
-   return port;
+ aux_ch_name(aux_ch), port_name(port));
+   return aux_ch;
}
 
switch (info->alternate_aux_channel) {
case DP_AUX_A:
-   aux_port = PORT_A;
+   aux_ch = AUX_CH_A;
break;
case DP_AUX_B:
-   aux_port = PORT_B;
+   aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
-   aux_port = PORT_C;
+   aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
-   aux_port = PORT_D;
+   aux_ch = AUX_CH_D;
break;
case DP_AUX_F:
-   aux_port = PORT_F;
+   aux_ch = AUX_CH_F;
break;
default:
MISSING_CASE(info->alternate_aux_channel);
-   aux_port = PORT_A;
+   aux_ch = AUX_CH_A;
break;
  

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

[Pandiyan, Dhinakaran]

On Tue, 2018-02-20 at 11:31 -0800, Rodrigo Vivi wrote:
> On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Since we no longer have a 1:1 correspondence between ports and AUX
> > channels, let's give AUX channels their own enum. Makes it easier
> > to tell the apples from the oranges, and we get rid of the
> > port E AUX power domain FIXME since we now derive the power domain
> > from the actual AUX CH.
> 
> 
> Beautiful clean-up. I had this in a todo list years ago and
> after staying on the bottom for so long I had removed it from there...
> > 
> > v2: Rebase due to AUX F
> 
> sorry and thanks! :)
> 
> > 
> > Signed-off-by: Ville Syrjälä 
> 
> I wondered if at least aux_power_domain part could be in a
> separated patch because by the end I was a bit confused...
> But in the end I could put all pieces together and it made sense
> again. So one patch for easy back porting seems better.
> 
> Reviewed-by: Rodrigo Vivi 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |   8 +-
> >  drivers/gpu/drm/i915/intel_display.h |  11 ++
> >  drivers/gpu/drm/i915/intel_dp.c  | 240 
> > +--
> >  drivers/gpu/drm/i915/intel_drv.h |   1 +
> >  4 files changed, 131 insertions(+), 129 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 1412abcb27d4..39d624083a17 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5347,8 +5347,8 @@ enum {
> >  #define _DPF_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64520)
> >  #define _DPF_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64524)
> >  
> > -#define DP_AUX_CH_CTL(port)_MMIO_PORT(port, _DPA_AUX_CH_CTL, 
> > _DPB_AUX_CH_CTL)
> > -#define DP_AUX_CH_DATA(port, i)_MMIO(_PORT(port, _DPA_AUX_CH_DATA1, 
> > _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > +#define DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, 
> > _DPB_AUX_CH_CTL)
> > +#define DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, 
> > _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >  
> >  #define   DP_AUX_CH_CTL_SEND_BUSY  (1 << 31)
> >  #define   DP_AUX_CH_CTL_DONE   (1 << 30)
> > @@ -7875,8 +7875,8 @@ enum {
> >  #define _PCH_DPD_AUX_CH_DATA4  0xe4320
> >  #define _PCH_DPD_AUX_CH_DATA5  0xe4324
> >  
> > -#define PCH_DP_AUX_CH_CTL(port)_MMIO_PORT((port) - PORT_B, 
> > _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> > -#define PCH_DP_AUX_CH_DATA(port, i)_MMIO(_PORT((port) - PORT_B, 
> > _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > +#define PCH_DP_AUX_CH_CTL(aux_ch)  _MMIO_PORT((aux_ch) - AUX_CH_B, 
> > _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> > +#define PCH_DP_AUX_CH_DATA(aux_ch, i)  _MMIO(_PORT((aux_ch) - 
> > AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 
> > registers */
> >  
> >  /* CPT */
> >  #define  PORT_TRANS_A_SEL_CPT  0
> > diff --git a/drivers/gpu/drm/i915/intel_display.h 
> > b/drivers/gpu/drm/i915/intel_display.h
> > index c4042e342f50..f5733a2576e7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -139,6 +139,17 @@ enum dpio_phy {
> >  
> >  #define I915_NUM_PHYS_VLV 2
> >  
> > +enum aux_ch {
> > +   AUX_CH_A,
> > +   AUX_CH_B,
> > +   AUX_CH_C,
> > +   AUX_CH_D,
> > +   _AUX_CH_E, /* does not exist */
> > +   AUX_CH_F,
> > +};
> > +
> > +#define aux_ch_name(a) ((a) + 'A')
> > +
> >  enum intel_display_power_domain {
> > POWER_DOMAIN_PIPE_A,
> > POWER_DOMAIN_PIPE_B,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index f20b25f98e5a..eeb8a026fd08 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1331,171 +1331,194 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, 
> > struct drm_dp_aux_msg *msg)
> > return ret;
> >  }
> >  
> > -static enum port intel_aux_port(struct drm_i915_private *dev_priv,
> > -   enum port port)
> > +static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
> >  {
> > +   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +   enum port port = encoder->port;
> > const struct ddi_vbt_port_info *info =
> > _priv->vbt.ddi_port_info[port];
> > -   enum port aux_port;
> > +   enum aux_ch aux_ch;
> >  
> > if (!info->alternate_aux_channel) {
> > +   aux_ch = (enum aux_ch) port;
> > +
> > DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
> > - port_name(port), port_name(port));
> > -   return port;
> > + aux_ch_name(aux_ch), port_name(port));
> 

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

[Chris Wilson]

Quoting Zhenyu Wang (2018-02-22 03:13:19)
> On 2018.02.20 20:15:22 +, Chris Wilson wrote:
> > Quoting Zhenyu Wang (2018-02-14 05:28:27)
> > > 
> > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
> > > chinese new year, team would take one week off at least, so like to
> > > send this out before vacation. This has one to fix GTT mmio 8b access
> > > from guest and two simple ones for mmio switch and typo fix. And sorry
> > > that patchwork link is still not there yet, using dim to pull should
> > > be ok but might need direct push to skip dim push check for now.
> > 
> > There are still quite a few sore points that would be nice to fix:
> > 
> > drivers/gpu/drm/i915/gvt/handlers.c:203 sanitize_fence_mmio_access()
> > error: 'vgpu' dereferencing possible ERR_PTR()
> > drivers/gpu/drm/i915/gvt/handlers.c:323 gdrst_mmio_write() warn:
> > inconsistent indenting
> > drivers/gpu/drm/i915/gvt/handlers.c:871 dp_aux_ch_ctl_mmio_write()
> > error: buffer overflow 'display->ports' 5 <= 5
> > drivers/gpu/drm/i915/gvt/handlers.c:1392 hws_pga_write() error: 'vgpu'
> > dereferencing possible ERR_PTR()
> > drivers/gpu/drm/i915/gvt/handlers.c:1402 hws_pga_write() error: 'vgpu'
> > dereferencing possible ERR_PTR()
> > 
> > + Lots of kerneldoc errors that should be tidied up.
> 
> Chris, thanks for this, we will double check those smatch warnings.
> 
> Strange thing is that 0day kernel does run kinds of static checker
> against our tree, but seems reports are sent to Dan instead of our
> developers...

Dan Carpenter is the developer behind smatch, and he runs and sends
reports himself. It's a reasonable tool for its signal:noise ratio.
-Chris
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Nuke aux regs from intel_dp

[Pandiyan, Dhinakaran]

On Tue, 2018-02-20 at 21:00 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Just store function pointers that give us the correct register offsets
> instead of storing the register offsets themselves. Slightly less
> efficient perhaps but saves a few bytes and better matches how we do
> things elsewhere.
> 
> v2: Keep a local array of data registers (Chris)
> 
Intriguing, why bother storing register offsets in one go if it's okay
to make these additional function calls for every aux transaction.

What am I missing here?



> Reviewed-by: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 85 
> 
>  drivers/gpu/drm/i915/intel_drv.h |  5 ++-
>  2 files changed, 45 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index eeb8a026fd08..b0c273b5b2a9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -936,7 +936,7 @@ static uint32_t
>  intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
>  {
>   struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> + i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
>   uint32_t status;
>   bool done;
>  
> @@ -1089,7 +1089,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv =
>   to_i915(intel_dig_port->base.base.dev);
> - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> + i915_reg_t ch_ctl, ch_data[5];
>   uint32_t aux_clock_divider;
>   int i, ret, recv_bytes;
>   uint32_t status;
> @@ -1097,6 +1097,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>   bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
>   bool vdd;
>  
> + ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> + for (i = 0; i < ARRAY_SIZE(ch_data); i++)
> +  ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
> +
>   pps_lock(intel_dp);
>  
>   /*
> @@ -1154,7 +1158,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>   for (try = 0; try < 5; try++) {
>   /* Load the send data into the aux channel data 
> registers */
>   for (i = 0; i < send_bytes; i += 4)
> - I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
> + I915_WRITE(ch_data[i >> 2],
>  intel_dp_pack_aux(send + i,
>send_bytes - i));
>  
> @@ -1239,7 +1243,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>   recv_bytes = recv_size;
>  
>   for (i = 0; i < recv_bytes; i += 4)
> - intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 
> 2]),
> + intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
>   recv + i, recv_bytes - i);
>  
>   ret = recv_bytes;
> @@ -1396,9 +1400,11 @@ intel_aux_power_domain(struct intel_dp *intel_dp)
>   }
>  }
>  
> -static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -   enum aux_ch aux_ch)
> +static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
>  {
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> + enum aux_ch aux_ch = intel_dp->aux_ch;
> +
>   switch (aux_ch) {
>   case AUX_CH_B:
>   case AUX_CH_C:
> @@ -1410,9 +1416,11 @@ static i915_reg_t g4x_aux_ctl_reg(struct 
> drm_i915_private *dev_priv,
>   }
>  }
>  
> -static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
> -enum aux_ch aux_ch, int index)
> +static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
>  {
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> + enum aux_ch aux_ch = intel_dp->aux_ch;
> +
>   switch (aux_ch) {
>   case AUX_CH_B:
>   case AUX_CH_C:
> @@ -1424,9 +1432,11 @@ static i915_reg_t g4x_aux_data_reg(struct 
> drm_i915_private *dev_priv,
>   }
>  }
>  
> -static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -   enum aux_ch aux_ch)
> +static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
>  {
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> + enum aux_ch aux_ch = intel_dp->aux_ch;
> +
>   switch (aux_ch) {
>   case AUX_CH_A:
>   return DP_AUX_CH_CTL(aux_ch);
> @@ -1440,9 +1450,11 @@ static i915_reg_t ilk_aux_ctl_reg(struct 
> drm_i915_private *dev_priv,
>   }
>  }
>  
> -static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
> -enum 

Re: [Intel-gfx] drm-intel-fixes issues on CI

[Chris Wilson]

Quoting Rodrigo Vivi (2018-02-22 04:26:29)
> Hi guys, 
> 
> looking at gem_eio_flight* for gen9 on:
> https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
> 
> run 246 x 247
> pure v4.16-rc2 x our fixes
> 
> would any of 2 patches explain:
> 
> drm/i915: Clear the in-use marker on execbuf failure
> drm/i915: Fix rsvd2 mask when out-fence is returned
> 
> Anything else we might be missing?

The test got harsher and seems to be finding a new old bug.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats 
(rev2)
URL   : https://patchwork.freedesktop.org/series/38717/
State : success

== Summary ==

Series 38717v2 series starting with [1/2] drm/i915/guc: Support engine busy 
stats
https://patchwork.freedesktop.org/api/1.0/series/38717/revisions/2/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:378s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:286s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:506s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:383s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:441s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:409s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:453s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:488s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:586s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:423s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:529s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:391s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8118/fi-bxt-dsi/run0.log

42016703e66b7b572d4ab651946b715cdbff3050 drm-tip: 2018y-02m-21d-21h-26m-53s UTC 
integration manifest
bffcb2b6b6b0 drm/i915: GuC test run
690dfe054013 drm/i915/guc: Support engine busy stats

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8118/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats 
(rev2)
URL   : https://patchwork.freedesktop.org/series/38717/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
690dfe054013 drm/i915/guc: Support engine busy stats
-:33: WARNING: line over 80 characters
#33: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:725:
+   
intel_engine_context_in(last->engine);

total: 0 errors, 1 warnings, 0 checks, 44 lines checked
bffcb2b6b6b0 drm/i915: GuC test run

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Re: [Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

Looks good to me. Few cosmetic changes suggested below. With those 
addressed:

Reviewed-by: Sagar Arun Kamble 

On 2/22/2018 5:05 AM, Oscar Mateo wrote:

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.

Unfortunately, we have a Catch-22 situation going on: we need the blitter
forcewake to read the register with the fuse info, but we cannot initialize
the forcewake domains without knowin about the engines present in the HW.

*knowing

We workaround this problem by pruning the forcewake domains after reading
the fuse information.

This line can be re-framed like:
"We workaround this problem by allowing initialization of all forcewake 
domains and then pruning the fused off forcewake domains

based on fuse info which can be read acquiring blitter forcewake"


Bspec: 20680

v2: We were shifting incorrectly for vebox disable (Vinay)

v3: Assert mmio is ready and warn if we have attempted to initialize
 forcewake for fused-off engines (Paulo)

v4:
   - Use INTEL_GEN in new code (Tvrtko)
   - Shorter local variable (Tvrtko, Michal)
   - Keep "if (!...) continue" style (Tvrtko)
   - No unnecessary BUG_ON (Tvrtko)
   - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
   - Use I915_READ_FW (Michal)
   - Use I915_MAX_VCS/VECS macros (Michal)

v5: Rebased by Rodrigo fixing conflicts on top of:
 commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

v6: Fix v5. Remove info->num_rings. (by Oscar)

v7: Rebase (Rodrigo).

v8:
   - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
   - Make vdbox_disable & vebox_disable local variables (Chris)

v9:
   - Move function declaration to intel_device_info.h (Michal)
   - Missing indent in bit fields definitions (Michal)
   - When RC6 is enabled by BIOS, the fuse register cannot be read until
 the blitter powerwell is awake. Shuffle where the fuse is read, prune
 the forcewake domains after the fact and change the commit message
 accordingly (Vinay, Sagar, Chris).

Cc: Paulo Zanoni 
Cc: Vinay Belgaumkar 
Cc: Tvrtko Ursulin 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/i915_drv.c  |  4 +++
  drivers/gpu/drm/i915/i915_reg.h  |  5 +++
  drivers/gpu/drm/i915/intel_device_info.c | 47 +++
  drivers/gpu/drm/i915/intel_device_info.h |  1 +
  drivers/gpu/drm/i915/intel_uncore.c  | 55 
  drivers/gpu/drm/i915/intel_uncore.h  |  1 +
  6 files changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d09f8e6..2269b56 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1031,6 +1031,10 @@ static int i915_driver_init_mmio(struct drm_i915_private 
*dev_priv)
  
  	intel_uncore_init(dev_priv);
  
+	intel_device_info_init_mmio(dev_priv);

+
+   intel_uncore_prune(dev_priv);
+
intel_uc_init_mmio(dev_priv);
  
  	ret = intel_engines_init_mmio(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 784d79c..e6a0d84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2854,6 +2854,11 @@ enum i915_power_well_id {
  #define GEN10_EU_DISABLE3 _MMIO(0x9140)
  #define   GEN10_EU_DIS_SS_MASK0xff
  
+#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)

+#define   GEN11_GT_VDBOX_DISABLE_MASK  0xff
+#define   GEN11_GT_VEBOX_DISABLE_SHIFT 16
+#define   GEN11_GT_VEBOX_DISABLE_MASK  (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
  #define GEN6_BSD_SLEEP_PSMI_CONTROL   _MMIO(0x12050)
  #define   GEN6_BSD_SLEEP_MSG_DISABLE  (1 << 0)
  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 9352f34..70ea654 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -595,3 +595,50 @@ void intel_driver_caps_print(const struct 
intel_driver_caps *caps,
  {
drm_printf(p, "scheduler: %x\n", caps->scheduler);
  }
+
+/*
+ * Determine which engines are fused off in our particular hardware. Since the
+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
+ * this point (but later we need to prune the forcewake domains for engines 
that
+ * are indeed fused off).
+ */
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

[Pandiyan, Dhinakaran]

On Tue, 2018-02-20 at 19:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Since we no longer have a 1:1 correspondence between ports and AUX
> channels, let's give AUX channels their own enum. Makes it easier
> to tell the apples from the oranges, and we get rid of the
> port E AUX power domain FIXME since we now derive the power domain
> from the actual AUX CH.

Neat, this solves the problem I noticed while adding cnl aux io power
domain. Thanks.

> 
> v2: Rebase due to AUX F
> 
> Signed-off-by: Ville Syrjälä 
> ---
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: GuC test run (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: GuC test run (rev4)
URL   : https://patchwork.freedesktop.org/series/38615/
State : success

== Summary ==

Series 38615v4 drm/i915: GuC test run
https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/4/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bxt-dsi) fdo#103927

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:375s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:285s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:384s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:452s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:410s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:449s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:490s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:587s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:425s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:503s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:406s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s

42016703e66b7b572d4ab651946b715cdbff3050 drm-tip: 2018y-02m-21d-21h-26m-53s UTC 
integration manifest
fb0c41291286 drm/i915: GuC test run

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8117/issues.html
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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Place context in/out hooks into the GuC backend, when contexts are
assigned to ports, and removed from them, in order to be able to
provide engine busy stats in GuC mode.

Signed-off-by: Tvrtko Ursulin 
Testcase: igt/perf_pmu/busy-accuracy-*-*
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 649113c7a3c2..8e99f8fd6da2 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -673,6 +673,7 @@ static void guc_dequeue(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = execlists->port;
struct i915_request *last = NULL;
+   struct i915_gem_context *last_ctx = NULL;
const struct execlist_port * const last_port =
>port[execlists->port_mask];
bool submit = false;
@@ -718,8 +719,13 @@ static void guc_dequeue(struct intel_engine_cs *engine)
goto done;
}
 
-   if (submit)
+   if (submit) {
port_assign(port, last);
+   if (last->ctx != last_ctx) {
+   
intel_engine_context_in(last->engine);
+   last_ctx = last->ctx;
+   }
+   }
port++;
}
 
@@ -741,6 +747,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
execlists->first = rb;
if (submit) {
port_assign(port, last);
+   if (last->ctx != last_ctx)
+   intel_engine_context_in(last->engine);
execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
guc_submit(engine);
}
@@ -763,6 +771,7 @@ static void guc_submission_tasklet(unsigned long data)
 
rq = port_request([0]);
while (rq && i915_request_completed(rq)) {
+   intel_engine_context_out(rq->engine);
trace_i915_request_out(rq);
i915_request_put(rq);
 
@@ -1192,8 +1201,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
execlists->tasklet.func = guc_submission_tasklet;
engine->park = guc_submission_park;
engine->unpark = guc_submission_unpark;
-
-   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
}
 
return 0;
-- 
2.14.1

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Re: [Intel-gfx] [PATCH 01/43] drm: hdcp2.2 authentication msg definitions

[Ramalingam C]

On Wednesday 14 February 2018 08:45 PM, Winkler, Tomas wrote:

This patch defines the hdcp2.2 protocol messages for the
HDCP2.2 authentication.

Signed-off-by: Ramalingam C 
---
  include/drm/drm_hdcp.h | 226
+
  1 file changed, 226 insertions(+)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
562fa7df2637..9661c700cebb 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -38,4 +38,230 @@
  #define DRM_HDCP_DDC_BSTATUS  0x41
  #define DRM_HDCP_DDC_KSV_FIFO 0x43

+#define DRM_HDCP_1_4_SRM_ID0x8
+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE   3
+#define DRM_HDCP_1_4_DCP_SIG_SIZE  40
+
+struct cp_srm_header {
+   struct {
+   uint8_t reserved_hi:4;
+   uint8_t srm_id:4;
+   uint8_t reserved_lo;
+   } spec_indicator;

Do you really want to work with bit fields?  I mean in all the all structures.

I will rework on replacing all bitfields.

+   uint16_t srm_version;

Shouldn't be it __le16?

And all multi-byte variables needs to be revisited for endianness.

+   uint8_t srm_gen_no;
+} __packed;
+
+/**
+ * Protocol message definition for HDCP2.2 specification  */
+
+#define HDCP_STREAM_TYPE0  0x00
+#define HDCP_STREAM_TYPE1  0x01
+
+/* HDCP2.2 Msg IDs */
+#define NULL_MSG   1


We need some HDCP2_ prefix this is in kernel global space and
some of the constants have very generic name that can collide.

Sure I will add the prefix, to avoid possible conflicts. Thanks.
--Ram



+#define AKE_INIT   2
+#define AKE_SEND_CERT  3




+#define AKE_NO_STORED_KM   4
+#define AKE_STORED_KM  5
+#define AKE_SEND_HPRIME7
+#define AKE_SEND_PARING_INFO   8
+#define LC_INIT9
+#define LC_SEND_LPRIME 10
+#define SKE_SEND_EKS   11
+#define REP_SEND_RECVID_LIST   12
+#define REP_SEND_ACK   15
+#define REP_STREAM_MANAGE  16
+#define REP_STREAM_READY   17
+#define ERRATA_DP_STREAM_TYPE  50
+
+#define HDCP_RTX_LEN   8
+#define HDCP_RRX_LEN   8
+#define RECEIVER_ID_SIZE   5
+
+#define K_PUB_RX_MOD_N_SIZE128
+#define K_PUB_RX_EXP_E_SIZE3
+#define K_PUB_RX_SIZE
(K_PUB_RX_MOD_N_SIZE + \
+K_PUB_RX_EXP_E_SIZE)
+
+#define DCP_LLC_SIGNATURE_SIZE 384
+
+#define HDCP_E_KPUB_KM_LEN 128
+#define HDCP_E_KH_KM_M_LEN (16 + 16)
+#define HDCP_H_PRIME_LEN   32
+#define HDCP_E_KH_KM_LEN   16
+#define HDCP_RN_LEN8
+#define HDCP_L_PRIME_LEN   32
+#define HDCP_E_DKEY_KS_LEN 16
+#define HDCP_RIV_LEN   8
+#define HDCP_SEQ_NUM_LEN   3
+#define HDCP_LPRIME_HALF_SIZE  (HDCP_L_PRIME_LEN
/ 2)
+#define HDCP_RECEIVER_ID_LEN   5
+#define HDCP_MAX_DEVICE_COUNT  31
+#define HDCP_RECEIVER_IDS_MAX_LEN
(HDCP_RECEIVER_ID_LEN * \
+HDCP_MAX_DEVICE_COUNT)
+
+/**
+ * TODO: This has to be changed for DP MST, as multiple stream on
+ * same port is possible.
+ * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ */
+#define MAX_CONTENT_STREAMS_CNT1
+
+#define HDCP_MPRIME_LEN32
+
+struct hdcp2_cert_rx {
+   uint8_t receiver_id[RECEIVER_ID_SIZE];
+   uint8_t kpub_rx[K_PUB_RX_SIZE];
+   uint8_t reserved1   :4;
+
+   /* As per HDMI & DP HDCP Spec, must be 0x0 or 0x1 */
+   uint8_t protocol_descriptor :4;
+
+   /* As per HDMI & DP HDCP Spec, must be 0x */
+   uint8_t reserved2;
+   uint8_t dcp_signature[DCP_LLC_SIGNATURE_SIZE];
+} __packed;
+
+/**
+ * The RxCaps field specified in the HDCP HDMI, DP specs
+ * This field is big endian as specified in the errata.
+ */
+union hdcp2_rx_caps {
+   struct  {
+   uint8_t version;
+   uint8_t receiver_capability_mask_hi;
+   uint8_t repeater:1;
+
+   /* Rsvd in HDMI. Applicable in DP alone */
+   uint8_t hdcp_capable:1;
+   uint8_t receiver_capability_mask_low:6;
+   } fields;
+   uint8_t rx_caps_value[3];
+} __packed;
+
+/**
+ * RxInfo fields Contains various topology information for the
+ * repeater authentication flows
+ */
+union hdcp2_rx_info {
+   

Re: [Intel-gfx] [PATCH 01/43] drm: hdcp2.2 authentication msg definitions

[Ramalingam C]

On Thursday 15 February 2018 01:10 AM, Jani Nikula wrote:

On Wed, 14 Feb 2018, "Winkler, Tomas"  wrote:

This patch defines the hdcp2.2 protocol messages for the
HDCP2.2 authentication.

Signed-off-by: Ramalingam C 
---
  include/drm/drm_hdcp.h | 226
+
  1 file changed, 226 insertions(+)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
562fa7df2637..9661c700cebb 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -38,4 +38,230 @@
  #define DRM_HDCP_DDC_BSTATUS  0x41
  #define DRM_HDCP_DDC_KSV_FIFO 0x43

+#define DRM_HDCP_1_4_SRM_ID0x8
+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE   3
+#define DRM_HDCP_1_4_DCP_SIG_SIZE  40
+
+struct cp_srm_header {
+   struct {
+   uint8_t reserved_hi:4;
+   uint8_t srm_id:4;
+   uint8_t reserved_lo;
+   } spec_indicator;

Do you really want to work with bit fields?  I mean in all the all structures.

We *can't* use bitfields in drm core for (un)marshalling. They depend on
endianness. (Thanks to folks on #dri-devel for confirming.) We use them
at places in i915 where we can be pretty sure about running on
little-endian machines, but that doesn't hold here.

Packed structs are fine otherwise though, just not bitfields.

Thanks Jani. I will rework on that.

--Ram


BR,
Jani.



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Re: [Intel-gfx] [PATCH 04/43] mei: me: add gemini lake devices ids

[Ramalingam C]

On Wednesday 14 February 2018 08:15 PM, Winkler, Tomas wrote:

This one is already upstream

Thanks for pointing that out. I will drop this patch.

--Ram


Thanks
Tomas



From: Tomas Winkler 

Signed-off-by: Tomas Winkler 
---
  drivers/misc/mei/hw-me-regs.h | 2 ++
  drivers/misc/mei/pci-me.c | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 0baf530d..5a36ca403a24 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -132,6 +132,8 @@
  #define MEI_DEV_ID_KBP0xA2BA  /* Kaby Point */
  #define MEI_DEV_ID_KBP_2  0xA2BB  /* Kaby Point 2 */

+#define MEI_DEV_ID_GLK0x319A  /* Gemini Lake */
+
  /*
   * MEI HW Section
   */
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c index
4a0ccda4d04b..fe44ac2a9b2d 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -98,6 +98,8 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},

+   {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
+
/* required last entry */
{0, }
  };
--
2.7.4


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[Intel-gfx] drm-intel-fixes issues on CI

[Rodrigo Vivi]

Hi guys, 

looking at gem_eio_flight* for gen9 on:
https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html

run 246 x 247
pure v4.16-rc2 x our fixes

would any of 2 patches explain:

drm/i915: Clear the in-use marker on execbuf failure
drm/i915: Fix rsvd2 mask when out-fence is returned

Anything else we might be missing?

Thanks,
Rodrigo.
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[Intel-gfx] ✗ Fi.CI.BAT: warning for ICL PLLs, DP/HDMI and misc display

[Patchwork]

== Series Details ==

Series: ICL PLLs, DP/HDMI and misc display
URL   : https://patchwork.freedesktop.org/series/38737/
State : warning

== Summary ==

Series 38737v1 ICL PLLs, DP/HDMI and misc display
https://patchwork.freedesktop.org/api/1.0/series/38737/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-edid-read:
pass   -> FAIL   (fi-kbl-7500u) fdo#102505
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bxt-dsi) fdo#103927

fdo#102575 
fdo#102505 
fdo#103927 

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:375s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:490s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:287s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:479s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:385s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:408s
fi-kbl-7500u total:288  pass:261  dwarn:2   dfail:0   fail:1   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:594s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:504s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:523s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:406s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s

42016703e66b7b572d4ab651946b715cdbff3050 drm-tip: 2018y-02m-21d-21h-26m-53s UTC 
integration manifest
b154a6a9c427 drm/i915/icl: Fix the DP Max Voltage for ICL
78a0633561af drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes
f39480af7607 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
137ca2ea6e11 drm/i915/icl: Calculate link clock using the new registers
390f90f94037 drm/i915/icl: Added 5k source scaling support for Gen11 platform
564b8c7a2810 drm/i915/icl: HPD pin for port F
a996d61691a8 drm/i915/icl: Implement voltage swing programming sequence for MG 
PHY DDI
87682ffe4e06 drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
95188dc60dea drm/i915/icl: Add register defs for voltage swing sequences for MG 
PHY DDI
f68122f9a0b6 drm/i915/icl: Implement voltage swing programming sequence for 
Combo PHY DDI
7767df908beb drm/i915/icl: Add Combo PHY DDI Buffer translation tables for 
Icelake.
96d7a0b68153 drm/i915/icl: Add register definitions for Combo PHY vswing 
sequences.
756e2fb14b68 drm/i915/icl: compute the MG PLL registers
083e316a0ea3 drm/i915/icl: compute the combo PHY (DPLL) DP registers
394ce70a7d01 drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
0212a3eaf876 drm/i915/icl: add basic support for the ICL clocks
176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8116/issues.html
___

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display

[Patchwork]

== Series Details ==

Series: ICL PLLs, DP/HDMI and misc display
URL   : https://patchwork.freedesktop.org/series/38737/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers
-:87: CHECK: Prefer using the BIT macro
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:8982:
+#define   MG_PLL_DIV0_FRACNEN_H(1 << 30)

-:99: CHECK: Prefer using the BIT macro
#99: FILE: drivers/gpu/drm/i915/i915_reg.h:8994:
+#define   MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)

-:113: CHECK: Prefer using the BIT macro
#113: FILE: drivers/gpu/drm/i915/i915_reg.h:9008:
+#define   MG_PLL_LF_AFCCNTSEL_512  (1 << 20)

-:124: CHECK: Prefer using the BIT macro
#124: FILE: drivers/gpu/drm/i915/i915_reg.h:9019:
+#define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32(1 << 18)

-:125: CHECK: Prefer using the BIT macro
#125: FILE: drivers/gpu/drm/i915/i915_reg.h:9020:
+#define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32   (1 << 16)

-:127: CHECK: Prefer using the BIT macro
#127: FILE: drivers/gpu/drm/i915/i915_reg.h:9022:
+#define   MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)

-:128: CHECK: Prefer using the BIT macro
#128: FILE: drivers/gpu/drm/i915/i915_reg.h:9023:
+#define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN  (1 << 8)

-:138: CHECK: Prefer using the BIT macro
#138: FILE: drivers/gpu/drm/i915/i915_reg.h:9033:
+#define   MG_PLL_SSC_EN(1 << 28)

-:142: CHECK: Prefer using the BIT macro
#142: FILE: drivers/gpu/drm/i915/i915_reg.h:9037:
+#define   MG_PLL_SSC_FILEN (1 << 9)

-:154: CHECK: Prefer using the BIT macro
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:9049:
+#define   MG_PLL_BIAS_BIASCAL_EN   (1 << 15)

-:165: CHECK: Prefer using the BIT macro
#165: FILE: drivers/gpu/drm/i915/i915_reg.h:9060:
+#define   MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)

-:167: CHECK: Prefer using the BIT macro
#167: FILE: drivers/gpu/drm/i915/i915_reg.h:9062:
+#define   MG_PLL_TDC_COLDST_COLDSTART  (1 << 16)

-:168: CHECK: Prefer using the BIT macro
#168: FILE: drivers/gpu/drm/i915/i915_reg.h:9063:
+#define   MG_PLL_TDC_TDCCOVCCORR_EN(1 << 2)

-:178: CHECK: Prefer using the BIT macro
#178: FILE: drivers/gpu/drm/i915/i915_reg.h:9073:
+#define  DPLL_CFGCR0_SSC_ENABLE_ICL(1 << 25)

total: 0 errors, 0 warnings, 14 checks, 179 lines checked
0212a3eaf876 drm/i915/icl: add basic support for the ICL clocks
-:105: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#105: FILE: drivers/gpu/drm/i915/intel_ddi.c:2151:
+   uint32_t val;

-:291: CHECK: multiple assignments should be avoided
#291: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2436:
+   min = max = icl_port_to_mg_pll_id(port);

-:339: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#339: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2484:
+   uint32_t val;

-:421: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#421: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2566:
+   uint32_t val;

-:472: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#472: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2617:
+   uint32_t val;

-:509: WARNING: quoted string split across lines
#509: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2654:
+   DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
+ "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "

-:510: WARNING: quoted string split across lines
#510: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2655:
+ "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
+ "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "

-:511: WARNING: quoted string split across lines
#511: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2656:
+ "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
+ "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "

-:512: WARNING: quoted string split across lines
#512: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2657:
+ "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
+ "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "

-:513: WARNING: quoted string split across lines
#513: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2658:
+ "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
+ "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",

-:572: CHECK: Please don't use multiple blank lines
#572: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:107:
+
+

-:609: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#609: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:169:
+   uint32_t mg_refclkin_ctl;

-:610: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#610: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:170:
+   uint32_t mg_clktop2_coreclkctl1;

-:611: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#611: FILE: 

[Intel-gfx] [PATCH 16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes

[Paulo Zanoni]

And the DDI_A_4_LANES bit from DDI_BUF_CTL doesn't even exist anymore.

This commit prevents us from auto picking a maximum of 2 lanes, which
makes some panels useless by rejecting their only native mode.

Thanks to Manasi for the help debugging this one.

v2: Typo fix (Rodrigo).

Cc: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 21 +
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c1f1966d471c..ad82ef91263e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3300,6 +3300,13 @@ static bool intel_ddi_a_force_4_lanes(struct 
intel_digital_port *dport)
 {
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
 
+   /*
+* Starting on gen 11, all ports support 4 lanes, don't print messages
+* related to this.
+*/
+   if (INTEL_GEN(dev_priv) >= 11)
+   return false;
+
if (dport->base.port != PORT_A)
return false;
 
@@ -3332,7 +3339,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
bool init_hdmi, init_dp, init_lspcon = false;
int max_lanes;
 
-   if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   max_lanes = 4;
+   } else if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
switch (port) {
case PORT_A:
max_lanes = 4;
@@ -3403,9 +3412,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
intel_encoder->suspend = intel_dp_encoder_suspend;
intel_encoder->get_power_domains = intel_ddi_get_power_domains;
 
-   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
- (DDI_BUF_PORT_REVERSAL |
-  DDI_A_4_LANES);
+   if (INTEL_GEN(dev_priv) >= 11)
+   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
+ DDI_BUF_PORT_REVERSAL;
+   else
+   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
+ (DDI_BUF_PORT_REVERSAL |
+  DDI_A_4_LANES);
 
switch (port) {
case PORT_A:
-- 
2.14.3

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[Intel-gfx] [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL

[Paulo Zanoni]

From: Manasi Navare 

On clock recovery this function is called to find out
the max voltage swing level that we could go.

However gen 9 functions use the old buffer translation tables
to figure that out. ICL uses different set of tables for eDP
and DP for both Combo and MG PHY ports. This patch adds the hook
for ICL for getting this information from appropriate buf trans tables.

v5 (from Paulo):
* New rebase after changes to earlier patches.
v4:
* Rebase.
v3:
* Follow the coding conventions here
(https://cgit.freedesktop.org/drm-intel/tree/Documentation/process/codin
g-style.rst#n191) (Paulo)
v2:
* Rebase after patch that adds voltage check inside buf trans
function (Rodrigo)

Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad82ef91263e..fbdd2340c8aa 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2085,7 +2085,13 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
enum port port = encoder->port;
int n_entries;
 
-   if (IS_CANNONLAKE(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   if (port == PORT_A || port == PORT_B)
+   icl_get_combo_buf_trans(dev_priv, port, encoder->type,
+   _entries);
+   else
+   n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+   } else if (IS_CANNONLAKE(dev_priv)) {
if (encoder->type == INTEL_OUTPUT_EDP)
cnl_get_buf_trans_edp(dev_priv, _entries);
else
-- 
2.14.3

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[Intel-gfx] [PATCH 15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL

[Paulo Zanoni]

From: James Ausmus 

These fields have been deprecated and moved in ICL+. Stop setting the
bits.

They have moved to GAMMA_MODE and CSC_MODE, respectively. This patch
is just to stop incorrectly setting bits in PLANE_COLOR_CTL while
we're waiting for the new replacement functionality to be done.

v2: Drop useless comment, and change !(GEN >= 11) to (GEN < 11). (Ville)

v3: No changes

Cc: Paulo Zanoni 
Cc: Ville Syrjälä 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 ++--
 drivers/gpu/drm/i915/intel_display.c | 8 ++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a389d4030b7f..fc13d9b63c74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6611,8 +6611,8 @@ enum {
 #define _PLANE_COLOR_CTL_1_A   0x701CC /* GLK+ */
 #define _PLANE_COLOR_CTL_2_A   0x702CC /* GLK+ */
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
-#define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
-#define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
+#define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
+#define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23) /* Pre-ICL */
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index aa5c04788041..8ca828c446a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3585,11 +3585,15 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
 {
+   struct drm_i915_private *dev_priv =
+   to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
u32 plane_color_ctl = 0;
 
-   plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
-   plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+   if (INTEL_GEN(dev_priv) < 11) {
+   plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+   plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+   }
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
 
-- 
2.14.3

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[Intel-gfx] [PATCH 05/17] drm/i915/icl: compute the MG PLL registers

[Paulo Zanoni]

This implements the "MG PLL Programming" sequence from our spec. The
biggest problem was that the spec assumes real numbers, so we had to
adjust some numbers and alculations due to the fact that the Kernel
prefers to deal with integers.

I recommend grabbing some coffee, a pen and paper before reviewing
this patch.

v2:
 - Correctly identify DP encoders after upstream change.
 - Small checkpatch issues.
 - Rebase.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 217 +-
 1 file changed, 216 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5d7bacc80688..9a2965e0b883 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2514,11 +2514,226 @@ static enum intel_dpll_id icl_port_to_mg_pll_id(enum 
port port)
return port - PORT_C + DPLL_ID_ICL_MGPLL1;
 }
 
+static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
+uint32_t *target_dco_khz,
+struct intel_dpll_hw_state *state)
+{
+   uint32_t dco_min_freq, dco_max_freq;
+   int div1_vals[] = {7, 5, 3, 2};
+   unsigned int i;
+   int div2;
+
+   dco_min_freq = is_dp ? 810 : use_ssc ? 800 : 7992000;
+   dco_max_freq = is_dp ? 810 : 1000;
+
+   for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
+   int div1 = div1_vals[i];
+
+   for (div2 = 10; div2 > 0; div2--) {
+   int dco = div1 * div2 * clock_khz * 5;
+   int a_divratio, tlinedrv, inputsel, hsdiv;
+
+   if (dco < dco_min_freq || dco > dco_max_freq)
+   continue;
+
+   if (div2 >= 2) {
+   a_divratio = is_dp ? 10 : 5;
+   tlinedrv = 2;
+   } else {
+   a_divratio = 5;
+   tlinedrv = 0;
+   }
+   inputsel = is_dp ? 0 : 1;
+
+   switch (div1) {
+   default:
+   MISSING_CASE(div1);
+   case 2:
+   hsdiv = 0;
+   break;
+   case 3:
+   hsdiv = 1;
+   break;
+   case 5:
+   hsdiv = 2;
+   break;
+   case 7:
+   hsdiv = 3;
+   break;
+   }
+
+   *target_dco_khz = dco;
+
+   state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
+
+   state->mg_clktop2_coreclkctl1 =
+   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
+
+   state->mg_clktop2_hsclkctl =
+   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
+   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
+   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
+   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
+
+   return true;
+   }
+   }
+
+   return false;
+}
+
+/*
+ * The specification for this function uses real numbers, so the math had to be
+ * adapted to integer-only calculation, that's why it looks so different.
+ */
 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
  struct intel_encoder *encoder, int clock,
  struct intel_dpll_hw_state *pll_state)
 {
-   /* TODO */
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int refclk_khz = dev_priv->cdclk.hw.ref;
+   uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
+   uint32_t iref_ndiv, iref_trim, iref_pulse_w;
+   uint32_t prop_coeff, int_coeff;
+   uint32_t tdc_targetcnt, feedfwgain;
+   uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
+   uint64_t tmp;
+   bool use_ssc = false;
+   bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
+
+   if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, _khz,
+ pll_state)) {
+   DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
+   return false;
+   }
+
+   m1div = 2;
+   m2div_int = dco_khz / (refclk_khz * m1div);
+   if (m2div_int > 255) {
+   m1div = 4;
+   m2div_int = dco_khz / (refclk_khz * m1div);
+   if (m2div_int > 255) {
+   DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
+ 

[Intel-gfx] [PATCH 00/17] ICL PLLs, DP/HDMI and misc display

[Paulo Zanoni]

Hello

Here are some more ICL patches, now with the Combo & MG PLLs, some DP/HDMI
initialization code and a few misc fixes.

Again, the R-B tags already present in some of the patches (including those form
me) were given a long time ago, so they need to be re-issued due to the
rebasing.

Thanks,
Paulo

Arkadiusz Hiler (1):
  drm/i915/icl: Calculate link clock using the new registers

Dhinakaran Pandiyan (1):
  drm/i915/icl: HPD pin for port F

James Ausmus (1):
  drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL

Manasi Navare (7):
  drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
  drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
  drm/i915/icl: Implement voltage swing programming sequence for Combo
PHY DDI
  drm/i915/icl: Add register defs for voltage swing sequences for MG PHY
DDI
  drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
  drm/i915/icl: Implement voltage swing programming sequence for MG PHY
DDI
  drm/i915/icl: Fix the DP Max Voltage for ICL

Nabendu Maiti (1):
  drm/i915/icl: Added 5k source scaling support for Gen11 platform

Paulo Zanoni (6):
  drm/i915/icl: add definitions for the ICL PLL registers
  drm/i915/icl: add basic support for the ICL clocks
  drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
  drm/i915/icl: compute the combo PHY (DPLL) DP registers
  drm/i915/icl: compute the MG PLL registers
  drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes

 drivers/gpu/drm/i915/i915_debugfs.c   |  22 ++
 drivers/gpu/drm/i915/i915_drv.h   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 313 -
 drivers/gpu/drm/i915/intel_ddi.c  | 529 +++-
 drivers/gpu/drm/i915/intel_display.c  |  33 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 642 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +++
 drivers/gpu/drm/i915/intel_drv.h  |  10 +
 drivers/gpu/drm/i915/intel_hotplug.c  |   3 +
 9 files changed, 1569 insertions(+), 25 deletions(-)

-- 
2.14.3

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[Intel-gfx] [PATCH 12/17] drm/i915/icl: HPD pin for port F

[Paulo Zanoni]

From: Dhinakaran Pandiyan 

Extend enum hpd_pin to port F so that we can start using this for ICL.

v2: Rebase.

Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_hotplug.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 92883a40bdd5..b7fb8e368762 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -261,6 +261,7 @@ enum hpd_pin {
HPD_PORT_C,
HPD_PORT_D,
HPD_PORT_E,
+   HPD_PORT_F,
HPD_NUM_PINS
 };
 
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
b/drivers/gpu/drm/i915/intel_hotplug.c
index fe28c1ea84a5..8bb9d8436486 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -100,6 +100,8 @@ enum port intel_hpd_pin_to_port(struct drm_i915_private 
*dev_priv,
if (IS_CNL_WITH_PORT_F(dev_priv))
return PORT_F;
return PORT_E;
+   case HPD_PORT_F:
+   return PORT_F;
default:
return PORT_NONE; /* no port for this pin */
}
@@ -132,6 +134,7 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private 
*dev_priv,
case PORT_F:
if (IS_CNL_WITH_PORT_F(dev_priv))
return HPD_PORT_E;
+   return HPD_PORT_F;
default:
MISSING_CASE(port);
return HPD_NONE;
-- 
2.14.3

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[Intel-gfx] [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers

[Paulo Zanoni]

From: Arkadiusz Hiler 

Start using the new registers for ICL and on.

Cc: Manasi Navare 
Cc: Rodrigo Vivi 
Reviewed-by: Paulo Zanoni 
Signed-off-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 88a6c5107975..c1f1966d471c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1371,8 +1371,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private 
*dev_priv,
uint32_t cfgcr0, cfgcr1;
uint32_t p0, p1, p2, dco_freq, ref_clock;
 
-   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
-   cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+   if (INTEL_GEN(dev_priv) >= 11) {
+   cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+   cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+   } else {
+   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+   cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+   }
 
p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
-- 
2.14.3

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[Intel-gfx] [PATCH 11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI

[Paulo Zanoni]

From: Manasi Navare 

This sequence is used to setup voltage swing before enabling MG PHY DDI
as well as for changing the voltage during DisplayPort Link training.

For ICL, there are two types of DDIs. This sequence needs to be used
for MG PHY DDI which is ports C-F.

v5 (from Paulo):
* Checkpatch.
v4 (from Paulo):
* Fix bogus error message
* Fix copy+paste bugs (missing s/TX1/TX2/ after copy+paste)
* Use the new mask names
* Stay under 80 columns
* Add some blank lines
v3:
* Clear the regs before writing (Paulo)
v2:
* Rename to MG PHY in the function def (Jani Nikula)
* Rebase on top of new revision of other patches in series

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 85 +++-
 1 file changed, 83 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 98471b5c5f70..88a6c5107975 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2364,6 +2364,88 @@ static void icl_combo_phy_ddi_vswing_sequence(struct 
intel_encoder *encoder, u32
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
 }
 
+static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+  u32 level)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
+   u32 n_entries, val;
+   int ln;
+
+   /*
+* Values are listed in voltage swing programming tables.
+* Same values for all voltage levels and port types.
+*/
+   n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+   ddi_translations = icl_mg_phy_ddi_translations;
+   /* The table does not have values for level 3 and level 9. */
+   if (level >= n_entries || level == 3 || level == 9) {
+   DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d 
instead.",
+ level, n_entries - 2);
+   level = n_entries - 2;
+   }
+
+   /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
+   for (ln = 0; ln < 2; ln++) {
+   val = I915_READ(ICL_PORT_MG_TX1_LINK_PARAMS(port, ln));
+   val &= ~CRI_USE_FS32;
+   I915_WRITE(ICL_PORT_MG_TX1_LINK_PARAMS(port, ln), val);
+
+   val = I915_READ(ICL_PORT_MG_TX2_LINK_PARAMS(port, ln));
+   val &= ~CRI_USE_FS32;
+   I915_WRITE(ICL_PORT_MG_TX2_LINK_PARAMS(port, ln), val);
+   }
+
+   /* Program MG_TX_SWINGCTRL with values from vswing table */
+   for (ln = 0; ln < 2; ln++) {
+   val = I915_READ(ICL_PORT_MG_TX1_SWINGCTRL(port, ln));
+   val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
+   val |= CRI_TXDEEMPH_OVERRIDE_17_12(
+   ddi_translations[level].cri_txdeemph_override_17_12);
+   I915_WRITE(ICL_PORT_MG_TX1_SWINGCTRL(port, ln), val);
+
+   val = I915_READ(ICL_PORT_MG_TX2_SWINGCTRL(port, ln));
+   val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
+   val |= CRI_TXDEEMPH_OVERRIDE_17_12(
+   ddi_translations[level].cri_txdeemph_override_17_12);
+   I915_WRITE(ICL_PORT_MG_TX2_SWINGCTRL(port, ln), val);
+   }
+
+   /* Program MG_TX_DRVCTRL with values from vswing table */
+   for (ln = 0; ln < 2; ln++) {
+   val = I915_READ(ICL_PORT_MG_TX1_DRVCTRL(port, ln));
+   val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
+   val |= CRI_TXDEEMPH_OVERRIDE_5_0(
+   ddi_translations[level].cri_txdeemph_override_5_0) |
+  CRI_TXDEEMPH_OVERRIDE_11_6(
+   ddi_translations[level].cri_txdeemph_override_11_6) |
+  CRI_TXDEEMPH_OVERRIDE_EN;
+   I915_WRITE(ICL_PORT_MG_TX1_DRVCTRL(port, ln), val);
+
+   val = I915_READ(ICL_PORT_MG_TX2_DRVCTRL(port, ln));
+   val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
+   val |= CRI_TXDEEMPH_OVERRIDE_5_0(
+   ddi_translations[level].cri_txdeemph_override_5_0) |
+  CRI_TXDEEMPH_OVERRIDE_11_6(
+   ddi_translations[level].cri_txdeemph_override_11_6) |
+ CRI_TXDEEMPH_OVERRIDE_EN;
+   I915_WRITE(ICL_PORT_MG_TX2_DRVCTRL(port, ln), val);
+   }
+   /* Program MG_TX_PISO_READLOAD with values from vswing table */
+   for (ln = 0; ln < 2; ln++) {
+   val = I915_READ(ICL_PORT_MG_TX1_PISO_READLOAD(port, ln));
+   val |= 

[Intel-gfx] [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform

[Paulo Zanoni]

From: Nabendu Maiti 

Gen11 supports upto 5k source scaling

v2: Re-factoring of code as per review
v3: Corrected max Vertical size and indentation
v4: Added max Vertical dst size in same patch

Signed-off-by: Nabendu Maiti 
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++
 drivers/gpu/drm/i915/intel_drv.h |  4 
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index bc4131a36c10..aa5c04788041 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4735,10 +4735,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 
/* range checks */
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
-   dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-
-   src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
-   dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
+   dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
+   (IS_GEN11(dev_priv) &&
+(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
+ dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
+   (!IS_GEN11(dev_priv) &&
+(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
+ dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
"size is out of scaler range\n",
intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, 
dst_h);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 47d40b8c31b4..f536b7fc7c92 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -547,6 +547,10 @@ struct intel_initial_plane_config {
 #define SKL_MAX_DST_W 4096
 #define SKL_MIN_DST_H 8
 #define SKL_MAX_DST_H 4096
+#define ICL_MAX_SRC_W 5120
+#define ICL_MAX_SRC_H 4096
+#define ICL_MAX_DST_W 5120
+#define ICL_MAX_DST_H 4096
 
 struct intel_scaler {
int in_use;
-- 
2.14.3

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[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

[Paulo Zanoni]

This commit introduces the definitions for the ICL clocks and adds the
basic functions to the shared DPLL framework. It adds code for the
Enable and Disable sequences for some PLLs, but it does not have the
code to compute the actual PLL values, which are marked as TODO
comments and should be introduced as separate commits.

v2:
 - Rebase around dpll_lock changes.
v3:
 - The spec now says what the timeouts should be.
 - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
   the machine.
 - Checkpatch found a white space problem.
 - Small adjustments before upstreaming.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
 drivers/gpu/drm/i915/intel_ddi.c  | 102 ++-
 drivers/gpu/drm/i915/intel_display.c  |  14 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 311 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 6 files changed, 491 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 05b41045b8f9..7ccb5ef212a1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3180,6 +3180,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
+   seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
+   seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
+   seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
+  pll->state.hw_state.mg_refclkin_ctl);
+   seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
+  pll->state.hw_state.mg_clktop2_coreclkctl1);
+   seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
+  pll->state.hw_state.mg_clktop2_hsclkctl);
+   seq_printf(m, " mg_pll_div0:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div0);
+   seq_printf(m, " mg_pll_div1:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div1);
+   seq_printf(m, " mg_pll_lf:0x%08x\n",
+  pll->state.hw_state.mg_pll_lf);
+   seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
+  pll->state.hw_state.mg_pll_frac_lock);
+   seq_printf(m, " mg_pll_ssc:   0x%08x\n",
+  pll->state.hw_state.mg_pll_ssc);
+   seq_printf(m, " mg_pll_bias:  0x%08x\n",
+  pll->state.hw_state.mg_pll_bias);
+   seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
+  pll->state.hw_state.mg_pll_tdc_coldst_bias);
}
drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8ca376aca8bd..81383e3dc91f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -893,6 +893,23 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
intel_shared_dpll *pll)
}
 }
 
+static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
+  const struct intel_shared_dpll *pll)
+{
+   switch (pll->id) {
+   default:
+   MISSING_CASE(pll->id);
+   case DPLL_ID_ICL_DPLL0:
+   case DPLL_ID_ICL_DPLL1:
+   return DDI_CLK_SEL_NONE;
+   case DPLL_ID_ICL_MGPLL1:
+   case DPLL_ID_ICL_MGPLL2:
+   case DPLL_ID_ICL_MGPLL3:
+   case DPLL_ID_ICL_MGPLL4:
+   return DDI_CLK_SEL_MG;
+   }
+}
+
 /* Starting with Haswell, different DDI ports can work in FDI mode for
  * connection to the PCH-located connectors. For this, it is necessary to train
  * both the DDI port and PCH receiver for the desired DDI buffer settings.
@@ -2114,6 +2131,75 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
 }
 
+void icl_map_plls_to_ports(struct drm_crtc *crtc,
+  struct intel_crtc_state *crtc_state,
+  struct drm_atomic_state *old_state)
+{
+   struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+   struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+   struct drm_connector_state *conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   if (!IS_ICELAKE(dev_priv))
+   return;
+
+   for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+   struct intel_encoder *encoder =
+   to_intel_encoder(conn_state->best_encoder);
+   enum port port = encoder->port;
+   uint32_t val;
+
+   if 

[Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

[Paulo Zanoni]

HDMI mode DPLL programming on ICL is the same as CNL, so just reuse
the CNL code.

v2:
 - Properly detect HDMI crtcs.
 - Rebase after changes to the cnl function (clock * 1000).

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 34 +++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8520a1b0279f..4d9265d14661 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2203,6 +2203,7 @@ cnl_ddi_calculate_wrpll(int clock,
struct skl_wrpll_params *wrpll_params)
 {
u32 afe_clock = clock * 5;
+   uint32_t ref_clock;
u32 dco_min = 7998000;
u32 dco_max = 1000;
u32 dco_mid = (dco_min + dco_max) / 2;
@@ -2235,8 +2236,12 @@ cnl_ddi_calculate_wrpll(int clock,
 
cnl_wrpll_get_multipliers(best_div, , , );
 
-   cnl_wrpll_params_populate(wrpll_params, best_dco,
- dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
+   ref_clock = dev_priv->cdclk.hw.ref;
+   if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
+   ref_clock = 19200;
+
+   cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
+ kdiv);
 
return true;
 }
@@ -2388,7 +2393,30 @@ static bool icl_calc_dpll_state(struct intel_crtc_state 
*crtc_state,
struct intel_encoder *encoder, int clock,
struct intel_dpll_hw_state *pll_state)
 {
-   /* TODO */
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   uint32_t cfgcr0, cfgcr1;
+   struct skl_wrpll_params pll_params = { 0 };
+   bool ret;
+
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+   ret = cnl_ddi_calculate_wrpll(clock, dev_priv, _params);
+   else
+   ret = false; /* TODO */
+
+   if (!ret)
+   return false;
+
+   cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
+pll_params.dco_integer;
+
+   cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
+DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
+DPLL_CFGCR1_KDIV(pll_params.kdiv) |
+DPLL_CFGCR1_PDIV(pll_params.pdiv) |
+DPLL_CFGCR1_CENTRAL_FREQ_8400;
+
+   pll_state->cfgcr0 = cfgcr0;
+   pll_state->cfgcr1 = cfgcr1;
return true;
 }
 
-- 
2.14.3

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[Intel-gfx] [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

[Paulo Zanoni]

From: Manasi Navare 

This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.

The Voltage swing seqeuence is similar to Cannonlake.
However it has different register definitions and hence
it makes sense to create a separate vswing sequence and
program functions for ICL to leave room for more changes
in case the Bspec changes later and deviates from CNL sequence.

v2:
Use ~TAP3_DISABLE for enbaling that bit (Jani Nikula)

v3:
* Use dw4_scaling column for PORT_TX_DW4 values (Rodrigo)

v4:
* Call it combo_vswing, use switch statement (Paulo)

v5 (from Paulo):
* Fix a typo.
* s/rate < 60/rate <= 60/.
* Don't remove blank lines that should be there.

v6:
* Rebased by Rodrigo on top of Cannonlake changes
  where non vswing sequences are not aligned with iboost
  anymore.

v7: Another rebase after an upstream rework.

v8 (from Paulo):
* Adjust the code to the upstream output type changes.
* Squash the patch that moved some functions up.
* Merge both get_combo_buf_trans functions in order to simplify the
  code.
* Change the changelog format.

Cc: Jani Nikula 
Reviewed-by: Paulo Zanoni  (v5)
Signed-off-by: Manasi Navare 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 189 ++-
 1 file changed, 186 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0a4683991ec2..c38873cb98ca 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -849,6 +849,45 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
int *n_entries)
}
 }
 
+static const struct icl_combo_phy_ddi_buf_trans *
+icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
+   int type, int *n_entries)
+{
+   u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
+
+   if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+   switch (voltage) {
+   case VOLTAGE_INFO_0_85V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
+   return icl_combo_phy_ddi_translations_edp_0_85V;
+   case VOLTAGE_INFO_0_95V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
+   return icl_combo_phy_ddi_translations_edp_0_95V;
+   case VOLTAGE_INFO_1_05V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
+   return icl_combo_phy_ddi_translations_edp_1_05V;
+   default:
+   MISSING_CASE(voltage);
+   return NULL;
+   }
+   } else {
+   switch (voltage) {
+   case VOLTAGE_INFO_0_85V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
+   case VOLTAGE_INFO_0_95V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
+   case VOLTAGE_INFO_1_05V:
+   *n_entries = 
ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
+   return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
+   default:
+   MISSING_CASE(voltage);
+   return NULL;
+   }
+   }
+}
+
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
port)
 {
int n_entries, level, default_entry;
@@ -2178,6 +2217,144 @@ static void cnl_ddi_vswing_sequence(struct 
intel_encoder *encoder,
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
 }
 
+static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
+u32 level, enum port port, int type)
+{
+   const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+   u32 n_entries, val;
+   int ln;
+
+   ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
+  _entries);
+   if (!ddi_translations)
+   return;
+
+   if (level >= n_entries) {
+   DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d 
instead.", level, n_entries - 1);
+   level = n_entries - 1;
+   }
+
+   /* Set PORT_TX_DW5 Scaling Mode Sel to 110b. */
+   val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+   val &= ~SCALING_MODE_SEL_MASK;
+   val |= SCALING_MODE_SEL(0x6);
+   I915_WRITE(ICL_PORT_TX_DW5_GRP(port), 

[Intel-gfx] [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers

[Paulo Zanoni]

There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.

v2: Coding style (Jani).
v3: Preparation for upstreaming.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 149 
 1 file changed, 149 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abcb27d4..f62335c4a748 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8783,6 +8783,12 @@ enum skl_power_gate {
 #define  PORT_CLK_SEL_NONE (7<<29)
 #define  PORT_CLK_SEL_MASK (7<<29)
 
+/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
+#define DDI_CLK_SEL(port)  PORT_CLK_SEL(port)
+#define  DDI_CLK_SEL_NONE  (0x0 << 28)
+#define  DDI_CLK_SEL_MG(0x8 << 28)
+#define  DDI_CLK_SEL_MASK  (0xF << 28)
+
 /* Transcoder clock selection */
 #define _TRANS_CLK_SEL_A   0x46140
 #define _TRANS_CLK_SEL_B   0x46144
@@ -8913,6 +8919,7 @@ enum skl_power_gate {
  * CNL Clocks
  */
 #define DPCLKA_CFGCR0  _MMIO(0x6C200)
+#define DPCLKA_CFGCR0_ICL  _MMIO(0x164280)
 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) ==  PORT_F ? 23 : 
\
  (port)+10))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
@@ -8929,10 +8936,141 @@ enum skl_power_gate {
 #define  PLL_POWER_STATE   (1 << 26)
 #define CNL_DPLL_ENABLE(pll)   _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
 
+#define _MG_PLL1_ENABLE0x46030
+#define _MG_PLL2_ENABLE0x46034
+#define _MG_PLL3_ENABLE0x46038
+#define _MG_PLL4_ENABLE0x4603C
+/* Bits are the same as DPLL0_ENABLE */
+#define MG_PLL_ENABLE(port)_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
+  _MG_PLL2_ENABLE)
+
+#define _MG_REFCLKIN_CTL_PORT1 0x16892C
+#define _MG_REFCLKIN_CTL_PORT2 0x16992C
+#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
+#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
+#define   MG_REFCLKIN_CTL_OD_2_MUX(x)  ((x) << 8)
+#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
+_MG_REFCLKIN_CTL_PORT1, \
+_MG_REFCLKIN_CTL_PORT2)
+
+#define _MG_CLKTOP2_CORECLKCTL1_PORT1  0x1690D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT2  0x16B0D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT3  0x16D0D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT4  0x16F0D8
+#define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
+#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
+#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
+   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
+   _MG_CLKTOP2_CORECLKCTL1_PORT2)
+
+#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
+#define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
+#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)   ((x) << 14)
+#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x)   ((x) << 12)
+#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)   ((x) << 8)
+#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
+_MG_CLKTOP2_HSCLKCTL_PORT1, \
+_MG_CLKTOP2_HSCLKCTL_PORT2)
+
+#define _MG_PLL_DIV0_PORT1 0x168A00
+#define _MG_PLL_DIV0_PORT2 0x169A00
+#define _MG_PLL_DIV0_PORT3 0x16AA00
+#define _MG_PLL_DIV0_PORT4 0x16BA00
+#define   MG_PLL_DIV0_FRACNEN_H(1 << 30)
+#define   MG_PLL_DIV0_FBDIV_FRAC(x)((x) << 8)
+#define   MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
+_MG_PLL_DIV0_PORT2)
+
+#define _MG_PLL_DIV1_PORT1 0x168A04
+#define _MG_PLL_DIV1_PORT2 0x169A04
+#define _MG_PLL_DIV1_PORT3 0x16AA04
+#define _MG_PLL_DIV1_PORT4 0x16BA04
+#define   MG_PLL_DIV1_IREF_NDIVRATIO(x)((x) << 16)
+#define   MG_PLL_DIV1_DITHER_DIV_1 (0 << 

[Intel-gfx] [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer

[Paulo Zanoni]

From: Manasi Navare 

This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.

v2 (from Paulo):
* Fix white space issues.

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Reviewed-by: Paulo Zanoni 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c38873cb98ca..98471b5c5f70 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -591,6 +591,26 @@ static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_e
{ 0x0, 0x00, 0x00 },/* 350 0.0   */
 };
 
+struct icl_mg_phy_ddi_buf_trans {
+   u32 cri_txdeemph_override_5_0;
+   u32 cri_txdeemph_override_11_6;
+   u32 cri_txdeemph_override_17_12;
+};
+
+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
+   /* Voltage swing  pre-emphasis */
+   { 0x0, 0x1B, 0x00 },/* 0  0   */
+   { 0x0, 0x23, 0x08 },/* 0  1   */
+   { 0x0, 0x2D, 0x12 },/* 0  2   */
+   { 0x0, 0x00, 0x00 },/* 0  3   */
+   { 0x0, 0x23, 0x00 },/* 1  0   */
+   { 0x0, 0x2B, 0x09 },/* 1  1   */
+   { 0x0, 0x2E, 0x11 },/* 1  2   */
+   { 0x0, 0x2F, 0x00 },/* 2  0   */
+   { 0x0, 0x33, 0x0C },/* 2  1   */
+   { 0x0, 0x00, 0x00 },/* 3  0   */
+};
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
-- 
2.14.3

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[Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

[Paulo Zanoni]

Just use the hardcoded tables provided by our spec.

v2: Rebase.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 ++-
 1 file changed, 85 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 4d9265d14661..5d7bacc80688 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2389,6 +2389,90 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
.dump_hw_state = cnl_dump_hw_state,
 };
 
+/*
+ * These values alrea already adjusted: they're the bits we write to the
+ * registers, not the logical values.
+ */
+static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = {
+   { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
+ .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x168, .dco_fraction = 0x, /* [4]: 2.16 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
+   { .dco_integer = 0x168, .dco_fraction = 0x, /* [5]: 4.32 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x195, .dco_fraction = 0x, /* [6]: 6.48 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+};
+
+static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
+   { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
+ .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1C2, .dco_fraction = 0x, /* [4]: 2.16 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
+   { .dco_integer = 0x1C2, .dco_fraction = 0x, /* [5]: 4.32 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
+ .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+   { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
+ .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
+};
+
+static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
+ struct skl_wrpll_params *pll_params)
+{
+   const struct skl_wrpll_params *params;
+
+   params = dev_priv->cdclk.hw.ref == 24000 ?
+   icl_dp_combo_pll_24MHz_values :
+   icl_dp_combo_pll_19_2MHz_values;
+
+   switch (clock) {
+   case 54:
+   *pll_params = params[0];
+   break;
+   case 27:
+   *pll_params = params[1];
+   break;
+   case 162000:
+   *pll_params = params[2];
+   break;
+   case 324000:
+   *pll_params = params[3];
+   break;
+   case 216000:
+   *pll_params = params[4];
+   break;
+   case 432000:
+   *pll_params = params[5];
+   break;
+   case 648000:
+   *pll_params = params[6];
+   break;
+   case 81:
+   *pll_params = params[7];
+   break;
+   default:
+   MISSING_CASE(clock);
+   return false;
+   }
+
+   return true;
+}
+
 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder, int clock,
struct intel_dpll_hw_state *pll_state)
@@ -2401,7 +2485,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state 
*crtc_state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ret = cnl_ddi_calculate_wrpll(clock, 

[Intel-gfx] [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.

[Paulo Zanoni]

From: Manasi Navare 

These tables are used on voltage vswing sequence initialization on
Icelake.

The swing_sel on the spec's table is defined in a 4 bits binary like
1010.  However the register bits are split in upper 1 bit swing_sel
and lower 3 bits swing sel.

In this table here we store this value as a single value in hex like
it is mentioned in the Bspec and split it to the upper and lower bit
values only while programming the registers.

For instance: b1010 is written as 0xA and then while writing to the
register, the upper 1 bit is obtained by (0xA & 0x8) and shifting by
appropriate bits while lower 3 bits are obtained by (0xA & 0x7) and
shifting by appropriate bits.

Some of the columns need to be updated after the spec is updated.

v5 (from Paulo):
* Checkpatch fixes.
v4 (from Paulo):
* Fix minor typo
* Coding style conformance
v3:
* Get rid of HDMI/DVI tables, same as DP (Paulo)
* Use combo_phy in ddi buf trans table defs (Paulo)
v2:
* Added DW4_scaling_hex column to the translation tables (Rodrigo)

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Reviewed-by: Paulo Zanoni 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_ddi.c | 99 
 1 file changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 81383e3dc91f..0a4683991ec2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -492,6 +492,105 @@ static const struct cnl_ddi_buf_trans 
cnl_ddi_translations_edp_1_05V[] = {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
+struct icl_combo_phy_ddi_buf_trans {
+   u32 dw2_swing_select;
+   u32 dw2_swing_scalar;
+   u32 dw4_scaling;
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for DP */
+static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
+   /* Voltage mV  db*/
+   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
+   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
+   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
+   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
+   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
+   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
+   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
+   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
+   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
+   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.85V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
+   /* Voltage mV  db*/
+   { 0x0, 0x00, 0x00 },/* 200 0.0   */
+   { 0x0, 0x00, 0x00 },/* 200 1.5   */
+   { 0x0, 0x00, 0x00 },/* 200 4.0   */
+   { 0x0, 0x00, 0x00 },/* 200 6.0   */
+   { 0x0, 0x00, 0x00 },/* 250 0.0   */
+   { 0x0, 0x00, 0x00 },/* 250 1.5   */
+   { 0x0, 0x00, 0x00 },/* 250 4.0   */
+   { 0x0, 0x00, 0x00 },/* 300 0.0   */
+   { 0x0, 0x00, 0x00 },/* 300 1.5   */
+   { 0x0, 0x00, 0x00 },/* 350 0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for DP */
+static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
+   /* Voltage mV  db*/
+   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
+   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
+   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
+   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
+   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
+   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
+   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
+   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
+   { 0x5, 0x76, 0x3015 },  /* 800 3.5   */
+   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.95V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_95V[] = {
+   /* Voltage mV  db*/
+   { 0x0, 0x00, 0x00 },/* 200 0.0   */
+   { 0x0, 0x00, 0x00 },/* 200 1.5   */
+   { 0x0, 0x00, 0x00 },/* 200 4.0   */
+   { 0x0, 0x00, 0x00 },/* 200 6.0   */
+   { 0x0, 0x00, 0x00 },/* 250 0.0   */
+   { 0x0, 0x00, 0x00 },/* 250 1.5   */
+   { 0x0, 0x00, 0x00 },/* 250 4.0   */
+   { 0x0, 0x00, 0x00 },/* 

[Intel-gfx] [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI

[Paulo Zanoni]

From: Manasi Navare 

On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.

This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.

v4 (from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 116 
 1 file changed, 116 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b45a9435ebff..a389d4030b7f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2128,6 +2128,122 @@ enum i915_power_well_id {
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+   _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT10x16812C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT10x16852C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT20x16912C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT20x16952C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT30x16A12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT30x16A52C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT40x16B12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT40x16B52C
+#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
+   _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT10x1680AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT10x1684AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT20x1690AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT20x1694AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT30x16A0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT30x16A4AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT40x16B0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT40x16B4AC
+#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
+   _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32   (1 << 5)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1  0x16814C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1  0x16854C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2  0x16914C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2  0x16954C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3  0x16A14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3  0x16A54C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4  0x16B14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4  0x16B54C
+#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
+   _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1  0x1680CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1  0x1684CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2  0x1690CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2  0x1694CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3  0x16A0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3  0x16A4CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4  0x16B0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4  0x16B4CC
+#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
+   _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define CRI_CALCINIT   (1 << 1)
+
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1  0x168148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1  0x168548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2  0x169148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2  0x169548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3  

[Intel-gfx] [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences.

[Paulo Zanoni]

From: Manasi Navare 

This patch defines register definitions required for ICL voltage
vswing programming for Combo PHY DDI Ports. It uses the same bit
definitions and macros as the CNL voltage swing sequences.

v7:
* Kill _MMIIO_PORT2_LN (Paulo)
v6:
* Replace some spaces with TAB (Paulo)
v5:
* Use _PORT instead of _PICK (Paulo)
* Remove DW7 defs for ICL, not used (Paulo)
v4:
* Rebase after _PICK was used instead of _PORT3
* Use _PICK for _MMIO_PORT2 since address of B is less
than address of A so cant use the math (Paulo)
v3:
* Make changes to the existing macro in a diff patch (Paulo)
v2:
* Add new defs fro ICL regs (Paulo)

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Reviewed-by: Paulo Zanoni 
Signed-off-by: Manasi Navare 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 44 +
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f62335c4a748..b45a9435ebff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1959,6 +1959,16 @@ enum i915_power_well_id {
_CNL_PORT_PCS_DW1_LN0_D, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_F)
+#define _ICL_PORT_PCS_DW1_GRP_A0x162604
+#define _ICL_PORT_PCS_DW1_GRP_B0x6C604
+#define _ICL_PORT_PCS_DW1_LN0_A0x162804
+#define _ICL_PORT_PCS_DW1_LN0_B0x6C804
+#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
+  _ICL_PORT_PCS_DW1_GRP_A, \
+  _ICL_PORT_PCS_DW1_GRP_B)
+#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
+  _ICL_PORT_PCS_DW1_LN0_A, \
+  _ICL_PORT_PCS_DW1_LN0_B)
 #define   COMMON_KEEPER_EN (1 << 26)
 
 #define _CNL_PORT_TX_DW2_GRP_AE0x162348
@@ -1985,6 +1995,16 @@ enum i915_power_well_id {
_CNL_PORT_TX_DW2_LN0_D, \
_CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F)
+#define _ICL_PORT_TX_DW2_GRP_A 0x162688
+#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
+#define _ICL_PORT_TX_DW2_LN0_A 0x162888
+#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
+#define ICL_PORT_TX_DW2_GRP(port)  _MMIO_PORT(port, \
+  _ICL_PORT_TX_DW2_GRP_A, \
+  _ICL_PORT_TX_DW2_GRP_B)
+#define ICL_PORT_TX_DW2_LN0(port)  _MMIO_PORT(port, \
+  _ICL_PORT_TX_DW2_LN0_A, \
+  _ICL_PORT_TX_DW2_LN0_B)
 #define   SWING_SEL_UPPER(x)   ((x >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK (1 << 15)
 #define   SWING_SEL_LOWER(x)   ((x & 0x7) << 11)
@@ -2018,6 +2038,19 @@ enum i915_power_well_id {
_CNL_PORT_TX_DW4_LN0_D, \
_CNL_PORT_TX_DW4_LN0_AE, \
_CNL_PORT_TX_DW4_LN0_F)
+#define _ICL_PORT_TX_DW4_GRP_A 0x162690
+#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
+#define _ICL_PORT_TX_DW4_LN0_A 0x162890
+#define _ICL_PORT_TX_DW4_LN1_A 0x162990
+#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
+#define ICL_PORT_TX_DW4_GRP(port)  _MMIO_PORT(port, \
+  _ICL_PORT_TX_DW4_GRP_A, \
+  _ICL_PORT_TX_DW4_GRP_B)
+#define ICL_PORT_TX_DW4_LN(port, ln)   _MMIO(_PORT(port, \
+  _ICL_PORT_TX_DW4_LN0_A, \
+  _ICL_PORT_TX_DW4_LN0_B) + \
+ (ln * (_ICL_PORT_TX_DW4_LN1_A - \
+_ICL_PORT_TX_DW4_LN0_A)))
 #define   LOADGEN_SELECT   (1 << 31)
 #define   POST_CURSOR_1(x) ((x) << 12)
 #define   POST_CURSOR_1_MASK   (0x3F << 12)
@@ -2050,7 +2083,18 @@ enum i915_power_well_id {
_CNL_PORT_TX_DW5_LN0_D, \
_CNL_PORT_TX_DW5_LN0_AE, \
_CNL_PORT_TX_DW5_LN0_F)
+#define _ICL_PORT_TX_DW5_GRP_A 0x162694
+#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
+#define 

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

[Zhenyu Wang]

On 2018.02.20 20:15:22 +, Chris Wilson wrote:
> Quoting Zhenyu Wang (2018-02-14 05:28:27)
> > 
> > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
> > chinese new year, team would take one week off at least, so like to
> > send this out before vacation. This has one to fix GTT mmio 8b access
> > from guest and two simple ones for mmio switch and typo fix. And sorry
> > that patchwork link is still not there yet, using dim to pull should
> > be ok but might need direct push to skip dim push check for now.
> 
> There are still quite a few sore points that would be nice to fix:
> 
> drivers/gpu/drm/i915/gvt/handlers.c:203 sanitize_fence_mmio_access()
> error: 'vgpu' dereferencing possible ERR_PTR()
> drivers/gpu/drm/i915/gvt/handlers.c:323 gdrst_mmio_write() warn:
> inconsistent indenting
> drivers/gpu/drm/i915/gvt/handlers.c:871 dp_aux_ch_ctl_mmio_write()
> error: buffer overflow 'display->ports' 5 <= 5
> drivers/gpu/drm/i915/gvt/handlers.c:1392 hws_pga_write() error: 'vgpu'
> dereferencing possible ERR_PTR()
> drivers/gpu/drm/i915/gvt/handlers.c:1402 hws_pga_write() error: 'vgpu'
> dereferencing possible ERR_PTR()
> 
> + Lots of kerneldoc errors that should be tidied up.

Chris, thanks for this, we will double check those smatch warnings.

Strange thing is that 0day kernel does run kinds of static checker
against our tree, but seems reports are sent to Dan instead of our
developers...

-- 
Open Source Technology Center, Intel ltd.

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Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -Original Message-
> From: Juha-Pekka Heikkila [mailto:juhapekka.heikk...@gmail.com]
> Sent: Wednesday, February 21, 2018 7:52 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary plane
> 
> On 21.02.2018 12:20, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch adds NV12 to list of supported formats for primary plane
> >
> > v2: Rebased (Chandra Konduru)
> >
> > v3: Rebased (me)
> >
> > v4: Review comments by Ville addressed Removed the
> > skl_primary_formats_with_nv12 and added NV12 case in existing
> > skl_primary_formats
> >
> > v5: Rebased (me)
> >
> > v6: Missed the Tested-by/Reviewed-by in the previous series Adding the
> > same to commit message in this version.
> >
> > v7: Review comments by Ville addressed
> > Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
> >
> > v8: Rebased (me)
> > Modified restricting the NV12 support for both BXT and KBL.
> >
> > v9: Rebased (me)
> >
> > v10: Addressed review comments from Maarten.
> > Adding NV12 inside skl_primary_formats itself.
> >
> > v11: Adding Reviewed By tag from Shashank Sharma
> >
> > Tested-by: Clinton Taylor 
> > Reviewed-by: Clinton Taylor 
> > Reviewed-by: Shashank Sharma 
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 5 +
> >   1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 142dfe0..1870366 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> > DRM_FORMAT_YVYU,
> > DRM_FORMAT_UYVY,
> > DRM_FORMAT_VYUY,
> > +   DRM_FORMAT_NV12,
> >   };
> >
> >   static const uint64_t skl_format_modifiers_noccs[] = { @@ -13282,6
> > +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> > intel_primary_formats = skl_primary_formats;
> > num_formats = ARRAY_SIZE(skl_primary_formats);
> >
> > +   if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> > +   !IS_GEMINILAKE(dev_priv))
> > +   num_formats -= 1;
> 
> This doesn't look future proof solution. This creates invisible dependency
> where it is required NV12 is last item in list of formats.

Initially we had a different array for this. But as a part of one of the review
comments, I made this change.

Regards
Vidya

> 
> > +
> > if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
> > modifiers = skl_format_modifiers_ccs;
> > else
> >

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4)
URL   : https://patchwork.freedesktop.org/series/38441/
State : success

== Summary ==

Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060 +1
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +2
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> FAIL   (shard-apl) fdo#103481
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup oa-exponents:
pass   -> INCOMPLETE (shard-apl) fdo#102254

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254

shard-apltotal:3331 pass:1740 dwarn:1   dfail:0   fail:14  skip:1574 
time:11723s
shard-hswtotal:3464 pass:1763 dwarn:1   dfail:0   fail:6   skip:1693 
time:11824s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6625s
Blacklisted hosts:
shard-kbltotal:3464 pass:1962 dwarn:1   dfail:0   fail:14  skip:1487 
time:9639s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8114/shards.html
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Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

[Mustaffa, Mustamin B]

Hi Ville, 

I already resubmit the patch https://patchwork.freedesktop.org/patch/205823/ 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..b9068bd1943f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,16 @@  bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+   int backlight_controller =
+   intel_dp->attached_connector->panel.backlight.controller;
+

Best regard 

Mustamin


-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] 
Sent: Wednesday, February 21, 2018 9:19 PM
To: Mustaffa, Mustamin B 
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

On Wed, Feb 21, 2018 at 12:04:43AM +, Mustaffa, Mustamin B wrote:
> Hi Ville,
> 
> Can you point out what makes you says the git diff is broken? 
> 
> Best regard
> 
> Mustamin
> 
> 
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Tuesday, February 20, 2018 10:26 PM
> To: Mustaffa, Mustamin B 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control 
> for DP
> 
> On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> > Currently, BXT_PP is hardcoded with value '0'.
> > It practically disabled eDP backlight on MRB (BXT) platform.
> > 
> > This patch will tell which BXT_PP registers (there are two set of 
> > PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> > Timing
> > table) and this will enabled eDP backlight controller on MRB (BXT) 
> > platform.
> > 
> > v2:
> >  - Remove unnecessary information in commit message.
> >  - Assign vbt.backlight.controller to a backlight_controller variable and
> >return the variable value.
> > v3:
> >  - Rebased to latest code base.
> >  - updated commit title.
> > V4:
> >  - Use sanitized panel backlight controller instead of vbt backlight
> >controller
> > 
> > Signed-off-by: Mustamin B Mustaffa 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 11 ---
> >  1 file changed, 4 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct
   ^

That is not the function you're patching here.

> > drm_i915_private *dev_priv)
> 
> Your git diff is clearly broken. This makes patch review harder than it has 
> to be. Please consider updating to a non-broken version.
> 
> >  {
> > struct drm_i915_private *dev_priv = 
> > to_i915(intel_dp_to_dev(intel_dp));
> >  
> > +   int backlight_controller = 
> > +intel_dp->attached_connector->panel.backlight.controller;
> > +
> > lockdep_assert_held(_priv->pps_mutex);
> >  
> > /* We should never land here with regular DP ports */
> > WARN_ON(!intel_dp_is_edp(intel_dp));
> >  
> > -   /*
> > -* TODO: BXT has 2 PPS instances. The correct port->PPS instance
> > -* mapping needs to be retrieved from VBT, for now just hard-code to
> > -* use instance #0 always.
> > -*/
> > if (!intel_dp->pps_reset)
> > -   return 0;
> > +   return backlight_controller;
> >  
> > intel_dp->pps_reset = false;
> >  
> > @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct 
> > drm_i915_private *dev_priv)
> >  */
> > intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> >  
> > -   return 0;
> > +   return backlight_controller;
> >  }
> >  
> >  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> > --
> > 1.9.1
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs

[Daniele Ceraolo Spurio]

On 20/02/18 07:37, Mika Kuoppala wrote:

From: Tvrtko Ursulin 

Show GEN11 specific interrupt registers in debugfs

v2: Update for POR changes. (Daniele Ceraolo Spurio)
v3: get runtime pm ref. unify common parts with gen8 (Daniele)

Cc: Ceraolo Spurio, Daniele 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Mika Kuoppala 


Reviewed-by: Daniele Ceraolo Spurio 


---
  drivers/gpu/drm/i915/i915_debugfs.c | 139 
  1 file changed, 95 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 05b41045b8f9..d4991b335cf5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, 
void *data)
return 0;
  }
  
+static void gen8_display_interrupt_info(struct seq_file *m)

+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   int pipe;
+
+   for_each_pipe(dev_priv, pipe) {
+   enum intel_display_power_domain power_domain;
+
+   power_domain = POWER_DOMAIN_PIPE(pipe);
+   if (!intel_display_power_get_if_enabled(dev_priv,
+   power_domain)) {
+   seq_printf(m, "Pipe %c power disabled\n",
+  pipe_name(pipe));
+   continue;
+   }
+   seq_printf(m, "Pipe %c IMR:\t%08x\n",
+  pipe_name(pipe),
+  I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+   seq_printf(m, "Pipe %c IIR:\t%08x\n",
+  pipe_name(pipe),
+  I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+   seq_printf(m, "Pipe %c IER:\t%08x\n",
+  pipe_name(pipe),
+  I915_READ(GEN8_DE_PIPE_IER(pipe)));
+
+   intel_display_power_put(dev_priv, power_domain);
+   }
+
+   seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+  I915_READ(GEN8_DE_PORT_IMR));
+   seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+  I915_READ(GEN8_DE_PORT_IIR));
+   seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+  I915_READ(GEN8_DE_PORT_IER));
+
+   seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+  I915_READ(GEN8_DE_MISC_IMR));
+   seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+  I915_READ(GEN8_DE_MISC_IIR));
+   seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+  I915_READ(GEN8_DE_MISC_IER));
+
+   seq_printf(m, "PCU interrupt mask:\t%08x\n",
+  I915_READ(GEN8_PCU_IMR));
+   seq_printf(m, "PCU interrupt identity:\t%08x\n",
+  I915_READ(GEN8_PCU_IIR));
+   seq_printf(m, "PCU interrupt enable:\t%08x\n",
+  I915_READ(GEN8_PCU_IER));
+}
+
  static int i915_interrupt_info(struct seq_file *m, void *data)
  {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void 
*data)
   I915_READ(GEN8_PCU_IIR));
seq_printf(m, "PCU interrupt enable:\t%08x\n",
   I915_READ(GEN8_PCU_IER));
+   } else if (INTEL_GEN(dev_priv) >= 11) {
+   seq_printf(m, "Master Interrupt Control:  %08x\n",
+  I915_READ(GEN11_GFX_MSTR_IRQ));
+
+   seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
+  I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+   seq_printf(m, "VCS/VECS Intr Enable:  %08x\n",
+  I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+   seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
+  I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+   seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+  I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+   seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
+  I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+   seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
+  I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+
+   seq_printf(m, "Display Interrupt Control:\t%08x\n",
+  I915_READ(GEN11_DISPLAY_INT_CTL));
+
+   gen8_display_interrupt_info(m);
} else if (INTEL_GEN(dev_priv) >= 8) {
seq_printf(m, "Master Interrupt Control:\t%08x\n",
   I915_READ(GEN8_MASTER_IRQ));
@@ -722,49 +793,7 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Scanout fence fixes/cleanups (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/38714/
State : success

== Summary ==

Test drv_suspend:
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (shard-hsw) fdo#103928
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-apl) fdo#103060
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (shard-hsw) fdo#104152
Test perf:
Subgroup oa-exponents:
incomplete -> FAIL   (shard-apl) fdo#102254
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103540

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#104152 https://bugs.freedesktop.org/show_bug.cgi?id=104152
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-apltotal:3369 pass:1764 dwarn:1   dfail:0   fail:14  skip:1589 
time:12050s
shard-hswtotal:3455 pass:1758 dwarn:1   dfail:0   fail:4   skip:1690 
time:11313s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6647s
Blacklisted hosts:
shard-kbltotal:3464 pass:1959 dwarn:1   dfail:0   fail:16  skip:1488 
time:9690s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8113/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev6)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Applying: drm/i915/icl: Add the ICL PCI IDs
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_pci.c
M   include/drm/i915_pciids.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/i915_pciids.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_drv.h
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_ringbuffer.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_ringbuffer.h
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: new context descriptor support
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_drv.h
M   drivers/gpu/drm/i915/i915_gem_context.c
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_engine_cs.c
M   drivers/gpu/drm/i915/intel_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_lrc.c
Auto-merging drivers/gpu/drm/i915/intel_engine_cs.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_gem_context.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Applying: drm/i915/icl: Enhanced execution list support
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.h).
error: could not build fake ancestor
Patch failed at 0009 drm/i915/icl: Enhanced execution list support
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

[Xiong, James]

On Wed, Feb 21, 2018 at 09:43:55PM +, Chris Wilson wrote:
> Quoting James Xiong (2018-02-20 17:48:03)
> > From: "Xiong, James" 
> > 
> > With gem_reuse enabled, when a buffer size is different than
> > the sizes of buckets, it is aligned to the next bucket's size,
> > which means about 25% more memory than the requested is allocated
> > in the worst senario. For example:
> > 
> > Orignal sizeActual
> > 32KB+1Byte  40KB
> > .
> > .
> > .
> > 8MB+1Byte   10MB
> > .
> > .
> > .
> > 96MB+1Byte  112MB
> > 
> > This is very memory expensive and make the reuse feature less
> > favorable than it deserves to be.
> 
> The reuse feature also misses one important source: reusing temporaries
> within a batch.
>  
> > This commit aligns the reuse buffer size on page size instead,
> > the buffer whose size falls between bucket[n] and bucket[n+1] is
> > put in bucket[n] when it's done; And when searching for a cached
> > buffer for reuse, it goes through the cached buffers list in the
> > bucket until a cached buffer, whose size is larger than or equal
> > to the requested size, is found.
> 
> So how many times do you have to allocate a new buffer because you
> refused to hand back a slightly larger buffer? Have you checked the
> impact on !llc? With mmaps? On how wide a workload?
bucket[n] contains a list of buffers with size between bucket[n].size
and bucket[n+1].size - 1, a larger cached buffer could still be reused
if available.
I managed to run some performance tests on GEN9 without noticeable
performance impact but didn't have chance to test for more coverages.
> 
> > Signed-off-by: Xiong, James 
> > ---
> >  intel/intel_bufmgr_gem.c | 180 
> > +--
> >  libdrm_lists.h   |   6 ++
> >  2 files changed, 101 insertions(+), 85 deletions(-)
> > 
> > diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> > index 386da30..5b2d0d0 100644
> > --- a/intel/intel_bufmgr_gem.c
> > +++ b/intel/intel_bufmgr_gem.c
> > @@ -402,11 +402,10 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem 
> > *bufmgr_gem,
> >  {
> > int i;
> >  
> > -   for (i = 0; i < bufmgr_gem->num_buckets; i++) {
> > -   struct drm_intel_gem_bo_bucket *bucket =
> > -   _gem->cache_bucket[i];
> > -   if (bucket->size >= size) {
> > -   return bucket;
> > +   for (i = 0; i < bufmgr_gem->num_buckets - 1; i++) {
> > +   if (size >= bufmgr_gem->cache_bucket[i].size &&
> > +   size < bufmgr_gem->cache_bucket[i+1].size) {
> > +   return _gem->cache_bucket[i];
> 
> So you never return the last bucket?
The last bucket's size is 112MB, I can add a 128M bucket at the end to
cache and reuse allocations between [112MB, 128M-1] if you think it's
important.
> 
> Given the ordered set of buckets, the test remains correct even when
> every bo within the bucket is not the full size (each bo is still at
> least bigger than the previous bucket).
The function returns an bucket according to the requested buffer size
at allocating.
if (buffer_size in [bucket[n].size, bucket[n+1].size))
return [n];
it also gets called at freeing. In both cases, the correct bucket is returned.
> 
> > }
> > }
> >  
> > @@ -685,25 +684,95 @@ drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
> >  madv);
> >  }
> >  
> > -/* drop the oldest entries that have been purged by the kernel */
> > +/* drop the entries that are older than the given time */
> >  static void
> >  drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
> > -   struct drm_intel_gem_bo_bucket *bucket)
> > +   struct drm_intel_gem_bo_bucket *bucket,
> > +   time_t time)
> >  {
> > -   while (!DRMLISTEMPTY(>head)) {
> > -   drm_intel_bo_gem *bo_gem;
> > -
> > -   bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
> > - bucket->head.next, head);
> > -   if (drm_intel_gem_bo_madvise_internal
> > -   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
> > -   break;
> > -
> > -   DRMLISTDEL(_gem->head);
> > -   drm_intel_gem_bo_free(_gem->bo);
> > +   drm_intel_bo_gem *bo_gem, *temp;
> > +   DRMLISTFOREACHENTRYSAFE(bo_gem, temp, >head, head) {
> > +   if (bo_gem->free_time >= time) {
> > +   drm_intel_gem_bo_madvise_internal
> > +   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED);
> > +   DRMLISTDEL(_gem->head);
> > +   drm_intel_gem_bo_free(_gem->bo);
> > +   }
> 
> This function is called after the kernel reports that it purged a
> buffer, and the intent here is that we find all the buffers that the
> 

[Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Oscar Mateo]

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.

Unfortunately, we have a Catch-22 situation going on: we need the blitter
forcewake to read the register with the fuse info, but we cannot initialize
the forcewake domains without knowin about the engines present in the HW.
We workaround this problem by pruning the forcewake domains after reading
the fuse information.

Bspec: 20680

v2: We were shifting incorrectly for vebox disable (Vinay)

v3: Assert mmio is ready and warn if we have attempted to initialize
forcewake for fused-off engines (Paulo)

v4:
  - Use INTEL_GEN in new code (Tvrtko)
  - Shorter local variable (Tvrtko, Michal)
  - Keep "if (!...) continue" style (Tvrtko)
  - No unnecessary BUG_ON (Tvrtko)
  - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
  - Use I915_READ_FW (Michal)
  - Use I915_MAX_VCS/VECS macros (Michal)

v5: Rebased by Rodrigo fixing conflicts on top of:
commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

v6: Fix v5. Remove info->num_rings. (by Oscar)

v7: Rebase (Rodrigo).

v8:
  - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
  - Make vdbox_disable & vebox_disable local variables (Chris)

v9:
  - Move function declaration to intel_device_info.h (Michal)
  - Missing indent in bit fields definitions (Michal)
  - When RC6 is enabled by BIOS, the fuse register cannot be read until
the blitter powerwell is awake. Shuffle where the fuse is read, prune
the forcewake domains after the fact and change the commit message
accordingly (Vinay, Sagar, Chris).

Cc: Paulo Zanoni 
Cc: Vinay Belgaumkar 
Cc: Tvrtko Ursulin 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.c  |  4 +++
 drivers/gpu/drm/i915/i915_reg.h  |  5 +++
 drivers/gpu/drm/i915/intel_device_info.c | 47 +++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_uncore.c  | 55 
 drivers/gpu/drm/i915/intel_uncore.h  |  1 +
 6 files changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d09f8e6..2269b56 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1031,6 +1031,10 @@ static int i915_driver_init_mmio(struct drm_i915_private 
*dev_priv)
 
intel_uncore_init(dev_priv);
 
+   intel_device_info_init_mmio(dev_priv);
+
+   intel_uncore_prune(dev_priv);
+
intel_uc_init_mmio(dev_priv);
 
ret = intel_engines_init_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 784d79c..e6a0d84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2854,6 +2854,11 @@ enum i915_power_well_id {
 #define GEN10_EU_DISABLE3  _MMIO(0x9140)
 #define   GEN10_EU_DIS_SS_MASK 0xff
 
+#define GEN11_GT_VEBOX_VDBOX_DISABLE   _MMIO(0x9140)
+#define   GEN11_GT_VDBOX_DISABLE_MASK  0xff
+#define   GEN11_GT_VEBOX_DISABLE_SHIFT 16
+#define   GEN11_GT_VEBOX_DISABLE_MASK  (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 9352f34..70ea654 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -595,3 +595,50 @@ void intel_driver_caps_print(const struct 
intel_driver_caps *caps,
 {
drm_printf(p, "scheduler: %x\n", caps->scheduler);
 }
+
+/*
+ * Determine which engines are fused off in our particular hardware. Since the
+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
+ * this point (but later we need to prune the forcewake domains for engines 
that
+ * are indeed fused off).
+ */
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
+{
+   struct intel_device_info *info = mkwrite_device_info(dev_priv);
+   u8 vdbox_disable, vebox_disable;
+   u32 media_fuse;
+   int i;
+
+   if (INTEL_GEN(dev_priv) < 11)
+   return;
+
+   media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
+
+   vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+   vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+   

Re: [Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

[Lyude Paul]

Nice, this is a no-brainer

Reviewed-by: Lyude Paul 

On Wed, 2018-02-21 at 10:28 +0100, Maarten Lankhorst wrote:
> Moving the check upwards will mean we we no longer have to add planes
> and connectors manually, because everything is handled correctly by
> drm_atomic_helper_check_modeset() as intended.
> 
> Signed-off-by: Maarten Lankhorst 
> Cc: Lyude Paul 
> Cc: Daniel Vetter 
> Reviewed-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 +---
>  1 file changed, 5 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 65be7af7f647..c5cc9022d545 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11927,6 +11927,11 @@ static int intel_atomic_check(struct drm_device
> *dev,
>   int ret, i;
>   bool any_ms = false;
>  
> + /* Catch I915_MODE_FLAG_INHERITED */
> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> crtc_state, i)
> + if (crtc_state->mode.private_flags != old_crtc_state-
> >mode.private_flags)
> + crtc_state->mode_changed = true;
> +
>   ret = drm_atomic_helper_check_modeset(dev, state);
>   if (ret)
>   return ret;
> @@ -11935,10 +11940,6 @@ static int intel_atomic_check(struct drm_device
> *dev,
>   struct intel_crtc_state *pipe_config =
>   to_intel_crtc_state(crtc_state);
>  
> - /* Catch I915_MODE_FLAG_INHERITED */
> - if (crtc_state->mode.private_flags != old_crtc_state-
> >mode.private_flags)
> - crtc_state->mode_changed = true;
> -
>   if (!needs_modeset(crtc_state))
>   continue;
>  
> @@ -11947,13 +11948,6 @@ static int intel_atomic_check(struct drm_device
> *dev,
>   continue;
>   }
>  
> - /* FIXME: For only active_changed we shouldn't need to do
> any
> -  * state recomputation at all. */
> -
> - ret = drm_atomic_add_affected_connectors(state, crtc);
> - if (ret)
> - return ret;
> -
>   ret = intel_modeset_pipe_config(crtc, pipe_config);
>   if (ret) {
>   intel_dump_pipe_config(to_intel_crtc(crtc),
> @@ -11972,10 +11966,6 @@ static int intel_atomic_check(struct drm_device
> *dev,
>   if (needs_modeset(crtc_state))
>   any_ms = true;
>  
> - ret = drm_atomic_add_affected_planes(state, crtc);
> - if (ret)
> - return ret;
> -
>   intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
>  needs_modeset(crtc_state) ?
>  "[modeset]" : "[fastset]");
-- 
Cheers,
Lyude Paul
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Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

[Rodrigo Vivi]

On Wed, Feb 21, 2018 at 01:12:08PM -0800, Souza, Jose wrote:
> On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote:
> > On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza
> > wrote:
> > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > > self, so lets use the mutex register that is available in gen9+ to
> > > avoid concurrent access by hardware and driver.
> > > 
> > > Reference: https://01.org/sites/default/files/documentation/intel-g
> > > fx-prm-osrc-skl-vol12-display.pdf
> > > Page 198 - AUX programming sequence
> > > 
> > 
> > Cc: Ville
> > Cc: DK
> > > Cc: Rodrigo Vivi 
> > > Cc: Jani Nikula 
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  |  9 
> > >  drivers/gpu/drm/i915/intel_dp.c  | 50
> > > 
> > >  drivers/gpu/drm/i915/intel_drv.h |  1 +
> > >  3 files changed, 60 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1412abcb27d4..a62e3c1badab 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -5318,6 +5318,7 @@ enum {
> > >  #define _DPA_AUX_CH_DATA3(dev_priv-
> > > >info.display_mmio_offset + 0x6401c)
> > >  #define _DPA_AUX_CH_DATA4(dev_priv-
> > > >info.display_mmio_offset + 0x64020)
> > >  #define _DPA_AUX_CH_DATA5(dev_priv-
> > > >info.display_mmio_offset + 0x64024)
> > > +#define _DPA_AUX_CH_MUTEX(dev_priv-
> > > >info.display_mmio_offset + 0x6402C)
> > >  
> > >  #define _DPB_AUX_CH_CTL  (dev_priv-
> > > >info.display_mmio_offset + 0x64110)
> > >  #define _DPB_AUX_CH_DATA1(dev_priv-
> > > >info.display_mmio_offset + 0x64114)
> > > @@ -5325,6 +5326,7 @@ enum {
> > >  #define _DPB_AUX_CH_DATA3(dev_priv-
> > > >info.display_mmio_offset + 0x6411c)
> > >  #define _DPB_AUX_CH_DATA4(dev_priv-
> > > >info.display_mmio_offset + 0x64120)
> > >  #define _DPB_AUX_CH_DATA5(dev_priv-
> > > >info.display_mmio_offset + 0x64124)
> > > +#define _DPB_AUX_CH_MUTEX(dev_priv-
> > > >info.display_mmio_offset + 0x6412C)
> > >  
> > >  #define _DPC_AUX_CH_CTL  (dev_priv-
> > > >info.display_mmio_offset + 0x64210)
> > >  #define _DPC_AUX_CH_DATA1(dev_priv-
> > > >info.display_mmio_offset + 0x64214)
> > > @@ -5332,6 +5334,7 @@ enum {
> > >  #define _DPC_AUX_CH_DATA3(dev_priv-
> > > >info.display_mmio_offset + 0x6421c)
> > >  #define _DPC_AUX_CH_DATA4(dev_priv-
> > > >info.display_mmio_offset + 0x64220)
> > >  #define _DPC_AUX_CH_DATA5(dev_priv-
> > > >info.display_mmio_offset + 0x64224)
> > > +#define _DPC_AUX_CH_MUTEX(dev_priv-
> > > >info.display_mmio_offset + 0x6422C)
> > >  
> > >  #define _DPD_AUX_CH_CTL  (dev_priv-
> > > >info.display_mmio_offset + 0x64310)
> > >  #define _DPD_AUX_CH_DATA1(dev_priv-
> > > >info.display_mmio_offset + 0x64314)
> > > @@ -5339,6 +5342,7 @@ enum {
> > >  #define _DPD_AUX_CH_DATA3(dev_priv-
> > > >info.display_mmio_offset + 0x6431c)
> > >  #define _DPD_AUX_CH_DATA4(dev_priv-
> > > >info.display_mmio_offset + 0x64320)
> > >  #define _DPD_AUX_CH_DATA5(dev_priv-
> > > >info.display_mmio_offset + 0x64324)
> > > +#define _DPD_AUX_CH_MUTEX(dev_priv-
> > > >info.display_mmio_offset + 0x6432C)
> > >  
> > >  #define _DPF_AUX_CH_CTL  (dev_priv-
> > > >info.display_mmio_offset + 0x64510)
> > >  #define _DPF_AUX_CH_DATA1(dev_priv-
> > > >info.display_mmio_offset + 0x64514)
> > > @@ -5346,6 +5350,7 @@ enum {
> > >  #define _DPF_AUX_CH_DATA3(dev_priv-
> > > >info.display_mmio_offset + 0x6451c)
> > >  #define _DPF_AUX_CH_DATA4(dev_priv-
> > > >info.display_mmio_offset + 0x64520)
> > >  #define _DPF_AUX_CH_DATA5(dev_priv-
> > > >info.display_mmio_offset + 0x64524)
> > > +#define _DPF_AUX_CH_MUTEX(dev_priv-
> > > >info.display_mmio_offset + 0x6452C)
> > >  
> > >  #define DP_AUX_CH_CTL(port)  _MMIO_PORT(port,
> > > _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> > >  #define DP_AUX_CH_DATA(port, i)  _MMIO(_PORT(port,
> > > _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > > @@ -5378,6 +5383,10 @@ enum {
> > >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> > >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
> > > 
> > 
> > 
> > I believe _DPA_AUX_CH_MUTEX and _DPB_AUX_CH_MUTEX should be defined
> > here along
> > with the bits as Jani suggested.
> > I don't see any reason to tag that far from the bits and close to CTL
> > and DATA.
> > 
> > > +#define DP_AUX_CH_MUTEX(port)_MMIO_PORT(port,
> > > _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
> > > +#define   DP_AUX_CH_MUTEX_ENABLE (1 << 31)
> > > +#define   DP_AUX_CH_MUTEX_STATUS (1 << 30)
> > > +
> > >  /*
> > >   * Computing GMCH M and N values for the 

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 16:02:35)
> From: Ville Syrjälä 
> 
> Currently the FBC code doesn't handle the 90/270 degree rotated case
> correctly. We would need the GTT tracking to monitor the fence on the
> normal GTT view (the rotated view doesn't even have a fence). Not quite
> sure how we should program the fence Y offset etc. in that case. For now
> we'll end up disabling FBC with 90/270 degree rotation. Add a FIXME
> to remind people about this fact.

Oh my. plane_state would have to track both normal_vma and rotated_vma,
at least that is less complicated than having rotated_vma automagically
pin the normal_vma.

> v2: Reword the text (Chris)
> Move the FIXME to the fbc code
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Extract intel_plane_{pin, unpin}_fb()

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 16:02:34)
> From: Ville Syrjälä 
> 
> We've replicated the fb pin/unpin code in a few places. Pull it into
> convenint helpers.
> 
> Slight change in locking behaviour as intel_cleanup_plane_fb() now
> grab struct_mutex unconditionally.
> 
> v2: Change the locking to be symmetric between pin and unpin
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Require fence only for FBC capable planes

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 16:02:33)
> From: Ville Syrjälä 
> 
> As only a subset of primary planes are FBC capable there's no need
> to waste fences on all of them. So let's skip the fence if the plane
> isn't even fbc capable.
> 
> In the future we might extend this to skip the fence even for FBC
> capable planes if the crtc and/or plane state isn't suitable
> for FBC.
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 8aeb6b686bac..b4048b425ffd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2076,7 +2076,7 @@ static bool intel_plane_uses_fence(const struct 
> intel_plane_state *plane_state)
> if (i915_gem_object_get_tiling(obj) == I915_TILING_NONE)
> return false;
>  
> -   return INTEL_GEN(dev_priv) < 4 || plane->id == PLANE_PRIMARY;
> +   return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 17:31:01)
> From: Ville Syrjälä 
> 
> Let's record the information whether a plane can do fbc or not under
> struct inte_plane.
> 
> v2: Rebase due to i9xx_plane_id
> Handle BDW/HSW correctly
> v3: Move inte_fbc_init() back since we depend on it happening
> even with i915.disable_display, and populate
> fbc->possible_framebuffer_bits directly from the
> plane init code instead
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 41 
> 
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_fbc.c | 26 ++-
>  3 files changed, 44 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d2a66704e6f5..c60d2215b377 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13238,6 +13238,32 @@ static const struct drm_plane_funcs 
> intel_cursor_plane_funcs = {
> .format_mod_supported = intel_cursor_plane_format_mod_supported,
>  };
>  
> +static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
> +  enum i9xx_plane_id i9xx_plane)
> +{
> +   if (!HAS_FBC(dev_priv))
> +   return false;

> -static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
> -{
> -   return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
> -}
> -
> -static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
> -{
> -   return INTEL_GEN(dev_priv) < 4;
> -}

> +
> +   if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> +   return i9xx_plane == PLANE_A;

Where PLANE_A is tied to PIPE_A by construction. Is that worth a quick
comment?

> +   else if (IS_IVYBRIDGE(dev_priv))
> +   return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
> +   i9xx_plane == PLANE_C;
> +   else if (INTEL_GEN(dev_priv) >= 4)
> +   return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
> +   else
> +   return i9xx_plane == PLANE_A;

Ok, looks a bit more complete than before.

> +}
> +
> +static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> +   if (!HAS_FBC(dev_priv))
> +   return false;
> +
> +   return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
> +}
> +
>  static struct intel_plane *
>  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> @@ -13280,6 +13306,21 @@ intel_primary_plane_create(struct drm_i915_private 
> *dev_priv, enum pipe pipe)
> primary->i9xx_plane = (enum i9xx_plane_id) pipe;
> primary->id = PLANE_PRIMARY;
> primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
> +
> +   if (INTEL_GEN(dev_priv) >= 9)
> +   primary->has_fbc = skl_plane_has_fbc(dev_priv,
> +primary->pipe,
> +primary->id);
> +   else
> +   primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
> + primary->i9xx_plane);
> +
> +   if (primary->has_fbc) {
> +   struct intel_fbc *fbc = _priv->fbc;
> +
> +   fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
> +   }

So an equivalent init loop to

> -   for_each_pipe(dev_priv, pipe) {
> -   fbc->possible_framebuffer_bits |=
> -   INTEL_FRONTBUFFER(pipe, PLANE_PRIMARY);
> -
> -   if (fbc_on_pipe_a_only(dev_priv))
> -   break;
> -   }

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

[Ville Syrjala]

From: Ville Syrjälä 

Currently we pin a fence on every plane doing tiled scanout. The
number of planes we have available is fast apporaching the number
of fences so we really should stop wasting them. Only FBC needs
the fence on gen4+, so let's use fences only for the primary planes
on those platforms.

v2: drop the tiling check from plane_uses_fence() as the obj is
NULL during initial_plane_config() and we don't rally need the
check since i915_vma_pin_fence() does the check anyway

Cc: Chris Wilson 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 14 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_fbdev.c   |  2 +-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 66b269bc24b9..f2c1bb715e7b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2067,9 +2067,18 @@ static unsigned int intel_surf_alignment(const struct 
drm_framebuffer *fb,
}
 }
 
+static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
+{
+   struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+   return INTEL_GEN(dev_priv) < 4 || plane->id == PLANE_PRIMARY;
+}
+
 struct i915_vma *
 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
   unsigned int rotation,
+  bool uses_fence,
   unsigned long *out_flags)
 {
struct drm_device *dev = fb->dev;
@@ -2122,7 +2131,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
if (IS_ERR(vma))
goto err;
 
-   if (i915_vma_is_map_and_fenceable(vma)) {
+   if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
int ret;
 
/* Install a fence for tiled scan-out. Pre-i965 always needs a
@@ -2836,6 +2845,7 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
intel_state->vma =
intel_pin_and_fence_fb_obj(fb,
   primary->state->rotation,
+  intel_plane_uses_fence(intel_state),
   _state->flags);
mutex_unlock(>struct_mutex);
if (IS_ERR(intel_state->vma)) {
@@ -12744,6 +12754,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 
vma = intel_pin_and_fence_fb_obj(fb,
 new_state->rotation,
+
intel_plane_uses_fence(to_intel_plane_state(new_state)),
 
_intel_plane_state(new_state)->flags);
if (!IS_ERR(vma))
to_intel_plane_state(new_state)->vma = vma;
@@ -13162,6 +13173,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
} else {
vma = intel_pin_and_fence_fb_obj(fb,
 new_plane_state->rotation,
+false,
 
_intel_plane_state(new_plane_state)->flags);
if (IS_ERR(vma)) {
DRM_DEBUG_KMS("failed to pin object\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 50874f4035cf..e3f78fdae859 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1508,6 +1508,7 @@ void intel_release_load_detect_pipe(struct drm_connector 
*connector,
 struct i915_vma *
 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
   unsigned int rotation,
+  bool uses_fence,
   unsigned long *out_flags);
 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 struct drm_framebuffer *
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c 
b/drivers/gpu/drm/i915/intel_fbdev.c
index 055f409f8b75..6f12adc06365 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -215,7 +215,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 */
vma = intel_pin_and_fence_fb_obj(>fb->base,
 DRM_MODE_ROTATE_0,
-);
+false, );
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_unlock;
-- 
2.13.6

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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 18:48:07)
> From: Ville Syrjälä 
> 
> Currently we pin a fence on every plane doing tiled scanout. The
> number of planes we have available is fast apporaching the number
> of fences so we really should stop wasting them. Only FBC needs
> the fence on gen4+, so let's use fences only for the primary planes
> on those platforms.
> 
> v2: drop the tiling check from plane_uses_fence() as the obj is
> NULL during initial_plane_config() and we don't rally need the
> check since i915_vma_pin_fence() does the check anyway
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 14 +-
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_fbdev.c   |  2 +-
>  3 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 66b269bc24b9..f2c1bb715e7b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2067,9 +2067,18 @@ static unsigned int intel_surf_alignment(const struct 
> drm_framebuffer *fb,
> }
>  }
>  
> +static bool intel_plane_uses_fence(const struct intel_plane_state 
> *plane_state)
> +{
> +   struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> +   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> +   return INTEL_GEN(dev_priv) < 4 || plane->id == PLANE_PRIMARY;
> +}
> +
>  struct i915_vma *
>  intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
>unsigned int rotation,
> +  bool uses_fence,

(Before long you'll have more than one bool :)

>unsigned long *out_flags)
>  {
> struct drm_device *dev = fb->dev;
> @@ -2122,7 +2131,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> if (IS_ERR(vma))
> goto err;
>  
> -   if (i915_vma_is_map_and_fenceable(vma)) {
> +   if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {

Ok.

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

[Chris Wilson]

Quoting Ville Syrjala (2018-02-21 16:02:30)
> From: Ville Syrjälä 
> 
> Gen2/3 display engine depends on the fence for tiled scanout. So if we
> fail to get a fence fail the entire operation.
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 5d46771d58f6..66b269bc24b9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2123,6 +2123,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> goto err;
>  
> if (i915_vma_is_map_and_fenceable(vma)) {
> +   int ret;
> +
> /* Install a fence for tiled scan-out. Pre-i965 always needs a
>  * fence, whereas 965+ only requires a fence if using
>  * framebuffer compression.  For simplicity, we always, when
> @@ -2139,7 +2141,13 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
>  * something and try to run the system in a "less than 
> optimal"
>  * mode that matches the user configuration.
>  */
> -   if (i915_vma_pin_fence(vma) == 0 && vma->fence)
> +   ret = i915_vma_pin_fence(vma);
> +   if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
> +   vma = ERR_PTR(ret);
> +   goto err;
> +   }
> +
> +   if (ret == 0 && vma->fence)
> *out_flags |= PLANE_HAS_FENCE;
> }

Ok, I'd like to see INTEL_GEN(dev_priv) < 4 be replaced with say
needs_fence (and may be passed in from the caller like wants_fence?).
Then I'm wondering if a 
if (WARN_ON(needs_fence && !(*flags & PLANE_HAS_FENCE))
makes sense.

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

[Chris Wilson]

Quoting James Xiong (2018-02-20 17:48:03)
> From: "Xiong, James" 
> 
> With gem_reuse enabled, when a buffer size is different than
> the sizes of buckets, it is aligned to the next bucket's size,
> which means about 25% more memory than the requested is allocated
> in the worst senario. For example:
> 
> Orignal sizeActual
> 32KB+1Byte  40KB
> .
> .
> .
> 8MB+1Byte   10MB
> .
> .
> .
> 96MB+1Byte  112MB
> 
> This is very memory expensive and make the reuse feature less
> favorable than it deserves to be.

The reuse feature also misses one important source: reusing temporaries
within a batch.
 
> This commit aligns the reuse buffer size on page size instead,
> the buffer whose size falls between bucket[n] and bucket[n+1] is
> put in bucket[n] when it's done; And when searching for a cached
> buffer for reuse, it goes through the cached buffers list in the
> bucket until a cached buffer, whose size is larger than or equal
> to the requested size, is found.

So how many times do you have to allocate a new buffer because you
refused to hand back a slightly larger buffer? Have you checked the
impact on !llc? With mmaps? On how wide a workload?

> Signed-off-by: Xiong, James 
> ---
>  intel/intel_bufmgr_gem.c | 180 
> +--
>  libdrm_lists.h   |   6 ++
>  2 files changed, 101 insertions(+), 85 deletions(-)
> 
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 386da30..5b2d0d0 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -402,11 +402,10 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem 
> *bufmgr_gem,
>  {
> int i;
>  
> -   for (i = 0; i < bufmgr_gem->num_buckets; i++) {
> -   struct drm_intel_gem_bo_bucket *bucket =
> -   _gem->cache_bucket[i];
> -   if (bucket->size >= size) {
> -   return bucket;
> +   for (i = 0; i < bufmgr_gem->num_buckets - 1; i++) {
> +   if (size >= bufmgr_gem->cache_bucket[i].size &&
> +   size < bufmgr_gem->cache_bucket[i+1].size) {
> +   return _gem->cache_bucket[i];

So you never return the last bucket?

Given the ordered set of buckets, the test remains correct even when
every bo within the bucket is not the full size (each bo is still at
least bigger than the previous bucket).

> }
> }
>  
> @@ -685,25 +684,95 @@ drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
>  madv);
>  }
>  
> -/* drop the oldest entries that have been purged by the kernel */
> +/* drop the entries that are older than the given time */
>  static void
>  drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
> -   struct drm_intel_gem_bo_bucket *bucket)
> +   struct drm_intel_gem_bo_bucket *bucket,
> +   time_t time)
>  {
> -   while (!DRMLISTEMPTY(>head)) {
> -   drm_intel_bo_gem *bo_gem;
> -
> -   bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
> - bucket->head.next, head);
> -   if (drm_intel_gem_bo_madvise_internal
> -   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
> -   break;
> -
> -   DRMLISTDEL(_gem->head);
> -   drm_intel_gem_bo_free(_gem->bo);
> +   drm_intel_bo_gem *bo_gem, *temp;
> +   DRMLISTFOREACHENTRYSAFE(bo_gem, temp, >head, head) {
> +   if (bo_gem->free_time >= time) {
> +   drm_intel_gem_bo_madvise_internal
> +   (bufmgr_gem, bo_gem, I915_MADV_DONTNEED);
> +   DRMLISTDEL(_gem->head);
> +   drm_intel_gem_bo_free(_gem->bo);
> +   }

This function is called after the kernel reports that it purged a
buffer, and the intent here is that we find all the buffers that the
kernel purged and evict them. It is not about discarding old buffers,
just throwing out the empty.

Honestly, it's pointless. The cost of having the empty purged bo around
is insignificant (we reclaim a little bit of mmap virtual space
quicker).

> }
>  }
>  
> +static drm_intel_bo_gem *
> +drm_intel_gem_bo_cached_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
> + unsigned long size,
> + uint32_t tiling_mode,
> + unsigned long stride,
> + unsigned long alignment,
> + bool for_render)
> +{
> +   struct drm_intel_gem_bo_bucket *bucket =
> +   drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
> +
> +   if(bucket != NULL) {
> +   drm_intel_bo_gem *bo_gem, *temp_bo_gem;
> +retry:
> +   bo_gem = NULL;
> +   if (for_render) {
> + 

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Remove the ring advancement under preemption

[Chris Wilson]

Quoting Michel Thierry (2018-02-21 17:25:54)
> On 21/02/18 05:32, Chris Wilson wrote:
> > Load an empty ringbuffer for preemption, ignoring the lite-restore
> > workaround as we know the preempt context is always idle before preemption.
> > 
> 
> True, injecting the preempt context shouldn't cause a lite-restore.
> And the restriction was to always have Head!=Tail when attempting lite 
> restore.
> 
> > Note that after some digging by Michal Winiarski, we found that
> > RING_HEAD is no longer being updated (due to inhibiting context save
> > restore) so this patch is already in effect!
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Michal Winiarski 
> > Cc: Michel Thierry 
> > Cc: Michal Wajdeczko 
> > Cc: Tvrtko Ursulin 
> > Cc: Mika Kuoppala 
> 
> Reviewed-by: Michel Thierry 

And pushed. Thanks for the review, at worst this just shows that we have
an issue more readily :)
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Re: [Intel-gfx] [PATCH] drm/i915: Rename drm_i915_gem_request to i915_request

[Chris Wilson]

Quoting Joonas Lahtinen (2018-02-21 18:40:51)
> Quoting Chris Wilson (2018-02-21 11:56:36)
> > We want to de-emphasize the link between the request (dependency,
> > execution and fence tracking) from GEM and so rename the struct from
> > drm_i915_gem_request to i915_request. That is we may implement the GEM
> > user interface on top of requests, but they are an abstraction for
> > tracking execution rather than an implementation detail of GEM. (Since
> > they are not tied to HW, we keep the i915 prefix as opposed to intel.)
> > 
> > In short, the spatch:
> > @@
> > 
> > @@
> > - struct drm_i915_gem_request
> > + struct i915_request
> > 
> > A corollary to contracting the type name, we also harmonise on using
> > 'rq' shorthand for local variables where space if of the essence and
> > repetition makes 'request' unwieldy. For globals and struct members,
> > 'request' is still much preferred for its clarity.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Joonas Lahtinen 
> > Cc: Mika Kuoppala 
> > Cc: Tvrtko Ursulin 
> > Cc: Michał Winiarski 
> > Cc: Michal Wajdeczko 
> 
> Right, should not cause a mayhem when merged now.
> 
> Acked-by: Joonas Lahtinen 

And pushed before the pain starts.
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4)
URL   : https://patchwork.freedesktop.org/series/38441/
State : success

== Summary ==

Series 38441v4 drm/i915/hsw: add missing disabled EUs registers reads
https://patchwork.freedesktop.org/api/1.0/series/38441/revisions/4/mbox/

Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> INCOMPLETE (fi-pnv-d510) fdo#101600
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:412s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:484s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:284s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:479s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:408s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:451s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:410s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:451s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:490s
fi-pnv-d510  total:146  pass:113  dwarn:0   dfail:0   fail:0   skip:32 
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:503s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:516s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:484s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:405s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:389s

1a9284c71b40c7a1e363d2b70f0f4574e4214bbd drm-tip: 2018y-02m-21d-20h-41m-30s UTC 
integration manifest
9ea2d5e8c8fd drm/i915/hsw: add missing disabled EUs registers reads

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8114/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later
URL   : https://patchwork.freedesktop.org/series/38709/
State : failure

== Summary ==

Test kms_plane_multiple:
Subgroup legacy-pipe-b-tiling-none:
skip   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-wait-busy-hang:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Subgroup 2x-dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
fail   -> PASS   (shard-apl) fdo#103481
Test gem_eio:
Subgroup suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#105055
Subgroup in-flight:
incomplete -> PASS   (shard-apl)
Subgroup in-flight-external:
pass   -> INCOMPLETE (shard-apl)
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-nonblocking-fencing:
fail   -> PASS   (shard-apl) fdo#103207

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#105055 https://bugs.freedesktop.org/show_bug.cgi?id=105055
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103207 https://bugs.freedesktop.org/show_bug.cgi?id=103207

shard-apltotal:3275 pass:1712 dwarn:1   dfail:0   fail:13  skip:1547 
time:11710s
shard-hswtotal:3422 pass:1743 dwarn:1   dfail:0   fail:3   skip:1672 
time:11273s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6627s
Blacklisted hosts:
shard-kbltotal:3464 pass:1960 dwarn:1   dfail:0   fail:15  skip:1488 
time:9697s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8107/shards.html
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Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

[Souza, Jose]

On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote:
> On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza
> wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent access by hardware and driver.
> > 
> > Reference: https://01.org/sites/default/files/documentation/intel-g
> > fx-prm-osrc-skl-vol12-display.pdf
> > Page 198 - AUX programming sequence
> > 
> 
> Cc: Ville
> Cc: DK
> > Cc: Rodrigo Vivi 
> > Cc: Jani Nikula 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  9 
> >  drivers/gpu/drm/i915/intel_dp.c  | 50
> > 
> >  drivers/gpu/drm/i915/intel_drv.h |  1 +
> >  3 files changed, 60 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 1412abcb27d4..a62e3c1badab 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5318,6 +5318,7 @@ enum {
> >  #define _DPA_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6401c)
> >  #define _DPA_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64020)
> >  #define _DPA_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64024)
> > +#define _DPA_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6402C)
> >  
> >  #define _DPB_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64110)
> >  #define _DPB_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64114)
> > @@ -5325,6 +5326,7 @@ enum {
> >  #define _DPB_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6411c)
> >  #define _DPB_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64120)
> >  #define _DPB_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64124)
> > +#define _DPB_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6412C)
> >  
> >  #define _DPC_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64210)
> >  #define _DPC_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64214)
> > @@ -5332,6 +5334,7 @@ enum {
> >  #define _DPC_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6421c)
> >  #define _DPC_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64220)
> >  #define _DPC_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64224)
> > +#define _DPC_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6422C)
> >  
> >  #define _DPD_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64310)
> >  #define _DPD_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64314)
> > @@ -5339,6 +5342,7 @@ enum {
> >  #define _DPD_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6431c)
> >  #define _DPD_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64320)
> >  #define _DPD_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64324)
> > +#define _DPD_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6432C)
> >  
> >  #define _DPF_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64510)
> >  #define _DPF_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64514)
> > @@ -5346,6 +5350,7 @@ enum {
> >  #define _DPF_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6451c)
> >  #define _DPF_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64520)
> >  #define _DPF_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64524)
> > +#define _DPF_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6452C)
> >  
> >  #define DP_AUX_CH_CTL(port)_MMIO_PORT(port,
> > _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> >  #define DP_AUX_CH_DATA(port, i)_MMIO(_PORT(port,
> > _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > @@ -5378,6 +5383,10 @@ enum {
> >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
> > 
> 
> 
> I believe _DPA_AUX_CH_MUTEX and _DPB_AUX_CH_MUTEX should be defined
> here along
> with the bits as Jani suggested.
> I don't see any reason to tag that far from the bits and close to CTL
> and DATA.
> 
> > +#define DP_AUX_CH_MUTEX(port)  _MMIO_PORT(port,
> > _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX)
> > +#define   DP_AUX_CH_MUTEX_ENABLE   (1 << 31)
> > +#define   DP_AUX_CH_MUTEX_STATUS   (1 << 30)
> > +
> >  /*
> >   * Computing GMCH M and N values for the Display Port link
> >   *
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index f20b25f98e5a..af07563bafba 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1081,6 +1081,45 @@ static uint32_t
> > intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
> > aux_clock_divider)
> > ;
> >  }
> 

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

[Patchwork]

== Series Details ==

Series: drm/atomic: Call ww_acquire_done after drm_modeset_lock_all
URL   : https://patchwork.freedesktop.org/series/38711/
State : warning

== Summary ==

Test kms_flip:
Subgroup 2x-plain-flip-ts-check:
pass   -> FAIL   (shard-hsw) fdo#100368 +1
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Test perf:
Subgroup enable-disable:
pass   -> FAIL   (shard-apl) fdo#103715
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
pass   -> FAIL   (shard-apl) fdo#101623
Test kms_sysfs_edid_timing:
warn   -> FAIL   (shard-hsw) fdo#100047
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
fail   -> PASS   (shard-apl) fdo#103481
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-bottom-edge:
pass   -> DMESG-WARN (shard-snb)
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-nonblocking-fencing:
fail   -> PASS   (shard-apl) fdo#103207
Test drv_suspend:
Subgroup fence-restore-untiled:
pass   -> SKIP   (shard-snb)

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103207 https://bugs.freedesktop.org/show_bug.cgi?id=103207

shard-apltotal:3300 pass:1729 dwarn:1   dfail:0   fail:15  skip:1553 
time:11773s
shard-hswtotal:3464 pass:1764 dwarn:1   dfail:0   fail:6   skip:1693 
time:11927s
shard-snbtotal:3464 pass:1352 dwarn:2   dfail:0   fail:3   skip:2107 
time:6611s
Blacklisted hosts:
shard-kbltotal:3464 pass:1940 dwarn:18  dfail:4   fail:13  skip:1489 
time:9659s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8108/shards.html
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Re: [Intel-gfx] [PATCH igt 1/2] Iterate over physical engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-21 16:25:34)
> 
> On 21/02/2018 14:45, Chris Wilson wrote:
> > We current have a single for_each_engine() iterator which we use to
> > generate both a set of uABI engines and a set of physical engines.
> > Determining what uABI ring-id corresponds to an actual HW engine is
> > tricky, so pull that out to a library function and introduce
> > for_each_physical_engine() for cases where we want to issue requests
> > once on each HW ring (avoiding aliasing issues).
> 
> As you know I tried to make for_each_engine actually behave like this 
> (iterate physical engines). I still think it would be better / more 
> intuitive, and leave the uABI for a specially named iterator instead. 
> However, I am willing to accept this compromise in order to start moving 
> towards the long overdue cleanup in this respect.

Right, next step would be s/for_each_engine/for_each_uabi_ring/ to catch
the remaining cases, although most now in this case iterate over the
engine static array and igt_require(gem_has_ring()), so that the test
list is stable across machines.

[snip]

> Hm, what I did with intel_execution_engines2 to fake class/instance. 
> Have to think if that could somehow be merged into one. Or perhaps the 
> approach adopted and then when available just switch the implementation 
> to real class/instance.

Yeah, I think of this as an intermediate stepping stone so will be
refined as we refine the uABI. In the meantime, if there are trivial
refactors, no problem, but I wouldn't spend too much effort forcing it
as I think we will end up replacing it.
-Chris
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Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

[Rodrigo Vivi]

On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> 
> Reference: 
> https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf
> Page 198 - AUX programming sequence
>

Cc: Ville
Cc: DK
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  9 
>  drivers/gpu/drm/i915/intel_dp.c  | 50 
> 
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  3 files changed, 60 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1412abcb27d4..a62e3c1badab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5318,6 +5318,7 @@ enum {
>  #define _DPA_AUX_CH_DATA3(dev_priv->info.display_mmio_offset + 0x6401c)
>  #define _DPA_AUX_CH_DATA4(dev_priv->info.display_mmio_offset + 0x64020)
>  #define _DPA_AUX_CH_DATA5(dev_priv->info.display_mmio_offset + 0x64024)
> +#define _DPA_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6402C)
>  
>  #define _DPB_AUX_CH_CTL  (dev_priv->info.display_mmio_offset + 
> 0x64110)
>  #define _DPB_AUX_CH_DATA1(dev_priv->info.display_mmio_offset + 0x64114)
> @@ -5325,6 +5326,7 @@ enum {
>  #define _DPB_AUX_CH_DATA3(dev_priv->info.display_mmio_offset + 0x6411c)
>  #define _DPB_AUX_CH_DATA4(dev_priv->info.display_mmio_offset + 0x64120)
>  #define _DPB_AUX_CH_DATA5(dev_priv->info.display_mmio_offset + 0x64124)
> +#define _DPB_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6412C)
>  
>  #define _DPC_AUX_CH_CTL  (dev_priv->info.display_mmio_offset + 
> 0x64210)
>  #define _DPC_AUX_CH_DATA1(dev_priv->info.display_mmio_offset + 0x64214)
> @@ -5332,6 +5334,7 @@ enum {
>  #define _DPC_AUX_CH_DATA3(dev_priv->info.display_mmio_offset + 0x6421c)
>  #define _DPC_AUX_CH_DATA4(dev_priv->info.display_mmio_offset + 0x64220)
>  #define _DPC_AUX_CH_DATA5(dev_priv->info.display_mmio_offset + 0x64224)
> +#define _DPC_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6422C)
>  
>  #define _DPD_AUX_CH_CTL  (dev_priv->info.display_mmio_offset + 
> 0x64310)
>  #define _DPD_AUX_CH_DATA1(dev_priv->info.display_mmio_offset + 0x64314)
> @@ -5339,6 +5342,7 @@ enum {
>  #define _DPD_AUX_CH_DATA3(dev_priv->info.display_mmio_offset + 0x6431c)
>  #define _DPD_AUX_CH_DATA4(dev_priv->info.display_mmio_offset + 0x64320)
>  #define _DPD_AUX_CH_DATA5(dev_priv->info.display_mmio_offset + 0x64324)
> +#define _DPD_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6432C)
>  
>  #define _DPF_AUX_CH_CTL  (dev_priv->info.display_mmio_offset + 
> 0x64510)
>  #define _DPF_AUX_CH_DATA1(dev_priv->info.display_mmio_offset + 0x64514)
> @@ -5346,6 +5350,7 @@ enum {
>  #define _DPF_AUX_CH_DATA3(dev_priv->info.display_mmio_offset + 0x6451c)
>  #define _DPF_AUX_CH_DATA4(dev_priv->info.display_mmio_offset + 0x64520)
>  #define _DPF_AUX_CH_DATA5(dev_priv->info.display_mmio_offset + 0x64524)
> +#define _DPF_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6452C)
>  
>  #define DP_AUX_CH_CTL(port)  _MMIO_PORT(port, _DPA_AUX_CH_CTL, 
> _DPB_AUX_CH_CTL)
>  #define DP_AUX_CH_DATA(port, i)  _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, 
> _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> @@ -5378,6 +5383,10 @@ enum {
>  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
>


I believe _DPA_AUX_CH_MUTEX and _DPB_AUX_CH_MUTEX should be defined here along
with the bits as Jani suggested.
I don't see any reason to tag that far from the bits and close to CTL and DATA.

> +#define DP_AUX_CH_MUTEX(port)_MMIO_PORT(port, _DPA_AUX_CH_MUTEX, 
> _DPB_AUX_CH_MUTEX)
> +#define   DP_AUX_CH_MUTEX_ENABLE (1 << 31)
> +#define   DP_AUX_CH_MUTEX_STATUS (1 << 30)
> +
>  /*
>   * Computing GMCH M and N values for the Display Port link
>   *
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f20b25f98e5a..af07563bafba 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct 
> intel_dp *intel_dp,
>   aux_clock_divider);
>  }
>  
> +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_dig_port->base.base.dev);
> +
> + if (INTEL_GEN(dev_priv) < 9)
> + return 

[Intel-gfx] [PATCH v3] drm/i915/hsw: add missing disabled EUs registers reads

[Lionel Landwerlin]

It turns out that HSW has a register that tells us how many EUs are
disabled per half-slice (roughly a similar notion to subslice). We
didn't read those registers so far as most userspace drivers didn't
need those values prior to Gen8, but an internal library would like to
have access to this.

Since we already have the getparam interface, there is no harm in
exposing this.

v2: Rename bits value (Joonas)

v3: s/GEM_BUG_ON/MISSING_CASE/ (Joonas)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 
 drivers/gpu/drm/i915/intel_device_info.c | 56 +++-
 2 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fc24ab3a8ca..2e548fb72170 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2807,6 +2807,13 @@ enum i915_power_well_id {
 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
 
 /* Fuse readout registers for GT */
+#define HSW_PAVP_FUSE1 _MMIO(0x911C)
+#define   HSW_F1_EU_DIS_SHIFT  16
+#define   HSW_F1_EU_DIS_MASK   (0x3 << HSW_F1_EU_DIS_SHIFT)
+#define   HSW_F1_EU_DIS_10EUS  0
+#define   HSW_F1_EU_DIS_8EUS   1
+#define   HSW_F1_EU_DIS_6EUS   2
+
 #define CHV_FUSE_GT_MMIO(VLV_DISPLAY_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0  (1 << 10)
 #define   CHV_FGT_DISABLE_SS1  (1 << 11)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..17f6352fe22f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -357,6 +357,58 @@ static void broadwell_sseu_info_init(struct 
drm_i915_private *dev_priv)
sseu->has_eu_pg = 0;
 }
 
+static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+   struct intel_device_info *info = mkwrite_device_info(dev_priv);
+   struct sseu_dev_info *sseu = >sseu;
+   u32 fuse1;
+
+   /*
+* There isn't a register to tell us how many slices/subslices. We
+* work off the PCI-ids here.
+*/
+   switch (info->gt) {
+   default:
+   MISSING_CASE(info->gt);
+   /* fall through */
+   case 1:
+   sseu->slice_mask = BIT(0);
+   sseu->subslice_mask = BIT(0);
+   break;
+   case 2:
+   sseu->slice_mask = BIT(0);
+   sseu->subslice_mask = BIT(0) | BIT(1);
+   break;
+   case 3:
+   sseu->slice_mask = BIT(0) | BIT(1);
+   sseu->subslice_mask = BIT(0) | BIT(1);
+   break;
+   }
+
+   fuse1 = I915_READ(HSW_PAVP_FUSE1);
+   switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
+   case HSW_F1_EU_DIS_10EUS:
+   sseu->eu_per_subslice = 10;
+   break;
+   case HSW_F1_EU_DIS_8EUS:
+   sseu->eu_per_subslice = 8;
+   break;
+   case HSW_F1_EU_DIS_6EUS:
+   sseu->eu_per_subslice = 6;
+   break;
+   default:
+   GEM_BUG_ON(true);
+   break;
+   }
+
+   sseu->eu_total = sseu_subslice_total(sseu) * sseu->eu_per_subslice;
+
+   /* No powergating for you. */
+   sseu->has_slice_pg = 0;
+   sseu->has_subslice_pg = 0;
+   sseu->has_eu_pg = 0;
+}
+
 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 {
u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
@@ -574,7 +626,9 @@ void intel_device_info_runtime_init(struct 
intel_device_info *info)
}
 
/* Initialize slice/subslice/EU info */
-   if (IS_CHERRYVIEW(dev_priv))
+   if (IS_HASWELL(dev_priv))
+   haswell_sseu_info_init(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv))
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-- 
2.16.1

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[Intel-gfx] [PATCH igt v2] Iterate over physical engines

[Chris Wilson]

We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for cases where we want to issue requests
once on each HW ring (avoiding aliasing issues).

v2: Remember can_store_dword for gem_sync

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 lib/igt_gt.c   |  23 ++
 lib/igt_gt.h   |   9 
 tests/amdgpu/amd_prime.c   |   6 +--
 tests/gem_concurrent_all.c |   2 +-
 tests/gem_ctx_create.c |   5 +--
 tests/gem_exec_await.c |  17 +---
 tests/gem_exec_create.c|  17 +---
 tests/gem_exec_fence.c |  16 ++-
 tests/gem_exec_gttfill.c   |  16 +--
 tests/gem_exec_nop.c   |  32 ++
 tests/gem_exec_parallel.c  |  15 +--
 tests/gem_exec_reloc.c |   2 +-
 tests/gem_exec_schedule.c  |  21 ++---
 tests/gem_exec_store.c |   2 +-
 tests/gem_exec_suspend.c   |  20 ++---
 tests/gem_exec_whisper.c   |  15 +--
 tests/gem_ring_sync_loop.c |   2 +-
 tests/gem_spin_batch.c |   5 +--
 tests/gem_sync.c   | 104 -
 19 files changed, 78 insertions(+), 251 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index f70fcb92..e630550b 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -660,3 +660,26 @@ bool gem_has_engine(int gem_fd,
gem_class_instance_to_eb_flags(gem_fd, class,
   instance));
 }
+
+bool gem_ring_is_physical_engine(int fd, unsigned ring)
+{
+   if (ring == I915_EXEC_DEFAULT)
+   return false;
+
+   /* BSD uses an extra flag to chose between aliasing modes */
+   if ((ring & 63) == I915_EXEC_BSD) {
+   bool explicit_bsd = ring & (3 << 13);
+   bool has_bsd2 = gem_has_bsd2(fd);
+   return explicit_bsd ? has_bsd2 : !has_bsd2;
+   }
+
+   return true;
+}
+
+bool gem_ring_has_physical_engine(int fd, unsigned ring)
+{
+   if (!gem_ring_is_physical_engine(fd, ring))
+   return false;
+
+   return gem_has_ring(fd, ring);
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 68592410..4d9d1aa0 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -81,6 +81,15 @@ extern const struct intel_execution_engine {
 e__++) \
for_if (gem_has_ring(fd__, flags__ = e__->exec_id | e__->flags))
 
+#define for_each_physical_engine(fd__, flags__) \
+   for (const struct intel_execution_engine *e__ = 
intel_execution_engines;\
+e__->name; \
+e__++) \
+   for_if (gem_ring_has_physical_engine(fd__, flags__ = 
e__->exec_id | e__->flags))
+
+bool gem_ring_is_physical_engine(int fd, unsigned int ring);
+bool gem_ring_has_physical_engine(int fd, unsigned int ring);
+
 bool gem_can_store_dword(int fd, unsigned int engine);
 
 extern const struct intel_execution_engine2 {
diff --git a/tests/amdgpu/amd_prime.c b/tests/amdgpu/amd_prime.c
index b2f326b4..bb68ccf3 100644
--- a/tests/amdgpu/amd_prime.c
+++ b/tests/amdgpu/amd_prime.c
@@ -179,12 +179,8 @@ static void i915_to_amd(int i915, int amd, 
amdgpu_device_handle device)
struct cork c;
 
nengine = 0;
-   for_each_engine(i915, engine) {
-   if (engine == 0)
-   continue;
-
+   for_each_physical_engine(i915, engine)
engines[nengine++] = engine;
-   }
igt_require(nengine);
 
memset(obj, 0, sizeof(obj));
diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
index 201b491b..3a1097ba 100644
--- a/tests/gem_concurrent_all.c
+++ b/tests/gem_concurrent_all.c
@@ -960,7 +960,7 @@ static igt_hang_t all_hang(void)
execbuf.buffers_ptr = to_user_pointer();
execbuf.buffer_count = 1;
 
-   for_each_engine(fd, engine) {
+   for_each_physical_engine(fd, engine) {
hang = igt_hang_ring(fd, engine);
 
execbuf.flags = engine;
diff --git a/tests/gem_ctx_create.c b/tests/gem_ctx_create.c
index 058445b6..1b32d6c3 100644
--- a/tests/gem_ctx_create.c
+++ b/tests/gem_ctx_create.c
@@ -321,11 +321,8 @@ igt_main
igt_require_gem(fd);
gem_require_contexts(fd);
 
-   for_each_engine(fd, engine) {
-   if (engine == 0)
-   continue;
+   for_each_physical_engine(fd, engine)
all_engines[all_nengine++] = engine;
-   }
igt_require(all_nengine);
 
if (gem_uses_full_ppgtt(fd)) {
diff --git a/tests/gem_exec_await.c b/tests/gem_exec_await.c
index e19363c4..fccc24d9 100644
--- a/tests/gem_exec_await.c
+++ b/tests/gem_exec_await.c
@@ -44,17 +44,6 @@ static 

[Intel-gfx] [PATCH v4] drm/i915/hsw: add missing disabled EUs registers reads

[Lionel Landwerlin]

It turns out that HSW has a register that tells us how many EUs are
disabled per half-slice (roughly a similar notion to subslice). We
didn't read those registers so far as most userspace drivers didn't
need those values prior to Gen8, but an internal library would like to
have access to this.

Since we already have the getparam interface, there is no harm in
exposing this.

v2: Rename bits value (Joonas)

v3: s/GEM_BUG_ON/MISSING_CASE/ (Joonas)

v4: s/GEM_BUG_ON/MISSING_CASE/ again... (Lionel)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 
 drivers/gpu/drm/i915/intel_device_info.c | 57 +++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fc24ab3a8ca..2e548fb72170 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2807,6 +2807,13 @@ enum i915_power_well_id {
 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
 
 /* Fuse readout registers for GT */
+#define HSW_PAVP_FUSE1 _MMIO(0x911C)
+#define   HSW_F1_EU_DIS_SHIFT  16
+#define   HSW_F1_EU_DIS_MASK   (0x3 << HSW_F1_EU_DIS_SHIFT)
+#define   HSW_F1_EU_DIS_10EUS  0
+#define   HSW_F1_EU_DIS_8EUS   1
+#define   HSW_F1_EU_DIS_6EUS   2
+
 #define CHV_FUSE_GT_MMIO(VLV_DISPLAY_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0  (1 << 10)
 #define   CHV_FGT_DISABLE_SS1  (1 << 11)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..1c780cc4cd48 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -357,6 +357,59 @@ static void broadwell_sseu_info_init(struct 
drm_i915_private *dev_priv)
sseu->has_eu_pg = 0;
 }
 
+static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+   struct intel_device_info *info = mkwrite_device_info(dev_priv);
+   struct sseu_dev_info *sseu = >sseu;
+   u32 fuse1;
+
+   /*
+* There isn't a register to tell us how many slices/subslices. We
+* work off the PCI-ids here.
+*/
+   switch (info->gt) {
+   default:
+   MISSING_CASE(info->gt);
+   /* fall through */
+   case 1:
+   sseu->slice_mask = BIT(0);
+   sseu->subslice_mask = BIT(0);
+   break;
+   case 2:
+   sseu->slice_mask = BIT(0);
+   sseu->subslice_mask = BIT(0) | BIT(1);
+   break;
+   case 3:
+   sseu->slice_mask = BIT(0) | BIT(1);
+   sseu->subslice_mask = BIT(0) | BIT(1);
+   break;
+   }
+
+   fuse1 = I915_READ(HSW_PAVP_FUSE1);
+   switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
+   default:
+   MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
+HSW_F1_EU_DIS_SHIFT);
+   /* fall through */
+   case HSW_F1_EU_DIS_10EUS:
+   sseu->eu_per_subslice = 10;
+   break;
+   case HSW_F1_EU_DIS_8EUS:
+   sseu->eu_per_subslice = 8;
+   break;
+   case HSW_F1_EU_DIS_6EUS:
+   sseu->eu_per_subslice = 6;
+   break;
+   }
+
+   sseu->eu_total = sseu_subslice_total(sseu) * sseu->eu_per_subslice;
+
+   /* No powergating for you. */
+   sseu->has_slice_pg = 0;
+   sseu->has_subslice_pg = 0;
+   sseu->has_eu_pg = 0;
+}
+
 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 {
u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
@@ -574,7 +627,9 @@ void intel_device_info_runtime_init(struct 
intel_device_info *info)
}
 
/* Initialize slice/subslice/EU info */
-   if (IS_CHERRYVIEW(dev_priv))
+   if (IS_HASWELL(dev_priv))
+   haswell_sseu_info_init(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv))
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-- 
2.16.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scanout fence fixes/cleanups (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/38714/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ec43511e598e drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout
a686f373992f drm/i915: Only pin the fence for primary planes (and gen2/3)
-:66: WARNING: line over 80 characters
#66: FILE: drivers/gpu/drm/i915/intel_display.c:12757:
+
intel_plane_uses_fence(to_intel_plane_state(new_state)),

total: 0 errors, 1 warnings, 0 checks, 62 lines checked
5be9e603df0c drm/i915: Clean up fbc vs. plane checks
1b9e5a1fcd03 drm/i915: Require fence only for FBC capable planes
1a5caafb2917 drm/i915: Extract intel_plane_{pin, unpin}_fb()
a88746960907 drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

[Guang (George) Bai]

On Wed, 21 Feb 2018 20:48:07 +0200
Ville Syrjala  wrote:

> From: Ville Syrjälä 
> 
> Currently we pin a fence on every plane doing tiled scanout. The
> number of planes we have available is fast apporaching the number
> of fences so we really should stop wasting them. Only FBC needs
> the fence on gen4+, so let's use fences only for the primary planes
> on those platforms.
> 
> v2: drop the tiling check from plane_uses_fence() as the obj is
> NULL during initial_plane_config() and we don't rally need the
> check since i915_vma_pin_fence() does the check anyway
> 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 14 +-
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_fbdev.c   |  2 +-
>  3 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c index
> 66b269bc24b9..f2c1bb715e7b 100644 ---
> a/drivers/gpu/drm/i915/intel_display.c +++
> b/drivers/gpu/drm/i915/intel_display.c @@ -2067,9 +2067,18 @@ static
> unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, }
>  }
>  
> +static bool intel_plane_uses_fence(const struct intel_plane_state
> *plane_state) +{
> + struct intel_plane *plane =
> to_intel_plane(plane_state->base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> + return INTEL_GEN(dev_priv) < 4 || plane->id == PLANE_PRIMARY;
> +}
> +
>  struct i915_vma *
>  intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
>  unsigned int rotation,
> +bool uses_fence,
>  unsigned long *out_flags)
>  {
>   struct drm_device *dev = fb->dev;
> @@ -2122,7 +2131,7 @@ intel_pin_and_fence_fb_obj(struct
> drm_framebuffer *fb, if (IS_ERR(vma))
>   goto err;
>  
> - if (i915_vma_is_map_and_fenceable(vma)) {
> + if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
>   int ret;
>  
>   /* Install a fence for tiled scan-out. Pre-i965
> always needs a @@ -2836,6 +2845,7 @@
> intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> intel_state->vma = intel_pin_and_fence_fb_obj(fb,
>  primary->state->rotation,
> +
> intel_plane_uses_fence(intel_state), _state->flags);
>   mutex_unlock(>struct_mutex);
>   if (IS_ERR(intel_state->vma)) {
> @@ -12744,6 +12754,7 @@ intel_prepare_plane_fb(struct drm_plane
> *plane, 
>   vma = intel_pin_and_fence_fb_obj(fb,
>new_state->rotation,
> +
> intel_plane_uses_fence(to_intel_plane_state(new_state)),
> _intel_plane_state(new_state)->flags); if (!IS_ERR(vma))
>   to_intel_plane_state(new_state)->vma = vma;
> @@ -13162,6 +13173,7 @@ intel_legacy_cursor_update(struct drm_plane
> *plane, } else {
>   vma = intel_pin_and_fence_fb_obj(fb,
>new_plane_state->rotation,
> +  false,
>
> _intel_plane_state(new_plane_state)->flags);
>   if (IS_ERR(vma)) {
>   DRM_DEBUG_KMS("failed to pin object\n");
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h index 50874f4035cf..e3f78fdae859
> 100644 --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1508,6 +1508,7 @@ void intel_release_load_detect_pipe(struct
> drm_connector *connector, struct i915_vma *
>  intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
>  unsigned int rotation,
> +bool uses_fence,
>  unsigned long *out_flags);
>  void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
>  struct drm_framebuffer *
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> b/drivers/gpu/drm/i915/intel_fbdev.c index 055f409f8b75..6f12adc06365
> 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -215,7 +215,7 @@ static int intelfb_create(struct drm_fb_helper
> *helper, */
>   vma = intel_pin_and_fence_fb_obj(>fb->base,
>DRM_MODE_ROTATE_0,
> -  );
> +  false, );
>   if (IS_ERR(vma)) {
>   ret = PTR_ERR(vma);
>   goto out_unlock;

All these fence and fbc related changes will fix the gen9lp fence
starvation problems from virtualization use cases.
Thanks,
Guang
 
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[Intel-gfx] [PULL] drm-misc-next

[Sean Paul]

Hi Dave,
A delicious collection of fixes and features for you this week. The backlight
helpers have been picked up by Lee Jones in the backlight tree, so hopefully
no fireworks there. Everything else is business as usual.

drm-misc-next-2018-02-21:
drm-misc-next for 4.17:

Cross-subsystem Changes:
- Backlight helpers to enable/disable and find devices in dt (Meghana)

Core Changes:
- Documentation improvements (Chris/Daniel/Jani)
- simple_kms_helper: Add mode_valid() support (Linus)
- mm: Fix bug in interval_tree causing nodes to be out-of-order (Chris)

Driver Changes:
- tinydrm/panel: Use the new backlight helpers (Meghana)
- rockchip: Support gem_prime_import_sg_table + some fixes (Various)
- sun4i: Add A83T HDMI support using dw-hdmi (Jernej)

Cc: Meghana Madhyastha 
Cc: Jani Nikula 
Cc: Daniel Vetter 
Cc: Chris Wilson 
Cc: Linus Walleij 
Cc: Heiko Stuebner 
Cc: Jernej Skrabec 

Cheers, Sean


The following changes since commit 933519a5a269d8460450545adefcb5caec622cac:

  Merge tag 'topic/hdcp-2018-02-13' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2018-02-16 09:36:04 
+1000)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2018-02-21

for you to fetch changes up to 2b91e3c43b4f3d3cd4d84a31cfbe6b165d89b70e:

  drm/omapdrm: Use of_find_backlight helper (2018-02-20 11:07:22 -0500)


drm-misc-next for 4.17:

Cross-subsystem Changes:
- Backlight helpers to enable/disable and find devices in dt (Meghana)

Core Changes:
- Documentation improvements (Chris/Daniel/Jani)
- simple_kms_helper: Add mode_valid() support (Linus)
- mm: Fix bug in interval_tree causing nodes to be out-of-order (Chris)

Driver Changes:
- tinydrm/panel: Use the new backlight helpers (Meghana)
- rockchip: Support gem_prime_import_sg_table + some fixes (Various)
- sun4i: Add A83T HDMI support using dw-hdmi (Jernej)

Cc: Meghana Madhyastha 
Cc: Jani Nikula 
Cc: Daniel Vetter 
Cc: Chris Wilson 
Cc: Linus Walleij 
Cc: Heiko Stuebner 
Cc: Jernej Skrabec 


Anusha Srivatsa (1):
  drm: Add DPCD definitions for DP 1.4 FEC feature

Chris Wilson (3):
  drm: Fix kerneldoc warnings for drm_lease
  dma-buf/sw_sync: Fix kerneldoc warnings
  drm: Use idr_init_base(1) when using id==0 for invalid

Chris Zhong (1):
  Documentation: bindings: add dt documentation for cdn DP controller

Colin Ian King (1):
  drm/bochs: make structure bochs_bo_driver static

Daniel Vetter (6):
  drm/todo: Add idr_init_base todo
  drm/docs: Discourage adding more to kms-properties.csv
  drm/docs: Align layout of optional plane blending properties
  drm/docs: Document "scaling mode" property better
  drm/doc: Polish for drm_mode_parse_command_line_for_connector
  drm/doc: Use new substruct support

Fabio Estevam (2):
  drm/rockchip: dsi: Remove unnecessary platform_get_resource() error check
  drm/rockchip: inno_hdmi: Remove unnecessary platform_get_resource() error 
check

Giulio Benetti (1):
  drm/sun4i: fix HSYNC and VSYNC polarity

Haixia Shi (1):
  drm/rockchip: support prime import sg table

Jani Nikula (1):
  drm: add documentation for tv connector state margins

Jernej Skrabec (8):
  drm/bridge/synopsys: dw-hdmi: Enable workaround for v1.32a
  drm/bridge/synopsys: dw-hdmi: Export some PHY related functions
  drm/bridge/synopsys: dw-hdmi: don't clobber drvdata
  dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
  drm/sun4i: Add has_channel_0 TCON quirk
  drm/sun4i: Add support for A83T second TCON
  drm/sun4i: Add support for A83T second DE2 mixer
  drm/sun4i: Implement A83T HDMI driver

Joe Moriarty (2):
  drm: NULL pointer dereference [null-pointer-deref] (CWE 476) problem
  drm: NULL pointer dereference [null-pointer-deref] (CWE 476) problem

Linus Walleij (1):
  drm: simple_kms_helper: Add mode_valid() callback support

Maxime Ripard (1):
  drm/rcar-du: dw-hdmi: Fix compilation

Meghana Madhyastha (10):
  video: backlight: Add helpers to enable and disable backlight
  video: backlight: Add of_find_backlight helper in backlight.c
  video: backlight: Add devres versions of of_find_backlight
  drm/tinydrm: Convert tinydrm_enable/disable_backlight to 
backlight_enable/disable
  drm/tinydrm: Replace tinydrm_of_find_backlight with of_find_backlight
  drm/tinydrm: Call devres version of of_find_backlight
  drm/panel: Use backlight_enable/disable helpers
  drm/omapdrm: Use 

Re: [Intel-gfx] [PATCH igt 1/2] Iterate over physical engines

[Chris Wilson]

Quoting Chris Wilson (2018-02-21 14:45:21)
> diff --git a/tests/gem_sync.c b/tests/gem_sync.c
> index d70515ea..788fafc3 100644
> --- a/tests/gem_sync.c
> +++ b/tests/gem_sync.c
> @@ -86,23 +86,9 @@ sync_ring(int fd, unsigned ring, int num_children, int 
> timeout)
> int num_engines = 0;
>  
> if (ring == ~0u) {
> -   const struct intel_execution_engine *e;
> -
> -   for (e = intel_execution_engines; e->name; e++) {
> -   if (e->exec_id == 0)
> -   continue;
> -
> -   if (!gem_has_ring(fd, e->exec_id | e->flags))
> -   continue;
> -
> -   if (e->exec_id == I915_EXEC_BSD) {
> -   int is_bsd2 = e->flags != 0;
> -   if (gem_has_bsd2(fd) != is_bsd2)
> -   continue;
> -   }
> -
> -   names[num_engines] = e->name;
> -   engines[num_engines++] = e->exec_id | e->flags;
> +   for_each_physical_engine(fd, ring) {
> +   names[num_engines] = e__->name;
> +   engines[num_engines++] = ring;
> if (num_engines == ARRAY_SIZE(engines))
> break;
> }
> @@ -200,26 +186,9 @@ store_ring(int fd, unsigned ring, int num_children, int 
> timeout)
> int num_engines = 0;
>  
> if (ring == ~0u) {
> -   const struct intel_execution_engine *e;
> -
> -   for (e = intel_execution_engines; e->name; e++) {
> -   if (e->exec_id == 0)
> -   continue;
> -
> -   if (!gem_has_ring(fd, e->exec_id | e->flags))
> -   continue;
> -
> -   if (!gem_can_store_dword(fd, e->exec_id | e->flags))
> -   continue;
> -
> -   if (e->exec_id == I915_EXEC_BSD) {
> -   int is_bsd2 = e->flags != 0;
> -   if (gem_has_bsd2(fd) != is_bsd2)
> -   continue;
> -   }
> -
> -   names[num_engines] = e->name;
> -   engines[num_engines++] = e->exec_id | e->flags;
> +   for_each_physical_engine(fd, ring) {
> +   names[num_engines] = e__->name;
> +   engines[num_engines++] = ring;
> if (num_engines == ARRAY_SIZE(engines))
> break;
> }

So I missed the stores inside gem_sync, which require
gem_can_store_dword() protection.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Add a GEM_TRACE to show when the context is completed

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Add a GEM_TRACE to show when the context is 
completed
URL   : https://patchwork.freedesktop.org/series/38707/
State : success

== Summary ==

Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-nonblocking-fencing:
fail   -> PASS   (shard-apl) fdo#103207
Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +2
Test kms_plane_multiple:
Subgroup legacy-pipe-b-tiling-none:
skip   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-wait-busy-hang:
skip   -> PASS   (shard-snb)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
fail   -> PASS   (shard-apl) fdo#103481
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test gem_eio:
Subgroup in-flight:
incomplete -> PASS   (shard-apl)

fdo#103207 https://bugs.freedesktop.org/show_bug.cgi?id=103207
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3369 pass:1764 dwarn:1   dfail:0   fail:13  skip:1589 
time:12067s
shard-hswtotal:3464 pass:1766 dwarn:1   dfail:0   fail:3   skip:1693 
time:11853s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6699s
Blacklisted hosts:
shard-kbltotal:3464 pass:1962 dwarn:1   dfail:0   fail:14  skip:1487 
time:9662s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8106/shards.html
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Re: [Intel-gfx] [PATCH] drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

[Daniel Vetter]

On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote:
> After we acquired all generic modeset locks in drm_modeset_lock_all, it's
> unsafe acquire any other so just mark acquisition as done.
> 
> Atomic drivers shouldn't use drm_modeset_lock_all.
> 
> Signed-off-by: Maarten Lankhorst 

Reviewed-by: Daniel Vetter 

Also, I'm pretty much expecting to regret this like all the other
ww_acquire_done patches I've acked, but where's the fun in not trying :-)

Cheers, Daniel

> ---
>  drivers/gpu/drm/drm_modeset_lock.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/drm_modeset_lock.c 
> b/drivers/gpu/drm/drm_modeset_lock.c
> index 963e23db0fe7..8a5100685875 100644
> --- a/drivers/gpu/drm/drm_modeset_lock.c
> +++ b/drivers/gpu/drm/drm_modeset_lock.c
> @@ -113,6 +113,7 @@ void drm_modeset_lock_all(struct drm_device *dev)
>   kfree(ctx);
>   return;
>   }
> + ww_acquire_done(>ww_ctx);
>  
>   WARN_ON(config->acquire_ctx);
>  
> -- 
> 2.16.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Support engine busy stats

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL   : https://patchwork.freedesktop.org/series/38717/
State : failure

== Summary ==

Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy 
stats
https://patchwork.freedesktop.org/api/1.0/series/38717/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-FAIL (fi-skl-6260u)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:413s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:478s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:463s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:415s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:281s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:505s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:379s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:405s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:409s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:446s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:487s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:583s
fi-skl-6260u total:288  pass:267  dwarn:0   dfail:1   fail:0   skip:20  
time:427s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:402s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:428s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:512s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:388s

562a3886d1cd6e2763a022037e6090d7ceb00ee3 drm-tip: 2018y-02m-21d-18h-35m-44s UTC 
integration manifest
bb48a00cb0a5 drm/i915: GuC test run
dc87ce86e08d drm/i915/guc: Support engine busy stats

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8112/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Scanout fence fixes/cleanups (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/38714/
State : success

== Summary ==

Series 38714v3 drm/i915: Scanout fence fixes/cleanups
https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/3/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:416s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:451s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:558s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:412s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:506s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:386s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:406s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:446s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:417s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:449s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:492s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:585s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:436s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:478s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:405s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:426s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:400s

562a3886d1cd6e2763a022037e6090d7ceb00ee3 drm-tip: 2018y-02m-21d-18h-35m-44s UTC 
integration manifest
a88746960907 drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation
1a5caafb2917 drm/i915: Extract intel_plane_{pin, unpin}_fb()
1b9e5a1fcd03 drm/i915: Require fence only for FBC capable planes
5be9e603df0c drm/i915: Clean up fbc vs. plane checks
a686f373992f drm/i915: Only pin the fence for primary planes (and gen2/3)
ec43511e598e drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8113/issues.html
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Re: [Intel-gfx] [PATCH] drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

[Harry Wentland]

On 2018-02-21 01:36 PM, Daniel Vetter wrote:
> On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote:
>> After we acquired all generic modeset locks in drm_modeset_lock_all, it's
>> unsafe acquire any other so just mark acquisition as done.
>>
>> Atomic drivers shouldn't use drm_modeset_lock_all.
>>
>> Signed-off-by: Maarten Lankhorst 
> 
> Reviewed-by: Daniel Vetter 
> 
> Also, I'm pretty much expecting to regret this like all the other
> ww_acquire_done patches I've acked, but where's the fun in not trying :-)
> 

This shouldn't really hurt anything, other than throw DEBUG warnings if 
DEBUG_MUTEXES is on.

Acked-by: Harry Wentland 

Harry

> Cheers, Daniel
> 
>> ---
>>  drivers/gpu/drm/drm_modeset_lock.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/drm_modeset_lock.c 
>> b/drivers/gpu/drm/drm_modeset_lock.c
>> index 963e23db0fe7..8a5100685875 100644
>> --- a/drivers/gpu/drm/drm_modeset_lock.c
>> +++ b/drivers/gpu/drm/drm_modeset_lock.c
>> @@ -113,6 +113,7 @@ void drm_modeset_lock_all(struct drm_device *dev)
>>  kfree(ctx);
>>  return;
>>  }
>> +ww_acquire_done(>ww_ctx);
>>  
>>  WARN_ON(config->acquire_ctx);
>>  
>> -- 
>> 2.16.1
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL   : https://patchwork.freedesktop.org/series/38717/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
dc87ce86e08d drm/i915/guc: Support engine busy stats
-:33: WARNING: line over 80 characters
#33: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:727:
+   
intel_engine_context_in(last->engine);

total: 0 errors, 1 warnings, 0 checks, 44 lines checked
bb48a00cb0a5 drm/i915: GuC test run

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Re: [Intel-gfx] [PATCH] drm/i915: Rename drm_i915_gem_request to i915_request

[Joonas Lahtinen]

Quoting Chris Wilson (2018-02-21 11:56:36)
> We want to de-emphasize the link between the request (dependency,
> execution and fence tracking) from GEM and so rename the struct from
> drm_i915_gem_request to i915_request. That is we may implement the GEM
> user interface on top of requests, but they are an abstraction for
> tracking execution rather than an implementation detail of GEM. (Since
> they are not tied to HW, we keep the i915 prefix as opposed to intel.)
> 
> In short, the spatch:
> @@
> 
> @@
> - struct drm_i915_gem_request
> + struct i915_request
> 
> A corollary to contracting the type name, we also harmonise on using
> 'rq' shorthand for local variables where space if of the essence and
> repetition makes 'request' unwieldy. For globals and struct members,
> 'request' is still much preferred for its clarity.
> 
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Mika Kuoppala 
> Cc: Tvrtko Ursulin 
> Cc: Michał Winiarski 
> Cc: Michal Wajdeczko 

Right, should not cause a mayhem when merged now.

Acked-by: Joonas Lahtinen 

Regards, Joonas
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Re: [Intel-gfx] [PATCH] drm/i915/hsw: add missing disabled EUs registers reads

[Joonas Lahtinen]

Quoting Lionel Landwerlin (2018-02-16 17:31:01)
> +static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +   struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +   struct sseu_dev_info *sseu = >sseu;
> +   u32 fuse1;
> +
> +   /*
> +* There isn't a register to tell us how many slices/subslices. We
> +* work off the PCI-ids here.
> +*/
> +   switch (info->gt) {
> +   case 1:
> +   sseu->slice_mask = BIT(0);
> +   sseu->subslice_mask = BIT(0);
> +   break;
> +   case 2:
> +   sseu->slice_mask = BIT(0);
> +   sseu->subslice_mask = BIT(0) | BIT(1);
> +   break;
> +   case 3:
> +   sseu->slice_mask = BIT(0) | BIT(1);
> +   sseu->subslice_mask = BIT(0) | BIT(1);
> +   break;
> +   default:
> +   GEM_BUG_ON(true);

MISSING_CASE() and maybe return GT1 values in the default case? So how
about:

default:
MISSING_CASE(info->gt);
case 1:
...

> +   break;
> +   }
> +
> +   fuse1 = I915_READ(HSW_PAVP_FUSE1);
> +   switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> +   case HSW_F1_EU_DIS_MASK_10EUS:
> +   sseu->eu_per_subslice = 10;
> +   break;
> +   case HSW_F1_EU_DIS_MASK_8EUS:
> +   sseu->eu_per_subslice = 8;
> +   break;
> +   case HSW_F1_EU_DIS_MASK_6EUS:
> +   sseu->eu_per_subslice = 6;
> +   break;
> +   default:
> +   GEM_BUG_ON(true);
> +   break;

Ditto.

With at least s/GEM_BUG_ON(true)/MISSING_CASE(val)/, this is:

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
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Re: [Intel-gfx] [PATCH] drm/doc: Fix documentation for _vblank_restore().

[Daniel Vetter]

On Tue, Feb 20, 2018 at 11:39:08PM -0800, Dhinakaran Pandiyan wrote:
> No code changes, fixes doc build warnings and polish some doc text.
> 
> Reported-by: Daniel Vetter 
> Cc: Rodrigo Vivi 
> Cc: Daniel Vetter 
> Signed-off-by: Dhinakaran Pandiyan 

Thanks for the quick follow-up. Patch applied.
-Daniel

> ---
>  drivers/gpu/drm/drm_vblank.c | 22 ++
>  1 file changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
> index c781cb426bf1..51041eec0047 100644
> --- a/drivers/gpu/drm/drm_vblank.c
> +++ b/drivers/gpu/drm/drm_vblank.c
> @@ -1238,12 +1238,15 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc)
>  EXPORT_SYMBOL(drm_crtc_vblank_on);
>  
>  /**
> - * drm_vblank_restore - estimated vblanks using timestamps and update it.
> + * drm_vblank_restore - estimate missed vblanks and update vblank count.
> + * @dev: DRM device
> + * @pipe: CRTC index
>   *
>   * Power manamement features can cause frame counter resets between vblank
> - * disable and enable. Drivers can then use this function in their
> - * _crtc_funcs.enable_vblank implementation to estimate the vblanks since
> - * the last _crtc_funcs.disable_vblank.
> + * disable and enable. Drivers can use this function in their
> + * _crtc_funcs.enable_vblank implementation to estimate missed vblanks 
> since
> + * the last _crtc_funcs.disable_vblank using timestamps and update the
> + * vblank counter.
>   *
>   * This function is the legacy version of drm_crtc_vblank_restore().
>   */
> @@ -1284,11 +1287,14 @@ void drm_vblank_restore(struct drm_device *dev, 
> unsigned int pipe)
>  EXPORT_SYMBOL(drm_vblank_restore);
>  
>  /**
> - * drm_crtc_vblank_restore - estimate vblanks using timestamps and update it.
> + * drm_crtc_vblank_restore - estimate missed vblanks and update vblank count.
> + * @crtc: CRTC in question
> + *
>   * Power manamement features can cause frame counter resets between vblank
> - * disable and enable. Drivers can then use this function in their
> - * _crtc_funcs.enable_vblank implementation to estimate the vblanks since
> - * the last _crtc_funcs.disable_vblank.
> + * disable and enable. Drivers can use this function in their
> + * _crtc_funcs.enable_vblank implementation to estimate missed vblanks 
> since
> + * the last _crtc_funcs.disable_vblank using timestamps and update the
> + * vblank counter.
>   */
>  void drm_crtc_vblank_restore(struct drm_crtc *crtc)
>  {
> -- 
> 2.14.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: warning for lib: Skip aliased bsd ABI ring if bsd2 is available (rev2)

[Patchwork]

== Series Details ==

Series: lib: Skip aliased bsd ABI ring if bsd2 is available (rev2)
URL   : https://patchwork.freedesktop.org/series/38690/
State : warning

== Summary ==

IGT patchset tested on top of latest successful build
960e55a87d7b7d7385063e37cc9f281df2be8037 igt/gem_ctx_isolation: Check isolation 
of registers between contexts

with latest DRM-Tip kernel build CI_DRM_3816
42d073db2a85 drm-tip: 2018y-02m-21d-14h-03m-58s UTC integration manifest

No testlist changes.

Test gem_exec_basic:
Subgroup basic-bsd:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-6260u)
pass   -> SKIP   (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
Subgroup gtt-bsd:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-6260u)
pass   -> SKIP   (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
Subgroup readonly-bsd:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-6260u)
pass   -> SKIP   (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
Test gem_exec_store:
Subgroup basic-bsd:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-skl-6260u)
pass   -> SKIP   (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
fail   -> PASS   (fi-ivb-3520m)
pass   -> FAIL   (fi-skl-guc) fdo#103191
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
fail   -> PASS   (fi-ivb-3520m)
Subgroup suspend-read-crc-pipe-c:
fail   -> PASS   (fi-ivb-3520m)
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:417s
fi-bdw-gvtdvmtotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:376s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:490s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:286s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:287s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:385s
fi-ilk-650   total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  
time:408s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:452s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:452s
fi-kbl-7560u total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:492s
fi-kbl-7567u total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:448s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:599s

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Scanout fence fixes/cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Scanout fence fixes/cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/38714/
State : failure

== Summary ==

Series 38714v2 drm/i915: Scanout fence fixes/cleanups
https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/2/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-ivb-3520m)
pass   -> INCOMPLETE (fi-ivb-3770)
pass   -> INCOMPLETE (fi-byt-j1900)
pass   -> INCOMPLETE (fi-byt-n2820)
pass   -> INCOMPLETE (fi-hsw-4770)
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:416s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:481s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:286s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:475s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-byt-n2820 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:281s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ilk-650   total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  
time:407s
fi-ivb-3520m total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ivb-3770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:448s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:490s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:583s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:424s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:519s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:485s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:435s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:396s

42d073db2a8593a8d1832037ffe0988403031568 drm-tip: 2018y-02m-21d-14h-03m-58s UTC 
integration manifest
0225359291c9 drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation
39994518 drm/i915: Extract intel_plane_{pin, unpin}_fb()
097680894b64 drm/i915: Require fence only for FBC capable planes
8219c0edc31e drm/i915: Clean up fbc vs. plane checks
b5042b8f97b3 drm/i915: Only pin the fence for primary planes (and gen2/3)
c4c108df218b drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8111/issues.html
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Re: [Intel-gfx] [PATCH 00/16] Adding NV12 support

[Maarten Lankhorst]

Op 21-02-18 om 11:20 schreef Vidya Srinivas:
> This patch series is adding NV12 support for Broxton display after rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
>
> Previous revision history:
> The first version of patches were reviewed when floated by Chandra in 2015
> but currently there was a design change with respect to
> - the way fb offset is handled
> - the way rotation is handled
> Current NV12 patch series has been ported as per the
> current changes on drm-tip
>
> Review comments from Ville (12th June 2017) have been addressed Review
> comments from Clinton A Taylor (7th July 2017) have been addressed
>
> Review comments from Clinton A Taylor (10th July 2017)
>   have been addressed. Had missed out tested-by/reviewed-by in the 
> patches.
>
>   Fixed that error in this series.
>   Review comments from Ville (11th July 2017) addressed.
>   Review comments from Paauwe, Bob (29th July 2017) addressed.
>
> Update from rev 28 Aug 2017
>   Rebased the series.
>   Tested with IGT for rotation, sprite and tiling combinations.
>   IGT Links:
>   https://patchwork.kernel.org/patch/9995943/
>   https://patchwork.kernel.org/patch/9995945/
>   Review comments by Maarten are addressed in this series.
>   NV12 enabled for Gen10.
>   Review comments from Shashank Sharma are addressed.
>   IGT debug_fs test failure fixed.
>
> Update from previous version:
>   Added reviewed-by tag from Shashank Sharma for few patches
>   Addressed review comments from Shashank Sharma in few patches
>   Rebased the series
>
> Chandra Konduru (6):
>   drm/i915: Set scaler mode for NV12
>   drm/i915: Update format_is_yuv() to include NV12
>   drm/i915: Upscale scaler max scale for NV12
>   drm/i915: Add NV12 as supported format for primary plane
>   drm/i915: Add NV12 as supported format for sprite plane
>   drm/i915: Add NV12 support to intel_framebuffer_init
>
> Mahesh Kumar (9):
>   drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
>   drm/i915/skl+: refactor WM calculation for NV12
>   drm/i915/skl+: add NV12 in skl_format_to_fourcc
>   drm/i915/skl+: support verification of DDB HW state for NV12
>   drm/i915/skl+: NV12 related changes for WM
>   drm/i915/skl+: pass skl_wm_level struct to wm compute func
>   drm/i915/skl+: make sure higher latency level has higher wm value
>   drm/i915/skl+: nv12 workaround disable WM level 1-7
>   drm/i915/skl: split skl_compute_ddb function
>
> Vidya Srinivas (1):
>   drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
>
>  drivers/gpu/drm/i915/i915_drv.h  |  10 +-
>  drivers/gpu/drm/i915/i915_reg.h  |   8 +
>  drivers/gpu/drm/i915/intel_atomic.c  |  13 +-
>  drivers/gpu/drm/i915/intel_display.c |  59 -
>  drivers/gpu/drm/i915/intel_drv.h |   9 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 438 
> ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |  20 +-
>  7 files changed, 369 insertions(+), 188 deletions(-)
>
This patch series still has FIFO underruns on kms_plane@pixel-format-* and 
kms_plane_scaling, could this please be fixed before this gets merged?

https://patchwork.freedesktop.org/series/28103/ Fi.CI.IGT

and also visible on

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8103/shards.html

~Maarten

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Remove the ring advancement under preemption

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Remove the ring advancement under preemption
URL   : https://patchwork.freedesktop.org/series/38698/
State : success

== Summary ==

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
fail   -> PASS   (shard-apl) fdo#103481
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test gem_eio:
Subgroup in-flight:
incomplete -> PASS   (shard-apl)
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test drv_suspend:
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-snb)

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873

shard-apltotal:3369 pass:1765 dwarn:1   dfail:0   fail:13  skip:1589 
time:12049s
shard-hswtotal:3464 pass:1766 dwarn:1   dfail:0   fail:3   skip:1693 
time:11823s
shard-snbtotal:3464 pass:1356 dwarn:1   dfail:0   fail:3   skip:2104 
time:6643s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8105/shards.html
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[Intel-gfx] Updated drm-intel-testing

[Joonas Lahtinen]

Hi all,

Mostly fixes in this tag. QA/testing could emphasis on CNL hardware as we're
removing the alpha_support flag for it.

Regards, Joonas
---
The following changes tagged drm-intel-testing-2018-02-21:

drm-intel-next-2018-02-21:

Driver Changes:

- Lift alpha_support protection from Cannonlake (Rodrigo)
* Meaning the driver should mostly work for the hardware we had
  at our disposal when testing
* Used to be preliminary_hw_support
- Add missing Cannonlake PCI device ID of 0x5A4C (Rodrigo)
- Cannonlake port register fix (Mahesh)

- Fix Dell Venue 8 Pro black screen after modeset (Hans)
- Fix for always returning zero out-fence from execbuf (Daniele)
- Fix HDMI audio when no no relevant video output is active (Jani)
- Fix memleak of VBT data on driver_unload (Hans)

- Fix for KASAN found locking issue (Maarten)
- RCU barrier consolidation to improve igt/gem_sync/idle (Chris)
- Optimizations to IRQ handlers (Chris)
- vblank tracking improvements (64-bit resolution, PM) (Dhinakaran)
- Pipe select bit corrections (Ville)
- Reduce runtime computed device_info fields (Chris)
- Tune down some WARN_ONs to GEM_BUG_ON now that CI has good coverage (Chris)
- A bunch of kerneldoc warning fixes (Chris)

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scanout fence fixes/cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Scanout fence fixes/cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/38714/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c4c108df218b drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout
b5042b8f97b3 drm/i915: Only pin the fence for primary planes (and gen2/3)
-:66: WARNING: line over 80 characters
#66: FILE: drivers/gpu/drm/i915/intel_display.c:12761:
+
intel_plane_uses_fence(to_intel_plane_state(new_state)),

total: 0 errors, 1 warnings, 0 checks, 66 lines checked
8219c0edc31e drm/i915: Clean up fbc vs. plane checks
097680894b64 drm/i915: Require fence only for FBC capable planes
39994518 drm/i915: Extract intel_plane_{pin, unpin}_fb()
0225359291c9 drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Support engine busy stats

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL   : https://patchwork.freedesktop.org/series/38717/
State : failure

== Summary ==

Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy 
stats
https://patchwork.freedesktop.org/api/1.0/series/38717/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-edid-read:
pass   -> FAIL   (fi-kbl-7500u) fdo#102505
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
fail   -> PASS   (fi-ivb-3520m)
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
fail   -> PASS   (fi-ivb-3520m)
Subgroup suspend-read-crc-pipe-c:
fail   -> PASS   (fi-ivb-3520m)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:285s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:286s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:506s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:383s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:451s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:262  dwarn:1   dfail:0   fail:1   skip:24  
time:447s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:494s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:592s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:267  dwarn:0   dfail:0   fail:1   skip:20  
time:483s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:405s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:436s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:521s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:392s

42d073db2a8593a8d1832037ffe0988403031568 drm-tip: 2018y-02m-21d-14h-03m-58s UTC 
integration manifest
2acf999e7adf drm/i915: GuC test run
661f5ef77993 drm/i915/guc: Support engine busy stats

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8110/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL   : https://patchwork.freedesktop.org/series/38717/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
661f5ef77993 drm/i915/guc: Support engine busy stats
-:33: WARNING: line over 80 characters
#33: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:727:
+   
intel_engine_context_in(last->engine);

total: 0 errors, 1 warnings, 0 checks, 44 lines checked
2acf999e7adf drm/i915: GuC test run

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[Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

[Ville Syrjala]

From: Ville Syrjälä 

Let's record the information whether a plane can do fbc or not under
struct inte_plane.

v2: Rebase due to i9xx_plane_id
Handle BDW/HSW correctly
v3: Move inte_fbc_init() back since we depend on it happening
even with i915.disable_display, and populate
fbc->possible_framebuffer_bits directly from the
plane init code instead

Cc: Chris Wilson 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 41 
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_fbc.c | 26 ++-
 3 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d2a66704e6f5..c60d2215b377 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13238,6 +13238,32 @@ static const struct drm_plane_funcs 
intel_cursor_plane_funcs = {
.format_mod_supported = intel_cursor_plane_format_mod_supported,
 };
 
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+  enum i9xx_plane_id i9xx_plane)
+{
+   if (!HAS_FBC(dev_priv))
+   return false;
+
+   if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+   return i9xx_plane == PLANE_A;
+   else if (IS_IVYBRIDGE(dev_priv))
+   return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
+   i9xx_plane == PLANE_C;
+   else if (INTEL_GEN(dev_priv) >= 4)
+   return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
+   else
+   return i9xx_plane == PLANE_A;
+}
+
+static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum plane_id plane_id)
+{
+   if (!HAS_FBC(dev_priv))
+   return false;
+
+   return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
+}
+
 static struct intel_plane *
 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
@@ -13280,6 +13306,21 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
primary->i9xx_plane = (enum i9xx_plane_id) pipe;
primary->id = PLANE_PRIMARY;
primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
+
+   if (INTEL_GEN(dev_priv) >= 9)
+   primary->has_fbc = skl_plane_has_fbc(dev_priv,
+primary->pipe,
+primary->id);
+   else
+   primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
+ primary->i9xx_plane);
+
+   if (primary->has_fbc) {
+   struct intel_fbc *fbc = _priv->fbc;
+
+   fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
+   }
+
primary->check_plane = intel_check_primary_plane;
 
if (INTEL_GEN(dev_priv) >= 9) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e3f78fdae859..af82feb4a3cd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -935,6 +935,7 @@ struct intel_plane {
enum plane_id id;
enum pipe pipe;
bool can_scale;
+   bool has_fbc;
int max_downscale;
uint32_t frontbuffer_bit;
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index f66f6fb5743d..7fcb22a12e39 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -46,16 +46,6 @@ static inline bool fbc_supported(struct drm_i915_private 
*dev_priv)
return HAS_FBC(dev_priv);
 }
 
-static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
-{
-   return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
-}
-
-static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
-{
-   return INTEL_GEN(dev_priv) < 4;
-}
-
 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
 {
return INTEL_GEN(dev_priv) <= 3;
@@ -1094,13 +1084,10 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
 
-   if (!plane_state->base.visible)
+   if (!plane->has_fbc)
continue;
 
-   if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
-   continue;
-
-   if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != 
PLANE_A)
+   if (!plane_state->base.visible)
continue;
 
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@@ -1357,7 +1344,6 @@ static bool need_fbc_vtd_wa(struct drm_i915_private 

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Remove the ring advancement under preemption

[Michel Thierry]

On 21/02/18 05:32, Chris Wilson wrote:

Load an empty ringbuffer for preemption, ignoring the lite-restore
workaround as we know the preempt context is always idle before preemption.



True, injecting the preempt context shouldn't cause a lite-restore.
And the restriction was to always have Head!=Tail when attempting lite 
restore.



Note that after some digging by Michal Winiarski, we found that
RING_HEAD is no longer being updated (due to inhibiting context save
restore) so this patch is already in effect!

Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 


Reviewed-by: Michel Thierry 


---
  drivers/gpu/drm/i915/intel_lrc.c | 7 ---
  1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b6d781b22ec..e2d5e19b8a5e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -449,13 +449,6 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
  
  	GEM_BUG_ON(engine->execlists.preempt_complete_status !=

   upper_32_bits(ce->lrc_desc));
-   GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES));
-
-   memset(ce->ring->vaddr + ce->ring->tail, 0, WA_TAIL_BYTES);
-   ce->ring->tail += WA_TAIL_BYTES;
-   ce->ring->tail &= (ce->ring->size - 1);
-   ce->lrc_reg_state[CTX_RING_TAIL+1] = ce->ring->tail;
-
GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=


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[Intel-gfx] [PATCH 2/2] drm/i915: GuC test run

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

With disabled aggressive idling from IGT. To see how shard run fares.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 2 +-
 drivers/gpu/drm/i915/intel_uc.c | 2 ++
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 05b41045b8f9..61da6569ad6c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4076,9 +4076,6 @@ i915_drop_caches_set(void *data, u64 val)
i915_gem_shrink_all(dev_priv);
fs_reclaim_release(GFP_KERNEL);
 
-   if (val & DROP_IDLE)
-   drain_delayed_work(_priv->gt.idle_work);
-
if (val & DROP_FREED)
i915_gem_drain_freed_objects(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6398fb..b48056fb769d 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private 
*dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
 
/* Any platform specific fine-tuning can be done here */
+   if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+   enable_guc = 0;
 
return enable_guc;
 }
-- 
2.14.1

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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Place context in/out hooks into the GuC backend, when contexts are
assigned to ports, and removed from them, in order to be able to
provide engine busy stats in GuC mode.

Signed-off-by: Tvrtko Ursulin 
Testcase: igt/perf_pmu/busy-accuracy-*-*
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 946766b62459..fab5033b9987 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -675,6 +675,7 @@ static void guc_dequeue(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_gem_request *last = NULL;
+   struct i915_gem_context *last_ctx = NULL;
const struct execlist_port * const last_port =
>port[execlists->port_mask];
bool submit = false;
@@ -720,8 +721,13 @@ static void guc_dequeue(struct intel_engine_cs *engine)
goto done;
}
 
-   if (submit)
+   if (submit) {
port_assign(port, last);
+   if (last->ctx != last_ctx) {
+   
intel_engine_context_in(last->engine);
+   last_ctx = last->ctx;
+   }
+   }
port++;
}
 
@@ -744,6 +750,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
execlists->first = rb;
if (submit) {
port_assign(port, last);
+   if (last->ctx != last_ctx)
+   intel_engine_context_in(last->engine);
execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
guc_submit(engine);
}
@@ -766,6 +774,7 @@ static void guc_submission_tasklet(unsigned long data)
 
rq = port_request([0]);
while (rq && i915_gem_request_completed(rq)) {
+   intel_engine_context_out(rq->engine);
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
 
@@ -1195,8 +1204,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
execlists->tasklet.func = guc_submission_tasklet;
engine->park = guc_submission_park;
engine->unpark = guc_submission_unpark;
-
-   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
}
 
return 0;
-- 
2.14.1

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Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

[Souza, Jose]

On Wed, 2018-02-21 at 00:59 -0800, Dhinakaran Pandiyan wrote:
> On Tuesday, February 20, 2018 6:23:47 PM PST José Roberto de Souza
> wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent access by hardware and driver.
> > 
> > Reference:
> > https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc
> > -skl-vol
> > 12-display.pdf Page 198 - AUX programming sequence
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Jani Nikula 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  9 
> >  drivers/gpu/drm/i915/intel_dp.c  | 50
> > 
> > drivers/gpu/drm/i915/intel_drv.h |
> >  1 +
> >  3 files changed, 60 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 1412abcb27d4..a62e3c1badab
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5318,6 +5318,7 @@ enum {
> >  #define _DPA_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6401c)
> >  #define _DPA_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64020)
> >  #define _DPA_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64024)
> > +#define _DPA_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6402C)
> > 
> >  #define _DPB_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64110)
> >  #define _DPB_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64114)
> > @@ -5325,6 +5326,7 @@ enum {
> >  #define _DPB_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6411c)
> >  #define _DPB_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64120)
> >  #define _DPB_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64124)
> > +#define _DPB_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6412C)
> > 
> >  #define _DPC_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64210)
> >  #define _DPC_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64214)
> > @@ -5332,6 +5334,7 @@ enum {
> >  #define _DPC_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6421c)
> >  #define _DPC_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64220)
> >  #define _DPC_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64224)
> > +#define _DPC_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6422C)
> > 
> >  #define _DPD_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64310)
> >  #define _DPD_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64314)
> > @@ -5339,6 +5342,7 @@ enum {
> >  #define _DPD_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6431c)
> >  #define _DPD_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64320)
> >  #define _DPD_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64324)
> > +#define _DPD_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6432C)
> > 
> >  #define _DPF_AUX_CH_CTL(dev_priv-
> > >info.display_mmio_offset + 0x64510)
> >  #define _DPF_AUX_CH_DATA1  (dev_priv-
> > >info.display_mmio_offset + 0x64514)
> > @@ -5346,6 +5350,7 @@ enum {
> >  #define _DPF_AUX_CH_DATA3  (dev_priv-
> > >info.display_mmio_offset + 0x6451c)
> >  #define _DPF_AUX_CH_DATA4  (dev_priv-
> > >info.display_mmio_offset + 0x64520)
> >  #define _DPF_AUX_CH_DATA5  (dev_priv-
> > >info.display_mmio_offset + 0x64524)
> > +#define _DPF_AUX_CH_MUTEX  (dev_priv-
> > >info.display_mmio_offset + 0x6452C)
> > 
> >  #define DP_AUX_CH_CTL(port)_MMIO_PORT(port,
> > _DPA_AUX_CH_CTL,
> > _DPB_AUX_CH_CTL) #define DP_AUX_CH_DATA(port, i)_MMIO(_PORT
> > (port,
> > _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > @@
> > -5378,6 +5383,10 @@ enum {
> >  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> >  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
> > 
> > +#define DP_AUX_CH_MUTEX(port)  _MMIO_PORT(port,
> > _DPA_AUX_CH_MUTEX,
> > _DPB_AUX_CH_MUTEX) +#define   DP_AUX_CH_MUTEX_ENABLE
> > (1 << 31)
> > +#define   DP_AUX_CH_MUTEX_STATUS   (1 << 30)
> > +
> >  /*
> >   * Computing GMCH M and N values for the Display Port link
> >   *
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index f20b25f98e5a..af07563bafba
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1081,6 +1081,45 @@ static uint32_t
> > intel_dp_get_aux_send_ctl(struct
> > intel_dp *intel_dp, aux_clock_divider);
> >  }
> > 
> > +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
> > +{
> > +   struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > +   struct drm_i915_private *dev_priv =
> > +   

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

[Sagar Arun Kamble]

On 2/21/2018 5:50 PM, Michal Wajdeczko wrote:
On Wed, 21 Feb 2018 09:08:08 +0100, Sagar Arun Kamble 
 wrote:





On 2/21/2018 4:27 AM, Michal Wajdeczko wrote:

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-EIO).

Unfortunately since commit 121981fafe69 ("drm/i915/guc: Combine
enable_guc_loading|submission modparams") we stopped using that
error code to avoid unwanted fallback to execlist submission mode.

In result any GuC initialization failure was treated as non-recoverable
error leading to driver load abort, so we could not even read related
GuC error log to investigate cause of the problem.

Fix that by always returning -EIO on uC hardware related failure.

v2: don't allow -EIO from uc_init
 don't call uc_fini[_misc] on -EIO
 mark guc fw as failed on hw init failure
 prepare uc_fini_hw to run after earlier -EIO

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Michal Winiarski 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_gem.c    | 13 -
  drivers/gpu/drm/i915/intel_guc.h   |  5 +
  drivers/gpu/drm/i915/intel_uc.c    | 13 +
  drivers/gpu/drm/i915/intel_uc_fw.h |  5 +
  4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index 631a2db..80f23a8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5324,8 +5324,10 @@ int i915_gem_init(struct drm_i915_private 
*dev_priv)

  intel_init_gt_powersave(dev_priv);
    ret = intel_uc_init(dev_priv);
-    if (ret)
+    if (ret) {
+    GEM_BUG_ON(ret == -EIO);
  goto err_pm;
+    }
    ret = i915_gem_init_hw(dev_priv);
  if (ret)
@@ -5372,7 +5374,8 @@ int i915_gem_init(struct drm_i915_private 
*dev_priv)

  i915_gem_contexts_lost(dev_priv);
  intel_uc_fini_hw(dev_priv);

This uc_fini_hw should also be not called on -EIO?


This one here is fine. But I need to clear guc->fw.load_status
there to make sure we will not try to perform full fini_hw() again.

Yes. Will need to set load_status as FIRMWARE_FAIL.



  err_uc_init:
-    intel_uc_fini(dev_priv);
+    if (ret != -EIO)
+    intel_uc_fini(dev_priv);
  err_pm:
  if (ret != -EIO) {
  intel_cleanup_gt_powersave(dev_priv);
@@ -5386,10 +5389,10 @@ int i915_gem_init(struct drm_i915_private 
*dev_priv)

  intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  mutex_unlock(_priv->drm.struct_mutex);
  -    intel_uc_fini_misc(dev_priv);
-
-    if (ret != -EIO)
+    if (ret != -EIO) {
+    intel_uc_fini_misc(dev_priv);
  i915_gem_cleanup_userptr(dev_priv);
+    }
    if (ret == -EIO) {
  /*
Comment here can be updated to say "Allow engines or uC 
initialization to fail ... "


ok

diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h

index 52856a9..512ff7b 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -100,6 +100,11 @@ static inline void intel_guc_notify(struct 
intel_guc *guc)

  guc->notify(guc);
  }
  +static inline bool intel_guc_is_loaded(struct intel_guc *guc)
+{
+    return intel_uc_fw_is_loaded(>fw);
+}
+
  /*
   * GuC does not allow any gfx GGTT address that falls into range 
[0, WOPCM_TOP),
   * which is reserved for Boot ROM, SRAM and WOPCM. Currently this 
top address is
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 9f1bac6..75d0eb9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -421,11 +421,13 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)
   * Note that there is no fallback as either user explicitly 
asked for
   * the GuC or driver default option was to run with the GuC 
enabled.

   */
-    if (GEM_WARN_ON(ret == -EIO))
-    ret = -EINVAL;
-
  dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", 
ret);

-    return ret;
+
+    /* Mark GuC firmware as failed to avoid redundant clean-up */
uc_fini_hw is not redundant. uc_fini[_misc] was redundant. May be we 
should say

"to avoid clean-up on wedged"


ok


+    guc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
+
+    /* We want to disable GPU submission but keep KMS alive */
+    return -EIO;
  }
    void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
@@ -437,6 +439,9 @@ void intel_uc_fini_hw(struct drm_i915_private 
*dev_priv)

    GEM_BUG_ON(!HAS_GUC(dev_priv));
  +    if (!intel_guc_is_loaded(guc))
+    return;
+

Can we skip based on i915_terminally_wedged instead?


I'm not sure, as we declare GPU as wedged 

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

[Daniele Ceraolo Spurio]

diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h 
b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..0e3b237 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,11 @@ static inline bool intel_uc_fw_is_selected(struct 
intel_uc_fw *uc_fw)
return uc_fw->path != NULL;
  }
  
+static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)

+{
+   return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;


Since we do not immediately update uc_fw->load_status after full GPU 
reset we have a small window of time during re-initialization where this 
function would falsely return true. We don't hit the issue in this 
patch, but I'd personally prefer not to add this function until 
uc_fw->load_status is correctly updated as we might inadvertently start 
to use it at the wrong time. Alternatively, if you want to merge this 
soon we could read the status from the HW as an initial version and then 
switch to uc_fw->load_status after we've fixed it.


Daniele


+}
+
  void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
   struct intel_uc_fw *uc_fw);
  int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,


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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/hsw: add missing disabled EUs registers reads (rev2)
URL   : https://patchwork.freedesktop.org/series/38441/
State : success

== Summary ==

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_chv_cursor_fail:
Subgroup pipe-b-64x64-bottom-edge:
dmesg-warn -> PASS   (shard-snb) fdo#105185
Test gem_eio:
Subgroup in-flight-external:
fail   -> PASS   (shard-hsw) fdo#104676

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676

shard-apltotal:3367 pass:1765 dwarn:1   dfail:0   fail:8   skip:1592 
time:11937s
shard-hswtotal:3429 pass:1759 dwarn:1   dfail:0   fail:3   skip:1665 
time:11602s
shard-snbtotal:3429 pass:1350 dwarn:1   dfail:0   fail:2   skip:2076 
time:6548s
Blacklisted hosts:
shard-kbltotal:3429 pass:1925 dwarn:1   dfail:0   fail:9   skip:1494 
time:9580s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8104/shards.html
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