[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Avoid sleeping inside per-engine reset

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Avoid sleeping inside 
per-engine reset
URL   : https://patchwork.freedesktop.org/series/40915/
State : success

== Summary ==

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3-devices:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887

shard-apltotal:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 
time:12890s
shard-hswtotal:3460 pass:1765 dwarn:1   dfail:0   fail:2   skip:1690 
time:11102s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:7052s
Blacklisted hosts:
shard-kbltotal:3495 pass:1926 dwarn:35  dfail:0   fail:6   skip:1528 
time:9330s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8542/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for trace: Default to using trace_global_clock if sched_clock is unstable (rev2)

[Patchwork]

== Series Details ==

Series: trace: Default to using trace_global_clock if sched_clock is unstable 
(rev2)
URL   : https://patchwork.freedesktop.org/series/40728/
State : failure

== Summary ==

 Possible new issues:

Test kms_cursor_legacy:
Subgroup cursor-vs-flip-atomic-transitions-varying-size:
pass   -> FAIL   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887 +1
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +2
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-shrfb-fliptrack:
skip   -> FAIL   (shard-snb) fdo#103167

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apltotal:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 
time:12893s
shard-hswtotal:3495 pass:1778 dwarn:1   dfail:0   fail:6   skip:1709 
time:11442s
shard-snbtotal:3495 pass:1373 dwarn:1   dfail:0   fail:6   skip:2115 
time:6996s
Blacklisted hosts:
shard-kbltotal:3495 pass:1957 dwarn:1   dfail:0   fail:9   skip:1528 
time:9236s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8541/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40839/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-absolute-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_rotation_crc:
Subgroup sprite-rotation-90:
pass   -> FAIL   (shard-apl) fdo#103925

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925

shard-apltotal:3495 pass:1830 dwarn:1   dfail:0   fail:8   skip:1655 
time:12881s
shard-hswtotal:3495 pass:1782 dwarn:1   dfail:0   fail:2   skip:1709 
time:11604s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:7006s
Blacklisted hosts:
shard-kbltotal:3495 pass:1959 dwarn:1   dfail:0   fail:7   skip:1528 
time:9240s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8540/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Avoid sleeping inside per-engine reset

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Avoid sleeping inside 
per-engine reset
URL   : https://patchwork.freedesktop.org/series/40915/
State : success

== Summary ==

Series 40915v1 series starting with [CI,1/2] drm/i915: Avoid sleeping inside 
per-engine reset
https://patchwork.freedesktop.org/api/1.0/series/40915/revisions/1/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS   (fi-skl-6700k2) fdo#104108
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#103191

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:510s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:522s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:412s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:419s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:437s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:654s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:520s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:426s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:588s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:255  dwarn:3   dfail:0   fail:1   skip:26  
time:530s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s

9829fcd7ae99d5955bb76a8fb8060e63339d7c9d drm-tip: 2018y-03m-29d-19h-56m-48s UTC 
integration manifest
7c37feb18536 drm/i915: Only warn for might_sleep() before a slow 
wait_for_register
0cc5d44ff77f drm/i915: Avoid sleeping inside per-engine reset

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8542/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for trace: Default to using trace_global_clock if sched_clock is unstable (rev2)

[Patchwork]

== Series Details ==

Series: trace: Default to using trace_global_clock if sched_clock is unstable 
(rev2)
URL   : https://patchwork.freedesktop.org/series/40728/
State : success

== Summary ==

Series 40728v2 trace: Default to using trace_global_clock if sched_clock is 
unstable
https://patchwork.freedesktop.org/api/1.0/series/40728/revisions/2/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989
incomplete -> PASS   (fi-skl-6700k2) fdo#104108
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
notrun -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:435s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:534s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:527s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:505s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:516s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:661s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:445s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:498s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:509s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:429s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:567s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:405s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:522s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:490s

9829fcd7ae99d5955bb76a8fb8060e63339d7c9d drm-tip: 2018y-03m-29d-19h-56m-48s UTC 
integration manifest
206b3fc619b5 trace: Default to using trace_global_clock if sched_clock is 
unstable

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8541/issues.html
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[Intel-gfx] [CI 2/2] drm/i915: Only warn for might_sleep() before a slow wait_for_register

[Chris Wilson]

As intel_wait_for_register_fw() may use, and if successful only use, a
busy-wait loop, the might_sleep() warning is a little over-zealous.
Restrict it to a might_sleep_if() a slow timeout is specified (and so
the caller authorises use of a usleep).

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a0d7e0cfbd32..e7540bb9786c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1996,7 +1996,7 @@ int __intel_wait_for_register(struct drm_i915_private 
*dev_priv,
u32 reg_value;
int ret;
 
-   might_sleep();
+   might_sleep_if(slow_timeout_ms);
 
spin_lock_irq(_priv->uncore.lock);
intel_uncore_forcewake_get__locked(dev_priv, fw);
@@ -2008,7 +2008,7 @@ int __intel_wait_for_register(struct drm_i915_private 
*dev_priv,
intel_uncore_forcewake_put__locked(dev_priv, fw);
spin_unlock_irq(_priv->uncore.lock);
 
-   if (ret)
+   if (ret && slow_timeout_ms)
ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
 (reg_value & mask) == value,
 slow_timeout_ms * 1000, 10, 1000);
-- 
2.16.3

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[Intel-gfx] [CI 1/2] drm/i915: Avoid sleeping inside per-engine reset

[Chris Wilson]

Only sleep and repeat when asked for a full device reset (ALL_ENGINES)
and avoid using sleeping waits when asked for a per-engine reset. The
goal is to be able to use a per-engine reset from hardirq/softirq/timer
context. A consequence is that our individual wait timeouts are a
thousand times shorter, on the order of a hundred microseconds rather
than hundreds of millisecond. This may make hitting the timeouts more
common, but hopefully the fallover to the full-device reset will be
sufficient to pick up the pieces.

Note, that the sleeps inside older gen (pre-gen8) have been left as they
are only used in full device reset mode.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michał Winiarski 
CC: Michel Thierry 
Cc: Jeff McGee 
Cc: Tvrtko Ursulin 
Reviewed-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_uncore.c | 51 -
 1 file changed, 34 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index f37ecfc69e49..a0d7e0cfbd32 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1702,11 +1702,10 @@ static void gen3_stop_engine(struct intel_engine_cs 
*engine)
const i915_reg_t mode = RING_MI_MODE(base);
 
I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
-   if (intel_wait_for_register_fw(dev_priv,
-  mode,
-  MODE_IDLE,
-  MODE_IDLE,
-  500))
+   if (__intel_wait_for_register_fw(dev_priv,
+mode, MODE_IDLE, MODE_IDLE,
+500, 0,
+NULL))
DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
 engine->name);
 
@@ -1860,9 +1859,10 @@ static int gen6_hw_domain_reset(struct drm_i915_private 
*dev_priv,
__raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
 
/* Wait for the device to ack the reset requests */
-   err = intel_wait_for_register_fw(dev_priv,
- GEN6_GDRST, hw_domain_mask, 0,
- 500);
+   err = __intel_wait_for_register_fw(dev_priv,
+  GEN6_GDRST, hw_domain_mask, 0,
+  500, 0,
+  NULL);
if (err)
DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
 hw_domain_mask);
@@ -2027,11 +2027,12 @@ static int gen8_reset_engine_start(struct 
intel_engine_cs *engine)
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
  _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
 
-   ret = intel_wait_for_register_fw(dev_priv,
-RING_RESET_CTL(engine->mmio_base),
-RESET_CTL_READY_TO_RESET,
-RESET_CTL_READY_TO_RESET,
-700);
+   ret = __intel_wait_for_register_fw(dev_priv,
+  RING_RESET_CTL(engine->mmio_base),
+  RESET_CTL_READY_TO_RESET,
+  RESET_CTL_READY_TO_RESET,
+  700, 0,
+  NULL);
if (ret)
DRM_ERROR("%s: reset request timeout\n", engine->name);
 
@@ -2094,15 +2095,31 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, 
unsigned engine_mask)
int retry;
int ret;
 
-   might_sleep();
+   /*
+* We want to perform per-engine reset from atomic context (e.g.
+* softirq), which imposes the constraint that we cannot sleep.
+* However, experience suggests that spending a bit of time waiting
+* for a reset helps in various cases, so for a full-device reset
+* we apply the opposite rule and wait if we want to. As we should
+* always follow up a failed per-engine reset with a full device reset,
+* being a little faster, stricter and more error prone for the
+* atomic case seems an acceptable compromise.
+*
+* Unfortunately this leads to a bimodal routine, when the goal was
+* to have a single reset function that worked for resetting any
+* number of engines simultaneously.
+*/
+   might_sleep_if(engine_mask == ALL_ENGINES);
 
-   /* If the power well sleeps during the reset, the reset
+   /*
+* If the power well sleeps during the reset, 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for trace: Default to using trace_global_clock if sched_clock is unstable (rev2)

[Patchwork]

== Series Details ==

Series: trace: Default to using trace_global_clock if sched_clock is unstable 
(rev2)
URL   : https://patchwork.freedesktop.org/series/40728/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
206b3fc619b5 trace: Default to using trace_global_clock if sched_clock is 
unstable
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#17: 
Delta way too big! 18446743856563626466 ts=18446744054496180323 write stamp 
= 197932553857

total: 0 errors, 1 warnings, 0 checks, 22 lines checked

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[Intel-gfx] [PATCH] trace: Default to using trace_global_clock if sched_clock is unstable

[Chris Wilson]

Across suspend, we may see a very large drift in timestamps if the sched
clock is unstable, prompting the global trace's ringbuffer code to warn
and suggest switching to the global clock. Preempt this request by
detecting when the sched clock is unstable (determined during
late_initcall) and automatically switching the default clock over to
trace_global_clock.

This should prevent requiring user interaction to resolve warnings such
as:

Delta way too big! 18446743856563626466 ts=18446744054496180323 write stamp 
= 197932553857
If you just came from a suspend/resume,
please switch to the trace global clock:
echo global > /sys/kernel/debug/tracing/trace_clock

Signed-off-by: Chris Wilson 
Cc: Steven Rostedt (VMware) 
---
 kernel/trace/trace.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 13baf85b27d8..c5462513db90 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -41,6 +41,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "trace.h"
@@ -8505,3 +8506,15 @@ __init static int clear_boot_tracer(void)
 
 fs_initcall(tracer_init_tracefs);
 late_initcall_sync(clear_boot_tracer);
+
+#ifdef CONFIG_HAVE_UNSTABLE_SCHED_CLOCK
+__init static int tracing_set_default_clock(void)
+{
+   /* sched_clock_stable() is determined in late_initcall */
+   if (!trace_boot_clock && !sched_clock_stable())
+   tracing_set_clock(_trace, "global");
+
+   return 0;
+}
+late_initcall_sync(tracing_set_default_clock);
+#endif
-- 
2.16.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40839/
State : success

== Summary ==

Series 40839v1 series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
https://patchwork.freedesktop.org/api/1.0/series/40839/revisions/1/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS   (fi-skl-6700k2) fdo#104108
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#103191

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:295s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:523s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:589s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:467s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:666s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:451s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:566s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:408s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:533s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:484s

9829fcd7ae99d5955bb76a8fb8060e63339d7c9d drm-tip: 2018y-03m-29d-19h-56m-48s UTC 
integration manifest
2ec83428a832 drm/i915/debugfs: Print sink PSR status
20e02342f2b0 drm/i915/psr: Set DPCD PSR2 enable bit when needed
82122405ae92 drm/i915/psr: Cache sink synchronization latency
bf021489296c drm/i915/psr: Use PSR2 macro for PSR2
5c9248d38cda drm/i915/psr: Do not override PSR2 sink support
4cc799de37d9 drm/i915/psr/cnl: Enable Y-coordinate support in source
45b2682dc7e8 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
c4ff90984726 drm/i915/psr: Nuke aux frame sync
ea5ff834dac7 drm: Add DP last received PSR SDP VSC register and bits
9ae66e05586d drm: Add DP PSR2 sink enable bit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8540/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: Dump valid EDIDs too

[Patchwork]

== Series Details ==

Series: drm/edid: Dump valid EDIDs too
URL   : https://patchwork.freedesktop.org/series/40896/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (shard-hsw) fdo#103375
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-hsw) fdo#103925

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925

shard-apltotal:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 
time:12884s
shard-hswtotal:3495 pass:1780 dwarn:1   dfail:0   fail:4   skip:1709 
time:11516s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:7033s
Blacklisted hosts:
shard-kbltotal:3495 pass:1910 dwarn:49  dfail:1   fail:7   skip:1528 
time:9295s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8537/shards.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40839/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9ae66e05586d drm: Add DP PSR2 sink enable bit
ea5ff834dac7 drm: Add DP last received PSR SDP VSC register and bits
c4ff90984726 drm/i915/psr: Nuke aux frame sync
45b2682dc7e8 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
4cc799de37d9 drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:4061:
+#define   EDP_Y_COORDINATE_VALID   (1<<26) /* GLK and CNL+ */
  ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:4062:
+#define   EDP_Y_COORDINATE_ENABLE  (1<<25) /* GLK and CNL+ */
  ^

-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:7069:
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
  ^

total: 0 errors, 0 warnings, 3 checks, 43 lines checked
5c9248d38cda drm/i915/psr: Do not override PSR2 sink support
bf021489296c drm/i915/psr: Use PSR2 macro for PSR2
82122405ae92 drm/i915/psr: Cache sink synchronization latency
20e02342f2b0 drm/i915/psr: Set DPCD PSR2 enable bit when needed
2ec83428a832 drm/i915/debugfs: Print sink PSR status

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Write to SET_POWER dpcd to enable MST hub. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Write to SET_POWER dpcd to enable MST hub. (rev2)
URL   : https://patchwork.freedesktop.org/series/39927/
State : failure

== Summary ==

Applying: drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_ddi.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.

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[Intel-gfx] [stable:v4.15] drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.

[Dhinakaran Pandiyan]

If bios sets up an MST output and hardware state readout code sees this is
an SST configuration, when disabling the encoder we end up calling
->post_disable_dp() hook instead of the MST version. Consequently, we write
to the DP_SET_POWER dpcd to set it D3 state. Further along when we try
enable the encoder in MST mode, POWER_UP_PHY transaction fails to power up
the MST hub. This results in continuous link training failures which keep
the system busy delaying boot. We could identify bios MST boot discrepancy
and handle it accordingly but a simple way to solve this is to write to the
DP_SET_POWER dpcd for MST too.

v2: Rebased on stable/linux-4.15.y and fixed minor conflict.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105470
Cc: Ville Syrjälä 
Cc: Jani Nikula 
Reviewed-by: Ville Syrjälä 
Reported-by: Laura Abbott 
Cc:  # 4.15+
Fixes: 5ea2355a100a ("drm/i915/mst: Use MST sideband message transactions for 
dpms control")
Tested-by: Laura Abbott 
Signed-off-by: Dhinakaran Pandiyan 
Signed-off-by: Jani Nikula 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20180314054825.1718-1-dhinakaran.pandi...@intel.com
(cherry picked from commit ad260ab32a4d94fa974f58262f8000472d34fd5b)
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_ddi.c | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 58a3755544b2..38e53d6b8127 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2208,8 +2208,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder);
 
intel_ddi_init_dp_buf_reg(encoder);
-   if (!is_mst)
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2294,19 +2293,12 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct intel_dp *intel_dp = _port->dp;
-   /*
-* old_crtc_state and old_conn_state are NULL when called from
-* DP_MST. The main connector associated with this port is never
-* bound to a crtc for MST.
-*/
-   bool is_mst = !old_crtc_state;
 
/*
 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   if (!is_mst)
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_disable_ddi_buf(encoder);
 
-- 
2.14.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for blacklist: Don't run DRRS test on Intel CI system

[Patchwork]

== Series Details ==

Series: blacklist: Don't run DRRS test on Intel CI system
URL   : https://patchwork.freedesktop.org/series/40871/
State : failure

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-cur-indfb-draw-render:
pass   -> FAIL   (shard-apl)

 Known issues:

Test kms_flip:
Subgroup plain-flip-fb-recreate:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-indfb-msflip-blt:
pass   -> SKIP   (shard-snb) fdo#103167
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (shard-hsw) fdo#103375

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apltotal:2925 pass:1830 dwarn:1   dfail:0   fail:8   skip:1085 
time:12739s
shard-hswtotal:2925 pass:1782 dwarn:1   dfail:0   fail:2   skip:1139 
time:11535s
shard-snbtotal:2925 pass:1373 dwarn:1   dfail:0   fail:3   skip:1548 
time:6876s
Blacklisted hosts:
shard-kbltotal:2925 pass:1952 dwarn:8   dfail:0   fail:7   skip:958 
time:9166s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1207/shards.html
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[Intel-gfx] [PATCH i-g-t v3] intel-gpu-top: Rewrite the tool to be safe to use

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.

Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.

For access to more GPU functional unit level data, an OA metric based tool
like gpu-top should be used instead.

v2:
 * Sort engines by class and instance.
 * Do not wait for one sampling period to display something on screen.
 * Move code out of the asserts. (Rinat Ibragimov)
 * Continuously adapt to terminal size. (Rinat Ibgragimov)

v3:
 * Change layout and precision of some field. (Chris Wilson)
 Eero Tamminen:
 * Use more user friendly engine names.
 * Don't error out if a counter is missing.
 * Add IMC read/write bandwidth.
 * Report minimum required kernel version.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Petri Latvala 
Cc: Eero Tamminen 
Cc: Rinat Ibragimov 
Reviewed-by: Lionel Landwerlin  # v1
Reviewed-by: Chris Wilson  # v0.5
---
 lib/igt_perf.c|6 +
 lib/igt_perf.h|1 +
 tools/Makefile.am |2 +
 tools/intel_gpu_top.c | 1216 ++---
 tools/meson.build |6 +-
 5 files changed, 657 insertions(+), 574 deletions(-)

diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 99d82ea51c9b..e3dec2cc29c7 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -69,3 +69,9 @@ int igt_perf_open(uint64_t type, uint64_t config)
return _perf_open(type, config, -1,
  PERF_FORMAT_TOTAL_TIME_ENABLED);
 }
+
+int igt_perf_open_group(uint64_t type, uint64_t config, int group)
+{
+   return _perf_open(type, config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 614ea5d23fa6..e00718f4769a 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -55,5 +55,6 @@ uint64_t i915_type_id(void);
 int perf_i915_open(uint64_t config);
 int perf_i915_open_group(uint64_t config, int group);
 int igt_perf_open(uint64_t type, uint64_t config);
+int igt_perf_open_group(uint64_t type, uint64_t config, int group);
 
 #endif /* I915_PERF_H */
diff --git a/tools/Makefile.am b/tools/Makefile.am
index 09b6dbcc3ece..a0b016ddd7ff 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -28,6 +28,8 @@ intel_aubdump_la_LDFLAGS = -module -avoid-version 
-no-undefined
 intel_aubdump_la_SOURCES = aubdump.c
 intel_aubdump_la_LIBADD = $(top_builddir)/lib/libintel_tools.la -ldl
 
+intel_gpu_top_LDADD = $(top_builddir)/lib/libigt_perf.la
+
 bin_SCRIPTS = intel_aubdump
 CLEANFILES = $(bin_SCRIPTS)
 
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 098e6ce3ff86..46a3db42d3d6 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1,6 +1,5 @@
 /*
- * Copyright © 2007 Intel Corporation
- * Copyright © 2011 Intel Corporation
+ * Copyright © 2018 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -18,701 +17,772 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *Eugeni Dodonov 
- *
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  */
 
-#include "config.h"
-
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#ifdef HAVE_TERMIOS_H
-#include 
-#endif
-#include "intel_io.h"
-#include "instdone.h"
-#include "intel_reg.h"
-#include "intel_chipset.h"
-#include "drmtest.h"
-
-#define  FORCEWAKE 0xA18C
-#define  FORCEWAKE_ACK 0x130090
-
-#define SAMPLES_PER_SEC 1
-#define SAMPLES_TO_PERCENT_RATIO(SAMPLES_PER_SEC / 100)
-
-#define MAX_NUM_TOP_BITS100
-
-#define HAS_STATS_REGS(devid)  IS_965(devid)
-
-struct top_bit {
-   struct instdone_bit *bit;
-   int count;
-} top_bits[MAX_NUM_TOP_BITS];
-struct top_bit *top_bits_sorted[MAX_NUM_TOP_BITS];
-
-static uint32_t instdone, instdone1;
-
-static const char *bars[] = {
-   " ",
-   "▏",
-   "▎",
-   "▍",
-   "▌",
-   "▋",
-   "▊",
-   "▉",
-   "█"
-};
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 

[Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP1.4 fixes (rev3)

[Patchwork]

== Series Details ==

Series: HDCP1.4 fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/38978/
State : failure

== Summary ==

 Possible new issues:

Test drv_selftest:
Subgroup live_hangcheck:
pass   -> DMESG-FAIL (shard-apl)

 Known issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-cur-indfb-draw-blt:
pass   -> FAIL   (shard-apl) fdo#103167
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (shard-hsw) fdo#103375
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:3495 pass:1829 dwarn:1   dfail:1   fail:8   skip:1655 
time:12911s
shard-hswtotal:3495 pass:1782 dwarn:1   dfail:0   fail:2   skip:1709 
time:11414s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:7041s
Blacklisted hosts:
shard-kbltotal:3495 pass:1953 dwarn:6   dfail:0   fail:8   skip:1528 
time:9333s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8535/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Track begin/end of execlists submission sequences

[Francisco Jerez]

Chris Wilson  writes:

> We would like to start doing some bookkeeping at the beginning, between
> contexts and at the end of execlists submission. We already mark the
> beginning and end using EXECLISTS_ACTIVE_USER, to provide an indication
> when the HW is idle. This give us a pair of sequence points we can then
> expand on for further bookkeeping.
>
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Francisco Jerez 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c| 42 
> -
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 11 -
>  2 files changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 654634254b64..61fb1387feb3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -374,6 +374,19 @@ execlists_context_status_change(struct i915_request *rq, 
> unsigned long status)
>  status, rq);
>  }
>  
> +static inline void
> +execlists_user_begin(struct intel_engine_execlists *execlists,
> +  const struct execlist_port *port)
> +{
> + execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
> +}
> +
> +static inline void
> +execlists_user_end(struct intel_engine_execlists *execlists)
> +{
> + execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
> +}
> +
>  static inline void
>  execlists_context_schedule_in(struct i915_request *rq)
>  {
> @@ -710,7 +723,7 @@ static void execlists_dequeue(struct intel_engine_cs 
> *engine)
>   spin_unlock_irq(>timeline->lock);
>  
>   if (submit) {
> - execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
> + execlists_user_begin(execlists, execlists->port);
>   execlists_submit_ports(engine);
>   }
>  
> @@ -741,7 +754,7 @@ execlists_cancel_port_requests(struct 
> intel_engine_execlists * const execlists)
>   port++;
>   }
>  
> - execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
> + execlists_user_end(execlists);
>  }
>  
>  static void clear_gtiir(struct intel_engine_cs *engine)
> @@ -872,7 +885,7 @@ static void execlists_submission_tasklet(unsigned long 
> data)
>  {
>   struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
>   struct intel_engine_execlists * const execlists = >execlists;
> - struct execlist_port * const port = execlists->port;
> + struct execlist_port *port = execlists->port;
>   struct drm_i915_private *dev_priv = engine->i915;
>   bool fw = false;
>  
> @@ -1010,9 +1023,19 @@ static void execlists_submission_tasklet(unsigned long 
> data)
>  
>   GEM_BUG_ON(count == 0);
>   if (--count == 0) {
> + /*
> +  * On the final event corresponding to the
> +  * submission of this context, we expect either
> +  * an element-switch event or a completion
> +  * event (and on completion, the active-idle
> +  * marker). No more preemptions, lite-restore
> +  * or otherwise

Missing punctuation in the last sentence.

> +  */
>   GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
>   GEM_BUG_ON(port_isset([1]) &&
>  !(status & 
> GEN8_CTX_STATUS_ELEMENT_SWITCH));
> + GEM_BUG_ON(!port_isset([1]) &&
> +!(status & 
> GEN8_CTX_STATUS_ACTIVE_IDLE));
>   GEM_BUG_ON(!i915_request_completed(rq));
>   execlists_context_schedule_out(rq);
>   trace_i915_request_out(rq);
> @@ -1021,17 +1044,14 @@ static void execlists_submission_tasklet(unsigned 
> long data)
>   GEM_TRACE("%s completed ctx=%d\n",
> engine->name, port->context_id);
>  
> - execlists_port_complete(execlists, port);
> + port = execlists_port_complete(execlists, port);
> + if (port_isset(port))
> + execlists_user_begin(execlists, port);
> + else
> + execlists_user_end(execlists);
>   } else {
>   port_set(port, port_pack(rq, count));
>   }
> -
> - /* After the final element, the hw should be idle */
> - GEM_BUG_ON(port_count(port) == 0 &&
> -!(status & 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev7)

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev7)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

Series 40503v7 series starting with [v6,1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/7/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-bxt-j4205)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-skl-6700k2) fdo#104108
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:435s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:387s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:532s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-j4205 total:242  pass:216  dwarn:0   dfail:0   fail:0   skip:25 
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:517s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:583s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:422s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:419s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:439s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:657s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:243  pass:222  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:511s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:558s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:408s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:526s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s

befd0b655b91ec3977909f136e663dcee41e5c56 drm-tip: 2018y-03m-29d-16h-19m-32s UTC 
integration manifest
92da09cfa7cd drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
d52cd4564412 drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8538/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Some plane init cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Some plane init cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/39390/
State : failure

== Summary ==

 Possible new issues:

Test kms_chv_cursor_fail:
Subgroup pipe-b-64x64-top-edge:
pass   -> FAIL   (shard-apl)

 Known issues:

Test kms_flip:
Subgroup blocking-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_flip_tiling:
Subgroup flip-to-x-tiled:
pass   -> FAIL   (shard-apl) fdo#103822
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (shard-hsw) fdo#103375
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:3495 pass:1829 dwarn:1   dfail:0   fail:9   skip:1655 
time:12960s
shard-hswtotal:3495 pass:1781 dwarn:1   dfail:0   fail:3   skip:1709 
time:11624s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:7018s
Blacklisted hosts:
shard-kbltotal:3495 pass:1958 dwarn:1   dfail:0   fail:7   skip:1529 
time:9279s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8533/shards.html
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Re: [Intel-gfx] [PATCH] drm/edid: Dump valid EDIDs too

[Chris Wilson]

Quoting Ville Syrjälä (2018-03-29 17:14:05)
> On Thu, Mar 29, 2018 at 05:01:13PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-03-29 16:50:23)
> > > From: Ville Syrjälä 
> > > 
> > > Having the EDID available is often very beneficial for bug analysis,
> > > even when the EDID itself is valid and not the direct cause of the
> > > bug. So let's dump the EDID to dmesg even when it's valid. This
> > > should also give us a better historical record of EDIDs for later
> > > analysis.
> > 
> > Isn't this a bit frequent for a largely unchanging blob?
> 
> Perhaps. Though ideally we shouldn't go re-reading it all the time.
> But I guess that's wisful thinking.

Ok, that was far less frequent that I expected for an igt run, though it
does look like Maarten has a few more probes to kill.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Dump valid EDIDs too

[Patchwork]

== Series Details ==

Series: drm/edid: Dump valid EDIDs too
URL   : https://patchwork.freedesktop.org/series/40896/
State : success

== Summary ==

Series 40896v1 drm/edid: Dump valid EDIDs too
https://patchwork.freedesktop.org/api/1.0/series/40896/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
pass   -> FAIL   (fi-skl-guc) fdo#103191
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:438s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:295s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:509s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:420s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:407s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:522s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:482s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
aaffa0db447e drm/edid: Dump valid EDIDs too

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8537/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Track begin/end of execlists submission sequences

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Track begin/end of execlists submission sequences
URL   : https://patchwork.freedesktop.org/series/40870/
State : failure

== Summary ==

 Possible new issues:

Test kms_chv_cursor_fail:
Subgroup pipe-a-64x64-left-edge:
pass   -> FAIL   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
skip   -> FAIL   (shard-snb)
Subgroup psr-1p-rte:
skip   -> FAIL   (shard-snb)
Subgroup psr-2p-primscrn-indfb-plflip-blt:
skip   -> FAIL   (shard-snb)
Subgroup psr-2p-scndscrn-indfb-plflip-blt:
skip   -> FAIL   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-ts-continuation-modeset-hang:
pass   -> FAIL   (shard-snb)

 Known issues:

Test drv_selftest:
Subgroup live_gtt:
pass   -> INCOMPLETE (shard-apl) fdo#103927
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (shard-hsw) fdo#103375

fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apltotal:3473 pass:1808 dwarn:1   dfail:0   fail:7   skip:1655 
time:12434s
shard-hswtotal:3495 pass:1783 dwarn:1   dfail:0   fail:1   skip:1709 
time:11528s
shard-snbtotal:3495 pass:1372 dwarn:1   dfail:0   fail:14  skip:2108 
time:7006s
Blacklisted hosts:
shard-kbltotal:3495 pass:1958 dwarn:1   dfail:0   fail:8   skip:1528 
time:9285s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8532/shards.html
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[Intel-gfx] [PATCH v6 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style change and uses of local variables for clearer
   logic (Ursulin)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 
---
 drivers/gpu/drm/i915/i915_reg.h|  4 
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32c297a..994870f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2697,6 +2697,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT18
 #define   GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#defineGEN10_MIRROR_FUSE3  _MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT 4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0   _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK 0xff
 #define   GEN8_EU_DIS0_S1_SHIFT24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4c50bee..57f4c35 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -810,8 +810,33 @@ static u32 calculate_mcr(struct drm_i915_private 
*dev_priv, u32 mcr)
 
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
u32 mcr;
 
+   /*
+* L3Banks could be fused off in single slice scenario, however, if
+* more than one slice is enabled, this should not happen.
+*/
+   if (is_power_of_2(sseu->slice_mask)) {
+   /*
+* WaProgramMgsrForL3BankSpecificMmioReads:
+* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+* enabled subslice, no need to redirect MCR packet
+*/
+   u32 slice = fls(sseu->slice_mask);
+   u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+   u8 ss_mask = sseu->subslice_mask[slice];
+
+   u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
+   u8 disabled_mask = fuse3 & 0xf;
+
+   /*
+* Production silicon should have matched L3Bank and
+* subslice enabled
+*/
+   WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+   }
+
mcr = I915_READ(GEN8_MCR_SELECTOR);
mcr = calculate_mcr(dev_priv, mcr);
I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 02/23] drm/atomic-helper: Make drm_atomic_helper_disable_all() update the plane->fb pointers

[Ville Syrjälä]

On Mon, Mar 26, 2018 at 10:28:06PM +0200, Daniel Vetter wrote:
> On Thu, Mar 22, 2018 at 05:22:52PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > drm_atomic_helper_shutdown() needs to release the reference held by
> > plane->fb, so we want to use drm_atomic_clean_old_fb() in
> > drm_atomic_helper_disable_all(). However during suspend/resume, gpu
> > reset and load detection we should probably leave that stuff alone,
> > as otherwise we'd have to make sure we put them back again when
> > we restore the duplicated state to the device. Seems simpler to me
> > to not touch any of it anyway.
> > 
> > v2: Don't inflict the clean_old_fbs bool to drivers (Daniel)
> > 
> > Cc: martin.pe...@free.fr
> > Cc: ch...@chris-wilson.co.uk
> > Cc: Dave Airlie  (v1)
> > Cc: Maarten Lankhorst 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> 
> I think this would be cleaner diff to read if you squash the first 2
> patches together. Also avoids the bisect fail. With that (and I trust you
> to come up with a suitably merged commit message):
> 
> Reviewed-by: Daniel Vetter 

Squashed, and commit message rescribbeled. And with sufficient confidence
from a local smoke test I proceeded to push the easy ones 1-13 (except msm), 
and 22-23 (the load detect stuff for i915). I'll have to figure out the
correct merge order for the rest next week.

Thanks for the reviews.

> 
> I reviewed this by re-reading the analysis from 49d70aeaeca8f62b72b77 and
> trusting my former self :-)
> 
> Cheers, Daniel
> 
> > ---
> >  drivers/gpu/drm/drm_atomic_helper.c | 67 
> > ++---
> >  1 file changed, 40 insertions(+), 27 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index c48f187d08de..39a69508d8c9 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -2881,31 +2881,9 @@ int __drm_atomic_helper_set_config(struct 
> > drm_mode_set *set,
> > return 0;
> >  }
> >  
> > -/**
> > - * drm_atomic_helper_disable_all - disable all currently active outputs
> > - * @dev: DRM device
> > - * @ctx: lock acquisition context
> > - *
> > - * Loops through all connectors, finding those that aren't turned off and 
> > then
> > - * turns them off by setting their DPMS mode to OFF and deactivating the 
> > CRTC
> > - * that they are connected to.
> > - *
> > - * This is used for example in suspend/resume to disable all currently 
> > active
> > - * functions when suspending. If you just want to shut down everything at 
> > e.g.
> > - * driver unload, look at drm_atomic_helper_shutdown().
> > - *
> > - * Note that if callers haven't already acquired all modeset locks this 
> > might
> > - * return -EDEADLK, which must be handled by calling drm_modeset_backoff().
> > - *
> > - * Returns:
> > - * 0 on success or a negative error code on failure.
> > - *
> > - * See also:
> > - * drm_atomic_helper_suspend(), drm_atomic_helper_resume() and
> > - * drm_atomic_helper_shutdown().
> > - */
> > -int drm_atomic_helper_disable_all(struct drm_device *dev,
> > - struct drm_modeset_acquire_ctx *ctx)
> > +static int __drm_atomic_helper_disable_all(struct drm_device *dev,
> > +  struct drm_modeset_acquire_ctx *ctx,
> > +  bool clean_old_fbs)
> >  {
> > struct drm_atomic_state *state;
> > struct drm_connector_state *conn_state;
> > @@ -2914,6 +2892,7 @@ int drm_atomic_helper_disable_all(struct drm_device 
> > *dev,
> > struct drm_plane *plane;
> > struct drm_crtc_state *crtc_state;
> > struct drm_crtc *crtc;
> > +   unsigned int plane_mask = 0;
> > int ret, i;
> >  
> > state = drm_atomic_state_alloc(dev);
> > @@ -2956,14 +2935,48 @@ int drm_atomic_helper_disable_all(struct drm_device 
> > *dev,
> > goto free;
> >  
> > drm_atomic_set_fb_for_plane(plane_state, NULL);
> > +
> > +   if (clean_old_fbs) {
> > +   plane->old_fb = plane->fb;
> > +   plane_mask |= BIT(drm_plane_index(plane));
> > +   }
> > }
> >  
> > ret = drm_atomic_commit(state);
> >  free:
> > +   drm_atomic_clean_old_fb(dev, plane_mask, ret);
> > +
> > drm_atomic_state_put(state);
> > return ret;
> >  }
> > -
> > +/**
> > + * drm_atomic_helper_disable_all - disable all currently active outputs
> > + * @dev: DRM device
> > + * @ctx: lock acquisition context
> > + *
> > + * Loops through all connectors, finding those that aren't turned off and 
> > then
> > + * turns them off by setting their DPMS mode to OFF and deactivating the 
> > CRTC
> > + * that they are connected to.
> > + *
> > + * This is used for example in suspend/resume to disable all currently 
> > 

Re: [Intel-gfx] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-29 11:33:34)
> From: Tvrtko Ursulin 
> 
> intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
> register access. This patch rewrites it to use only PMU.
> 
> Only overall command streamer busyness and GPU global data such as power
> and frequencies are included in this new version.
> 
> For access to more GPU functional unit level data, an OA metric based tool
> like gpu-top should be used instead.

intel-gpu-top -  750/ 581 MHz;0% RC6;   6211mW;98952 irqs/s

 ^ easier as actual/request.  Maybe just actual?

rcs0  97.58% |█▏|  0.00% wait,   0.00% sema
bcs0  92.87% |███▌  |  0.00% wait,   0.00% sema
vcs0  92.70% |███▌  |  0.00% wait,   0.00% sema
   vecs0  92.90% |███▌  |  0.00% wait,   0.00% sema

2 decimal places seem ok for busyness, but for wait/sema seem overkill.
Drop down to 1dp for them (or all), or even 0dp. Don't fancy overlaying
them on the bar as a different colour block? ;) Hmm, already using ANSI
so you could...
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: warn only once about ddi translation table missing

[Ville Syrjälä]

On Wed, Mar 28, 2018 at 02:03:04PM -0700, Michel Thierry wrote:
> It's not like it will magically appear or disappear ;)
> 
> Signed-off-by: Michel Thierry 
> Cc: Ville Syrjälä 

Not sure why someone keeps using a driver that doesn't support the
hw they have ;)

Anyways,
Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..1558eeb13b80 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -892,7 +892,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private 
> *dev_priv, enum port por
>   intel_ddi_get_buf_trans_hdmi(dev_priv, _entries);
>   default_entry = 6;
>   } else {
> - WARN(1, "ddi translation table missing\n");
> + WARN_ONCE(1, "ddi translation table missing\n");
>   return 0;
>   }
>  
> -- 
> 2.16.2

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

Series 40503v6 series starting with [v6,1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/6/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> INCOMPLETE (fi-elk-e7500)

 Known issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:517s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:522s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:511s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:520s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:590s
fi-elk-e7500 total:284  pass:224  dwarn:1   dfail:0   fail:0   skip:58 
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:435s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:659s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:248  dwarn:11  dfail:0   fail:0   skip:26  
time:524s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
1689ed7a8137 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
5b5140ece582 drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8536/issues.html
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Re: [Intel-gfx] [PATCH] drm/edid: Dump valid EDIDs too

[Ville Syrjälä]

On Thu, Mar 29, 2018 at 05:01:13PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-03-29 16:50:23)
> > From: Ville Syrjälä 
> > 
> > Having the EDID available is often very beneficial for bug analysis,
> > even when the EDID itself is valid and not the direct cause of the
> > bug. So let's dump the EDID to dmesg even when it's valid. This
> > should also give us a better historical record of EDIDs for later
> > analysis.
> 
> Isn't this a bit frequent for a largely unchanging blob?

Perhaps. Though ideally we shouldn't go re-reading it all the time.
But I guess that's wisful thinking.

Not sure we have a good place where we could memcmp() the new EDID
against the old one and only print if it changed.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/edid: Dump valid EDIDs too

[Chris Wilson]

Quoting Ville Syrjala (2018-03-29 16:50:23)
> From: Ville Syrjälä 
> 
> Having the EDID available is often very beneficial for bug analysis,
> even when the EDID itself is valid and not the direct cause of the
> bug. So let's dump the EDID to dmesg even when it's valid. This
> should also give us a better historical record of EDIDs for later
> analysis.

Isn't this a bit frequent for a largely unchanging blob?
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Fix usage of for_each_engine_class_instance

[Michel Thierry]

On 29/03/18 02:11, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Wrong file descriptor was passed to the iterator. This had currently no
effect, since it wasn't used in the macro, but needs to be fixed.

At the same time make the macro consistent by checking for engine presence
like the other iterators do.

Added __for_each_engine_class_instance which does not check for engine
presence and so is useful for enumerating all possible engines - like for
instance for subtest enumeration.

And another 'wrong fd used' fixlet in the render node subtests.

Signed-off-by: Tvrtko Ursulin 
Reported-by: Michel Thierry 
Cc: Michel Thierry 


Thanks,

Reviewed-by: Michel Thierry 

---
  lib/igt_gt.h | 12 +++-
  tests/perf_pmu.c | 30 ++
  2 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index a517ed7b29a0..d44b7552f3c4 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -100,11 +100,6 @@ extern const struct intel_execution_engine2 {
int instance;
  } intel_execution_engines2[];
  
-#define for_each_engine_class_instance(fd__, e__) \

-   for ((e__) = intel_execution_engines2;\
-(e__)->name; \
-(e__)++)
-
  unsigned int
  gem_class_instance_to_eb_flags(int gem_fd,
   enum drm_i915_gem_engine_class class,
@@ -122,4 +117,11 @@ void gem_require_engine(int gem_fd,
igt_require(gem_has_engine(gem_fd, class, instance));
  }
  
+#define __for_each_engine_class_instance(fd__, e__) \

+   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_engine_class_instance(fd__, e__) \
+   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
+   for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+
  #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index b59af81819c7..2273ddb9e684 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,10 +434,8 @@ busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
  
  	i = 0;

fd[0] = -1;
-   for_each_engine_class_instance(fd, e_) {
-   if (!gem_has_engine(gem_fd, e_->class, e_->instance))
-   continue;
-   else if (e == e_)
+   for_each_engine_class_instance(gem_fd, e_) {
+   if (e == e_)
busy_idx = i;
  
  		fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,

@@ -499,10 +497,7 @@ most_busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
unsigned int idle_idx, i;
  
  	i = 0;

-   for_each_engine_class_instance(fd, e_) {
-   if (!gem_has_engine(gem_fd, e_->class, e_->instance))
-   continue;
-
+   for_each_engine_class_instance(gem_fd, e_) {
if (e == e_)
idle_idx = i;
else if (spin)
@@ -559,10 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int 
num_engines,
unsigned int i;
  
  	i = 0;

-   for_each_engine_class_instance(fd, e) {
-   if (!gem_has_engine(gem_fd, e->class, e->instance))
-   continue;
-
+   for_each_engine_class_instance(gem_fd, e) {
if (spin)
__submit_spin_batch(gem_fd, spin, e, 64);
else
@@ -1677,10 +1669,8 @@ igt_main
igt_require_gem(fd);
igt_require(i915_type_id() > 0);
  
-		for_each_engine_class_instance(fd, e) {

-   if (gem_has_engine(fd, e->class, e->instance))
-   num_engines++;
-   }
+   for_each_engine_class_instance(fd, e)
+   num_engines++;
}
  
  	/**

@@ -1689,7 +1679,7 @@ igt_main
igt_subtest("invalid-init")
invalid_init();
  
-	for_each_engine_class_instance(fd, e) {

+   __for_each_engine_class_instance(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
  
  		/**

@@ -1888,7 +1878,7 @@ igt_main
gem_quiescent_gpu(fd);
}
  
-		for_each_engine_class_instance(fd, e) {

+   __for_each_engine_class_instance(render_fd, e) {
igt_subtest_group {
igt_fixture {
gem_require_engine(render_fd,
@@ -1897,10 +1887,10 @@ igt_main
}
  
  igt_subtest_f("render-node-busy-%s", e->name)

-   single(fd, e, TEST_BUSY);
+   single(render_fd, e, TEST_BUSY);
igt_subtest_f("render-node-busy-idle-%s",
  e->name)
-   single(fd, e,
+ 

[Intel-gfx] [PATCH v6 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v6:
 - Updated the comment that conflict with the patch. (Chris)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++---
 1 file changed, 39 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..4c50bee 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private 
*i915, int type)
}
 }
 
+static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
+{
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+   u32 slice = fls(sseu->slice_mask);
+   u32 subslice = fls(sseu->subslice_mask[slice]);
+
+   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+   mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+   return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+   u32 mcr;
+
+   mcr = I915_READ(GEN8_MCR_SELECTOR);
+   mcr = calculate_mcr(dev_priv, mcr);
+   I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
  int subslice, i915_reg_t reg)
@@ -828,18 +849,30 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
 * The HW expects the slice and sublice selectors to be reset to 0
-* after reading out the registers.
+* before GEN10 or to a enabled s/ss post GEN10 after reading out the
+* registers.
 */
-   WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+   WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
+(mcr & mcr_slice_subslice_mask));
mcr &= ~mcr_slice_subslice_mask;
mcr |= mcr_slice_subslice_select;
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
ret = I915_READ_FW(reg);
 
-   mcr &= ~mcr_slice_subslice_mask;
+   /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+* expects mcr to be programed to a enabled slice/subslice pair
+* before any MMIO read into slice/subslice register
+*/
+   if (INTEL_GEN(dev_priv) < 10)
+   mcr &= ~mcr_slice_subslice_mask;
+   else
+   mcr = calculate_mcr(dev_priv, mcr);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1340,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
 
+   /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+   wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/edid: Dump valid EDIDs too

[Ville Syrjala]

From: Ville Syrjälä 

Having the EDID available is often very beneficial for bug analysis,
even when the EDID itself is valid and not the direct cause of the
bug. So let's dump the EDID to dmesg even when it's valid. This
should also give us a better historical record of EDIDs for later
analysis.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_edid.c | 39 +++
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 134069f36482..1153b2f74c58 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1517,17 +1517,27 @@ drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int 
block, size_t len)
return ret == xfers ? 0 : -1;
 }
 
-static void connector_bad_edid(struct drm_connector *connector,
-  u8 *edid, int num_blocks)
+static void connector_dump_edid(struct drm_connector *connector,
+   u8 *edid, int num_blocks,
+   bool valid)
 {
int i;
 
-   if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
-   return;
+   if (valid) {
+   if (!(drm_debug & DRM_UT_KMS))
+   return;
+
+   DRM_DEBUG_KMS("[CONNECTOR:%d:%s] EDID is valid:\n",
+ connector->base.id, connector->name);
+   } else {
+   if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
+   return;
+
+   dev_warn(connector->dev->dev,
+"[CONNECTOR:%d:%s] EDID is invalid:\n",
+connector->base.id, connector->name);
+   }
 
-   dev_warn(connector->dev->dev,
-"%s: EDID is invalid:\n",
-connector->name);
for (i = 0; i < num_blocks; i++) {
u8 *block = edid + i * EDID_LENGTH;
char prefix[20];
@@ -1539,7 +1549,7 @@ static void connector_bad_edid(struct drm_connector 
*connector,
else
sprintf(prefix, "\t[%02x] GOOD ", i);
 
-   print_hex_dump(KERN_WARNING,
+   print_hex_dump(valid ? KERN_DEBUG : KERN_WARNING,
   prefix, DUMP_PREFIX_NONE, 16, 1,
   block, EDID_LENGTH, false);
}
@@ -1580,8 +1590,10 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
if (!override)
override = drm_load_edid_firmware(connector);
 
-   if (!IS_ERR_OR_NULL(override))
-   return override;
+   if (!IS_ERR_OR_NULL(override)) {
+   edid = (u8 *)override;
+   goto done;
+   }
 
if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
return NULL;
@@ -1628,7 +1640,7 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
if (valid_extensions != edid[0x7e]) {
u8 *base;
 
-   connector_bad_edid(connector, edid, edid[0x7e] + 1);
+   connector_dump_edid(connector, edid, edid[0x7e] + 1, false);
 
edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
edid[0x7e] = valid_extensions;
@@ -1652,10 +1664,13 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
edid = new;
}
 
+done:
+   connector_dump_edid(connector, edid, edid[0x7e] + 1, true);
+
return (struct edid *)edid;
 
 carp:
-   connector_bad_edid(connector, edid, 1);
+   connector_dump_edid(connector, edid, 1, false);
 out:
kfree(edid);
return NULL;
-- 
2.16.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for blacklist: Don't run DRRS test on Intel CI system

[Patchwork]

== Series Details ==

Series: blacklist: Don't run DRRS test on Intel CI system
URL   : https://patchwork.freedesktop.org/series/40871/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2cbd4ddf11b3eaf01f33d8bc2ad46411ec6c299a lib/igt_kms: Improve connector probing 
in igt_display_init(), v2.

with latest DRM-Tip kernel build CI_DRM_4007
d6e43ca115e5 drm-tip: 2018y-03m-29d-12h-46m-03s UTC integration manifest

No testlist changes.

 Known issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:383s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:527s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:511s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:519s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:668s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:441s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:526s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:493s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1207/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Set queue priority from secondary port

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Set queue priority from secondary port
URL   : https://patchwork.freedesktop.org/series/40869/
State : success

== Summary ==

 Known issues:

Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3495 pass:1832 dwarn:1   dfail:0   fail:7   skip:1655 
time:12793s
shard-hswtotal:3495 pass:1783 dwarn:1   dfail:0   fail:1   skip:1709 
time:11539s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:6943s
Blacklisted hosts:
shard-kbltotal:3495 pass:1904 dwarn:55  dfail:0   fail:8   skip:1528 
time:9232s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8531/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev3)

[Patchwork]

== Series Details ==

Series: HDCP1.4 fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/38978/
State : success

== Summary ==

Series 38978v3 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/3/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:516s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:518s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:588s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:477s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:659s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:528s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:500s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:400s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:542s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
09c85a8e205c drm/i915: Fix downstream dev count read
e0351b8ec3e2 drm/i915: Check hdcp key loadability
f0df339306d6 drm/i915: Read Vprime thrice incase of mismatch
dcb5fbdd94a2 drm/i915: Read HDCP R0 thrice in case of mismatch

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8535/issues.html
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Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Fix downstream dev count read

[Sean Paul]

On Thu, Mar 29, 2018 at 07:39:08PM +0530, Ramalingam C wrote:
> In both HDMI and DP, device count is represented by 6:0 bits of a
> register(BInfo/Bstatus)
> 
> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> 


Reviewed-by: Sean Paul 

> Signed-off-by: Ramalingam C 
> cc: Sean Paul 
> ---
>  include/drm/drm_hdcp.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 562fa7df2637..98e63d870139 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -19,7 +19,7 @@
>  #define DRM_HDCP_RI_LEN  2
>  #define DRM_HDCP_V_PRIME_PART_LEN4
>  #define DRM_HDCP_V_PRIME_NUM_PARTS   5
> -#define DRM_HDCP_NUM_DOWNSTREAM(x)   (x & 0x3f)
> +#define DRM_HDCP_NUM_DOWNSTREAM(x)   (x & 0x7f)
>  #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
>  #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)  (x & BIT(7))
>  
> -- 
> 2.7.4
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Read Vprime thrice incase of mismatch

[Sean Paul]

On Thu, Mar 29, 2018 at 07:39:06PM +0530, Ramalingam C wrote:
> In case of V prime mismatch, DP HDCP spec mandates the re-read of
> Vprime atleast twice.
> 
> This patch needed for DP HDCP1.4 CTS Test: 1B-05.
> 
> v2:
>   Moved the V' validation into a function for retry. [Sean Paul]
> 
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/intel_hdcp.c | 113 
> +++---
>  1 file changed, 70 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index 96b9025dc759..f77d956b2b18 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -142,53 +142,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
>   return true;
>  }
>  
> -/* Implements Part 2 of the HDCP authorization procedure */
> -static
> -int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> -const struct intel_hdcp_shim *shim)
> +static inline

Why inline?

> +int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> + const struct intel_hdcp_shim *shim,
> + u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
>  {
>   struct drm_i915_private *dev_priv;
>   u32 vprime, sha_text, sha_leftovers, rep_ctl;
> - u8 bstatus[2], num_downstream, *ksv_fifo;
>   int ret, i, j, sha_idx;
>  
>   dev_priv = intel_dig_port->base.base.dev->dev_private;
>  
> - ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> - if (ret) {
> - DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> - return ret;
> - }
> -
> - ret = shim->read_bstatus(intel_dig_port, bstatus);
> - if (ret)
> - return ret;
> -
> - if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> - DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> - DRM_ERROR("Max Topology Limit Exceeded\n");
> - return -EPERM;
> - }
> -
> - /*
> -  * When repeater reports 0 device count, HDCP1.4 spec allows disabling
> -  * the HDCP encryption. That implies that repeater can't have its own
> -  * display. As there is no consumption of encrypted content in the
> -  * repeater with 0 downstream devices, we are failing the
> -  * authentication.
> -  */
> - num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
> - if (num_downstream == 0)
> - return -EINVAL;
> -
> - ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
> - if (!ksv_fifo)
> - return -ENOMEM;
> -
> - ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> - if (ret)
> - return ret;
> -
>   /* Process V' values from the receiver */
>   for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
>   ret = shim->read_v_prime_part(intel_dig_port, i, );
> @@ -353,7 +317,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port 
> *intel_dig_port,
>   return ret;
>   sha_idx += sizeof(sha_text);
>   } else {
> - DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
> + DRM_DEBUG("Invalid number of leftovers %d\n", sha_leftovers);
>   return -EINVAL;
>   }
>  
> @@ -381,14 +345,77 @@ int intel_hdcp_auth_downstream(struct 
> intel_digital_port *intel_dig_port,
>   if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
>   HDCP_SHA1_COMPLETE,
>   HDCP_SHA1_COMPLETE, 1)) {
> - DRM_ERROR("Timed out waiting for SHA1 complete\n");
> + DRM_DEBUG("Timed out waiting for SHA1 complete\n");
>   return -ETIMEDOUT;
>   }
>   if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
> - DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
> + DRM_DEBUG("SHA-1 mismatch, HDCP failed\n");

I think the DEBUG should be DEBUG_KMS, consistent with the rest of the file?

>   return -ENXIO;
>   }
>  
> + return 0;
> +}
> +
> +/* Implements Part 2 of the HDCP authorization procedure */
> +static
> +int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> +const struct intel_hdcp_shim *shim)
> +{
> + u8 bstatus[2], num_downstream, *ksv_fifo;
> + int ret, i, tries = 3;
> +
> + ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> + if (ret) {
> + DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> + return ret;
> + }
> +
> + ret = shim->read_bstatus(intel_dig_port, bstatus);
> + if (ret)
> + return ret;
> +
> + if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> + DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> + DRM_ERROR("Max Topology Limit Exceeded\n");
> + return -EPERM;
> + }
> +
> + /*
> + 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch

[Sean Paul]

On Thu, Mar 29, 2018 at 07:39:05PM +0530, Ramalingam C wrote:
> As per DP spec when R0 mismatch is detected, HDCP source supported
> re-read the R0 atleast twice.
> 
> And For HDMI and DP minimum wait required for the R0 availability is
> 100mSec. So this patch changes the wait time to 100mSec but retries
> twice with the time interval of 100mSec for each attempt.
> 
> This patch is needed for DP HDCP1.4 CTS Test: 1A-06.
> 
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/intel_hdcp.c | 30 +++---
>  1 file changed, 19 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index 14ca5d3057a7..96b9025dc759 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -496,9 +496,11 @@ static int intel_hdcp_auth(struct intel_digital_port 
> *intel_dig_port,
>   }
>  
>   /*
> -  * Wait for R0' to become available. The spec says 100ms from Aksv, but
> -  * some monitors can take longer than this. We'll set the timeout at
> -  * 300ms just to be sure.
> +  * Wait for R0' to become available. The spec says minimum 100ms from
> +  * Aksv, but some monitors can take longer than this. So we are
> +  * combinely waiting for 300mSec just to be sure in case of HDMI.
> +  * DP HDCP Spec mandates the two more reattempt to read R0, incase
> +  * of R0 mismatch.

I am sorry to nitpick comments, but this doesn't belong here. Leave this comment
alone and add the part about the DP spec requiring retries directly above the
loop where we're actually doing the retries.

Sean

>*
>* On DP, there's an R0_READY bit available but no such bit
>* exists on HDMI. Since the upper-bound is the same, we'll just do
> @@ -506,15 +508,21 @@ static int intel_hdcp_auth(struct intel_digital_port 
> *intel_dig_port,
>*/
>   wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
>  
> - ri.reg = 0;
> - ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> - if (ret)
> - return ret;
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + tries = 3;
> + for (i = 0; i < tries; i++) {
> + ri.reg = 0;
> + ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> + if (ret)
> + return ret;
> + I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
>  
> - /* Wait for Ri prime match */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> -  (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> + /* Wait for Ri prime match */
> + if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> + break;
> + }
> +
> + if (i == tries) {
>   DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
> I915_READ(PORT_HDCP_STATUS(port)));
>   return -ETIMEDOUT;
> -- 
> 2.7.4
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: Check hdcp key loadability

[Ville Syrjälä]

On Thu, Mar 29, 2018 at 07:39:07PM +0530, Ramalingam C wrote:
> HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
> is enabled. Using the I915 power well infrastruture, above requirement
> is verified.
> 
> This patch enables the hdcp initialization for HSW, BDW, and BXT.
> 
> v2:
>   Choose the PW# based on the platform.
> 
> Signed-off-by: Ramalingam C 
> Reviewed-by: Sean Paul 
> ---
>  drivers/gpu/drm/i915/intel_hdcp.c | 41 
> +--
>  1 file changed, 39 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index f77d956b2b18..d8af09b46a44 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct 
> intel_digital_port *intel_dig_port,
>   return 0;
>  }
>  
> +static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
> +{
> + struct i915_power_domains *power_domains = _priv->power_domains;
> + struct i915_power_well *power_well;
> + enum i915_power_well_id id;
> + bool enabled = false;
> +
> + /*
> +  * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
> +  * On all BXT+, SW can load the keys only when the PW#1 is turned on.
> +  */
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + id = HSW_DISP_PW_GLOBAL;
> + else
> + id = SKL_DISP_PW_1;
> +
> + mutex_lock(_domains->lock);
> +
> + /* PG1 (power well #1) needs to be enabled */
> + for_each_power_well(dev_priv, power_well) {
> + if (power_well->id == id) {
> + enabled = power_well->ops->is_enabled(dev_priv,
> +   power_well);
> + break;
> + }
> + }
> + mutex_unlock(_domains->lock);
> +
> + /*
> +  * Another req for hdcp key loadability is enabled state of pll for
> +  * cdclk. Without active crtc we wont land here. So we are assuming that
> +  * cdclk is already on.
> +  */
> +
> + return enabled;
> +}
> +
>  static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
>  {
>   I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
> @@ -615,8 +652,8 @@ static int _intel_hdcp_enable(struct intel_connector 
> *connector)
>   DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
> connector->base.name, connector->base.base.id);
>  
> - if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
> - DRM_ERROR("PG1 is disabled, cannot load keys\n");
> + if (!hdcp_key_loadable(dev_priv)) {
> + DRM_ERROR("HDCP key Load is not possible\n");
>   return -ENXIO;
>   }

If you need the power well then why aren't you grabbing the correct
power domain reference somewhere?

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)

[Patchwork]

== Series Details ==

Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)
URL   : https://patchwork.freedesktop.org/series/36068/
State : warning

== Summary ==

Series 36068v4 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/4/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-7567u)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-kbl-7567u)
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (fi-kbl-7567u)

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> DMESG-WARN (fi-kbl-7567u) fdo#103665
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481

fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:532s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:512s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:588s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:418s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:313s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:261  dwarn:4   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:515s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:514s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:483s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
dc7f98442172 drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
49398d81198f drm/i915: Write AVI infoframes for Parade LSPCON
e0c80446404d drm/i915: Write AVI infoframes for MCA LSPCON
0851a6cc6bb1 drm/i915: Add AVI infoframe support for LSPCON
f314d0a6f3c4 drm/i915: Check LSPCON vendor OUI
589f5c1ab004 drm/i915: Add CRTC output format YCBCR 4:4:4
ce026cbd59bf drm/i915: Add CRTC output format YCBCR 4:2:0
2b5dfa9c4aa1 drm/i915: Introduce CRTC output format

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8534/issues.html
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Re: [Intel-gfx] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

[Eero Tamminen]

Hi,

I tested this on HSW GT2, BYT, BDW GT3, SKL GT2 and KBL GT3e,
with Ubuntu 16.04 and 17.10, using Ubuntu default kernels (4.4 to 4.13)
and latest drm-tip build (4.16.0-rc7).


General comments


This will be used by our customers and people who aren't necessarily
familiar with i915 internal details.  Therefore it should use
common terminology in the field and in similar tools, instead of
I3As (Intel 3-letter Acronyms).

For example:
 - rcs -> 3D render
 - bcs -> blitter
 - vecs -> video
 - vcs -> video decode
etc.


Old tool showed also GPU system memory interface (GAM) busyness.
That was valuable info, and reasonably accurate for stable loads.

Could this tool show also either that information (preferred), or
bandwidth utilized by GPU/CPU/display?

(Latest kernels offer GPU memory bandwidth usage through perf
"uncore_imc" "data_reads" & "date_writes" counters.)


Is "wait" value supposed to be IO-wait for given engine interface?

I never saw that change from 0%, although IO-wait in top jumped
from 0 to 20-30% with my test GPU load.


HW specific test results


BYT:
* Reports "Failed to initialize PMU!" although old intel_gpu_top
  works fine.

HSW GT2,  BDW GT3, SKL GT2 and KBL GT3e seems to work fine except
for the "wait" value.

I never saw blitter engine to do anything, but that's because
modesetting uses just 3D pipeline, and because I couldn't get
Intel DDX to work with rest of latest git version of X / 3D stack.



Kernel version support
--

My HW specific testing above was with drm-tip kernel, but I did one test
also with Ubuntu 16.04 v4.4 kernel (which includes v4.6 or v4.8 i915 
backport) on KBL.  For that, the tool reported:

"Failed to detect engines!"

Although the previous intel_gpu_top works fine with that kernel version.

Same happens also with Ubuntu 17.04 v4.13 kernel.


-> If new version needs a certain kernel version, it should tell
   which version is required.



- Eero

On 29.03.2018 13:33, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.

Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.

For access to more GPU functional unit level data, an OA metric based tool
like gpu-top should be used instead.

v2:
  * Sort engines by class and instance.
  * Do not wait for one sampling period to display something on screen.
  * Move code out of the asserts. (Rinat Ibragimov)
  * Continuously adapt to terminal size. (Rinat Ibgragimov)

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Petri Latvala 
Cc: Eero Tamminen 
Cc: Rinat Ibragimov 
Reviewed-by: Lionel Landwerlin  # v1
Reviewed-by: Chris Wilson  # v0.5
---
  tools/Makefile.am |2 +
  tools/intel_gpu_top.c | 1009 +
  tools/meson.build |6 +-
  3 files changed, 441 insertions(+), 576 deletions(-)

diff --git a/tools/Makefile.am b/tools/Makefile.am
index 09b6dbcc3ece..a0b016ddd7ff 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -28,6 +28,8 @@ intel_aubdump_la_LDFLAGS = -module -avoid-version 
-no-undefined
  intel_aubdump_la_SOURCES = aubdump.c
  intel_aubdump_la_LIBADD = $(top_builddir)/lib/libintel_tools.la -ldl
  
+intel_gpu_top_LDADD = $(top_builddir)/lib/libigt_perf.la

+
  bin_SCRIPTS = intel_aubdump
  CLEANFILES = $(bin_SCRIPTS)
  
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c

index 098e6ce3ff86..94091d97c4a3 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1,6 +1,5 @@
  /*
- * Copyright © 2007 Intel Corporation
- * Copyright © 2011 Intel Corporation
+ * Copyright © 2018 Intel Corporation
   *
   * Permission is hereby granted, free of charge, to any person obtaining a
   * copy of this software and associated documentation files (the "Software"),
@@ -18,701 +17,561 @@
   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *Eugeni Dodonov 
- *
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
   */
  
-#include "config.h"

-
-#include 
-#include 
-#include 
  #include 
-#include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
  #include 
-#ifdef 

Re: [Intel-gfx] [PATCH v2 0/4] HDCP1.4 fixes

[Ramalingam C]

On Thursday 29 March 2018 07:39 PM, Ramalingam C wrote:

First two patches needed for below DP HDCP compliance tests
1A-06 and 1B-05

Third patch fixes the HDCP1.4 Key loadability check. where as fourth
one fixes the downstream device count read.

Fix for HDMI HDCP1.4 CTS tests: 1A-04 and 1A-07a are functional.
But the change from v2, as thinking to put through more regressive


The change is removed from v2*

All other changes are well tested on KBL.

--Ram


testing before upstreaming.

Ramalingam C (4):
   drm/i915: Read HDCP R0 thrice in case of mismatch
   drm/i915: Read Vprime thrice incase of mismatch
   drm/i915: Check hdcp key loadability
   drm/i915: Fix downstream dev count read

  drivers/gpu/drm/i915/intel_hdcp.c | 184 ++
  include/drm/drm_hdcp.h|   2 +-
  2 files changed, 129 insertions(+), 57 deletions(-)



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[Intel-gfx] [PATCH v2 3/4] drm/i915: Check hdcp key loadability

[Ramalingam C]

HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.

This patch enables the hdcp initialization for HSW, BDW, and BXT.

v2:
  Choose the PW# based on the platform.

Signed-off-by: Ramalingam C 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 41 +--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index f77d956b2b18..d8af09b46a44 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct 
intel_digital_port *intel_dig_port,
return 0;
 }
 
+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+{
+   struct i915_power_domains *power_domains = _priv->power_domains;
+   struct i915_power_well *power_well;
+   enum i915_power_well_id id;
+   bool enabled = false;
+
+   /*
+* On HSW and BDW, Display HW loads the Key as soon as Display resumes.
+* On all BXT+, SW can load the keys only when the PW#1 is turned on.
+*/
+   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+   id = HSW_DISP_PW_GLOBAL;
+   else
+   id = SKL_DISP_PW_1;
+
+   mutex_lock(_domains->lock);
+
+   /* PG1 (power well #1) needs to be enabled */
+   for_each_power_well(dev_priv, power_well) {
+   if (power_well->id == id) {
+   enabled = power_well->ops->is_enabled(dev_priv,
+ power_well);
+   break;
+   }
+   }
+   mutex_unlock(_domains->lock);
+
+   /*
+* Another req for hdcp key loadability is enabled state of pll for
+* cdclk. Without active crtc we wont land here. So we are assuming that
+* cdclk is already on.
+*/
+
+   return enabled;
+}
+
 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
 {
I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -615,8 +652,8 @@ static int _intel_hdcp_enable(struct intel_connector 
*connector)
DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
  connector->base.name, connector->base.base.id);
 
-   if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
-   DRM_ERROR("PG1 is disabled, cannot load keys\n");
+   if (!hdcp_key_loadable(dev_priv)) {
+   DRM_ERROR("HDCP key Load is not possible\n");
return -ENXIO;
}
 
-- 
2.7.4

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[Intel-gfx] [PATCH v2 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch

[Ramalingam C]

As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.

And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.

This patch is needed for DP HDCP1.4 CTS Test: 1A-06.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 30 +++---
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..96b9025dc759 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -496,9 +496,11 @@ static int intel_hdcp_auth(struct intel_digital_port 
*intel_dig_port,
}
 
/*
-* Wait for R0' to become available. The spec says 100ms from Aksv, but
-* some monitors can take longer than this. We'll set the timeout at
-* 300ms just to be sure.
+* Wait for R0' to become available. The spec says minimum 100ms from
+* Aksv, but some monitors can take longer than this. So we are
+* combinely waiting for 300mSec just to be sure in case of HDMI.
+* DP HDCP Spec mandates the two more reattempt to read R0, incase
+* of R0 mismatch.
 *
 * On DP, there's an R0_READY bit available but no such bit
 * exists on HDMI. Since the upper-bound is the same, we'll just do
@@ -506,15 +508,21 @@ static int intel_hdcp_auth(struct intel_digital_port 
*intel_dig_port,
 */
wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
 
-   ri.reg = 0;
-   ret = shim->read_ri_prime(intel_dig_port, ri.shim);
-   if (ret)
-   return ret;
-   I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+   tries = 3;
+   for (i = 0; i < tries; i++) {
+   ri.reg = 0;
+   ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+   if (ret)
+   return ret;
+   I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
 
-   /* Wait for Ri prime match */
-   if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
-(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+   /* Wait for Ri prime match */
+   if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+   (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+   break;
+   }
+
+   if (i == tries) {
DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
  I915_READ(PORT_HDCP_STATUS(port)));
return -ETIMEDOUT;
-- 
2.7.4

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[Intel-gfx] [PATCH v2 0/4] HDCP1.4 fixes

[Ramalingam C]

First two patches needed for below DP HDCP compliance tests
1A-06 and 1B-05

Third patch fixes the HDCP1.4 Key loadability check. where as fourth
one fixes the downstream device count read.

Fix for HDMI HDCP1.4 CTS tests: 1A-04 and 1A-07a are functional.
But the change from v2, as thinking to put through more regressive
testing before upstreaming.

Ramalingam C (4):
  drm/i915: Read HDCP R0 thrice in case of mismatch
  drm/i915: Read Vprime thrice incase of mismatch
  drm/i915: Check hdcp key loadability
  drm/i915: Fix downstream dev count read

 drivers/gpu/drm/i915/intel_hdcp.c | 184 ++
 include/drm/drm_hdcp.h|   2 +-
 2 files changed, 129 insertions(+), 57 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v2 4/4] drm/i915: Fix downstream dev count read

[Ramalingam C]

In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)

So macro for bitmasking the device_count is fixed(0x3F->0x7F).

Signed-off-by: Ramalingam C 
cc: Sean Paul 
---
 include/drm/drm_hdcp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
 #define DRM_HDCP_RI_LEN2
 #define DRM_HDCP_V_PRIME_PART_LEN  4
 #define DRM_HDCP_V_PRIME_NUM_PARTS 5
-#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)   (x & BIT(3))
 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)(x & BIT(7))
 
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)

[Patchwork]

== Series Details ==

Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)
URL   : https://patchwork.freedesktop.org/series/36068/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Introduce CRTC output format
Okay!

Commit: drm/i915: Add CRTC output format YCBCR 4:2:0
Okay!

Commit: drm/i915: Add CRTC output format YCBCR 4:4:4
Okay!

Commit: drm/i915: Check LSPCON vendor OUI
Okay!

Commit: drm/i915: Add AVI infoframe support for LSPCON
Okay!

Commit: drm/i915: Write AVI infoframes for MCA LSPCON
+drivers/gpu/drm/i915/intel_hdmi.c:2283:57:expected void ( *write_infoframe 
)( ... )
+drivers/gpu/drm/i915/intel_hdmi.c:2283:57:got void ( * )( ... )
+drivers/gpu/drm/i915/intel_hdmi.c:2283:57: warning: incorrect type in 
assignment (incompatible argument 3 (different signedness))

Commit: drm/i915: Write AVI infoframes for Parade LSPCON
Okay!

Commit: drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)

[Patchwork]

== Series Details ==

Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev4)
URL   : https://patchwork.freedesktop.org/series/36068/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2b5dfa9c4aa1 drm/i915: Introduce CRTC output format
-:86: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#86: FILE: drivers/gpu/drm/i915/intel_display.c:10688:
+   DRM_DEBUG_KMS("output format: %s\n",
+   output_formats(pipe_config->output_format));

total: 0 errors, 0 warnings, 1 checks, 139 lines checked
ce026cbd59bf drm/i915: Add CRTC output format YCBCR 4:2:0
-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/intel_display.c:7659:
+static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
+   struct intel_crtc_state *pipe_config)

-:191: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#191: FILE: drivers/gpu/drm/i915/intel_display.c:10681:
+   if (format < INTEL_OUTPUT_FORMAT_RGB ||
+   format > ARRAY_SIZE(output_format_str))

total: 0 errors, 0 warnings, 2 checks, 204 lines checked
589f5c1ab004 drm/i915: Add CRTC output format YCBCR 4:4:4
-:37: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#37: FILE: drivers/gpu/drm/i915/intel_color.c:153:
+   if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {

total: 0 errors, 0 warnings, 1 checks, 58 lines checked
f314d0a6f3c4 drm/i915: Check LSPCON vendor OUI
0851a6cc6bb1 drm/i915: Add AVI infoframe support for LSPCON
e0c80446404d drm/i915: Write AVI infoframes for MCA LSPCON
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#38: FILE: drivers/gpu/drm/i915/intel_drv.h:2159:
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state *crtc_state,

-:79: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#79: FILE: drivers/gpu/drm/i915/intel_lspcon.c:244:
+static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
+const uint8_t *buffer, ssize_t len)

-:128: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#128: FILE: drivers/gpu/drm/i915/intel_lspcon.c:293:
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state *crtc_state,

-:151: CHECK:LINE_SPACING: Please don't use multiple blank lines
#151: FILE: drivers/gpu/drm/i915/intel_lspcon.c:316:
+
+

total: 0 errors, 0 warnings, 4 checks, 110 lines checked
49398d81198f drm/i915: Write AVI infoframes for Parade LSPCON
-:56: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#56: FILE: drivers/gpu/drm/i915/intel_lspcon.c:257:
+   for (retry = 0; retry < 5; retry++) {
+

-:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#76: FILE: drivers/gpu/drm/i915/intel_lspcon.c:277:
+static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
+  uint8_t *avi_buf)

-:85: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#85: FILE: drivers/gpu/drm/i915/intel_lspcon.c:286:
+   while (block_count < 4) {
+

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/intel_lspcon.c:289:
+   DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
+  block_count);

-:97: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#97: FILE: drivers/gpu/drm/i915/intel_lspcon.c:298:
+   DRM_ERROR("Failed to write AVI IF block %d\n",
+  block_count);

-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/intel_lspcon.c:313:
+   DRM_ERROR("Failed to update (0x%x), block %d\n",
+   reg, block_count);

total: 0 errors, 0 warnings, 6 checks, 143 lines checked
dc7f98442172 drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
-:53: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#53: FILE: drivers/gpu/drm/i915/i915_reg.h:8721:
+#define  TRANS_MSA_SAMPLING_444(2<<1)
  ^

-:54: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:8722:
+#define  TRANS_MSA_CLRSP_YCBCR (2<<3)
  ^

total: 0 errors, 0 warnings, 2 checks, 128 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some plane init cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Some plane init cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/39390/
State : success

== Summary ==

Series 39390v2 drm/i915: Some plane init cleanups
https://patchwork.freedesktop.org/api/1.0/series/39390/revisions/2/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:534s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:295s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:505s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:659s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:438s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:519s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:484s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
ca6214e99d5b drm/i915: s/intel_plane/plane/ in sprite init
ddeff3237e98 drm/i915: Extract skl_universal_plane_init()
fd7566435480 drm/i915: Introduce intel_plane_alloc()
6176748cf0ba drm/i915: Move plane_state->scaler_id initialization into 
intel_create_plane_state()
2db8f3765e78 drm/i915: Add missing pixel formats for skl+ "sprites"
aec881e275b5 drm/i915: Disallow plane scaling with specific pixel formats
337d697f3b0d drm/i915: Allow horizontal mirroring for cnl+ "sprite" planes
257570f84e78 drm/i915: Don't populate plane->i9xx_plane for sprites
adcdb8e9684d drm/i915: Populate possible_crtcs for primary/cursor planes
ec13bb3a5a64 drm/i915: Fix tabs vs. spaces
dbb14497f77a drm/i915: Constify intel_plane_funcs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8533/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Track begin/end of execlists submission sequences

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Track begin/end of execlists submission sequences
URL   : https://patchwork.freedesktop.org/series/40870/
State : success

== Summary ==

Series 40870v1 drm/i915/execlists: Track begin/end of execlists submission 
sequences
https://patchwork.freedesktop.org/api/1.0/series/40870/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927
pass   -> DMESG-WARN (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:518s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:258  dwarn:1   dfail:0   fail:0   skip:26  
time:587s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:422s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:224  dwarn:0   dfail:0   fail:1   skip:60  
time:427s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:431s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:656s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:501s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:497s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:448s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:515s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:484s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC 
integration manifest
08b56dea65d9 drm/i915/execlists: Track begin/end of execlists submission 
sequences

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8532/issues.html
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Re: [Intel-gfx] [PATCH 1/1] drm/i915: move audio component intialization before audio driver use it

[Jani Nikula]

On Thu, 29 Mar 2018, Chris Wilson  wrote:
> Quoting Yang (2018-03-29 08:12:13)
>> From: Yang Shi 
>> 
>> snd_hdac driver would use the component interface from i915 driver.
>> if i915 driver do the audio component intialization too late, snd_hdac
>> driver will meet ipanic.
>> 
>> Signed-off-by: Bo He 
>> Signed-off-by: Yang Shi 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c  | 2 --
>>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 2f5209d..9d25d7e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1243,8 +1243,6 @@ static void i915_driver_register(struct 
>> drm_i915_private *dev_priv)
>> if (IS_GEN5(dev_priv))
>> intel_gpu_ips_init(dev_priv);
>>  
>> -   intel_audio_init(dev_priv);
>> -
>> /*
>>  * Some ports require correctly set-up hpd registers for detection to
>>  * work properly (leading to ghost connected connector status), e.g. 
>> VGA
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index f288bcc..a471c88 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -14468,6 +14468,8 @@ int intel_modeset_init(struct drm_device *dev)
>>  
>> dev->mode_config.funcs = _mode_funcs;
>>  
>> +   intel_audio_init(dev_priv);
>
> Has info->num_pipes been finalized yet? Does the component framework
> expose the device to the external clients (if so, it can not be done
> before we are ready).

Hmmh, the same patch seems to have been sent twice. I replied at [1].

BR,
Jani.


[1] 87k1tvciec.fsf@intel.com">http://mid.mail-archive.com/87k1tvciec.fsf@intel.com


> -Chris
> ___
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-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH i-g-t 2/2] tests/gem_eio: Add context destroyer test

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Context destroyer is supposed to trigger wedging or resets at incovenient
times and then re-use the context so either the context or driver tracking
might get confused and break.

Signed-off-by: Tvrtko Ursulin 
---
 tests/gem_eio.c | 62 +
 1 file changed, 62 insertions(+)

diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b7c5047f0816..f3a452b2265c 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -591,6 +591,62 @@ static void test_inflight_internal(int fd, unsigned int 
wait)
close(fd);
 }
 
+static void test_context_destroyer(int fd, unsigned int flags)
+{
+   uint32_t ctx0 = gem_context_create(fd);
+
+   igt_until_timeout(10) {
+   struct drm_i915_gem_execbuffer2 execbuf = { };
+   struct drm_i915_gem_exec_object2 obj = { };
+   uint32_t bbe = MI_BATCH_BUFFER_END;
+   igt_spin_t *hang;
+   unsigned int i;
+   uint32_t ctx;
+
+   gem_quiescent_gpu(fd);
+
+   igt_require(i915_reset_control(flags & TEST_WEDGE ?
+  false : true));
+
+   ctx = context_create_safe(fd);
+
+   hang = spin_sync(fd, ctx0, 0);
+
+   obj.handle = gem_create(fd, 4096);
+   gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.rsvd1 = ctx0;
+
+   for (i = 0; i < 10; i++)
+   gem_execbuf(fd, );
+
+   igt_assert_eq(__check_wait(fd, obj.handle, 100e3), 0);
+
+   igt_assert(i915_reset_control(true));
+   trigger_reset(fd);
+
+   gem_quiescent_gpu(fd);
+
+   execbuf.rsvd1 = ctx;
+   for (i = 0; i < 5; i++)
+   gem_execbuf(fd, );
+
+   execbuf.rsvd1 = ctx0;
+   for (i = 0; i < 5; i++)
+   gem_execbuf(fd, );
+
+   gem_sync(fd, obj.handle);
+   igt_spin_batch_free(fd, hang);
+   gem_context_destroy(fd, ctx);
+   gem_close(fd, obj.handle);
+
+   }
+
+   gem_context_destroy(fd, ctx0);
+}
+
 static int fd = -1;
 
 static void
@@ -635,6 +691,12 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
 
+   igt_subtest("context-destroyer")
+   test_context_destroyer(fd, 0);
+
+   igt_subtest("context-destroyer-wedge")
+   test_context_destroyer(fd, TEST_WEDGE);
+
igt_subtest_group {
const struct {
unsigned int wait;
-- 
2.14.1

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[Intel-gfx] [PATCH v6 3/8] drm/i915: Add CRTC output format YCBCR 4:4:4

[Shashank Sharma]

This patch adds support for YCBCR 4:4:4 CRTC output format.
To do this, this patch extends the existing YCBCR 4:2:0
framework by:
- Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
- Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
- Adding necessary checks in modeset sequence.

V3: Added this patch in the series
V4: Added r-b from Maarten (for v3)
Addressed review comment from Ville:
Do not use (config->output_format > CRTC_OUTPUT_RGB)
V5: Rebase
V6: Rebase and small change, to accommodate changes in patch 2

Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_color.c   |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 13 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c|  2 ++
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index bf9d8f6..e5c7602 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -149,7 +149,8 @@ static void ilk_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
limited_color_range = intel_crtc_state->limited_color_range;
 
-   if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+   if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
ilk_load_ycbcr_conversion_matrix(intel_crtc);
return;
} else if (crtc_state->ctm) {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7a732ae..4623fda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6458,8 +6458,9 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
-   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
-   pipe_config->base.ctm) {
+   if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
+pipe_config->base.ctm) {
/*
 * There is only one pipe CSC unit per pipe, and we need that
 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -7677,6 +7678,8 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc 
*crtc,
output = INTEL_OUTPUT_FORMAT_INVALID;
else
output = INTEL_OUTPUT_FORMAT_YCBCR420;
+   } else {
+   output = INTEL_OUTPUT_FORMAT_YCBCR444;
}
}
}
@@ -8319,11 +8322,13 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
 
-   if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+   if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
+
+   if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
val |= PIPEMISC_YUV420_ENABLE |
   PIPEMISC_YUV420_MODE_FULL_BLEND;
-   }
 
I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2afecfd..6282e70 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -703,6 +703,7 @@ enum intel_output_format {
INTEL_OUTPUT_FORMAT_INVALID,
INTEL_OUTPUT_FORMAT_RGB,
INTEL_OUTPUT_FORMAT_YCBCR420,
+   INTEL_OUTPUT_FORMAT_YCBCR444,
 };
 
 struct intel_crtc_state {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index f38a1de..dafdc63 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -481,6 +481,8 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder 
*encoder,
 
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
+   else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+   frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
else
frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 
-- 
2.7.4

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[Intel-gfx] [PATCH v6 8/8] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

[Shashank Sharma]

LSPCON chips can generate YCBCR outputs, if asked nicely :).

In order to generate YCBCR 4:2:0 outputs, a source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:2:0 in AVI infoframes

Whereas for YCBCR 4:4:4 outputs, the source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:4:4 in AVI infoframes

So for both 4:2:0 as well as 4:4:4 outputs, we are driving the
pipe for YCBCR 4:4:4 output, but AVI infoframe's color space
information indicates LSPCON FW to start scaling down from YCBCR
4:4:4 and generate YCBCR 4:2:0 output. As the scaling is done by
LSPCON device, we need not to reserve a scaler for 4:2:0 outputs.

V2: rebase
V3: Addressed review comments from Ville
- add enum crtc_output_format instead of bool ycbcr420
- use crtc_output_format=4:4:4 for modeset of LSPCON 4:2:0 output
  cases in this way we will have YCBCR 4:4:4 framework ready (except
  the ABI part)
V4: Added r-b from Maarten (for v3)
Addressed review comments from Ville:
- Do not add a non-atomic state variable to determine lspcon output.
  Instead add bool in CRTC state to indicate lspcon based scaling.
V5: Addressed review comments from Ville:
- Change the state bool name from external scaling to something more
  relavent.
- Keep the info and adjusted_mode structures const.
- use crtc_state instead of pipe_config.
- Push all the config change into lspcon_ycbcr420_config function.
V6: Rebase, small changes to accommodate changes in patch 2.

Cc: Ville Syrjala 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c |  7 +++
 drivers/gpu/drm/i915/intel_display.c | 12 
 drivers/gpu/drm/i915/intel_dp.c  |  4 
 drivers/gpu/drm/i915/intel_drv.h |  5 +
 drivers/gpu/drm/i915/intel_lspcon.c  | 26 ++
 6 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33e52cc..9a55fce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8718,6 +8718,8 @@ enum skl_power_gate {
 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
 
 #define  TRANS_MSA_SYNC_CLK(1<<0)
+#define  TRANS_MSA_SAMPLING_444(2<<1)
+#define  TRANS_MSA_CLRSP_YCBCR (2<<3)
 #define  TRANS_MSA_6_BPC   (0<<5)
 #define  TRANS_MSA_8_BPC   (1<<5)
 #define  TRANS_MSA_10_BPC  (2<<5)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5fcbb924..cc7f878 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1619,6 +1619,13 @@ void intel_ddi_set_pipe_settings(const struct 
intel_crtc_state *crtc_state)
break;
}
 
+   /*
+* As per DP 1.2 spec section 2.3.4.3 while sending
+* YCBCR 444 signals we should program MSA MISC1/0 fields with
+* colorspace information. The output colorspace encoding is BT601.
+*/
+   if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+   temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 4623fda..eb9cac5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7662,6 +7662,8 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc 
*crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
 
+   pipe_config->lspcon_downsampling = false;
+
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
 
@@ -7679,6 +7681,16 @@ static void intel_get_crtc_ycbcr_config(struct 
intel_crtc *crtc,
else
output = INTEL_OUTPUT_FORMAT_YCBCR420;
} else {
+   /*
+* Currently there is no interface defined to
+* check user preference between RGB/YCBCR444
+* or YCBCR420. So the only possible case for
+* YCBCR444 usage is driving YCBCR420 output
+* with LSPCON, when pipe is configured for
+* YCBCR444 output and LSPCON takes care of
+* downsampling it.
+*/
+   pipe_config->lspcon_downsampling = true;
   

[Intel-gfx] [PATCH v6 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON

[Shashank Sharma]

This patch series adds YCBCR 4:2:0 output support for LSPCON displays.
In order to indicate the color format of output, to the LSPCON device,
a source has to set and send proper AVI infoframes to LSPCON. So this
patch series:
- introduces concept of CRTC output format.
- adds AVI infoframes support for LSPCON.
- then adds YCBCR 4:2:0 and 4:4:4 output support for LSPCON.

Previous versions of this series and its review can be found here:
https://patchwork.freedesktop.org/series/28536/
https://patchwork.freedesktop.org/series/33794/

- In order to address review comment from V2, I have added 2 new patches
  in this series, hence sent V3, and then V4 and to address additional
  comments.
- V5 of the series adds a new patch (first patch) just to
  introduce CRTC_OUTPUT_FORMAT concept, and later adds patches for 4:2:0
  and 4:4:4 outputs.
- V6 fixes a warning in CI builds, related to state->get_config(). 

Sharma, Shashank (3):
  drm/i915: Check LSPCON vendor OUI
  drm/i915: Write AVI infoframes for MCA LSPCON
  drm/i915: Write AVI infoframes for Parade LSPCON

Shashank Sharma (5):
  drm/i915: Introduce CRTC output format
  drm/i915: Add CRTC output format YCBCR 4:2:0
  drm/i915: Add CRTC output format YCBCR 4:4:4
  drm/i915: Add AVI infoframe support for LSPCON
  drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

 drivers/gpu/drm/i915/i915_reg.h  |   2 +
 drivers/gpu/drm/i915/intel_color.c   |   3 +-
 drivers/gpu/drm/i915/intel_crt.c |   3 +
 drivers/gpu/drm/i915/intel_ddi.c |  28 ++-
 drivers/gpu/drm/i915/intel_display.c | 104 ---
 drivers/gpu/drm/i915/intel_dp.c  |   5 +
 drivers/gpu/drm/i915/intel_dp_mst.c  |   1 +
 drivers/gpu/drm/i915/intel_drv.h |  39 +++-
 drivers/gpu/drm/i915/intel_dsi.c |   1 +
 drivers/gpu/drm/i915/intel_dvo.c |   1 +
 drivers/gpu/drm/i915/intel_hdmi.c|  24 ++-
 drivers/gpu/drm/i915/intel_lspcon.c  | 341 +--
 drivers/gpu/drm/i915/intel_lvds.c|   2 +
 drivers/gpu/drm/i915/intel_panel.c   |   2 +-
 drivers/gpu/drm/i915/intel_sdvo.c|   1 +
 drivers/gpu/drm/i915/intel_tv.c  |   1 +
 16 files changed, 500 insertions(+), 58 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v6 2/8] drm/i915: Add CRTC output format YCBCR 4:2:0

[Shashank Sharma]

Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR formats, we will need more such flags.

This patch adds a new enum parameter for YCBCR 4:2:0 outputs, in the
CRTC output formats and then plugs it during the modeset.

V3: Added this patch in the series, to address review comments from
second patchset.
V4: Added r-b from Maarten (on v3)
Addressed review comments from Ville:
- Change the enum name to intel_output_format from crtc_output_format.
- Start the enum value (INVALID) from 0 instaed of 1.
- Set the crtc's output_format to RGB in encoder's compute_config.
V5: Broke previous patch 1 into two parts,
- first patch to add CRTC output format in general
- second patch (this one) to add YCBCR 4:2:0 output
  format specifically.
- Use ARRAY_SIZE(format_str) for output format validity check (Ville)
V6: Added a separate function to calculate crtc_state->output_format, and
calling it from various get_config function (Fix CI build warning)

Cc: Ville Syrjala 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_color.c   |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 72 +---
 drivers/gpu/drm/i915/intel_drv.h |  4 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  6 +--
 drivers/gpu/drm/i915/intel_panel.c   |  2 +-
 6 files changed, 50 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index c6a7bea..bf9d8f6 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -149,7 +149,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
limited_color_range = intel_crtc_state->limited_color_range;
 
-   if (intel_crtc_state->ycbcr420) {
+   if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
ilk_load_ycbcr_conversion_matrix(intel_crtc);
return;
} else if (crtc_state->ctm) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9..ade389a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1384,7 +1384,7 @@ static void ddi_dotclock_get(struct intel_crtc_state 
*pipe_config)
else
dotclock = pipe_config->port_clock;
 
-   if (pipe_config->ycbcr420)
+   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
dotclock *= 2;
 
if (pipe_config->pixel_multiplier)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e184e3f..7a732ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4723,7 +4723,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 */
need_scaling = src_w != dst_w || src_h != dst_h;
 
-   if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
+   if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+   scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
 
/*
@@ -6457,7 +6458,8 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
-   if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
+   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+   pipe_config->base.ctm) {
/*
 * There is only one pipe CSC unit per pipe, and we need that
 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -7653,6 +7655,35 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = chv_calc_dpll_params(refclk, );
 }
 
+static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
+   struct intel_crtc_state *pipe_config)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
+
+   if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
+   u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
+
+   if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
+   bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
+   bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
+
+   if (ycbcr420_enabled) {
+   /* We support 4:2:0 in full blend mode only */
+   if (!blend)
+   output = 

[Intel-gfx] [PATCH v6 5/8] drm/i915: Add AVI infoframe support for LSPCON

[Shashank Sharma]

In order to pass AVI infoframes to LSPCON devices, a source has to
write them in a vendor recommended method and location.

This patch series:
- adds generic LSPCON infoframe setup functions.
- registers these functions into existing AVI infoframe framework.
- triggers these functions from modeset sequence.

Next patches in the series will add vendor specific code.

V2: Added new parameter to align with new definition of
drm_hdmi_avi_infoframe_quant_range
V3: Added r-b from Maarten (for V2)
Added new parameter output_format in struct lspcon to accommodate
Ville's review comments on last patch of the series
V4: Addressed Ville's review comment
- Do not add output_format in LSPCON state, as its non-atomic. Add
  this into CRTC state (added in a later patch).
V5: Rebase
V6: Rebase

Cc: Ville Syrjala 
Cc: Imre Deak 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_ddi.c| 19 +++---
 drivers/gpu/drm/i915/intel_drv.h| 13 +-
 drivers/gpu/drm/i915/intel_hdmi.c   | 13 +++---
 drivers/gpu/drm/i915/intel_lspcon.c | 49 +
 4 files changed, 86 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ade389a..5fcbb924 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2386,10 +2386,22 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*encoder,
 
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
-   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
-   else
+   } else {
+   struct intel_lspcon *lspcon =
+   enc_to_intel_lspcon(>base);
+
intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+   if (lspcon->active) {
+   struct intel_digital_port *dig_port =
+   enc_to_dig_port(>base);
+
+   dig_port->set_infoframes(>base,
+crtc_state->has_infoframe,
+crtc_state, conn_state);
+   }
+   }
 }
 
 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
@@ -3239,8 +3251,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
MISSING_CASE(port);
}
 
-   intel_infoframe_init(intel_dig_port);
-
if (init_dp) {
if (!intel_ddi_init_dp_connector(intel_dig_port))
goto err;
@@ -3270,6 +3280,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
port_name(port));
}
 
+   intel_infoframe_init(intel_dig_port);
return;
 
 err:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c72b79e..f281ccd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1282,6 +1282,12 @@ static inline struct intel_dp *enc_to_intel_dp(struct 
drm_encoder *encoder)
return _to_dig_port(encoder)->dp;
 }
 
+static inline struct intel_lspcon *
+enc_to_intel_lspcon(struct drm_encoder *encoder)
+{
+   return _to_dig_port(encoder)->lspcon;
+}
+
 static inline struct intel_digital_port *
 dp_to_dig_port(struct intel_dp *intel_dp)
 {
@@ -1807,7 +1813,6 @@ bool intel_hdmi_handle_sink_scrambling(struct 
intel_encoder *encoder,
 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
 
-
 /* intel_lvds.c */
 void intel_lvds_init(struct drm_i915_private *dev_priv);
 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
@@ -2150,6 +2155,12 @@ void intel_color_load_luts(struct drm_crtc_state 
*crtc_state);
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
 void lspcon_resume(struct intel_lspcon *lspcon);
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
+void lspcon_set_infoframes(struct drm_encoder *encoder,
+  bool enable,
+  const struct intel_crtc_state *crtc_state,
+  const struct drm_connector_state *conn_state);
+bool lspcon_infoframe_enabled(struct drm_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
 
 /* intel_pipe_crc.c */
 int intel_pipe_crc_create(struct drm_minor *minor);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index dafdc63..7091a68 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ 

[Intel-gfx] [PATCH v6 7/8] drm/i915: Write AVI infoframes for Parade LSPCON

[Shashank Sharma]

From: "Sharma, Shashank" 

Different LSPCON vendors specify their custom methods to pass
AVI infoframes to the LSPCON chip, so does Parade tech.

This patch adds functions to arrange and write AVI infoframes
into Parade LSPCON chips.

V2: rebase
V3: Added r-b from Maarten
V4: rebase
V5: rebase
V6: rebase

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_lspcon.c | 119 +++-
 1 file changed, 118 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 149fdf1..c7755ee 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -37,6 +37,12 @@
 #define  LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
 #define  LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
 
+/* AUX addresses to write Parade AVI IF */
+#define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516
+#define LSPCON_PARADE_AVI_IF_CTRL 0x51E
+#define  LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7)
+#define LSPCON_PARADE_AVI_IF_DATA_SIZE 32
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -240,6 +246,113 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon 
*lspcon)
DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
 }
 
+static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
+{
+   u8 avi_if_ctrl;
+   u8 retry;
+   ssize_t ret;
+
+   /* Check if LSPCON FW is ready for data */
+   for (retry = 0; retry < 5; retry++) {
+
+   if (retry)
+   usleep_range(200, 300);
+
+   ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
+  _if_ctrl, 1);
+   if (ret < 0) {
+   DRM_ERROR("Failed to read AVI IF control\n");
+   return false;
+   }
+
+   if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0)
+   return true;
+   }
+
+   DRM_ERROR("Parade FW not ready to accept AVI IF\n");
+   return false;
+}
+
+static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
+  uint8_t *avi_buf)
+{
+   u8 avi_if_ctrl;
+   u8 block_count = 0;
+   u8 *data;
+   uint16_t reg;
+   ssize_t ret;
+
+   while (block_count < 4) {
+
+   if (!lspcon_parade_fw_ready(aux)) {
+   DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
+  block_count);
+   return false;
+   }
+
+   reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
+   data = avi_buf + block_count * 8;
+   ret = drm_dp_dpcd_write(aux, reg, data, 8);
+   if (ret < 0) {
+   DRM_ERROR("Failed to write AVI IF block %d\n",
+  block_count);
+   return false;
+   }
+
+   /*
+* Once a block of data is written, we have to inform the FW
+* about this by writing into avi infoframe control register:
+* - set the kickoff bit[7] to 1
+* - write the block no. to bits[1:0]
+*/
+   reg = LSPCON_PARADE_AVI_IF_CTRL;
+   avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
+   ret = drm_dp_dpcd_write(aux, reg, _if_ctrl, 1);
+   if (ret < 0) {
+   DRM_ERROR("Failed to update (0x%x), block %d\n",
+   reg, block_count);
+   return false;
+   }
+
+   block_count++;
+   }
+
+   DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
+   return true;
+}
+
+static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
+  const uint8_t *frame,
+  ssize_t len)
+{
+   uint8_t avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
+
+   /*
+* Parade's frames contains 32 bytes of data, divided
+* into 4 frames:
+*  Token byte (first byte of first frame, must be non-zero)
+*  HB0 to HB2   from AVI IF (3 bytes header)
+*  PB0 to PB27 from AVI IF (28 bytes data)
+* So it should look like this
+*  first block: ||
+*  next 3 blocks: 
+*/
+
+   if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
+   DRM_ERROR("Invalid length of infoframes\n");
+   return false;
+   }
+
+   memcpy(_if[1], frame, len);
+
+   if 

[Intel-gfx] [PATCH v6 6/8] drm/i915: Write AVI infoframes for MCA LSPCON

[Shashank Sharma]

From: "Sharma, Shashank" 

As LSPCON is a DP branch device, LSPCON vendors define
specific methods to pass AVI infoframes to the the chip.
This patch adds:
- a generic wrapper function for writing AVI infoframes for
  all LSPCON devices.
- a vendor specific function to wrire AVI infoframes into
  MCA LSPCON devices.

V2: Rebase
V3: Added r-b from Maarten
V4: Rebase
V5: Rebase
V6: Rebase

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_drv.h|  4 ++
 drivers/gpu/drm/i915/intel_hdmi.c   |  2 +
 drivers/gpu/drm/i915/intel_lspcon.c | 80 +
 3 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f281ccd..46297f3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2155,6 +2155,10 @@ void intel_color_load_luts(struct drm_crtc_state 
*crtc_state);
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
 void lspcon_resume(struct intel_lspcon *lspcon);
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+enum hdmi_infoframe_type type,
+const void *buf, ssize_t len);
 void lspcon_set_infoframes(struct drm_encoder *encoder,
   bool enable,
   const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 7091a68..176a8db 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2280,6 +2280,8 @@ void intel_infoframe_init(struct intel_digital_port 
*intel_dig_port)
intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
} else if (HAS_DDI(dev_priv)) {
if (intel_dig_port->lspcon.active) {
+   intel_dig_port->write_infoframe =
+   lspcon_write_infoframe;
intel_dig_port->set_infoframes = lspcon_set_infoframes;
intel_dig_port->infoframe_enabled =
lspcon_infoframe_enabled;
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 56526eb..149fdf1 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -31,6 +31,12 @@
 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
+/* AUX addresses to write MCA AVI IF */
+#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
+#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
+#define  LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
+#define  LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -234,6 +240,80 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon 
*lspcon)
DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
 }
 
+static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
+const uint8_t *buffer, ssize_t len)
+{
+   int ret;
+   uint32_t val = 0;
+   uint16_t reg;
+   const uint8_t *data = buffer;
+
+   reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
+   while (val < len) {
+   ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD write failed, add:0x%x\n", reg);
+   return false;
+   }
+   val++; reg++; data++;
+   }
+
+   val = 0;
+   reg = LSPCON_MCA_AVI_IF_CTRL;
+   ret = drm_dp_dpcd_read(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */
+   val &= ~LSPCON_MCA_AVI_IF_HANDLED;
+   val |= LSPCON_MCA_AVI_IF_KICKOFF;
+
+   ret = drm_dp_dpcd_write(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   val = 0;
+   ret = drm_dp_dpcd_read(aux, reg, , 1);
+   if (ret < 0) {
+   DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+   return false;
+   }
+
+   if (val == LSPCON_MCA_AVI_IF_HANDLED)
+   DRM_DEBUG_KMS("AVI IF handled by FW\n");
+
+   return true;
+}
+
+void lspcon_write_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state 

[Intel-gfx] [PATCH v6 1/8] drm/i915: Introduce CRTC output format

[Shashank Sharma]

This patch adds an enum "intel_output_format" to represent
the output format of a particular CRTC. This enum will be
used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format
during the atomic modeset calculations.

V5:
- Created this separate patch to introduce and init output_format.
- Initialize parameters of output_format_str respectively (Jani N).
- Call it intel_output_format than crtc_output_format(Ville).
- Set output format in pipe_config for every encoder (Ville).
- Get rid of extra DRM_DEBUG_KMS during get_pipe_config (Ville)

V6: Rebase

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_crt.c |  3 +++
 drivers/gpu/drm/i915/intel_display.c | 17 +
 drivers/gpu/drm/i915/intel_dp.c  |  1 +
 drivers/gpu/drm/i915/intel_dp_mst.c  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  8 
 drivers/gpu/drm/i915/intel_dsi.c |  1 +
 drivers/gpu/drm/i915/intel_dvo.c |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c|  1 +
 drivers/gpu/drm/i915/intel_lvds.c|  2 ++
 drivers/gpu/drm/i915/intel_sdvo.c|  1 +
 drivers/gpu/drm/i915/intel_tv.c  |  1 +
 11 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c0a8805..b42c22d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -337,6 +337,7 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
+   pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return true;
 }
 
@@ -345,6 +346,7 @@ static bool pch_crt_compute_config(struct intel_encoder 
*encoder,
   struct drm_connector_state *conn_state)
 {
pipe_config->has_pch_encoder = true;
+   pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 
return true;
 }
@@ -356,6 +358,7 @@ static bool hsw_crt_compute_config(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
pipe_config->has_pch_encoder = true;
+   pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 
/* LPT FDI RX only supports 8bpc. */
if (HAS_PCH_LPT(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3acd757..e184e3f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9324,6 +9324,7 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
}
}
 
+   pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
power_domain_mask |= BIT_ULL(power_domain);
@@ -10652,6 +10653,18 @@ static void snprintf_output_types(char *buf, size_t 
len,
WARN_ON_ONCE(output_types != 0);
 }
 
+static const char * const output_format_str[] = {
+   [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
+   [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
+};
+
+static const char *output_formats(enum intel_output_format format)
+{
+   if (format != INTEL_OUTPUT_FORMAT_RGB)
+   format = INTEL_OUTPUT_FORMAT_INVALID;
+   return output_format_str[format];
+}
+
 static void intel_dump_pipe_config(struct intel_crtc *crtc,
   struct intel_crtc_state *pipe_config,
   const char *context)
@@ -10671,6 +10684,9 @@ static void intel_dump_pipe_config(struct intel_crtc 
*crtc,
DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
  buf, pipe_config->output_types);
 
+   DRM_DEBUG_KMS("output format: %s\n",
+   output_formats(pipe_config->output_format));
+
DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
  transcoder_name(pipe_config->cpu_transcoder),
  pipe_config->pipe_bpp, pipe_config->dither);
@@ -11250,6 +11266,7 @@ intel_pipe_config_compare(struct drm_i915_private 
*dev_priv,
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
 
PIPE_CONF_CHECK_I(pixel_multiplier);
+   PIPE_CONF_CHECK_I(output_format);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62f82c4..4eb2fe9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1722,6 +1722,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
 
+   pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;

[Intel-gfx] [PATCH v6 4/8] drm/i915: Check LSPCON vendor OUI

[Shashank Sharma]

From: "Sharma, Shashank" 

Intel LSPCON chip is provided by 2 vendors:
- Megachips America (MCA)
- Parade technologies (Parade tech)

Its important to know the vendor of this chip, as the address to
write AVI infoframes is different for those two.

This patch reads the vendor OUI signature, and marks into LSPCON
encoder structure for future usages.

This patch also does a small re-arrangement of the code, by moving
lspcon mode change into probe function.

V2: Use dp->desc for OUI detection, dont add a helper for this
(Ville)
V3: Rebase, Added r-b from Maarten
V4: Rebase
V5: Rebase
V6: Rebase

Cc: Imre Deak 
Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Reviewed-by: Lankhorst 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_drv.h|  6 
 drivers/gpu/drm/i915/intel_lspcon.c | 69 +
 2 files changed, 61 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6282e70..c72b79e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1148,9 +1148,15 @@ struct intel_dp {
struct intel_dp_compliance compliance;
 };
 
+enum lspcon_vendor {
+   LSPCON_VENDOR_MCA,
+   LSPCON_VENDOR_PARADE
+};
+
 struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
+   enum lspcon_vendor vendor;
 };
 
 struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c 
b/drivers/gpu/drm/i915/intel_lspcon.c
index 8ae8f42..40929c2 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -27,6 +27,10 @@
 #include 
 #include "intel_drv.h"
 
+/* LSPCON OUI Vendor ID(signatures) */
+#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
+#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+
 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
 {
struct intel_digital_port *dig_port =
@@ -50,6 +54,40 @@ static const char *lspcon_mode_name(enum drm_lspcon_mode 
mode)
}
 }
 
+static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
+{
+   struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+   struct drm_dp_dpcd_ident *ident;
+   u32 vendor_oui;
+
+   if (drm_dp_read_desc(>aux, >desc, drm_dp_is_branch(dp->dpcd))) {
+   DRM_ERROR("Can't read description\n");
+   return false;
+   }
+
+   ident = >desc.ident;
+   vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) |
+ ident->oui[2];
+
+   switch (vendor_oui) {
+   case LSPCON_VENDOR_MCA_OUI:
+   lspcon->vendor = LSPCON_VENDOR_MCA;
+   DRM_DEBUG_KMS("Vendor: Mega Chips\n");
+   break;
+
+   case LSPCON_VENDOR_PARADE_OUI:
+   lspcon->vendor = LSPCON_VENDOR_PARADE;
+   DRM_DEBUG_KMS("Vendor: Parade Tech\n");
+   break;
+
+   default:
+   DRM_ERROR("Invalid/Unknown vendor OUI\n");
+   return false;
+   }
+
+   return true;
+}
+
 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon 
*lspcon)
 {
enum drm_lspcon_mode current_mode;
@@ -159,7 +197,18 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
/* Yay ... got a LSPCON device */
DRM_DEBUG_KMS("LSPCON detected\n");
lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
-   lspcon->active = true;
+
+   /*
+* In the SW state machine, lets Put LSPCON in PCON mode only.
+* In this way, it will work with both HDMI 1.4 sinks as well as HDMI
+* 2.0 sinks.
+*/
+   if (lspcon->active && lspcon->mode != DRM_LSPCON_MODE_PCON) {
+   if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
+   DRM_ERROR("LSPCON mode change to PCON failed\n");
+   return false;
+   }
+   }
return true;
 }
 
@@ -230,25 +279,17 @@ bool lspcon_init(struct intel_digital_port 
*intel_dig_port)
return false;
}
 
-   /*
-   * In the SW state machine, lets Put LSPCON in PCON mode only.
-   * In this way, it will work with both HDMI 1.4 sinks as well as HDMI
-   * 2.0 sinks.
-   */
-   if (lspcon->active && lspcon->mode != DRM_LSPCON_MODE_PCON) {
-   if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
-   DRM_ERROR("LSPCON mode change to PCON failed\n");
-   return false;
-   }
-   }
-
if (!intel_dp_read_dpcd(dp)) {
DRM_ERROR("LSPCON DPCD read failed\n");
return false;
}
 
-   drm_dp_read_desc(>aux, >desc, drm_dp_is_branch(dp->dpcd));
+   if (!lspcon_detect_vendor(lspcon)) {
+   DRM_ERROR("LSPCON vendor 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev6)

[Patchwork]

== Series Details ==

Series: Add NV12 support (rev6)
URL   : https://patchwork.freedesktop.org/series/39670/
State : failure

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-blt:
pass   -> FAIL   (shard-apl)
Test kms_plane:
Subgroup pixel-format-pipe-a-planes:
pass   -> DMESG-WARN (shard-apl)
Subgroup pixel-format-pipe-b-planes:
pass   -> DMESG-WARN (shard-apl)
Test kms_plane_scaling:
Subgroup pipe-a-scaler-with-clipping-clamping:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-a-scaler-with-pixel-format:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-a-scaler-with-rotation:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-b-scaler-with-clipping-clamping:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-b-scaler-with-pixel-format:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-b-scaler-with-rotation:
pass   -> DMESG-WARN (shard-apl)

 Known issues:

Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540 +1
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup 2x-modeset-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060 +1
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3495 pass:1823 dwarn:9   dfail:0   fail:8   skip:1655 
time:12884s
shard-hswtotal:3449 pass:1763 dwarn:1   dfail:0   fail:3   skip:1680 
time:11066s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:6961s
Blacklisted hosts:
shard-kbltotal:3410 pass:1898 dwarn:7   dfail:1   fail:8   skip:1494 
time:8546s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8529/shards.html
___
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Re: [Intel-gfx] [PATCH 1/1] drm/i915: move audio component intialization before audio driver use it

[Chris Wilson]

Quoting Yang (2018-03-29 08:12:13)
> From: Yang Shi 
> 
> snd_hdac driver would use the component interface from i915 driver.
> if i915 driver do the audio component intialization too late, snd_hdac
> driver will meet ipanic.
> 
> Signed-off-by: Bo He 
> Signed-off-by: Yang Shi 
> ---
>  drivers/gpu/drm/i915/i915_drv.c  | 2 --
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f5209d..9d25d7e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1243,8 +1243,6 @@ static void i915_driver_register(struct 
> drm_i915_private *dev_priv)
> if (IS_GEN5(dev_priv))
> intel_gpu_ips_init(dev_priv);
>  
> -   intel_audio_init(dev_priv);
> -
> /*
>  * Some ports require correctly set-up hpd registers for detection to
>  * work properly (leading to ghost connected connector status), e.g. 
> VGA
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index f288bcc..a471c88 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14468,6 +14468,8 @@ int intel_modeset_init(struct drm_device *dev)
>  
> dev->mode_config.funcs = _mode_funcs;
>  
> +   intel_audio_init(dev_priv);

Has info->num_pipes been finalized yet? Does the component framework
expose the device to the external clients (if so, it can not be done
before we are ready).
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add basic sanitychecks for execlists

[kbuild test robot]

Hi Chris,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.16-rc7 next-20180328]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-selftests-Add-basic-sanitychecks-for-execlists/20180329-183934
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x011-201812 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/intel_lrc.c:2547:0:
   drivers/gpu/drm/i915/selftests/intel_lrc.c: In function 'wedge_me':
>> drivers/gpu/drm/i915/selftests/intel_lrc.c:176:2: error: implicit 
>> declaration of function 'GEM_TRACE_DUMP'; did you mean 'GEM_TRACE'? 
>> [-Werror=implicit-function-declaration]
 GEM_TRACE_DUMP();
 ^~
 GEM_TRACE
   cc1: all warnings being treated as errors

vim +176 drivers/gpu/drm/i915/selftests/intel_lrc.c

   168  
   169  static void wedge_me(struct work_struct *work)
   170  {
   171  struct wedge_me *w = container_of(work, typeof(*w), work.work);
   172  
   173  pr_err("%pS timed out, cancelling all further testing.\n", 
w->symbol);
   174  
   175  GEM_TRACE("%pS timed out.\n", w->symbol);
 > 176  GEM_TRACE_DUMP();
   177  
   178  i915_gem_set_wedged(w->i915);
   179  }
   180  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] drm/i915: move audio component intialization before audio driver use it

[Patchwork]

== Series Details ==

Series: series starting with [1/1] drm/i915: move audio component intialization 
before audio driver use it
URL   : https://patchwork.freedesktop.org/series/40858/
State : success

== Summary ==

 Known issues:

Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 
time:12847s
shard-hswtotal:3495 pass:1782 dwarn:1   dfail:0   fail:2   skip:1709 
time:11560s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:6936s
Blacklisted hosts:
shard-kbltotal:3495 pass:1959 dwarn:1   dfail:0   fail:7   skip:1528 
time:9189s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8528/shards.html
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Ville Syrjälä]

On Thu, Mar 29, 2018 at 12:28:48PM +0200, Maarten Lankhorst wrote:
> Op 29-03-18 om 11:19 schreef Srinivas, Vidya:
> >
> >> -Original Message-
> >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> >> Sent: Thursday, March 29, 2018 2:19 PM
> >> To: Srinivas, Vidya ; intel-
> >> g...@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult 
> >> of
> >> 4 for NV12
> >>
> >> Op 29-03-18 om 10:06 schreef Vidya Srinivas:
> >>> As per display WA 1106, to avoid corruption issues
> >>> NV12 plane height needs to be multiplier of 4 Hence we modify the fb
> >>> src and destination height and width to be multiples of 4. Without
> >>> this, pipe fifo underruns were seen on APL and KBL.
> >>>
> >>> Credits-to: Maarten Lankhorst 
> >>> Signed-off-by: Vidya Srinivas 
> >>> ---
> >>>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> >>>  drivers/gpu/drm/i915/intel_sprite.c | 8 
> >>>  2 files changed, 10 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >>> b/drivers/gpu/drm/i915/intel_drv.h
> >>> index 9c58da0..a1f718d 100644
> >>> --- a/drivers/gpu/drm/i915/intel_drv.h
> >>> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >>> @@ -159,6 +159,8 @@
> >>>  #define INTEL_I2C_BUS_DVO 1
> >>>  #define INTEL_I2C_BUS_SDVO 2
> >>>
> >>> +#define MULT4(x) ((x + 3) & ~0x03)
> >>> +
> >>>  /* these are outputs from the chip - integrated only
> >>> external chips are via DVO or SDVO output */  enum
> >>> intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >>> b/drivers/gpu/drm/i915/intel_sprite.c
> >>> index 538d938..9f466c6 100644
> >>> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >>> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> >>>   crtc_w--;
> >>>   crtc_h--;
> >>>
> >>> + if (fb->format->format == DRM_FORMAT_NV12) {
> >>> + src_w = MULT4(src_w);
> >>> + src_h = MULT4(src_h);
> >>> + crtc_w = MULT4(crtc_w);
> >>> + crtc_h = MULT4(crtc_h);
> >>> + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> >> crtc_h);
> >>> + }
> >>> +
> >>>   spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >>>
> >>>   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> Nearly there!
> >>
> >> Do we have limitations for width too? But I think we shouldn't ever adjust
> >> src for any format.
> >> This means that we should probably get rid of the drm_rect_adjust_size call
> >> in intel_check_sprite_plane.
> >>
> >> If any limitations of NV12 are hit, we should reject with -EINVAL instead 
> >> so
> >> userspace can decide what to do.
> >> The best place to put those checks is probably in skl_update_scaler, where
> >> they will be checked by the primary plane too.
> >>
> >> This will mean the tests fail, but that can be fixed by selecting 16 as
> >> width/height for NV12 in IGT. If you change it to 16 you can put my r-b on 
> >> it.
> >>
> >> Also I think we should put the same limitations for width and height being 
> >> a
> >> multiple in intel_framebuffer_init.
> >>
> >> And on a final note for patch ordering, put the workaround and gen10 patch
> >> before enabling nv12 support.
> > Thank you. Okay, I will make these changes and check once. The limitation in
> > Framebuffer init is already present where it expects width and height >= 16
> > As per bspec no minimum for width has been mentioned. And regarding the
> > Add check for primary plane (same like sprite), can we add that as a 
> > separate patch
> > Because if we add it with NV12 series, it would be like adding the changes 
> > and 
> > Returning before executing them.
> I don't think we'll lose much if we fail to create a fb that's not a multiple 
> of 4 in
> height and width. Since the NV12 format is defined in terms of 4x4 pixel 
> blocks,
> I don't think it would be a loss to fail to create it, if we can't even 
> display it.

The fb size is pretty much irrelevant since you can scan out just part
of it anyway.

Anyway, as far as the src rect adjustments for sprites go, I guess we
can just switch SKL sprites over to the primary plane codepath and add
the relevant checks there. Hmm, and it looks like the primary plane
packed YUV stuff is already pretty much broken since we don't check
for odd widths there.

Anyway I just hacked together this:
git://github.com/vsyrjala/linux.git plane_check_skl

It's sittin on top of https://patchwork.freedesktop.org/series/39390/,
which itself could use some review...

> > Right now range check only exists for NV12 in skl_update_scaler. My worry 
> > was:
> > If the width and height are not multiplier of 4 do we return from 
> > skl_update_scaler?
> We should always refuse to show when the src height is not a multiple of 4, 
> and return -EINVAL.
> > What if some other user level program wants to set src width and height 
> > 23x23 etc?
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Set queue priority from secondary port

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Set queue priority from secondary port
URL   : https://patchwork.freedesktop.org/series/40869/
State : success

== Summary ==

Series 40869v1 drm/i915/execlists: Set queue priority from secondary port
https://patchwork.freedesktop.org/api/1.0/series/40869/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-cfl-s3) fdo#100368
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481 +1

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:295s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:518s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:593s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:439s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:582s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:525s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s

4668e88d66074a81aae645e0db0391e7ea9afe8a drm-tip: 2018y-03m-28d-20h-45m-29s UTC 
integration manifest
c8d32fcce635 drm/i915/execlists: Set queue priority from secondary port

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8531/issues.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Include the HW breadcrumb whenever we trace the global_seqno

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-29 10:43:11)
> 
> On 29/03/2018 09:55, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-03-29 09:42:52)
> >>
> >> On 27/03/2018 22:01, Chris Wilson wrote:
> >>> When we include a request's global_seqno in a GEM_TRACE it often helps
> >>> to know how that relates to the current breadcrumb as seen by the
> >>> hardware.
> >>>
> >>> Signed-off-by: Chris Wilson 
> >>> ---
> >>>drivers/gpu/drm/i915/i915_request.c | 28 +---
> >>>drivers/gpu/drm/i915/intel_lrc.c|  6 --
> >>>2 files changed, 21 insertions(+), 13 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> >>> b/drivers/gpu/drm/i915/i915_request.c
> >>> index 2314a26cd7f8..585242831974 100644
> >>> --- a/drivers/gpu/drm/i915/i915_request.c
> >>> +++ b/drivers/gpu/drm/i915/i915_request.c
> >>> @@ -214,8 +214,11 @@ static int reset_all_global_seqno(struct 
> >>> drm_i915_private *i915, u32 seqno)
> >>>struct i915_gem_timeline *timeline;
> >>>struct intel_timeline *tl = engine->timeline;
> >>>
> >>> - GEM_TRACE("%s seqno %d -> %d\n",
> >>> -   engine->name, tl->seqno, seqno);
> >>> + GEM_TRACE("%s seqno %d (current %d) -> %d\n",
> >>> +   engine->name,
> >>> +   tl->seqno,
> >>> +   intel_engine_get_seqno(engine),
> >>> +   seqno);
> >>>
> >>>if (!i915_seqno_passed(seqno, tl->seqno)) {
> >>>/* Flush any waiters before we reuse the seqno */
> >>> @@ -386,10 +389,11 @@ static void i915_request_retire(struct i915_request 
> >>> *request)
> >>>struct intel_engine_cs *engine = request->engine;
> >>>struct i915_gem_active *active, *next;
> >>>
> >>> - GEM_TRACE("%s(%d) fence %llx:%d, global_seqno %d\n",
> >>> -   engine->name, intel_engine_get_seqno(engine),
> >>> + GEM_TRACE("%s fence %llx:%d, global_seqno %d, current %d\n",
> >>> +   engine->name,
> >>>  request->fence.context, request->fence.seqno,
> >>> -   request->global_seqno);
> >>> +   request->global_seqno,
> >>> +   intel_engine_get_seqno(engine));
> >>>
> >>>lockdep_assert_held(>i915->drm.struct_mutex);
> >>>GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
> >>> @@ -508,10 +512,11 @@ void __i915_request_submit(struct i915_request 
> >>> *request)
> >>>struct intel_engine_cs *engine = request->engine;
> >>>u32 seqno;
> >>>
> >>> - GEM_TRACE("%s fence %llx:%d -> global_seqno %d\n",
> >>> -   request->engine->name,
> >>> + GEM_TRACE("%s fence %llx:%d -> global_seqno %d, current %d\n",
> >>> +   engine->name,
> >>>  request->fence.context, request->fence.seqno,
> >>> -   engine->timeline->seqno + 1);
> >>> +   engine->timeline->seqno + 1,
> >>> +   intel_engine_get_seqno(engine));
> >>>
> >>>GEM_BUG_ON(!irqs_disabled());
> >>>lockdep_assert_held(>timeline->lock);
> >>> @@ -557,10 +562,11 @@ void __i915_request_unsubmit(struct i915_request 
> >>> *request)
> >>>{
> >>>struct intel_engine_cs *engine = request->engine;
> >>>
> >>> - GEM_TRACE("%s fence %llx:%d <- global_seqno %d\n",
> >>> -   request->engine->name,
> >>> + GEM_TRACE("%s fence %llx:%d <- global_seqno %d, current %d\n",
> >>> +   engine->name,
> >>>  request->fence.context, request->fence.seqno,
> >>> -   request->global_seqno);
> >>> +   request->global_seqno,
> >>> +   intel_engine_get_seqno(engine));
> >>>
> >>>GEM_BUG_ON(!irqs_disabled());
> >>>lockdep_assert_held(>timeline->lock);
> >>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> >>> b/drivers/gpu/drm/i915/intel_lrc.c
> >>> index ed2c833a8b20..b5235f52a81b 100644
> >>> --- a/drivers/gpu/drm/i915/intel_lrc.c
> >>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >>> @@ -454,10 +454,11 @@ static void execlists_submit_ports(struct 
> >>> intel_engine_cs *engine)
> >>>desc = execlists_update_context(rq);
> >>>GEM_DEBUG_EXEC(port[n].context_id = 
> >>> upper_32_bits(desc));
> >>>
> >>> - GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%x, 
> >>> prio=%d\n",
> >>> + GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%d (current 
> >>> %d), prio=%d\n",
> >>>  engine->name, n,
> >>>  port[n].context_id, count,
> >>>  rq->global_seqno,
> >>> +   intel_engine_get_seqno(engine),
> >>>  rq_prio(rq));
> >>>} else {
> >>>GEM_BUG_ON(!n);
> >>> @@ -999,10 

Re: [Intel-gfx] [PATCH] drm: Use srcu to protect drm_device.unplugged

[Oleksandr Andrushchenko]

On 03/28/2018 06:09 PM, Daniel Vetter wrote:

On Wed, Mar 28, 2018 at 10:38:35AM +0300, Oleksandr Andrushchenko wrote:

From: Noralf Trønnes 

Use srcu to protect drm_device.unplugged in a race free manner.
Drivers can use drm_dev_enter()/drm_dev_exit() to protect and mark
sections preventing access to device resources that are not available
after the device is gone.

Suggested-by: Daniel Vetter 
Signed-off-by: Noralf Trønnes 
Signed-off-by: Oleksandr Andrushchenko 
Reviewed-by: Oleksandr Andrushchenko 
Tested-by: Oleksandr Andrushchenko 
Cc: intel-gfx@lists.freedesktop.org

Reviewed-by: Daniel Vetter 

Oleksandr, please push to drm-misc-next once you have dim tools setup up
and everything.

Pushed to drm-misc-next


Thanks, Daniel

Thank you,
Oleksandr

---
  drivers/gpu/drm/drm_drv.c | 54 ++-
  include/drm/drm_device.h  |  9 +++-
  include/drm/drm_drv.h | 15 +
  3 files changed, 68 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index a1b9338736e3..32a83b41ab61 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -32,6 +32,7 @@
  #include 
  #include 
  #include 
+#include 
  
  #include 

  #include 
@@ -75,6 +76,8 @@ static bool drm_core_init_complete = false;
  
  static struct dentry *drm_debugfs_root;
  
+DEFINE_STATIC_SRCU(drm_unplug_srcu);

+
  /*
   * DRM Minors
   * A DRM device can provide several char-dev interfaces on the DRM-Major. Each
@@ -318,18 +321,51 @@ void drm_put_dev(struct drm_device *dev)
  }
  EXPORT_SYMBOL(drm_put_dev);
  
-static void drm_device_set_unplugged(struct drm_device *dev)

+/**
+ * drm_dev_enter - Enter device critical section
+ * @dev: DRM device
+ * @idx: Pointer to index that will be passed to the matching drm_dev_exit()
+ *
+ * This function marks and protects the beginning of a section that should not
+ * be entered after the device has been unplugged. The section end is marked
+ * with drm_dev_exit(). Calls to this function can be nested.
+ *
+ * Returns:
+ * True if it is OK to enter the section, false otherwise.
+ */
+bool drm_dev_enter(struct drm_device *dev, int *idx)
+{
+   *idx = srcu_read_lock(_unplug_srcu);
+
+   if (dev->unplugged) {
+   srcu_read_unlock(_unplug_srcu, *idx);
+   return false;
+   }
+
+   return true;
+}
+EXPORT_SYMBOL(drm_dev_enter);
+
+/**
+ * drm_dev_exit - Exit device critical section
+ * @idx: index returned from drm_dev_enter()
+ *
+ * This function marks the end of a section that should not be entered after
+ * the device has been unplugged.
+ */
+void drm_dev_exit(int idx)
  {
-   smp_wmb();
-   atomic_set(>unplugged, 1);
+   srcu_read_unlock(_unplug_srcu, idx);
  }
+EXPORT_SYMBOL(drm_dev_exit);
  
  /**

   * drm_dev_unplug - unplug a DRM device
   * @dev: DRM device
   *
   * This unplugs a hotpluggable DRM device, which makes it inaccessible to
- * userspace operations. Entry-points can use drm_dev_is_unplugged(). This
+ * userspace operations. Entry-points can use drm_dev_enter() and
+ * drm_dev_exit() to protect device resources in a race free manner. This
   * essentially unregisters the device like drm_dev_unregister(), but can be
   * called while there are still open users of @dev.
   */
@@ -338,10 +374,18 @@ void drm_dev_unplug(struct drm_device *dev)
drm_dev_unregister(dev);
  
  	mutex_lock(_global_mutex);

-   drm_device_set_unplugged(dev);
if (dev->open_count == 0)
drm_dev_put(dev);
mutex_unlock(_global_mutex);
+
+   /*
+* After synchronizing any critical read section is guaranteed to see
+* the new value of ->unplugged, and any critical section which might
+* still have seen the old value of ->unplugged is guaranteed to have
+* finished.
+*/
+   dev->unplugged = true;
+   synchronize_srcu(_unplug_srcu);
  }
  EXPORT_SYMBOL(drm_dev_unplug);
  
diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h

index 7c4fa32f3fc6..3a0eac2885b7 100644
--- a/include/drm/drm_device.h
+++ b/include/drm/drm_device.h
@@ -46,7 +46,14 @@ struct drm_device {
/* currently active master for this device. Protected by master_mutex */
struct drm_master *master;
  
-	atomic_t unplugged;			/**< Flag whether dev is dead */

+   /**
+* @unplugged:
+*
+* Flag to tell if the device has been unplugged.
+* See drm_dev_enter() and drm_dev_is_unplugged().
+*/
+   bool unplugged;
+
struct inode *anon_inode;   /**< inode for private 
address-space */
char *unique;   /**< unique name of the device 
*/
/*@} */
diff --git a/include/drm/drm_drv.h 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Set queue priority from secondary port

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Set queue priority from secondary port
URL   : https://patchwork.freedesktop.org/series/40869/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c8d32fcce635 drm/i915/execlists: Set queue priority from secondary port
-:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#25: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between 
submission ports")

-:25: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit f6322eddaff7 
("drm/i915/preemption: Allow preemption between submission ports")'
#25: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between 
submission ports")

total: 1 errors, 1 warnings, 0 checks, 9 lines checked

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest

[Patchwork]

== Series Details ==

Series: drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest
URL   : https://patchwork.freedesktop.org/series/40851/
State : failure

== Summary ==

 Possible new issues:

Test drm_read:
Subgroup empty-nonblock:
pass   -> FAIL   (shard-snb)
Test kms_chv_cursor_fail:
Subgroup pipe-a-128x128-right-edge:
pass   -> FAIL   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-sliding:
pass   -> FAIL   (shard-snb)
Subgroup cursor-64x64-random:
pass   -> FAIL   (shard-snb)
Test kms_flip:
Subgroup flip-vs-dpms-off-vs-modeset-interruptible:
pass   -> DMESG-WARN (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-cur-indfb-onoff:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-2p-primscrn-spr-indfb-draw-render:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-badstride:
skip   -> FAIL   (shard-snb)
Test kms_plane:
Subgroup plane-panning-bottom-right-pipe-b-planes:
pass   -> FAIL   (shard-snb)
Test kms_universal_plane:
Subgroup disable-primary-vs-flip-pipe-a:
pass   -> FAIL   (shard-snb)

 Known issues:

Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-shrfb-pgflip-blt:
skip   -> FAIL   (shard-snb) fdo#103167 +2
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
pass   -> FAIL   (shard-snb) fdo#103375
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 
time:12858s
shard-hswtotal:3495 pass:1782 dwarn:2   dfail:0   fail:1   skip:1709 
time:11525s
shard-snbtotal:3495 pass:1366 dwarn:1   dfail:0   fail:30  skip:2098 
time:6870s
Blacklisted hosts:
shard-kbltotal:3495 pass:1958 dwarn:1   dfail:1   fail:7   skip:1528 
time:9214s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8527/shards.html
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Re: [Intel-gfx] [igt-dev] [RFC i-g-t] intel-gpu-top: Rewrite the tool to be safe to use

[Tvrtko Ursulin]

On 28/03/2018 21:11, Rinat Ibragimov wrote:



Среда, 28 марта 2018, 21:30 +03:00 от Tvrtko Ursulin :




+static struct engines *discover_engines(void)
  {
-uint32_t devid = pci_dev->device_id;
-uint16_t gcfgc;
+const char *sysfs_root = "/sys/devices/i915/events";


Just a question.
I think, I have Linux 4.15.11 (from Debian testing) now. And there are no such 
files.
Are there any estimates about when this feature is expected to be available?


4.17 I think. I could make it work with 4.16 as well, if there would be 
demand, just need to ignore counters enumerated in sysfs but not 
actually present in hardware.



-static void ring_init(struct ring *ring)
+static uint64_t pmu_read_multi(int fd, unsigned int num, uint64_t *val)
  {
-ring->size = (((ring_read(ring, RING_LEN) & RING_NR_PAGES) >> 12) + 1) * 4096;
+uint64_t buf[2 + num];
+unsigned int i;
+
+assert(read(fd, buf, sizeof(buf)) == sizeof(buf));


Will have undesired effects with NDEBUG.


-int full;
+uint64_t data[2];
  
-if (!ring->size)

-return;
+assert(read(fd, data, sizeof(data)) == sizeof(data));


Same here.


Thanks, got a bit disconnected from userspace development patterns over 
the years.





+/* Get terminal size. */
+if (ioctl(0, TIOCGWINSZ, ) != -1) {
+con_w = ws.ws_col;
+con_h = ws.ws_row;
+}


If you move this into the loop itself, the tool will adapt to changes in
terminal width and height dynamically.


Makes sense, done in v2.

Regards,

Tvrtko
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[Intel-gfx] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.

Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.

For access to more GPU functional unit level data, an OA metric based tool
like gpu-top should be used instead.

v2:
 * Sort engines by class and instance.
 * Do not wait for one sampling period to display something on screen.
 * Move code out of the asserts. (Rinat Ibragimov)
 * Continuously adapt to terminal size. (Rinat Ibgragimov)

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Petri Latvala 
Cc: Eero Tamminen 
Cc: Rinat Ibragimov 
Reviewed-by: Lionel Landwerlin  # v1
Reviewed-by: Chris Wilson  # v0.5
---
 tools/Makefile.am |2 +
 tools/intel_gpu_top.c | 1009 +
 tools/meson.build |6 +-
 3 files changed, 441 insertions(+), 576 deletions(-)

diff --git a/tools/Makefile.am b/tools/Makefile.am
index 09b6dbcc3ece..a0b016ddd7ff 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -28,6 +28,8 @@ intel_aubdump_la_LDFLAGS = -module -avoid-version 
-no-undefined
 intel_aubdump_la_SOURCES = aubdump.c
 intel_aubdump_la_LIBADD = $(top_builddir)/lib/libintel_tools.la -ldl
 
+intel_gpu_top_LDADD = $(top_builddir)/lib/libigt_perf.la
+
 bin_SCRIPTS = intel_aubdump
 CLEANFILES = $(bin_SCRIPTS)
 
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 098e6ce3ff86..94091d97c4a3 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1,6 +1,5 @@
 /*
- * Copyright © 2007 Intel Corporation
- * Copyright © 2011 Intel Corporation
+ * Copyright © 2018 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -18,701 +17,561 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *Eugeni Dodonov 
- *
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
  */
 
-#include "config.h"
-
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#ifdef HAVE_TERMIOS_H
-#include 
-#endif
-#include "intel_io.h"
-#include "instdone.h"
-#include "intel_reg.h"
-#include "intel_chipset.h"
-#include "drmtest.h"
-
-#define  FORCEWAKE 0xA18C
-#define  FORCEWAKE_ACK 0x130090
-
-#define SAMPLES_PER_SEC 1
-#define SAMPLES_TO_PERCENT_RATIO(SAMPLES_PER_SEC / 100)
-
-#define MAX_NUM_TOP_BITS100
-
-#define HAS_STATS_REGS(devid)  IS_965(devid)
-
-struct top_bit {
-   struct instdone_bit *bit;
-   int count;
-} top_bits[MAX_NUM_TOP_BITS];
-struct top_bit *top_bits_sorted[MAX_NUM_TOP_BITS];
-
-static uint32_t instdone, instdone1;
-
-static const char *bars[] = {
-   " ",
-   "▏",
-   "▎",
-   "▍",
-   "▌",
-   "▋",
-   "▊",
-   "▉",
-   "█"
-};
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_perf.h"
 
-enum stats_counts {
-   IA_VERTICES,
-   IA_PRIMITIVES,
-   VS_INVOCATION,
-   GS_INVOCATION,
-   GS_PRIMITIVES,
-   CL_INVOCATION,
-   CL_PRIMITIVES,
-   PS_INVOCATION,
-   PS_DEPTH,
-   STATS_COUNT
+struct pmu_pair {
+   uint64_t cur;
+   uint64_t prev;
 };
 
-const uint32_t stats_regs[STATS_COUNT] = {
-   IA_VERTICES_COUNT_QW,
-   IA_PRIMITIVES_COUNT_QW,
-   VS_INVOCATION_COUNT_QW,
-   GS_INVOCATION_COUNT_QW,
-   GS_PRIMITIVES_COUNT_QW,
-   CL_INVOCATION_COUNT_QW,
-   CL_PRIMITIVES_COUNT_QW,
-   PS_INVOCATION_COUNT_QW,
-   PS_DEPTH_COUNT_QW,
+struct pmu_counter {
+   uint64_t config;
+   unsigned int idx;
+   struct pmu_pair val;
 };
 
-const char *stats_reg_names[STATS_COUNT] = {
-   "vert fetch",
-   "prim fetch",
-   "VS invocations",
-   "GS invocations",
-   "GS prims",
-   "CL invocations",
-   "CL prims",
-   "PS invocations",
-   "PS depth pass",
+struct engine {
+   const char *name;
+   struct pmu_counter busy;
+   struct pmu_counter wait;
+   struct pmu_counter sema;
 };
 
-uint64_t 

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: enable guc interrupts unconditionally in uc_resume

[Chris Wilson]

Quoting Michel Thierry (2018-03-28 21:58:50)
> Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
> interrupts enabled when using GuC").
> 
> Not really needed since i915_gem_init_hw is called before uc_resume, but
> it brings symmetry to uc_suspend.
> 
> Signed-off-by: Michel Thierry 
> Cc: Michał Winiarski 
> Reviewed-by: Michał Winiarski 

And applied, thanks for the patch and review.
(Will push later, having issues reaching fdo right now.)
-Chris
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Thursday, March 29, 2018 3:59 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
> 4 for NV12
> 
> Op 29-03-18 om 11:19 schreef Srinivas, Vidya:
> >
> >> -Original Message-
> >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> >> Sent: Thursday, March 29, 2018 2:19 PM
> >> To: Srinivas, Vidya ; intel-
> >> g...@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size
> >> mult of
> >> 4 for NV12
> >>
> >> Op 29-03-18 om 10:06 schreef Vidya Srinivas:
> >>> As per display WA 1106, to avoid corruption issues
> >>> NV12 plane height needs to be multiplier of 4 Hence we modify the fb
> >>> src and destination height and width to be multiples of 4. Without
> >>> this, pipe fifo underruns were seen on APL and KBL.
> >>>
> >>> Credits-to: Maarten Lankhorst 
> >>> Signed-off-by: Vidya Srinivas 
> >>> ---
> >>>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> >>>  drivers/gpu/drm/i915/intel_sprite.c | 8 
> >>>  2 files changed, 10 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >>> b/drivers/gpu/drm/i915/intel_drv.h
> >>> index 9c58da0..a1f718d 100644
> >>> --- a/drivers/gpu/drm/i915/intel_drv.h
> >>> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >>> @@ -159,6 +159,8 @@
> >>>  #define INTEL_I2C_BUS_DVO 1
> >>>  #define INTEL_I2C_BUS_SDVO 2
> >>>
> >>> +#define MULT4(x) ((x + 3) & ~0x03)
> >>> +
> >>>  /* these are outputs from the chip - integrated only
> >>> external chips are via DVO or SDVO output */  enum
> >>> intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >>> b/drivers/gpu/drm/i915/intel_sprite.c
> >>> index 538d938..9f466c6 100644
> >>> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >>> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> >>>   crtc_w--;
> >>>   crtc_h--;
> >>>
> >>> + if (fb->format->format == DRM_FORMAT_NV12) {
> >>> + src_w = MULT4(src_w);
> >>> + src_h = MULT4(src_h);
> >>> + crtc_w = MULT4(crtc_w);
> >>> + crtc_h = MULT4(crtc_h);
> >>> + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> >> crtc_h);
> >>> + }
> >>> +
> >>>   spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >>>
> >>>   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> Nearly there!
> >>
> >> Do we have limitations for width too? But I think we shouldn't ever
> >> adjust src for any format.
> >> This means that we should probably get rid of the
> >> drm_rect_adjust_size call in intel_check_sprite_plane.
> >>
> >> If any limitations of NV12 are hit, we should reject with -EINVAL
> >> instead so userspace can decide what to do.
> >> The best place to put those checks is probably in skl_update_scaler,
> >> where they will be checked by the primary plane too.
> >>
> >> This will mean the tests fail, but that can be fixed by selecting 16
> >> as width/height for NV12 in IGT. If you change it to 16 you can put my r-b
> on it.
> >>
> >> Also I think we should put the same limitations for width and height
> >> being a multiple in intel_framebuffer_init.
> >>
> >> And on a final note for patch ordering, put the workaround and gen10
> >> patch before enabling nv12 support.
> > Thank you. Okay, I will make these changes and check once. The
> > limitation in Framebuffer init is already present where it expects
> > width and height >= 16 As per bspec no minimum for width has been
> > mentioned. And regarding the Add check for primary plane (same like
> > sprite), can we add that as a separate patch Because if we add it with
> > NV12 series, it would be like adding the changes and Returning before
> executing them.
> I don't think we'll lose much if we fail to create a fb that's not a multiple 
> of
> 4 in height and width. Since the NV12 format is defined in terms of 4x4 pixel
> blocks, I don't think it would be a loss to fail to create it, if we can't 
> even
> display it.
> > Right now range check only exists for NV12 in skl_update_scaler. My worry
> was:
> > If the width and height are not multiplier of 4 do we return from
> skl_update_scaler?
> We should always refuse to show when the src height is not a multiple of 4,
> and return -EINVAL.
> > What if some other user level program wants to set src width and height
> 23x23 etc?
> Then userspace will see that it will fail with -EINVAL, if it's done by a
> compositor with a TEST_ONLY commit, it will see the src cannot be set and
> either choose a different size or fallback to software rendering before
> displaying the output.
> 
> This is still better than silently succeeding, but showing something 
> different.

Sure, thank you. I will make the 

Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Maarten Lankhorst]

Op 29-03-18 om 11:19 schreef Srinivas, Vidya:
>
>> -Original Message-
>> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>> Sent: Thursday, March 29, 2018 2:19 PM
>> To: Srinivas, Vidya ; intel-
>> g...@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
>> 4 for NV12
>>
>> Op 29-03-18 om 10:06 schreef Vidya Srinivas:
>>> As per display WA 1106, to avoid corruption issues
>>> NV12 plane height needs to be multiplier of 4 Hence we modify the fb
>>> src and destination height and width to be multiples of 4. Without
>>> this, pipe fifo underruns were seen on APL and KBL.
>>>
>>> Credits-to: Maarten Lankhorst 
>>> Signed-off-by: Vidya Srinivas 
>>> ---
>>>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
>>>  drivers/gpu/drm/i915/intel_sprite.c | 8 
>>>  2 files changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>> b/drivers/gpu/drm/i915/intel_drv.h
>>> index 9c58da0..a1f718d 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -159,6 +159,8 @@
>>>  #define INTEL_I2C_BUS_DVO 1
>>>  #define INTEL_I2C_BUS_SDVO 2
>>>
>>> +#define MULT4(x) ((x + 3) & ~0x03)
>>> +
>>>  /* these are outputs from the chip - integrated only
>>> external chips are via DVO or SDVO output */  enum
>>> intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>>> b/drivers/gpu/drm/i915/intel_sprite.c
>>> index 538d938..9f466c6 100644
>>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>>> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
>>> crtc_w--;
>>> crtc_h--;
>>>
>>> +   if (fb->format->format == DRM_FORMAT_NV12) {
>>> +   src_w = MULT4(src_w);
>>> +   src_h = MULT4(src_h);
>>> +   crtc_w = MULT4(crtc_w);
>>> +   crtc_h = MULT4(crtc_h);
>>> +   DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
>> crtc_h);
>>> +   }
>>> +
>>> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>>>
>>> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> Nearly there!
>>
>> Do we have limitations for width too? But I think we shouldn't ever adjust
>> src for any format.
>> This means that we should probably get rid of the drm_rect_adjust_size call
>> in intel_check_sprite_plane.
>>
>> If any limitations of NV12 are hit, we should reject with -EINVAL instead so
>> userspace can decide what to do.
>> The best place to put those checks is probably in skl_update_scaler, where
>> they will be checked by the primary plane too.
>>
>> This will mean the tests fail, but that can be fixed by selecting 16 as
>> width/height for NV12 in IGT. If you change it to 16 you can put my r-b on 
>> it.
>>
>> Also I think we should put the same limitations for width and height being a
>> multiple in intel_framebuffer_init.
>>
>> And on a final note for patch ordering, put the workaround and gen10 patch
>> before enabling nv12 support.
> Thank you. Okay, I will make these changes and check once. The limitation in
> Framebuffer init is already present where it expects width and height >= 16
> As per bspec no minimum for width has been mentioned. And regarding the
> Add check for primary plane (same like sprite), can we add that as a separate 
> patch
> Because if we add it with NV12 series, it would be like adding the changes 
> and 
> Returning before executing them.
I don't think we'll lose much if we fail to create a fb that's not a multiple 
of 4 in
height and width. Since the NV12 format is defined in terms of 4x4 pixel blocks,
I don't think it would be a loss to fail to create it, if we can't even display 
it.
> Right now range check only exists for NV12 in skl_update_scaler. My worry was:
> If the width and height are not multiplier of 4 do we return from 
> skl_update_scaler?
We should always refuse to show when the src height is not a multiple of 4, and 
return -EINVAL.
> What if some other user level program wants to set src width and height 23x23 
> etc?
Then userspace will see that it will fail with -EINVAL, if it's done by a 
compositor with a TEST_ONLY commit,
it will see the src cannot be set and either choose a different size or 
fallback to software rendering before
displaying the output.

This is still better than silently succeeding, but showing something different.
> I will check if we remove the src aligning from skl_update_plane and just 
> keep the
> Destination as multiplier of 4 in skl_update_plane.
I think it's more likely the src that needs to be a multiple of 4. I don't 
think there's
much of a failure in destination.
> Regarding the reordering, I will make the change and float the series. Thank 
> you
> So much for all the support and pointers.
>
> If no fifo underruns are seen with just keeping the dest width and height 
> mult of 4,
> We anyways don’t do the 

[Intel-gfx] [PATCH i-g-t v2] blacklist: Don't run DRRS test on Intel CI system

[Marta Lofstedt]

Skipping takes time, specifically for the big amount of drrs
related kms_frontbuffer_tracking tests. Since we currently
don't have any system set up with DRRS panels, blacklisting
all those test will save time, and we can avoid the need to
increase the Jenkins timeout in order to solve the Bugzilla
below.

V2: Changed typo and added comment.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105617
Signed-off-by: Marta Lofstedt 
---
 tests/intel-ci/blacklist.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 7ca313ac..ef3b45e9 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -58,6 +58,10 @@ igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
 igt@gem_wait@.*hang.*
 igt@gem_write_read_ring_switch(@.*)?
 ###
+# There are no DRRS capable displays in CI lab
+###
+igt@kms_frontbuffer_tracking@.*drrs.*
+###
 # Broadcom
 ###
 igt@vc4_.*
-- 
2.11.0

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[Intel-gfx] [PATCH] drm/i915/execlists: Track begin/end of execlists submission sequences

[Chris Wilson]

We would like to start doing some bookkeeping at the beginning, between
contexts and at the end of execlists submission. We already mark the
beginning and end using EXECLISTS_ACTIVE_USER, to provide an indication
when the HW is idle. This give us a pair of sequence points we can then
expand on for further bookkeeping.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Francisco Jerez 
---
 drivers/gpu/drm/i915/intel_lrc.c| 42 -
 drivers/gpu/drm/i915/intel_ringbuffer.h | 11 -
 2 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 654634254b64..61fb1387feb3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -374,6 +374,19 @@ execlists_context_status_change(struct i915_request *rq, 
unsigned long status)
   status, rq);
 }
 
+static inline void
+execlists_user_begin(struct intel_engine_execlists *execlists,
+const struct execlist_port *port)
+{
+   execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
+}
+
+static inline void
+execlists_user_end(struct intel_engine_execlists *execlists)
+{
+   execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
+}
+
 static inline void
 execlists_context_schedule_in(struct i915_request *rq)
 {
@@ -710,7 +723,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
spin_unlock_irq(>timeline->lock);
 
if (submit) {
-   execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
+   execlists_user_begin(execlists, execlists->port);
execlists_submit_ports(engine);
}
 
@@ -741,7 +754,7 @@ execlists_cancel_port_requests(struct 
intel_engine_execlists * const execlists)
port++;
}
 
-   execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
+   execlists_user_end(execlists);
 }
 
 static void clear_gtiir(struct intel_engine_cs *engine)
@@ -872,7 +885,7 @@ static void execlists_submission_tasklet(unsigned long data)
 {
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlists * const execlists = >execlists;
-   struct execlist_port * const port = execlists->port;
+   struct execlist_port *port = execlists->port;
struct drm_i915_private *dev_priv = engine->i915;
bool fw = false;
 
@@ -1010,9 +1023,19 @@ static void execlists_submission_tasklet(unsigned long 
data)
 
GEM_BUG_ON(count == 0);
if (--count == 0) {
+   /*
+* On the final event corresponding to the
+* submission of this context, we expect either
+* an element-switch event or a completion
+* event (and on completion, the active-idle
+* marker). No more preemptions, lite-restore
+* or otherwise
+*/
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
GEM_BUG_ON(port_isset([1]) &&
   !(status & 
GEN8_CTX_STATUS_ELEMENT_SWITCH));
+   GEM_BUG_ON(!port_isset([1]) &&
+  !(status & 
GEN8_CTX_STATUS_ACTIVE_IDLE));
GEM_BUG_ON(!i915_request_completed(rq));
execlists_context_schedule_out(rq);
trace_i915_request_out(rq);
@@ -1021,17 +1044,14 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s completed ctx=%d\n",
  engine->name, port->context_id);
 
-   execlists_port_complete(execlists, port);
+   port = execlists_port_complete(execlists, port);
+   if (port_isset(port))
+   execlists_user_begin(execlists, port);
+   else
+   execlists_user_end(execlists);
} else {
port_set(port, port_pack(rq, count));
}
-
-   /* After the final element, the hw should be idle */
-   GEM_BUG_ON(port_count(port) == 0 &&
-  !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
-   if (port_count(port) == 0)
-   execlists_clear_active(execlists,
-  EXECLISTS_ACTIVE_USER);

Re: [Intel-gfx] Subject: [PATCH 1/1] drm/i915: move audio component intialization before audio

[Jani Nikula]

On Thu, 29 Mar 2018, "Shi, Yang A"  wrote:
> snd_hdac driver would use the component interface from i915 driver.
> if i915 driver do the audio component intialization too late, snd_hdac
> driver will meet ipanic.

Please include the oops.

What is it about this patch that fixes the issue? Based on the
description I presume it has nothing to do with i915 internal ordering,
and everything to do with i915 and hdac probe racing. In that case, this
is not a fix, just something to make the race a bit less likely. Is that
the case?

We try hard to make sure our driver has properly been set up internally
before we go ahead and reveal ourselves to the userspace and the rest of
the kernel. This is the i915_driver_register() part. We aren't ready to
register the component ops before that. We aren't ready to handle calls
from audio drivers before that.

What's the problem you have exactly?

BR,
Jani.

>
> Signed-off-by: Bo He 
> Signed-off-by: Yang Shi 
> ---
>  drivers/gpu/drm/i915/i915_drv.c  | 2 --
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f5209d..9d25d7e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1243,8 +1243,6 @@ static void i915_driver_register(struct 
> drm_i915_private *dev_priv)
>   if (IS_GEN5(dev_priv))
>   intel_gpu_ips_init(dev_priv);
>  
> - intel_audio_init(dev_priv);
> -
>   /*
>* Some ports require correctly set-up hpd registers for detection to
>* work properly (leading to ghost connected connector status), e.g. VGA
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index f288bcc..a471c88 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14468,6 +14468,8 @@ int intel_modeset_init(struct drm_device *dev)
>  
>   dev->mode_config.funcs = _mode_funcs;
>  
> + intel_audio_init(dev_priv);
> +
>   init_llist_head(_priv->atomic_helper.free_list);
>   INIT_WORK(_priv->atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid sleeping inside per-engine reset

[Patchwork]

== Series Details ==

Series: drm/i915: Avoid sleeping inside per-engine reset
URL   : https://patchwork.freedesktop.org/series/40838/
State : success

== Summary ==

Series 40838v1 drm/i915: Avoid sleeping inside per-engine reset
https://patchwork.freedesktop.org/api/1.0/series/40838/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-cfl-s3) fdo#100368
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481 +1

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:512s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:516s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:516s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:495s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:571s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:516s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s

4668e88d66074a81aae645e0db0391e7ea9afe8a drm-tip: 2018y-03m-28d-20h-45m-29s UTC 
integration manifest
b68e4fdb61d2 drm/i915: Avoid sleeping inside per-engine reset

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8530/issues.html
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Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-29 10:34:40)
> From: Tvrtko Ursulin 
> 
> Contexts executing when reset triggers are potentialy corrupt so trying to
> use them from a subsequent test (like the default context) can hang the
> GPU or even the driver.
> 
> Workaround that by always creating a dedicated context which will be
> running when GPU reset happens.
> 
> v2:
>  * Export and use gem_reopen_device so the test works on old gens as well.
>(Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin 

Matches what I wrote^W imagined (as if you believe I would have bothered
with the export rather than cut'n'paste ;)

Have a conditional
Reviewed-by: Chris Wilson 
on the condition that you throw in a test that reused a few contexts a few
times. I think something like

for (nctx in prime(1, next_prime(MAX_ELSP))) {
while (loop) {
for (ctx = nctx) {
for_each_engine() {
add-spin(ctx, engine);
}
end-spin.
}
// something, something inject wedge
}

?
-Chris
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Include the HW breadcrumb whenever we trace the global_seqno

[Tvrtko Ursulin]

On 29/03/2018 09:55, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-03-29 09:42:52)


On 27/03/2018 22:01, Chris Wilson wrote:

When we include a request's global_seqno in a GEM_TRACE it often helps
to know how that relates to the current breadcrumb as seen by the
hardware.

Signed-off-by: Chris Wilson 
---
   drivers/gpu/drm/i915/i915_request.c | 28 +---
   drivers/gpu/drm/i915/intel_lrc.c|  6 --
   2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 2314a26cd7f8..585242831974 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -214,8 +214,11 @@ static int reset_all_global_seqno(struct drm_i915_private 
*i915, u32 seqno)
   struct i915_gem_timeline *timeline;
   struct intel_timeline *tl = engine->timeline;
   
- GEM_TRACE("%s seqno %d -> %d\n",

-   engine->name, tl->seqno, seqno);
+ GEM_TRACE("%s seqno %d (current %d) -> %d\n",
+   engine->name,
+   tl->seqno,
+   intel_engine_get_seqno(engine),
+   seqno);
   
   if (!i915_seqno_passed(seqno, tl->seqno)) {

   /* Flush any waiters before we reuse the seqno */
@@ -386,10 +389,11 @@ static void i915_request_retire(struct i915_request 
*request)
   struct intel_engine_cs *engine = request->engine;
   struct i915_gem_active *active, *next;
   
- GEM_TRACE("%s(%d) fence %llx:%d, global_seqno %d\n",

-   engine->name, intel_engine_get_seqno(engine),
+ GEM_TRACE("%s fence %llx:%d, global_seqno %d, current %d\n",
+   engine->name,
 request->fence.context, request->fence.seqno,
-   request->global_seqno);
+   request->global_seqno,
+   intel_engine_get_seqno(engine));
   
   lockdep_assert_held(>i915->drm.struct_mutex);

   GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
@@ -508,10 +512,11 @@ void __i915_request_submit(struct i915_request *request)
   struct intel_engine_cs *engine = request->engine;
   u32 seqno;
   
- GEM_TRACE("%s fence %llx:%d -> global_seqno %d\n",

-   request->engine->name,
+ GEM_TRACE("%s fence %llx:%d -> global_seqno %d, current %d\n",
+   engine->name,
 request->fence.context, request->fence.seqno,
-   engine->timeline->seqno + 1);
+   engine->timeline->seqno + 1,
+   intel_engine_get_seqno(engine));
   
   GEM_BUG_ON(!irqs_disabled());

   lockdep_assert_held(>timeline->lock);
@@ -557,10 +562,11 @@ void __i915_request_unsubmit(struct i915_request *request)
   {
   struct intel_engine_cs *engine = request->engine;
   
- GEM_TRACE("%s fence %llx:%d <- global_seqno %d\n",

-   request->engine->name,
+ GEM_TRACE("%s fence %llx:%d <- global_seqno %d, current %d\n",
+   engine->name,
 request->fence.context, request->fence.seqno,
-   request->global_seqno);
+   request->global_seqno,
+   intel_engine_get_seqno(engine));
   
   GEM_BUG_ON(!irqs_disabled());

   lockdep_assert_held(>timeline->lock);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ed2c833a8b20..b5235f52a81b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,10 +454,11 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
   desc = execlists_update_context(rq);
   GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
   
- GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%x, prio=%d\n",

+ GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%d (current %d), 
prio=%d\n",
 engine->name, n,
 port[n].context_id, count,
 rq->global_seqno,
+   intel_engine_get_seqno(engine),
 rq_prio(rq));
   } else {
   GEM_BUG_ON(!n);
@@ -999,10 +1000,11 @@ static void execlists_submission_tasklet(unsigned long 
data)
   EXECLISTS_ACTIVE_USER));
   
   rq = port_unpack(port, );

- GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x, prio=%d\n",
+ GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%d (current %d), 
prio=%d\n",
 engine->name,
 port->context_id, count,
 rq ? rq->global_seqno : 0,
+   intel_engine_get_seqno(engine),
 rq ? rq_prio(rq) : 0);
 

Re: [Intel-gfx] [PATCH] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest

[Joonas Lahtinen]

+ Zhi and Zhenyu

Quoting Xiong Zhang (2018-03-29 13:58:41)
> Four drm_mm_node are used to reserve guest ggtt space, but some of them
> may aren't initialized and used in intel_vgt_balloon(), so these unused
> drm_mm_node couldn't be removed through drm_mm_remove_node().

I'm not sure how this slipped by in previous review, but is there an
explanation why we have;

static struct _balloon_info_ bl_info;

... and are not even initializing it?

This should definitely find it's way into dev_priv and be properly
initialized.

Regards, Joonas

> 
> Fixes: ff8f797557c7("drm/i915: return the correct usable aperture size under 
> gvt environment")
> Signed-off-by: Xiong Zhang 
> ---
>  drivers/gpu/drm/i915/i915_vgpu.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c 
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index 5fe9f3f..7545686 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -100,6 +100,9 @@ static struct _balloon_info_ bl_info;
>  static void vgt_deballoon_space(struct i915_ggtt *ggtt,
> struct drm_mm_node *node)
>  {
> +   if (!node->allocated)
> +   return;
> +
> DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu 
> KiB.\n",
>  node->start,
>  node->start + node->size,
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, March 29, 2018 3:04 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> 
> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
> 4 for NV12
> 
> On Thu, Mar 29, 2018 at 09:29:06AM +, Srinivas, Vidya wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Thursday, March 29, 2018 2:56 PM
> > > To: Srinivas, Vidya 
> > > Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> > > 
> > > Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size
> > > mult of
> > > 4 for NV12
> > >
> > > On Thu, Mar 29, 2018 at 01:36:02PM +0530, Vidya Srinivas wrote:
> > > > As per display WA 1106, to avoid corruption issues
> > > > NV12 plane height needs to be multiplier of 4 Hence we modify the
> > > > fb src and destination height and width to be multiples of 4.
> > > > Without this, pipe fifo underruns were seen on APL and KBL.
> > > >
> > > > Credits-to: Maarten Lankhorst 
> > > > Signed-off-by: Vidya Srinivas 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> > > >  drivers/gpu/drm/i915/intel_sprite.c | 8 
> > > >  2 files changed, 10 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 9c58da0..a1f718d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -159,6 +159,8 @@
> > > >  #define INTEL_I2C_BUS_DVO 1
> > > >  #define INTEL_I2C_BUS_SDVO 2
> > > >
> > > > +#define MULT4(x) ((x + 3) & ~0x03)
> > > > +
> > > >  /* these are outputs from the chip - integrated only
> > > > external chips are via DVO or SDVO output */  enum
> > > > intel_output_type { diff --git
> > > > a/drivers/gpu/drm/i915/intel_sprite.c
> > > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > > index 538d938..9f466c6 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> > > > crtc_w--;
> > > > crtc_h--;
> > > >
> > > > +   if (fb->format->format == DRM_FORMAT_NV12) {
> > > > +   src_w = MULT4(src_w);
> > > > +   src_h = MULT4(src_h);
> > > > +   crtc_w = MULT4(crtc_w);
> > > > +   crtc_h = MULT4(crtc_h);
> > >
> > > No macros like this pls. I want to know what it's doing. Also this is
> wrong.
> > > You can't increase src_w/h without potentially pushing the scale
> > > factor past the hardware limits.
> >
> >
> > Thank you. I am trying with not modifying the src w and h. Instead we
> > just Avoid the truncation (drm_rect_adjust_size and remaining things)
> > for NV12 in Intel_check_sprite_plane. I will keep only crtc_w and
> > crtc_h as a mult of 4 and See if no fifo underruns are seen.
> 
> The limitations are on the scaler source side, so I doubt that will do
> anything. So I don't even understand why we're playing around with the
> destination coordinates here.
> 
> Anywyay, I thought we already agreed to just return an error when things
> are misaligned?

The limitation for height is on scaler side. But for Gen9, GLK and GLV
There is a workaround 1106 which says:

Display corruption/color shift observed when using NV12 with 270 rotation or 90 
rotation + horizontal flip.
WA: NV12 with 270 rotation or 90 rotation + horizontal flip requires the 
programmed plane height to be a multiple of 4.

Based on all the trials we have done, if we don't keep the dest width and 
height aligned to mult of 4, we see fifo underrun on APL
and KBL.

> 
> >
> > Regards
> > Vidya
> >
> > >
> > > > +   DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> > > crtc_h);
> > >
> > > No user triggrable errors. Also this doesn't even explain what it's
> printing.
> > Sorry about this. This went in by mistake. Will remove it.
> > >
> > > > +   }
> > > > +
> > > > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > > >
> > > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > > --
> > > > 2.7.4
> > > >
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Ville Syrjälä
> > > Intel OTC
> 
> --
> Ville Syrjälä
> Intel OTC
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[Intel-gfx] [PATCH] drm/i915/execlists: Set queue priority from secondary port

[Chris Wilson]

We can refine our current execlists->queue_priority if we inspect
ELSP[1] rather than the head of the unsubmitted queue. Currently, we use
the unsubmitted queue and say that if a subsequent request is more than
important than the current queue, we will rerun the submission tasklet
to evaluate the need for preemption. However, we only want to preempt if
we need to jump ahead of a currently executing request in ELSP. The
second reason for running the submission tasklet is amalgamate requests
into the active context on ELSP[0] to avoid a stall when ELSP[0] drains.
(Though repeatedly amalgamating requests into the active context and
triggering many lite-restore is off question gain, the goal really is to
put a context into ELSP[1] to cover the interrupt.) So if instead of
looking at the head of the queue, we look at the context in ELSP[1] we
can answer both of the questions more accurately -- we don't need to
rerun the submission tasklet unless our new request is important enough
to feed into, at least, ELSP[1].

References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between 
submission ports")
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 654634254b64..e6d3ee4ca0b2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -698,7 +698,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
kmem_cache_free(engine->i915->priorities, p);
}
 done:
-   execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
+   execlists->queue_priority =
+   port != execlists->port ? rq_prio(last) : INT_MIN;
execlists->first = rb;
if (submit)
port_assign(port, last);
-- 
2.16.3

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[Intel-gfx] [PATCH i-g-t v2] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Contexts executing when reset triggers are potentialy corrupt so trying to
use them from a subsequent test (like the default context) can hang the
GPU or even the driver.

Workaround that by always creating a dedicated context which will be
running when GPU reset happens.

v2:
 * Export and use gem_reopen_device so the test works on old gens as well.
   (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 lib/i915/gem_submission.c | 11 +--
 lib/i915/gem_submission.h |  2 ++
 tests/gem_eio.c   | 77 ---
 3 files changed, 64 insertions(+), 26 deletions(-)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index 7d3cbdbf8e77..2fd460d5ed2b 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -165,7 +165,14 @@ bool gem_has_guc_submission(int fd)
return gem_submission_method(fd) & GEM_SUBMISSION_GUC;
 }
 
-static int reopen_driver(int fd)
+/**
+ * gem_reopen_driver:
+ * @fd: re-open the i915 drm file descriptor
+ *
+ * Re-opens the drm fd which is useful in instances where a clean default
+ * context is needed.
+ */
+int gem_reopen_driver(int fd)
 {
char path[256];
 
@@ -201,7 +208,7 @@ void gem_test_engine(int i915, unsigned int engine)
.buffer_count = 1,
};
 
-   i915 = reopen_driver(i915);
+   i915 = gem_reopen_driver(i915);
igt_assert(!is_wedged(i915));
 
obj.handle = gem_create(i915, 4096);
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index 6b39a0532295..f94eabb201b4 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -35,4 +35,6 @@ bool gem_has_guc_submission(int fd);
 
 void gem_test_engine(int fd, unsigned int engine);
 
+int gem_reopen_driver(int fd);
+
 #endif /* GEM_SUBMISSION_H */
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b824d9d4c9c0..b7c5047f0816 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -255,6 +255,7 @@ static void test_wait(int fd, unsigned int flags, unsigned 
int wait)
 {
igt_spin_t *hang;
 
+   fd = gem_reopen_driver(fd);
igt_require_gem(fd);
 
/*
@@ -276,10 +277,14 @@ static void test_wait(int fd, unsigned int flags, 
unsigned int wait)
igt_require(i915_reset_control(true));
 
trigger_reset(fd);
+   close(fd);
 }
 
 static void test_suspend(int fd, int state)
 {
+   fd = gem_reopen_driver(fd);
+   igt_require_gem(fd);
+
/* Do a suspend first so that we don't skip inside the test */
igt_system_suspend_autoresume(state, SUSPEND_TEST_DEVICES);
 
@@ -291,27 +296,32 @@ static void test_suspend(int fd, int state)
 
igt_require(i915_reset_control(true));
trigger_reset(fd);
+   close(fd);
 }
 
 static void test_inflight(int fd, unsigned int wait)
 {
-   const uint32_t bbe = MI_BATCH_BUFFER_END;
-   struct drm_i915_gem_exec_object2 obj[2];
+   int parent_fd = fd;
unsigned int engine;
 
igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
 
-   memset(obj, 0, sizeof(obj));
-   obj[0].flags = EXEC_OBJECT_WRITE;
-   obj[1].handle = gem_create(fd, 4096);
-   gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
-
-   for_each_engine(fd, engine) {
+   for_each_engine(parent_fd, engine) {
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+   struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_execbuffer2 execbuf;
igt_spin_t *hang;
int fence[64]; /* conservative estimate of ring size */
 
+   fd = gem_reopen_driver(parent_fd);
+   igt_require_gem(fd);
+
+   memset(obj, 0, sizeof(obj));
+   obj[0].flags = EXEC_OBJECT_WRITE;
+   obj[1].handle = gem_create(fd, 4096);
+   gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
+
gem_quiescent_gpu(fd);
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
@@ -340,6 +350,9 @@ static void test_inflight(int fd, unsigned int wait)
igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
+
+   gem_close(fd, obj[1].handle);
+   close(fd);
}
 }
 
@@ -351,6 +364,7 @@ static void test_inflight_suspend(int fd)
int fence[64]; /* conservative estimate of ring size */
igt_spin_t *hang;
 
+   fd = gem_reopen_driver(fd);
igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
@@ -387,6 +401,7 @@ static void test_inflight_suspend(int fd)
igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
+   close(fd);
 }
 
 static uint32_t 

Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Ville Syrjälä]

On Thu, Mar 29, 2018 at 09:29:06AM +, Srinivas, Vidya wrote:
> 
> 
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Thursday, March 29, 2018 2:56 PM
> > To: Srinivas, Vidya 
> > Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> > 
> > Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
> > 4 for NV12
> > 
> > On Thu, Mar 29, 2018 at 01:36:02PM +0530, Vidya Srinivas wrote:
> > > As per display WA 1106, to avoid corruption issues
> > > NV12 plane height needs to be multiplier of 4 Hence we modify the fb
> > > src and destination height and width to be multiples of 4. Without
> > > this, pipe fifo underruns were seen on APL and KBL.
> > >
> > > Credits-to: Maarten Lankhorst 
> > > Signed-off-by: Vidya Srinivas 
> > > ---
> > >  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> > >  drivers/gpu/drm/i915/intel_sprite.c | 8 
> > >  2 files changed, 10 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 9c58da0..a1f718d 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -159,6 +159,8 @@
> > >  #define INTEL_I2C_BUS_DVO 1
> > >  #define INTEL_I2C_BUS_SDVO 2
> > >
> > > +#define MULT4(x) ((x + 3) & ~0x03)
> > > +
> > >  /* these are outputs from the chip - integrated only
> > > external chips are via DVO or SDVO output */  enum
> > > intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 538d938..9f466c6 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> > >   crtc_w--;
> > >   crtc_h--;
> > >
> > > + if (fb->format->format == DRM_FORMAT_NV12) {
> > > + src_w = MULT4(src_w);
> > > + src_h = MULT4(src_h);
> > > + crtc_w = MULT4(crtc_w);
> > > + crtc_h = MULT4(crtc_h);
> > 
> > No macros like this pls. I want to know what it's doing. Also this is wrong.
> > You can't increase src_w/h without potentially pushing the scale factor past
> > the hardware limits.
> 
> 
> Thank you. I am trying with not modifying the src w and h. Instead we just
> Avoid the truncation (drm_rect_adjust_size and remaining things) for NV12 in
> Intel_check_sprite_plane. I will keep only crtc_w and crtc_h as a mult of 4 
> and
> See if no fifo underruns are seen.

The limitations are on the scaler source side, so I doubt that will do
anything. So I don't even understand why we're playing around with the
destination coordinates here.

Anywyay, I thought we already agreed to just return an error when things
are misaligned?

> 
> Regards
> Vidya
> 
> > 
> > > + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> > crtc_h);
> > 
> > No user triggrable errors. Also this doesn't even explain what it's 
> > printing.
> Sorry about this. This went in by mistake. Will remove it.
> > 
> > > + }
> > > +
> > >   spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > >
> > >   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > --
> > > 2.7.4
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > --
> > Ville Syrjälä
> > Intel OTC

-- 
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, March 29, 2018 2:56 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> 
> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
> 4 for NV12
> 
> On Thu, Mar 29, 2018 at 01:36:02PM +0530, Vidya Srinivas wrote:
> > As per display WA 1106, to avoid corruption issues
> > NV12 plane height needs to be multiplier of 4 Hence we modify the fb
> > src and destination height and width to be multiples of 4. Without
> > this, pipe fifo underruns were seen on APL and KBL.
> >
> > Credits-to: Maarten Lankhorst 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> >  drivers/gpu/drm/i915/intel_sprite.c | 8 
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 9c58da0..a1f718d 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -159,6 +159,8 @@
> >  #define INTEL_I2C_BUS_DVO 1
> >  #define INTEL_I2C_BUS_SDVO 2
> >
> > +#define MULT4(x) ((x + 3) & ~0x03)
> > +
> >  /* these are outputs from the chip - integrated only
> > external chips are via DVO or SDVO output */  enum
> > intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 538d938..9f466c6 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> > crtc_w--;
> > crtc_h--;
> >
> > +   if (fb->format->format == DRM_FORMAT_NV12) {
> > +   src_w = MULT4(src_w);
> > +   src_h = MULT4(src_h);
> > +   crtc_w = MULT4(crtc_w);
> > +   crtc_h = MULT4(crtc_h);
> 
> No macros like this pls. I want to know what it's doing. Also this is wrong.
> You can't increase src_w/h without potentially pushing the scale factor past
> the hardware limits.


Thank you. I am trying with not modifying the src w and h. Instead we just
Avoid the truncation (drm_rect_adjust_size and remaining things) for NV12 in
Intel_check_sprite_plane. I will keep only crtc_w and crtc_h as a mult of 4 and
See if no fifo underruns are seen.

Regards
Vidya

> 
> > +   DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> crtc_h);
> 
> No user triggrable errors. Also this doesn't even explain what it's printing.
Sorry about this. This went in by mistake. Will remove it.
> 
> > +   }
> > +
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >
> > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > --
> > 2.7.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Ville Syrjälä]

On Thu, Mar 29, 2018 at 01:36:02PM +0530, Vidya Srinivas wrote:
> As per display WA 1106, to avoid corruption issues
> NV12 plane height needs to be multiplier of 4
> Hence we modify the fb src and destination height
> and width to be multiples of 4. Without this, pipe
> fifo underruns were seen on APL and KBL.
> 
> Credits-to: Maarten Lankhorst 
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
>  drivers/gpu/drm/i915/intel_sprite.c | 8 
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9c58da0..a1f718d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -159,6 +159,8 @@
>  #define INTEL_I2C_BUS_DVO 1
>  #define INTEL_I2C_BUS_SDVO 2
>  
> +#define MULT4(x) ((x + 3) & ~0x03)
> +
>  /* these are outputs from the chip - integrated only
> external chips are via DVO or SDVO output */
>  enum intel_output_type {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 538d938..9f466c6 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
>   crtc_w--;
>   crtc_h--;
>  
> + if (fb->format->format == DRM_FORMAT_NV12) {
> + src_w = MULT4(src_w);
> + src_h = MULT4(src_h);
> + crtc_w = MULT4(crtc_w);
> + crtc_h = MULT4(crtc_h);

No macros like this pls. I want to know what it's doing. Also this is
wrong. You can't increase src_w/h without potentially pushing the scale
factor past the hardware limits.

> + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w, crtc_h);

No user triggrable errors. Also this doesn't even explain what it's
printing.

> + }
> +
>   spin_lock_irqsave(_priv->uncore.lock, irqflags);
>  
>   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> -- 
> 2.7.4
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Fix usage of for_each_engine_class_instance

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-29 10:11:28)
> From: Tvrtko Ursulin 
> 
> Wrong file descriptor was passed to the iterator. This had currently no
> effect, since it wasn't used in the macro, but needs to be fixed.
> 
> At the same time make the macro consistent by checking for engine presence
> like the other iterators do.
> 
> Added __for_each_engine_class_instance which does not check for engine
> presence and so is useful for enumerating all possible engines - like for
> instance for subtest enumeration.
> 
> And another 'wrong fd used' fixlet in the render node subtests.
> 
> Signed-off-by: Tvrtko Ursulin 
> Reported-by: Michel Thierry 
> Cc: Michel Thierry 
> ---
>  lib/igt_gt.h | 12 +++-
>  tests/perf_pmu.c | 30 ++
>  2 files changed, 17 insertions(+), 25 deletions(-)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index a517ed7b29a0..d44b7552f3c4 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -100,11 +100,6 @@ extern const struct intel_execution_engine2 {
> int instance;
>  } intel_execution_engines2[];
>  
> -#define for_each_engine_class_instance(fd__, e__) \
> -   for ((e__) = intel_execution_engines2;\
> -(e__)->name; \
> -(e__)++)
> -
>  unsigned int
>  gem_class_instance_to_eb_flags(int gem_fd,
>enum drm_i915_gem_engine_class class,
> @@ -122,4 +117,11 @@ void gem_require_engine(int gem_fd,
> igt_require(gem_has_engine(gem_fd, class, instance));
>  }
>  
> +#define __for_each_engine_class_instance(fd__, e__) \
> +   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> +
> +#define for_each_engine_class_instance(fd__, e__) \
> +   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> +   for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))

Ok.

Conversions made sense.
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Thursday, March 29, 2018 2:19 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of
> 4 for NV12
> 
> Op 29-03-18 om 10:06 schreef Vidya Srinivas:
> > As per display WA 1106, to avoid corruption issues
> > NV12 plane height needs to be multiplier of 4 Hence we modify the fb
> > src and destination height and width to be multiples of 4. Without
> > this, pipe fifo underruns were seen on APL and KBL.
> >
> > Credits-to: Maarten Lankhorst 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h| 2 ++
> >  drivers/gpu/drm/i915/intel_sprite.c | 8 
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 9c58da0..a1f718d 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -159,6 +159,8 @@
> >  #define INTEL_I2C_BUS_DVO 1
> >  #define INTEL_I2C_BUS_SDVO 2
> >
> > +#define MULT4(x) ((x + 3) & ~0x03)
> > +
> >  /* these are outputs from the chip - integrated only
> > external chips are via DVO or SDVO output */  enum
> > intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 538d938..9f466c6 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
> > crtc_w--;
> > crtc_h--;
> >
> > +   if (fb->format->format == DRM_FORMAT_NV12) {
> > +   src_w = MULT4(src_w);
> > +   src_h = MULT4(src_h);
> > +   crtc_w = MULT4(crtc_w);
> > +   crtc_h = MULT4(crtc_h);
> > +   DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w,
> crtc_h);
> > +   }
> > +
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >
> > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> 
> Nearly there!
> 
> Do we have limitations for width too? But I think we shouldn't ever adjust
> src for any format.
> This means that we should probably get rid of the drm_rect_adjust_size call
> in intel_check_sprite_plane.
> 
> If any limitations of NV12 are hit, we should reject with -EINVAL instead so
> userspace can decide what to do.
> The best place to put those checks is probably in skl_update_scaler, where
> they will be checked by the primary plane too.
> 
> This will mean the tests fail, but that can be fixed by selecting 16 as
> width/height for NV12 in IGT. If you change it to 16 you can put my r-b on it.
> 
> Also I think we should put the same limitations for width and height being a
> multiple in intel_framebuffer_init.
> 
> And on a final note for patch ordering, put the workaround and gen10 patch
> before enabling nv12 support.

Thank you. Okay, I will make these changes and check once. The limitation in
Framebuffer init is already present where it expects width and height >= 16
As per bspec no minimum for width has been mentioned. And regarding the
Add check for primary plane (same like sprite), can we add that as a separate 
patch
Because if we add it with NV12 series, it would be like adding the changes and 
Returning before executing them.

Right now range check only exists for NV12 in skl_update_scaler. My worry was:
If the width and height are not multiplier of 4 do we return from 
skl_update_scaler?
What if some other user level program wants to set src width and height 23x23 
etc?
I will check if we remove the src aligning from skl_update_plane and just keep 
the
Destination as multiplier of 4 in skl_update_plane.
Regarding the reordering, I will make the change and float the series. Thank you
So much for all the support and pointers.

If no fifo underruns are seen with just keeping the dest width and height mult 
of 4,
We anyways don’t do the drm_rect_adjust_size, then we can avoid putting any
Limitation (other than range check) in skl_update_scaler correct?

Regards
Vidya


> 
> ~Maarten

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Re: [Intel-gfx] [PATCH 06/15] drm/i915: Only warn for might_sleep() before a slow wait_for_register

[Mika Kuoppala]

Chris Wilson  writes:

> As intel_wait_for_register_fw() may use, and if successful only use, a
> busy-wait loop, the might_sleep() warning is a little over-zealous.
> Restrict it to a might_sleep_if() a slow timeout is specified (and so
> the caller authorises use of a usleep).
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index f37ecfc69e49..44c4654443ba 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1996,7 +1996,7 @@ int __intel_wait_for_register(struct drm_i915_private 
> *dev_priv,
>   u32 reg_value;
>   int ret;
>  
> - might_sleep();
> + might_sleep_if(slow_timeout_ms);
>  
>   spin_lock_irq(_priv->uncore.lock);
>   intel_uncore_forcewake_get__locked(dev_priv, fw);
> @@ -2008,7 +2008,7 @@ int __intel_wait_for_register(struct drm_i915_private 
> *dev_priv,
>   intel_uncore_forcewake_put__locked(dev_priv, fw);
>   spin_unlock_irq(_priv->uncore.lock);
>  
> - if (ret)
> + if (ret && slow_timeout_ms)
>   ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
>(reg_value & mask) == value,
>slow_timeout_ms * 1000, 10, 1000);
> -- 
> 2.16.3
>
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[Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Fix usage of for_each_engine_class_instance

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Wrong file descriptor was passed to the iterator. This had currently no
effect, since it wasn't used in the macro, but needs to be fixed.

At the same time make the macro consistent by checking for engine presence
like the other iterators do.

Added __for_each_engine_class_instance which does not check for engine
presence and so is useful for enumerating all possible engines - like for
instance for subtest enumeration.

And another 'wrong fd used' fixlet in the render node subtests.

Signed-off-by: Tvrtko Ursulin 
Reported-by: Michel Thierry 
Cc: Michel Thierry 
---
 lib/igt_gt.h | 12 +++-
 tests/perf_pmu.c | 30 ++
 2 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index a517ed7b29a0..d44b7552f3c4 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -100,11 +100,6 @@ extern const struct intel_execution_engine2 {
int instance;
 } intel_execution_engines2[];
 
-#define for_each_engine_class_instance(fd__, e__) \
-   for ((e__) = intel_execution_engines2;\
-(e__)->name; \
-(e__)++)
-
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
   enum drm_i915_gem_engine_class class,
@@ -122,4 +117,11 @@ void gem_require_engine(int gem_fd,
igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
+#define __for_each_engine_class_instance(fd__, e__) \
+   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_engine_class_instance(fd__, e__) \
+   for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
+   for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index b59af81819c7..2273ddb9e684 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,10 +434,8 @@ busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
 
i = 0;
fd[0] = -1;
-   for_each_engine_class_instance(fd, e_) {
-   if (!gem_has_engine(gem_fd, e_->class, e_->instance))
-   continue;
-   else if (e == e_)
+   for_each_engine_class_instance(gem_fd, e_) {
+   if (e == e_)
busy_idx = i;
 
fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
@@ -499,10 +497,7 @@ most_busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
unsigned int idle_idx, i;
 
i = 0;
-   for_each_engine_class_instance(fd, e_) {
-   if (!gem_has_engine(gem_fd, e_->class, e_->instance))
-   continue;
-
+   for_each_engine_class_instance(gem_fd, e_) {
if (e == e_)
idle_idx = i;
else if (spin)
@@ -559,10 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int 
num_engines,
unsigned int i;
 
i = 0;
-   for_each_engine_class_instance(fd, e) {
-   if (!gem_has_engine(gem_fd, e->class, e->instance))
-   continue;
-
+   for_each_engine_class_instance(gem_fd, e) {
if (spin)
__submit_spin_batch(gem_fd, spin, e, 64);
else
@@ -1677,10 +1669,8 @@ igt_main
igt_require_gem(fd);
igt_require(i915_type_id() > 0);
 
-   for_each_engine_class_instance(fd, e) {
-   if (gem_has_engine(fd, e->class, e->instance))
-   num_engines++;
-   }
+   for_each_engine_class_instance(fd, e)
+   num_engines++;
}
 
/**
@@ -1689,7 +1679,7 @@ igt_main
igt_subtest("invalid-init")
invalid_init();
 
-   for_each_engine_class_instance(fd, e) {
+   __for_each_engine_class_instance(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
 
/**
@@ -1888,7 +1878,7 @@ igt_main
gem_quiescent_gpu(fd);
}
 
-   for_each_engine_class_instance(fd, e) {
+   __for_each_engine_class_instance(render_fd, e) {
igt_subtest_group {
igt_fixture {
gem_require_engine(render_fd,
@@ -1897,10 +1887,10 @@ igt_main
}
 
igt_subtest_f("render-node-busy-%s", e->name)
-   single(fd, e, TEST_BUSY);
+   single(render_fd, e, TEST_BUSY);
igt_subtest_f("render-node-busy-idle-%s",
  e->name)
-   single(fd, e,
+   single(render_fd, e,
 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Avoid sleeping inside per-engine reset

[Patchwork]

== Series Details ==

Series: drm/i915: Avoid sleeping inside per-engine reset
URL   : https://patchwork.freedesktop.org/series/40838/
State : success

== Summary ==

 Known issues:

Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-nonblocking:
pass   -> FAIL   (shard-apl) fdo#103207
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#103207 https://bugs.freedesktop.org/show_bug.cgi?id=103207
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3495 pass:1830 dwarn:1   dfail:0   fail:8   skip:1655 
time:12853s
shard-hswtotal:3495 pass:1783 dwarn:1   dfail:0   fail:1   skip:1709 
time:11592s
shard-snbtotal:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 
time:6952s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8525/shards.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Include the HW breadcrumb whenever we trace the global_seqno

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-29 09:42:52)
> 
> On 27/03/2018 22:01, Chris Wilson wrote:
> > When we include a request's global_seqno in a GEM_TRACE it often helps
> > to know how that relates to the current breadcrumb as seen by the
> > hardware.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   drivers/gpu/drm/i915/i915_request.c | 28 +---
> >   drivers/gpu/drm/i915/intel_lrc.c|  6 --
> >   2 files changed, 21 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_request.c 
> > b/drivers/gpu/drm/i915/i915_request.c
> > index 2314a26cd7f8..585242831974 100644
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/drm/i915/i915_request.c
> > @@ -214,8 +214,11 @@ static int reset_all_global_seqno(struct 
> > drm_i915_private *i915, u32 seqno)
> >   struct i915_gem_timeline *timeline;
> >   struct intel_timeline *tl = engine->timeline;
> >   
> > - GEM_TRACE("%s seqno %d -> %d\n",
> > -   engine->name, tl->seqno, seqno);
> > + GEM_TRACE("%s seqno %d (current %d) -> %d\n",
> > +   engine->name,
> > +   tl->seqno,
> > +   intel_engine_get_seqno(engine),
> > +   seqno);
> >   
> >   if (!i915_seqno_passed(seqno, tl->seqno)) {
> >   /* Flush any waiters before we reuse the seqno */
> > @@ -386,10 +389,11 @@ static void i915_request_retire(struct i915_request 
> > *request)
> >   struct intel_engine_cs *engine = request->engine;
> >   struct i915_gem_active *active, *next;
> >   
> > - GEM_TRACE("%s(%d) fence %llx:%d, global_seqno %d\n",
> > -   engine->name, intel_engine_get_seqno(engine),
> > + GEM_TRACE("%s fence %llx:%d, global_seqno %d, current %d\n",
> > +   engine->name,
> > request->fence.context, request->fence.seqno,
> > -   request->global_seqno);
> > +   request->global_seqno,
> > +   intel_engine_get_seqno(engine));
> >   
> >   lockdep_assert_held(>i915->drm.struct_mutex);
> >   GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
> > @@ -508,10 +512,11 @@ void __i915_request_submit(struct i915_request 
> > *request)
> >   struct intel_engine_cs *engine = request->engine;
> >   u32 seqno;
> >   
> > - GEM_TRACE("%s fence %llx:%d -> global_seqno %d\n",
> > -   request->engine->name,
> > + GEM_TRACE("%s fence %llx:%d -> global_seqno %d, current %d\n",
> > +   engine->name,
> > request->fence.context, request->fence.seqno,
> > -   engine->timeline->seqno + 1);
> > +   engine->timeline->seqno + 1,
> > +   intel_engine_get_seqno(engine));
> >   
> >   GEM_BUG_ON(!irqs_disabled());
> >   lockdep_assert_held(>timeline->lock);
> > @@ -557,10 +562,11 @@ void __i915_request_unsubmit(struct i915_request 
> > *request)
> >   {
> >   struct intel_engine_cs *engine = request->engine;
> >   
> > - GEM_TRACE("%s fence %llx:%d <- global_seqno %d\n",
> > -   request->engine->name,
> > + GEM_TRACE("%s fence %llx:%d <- global_seqno %d, current %d\n",
> > +   engine->name,
> > request->fence.context, request->fence.seqno,
> > -   request->global_seqno);
> > +   request->global_seqno,
> > +   intel_engine_get_seqno(engine));
> >   
> >   GEM_BUG_ON(!irqs_disabled());
> >   lockdep_assert_held(>timeline->lock);
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index ed2c833a8b20..b5235f52a81b 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -454,10 +454,11 @@ static void execlists_submit_ports(struct 
> > intel_engine_cs *engine)
> >   desc = execlists_update_context(rq);
> >   GEM_DEBUG_EXEC(port[n].context_id = 
> > upper_32_bits(desc));
> >   
> > - GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%x, 
> > prio=%d\n",
> > + GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%d (current 
> > %d), prio=%d\n",
> > engine->name, n,
> > port[n].context_id, count,
> > rq->global_seqno,
> > +   intel_engine_get_seqno(engine),
> > rq_prio(rq));
> >   } else {
> >   GEM_BUG_ON(!n);
> > @@ -999,10 +1000,11 @@ static void execlists_submission_tasklet(unsigned 
> > long data)
> >   
> > EXECLISTS_ACTIVE_USER));
> >   
> >   rq = port_unpack(port, );
> > - GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x, prio=%d\n",
> > + 

Re: [Intel-gfx] [PATCH] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest

[Zhang, Xiong Y]

> Quoting Xiong Zhang (2018-03-29 11:58:41)
> > Four drm_mm_node are used to reserve guest ggtt space, but some of
> > them may aren't initialized and used in intel_vgt_balloon(), so these
> > unused
> 
> may be skipped and not initialised due to space constraints,
[Zhang, Xiong Y] OK, I will apply it. thanks
> 
> > drm_mm_node couldn't be removed through drm_mm_remove_node().
> >
> > Fixes: ff8f797557c7("drm/i915: return the correct usable aperture size
> > under gvt environment")
> > Signed-off-by: Xiong Zhang 
> 
> Had to read through and work out what the problem was; whether it was a
> bug elsewhere in vgpu or deliberate, so amending the commit msg to be
> clear would be helpful.
[Zhang, Xiong Y] bl_info.space[i] is initialized only on specific condition in 
intel_vgt_balloon(). When guest i915 driver is unloaded, intel_vgt_deballon() 
go through all four bl_info.space[3:0] and call drm_mm_remove_node() for each. 
If one isn't initialized, warning and reference null pointer occur in 
drm_mm_remove_node().
I will update commit message. Thanks.
> 
> Reviewed-by: Chris Wilson 
> 
> Who actually consumes bl_info? It just looks like being a balloon being set
> adrift.
[Zhang, Xiong Y] bl_info is internal static variable, only 
intel_vgt_deballoon() consume it at driver unload, it deballoon reserved ggtt 
space. 
> -Chris
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Re: [Intel-gfx] [PATCH v18 18/18] drm/i915: Keep plane size mult of 4 for NV12

[Maarten Lankhorst]

Op 29-03-18 om 10:06 schreef Vidya Srinivas:
> As per display WA 1106, to avoid corruption issues
> NV12 plane height needs to be multiplier of 4
> Hence we modify the fb src and destination height
> and width to be multiples of 4. Without this, pipe
> fifo underruns were seen on APL and KBL.
>
> Credits-to: Maarten Lankhorst 
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/intel_drv.h| 2 ++
>  drivers/gpu/drm/i915/intel_sprite.c | 8 
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9c58da0..a1f718d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -159,6 +159,8 @@
>  #define INTEL_I2C_BUS_DVO 1
>  #define INTEL_I2C_BUS_SDVO 2
>  
> +#define MULT4(x) ((x + 3) & ~0x03)
> +
>  /* these are outputs from the chip - integrated only
> external chips are via DVO or SDVO output */
>  enum intel_output_type {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 538d938..9f466c6 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane,
>   crtc_w--;
>   crtc_h--;
>  
> + if (fb->format->format == DRM_FORMAT_NV12) {
> + src_w = MULT4(src_w);
> + src_h = MULT4(src_h);
> + crtc_w = MULT4(crtc_w);
> + crtc_h = MULT4(crtc_h);
> + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w, crtc_h);
> + }
> +
>   spin_lock_irqsave(_priv->uncore.lock, irqflags);
>  
>   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

Nearly there!

Do we have limitations for width too? But I think we shouldn't ever adjust src 
for any format.
This means that we should probably get rid of the drm_rect_adjust_size call in 
intel_check_sprite_plane.

If any limitations of NV12 are hit, we should reject with -EINVAL instead so 
userspace can decide what to do.
The best place to put those checks is probably in skl_update_scaler, where they 
will be checked by the primary plane too.

This will mean the tests fail, but that can be fixed by selecting 16 as 
width/height for NV12 in IGT. If you change it to 16 you can put my r-b on it.

Also I think we should put the same limitations for width and height being a 
multiple in intel_framebuffer_init.

And on a final note for patch ordering, put the workaround and gen10 patch 
before enabling nv12 support.

~Maarten

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[Intel-gfx] ✓ Fi.CI.BAT: success for Add NV12 support (rev6)

[Patchwork]

== Series Details ==

Series: Add NV12 support (rev6)
URL   : https://patchwork.freedesktop.org/series/39670/
State : success

== Summary ==

Series 39670v6 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/6/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a-frame-sequence:
fail   -> PASS   (fi-cfl-s3) fdo#103481 +2

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:294s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:510s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:526s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:505s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:257  dwarn:0   dfail:0   fail:2   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:428s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:660s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:579s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:403s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:524s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s

4668e88d66074a81aae645e0db0391e7ea9afe8a drm-tip: 2018y-03m-28d-20h-45m-29s UTC 
integration manifest
5d680b7f7f67 drm/i915: Keep plane size mult of 4 for NV12
d9d4f4aca2bd drm/i915: Display WA 827
9f0ba6cc1fb6 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
92d4c93e45e6 drm/i915: Add NV12 support to intel_framebuffer_init
1e6aae51996a drm/i915: Add NV12 as supported format for sprite plane
d885f415973b drm/i915: Add NV12 as supported format for primary plane
6cd4cef9e05c drm/i915: Upscale scaler max scale for NV12
5a2b24e37735 drm/i915: Update format_is_yuv() to include NV12
80c277114c14 drm/i915: Set scaler mode for NV12
4afcd496d218 drm/i915/skl: split skl_compute_ddb function
2d0a3ec3badd drm/i915/skl+: nv12 workaround disable WM level 1-7
a874a478f08d drm/i915/skl+: make sure higher latency level has higher wm value
ec22906e4217 drm/i915/skl+: pass skl_wm_level struct to wm compute func
d6c846e59860 drm/i915/skl+: NV12 related changes for WM
987b18901f15 drm/i915/skl+: support verification of DDB HW state for NV12
6fb7287b6025 drm/i915/skl+: add NV12 in skl_format_to_fourcc
bb3b63aae302 drm/i915/skl+: refactor WM calculation for NV12
1a22e9ce642f drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8529/issues.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Include the HW breadcrumb whenever we trace the global_seqno

[Tvrtko Ursulin]

On 27/03/2018 22:01, Chris Wilson wrote:

When we include a request's global_seqno in a GEM_TRACE it often helps
to know how that relates to the current breadcrumb as seen by the
hardware.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_request.c | 28 +---
  drivers/gpu/drm/i915/intel_lrc.c|  6 --
  2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 2314a26cd7f8..585242831974 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -214,8 +214,11 @@ static int reset_all_global_seqno(struct drm_i915_private 
*i915, u32 seqno)
struct i915_gem_timeline *timeline;
struct intel_timeline *tl = engine->timeline;
  
-		GEM_TRACE("%s seqno %d -> %d\n",

- engine->name, tl->seqno, seqno);
+   GEM_TRACE("%s seqno %d (current %d) -> %d\n",
+ engine->name,
+ tl->seqno,
+ intel_engine_get_seqno(engine),
+ seqno);
  
  		if (!i915_seqno_passed(seqno, tl->seqno)) {

/* Flush any waiters before we reuse the seqno */
@@ -386,10 +389,11 @@ static void i915_request_retire(struct i915_request 
*request)
struct intel_engine_cs *engine = request->engine;
struct i915_gem_active *active, *next;
  
-	GEM_TRACE("%s(%d) fence %llx:%d, global_seqno %d\n",

- engine->name, intel_engine_get_seqno(engine),
+   GEM_TRACE("%s fence %llx:%d, global_seqno %d, current %d\n",
+ engine->name,
  request->fence.context, request->fence.seqno,
- request->global_seqno);
+ request->global_seqno,
+ intel_engine_get_seqno(engine));
  
  	lockdep_assert_held(>i915->drm.struct_mutex);

GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
@@ -508,10 +512,11 @@ void __i915_request_submit(struct i915_request *request)
struct intel_engine_cs *engine = request->engine;
u32 seqno;
  
-	GEM_TRACE("%s fence %llx:%d -> global_seqno %d\n",

- request->engine->name,
+   GEM_TRACE("%s fence %llx:%d -> global_seqno %d, current %d\n",
+ engine->name,
  request->fence.context, request->fence.seqno,
- engine->timeline->seqno + 1);
+ engine->timeline->seqno + 1,
+ intel_engine_get_seqno(engine));
  
  	GEM_BUG_ON(!irqs_disabled());

lockdep_assert_held(>timeline->lock);
@@ -557,10 +562,11 @@ void __i915_request_unsubmit(struct i915_request *request)
  {
struct intel_engine_cs *engine = request->engine;
  
-	GEM_TRACE("%s fence %llx:%d <- global_seqno %d\n",

- request->engine->name,
+   GEM_TRACE("%s fence %llx:%d <- global_seqno %d, current %d\n",
+ engine->name,
  request->fence.context, request->fence.seqno,
- request->global_seqno);
+ request->global_seqno,
+ intel_engine_get_seqno(engine));
  
  	GEM_BUG_ON(!irqs_disabled());

lockdep_assert_held(>timeline->lock);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ed2c833a8b20..b5235f52a81b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,10 +454,11 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
desc = execlists_update_context(rq);
GEM_DEBUG_EXEC(port[n].context_id = 
upper_32_bits(desc));
  
-			GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%x, prio=%d\n",

+   GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%d (current %d), 
prio=%d\n",
  engine->name, n,
  port[n].context_id, count,
  rq->global_seqno,
+ intel_engine_get_seqno(engine),
  rq_prio(rq));
} else {
GEM_BUG_ON(!n);
@@ -999,10 +1000,11 @@ static void execlists_submission_tasklet(unsigned long 
data)
EXECLISTS_ACTIVE_USER));
  
  			rq = port_unpack(port, );

-   GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x, prio=%d\n",
+   GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%d (current %d), 
prio=%d\n",
  engine->name,
  port->context_id, count,
  rq ? rq->global_seqno : 0,
+ intel_engine_get_seqno(engine),
  rq ? rq_prio(rq) : 0);
  
  			/* Check the context/desc id for this event matches */




The only thing I am not sure if