[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Fix memory leak in intel_hdcp auth

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Fix memory leak in intel_hdcp auth
URL   : https://patchwork.freedesktop.org/series/41099/
State : success

== Summary ==

 Possible new issues:

Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip   -> PASS   (shard-snb)
Subgroup fbc-stridechange:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-rgb565-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-pri-indfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
fail   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167 +1
Test kms_mmap_write_crc:
dmesg-warn -> PASS   (shard-hsw) fdo#103286

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286

shard-apltotal:3498 pass:1834 dwarn:1   dfail:0   fail:7   skip:1655 
time:12886s
shard-hswtotal:3498 pass:1784 dwarn:1   dfail:0   fail:2   skip:1710 
time:11590s
shard-snbtotal:3498 pass:1377 dwarn:1   dfail:0   fail:2   skip:2118 
time:7082s
Blacklisted hosts:
shard-kbltotal:3498 pass:1962 dwarn:1   dfail:0   fail:7   skip:1528 
time:9326s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8575/shards.html
___
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Re: [Intel-gfx] [PATCH v3 24/40] drm/i915: Implement HDCP2.2 repeater authentication

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/intel_hdcp.c:1182:30: sparse: incorrect type in 
>> assignment (different base types) @@expected restricted __be16 
>> [assigned] [usertype] k @@got e] k @@
   drivers/gpu/drm/i915/intel_hdcp.c:1182:30:expected restricted __be16 
[assigned] [usertype] k
   drivers/gpu/drm/i915/intel_hdcp.c:1182:30:got int
   drivers/gpu/drm/i915/intel_hdcp.c:1277:12: warning: 
'hdcp2_authenticate_sink' defined but not used [-Wunused-function]
static int hdcp2_authenticate_sink(struct intel_connector *connector)
   ^~~
   In file included from drivers/gpu/drm/i915/intel_hdcp.c:13:0:
   include/linux/mei_hdcp.h:148:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:144:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +1182 drivers/gpu/drm/i915/intel_hdcp.c

  1163  
  1164  static
  1165  int hdcp2_propagate_stream_management_info(struct intel_connector 
*connector)
  1166  {
  1167  struct intel_digital_port *intel_dig_port = 
conn_to_dig_port(connector);
  1168  struct intel_hdcp *hdcp = >hdcp;
  1169  union {
  1170  struct hdcp2_rep_stream_manage stream_manage;
  1171  struct hdcp2_rep_stream_ready stream_ready;
  1172  } msgs;
  1173  const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
  1174  int ret;
  1175  
  1176  /* Prepare RepeaterAuth_Stream_Manage msg */
  1177  msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
  1178  reverse_endianness(msgs.stream_manage.seq_num_m, 
HDCP_2_2_SEQ_NUM_LEN,
  1179 (u8 *)>seq_num_m);
  1180  
  1181  /* K no of streams is fixed as 1. Stored as big-endian. */
> 1182  msgs.stream_manage.k = __swab16(1);
  1183  
  1184  /* For HDMI this is forced to be 0x0. For DP SST also this is 
0x0. */
  1185  msgs.stream_manage.streams[0].stream_id = 0;
  1186  msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
  1187  
  1188  /* Send it to Repeater */
  1189  ret = shim->write_2_2_msg(intel_dig_port, _manage,
  1190sizeof(msgs.stream_manage));
  1191  if (ret < 0)
  1192  return ret;
  1193  
  1194  ret = shim->read_2_2_msg(intel_dig_port, 
HDCP_2_2_REP_STREAM_READY,
  1195   _ready, 
sizeof(msgs.stream_ready));
  1196  if (ret < 0)
  1197  return ret;
  1198  
  1199  hdcp->mei_data.seq_num_m = hdcp->seq_num_m;
  1200  hdcp->mei_data.streams[0].stream_type = hdcp->content_type;
  1201  
  1202  ret = hdcp2_verify_mprime(hdcp, _ready);
  1203  if (ret < 0)
  1204  return ret;
  1205  
  1206  hdcp->seq_num_m++;
  1207  
  1208  if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
  1209  DRM_DEBUG_KMS("seq_num_m roll over.\n");
  1210  return -1;
  1211  }
  1212  return 0;
  1213  }
  1214  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Timestamps for PSR entry and exit interrupts.

[Souza, Jose]

On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> Timestamps are useful for IGT tests that trigger PSR exit and/or wait
> for
> PSR entry.
> 
> v2: Removed seqlock (Ville)
> Removed erroneous warning in irq loop (Chris)
> 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Signed-off-by: Dhinakaran Pandiyan 

Reviewed-by: Jose Roberto de Souza 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
>  drivers/gpu/drm/i915/i915_drv.h | 2 ++
>  drivers/gpu/drm/i915/intel_psr.c| 9 +++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 28f91df5b401..b378fa013054 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2686,6 +2686,13 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
>   }
>   mutex_unlock(_priv->psr.lock);
>  
> + if (READ_ONCE(dev_priv->psr.debug)) {
> + seq_printf(m, "Last attempted entry at: %lld\n",
> +dev_priv->psr.last_entry_attempt);
> + seq_printf(m, "Last exit at: %lld\n",
> +dev_priv->psr.last_exit);
> + }
> +
>   intel_runtime_pm_put(dev_priv);
>   return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index b97ed0cd4ca9..2124a795d10c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -610,6 +610,8 @@ struct i915_psr {
>   bool psr2_enabled;
>   u8 sink_sync_latency;
>   bool debug;
> + ktime_t last_entry_attempt;
> + ktime_t last_exit;
>  
>   void (*enable_source)(struct intel_dp *,
> const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 56ff2d7691a1..a11a6d940203 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -131,6 +131,7 @@ void intel_psr_irq_handler(struct
> drm_i915_private *dev_priv, u32 psr_iir)
>  {
>   u32 transcoders = BIT(TRANSCODER_EDP);
>   enum transcoder cpu_transcoder;
> + ktime_t time_ns =  ktime_get();
>  
>   if (INTEL_GEN(dev_priv) >= 8)
>   transcoders |= BIT(TRANSCODER_A) |
> @@ -143,13 +144,17 @@ void intel_psr_irq_handler(struct
> drm_i915_private *dev_priv, u32 psr_iir)
>   DRM_DEBUG_KMS("[transcoder %s] PSR aux
> error\n",
> transcoder_name(cpu_transcoder
> ));
>  
> - if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder))
> + if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> + dev_priv->psr.last_entry_attempt = time_ns;
>   DRM_DEBUG_KMS("[transcoder %s] PSR entry
> attempt in 2 vblanks\n",
> transcoder_name(cpu_transcoder
> ));
> + }
>  
> - if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder))
> + if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
> + dev_priv->psr.last_exit = time_ns;
>   DRM_DEBUG_KMS("[transcoder %s] PSR exit
> completed\n",
> transcoder_name(cpu_transcoder
> ));
> + }
>   }
>  }
>  
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Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Control PSR interrupts via debugfs

[Souza, Jose]

On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> Interrupts other than the one for AUX errors are required only for
> debug,
> so unmask them via debugfs when the user requests debug.
> 
> User can make such a request with
> echo 1 > /dri/0/i915_edp_psr_debug
> 
> There are no locks to serialize PSR debug enabling from
> irq_postinstall() and debugfs for simplicity. As irq_postinstall() is
> called only during module initialization/resume and IGT subtests
> aren't expected to modify PSR debug at those times, we should be
> safe.
> 
> v2: Unroll loops (Ville)
> Avoid resetting error mask bits.
> 
> v3: Unmask interrupts in postinstall() if debug was still enabled.
> Avoid RMW (Ville)
> 
> Cc: Rodrigo Vivi 
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 36 +-
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_irq.c | 57 +++--
> --
>  drivers/gpu/drm/i915/intel_drv.h|  2 ++
>  drivers/gpu/drm/i915/intel_psr.c| 60
> +
>  5 files changed, 116 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1dba2c451255..28f91df5b401 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2690,6 +2690,39 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
>   return 0;
>  }
>  
> +static int
> +i915_edp_psr_debug_set(void *data, u64 val)
> +{
> + struct drm_i915_private *dev_priv = data;
> +
> + if (!CAN_PSR(dev_priv))
> + return -ENODEV;
> +
> + DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
> +
> + intel_runtime_pm_get(dev_priv);
> + intel_psr_debug_control(dev_priv, !!val);
> + intel_runtime_pm_put(dev_priv);
> +
> + return 0;
> +}
> +
> +static int
> +i915_edp_psr_debug_get(void *data, u64 *val)
> +{
> + struct drm_i915_private *dev_priv = data;
> +
> + if (!CAN_PSR(dev_priv))
> + return -ENODEV;
> +
> + *val = READ_ONCE(dev_priv->psr.debug);
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> + i915_edp_psr_debug_get,
> i915_edp_psr_debug_set,
> + "%llu\n");
> +
>  static int i915_sink_crc(struct seq_file *m, void *data)
>  {
>   struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4812,7 +4845,8 @@ static const struct i915_debugfs_files {
>   {"i915_guc_log_relay", _guc_log_relay_fops},
>   {"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
>   {"i915_ipc_status", _ipc_status_fops},
> - {"i915_drrs_ctl", _drrs_ctl_fops}
> + {"i915_drrs_ctl", _drrs_ctl_fops},
> + {"i915_edp_psr_debug", _edp_psr_debug_fops}


same as bellow, why not i915_edp_psr_int_debug?

>  };
>  
>  int i915_debugfs_register(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b171bb96..b97ed0cd4ca9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -609,6 +609,7 @@ struct i915_psr {
>   bool has_hw_tracking;
>   bool psr2_enabled;
>   u8 sink_sync_latency;
> + bool debug;

maybe change to a name that gives more information about the use of
this flag? like int_debug?

>  
>   void (*enable_source)(struct intel_dp *,
> const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 8a894adf2ca1..714570955196 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2391,40 +2391,6 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>   ironlake_rps_change_irq_handler(dev_priv);
>  }
>  
> -static void hsw_edp_psr_irq_handler(struct drm_i915_private
> *dev_priv)
> -{
> - u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> - u32 edp_psr_imr = I915_READ(EDP_PSR_IMR);
> - u32 mask = BIT(TRANSCODER_EDP);
> - enum transcoder cpu_transcoder;
> -
> - if (INTEL_GEN(dev_priv) >= 8)
> - mask |= BIT(TRANSCODER_A) |
> - BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C);
> -
> - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
> mask) {
> - if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder))
> - DRM_DEBUG_KMS("Transcoder %s PSR error\n",
> -   transcoder_name(cpu_transcoder
> ));
> -
> - if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder))
> {
> - DRM_DEBUG_KMS("Transcoder %s PSR prepare
> entry in 2 vblanks\n",
> -   

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix memory leak in intel_hdcp auth

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Fix memory leak in intel_hdcp auth
URL   : https://patchwork.freedesktop.org/series/41099/
State : success

== Summary ==

Series 41099v1 series starting with [1/2] drm/i915: Fix memory leak in 
intel_hdcp auth
https://patchwork.freedesktop.org/api/1.0/series/41099/revisions/1/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail   -> PASS   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:521s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:524s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:517s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:418s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:412s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:426s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:502s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:501s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:417s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:541s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s

29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC 
integration manifest
54ab53f6b376 drm/i915: Use int instead of u32 to cache GuC logging level
c7076cb5c716 drm/i915: Fix memory leak in intel_hdcp auth

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8575/issues.html
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[Intel-gfx] [PATCH i-g-t v4] tests/kms_rotation_crc: Move platform checks to one place for non exhaust fence cases

[Radhakrishna Sripada]

From: Anusha Srivatsa 

Cleanup the testcases by moving the platform checks to a single function.

The earlier version of the path is posted here [1]

v2: Make use of the property enums to get the supported rotations
v3: Move hardcodings to a single function(Ville)
v4: Include the cherryview exception for reflect subtest(Maarten)

[1]: https://patchwork.freedesktop.org/patch/209647/

Cc: Radhakrishna Sripada 
Cc: Ville Syrjälä 
Cc: Daniel Vetter 
Cc: Maarten Lankhorst 
Cc: Mika Kahola 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Radhakrishna Sripada 
---
 tests/kms_rotation_crc.c | 35 ---
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 0cd5c6e..aeb6c73 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -43,6 +43,7 @@ typedef struct {
uint32_t override_fmt;
uint64_t override_tiling;
int devid;
+   int gen;
 } data_t;
 
 typedef struct {
@@ -301,6 +302,17 @@ static void wait_for_pageflip(int fd)
igt_assert(drmHandleEvent(fd, ) == 0);
 }
 
+static void igt_check_rotation(data_t *data)
+{
+   if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
+   igt_require(data->gen >= 9);
+   else if (data->rotation & IGT_REFLECT_X)
+   igt_require(data->gen >= 10 ||
+   (IS_CHERRYVIEW(data->devid) && (data->rotation & 
IGT_ROTATION_0)));
+   else if (data->rotation & IGT_ROTATION_180)
+   igt_require(data->gen >= 4);
+}
+
 static void test_single_case(data_t *data, enum pipe pipe,
 igt_output_t *output, igt_plane_t *plane,
 enum rectangle_type rect,
@@ -369,15 +381,18 @@ static void test_plane_rotation(data_t *data, int 
plane_type, bool test_bad_form
 
igt_display_require_output(display);
 
+   igt_check_rotation(data);
+
for_each_pipe_with_valid_output(display, pipe, output) {
igt_plane_t *plane;
int i, j;
 
-   if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
-   continue;
-
igt_output_set_pipe(output, pipe);
 
+   if (IS_CHERRYVIEW(data->devid) && (data->rotation & 
IGT_REFLECT_X) &&
+   pipe != kmstest_pipe_to_index('B'))
+   continue;
+
plane = igt_output_get_plane_type(output, plane_type);
igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 
@@ -538,14 +553,13 @@ igt_main
};
 
data_t data = {};
-   int gen = 0;
 
igt_skip_on_simulation();
 
igt_fixture {
data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
data.devid = intel_get_drm_devid(data.gfx_fd);
-   gen = intel_gen(data.devid);
+   data.gen = intel_gen(data.devid);
 
kmstest_set_vt_graphics_mode();
 
@@ -558,16 +572,12 @@ igt_main
igt_subtest_f("%s-rotation-%s",
  plane_test_str(subtest->plane),
  rot_test_str(subtest->rot)) {
-   igt_require(!(subtest->rot &
-   (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
-   gen >= 9);
data.rotation = subtest->rot;
test_plane_rotation(, subtest->plane, false);
}
}
 
igt_subtest_f("sprite-rotation-90-pos-100-0") {
-   igt_require(gen >= 9);
data.rotation = IGT_ROTATION_90;
data.pos_x = 100,
data.pos_y = 0;
@@ -577,7 +587,6 @@ igt_main
data.pos_y = 0;
 
igt_subtest_f("bad-pixel-format") {
-   igt_require(gen >= 9);
data.rotation = IGT_ROTATION_90;
data.override_fmt = DRM_FORMAT_RGB565;
test_plane_rotation(, DRM_PLANE_TYPE_PRIMARY, true);
@@ -585,7 +594,6 @@ igt_main
data.override_fmt = 0;
 
igt_subtest_f("bad-tiling") {
-   igt_require(gen >= 9);
data.rotation = IGT_ROTATION_90;
data.override_tiling = LOCAL_I915_FORMAT_MOD_X_TILED;
test_plane_rotation(, DRM_PLANE_TYPE_PRIMARY, true);
@@ -596,9 +604,6 @@ igt_main
igt_subtest_f("primary-%s-reflect-x-%s",
  tiling_test_str(reflect_x->tiling),
  rot_test_str(reflect_x->rot)) {
-   igt_require(gen >= 10 ||
-   (IS_CHERRYVIEW(data.devid) && 
reflect_x->rot == IGT_ROTATION_0
- 

[Intel-gfx] [PATCH 1/2] drm/i915: Fix memory leak in intel_hdcp auth

[Radhakrishna Sripada]

Static code analysis tool reported memory leak in
intel_hdcp_auth_downstream. Fixing the memory leak.

Cc: Anusha Srivatsa 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..ce771f6c1a5a 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -186,14 +186,18 @@ int intel_hdcp_auth_downstream(struct intel_digital_port 
*intel_dig_port,
return -ENOMEM;
 
ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
-   if (ret)
+   if (ret) {
+   kfree(ksv_fifo);
return ret;
+   }
 
/* Process V' values from the receiver */
for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
ret = shim->read_v_prime_part(intel_dig_port, i, );
-   if (ret)
+   if (ret) {
+   kfree(ksv_fifo);
return ret;
+   }
I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
}
 
@@ -222,8 +226,10 @@ int intel_hdcp_auth_downstream(struct intel_digital_port 
*intel_dig_port,
sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
 
ret = intel_write_sha_text(dev_priv, sha_text);
-   if (ret < 0)
+   if (ret < 0) {
+   kfree(ksv_fifo);
return ret;
+   }
 
/* Programming guide writes this every 64 bytes */
sha_idx += sizeof(sha_text);
@@ -245,13 +251,18 @@ int intel_hdcp_auth_downstream(struct intel_digital_port 
*intel_dig_port,
continue;
 
ret = intel_write_sha_text(dev_priv, sha_text);
-   if (ret < 0)
+   if (ret < 0) {
+   kfree(ksv_fifo);
return ret;
+   }
+
sha_leftovers = 0;
sha_text = 0;
sha_idx += sizeof(sha_text);
}
 
+   kfree(ksv_fifo);
+
/*
 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many
 * bytes are leftover from the last ksv, we might be able to fit them
-- 
2.9.3

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[Intel-gfx] [PATCH 2/2] drm/i915: Use int instead of u32 to cache GuC logging level

[Radhakrishna Sripada]

Static code analysis tool has reported an unused check of
log_level<0 when using u32. Use int instead of u32 to store guc_log_level.

Cc: Anusha Srivatsa 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_guc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a00a59a7d9ec..eb6f0bb7c084 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -225,7 +225,7 @@ static u32 get_core_family(struct drm_i915_private 
*dev_priv)
 
 static u32 get_log_control_flags(void)
 {
-   u32 level = i915_modparams.guc_log_level;
+   int level = i915_modparams.guc_log_level;
u32 flags = 0;
 
GEM_BUG_ON(level < 0);
-- 
2.9.3

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[Intel-gfx] [RFC PATCH] misc/mei/hdcp: mei_cldev_state_notify_clients() can be static

[kbuild test robot]

Fixes: ca998fc3888e ("misc/mei/hdcp: Notifier chain for mei cldev state change")
Signed-off-by: Fengguang Wu 
---
 mei_hdcp.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 2811a25..452e60d 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -36,7 +36,7 @@
 
 static BLOCKING_NOTIFIER_HEAD(mei_cldev_notifier_list);
 
-void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
+static void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool 
enabled)
 {
if (enabled)
blocking_notifier_call_chain(_cldev_notifier_list,
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Re: [Intel-gfx] [PATCH v3 12/40] misc/mei/hdcp: Initiate Locality check

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/misc/mei/hdcp/mei_hdcp.c:52:5: error: redefinition of 
'mei_initiate_hdcp2_session'
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:137:5: note: previous definition of 
'mei_initiate_hdcp2_session' was here
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   drivers/misc/mei/hdcp/mei_hdcp.c:122:1: error: redefinition of 
'mei_verify_receiver_cert_prepare_km'
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:144:1: note: previous definition of 
'mei_verify_receiver_cert_prepare_km' was here
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   drivers/misc/mei/hdcp/mei_hdcp.c:200:5: error: redefinition of 
'mei_verify_hprime'
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:154:5: note: previous definition of 
'mei_verify_hprime' was here
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
   drivers/misc/mei/hdcp/mei_hdcp.c:258:5: error: redefinition of 
'mei_store_pairing_info'
int mei_store_pairing_info(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:160:5: note: previous definition of 
'mei_store_pairing_info' was here
int mei_store_pairing_info(struct mei_cl_device *cldev,
^~
>> drivers/misc/mei/hdcp/mei_hdcp.c:318:5: error: redefinition of 
>> 'mei_initiate_locality_check'
int mei_initiate_locality_check(struct mei_cl_device *cldev,
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:167:5: note: previous definition of 
'mei_initiate_locality_check' was here
int mei_initiate_locality_check(struct mei_cl_device *cldev,
^~~
   drivers/misc/mei/hdcp/mei_hdcp.c:374:5: error: redefinition of 
'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:128:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   drivers/misc/mei/hdcp/mei_hdcp.c:380:5: error: redefinition of 
'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:132:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:132:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:128:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_initiate_locality_check +318 drivers/misc/mei/hdcp/mei_hdcp.c

   246  
   247  /**
   248   * mei_store_pairing_info:
   249   *  Function to store pairing info received from panel
   250   *
   251   * @cldev   : Pointer for mei client device
   252   * @data: Intel HW specific Data
   253   * @pairing_info: Pointer for AKE_Send_Pairing_Info
   254   *
   255   * Returns 0 on Success, <0 on Failure
   256   */
   257  
 > 258  int mei_store_pairing_info(struct mei_cl_device *cldev,
   259 struct mei_hdcp_data *data,
   260 struct hdcp2_ake_send_pairing_info 
*pairin

Re: [Intel-gfx] [PATCH v3 11/40] misc/mei/hdcp: Store the HDCP Pairing info

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/misc/mei/hdcp/mei_hdcp.c:52:5: error: redefinition of 
'mei_initiate_hdcp2_session'
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:134:5: note: previous definition of 
'mei_initiate_hdcp2_session' was here
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   drivers/misc/mei/hdcp/mei_hdcp.c:122:1: error: redefinition of 
'mei_verify_receiver_cert_prepare_km'
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:141:1: note: previous definition of 
'mei_verify_receiver_cert_prepare_km' was here
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   drivers/misc/mei/hdcp/mei_hdcp.c:200:5: error: redefinition of 
'mei_verify_hprime'
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:151:5: note: previous definition of 
'mei_verify_hprime' was here
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
>> drivers/misc/mei/hdcp/mei_hdcp.c:258:5: error: redefinition of 
>> 'mei_store_pairing_info'
int mei_store_pairing_info(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:157:5: note: previous definition of 
'mei_store_pairing_info' was here
int mei_store_pairing_info(struct mei_cl_device *cldev,
^~
   drivers/misc/mei/hdcp/mei_hdcp.c:318:5: error: redefinition of 
'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:125:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   drivers/misc/mei/hdcp/mei_hdcp.c:324:5: error: redefinition of 
'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:129:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:129:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:125:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_store_pairing_info +258 drivers/misc/mei/hdcp/mei_hdcp.c

   188  
   189  /**
   190   * mei_verify_hprime:
   191   *  Function to verify AKE_Send_H_prime received
   192   *
   193   * @cldev   : Pointer for mei client device
   194   * @data: Intel HW specific Data
   195   * @rx_hprime   : Pointer for AKE_Send_H_prime
   196   * @hprime_sz   : Input buffer size
   197   *
   198   * Returns 0 on Success, <0 on Failure
   199   */
 > 200  int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
 > *data,
   201struct hdcp2_ake_send_hprime *rx_hprime)
   202  {
   203  struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } };
   204  struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } 
};
   205  struct device *dev;
   206  ssize_t byte;
   207  
   208  if (!data || !rx_hprime)
   209  return -EINVAL;
   210  
   211  dev = >dev;
   212  
   213  send_hprime_in.header.api_version = HDCP_API_VERSION;
   214  se

Re: [Intel-gfx] [PATCH v3 10/40] misc/mei/hdcp: Verify H_prime

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/misc/mei/hdcp/mei_hdcp.c:52:5: error: redefinition of 
'mei_initiate_hdcp2_session'
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:131:5: note: previous definition of 
'mei_initiate_hdcp2_session' was here
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   drivers/misc/mei/hdcp/mei_hdcp.c:122:1: error: redefinition of 
'mei_verify_receiver_cert_prepare_km'
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:138:1: note: previous definition of 
'mei_verify_receiver_cert_prepare_km' was here
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
>> drivers/misc/mei/hdcp/mei_hdcp.c:200:5: error: redefinition of 
>> 'mei_verify_hprime'
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:148:5: note: previous definition of 
'mei_verify_hprime' was here
int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
^
   drivers/misc/mei/hdcp/mei_hdcp.c:257:5: error: redefinition of 
'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:122:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   drivers/misc/mei/hdcp/mei_hdcp.c:263:5: error: redefinition of 
'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:126:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:126:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:122:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_verify_hprime +200 drivers/misc/mei/hdcp/mei_hdcp.c

   106  
   107  /**
   108   * mei_verify_receiver_cert_prepare_km:
   109   *  Function to verify the Receiver Certificate AKE_Send_Cert
   110   *  and prepare AKE_Stored_Km or AKE_No_Stored_Km
   111   *
   112   * @cldev   : Pointer for mei client device
   113   * @data: Intel HW specific Data
   114   * @rx_cert : Pointer for AKE_Send_Cert
   115   * @km_stored   : Pointer for pairing status flag
   116   * @ek_pub_km   : Pointer for output msg
   117   * @msg_sz  : Pointer for size of AKE_X_Km
   118   *
   119   * Returns 0 on Success, <0 on Failure
   120   */
   121  int
 > 122  mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
   123  struct mei_hdcp_data *data,
   124  struct hdcp2_ake_send_cert *rx_cert,
   125  bool *km_stored,
   126  struct hdcp2_ake_no_stored_km 
*ek_pub_km,
   127  size_t *msg_sz)
   128  {
   129  struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 
0 } };
   130  struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { 
{ 0 } };
   131  struct device *dev;
   132  ssize_t byte;
   133  
   134  if (!data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz)
   135  return -EINVAL;
   136  
   137  dev

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/4] drm/i915: Enable edp psr error interrupts on hsw

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915: Enable edp psr error interrupts 
on hsw
URL   : https://patchwork.freedesktop.org/series/41095/
State : failure

== Summary ==

Series 41095v1 series starting with [v3,1/4] drm/i915: Enable edp psr error 
interrupts on hsw
https://patchwork.freedesktop.org/api/1.0/series/41095/revisions/1/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass   -> INCOMPLETE (fi-elk-e7500)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103841
Subgroup hdmi-hpd-fast:
skip   -> FAIL   (fi-kbl-7500u) fdo#102672
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail   -> PASS   (fi-skl-6700k2) fdo#103191

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:428s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:383s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:216  pass:193  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-elk-e7500 total:229  pass:180  dwarn:1   dfail:0   fail:0   skip:47 
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:259  dwarn:1   dfail:0   fail:2   skip:23  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:663s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:435s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:575s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:402s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:526s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:490s

29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC 
integration manifest
9fde80e28074 drm/i915/psr: Timestamps for PSR entry and exit interrupts.
eb2120118831 drm/i915/psr: Control PSR interrupts via debugfs
bf91538c6b8d drm/i915: Enable edp psr error interrupts on bdw+
7f73ae199d28 drm/i915: Enable edp psr error interrupts on hsw

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8574/issues.html
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: Store preemption capability in engine->flags

[Daniele Ceraolo Spurio]

On 03/04/18 11:35, Chris Wilson wrote:

Let's avoid having to delve down the pointer chain to see if the i915
device has support for preemption and store that on the engine, which
made the decision in the first place!

v2: Refactor common preemption policy between execlists/guc.

Signed-off-by: Chris Wilson 
Cc: Tomasz Lis 
Cc: Daniele Ceraolo Spurio 
Cc: Michał Winiarski 
Cc: Tvrtko Ursulin 


Reviewed-by: Daniele Ceraolo Spurio 




+static inline bool
+__execlists_need_preempt(int prio, int last)


Nitpick: this fits on a single line

Daniele


+{
+   return prio > max(0, last);
+}
+
  static inline void
  execlists_set_active(struct intel_engine_execlists *execlists,
 unsigned int bit)


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915: Enable edp psr error interrupts on hsw

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915: Enable edp psr error interrupts 
on hsw
URL   : https://patchwork.freedesktop.org/series/41095/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7f73ae199d28 drm/i915: Enable edp psr error interrupts on hsw
-:109: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#109: FILE: drivers/gpu/drm/i915/i915_reg.h:4017:
+#define   EDP_PSR_ERROR(1<<2)
  ^

-:110: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#110: FILE: drivers/gpu/drm/i915/i915_reg.h:4018:
+#define   EDP_PSR_POST_EXIT(1<<1)
  ^

-:111: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#111: FILE: drivers/gpu/drm/i915/i915_reg.h:4019:
+#define   EDP_PSR_PRE_ENTRY(1<<0)
  ^

-:120: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#120: FILE: drivers/gpu/drm/i915/i915_reg.h:6830:
+#define DE_EDP_PSR_INT_HSW (1<<19)
  ^

total: 0 errors, 0 warnings, 4 checks, 78 lines checked
bf91538c6b8d drm/i915: Enable edp psr error interrupts on bdw+
-:158: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#158: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:158: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__t' - possible 
side-effects?
#158: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:159: CHECK:SPACING: No space is necessary after a cast
#159: FILE: drivers/gpu/drm/i915/intel_display.h:222:
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \

-:160: WARNING:SPACING: space prohibited between function name and open 
parenthesis '('
#160: FILE: drivers/gpu/drm/i915/intel_display.h:223:
+   for_each_if ((__mask) & (1 << (__t)))

total: 1 errors, 1 warnings, 2 checks, 123 lines checked
eb2120118831 drm/i915/psr: Control PSR interrupts via debugfs
9fde80e28074 drm/i915/psr: Timestamps for PSR entry and exit interrupts.

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Re: [Intel-gfx] [PATCH v3 09/40] misc/mei/hdcp: Verify Receiver Cert and prepare km

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/misc/mei/hdcp/mei_hdcp.c:52:5: error: redefinition of 
'mei_initiate_hdcp2_session'
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:129:5: note: previous definition of 
'mei_initiate_hdcp2_session' was here
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
>> drivers/misc/mei/hdcp/mei_hdcp.c:122:1: error: redefinition of 
>> 'mei_verify_receiver_cert_prepare_km'
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:136:1: note: previous definition of 
'mei_verify_receiver_cert_prepare_km' was here
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
^~~
   drivers/misc/mei/hdcp/mei_hdcp.c:199:5: error: redefinition of 
'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:120:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   drivers/misc/mei/hdcp/mei_hdcp.c:205:5: error: redefinition of 
'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:124:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:124:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:120:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_verify_receiver_cert_prepare_km +122 drivers/misc/mei/hdcp/mei_hdcp.c

41  
42  /**
43   * mei_initiate_hdcp2_session:
44   *  Function to start a Wired HDCP2.2 Tx Session with ME FW
45   *
46   * @cldev   : Pointer for mei client device
47   * @data: Intel HW specific Data
48   * @ake_data: ptr to store AKE_Init
49   *
50   * Returns 0 on Success, <0 on Failure.
51   */
  > 52  int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
53 struct mei_hdcp_data *data,
54 struct hdcp2_ake_init *ake_data)
55  {
56  struct wired_cmd_initiate_hdcp2_session_in session_init_in = { 
{ 0 } };
57  struct wired_cmd_initiate_hdcp2_session_out
58  session_init_out = { { 
0 } };
59  struct device *dev;
60  ssize_t byte;
61  
62  if (!data || !ake_data)
63  return -EINVAL;
64  
65  dev = >dev;
66  
67  session_init_in.header.api_version = HDCP_API_VERSION;
68  session_init_in.header.command_id = 
WIRED_INITIATE_HDCP2_SESSION;
69  session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
70  session_init_in.header.buffer_len =
71  
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
72  
73  session_init_in.port.integrated_port_type = data->port_type;
74  session_init_in.port.physical_port = data->port;
75  session_init_in.protocol = (uint8_t)data->protocol;
76  
77  byte = mei_cldev_send(cldev, (u8 *)_init_in,
78sizeof(session_init_in));
79  if (byte < 0) {
80  dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
81  return byte;
82  }
83  

[Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Control PSR interrupts via debugfs

[Dhinakaran Pandiyan]

Interrupts other than the one for AUX errors are required only for debug,
so unmask them via debugfs when the user requests debug.

User can make such a request with
echo 1 > /dri/0/i915_edp_psr_debug

There are no locks to serialize PSR debug enabling from
irq_postinstall() and debugfs for simplicity. As irq_postinstall() is
called only during module initialization/resume and IGT subtests
aren't expected to modify PSR debug at those times, we should be safe.

v2: Unroll loops (Ville)
Avoid resetting error mask bits.

v3: Unmask interrupts in postinstall() if debug was still enabled.
Avoid RMW (Ville)

Cc: Rodrigo Vivi 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 36 +-
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_irq.c | 57 +++
 drivers/gpu/drm/i915/intel_drv.h|  2 ++
 drivers/gpu/drm/i915/intel_psr.c| 60 +
 5 files changed, 116 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1dba2c451255..28f91df5b401 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2690,6 +2690,39 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
return 0;
 }
 
+static int
+i915_edp_psr_debug_set(void *data, u64 val)
+{
+   struct drm_i915_private *dev_priv = data;
+
+   if (!CAN_PSR(dev_priv))
+   return -ENODEV;
+
+   DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
+
+   intel_runtime_pm_get(dev_priv);
+   intel_psr_debug_control(dev_priv, !!val);
+   intel_runtime_pm_put(dev_priv);
+
+   return 0;
+}
+
+static int
+i915_edp_psr_debug_get(void *data, u64 *val)
+{
+   struct drm_i915_private *dev_priv = data;
+
+   if (!CAN_PSR(dev_priv))
+   return -ENODEV;
+
+   *val = READ_ONCE(dev_priv->psr.debug);
+   return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
+   i915_edp_psr_debug_get, i915_edp_psr_debug_set,
+   "%llu\n");
+
 static int i915_sink_crc(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4812,7 +4845,8 @@ static const struct i915_debugfs_files {
{"i915_guc_log_relay", _guc_log_relay_fops},
{"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
{"i915_ipc_status", _ipc_status_fops},
-   {"i915_drrs_ctl", _drrs_ctl_fops}
+   {"i915_drrs_ctl", _drrs_ctl_fops},
+   {"i915_edp_psr_debug", _edp_psr_debug_fops}
 };
 
 int i915_debugfs_register(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b171bb96..b97ed0cd4ca9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -609,6 +609,7 @@ struct i915_psr {
bool has_hw_tracking;
bool psr2_enabled;
u8 sink_sync_latency;
+   bool debug;
 
void (*enable_source)(struct intel_dp *,
  const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a894adf2ca1..714570955196 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2391,40 +2391,6 @@ static void ilk_display_irq_handler(struct 
drm_i915_private *dev_priv,
ironlake_rps_change_irq_handler(dev_priv);
 }
 
-static void hsw_edp_psr_irq_handler(struct drm_i915_private *dev_priv)
-{
-   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
-   u32 edp_psr_imr = I915_READ(EDP_PSR_IMR);
-   u32 mask = BIT(TRANSCODER_EDP);
-   enum transcoder cpu_transcoder;
-
-   if (INTEL_GEN(dev_priv) >= 8)
-   mask |= BIT(TRANSCODER_A) |
-   BIT(TRANSCODER_B) |
-   BIT(TRANSCODER_C);
-
-   for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, mask) {
-   if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder))
-   DRM_DEBUG_KMS("Transcoder %s PSR error\n",
- transcoder_name(cpu_transcoder));
-
-   if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
-   DRM_DEBUG_KMS("Transcoder %s PSR prepare entry in 2 
vblanks\n",
- transcoder_name(cpu_transcoder));
-   edp_psr_imr |= EDP_PSR_PRE_ENTRY(cpu_transcoder);
-   }
-
-   if (edp_psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
-   DRM_DEBUG_KMS("Transcoder %s PSR exit completed\n",
- transcoder_name(cpu_transcoder));
-   edp_psr_imr &= 

[Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Timestamps for PSR entry and exit interrupts.

[Dhinakaran Pandiyan]

Timestamps are useful for IGT tests that trigger PSR exit and/or wait for
PSR entry.

v2: Removed seqlock (Ville)
Removed erroneous warning in irq loop (Chris)

Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 drivers/gpu/drm/i915/intel_psr.c| 9 +++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 28f91df5b401..b378fa013054 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2686,6 +2686,13 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
}
mutex_unlock(_priv->psr.lock);
 
+   if (READ_ONCE(dev_priv->psr.debug)) {
+   seq_printf(m, "Last attempted entry at: %lld\n",
+  dev_priv->psr.last_entry_attempt);
+   seq_printf(m, "Last exit at: %lld\n",
+  dev_priv->psr.last_exit);
+   }
+
intel_runtime_pm_put(dev_priv);
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b97ed0cd4ca9..2124a795d10c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,6 +610,8 @@ struct i915_psr {
bool psr2_enabled;
u8 sink_sync_latency;
bool debug;
+   ktime_t last_entry_attempt;
+   ktime_t last_exit;
 
void (*enable_source)(struct intel_dp *,
  const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 56ff2d7691a1..a11a6d940203 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -131,6 +131,7 @@ void intel_psr_irq_handler(struct drm_i915_private 
*dev_priv, u32 psr_iir)
 {
u32 transcoders = BIT(TRANSCODER_EDP);
enum transcoder cpu_transcoder;
+   ktime_t time_ns =  ktime_get();
 
if (INTEL_GEN(dev_priv) >= 8)
transcoders |= BIT(TRANSCODER_A) |
@@ -143,13 +144,17 @@ void intel_psr_irq_handler(struct drm_i915_private 
*dev_priv, u32 psr_iir)
DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
  transcoder_name(cpu_transcoder));
 
-   if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder))
+   if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+   dev_priv->psr.last_entry_attempt = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 
vblanks\n",
  transcoder_name(cpu_transcoder));
+   }
 
-   if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder))
+   if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+   dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
  transcoder_name(cpu_transcoder));
+   }
}
 }
 
-- 
2.14.1

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[Intel-gfx] [PATCH v3 2/4] drm/i915: Enable edp psr error interrupts on bdw+

[Dhinakaran Pandiyan]

From: Ville Syrjälä 

Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr on
any transcoder in theory, though the we don't currenty enable PSR except
on the EDP transcoder.

v2: From DK
 * Rebased on drm-tip
v3: Switched author to Ville based on IRC discussion.

Cc: Rodrigo Vivi 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_irq.c  | 57 
 drivers/gpu/drm/i915/i915_reg.h  |  7 +++--
 drivers/gpu/drm/i915/intel_display.h |  4 +++
 3 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c2d3f30778ee..8a894adf2ca1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2394,20 +2394,34 @@ static void ilk_display_irq_handler(struct 
drm_i915_private *dev_priv,
 static void hsw_edp_psr_irq_handler(struct drm_i915_private *dev_priv)
 {
u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
+   u32 edp_psr_imr = I915_READ(EDP_PSR_IMR);
+   u32 mask = BIT(TRANSCODER_EDP);
+   enum transcoder cpu_transcoder;
 
-   if (edp_psr_iir & EDP_PSR_ERROR)
-   DRM_DEBUG_KMS("PSR error\n");
-
-   if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
-   DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
-   I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
-   }
+   if (INTEL_GEN(dev_priv) >= 8)
+   mask |= BIT(TRANSCODER_A) |
+   BIT(TRANSCODER_B) |
+   BIT(TRANSCODER_C);
+
+   for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, mask) {
+   if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder))
+   DRM_DEBUG_KMS("Transcoder %s PSR error\n",
+ transcoder_name(cpu_transcoder));
+
+   if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+   DRM_DEBUG_KMS("Transcoder %s PSR prepare entry in 2 
vblanks\n",
+ transcoder_name(cpu_transcoder));
+   edp_psr_imr |= EDP_PSR_PRE_ENTRY(cpu_transcoder);
+   }
 
-   if (edp_psr_iir & EDP_PSR_POST_EXIT) {
-   DRM_DEBUG_KMS("PSR exit completed\n");
-   I915_WRITE(EDP_PSR_IMR, 0);
+   if (edp_psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+   DRM_DEBUG_KMS("Transcoder %s PSR exit completed\n",
+ transcoder_name(cpu_transcoder));
+   edp_psr_imr &= ~EDP_PSR_PRE_ENTRY(cpu_transcoder);
+   }
}
 
+   I915_WRITE(EDP_PSR_IMR, edp_psr_imr);
I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
 }
 
@@ -2555,11 +2569,22 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
if (master_ctl & GEN8_DE_MISC_IRQ) {
iir = I915_READ(GEN8_DE_MISC_IIR);
if (iir) {
+   bool found = false;
+
I915_WRITE(GEN8_DE_MISC_IIR, iir);
ret = IRQ_HANDLED;
-   if (iir & GEN8_DE_MISC_GSE)
+
+   if (iir & GEN8_DE_MISC_GSE) {
intel_opregion_asle_intr(dev_priv);
-   else
+   found = true;
+   }
+
+   if (iir & GEN8_DE_EDP_PSR) {
+   hsw_edp_psr_irq_handler(dev_priv);
+   found = true;
+   }
+
+   if (!found)
DRM_ERROR("Unexpected DE Misc interrupt\n");
}
else
@@ -3326,6 +3351,9 @@ static void gen8_irq_reset(struct drm_device *dev)
 
gen8_gt_irq_reset(dev_priv);
 
+   I915_WRITE(EDP_PSR_IMR, 0x);
+   I915_WRITE(EDP_PSR_IIR, 0x);
+
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
   POWER_DOMAIN_PIPE(pipe)))
@@ -3815,7 +3843,7 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
uint32_t de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
u32 de_port_enables;
-   u32 de_misc_masked = GEN8_DE_MISC_GSE;
+   u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
enum pipe pipe;
 
if (INTEL_GEN(dev_priv) >= 9) {
@@ -3840,6 +3868,9 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
 
+   gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
+   I915_WRITE(EDP_PSR_IMR, 0);
+

[Intel-gfx] [PATCH v3 1/4] drm/i915: Enable edp psr error interrupts on hsw

[Dhinakaran Pandiyan]

From: Daniel Vetter 

The definitions for the error register should be valid on bdw/skl too,
but there we haven't even enabled DE_MISC handling yet.

Somewhat confusing the the moved register offset on bdw is only for
the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
on bdw.

v2: Fixes from Ville.

v3: From DK
 * Rebased on drm-tip
 * Removed BDW IIR bit definition, looks like an unintentional change that
should be in the following patch.

v4: From DK
 * Don't mask REG_WRITE.

Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Cc: Daniel Vetter 
Signed-off-by: Daniel Vetter 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_irq.c | 34 ++
 drivers/gpu/drm/i915/i915_reg.h |  8 
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27aee25429b7..c2d3f30778ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct 
drm_i915_private *dev_priv,
ironlake_rps_change_irq_handler(dev_priv);
 }
 
+static void hsw_edp_psr_irq_handler(struct drm_i915_private *dev_priv)
+{
+   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
+
+   if (edp_psr_iir & EDP_PSR_ERROR)
+   DRM_DEBUG_KMS("PSR error\n");
+
+   if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
+   DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
+   I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
+   }
+
+   if (edp_psr_iir & EDP_PSR_POST_EXIT) {
+   DRM_DEBUG_KMS("PSR exit completed\n");
+   I915_WRITE(EDP_PSR_IMR, 0);
+   }
+
+   I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
+}
+
 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
u32 de_iir)
 {
@@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct 
drm_i915_private *dev_priv,
if (de_iir & DE_ERR_INT_IVB)
ivb_err_int_handler(dev_priv);
 
+   if (de_iir & DE_EDP_PSR_INT_HSW)
+   hsw_edp_psr_irq_handler(dev_priv);
+
if (de_iir & DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev_priv);
 
@@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct drm_device *dev)
if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0x);
 
+   if (IS_HASWELL(dev_priv)) {
+   I915_WRITE(EDP_PSR_IMR, 0x);
+   I915_WRITE(EDP_PSR_IIR, 0x);
+   }
+
gen5_gt_irq_reset(dev_priv);
 
ibx_irq_reset(dev_priv);
@@ -3671,6 +3699,12 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
  DE_DP_A_HOTPLUG);
}
 
+   if (IS_HASWELL(dev_priv)) {
+   gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
+   I915_WRITE(EDP_PSR_IMR, 0);
+   display_mask |= DE_EDP_PSR_INT_HSW;
+   }
+
dev_priv->irq_mask = ~display_mask;
 
ibx_irq_pre_postinstall(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6554f4..f5783d6db614 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4011,6 +4011,13 @@ enum {
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
+/* Bspec claims those aren't shifted but stay at 0x64800 */
+#define EDP_PSR_IMR_MMIO(0x64834)
+#define EDP_PSR_IIR_MMIO(0x64838)
+#define   EDP_PSR_ERROR(1<<2)
+#define   EDP_PSR_POST_EXIT(1<<1)
+#define   EDP_PSR_PRE_ENTRY(1<<0)
+
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK(3 << 26)
 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK(0x1f << 20)
@@ -6820,6 +6827,7 @@ enum {
 #define DE_PCH_EVENT_IVB   (1<<28)
 #define DE_DP_A_HOTPLUG_IVB(1<<27)
 #define DE_AUX_CHANNEL_A_IVB   (1<<26)
+#define DE_EDP_PSR_INT_HSW (1<<19)
 #define DE_SPRITEC_FLIP_DONE_IVB   (1<<14)
 #define DE_PLANEC_FLIP_DONE_IVB(1<<13)
 #define DE_PIPEC_VBLANK_IVB(1<<10)
-- 
2.14.1

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Re: [Intel-gfx] [PATCH v3 08/40] misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

>> drivers/misc/mei/hdcp/mei_hdcp.c:52:5: error: redefinition of 
>> 'mei_initiate_hdcp2_session'
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:122:5: note: previous definition of 
'mei_initiate_hdcp2_session' was here
int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
^~
   drivers/misc/mei/hdcp/mei_hdcp.c:117:5: error: redefinition of 
'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:113:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   drivers/misc/mei/hdcp/mei_hdcp.c:123:5: error: redefinition of 
'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:117:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:117:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:113:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_initiate_hdcp2_session +52 drivers/misc/mei/hdcp/mei_hdcp.c

41  
42  /**
43   * mei_initiate_hdcp2_session:
44   *  Function to start a Wired HDCP2.2 Tx Session with ME FW
45   *
46   * @cldev   : Pointer for mei client device
47   * @data: Intel HW specific Data
48   * @ake_data: ptr to store AKE_Init
49   *
50   * Returns 0 on Success, <0 on Failure.
51   */
  > 52  int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
53 struct mei_hdcp_data *data,
54 struct hdcp2_ake_init *ake_data)
55  {
56  struct wired_cmd_initiate_hdcp2_session_in session_init_in = { 
{ 0 } };
57  struct wired_cmd_initiate_hdcp2_session_out
58  session_init_out = { { 
0 } };
59  struct device *dev;
60  ssize_t byte;
61  
62  if (!data || !ake_data)
63  return -EINVAL;
64  
65  dev = >dev;
66  
67  session_init_in.header.api_version = HDCP_API_VERSION;
68  session_init_in.header.command_id = 
WIRED_INITIATE_HDCP2_SESSION;
69  session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
70  session_init_in.header.buffer_len =
71  
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
72  
73  session_init_in.port.integrated_port_type = data->port_type;
74  session_init_in.port.physical_port = data->port;
75  session_init_in.protocol = (uint8_t)data->protocol;
76  
77  byte = mei_cldev_send(cldev, (u8 *)_init_in,
78sizeof(session_init_in));
79  if (byte < 0) {
80  dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
81  return byte;
82  }
83  
84  byte = mei_cldev_recv(cldev, (u8 *)_init_out,
85sizeof(session_init_out));
86  if (byte < 0) {
87  dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
88  return byte;
89  }
90  
91  if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
92  dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n&quo

Re: [Intel-gfx] [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a1-201813 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   drivers/gpu//drm/i915/intel_dp.c: In function 
'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu//drm/i915/intel_dp.c:5377:3: warning: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t' [-Wformat=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
  ^
   In file included from drivers/gpu//drm/i915/intel_dp.c:34:0:
   drivers/gpu//drm/i915/intel_dp.c: At top level:
   include/linux/mei_hdcp.h:144:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   include/linux/mei_hdcp.h:148:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 3 include/linux/string.h:memset
   Cyclomatic Complexity 4 include/linux/string.h:memcpy
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 3 include/linux/log2.h:is_power_of_2
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_read
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_set
   Cyclomatic Complexity 1 include/asm-generic/atomic-long.h:atomic_long_read
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 include/linux/mutex.h:__mutex_owner
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/kasan.h:kasan_kmalloc
   Cyclomatic Complexity 28 include/linux/slab.h:kmalloc_index
   Cyclomatic Complexity 1 include/linux/slab.h:kmem_cache_alloc_trace
   Cyclomatic Complexity 1 include/linux/slab.h:kmalloc_order_trace
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 5 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 1 
include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_max_lane_count
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_enhanced_frame_cap
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_is_branch
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_has_quirk
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_equal
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_valid
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_utils.h:onoff
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/i915_drv.h:msecs_to_jiffies_timeout
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_drv.h:intel_get_crtc_for_pipe
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_crtc_has_type
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_drv.h:intel_crtc_has_dp_encoder
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_drv.h:intel_dp_unused_lane_mask
   Cyclomatic Complexity 3 
drivers/gpu//drm/i915/intel_dp.c:intel_dp_rate_limit_len
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_dp.c:intel_dp_common_len_rate_limit
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_dp.c:intel_dp_max_common_rate
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:intel_dp_rate_index
   Cyc

Re: [Intel-gfx] [PATCH v3 05/40] misc/mei/hdcp: Notifier chain for mei cldev state change

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

>> drivers/misc/mei/hdcp/mei_hdcp.c:49:5: error: redefinition of 
>> 'mei_cldev_register_notify'
int mei_cldev_register_notify(struct notifier_block *nb)
^
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:39:12: note: previous definition of 
'mei_cldev_register_notify' was here
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
>> drivers/misc/mei/hdcp/mei_hdcp.c:55:5: error: redefinition of 
>> 'mei_cldev_unregister_notify'
int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
   In file included from drivers/misc/mei/hdcp/mei_hdcp.c:35:0:
   include/linux/mei_hdcp.h:43:12: note: previous definition of 
'mei_cldev_unregister_notify' was here
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:43:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
   include/linux/mei_hdcp.h:39:12: warning: 'mei_cldev_register_notify' defined 
but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +/mei_cldev_register_notify +49 drivers/misc/mei/hdcp/mei_hdcp.c

48  
  > 49  int mei_cldev_register_notify(struct notifier_block *nb)
50  {
51  return 
blocking_notifier_chain_register(_cldev_notifier_list, nb);
52  }
53  EXPORT_SYMBOL_GPL(mei_cldev_register_notify);
54  
  > 55  int mei_cldev_unregister_notify(struct notifier_block *nb)
56  {
57  return 
blocking_notifier_chain_unregister(_cldev_notifier_list, nb);
58  }
59  EXPORT_SYMBOL_GPL(mei_cldev_unregister_notify);
60  

---
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Re: [Intel-gfx] [PATCH v3 20/40] drm/i915: Define HDCP2.2 related variables

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x001-201813 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu//drm/i915/intel_drv.h:32:0,
from drivers/gpu//drm/i915/i915_trace.h:11,
from drivers/gpu//drm/i915/i915_drv.h:2919,
from drivers/gpu//drm/i915/i915_drv.c:49:
>> include/linux/mei_hdcp.h:148:12: error: 'mei_cldev_unregister_notify' 
>> defined but not used [-Werror=unused-function]
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
>> include/linux/mei_hdcp.h:144:12: error: 'mei_cldev_register_notify' defined 
>> but not used [-Werror=unused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^
   cc1: all warnings being treated as errors

vim +/mei_cldev_unregister_notify +148 include/linux/mei_hdcp.h

3ce9e24eb Ramalingam C 2018-04-03  105  
ca998fc38 Ramalingam C 2018-04-03  106  #ifdef CONFIG_INTEL_MEI_HDCP
ca998fc38 Ramalingam C 2018-04-03  107  int mei_cldev_register_notify(struct 
notifier_block *nb);
ca998fc38 Ramalingam C 2018-04-03  108  int mei_cldev_unregister_notify(struct 
notifier_block *nb);
5240fee41 Ramalingam C 2018-04-03  109  int mei_initiate_hdcp2_session(struct 
mei_cl_device *cldev,
5240fee41 Ramalingam C 2018-04-03  110 struct 
mei_hdcp_data *data,
5240fee41 Ramalingam C 2018-04-03  111 struct 
hdcp2_ake_init *ake_data);
e33886f53 Ramalingam C 2018-04-03  112  int
e33886f53 Ramalingam C 2018-04-03  113  
mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
e33886f53 Ramalingam C 2018-04-03  114  
struct mei_hdcp_data *data,
e33886f53 Ramalingam C 2018-04-03  115  
struct hdcp2_ake_send_cert *rx_cert,
e33886f53 Ramalingam C 2018-04-03  116  
bool *km_stored,
e33886f53 Ramalingam C 2018-04-03  117  
struct hdcp2_ake_no_stored_km *ek_pub_km,
e33886f53 Ramalingam C 2018-04-03  118  
size_t *msg_sz);
a27b68fb5 Ramalingam C 2018-04-03  119  int mei_verify_hprime(struct 
mei_cl_device *cldev, struct mei_hdcp_data *data,
a27b68fb5 Ramalingam C 2018-04-03  120struct 
hdcp2_ake_send_hprime *rx_hprime);
dc86bde43 Ramalingam C 2018-04-03  121  int mei_store_pairing_info(struct 
mei_cl_device *cldev,
dc86bde43 Ramalingam C 2018-04-03  122 struct 
mei_hdcp_data *data,
dc86bde43 Ramalingam C 2018-04-03  123 struct 
hdcp2_ake_send_pairing_info *pairing_info);
67158470b Ramalingam C 2018-04-03  124  int mei_initiate_locality_check(struct 
mei_cl_device *cldev,
67158470b Ramalingam C 2018-04-03  125  struct 
mei_hdcp_data *data,
67158470b Ramalingam C 2018-04-03  126  struct 
hdcp2_lc_init *lc_init_data);
b10099c9a Ramalingam C 2018-04-03  127  int mei_verify_lprime(struct 
mei_cl_device *cldev, struct mei_hdcp_data *data,
b10099c9a Ramalingam C 2018-04-03  128struct 
hdcp2_lc_send_lprime *rx_lprime);
931c35709 Ramalingam C 2018-04-03  129  int mei_get_session_key(struct 
mei_cl_device *cldev, struct mei_hdcp_data *data,
931c35709 Ramalingam C 2018-04-03  130  struct 
hdcp2_ske_send_eks *ske_data);
654828e8b Ramalingam C 2018-04-03  131  int
654828e8b Ramalingam C 2018-04-03  132  
mei_repeater_check_flow_prepare_ack(struct mei_cl_device *cldev,
654828e8b Ramalingam C 2018-04-03  133  
struct mei_hdcp_data *data,
654828e8b Ramalingam C 2018-04-03  134  
struct hdcp2_rep_send_receiverid_list
654828e8b Ramalingam C 2018-04-03  135  
*rep_topology,
654828e8b Ramalingam C 2018-04-03  136  
struct hdcp2_rep_send_ack *rep_send_ack);
315c37225 Ramalingam C 2018-04-03  137  int mei_verify_mprime(struct 
mei_cl_device *cldev, struct mei_hdcp_data *data,
315c37225 Ramalingam C 2018-04-03  138struct 
hdcp2_rep_stream_ready *stream_ready);
702a0ad13 Ram

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Store preemption capability in engine->flags (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Store preemption capability in engine->flags (rev2)
URL   : https://patchwork.freedesktop.org/series/40982/
State : success

== Summary ==

 Possible new issues:

Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip   -> PASS   (shard-snb)
Subgroup fbc-stridechange:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-rgb565-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-pri-indfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
fail   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb565-draw-mmap-wc:
fail   -> PASS   (shard-apl) fdo#103167 +1
Test kms_mmap_write_crc:
dmesg-warn -> PASS   (shard-hsw) fdo#103286
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
pass   -> FAIL   (shard-snb) fdo#103166
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3498 pass:1835 dwarn:1   dfail:0   fail:7   skip:1655 
time:12948s
shard-hswtotal:3498 pass:1783 dwarn:1   dfail:0   fail:3   skip:1710 
time:11469s
shard-snbtotal:3498 pass:1376 dwarn:1   dfail:0   fail:3   skip:2118 
time:7096s
Blacklisted hosts:
shard-kbltotal:3443 pass:1928 dwarn:1   dfail:1   fail:7   skip:1505 
time:9165s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8573/shards.html
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Re: [Intel-gfx] [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180403]
[cannot apply to v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180404-031743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x071-201813 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
from include/drm/drmP.h:73,
from drivers/gpu/drm/i915/intel_dp.c:36:
   drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu/drm/i915/intel_dp.c:5377:13: warning: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t {aka int}' 
>> [-Wformat=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
^
   include/drm/drm_print.h:239:10: note: in definition of macro 'DRM_ERROR'
 drm_err(fmt, ##__VA_ARGS__)
 ^~~
   In file included from drivers/gpu/drm/i915/intel_dp.c:34:0:
   At top level:
   include/linux/mei_hdcp.h:148:12: warning: 'mei_cldev_unregister_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_unregister_notify(struct notifier_block *nb)
   ^~~
   include/linux/mei_hdcp.h:144:12: warning: 'mei_cldev_register_notify' 
defined but not used [-Wunused-function]
static int mei_cldev_register_notify(struct notifier_block *nb)
   ^

vim +5377 drivers/gpu/drm/i915/intel_dp.c

  5366  
  5367  static inline
  5368  int intel_dp_hdcp2_read_rx_status(struct intel_digital_port 
*intel_dig_port,
  5369uint8_t *rx_status)
  5370  {
  5371  ssize_t ret;
  5372  
  5373  ret = drm_dp_dpcd_read(_dig_port->dp.aux,
  5374 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, 
rx_status,
  5375 HDCP_2_2_DP_RXSTATUS_LEN);
  5376  if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
> 5377  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", 
> ret);
  5378  return ret >= 0 ? -EIO : ret;
  5379  }
  5380  
  5381  return 0;
  5382  }
  5383  

---
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: WARN if we hit a signal from kernel context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: WARN if we hit a signal from kernel context (rev2)
URL   : https://patchwork.freedesktop.org/series/41082/
State : warning

== Summary ==

 Possible new issues:

Test gem_persistent_relocs:
Subgroup forked-interruptible:
pass   -> DMESG-WARN (shard-apl)
Subgroup forked-interruptible-faulting-reloc:
pass   -> DMESG-WARN (shard-apl)
pass   -> DMESG-WARN (shard-hsw)
Subgroup forked-interruptible-faulting-reloc-thrash-inactive:
pass   -> DMESG-WARN (shard-apl)
pass   -> DMESG-WARN (shard-hsw)
Subgroup forked-interruptible-faulting-reloc-thrashing:
pass   -> DMESG-WARN (shard-apl)
pass   -> DMESG-WARN (shard-hsw)
pass   -> DMESG-WARN (shard-snb)
Subgroup forked-interruptible-thrash-inactive:
pass   -> DMESG-WARN (shard-apl)
pass   -> DMESG-WARN (shard-hsw)
pass   -> DMESG-WARN (shard-snb)
Subgroup forked-interruptible-thrashing:
pass   -> DMESG-WARN (shard-apl)
pass   -> DMESG-WARN (shard-hsw)
pass   -> DMESG-WARN (shard-snb)
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip   -> PASS   (shard-snb)
Subgroup fbc-stridechange:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-rgb565-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-pri-indfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
fail   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887 +1
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167 +1
Test kms_mmap_write_crc:
dmesg-warn -> PASS   (shard-hsw) fdo#103286
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3498 pass:1828 dwarn:7   dfail:0   fail:7   skip:1655 
time:12985s
shard-hswtotal:3498 pass:1777 dwarn:6   dfail:0   fail:4   skip:1710 
time:11502s
shard-snbtotal:3498 pass:1374 dwarn:4   dfail:0   fail:2   skip:2118 
time:7101s
Blacklisted hosts:
shard-kbltotal:3443 pass:1925 dwarn:5   dfail:0   fail:7   skip:1505 
time:9180s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8572/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Store preemption capability in engine->flags (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Store preemption capability in engine->flags (rev2)
URL   : https://patchwork.freedesktop.org/series/40982/
State : success

== Summary ==

Series 40982v2 drm/i915: Store preemption capability in engine->flags
https://patchwork.freedesktop.org/api/1.0/series/40982/revisions/2/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-cfl-s3) fdo#104056
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail   -> PASS   (fi-skl-6700k2) fdo#103191

fdo#104056 https://bugs.freedesktop.org/show_bug.cgi?id=104056
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:439s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-cfl-s3total:285  pass:258  dwarn:1   dfail:0   fail:0   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:417s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:320s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:672s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:503s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:563s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:530s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s

29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC 
integration manifest
68cff338df15 drm/i915: Store preemption capability in engine->flags

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8573/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev5)

[Patchwork]

== Series Details ==

Series: HDCP1.4 fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/38978/
State : success

== Summary ==

 Possible new issues:

Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip   -> PASS   (shard-snb)
Subgroup fbc-stridechange:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-rgb565-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-pri-indfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Test kms_universal_plane:
Subgroup universal-plane-pipe-a-sanity:
fail   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167 +1
Test kms_mmap_write_crc:
dmesg-warn -> PASS   (shard-hsw) fdo#103286
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
pass   -> FAIL   (shard-snb) fdo#103166

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103286 https://bugs.freedesktop.org/show_bug.cgi?id=103286
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166

shard-apltotal:3498 pass:1834 dwarn:1   dfail:0   fail:7   skip:1655 
time:12960s
shard-hswtotal:3498 pass:1785 dwarn:1   dfail:0   fail:1   skip:1710 
time:11534s
shard-snbtotal:3498 pass:1376 dwarn:1   dfail:0   fail:3   skip:2118 
time:7086s
Blacklisted hosts:
shard-kbltotal:3443 pass:1929 dwarn:1   dfail:1   fail:7   skip:1504 
time:9124s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8570/shards.html
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: WARN if we hit a signal from kernel context (rev2)

[Chris Wilson]

Quoting Patchwork (2018-04-03 19:38:40)
> == Series Details ==
> 
> Series: drm/i915: WARN if we hit a signal from kernel context (rev2)
> URL   : https://patchwork.freedesktop.org/series/41082/
> State : success
> 
> == Summary ==
> 
> Series 41082v2 drm/i915: WARN if we hit a signal from kernel context
> https://patchwork.freedesktop.org/api/1.0/series/41082/revisions/2/mbox/
> 
>  Known issues:
> 
> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
> Test kms_pipe_crc_basic:
> Subgroup hang-read-crc-pipe-c:
> fail   -> PASS   (fi-skl-6700k2) fdo#103191
> 
> fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
> fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
> 
> fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
> time:432s
> fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
> time:443s
> fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
> time:382s
> fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
> time:537s
> fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
> time:299s
> fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
> time:519s
> fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
> time:514s
> fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
> time:526s
> fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
> time:508s
> fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
> time:408s
> fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
> time:559s
> fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
> time:510s
> fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
> time:588s
> fi-elk-e7500 total:285  pass:224  dwarn:2   dfail:0   fail:0   skip:59  
> time:423s
> fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
> time:313s
> fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
> time:543s
> fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
> time:402s
> fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
> time:430s
> fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
> time:467s
> fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
> time:429s
> fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
> time:473s
> fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
> time:459s
> fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
> time:509s
> fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
> time:665s
> fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
> time:441s
> fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
> time:532s
> fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
> time:503s
> fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
> time:497s
> fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
> time:430s
> fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
> time:446s
> fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
> time:588s
> fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
> time:398s
> Blacklisted hosts:
> fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
> time:523s
> fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
> time:484s
> 
> 29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s 
> UTC integration manifest
> 92d026855039 drm/i915: WARN if we hit a signal from kernel context
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8572/issues.html

Is the CI reporter feeling ok? gem_mmap_gtt tripped over the
WARN_ON on *all* machines.

I think it's an internal -EIO and not the case Daniel was looking for.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: WARN if we hit a signal from kernel context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: WARN if we hit a signal from kernel context (rev2)
URL   : https://patchwork.freedesktop.org/series/41082/
State : success

== Summary ==

Series 41082v2 drm/i915: WARN if we hit a signal from kernel context
https://patchwork.freedesktop.org/api/1.0/series/41082/revisions/2/mbox/

 Known issues:

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail   -> PASS   (fi-skl-6700k2) fdo#103191

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:519s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:526s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:588s
fi-elk-e7500 total:285  pass:224  dwarn:2   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:313s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:467s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:665s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:441s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:497s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:588s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:523s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:484s

29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC 
integration manifest
92d026855039 drm/i915: WARN if we hit a signal from kernel context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8572/issues.html
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[Intel-gfx] [PATCH v2] drm/i915: Store preemption capability in engine->flags

[Chris Wilson]

Let's avoid having to delve down the pointer chain to see if the i915
device has support for preemption and store that on the engine, which
made the decision in the first place!

v2: Refactor common preemption policy between execlists/guc.

Signed-off-by: Chris Wilson 
Cc: Tomasz Lis 
Cc: Daniele Ceraolo Spurio 
Cc: Michał Winiarski 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 16 +---
 drivers/gpu/drm/i915/intel_lrc.c|  7 +--
 drivers/gpu/drm/i915/intel_ringbuffer.h | 19 +--
 3 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 749f27916a02..97121230656c 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -657,6 +657,16 @@ static void port_assign(struct execlist_port *port, struct 
i915_request *rq)
port_set(port, i915_request_get(rq));
 }
 
+static inline int rq_prio(const struct i915_request *rq)
+{
+   return rq->priotree.priority;
+}
+
+static inline int port_prio(const struct execlist_port *port)
+{
+   return rq_prio(port_request(port));
+}
+
 static void guc_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
@@ -672,12 +682,12 @@ static void guc_dequeue(struct intel_engine_cs *engine)
GEM_BUG_ON(rb_first(>queue) != rb);
 
if (port_isset(port)) {
-   if (engine->i915->preempt_context) {
+   if (intel_engine_has_preemption(engine)) {
struct guc_preempt_work *preempt_work =
>i915->guc.preempt_work[engine->id];
+   int prio = execlists->queue_priority;
 
-   if (execlists->queue_priority >
-   max(port_request(port)->priotree.priority, 0)) {
+   if (__execlists_need_preempt(prio, port_prio(port))) {
execlists_set_active(execlists,
 EXECLISTS_ACTIVE_PREEMPT);
queue_work(engine->i915->guc.preempt_wq,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4d08875422b6..88472845ce96 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -183,7 +183,8 @@ static inline bool need_preempt(const struct 
intel_engine_cs *engine,
const struct i915_request *last,
int prio)
 {
-   return engine->i915->preempt_context && prio > max(rq_prio(last), 0);
+   return (intel_engine_has_preemption(engine) &&
+   __execlists_need_preempt(prio, rq_prio(last)));
 }
 
 /**
@@ -2117,11 +2118,13 @@ static void execlists_set_default_submission(struct 
intel_engine_cs *engine)
engine->unpark = NULL;
 
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
+   if (engine->i915->preempt_context)
+   engine->flags |= I915_ENGINE_HAS_PREEMPTION;
 
engine->i915->caps.scheduler =
I915_SCHEDULER_CAP_ENABLED |
I915_SCHEDULER_CAP_PRIORITY;
-   if (engine->i915->preempt_context)
+   if (intel_engine_has_preemption(engine))
engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 40461e29cdab..5dfb15fdfd0c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -562,6 +562,7 @@ struct intel_engine_cs {
 
 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
 #define I915_ENGINE_SUPPORTS_STATS   BIT(1)
+#define I915_ENGINE_HAS_PREEMPTION   BIT(2)
unsigned int flags;
 
/*
@@ -621,16 +622,30 @@ struct intel_engine_cs {
} stats;
 };
 
-static inline bool intel_engine_needs_cmd_parser(struct intel_engine_cs 
*engine)
+static inline bool
+intel_engine_needs_cmd_parser(const struct intel_engine_cs *engine)
 {
return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
 }
 
-static inline bool intel_engine_supports_stats(struct intel_engine_cs *engine)
+static inline bool
+intel_engine_supports_stats(const struct intel_engine_cs *engine)
 {
return engine->flags & I915_ENGINE_SUPPORTS_STATS;
 }
 
+static inline bool
+intel_engine_has_preemption(const struct intel_engine_cs *engine)
+{
+   return engine->flags & I915_ENGINE_HAS_PREEMPTION;
+}
+
+static inline bool
+__execlists_need_preempt(int prio, int last)
+{
+   return prio > max(0, last);
+}
+
 static inline void
 execlists_set_active(struct intel_engine_execlists *execlists,
 unsigned int bit)
-- 
2.16.3

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing

[Antonio Argenziano]

On 03/04/18 11:24, Antonio Argenziano wrote:



On 03/04/18 04:36, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Reset and unwedge stress testing is supposed to trigger wedging or resets
at incovenient times and then re-use the context so either the context or
driver tracking might get confused and break.

v2:
  * Renamed for more sensible naming.
  * Added some comments to explain what the test is doing. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
  tests/gem_eio.c | 74 
+

  1 file changed, 74 insertions(+)

diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b7c5047f0816..9599e73db736 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -591,6 +591,74 @@ static void test_inflight_internal(int fd, 
unsigned int wait)

  close(fd);
  }
+/*
+ * Verify that we can submit and execute work after unwedging the GPU.
+ */
+static void test_reset_stress(int fd, unsigned int flags)
+{
+    uint32_t ctx0 = gem_context_create(fd);
+
+    igt_until_timeout(5) {
+    struct drm_i915_gem_execbuffer2 execbuf = { };
+    struct drm_i915_gem_exec_object2 obj = { };
+    uint32_t bbe = MI_BATCH_BUFFER_END;
+    igt_spin_t *hang;
+    unsigned int i;
+    uint32_t ctx;
+
+    gem_quiescent_gpu(fd);
+
+    igt_require(i915_reset_control(flags & TEST_WEDGE ?
+   false : true));
+
+    ctx = context_create_safe(fd);
+
+    /*
+ * Start executing a spin batch with some queued batches
+ * against a different context after it.
+ */


Aren't all batches queued on ctx0? Or is this a reference to the check 
on ctx you have later in the test.


Thanks,
Antonio


+    hang = spin_sync(fd, ctx0, 0);


I think you meant to send this^ on ctx.

Antonio.


+
+    obj.handle = gem_create(fd, 4096);
+    gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+    execbuf.buffers_ptr = to_user_pointer();
+    execbuf.buffer_count = 1;
+    execbuf.rsvd1 = ctx0;
+
+    for (i = 0; i < 10; i++)
+    gem_execbuf(fd, );
+
+    /* Wedge after a small delay. */
+    igt_assert_eq(__check_wait(fd, obj.handle, 100e3), 0);
+
+    /* Unwedge by forcing a reset. */
+    igt_assert(i915_reset_control(true));
+    trigger_reset(fd);
+
+    gem_quiescent_gpu(fd);
+
+    /*
+ * Verify that we are able to submit work after unwedging from
+ * both contexts.
+ */
+    execbuf.rsvd1 = ctx;
+    for (i = 0; i < 5; i++)
+    gem_execbuf(fd, );
+
+    execbuf.rsvd1 = ctx0;
+    for (i = 0; i < 5; i++)
+    gem_execbuf(fd, );
+
+    gem_sync(fd, obj.handle);
+    igt_spin_batch_free(fd, hang);
+    gem_context_destroy(fd, ctx);
+    gem_close(fd, obj.handle);
+    }
+
+    gem_context_destroy(fd, ctx0);
+}
+
  static int fd = -1;
  static void
@@ -635,6 +703,12 @@ igt_main
  igt_subtest("in-flight-suspend")
  test_inflight_suspend(fd);
+    igt_subtest("reset-stress")
+    test_reset_stress(fd, 0);
+
+    igt_subtest("unwedge-stress")
+    test_reset_stress(fd, TEST_WEDGE);
+
  igt_subtest_group {
  const struct {
  unsigned int wait;


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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing

[Antonio Argenziano]

On 03/04/18 04:36, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Reset and unwedge stress testing is supposed to trigger wedging or resets
at incovenient times and then re-use the context so either the context or
driver tracking might get confused and break.

v2:
  * Renamed for more sensible naming.
  * Added some comments to explain what the test is doing. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
  tests/gem_eio.c | 74 +
  1 file changed, 74 insertions(+)

diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b7c5047f0816..9599e73db736 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -591,6 +591,74 @@ static void test_inflight_internal(int fd, unsigned int 
wait)
close(fd);
  }
  
+/*

+ * Verify that we can submit and execute work after unwedging the GPU.
+ */
+static void test_reset_stress(int fd, unsigned int flags)
+{
+   uint32_t ctx0 = gem_context_create(fd);
+
+   igt_until_timeout(5) {
+   struct drm_i915_gem_execbuffer2 execbuf = { };
+   struct drm_i915_gem_exec_object2 obj = { };
+   uint32_t bbe = MI_BATCH_BUFFER_END;
+   igt_spin_t *hang;
+   unsigned int i;
+   uint32_t ctx;
+
+   gem_quiescent_gpu(fd);
+
+   igt_require(i915_reset_control(flags & TEST_WEDGE ?
+  false : true));
+
+   ctx = context_create_safe(fd);
+
+   /*
+* Start executing a spin batch with some queued batches
+* against a different context after it.
+*/


Aren't all batches queued on ctx0? Or is this a reference to the check 
on ctx you have later in the test.


Thanks,
Antonio


+   hang = spin_sync(fd, ctx0, 0);
+
+   obj.handle = gem_create(fd, 4096);
+   gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.rsvd1 = ctx0;
+
+   for (i = 0; i < 10; i++)
+   gem_execbuf(fd, );
+
+   /* Wedge after a small delay. */
+   igt_assert_eq(__check_wait(fd, obj.handle, 100e3), 0);
+
+   /* Unwedge by forcing a reset. */
+   igt_assert(i915_reset_control(true));
+   trigger_reset(fd);
+
+   gem_quiescent_gpu(fd);
+
+   /*
+* Verify that we are able to submit work after unwedging from
+* both contexts.
+*/
+   execbuf.rsvd1 = ctx;
+   for (i = 0; i < 5; i++)
+   gem_execbuf(fd, );
+
+   execbuf.rsvd1 = ctx0;
+   for (i = 0; i < 5; i++)
+   gem_execbuf(fd, );
+
+   gem_sync(fd, obj.handle);
+   igt_spin_batch_free(fd, hang);
+   gem_context_destroy(fd, ctx);
+   gem_close(fd, obj.handle);
+   }
+
+   gem_context_destroy(fd, ctx0);
+}
+
  static int fd = -1;
  
  static void

@@ -635,6 +703,12 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
  
+	igt_subtest("reset-stress")

+   test_reset_stress(fd, 0);
+
+   igt_subtest("unwedge-stress")
+   test_reset_stress(fd, TEST_WEDGE);
+
igt_subtest_group {
const struct {
unsigned int wait;


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: WARN if we hit a signal from kernel context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: WARN if we hit a signal from kernel context (rev2)
URL   : https://patchwork.freedesktop.org/series/41082/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
92d026855039 drm/i915: WARN if we hit a signal from kernel context
-:44: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break 
or fallthrough comment
#44: FILE: drivers/gpu/drm/i915/i915_gem.c:2024:
+   case 0:

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: WARN if we hit a signal from kernel context

[Patchwork]

== Series Details ==

Series: drm/i915: WARN if we hit a signal from kernel context
URL   : https://patchwork.freedesktop.org/series/41082/
State : warning

== Summary ==

Series 41082v1 drm/i915: WARN if we hit a signal from kernel context
https://patchwork.freedesktop.org/api/1.0/series/41082/revisions/1/mbox/

 Possible new issues:

Test gem_mmap_gtt:
Subgroup basic-read:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-blb-e6850)
pass   -> DMESG-WARN (fi-bsw-n3050)
pass   -> DMESG-WARN (fi-bwr-2160)
pass   -> DMESG-WARN (fi-bxt-dsi)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-cfl-8700k)
pass   -> DMESG-WARN (fi-cfl-s3)
pass   -> DMESG-WARN (fi-cfl-u)
pass   -> DMESG-WARN (fi-cnl-y3)
pass   -> DMESG-WARN (fi-elk-e7500)
pass   -> DMESG-WARN (fi-gdg-551)
pass   -> DMESG-WARN (fi-glk-1)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-ilk-650)
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-kbl-7500u)
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r)
pass   -> DMESG-WARN (fi-pnv-d510)
pass   -> DMESG-WARN (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6600u)
pass   -> DMESG-WARN (fi-skl-6700k2)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> DMESG-WARN (fi-skl-guc)
pass   -> DMESG-WARN (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600)
Subgroup basic-read-no-prefault:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-blb-e6850)
pass   -> DMESG-WARN (fi-bsw-n3050)
pass   -> DMESG-WARN (fi-bwr-2160)
pass   -> DMESG-WARN (fi-bxt-dsi)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-cfl-8700k)
pass   -> DMESG-WARN (fi-cfl-s3)
pass   -> DMESG-WARN (fi-cfl-u)
pass   -> DMESG-WARN (fi-cnl-y3)
pass   -> DMESG-WARN (fi-elk-e7500)
pass   -> DMESG-WARN (fi-gdg-551)
pass   -> DMESG-WARN (fi-glk-1)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-ilk-650)
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-kbl-7500u)
pass   -> DMESG-WARN (fi-kbl-7567u)
pass   -> DMESG-WARN (fi-kbl-r)
pass   -> DMESG-WARN (fi-pnv-d510)
pass   -> DMESG-WARN (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6600u)
pass   -> DMESG-WARN (fi-skl-6700k2)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> DMESG-WARN (fi-skl-guc)
pass   -> DMESG-WARN (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600)
Subgroup basic-write:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-blb-e6850)
pass   -> DMESG-WARN (fi-bsw-n3050)
pass   -> DMESG-WARN (fi-bwr-2160)
pass   -> DMESG-WARN (fi-bxt-dsi)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-cfl-8700k)
pass   -> DMESG-WARN (fi-cfl-s3)
pass   -> DMESG-WARN (fi-cfl-u)
pass   -> DMESG-WARN (fi-cnl-y3)
pass   -> DMESG-WARN (fi-elk-e7500)
pass   -> DMESG-WARN (fi-gdg-551)
pass   -> DMESG-WARN (fi-glk-1)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-ilk-650)
pass 

[Intel-gfx] [PATCH] drm/i915: WARN if we hit a signal from kernel context

[Daniel Vetter]

After a discussion with Wily I got the nagging feeling we might have
some cases of nasty busy loops. The window is fairly small since we
always have a non-faulting fastpath (using page_fault_dis|enable())
first, usually followed by a pile of pending signal checks, before we
go into the slowpath copy_to|from_user that might blow up for real.

Test patch to check what CI thinks of this theory.

v2: Don't WARN on success (Ville).

Cc: Matthew Wilcox 
Cc: Chris Wilson 
Cc: Ville Syrjälä 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_gem.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9650a7b10c5f..9766fa152e05 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1902,6 +1902,7 @@ int i915_gem_fault(struct vm_fault *vmf)
struct i915_vma *vma;
pgoff_t page_offset;
unsigned int flags;
+   bool user_fault = vmf->flags & FAULT_FLAG_USER;
int ret;
 
/* We don't use vmf->pgoff since that has the fake offset */
@@ -2017,9 +2018,10 @@ int i915_gem_fault(struct vm_fault *vmf)
 * handler to reset everything when re-faulting in
 * i915_mutex_lock_interruptible.
 */
-   case 0:
case -ERESTARTSYS:
case -EINTR:
+   WARN_ON(!user_fault);
+   case 0:
case -EBUSY:
/*
 * EBUSY is ok: this just means that another thread
-- 
2.16.2

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Re: [Intel-gfx] [stable:v4.15] drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.

[Pandiyan, Dhinakaran]

On Tue, 2018-04-03 at 19:40 +0200, Greg KH wrote:
> On Tue, Apr 03, 2018 at 10:27:16AM +0300, Jani Nikula wrote:
> > 
> > DK, please start stable backport commit messages with:
> > 
> > commit b1e314462bba76660eec62760bb2e87f28f58866 upstream.
Got it, I'll do that next time onwards since Greg took care of this
patch. Thanks!


> 
> Thank you for that, it helped me figure this out...
> 
> greg k-h

Thanks for fixing up the commit message.

-DK
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Re: [Intel-gfx] [PATCH 04/11] drm/i915/psr: Remove intel_crtc_state parameter from disable()

[Ville Syrjälä]

On Fri, Mar 30, 2018 at 03:23:29PM -0700, José Roberto de Souza wrote:
> It is not necessary as is possible to get the pipe information
> from intel_dp.
> 
> Signed-off-by: José Roberto de Souza 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  3 +--
>  drivers/gpu/drm/i915/intel_psr.c | 13 ++---
>  2 files changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb72ee27422f..99af9169d792 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -612,8 +612,7 @@ struct i915_psr {
>  
>   void (*enable_source)(struct intel_dp *,
> const struct intel_crtc_state *);
> - void (*disable_source)(struct intel_dp *,
> -const struct intel_crtc_state *);
> + void (*disable_source)(struct intel_dp *intel_dp);
>   void (*enable_sink)(struct intel_dp *);
>   void (*activate)(struct intel_dp *);
>   void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index d3451afeb8bb..c4720b0152c3 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -665,24 +665,23 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>   mutex_unlock(_priv->psr.lock);
>  }
>  
> -static void vlv_psr_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *old_crtc_state)
> +static void vlv_psr_disable(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>   struct drm_device *dev = intel_dig_port->base.base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct drm_crtc *crtc = intel_dig_port->base.base.crtc;

That is a legacy pointer that should not be used anymore.

> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>  
>   if (dev_priv->psr.active) {
>   dev_priv->psr.exit(intel_dp, true);
>   dev_priv->psr.active = false;
>   } else {
> - WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
> + WARN_ON(vlv_is_psr_active_on_pipe(dev, pipe));
>   }
>  }
>  
> -static void hsw_psr_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *old_crtc_state)
> +static void hsw_psr_disable(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>   struct drm_device *dev = intel_dig_port->base.base.dev;
> @@ -727,7 +726,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>   return;
>   }
>  
> - dev_priv->psr.disable_source(intel_dp, old_crtc_state);
> + dev_priv->psr.disable_source(intel_dp);
>  
>   /* Disable PSR on Sink */
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> -- 
> 2.16.3
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH] drm/i915: WARN if we hit a signal from kernel context

[Daniel Vetter]

After a discussion with Wily I got the nagging feeling we might have
some cases of nasty busy loops. The window is fairly small since we
always have a non-faulting fastpath (using page_fault_dis|enable())
first, usually followed by a pile of pending signal checks, before we
go into the slowpath copy_to|from_user that might blow up for real.

Test patch to check what CI thinks of this theory.

Cc: Matthew Wilcox 
Cc: Chris Wilson 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9650a7b10c5f..bf4b0ed70fd2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1902,6 +1902,7 @@ int i915_gem_fault(struct vm_fault *vmf)
struct i915_vma *vma;
pgoff_t page_offset;
unsigned int flags;
+   bool user_fault = vmf->flags & FAULT_FLAG_USER;
int ret;
 
/* We don't use vmf->pgoff since that has the fake offset */
@@ -2020,6 +2021,7 @@ int i915_gem_fault(struct vm_fault *vmf)
case 0:
case -ERESTARTSYS:
case -EINTR:
+   WARN_ON(!user_fault);
case -EBUSY:
/*
 * EBUSY is ok: this just means that another thread
-- 
2.16.2

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Re: [Intel-gfx] [stable:v4.15] drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.

[Greg KH]

On Tue, Apr 03, 2018 at 10:27:16AM +0300, Jani Nikula wrote:
> 
> DK, please start stable backport commit messages with:
> 
> commit b1e314462bba76660eec62760bb2e87f28f58866 upstream.

Thank you for that, it helped me figure this out...

greg k-h
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[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev5)

[Patchwork]

== Series Details ==

Series: HDCP1.4 fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/38978/
State : success

== Summary ==

Series 38978v5 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/5/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
fail   -> PASS   (fi-skl-6700k2) fdo#103191

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:384s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:421s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:426s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:478s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:665s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:450s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:569s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:412s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:255  dwarn:3   dfail:0   fail:1   skip:26  
time:517s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:490s

29940f138482ff38047287ad288cea1fcf1f73b4 drm-tip: 2018y-04m-03d-13h-23m-36s UTC 
integration manifest
28f776e9d930 drm/i915: Fix reading downstream dev count
8259d0865458 drm/i915: Check hdcp key loadability
37d83a96d5ff drm/i915: Read Vprime thrice incase of mismatch
3db387dec7ec drm/i915: Read HDCP R0 thrice in case of mismatch

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8570/issues.html
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Re: [Intel-gfx] [PATCH 06/11] drm/i915/psr: Add intel_psr_activate_block_get()/put()

[Rodrigo Vivi]

On Mon, Apr 02, 2018 at 03:11:54PM -0700, Souza, Jose wrote:
> On Mon, 2018-04-02 at 11:20 -0700, Rodrigo Vivi wrote:
> > On Fri, Mar 30, 2018 at 03:23:31PM -0700, José Roberto de Souza
> > wrote:
> > > intel_psr_activate_block_get() should be called when by some reason
> > > PSR should not be activated for some time, it will increment
> > > counter
> > > and it should the decremented by intel_psr_activate_block_put()
> > > when PSR can be activated again.
> > > intel_psr_activate_block_put() will not actually activate PSR,
> > > users
> > > of this function should also call intel_psr_activate().
> > 
> > Ohh cool! you made the counter.
> > probably we will need to change things from mutex to spin locker.
> > But also the blocker functions here could already introduce the
> > function
> > calls to really block and release psr.
> 
> Oh so drop the 'drm/i915/psr: Export intel_psr_activate/exit()' and
> call PSR exit and activate from intel_psr_activate_block_get()/put()?

yeap.

> 
> I dind't understand why you want to change struct mutex lock; to
> spinlock_t?

I'm not sure, but I believe that aux transactions can be called from
atomic areas protected with spin locks... if this assumption is true
than you cannot use any code that can sleep inside these areas, and
mutex can sleep. But in case no aux transaction is getting called
from atomic areas feel free to just ignore me ;)

> 
> > 
> > > 
> > > Signed-off-by: José Roberto de Souza 
> > > Cc: Dhinakaran Pandiyan 
> > > Cc: Rodrigo Vivi 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
> > >  drivers/gpu/drm/i915/intel_drv.h |  2 ++
> > >  drivers/gpu/drm/i915/intel_psr.c | 54
> > > 
> > >  3 files changed, 57 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 99af9169d792..41ebb144594e 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -609,6 +609,7 @@ struct i915_psr {
> > >   bool has_hw_tracking;
> > >   bool psr2_enabled;
> > >   u8 sink_sync_latency;
> > > + unsigned int activate_block_count;
> > >  
> > >   void (*enable_source)(struct intel_dp *,
> > > const struct intel_crtc_state *);
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 70026b772721..020b96324135 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1893,6 +1893,8 @@ void intel_psr_compute_config(struct intel_dp
> > > *intel_dp,
> > > struct intel_crtc_state
> > > *crtc_state);
> > >  void intel_psr_exit(struct intel_dp *intel_dp, bool wait_idle);
> > >  void intel_psr_activate(struct intel_dp *intel_dp, bool schedule);
> > > +void intel_psr_activate_block_get(struct intel_dp *intel_dp);
> > > +void intel_psr_activate_block_put(struct intel_dp *intel_dp);
> > >  
> > >  /* intel_runtime_pm.c */
> > >  int intel_power_domains_init(struct drm_i915_private *);
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 906a12ea934d..8702dbafb42d 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -558,6 +558,8 @@ static void __intel_psr_activate(struct
> > > intel_dp *intel_dp)
> > >  
> > >   WARN_ON(dev_priv->psr.active);
> > >   lockdep_assert_held(_priv->psr.lock);
> > > + if (dev_priv->psr.activate_block_count)
> > > + return;
> > >  
> > >   dev_priv->psr.activate(intel_dp);
> > >   dev_priv->psr.active = true;
> > > @@ -1188,3 +1190,55 @@ void intel_psr_activate(struct intel_dp
> > > *intel_dp, bool schedule)
> > >  out:
> > >   mutex_unlock(_priv->psr.lock);
> > >  }
> > > +
> > > +/**
> > > + * intel_psr_activate_block_get - Block further attempts to
> > > activate PSR
> > > + * @intel_dp: DisplayPort that have PSR enabled
> > > + *
> > > + * It have a internal reference count, so each
> > > intel_psr_activate_block_get()
> > > + * should have a intel_psr_activate_block_put() counterpart.
> > > + */
> > > +void intel_psr_activate_block_get(struct intel_dp *intel_dp)
> > > +{
> > > + struct intel_digital_port *dig_port =
> > > dp_to_dig_port(intel_dp);
> > > + struct drm_device *dev = dig_port->base.base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > +
> > > + if (!CAN_PSR(dev_priv))
> > > + return;
> > > +
> > > + mutex_lock(_priv->psr.lock);
> > > + if (dev_priv->psr.enabled != intel_dp)
> > > + goto out;
> > > +
> > > + dev_priv->psr.activate_block_count++;
> > > +out:
> > > + mutex_unlock(_priv->psr.lock);
> > > +}
> > > +
> > > +
> > > +/**
> > > + * intel_psr_activate_block_put - Unblock further attempts to
> > > activate PSR
> > > + * @intel_dp: DisplayPort that have PSR enabled
> > > + *
> > > + * Decrease the reference counter 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

[Tvrtko Ursulin]

On 03/04/2018 15:06, Eero Tamminen wrote:

Hi,

On 03.04.2018 12:36, Tvrtko Ursulin wrote:

On 29/03/2018 15:30, Eero Tamminen wrote:

I tested this on HSW GT2, BYT, BDW GT3, SKL GT2 and KBL GT3e,
with Ubuntu 16.04 and 17.10, using Ubuntu default kernels (4.4 to 4.13)
and latest drm-tip build (4.16.0-rc7).


General comments


This will be used by our customers and people who aren't necessarily
familiar with i915 internal details.  Therefore it should use
common terminology in the field and in similar tools, instead of
I3As (Intel 3-letter Acronyms).

For example:
  - rcs -> 3D render
  - bcs -> blitter
  - vecs -> video
  - vcs -> video decode
etc.


Done. And I am open to bike-shedding of the names and display format 
for instance reporting.


New names look fine to me!



Old tool showed also GPU system memory interface (GAM) busyness.
That was valuable info, and reasonably accurate for stable loads.

Could this tool show also either that information (preferred), or
bandwidth utilized by GPU/CPU/display?

(Latest kernels offer GPU memory bandwidth usage through perf
"uncore_imc" "data_reads" & "date_writes" counters.)


Excellent suggestion and I've added IMC data_reads and data_writes to 
the tool.


Thanks, it looks fine too.  I'm just wondering about the numbers
it's reporting on SKL GT2...

AFAIK IMC counters are for uncore, so I though that they should
correspond to GTI (memory interface to outside of GPU) read and
write HW counter values.  While it seemed in some cases quite close,
in some cases the it showed a lot smaller (2/3) value than expected.

I can understand why reads are sometimes larger, because I think
uncore will include also display engine display content reads.

However, I don't see how uncore writes could be considerably smaller
than the GTI interface write amount.

(GTI interface reports the expected value which corresponds directly
to what my test application is doing (64x blended FullHD layer writes).)

Idle machine read amounts are also much smaller (60-65MB/s) than what
I think display update read should be (1920*1080*4*60Hz = 475MiB/s).

Any ideas for these two discrepancies?


I'm afraid I am not familiar with the uncore IMC, but we could always 
approach its authors?



Is "wait" value supposed to be IO-wait for given engine interface?

I never saw that change from 0%, although IO-wait in top jumped
from 0 to 20-30% with my test GPU load.


No, that is time spent in MI_WAIT_FOR_EVENT.


Could you add that info to the UI?

E.g. just have "MI" on top of the "wait" column.


Like a full header strip? Yeah makes sense, I'll add it.


 > I think not very used in current codebase.

What you're using to validate that it reports correct value?


That would be igt/tests/perf_pmu/event-wait-rcs0.




HW specific test results


BYT:
* Reports "Failed to initialize PMU!" although old intel_gpu_top
   works fine.

HSW GT2,  BDW GT3, SKL GT2 and KBL GT3e seems to work fine except
for the "wait" value.

I never saw blitter engine to do anything, but that's because
modesetting uses just 3D pipeline, and because I couldn't get
Intel DDX to work with rest of latest git version of X / 3D stack.


Thank you for testing this so thoroughly - this was really invaluable 
since I don't have access too such number of platforms. I've tried to 
fix all this in the latest version.


Machines are currently running tests, I'll check these tomorrow.


Thanks!




Kernel version support
--

My HW specific testing above was with drm-tip kernel, but I did one test
also with Ubuntu 16.04 v4.4 kernel (which includes v4.6 or v4.8 i915 
backport) on KBL.  For that, the tool reported:

"Failed to detect engines!"

Although the previous intel_gpu_top works fine with that kernel version.

Same happens also with Ubuntu 17.04 v4.13 kernel.


-> If new version needs a certain kernel version, it should tell
    which version is required.


Yep, at least 4.16 is needed so I have added this info to the error 
message.


IMHO the message is a bit ambivalent:
 Failed to detect engines! Kernel 4.16 or newer?

I would suggest checking whether kernel is new enough, and if not:
 Kernel X.YY detected, 4.16 or newer required.


Maybe yeah. I was planning to improve error messages altogether but 
forgot. Will see what improvements make sense.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH v3 36/40] drm/i915: Implement gmbus burst read

[Daniel Vetter]

On Tue, Apr 03, 2018 at 07:27:49PM +0530, Ramalingam C wrote:
> Implements a interface for single burst read of data that is larger
> than 512 Bytes through gmbus.
> 
> HDCP2.2 spec expects HDCP2.2 transmitter to read 522Bytes of HDCP
> receiver certificates in single burst read. On gmbus, to read more
> than 511Bytes, HW provides a workaround for burst read.
> 
> This patch passes the burst read request through gmbus read functions.
> And implements the sequence of enabling and disabling the burst read.
> 
> v2:
>   No Changes.
> v3:
>   No Changes.
> 
> Signed-off-by: Ramalingam C 

Why only enable this burst_read mode for hdcp, and not for all i2c
transactions? Seems to unecessarily complicate the code, since it requires
that you pass burst_read through the entire call chain. For other changes
we've done for hdcp (like enabling the read/write mode and other stuff)
we've enabled it for all i2c transactions. That also means more testing,
since it will be used even when HDCP is not in use.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |   2 +
>  drivers/gpu/drm/i915/i915_reg.h  |   3 +
>  drivers/gpu/drm/i915/intel_i2c.c | 124 
> +--
>  3 files changed, 112 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6e740f6fe33f..72534a1e544b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3688,6 +3688,8 @@ extern void intel_teardown_gmbus(struct 
> drm_i915_private *dev_priv);
>  extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>unsigned int pin);
>  extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
> +extern int intel_gmbus_burst_read(struct i2c_adapter *adapter,
> +   unsigned int offset, void *buf, size_t size);
>  
>  extern struct i2c_adapter *
>  intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f04ad3c15abd..56979bc4e9d8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3123,6 +3123,7 @@ enum i915_power_well_id {
>  #define   GMBUS_RATE_400KHZ  (2<<8) /* reserved on Pineview */
>  #define   GMBUS_RATE_1MHZ(3<<8) /* reserved on Pineview */
>  #define   GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
> +#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
>  #define   GMBUS_PIN_DISABLED 0
>  #define   GMBUS_PIN_SSC  1
>  #define   GMBUS_PIN_VGADDC   2
> @@ -3150,8 +3151,10 @@ enum i915_power_well_id {
>  #define   GMBUS_CYCLE_WAIT   (1<<25)
>  #define   GMBUS_CYCLE_INDEX  (2<<25)
>  #define   GMBUS_CYCLE_STOP   (4<<25)
> +#define   GMBUS_CYCLE_MASK   (7<<25)
>  #define   GMBUS_BYTE_COUNT_SHIFT 16
>  #define   GMBUS_BYTE_COUNT_MAX   256U
> +#define   GMBUS_BYTE_COUNT_HW_MAX 511U
>  #define   GMBUS_SLAVE_INDEX_SHIFT 8
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ   (1<<0)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..dcb2be0d54ee 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -364,21 +364,30 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
>  static int
>  gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
> unsigned short addr, u8 *buf, unsigned int len,
> -   u32 gmbus1_index)
> +   u32 gmbus1_index, bool burst_read)
>  {
> + unsigned int size = len;
> + int ret;
> +
> + if (burst_read) {
> + /* Seq to enable Burst Read */
> + I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) |
> +   GMBUS_BYTE_CNT_OVERRIDE));
> + size = GMBUS_BYTE_COUNT_HW_MAX;
> + }
> +
>   I915_WRITE_FW(GMBUS1,
> gmbus1_index |
> GMBUS_CYCLE_WAIT |
> -   (len << GMBUS_BYTE_COUNT_SHIFT) |
> +   (size << GMBUS_BYTE_COUNT_SHIFT) |
> (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> GMBUS_SLAVE_READ | GMBUS_SW_RDY);
>   while (len) {
> - int ret;
>   u32 val, loop = 0;
>  
>   ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
>   if (ret)
> - return ret;
> + goto exit;
>  
>   val = I915_READ_FW(GMBUS3);
>   do {
> @@ -387,12 +396,29 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   } while (--len && ++loop < 4);
>   }
>  
> - return 0;
> +exit:
> + if (burst_read) {
> +
> + /* Seq to disable the Burst Read */
> + I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) &
> +   ~GMBUS_BYTE_CNT_OVERRIDE));
> + 

[Intel-gfx] [PATCH i-g-t v3] tests/perf_pmu: Avoid RT thread for accuracy test

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Realtime scheduling interferes with execlists submission (tasklet) so try
to simplify the PWM loop in a few ways:

 * Drop RT.
 * Longer batches for smaller systematic error.
 * More truthful test duration calculation.
 * Less clock queries.
 * No self-adjust - instead just report the achieved cycle and let the
   parent check against it.
 * Report absolute cycle error.

v2:
 * Bring back self-adjust. (Chris Wilson)
   (But slightly fixed version with no overflow.)

v3:
 * Log average and mean calibration for each pass.

Signed-off-by: Tvrtko Ursulin 
---
 tests/perf_pmu.c | 108 +++
 1 file changed, 53 insertions(+), 55 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 2273ddb9e684..697008c855fd 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1497,12 +1497,6 @@ test_enable_race(int gem_fd, const struct 
intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
 }
 
-static double __error(double val, double ref)
-{
-   igt_assert(ref > 1e-5 /* smallval */);
-   return (100.0 * val / ref) - 100.0;
-}
-
 static void __rearm_spin_batch(igt_spin_t *spin)
 {
const uint32_t mi_arb_chk = 0x5 << 23;
@@ -1525,13 +1519,12 @@ static void
 accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 unsigned long target_busy_pct)
 {
-   const unsigned int min_test_loops = 7;
-   const unsigned long min_test_us = 1e6;
-   unsigned long busy_us = 2500;
+   unsigned long busy_us = 1 - 100 * (1 + abs(50 - target_busy_pct));
unsigned long idle_us = 100 * (busy_us - target_busy_pct *
busy_us / 100) / target_busy_pct;
-   unsigned long pwm_calibration_us;
-   unsigned long test_us;
+   const unsigned long min_test_us = 1e6;
+   const unsigned long pwm_calibration_us = min_test_us;
+   const unsigned long test_us = min_test_us;
double busy_r, expected;
uint64_t val[2];
uint64_t ts[2];
@@ -1546,13 +1539,6 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
idle_us *= 2;
}
 
-   pwm_calibration_us = min_test_loops * (busy_us + idle_us);
-   while (pwm_calibration_us < min_test_us)
-   pwm_calibration_us += busy_us + idle_us;
-   test_us = min_test_loops * (idle_us + busy_us);
-   while (test_us < min_test_us)
-   test_us += busy_us + idle_us;
-
igt_info("calibration=%lums, test=%lums; ratio=%.2f%% (%luus/%luus)\n",
 pwm_calibration_us / 1000, test_us / 1000,
 (double)busy_us / (busy_us + idle_us) * 100.0,
@@ -1565,20 +1551,11 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
 
/* Emit PWM pattern on the engine from a child. */
igt_fork(child, 1) {
-   struct sched_param rt = { .sched_priority = 99 };
const unsigned long timeout[] = {
pwm_calibration_us * 1000, test_us * 1000
};
-   uint64_t total_busy_ns = 0, total_idle_ns = 0;
+   uint64_t total_busy_ns = 0, total_ns = 0;
igt_spin_t *spin;
-   int ret;
-
-   /* We need the best sleep accuracy we can get. */
-   ret = sched_setscheduler(0,
-SCHED_FIFO | SCHED_RESET_ON_FORK,
-);
-   if (ret)
-   igt_warn("Failed to set scheduling policy!\n");
 
/* Allocate our spin batch and idle it. */
spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
@@ -1587,42 +1564,63 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
 
/* 1st pass is calibration, second pass is the test. */
for (int pass = 0; pass < ARRAY_SIZE(timeout); pass++) {
-   uint64_t busy_ns = -total_busy_ns;
-   uint64_t idle_ns = -total_idle_ns;
-   struct timespec test_start = { };
+   unsigned int target_idle_us = idle_us;
+   uint64_t busy_ns = 0, idle_ns = 0;
+   struct timespec start = { };
+   unsigned long pass_ns = 0;
+   double avg = 0.0, var = 0.0;
+   unsigned int n = 0;
+
+   igt_nsec_elapsed();
 
-   igt_nsec_elapsed(_start);
do {
-   unsigned int target_idle_us, t_busy;
+   unsigned long loop_ns, loop_busy;
+   struct timespec _ts = { };
+   double err, tmp;
+
+   /* PWM idle sleep. */
+   _ts.tv_nsec = target_idle_us * 1000;
+   

Re: [Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Avoid RT thread for accuracy test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-03 17:09:09)
> 
> On 03/04/2018 14:10, Chris Wilson wrote:
> > To me it seems like the closed system with each loop being "spin then
> > adjusted sleep" will autocorrect and more likely to finish correct (as
> > we are less reliant on the next loop for the accuracy). It's pretty much
> > immaterial, as we expect the pmu to match the measurements (and not our
> > expectations), but I find the one pass does all much simpler to follow.
> 
> Since we do a good number of loops, and hope the calibration will 
> converge quickly (which it does for me), I don't see that there is an 
> issue there.

I'm sitting here drinking coffee trying to decide if it does converge ;)
That's the problem here, I need to actually find a pencil, some paper
and remember some basic maths for series convergence. Not happening with
the amount of coffee I need to drink at the moment.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Avoid RT thread for accuracy test

[Tvrtko Ursulin]

On 03/04/2018 14:10, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-04-03 13:38:25)

From: Tvrtko Ursulin 

Realtime scheduling interferes with execlists submission (tasklet) so try
to simplify the PWM loop in a few ways:

  * Drop RT.
  * Longer batches for smaller systematic error.
  * More truthful test duration calculation.
  * Less clock queries.
  * No self-adjust - instead just report the achieved cycle and let the
parent check against it.
  * Report absolute cycle error.

v2:
  * Bring back self-adjust. (Chris Wilson)
(But slightly fixed version with no overflow.)

Signed-off-by: Tvrtko Ursulin 
---
  tests/perf_pmu.c | 97 +---
  1 file changed, 43 insertions(+), 54 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index f27b7ec7d2c2..0cfacd4a8fbe 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1504,12 +1504,6 @@ test_enable_race(int gem_fd, const struct 
intel_execution_engine2 *e)
 gem_quiescent_gpu(gem_fd);
  }
  
-static double __error(double val, double ref)

-{
-   igt_assert(ref > 1e-5 /* smallval */);
-   return (100.0 * val / ref) - 100.0;
-}
-
  static void __rearm_spin_batch(igt_spin_t *spin)
  {
 const uint32_t mi_arb_chk = 0x5 << 23;
@@ -1532,13 +1526,12 @@ static void
  accuracy(int gem_fd, const struct intel_execution_engine2 *e,
  unsigned long target_busy_pct)
  {
-   const unsigned int min_test_loops = 7;
-   const unsigned long min_test_us = 1e6;
-   unsigned long busy_us = 2500;
+   unsigned long busy_us = 1 - 100 * (1 + abs(50 - target_busy_pct));
 unsigned long idle_us = 100 * (busy_us - target_busy_pct *
 busy_us / 100) / target_busy_pct;
-   unsigned long pwm_calibration_us;
-   unsigned long test_us;
+   const unsigned long min_test_us = 1e6;
+   const unsigned long pwm_calibration_us = min_test_us;
+   const unsigned long test_us = min_test_us;
 double busy_r, expected;
 uint64_t val[2];
 uint64_t ts[2];
@@ -1553,13 +1546,6 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
 idle_us *= 2;
 }
  
-   pwm_calibration_us = min_test_loops * (busy_us + idle_us);

-   while (pwm_calibration_us < min_test_us)
-   pwm_calibration_us += busy_us + idle_us;
-   test_us = min_test_loops * (idle_us + busy_us);
-   while (test_us < min_test_us)
-   test_us += busy_us + idle_us;
-
 igt_info("calibration=%lums, test=%lums; ratio=%.2f%% (%luus/%luus)\n",
  pwm_calibration_us / 1000, test_us / 1000,
  (double)busy_us / (busy_us + idle_us) * 100.0,
@@ -1572,20 +1558,11 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
  
 /* Emit PWM pattern on the engine from a child. */

 igt_fork(child, 1) {
-   struct sched_param rt = { .sched_priority = 99 };
 const unsigned long timeout[] = {
 pwm_calibration_us * 1000, test_us * 1000
 };
-   uint64_t total_busy_ns = 0, total_idle_ns = 0;
+   uint64_t total_busy_ns = 0, total_ns = 0;
 igt_spin_t *spin;
-   int ret;
-
-   /* We need the best sleep accuracy we can get. */
-   ret = sched_setscheduler(0,
-SCHED_FIFO | SCHED_RESET_ON_FORK,
-);
-   if (ret)
-   igt_warn("Failed to set scheduling policy!\n");
  
 /* Allocate our spin batch and idle it. */

 spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
@@ -1594,39 +1571,51 @@ accuracy(int gem_fd, const struct 
intel_execution_engine2 *e,
  
 /* 1st pass is calibration, second pass is the test. */

 for (int pass = 0; pass < ARRAY_SIZE(timeout); pass++) {
-   uint64_t busy_ns = -total_busy_ns;
-   uint64_t idle_ns = -total_idle_ns;
-   struct timespec test_start = { };
+   unsigned int target_idle_us = idle_us;
+   uint64_t busy_ns = 0, idle_ns = 0;
+   struct timespec start = { };
+   unsigned long pass_ns = 0;
+
+   igt_nsec_elapsed();
  
-   igt_nsec_elapsed(_start);

 do {
-   unsigned int target_idle_us, t_busy;
+   unsigned long loop_ns, loop_busy;
+   struct timespec _ts = { };
+   double err;
+
+   /* PWM idle sleep. */
+   _ts.tv_nsec = target_idle_us * 1000;
+   

Re: [Intel-gfx] [PATCH v3 05/40] misc/mei/hdcp: Notifier chain for mei cldev state change

[Daniel Vetter]

On Tue, Apr 03, 2018 at 07:27:18PM +0530, Ramalingam C wrote:
> Notifier Chain is defined to inform all its clients about the mei
> client device state change. Routine is defined for the clients to
> register and unregister for the notification on state change.
> 
> v2:
>   Rebased.
> v3:
>   Notifier chain is adopted for cldev state update [Tomas]
> 
> Signed-off-by: Ramalingam C 

For managing interactions between multiple drivers notifier chains are
fairly problematic. The main reason is the locking embedded in the
notifier chain. To make things safe, that lock must be held everytime we
add/remove any part of the link, and when calling any callback. Usually
that means you get a neat deadlock sooner or later, because the
load/unload code has inverse paths compared to normal operation.

Notifiers also not not provide a clean way to handle suspend/resume
ordering.

There's two parts to do this properly.

1. Finding the other driver. Multi-part drivers are assembled nowadays
using the component framework. We're using that already to manage the
interaction between drm/i915 and snd-hda. If not all components are ready
yet, then the driver load sequence must be aborted by returning
-EPROBE_DEFER. That's going to be lots of fun, since for the mei/i915
interaction it's probably going to be i915 that needs to abort and retry
the driver load. But we do CI test all the abort points in our driver
load, so should work well.

2. Handling the ordering restrictions for suspend/resume. For i915/snd-hda
we used a early_resume/late_suspend callback trickery, but that doesn't
really scale to multiple levels. Since we've done that device_link has
been added. As a bonus device_link can also ensure that not only
suspend/resume (including runtime suspend/resume) is ordered correctly,
but also that driver bind/unbind works correctly. Still needs the
component stuff and initial -EPROBE_DEFER, but will all least make sure
we' only reprobe once more. See device_link_add + docs in device_link.rst.

One thing I didn't check is whether we want the device linke to also
manage runtime pm for us. It would mean that we keep the ME awake as long
as anything is using the gpu (any display on or any rendering happening).
That might be too much, but could also be that it won't matter (and then
using DL_FLAG_PM_RUNTIME would simply our code).

We might also need to convert the i915/snd-hda interactions to device_link
first, since the early/late_resume/suspend hack probably doesn't interact
too well with proper device_links.

Cheers, Daniel

> ---
>  drivers/misc/mei/hdcp/mei_hdcp.c | 36 +++---
>  include/linux/mei_hdcp.h | 48 
> 
>  2 files changed, 81 insertions(+), 3 deletions(-)
>  create mode 100644 include/linux/mei_hdcp.h
> 
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c 
> b/drivers/misc/mei/hdcp/mei_hdcp.c
> index b334615728a7..2811a25f8c57 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -31,6 +31,32 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +
> +static BLOCKING_NOTIFIER_HEAD(mei_cldev_notifier_list);
> +
> +void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool 
> enabled)
> +{
> + if (enabled)
> + blocking_notifier_call_chain(_cldev_notifier_list,
> +  MEI_CLDEV_ENABLED, cldev);
> + else
> + blocking_notifier_call_chain(_cldev_notifier_list,
> +  MEI_CLDEV_DISABLED, NULL);
> +}
> +
> +int mei_cldev_register_notify(struct notifier_block *nb)
> +{
> + return blocking_notifier_chain_register(_cldev_notifier_list, nb);
> +}
> +EXPORT_SYMBOL_GPL(mei_cldev_register_notify);
> +
> +int mei_cldev_unregister_notify(struct notifier_block *nb)
> +{
> + return blocking_notifier_chain_unregister(_cldev_notifier_list, nb);
> +}
> +EXPORT_SYMBOL_GPL(mei_cldev_unregister_notify);
>  
>  static int mei_hdcp_probe(struct mei_cl_device *cldev,
> const struct mei_cl_device_id *id)
> @@ -38,14 +64,18 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev,
>   int ret;
>  
>   ret = mei_cldev_enable(cldev);
> - if (ret < 0)
> + if (ret < 0) {
>   dev_err(>dev, "mei_cldev_enable Failed. %d\n", ret);
> + return ret;
> + }
>  
> - return ret;
> + mei_cldev_state_notify_clients(cldev, true);
> + return 0;
>  }
>  
>  static int mei_hdcp_remove(struct mei_cl_device *cldev)
>  {
> + mei_cldev_state_notify_clients(cldev, false);
>   mei_cldev_set_drvdata(cldev, NULL);
>   return mei_cldev_disable(cldev);
>  }
> @@ -71,4 +101,4 @@ module_mei_cl_driver(mei_hdcp_driver);
>  
>  MODULE_AUTHOR("Intel Corporation");
>  MODULE_LICENSE("Dual BSD/GPL");
> -MODULE_DESCRIPTION("HDCP");
> +MODULE_DESCRIPTION("MEI HDCP");
> diff --git a/include/linux/mei_hdcp.h 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev7)

[Saarinen, Jani]

HI, 
Clear idea if caused by changes? 

> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: tiistai 3. huhtikuuta 2018 18.06
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev7)
> 
> == Series Details ==
> 
> Series: Add NV12 support (rev7)
> URL   : https://patchwork.freedesktop.org/series/39670/
> State : failure
> 
> == Summary ==
> 
>  Possible new issues:
> 
> Test gem_linear_blits:
> Subgroup normal:
> pass   -> INCOMPLETE (shard-hsw)
> Test kms_draw_crc:
> Subgroup draw-method-xrgb-mmap-wc-untiled:
> skip   -> PASS   (shard-snb)
> Test kms_flip:
> Subgroup flip-vs-modeset-vs-hang:
> dmesg-warn -> PASS   (shard-hsw)
> Test kms_frontbuffer_tracking:
> Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
> skip   -> PASS   (shard-snb)
> Subgroup fbc-1p-primscrn-spr-indfb-move:
> skip   -> PASS   (shard-snb)
> Test kms_plane_scaling:
> Subgroup pipe-a-scaler-with-clipping-clamping:
> pass   -> FAIL   (shard-apl)
> Subgroup pipe-b-scaler-with-clipping-clamping:
> pass   -> FAIL   (shard-apl)
> Test prime_vgem:
> Subgroup basic-fence-flip:
> skip   -> PASS   (shard-snb)
> Test syncobj_wait:
> Subgroup multi-wait-for-submit-unsubmitted-signaled:
> incomplete -> PASS   (shard-snb)
> 
>  Known issues:
> 
> Test kms_cursor_legacy:
> Subgroup flip-vs-cursor-toggle:
> fail   -> PASS   (shard-hsw) fdo#102670
> Test kms_flip:
> Subgroup 2x-dpms-vs-vblank-race-interruptible:
> fail   -> PASS   (shard-hsw) fdo#103060 +1
> Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
> pass   -> FAIL   (shard-hsw) fdo#100368
> Subgroup flip-vs-expired-vblank-interruptible:
> fail   -> PASS   (shard-hsw) fdo#102887
> Test kms_sysfs_edid_timing:
> pass   -> WARN   (shard-apl) fdo#100047
> Test kms_vblank:
> Subgroup pipe-c-accuracy-idle:
> fail   -> PASS   (shard-hsw) fdo#102583
> 
> fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
> fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
> fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
> fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
> 
> shard-apltotal:3496 pass:1830 dwarn:1   dfail:0   fail:9   skip:1655
> time:12898s
> shard-hswtotal:3480 pass:1774 dwarn:1   dfail:0   fail:4   skip:1699
> time:10869s
> shard-snbtotal:3496 pass:1375 dwarn:1   dfail:0   fail:2   skip:2118
> time:7026s
> Blacklisted hosts:
> shard-kbltotal:3496 pass:1931 dwarn:27  dfail:0   fail:9   skip:1529
> time:9411s
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_8568/shards.html
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev7)

[Patchwork]

== Series Details ==

Series: Add NV12 support (rev7)
URL   : https://patchwork.freedesktop.org/series/39670/
State : failure

== Summary ==

 Possible new issues:

Test gem_linear_blits:
Subgroup normal:
pass   -> INCOMPLETE (shard-hsw)
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup flip-vs-modeset-vs-hang:
dmesg-warn -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
skip   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-spr-indfb-move:
skip   -> PASS   (shard-snb)
Test kms_plane_scaling:
Subgroup pipe-a-scaler-with-clipping-clamping:
pass   -> FAIL   (shard-apl)
Subgroup pipe-b-scaler-with-clipping-clamping:
pass   -> FAIL   (shard-apl)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (shard-snb)
Test syncobj_wait:
Subgroup multi-wait-for-submit-unsubmitted-signaled:
incomplete -> PASS   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup flip-vs-cursor-toggle:
fail   -> PASS   (shard-hsw) fdo#102670
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060 +1
Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test kms_vblank:
Subgroup pipe-c-accuracy-idle:
fail   -> PASS   (shard-hsw) fdo#102583

fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583

shard-apltotal:3496 pass:1830 dwarn:1   dfail:0   fail:9   skip:1655 
time:12898s
shard-hswtotal:3480 pass:1774 dwarn:1   dfail:0   fail:4   skip:1699 
time:10869s
shard-snbtotal:3496 pass:1375 dwarn:1   dfail:0   fail:2   skip:2118 
time:7026s
Blacklisted hosts:
shard-kbltotal:3496 pass:1931 dwarn:27  dfail:0   fail:9   skip:1529 
time:9411s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8568/shards.html
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Re: [Intel-gfx] [PATCH v4 5/5] i915: add documentation to intel_engine_cs

[Rogovin, Kevin]

HI,


-Original Message-
From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] 

 - snip -
>>  
>> void(*set_default_submission)(struct intel_engine_cs 
>> *engine);
>>  
>> +   /* In addition to pinning the context, returns the intel_ringbuffer
>> +* to which to write commands.

>   /* Pin context and return intel_ring to write commands to. */

I like that since it is shorter :)

>> +
>> +   /* Request room on the ringbuffer of a request in order to write
>> +* commands for a request; In addition, if necessary, add commands
>> +* to the buffer so that the i915_gem_context of the request
>> +* is the one active for the commands.
>> +*/

> "Reserve room from the ringbuffer for commands and emit necessary context 
> switching commands."?

Agreed; reserved is word to use here.

>> +   /* Add a batchbuffer start command; the GPU command is added to
>> +* the buffer holding the commands of the request (i.e. calling
>> +* intel_ring_begin() on i915_request::ring).
>> +*/
>> int (*emit_bb_start)(struct i915_request *rq,
>>  u64 offset, u32 length,
>> unsigned int dispatch_flags);  
>> #define I915_DISPATCH_SECURE BIT(0)  #define I915_DISPATCH_PINNED 
>> BIT(1)
>>  #define I915_DISPATCH_RS BIT(2)
>> +   /* Add a memory write command that writes the global sequence number
>> +* (i915_request::global_seqno) and also add an interrupt command;
>> +* the GPU command is added to the buffer holding the commands of
>> +* the request (i.e. calling intel_ring_begin() on
>> +* i915_request::ring).

>This is more about what a breadcrumb is than what this interface is about. 
>"Add commands for triggering a breadcrumb 
> to be picked up" and maybe explain elsewhere what a breadcrumb is.

> So overall, try to make the comments bit less verbose and leave the 
> implementation detail to the implementation functions :)

I am somewhat tempted to just drop this patch or add more documentation. The 
function pointers are used in the code common
to the legacy way and LRC way of submitting batchbuffers to the GPU, so they 
should have somekind of contract to what they are
supposed to do... but spelling out that contract might be a bit much...

Opinions?

 -Kevin
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP2.2 (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Implement HDCP2.2 (rev3)
URL   : https://patchwork.freedesktop.org/series/38254/
State : failure

== Summary ==

CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_drv.o
In file included from drivers/gpu/drm/i915/intel_drv.h:32:0,
 from drivers/gpu/drm/i915/i915_trace.h:11,
 from drivers/gpu/drm/i915/i915_drv.h:2657,
 from drivers/gpu/drm/i915/i915_drv.c:49:
./include/linux/mei_hdcp.h:148:12: error: ‘mei_cldev_unregister_notify’ defined 
but not used [-Werror=unused-function]
 static int mei_cldev_unregister_notify(struct notifier_block *nb)
^~~
./include/linux/mei_hdcp.h:144:12: error: ‘mei_cldev_register_notify’ defined 
but not used [-Werror=unused-function]
 static int mei_cldev_register_notify(struct notifier_block *nb)
^
cc1: all warnings being treated as errors
scripts/Makefile.build:324: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' 
failed
make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
scripts/Makefile.build:583: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:583: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:583: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] [PATCH v3 40/40] drm/i915: Add HDCP2.2 support for HDMI connectors

[Ramalingam C]

On HDMI connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index a974d3e2097a..29689269dc80 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2545,7 +2545,8 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
 
if (is_hdcp_supported(dev_priv, port)) {
int ret = intel_hdcp_init(intel_connector,
- _hdmi_hdcp_shim, false);
+_hdmi_hdcp_shim,
+is_hdcp2_supported(dev_priv));
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
-- 
2.7.4

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[Intel-gfx] [PATCH v3 39/40] drm/i915: Add HDCP2.2 support for DP connectors

[Ramalingam C]

On DP connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c   | 2 +-
 drivers/gpu/drm/i915/intel_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_hdcp.c | 1 -
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e5cb54ceda38..43318003ce14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6733,7 +6733,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
 
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
int ret = intel_hdcp_init(intel_connector, _dp_hdcp_shim,
- false);
+ is_hdcp2_supported(dev_priv));
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 37f9a0e2ea13..2bb562738964 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1941,6 +1941,7 @@ int intel_hdcp_enable(struct intel_connector *connector);
 int intel_hdcp_disable(struct intel_connector *connector);
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
 void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
+bool is_hdcp2_supported(struct drm_i915_private *dev_priv);
 
 /* intel_psr.c */
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 9386b451191e..9d5cade3b236 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1723,7 +1723,6 @@ static int mei_cldev_notify(struct notifier_block *nb, 
unsigned long event,
return NOTIFY_OK;
 }
 
-static inline
 bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
 {
return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
-- 
2.7.4

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[Intel-gfx] [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP

[Ramalingam C]

Implements the DP adaptation specific HDCP2.2 functions.

These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.

Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
than completions concept. WIP to understand and implement that,
if needed. Just to unblock the review of other changes, v2 still
continues with completions.

v2:
  wait for cp_irq is merged with this patch. Rebased.
v3:
  wait_queue is used for wait for cp_irq [Chris Wilson]

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c   | 352 ++
 drivers/gpu/drm/i915/intel_drv.h  |   7 +
 drivers/gpu/drm/i915/intel_hdcp.c |   5 +
 3 files changed, 364 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f92c0326fff5..e5cb54ceda38 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -5070,6 +5071,28 @@ void intel_dp_encoder_suspend(struct intel_encoder 
*intel_encoder)
pps_unlock(intel_dp);
 }
 
+static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
+int timeout)
+{
+   long ret;
+
+   /* Reinit */
+   atomic_set(>cp_irq_recved, 0);
+
+#define C (atomic_read(>cp_irq_recved) > 0)
+   ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
+  msecs_to_jiffies(timeout));
+
+   if (ret > 0) {
+   atomic_set(>cp_irq_recved, 0);
+   return 0;
+   } else if (!ret) {
+   return -ETIMEDOUT;
+   }
+   return (int)ret;
+}
+
+
 static
 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
@@ -5288,6 +5311,329 @@ int intel_dp_hdcp_capable(struct intel_digital_port 
*intel_dig_port,
return 0;
 }
 
+static inline
+int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int *offset)
+{
+   switch (byte) {
+   case HDCP_2_2_AKE_INIT:
+   *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_CERT:
+   *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_NO_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   *offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_PARING_INFO:
+   *offset = DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET;
+   break;
+   case HDCP_2_2_LC_INIT:
+   *offset = DP_HDCP_2_2_LC_INIT_OFFSET;
+   break;
+   case HDCP_2_2_LC_SEND_LPRIME:
+   *offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
+   break;
+   case HDCP_2_2_SKE_SEND_EKS:
+   *offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_RECVID_LIST:
+   *offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_ACK:
+   *offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_MANAGE:
+   *offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_READY:
+   *offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
+   break;
+   case HDCP_2_2_ERRATA_DP_STREAM_TYPE:
+   *offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
+   break;
+   default:
+   DRM_ERROR("Unrecognized Msg ID\n");
+   return -EINVAL;
+   }
+   return 0;
+}
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+ uint8_t *rx_status)
+{
+   ssize_t ret;
+
+   ret = drm_dp_dpcd_read(_dig_port->dp.aux,
+  DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
+  HDCP_2_2_DP_RXSTATUS_LEN);
+   if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
+   DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
+   return ret >= 0 ? -EIO : ret;
+   }
+
+   return 0;
+}
+
+static inline
+int intel_dp_hdcp2_timeout_for_msg(uint8_t msg_id, bool paired)
+{
+   int timeout = -EINVAL;
+
+   switch (msg_id) {
+   case HDCP_2_2_AKE_SEND_CERT:
+   timeout = HDCP_2_2_CERT_TIMEOUT;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   if (paired)
+   timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
+   else
+   timeout = 

[Intel-gfx] [PATCH v3 38/40] drm/i915: Implement the HDCP2.2 support for HDMI

[Ramalingam C]

Implements the HDMI adapatation specific HDCP2.2 operations.

Basically these are DDC read and write for authenticating through
HDCP2.2 messages.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 203 ++
 1 file changed, 203 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index b8b1086c0cbd..a974d3e2097a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1106,6 +1107,203 @@ bool intel_hdmi_hdcp_check_link(struct 
intel_digital_port *intel_dig_port)
return true;
 }
 
+static
+int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+   uint8_t *rx_status)
+{
+   return intel_hdmi_hdcp_read(intel_dig_port,
+   HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
+   rx_status,
+   HDCP_2_2_HDMI_RXSTATUS_LEN);
+}
+
+static inline
+int intel_hdmi_hdcp2_timeout_for_msg(uint8_t msg_id, bool is_paired)
+{
+   int timeout = -EINVAL;
+
+   switch (msg_id) {
+   case HDCP_2_2_AKE_SEND_CERT:
+   timeout = HDCP_2_2_CERT_TIMEOUT;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   if (is_paired)
+   timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
+   else
+   timeout = HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT;
+   break;
+   case HDCP_2_2_AKE_SEND_PARING_INFO:
+   timeout = HDCP_2_2_PAIRING_TIMEOUT;
+   break;
+   case HDCP_2_2_LC_SEND_LPRIME:
+   timeout = HDCP_2_2_HDMI_LPRIME_TIMEOUT;
+   break;
+   case HDCP_2_2_REP_SEND_RECVID_LIST:
+   timeout = HDCP_2_2_RECVID_LIST_TIMEOUT;
+   break;
+   case HDCP_2_2_REP_STREAM_READY:
+   timeout = HDCP_2_2_STREAM_READY_TIMEOUT;
+   break;
+   default:
+   DRM_ERROR("Unsupported msg_id: %d\n", (int)msg_id);
+   }
+   return timeout;
+}
+
+static inline
+int hdcp2_detect_msg_availability(struct intel_digital_port 
*intel_digital_port,
+ uint8_t msg_id, bool *msg_ready,
+ ssize_t *msg_sz)
+{
+   uint8_t rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
+   int ret;
+
+   ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
+   if (ret < 0) {
+   DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
+   return ret;
+   }
+
+   *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
+ rx_status[0]);
+
+   if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
+   *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
+*msg_sz);
+   else
+   *msg_ready = *msg_sz;
+
+   return 0;
+}
+
+/**
+ * intel_hdmi_hdcp2_wait_for_msg: Detects the hdmi hdcp2.2 msg availability
+ * @hdcp:  hdcp structure
+ * @msg_id:Message ID for which we are waiting
+ *
+ * Detects the HDMI HDCP2.2 Message availability
+ *
+ * Returns -ETIMEOUT in case of timeout, Message Size on success
+ */
+static ssize_t
+intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, bool paired)
+{
+   bool msg_ready = false;
+   int timeout, ret;
+   ssize_t msg_sz;
+
+   timeout = intel_hdmi_hdcp2_timeout_for_msg(msg_id, paired);
+   if (timeout < 0)
+   return timeout;
+
+   ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
+msg_id, _ready, _sz),
+!ret && msg_ready && msg_sz, timeout * 1000,
+1000, 5 * 1000);
+   if (ret)
+   DRM_ERROR("msg_id: %d, ret: %d, timeout: %d\n",
+ msg_id, ret, timeout);
+   return ret ? ret : msg_sz;
+}
+
+static
+int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
+  void *buf, size_t size)
+{
+   unsigned int offset;
+
+   offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
+   return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
+}
+
+static
+int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, void *buf, size_t size)
+{
+   struct intel_hdmi *hdmi = _dig_port->hdmi;
+   struct intel_hdcp *hdcp = >attached_connector->hdcp;
+   struct drm_i915_private *dev_priv;
+   struct i2c_adapter *adapter;
+   unsigned int offset;
+   ssize_t ret;
+
+   ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
+   

[Intel-gfx] [PATCH v3 36/40] drm/i915: Implement gmbus burst read

[Ramalingam C]

Implements a interface for single burst read of data that is larger
than 512 Bytes through gmbus.

HDCP2.2 spec expects HDCP2.2 transmitter to read 522Bytes of HDCP
receiver certificates in single burst read. On gmbus, to read more
than 511Bytes, HW provides a workaround for burst read.

This patch passes the burst read request through gmbus read functions.
And implements the sequence of enabling and disabling the burst read.

v2:
  No Changes.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_reg.h  |   3 +
 drivers/gpu/drm/i915/intel_i2c.c | 124 +--
 3 files changed, 112 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6e740f6fe33f..72534a1e544b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3688,6 +3688,8 @@ extern void intel_teardown_gmbus(struct drm_i915_private 
*dev_priv);
 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 unsigned int pin);
 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
+extern int intel_gmbus_burst_read(struct i2c_adapter *adapter,
+ unsigned int offset, void *buf, size_t size);
 
 extern struct i2c_adapter *
 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f04ad3c15abd..56979bc4e9d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3123,6 +3123,7 @@ enum i915_power_well_id {
 #define   GMBUS_RATE_400KHZ(2<<8) /* reserved on Pineview */
 #define   GMBUS_RATE_1MHZ  (3<<8) /* reserved on Pineview */
 #define   GMBUS_HOLD_EXT   (1<<7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
 #define   GMBUS_PIN_DISABLED   0
 #define   GMBUS_PIN_SSC1
 #define   GMBUS_PIN_VGADDC 2
@@ -3150,8 +3151,10 @@ enum i915_power_well_id {
 #define   GMBUS_CYCLE_WAIT (1<<25)
 #define   GMBUS_CYCLE_INDEX(2<<25)
 #define   GMBUS_CYCLE_STOP (4<<25)
+#define   GMBUS_CYCLE_MASK (7<<25)
 #define   GMBUS_BYTE_COUNT_SHIFT 16
 #define   GMBUS_BYTE_COUNT_MAX   256U
+#define   GMBUS_BYTE_COUNT_HW_MAX 511U
 #define   GMBUS_SLAVE_INDEX_SHIFT 8
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e6875509bcd9..dcb2be0d54ee 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -364,21 +364,30 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
  unsigned short addr, u8 *buf, unsigned int len,
- u32 gmbus1_index)
+ u32 gmbus1_index, bool burst_read)
 {
+   unsigned int size = len;
+   int ret;
+
+   if (burst_read) {
+   /* Seq to enable Burst Read */
+   I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) |
+ GMBUS_BYTE_CNT_OVERRIDE));
+   size = GMBUS_BYTE_COUNT_HW_MAX;
+   }
+
I915_WRITE_FW(GMBUS1,
  gmbus1_index |
  GMBUS_CYCLE_WAIT |
- (len << GMBUS_BYTE_COUNT_SHIFT) |
+ (size << GMBUS_BYTE_COUNT_SHIFT) |
  (addr << GMBUS_SLAVE_ADDR_SHIFT) |
  GMBUS_SLAVE_READ | GMBUS_SW_RDY);
while (len) {
-   int ret;
u32 val, loop = 0;
 
ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
if (ret)
-   return ret;
+   goto exit;
 
val = I915_READ_FW(GMBUS3);
do {
@@ -387,12 +396,29 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
} while (--len && ++loop < 4);
}
 
-   return 0;
+exit:
+   if (burst_read) {
+
+   /* Seq to disable the Burst Read */
+   I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) &
+ ~GMBUS_BYTE_CNT_OVERRIDE));
+   I915_WRITE_FW(GMBUS1, (I915_READ_FW(GMBUS1) &
+ ~GMBUS_CYCLE_MASK) | GMBUS_CYCLE_STOP);
+
+   /*
+* On Burst read disable, GMBUS need more time to settle
+* down to Idle State.
+*/
+   ret = intel_wait_for_register_fw(dev_priv, GMBUS2,
+GMBUS_ACTIVE, 0, 50);
+   }
+
+   return ret;
 }
 
 static int
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
-   u32 gmbus1_index)
+   u32 gmbus1_index, bool burst_read)
 {

[Intel-gfx] [PATCH v3 35/40] drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ

[Ramalingam C]

On DP HDCP1.4 and 2.2, when CP_IRQ is received, start the link
integrity check for the HDCP version that is enabled.

v2:
  Rebased. Function name is changed.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 +-
 drivers/gpu/drm/i915/intel_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_hdcp.c | 31 ++-
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4a9f5a690528..f92c0326fff5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4468,7 +4468,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector & DP_CP_IRQ)
-   intel_hdcp_check_link(intel_dp->attached_connector);
+   intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
if (sink_irq_vector & DP_SINK_SPECIFIC_IRQ)
DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2f14756b4b0e..8e60ccd0d368 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1932,8 +1932,8 @@ int intel_hdcp_init(struct intel_connector *connector,
bool hdcp2_supported);
 int intel_hdcp_enable(struct intel_connector *connector);
 int intel_hdcp_disable(struct intel_connector *connector);
-int intel_hdcp_check_link(struct intel_connector *connector);
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
+void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
 
 /* intel_psr.c */
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 5707830a4617..8cf0eeb4b3f8 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -32,6 +32,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port 
*intel_dig_port,
   const struct intel_hdcp_shim *shim, u8 *bksv);
 static
 struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector);
+static int intel_hdcp_check_link(struct intel_connector *connector);
 
 static inline
 bool panel_supports_hdcp(struct intel_connector *connector)
@@ -79,6 +80,26 @@ static inline bool intel_hdcp2_capable(struct 
intel_connector *connector)
panel_supports_hdcp2(connector));
 }
 
+static inline bool intel_hdcp_in_force(struct intel_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   enum port port = connector->encoder->port;
+   u32 reg;
+
+   reg = I915_READ(PORT_HDCP_STATUS(port));
+   return reg & (HDCP_STATUS_AUTH | HDCP_STATUS_ENC);
+}
+
+static inline bool intel_hdcp2_in_force(struct intel_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   enum port port = connector->encoder->port;
+   u32 reg;
+
+   reg = I915_READ(HDCP2_STATUS_DDI(port));
+   return reg & (LINK_ENCRYPTION_STATUS | LINK_AUTH_STATUS);
+}
+
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
 {
@@ -858,7 +879,7 @@ void intel_hdcp_atomic_check(struct drm_connector 
*connector,
 }
 
 /* Implements Part 3 of the HDCP authorization procedure */
-int intel_hdcp_check_link(struct intel_connector *connector)
+static int intel_hdcp_check_link(struct intel_connector *connector)
 {
struct intel_hdcp *hdcp = >hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
@@ -1734,3 +1755,11 @@ static int intel_hdcp2_init(struct intel_connector 
*connector)
hdcp->hdcp2_supported = false;
return ret;
 }
+
+void intel_hdcp_handle_cp_irq(struct intel_connector *connector)
+{
+   if (intel_hdcp_in_force(connector))
+   intel_hdcp_check_link(connector);
+   else if (intel_hdcp2_in_force(connector))
+   intel_hdcp2_check_link(connector);
+}
-- 
2.7.4

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[Intel-gfx] [PATCH v3 33/40] drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure

[Ramalingam C]

When HDCP2.2 enabling fails and HDCP1.4 is supported, HDCP1.4 is
enabled.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 01701d7b7b07..5707830a4617 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -786,7 +786,9 @@ int intel_hdcp_enable(struct intel_connector *connector)
 */
if (intel_hdcp2_capable(connector))
ret = _intel_hdcp2_enable(connector);
-   else if (intel_hdcp_capable(connector))
+
+   /* When HDCP2.2 fails, HDCP1.4 will be attempted */
+   if (ret && intel_hdcp_capable(connector))
ret = _intel_hdcp_enable(connector);
 
if (!ret) {
-- 
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[Intel-gfx] [PATCH v3 34/40] drm/i915: hdcp_check_link only on CP_IRQ

[Ramalingam C]

HDCP check link is invoked only on CP_IRQ detection, instead of all
short pulses.

v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 955a20208097..4a9f5a690528 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4467,8 +4467,10 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
-   if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
-   DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+   if (sink_irq_vector & DP_CP_IRQ)
+   intel_hdcp_check_link(intel_dp->attached_connector);
+   if (sink_irq_vector & DP_SINK_SPECIFIC_IRQ)
+   DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
}
 
/* defer to the hotplug work for link retraining if needed */
@@ -5438,9 +5440,6 @@ intel_dp_hpd_pulse(struct intel_digital_port 
*intel_dig_port, bool long_hpd)
 
handled = intel_dp_short_pulse(intel_dp);
 
-   /* Short pulse can signify loss of hdcp authentication */
-   intel_hdcp_check_link(intel_dp->attached_connector);
-
if (!handled) {
intel_dp->detect_done = false;
goto put_power;
-- 
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[Intel-gfx] [PATCH v3 32/40] drm/i915: Enable superior HDCP ver that is capable

[Ramalingam C]

Considering that HDCP2.2 is more secure than HDCP1.4, When a setup
supports HDCP2.2 and HDCP1.4, HDCP2.2 will be enabled.

v2:
  Included few optimization suggestions [Chris Wilson]
  Commit message is updated as per the rebased version.
v3:
  No changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 76 +++
 1 file changed, 69 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 383e35689fbd..01701d7b7b07 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -27,6 +27,57 @@ static int _intel_hdcp2_disable(struct intel_connector 
*connector);
 static void intel_hdcp2_check_work(struct work_struct *work);
 static int intel_hdcp2_check_link(struct intel_connector *connector);
 static int intel_hdcp2_init(struct intel_connector *connector);
+static inline
+int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
+  const struct intel_hdcp_shim *shim, u8 *bksv);
+static
+struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector);
+
+static inline
+bool panel_supports_hdcp(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   bool capable = false;
+   u8 bksv[5];
+
+   if (hdcp->hdcp_shim) {
+   if (hdcp->hdcp_shim->hdcp_capable) {
+   hdcp->hdcp_shim->hdcp_capable(intel_dig_port, );
+   } else {
+   if (!intel_hdcp_read_valid_bksv(intel_dig_port,
+   hdcp->hdcp_shim, bksv))
+   capable = true;
+   }
+   }
+   return capable;
+}
+
+static inline
+bool panel_supports_hdcp2(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   bool capable = false;
+
+   if (hdcp->hdcp2_supported)
+   hdcp->hdcp_shim->hdcp_2_2_capable(intel_dig_port, );
+
+   return capable;
+}
+
+/* Is HDCP1.4 capable on Platform and Panel */
+static inline bool intel_hdcp_capable(struct intel_connector *connector)
+{
+   return (connector->hdcp.hdcp_shim && panel_supports_hdcp(connector));
+}
+
+/* Is HDCP2.2 capable on Platform and Panel */
+static inline bool intel_hdcp2_capable(struct intel_connector *connector)
+{
+   return (connector->hdcp.hdcp2_supported &&
+   panel_supports_hdcp2(connector));
+}
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -722,20 +773,27 @@ int intel_hdcp_init(struct intel_connector *connector,
 int intel_hdcp_enable(struct intel_connector *connector)
 {
struct intel_hdcp *hdcp = >hdcp;
-   int ret;
+   int ret = -EINVAL;
 
if (!hdcp->hdcp_shim)
return -ENOENT;
 
mutex_lock(>hdcp_mutex);
 
-   ret = _intel_hdcp_enable(connector);
-   if (ret)
-   goto out;
+   /*
+* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
+* is capable of HDCP2.2, it is preferred to use HDCP2.2.
+*/
+   if (intel_hdcp2_capable(connector))
+   ret = _intel_hdcp2_enable(connector);
+   else if (intel_hdcp_capable(connector))
+   ret = _intel_hdcp_enable(connector);
+
+   if (!ret) {
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+   schedule_work(>hdcp_prop_work);
+   }
 
-   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
-   schedule_work(>hdcp_prop_work);
-out:
mutex_unlock(>hdcp_mutex);
return ret;
 }
@@ -752,10 +810,14 @@ int intel_hdcp_disable(struct intel_connector *connector)
 
if (hdcp->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
+   if (hdcp->hdcp2_supported)
+   _intel_hdcp2_disable(connector);
+
ret = _intel_hdcp_disable(connector);
}
 
mutex_unlock(>hdcp_mutex);
+   cancel_delayed_work_sync(>hdcp2_check_work);
cancel_delayed_work_sync(>hdcp_check_work);
return ret;
 }
-- 
2.7.4

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[Intel-gfx] [PATCH v3 31/40] drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable

[Ramalingam C]

As a preparation for making the intel_hdcp_enable as common function
for both HDCP1.4 and HDCP2.2, HDCP1.4 check_link scheduling is moved
into _intel_hdcp_enable() function.

v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 6eb58a833c7d..383e35689fbd 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -627,7 +627,7 @@ static int _intel_hdcp_enable(struct intel_connector 
*connector)
ret = intel_hdcp_auth(conn_to_dig_port(connector),
  hdcp->hdcp_shim);
if (!ret)
-   return 0;
+   break;
 
DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
 
@@ -635,7 +635,12 @@ static int _intel_hdcp_enable(struct intel_connector 
*connector)
_intel_hdcp_disable(connector);
}
 
-   DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret);
+   if (i != tries)
+   schedule_delayed_work(>hdcp_check_work,
+ DRM_HDCP_CHECK_PERIOD_MS);
+   else
+   DRM_ERROR("HDCP authentication failed (%d tries/%d)\n",
+ tries, ret);
return ret;
 }
 
@@ -730,8 +735,6 @@ int intel_hdcp_enable(struct intel_connector *connector)
 
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
schedule_work(>hdcp_prop_work);
-   schedule_delayed_work(>hdcp_check_work,
- DRM_HDCP_CHECK_PERIOD_MS);
 out:
mutex_unlock(>hdcp_mutex);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v3 30/40] drm/i915: Initialize HDCP2.2 and its MEI interface

[Ramalingam C]

Initialize HDCP2.2 support. This includes the mei interface
initialization along with required notifier registration.

v2:
  mei interface handle is protected with mutex. [Chris Wilson]
v3:
  Notifiers are used for the mei interface state.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c   |   3 +-
 drivers/gpu/drm/i915/intel_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_hdcp.c | 104 +-
 drivers/gpu/drm/i915/intel_hdmi.c |   2 +-
 4 files changed, 109 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9a4a51e79fa1..955a20208097 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6381,7 +6381,8 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_add_properties(intel_dp, connector);
 
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
-   int ret = intel_hdcp_init(intel_connector, _dp_hdcp_shim);
+   int ret = intel_hdcp_init(intel_connector, _dp_hdcp_shim,
+ false);
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ca06d9a158f6..2f14756b4b0e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -442,7 +442,7 @@ struct intel_hdcp {
/* mei interface related information */
struct mei_cl_device *cldev;
struct mei_hdcp_data mei_data;
-
+   struct notifier_block mei_cldev_nb;
struct delayed_work hdcp2_check_work;
 };
 
@@ -1928,7 +1928,8 @@ void intel_hdcp_atomic_check(struct drm_connector 
*connector,
 struct drm_connector_state *old_state,
 struct drm_connector_state *new_state);
 int intel_hdcp_init(struct intel_connector *connector,
-   const struct intel_hdcp_shim *hdcp_shim);
+   const struct intel_hdcp_shim *hdcp_shim,
+   bool hdcp2_supported);
 int intel_hdcp_enable(struct intel_connector *connector);
 int intel_hdcp_disable(struct intel_connector *connector);
 int intel_hdcp_check_link(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 53d35ee8f683..6eb58a833c7d 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "intel_drv.h"
 #include "i915_reg.h"
@@ -25,6 +26,7 @@ static int _intel_hdcp2_enable(struct intel_connector 
*connector);
 static int _intel_hdcp2_disable(struct intel_connector *connector);
 static void intel_hdcp2_check_work(struct work_struct *work);
 static int intel_hdcp2_check_link(struct intel_connector *connector);
+static int intel_hdcp2_init(struct intel_connector *connector);
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -686,11 +688,15 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv, 
enum port port)
 }
 
 int intel_hdcp_init(struct intel_connector *connector,
-   const struct intel_hdcp_shim *hdcp_shim)
+   const struct intel_hdcp_shim *hdcp_shim,
+   bool hdcp2_supported)
 {
struct intel_hdcp *hdcp = >hdcp;
int ret;
 
+   if (!hdcp_shim)
+   return -EINVAL;
+
ret = drm_connector_attach_content_protection_property(
>base);
if (ret)
@@ -699,7 +705,12 @@ int intel_hdcp_init(struct intel_connector *connector,
hdcp->hdcp_shim = hdcp_shim;
mutex_init(>hdcp_mutex);
INIT_DELAYED_WORK(>hdcp_check_work, intel_hdcp_check_work);
+   INIT_DELAYED_WORK(>hdcp2_check_work, intel_hdcp2_check_work);
INIT_WORK(>hdcp_prop_work, intel_hdcp_prop_work);
+
+   if (hdcp2_supported)
+   intel_hdcp2_init(connector);
+
return 0;
 }
 
@@ -1565,3 +1576,94 @@ static void intel_hdcp2_check_work(struct work_struct 
*work)
schedule_delayed_work(>hdcp2_check_work,
  DRM_HDCP2_CHECK_PERIOD_MS);
 }
+
+static inline int initialize_mei_hdcp_data(struct intel_connector *connector)
+{
+   struct intel_hdcp *hdcp = >hdcp;
+   struct mei_hdcp_data *data = >mei_data;
+   enum port port;
+
+   if (connector->encoder) {
+   port = connector->encoder->port;
+   data->port = GET_MEI_DDI_INDEX(port);
+   }
+
+   data->port_type = INTEGRATED;
+   data->protocol = hdcp->hdcp_shim->hdcp_protocol();
+
+   data->k = 1;
+   if (!data->streams)
+   data->streams = kcalloc(data->k,
+   

[Intel-gfx] [PATCH v3 29/40] drm/i915: Pullout the bksv read and validation

[Ramalingam C]

For reusability purpose, this patch implements the hdcp1.4 bksv's
read and validation as a functions.

For detecting the HDMI panel's HDCP capability this fucntions will be
used.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 38 +-
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index fd30e2b1ddc3..53d35ee8f683 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -152,6 +152,27 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
return true;
 }
 
+static inline
+int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
+  const struct intel_hdcp_shim *shim, u8 *bksv)
+{
+   int ret, i, tries = 2;
+
+   /* HDCP spec states that we must retry the bksv if it is invalid */
+   for (i = 0; i < tries; i++) {
+   ret = shim->read_bksv(intel_dig_port, bksv);
+   if (ret)
+   return ret;
+   if (intel_hdcp_is_ksv_valid(bksv))
+   break;
+   }
+   if (i == tries) {
+   DRM_ERROR("HDCP failed, Bksv is invalid\n");
+   return -ENODEV;
+   }
+   return 0;
+}
+
 /* Implements Part 2 of the HDCP authorization procedure */
 static
 int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
@@ -411,7 +432,7 @@ static int intel_hdcp_auth(struct intel_digital_port 
*intel_dig_port,
struct drm_i915_private *dev_priv;
enum port port;
unsigned long r0_prime_gen_start;
-   int ret, i, tries = 2;
+   int ret, i;
union {
u32 reg[2];
u8 shim[DRM_HDCP_AN_LEN];
@@ -469,18 +490,9 @@ static int intel_hdcp_auth(struct intel_digital_port 
*intel_dig_port,
 
memset(, 0, sizeof(bksv));
 
-   /* HDCP spec states that we must retry the bksv if it is invalid */
-   for (i = 0; i < tries; i++) {
-   ret = shim->read_bksv(intel_dig_port, bksv.shim);
-   if (ret)
-   return ret;
-   if (intel_hdcp_is_ksv_valid(bksv.shim))
-   break;
-   }
-   if (i == tries) {
-   DRM_ERROR("HDCP failed, Bksv is invalid\n");
-   return -ENODEV;
-   }
+   ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim);
+   if (ret < 0)
+   return ret;
 
I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
-- 
2.7.4

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[Intel-gfx] [PATCH v3 28/40] drm/i915: Handle HDCP2.2 downstream topology change

[Ramalingam C]

When repeater notifies a downstream topology change, this patch
reauthenticate the repeater alone with out disabling the hdcp
encryption. If that fails then complete reauthentication is executed.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index e2aec73aefe3..fd30e2b1ddc3 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1497,8 +1497,23 @@ static int intel_hdcp2_check_link(struct intel_connector 
*connector)
goto out;
}
 
-   DRM_INFO("[%s:%d] HDCP2.2 link failed, retrying authentication\n",
-connector->base.name, connector->base.base.id);
+   if (ret == DRM_HDCP_TOPOLOGY_CHANGE) {
+   if (hdcp->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+   goto out;
+
+   DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n");
+   ret = hdcp2_authenticate_repeater_topology(connector);
+   if (!ret) {
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+   schedule_work(>hdcp_prop_work);
+   goto out;
+   }
+   DRM_ERROR("[%s:%d] Repeater topology auth failed.(%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+   } else {
+   DRM_ERROR("[%s:%d] HDCP2.2 link failed, retrying auth\n",
+connector->base.name, connector->base.base.id);
+   }
 
ret = _intel_hdcp2_disable(connector);
if (ret) {
-- 
2.7.4

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[Intel-gfx] [PATCH v3 27/40] drm/i915: Implement HDCP2.2 link integrity check

[Ramalingam C]

Implements the link integrity check once in 500mSec.

Once encryption is enabled, an ongoing Link Integrity Check is
performed by the HDCP Receiver to check that cipher synchronization
is maintained between the HDCP Transmitter and the HDCP Receiver.

On the detection of synchronization lost, the HDCP Receiver must assert
the corresponding bits of the RxStatus register. The Transmitter polls
the RxStatus register and it may initiate re-authentication.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 81 ++-
 include/drm/drm_hdcp.h|  8 
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 005627746ca5..e2aec73aefe3 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -23,6 +23,8 @@
 
 static int _intel_hdcp2_enable(struct intel_connector *connector);
 static int _intel_hdcp2_disable(struct intel_connector *connector);
+static void intel_hdcp2_check_work(struct work_struct *work);
+static int intel_hdcp2_check_link(struct intel_connector *connector);
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -1456,6 +1458,83 @@ static int _intel_hdcp2_enable(struct intel_connector 
*connector)
 
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
schedule_work(>hdcp_prop_work);
-
+   schedule_delayed_work(>hdcp2_check_work,
+ DRM_HDCP2_CHECK_PERIOD_MS);
return 0;
 }
+
+static int intel_hdcp2_check_link(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_hdcp *hdcp = >hdcp;
+   enum port port = connector->encoder->port;
+   int ret = 0;
+
+   if (!hdcp->hdcp_shim)
+   return -ENOENT;
+
+   mutex_lock(>hdcp_mutex);
+
+   if (hdcp->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+   goto out;
+
+   if (!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)) {
+   DRM_ERROR("HDCP check failed: link is not encrypted, %x\n",
+  I915_READ(HDCP2_STATUS_DDI(port)));
+   ret = -ENXIO;
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+   schedule_work(>hdcp_prop_work);
+   goto out;
+   }
+
+   ret = hdcp->hdcp_shim->check_2_2_link(intel_dig_port);
+   if (!ret) {
+   if (hdcp->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+   schedule_work(>hdcp_prop_work);
+   }
+   goto out;
+   }
+
+   DRM_INFO("[%s:%d] HDCP2.2 link failed, retrying authentication\n",
+connector->base.name, connector->base.base.id);
+
+   ret = _intel_hdcp2_disable(connector);
+   if (ret) {
+   DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+   schedule_work(>hdcp_prop_work);
+   goto out;
+   }
+
+   ret = _intel_hdcp2_enable(connector);
+   if (ret) {
+   DRM_ERROR("[%s:%d] Failed to enable hdcp2.2 (%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+   schedule_work(>hdcp_prop_work);
+   goto out;
+   }
+
+out:
+   mutex_unlock(>hdcp_mutex);
+   return ret;
+}
+
+static void intel_hdcp2_check_work(struct work_struct *work)
+{
+   struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
+   struct intel_hdcp,
+   hdcp2_check_work);
+   struct intel_connector *connector = container_of(hdcp,
+   struct intel_connector,
+   hdcp);
+
+   if (!intel_hdcp2_check_link(connector))
+   schedule_delayed_work(>hdcp2_check_work,
+ DRM_HDCP2_CHECK_PERIOD_MS);
+}
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index f3f28414b189..b0601215c798 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -11,6 +11,14 @@
 
 /* Period of hdcp checks (to ensure we're still authenticated) */
 #define DRM_HDCP_CHECK_PERIOD_MS   (128 * 16)
+#define DRM_HDCP2_CHECK_PERIOD_MS  500
+
+enum check_link_response {
+   

[Intel-gfx] [PATCH v3 25/40] drm/i915: Enable and Disable HDCP2.2 port encryption

[Ramalingam C]

Implements the enable and disable functions for HDCP2.2 encryption
of the PORT.

v2:
  intel_wait_for_register is used instead of wait_for. [Chris Wilson]
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 54 +++
 1 file changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index d70320da85e4..91cac643f083 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -19,6 +19,7 @@
 (enum hdcp_physical_port) (port))
 #define KEY_LOAD_TRIES 5
 #define HDCP2_LC_RETRY_CNT 3
+#define TIME_FOR_ENCRYPT_STATUS_CHANGE 32
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -1330,3 +1331,56 @@ static int hdcp2_authenticate_sink(struct 
intel_connector *connector)
 
return ret;
 }
+
+static int hdcp2_enable_encryption(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_hdcp *hdcp = >hdcp;
+   enum port port = connector->encoder->port;
+   int ret;
+
+   if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)
+   return 0;
+
+   if (hdcp->hdcp_shim->toggle_signalling)
+   hdcp->hdcp_shim->toggle_signalling(intel_dig_port, true);
+
+   if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
+
+   /* Link is Authenticated. Now set for Encryption */
+   I915_WRITE(HDCP2_CTR_DDI(port),
+  I915_READ(HDCP2_CTR_DDI(port)) |
+  CTL_LINK_ENCRYPTION_REQ);
+   }
+
+   ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS,
+ LINK_ENCRYPTION_STATUS,
+ TIME_FOR_ENCRYPT_STATUS_CHANGE);
+   return ret;
+}
+
+static int hdcp2_disable_encryption(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_hdcp *hdcp = >hdcp;
+   enum port port = connector->encoder->port;
+   int ret;
+
+   if (!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS))
+   return 0;
+
+   I915_WRITE(HDCP2_CTR_DDI(port),
+  I915_READ(HDCP2_CTR_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
+
+   ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS, 0x0,
+ TIME_FOR_ENCRYPT_STATUS_CHANGE);
+
+   if (hdcp->hdcp_shim->toggle_signalling)
+   hdcp->hdcp_shim->toggle_signalling(intel_dig_port, false);
+
+   return ret;
+}
-- 
2.7.4

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[Intel-gfx] [PATCH v3 24/40] drm/i915: Implement HDCP2.2 repeater authentication

[Ramalingam C]

Implements the HDCP2.2 repeaters authentication steps such as verifying
the downstream topology and sending stream management information.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 135 ++
 1 file changed, 135 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index ee9b7519fe73..d70320da85e4 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1145,6 +1145,135 @@ static int hdcp2_session_key_exchange(struct 
intel_connector *connector)
return 0;
 }
 
+/*
+ * Lib endianness functions are aligned for 16/32/64 bits. Since here sequence
+ * num is 24bits developed a small conversion function.
+ */
+static inline void reverse_endianness(u8 *dest, size_t dst_sz, u8 *src)
+{
+   u32 index;
+
+   if (dest != NULL && dst_sz != 0) {
+   for (index = 0; index < dst_sz && index < sizeof(u32);
+index++) {
+   dest[dst_sz - index - 1] = src[index];
+   }
+   }
+}
+
+static
+int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   union {
+   struct hdcp2_rep_stream_manage stream_manage;
+   struct hdcp2_rep_stream_ready stream_ready;
+   } msgs;
+   const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
+   int ret;
+
+   /* Prepare RepeaterAuth_Stream_Manage msg */
+   msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
+   reverse_endianness(msgs.stream_manage.seq_num_m, HDCP_2_2_SEQ_NUM_LEN,
+  (u8 *)>seq_num_m);
+
+   /* K no of streams is fixed as 1. Stored as big-endian. */
+   msgs.stream_manage.k = __swab16(1);
+
+   /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+   msgs.stream_manage.streams[0].stream_id = 0;
+   msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+
+   /* Send it to Repeater */
+   ret = shim->write_2_2_msg(intel_dig_port, _manage,
+ sizeof(msgs.stream_manage));
+   if (ret < 0)
+   return ret;
+
+   ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY,
+_ready, sizeof(msgs.stream_ready));
+   if (ret < 0)
+   return ret;
+
+   hdcp->mei_data.seq_num_m = hdcp->seq_num_m;
+   hdcp->mei_data.streams[0].stream_type = hdcp->content_type;
+
+   ret = hdcp2_verify_mprime(hdcp, _ready);
+   if (ret < 0)
+   return ret;
+
+   hdcp->seq_num_m++;
+
+   if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
+   DRM_DEBUG_KMS("seq_num_m roll over.\n");
+   return -1;
+   }
+   return 0;
+}
+
+static
+int hdcp2_authenticate_repeater_topology(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   union {
+   struct hdcp2_rep_send_receiverid_list recvid_list;
+   struct hdcp2_rep_send_ack rep_ack;
+   } msgs;
+   const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
+   uint8_t *rx_info;
+   uint32_t seq_num_v;
+   int ret;
+
+   ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST,
+_list, sizeof(msgs.recvid_list));
+   if (ret < 0)
+   return ret;
+
+   rx_info = msgs.recvid_list.rx_info;
+
+   if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) ||
+   HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) {
+   DRM_DEBUG_KMS("Topology Max Size Exceeded\n");
+   return -1;
+   }
+
+   /* Converting and Storing the seq_num_v to local variable as DWORD */
+   reverse_endianness((u8 *)_num_v, HDCP_2_2_SEQ_NUM_LEN,
+  msgs.recvid_list.seq_num_v);
+
+   if (seq_num_v < hdcp->seq_num_v) {
+   /* Roll over of the seq_num_v from repeater. Reauthenticate. */
+   DRM_DEBUG_KMS("Seq_num_v roll over.\n");
+   return -1;
+   }
+
+   ret = hdcp2_verify_rep_topology_prepare_ack(hdcp, _list,
+   _ack);
+   if (ret < 0)
+   return ret;
+
+   hdcp->seq_num_v = seq_num_v;
+   ret = shim->write_2_2_msg(intel_dig_port, _ack,
+ sizeof(msgs.rep_ack));
+   if (ret < 0)
+   return ret;
+
+   return 0;
+}
+
+static int hdcp2_authenticate_repeater(struct intel_connector *connector)
+{
+   int ret;
+
+   ret = hdcp2_authenticate_repeater_topology(connector);
+   if (ret < 0)
+   return ret;
+
+   return 

[Intel-gfx] [PATCH v3 26/40] drm/i915: Implement HDCP2.2 En/Dis-able

[Ramalingam C]

Implements a sequence of enabling and disabling the HDCP2.2
(auth and encryption).

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 75 +++
 1 file changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 91cac643f083..005627746ca5 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -21,6 +21,9 @@
 #define HDCP2_LC_RETRY_CNT 3
 #define TIME_FOR_ENCRYPT_STATUS_CHANGE 32
 
+static int _intel_hdcp2_enable(struct intel_connector *connector);
+static int _intel_hdcp2_disable(struct intel_connector *connector);
+
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
 {
@@ -1384,3 +1387,75 @@ static int hdcp2_disable_encryption(struct 
intel_connector *connector)
 
return ret;
 }
+
+static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
+{
+   int ret, i, tries = 3;
+
+   for (i = 0; i < tries; i++) {
+   ret = hdcp2_authenticate_sink(connector);
+   if (!ret)
+   break;
+
+   /* Clearing the mei hdcp session */
+   hdcp2_deauthenticate_port(>hdcp);
+   DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n",
+ i + 1, tries, ret);
+   }
+
+   if (i != tries) {
+
+   /*
+* Ensuring the required 200mSec min time interval between
+* Session Key Exchange and encryption.
+*/
+   msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN);
+   ret = hdcp2_enable_encryption(connector);
+   if (ret < 0) {
+   DRM_DEBUG_KMS("Encryption Enable Failed.(%d)\n", ret);
+   hdcp2_deauthenticate_port(>hdcp);
+   }
+   }
+
+   return ret;
+}
+
+static int _intel_hdcp2_disable(struct intel_connector *connector)
+{
+   int ret;
+
+   DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n",
+ connector->base.name, connector->base.base.id);
+
+   ret = hdcp2_disable_encryption(connector);
+
+   hdcp2_deauthenticate_port(>hdcp);
+
+   return ret;
+}
+
+static int _intel_hdcp2_enable(struct intel_connector *connector)
+{
+   struct intel_hdcp *hdcp = >hdcp;
+   int ret;
+
+   DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being enabled. Type: %d\n",
+ connector->base.name, connector->base.base.id,
+ hdcp->content_type);
+
+   ret = hdcp2_authenticate_and_encrypt(connector);
+   if (ret) {
+   DRM_ERROR("HDCP2 Type%d  Enabling Failed. (%d)\n",
+  hdcp->content_type, ret);
+   return ret;
+   }
+
+   DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is enabled. Type %d\n",
+ connector->base.name, connector->base.base.id,
+ hdcp->content_type);
+
+   hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+   schedule_work(>hdcp_prop_work);
+
+   return 0;
+}
-- 
2.7.4

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[Intel-gfx] [PATCH v3 23/40] drm/i915: Implement HDCP2.2 receiver authentication

[Ramalingam C]

Implements HDCP2.2 authentication for hdcp2.2 receivers, with
following steps:
Authentication and Key enchange (AKE).
Locality Check (LC).
Session Key Exchange(SKE).
DP Errata for stream type confuguration for receivers.

At AKE, the HDCP Receiver’s public key certificate is verified by the
HDCP Transmitter. A Master Key k m is exchanged.

At LC, the HDCP Transmitter enforces locality on the content by
requiring that the Round Trip Time (RTT) between a pair of messages
is not more than 20 ms.

At SKE, The HDCP Transmitter exchanges Session Key ks with
the HDCP Receiver.

In DP HDCP2.2 encryption and decryption logics use the stream type as
one of the parameter. So Before enabling the Encryption DP HDCP2.2
receiver needs to be communicated with stream type. This is added to
spec as ERRATA.

This generic implementation is complete only with the hdcp2_shim
defined.

v2:
  Rebased.
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 184 ++
 1 file changed, 184 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index b4d56b21cf9b..ee9b7519fe73 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -18,6 +18,7 @@
 #define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
 (enum hdcp_physical_port) (port))
 #define KEY_LOAD_TRIES 5
+#define HDCP2_LC_RETRY_CNT 3
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -1011,3 +1012,186 @@ static inline int hdcp2_deauthenticate_port(struct 
intel_hdcp *hdcp)
 {
return hdcp2_close_mei_session(hdcp);
 }
+
+static int hdcp2_authentication_key_exchange(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   union {
+   struct hdcp2_ake_init ake_init;
+   struct hdcp2_ake_send_cert send_cert;
+   struct hdcp2_ake_no_stored_km no_stored_km;
+   struct hdcp2_ake_send_hprime send_hprime;
+   struct hdcp2_ake_send_pairing_info pairing_info;
+   } msgs;
+   const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
+   size_t size;
+   int ret;
+
+   /* Init for seq_num */
+   hdcp->seq_num_v = 0;
+   hdcp->seq_num_m = 0;
+
+   ret = hdcp2_prepare_ake_init(hdcp, _init);
+   if (ret < 0)
+   return ret;
+
+   ret = shim->write_2_2_msg(intel_dig_port, _init,
+ sizeof(msgs.ake_init));
+   if (ret < 0)
+   return ret;
+
+   ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT,
+_cert, sizeof(msgs.send_cert));
+   if (ret < 0)
+   return ret;
+
+   if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL)
+   return -EINVAL;
+
+   hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]);
+
+   /*
+* Here msgs.no_stored_km will hold msgs corresponding to the km
+* stored also.
+*/
+   ret = hdcp2_verify_rx_cert_prepare_km(hdcp, _cert,
+ >is_paired,
+ _stored_km, );
+   if (ret < 0)
+   return ret;
+
+   ret = shim->write_2_2_msg(intel_dig_port, _stored_km, size);
+   if (ret < 0)
+   return ret;
+
+   ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME,
+_hprime, sizeof(msgs.send_hprime));
+   if (ret < 0)
+   return ret;
+
+   ret = hdcp2_verify_hprime(hdcp, _hprime);
+   if (ret < 0)
+   return ret;
+
+   if (!hdcp->is_paired) {
+   /* Pairing is required */
+   ret = shim->read_2_2_msg(intel_dig_port,
+HDCP_2_2_AKE_SEND_PARING_INFO,
+_info,
+sizeof(msgs.pairing_info));
+   if (ret < 0)
+   return ret;
+
+   ret = hdcp2_store_paring_info(hdcp, _info);
+   if (ret < 0)
+   return ret;
+   hdcp->is_paired = true;
+   }
+   return 0;
+}
+
+static int hdcp2_locality_check(struct intel_connector *connector)
+{
+   struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+   struct intel_hdcp *hdcp = >hdcp;
+   union {
+   struct hdcp2_lc_init lc_init;
+   struct hdcp2_lc_send_lprime send_lprime;
+   } msgs;
+   const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
+   int tries = HDCP2_LC_RETRY_CNT, 

[Intel-gfx] [PATCH v3 20/40] drm/i915: Define HDCP2.2 related variables

[Ramalingam C]

For upcoming implementation of HDCP2.2 in I915, important variable
required for HDCP2.2 are defined.

HDCP_shim is extended to support encoder specific HDCP2.2 flows.

v2:
  1.4 shim is extended to support hdcp2.2. [Sean Paul]
  platform's/panel's hdcp ver capability is removed. [Sean Paul]
  mei references in i915_private are moved to later patches. [Chris Wilson]
v3:
  mei_cl_device ref is moved into intel_hdcp

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_drv.h | 61 
 1 file changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fdffcb833cd2..ca06d9a158f6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "i915_drv.h"
 #include 
@@ -375,6 +376,32 @@ struct intel_hdcp_shim {
/* Detects panel's hdcp capability. This is optional for HDMI. */
int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
bool *hdcp_capable);
+
+   /* Write HDCP2.2 messages */
+   int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
+void *buf, size_t size);
+
+   /* Read HDCP2.2 messages */
+   int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
+   uint8_t msg_id, void *buf, size_t size);
+
+   /*
+* Implementation of DP HDCP2.2 Errata for the communication of stream
+* type to Receivers. In DP HDCP2.2 Stream type is one of the input to
+* the HDCP2.2 Chiper for En/De-Cryption. Not applicable for HDMI.
+*/
+   int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
+ void *buf, size_t size);
+
+   /* HDCP2.2 Link Integrity Check */
+   int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
+
+   /* Detects whether Panel is HDCP2.2 capable */
+   int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
+   bool *capable);
+
+   /* Detects the HDCP protocol(DP/HDMI) required on the port */
+   enum hdcp_protocol (*hdcp_protocol)(void);
 };
 
 struct intel_hdcp {
@@ -383,6 +410,40 @@ struct intel_hdcp {
uint64_t hdcp_value; /* protected by hdcp_mutex */
struct delayed_work hdcp_check_work;
struct work_struct hdcp_prop_work;
+
+   /** HDCP2.2 related definitions **/
+   bool hdcp2_supported;
+
+   /*
+* Content Stream Type defined by content owner. TYPE0(0x0) content can
+* flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
+* content can flow only through a link protected by HDCP2.2.
+*/
+   u8 content_type;
+
+   bool is_paired;
+   bool is_repeater;
+
+   /*
+* Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
+* Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
+* When it rolls over re-auth has to be triggered.
+*/
+   uint32_t seq_num_v;
+
+   /*
+* Count of RepeaterAuth_Stream_Manage msg propagated.
+* Initialized to 0 on AKE_INIT. Incremented after every successful
+* transmission of RepeaterAuth_Stream_Manage message. When it rolls
+* over re-Auth has to be triggered.
+*/
+   uint32_t seq_num_m;
+
+   /* mei interface related information */
+   struct mei_cl_device *cldev;
+   struct mei_hdcp_data mei_data;
+
+   struct delayed_work hdcp2_check_work;
 };
 
 struct intel_connector {
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 19/40] drm/i915: wrapping all hdcp var into intel_hdcp

[Ramalingam C]

Considering the upcoming significant no HDCP2.2 variables, it will
be clean to have separate struct fo HDCP.

New structure called intel_hdcp is introduced.

v2:
  struct hdcp statically allocated. [Sean Paul]
  enable and disable function parameters are retained.[Sean Paul]
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_display.c |  7 +--
 drivers/gpu/drm/i915/intel_drv.h | 14 --
 drivers/gpu/drm/i915/intel_hdcp.c| 94 
 3 files changed, 66 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 331084082545..2d7c47135e1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15395,9 +15395,10 @@ static void intel_hpd_poll_fini(struct drm_device *dev)
for_each_intel_connector_iter(connector, _iter) {
if (connector->modeset_retry_work.func)
cancel_work_sync(>modeset_retry_work);
-   if (connector->hdcp_shim) {
-   cancel_delayed_work_sync(>hdcp_check_work);
-   cancel_work_sync(>hdcp_prop_work);
+   if (connector->hdcp.hdcp_shim) {
+   cancel_delayed_work_sync(
+   >hdcp.hdcp_check_work);
+   cancel_work_sync(>hdcp.hdcp_prop_work);
}
}
drm_connector_list_iter_end(_iter);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d4368589b355..fdffcb833cd2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -377,6 +377,14 @@ struct intel_hdcp_shim {
bool *hdcp_capable);
 };
 
+struct intel_hdcp {
+   const struct intel_hdcp_shim *hdcp_shim;
+   struct mutex hdcp_mutex;
+   uint64_t hdcp_value; /* protected by hdcp_mutex */
+   struct delayed_work hdcp_check_work;
+   struct work_struct hdcp_prop_work;
+};
+
 struct intel_connector {
struct drm_connector base;
/*
@@ -409,11 +417,7 @@ struct intel_connector {
/* Work struct to schedule a uevent on link train failure */
struct work_struct modeset_retry_work;
 
-   const struct intel_hdcp_shim *hdcp_shim;
-   struct mutex hdcp_mutex;
-   uint64_t hdcp_value; /* protected by hdcp_mutex */
-   struct delayed_work hdcp_check_work;
-   struct work_struct hdcp_prop_work;
+   struct intel_hdcp hdcp;
 };
 
 struct intel_digital_connector_state {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..1cca4f349064 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -547,6 +547,7 @@ struct intel_digital_port *conn_to_dig_port(struct 
intel_connector *connector)
 
 static int _intel_hdcp_disable(struct intel_connector *connector)
 {
+   struct intel_hdcp *hdcp = >hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
@@ -562,7 +563,7 @@ static int _intel_hdcp_disable(struct intel_connector 
*connector)
return -ETIMEDOUT;
}
 
-   ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
+   ret = hdcp->hdcp_shim->toggle_signalling(intel_dig_port, false);
if (ret) {
DRM_ERROR("Failed to disable HDCP signalling\n");
return ret;
@@ -574,6 +575,7 @@ static int _intel_hdcp_disable(struct intel_connector 
*connector)
 
 static int _intel_hdcp_enable(struct intel_connector *connector)
 {
+   struct intel_hdcp *hdcp = >hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
int i, ret, tries = 3;
 
@@ -599,7 +601,7 @@ static int _intel_hdcp_enable(struct intel_connector 
*connector)
/* Incase of authentication failures, HDCP spec expects reauth. */
for (i = 0; i < tries; i++) {
ret = intel_hdcp_auth(conn_to_dig_port(connector),
- connector->hdcp_shim);
+ hdcp->hdcp_shim);
if (!ret)
return 0;
 
@@ -615,36 +617,42 @@ static int _intel_hdcp_enable(struct intel_connector 
*connector)
 
 static void intel_hdcp_check_work(struct work_struct *work)
 {
-   struct intel_connector *connector = container_of(to_delayed_work(work),
+   struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
+  struct intel_hdcp,
+  hdcp_check_work);
+   struct intel_connector *connector = container_of(hdcp,
 struct intel_connector,
- 

[Intel-gfx] [PATCH v3 16/40] misc/mei/hdcp: Verify M_prime

[Ramalingam C]

Request to ME to verify the M_Prime received from the HDCP sink.

ME FW will calculate the M and compare with M_prime received
as part of RepeaterAuth_Stream_Ready, which is HDCP2.2 protocol msg.

On successful completion of this stage, downstream propagation of
the stream management info is completed.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 79 
 include/linux/mei_hdcp.h |  8 
 2 files changed, 87 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 64fcecfa5b10..68eb5267a8e7 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -553,6 +553,85 @@ mei_repeater_check_flow_prepare_ack(struct mei_cl_device 
*cldev,
 }
 EXPORT_SYMBOL(mei_repeater_check_flow_prepare_ack);
 
+static inline void reverse_endianness(u8 *dest, size_t dst_sz, u8 *src)
+{
+   u32 index;
+
+   if (dest != NULL && dst_sz != 0) {
+   for (index = 0; index < dst_sz && index < sizeof(u32);
+index++) {
+   dest[dst_sz - index - 1] = src[index];
+   }
+   }
+}
+
+/**
+ * mei_verify_mprime:
+ * Function to verify mprime.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @stream_ready   : pointer for RepeaterAuth_Stream_Ready message.
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_verify_mprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_rep_stream_ready *stream_ready)
+{
+   struct wired_cmd_repeater_auth_stream_req_in
+   verify_mprime_in = { { 0 } };
+   struct wired_cmd_repeater_auth_stream_req_out
+   verify_mprime_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!stream_ready || !data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   verify_mprime_in.header.api_version = HDCP_API_VERSION;
+   verify_mprime_in.header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
+   verify_mprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_mprime_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+
+   verify_mprime_in.port.integrated_port_type = data->port_type;
+   verify_mprime_in.port.physical_port = data->port;
+
+   memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
+  HDCP_2_2_MPRIME_LEN);
+   reverse_endianness((u8 *)_mprime_in.seq_num_m,
+  HDCP_2_2_SEQ_NUM_LEN, (u8 *)>seq_num_m);
+   memcpy(verify_mprime_in.streams, data->streams,
+  (data->k * sizeof(struct hdcp2_streamid_type)));
+
+   verify_mprime_in.k = __swab16(data->k);
+
+   byte = mei_cldev_send(cldev, (u8 *)_mprime_in,
+ sizeof(verify_mprime_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_mprime_out,
+ sizeof(verify_mprime_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (verify_mprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+   WIRED_REPEATER_AUTH_STREAM_REQ,
+   verify_mprime_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_verify_mprime);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 46e2dc295d03..dbc216e13f97 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -134,6 +134,8 @@ mei_repeater_check_flow_prepare_ack(struct mei_cl_device 
*cldev,
struct hdcp2_rep_send_receiverid_list
*rep_topology,
struct hdcp2_rep_send_ack *rep_send_ack);
+int mei_verify_mprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_rep_stream_ready *stream_ready);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -201,5 +203,11 @@ mei_repeater_check_flow_prepare_ack(struct mei_cl_device 
*cldev,
 {
return -ENODEV;
 }
+static inline
+int mei_verify_mprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_rep_stream_ready *stream_ready)
+{
+   return -ENODEV;
+}
 #endif /* defined 

[Intel-gfx] [PATCH v3 15/40] misc/mei/hdcp: Repeater topology verifcation and ack

[Ramalingam C]

Request ot ME to verify the downatream topology information received.

ME FW will validate the Repeaters receiver id list and
downstream topology.

On Success ME FW will provide the Least Significant
128bits of VPrime, which forms the repeater ack.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 75 
 include/linux/mei_hdcp.h | 15 
 2 files changed, 90 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index abfcc57863b8..64fcecfa5b10 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -478,6 +478,81 @@ int mei_get_session_key(struct mei_cl_device *cldev, 
struct mei_hdcp_data *data,
 }
 EXPORT_SYMBOL(mei_get_session_key);
 
+/**
+ * mei_repeater_check_flow_prepare_ack:
+ * Function to validate the Downstream topology and prepare rep_ack.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @rep_topology   : Pointer for Receiver Id List to be validated.
+ * @rep_send_ack   : Pointer for repeater ack
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+
+int
+mei_repeater_check_flow_prepare_ack(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_rep_send_receiverid_list
+   *rep_topology,
+   struct hdcp2_rep_send_ack *rep_send_ack)
+{
+   struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } };
+   struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!rep_topology || !rep_send_ack || !data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   verify_repeater_in.header.api_version = HDCP_API_VERSION;
+   verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER;
+   verify_repeater_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_repeater_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
+
+   verify_repeater_in.port.integrated_port_type = data->port_type;
+   verify_repeater_in.port.physical_port = data->port;
+
+   memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
+  HDCP_2_2_RXINFO_LEN);
+   memcpy(verify_repeater_in.seq_num_v, rep_topology->seq_num_v,
+  HDCP_2_2_SEQ_NUM_LEN);
+   memcpy(verify_repeater_in.v_prime, rep_topology->v_prime,
+  HDCP_2_2_LPRIME_HALF_LEN);
+   memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids,
+  HDCP_2_2_RECEIVER_IDS_MAX_LEN);
+
+   byte = mei_cldev_send(cldev, (u8 *)_repeater_in,
+ sizeof(verify_repeater_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_repeater_out,
+ sizeof(verify_repeater_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (verify_repeater_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+   WIRED_VERIFY_REPEATER,
+   verify_repeater_out.header.status);
+   return -1;
+   }
+
+   memcpy(rep_send_ack->v, verify_repeater_out.v,
+  HDCP_2_2_LPRIME_HALF_LEN);
+   rep_send_ack->msg_id = HDCP_2_2_REP_SEND_ACK;
+   return 0;
+}
+EXPORT_SYMBOL(mei_repeater_check_flow_prepare_ack);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 534170d746af..46e2dc295d03 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -128,6 +128,12 @@ int mei_verify_lprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
  struct hdcp2_lc_send_lprime *rx_lprime);
 int mei_get_session_key(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
struct hdcp2_ske_send_eks *ske_data);
+int
+mei_repeater_check_flow_prepare_ack(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_rep_send_receiverid_list
+   *rep_topology,
+   struct hdcp2_rep_send_ack *rep_send_ack);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -186,5 +192,14 @@ int 

[Intel-gfx] [PATCH v3 13/40] misc/mei/hdcp: Verify L_prime

[Ramalingam C]

Request to ME to verify the LPrime received from HDCP sink.

On Success, ME FW will verify the received Lprime by calculating and
comparing with L.

This represents the completion of Locality Check.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 59 
 include/linux/mei_hdcp.h |  8 ++
 2 files changed, 67 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 9bd7e66a91e4..ea84177311b7 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -361,6 +361,65 @@ int mei_initiate_locality_check(struct mei_cl_device 
*cldev,
 }
 EXPORT_SYMBOL(mei_initiate_locality_check);
 
+/**
+ * mei_verify_lprime:
+ * Function to verify lprime.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @rx_lprime  : Pointer for LC_Send_L_prime
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_verify_lprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_lc_send_lprime *rx_lprime)
+{
+   struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } };
+   struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !rx_lprime)
+   return -EINVAL;
+
+   dev = >dev;
+
+   verify_lprime_in.header.api_version = HDCP_API_VERSION;
+   verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY;
+   verify_lprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_lprime_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
+
+   verify_lprime_in.port.integrated_port_type = data->port_type;
+   verify_lprime_in.port.physical_port = data->port;
+
+   memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
+  sizeof(rx_lprime->l_prime));
+
+   byte = mei_cldev_send(cldev, (u8 *)_lprime_in,
+ sizeof(verify_lprime_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_lprime_out,
+ sizeof(verify_lprime_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (verify_lprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+   WIRED_VALIDATE_LOCALITY,
+   verify_lprime_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_verify_lprime);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index d9c4cac0b276..792143563c46 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -124,6 +124,8 @@ int mei_store_pairing_info(struct mei_cl_device *cldev,
 int mei_initiate_locality_check(struct mei_cl_device *cldev,
struct mei_hdcp_data *data,
struct hdcp2_lc_init *lc_init_data);
+int mei_verify_lprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_lc_send_lprime *rx_lprime);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -170,5 +172,11 @@ int mei_initiate_locality_check(struct mei_cl_device 
*cldev,
 {
return -ENODEV;
 }
+static inline
+int mei_verify_lprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_lc_send_lprime *rx_lprime)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 12/40] misc/mei/hdcp: Initiate Locality check

[Ramalingam C]

Requests ME to start the second stage of HDCP2.2 authentication,
called Locality Check.

On Success, ME FW will provide LC_Init message to send to hdcp sink.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 56 
 include/linux/mei_hdcp.h | 10 +++
 2 files changed, 66 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 60afdd0cee79..9bd7e66a91e4 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -305,6 +305,62 @@ int mei_store_pairing_info(struct mei_cl_device *cldev,
 }
 EXPORT_SYMBOL(mei_store_pairing_info);
 
+/**
+ * mei_initiate_locality_check:
+ * Function to prepare LC_Init.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @hdcp2_lc_init  : Pointer for storing LC_Init
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_initiate_locality_check(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_lc_init *lc_init_data)
+{
+   struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } };
+   struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !lc_init_data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   lc_init_in.header.api_version = HDCP_API_VERSION;
+   lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
+   lc_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
+
+   lc_init_in.port.integrated_port_type = data->port_type;
+   lc_init_in.port.physical_port = data->port;
+
+   byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_init_out, sizeof(lc_init_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (lc_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X Failed. status: 0x%X\n",
+   WIRED_INIT_LOCALITY_CHECK, lc_init_out.header.status);
+   return -1;
+   }
+
+   lc_init_data->msg_id = HDCP_2_2_LC_INIT;
+   memcpy(lc_init_data->r_n, lc_init_out.r_n, HDCP_2_2_RN_LEN);
+   return 0;
+}
+EXPORT_SYMBOL(mei_initiate_locality_check);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index be16e49d8018..d9c4cac0b276 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -121,6 +121,9 @@ int mei_verify_hprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 int mei_store_pairing_info(struct mei_cl_device *cldev,
   struct mei_hdcp_data *data,
   struct hdcp2_ake_send_pairing_info *pairing_info);
+int mei_initiate_locality_check(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_lc_init *lc_init_data);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -160,5 +163,12 @@ int mei_store_pairing_info(struct mei_cl_device *cldev,
 {
return -ENODEV;
 }
+static inline
+int mei_initiate_locality_check(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_lc_init *lc_init_data)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 22/40] drm/i915: Wrappers for mei HDCP2.2 services

[Ramalingam C]

Adds the wrapper for all mei hdcp2.2 service functions.

v2:
  Rebased.
v3:
  cldev is moved from mei_hdcp_data to hdcp.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_hdcp.c | 194 ++
 1 file changed, 194 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
b/drivers/gpu/drm/i915/intel_hdcp.c
index 1cca4f349064..b4d56b21cf9b 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -10,10 +10,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "intel_drv.h"
 #include "i915_reg.h"
 
+#define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
+(enum hdcp_physical_port) (port))
 #define KEY_LOAD_TRIES 5
 
 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
@@ -817,3 +820,194 @@ int intel_hdcp_check_link(struct intel_connector 
*connector)
mutex_unlock(>hdcp_mutex);
return ret;
 }
+
+static int
+hdcp2_prepare_ake_init(struct intel_hdcp *hdcp, struct hdcp2_ake_init 
*ake_data)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   struct intel_connector *connector = container_of(hdcp,
+struct intel_connector,
+hdcp);
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   if (data->port == INVALID_PORT && connector->encoder)
+   data->port = GET_MEI_DDI_INDEX(connector->encoder->port);
+
+   /* Clear ME FW instance for the port, just incase */
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return mei_initiate_hdcp2_session(hdcp->cldev, data, ake_data);
+}
+
+static int hdcp2_close_mei_session(struct intel_hdcp *hdcp)
+{
+   struct mei_hdcp_data *data = >mei_data;
+
+   if (!hdcp->cldev || data->port == INVALID_PORT)
+   return -EINVAL;
+
+   return mei_close_hdcp_session(hdcp->cldev, data);
+}
+
+static int
+hdcp2_verify_rx_cert_prepare_km(struct intel_hdcp *hdcp,
+   struct hdcp2_ake_send_cert *rx_cert,
+   bool *paired,
+   struct hdcp2_ake_no_stored_km *ek_pub_km,
+   size_t *msg_sz)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_verify_receiver_cert_prepare_km(hdcp->cldev, data, rx_cert,
+ paired, ek_pub_km, msg_sz);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int hdcp2_verify_hprime(struct intel_hdcp *hdcp,
+  struct hdcp2_ake_send_hprime *rx_hprime)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_verify_hprime(hdcp->cldev, data, rx_hprime);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int
+hdcp2_store_paring_info(struct intel_hdcp *hdcp,
+   struct hdcp2_ake_send_pairing_info *pairing_info)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_store_pairing_info(hdcp->cldev, data, pairing_info);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int
+hdcp2_prepare_lc_init(struct intel_hdcp *hdcp, struct hdcp2_lc_init *lc_init)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_initiate_locality_check(hdcp->cldev, data, lc_init);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int
+hdcp2_verify_lprime(struct intel_hdcp *hdcp,
+   struct hdcp2_lc_send_lprime *rx_lprime)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_verify_lprime(hdcp->cldev, data, rx_lprime);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int hdcp2_prepare_skey(struct intel_hdcp *hdcp,
+ struct hdcp2_ske_send_eks *ske_data)
+{
+   struct mei_hdcp_data *data = >mei_data;
+   int ret;
+
+   if (!hdcp->cldev)
+   return -EINVAL;
+
+   ret = mei_get_session_key(hdcp->cldev, data, ske_data);
+   if (ret < 0)
+   mei_close_hdcp_session(hdcp->cldev, data);
+
+   return ret;
+}
+
+static int
+hdcp2_verify_rep_topology_prepare_ack(
+   struct intel_hdcp *hdcp,
+   struct 

[Intel-gfx] [PATCH v3 18/40] misc/mei/hdcp: Closing wired HDCP2.2 Tx Session

[Ramalingam C]

Request the ME to terminate the HDCP2.2 session for a port.

On Success, ME FW will mark the intel port as Deauthenticated and
terminate the wired HDCP2.2 Tx session started due to the cmd
WIRED_INITIATE_HDCP2_SESSION.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 55 
 include/linux/mei_hdcp.h |  7 +
 2 files changed, 62 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index b5d1da41f1d9..ed402f1f2f64 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -686,6 +686,61 @@ int mei_enable_hdcp_authentication(struct mei_cl_device 
*cldev,
 }
 EXPORT_SYMBOL(mei_enable_hdcp_authentication);
 
+/**
+ * me_close_hdcp_session:
+ * Function to close the Wired HDCP Tx session of ME FW.
+ * This also disables the authenticated state of the port.
+ *
+ * @data   : Intel HW specific Data
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_close_hdcp_session(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data)
+{
+   struct wired_cmd_close_session_in session_close_in = { { 0 } };
+   struct wired_cmd_close_session_out session_close_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   session_close_in.header.api_version = HDCP_API_VERSION;
+   session_close_in.header.command_id = WIRED_CLOSE_SESSION;
+   session_close_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   session_close_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
+
+   session_close_in.port.integrated_port_type = data->port_type;
+   session_close_in.port.physical_port = data->port;
+
+
+   byte = mei_cldev_send(cldev, (u8 *)_close_in,
+ sizeof(session_close_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_close_out,
+ sizeof(session_close_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (session_close_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "Session Close Failed. status: 0x%X\n",
+   session_close_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_close_hdcp_session);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 2366d0741abe..55cbde890571 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -138,6 +138,8 @@ int mei_verify_mprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
  struct hdcp2_rep_stream_ready *stream_ready);
 int mei_enable_hdcp_authentication(struct mei_cl_device *cldev,
   struct mei_hdcp_data *data);
+int mei_close_hdcp_session(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -216,5 +218,10 @@ static inline int mei_enable_hdcp_authentication(struct 
mei_cl_device *cldev,
 {
return -ENODEV;
 }
+static inline int mei_close_hdcp_session(struct mei_cl_device *cldev,
+struct mei_hdcp_data *data)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 17/40] misc/mei/hdcp: Enabling the HDCP authentication

[Ramalingam C]

Request to ME to configure a port as authenticated.

On Success, ME FW will mark th eport as authenticated and provides
HDCP chiper of the port with the encryption keys.

Enabling the Authentication can be requested once the all
stages of HDCP2.2 authentication is completed by interating with
ME FW.

Only after this stage, driver can enable the HDCP encryption for
the port, through HW registers.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 54 
 include/linux/mei_hdcp.h |  7 ++
 2 files changed, 61 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 68eb5267a8e7..b5d1da41f1d9 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -632,6 +632,60 @@ int mei_verify_mprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 }
 EXPORT_SYMBOL(mei_verify_mprime);
 
+/**
+ * mei_enable_hdcp_authentication:
+ * Function to request ME FW to mark a port as authenticated.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_enable_hdcp_authentication(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data)
+{
+   struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } };
+   struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   enable_auth_in.header.api_version = HDCP_API_VERSION;
+   enable_auth_in.header.command_id = WIRED_ENABLE_AUTH;
+   enable_auth_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
+
+   enable_auth_in.port.integrated_port_type = data->port_type;
+   enable_auth_in.port.physical_port = data->port;
+   enable_auth_in.stream_type = data->streams[0].stream_type;
+
+   byte = mei_cldev_send(cldev, (u8 *)_auth_in,
+ sizeof(enable_auth_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_auth_out,
+ sizeof(enable_auth_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (enable_auth_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+   WIRED_ENABLE_AUTH, enable_auth_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_enable_hdcp_authentication);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index dbc216e13f97..2366d0741abe 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -136,6 +136,8 @@ mei_repeater_check_flow_prepare_ack(struct mei_cl_device 
*cldev,
struct hdcp2_rep_send_ack *rep_send_ack);
 int mei_verify_mprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
  struct hdcp2_rep_stream_ready *stream_ready);
+int mei_enable_hdcp_authentication(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -209,5 +211,10 @@ int mei_verify_mprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 {
return -ENODEV;
 }
+static inline int mei_enable_hdcp_authentication(struct mei_cl_device *cldev,
+struct mei_hdcp_data *data)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers

[Ramalingam C]

Intel HDCP2.2 registers are defined with addr offsets and bit details.

v2:
  Replaced the arith calc with _PICK [Sean Paul]
v3:
  No changes.

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/i915_reg.h | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6a8c0ee7df1..f04ad3c15abd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8649,6 +8649,38 @@ enum skl_power_gate {
 #define  HDCP_STATUS_CIPHERBIT(16)
 #define  HDCP_STATUS_FRAME_CNT(x)  ((x >> 8) & 0xff)
 
+/* HDCP2.2 Registers */
+#define _PORTA_HDCP2_BASE  0x66800
+#define _PORTB_HDCP2_BASE  0x66500
+#define _PORTC_HDCP2_BASE  0x66600
+#define _PORTD_HDCP2_BASE  0x66700
+#define _PORTE_HDCP2_BASE  0x66A00
+#define _PORTF_HDCP2_BASE  0x66900
+#define _PORT_HDCP2_BASE(port, x)  _MMIO(_PICK(port, \
+ _PORTA_HDCP2_BASE, \
+ _PORTB_HDCP2_BASE, \
+ _PORTC_HDCP2_BASE, \
+ _PORTD_HDCP2_BASE, \
+ _PORTE_HDCP2_BASE, \
+ _PORTF_HDCP2_BASE) + x)
+
+#define HDCP2_AUTH_DDI(port)   _PORT_HDCP2_BASE(port, 0x98)
+#define   AUTH_LINK_AUTHENTICATED  BIT(31)
+#define   AUTH_LINK_TYPE   BIT(30)
+#define   AUTH_FORCE_CLR_INPUTCTR  BIT(19)
+#define   AUTH_CLR_KEYSBIT(18)
+
+#define HDCP2_CTR_DDI(port)_PORT_HDCP2_BASE(port, 0xB0)
+#define   CTL_LINK_ENCRYPTION_REQ  BIT(31)
+
+#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
+#define   STREAM_ENCRYPTION_STATUS_A   BIT(31)
+#define   STREAM_ENCRYPTION_STATUS_B   BIT(30)
+#define   STREAM_ENCRYPTION_STATUS_C   BIT(29)
+#define   LINK_TYPE_STATUS BIT(22)
+#define   LINK_AUTH_STATUS BIT(21)
+#define   LINK_ENCRYPTION_STATUS   BIT(20)
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A  0x60400
 #define _TRANS_DDI_FUNC_CTL_B  0x61400
-- 
2.7.4

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[Intel-gfx] [PATCH v3 11/40] misc/mei/hdcp: Store the HDCP Pairing info

[Ramalingam C]

Provides Pairing info to ME to store.

Pairing is a process to fast track the subsequent authentication
with the same HDCP sink.

On Success, received HDCP pairing info is stored in non-volatile
memory of ME.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 61 
 include/linux/mei_hdcp.h | 10 +++
 2 files changed, 71 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index fa548310de7a..60afdd0cee79 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -244,6 +244,67 @@ int mei_verify_hprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 }
 EXPORT_SYMBOL(mei_verify_hprime);
 
+/**
+ * mei_store_pairing_info:
+ * Function to store pairing info received from panel
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @pairing_info   : Pointer for AKE_Send_Pairing_Info
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+
+int mei_store_pairing_info(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_send_pairing_info *pairing_info)
+{
+   struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } };
+   struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !pairing_info)
+   return -EINVAL;
+
+   dev = >dev;
+
+   pairing_info_in.header.api_version = HDCP_API_VERSION;
+   pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
+   pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   pairing_info_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
+
+   pairing_info_in.port.integrated_port_type = data->port_type;
+   pairing_info_in.port.physical_port = data->port;
+
+   memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
+  sizeof(pairing_info_in.e_kh_km));
+
+   byte = mei_cldev_send(cldev, (u8 *)_info_in,
+ sizeof(pairing_info_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_info_out,
+ sizeof(pairing_info_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",
+   WIRED_AKE_SEND_PAIRING_INFO,
+   pairing_info_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_store_pairing_info);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 00bfde251ba4..be16e49d8018 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -118,6 +118,9 @@ mei_verify_receiver_cert_prepare_km(struct mei_cl_device 
*cldev,
size_t *msg_sz);
 int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
  struct hdcp2_ake_send_hprime *rx_hprime);
+int mei_store_pairing_info(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_send_pairing_info *pairing_info);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -150,5 +153,12 @@ int mei_verify_hprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 {
return -ENODEV;
 }
+static inline
+int mei_store_pairing_info(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_send_pairing_info *pairing_info)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 14/40] misc/mei/hdcp: Prepare Session Key

[Ramalingam C]

Request to ME to prepare the encrypted session key.

On Success, ME provides Encrypted session key. Functions populates
the HDCP2.2 authentication msg SKE_Send_Eks.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 58 
 include/linux/mei_hdcp.h |  8 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index ea84177311b7..abfcc57863b8 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -420,6 +420,64 @@ int mei_verify_lprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 }
 EXPORT_SYMBOL(mei_verify_lprime);
 
+/**
+ * mei_get_session_key:
+ * Function to prepare SKE_Send_Eks.
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @ske_data   : Pointer for SKE_Send_Eks.
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_get_session_key(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
+   struct hdcp2_ske_send_eks *ske_data)
+{
+   struct wired_cmd_get_session_key_in get_skey_in = { { 0 } };
+   struct wired_cmd_get_session_key_out get_skey_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !ske_data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   get_skey_in.header.api_version = HDCP_API_VERSION;
+   get_skey_in.header.command_id = WIRED_GET_SESSION_KEY;
+   get_skey_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
+
+   get_skey_in.port.integrated_port_type = data->port_type;
+   get_skey_in.port.physical_port = data->port;
+
+   byte = mei_cldev_send(cldev, (u8 *)_skey_in, sizeof(get_skey_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_skey_out, sizeof(get_skey_out));
+
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (get_skey_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+   WIRED_GET_SESSION_KEY, get_skey_out.header.status);
+   return -1;
+   }
+
+   ske_data->msg_id = HDCP_2_2_SKE_SEND_EKS;
+   memcpy(ske_data->e_dkey_ks, get_skey_out.e_dkey_ks,
+  HDCP_2_2_E_DKEY_KS_LEN);
+   memcpy(ske_data->riv, get_skey_out.r_iv, HDCP_2_2_RIV_LEN);
+   return 0;
+}
+EXPORT_SYMBOL(mei_get_session_key);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 792143563c46..534170d746af 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -126,6 +126,8 @@ int mei_initiate_locality_check(struct mei_cl_device *cldev,
struct hdcp2_lc_init *lc_init_data);
 int mei_verify_lprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
  struct hdcp2_lc_send_lprime *rx_lprime);
+int mei_get_session_key(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
+   struct hdcp2_ske_send_eks *ske_data);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -178,5 +180,11 @@ int mei_verify_lprime(struct mei_cl_device *cldev, struct 
mei_hdcp_data *data,
 {
return -ENODEV;
 }
+static inline
+int mei_get_session_key(struct mei_cl_device *cldev, struct mei_hdcp_data 
*data,
+   struct hdcp2_ske_send_eks *ske_data)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 10/40] misc/mei/hdcp: Verify H_prime

[Ramalingam C]

Requests for the verifcation of AKE_Send_H_prime.

ME will calculation the H and comparing it with received H_Prime.
Here AKE_Send_H_prime is a HDCP2.2 Authentication msg.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 58 
 include/linux/mei_hdcp.h |  8 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 181994529058..fa548310de7a 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -186,6 +186,64 @@ mei_verify_receiver_cert_prepare_km(struct mei_cl_device 
*cldev,
 }
 EXPORT_SYMBOL(mei_verify_receiver_cert_prepare_km);
 
+/**
+ * mei_verify_hprime:
+ * Function to verify AKE_Send_H_prime received
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @rx_hprime  : Pointer for AKE_Send_H_prime
+ * @hprime_sz  : Input buffer size
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_ake_send_hprime *rx_hprime)
+{
+   struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } };
+   struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !rx_hprime)
+   return -EINVAL;
+
+   dev = >dev;
+
+   send_hprime_in.header.api_version = HDCP_API_VERSION;
+   send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
+   send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
+
+   send_hprime_in.port.integrated_port_type = data->port_type;
+   send_hprime_in.port.physical_port = data->port;
+
+   memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
+  sizeof(rx_hprime->h_prime));
+
+   byte = mei_cldev_send(cldev, (u8 *)_hprime_in,
+ sizeof(send_hprime_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_hprime_out,
+ sizeof(send_hprime_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+   WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
+   return -1;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(mei_verify_hprime);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 314b15f6afc0..00bfde251ba4 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -116,6 +116,8 @@ mei_verify_receiver_cert_prepare_km(struct mei_cl_device 
*cldev,
bool *km_stored,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz);
+int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_ake_send_hprime *rx_hprime);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -142,5 +144,11 @@ mei_verify_receiver_cert_prepare_km(struct mei_cl_device 
*cldev,
 {
return -ENODEV;
 }
+static inline
+int mei_verify_hprime(struct mei_cl_device *cldev, struct mei_hdcp_data *data,
+ struct hdcp2_ake_send_hprime *rx_hprime)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 06/40] misc/mei/hdcp: Define ME FW interface for HDCP2.2

[Ramalingam C]

Defines the HDCP specific ME FW interfaces such as Request CMDs,
payload structure for CMDs and their response status codes.

This patch defines payload size(Excluding the Header)for each WIRED
HDCP2.2 CMDs.

v2:
  Rebased.
v3:
  Extra comments are removed.

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.h | 415 +++
 1 file changed, 415 insertions(+)
 create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.h

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h b/drivers/misc/mei/hdcp/mei_hdcp.h
new file mode 100644
index ..59d8069a8586
--- /dev/null
+++ b/drivers/misc/mei/hdcp/mei_hdcp.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ramalingam C 
+ */
+
+#ifndef __MEI_HDCP_H__
+#define __MEI_HDCP_H__
+
+#include 
+
+/**
+ * me_hdcp_status: Enumeration of all HDCP Status Codes
+ */
+enum me_hdcp_status {
+   ME_HDCP_STATUS_SUCCESS  = 0x,
+
+   /* WiDi Generic Status Codes */
+   ME_HDCP_STATUS_INTERNAL_ERROR   = 0x1000,
+   ME_HDCP_STATUS_UNKNOWN_ERROR= 0x1001,
+   ME_HDCP_STATUS_INCORRECT_API_VERSION= 0x1002,
+   ME_HDCP_STATUS_INVALID_FUNCTION = 0x1003,
+   ME_HDCP_STATUS_INVALID_BUFFER_LENGTH= 0x1004,
+   ME_HDCP_STATUS_INVALID_PARAMS   = 0x1005,
+   ME_HDCP_STATUS_AUTHENTICATION_FAILED= 0x1006,
+
+   /* WiDi Status Codes */
+   ME_HDCP_INVALID_SESSION_STATE   = 0x6000,
+   ME_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001,
+   ME_HDCP_SRM_INVALID_LENGTH  = 0x6002,
+   ME_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003,
+   ME_HDCP_SRM_VERIFICATION_FAILED = 0x6004,
+   ME_HDCP_SRM_VERSION_TOO_OLD = 0x6005,
+   ME_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006,
+   ME_HDCP_RX_REVOKED  = 0x6007,
+   ME_HDCP_H_VERIFICATION_FAILED   = 0x6008,
+   ME_HDCP_REPEATER_CHECK_UNEXPECTED   = 0x6009,
+   ME_HDCP_TOPOLOGY_MAX_EXCEEDED   = 0x600A,
+   ME_HDCP_V_VERIFICATION_FAILED   = 0x600B,
+   ME_HDCP_L_VERIFICATION_FAILED   = 0x600C,
+   ME_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D,
+   ME_HDCP_BASE_KEY_RESET_FAILED   = 0x600E,
+   ME_HDCP_NONCE_GENERATION_FAILED = 0x600F,
+   ME_HDCP_STATUS_INVALID_E_KEY_STATE  = 0x6010,
+   ME_HDCP_STATUS_INVALID_CS_ICV   = 0x6011,
+   ME_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012,
+   ME_HDCP_STATUS_INVALID_PAVP_MODE_ICV= 0x6013,
+   ME_HDCP_STATUS_INVALID_PAVP_MODE= 0x6014,
+   ME_HDCP_STATUS_LC_MAX_ATTEMPTS  = 0x6015,
+
+   /* New status for HDCP 2.1 */
+   ME_HDCP_STATUS_MISMATCH_IN_M= 0x6016,
+
+   /* New status code for HDCP 2.2 Rx */
+   ME_HDCP_STATUS_RX_PROV_NOT_ALLOWED  = 0x6017,
+   ME_HDCP_STATUS_RX_PROV_WRONG_SUBJECT= 0x6018,
+   ME_HDCP_RX_NEEDS_PROVISIONING   = 0x6019,
+   ME_HDCP_BKSV_ICV_AUTH_FAILED= 0x6020,
+   ME_HDCP_STATUS_INVALID_STREAM_ID= 0x6021,
+   ME_HDCP_STATUS_CHAIN_NOT_INITIALIZED= 0x6022,
+   ME_HDCP_FAIL_NOT_EXPECTED   = 0x6023,
+   ME_HDCP_FAIL_HDCP_OFF   = 0x6024,
+   ME_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE   = 0x6025,
+   ME_HDCP_FAIL_AES_ECB_FAILURE= 0x6026,
+   ME_HDCP_FEATURE_NOT_SUPPORTED   = 0x6027,
+   ME_HDCP_DMA_READ_ERROR  = 0x6028,
+   ME_HDCP_DMA_WRITE_ERROR = 0x6029,
+   ME_HDCP_FAIL_INVALID_PACKET_SIZE= 0x6030,
+   ME_HDCP_H264_PARSING_ERROR  = 0x6031,
+   

[Intel-gfx] [PATCH v3 09/40] misc/mei/hdcp: Verify Receiver Cert and prepare km

[Ramalingam C]

Requests for verification for receiver certification and also the
preparation for next AKE auth message with km.

On Success ME FW validate the HDCP2.2 receivers certificate and do the
revocation check on the receiver ID. AKE_Stored_Km will be prepared if
the receiver is already paired, else AKE_No_Stored_Km will be prepared.

Here AKE_Stored_Km and AKE_No_Stored_Km are HDCP2.2 protocol msgs.

v2:
  Rebased.
v3:
  cldev is passed as first parameter [Tomas]
  Redundant comments and cast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 82 
 include/linux/mei_hdcp.h | 17 +
 2 files changed, 99 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 7caee0947761..181994529058 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -104,6 +104,88 @@ int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
 }
 EXPORT_SYMBOL(mei_initiate_hdcp2_session);
 
+/**
+ * mei_verify_receiver_cert_prepare_km:
+ * Function to verify the Receiver Certificate AKE_Send_Cert
+ * and prepare AKE_Stored_Km or AKE_No_Stored_Km
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @rx_cert: Pointer for AKE_Send_Cert
+ * @km_stored  : Pointer for pairing status flag
+ * @ek_pub_km  : Pointer for output msg
+ * @msg_sz : Pointer for size of AKE_X_Km
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+int
+mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
+   struct mei_hdcp_data *data,
+   struct hdcp2_ake_send_cert *rx_cert,
+   bool *km_stored,
+   struct hdcp2_ake_no_stored_km *ek_pub_km,
+   size_t *msg_sz)
+{
+   struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } };
+   struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz)
+   return -EINVAL;
+
+   dev = >dev;
+
+   verify_rxcert_in.header.api_version = HDCP_API_VERSION;
+   verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
+   verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_rxcert_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
+
+   verify_rxcert_in.port.integrated_port_type = data->port_type;
+   verify_rxcert_in.port.physical_port = data->port;
+
+   memcpy(_rxcert_in.cert_rx, _cert->cert_rx,
+  sizeof(rx_cert->cert_rx));
+   memcpy(verify_rxcert_in.r_rx, _cert->r_rx, sizeof(rx_cert->r_rx));
+   memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN);
+
+   byte = mei_cldev_send(cldev, (u8 *)_rxcert_in,
+ sizeof(verify_rxcert_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed: %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_rxcert_out,
+ sizeof(verify_rxcert_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed: %d\n", (int)byte);
+   return byte;
+   }
+
+   if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+   WIRED_VERIFY_RECEIVER_CERT,
+   verify_rxcert_out.header.status);
+   return -1;
+   }
+
+   *km_stored = verify_rxcert_out.km_stored;
+   if (verify_rxcert_out.km_stored) {
+   ek_pub_km->msg_id = HDCP_2_2_AKE_STORED_KM;
+   *msg_sz = sizeof(struct hdcp2_ake_stored_km);
+   } else {
+   ek_pub_km->msg_id = HDCP_2_2_AKE_NO_STORED_KM;
+   *msg_sz = sizeof(struct hdcp2_ake_no_stored_km);
+   }
+
+   memcpy(ek_pub_km->e_kpub_km, _rxcert_out.ekm_buff,
+  sizeof(verify_rxcert_out.ekm_buff));
+   return 0;
+}
+EXPORT_SYMBOL(mei_verify_receiver_cert_prepare_km);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index bb4f27d3abcb..314b15f6afc0 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -109,6 +109,13 @@ int mei_cldev_unregister_notify(struct notifier_block *nb);
 int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
   struct mei_hdcp_data *data,
   struct hdcp2_ake_init *ake_data);
+int
+mei_verify_receiver_cert_prepare_km(struct mei_cl_device 

[Intel-gfx] [PATCH v3 07/40] linux/mei: Header for mei_hdcp driver interface

[Ramalingam C]

Data structures and Enum for the I915-MEI_HDCP interface are defined
at 

v2:
  Rebased.
v3:
  mei_cl_device is removed from mei_hdcp_data [Tomas]

Signed-off-by: Ramalingam C 
---
 include/linux/mei_hdcp.h | 70 
 1 file changed, 70 insertions(+)

diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 3b46bebde718..634c1a5bdf1e 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -27,11 +27,81 @@
 #ifndef _LINUX_MEI_HDCP_H
 #define _LINUX_MEI_HDCP_H
 
+#include 
+
 enum mei_cldev_state {
MEI_CLDEV_DISABLED,
MEI_CLDEV_ENABLED
 };
 
+/*
+ * Enumeration of the physical DDI available on the platform
+ */
+enum hdcp_physical_port {
+   INVALID_PORT = 0x00,/* Not a valid port */
+
+   DDI_RANGE_BEGIN = 0x01, /* Beginning of the valid DDI port range */
+   DDI_B   = 0x01, /* Port DDI B */
+   DDI_C   = 0x02, /* Port DDI C */
+   DDI_D   = 0x03, /* Port DDI D */
+   DDI_E   = 0x04, /* Port DDI E */
+   DDI_F   = 0x05, /* Port DDI F */
+   DDI_A   = 0x07, /* Port DDI A */
+   DDI_RANGE_END   = DDI_A,/* End of the valid DDI port range */
+};
+
+/* The types of HDCP 2.2 ports supported */
+enum hdcp_integrated_port_type {
+   HDCP_INVALID_TYPE   = 0x00,
+
+   /* HDCP 2.x ports that are integrated into Intel HW */
+   INTEGRATED  = 0x01,
+
+   /* HDCP2.2 discrete wired Tx port with LSPCON (HDMI 2.0) solution */
+   LSPCON  = 0x02,
+
+   /* HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3) solution */
+   CPDP= 0x03,
+};
+
+/**
+ * wired_protocol: Supported integrated wired HDCP protocol.
+ * Based on this value, Minor differenceneeded between wired specifications
+ * are handled.
+ */
+enum hdcp_protocol {
+   HDCP_PROTOCOL_INVALID,
+   HDCP_PROTOCOL_HDMI,
+   HDCP_PROTOCOL_DP
+};
+
+/**
+ * mei_hdcp_data: Input data to the mei_hdcp APIs.
+ */
+struct mei_hdcp_data {
+   enum hdcp_physical_port port;
+   enum hdcp_integrated_port_type port_type;
+   enum hdcp_protocol protocol;
+
+   /*
+* No of streams transmitted on a port.
+* In case of HDMI & DP SST, single stream will be
+* transmitted on a port.
+*/
+   uint16_t k;
+
+   /*
+* Count of RepeaterAuth_Stream_Manage msg propagated.
+* Initialized to 0 on AKE_INIT. Incremented after every successful
+* transmission of RepeaterAuth_Stream_Manage message. When it rolls
+* over re-Auth has to be triggered.
+*/
+   uint32_t seq_num_m;
+
+   /* k(No of Streams per port) x structure of wired_streamid_type */
+   struct hdcp2_streamid_type *streams;
+};
+
 #ifdef CONFIG_INTEL_MEI_HDCP
 int mei_cldev_register_notify(struct notifier_block *nb);
 int mei_cldev_unregister_notify(struct notifier_block *nb);
-- 
2.7.4

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[Intel-gfx] [PATCH v3 05/40] misc/mei/hdcp: Notifier chain for mei cldev state change

[Ramalingam C]

Notifier Chain is defined to inform all its clients about the mei
client device state change. Routine is defined for the clients to
register and unregister for the notification on state change.

v2:
  Rebased.
v3:
  Notifier chain is adopted for cldev state update [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 36 +++---
 include/linux/mei_hdcp.h | 48 
 2 files changed, 81 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/mei_hdcp.h

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index b334615728a7..2811a25f8c57 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -31,6 +31,32 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+
+static BLOCKING_NOTIFIER_HEAD(mei_cldev_notifier_list);
+
+void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
+{
+   if (enabled)
+   blocking_notifier_call_chain(_cldev_notifier_list,
+MEI_CLDEV_ENABLED, cldev);
+   else
+   blocking_notifier_call_chain(_cldev_notifier_list,
+MEI_CLDEV_DISABLED, NULL);
+}
+
+int mei_cldev_register_notify(struct notifier_block *nb)
+{
+   return blocking_notifier_chain_register(_cldev_notifier_list, nb);
+}
+EXPORT_SYMBOL_GPL(mei_cldev_register_notify);
+
+int mei_cldev_unregister_notify(struct notifier_block *nb)
+{
+   return blocking_notifier_chain_unregister(_cldev_notifier_list, nb);
+}
+EXPORT_SYMBOL_GPL(mei_cldev_unregister_notify);
 
 static int mei_hdcp_probe(struct mei_cl_device *cldev,
  const struct mei_cl_device_id *id)
@@ -38,14 +64,18 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev,
int ret;
 
ret = mei_cldev_enable(cldev);
-   if (ret < 0)
+   if (ret < 0) {
dev_err(>dev, "mei_cldev_enable Failed. %d\n", ret);
+   return ret;
+   }
 
-   return ret;
+   mei_cldev_state_notify_clients(cldev, true);
+   return 0;
 }
 
 static int mei_hdcp_remove(struct mei_cl_device *cldev)
 {
+   mei_cldev_state_notify_clients(cldev, false);
mei_cldev_set_drvdata(cldev, NULL);
return mei_cldev_disable(cldev);
 }
@@ -71,4 +101,4 @@ module_mei_cl_driver(mei_hdcp_driver);
 
 MODULE_AUTHOR("Intel Corporation");
 MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DESCRIPTION("HDCP");
+MODULE_DESCRIPTION("MEI HDCP");
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
new file mode 100644
index ..3b46bebde718
--- /dev/null
+++ b/include/linux/mei_hdcp.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Authors:
+ * Ramalingam C 
+ */
+
+#ifndef _LINUX_MEI_HDCP_H
+#define _LINUX_MEI_HDCP_H
+
+enum mei_cldev_state {
+   MEI_CLDEV_DISABLED,
+   MEI_CLDEV_ENABLED
+};
+
+#ifdef CONFIG_INTEL_MEI_HDCP
+int mei_cldev_register_notify(struct notifier_block *nb);
+int mei_cldev_unregister_notify(struct notifier_block *nb);
+#else
+static int mei_cldev_register_notify(struct notifier_block *nb)
+{
+   return -ENODEV;
+}
+static int mei_cldev_unregister_notify(struct notifier_block *nb)
+{
+   return -ENODEV;
+}
+#endif /* defined (CONFIG_INTEL_MEI_HDCP) */
+#endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 04/40] misc/mei/hdcp: Client driver for HDCP application

[Ramalingam C]

ME FW is contributes a vital role in HDCP2.2 authentication.
HDCP2.2 driver needs to communicate to ME FW for each step of the
HDCP2.2 authentication.

ME FW prepare and HDCP2.2 authentication  parameters and encrypt them
as per spec. With such parameter Driver prepares HDCP2.2 auth messages
and communicate with HDCP2.2 sink.

Similarly HDCP2. sink's response is shared with ME FW for decrypt and
verification.

Once All the steps of HDCP2.2 authentications are complete on driver's
request ME FW will configure the port as authenticated and supply the
HDCP keys to the Gen HW for encryption.

Only after this stage HDCP2.2 driver can start the HDCP2.2 encryption
for a port.

ME FW is interfaced to kernel through MEI Bus Driver. To obtain the
HDCP2.2 services from the ME FW through MEI Bus driver MEI Client
Driver is developed.

v2:
  hdcp files are moved to drivers/misc/mei/hdcp/ [Tomas]
v3:
  Squashed the Kbuild support [Tomas]
  UUID renamed and Module License is modified [Tomas]
  drv_data is set to null at remove [Tomas]

Signed-off-by: Ramalingam C 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/Kconfig |  6 
 drivers/misc/mei/Makefile|  2 ++
 drivers/misc/mei/hdcp/Makefile   |  6 
 drivers/misc/mei/hdcp/mei_hdcp.c | 74 
 4 files changed, 88 insertions(+)
 create mode 100644 drivers/misc/mei/hdcp/Makefile
 create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.c

diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c49e1d2269af..90977132d1e2 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -43,3 +43,9 @@ config INTEL_MEI_TXE
 
  Supported SoCs:
  Intel Bay Trail
+
+config INTEL_MEI_HDCP
+   tristate "Intel HDCP2.2 services of ME Interface"
+   depends on INTEL_MEI && DRM_I915
+   help
+ MEI Support for HDCP2.2 Services on Intel SoCs.
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index cd6825afa8e1..e64d1212fb85 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -23,3 +23,5 @@ mei-txe-objs += hw-txe.o
 
 mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
 CFLAGS_mei-trace.o = -I$(src)
+
+obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
diff --git a/drivers/misc/mei/hdcp/Makefile b/drivers/misc/mei/hdcp/Makefile
new file mode 100644
index ..75ac50203223
--- /dev/null
+++ b/drivers/misc/mei/hdcp/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile - HDCP client driver for Intel MEI Bus Driver.
+# Copyright (c) 2010-2014, Intel Corporation.
+#
+obj-$(CONFIG_INTEL_MEI_HDCP) += mei_hdcp.o
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
new file mode 100644
index ..b334615728a7
--- /dev/null
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Mei_hdcp.c: HDCP client driver for mei bus
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ramalingam C 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int mei_hdcp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+   int ret;
+
+   ret = mei_cldev_enable(cldev);
+   if (ret < 0)
+   dev_err(>dev, "mei_cldev_enable Failed. %d\n", ret);
+
+   return ret;
+}
+
+static int mei_hdcp_remove(struct mei_cl_device *cldev)
+{
+   mei_cldev_set_drvdata(cldev, NULL);
+   return mei_cldev_disable(cldev);
+}
+
+#define MEI_UUID_HDCP  UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \
+   0x52, 0xD1, 0xC5, 0x4B, \
+   0x62, 0x7F, 0x04)
+
+static struct mei_cl_device_id mei_hdcp_tbl[] = {
+   { .uuid 

[Intel-gfx] [PATCH v3 08/40] misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session

[Ramalingam C]

Request ME FW to start the HDCP2.2 session for a intel port.
Prepares payloads for command WIRED_INITIATE_HDCP2_SESSION and sent
to ME FW.

On Success, ME FW will start a HDCP2.2 session for the port and
provides the content for HDCP2.2 AKE_Init message.

v2:
  Rebased.
v3:
  cldev is add as a separate parameter [Tomas]
  Redundant comment and typecast are removed [Tomas]

Signed-off-by: Ramalingam C 
---
 drivers/misc/mei/hdcp/mei_hdcp.c | 68 
 include/linux/mei_hdcp.h | 11 +++
 2 files changed, 79 insertions(+)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 2811a25f8c57..7caee0947761 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -33,9 +33,77 @@
 #include 
 #include 
 #include 
+#include 
+
+#include "mei_hdcp.h"
 
 static BLOCKING_NOTIFIER_HEAD(mei_cldev_notifier_list);
 
+/**
+ * mei_initiate_hdcp2_session:
+ * Function to start a Wired HDCP2.2 Tx Session with ME FW
+ *
+ * @cldev  : Pointer for mei client device
+ * @data   : Intel HW specific Data
+ * @ake_data   : ptr to store AKE_Init
+ *
+ * Returns 0 on Success, <0 on Failure.
+ */
+int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_init *ake_data)
+{
+   struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
+   struct wired_cmd_initiate_hdcp2_session_out
+   session_init_out = { { 0 } };
+   struct device *dev;
+   ssize_t byte;
+
+   if (!data || !ake_data)
+   return -EINVAL;
+
+   dev = >dev;
+
+   session_init_in.header.api_version = HDCP_API_VERSION;
+   session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
+   session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   session_init_in.header.buffer_len =
+   WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
+
+   session_init_in.port.integrated_port_type = data->port_type;
+   session_init_in.port.physical_port = data->port;
+   session_init_in.protocol = (uint8_t)data->protocol;
+
+   byte = mei_cldev_send(cldev, (u8 *)_init_in,
+ sizeof(session_init_in));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_send failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   byte = mei_cldev_recv(cldev, (u8 *)_init_out,
+ sizeof(session_init_out));
+   if (byte < 0) {
+   dev_dbg(dev, "mei_cldev_recv failed. %d\n", (int)byte);
+   return byte;
+   }
+
+   if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+   WIRED_INITIATE_HDCP2_SESSION,
+   session_init_out.header.status);
+   return -1;
+   }
+
+   ake_data->msg_id = HDCP_2_2_AKE_INIT;
+   ake_data->tx_caps = session_init_out.tx_caps;
+   memcpy(ake_data->r_tx, session_init_out.r_tx,
+  sizeof(session_init_out.r_tx));
+
+   return 0;
+}
+EXPORT_SYMBOL(mei_initiate_hdcp2_session);
+
 void mei_cldev_state_notify_clients(struct mei_cl_device *cldev, bool enabled)
 {
if (enabled)
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
index 634c1a5bdf1e..bb4f27d3abcb 100644
--- a/include/linux/mei_hdcp.h
+++ b/include/linux/mei_hdcp.h
@@ -28,6 +28,7 @@
 #define _LINUX_MEI_HDCP_H
 
 #include 
+#include 
 
 enum mei_cldev_state {
MEI_CLDEV_DISABLED,
@@ -105,6 +106,9 @@ struct mei_hdcp_data {
 #ifdef CONFIG_INTEL_MEI_HDCP
 int mei_cldev_register_notify(struct notifier_block *nb);
 int mei_cldev_unregister_notify(struct notifier_block *nb);
+int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_init *ake_data);
 #else
 static int mei_cldev_register_notify(struct notifier_block *nb)
 {
@@ -114,5 +118,12 @@ static int mei_cldev_unregister_notify(struct 
notifier_block *nb)
 {
return -ENODEV;
 }
+static inline
+int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
+  struct mei_hdcp_data *data,
+  struct hdcp2_ake_init *ake_data)
+{
+   return -ENODEV;
+}
 #endif /* defined (CONFIG_INTEL_MEI_HDCP) */
 #endif /* defined (_LINUX_MEI_HDCP_H) */
-- 
2.7.4

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[Intel-gfx] [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines

[Ramalingam C]

In preparation for implementing HDCP2.2 in I915, this patch adds
HDCP register definitions for HDMI and DP HDCP adaptations.

HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where are HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.

v2:
  bit_field definitions are replaced by macros. [Tomas and Jany]
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 include/drm/drm_dp_helper.h | 54 +
 include/drm/drm_hdcp.h  | 29 
 2 files changed, 83 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4de97e94ef9d..2185b3a88911 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -887,6 +887,60 @@
 #define DP_AUX_HDCP_KSV_FIFO   0x6802C
 #define DP_AUX_HDCP_AINFO  0x6803B
 
+/**
+ * DP HDCP2.2 parameter offsets in DPCD address space
+ */
+#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET  0x69008
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
+#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET0x69220
+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET  0x692A0
+#define DP_HDCP_2_2_REG_M_OFFSET   0x692B0
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET  0x692C0
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET   0x692E0
+#define DP_HDCP_2_2_REG_RN_OFFSET  0x692F0
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET  0x692F8
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET0x69318
+#defineDP_HDCP_2_2_REG_RIV_OFFSET  0x69328
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET  0x69330
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET   0x69332
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET  0x69335
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET0x69345
+#define DP_HDCP_2_2_REG_V_OFFSET   0x693E0
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET   0x693F0
+#define DP_HDCP_2_2_REG_K_OFFSET   0x693F3
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET  0x693F5
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET  0x69473
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET0x69493
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
+#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+
+/**
+ * DP HDCP message start offsets in DPCD address space
+ */
+#define DP_HDCP_2_2_AKE_INIT_OFFSETDP_HDCP_2_2_REG_RTX_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET   DP_HDCP_2_2_REG_CERT_RX_OFFSET
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSETDP_HDCP_2_2_REG_EKPUB_KM_OFFSET
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET   DP_HDCP_2_2_REG_EKH_KM_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET
DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
+#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET  DP_HDCP_2_2_REG_LPRIME_OFFSET
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSETDP_HDCP_2_2_REG_V_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET   DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSETDP_HDCP_2_2_REG_MPRIME_OFFSET
+
+#define HDCP_2_2_DP_RXSTATUS_LEN   1
+#define HDCP_2_2_DP_RXSTATUS_READY(x)  (x & BIT(0))
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)(x & BIT(1))
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)(x & BIT(2))
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) (x & BIT(3))
+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)(x & BIT(4))
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE0x0
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 5e0a5ed1a08e..f3f28414b189 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -221,4 +221,33 @@ struct hdcp2_dp_errata_stream_type {
uint8_t stream_type;
 } __packed;
 
+/* HDCP2.2 TIMEOUTs in mSec */
+#define HDCP_2_2_CERT_TIMEOUT  100
+#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT  1000
+#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200
+#define HDCP_2_2_PAIRING_TIMEOUT   200
+#defineHDCP_2_2_HDMI_LPRIME_TIMEOUT20
+#define HDCP_2_2_DP_LPRIME_TIMEOUT 7
+#define HDCP_2_2_RECVID_LIST_TIMEOUT   3000
+#define HDCP_2_2_STREAM_READY_TIMEOUT  100
+
+/* HDMI HDCP2.2 Register Offsets */
+#define HDCP_2_2_HDMI_REG_VER_OFFSET   0x50
+#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET0x60
+#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET  

[Intel-gfx] [PATCH v3 01/40] drm: hdcp2.2 authentication msg definitions

[Ramalingam C]

This patch defines the hdcp2.2 protocol messages for the
HDCP2.2 authentication.

v2:
  bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
  prefix HDCP_2_2_ is added to the macros. [Tomas]
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 include/drm/drm_hdcp.h | 183 +
 1 file changed, 183 insertions(+)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..5e0a5ed1a08e 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -38,4 +38,187 @@
 #define DRM_HDCP_DDC_BSTATUS   0x41
 #define DRM_HDCP_DDC_KSV_FIFO  0x43
 
+#define DRM_HDCP_1_4_SRM_ID0x8
+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE   3
+#define DRM_HDCP_1_4_DCP_SIG_SIZE  40
+
+/**
+ * Protocol message definition for HDCP2.2 specification
+ */
+
+#define HDCP_STREAM_TYPE0  0x00
+#define HDCP_STREAM_TYPE1  0x01
+
+/* HDCP2.2 Msg IDs */
+#define HDCP_2_2_NULL_MSG  1
+#define HDCP_2_2_AKE_INIT  2
+#define HDCP_2_2_AKE_SEND_CERT 3
+#define HDCP_2_2_AKE_NO_STORED_KM  4
+#define HDCP_2_2_AKE_STORED_KM 5
+#define HDCP_2_2_AKE_SEND_HPRIME   7
+#define HDCP_2_2_AKE_SEND_PARING_INFO  8
+#define HDCP_2_2_LC_INIT   9
+#define HDCP_2_2_LC_SEND_LPRIME10
+#define HDCP_2_2_SKE_SEND_EKS  11
+#define HDCP_2_2_REP_SEND_RECVID_LIST  12
+#define HDCP_2_2_REP_SEND_ACK  15
+#define HDCP_2_2_REP_STREAM_MANAGE 16
+#define HDCP_2_2_REP_STREAM_READY  17
+#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
+
+#define HDCP_2_2_RTX_LEN   8
+#define HDCP_2_2_RRX_LEN   8
+
+#define HDCP_2_2_K_PUB_RX_MOD_N_LEN128
+#define HDCP_2_2_K_PUB_RX_EXP_E_LEN3
+#define HDCP_2_2_K_PUB_RX_LEN  (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
+HDCP_2_2_K_PUB_RX_EXP_E_LEN)
+
+#define HDCP_2_2_DCP_LLC_SIG_LEN   384
+
+#define HDCP_2_2_E_KPUB_KM_LEN 128
+#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
+#define HDCP_2_2_H_PRIME_LEN   32
+#define HDCP_2_2_E_KH_KM_LEN   16
+#define HDCP_2_2_RN_LEN8
+#define HDCP_2_2_L_PRIME_LEN   32
+#define HDCP_2_2_E_DKEY_KS_LEN 16
+#define HDCP_2_2_RIV_LEN   8
+#define HDCP_2_2_SEQ_NUM_LEN   3
+#define HDCP_2_2_LPRIME_HALF_LEN   (HDCP_2_2_L_PRIME_LEN / 2)
+#define HDCP_2_2_RECEIVER_ID_LEN   DRM_HDCP_KSV_LEN
+#define HDCP_2_2_MAX_DEVICE_COUNT  31
+#define HDCP_2_2_RECEIVER_IDS_MAX_LEN  (HDCP_2_2_RECEIVER_ID_LEN * \
+HDCP_2_2_MAX_DEVICE_COUNT)
+#define HDCP_2_2_MPRIME_LEN32
+
+/**
+ * TODO: This has to be changed for DP MST, as multiple stream on
+ * same port is possible.
+ * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ */
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT   1
+#define HDCP_2_2_TXCAP_MASK_LEN2
+#define HDCP_2_2_RXCAPS_LEN3
+#define HDCP_2_2_RX_REPEATER(x)(x & BIT(0))
+#define HDCP_2_2_DP_HDCP_CAPABLE(x)(x & BIT(1))
+#define HDCP_2_2_RXINFO_LEN2
+
+/* HDCP1.x compliant device in downstream */
+#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) (x & BIT(0))
+
+/* HDCP2.0 Compliant repeater in downstream */
+#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) (x & BIT(1))
+#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x)   (x & BIT(2))
+#define HDCP_2_2_MAX_DEVS_EXCEEDED(x)  (x & BIT(3))
+#define HDCP_2_2_DEV_COUNT_LO(x)   ((x & (0xF << 4)) >> 4)
+#define HDCP_2_2_DEV_COUNT_HI(x)   (x & BIT(0))
+#define HDCP_2_2_DEPTH(x)  ((x & (0x7 << 1)) >> 1)
+
+struct hdcp2_cert_rx {
+   uint8_t receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
+   uint8_t kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
+   uint8_t reserved[2];
+   uint8_t dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
+} __packed;
+
+struct hdcp2_streamid_type {
+   uint8_t stream_id;
+   uint8_t stream_type;
+} __packed;
+
+/**
+ * The TxCaps field specified in the HDCP HDMI, DP specs
+ * This field is big endian as specified in the errata.
+ */
+struct hdcp2_tx_caps {
+   /* Transmitter must set this to 0x2 */
+   uint8_t version;
+
+   /* Reserved for HDCP and DP Spec. Read as Zero */
+   uint8_t tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
+} __packed;
+
+/*
+ * Main structures for HDCP2.2 protocol communication
+ */
+struct hdcp2_ake_init {
+   uint8_t msg_id;
+   

[Intel-gfx] [PATCH v3 00/40] drm/i915: Implement HDCP2.2

[Ramalingam C]

The sequence for HDCP2.2 authentication and encryption is implemented
in I915. Encoder specific implementations are moved into hdcp_shim.

Intel HWs supports HDCP2.2 through ME FW. Hence this series
introduces a client driver for mei bus, so that for HDCP2.2
authentication, HDCP2.2 stack in I915 can avail the services from
ME FW.

Userspace interface remains unchanged as version agnostic. When
userspace request for HDCP enable, Kernel will detect the HDCP source
and sink's HDCP version(1.4/2.2)capability and enable the best capable
version for that combination.

This series enables the HDCP2.2 for Type0 content streams.

Major Changes in v3:
  - Few patches are squashed in mei related code [Tomas]
  - Kernel Notifier is used for sync between mei_hdcp driver and I915 [Tomas]
  - mei_cl_device is passed to mei_hdcp driver as an arg [Tomas]
  - dropped double check of cl_device [Tomas]
  - Used the Dual Licenses and SPDX Notation for new files and drivers [Tomas]
  - wait_queue is used instead of completion for CP_IRQ [Chris Wilson]
  - mei_cl_device reference is removed from i915_dev_private
  - notification of mei_cldev change is handled for each connector

Ramalingam C (39):
  drm: hdcp2.2 authentication msg definitions
  drm: HDMI and DP specific HDCP2.2 defines
  misc/mei/hdcp: Client driver for HDCP application
  misc/mei/hdcp: Notifier chain for mei cldev state change
  misc/mei/hdcp: Define ME FW interface for HDCP2.2
  linux/mei: Header for mei_hdcp driver interface
  misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session
  misc/mei/hdcp: Verify Receiver Cert and prepare km
  misc/mei/hdcp: Verify H_prime
  misc/mei/hdcp: Store the HDCP Pairing info
  misc/mei/hdcp: Initiate Locality check
  misc/mei/hdcp: Verify L_prime
  misc/mei/hdcp: Prepare Session Key
  misc/mei/hdcp: Repeater topology verifcation and ack
  misc/mei/hdcp: Verify M_prime
  misc/mei/hdcp: Enabling the HDCP authentication
  misc/mei/hdcp: Closing wired HDCP2.2 Tx Session
  drm/i915: wrapping all hdcp var into intel_hdcp
  drm/i915: Define HDCP2.2 related variables
  drm/i915: Define Intel HDCP2.2 registers
  drm/i915: Wrappers for mei HDCP2.2 services
  drm/i915: Implement HDCP2.2 receiver authentication
  drm/i915: Implement HDCP2.2 repeater authentication
  drm/i915: Enable and Disable HDCP2.2 port encryption
  drm/i915: Implement HDCP2.2 En/Dis-able
  drm/i915: Implement HDCP2.2 link integrity check
  drm/i915: Handle HDCP2.2 downstream topology change
  drm/i915: Pullout the bksv read and validation
  drm/i915: Initialize HDCP2.2 and its MEI interface
  drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable
  drm/i915: Enable superior HDCP ver that is capable
  drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure
  drm/i915: hdcp_check_link only on CP_IRQ
  drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ
  drm/i915: Implement gmbus burst read
  drm/i915: Implement the HDCP2.2 support for DP
  drm/i915: Implement the HDCP2.2 support for HDMI
  drm/i915: Add HDCP2.2 support for DP connectors
  drm/i915: Add HDCP2.2 support for HDMI connectors

Tomas Winkler (1):
  mei: bus: whitelist hdcp client

 drivers/gpu/drm/i915/i915_drv.h  |2 +
 drivers/gpu/drm/i915/i915_reg.h  |   35 ++
 drivers/gpu/drm/i915/intel_display.c |7 +-
 drivers/gpu/drm/i915/intel_dp.c  |  364 +++-
 drivers/gpu/drm/i915/intel_drv.h |   88 ++-
 drivers/gpu/drm/i915/intel_hdcp.c| 1090 --
 drivers/gpu/drm/i915/intel_hdmi.c|  206 ++-
 drivers/gpu/drm/i915/intel_i2c.c |  124 +++-
 drivers/misc/mei/Kconfig |6 +
 drivers/misc/mei/Makefile|2 +
 drivers/misc/mei/bus-fixup.c |   16 +
 drivers/misc/mei/hdcp/Makefile   |6 +
 drivers/misc/mei/hdcp/mei_hdcp.c |  809 +
 drivers/misc/mei/hdcp/mei_hdcp.h |  415 +
 include/drm/drm_dp_helper.h  |   54 ++
 include/drm/drm_hdcp.h   |  220 +++
 include/linux/mei_hdcp.h |  227 +++
 17 files changed, 3573 insertions(+), 98 deletions(-)
 create mode 100644 drivers/misc/mei/hdcp/Makefile
 create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.c
 create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.h
 create mode 100644 include/linux/mei_hdcp.h

-- 
2.7.4

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[Intel-gfx] [PATCH v3 03/40] mei: bus: whitelist hdcp client

[Ramalingam C]

From: Tomas Winkler 

Whitelist HDCP client for in kernel drm use

v2:
  Rebased.
v3:
  No changes.

Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/bus-fixup.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 0208c4b027c5..3df2a69fddfb 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -41,6 +41,9 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
 #define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \
0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb)
 
+#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
+ 0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
+
 #define MEI_UUID_ANY NULL_UUID_LE
 
 /**
@@ -72,6 +75,18 @@ static void blacklist(struct mei_cl_device *cldev)
cldev->do_match = 0;
 }
 
+/**
+ * whitelist - forcefully whitelist client
+ *
+ * @cldev: me clients device
+ */
+static void whitelist(struct mei_cl_device *cldev)
+{
+   dev_dbg(>dev, "running hook %s\n", __func__);
+
+   cldev->do_match = 1;
+}
+
 #define OSTYPE_LINUX2
 struct mei_os_ver {
__le16 build;
@@ -399,6 +414,7 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc),
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
+   MEI_FIXUP(MEI_UUID_HDCP, whitelist),
 };
 
 /**
-- 
2.7.4

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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] intel-gpu-top: Rewrite the tool to be safe to use

[Eero Tamminen]

Hi,

On 03.04.2018 12:36, Tvrtko Ursulin wrote:

On 29/03/2018 15:30, Eero Tamminen wrote:

I tested this on HSW GT2, BYT, BDW GT3, SKL GT2 and KBL GT3e,
with Ubuntu 16.04 and 17.10, using Ubuntu default kernels (4.4 to 4.13)
and latest drm-tip build (4.16.0-rc7).


General comments


This will be used by our customers and people who aren't necessarily
familiar with i915 internal details.  Therefore it should use
common terminology in the field and in similar tools, instead of
I3As (Intel 3-letter Acronyms).

For example:
  - rcs -> 3D render
  - bcs -> blitter
  - vecs -> video
  - vcs -> video decode
etc.


Done. And I am open to bike-shedding of the names and display format for 
instance reporting.


New names look fine to me!



Old tool showed also GPU system memory interface (GAM) busyness.
That was valuable info, and reasonably accurate for stable loads.

Could this tool show also either that information (preferred), or
bandwidth utilized by GPU/CPU/display?

(Latest kernels offer GPU memory bandwidth usage through perf
"uncore_imc" "data_reads" & "date_writes" counters.)


Excellent suggestion and I've added IMC data_reads and data_writes to 
the tool.


Thanks, it looks fine too.  I'm just wondering about the numbers
it's reporting on SKL GT2...

AFAIK IMC counters are for uncore, so I though that they should
correspond to GTI (memory interface to outside of GPU) read and
write HW counter values.  While it seemed in some cases quite close,
in some cases the it showed a lot smaller (2/3) value than expected.

I can understand why reads are sometimes larger, because I think
uncore will include also display engine display content reads.

However, I don't see how uncore writes could be considerably smaller
than the GTI interface write amount.

(GTI interface reports the expected value which corresponds directly
to what my test application is doing (64x blended FullHD layer writes).)

Idle machine read amounts are also much smaller (60-65MB/s) than what
I think display update read should be (1920*1080*4*60Hz = 475MiB/s).

Any ideas for these two discrepancies?



Is "wait" value supposed to be IO-wait for given engine interface?

I never saw that change from 0%, although IO-wait in top jumped
from 0 to 20-30% with my test GPU load.


No, that is time spent in MI_WAIT_FOR_EVENT.


Could you add that info to the UI?

E.g. just have "MI" on top of the "wait" column.


> I think not very used in current codebase.

What you're using to validate that it reports correct value?



HW specific test results


BYT:
* Reports "Failed to initialize PMU!" although old intel_gpu_top
   works fine.

HSW GT2,  BDW GT3, SKL GT2 and KBL GT3e seems to work fine except
for the "wait" value.

I never saw blitter engine to do anything, but that's because
modesetting uses just 3D pipeline, and because I couldn't get
Intel DDX to work with rest of latest git version of X / 3D stack.


Thank you for testing this so thoroughly - this was really invaluable 
since I don't have access too such number of platforms. I've tried to 
fix all this in the latest version.


Machines are currently running tests, I'll check these tomorrow.



Kernel version support
--

My HW specific testing above was with drm-tip kernel, but I did one test
also with Ubuntu 16.04 v4.4 kernel (which includes v4.6 or v4.8 i915 
backport) on KBL.  For that, the tool reported:

"Failed to detect engines!"

Although the previous intel_gpu_top works fine with that kernel version.

Same happens also with Ubuntu 17.04 v4.13 kernel.


-> If new version needs a certain kernel version, it should tell
    which version is required.


Yep, at least 4.16 is needed so I have added this info to the error 
message.


IMHO the message is a bit ambivalent:
Failed to detect engines! Kernel 4.16 or newer?

I would suggest checking whether kernel is new enough, and if not:
Kernel X.YY detected, 4.16 or newer required.


- Eero

Thanks again for testing it and when you find the time if you could do 
it once more with the latest version (on the problematic platforms) that 
would be much appreciated.


Regards,

Tvrtko




 - Eero

On 29.03.2018 13:33, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

intel-gpu-top is a dangerous tool which can hang machines due unsafe 
mmio

register access. This patch rewrites it to use only PMU.

Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.

For access to more GPU functional unit level data, an OA metric based 
tool

like gpu-top should be used instead.

v2:
  * Sort engines by class and instance.
  * Do not wait for one sampling period to display something on screen.
  * Move code out of the asserts. (Rinat Ibragimov)
  * Continuously adapt to terminal size. (Rinat Ibgragimov)

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 

Re: [Intel-gfx] [PATCH v4 1/5] i915.rst: Narration overview on GEM + minor reorder to improve narration

[Mika Kuoppala]

kevin.rogo...@intel.com writes:

> From: Kevin Rogovin 
>
> Add a narration to i915.rst about Intel GEN GPU's: engines,
> driver context and relocation.
>
> Signed-off-by: Kevin Rogovin 
> ---
>  Documentation/gpu/i915.rst  | 116 
> 
>  drivers/gpu/drm/i915/i915_vma.h |  10 ++--
>  2 files changed, 100 insertions(+), 26 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 41dc881b00dc..00f897f67f85 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -249,6 +249,99 @@ Memory Management and Command Submission
>  This sections covers all things related to the GEM implementation in the
>  i915 driver.
>  
> +Intel GPU Basics
> +
> +
> +An Intel GPU has multiple engines. There are several engine types.
> +
> +- RCS engine is for rendering 3D and performing compute, this is named 
> `I915_EXEC_RENDER` in user space.
> +- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user 
> space.
> +- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` in 
> user space
> +- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user 
> space.
> +- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; 
> instead it is to be used by user space to specify a default rendering engine 
> (for 3D) that may or may not be the same as RCS.
> +
> +The Intel GPU family is a family of integrated GPU's using Unified
> +Memory Access. For having the GPU "do work", user space will feed the
> +GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
> +or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
> +instruct the GPU to perform work (for example rendering) and that work
> +needs memory from which to read and memory to which to write. All memory
> +is encapsulated within GEM buffer objects (usually created with the ioctl
> +`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
> +to create will also list all GEM buffer objects that the batchbuffer reads
> +and/or writes. For implementation details of memory management see
> +`GEM BO Management Implementation Details`_.
> +
> +The i915 driver allows user space to create a context via the ioctl
> +`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
> +integer. Such a context should be veiwed by user-space as -loosely-

s/veiwed/viewed

> +analogous to the idea of a CPU process of an operating system. The i915
> +driver guarantees that commands issued to a fixed context are to be
> +executed so that writes of a previously issued command are seen by
> +reads of following commands. Actions issued between different contexts
> +(even if from the same file descriptor) are NOT given that guarantee
> +and the only way to synchornize across contexts (even from the same
> +file descriptor) is through the use of fences. At least as far back as
> +Gen4, also have that a context carries with it a GPU HW context;
> +the HW context is essentially (most of atleast) the state of a GPU.
> +In addition to the ordering gaurantees, the kernel will restore GPU

s/gaurantees/guarantees

-Mika

> +state via HW context when commands are issued to a context, this saves
> +user space the need to restore (most of atleast) the GPU state at the
> +start of each batchbuffer. The ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE`
> +is used by user space to create a hardware context which is identified
> +by a 32-bit integer. The non-deprecated ioctls to submit batchbuffer
> +work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
> +to identify what context to use with the command.
> +
> +The GPU has its own memory management and address space. The kernel
> +driver maintains the memory translation table for the GPU. For older
> +GPUs (i.e. those before Gen8), there is a single global such translation
> +table, a global Graphics Translation Table (GTT). For newer generation
> +GPUs each context has its own translation table, called Per-Process
> +Graphics Translation Table (PPGTT). Of important note, is that although
> +PPGTT is named per-process it is actually per context. When user space
> +submits a batchbuffer, the kernel walks the list of GEM buffer objects
> +used by the batchbuffer and guarantees that not only is the memory of
> +each such GEM buffer object resident but it is also present in the
> +(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
> +then it is given an address. Two consequences of this are: the kernel
> +needs to edit the batchbuffer submitted to write the correct value of
> +the GPU address when a GEM BO is assigned a GPU address and the kernel
> +might evict a different GEM BO from the (PP)GTT to make address room
> +for another GEM BO. Consequently, the ioctls submitting a batchbuffer
> +for execution also include a list of all locations within 

Re: [Intel-gfx] [PATCH v4 1/5] i915.rst: Narration overview on GEM + minor reorder to improve narration

[Jani Nikula]

On Tue, 03 Apr 2018, Joonas Lahtinen  wrote:
> Quoting kevin.rogo...@intel.com (2018-04-03 13:52:23)
>> From: Kevin Rogovin 
>> 
>> Add a narration to i915.rst about Intel GEN GPU's: engines,
>> driver context and relocation.
>> 
>> Signed-off-by: Kevin Rogovin 
>
> I'm still bummed by the long lines in the bulleted list, but regardless:

Hum, there's no need to do that. Please reflow.

BR,
Jani.

>
> Reviewed-by: Joonas Lahtinen 
>
> Regards, Joonas
>
>> ---
>>  Documentation/gpu/i915.rst  | 116 
>> 
>>  drivers/gpu/drm/i915/i915_vma.h |  10 ++--
>>  2 files changed, 100 insertions(+), 26 deletions(-)
>> 
>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>> index 41dc881b00dc..00f897f67f85 100644
>> --- a/Documentation/gpu/i915.rst
>> +++ b/Documentation/gpu/i915.rst
>> @@ -249,6 +249,99 @@ Memory Management and Command Submission
>>  This sections covers all things related to the GEM implementation in the
>>  i915 driver.
>>  
>> +Intel GPU Basics
>> +
>> +
>> +An Intel GPU has multiple engines. There are several engine types.
>> +
>> +- RCS engine is for rendering 3D and performing compute, this is named 
>> `I915_EXEC_RENDER` in user space.
>> +- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user 
>> space.
>> +- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` in 
>> user space
>> +- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user 
>> space.
>> +- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; 
>> instead it is to be used by user space to specify a default rendering engine 
>> (for 3D) that may or may not be the same as RCS.
>> +
>> +The Intel GPU family is a family of integrated GPU's using Unified
>> +Memory Access. For having the GPU "do work", user space will feed the
>> +GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
>> +or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
>> +instruct the GPU to perform work (for example rendering) and that work
>> +needs memory from which to read and memory to which to write. All memory
>> +is encapsulated within GEM buffer objects (usually created with the ioctl
>> +`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
>> +to create will also list all GEM buffer objects that the batchbuffer reads
>> +and/or writes. For implementation details of memory management see
>> +`GEM BO Management Implementation Details`_.
>> +
>> +The i915 driver allows user space to create a context via the ioctl
>> +`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
>> +integer. Such a context should be veiwed by user-space as -loosely-
>> +analogous to the idea of a CPU process of an operating system. The i915
>> +driver guarantees that commands issued to a fixed context are to be
>> +executed so that writes of a previously issued command are seen by
>> +reads of following commands. Actions issued between different contexts
>> +(even if from the same file descriptor) are NOT given that guarantee
>> +and the only way to synchornize across contexts (even from the same
>> +file descriptor) is through the use of fences. At least as far back as
>> +Gen4, also have that a context carries with it a GPU HW context;
>> +the HW context is essentially (most of atleast) the state of a GPU.
>> +In addition to the ordering gaurantees, the kernel will restore GPU
>> +state via HW context when commands are issued to a context, this saves
>> +user space the need to restore (most of atleast) the GPU state at the
>> +start of each batchbuffer. The ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE`
>> +is used by user space to create a hardware context which is identified
>> +by a 32-bit integer. The non-deprecated ioctls to submit batchbuffer
>> +work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
>> +to identify what context to use with the command.
>> +
>> +The GPU has its own memory management and address space. The kernel
>> +driver maintains the memory translation table for the GPU. For older
>> +GPUs (i.e. those before Gen8), there is a single global such translation
>> +table, a global Graphics Translation Table (GTT). For newer generation
>> +GPUs each context has its own translation table, called Per-Process
>> +Graphics Translation Table (PPGTT). Of important note, is that although
>> +PPGTT is named per-process it is actually per context. When user space
>> +submits a batchbuffer, the kernel walks the list of GEM buffer objects
>> +used by the batchbuffer and guarantees that not only is the memory of
>> +each such GEM buffer object resident but it is also present in the
>> +(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
>> +then it is given an address. Two consequences of this are: the 

Re: [Intel-gfx] [PATCH v4 5/5] i915: add documentation to intel_engine_cs

[Joonas Lahtinen]

Quoting kevin.rogo...@intel.com (2018-04-03 13:52:27)
> From: Kevin Rogovin 
> 
> Add documentation to a number of the function pointer fields of
> intel_engine_cs.
> 
> Signed-off-by: Kevin Rogovin 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 29 +
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 1f50727a5ddb..eafd1690acde 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -426,23 +426,52 @@ struct intel_engine_cs {
>  
> void(*set_default_submission)(struct intel_engine_cs 
> *engine);
>  
> +   /* In addition to pinning the context, returns the intel_ringbuffer
> +* to which to write commands.

/* Pin context and return intel_ring to write commands to. */

And if you have to resort to multi-line comments, make them
balanced:

/*
 * Foo...
 * Bar...
 */

These comments feel bit verbose for just being internal ones.

> +*/
> struct intel_ring *(*context_pin)(struct intel_engine_cs *engine,
>   struct i915_gem_context *ctx);
> void(*context_unpin)(struct intel_engine_cs *engine,
>  struct i915_gem_context *ctx);
> +
> +   /* Request room on the ringbuffer of a request in order to write
> +* commands for a request; In addition, if necessary, add commands
> +* to the buffer so that the i915_gem_context of the request
> +* is the one active for the commands.
> +*/

"Reserve room from the ringbuffer for commands and emit necessary context
switching commands."?

> int (*request_alloc)(struct i915_request *rq);
> +
> +   /* Called only once (and only if non-NULL) for an engine; used to
> +* initialize the global driver default context.
> +*/
> int (*init_context)(struct i915_request *rq);
>  
> +   /* Add a GPU command to cache invalidate with EMIT_INVALIDATE,
> +* to pipeline flush with EMIT_FLUSH or to do both with EMIT_BARRIER;
> +* the GPU command is added to the buffer holding the commands of
> +* the request (i.e. calling intel_ring_begin() on
> +* i915_request::ring).
> +*/
> int (*emit_flush)(struct i915_request *request, u32 mode);
>  #define EMIT_INVALIDATEBIT(0)
>  #define EMIT_FLUSH BIT(1)
>  #define EMIT_BARRIER   (EMIT_INVALIDATE | EMIT_FLUSH)
> +   /* Add a batchbuffer start command; the GPU command is added to
> +* the buffer holding the commands of the request (i.e. calling
> +* intel_ring_begin() on i915_request::ring).
> +*/
> int (*emit_bb_start)(struct i915_request *rq,
>  u64 offset, u32 length,
>  unsigned int dispatch_flags);
>  #define I915_DISPATCH_SECURE BIT(0)
>  #define I915_DISPATCH_PINNED BIT(1)
>  #define I915_DISPATCH_RS BIT(2)
> +   /* Add a memory write command that writes the global sequence number
> +* (i915_request::global_seqno) and also add an interrupt command;
> +* the GPU command is added to the buffer holding the commands of
> +* the request (i.e. calling intel_ring_begin() on
> +* i915_request::ring).

This is more about what a breadcrumb is than what this interface is
about. "Add commands for triggering a breadcrumb to be picked up" and
maybe explain elsewhere what a breadcrumb is.

So overall, try to make the comments bit less verbose and leave the
implementation detail to the implementation functions :)

Regards, Joonas

> +*/
> void(*emit_breadcrumb)(struct i915_request *rq, u32 *cs);
> int emit_breadcrumb_sz;
>  
> -- 
> 2.16.2
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Avoid RT thread for accuracy test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-03 13:38:25)
> From: Tvrtko Ursulin 
> 
> Realtime scheduling interferes with execlists submission (tasklet) so try
> to simplify the PWM loop in a few ways:
> 
>  * Drop RT.
>  * Longer batches for smaller systematic error.
>  * More truthful test duration calculation.
>  * Less clock queries.
>  * No self-adjust - instead just report the achieved cycle and let the
>parent check against it.
>  * Report absolute cycle error.
> 
> v2:
>  * Bring back self-adjust. (Chris Wilson)
>(But slightly fixed version with no overflow.)
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tests/perf_pmu.c | 97 
> +---
>  1 file changed, 43 insertions(+), 54 deletions(-)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index f27b7ec7d2c2..0cfacd4a8fbe 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -1504,12 +1504,6 @@ test_enable_race(int gem_fd, const struct 
> intel_execution_engine2 *e)
> gem_quiescent_gpu(gem_fd);
>  }
>  
> -static double __error(double val, double ref)
> -{
> -   igt_assert(ref > 1e-5 /* smallval */);
> -   return (100.0 * val / ref) - 100.0;
> -}
> -
>  static void __rearm_spin_batch(igt_spin_t *spin)
>  {
> const uint32_t mi_arb_chk = 0x5 << 23;
> @@ -1532,13 +1526,12 @@ static void
>  accuracy(int gem_fd, const struct intel_execution_engine2 *e,
>  unsigned long target_busy_pct)
>  {
> -   const unsigned int min_test_loops = 7;
> -   const unsigned long min_test_us = 1e6;
> -   unsigned long busy_us = 2500;
> +   unsigned long busy_us = 1 - 100 * (1 + abs(50 - target_busy_pct));
> unsigned long idle_us = 100 * (busy_us - target_busy_pct *
> busy_us / 100) / target_busy_pct;
> -   unsigned long pwm_calibration_us;
> -   unsigned long test_us;
> +   const unsigned long min_test_us = 1e6;
> +   const unsigned long pwm_calibration_us = min_test_us;
> +   const unsigned long test_us = min_test_us;
> double busy_r, expected;
> uint64_t val[2];
> uint64_t ts[2];
> @@ -1553,13 +1546,6 @@ accuracy(int gem_fd, const struct 
> intel_execution_engine2 *e,
> idle_us *= 2;
> }
>  
> -   pwm_calibration_us = min_test_loops * (busy_us + idle_us);
> -   while (pwm_calibration_us < min_test_us)
> -   pwm_calibration_us += busy_us + idle_us;
> -   test_us = min_test_loops * (idle_us + busy_us);
> -   while (test_us < min_test_us)
> -   test_us += busy_us + idle_us;
> -
> igt_info("calibration=%lums, test=%lums; ratio=%.2f%% 
> (%luus/%luus)\n",
>  pwm_calibration_us / 1000, test_us / 1000,
>  (double)busy_us / (busy_us + idle_us) * 100.0,
> @@ -1572,20 +1558,11 @@ accuracy(int gem_fd, const struct 
> intel_execution_engine2 *e,
>  
> /* Emit PWM pattern on the engine from a child. */
> igt_fork(child, 1) {
> -   struct sched_param rt = { .sched_priority = 99 };
> const unsigned long timeout[] = {
> pwm_calibration_us * 1000, test_us * 1000
> };
> -   uint64_t total_busy_ns = 0, total_idle_ns = 0;
> +   uint64_t total_busy_ns = 0, total_ns = 0;
> igt_spin_t *spin;
> -   int ret;
> -
> -   /* We need the best sleep accuracy we can get. */
> -   ret = sched_setscheduler(0,
> -SCHED_FIFO | SCHED_RESET_ON_FORK,
> -);
> -   if (ret)
> -   igt_warn("Failed to set scheduling policy!\n");
>  
> /* Allocate our spin batch and idle it. */
> spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
> @@ -1594,39 +1571,51 @@ accuracy(int gem_fd, const struct 
> intel_execution_engine2 *e,
>  
> /* 1st pass is calibration, second pass is the test. */
> for (int pass = 0; pass < ARRAY_SIZE(timeout); pass++) {
> -   uint64_t busy_ns = -total_busy_ns;
> -   uint64_t idle_ns = -total_idle_ns;
> -   struct timespec test_start = { };
> +   unsigned int target_idle_us = idle_us;
> +   uint64_t busy_ns = 0, idle_ns = 0;
> +   struct timespec start = { };
> +   unsigned long pass_ns = 0;
> +
> +   igt_nsec_elapsed();
>  
> -   igt_nsec_elapsed(_start);
> do {
> -   unsigned int target_idle_us, t_busy;
> +   unsigned long loop_ns, loop_busy;
> +   struct timespec _ts = { };
> +   double err;
> +
> +   

[Intel-gfx] ✓ Fi.CI.BAT: success for Add NV12 support (rev7)

[Patchwork]

== Series Details ==

Series: Add NV12 support (rev7)
URL   : https://patchwork.freedesktop.org/series/39670/
State : success

== Summary ==

Series 39670v7 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/7/mbox/

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fi-bxt-dsi failed to connect after reboot

9a423e97b1f6e080f29d0f7f69806b67542de83b drm-tip: 2018y-04m-03d-11h-50m-53s UTC 
integration manifest
d72b38f1f959 drm/i915: Set src size restrictions for NV12
12dfb0c771d7 drm/i915: Add NV12 support to intel_framebuffer_init
f92ae4d22dbe drm/i915: Add NV12 as supported format for sprite plane
b14499e2f17d drm/i915: Add NV12 as supported format for primary plane
b364afbfa912 drm/i915: Upscale scaler max scale for NV12
351c24e47014 drm/i915: Update format_is_yuv() to include NV12
fe8faacef411 drm/i915: Set scaler mode for NV12
c6b5e1ee2b7e drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
a1a101fb2d41 drm/i915: Display WA 827
cf28f30661e4 drm/i915/skl: split skl_compute_ddb function
dfd59e90ed22 drm/i915/skl+: nv12 workaround disable WM level 1-7
170d8caed005 drm/i915/skl+: make sure higher latency level has higher wm value
dc4923fc1335 drm/i915/skl+: pass skl_wm_level struct to wm compute func
1b72ea89ace4 drm/i915/skl+: NV12 related changes for WM
5231d5353cb2 drm/i915/skl+: support verification of DDB HW state for NV12
79337fec4fab drm/i915/skl+: add NV12 in skl_format_to_fourcc
c37c92d65c7c drm/i915/skl+: refactor WM calculation for NV12
028f935bfc8a drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8568/issues.html
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