date:20180405

Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)

2018-04-05 Thread Saarinen, Jani

HI,

> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: perjantai 6. huhtikuuta 2018 1.51
> To: Ville Syrjala 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/7] 
> drm/arc:
> Stop consulting plane->fb (rev2)
> 
> == Series Details ==
> 
> Series: series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)
> URL   : https://patchwork.freedesktop.org/series/41230/
> State : warning
> 
> == Summary ==
> 
>  Possible new issues:
> 
> Test kms_flip:
> Subgroup 2x-flip-vs-modeset:
> pass   -> DMESG-WARN (shard-hsw)
> Test kms_frontbuffer_tracking:
> Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
> fail   -> SKIP   (shard-snb)
> 
>  Known issues:
> 
> Test kms_flip:
> Subgroup 2x-flip-vs-expired-vblank:
> fail   -> PASS   (shard-hsw) fdo#102887 +1
> Subgroup 2x-plain-flip-ts-check:
> pass   -> FAIL   (shard-hsw) fdo#100368 +1
> Subgroup modeset-vs-vblank-race:
> pass   -> FAIL   (shard-hsw) fdo#103060
> Test kms_setmode:
> Subgroup basic:
> pass   -> FAIL   (shard-apl) fdo#99912
> Test perf:
> Subgroup blocking:
> fail   -> PASS   (shard-hsw) fdo#102252
> 
> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
> 
> shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836
> time:12652s
> shard-hswtotal:2680 pass:1783 dwarn:2   dfail:0   fail:3   skip:891
> time:11339s
> shard-snbtotal:2680 pass:1375 dwarn:1   dfail:0   fail:5   skip:1299
> time:6880s
> Blacklisted hosts:
> shard-kbltotal:1945 pass:1424 dwarn:1   dfail:0   fail:3   skip:516
> time:6732s
For some reason not totally success run for kbl. 
Execution stops on   0.00 igt@pm_rpm@system-suspend-execbuf incomplete 
Tomi, Ville, any idea? 

> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_8606/shards.html
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 11/13] drm/omapdrm: Nuke omap_framebuffer_get_next_connector()

2018-04-05 Thread Tomi Valkeinen

On 05/04/18 19:50, Daniel Vetter wrote:
> On Thu, Apr 05, 2018 at 06:13:58PM +0300, Ville Syrjala wrote:
>> From: Ville Syrjälä 
>>
>> omap_framebuffer_get_next_connector() uses plane->fb which we want to
>> deprecate for atomic drivers. As omap_framebuffer_get_next_connector()
>> is unused just nuke the entire function.
>>
>> Cc: Tomi Valkeinen 
>> Signed-off-by: Ville Syrjälä 
> 
> Yeah was slightly worried how to fix up this one, but we're lucky!
> 
> Reviewed-by: Daniel Vetter 

I tried to remove it just a week ago, but Sebastian said that it's used
by a unmerged series about DSI command mode displays, so I dropped the
patch.

In the unmerged series, it's used by omap_framebuffer_dirty() ([PATCHv3
3/8] drm/omap: add support for manually updated displays). So we have a
framebuffer, and we want to know which crtcs need to be flushed.

 Tomi

-- 
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Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : warning

== Summary ==

 Possible new issues:

Test kms_flip:
Subgroup 2x-plain-flip:
pass   -> DMESG-WARN (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup flip-vs-cursor-varying-size:
pass   -> FAIL   (shard-hsw) fdo#102670
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
fail   -> PASS   (shard-snb) fdo#103166
Test kms_rotation_crc:
Subgroup primary-rotation-180:
fail   -> PASS   (shard-snb) fdo#103925
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test kms_vblank:
Subgroup pipe-b-accuracy-idle:
pass   -> FAIL   (shard-hsw) fdo#102583
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12628s
shard-hswtotal:2680 pass:1782 dwarn:2   dfail:0   fail:4   skip:891 
time:11444s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:2   skip:1299 
time:6949s
Blacklisted hosts:
shard-kbltotal:1955 pass:1414 dwarn:0   dfail:0   fail:6   skip:534 
time:6174s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8609/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL   : https://patchwork.freedesktop.org/series/41232/
State : success

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_plane_multiple:
Subgroup atomic-pipe-b-tiling-y:
pass   -> FAIL   (shard-apl) fdo#103166 +1
Test kms_rotation_crc:
Subgroup primary-rotation-180:
fail   -> PASS   (shard-snb) fdo#103925
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1834 dwarn:1   dfail:0   fail:8   skip:836 
time:12652s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11392s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:2   skip:1299 
time:6929s
Blacklisted hosts:
shard-kbltotal:2000 pass:1462 dwarn:1   dfail:0   fail:7   skip:529 
time:6487s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8608/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: set minimum CD clock to twice the BCLK. (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915: set minimum CD clock to twice the BCLK. (rev3)
URL   : https://patchwork.freedesktop.org/series/32657/
State : failure

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-cur-indfb-move:
pass   -> DMESG-FAIL (shard-hsw)
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
fail   -> PASS   (shard-snb) fdo#103166
Test kms_rotation_crc:
Subgroup primary-rotation-180:
fail   -> PASS   (shard-snb) fdo#103925
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12651s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:1   fail:1   skip:891 
time:11433s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:2   skip:1299 
time:6929s
Blacklisted hosts:
shard-kbltotal:1927 pass:1405 dwarn:2   dfail:0   fail:5   skip:515 
time:6526s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8607/shards.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: update ddb entry start/end mask during hw ddb readout

2018-04-05 Thread Lucas De Marchi

On Thu, Apr 05, 2018 at 02:47:56PM +0530, Mahesh Kumar wrote:
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
> 
> Changes since V1:
>  - Use _MASK & _SHIFT macro (James)
> Changes since V2:
>  - use kernel type u8 instead of uint8_t
> 
> Signed-off-by: Mahesh Kumar 

This is independent of the other patches and could be applied even if
they need a new iteration.

Reviewed-by: Lucas De Marchi 

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 18 ++
>  2 files changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 176dca6554f4..e3a6c535617d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6459,6 +6459,9 @@ enum {
>  
>  #define _PLANE_BUF_CFG_1_B   0x7127c
>  #define _PLANE_BUF_CFG_2_B   0x7137c
> +#define  SKL_DDB_ENTRY_MASK  0x3FF
> +#define  ICL_DDB_ENTRY_MASK  0x7FF
> +#define  DDB_ENTRY_END_SHIFT 16
>  #define _PLANE_BUF_CFG_1(pipe)   \
>   _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
>  #define _PLANE_BUF_CFG_2(pipe)   \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 615a084736f3..f7522b268494 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3864,10 +3864,18 @@ static unsigned int skl_cursor_allocation(int 
> num_active)
>   return 8;
>  }
>  
> -static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> +static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> +struct skl_ddb_entry *entry, u32 reg)
>  {
> - entry->start = reg & 0x3ff;
> - entry->end = (reg >> 16) & 0x3ff;
> + u16 mask;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + mask = ICL_DDB_ENTRY_MASK;
> + else
> + mask = SKL_DDB_ENTRY_MASK;
> + entry->start = reg & mask;
> + entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;
> +
>   if (entry->end)
>   entry->end += 1;
>  }
> @@ -3898,7 +3906,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
> *dev_priv,
>   else
>   val = I915_READ(CUR_BUF_CFG(pipe));
>  
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], 
> val);
> + skl_ddb_entry_init_from_hw(dev_priv,
> +&ddb->plane[pipe][plane_id],
> +val);
>   }
>  
>   intel_display_power_put(dev_priv, power_domain);
> -- 
> 2.16.2
> 
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Re: [Intel-gfx] [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

2018-04-05 Thread Rodrigo Vivi

On Thu, Feb 22, 2018 at 12:55:10AM -0300, Paulo Zanoni wrote:
> From: Manasi Navare 
> 
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
> 
> The Voltage swing seqeuence is similar to Cannonlake.
> However it has different register definitions and hence
> it makes sense to create a separate vswing sequence and
> program functions for ICL to leave room for more changes
> in case the Bspec changes later and deviates from CNL sequence.
> 
> v2:
> Use ~TAP3_DISABLE for enbaling that bit (Jani Nikula)
> 
> v3:
> * Use dw4_scaling column for PORT_TX_DW4 values (Rodrigo)
> 
> v4:
> * Call it combo_vswing, use switch statement (Paulo)
> 
> v5 (from Paulo):
> * Fix a typo.
> * s/rate < 60/rate <= 60/.
> * Don't remove blank lines that should be there.
> 
> v6:
> * Rebased by Rodrigo on top of Cannonlake changes
>   where non vswing sequences are not aligned with iboost
>   anymore.
> 
> v7: Another rebase after an upstream rework.
> 
> v8 (from Paulo):
> * Adjust the code to the upstream output type changes.
> * Squash the patch that moved some functions up.
> * Merge both get_combo_buf_trans functions in order to simplify the
>   code.
> * Change the changelog format.
> 
> Cc: Jani Nikula 
> Reviewed-by: Paulo Zanoni  (v5)
> Signed-off-by: Manasi Navare 
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 189 
> ++-
>  1 file changed, 186 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0a4683991ec2..c38873cb98ca 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -849,6 +849,45 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static const struct icl_combo_phy_ddi_buf_trans *
> +icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> + int type, int *n_entries)
> +{
> + u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> +
> + if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> + switch (voltage) {
> + case VOLTAGE_INFO_0_85V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> + return icl_combo_phy_ddi_translations_edp_0_85V;
> + case VOLTAGE_INFO_0_95V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> + return icl_combo_phy_ddi_translations_edp_0_95V;
> + case VOLTAGE_INFO_1_05V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> + return icl_combo_phy_ddi_translations_edp_1_05V;
> + default:
> + MISSING_CASE(voltage);
> + return NULL;
> + }
> + } else {

DP ends up here on HDMI?
This is strange...

Also, for clarity, why not to split this into separated functions
like all other platforms?

> + switch (voltage) {
> + case VOLTAGE_INFO_0_85V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> + return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> + case VOLTAGE_INFO_0_95V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> + return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> + case VOLTAGE_INFO_1_05V:
> + *n_entries = 
> ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> + return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> + default:
> + MISSING_CASE(voltage);
> + return NULL;
> + }
> + }
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_entries, level, default_entry;
> @@ -2178,6 +2217,144 @@ static void cnl_ddi_vswing_sequence(struct 
> intel_encoder *encoder,
>   I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>  }
>  
> +static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> +  u32 level, enum port port, int type)
> +{
> + const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> + u32 n_entries, val;
> + int ln;
> +
> + ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
> +&n_entries);
> + if (!ddi_translations)
> + return;
> +
> + if (level >= n_entries) {
> + DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d 
> instead.", level, n_entries - 1);
> + level = n_entries - 1;
> + }
> +
> + /* Set PORT

Re: [Intel-gfx] [PATCH v4] drm: Fix downstream dev count read

2018-04-05 Thread Rodrigo Vivi

On Thu, Apr 05, 2018 at 04:04:14AM +0530, Ramalingam C wrote:
> 
> 
> On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
> > On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
> > > On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> > > > In both HDMI and DP, device count is represented by 6:0 bits of a
> > > > register(BInfo/Bstatus)
> > > > 
> > > > So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> > > > 
> > > > v3:
> > > >Retained the Rb-ed.
> > > > v4:
> > > >%s/drm\/i915/drm [rodrigo]
> > > > 
> > > Shouldn't this patch have a "Fixes:" ?
> > Yes, I think that'd be good.
> Will add
> Fixes: 495eb7f877ab drm: Add some HDCP related #defines
> > 
> > > cc: stable?
> > It couldn't hurt.
> Sorry what is needed here?

nothing actually...

$ dim fixes 495eb7f877ab3
Fixes: 495eb7f877ab ("drm: Add some HDCP related #defines")
Cc: Daniel Vetter 
Cc: Ramalingam C 
Cc: Sean Paul 
Cc: Gustavo Padovan 
Cc: David Airlie 
Cc: dri-de...@lists.freedesktop.org

CC: Stable wasn't returned here so it is not needed.

> > 
> > > I pushed first 3 patches on the series to dinq.
> > > I believe this one here could be there with Dave's ack or
> > > maybe on drm-misc-fixes?
> > Meh. The severity of this isn't too big, given that I doubt people care 
> > _too_
> > much about plugging in more than 64 HDCP-enabled devices. If you want to 
> > drop it
> > in -misc-next-fixes, I can send it out next week.
> > 
> > While we're asking for a respin, could we add HDCP somewhere in the subject?
> will change the sub to
> drm: Fix HDCP downstream dev count read
> 
> --Ram
> > 
> > Sean
> > 
> > > > Signed-off-by: Ramalingam C 
> > > > cc: Sean Paul 
> > > > Reviewed-by: Sean Paul 
> > > > ---
> > > >   include/drm/drm_hdcp.h | 2 +-
> > > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > > > index 562fa7df2637..98e63d870139 100644
> > > > --- a/include/drm/drm_hdcp.h
> > > > +++ b/include/drm/drm_hdcp.h
> > > > @@ -19,7 +19,7 @@
> > > >   #define DRM_HDCP_RI_LEN   2
> > > >   #define DRM_HDCP_V_PRIME_PART_LEN 4
> > > >   #define DRM_HDCP_V_PRIME_NUM_PARTS5
> > > > -#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
> > > > +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
> > > >   #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)  (x & BIT(3))
> > > >   #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)   (x & BIT(7))
> > > > -- 
> > > > 2.7.4
> > > > 
> 
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/14] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [01/14] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41247/
State : warning

== Summary ==

Series 41247v1 series starting with [01/14] drm/i915/icl: Introduce initial 
Icelake Workarounds
https://patchwork.freedesktop.org/api/1.0/series/41247/revisions/1/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
pass   -> SKIP   (fi-pnv-d510)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:447s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:584s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:427s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:639s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:443s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:495s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:442s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:583s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:410s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:523s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
c8c87325e876 drm/i915/icl: Enable Sampler DFR
7ec11968e4ba drm/i915/icl: WaEnableStateCacheRedirectToCS
09f56bc1d1b4 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
dd4eb78cd9d2 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
5fe0770ab25c drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
1ae846bffbf6 drm/i915/icl: WaSendPushConstantsFromMMIO
0fa4530e8474 drm/i915/icl: WaDisCtxReload
8f02830b2c95 drm/i915/icl: WaCL2SFHalfMaxAlloc
1f0de8d1cf64 drm/i915/icl: WaDisableImprovedTdlClkGating
82b0e05d8d4c drm/i915/icl: WaDisableCleanEvicts
d557f2334dca drm/i915/icl: WaL3BankAddressHashing
612cf4f0cfa9 drm/i915/icl: WaModifyGamTlbPartitioning
0070d9f6a54e drm/i915/icl: WaGAPZPrio

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [01/14] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41247/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0dbd53fd7f8c drm/i915/icl: Introduce initial Icelake Workarounds
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
Inherit workarounds from previous platforms that are still valid for Icelake.

-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_drv.h:2467:
+#define IS_ICL_REVID(dev_priv, since, until) \
+   (IS_ICELAKE(dev_priv) && IS_REVID(dev_priv, since, until))

total: 0 errors, 1 warnings, 1 checks, 112 lines checked
0070d9f6a54e drm/i915/icl: WaGAPZPriorityScheme
612cf4f0cfa9 drm/i915/icl: WaModifyGamTlbPartitioning
d557f2334dca drm/i915/icl: WaL3BankAddressHashing
82b0e05d8d4c drm/i915/icl: WaDisableCleanEvicts
-:23: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:7181:
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE(1<<6)
  ^

total: 0 errors, 0 warnings, 1 checks, 19 lines checked
1f0de8d1cf64 drm/i915/icl: WaDisableImprovedTdlClkGating
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/i915_reg.h:8254:
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1<<1)
  ^

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
8f02830b2c95 drm/i915/icl: WaCL2SFHalfMaxAlloc
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
This workarounds an issue with insufficient storage for the CL2 and SF units.

total: 0 errors, 1 warnings, 0 checks, 23 lines checked
0fa4530e8474 drm/i915/icl: WaDisCtxReload
1ae846bffbf6 drm/i915/icl: WaSendPushConstantsFromMMIO
5fe0770ab25c drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
dd4eb78cd9d2 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
09f56bc1d1b4 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
7ec11968e4ba drm/i915/icl: WaEnableStateCacheRedirectToCS
c8c87325e876 drm/i915/icl: Enable Sampler DFR

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Re: [Intel-gfx] [PATCH v3] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Dhinakaran Pandiyan




On Thu, 2018-04-05 at 17:19 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> originally thought this might be an issue with us accidentally shutting
> off the aux block when putting the sink into D3, but since the DP spec
> mandates that sinks must wake up within 1ms while we have 100ms to
> respond to an ESI irq, this didn't really add up. Turns out that the
> problem is more subtle then that:
> 
> It turns out that the timeout is from us not enabling DPMS on the MST
> hub before actually trying to initiate sideband communications. This
> would cause the first sideband communication (power_up_phy()), to start
> timing out because the sink wasn't ready to respond. Afterwards, we
> would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> intel_ddi_pre_enable_dp(), which would actually result in waking up the
> sink so that sideband requests would work again.
> 
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
> 
> Changes since v1:
> - Remove comment above if (!intel_dp->is_mst) - vsryjala
> - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
>   keep enable/disable paths symmetrical
> - Improve commit message - dhnkrn
> Changes since v2:
> - Only send DPMS off when we're disabling the last sink, and only send
>   DPMS on when we're enabling the first sink - dhnkrn
> 
> Signed-off-by: Lyude Paul 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Cc: Laura Abbott 
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> hub.")
> ---
>  drivers/gpu/drm/i915/intel_ddi.c| 6 --
>  drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..c0bf7419e1c1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);



I believe Ville recommended to check for
is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)
here. The question is, are there cases where 
intel_dp->is_mst != is_mst? A disconnect in the middle of a modeset
would cause intel_dp->is_mst to be false, wouldn't it?







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Re: [Intel-gfx] [PATCH v3] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Pandiyan, Dhinakaran




On Thu, 2018-04-05 at 17:19 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> originally thought this might be an issue with us accidentally shutting
> off the aux block when putting the sink into D3, but since the DP spec
> mandates that sinks must wake up within 1ms while we have 100ms to
> respond to an ESI irq, this didn't really add up. Turns out that the
> problem is more subtle then that:
> 
> It turns out that the timeout is from us not enabling DPMS on the MST
> hub before actually trying to initiate sideband communications. This
> would cause the first sideband communication (power_up_phy()), to start
> timing out because the sink wasn't ready to respond. Afterwards, we
> would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> intel_ddi_pre_enable_dp(), which would actually result in waking up the
> sink so that sideband requests would work again.
> 
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
> 
> Changes since v1:
> - Remove comment above if (!intel_dp->is_mst) - vsryjala
> - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
>   keep enable/disable paths symmetrical
> - Improve commit message - dhnkrn
> Changes since v2:
> - Only send DPMS off when we're disabling the last sink, and only send
>   DPMS on when we're enabling the first sink - dhnkrn
> 
> Signed-off-by: Lyude Paul 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Cc: Laura Abbott 
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> hub.")
> ---
>  drivers/gpu/drm/i915/intel_ddi.c| 6 --
>  drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..c0bf7419e1c1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);



I believe Ville recommended to check for
is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)
here. The question is, are there cases where 
intel_dp->is_mst != is_mst? A disconnect in the middle of a modeset
would cause intel_dp->is_mst to be false, wouldn't it?






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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : success

== Summary ==

Series 41095v3 series starting with [v4] drm/i915: Enable edp psr error 
interrupts on hsw
https://patchwork.freedesktop.org/api/1.0/series/41095/revisions/3/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:450s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:384s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:516s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:422s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:669s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:441s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:513s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:562s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:411s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:522s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
443c59203be8 drm/i915/psr: Timestamps for PSR entry and exit interrupts.
8bfb9d8526bd drm/i915/psr: Control PSR interrupts via debugfs
536a6705099e drm/i915: Enable edp psr error interrupts on bdw+
6494853a48be drm/i915: Enable edp psr error interrupts on hsw

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8609/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)
URL   : https://patchwork.freedesktop.org/series/41230/
State : warning

== Summary ==

 Possible new issues:

Test kms_flip:
Subgroup 2x-flip-vs-modeset:
pass   -> DMESG-WARN (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887 +1
Subgroup 2x-plain-flip-ts-check:
pass   -> FAIL   (shard-hsw) fdo#100368 +1
Subgroup modeset-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12652s
shard-hswtotal:2680 pass:1783 dwarn:2   dfail:0   fail:3   skip:891 
time:11339s
shard-snbtotal:2680 pass:1375 dwarn:1   dfail:0   fail:5   skip:1299 
time:6880s
Blacklisted hosts:
shard-kbltotal:1945 pass:1424 dwarn:1   dfail:0   fail:3   skip:516 
time:6732s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8606/shards.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6494853a48be drm/i915: Enable edp psr error interrupts on hsw
-:111: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#111: FILE: drivers/gpu/drm/i915/i915_reg.h:4017:
+#define   EDP_PSR_ERROR(1<<2)
  ^

-:112: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#112: FILE: drivers/gpu/drm/i915/i915_reg.h:4018:
+#define   EDP_PSR_POST_EXIT(1<<1)
  ^

-:113: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#113: FILE: drivers/gpu/drm/i915/i915_reg.h:4019:
+#define   EDP_PSR_PRE_ENTRY(1<<0)
  ^

-:122: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#122: FILE: drivers/gpu/drm/i915/i915_reg.h:6830:
+#define DE_EDP_PSR_INT_HSW (1<<19)
  ^

total: 0 errors, 0 warnings, 4 checks, 78 lines checked
536a6705099e drm/i915: Enable edp psr error interrupts on bdw+
-:159: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__t' - possible 
side-effects?
#159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:160: CHECK:SPACING: No space is necessary after a cast
#160: FILE: drivers/gpu/drm/i915/intel_display.h:222:
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \

-:161: WARNING:SPACING: space prohibited between function name and open 
parenthesis '('
#161: FILE: drivers/gpu/drm/i915/intel_display.h:223:
+   for_each_if ((__mask) & (1 << (__t)))

total: 1 errors, 1 warnings, 2 checks, 123 lines checked
8bfb9d8526bd drm/i915/psr: Control PSR interrupts via debugfs
443c59203be8 drm/i915/psr: Timestamps for PSR entry and exit interrupts.

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL   : https://patchwork.freedesktop.org/series/41232/
State : success

== Summary ==

Series 41232v2 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41232/revisions/2/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-plain-flip:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-guc) fdo#104108
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:434s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:545s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:589s
fi-elk-e7500 total:285  pass:224  dwarn:2   dfail:0   fail:0   skip:59  
time:495s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:665s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:511s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:411s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:448s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:518s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
d8f2fc5804b9 drm/i915/dp: Send DPCD ON for MST before phy_up

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8608/issues.html
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[Intel-gfx] [PATCH 14/14] drm/i915/icl: Enable Sampler DFR

2018-04-05 Thread Oscar Mateo

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)

Cc: Sagar Arun Kamble 
Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83c55e3..818d57e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8220,6 +8220,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define   DFR_DISABLE  (1 << 9)
+
 #define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c5bf71b..8f1d028 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8505,6 +8505,10 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+   /* This is not an Wa. Enable to reduce Sampler power */
+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

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[Intel-gfx] [PATCH 03/14] drm/i915/icl: WaModifyGamTlbPartitioning

2018-04-05 Thread Oscar Mateo

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd5da2b..78abb49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8200,6 +8200,11 @@ enum {
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1b98ae..03c5de3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8518,6 +8518,11 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 10/14] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

2018-04-05 Thread Oscar Mateo

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ee16b88..f092c0f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1409,6 +1409,11 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+   ret = wa_ring_whitelist_reg(engine, HALF_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 06/14] drm/i915/icl: WaDisableImprovedTdlClkGating

2018-04-05 Thread Oscar Mateo

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee179c3..ca12316 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8251,6 +8251,7 @@ enum {
 #define GEN7_ROW_CHICKEN2_GT2  _MMIO(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE (1<<0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1<<8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1<<1)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ba8c137..0f13e1a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1487,6 +1487,13 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
 */
WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+   /* Wa_2006611047:icl
+* Formerly known as WaDisableImprovedTdlClkGating
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 12/14] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

2018-04-05 Thread Oscar Mateo

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4db85a..8d04e26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8219,6 +8219,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e053deb..de05946 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1419,6 +1419,14 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUmdWriteTRTTRootTable:icl */
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+   if (ret)
+   return ret;
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 05/14] drm/i915/icl: WaDisableCleanEvicts

2018-04-05 Thread Oscar Mateo

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10ed35f..ee179c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7178,6 +7178,7 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
 
 #define GEN8_L3SQCREG4 _MMIO(0xb118)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE(1<<6)
 #define  GEN8_LQSC_RO_PERF_DIS (1<<27)
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES(1<<21)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58974fa..84d9910 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,6 +8513,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
+   /* Wa_1405733216:icl
+* Formerly known as WaDisableCleanEvicts
+*/
+   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+   GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
   /* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
-- 
1.9.1

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[Intel-gfx] [PATCH 07/14] drm/i915/icl: WaCL2SFHalfMaxAlloc

2018-04-05 Thread Oscar Mateo

This workarounds an issue with insufficient storage for the CL2 and SF units.

v2: Renamed to Wa_1405766107

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 
 drivers/gpu/drm/i915/intel_pm.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca12316..b2663de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8212,6 +8212,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84d9910..3843c28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8541,6 +8541,13 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 02/14] drm/i915/icl: WaGAPZPriorityScheme

2018-04-05 Thread Oscar Mateo

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++--
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cd2f2a..cd5da2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8196,8 +8196,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE   (1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
 
-#define GEN8_GARBCNTL   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL  _MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f4c7ae..d1b98ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8512,6 +8512,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+  GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 13/14] drm/i915/icl: WaEnableStateCacheRedirectToCS

2018-04-05 Thread Oscar Mateo

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d04e26..83c55e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7150,6 +7150,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
 
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index de05946..ff25f90 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1513,6 +1513,10 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaEnableStateCacheRedirectToCS:icl */
+   WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
-- 
1.9.1

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[Intel-gfx] [PATCH 01/14] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-05 Thread Oscar Mateo

Inherit workarounds from previous platforms that are still valid for Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang,
since this has been fixed already in upstream.
  - Squashed with this patch from Paulo Zanoni :
drm/i915/icl: add icelake_init_clock_gating()
  - Squashed with this patch from Oscar Mateo :
drm/i915/icl: WaForceEnableNonCoherent
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and applies to B0 
as well
  - WaPipeControlBefore3DStateSamplePattern WABB was being incorrectly applied 
to ICL

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h|  9 +
 drivers/gpu/drm/i915/i915_gem_gtt.c|  4 ++--
 drivers/gpu/drm/i915/i915_reg.h|  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +
 drivers/gpu/drm/i915/intel_lrc.c   |  2 ++
 drivers/gpu/drm/i915/intel_pm.c| 19 ++-
 6 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..4d42a8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2458,6 +2458,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(dev_priv, since, until) \
+   (IS_ICELAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6..6cd2f2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7184,6 +7184,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..ba8c137 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1467,6 +1467,29 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
return 0;
 }
 
+static int icl_init_workarounds(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+
+   /* Wa_1604370585:icl (pre-prod)
+* Formerly known as WaPushConstantDereferenceHoldDisable
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+   /* WaForceEnableNonCoherent:icl
+* This is not the same workaround as in early Gen9 platforms, where
+* lacking this could cause system hangs, but coherency performance
+* overhead is high and only a few compute workloads really need it
+* (the register is whitelisted in hardware now, so UMDs can opt in
+* for coherency if they have a good reason).
+*/
+   WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+   return 0;
+}
+
 int init_workarounds_ring(struct inte

[Intel-gfx] [PATCH 11/14] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

2018-04-05 Thread Oscar Mateo

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index f092c0f..e053deb 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1414,6 +1414,11 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+   ret = wa_ring_whitelist_reg(engine, GEN9_HALF_SLICE_CHICKEN7);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 04/14] drm/i915/icl: WaL3BankAddressHashing

2018-04-05 Thread Oscar Mateo

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h |  6 ++
 drivers/gpu/drm/i915/intel_pm.c | 20 
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78abb49..10ed35f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8199,6 +8199,12 @@ enum {
 #define GEN8_GARBCNTL  _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0(1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0   (1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK   (0x3f << 5)
 
 #define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
 #define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03c5de3..58974fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,11 +8513,23 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-   /* Wa_1405543622:icl
-* Formerly known as WaGAPZPriorityScheme
+   I915_WRITE(GEN8_GARBCNTL,
+  /* Wa_1604223664:icl
+   * Formerly known as WaL3BankAddressHashing
+   */
+  ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+   GEN11_HASH_CTRL_EXCL_BIT0 |
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* Wa_1604223664:icl
+* Formerly known as WaL3BankAddressHashing
 */
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN11_ARBITRATION_PRIO_ORDER_MASK));
+   I915_WRITE(GEN11_GLBLINVL,
+  ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 
/* WaModifyGamTlbPartitioning:icl */
I915_WRITE(GEN11_GACB_PERF_CTRL,
-- 
1.9.1

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[Intel-gfx] [PATCH 09/14] drm/i915/icl: WaSendPushConstantsFromMMIO

2018-04-05 Thread Oscar Mateo

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0f13e1a..ee16b88 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1470,6 +1470,7 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
 static int icl_init_workarounds(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
+   int ret;
 
/* Wa_1604370585:icl (pre-prod)
 * Formerly known as WaPushConstantDereferenceHoldDisable
@@ -1494,6 +1495,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaSendPushConstantsFromMMIO:icl */
+   ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 08/14] drm/i915/icl: WaDisCtxReload

2018-04-05 Thread Oscar Mateo

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2663de..a4db85a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8216,6 +8216,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3843c28..c5bf71b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,6 +8519,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
 
+   /* Wa_220166154:icl
+* Formerly known as WaDisCtxReload
+*/
+   I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+   GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
   /* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb
URL   : https://patchwork.freedesktop.org/series/41230/
State : success

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12708s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 
time:11431s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6948s
Blacklisted hosts:
shard-kbltotal:1944 pass:1407 dwarn:12  dfail:0   fail:5   skip:519 
time:6332s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8605/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: set minimum CD clock to twice the BCLK. (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915: set minimum CD clock to twice the BCLK. (rev3)
URL   : https://patchwork.freedesktop.org/series/32657/
State : success

== Summary ==

Series 32657v3 drm/i915: set minimum CD clock to twice the BCLK.
https://patchwork.freedesktop.org/api/1.0/series/32657/revisions/3/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
pass   -> FAIL   (fi-ivb-3520m) k.org#198519 +2
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (fi-glk-j4005) fdo#105644
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
k.org#198519 https://bugzilla.kernel.org/show_bug.cgi?id=198519
fdo#105644 https://bugs.freedesktop.org/show_bug.cgi?id=105644
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:542s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:506s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:594s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-glk-j4005 total:285  pass:255  dwarn:1   dfail:0   fail:0   skip:29  
time:484s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:253  dwarn:0   dfail:0   fail:3   skip:29  
time:412s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:666s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:529s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
8183ab2bd26b drm/i915: set minimum CD clock to twice the BCLK.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8607/issues.html
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Re: [Intel-gfx] [Freedreno] [PATCH 01/10] include: Move ascii85 functions from i915 to linux/ascii85.h

2018-04-05 Thread Jordan Crouse

On Thu, Apr 05, 2018 at 04:00:47PM -0600, Jordan Crouse wrote:
> The i915 DRM driver very cleverly used ascii85 encoding for their
> GPU state file. Move the encode functions to a general header file to
> support other drivers that might be interested in the same
> functionality.

In a previous version of this patch, Chris asked what tree I wanted this applied
to, and the answer is: I'm not sure?  I'm hoping that Rob will be cool with
picking the rest up for msm-next for 4.18 but I'm okay with putting this
particular patch wherever it is easiest for the maintainers.

Jordan

> Reviewed-by: Chris Wilson 
> Signed-off-by: Jordan Crouse 
>  drivers/gpu/drm/i915/i915_gpu_error.c | 35 ---
>  include/linux/ascii85.h   | 39 
> +++
>  2 files changed, 43 insertions(+), 31 deletions(-)
>  create mode 100644 include/linux/ascii85.h
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 67c902412193..969d967e58c7 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -31,7 +31,7 @@
>  #include 
>  #include 
>  #include 
> -
> +#include 
>  #include "i915_drv.h"
>  
>  static inline const struct intel_engine_cs *
> @@ -518,35 +518,12 @@ void i915_error_printf(struct drm_i915_error_state_buf 
> *e, const char *f, ...)
>   va_end(args);
>  }
>  
> -static int
> -ascii85_encode_len(int len)
> -{
> - return DIV_ROUND_UP(len, 4);
> -}
> -
> -static bool
> -ascii85_encode(u32 in, char *out)
> -{
> - int i;
> -
> - if (in == 0)
> - return false;
> -
> - out[5] = '\0';
> - for (i = 5; i--; ) {
> - out[i] = '!' + in % 85;
> - in /= 85;
> - }
> -
> - return true;
> -}
> -
>  static void print_error_obj(struct drm_i915_error_state_buf *m,
>   struct intel_engine_cs *engine,
>   const char *name,
>   struct drm_i915_error_object *obj)
>  {
> - char out[6];
> + char out[ASCII85_BUFSZ];
>   int page;
>  
>   if (!obj)
> @@ -568,12 +545,8 @@ static void print_error_obj(struct 
> drm_i915_error_state_buf *m,
>   len -= obj->unused;
>   len = ascii85_encode_len(len);
>  
> - for (i = 0; i < len; i++) {
> - if (ascii85_encode(obj->pages[page][i], out))
> - err_puts(m, out);
> - else
> - err_puts(m, "z");
> - }
> + for (i = 0; i < len; i++)
> + error_puts(m, ascii85_encode(obj->pages[page][i], out));
>   }
>   err_puts(m, "\n");
>  }
> diff --git a/include/linux/ascii85.h b/include/linux/ascii85.h
> new file mode 100644
> index ..322bbed731ae
> --- /dev/null
> +++ b/include/linux/ascii85.h
> @@ -0,0 +1,39 @@
> +
> +/*
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (c) 2008 Intel Corporation
> + * Copyright (c) The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _ASCII85_H_
> +#define _ASCII85_H_
> +
> +#include 
> +
> +#define ASCII85_BUFSZ 6
> +
> +static inline long
> +ascii85_encode_len(long len)
> +{
> + return DIV_ROUND_UP(len, 4);
> +}
> +
> +static inline char *
> +ascii85_encode(u32 in, char *out)
> +{
> + int i;
> +
> + if (in == 0)
> + return "z";
> +
> + out[5] = '\0';
> + for (i = 5; i--; ) {
> + out[i] = '!' + in % 85;
> + in /= 85;
> + }
> +
> + return out;
> +}
> +
> +#endif
> -- 
> 2.16.1
> 
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a Linux Foundation Collaborative Project
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[Intel-gfx] [PATCH 01/10] include: Move ascii85 functions from i915 to linux/ascii85.h

2018-04-05 Thread Jordan Crouse

The i915 DRM driver very cleverly used ascii85 encoding for their
GPU state file. Move the encode functions to a general header file to
support other drivers that might be interested in the same
functionality.

Reviewed-by: Chris Wilson 
Signed-off-by: Jordan Crouse 
 drivers/gpu/drm/i915/i915_gpu_error.c | 35 ---
 include/linux/ascii85.h   | 39 +++
 2 files changed, 43 insertions(+), 31 deletions(-)
 create mode 100644 include/linux/ascii85.h

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 67c902412193..969d967e58c7 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -31,7 +31,7 @@
 #include 
 #include 
 #include 
-
+#include 
 #include "i915_drv.h"
 
 static inline const struct intel_engine_cs *
@@ -518,35 +518,12 @@ void i915_error_printf(struct drm_i915_error_state_buf 
*e, const char *f, ...)
va_end(args);
 }
 
-static int
-ascii85_encode_len(int len)
-{
-   return DIV_ROUND_UP(len, 4);
-}
-
-static bool
-ascii85_encode(u32 in, char *out)
-{
-   int i;
-
-   if (in == 0)
-   return false;
-
-   out[5] = '\0';
-   for (i = 5; i--; ) {
-   out[i] = '!' + in % 85;
-   in /= 85;
-   }
-
-   return true;
-}
-
 static void print_error_obj(struct drm_i915_error_state_buf *m,
struct intel_engine_cs *engine,
const char *name,
struct drm_i915_error_object *obj)
 {
-   char out[6];
+   char out[ASCII85_BUFSZ];
int page;
 
if (!obj)
@@ -568,12 +545,8 @@ static void print_error_obj(struct 
drm_i915_error_state_buf *m,
len -= obj->unused;
len = ascii85_encode_len(len);
 
-   for (i = 0; i < len; i++) {
-   if (ascii85_encode(obj->pages[page][i], out))
-   err_puts(m, out);
-   else
-   err_puts(m, "z");
-   }
+   for (i = 0; i < len; i++)
+   error_puts(m, ascii85_encode(obj->pages[page][i], out));
}
err_puts(m, "\n");
 }
diff --git a/include/linux/ascii85.h b/include/linux/ascii85.h
new file mode 100644
index ..322bbed731ae
--- /dev/null
+++ b/include/linux/ascii85.h
@@ -0,0 +1,39 @@
+
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2008 Intel Corporation
+ * Copyright (c) The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _ASCII85_H_
+#define _ASCII85_H_
+
+#include 
+
+#define ASCII85_BUFSZ 6
+
+static inline long
+ascii85_encode_len(long len)
+{
+   return DIV_ROUND_UP(len, 4);
+}
+
+static inline char *
+ascii85_encode(u32 in, char *out)
+{
+   int i;
+
+   if (in == 0)
+   return "z";
+
+   out[5] = '\0';
+   for (i = 5; i--; ) {
+   out[i] = '!' + in % 85;
+   in /= 85;
+   }
+
+   return out;
+}
+
+#endif
-- 
2.16.1

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[Intel-gfx] [PATCH v4] drm/i915: Enable edp psr error interrupts on hsw

2018-04-05 Thread Dhinakaran Pandiyan

From: Daniel Vetter 

The definitions for the error register should be valid on bdw/skl too,
but there we haven't even enabled DE_MISC handling yet.

Somewhat confusing the the moved register offset on bdw is only for
the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
on bdw.

v2: Fixes from Ville.

v3: From DK
 * Rebased on drm-tip
 * Removed BDW IIR bit definition, looks like an unintentional change that
should be in the following patch.

v4: From DK
 * Don't mask REG_WRITE.

References: bspec/11974 [SRD Interrupt Bit Definition DevHSW]
Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Cc: Daniel Vetter 
Signed-off-by: Daniel Vetter 
Signed-off-by: Dhinakaran Pandiyan 
Reviewed-by: Jose Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_irq.c | 34 ++
 drivers/gpu/drm/i915/i915_reg.h |  8 
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27aee25429b7..c2d3f30778ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct 
drm_i915_private *dev_priv,
ironlake_rps_change_irq_handler(dev_priv);
 }
 
+static void hsw_edp_psr_irq_handler(struct drm_i915_private *dev_priv)
+{
+   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
+
+   if (edp_psr_iir & EDP_PSR_ERROR)
+   DRM_DEBUG_KMS("PSR error\n");
+
+   if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
+   DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
+   I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
+   }
+
+   if (edp_psr_iir & EDP_PSR_POST_EXIT) {
+   DRM_DEBUG_KMS("PSR exit completed\n");
+   I915_WRITE(EDP_PSR_IMR, 0);
+   }
+
+   I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
+}
+
 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
u32 de_iir)
 {
@@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct 
drm_i915_private *dev_priv,
if (de_iir & DE_ERR_INT_IVB)
ivb_err_int_handler(dev_priv);
 
+   if (de_iir & DE_EDP_PSR_INT_HSW)
+   hsw_edp_psr_irq_handler(dev_priv);
+
if (de_iir & DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev_priv);
 
@@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct drm_device *dev)
if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0x);
 
+   if (IS_HASWELL(dev_priv)) {
+   I915_WRITE(EDP_PSR_IMR, 0x);
+   I915_WRITE(EDP_PSR_IIR, 0x);
+   }
+
gen5_gt_irq_reset(dev_priv);
 
ibx_irq_reset(dev_priv);
@@ -3671,6 +3699,12 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
  DE_DP_A_HOTPLUG);
}
 
+   if (IS_HASWELL(dev_priv)) {
+   gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
+   I915_WRITE(EDP_PSR_IMR, 0);
+   display_mask |= DE_EDP_PSR_INT_HSW;
+   }
+
dev_priv->irq_mask = ~display_mask;
 
ibx_irq_pre_postinstall(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6554f4..f5783d6db614 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4011,6 +4011,13 @@ enum {
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
+/* Bspec claims those aren't shifted but stay at 0x64800 */
+#define EDP_PSR_IMR_MMIO(0x64834)
+#define EDP_PSR_IIR_MMIO(0x64838)
+#define   EDP_PSR_ERROR(1<<2)
+#define   EDP_PSR_POST_EXIT(1<<1)
+#define   EDP_PSR_PRE_ENTRY(1<<0)
+
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK(3 << 26)
 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK(0x1f << 20)
@@ -6820,6 +6827,7 @@ enum {
 #define DE_PCH_EVENT_IVB   (1<<28)
 #define DE_DP_A_HOTPLUG_IVB(1<<27)
 #define DE_AUX_CHANNEL_A_IVB   (1<<26)
+#define DE_EDP_PSR_INT_HSW (1<<19)
 #define DE_SPRITEC_FLIP_DONE_IVB   (1<<14)
 #define DE_PLANEC_FLIP_DONE_IVB(1<<13)
 #define DE_PIPEC_VBLANK_IVB(1<<10)
-- 
2.14.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: set minimum CD clock to twice the BCLK. (rev3)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915: set minimum CD clock to twice the BCLK. (rev3)
URL   : https://patchwork.freedesktop.org/series/32657/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8183ab2bd26b drm/i915: set minimum CD clock to twice the BCLK.
-:98: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#98: FILE: drivers/gpu/drm/i915/intel_cdclk.c:1532:
+   cdclk_state.cdclk = glk_calc_cdclk((2*96000));
 ^

total: 0 errors, 0 warnings, 1 checks, 88 lines checked

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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Enable edp psr error interrupts on hsw

2018-04-05 Thread Souza, Jose

On Thu, 2018-04-05 at 14:42 -0700, Dhinakaran Pandiyan wrote:
> 
> 
> On Thu, 2018-04-05 at 20:40 +, Souza, Jose wrote:
> > On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> > > From: Daniel Vetter 
> > > 
> > > The definitions for the error register should be valid on bdw/skl
> > > too,
> > > but there we haven't even enabled DE_MISC handling yet.
> > > 
> > > Somewhat confusing the the moved register offset on bdw is only
> > > for
> > > the _CTL/_AUX register, and that _IIR/IMR stayed where they have
> > > been
> > > on bdw.
> > > 
> > > v2: Fixes from Ville.
> > > 
> > > v3: From DK
> > >  * Rebased on drm-tip
> > >  * Removed BDW IIR bit definition, looks like an unintentional
> > > change
> > > that
> > > should be in the following patch.
> > > 
> > > v4: From DK
> > >  * Don't mask REG_WRITE.
> > > 
> > > Cc: Ville Syrjälä 
> > > Cc: Rodrigo Vivi 
> > > Cc: Daniel Vetter 
> > 
> > With bspec id and comment about why are you masking interruptions
> > in
> > hsw_edp_psr_irq_handler() feel free to add:
> > 
> > Reviewed-by: Jose Roberto de Souza 
> > 
> > > Signed-off-by: Daniel Vetter 
> > > Signed-off-by: Dhinakaran Pandiyan  > > >
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 34
> > > ++
> > >  drivers/gpu/drm/i915/i915_reg.h |  8 
> > >  2 files changed, 42 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 27aee25429b7..c2d3f30778ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct
> > > drm_i915_private *dev_priv,
> > >   ironlake_rps_change_irq_handler(dev_priv);
> > >  }
> > >  
> > > +static void hsw_edp_psr_irq_handler(struct drm_i915_private
> > > *dev_priv)
> > > +{
> > > + u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> > > +
> > > + if (edp_psr_iir & EDP_PSR_ERROR)
> > > + DRM_DEBUG_KMS("PSR error\n");
> > > +
> > > + if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
> > > + DRM_DEBUG_KMS("PSR prepare entry in 2
> > > vblanks\n");
> > > + I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
> > 
> > Just to know... you need to mask this one otherwise it will keep
> > triggering EDP_PSR_PRE_ENTRY interruptions? Would be nice to have a
> > comment explaning why you are masking it.
> > 
> 
> The final implementation in patch 3/4 doesn't do that. Adding a
> comment
> here and removing will be pointless IMO.

Okay

> 
> > > + }
> > > +
> > > + if (edp_psr_iir & EDP_PSR_POST_EXIT) {
> > > + DRM_DEBUG_KMS("PSR exit completed\n");
> > > + I915_WRITE(EDP_PSR_IMR, 0);
> > > + }
> > > +
> > > + I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
> > > +}
> > > +
> > >  static void ivb_display_irq_handler(struct drm_i915_private
> > > *dev_priv,
> > >   u32 de_iir)
> > >  {
> > > @@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct
> > > drm_i915_private *dev_priv,
> > >   if (de_iir & DE_ERR_INT_IVB)
> > >   ivb_err_int_handler(dev_priv);
> > >  
> > > + if (de_iir & DE_EDP_PSR_INT_HSW)
> > > + hsw_edp_psr_irq_handler(dev_priv);
> > > +
> > >   if (de_iir & DE_AUX_CHANNEL_A_IVB)
> > >   dp_aux_irq_handler(dev_priv);
> > >  
> > > @@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct
> > > drm_device *dev)
> > >   if (IS_GEN7(dev_priv))
> > >   I915_WRITE(GEN7_ERR_INT, 0x);
> > >  
> > > + if (IS_HASWELL(dev_priv)) {
> > > + I915_WRITE(EDP_PSR_IMR, 0x);
> > > + I915_WRITE(EDP_PSR_IIR, 0x);
> > 
> > No need to do a POSTING_READ(EDP_PSR_IMR);? Like is done in:
> > GEN3_IRQ_RESET()
> > 
> 
> We should be fine without that. From what I was told a while ago,
> some
> of these POSTING_READS are cargo culted.

Ack

> 
> > > + }
> > > +
> > >   gen5_gt_irq_reset(dev_priv);
> > >  
> > >   ibx_irq_reset(dev_priv);
> > > @@ -3671,6 +3699,12 @@ static int ironlake_irq_postinstall(struct
> > > drm_device *dev)
> > > DE_DP_A_HOTPLUG);
> > >   }
> > >  
> > > + if (IS_HASWELL(dev_priv)) {
> > > + gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
> > > + I915_WRITE(EDP_PSR_IMR, 0);
> > > + display_mask |= DE_EDP_PSR_INT_HSW;
> > > + }
> > > +
> > >   dev_priv->irq_mask = ~display_mask;
> > >  
> > >   ibx_irq_pre_postinstall(dev);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 176dca6554f4..f5783d6db614 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4011,6 +4011,13 @@ enum {
> > >  #define   EDP_PSR_TP1_TIME_0us   (3<<4)
> > >  #define   EDP_PSR_IDLE_FRAME_SHIFT   0
> > >  
> > > +/* Bspec claims those aren't shifted but stay at 0x64800 */
> > > +#define EDP_PSR_IMR  _MMIO(0x64834
> > > )
> > > +#define EDP_PSR_IIR

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: Fix audio issue on BXT

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915/audio: Fix audio issue on BXT
URL   : https://patchwork.freedesktop.org/series/41227/
State : success

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test drv_selftest:
Subgroup live_gtt:
pass   -> INCOMPLETE (shard-apl) fdo#103927
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup 2x-modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup 2x-plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +1
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2657 pass:1811 dwarn:1   dfail:0   fail:7   skip:836 
time:12162s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 
time:11354s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6930s
Blacklisted hosts:
shard-kbltotal:1957 pass:1374 dwarn:33  dfail:1   fail:7   skip:542 
time:6262s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8603/shards.html
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Enable edp psr error interrupts on bdw+

2018-04-05 Thread Pandiyan, Dhinakaran




On Thu, 2018-04-05 at 20:38 +, Souza, Jose wrote:
> On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> > From: Ville Syrjälä 
> > 
> > Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr
> > on
> > any transcoder in theory, though the we don't currenty enable PSR
> > except
> > on the EDP transcoder.
> > 
> > v2: From DK
> >  * Rebased on drm-tip
> > v3: Switched author to Ville based on IRC discussion.
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Daniel Vetter 
> 
> Reviewed-by: Jose Roberto de Souza 
> 
> > Signed-off-by: Ville Syrjälä 
> > Signed-off-by: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c  | 57
> > 
> >  drivers/gpu/drm/i915/i915_reg.h  |  7 +++--
> >  drivers/gpu/drm/i915/intel_display.h |  4 +++
> >  3 files changed, 52 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index c2d3f30778ee..8a894adf2ca1 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2394,20 +2394,34 @@ static void ilk_display_irq_handler(struct
> > drm_i915_private *dev_priv,
> >  static void hsw_edp_psr_irq_handler(struct drm_i915_private
> > *dev_priv)
> 
> nitpick: Like I said in the other patch I would like to have this
> function renamed here.


To intel_psr_irq_handler? I renamed it in patch 3 because the function
was moved out of the file. I would like to leave this patch as it is, as
the original author intended.
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[Intel-gfx] [PATCH v3] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Lyude Paul

When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought this might be an issue with us accidentally shutting
off the aux block when putting the sink into D3, but since the DP spec
mandates that sinks must wake up within 1ms while we have 100ms to
respond to an ESI irq, this didn't really add up. Turns out that the
problem is more subtle then that:

It turns out that the timeout is from us not enabling DPMS on the MST
hub before actually trying to initiate sideband communications. This
would cause the first sideband communication (power_up_phy()), to start
timing out because the sink wasn't ready to respond. Afterwards, we
would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
intel_ddi_pre_enable_dp(), which would actually result in waking up the
sink so that sideband requests would work again.

Since DPMS is what lets us actually bring the hub up into a state where
sideband communications become functional again, we just need to make
sure to enable DPMS on the display before attempting to perform sideband
communications.

Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
  keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send
  DPMS on when we're enabling the first sink - dhnkrn

Signed-off-by: Lyude Paul 
Cc: Dhinakaran Pandiyan 
Cc: Ville Syrjälä 
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
---
 drivers/gpu/drm/i915/intel_ddi.c| 6 --
 drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9abd85..c0bf7419e1c1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
intel_ddi_init_dp_buf_reg(encoder);
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   if (!intel_dp->is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2427,7 +2428,8 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   if (!intel_dp->is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_disable_ddi_buf(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index c3de0918ee13..9e6956c08688 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
intel_dp->active_mst_links--;
 
intel_mst->connector = NULL;
-   if (intel_dp->active_mst_links == 0)
+   if (intel_dp->active_mst_links == 0) {
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
intel_dig_port->base.post_disable(&intel_dig_port->base,
  old_crtc_state, NULL);
+   }
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
+   if (intel_dp->active_mst_links == 0)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
+
if (intel_dp->active_mst_links == 0)
intel_dig_port->base.pre_enable(&intel_dig_port->base,
pipe_config, NULL);
-- 
2.14.3

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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Enable edp psr error interrupts on hsw

2018-04-05 Thread Dhinakaran Pandiyan




On Thu, 2018-04-05 at 20:40 +, Souza, Jose wrote:
> On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> > From: Daniel Vetter 
> > 
> > The definitions for the error register should be valid on bdw/skl
> > too,
> > but there we haven't even enabled DE_MISC handling yet.
> > 
> > Somewhat confusing the the moved register offset on bdw is only for
> > the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
> > on bdw.
> > 
> > v2: Fixes from Ville.
> > 
> > v3: From DK
> >  * Rebased on drm-tip
> >  * Removed BDW IIR bit definition, looks like an unintentional change
> > that
> > should be in the following patch.
> > 
> > v4: From DK
> >  * Don't mask REG_WRITE.
> > 
> > Cc: Ville Syrjälä 
> > Cc: Rodrigo Vivi 
> > Cc: Daniel Vetter 
> 
> With bspec id and comment about why are you masking interruptions in
> hsw_edp_psr_irq_handler() feel free to add:
> 
> Reviewed-by: Jose Roberto de Souza 
> 
> > Signed-off-by: Daniel Vetter 
> > Signed-off-by: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 34
> > ++
> >  drivers/gpu/drm/i915/i915_reg.h |  8 
> >  2 files changed, 42 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 27aee25429b7..c2d3f30778ee 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct
> > drm_i915_private *dev_priv,
> > ironlake_rps_change_irq_handler(dev_priv);
> >  }
> >  
> > +static void hsw_edp_psr_irq_handler(struct drm_i915_private
> > *dev_priv)
> > +{
> > +   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> > +
> > +   if (edp_psr_iir & EDP_PSR_ERROR)
> > +   DRM_DEBUG_KMS("PSR error\n");
> > +
> > +   if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
> > +   DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
> > +   I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
> 
> Just to know... you need to mask this one otherwise it will keep
> triggering EDP_PSR_PRE_ENTRY interruptions? Would be nice to have a
> comment explaning why you are masking it.
> 

The final implementation in patch 3/4 doesn't do that. Adding a comment
here and removing will be pointless IMO.

> > +   }
> > +
> > +   if (edp_psr_iir & EDP_PSR_POST_EXIT) {
> > +   DRM_DEBUG_KMS("PSR exit completed\n");
> > +   I915_WRITE(EDP_PSR_IMR, 0);
> > +   }
> > +
> > +   I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
> > +}
> > +
> >  static void ivb_display_irq_handler(struct drm_i915_private
> > *dev_priv,
> > u32 de_iir)
> >  {
> > @@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct
> > drm_i915_private *dev_priv,
> > if (de_iir & DE_ERR_INT_IVB)
> > ivb_err_int_handler(dev_priv);
> >  
> > +   if (de_iir & DE_EDP_PSR_INT_HSW)
> > +   hsw_edp_psr_irq_handler(dev_priv);
> > +
> > if (de_iir & DE_AUX_CHANNEL_A_IVB)
> > dp_aux_irq_handler(dev_priv);
> >  
> > @@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct
> > drm_device *dev)
> > if (IS_GEN7(dev_priv))
> > I915_WRITE(GEN7_ERR_INT, 0x);
> >  
> > +   if (IS_HASWELL(dev_priv)) {
> > +   I915_WRITE(EDP_PSR_IMR, 0x);
> > +   I915_WRITE(EDP_PSR_IIR, 0x);
> 
> No need to do a POSTING_READ(EDP_PSR_IMR);? Like is done in:
> GEN3_IRQ_RESET()
> 

We should be fine without that. From what I was told a while ago, some
of these POSTING_READS are cargo culted.

> > +   }
> > +
> > gen5_gt_irq_reset(dev_priv);
> >  
> > ibx_irq_reset(dev_priv);
> > @@ -3671,6 +3699,12 @@ static int ironlake_irq_postinstall(struct
> > drm_device *dev)
> >   DE_DP_A_HOTPLUG);
> > }
> >  
> > +   if (IS_HASWELL(dev_priv)) {
> > +   gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
> > +   I915_WRITE(EDP_PSR_IMR, 0);
> > +   display_mask |= DE_EDP_PSR_INT_HSW;
> > +   }
> > +
> > dev_priv->irq_mask = ~display_mask;
> >  
> > ibx_irq_pre_postinstall(dev);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 176dca6554f4..f5783d6db614 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4011,6 +4011,13 @@ enum {
> >  #define   EDP_PSR_TP1_TIME_0us (3<<4)
> >  #define   EDP_PSR_IDLE_FRAME_SHIFT 0
> >  
> > +/* Bspec claims those aren't shifted but stay at 0x64800 */
> > +#define EDP_PSR_IMR_MMIO(0x64834)
> > +#define EDP_PSR_IIR_MMIO(0x64838)
> > +#define   EDP_PSR_ERROR(1<<2)
> > +#define   EDP_PSR_POST_EXIT(1<<1)
> > +#define   EDP_PSR_PRE_ENTRY(1<<0)
> 
> Could you add the bspec id of where did you got this?
> The hsw spec that I'm reading don't have the bits, s

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)
URL   : https://patchwork.freedesktop.org/series/41230/
State : success

== Summary ==

Series 41230v2 series starting with [1/7] drm/arc: Stop consulting plane->fb
https://patchwork.freedesktop.org/api/1.0/series/41230/revisions/2/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
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fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
d1d669671e9b drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc
fbcdb617ee01 drm/vmwgfx: Stop using plane->fb in atomic_enable()
91ef12040af0 drm/vmwgfx: Stop updating plane->fb
416b0dd8d5bc drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
6cdbeabec8d8 drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
488cc436263f drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
72b80067880c drm/arc: Stop consulting plane->fb

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8606/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)
URL   : https://patchwork.freedesktop.org/series/41230/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
72b80067880c drm/arc: Stop consulting plane->fb
-:22: WARNING:BAD_SIGN_OFF: Duplicate signature
#22: 
Reviewed-by: Daniel Vetter 

total: 0 errors, 1 warnings, 0 checks, 9 lines checked
488cc436263f drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
6cdbeabec8d8 drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#12: 
concluded that the calls originating from vmw_*_primary_plane_atomic_update()

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
416b0dd8d5bc drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
91ef12040af0 drm/vmwgfx: Stop updating plane->fb
fbcdb617ee01 drm/vmwgfx: Stop using plane->fb in atomic_enable()
d1d669671e9b drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc

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Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Pandiyan, Dhinakaran




On Thu, 2018-04-05 at 16:36 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> originally thought this might be an issue with us accidentally shutting
> off the aux block when putting the sink into D3, but since the DP spec
> mandates that sinks must wake up within 1ms while we have 100ms to
> respond to an ESI irq, this didn't really add up. Turns out that the
> problem is more subtle then that:
> 
> It turns out that the timeout is from us not enabling DPMS on the MST
> hub before actually trying to initiate sideband communications. This
> would cause the first sideband communication (power_up_phy()), to start
> timing out because the sink wasn't ready to respond. Afterwards, we
> would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> intel_ddi_pre_enable_dp(), which would actually result in waking up the
> sink so that sideband requests would work again.
> 
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
> 
> Changes since v1:
> - Remove comment above if (!intel_dp->is_mst) - vsryjala
> - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
>   keep enable/disable paths symmetrical
> - Improve commit message - dhnkrn
> 
> Signed-off-by: Lyude Paul 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Cc: Laura Abbott 
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> hub.")
> ---
> This email should hopefully actually be picked up by patchwork this
> time, hooray!
> 
>  drivers/gpu/drm/i915/intel_ddi.c| 6 --
>  drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..c0bf7419e1c1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
>   if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>   intel_dp_stop_link_train(intel_dp);
> @@ -2427,7 +2428,8 @@ static void intel_ddi_post_disable_dp(struct 
> intel_encoder *encoder,
>* Power down sink before disabling the port, otherwise we end
>* up getting interrupts from the sink on detecting link loss.
>*/
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  
>   intel_disable_ddi_buf(encoder);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index c3de0918ee13..2493bd1e0e59 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -176,6 +176,7 @@ static void intel_mst_post_disable_dp(struct 
> intel_encoder *encoder,
>*/
>   drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
>false);
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);

Needed only when _links goes from 1 -> 0
>  
>   intel_dp->active_mst_links--;
>  
> @@ -223,6 +224,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
> *encoder,
>  
>   DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Needed only when _links goes from 0 -> 1
>   drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
>   if (intel_dp->active_mst_links == 0)
>   intel_dig_port->base.pre_enable(&intel_dig_port->base,
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Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Lyude Paul

Actually - ignore this patch, I'm going to do a v3 because i just noticed
there is something very silly and broken I just introduced into the disable
codepath

On Thu, 2018-04-05 at 16:36 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> originally thought this might be an issue with us accidentally shutting
> off the aux block when putting the sink into D3, but since the DP spec
> mandates that sinks must wake up within 1ms while we have 100ms to
> respond to an ESI irq, this didn't really add up. Turns out that the
> problem is more subtle then that:
> 
> It turns out that the timeout is from us not enabling DPMS on the MST
> hub before actually trying to initiate sideband communications. This
> would cause the first sideband communication (power_up_phy()), to start
> timing out because the sink wasn't ready to respond. Afterwards, we
> would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> intel_ddi_pre_enable_dp(), which would actually result in waking up the
> sink so that sideband requests would work again.
> 
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
> 
> Changes since v1:
> - Remove comment above if (!intel_dp->is_mst) - vsryjala
> - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
>   keep enable/disable paths symmetrical
> - Improve commit message - dhnkrn
> 
> Signed-off-by: Lyude Paul 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Cc: Laura Abbott 
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST
> hub.")
> ---
> This email should hopefully actually be picked up by patchwork this
> time, hooray!
> 
>  drivers/gpu/drm/i915/intel_ddi.c| 6 --
>  drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..c0bf7419e1c1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
>   if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>   intel_dp_stop_link_train(intel_dp);
> @@ -2427,7 +2428,8 @@ static void intel_ddi_post_disable_dp(struct
> intel_encoder *encoder,
>* Power down sink before disabling the port, otherwise we end
>* up getting interrupts from the sink on detecting link loss.
>*/
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + if (!intel_dp->is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  
>   intel_disable_ddi_buf(encoder);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index c3de0918ee13..2493bd1e0e59 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -176,6 +176,7 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder,
>*/
>   drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
>false);
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  
>   intel_dp->active_mst_links--;
>  
> @@ -223,6 +224,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
>  
>   DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
> true);
>   if (intel_dp->active_mst_links == 0)
>   intel_dig_port->base.pre_enable(&intel_dig_port->base,
-- 
Cheers,
Lyude Paul
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Re: [Intel-gfx] [PATCH 1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Daniel Vetter

On Thu, Apr 05, 2018 at 11:19:44PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 05, 2018 at 10:08:57PM +0200, Daniel Vetter wrote:
> > On Thu, Apr 05, 2018 at 10:50:29PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > We want to stop using plane->fb with atomic driver, so stop looking at
> > > it.
> > > 
> > > I have no idea what this code is trying to achieve. There is no
> > > corresponding check in the enable path. Also since
> > > arc_pgu_set_pxl_fmt() will anyway oops if there is no fb I'm going
> > > to assuming that I can just remove the check entirely. There seems
> > > to be a general shortage of .atomic_check() in this driver...
> > 
> > I think arcpgu is the perfect example of a small driver that _really_
> > wants to use drm_simple_display_pipe_helper. Which would address the
> > outright lack of any and all atomic_check code (beyond basic mode
> > validation through mode_valid).
> > 
> > I also just noticed that it still has a bunch of the legacy hooks set,
> > e.g. mode_set, mode_set_base are all no longer used in atomic.
> > 
> > I think the code won't be able to oops, since if there's no fb, we don't
> > enable the plane (and it happily allows that), so should be all
> > non-oopsing. Even with this check here removed.
> 
> arc_pgu_set_pxl_fmt() gets called from the .mode_set_nofb() hook
> which I assume doesn't care about planes at all. So to me it looks like
> it'll definitely oops.

Indeed, I was blind. Commit message looks good.

Reviewed-by: Daniel Vetter 

> 
> > 
> > Ofc the hw might get pissed at us in this case, but I can't tell that.
> > Like I said, conversion to drm_simple_display_pipe_helper is probably the
> > way to go.
> > 
> > Anyway, this patch here looks good, if you adjust the commit message to
> > explain why it can't oops:
> > 
> > Reviewed-by: Daniel Vetter 
> > 
> > > 
> > > Cc: Alexey Brodkin 
> > > Cc: Daniel Vetter 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/arc/arcpgu_crtc.c | 3 ---
> > >  1 file changed, 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c 
> > > b/drivers/gpu/drm/arc/arcpgu_crtc.c
> > > index 16903dc7fe0d..c3349b8fb58b 100644
> > > --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> > > +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> > > @@ -136,9 +136,6 @@ static void arc_pgu_crtc_atomic_disable(struct 
> > > drm_crtc *crtc,
> > >  {
> > >   struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> > >  
> > > - if (!crtc->primary->fb)
> > > - return;
> > > -
> > >   clk_disable_unprepare(arcpgu->clk);
> > >   arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
> > > arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
> > > -- 
> > > 2.16.1
> > > 
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Enable edp psr error interrupts on hsw

2018-04-05 Thread Souza, Jose

On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> From: Daniel Vetter 
> 
> The definitions for the error register should be valid on bdw/skl
> too,
> but there we haven't even enabled DE_MISC handling yet.
> 
> Somewhat confusing the the moved register offset on bdw is only for
> the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
> on bdw.
> 
> v2: Fixes from Ville.
> 
> v3: From DK
>  * Rebased on drm-tip
>  * Removed BDW IIR bit definition, looks like an unintentional change
> that
> should be in the following patch.
> 
> v4: From DK
>  * Don't mask REG_WRITE.
> 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Vivi 
> Cc: Daniel Vetter 

With bspec id and comment about why are you masking interruptions in
hsw_edp_psr_irq_handler() feel free to add:

Reviewed-by: Jose Roberto de Souza 

> Signed-off-by: Daniel Vetter 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 34
> ++
>  drivers/gpu/drm/i915/i915_reg.h |  8 
>  2 files changed, 42 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 27aee25429b7..c2d3f30778ee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>   ironlake_rps_change_irq_handler(dev_priv);
>  }
>  
> +static void hsw_edp_psr_irq_handler(struct drm_i915_private
> *dev_priv)
> +{
> + u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> +
> + if (edp_psr_iir & EDP_PSR_ERROR)
> + DRM_DEBUG_KMS("PSR error\n");
> +
> + if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
> + DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
> + I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);

Just to know... you need to mask this one otherwise it will keep
triggering EDP_PSR_PRE_ENTRY interruptions? Would be nice to have a
comment explaning why you are masking it.

> + }
> +
> + if (edp_psr_iir & EDP_PSR_POST_EXIT) {
> + DRM_DEBUG_KMS("PSR exit completed\n");
> + I915_WRITE(EDP_PSR_IMR, 0);
> + }
> +
> + I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
> +}
> +
>  static void ivb_display_irq_handler(struct drm_i915_private
> *dev_priv,
>   u32 de_iir)
>  {
> @@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct
> drm_i915_private *dev_priv,
>   if (de_iir & DE_ERR_INT_IVB)
>   ivb_err_int_handler(dev_priv);
>  
> + if (de_iir & DE_EDP_PSR_INT_HSW)
> + hsw_edp_psr_irq_handler(dev_priv);
> +
>   if (de_iir & DE_AUX_CHANNEL_A_IVB)
>   dp_aux_irq_handler(dev_priv);
>  
> @@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct
> drm_device *dev)
>   if (IS_GEN7(dev_priv))
>   I915_WRITE(GEN7_ERR_INT, 0x);
>  
> + if (IS_HASWELL(dev_priv)) {
> + I915_WRITE(EDP_PSR_IMR, 0x);
> + I915_WRITE(EDP_PSR_IIR, 0x);

No need to do a POSTING_READ(EDP_PSR_IMR);? Like is done in:
GEN3_IRQ_RESET()

> + }
> +
>   gen5_gt_irq_reset(dev_priv);
>  
>   ibx_irq_reset(dev_priv);
> @@ -3671,6 +3699,12 @@ static int ironlake_irq_postinstall(struct
> drm_device *dev)
> DE_DP_A_HOTPLUG);
>   }
>  
> + if (IS_HASWELL(dev_priv)) {
> + gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
> + I915_WRITE(EDP_PSR_IMR, 0);
> + display_mask |= DE_EDP_PSR_INT_HSW;
> + }
> +
>   dev_priv->irq_mask = ~display_mask;
>  
>   ibx_irq_pre_postinstall(dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 176dca6554f4..f5783d6db614 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4011,6 +4011,13 @@ enum {
>  #define   EDP_PSR_TP1_TIME_0us   (3<<4)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT   0
>  
> +/* Bspec claims those aren't shifted but stay at 0x64800 */
> +#define EDP_PSR_IMR  _MMIO(0x64834)
> +#define EDP_PSR_IIR  _MMIO(0x64838)
> +#define   EDP_PSR_ERROR  (1<<2)
> +#define   EDP_PSR_POST_EXIT  (1<<1)
> +#define   EDP_PSR_PRE_ENTRY  (1<<0)

Could you add the bspec id of where did you got this?
The hsw spec that I'm reading don't have the bits, skl have but don't
have the bits of the other transcoders.

> +
>  #define EDP_PSR_AUX_CTL  _MMIO(dev_pri
> v->psr_mmio_base + 0x10)
>  #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK  (3 << 26)
>  #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK  (0x1f << 20)
> @@ -6820,6 +6827,7 @@ enum {
>  #define DE_PCH_EVENT_IVB (1<<28)
>  #define DE_DP_A_HOTPLUG_IVB  (1<<27)
>  #define DE_AUX_CHANNEL_A_IVB (1<<26)
> +#define DE_EDP_PSR_INT_HSW   (1<<19

Re: [Intel-gfx] [PATCH 7/7] drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc

2018-04-05 Thread Daniel Vetter

On Thu, Apr 05, 2018 at 10:50:35PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> plane->fb/old_fb/crtc should no longer be used by atomic
> drivers. Stop messing about with them.
> 
> TODO: Squash with the core/helper patch?

Not possible, because the core setconfig one does no longer work with
atomic drivers ever since I've thrown away the magic backoff. Since then
we have the rule that for any atomic driver, you need a real atomic commit
(including passing the acquire_ctx down to that very call to
drm_atomic_commit).

See the patch that introduced this copypasta for full details plus how to
fix it up properly:

commit 3bacf4361cd07f988a13de78d672928606df24ad
Author: Daniel Vetter 
Date:   Thu Apr 6 22:02:56 2017 +0200

drm/vmwgfx: Fix fbdev emulation using legacy functions

I've broken this by removing the backoff handling from the
set_config2atomic helper in

commit 38b6441e4e75c0b319cfe4d9364c1059fc1e3c2b
Author: Daniel Vetter 
Date:   Wed Mar 22 22:50:58 2017 +0100

drm/atomic-helper: Remove the backoff hack from set_config

Fixing this properly would mean we get to wire the acquire_ctx all the
way through vmwgfx fbdev code, and doing the same was tricky for the
shared fbdev layer. Probably much better to look into refactoring the
entire code to use the helpers, but since that's not a viable
long-term solution fix the issue by open-coding a vmwgfx version of
set_config, that does the legacy backoff dance internally.

Note: Just compile-tested. The idea is to take
drm_mode_set_config_internal(), remove the "is this a legacy driver"
check, and whack the drm_atomic_legacy_backoff trickery at the end.
Since drm_atomic_legacy_backoff is for atomic commits only we need to
open-code it.

Cc: Thomas Hellstrom 
Signed-off-by: Daniel Vetter 
Reviewed-by: Thomas Hellstrom 
Signed-off-by: Sean Paul 
Link: 
http://patchwork.freedesktop.org/patch/msgid/20170406200256.26040-1-daniel.vet...@ffwll.ch

I scrolled through your vmwgfx patches, and will try to look at them maybe
next week. Too complicated for this late, and tomorrow I'm ooo.
-Daniel

> 
> Cc: Thomas Hellstrom 
> Cc: Sinclair Yeh 
> Cc: VMware Graphics 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/vmwgfx/vmwgfx_fb.c | 24 
>  1 file changed, 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c 
> b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
> index 2582ffd36bb5..3c5935f3d49e 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
> @@ -439,8 +439,6 @@ static int vmw_fb_compute_depth(struct fb_var_screeninfo 
> *var,
>  static int vmwgfx_set_config_internal(struct drm_mode_set *set)
>  {
>   struct drm_crtc *crtc = set->crtc;
> - struct drm_framebuffer *fb;
> - struct drm_crtc *tmp;
>   struct drm_modeset_acquire_ctx *ctx;
>   struct drm_device *dev = set->crtc->dev;
>   int ret;
> @@ -448,29 +446,7 @@ static int vmwgfx_set_config_internal(struct 
> drm_mode_set *set)
>   ctx = dev->mode_config.acquire_ctx;
>  
>  restart:
> - /*
> -  * NOTE: ->set_config can also disable other crtcs (if we steal all
> -  * connectors from it), hence we need to refcount the fbs across all
> -  * crtcs. Atomic modeset will have saner semantics ...
> -  */
> - drm_for_each_crtc(tmp, dev)
> - tmp->primary->old_fb = tmp->primary->fb;
> -
> - fb = set->fb;
> -
>   ret = crtc->funcs->set_config(set, ctx);
> - if (ret == 0) {
> - crtc->primary->crtc = crtc;
> - crtc->primary->fb = fb;
> - }
> -
> - drm_for_each_crtc(tmp, dev) {
> - if (tmp->primary->fb)
> - drm_framebuffer_get(tmp->primary->fb);
> - if (tmp->primary->old_fb)
> - drm_framebuffer_put(tmp->primary->old_fb);
> - tmp->primary->old_fb = NULL;
> - }
>  
>   if (ret == -EDEADLK) {
>   dev->mode_config.acquire_ctx = NULL;
> -- 
> 2.16.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Enable edp psr error interrupts on bdw+

2018-04-05 Thread Souza, Jose

On Tue, 2018-04-03 at 14:24 -0700, Dhinakaran Pandiyan wrote:
> From: Ville Syrjälä 
> 
> Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr
> on
> any transcoder in theory, though the we don't currenty enable PSR
> except
> on the EDP transcoder.
> 
> v2: From DK
>  * Rebased on drm-tip
> v3: Switched author to Ville based on IRC discussion.
> 
> Cc: Rodrigo Vivi 
> Cc: Daniel Vetter 

Reviewed-by: Jose Roberto de Souza 

> Signed-off-by: Ville Syrjälä 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/i915_irq.c  | 57
> 
>  drivers/gpu/drm/i915/i915_reg.h  |  7 +++--
>  drivers/gpu/drm/i915/intel_display.h |  4 +++
>  3 files changed, 52 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index c2d3f30778ee..8a894adf2ca1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2394,20 +2394,34 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>  static void hsw_edp_psr_irq_handler(struct drm_i915_private
> *dev_priv)

nitpick: Like I said in the other patch I would like to have this
function renamed here.

>  {
>   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> + u32 edp_psr_imr = I915_READ(EDP_PSR_IMR);
> + u32 mask = BIT(TRANSCODER_EDP);
> + enum transcoder cpu_transcoder;
>  
> - if (edp_psr_iir & EDP_PSR_ERROR)
> - DRM_DEBUG_KMS("PSR error\n");
> -
> - if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
> - DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
> - I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
> - }
> + if (INTEL_GEN(dev_priv) >= 8)
> + mask |= BIT(TRANSCODER_A) |
> + BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C);
> +
> + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
> mask) {
> + if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder))
> + DRM_DEBUG_KMS("Transcoder %s PSR error\n",
> +   transcoder_name(cpu_transcoder
> ));
> +
> + if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder))
> {
> + DRM_DEBUG_KMS("Transcoder %s PSR prepare
> entry in 2 vblanks\n",
> +   transcoder_name(cpu_transcoder
> ));
> + edp_psr_imr |=
> EDP_PSR_PRE_ENTRY(cpu_transcoder);
> + }
>  
> - if (edp_psr_iir & EDP_PSR_POST_EXIT) {
> - DRM_DEBUG_KMS("PSR exit completed\n");
> - I915_WRITE(EDP_PSR_IMR, 0);
> + if (edp_psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder))
> {
> + DRM_DEBUG_KMS("Transcoder %s PSR exit
> completed\n",
> +   transcoder_name(cpu_transcoder
> ));
> + edp_psr_imr &=
> ~EDP_PSR_PRE_ENTRY(cpu_transcoder);
> + }
>   }
>  
> + I915_WRITE(EDP_PSR_IMR, edp_psr_imr);
>   I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
>  }
>  
> @@ -2555,11 +2569,22 @@ gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
>   if (master_ctl & GEN8_DE_MISC_IRQ) {
>   iir = I915_READ(GEN8_DE_MISC_IIR);
>   if (iir) {
> + bool found = false;
> +
>   I915_WRITE(GEN8_DE_MISC_IIR, iir);
>   ret = IRQ_HANDLED;
> - if (iir & GEN8_DE_MISC_GSE)
> +
> + if (iir & GEN8_DE_MISC_GSE) {
>   intel_opregion_asle_intr(dev_priv);
> - else
> + found = true;
> + }
> +
> + if (iir & GEN8_DE_EDP_PSR) {
> + hsw_edp_psr_irq_handler(dev_priv);
> + found = true;
> + }
> +
> + if (!found)
>   DRM_ERROR("Unexpected DE Misc
> interrupt\n");
>   }
>   else
> @@ -3326,6 +3351,9 @@ static void gen8_irq_reset(struct drm_device
> *dev)
>  
>   gen8_gt_irq_reset(dev_priv);
>  
> + I915_WRITE(EDP_PSR_IMR, 0x);
> + I915_WRITE(EDP_PSR_IIR, 0x);
> +
>   for_each_pipe(dev_priv, pipe)
>   if (intel_display_power_is_enabled(dev_priv,
>  POWER_DOMAIN_PIPE
> (pipe)))
> @@ -3815,7 +3843,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>   uint32_t de_pipe_enables;
>   u32 de_port_masked = GEN8_AUX_CHANNEL_A;
>   u32 de_port_enables;
> - u32 de_misc_masked = GEN8_DE_MISC_GSE;
> + u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
>   enum pipe pipe;
>  
>   if (INTEL_GEN(dev_priv) >= 9) {
> @@ -3840,6 +3868,9 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>   else if (IS_BROADWELL(dev_priv))

Re: [Intel-gfx] [PATCH 2/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()

2018-04-05 Thread Deepak Singh Rawat

> 
> On Thu, Apr 05, 2018 at 08:15:05PM +, Deepak Singh Rawat wrote:
> >
> > >
> > > From: Ville Syrjälä 
> > >
> > > Instead of looking at plane->fb let's look at the proper new
> > > plane state.
> > >
> > > Not that the code makes a ton of sense. It's only going through the
> > > crtcs in the atomic state, so assuming not all of them are included
> > > we're not even calculating the total bandwidth here. Also we're
> > > not considering whether each crtc is actually enabled or not.
> > >
> > > Cc: Thomas Hellstrom 
> > > Cc: Sinclair Yeh 
> > > Cc: VMware Graphics 
> > > Cc: Daniel Vetter 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 10 +++---
> > >  1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > > b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > > index 6728c6247b4b..a2a796b4cc23 100644
> > > --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > > +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > > @@ -1536,9 +1536,13 @@ vmw_kms_atomic_check_modeset(struct
> > > drm_device *dev,
> > >   unsigned long requested_bb_mem = 0;
> > >
> > >   if (dev_priv->active_display_unit ==
> > > vmw_du_screen_target) {
> > > - if (crtc->primary->fb) {
> > > - int cpp = crtc->primary->fb->pitches[0] /
> > > -   crtc->primary->fb->width;
> > > + struct drm_plane *plane = crtc->primary;
> > > + struct drm_plane_state *plane_state;
> > > +
> > > + plane_state =
> > > drm_atomic_get_new_plane_state(state, plane);
> > > +
> > > + if (plane_state && plane_state->fb) {
> > > + int cpp = plane_state->fb->format->cpp[0];
> >
> > Hi Ville,
> >
> > Thanks for the patch, recently I have done some refactoring of this code
> area
> > which is no yet sent to dri-devel. But the refactored code eliminated the
> need
> > to look the fb
> >
> > https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__cgit.freedesktop.org_mesa_vmwgfx_commit_-3Fid-
> 3Dc54cdb6549b7d1c04ff61e639fc0e6de0dcc1ed6&d=DwIDAw&c=uilaK90D4T
> OVoH58JNXRgQ&r=zOOG28inJK0762SxAf-
> cyZdStnd2NQpRu98lJP2iYGw&m=lrHQqnjNpBdFNzU0f4b3rLTtaYp0VRzCgZztJ
> ew0kz0&s=mz1Kt2NO_HIpgVtQ9xHvKRQLGXx2HSqY8xt0oiEpGWg&e=
> 
> Hmm. What's the timelike for landing that stuff?

I am not sure, I still think there is more work here to clean this up. I guess 
for now
we can have your patch to take care of avoiding plane->fb.

> 
> A cursory glance tells me we should just change the current code with
> s/cpp/4/ and it should still be fine?

Yes replacing cpp with 4 is fine as that is what virtual hardware always look 
for.

> 
> BTW the drm_for_each_crtc(crtc, dev) loop in there doesn't look entirely
> kosher. It's potentially going to access crtc->state w/o holding the lock.

Thanks for the suggestion, I will look into this.

> 
> >
> > There is still some future work to be done in this area.
> >
> > >
> > >   requested_bb_mem += crtc->mode.hdisplay
> > > * cpp *
> > >   crtc->mode.vdisplay;
> > > --
> > > 2.16.1
> 
> --
> Ville Syrjälä
> Intel OTC
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[Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

2018-04-05 Thread Abhay Kumar

In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure CD clock to be twice of  BCLK.

v2:
- Address comment (Jani)
- New design approach

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
Signed-off-by: Abhay Kumar 
---
 drivers/gpu/drm/i915/intel_audio.c | 33 ++---
 drivers/gpu/drm/i915/intel_cdclk.c | 21 +
 drivers/gpu/drm/i915/intel_drv.h   |  1 +
 3 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 709d6ca68074..f7dd3d532e93 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -723,15 +723,37 @@ static void i915_audio_component_put_power(struct device 
*kdev)
intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
 }
 
+/* Get CDCLK in kHz  */
+static int i915_audio_component_get_cdclk_freq(struct device *kdev)
+{
+   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+   if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
+   return -ENODEV;
+
+   return dev_priv->cdclk.hw.cdclk;
+}
+
 static void i915_audio_component_codec_wake_override(struct device *kdev,
 bool enable)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
+   int current_cdclk;
 
if (!IS_GEN9_BC(dev_priv))
return;
 
+   current_cdclk = i915_audio_component_get_cdclk_freq(kdev);
+
+   /*
+* Before probing for HDA Codec we need to make sure
+* "The CD clock frequency must be at least twice
+* the frequency of the Azalia BCLK."
+*/
+   if (INTEL_GEN(dev_priv) >= 9 && current_cdclk <= 192000)
+   intel_cdclk_bump(dev_priv);
+
i915_audio_component_get_power(kdev);
 
/*
@@ -753,17 +775,6 @@ static void 
i915_audio_component_codec_wake_override(struct device *kdev,
i915_audio_component_put_power(kdev);
 }
 
-/* Get CDCLK in kHz  */
-static int i915_audio_component_get_cdclk_freq(struct device *kdev)
-{
-   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
-
-   if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
-   return -ENODEV;
-
-   return dev_priv->cdclk.hw.cdclk;
-}
-
 /*
  * get the intel_encoder according to the parameter port and pipe
  * intel_encoder is saved by the index of pipe
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index dc7db8a2caf8..9426e1b7badc 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1516,6 +1516,27 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 }
 
 /**
+ * intel_cdclk_bump - Increase cdclk to 2* BCLK
+ * @dev_priv: i915 device
+ *
+ * Increase CDCLK for GKL and CNL. This is done only
+ * during HDA codec probe.
+ */
+void intel_cdclk_bump(struct drm_i915_private *dev_priv)
+{
+   struct intel_cdclk_state cdclk_state;
+
+   cdclk_state = dev_priv->cdclk.hw;
+
+   if (IS_GEMINILAKE(dev_priv)) {
+   cdclk_state.cdclk = glk_calc_cdclk((2*96000));
+   cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
+   cdclk_state.voltage_level = 
bxt_calc_voltage_level(cdclk_state.cdclk);
+   bxt_set_cdclk(dev_priv, &cdclk_state);
+   }
+}
+
+/**
  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
  * @dev_priv: i915 device
  *
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1452fd2a58d..5192753df3dc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1417,6 +1417,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
+void intel_cdclk_bump(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void icl_init_cdclk(struct drm_i915_private *dev_priv);
 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
-- 
2.7.4

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[Intel-gfx] [PATCH v2] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Lyude Paul

When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought this might be an issue with us accidentally shutting
off the aux block when putting the sink into D3, but since the DP spec
mandates that sinks must wake up within 1ms while we have 100ms to
respond to an ESI irq, this didn't really add up. Turns out that the
problem is more subtle then that:

It turns out that the timeout is from us not enabling DPMS on the MST
hub before actually trying to initiate sideband communications. This
would cause the first sideband communication (power_up_phy()), to start
timing out because the sink wasn't ready to respond. Afterwards, we
would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
intel_ddi_pre_enable_dp(), which would actually result in waking up the
sink so that sideband requests would work again.

Since DPMS is what lets us actually bring the hub up into a state where
sideband communications become functional again, we just need to make
sure to enable DPMS on the display before attempting to perform sideband
communications.

Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
  keep enable/disable paths symmetrical
- Improve commit message - dhnkrn

Signed-off-by: Lyude Paul 
Cc: Dhinakaran Pandiyan 
Cc: Ville Syrjälä 
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
---
This email should hopefully actually be picked up by patchwork this
time, hooray!

 drivers/gpu/drm/i915/intel_ddi.c| 6 --
 drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9abd85..c0bf7419e1c1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
intel_ddi_init_dp_buf_reg(encoder);
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   if (!intel_dp->is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2427,7 +2428,8 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   if (!intel_dp->is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_disable_ddi_buf(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index c3de0918ee13..2493bd1e0e59 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -176,6 +176,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
 */
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
 false);
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_dp->active_mst_links--;
 
@@ -223,6 +224,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
if (intel_dp->active_mst_links == 0)
intel_dig_port->base.pre_enable(&intel_dig_port->base,
-- 
2.14.3

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[Intel-gfx] [PATCH v2 3/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

Instead of plane->fb (which we're going to deprecate for atomic drivers)
we need to look at plane->state->fb. The maze of code leading to
vmw_kms_helper_dirty() wasn't particularly clear, but my analysis
concluded that the calls originating from vmw_*_primary_plane_atomic_update()
all pass in the crtc which means we'll never end up in this branch
of the function. All other callers use drm_modeset_lock_all() somewhere
higher up, which means accessing plane->state is safe. We'll toss in
a lockdep assert to catch wrongdoers.

v2: Drop the comment and make the code do what it did before (Thomas)

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index a2a796b4cc23..73484ad1ceeb 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -2326,9 +2326,12 @@ int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
} else {
list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
head) {
-   if (crtc->primary->fb != &framebuffer->base)
-   continue;
-   units[num_units++] = vmw_crtc_to_du(crtc);
+   struct drm_plane *plane = crtc->primary;
+
+   lockdep_assert_held(&plane->mutex);
+
+   if (plane->state->fb == &framebuffer->base)
+   units[num_units++] = vmw_crtc_to_du(crtc);
}
}
 
-- 
2.16.1

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Re: [Intel-gfx] [PATCH 2/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()

2018-04-05 Thread Ville Syrjälä

On Thu, Apr 05, 2018 at 08:15:05PM +, Deepak Singh Rawat wrote:
> 
> > 
> > From: Ville Syrjälä 
> > 
> > Instead of looking at plane->fb let's look at the proper new
> > plane state.
> > 
> > Not that the code makes a ton of sense. It's only going through the
> > crtcs in the atomic state, so assuming not all of them are included
> > we're not even calculating the total bandwidth here. Also we're
> > not considering whether each crtc is actually enabled or not.
> > 
> > Cc: Thomas Hellstrom 
> > Cc: Sinclair Yeh 
> > Cc: VMware Graphics 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 10 +++---
> >  1 file changed, 7 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > index 6728c6247b4b..a2a796b4cc23 100644
> > --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > @@ -1536,9 +1536,13 @@ vmw_kms_atomic_check_modeset(struct
> > drm_device *dev,
> > unsigned long requested_bb_mem = 0;
> > 
> > if (dev_priv->active_display_unit ==
> > vmw_du_screen_target) {
> > -   if (crtc->primary->fb) {
> > -   int cpp = crtc->primary->fb->pitches[0] /
> > - crtc->primary->fb->width;
> > +   struct drm_plane *plane = crtc->primary;
> > +   struct drm_plane_state *plane_state;
> > +
> > +   plane_state =
> > drm_atomic_get_new_plane_state(state, plane);
> > +
> > +   if (plane_state && plane_state->fb) {
> > +   int cpp = plane_state->fb->format->cpp[0];
> 
> Hi Ville,
> 
> Thanks for the patch, recently I have done some refactoring of this code area
> which is no yet sent to dri-devel. But the refactored code eliminated the need
> to look the fb
> 
> https://cgit.freedesktop.org/mesa/vmwgfx/commit/?id=c54cdb6549b7d1c04ff61e639fc0e6de0dcc1ed6

Hmm. What's the timelike for landing that stuff?

A cursory glance tells me we should just change the current code with
s/cpp/4/ and it should still be fine?

BTW the drm_for_each_crtc(crtc, dev) loop in there doesn't look entirely
kosher. It's potentially going to access crtc->state w/o holding the lock.

> 
> There is still some future work to be done in this area. 
> 
> > 
> > requested_bb_mem += crtc->mode.hdisplay
> > * cpp *
> > crtc->mode.vdisplay;
> > --
> > 2.16.1

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 3/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()

2018-04-05 Thread Ville Syrjälä

On Thu, Apr 05, 2018 at 10:15:57PM +0200, Thomas Hellstrom wrote:
> On 04/05/2018 09:50 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> >
> > Instead of plane->fb (which we're going to deprecate for atomic drivers)
> > we need to look at plane->state->fb. The maze of code leading to
> > vmw_kms_helper_dirty() wasn't particularly clear, but my analysis
> > concluded that the calls originating from 
> > vmw_*_primary_plane_atomic_update()
> > all pass in the crtc which means we'll never end up in this branch
> > of the function. All other callers use drm_modeset_lock_all() somewhere
> > higher up, which means accessing plane->state is safe. We'll toss in
> > a lockdep assert to catch wrongdoers.
> >
> > Cc: Thomas Hellstrom 
> > Cc: Sinclair Yeh 
> > Cc: VMware Graphics 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >   drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 15 ---
> >   1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
> > b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > index a2a796b4cc23..5a824125c231 100644
> > --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> > @@ -2326,9 +2326,18 @@ int vmw_kms_helper_dirty(struct vmw_private 
> > *dev_priv,
> > } else {
> > list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
> > head) {
> > -   if (crtc->primary->fb != &framebuffer->base)
> > -   continue;
> > -   units[num_units++] = vmw_crtc_to_du(crtc);
> > +   struct drm_plane *plane = crtc->primary;
> > +
> > +   /*
> > +* vmw_*_primary_plane_atomic_update() pass in the crtc,
> > +* and so don't end up here. All other callers use
> > +* drm_modeset_lock_all(), hence we can access the
> > +* plane state safely.
> > +*/
> > +   lockdep_assert_held(&plane->mutex);
> > +
> I think we can remove the comment (it's a helper, so current users may 
> not be future users),
> but the lockdep assert should be OK.

OK.

> > +   if (plane->state->fb != &framebuffer->base)
> > +   units[num_units++] = vmw_crtc_to_du(crtc);
> 
> This doesn't seem to do what the original code did...

Whoops. Good catch.

> 
> > }
> > }
> >   
> 
> /Thomas
> 

-- 
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Intel OTC
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc 
(rev2)
URL   : https://patchwork.freedesktop.org/series/41216/
State : success

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test kms_vblank:
Subgroup pipe-a-accuracy-idle:
pass   -> FAIL   (shard-hsw) fdo#102583
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12708s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11402s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6911s
Blacklisted hosts:
shard-kbltotal:2680 pass:1961 dwarn:1   dfail:1   fail:8   skip:709 
time:9231s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8602/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb
URL   : https://patchwork.freedesktop.org/series/41230/
State : success

== Summary ==

Series 41230v1 series starting with [1/7] drm/arc: Stop consulting plane->fb
https://patchwork.freedesktop.org/api/1.0/series/41230/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:526s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:509s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:589s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:313s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:663s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:448s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:580s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:408s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:529s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
ac7ba740a34d drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc
192117f681f1 drm/vmwgfx: Stop using plane->fb in atomic_enable()
69073dfedd60 drm/vmwgfx: Stop updating plane->fb
90290f06a0cd drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
cf25abb66c8d drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
8c083114e1a4 drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
b94876325cd5 drm/arc: Stop consulting plane->fb

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8605/issues.html
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Re: [Intel-gfx] [PATCH 1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Ville Syrjälä

On Thu, Apr 05, 2018 at 10:08:57PM +0200, Daniel Vetter wrote:
> On Thu, Apr 05, 2018 at 10:50:29PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > We want to stop using plane->fb with atomic driver, so stop looking at
> > it.
> > 
> > I have no idea what this code is trying to achieve. There is no
> > corresponding check in the enable path. Also since
> > arc_pgu_set_pxl_fmt() will anyway oops if there is no fb I'm going
> > to assuming that I can just remove the check entirely. There seems
> > to be a general shortage of .atomic_check() in this driver...
> 
> I think arcpgu is the perfect example of a small driver that _really_
> wants to use drm_simple_display_pipe_helper. Which would address the
> outright lack of any and all atomic_check code (beyond basic mode
> validation through mode_valid).
> 
> I also just noticed that it still has a bunch of the legacy hooks set,
> e.g. mode_set, mode_set_base are all no longer used in atomic.
> 
> I think the code won't be able to oops, since if there's no fb, we don't
> enable the plane (and it happily allows that), so should be all
> non-oopsing. Even with this check here removed.

arc_pgu_set_pxl_fmt() gets called from the .mode_set_nofb() hook
which I assume doesn't care about planes at all. So to me it looks like
it'll definitely oops.

> 
> Ofc the hw might get pissed at us in this case, but I can't tell that.
> Like I said, conversion to drm_simple_display_pipe_helper is probably the
> way to go.
> 
> Anyway, this patch here looks good, if you adjust the commit message to
> explain why it can't oops:
> 
> Reviewed-by: Daniel Vetter 
> 
> > 
> > Cc: Alexey Brodkin 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/arc/arcpgu_crtc.c | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c 
> > b/drivers/gpu/drm/arc/arcpgu_crtc.c
> > index 16903dc7fe0d..c3349b8fb58b 100644
> > --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> > +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> > @@ -136,9 +136,6 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc 
> > *crtc,
> >  {
> > struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> >  
> > -   if (!crtc->primary->fb)
> > -   return;
> > -
> > clk_disable_unprepare(arcpgu->clk);
> > arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
> >   arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
> > -- 
> > 2.16.1
> > 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 3/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()

2018-04-05 Thread Thomas Hellstrom


On 04/05/2018 09:50 PM, Ville Syrjala wrote:

From: Ville Syrjälä 

Instead of plane->fb (which we're going to deprecate for atomic drivers)
we need to look at plane->state->fb. The maze of code leading to
vmw_kms_helper_dirty() wasn't particularly clear, but my analysis
concluded that the calls originating from vmw_*_primary_plane_atomic_update()
all pass in the crtc which means we'll never end up in this branch
of the function. All other callers use drm_modeset_lock_all() somewhere
higher up, which means accessing plane->state is safe. We'll toss in
a lockdep assert to catch wrongdoers.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 15 ---
  1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index a2a796b4cc23..5a824125c231 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -2326,9 +2326,18 @@ int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
} else {
list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
head) {
-   if (crtc->primary->fb != &framebuffer->base)
-   continue;
-   units[num_units++] = vmw_crtc_to_du(crtc);
+   struct drm_plane *plane = crtc->primary;
+
+   /*
+* vmw_*_primary_plane_atomic_update() pass in the crtc,
+* and so don't end up here. All other callers use
+* drm_modeset_lock_all(), hence we can access the
+* plane state safely.
+*/
+   lockdep_assert_held(&plane->mutex);
+
I think we can remove the comment (it's a helper, so current users may 
not be future users),

but the lockdep assert should be OK.

+   if (plane->state->fb != &framebuffer->base)
+   units[num_units++] = vmw_crtc_to_du(crtc);


This doesn't seem to do what the original code did...


}
}
  


/Thomas


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Re: [Intel-gfx] [PATCH 2/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()

2018-04-05 Thread Deepak Singh Rawat


> 
> From: Ville Syrjälä 
> 
> Instead of looking at plane->fb let's look at the proper new
> plane state.
> 
> Not that the code makes a ton of sense. It's only going through the
> crtcs in the atomic state, so assuming not all of them are included
> we're not even calculating the total bandwidth here. Also we're
> not considering whether each crtc is actually enabled or not.
> 
> Cc: Thomas Hellstrom 
> Cc: Sinclair Yeh 
> Cc: VMware Graphics 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 10 +++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> index 6728c6247b4b..a2a796b4cc23 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> @@ -1536,9 +1536,13 @@ vmw_kms_atomic_check_modeset(struct
> drm_device *dev,
>   unsigned long requested_bb_mem = 0;
> 
>   if (dev_priv->active_display_unit ==
> vmw_du_screen_target) {
> - if (crtc->primary->fb) {
> - int cpp = crtc->primary->fb->pitches[0] /
> -   crtc->primary->fb->width;
> + struct drm_plane *plane = crtc->primary;
> + struct drm_plane_state *plane_state;
> +
> + plane_state =
> drm_atomic_get_new_plane_state(state, plane);
> +
> + if (plane_state && plane_state->fb) {
> + int cpp = plane_state->fb->format->cpp[0];

Hi Ville,

Thanks for the patch, recently I have done some refactoring of this code area
which is no yet sent to dri-devel. But the refactored code eliminated the need
to look the fb

https://cgit.freedesktop.org/mesa/vmwgfx/commit/?id=c54cdb6549b7d1c04ff61e639fc0e6de0dcc1ed6

There is still some future work to be done in this area. 

> 
>   requested_bb_mem += crtc->mode.hdisplay
> * cpp *
>   crtc->mode.vdisplay;
> --
> 2.16.1
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Re: [Intel-gfx] [PATCH 1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Daniel Vetter

On Thu, Apr 05, 2018 at 10:50:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> We want to stop using plane->fb with atomic driver, so stop looking at
> it.
> 
> I have no idea what this code is trying to achieve. There is no
> corresponding check in the enable path. Also since
> arc_pgu_set_pxl_fmt() will anyway oops if there is no fb I'm going
> to assuming that I can just remove the check entirely. There seems
> to be a general shortage of .atomic_check() in this driver...

I think arcpgu is the perfect example of a small driver that _really_
wants to use drm_simple_display_pipe_helper. Which would address the
outright lack of any and all atomic_check code (beyond basic mode
validation through mode_valid).

I also just noticed that it still has a bunch of the legacy hooks set,
e.g. mode_set, mode_set_base are all no longer used in atomic.

I think the code won't be able to oops, since if there's no fb, we don't
enable the plane (and it happily allows that), so should be all
non-oopsing. Even with this check here removed.

Ofc the hw might get pissed at us in this case, but I can't tell that.
Like I said, conversion to drm_simple_display_pipe_helper is probably the
way to go.

Anyway, this patch here looks good, if you adjust the commit message to
explain why it can't oops:

Reviewed-by: Daniel Vetter 

> 
> Cc: Alexey Brodkin 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/arc/arcpgu_crtc.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c 
> b/drivers/gpu/drm/arc/arcpgu_crtc.c
> index 16903dc7fe0d..c3349b8fb58b 100644
> --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> @@ -136,9 +136,6 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc 
> *crtc,
>  {
>   struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
>  
> - if (!crtc->primary->fb)
> - return;
> -
>   clk_disable_unprepare(arcpgu->clk);
>   arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
> arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
> -- 
> 2.16.1
> 

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/7] drm/arc: Stop consulting plane->fb
URL   : https://patchwork.freedesktop.org/series/41230/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b94876325cd5 drm/arc: Stop consulting plane->fb
8c083114e1a4 drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
cf25abb66c8d drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#12: 
concluded that the calls originating from vmw_*_primary_plane_atomic_update()

total: 0 errors, 1 warnings, 0 checks, 21 lines checked
90290f06a0cd drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
69073dfedd60 drm/vmwgfx: Stop updating plane->fb
192117f681f1 drm/vmwgfx: Stop using plane->fb in atomic_enable()
ac7ba740a34d drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc

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Re: [Intel-gfx] [PATCH v2 05/13] drm/i915: Stop updating plane->fb/crtc

2018-04-05 Thread Daniel Vetter

On Thu, Apr 5, 2018 at 7:02 PM, Ville Syrjala
 wrote:
> From: Ville Syrjälä 
>
> We want to get rid of plane->fb/crtc on atomic drivers. Stop setting
> them.
>
> v2: Fix up the comment in intel_crtc_active() and
> nuke the rest of the stale comments (Daniel)
>
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> Reviewed-by: Maarten Lankhorst  #v1
> Reviewed-by: Daniel Vetter 

lgtm, ack on adding my r-b.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 12 
>  drivers/gpu/drm/i915/intel_display.c  |  7 +++
>  2 files changed, 3 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7481ce85746b..eb0579fb5e54 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -120,12 +120,6 @@ int intel_plane_atomic_check_with_state(const struct 
> intel_crtc_state *old_crtc_
> &crtc_state->base.adjusted_mode;
> int ret;
>
> -   /*
> -* Both crtc and plane->crtc could be NULL if we're updating a
> -* property while the plane is disabled.  We don't actually have
> -* anything driver-specific we need to test in that case, so
> -* just return success.
> -*/
> if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> return 0;
>
> @@ -204,12 +198,6 @@ static int intel_plane_atomic_check(struct drm_plane 
> *plane,
> const struct drm_crtc_state *old_crtc_state;
> struct drm_crtc_state *new_crtc_state;
>
> -   /*
> -* Both crtc and plane->crtc could be NULL if we're updating a
> -* property while the plane is disabled.  We don't actually have
> -* anything driver-specific we need to test in that case, so
> -* just return success.
> -*/
> if (!crtc)
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 415fb8cf2cf4..469792fa098d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -979,7 +979,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
>  * We can ditch the adjusted_mode.crtc_clock check as soon
>  * as Haswell has gained clock readout/fastboot support.
>  *
> -* We can ditch the crtc->primary->fb check as soon as we can
> +* We can ditch the crtc->primary->state->fb check as soon as we can
>  * properly reconstruct framebuffers.
>  *
>  * FIXME: The intel_crtc->active here should be switched to
> @@ -2877,9 +2877,8 @@ intel_find_initial_plane_obj(struct intel_crtc 
> *intel_crtc,
> if (i915_gem_object_is_tiled(obj))
> dev_priv->preserve_bios_swizzle = true;
>
> -   drm_framebuffer_get(fb);
> -   primary->fb = primary->state->fb = fb;
> -   primary->crtc = primary->state->crtc = &intel_crtc->base;
> +   plane_state->fb = fb;
> +   plane_state->crtc = &intel_crtc->base;
>
> intel_set_plane_visible(to_intel_crtc_state(crtc_state),
> to_intel_plane_state(plane_state),
> --
> 2.16.1
>



-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl: Add reset control register changes

2018-04-05 Thread Oscar Mateo




On 4/5/2018 7:00 AM, Mika Kuoppala wrote:

From: Michel Thierry 

The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.

v2: Use shift-left instead of BIT macro to match the file style (Paulo).
v3: Reuse gen8_reset_engines (Daniele).
v4: Do not call intel_uncore_forcewake_reset after reset, we may be
using the forcewake to read protected registers elsewhere and those
results may be clobbered by the concurrent dropping of forcewake.

bspec: 19212
Cc: Oscar Mateo 
Cc: Antonio Argenziano 
Cc: Paulo Zanoni 
Cc: Daniele Ceraolo Spurio 
Acked-by: Daniele Ceraolo Spurio 
Signed-off-by: Michel Thierry 
---
  drivers/gpu/drm/i915/i915_reg.h | 11 
  drivers/gpu/drm/i915/intel_uncore.c | 53 +++--
  2 files changed, 62 insertions(+), 2 deletions(-)


Knowing what I know about patches that are still in the pipeline (that 
justify why we don't reuse gen6_reset_engines), this is:


Reviewed-by: Oscar Mateo 


diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6554f4..b2a2d8fbbc68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -301,6 +301,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  #define  GEN6_GRDOM_VECS  (1 << 4)
  #define  GEN9_GRDOM_GUC   (1 << 5)
  #define  GEN8_GRDOM_MEDIA2(1 << 7)
+/* GEN11 changed all bit defs except for FULL & RENDER */
+#define  GEN11_GRDOM_FULL  GEN6_GRDOM_FULL
+#define  GEN11_GRDOM_RENDERGEN6_GRDOM_RENDER
+#define  GEN11_GRDOM_BLT   (1 << 2)
+#define  GEN11_GRDOM_GUC   (1 << 3)
+#define  GEN11_GRDOM_MEDIA (1 << 5)
+#define  GEN11_GRDOM_MEDIA2(1 << 6)
+#define  GEN11_GRDOM_MEDIA3(1 << 7)
+#define  GEN11_GRDOM_MEDIA4(1 << 8)
+#define  GEN11_GRDOM_VECS  (1 << 13)
+#define  GEN11_GRDOM_VECS2 (1 << 14)
  
  #define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base+0x228)

  #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index e7540bb9786c..d6e20f0f4c28 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1909,6 +1909,50 @@ static int gen6_reset_engines(struct drm_i915_private 
*dev_priv,
return gen6_hw_domain_reset(dev_priv, hw_mask);
  }
  
+/**

+ * gen11_reset_engines - reset individual engines
+ * @dev_priv: i915 device
+ * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full 
reset
+ *
+ * This function will reset the individual engines that are set in engine_mask.
+ * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
+ *
+ * Note: It is responsibility of the caller to handle the difference between
+ * asking full domain reset versus reset for all available individual engines.
+ *
+ * Returns 0 on success, nonzero on error.
+ */
+static int gen11_reset_engines(struct drm_i915_private *dev_priv,
+  unsigned engine_mask)
+{
+   struct intel_engine_cs *engine;
+   const u32 hw_engine_mask[I915_NUM_ENGINES] = {
+   [RCS] = GEN11_GRDOM_RENDER,
+   [BCS] = GEN11_GRDOM_BLT,
+   [VCS] = GEN11_GRDOM_MEDIA,
+   [VCS2] = GEN11_GRDOM_MEDIA2,
+   [VCS3] = GEN11_GRDOM_MEDIA3,
+   [VCS4] = GEN11_GRDOM_MEDIA4,
+   [VECS] = GEN11_GRDOM_VECS,
+   [VECS2] = GEN11_GRDOM_VECS2,
+   };
+   u32 hw_mask;
+
+   BUILD_BUG_ON(VECS2 + 1 != I915_NUM_ENGINES);
+
+   if (engine_mask == ALL_ENGINES) {
+   hw_mask = GEN11_GRDOM_FULL;
+   } else {
+   unsigned int tmp;
+
+   hw_mask = 0;
+   for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
+   hw_mask |= hw_engine_mask[engine->id];
+   }
+
+   return gen6_hw_domain_reset(dev_priv, hw_mask);
+}
+
  /**
   * __intel_wait_for_register_fw - wait until register matches expected state
   * @dev_priv: the i915 device
@@ -2057,7 +2101,10 @@ static int gen8_reset_engines(struct drm_i915_private 
*dev_priv,
if (gen8_reset_engine_start(engine))
goto not_ready;
  
-	return gen6_reset_engines(dev_priv, engine_mask);

+   if (INTEL_GEN(dev_priv) >= 11)
+   return gen11_reset_engines(dev_priv, engine_mask);
+   else
+   return gen6_reset_engines(dev_priv, engine_mask);
  
  not_ready:

for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
@@ -2160,12 +2207,14 @@ bool intel_has_reset_engine(struct drm_i915_private 
*dev_priv)
  
  int intel_reset_guc(struct drm_i915_private *dev_priv)

  {
+   u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_G

Re: [Intel-gfx] [PATCH 7/7] drm/i915/dp: fix compliance test adjustments

2018-04-05 Thread Manasi Navare

On Thu, Apr 05, 2018 at 05:39:05PM +0300, Jani Nikula wrote:
> Abstract compliance test adjustments to a single function. Also make the
> bpc adjustments affect the limits, actually forcing the bpc. Seems like
> directly changing the pipe_bpp in the past could not have been
> effective.
> 
> Signed-off-by: Jani Nikula 

Looks good to me w.r.t compliance test request parameters.

Reviewed-by: Manasi Navare 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 64 
> -
>  1 file changed, 38 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c98626b3af65..4ddb9dc61f46 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1666,14 +1666,6 @@ static int intel_dp_compute_bpp(struct intel_dp 
> *intel_dp,
>   if (bpc > 0)
>   bpp = min(bpp, 3*bpc);
>  
> - /* For DP Compliance we override the computed bpp for the pipe */
> - if (intel_dp->compliance.test_data.bpc != 0) {
> - pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
> - pipe_config->dither_force_disable = pipe_config->pipe_bpp == 
> 6*3;
> - DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
> -   pipe_config->pipe_bpp);
> - }
> -
>   if (intel_dp_is_edp(intel_dp)) {
>   /* Get bpp from vbt only for panels that dont have bpp in edid 
> */
>   if (intel_connector->base.display_info.bpc == 0 &&
> @@ -1704,6 +1696,42 @@ static bool intel_edp_compare_alt_mode(struct 
> drm_display_mode *m1,
>   return bres;
>  }
>  
> +/* Adjust link config limits based on compliance test requests. */
> +static void
> +intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
> +   struct intel_crtc_state *pipe_config,
> +   struct link_config_limits *limits)
> +{
> + /* For DP Compliance we override the computed bpp for the pipe */
> + if (intel_dp->compliance.test_data.bpc != 0) {
> + int bpp = 3 * intel_dp->compliance.test_data.bpc;
> +
> + limits->min_bpp = limits->max_bpp = bpp;
> + pipe_config->dither_force_disable = bpp == 6 * 3;
> +
> + DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
> + }
> +
> + /* Use values requested by Compliance Test Request */
> + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> + int index;
> +
> + /* Validate the compliance test data since max values
> +  * might have changed due to link train fallback.
> +  */
> + if (intel_dp_link_params_valid(intel_dp, 
> intel_dp->compliance.test_link_rate,
> +
> intel_dp->compliance.test_lane_count)) {
> + index = intel_dp_rate_index(intel_dp->common_rates,
> + intel_dp->num_common_rates,
> + 
> intel_dp->compliance.test_link_rate);
> + if (index >= 0)
> + limits->min_clock = limits->max_clock = index;
> + limits->min_lane_count = limits->max_lane_count =
> + intel_dp->compliance.test_lane_count;
> + }
> + }
> +}
> +
>  /* Optimize link config in order: max bpp, min clock, min lanes */
>  static bool
>  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> @@ -1764,24 +1792,6 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
>   limits.min_bpp = 6 * 3;
>   limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>  
> - /* Use values requested by Compliance Test Request */
> - if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> - int index;
> -
> - /* Validate the compliance test data since max values
> -  * might have changed due to link train fallback.
> -  */
> - if (intel_dp_link_params_valid(intel_dp, 
> intel_dp->compliance.test_link_rate,
> -
> intel_dp->compliance.test_lane_count)) {
> - index = intel_dp_rate_index(intel_dp->common_rates,
> - intel_dp->num_common_rates,
> - 
> intel_dp->compliance.test_link_rate);
> - if (index >= 0)
> - limits.min_clock = limits.max_clock = index;
> - limits.min_lane_count = limits.max_lane_count = 
> intel_dp->compliance.test_lane_count;
> - }
> - }
> -
>   if (intel_dp_is_edp(intel_dp)) {
>   /*
>* Use the maximum clock and number of lanes the eDP panel
> @@ -1794,6 +1804,8 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
>

Re: [Intel-gfx] [PATCH 6/7] drm/i915/dp: abstract link config selection

2018-04-05 Thread Manasi Navare

On Thu, Apr 05, 2018 at 05:39:04PM +0300, Jani Nikula wrote:
> For now, there's just the one link config selection, optimizing for slow
> and wide link. No functional changes.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 81 
> +
>  1 file changed, 50 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3c5fbdf42b9b..c98626b3af65 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1704,6 +1704,42 @@ static bool intel_edp_compare_alt_mode(struct 
> drm_display_mode *m1,
>   return bres;
>  }
>  
> +/* Optimize link config in order: max bpp, min clock, min lanes */
> +static bool
> +intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> +   struct intel_crtc_state *pipe_config,
> +   const struct link_config_limits *limits)
> +{
> + struct drm_display_mode *adjusted_mode = 
> &pipe_config->base.adjusted_mode;
> + int bpp, clock, lane_count;
> + int mode_rate, link_clock, link_avail;
> +
> + for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> + mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> +bpp);
> +
> + for (clock = limits->min_clock; clock <= limits->max_clock; 
> clock++) {
> + for (lane_count = limits->min_lane_count;
> +  lane_count <= limits->max_lane_count;
> +  lane_count <<= 1) {
> + link_clock = intel_dp->common_rates[clock];
> + link_avail = intel_dp_max_data_rate(link_clock,
> + lane_count);
> +
> + if (mode_rate <= link_avail) {
> + pipe_config->lane_count = lane_count;
> + pipe_config->pipe_bpp = bpp;
> + pipe_config->port_clock = link_clock;
> +
> + return true;
> + }
> + }
> + }
> + }
> +
> + return false;
> +}
> +
>  static bool
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
> @@ -1711,8 +1747,6 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
>   struct drm_display_mode *adjusted_mode = 
> &pipe_config->base.adjusted_mode;
>   struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>   struct link_config_limits limits;
> - int bpp, clock, lane_count;
> - int mode_rate, link_avail, link_clock;
>   int common_len;
>  
>   common_len = intel_dp_common_len_rate_limit(intel_dp,
> @@ -1766,37 +1800,22 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
> intel_dp->common_rates[limits.max_clock],
> limits.max_bpp, adjusted_mode->crtc_clock);
>  
> - for (bpp = limits.max_bpp; bpp >= limits.min_bpp; bpp -= 2 * 3) {
> - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> -bpp);
> -
> - for (clock = limits.min_clock; clock <= limits.max_clock; 
> clock++) {
> - for (lane_count = limits.min_lane_count;
> -  lane_count <= limits.max_lane_count;
> -  lane_count <<= 1) {
> -
> - link_clock = intel_dp->common_rates[clock];
> - link_avail = intel_dp_max_data_rate(link_clock,
> - lane_count);
> -
> - if (mode_rate <= link_avail) {
> - goto found;
> - }
> - }
> - }
> - }
> -
> - return false;
> -
> -found:
> - pipe_config->lane_count = lane_count;
> - pipe_config->pipe_bpp = bpp;
> - pipe_config->port_clock = intel_dp->common_rates[clock];
> + /*
> +  * Optimize for slow and wide. This is the place to add alternative
> +  * optimization policy.
> +  */
> + if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
> + return false;
>  
>   DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> -   pipe_config->lane_count, pipe_config->port_clock, bpp);
> - DRM_DEBUG_KMS("DP link bw required %i available %i\n",
> -   mode_rate, link_avail);
> +   pipe_config->lane_count, pipe_config->port_clock,
> +   pipe_config->pipe_bpp);
> +
> + DRM_DEBUG_KMS("DP link rate required %i available %i\n",
> +   i

[Intel-gfx] [PATCH 7/7] drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

plane->fb/old_fb/crtc should no longer be used by atomic
drivers. Stop messing about with them.

TODO: Squash with the core/helper patch?

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c | 24 
 1 file changed, 24 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 2582ffd36bb5..3c5935f3d49e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -439,8 +439,6 @@ static int vmw_fb_compute_depth(struct fb_var_screeninfo 
*var,
 static int vmwgfx_set_config_internal(struct drm_mode_set *set)
 {
struct drm_crtc *crtc = set->crtc;
-   struct drm_framebuffer *fb;
-   struct drm_crtc *tmp;
struct drm_modeset_acquire_ctx *ctx;
struct drm_device *dev = set->crtc->dev;
int ret;
@@ -448,29 +446,7 @@ static int vmwgfx_set_config_internal(struct drm_mode_set 
*set)
ctx = dev->mode_config.acquire_ctx;
 
 restart:
-   /*
-* NOTE: ->set_config can also disable other crtcs (if we steal all
-* connectors from it), hence we need to refcount the fbs across all
-* crtcs. Atomic modeset will have saner semantics ...
-*/
-   drm_for_each_crtc(tmp, dev)
-   tmp->primary->old_fb = tmp->primary->fb;
-
-   fb = set->fb;
-
ret = crtc->funcs->set_config(set, ctx);
-   if (ret == 0) {
-   crtc->primary->crtc = crtc;
-   crtc->primary->fb = fb;
-   }
-
-   drm_for_each_crtc(tmp, dev) {
-   if (tmp->primary->fb)
-   drm_framebuffer_get(tmp->primary->fb);
-   if (tmp->primary->old_fb)
-   drm_framebuffer_put(tmp->primary->old_fb);
-   tmp->primary->old_fb = NULL;
-   }
 
if (ret == -EDEADLK) {
dev->mode_config.acquire_ctx = NULL;
-- 
2.16.1

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[Intel-gfx] [PATCH 6/7] drm/vmwgfx: Stop using plane->fb in atomic_enable()

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

Instead of looking at the (soon to be deprecated) plane->fb we'll
examing plane->state->fb instead. We can do this because
vmw_du_crtc_atomic_check() prevents us from enabling a crtc
without the primary plane also being enabled.

Due to that same reason, I'm actually not sure what the checks here are
for NULL fb. If we can't enable the crtc without an enabled plane
we should always have an fb. But I'll leave that for someone else
to figure out.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 90445bc590cb..152e96cb1c01 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -414,6 +414,7 @@ static void vmw_stdu_crtc_helper_prepare(struct drm_crtc 
*crtc)
 static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
 {
+   struct drm_plane_state *plane_state = crtc->primary->state;
struct vmw_private *dev_priv;
struct vmw_screen_target_display_unit *stdu;
struct vmw_framebuffer *vfb;
@@ -422,7 +423,7 @@ static void vmw_stdu_crtc_atomic_enable(struct drm_crtc 
*crtc,
 
stdu = vmw_crtc_to_stdu(crtc);
dev_priv = vmw_priv(crtc->dev);
-   fb   = crtc->primary->fb;
+   fb   = plane_state->fb;
 
vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
 
-- 
2.16.1

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[Intel-gfx] [PATCH 5/7] drm/vmwgfx: Stop updating plane->fb

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

We want to get rid of plane->fb on atomic drivers. Stop setting it.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 2 --
 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 648f8127f65a..bbd3f19b1a0b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -525,8 +525,6 @@ vmw_sou_primary_plane_atomic_update(struct drm_plane *plane,
 */
if (ret != 0)
DRM_ERROR("Failed to update screen.\n");
-
-   crtc->primary->fb = plane->state->fb;
} else {
/*
 * When disabling a plane, CRTC and FB should always be NULL
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 67331f01ef32..90445bc590cb 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -1285,8 +1285,6 @@ vmw_stdu_primary_plane_atomic_update(struct drm_plane 
*plane,
 1, 1, NULL, crtc);
if (ret)
DRM_ERROR("Failed to update STDU.\n");
-
-   crtc->primary->fb = plane->state->fb;
} else {
crtc = old_state->crtc;
stdu = vmw_crtc_to_stdu(crtc);
-- 
2.16.1

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[Intel-gfx] [PATCH 4/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

The only caller of vmw_kms_update_implicit_fb() is the page_flip
hook which itself gets called with the plane mutex already held.
Hence we can look at plane->state safely. Toss in a lockdep assert
to make the situation more clear.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 5a824125c231..a93d290b0f35 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -2811,14 +2811,17 @@ void vmw_kms_update_implicit_fb(struct vmw_private 
*dev_priv,
struct drm_crtc *crtc)
 {
struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
+   struct drm_plane *plane = crtc->primary;
struct vmw_framebuffer *vfb;
 
+   lockdep_assert_held(&plane->mutex);
+
mutex_lock(&dev_priv->global_kms_state_mutex);
 
if (!du->is_implicit)
goto out_unlock;
 
-   vfb = vmw_framebuffer_to_vfb(crtc->primary->fb);
+   vfb = vmw_framebuffer_to_vfb(plane->state->fb);
WARN_ON_ONCE(dev_priv->num_implicit != 1 &&
 dev_priv->implicit_fb != vfb);
 
-- 
2.16.1

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[Intel-gfx] [PATCH 3/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

Instead of plane->fb (which we're going to deprecate for atomic drivers)
we need to look at plane->state->fb. The maze of code leading to
vmw_kms_helper_dirty() wasn't particularly clear, but my analysis
concluded that the calls originating from vmw_*_primary_plane_atomic_update()
all pass in the crtc which means we'll never end up in this branch
of the function. All other callers use drm_modeset_lock_all() somewhere
higher up, which means accessing plane->state is safe. We'll toss in
a lockdep assert to catch wrongdoers.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index a2a796b4cc23..5a824125c231 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -2326,9 +2326,18 @@ int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
} else {
list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
head) {
-   if (crtc->primary->fb != &framebuffer->base)
-   continue;
-   units[num_units++] = vmw_crtc_to_du(crtc);
+   struct drm_plane *plane = crtc->primary;
+
+   /*
+* vmw_*_primary_plane_atomic_update() pass in the crtc,
+* and so don't end up here. All other callers use
+* drm_modeset_lock_all(), hence we can access the
+* plane state safely.
+*/
+   lockdep_assert_held(&plane->mutex);
+
+   if (plane->state->fb != &framebuffer->base)
+   units[num_units++] = vmw_crtc_to_du(crtc);
}
}
 
-- 
2.16.1

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[Intel-gfx] [PATCH 2/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

Instead of looking at plane->fb let's look at the proper new
plane state.

Not that the code makes a ton of sense. It's only going through the
crtcs in the atomic state, so assuming not all of them are included
we're not even calculating the total bandwidth here. Also we're
not considering whether each crtc is actually enabled or not.

Cc: Thomas Hellstrom 
Cc: Sinclair Yeh 
Cc: VMware Graphics 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 6728c6247b4b..a2a796b4cc23 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1536,9 +1536,13 @@ vmw_kms_atomic_check_modeset(struct drm_device *dev,
unsigned long requested_bb_mem = 0;
 
if (dev_priv->active_display_unit == vmw_du_screen_target) {
-   if (crtc->primary->fb) {
-   int cpp = crtc->primary->fb->pitches[0] /
- crtc->primary->fb->width;
+   struct drm_plane *plane = crtc->primary;
+   struct drm_plane_state *plane_state;
+
+   plane_state = drm_atomic_get_new_plane_state(state, 
plane);
+
+   if (plane_state && plane_state->fb) {
+   int cpp = plane_state->fb->format->cpp[0];
 
requested_bb_mem += crtc->mode.hdisplay * cpp *
crtc->mode.vdisplay;
-- 
2.16.1

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[Intel-gfx] [PATCH 1/7] drm/arc: Stop consulting plane->fb

2018-04-05 Thread Ville Syrjala

From: Ville Syrjälä 

We want to stop using plane->fb with atomic driver, so stop looking at
it.

I have no idea what this code is trying to achieve. There is no
corresponding check in the enable path. Also since
arc_pgu_set_pxl_fmt() will anyway oops if there is no fb I'm going
to assuming that I can just remove the check entirely. There seems
to be a general shortage of .atomic_check() in this driver...

Cc: Alexey Brodkin 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/arc/arcpgu_crtc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c 
b/drivers/gpu/drm/arc/arcpgu_crtc.c
index 16903dc7fe0d..c3349b8fb58b 100644
--- a/drivers/gpu/drm/arc/arcpgu_crtc.c
+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
@@ -136,9 +136,6 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc 
*crtc,
 {
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 
-   if (!crtc->primary->fb)
-   return;
-
clk_disable_unprepare(arcpgu->clk);
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
  arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
-- 
2.16.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc
URL   : https://patchwork.freedesktop.org/series/41216/
State : success

== Summary ==

 Possible new issues:

Test kms_frontbuffer_tracking:
Subgroup fbcpsr-1p-primscrn-shrfb-msflip-blt:
fail   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1836 dwarn:1   dfail:0   fail:7   skip:836 
time:12644s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11509s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6932s
Blacklisted hosts:
shard-kbltotal:2622 pass:1918 dwarn:1   dfail:0   fail:7   skip:695 
time:8935s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8600/shards.html
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Re: [Intel-gfx] [PATCH v4 3/4] drm/i915/psr: Control PSR interrupts via debugfs

2018-04-05 Thread Souza, Jose

On Wed, 2018-04-04 at 18:37 -0700, Dhinakaran Pandiyan wrote:
> Interrupts other than the one for AUX errors are required only for
> debug,
> so unmask them via debugfs when the user requests debug.
> 
> User can make such a request with
> echo 1 > /dri/0/i915_edp_psr_debug
> 
> There are no locks to serialize PSR debug enabling from
> irq_postinstall() and debugfs for simplicity. As irq_postinstall() is
> called only during module initialization/resume and IGT subtests
> aren't expected to modify PSR debug at those times, we should be
> safe.
> 
> v2: Unroll loops (Ville)
> Avoid resetting error mask bits.
> 
> v3: Unmask interrupts in postinstall() if debug was still enabled.
> Avoid RMW (Ville)
> 
> v4: Avoid extra IMR write introduced in the previous version.(Jose)
> Style changes, renames (Jose).
> 
> Cc: Rodrigo Vivi 
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 

Reviewed-by: Jose Roberto de Souza 

> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 36 ++-
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_irq.c | 51 ---
> -
>  drivers/gpu/drm/i915/intel_drv.h|  2 ++
>  drivers/gpu/drm/i915/intel_psr.c| 58
> +
>  5 files changed, 108 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1dba2c451255..025410a08786 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2690,6 +2690,39 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
>   return 0;
>  }
>  
> +static int
> +i915_edp_psr_debug_set(void *data, u64 val)
> +{
> + struct drm_i915_private *dev_priv = data;
> +
> + if (!CAN_PSR(dev_priv))
> + return -ENODEV;
> +
> + DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
> +
> + intel_runtime_pm_get(dev_priv);
> + intel_psr_irq_control(dev_priv, !!val);
> + intel_runtime_pm_put(dev_priv);
> +
> + return 0;
> +}
> +
> +static int
> +i915_edp_psr_debug_get(void *data, u64 *val)
> +{
> + struct drm_i915_private *dev_priv = data;
> +
> + if (!CAN_PSR(dev_priv))
> + return -ENODEV;
> +
> + *val = READ_ONCE(dev_priv->psr.debug);
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> + i915_edp_psr_debug_get,
> i915_edp_psr_debug_set,
> + "%llu\n");
> +
>  static int i915_sink_crc(struct seq_file *m, void *data)
>  {
>   struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4812,7 +4845,8 @@ static const struct i915_debugfs_files {
>   {"i915_guc_log_relay", &i915_guc_log_relay_fops},
>   {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
>   {"i915_ipc_status", &i915_ipc_status_fops},
> - {"i915_drrs_ctl", &i915_drrs_ctl_fops}
> + {"i915_drrs_ctl", &i915_drrs_ctl_fops},
> + {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}
>  };
>  
>  int i915_debugfs_register(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b171bb96..b97ed0cd4ca9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -609,6 +609,7 @@ struct i915_psr {
>   bool has_hw_tracking;
>   bool psr2_enabled;
>   u8 sink_sync_latency;
> + bool debug;
>  
>   void (*enable_source)(struct intel_dp *,
> const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 8a894adf2ca1..91b66a52cae5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2391,40 +2391,6 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>   ironlake_rps_change_irq_handler(dev_priv);
>  }
>  
> -static void hsw_edp_psr_irq_handler(struct drm_i915_private
> *dev_priv)
> -{
> - u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> - u32 edp_psr_imr = I915_READ(EDP_PSR_IMR);
> - u32 mask = BIT(TRANSCODER_EDP);
> - enum transcoder cpu_transcoder;
> -
> - if (INTEL_GEN(dev_priv) >= 8)
> - mask |= BIT(TRANSCODER_A) |
> - BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C);
> -
> - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
> mask) {
> - if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder))
> - DRM_DEBUG_KMS("Transcoder %s PSR error\n",
> -   transcoder_name(cpu_transcoder
> ));
> -
> - if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder))
> {
> - DRM_DEBUG_KMS("Transcoder %s PSR prepare
> entry in 2 vblanks\n",
> -   transcoder_name(cpu_transcoder
> ));
> - edp_psr_imr |=
> EDP_PSR_PRE_ENTRY(cpu_tra

Re: [Intel-gfx] [PATCH 5/5] drm/i915/icl: Enable RC6 and RPS in Gen11

2018-04-05 Thread Michel Thierry


On 4/5/2018 7:00 AM, Mika Kuoppala wrote:

From: Oscar Mateo 

AFAICT, once the new interrupt is in place, the rest should behave the
same as Gen10.

v2: Update ring frequencies (Sagar)
v3: Rebase.

Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Cc: Paulo Zanoni 
Signed-off-by: Oscar Mateo 


If it's true that it's the same as Gen10,

Reviewed-by: Michel Thierry 


---
  drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
  drivers/gpu/drm/i915/intel_pm.c | 10 --
  2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1dba2c451255..785b710e4ee4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1215,20 +1215,20 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 rp_state_cap >> 16) & 0xff;
 max_freq *= (IS_GEN9_BC(dev_priv) ||
-IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));

 max_freq = (rp_state_cap & 0xff00) >> 8;
 max_freq *= (IS_GEN9_BC(dev_priv) ||
-IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));

 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 rp_state_cap >> 0) & 0xff;
 max_freq *= (IS_GEN9_BC(dev_priv) ||
-IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));
 seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1811,7 +1811,7 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)

 min_gpu_freq = rps->min_freq;
 max_gpu_freq = rps->max_freq;
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 /* Convert GT frequency to 50 HZ units */
 min_gpu_freq /= GEN9_FREQ_SCALER;
 max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -1827,7 +1827,7 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(dev_priv, (gpu_freq *
  (IS_GEN9_BC(dev_priv) ||
- IS_CANNONLAKE(dev_priv) ?
+ INTEL_GEN(dev_priv) >= 10 
?
   GEN9_FREQ_SCALER : 1))),
((ia_freq >> 0) & 0xff) * 100,
((ia_freq >> 8) & 0xff) * 100);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a018c9abc2b9..0d25e413ec0b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6572,7 +6572,7 @@ static void gen6_init_rps_frequencies(struct 
drm_i915_private *dev_priv)

 rps->efficient_freq = rps->rp1_freq;
 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
-   IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 u32 ddcc_status = 0;

 if (sandybridge_pcode_read(dev_priv,
@@ -6585,7 +6585,7 @@ static void gen6_init_rps_frequencies(struct 
drm_i915_private *dev_priv)
 rps->max_freq);
 }

-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 /* Store the frequency values in 16.66 MHZ units, which is
  * the natural hardware unit for SKL
  */
@@ -6923,7 +6923,7 @@ static void gen6_update_ring_freq(struct drm_i915_private 
*dev_priv)

 min_gpu_freq = rps->min_freq;
 max_gpu_freq = rps->max_freq;
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 /* Convert GT frequency to 50 HZ units */
 min_gpu_freq /= GEN9_FREQ_SCALER;
 max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -6938,7 +6938,7 @@ static void gen6_update_ring_freq(struct drm_i915_private 
*dev_priv)

Re: [Intel-gfx] [PATCH 4/7] drm/i915/dp: move eDP VBT bpp claming code to intel_dp_compute_bpp()

2018-04-05 Thread Manasi Navare

On Thu, Apr 05, 2018 at 05:39:02PM +0300, Jani Nikula wrote:
> Keep related things together. No functional changes.
> 
> Signed-off-by: Jani Nikula 
> ---

Definitely looks more organized.

Reviewed-by: Manasi Navare 

>  drivers/gpu/drm/i915/intel_dp.c | 24 +---
>  1 file changed, 13 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 19fe5eb8d32a..dd42e0422af6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1650,6 +1650,8 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, 
> int port_clock,
>  static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
>   struct intel_crtc_state *pipe_config)
>  {
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> + struct intel_connector *intel_connector = intel_dp->attached_connector;
>   int bpp, bpc;
>  
>   bpp = pipe_config->pipe_bpp;
> @@ -1665,6 +1667,17 @@ static int intel_dp_compute_bpp(struct intel_dp 
> *intel_dp,
>   DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
> pipe_config->pipe_bpp);
>   }
> +
> + if (intel_dp_is_edp(intel_dp)) {
> + /* Get bpp from vbt only for panels that dont have bpp in edid 
> */
> + if (intel_connector->base.display_info.bpc == 0 &&
> + (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) 
> {
> + DRM_DEBUG_KMS("clamping bpp for eDP panel to 
> BIOS-provided %i\n",
> +   dev_priv->vbt.edp.bpp);
> + bpp = dev_priv->vbt.edp.bpp;
> + }
> + }
> +
>   return bpp;
>  }
>  
> @@ -1689,10 +1702,8 @@ static bool
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
>  {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct drm_display_mode *adjusted_mode = 
> &pipe_config->base.adjusted_mode;
>   struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_connector *intel_connector = intel_dp->attached_connector;
>   int lane_count, clock;
>   int min_lane_count = 1;
>   int max_lane_count = intel_dp_max_lane_count(intel_dp);
> @@ -1735,15 +1746,6 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
>* bpc in between. */
>   bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>   if (intel_dp_is_edp(intel_dp)) {
> -
> - /* Get bpp from vbt only for panels that dont have bpp in edid 
> */
> - if (intel_connector->base.display_info.bpc == 0 &&
> - (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) 
> {
> - DRM_DEBUG_KMS("clamping bpp for eDP panel to 
> BIOS-provided %i\n",
> -   dev_priv->vbt.edp.bpp);
> - bpp = dev_priv->vbt.edp.bpp;
> - }
> -
>   /*
>* Use the maximum clock and number of lanes the eDP panel
>* advertizes being capable of. The panels are generally
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Avoid repeatedly harming the same innocent context

2018-04-05 Thread Chris Wilson

Quoting Chris Wilson (2018-03-30 14:18:01)
> We don't handle resetting the kernel context very well, or presumably any
> context executing its breadcrumb commands in the ring as opposed to the
> batchbuffer and flush. If we trigger a device reset twice in quick
> succession while the kernel context is executing, we may end up skipping
> the breadcrumb.  This is really only a problem for the selftest as
> normally there is a large interlude between resets (hangcheck), or we
> focus on resetting just one engine and so avoid repeatedly resetting
> innocents.
> 
> Something to try would be a preempt-to-idle to quiesce the engine before
> reset, so that innocent contexts would be spared the reset.
> 
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michał Winiarski 
> CC: Michel Thierry 

Anyone?

> ---
>  drivers/gpu/drm/i915/i915_drv.c  |  3 ++
>  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 48 
> ++--
>  2 files changed, 47 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d354627882e3..684060ed8db6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1886,6 +1886,8 @@ void i915_reset(struct drm_i915_private *i915)
> int ret;
> int i;
>  
> +   GEM_TRACE("flags=%lx\n", error->flags);
> +
> might_sleep();
> lockdep_assert_held(&i915->drm.struct_mutex);
> GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
> @@ -2016,6 +2018,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
> const char *msg)
> struct i915_request *active_request;
> int ret;
>  
> +   GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
> GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
>  
> active_request = i915_gem_reset_prepare_engine(engine);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
> b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 9e4e0ad62724..122a32e0a69d 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -979,6 +979,23 @@ static int igt_wait_reset(void *arg)
> return err;
>  }
>  
> +static int wait_for_others(struct drm_i915_private *i915,
> +   struct intel_engine_cs *exclude)
> +{
> +   struct intel_engine_cs *engine;
> +   enum intel_engine_id id;
> +
> +   for_each_engine(engine, i915, id) {
> +   if (engine == exclude)
> +   continue;
> +
> +   if (wait_for(intel_engine_is_idle(engine), 10))
> +   return -EIO;
> +   }
> +
> +   return 0;
> +}
> +
>  static int igt_reset_queue(void *arg)
>  {
> struct drm_i915_private *i915 = arg;
> @@ -1027,13 +1044,36 @@ static int igt_reset_queue(void *arg)
> i915_request_get(rq);
> __i915_request_add(rq, true);
>  
> +   /*
> +* XXX We don't handle resetting the kernel context
> +* very well. If we trigger a device reset twice in
> +* quick succession while the kernel context is
> +* executing, we may end up skipping the breadcrumb.
> +* This is really only a problem for the selftest as
> +* normally there is a large interlude between resets
> +* (hangcheck), or we focus on resetting just one
> +* engine and so avoid repeatedly resetting innocents.
> +*/
> +   err = wait_for_others(i915, engine);
> +   if (err) {
> +   pr_err("%s(%s): Failed to idle other inactive 
> engines after device reset\n",
> +  __func__, engine->name);
> +   i915_request_put(rq);
> +   i915_request_put(prev);
> +
> +   GEM_TRACE_DUMP();
> +   i915_gem_set_wedged(i915);
> +   goto fini;
> +   }
> +
> if (!wait_for_hang(&h, prev)) {
> struct drm_printer p = 
> drm_info_printer(i915->drm.dev);
>  
> -   pr_err("%s: Failed to start request %x, at 
> %x\n",
> -  __func__, prev->fence.seqno, 
> hws_seqno(&h, prev));
> -   intel_engine_dump(prev->engine, &p,
> - "%s\n", prev->engine->name);
> +   pr_err("%s(%s): Failed to start request %x, 
> at %x\n",
> +  __func__, engine->name,
> +  pre

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: set minimum CD clock to twice the BCLK. (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915: set minimum CD clock to twice the BCLK. (rev2)
URL   : https://patchwork.freedesktop.org/series/32657/
State : failure

== Summary ==

CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_audio.o
drivers/gpu/drm/i915/intel_audio.c: In function 
‘i915_audio_component_codec_wake_override’:
drivers/gpu/drm/i915/intel_audio.c:742:21: error: unused variable ‘min_cdclk’ 
[-Werror=unused-variable]
  int current_cdclk, min_cdclk;
 ^
cc1: all warnings being treated as errors
scripts/Makefile.build:324: recipe for target 
'drivers/gpu/drm/i915/intel_audio.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_audio.o] Error 1
scripts/Makefile.build:583: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:583: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:583: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [Intel-gfx] [PATCH 2/7] drm/i915/dp: move link_bw and rate_select debugging where used

2018-04-05 Thread Manasi Navare

On Thu, Apr 05, 2018 at 10:22:38AM -0700, Rodrigo Vivi wrote:
> On Thu, Apr 05, 2018 at 05:39:00PM +0300, Jani Nikula wrote:
> > The debug prints make more sense where the results are actually used,
> > and this cleans up extra clutter from the already overcrowded
> > intel_dp_compute_config().
> > 
> > Signed-off-by: Jani Nikula 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   | 9 ++---
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 5 +
> >  2 files changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 5f4b30faf6a2..81cf363e71af 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1706,7 +1706,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > int bpp, mode_rate;
> > int link_avail, link_clock;
> > int common_len;
> > -   uint8_t link_bw, rate_select;
> > bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
> >DP_DPCD_QUIRK_LIMITED_M_N);
> >  
> > @@ -1852,12 +1851,8 @@ intel_dp_compute_config(struct intel_encoder 
> > *encoder,
> > pipe_config->pipe_bpp = bpp;
> > pipe_config->port_clock = intel_dp->common_rates[clock];
> >  
> > -   intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
> > - &link_bw, &rate_select);
> 
> the commit message state more about the debug message itself,
> but by removing this call here it seems that you change
> the behavior of eDP. So I couldn't follow the changes you are
> actually aiming to do here.
>

Actually in dp_compute_config(), we just compute the optimum port_clock
selected from the common_rates array. We dont really use rate_select or link_bw 
here
in this function. These two parameters get used directly in the clock_recovery
where we either write rate_select or link_bw to the dpcd link config registers.
So by removing this call to intel_dp_compute_rate() from compute_config() makes 
sense
to me. And it does not alter the eDP compute config behaviour.

However I think to be clear, the above explanation needs to be included in th 
commit message.
With that included,

Reviewed-by: Manasi Navare 

Manasi 
> > -
> > -   DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d 
> > bpp %d\n",
> > - link_bw, rate_select, pipe_config->lane_count,
> > - pipe_config->port_clock, bpp);
> > +   DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> > + pipe_config->lane_count, pipe_config->port_clock, bpp);
> > DRM_DEBUG_KMS("DP link bw required %i available %i\n",
> >   mode_rate, link_avail);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index f59b59bb0a21..3fcaa98b9055 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -139,6 +139,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
> > *intel_dp)
> > intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> >   &link_bw, &rate_select);
> >  
> > +   if (link_bw)
> > +   DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
> > +   else
> > +   DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
> > +
> > /* Write the link configuration data */
> > link_config[0] = link_bw;
> > link_config[1] = intel_dp->lane_count;
> > -- 
> > 2.11.0
> > 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: Fix audio issue on BXT

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915/audio: Fix audio issue on BXT
URL   : https://patchwork.freedesktop.org/series/41227/
State : success

== Summary ==

Series 41227v1 drm/i915/audio: Fix audio issue on BXT
https://patchwork.freedesktop.org/api/1.0/series/41227/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:427s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:544s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:512s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:524s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:418s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:438s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:666s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:426s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:555s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:403s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:530s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
590e230abc83 drm/i915/audio: Fix audio issue on BXT

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8603/issues.html
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[Intel-gfx] [PATCH igt 2/2] igt/gem_eio: Drop DRM_MASTER so we can reacquire it in the subtests

2018-04-05 Thread Chris Wilson

As we reopen the fd for each subtest, and we need a DRM_MASTER, we need
to drop master on the original before we are allowed to claim DRM_MASTER
on the second.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 tests/gem_eio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 9599e73d..66d8c18a 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -41,6 +41,7 @@
 #include 
 
 #include "igt.h"
+#include "igt_device.h"
 #include "igt_sysfs.h"
 #include "sw_sync.h"
 
@@ -674,6 +675,7 @@ igt_main
 
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
+   igt_device_drop_master(fd);
 
igt_require(i915_reset_control(true));
igt_force_gpu_reset(fd);
-- 
2.16.3

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[Intel-gfx] [PATCH igt 1/2] lib: Acquire master for pollable spinbatch on gen4/5

2018-04-05 Thread Chris Wilson

gen4/5 require a DRM_MASTER to use MI_STORE_DW, make it so.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 lib/igt_dummyload.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 98ab7ac2..ba917ba5 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -31,6 +31,7 @@
 
 #include "igt_core.h"
 #include "drmtest.h"
+#include "igt_device.h"
 #include "igt_dummyload.h"
 #include "igt_gt.h"
 #include "intel_chipset.h"
@@ -144,8 +145,10 @@ emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t 
ctx, unsigned engine,
 
igt_assert(!dep);
 
-   if (gen == 4 || gen == 5)
+   if (gen == 4 || gen == 5) {
execbuf->flags |= I915_EXEC_SECURE;
+   igt_require(__igt_device_set_master(fd) == 0);
+   }
 
spin->poll_handle = gem_create(fd, 4096);
 
-- 
2.16.3

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Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Handle RPS interrupts correctly for Gen11

2018-04-05 Thread Michel Thierry


On 4/5/2018 7:00 AM, Mika Kuoppala wrote:

From: Oscar Mateo 

Using the new hierarchical interrupt infrastructure.

v2: Rebase
v3: Rebase
v4: use class/instance handler (Mika)

Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Cc: Paulo Zanoni 
Signed-off-by: Oscar Mateo 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_irq.c  | 73 ++--
  drivers/gpu/drm/i915/i915_reg.h  |  1 +
  drivers/gpu/drm/i915/intel_drv.h |  1 +
  drivers/gpu/drm/i915/intel_pm.c  |  6 ++--
  4 files changed, 67 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f984bf12a0b6..0b471775ce38 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -308,17 +308,29 @@ void gen5_disable_gt_irq(struct drm_i915_private 
*dev_priv, uint32_t mask)
  
  static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)

  {
+   WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
+
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
  }
  
  static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)

  {
-   return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+   if (INTEL_GEN(dev_priv) >= 11)
+   return GEN11_GPM_WGBOXPERF_INTR_MASK;
+   else if (INTEL_GEN(dev_priv) >= 8)
+   return GEN8_GT_IMR(2);
+   else
+   return GEN6_PMIMR;
  }
  
  static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)

  {
-   return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
+   if (INTEL_GEN(dev_priv) >= 11)
+   return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
+   else if (INTEL_GEN(dev_priv) >= 8)
+   return GEN8_GT_IER(2);
+   else
+   return GEN6_PMIER;
  }
  
  /**

@@ -400,6 +412,32 @@ static void gen6_disable_pm_irq(struct drm_i915_private 
*dev_priv, u32 disable_m
/* though a barrier is missing here, but don't really need a one */
  }
  
+static u32

+gen11_gt_engine_identity(struct drm_i915_private * const i915,
+const unsigned int bank, const unsigned int bit);
+
+void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
+{
+   u32 dw;
+
+   spin_lock_irq(&dev_priv->irq_lock);
+
+   /*
+* According to the BSpec, DW_IIR bits cannot be cleared without
+* first servicing the Selector & Shared IIR registers.
+*/
+   dw = I915_READ_FW(GEN11_GT_INTR_DW0);
+   while (dw & BIT(GEN11_GTPM)) {
+   gen11_gt_engine_identity(dev_priv, 0, GEN11_GTPM);
+   I915_WRITE_FW(GEN11_GT_INTR_DW0, BIT(GEN11_GTPM));
+   dw = I915_READ_FW(GEN11_GT_INTR_DW0);
+   }
+
+   dev_priv->gt_pm.rps.pm_iir = 0;
+
+   spin_unlock_irq(&dev_priv->irq_lock);
+}
+
  void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
  {
spin_lock_irq(&dev_priv->irq_lock);
@@ -415,12 +453,12 @@ void gen6_enable_rps_interrupts(struct drm_i915_private 
*dev_priv)
if (READ_ONCE(rps->interrupts_enabled))
return;
  
-	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))

-   return;
-
spin_lock_irq(&dev_priv->irq_lock);
WARN_ON_ONCE(rps->pm_iir);
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & 
dev_priv->pm_rps_events);
+   if (INTEL_GEN(dev_priv) >= 11)
+   WARN_ON_ONCE(I915_READ_FW(GEN11_GT_INTR_DW0) & BIT(GEN11_GTPM));
+   else
+   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & 
dev_priv->pm_rps_events);
rps->interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
  
@@ -434,9 +472,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)

if (!READ_ONCE(rps->interrupts_enabled))
return;
  
-	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))

-   return;
-
spin_lock_irq(&dev_priv->irq_lock);
rps->interrupts_enabled = false;
  
@@ -453,7 +488,10 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)

 * state of the worker can be discarded.
 */
cancel_work_sync(&rps->work);
-   gen6_reset_rps_interrupts(dev_priv);
+   if (INTEL_GEN(dev_priv) >= 11)
+   gen11_reset_rps_interrupts(dev_priv);
+   else
+   gen6_reset_rps_interrupts(dev_priv);
  }
  
  void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)

@@ -2768,6 +2806,9 @@ static void
  gen11_other_irq_handler(struct drm_i915_private * const i915,
const u8 instance, const u16 iir)
  {
+   if (instance == OTHER_GTPM_INSTANCE)
+   return gen6_rps_irq_handler(i915, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
  instance, iir);
  }
@@ -,6 +3374,9 @@ static void gen11_gt_irq_reset(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,

Re: [Intel-gfx] [PATCH 1/7] drm/i915/dp: remove stale comment about bw constants

2018-04-05 Thread Manasi Navare

On Thu, Apr 05, 2018 at 05:38:59PM +0300, Jani Nikula wrote:
> We haven't used the DP bw constants here for a while. No functional
> changes.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Manasi Navare 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 62f82c4298ac..5f4b30faf6a2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1701,7 +1701,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   int lane_count, clock;
>   int min_lane_count = 1;
>   int max_lane_count = intel_dp_max_lane_count(intel_dp);
> - /* Conveniently, the link BW constants become indices with a shift...*/
>   int min_clock = 0;
>   int max_clock;
>   int bpp, mode_rate;
> -- 
> 2.11.0
> 
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[Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

2018-04-05 Thread Abhay Kumar

In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure CD clock to be twice of  BCLK.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
Signed-off-by: Abhay Kumar 
---
 drivers/gpu/drm/i915/intel_audio.c | 34 +++---
 drivers/gpu/drm/i915/intel_cdclk.c | 21 +
 drivers/gpu/drm/i915/intel_drv.h   |  1 +
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 709d6ca68074..ca9859a69eb2 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -723,15 +723,38 @@ static void i915_audio_component_put_power(struct device 
*kdev)
intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
 }
 
+/* Get CDCLK in kHz  */
+static int i915_audio_component_get_cdclk_freq(struct device *kdev)
+{
+struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
+return -ENODEV;
+
+return dev_priv->cdclk.hw.cdclk;
+}
+
 static void i915_audio_component_codec_wake_override(struct device *kdev,
 bool enable)
 {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
+   int current_cdclk, min_cdclk;
 
if (!IS_GEN9_BC(dev_priv))
return;
 
+   current_cdclk = i915_audio_component_get_cdclk_freq(kdev);
+
+   /*
+* Before probing for HDA Codec we need to make sure
+* "The CD clock frequency must be at least twice
+ * the frequency of the Azalia BCLK."
+*/
+   if (INTEL_GEN(dev_priv) >= 9 && current_cdclk <= 192000) {
+   intel_cdclk_bump(dev_priv);
+   }
+
i915_audio_component_get_power(kdev);
 
/*
@@ -753,17 +776,6 @@ static void 
i915_audio_component_codec_wake_override(struct device *kdev,
i915_audio_component_put_power(kdev);
 }
 
-/* Get CDCLK in kHz  */
-static int i915_audio_component_get_cdclk_freq(struct device *kdev)
-{
-   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
-
-   if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
-   return -ENODEV;
-
-   return dev_priv->cdclk.hw.cdclk;
-}
-
 /*
  * get the intel_encoder according to the parameter port and pipe
  * intel_encoder is saved by the index of pipe
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index dc7db8a2caf8..9426e1b7badc 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1516,6 +1516,27 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 }
 
 /**
+ * intel_cdclk_bump - Increase cdclk to 2* BCLK
+ * @dev_priv: i915 device
+ *
+ * Increase CDCLK for GKL and CNL. This is done only
+ * during HDA codec probe.
+ */
+void intel_cdclk_bump(struct drm_i915_private *dev_priv)
+{
+   struct intel_cdclk_state cdclk_state;
+
+   cdclk_state = dev_priv->cdclk.hw;
+
+   if (IS_GEMINILAKE(dev_priv)) {
+   cdclk_state.cdclk = glk_calc_cdclk((2*96000));
+   cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
+   cdclk_state.voltage_level = 
bxt_calc_voltage_level(cdclk_state.cdclk);
+   bxt_set_cdclk(dev_priv, &cdclk_state);
+   }
+}
+
+/**
  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
  * @dev_priv: i915 device
  *
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1452fd2a58d..5192753df3dc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1417,6 +1417,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
+void intel_cdclk_bump(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void icl_init_cdclk(struct drm_i915_private *dev_priv);
 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915/audio: Fix audio issue on BXT

2018-04-05 Thread Gaurav K Singh

On Apollolake, with stress test warm reboot, audio card
was not getting enumerated after reboot. This was a
spurious issue happening on Apollolake. HW codec and
HD audio controller link was going out of sync for which
there was a fix in i915 driver but was not getting invoked
for BXT. Extending this fix to BXT as well.

Tested on apollolake chromebook by stress test warm reboot
with 2500 iterations.

Bspec: 21829

Signed-off-by: Gaurav K Singh 
Reviewed-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_audio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 709d6ca68074..656f6c931341 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -729,7 +729,7 @@ static void i915_audio_component_codec_wake_override(struct 
device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
 
-   if (!IS_GEN9_BC(dev_priv))
+   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
return;
 
i915_audio_component_get_power(kdev);
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: link config compute refactoring

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm/i915/dp: link config compute refactoring
URL   : https://patchwork.freedesktop.org/series/41215/
State : success

== Summary ==

 Possible new issues:

Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
fail   -> PASS   (shard-hsw)

 Known issues:

Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060 +1
Subgroup flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Test kms_flip_tiling:
Subgroup flip-to-yf-tiled:
pass   -> FAIL   (shard-apl) fdo#103822
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-render:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-apl) fdo#99912

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12686s
shard-hswtotal:2680 pass:1783 dwarn:2   dfail:0   fail:3   skip:891 
time:11538s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6944s
Blacklisted hosts:
shard-kbltotal:2622 pass:1860 dwarn:18  dfail:1   fail:20  skip:722 
time:8645s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8598/shards.html
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/icl: Deal with GT INT DW correctly

2018-04-05 Thread Michel Thierry


On 4/5/2018 7:00 AM, Mika Kuoppala wrote:

From: Oscar Mateo 

BSpec says:

"Second level interrupt events are stored in the GT INT DW. GT INT DW is
a double buffered structure. A snapshot of events is taken when SW reads
GT INT DW. From the time of read to the time of SW completely clearing
GT INT DW (to indicate end of service), all incoming interrupts are logged
in a secondary storage structure. this guarantees that the record of
interrupts SW is servicing will not change while under service".

We read GT INT DW in several places now:

- The IRQ handler (banks 0 and 1) where, hopefully, it is completely
   cleared (operation now covered with the irq lock).
- The 'reset' interrupts functions for RPS and GuC logs, where we clear
   the bit we are interested in and leave the others for the normal
   interrupt handler.
- The 'enable' interrupts functions for RPS and GuC logs, as a measure
   of precaution. Here we could relax a bit and don't check GT INT DW
   at all or, if we do, at least we should clear the offending bit
   (which is what this patch does).

Note that, if every bit is cleared on reading GT INT DW, the register
won't be locked. Also note that, according to the BSpec, GT INT DW
cannot be cleared without first servicing the Selector & Shared IIR
registers.

v2:
   - Remove some code duplication (Tvrtko)
   - Make sure GT_INTR_DW are protected by the irq spinlock, since it's a
 global resource (Tvrtko)

v3: Optimize the spinlock (Tvrtko)

v4: Rebase.
v5:
   - take spinlock on outer scope to please sparse (Mika)
   - use raw_reg accessors (Mika)

Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Signed-off-by: Oscar Mateo 
Reviewed-by: Tvrtko Ursulin  (v4)
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_irq.c | 112 +++-
  1 file changed, 75 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b471775ce38..653bab682d5e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -243,6 +243,41 @@ void i915_hotplug_interrupt_update(struct drm_i915_private 
*dev_priv,
spin_unlock_irq(&dev_priv->irq_lock);
  }
  
+static u32

+gen11_gt_engine_identity(struct drm_i915_private * const i915,
+const unsigned int bank, const unsigned int bit);
+
+static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
+   const unsigned int bank,
+   const unsigned int bit)
+{
+   void __iomem * const regs = i915->regs;
+   u32 dw;
+
+   lockdep_assert_held(&i915->irq_lock);
+
+   dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+   if (dw & BIT(bit)) {
+   /*
+* According to the BSpec, DW_IIR bits cannot be cleared without
+* first servicing the Selector & Shared IIR registers.
+*/
+   gen11_gt_engine_identity(i915, bank, bit);
+
+   /*
+* We locked GT INT DW by reading it. If we want to (try
+* to) recover from this succesfully, we need to clear
+* our bit, otherwise we are locking the register for
+* everybody.
+*/
+   raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
+
+   return true;
+   }
+
+   return false;
+}
+
  /**
   * ilk_update_display_irq - update DEIMR
   * @dev_priv: driver private
@@ -412,26 +447,12 @@ static void gen6_disable_pm_irq(struct drm_i915_private 
*dev_priv, u32 disable_m
/* though a barrier is missing here, but don't really need a one */
  }
  
-static u32

-gen11_gt_engine_identity(struct drm_i915_private * const i915,
-const unsigned int bank, const unsigned int bit);
-
  void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
  {
-   u32 dw;
-
spin_lock_irq(&dev_priv->irq_lock);
  
-	/*

-* According to the BSpec, DW_IIR bits cannot be cleared without
-* first servicing the Selector & Shared IIR registers.
-*/
-   dw = I915_READ_FW(GEN11_GT_INTR_DW0);
-   while (dw & BIT(GEN11_GTPM)) {
-   gen11_gt_engine_identity(dev_priv, 0, GEN11_GTPM);
-   I915_WRITE_FW(GEN11_GT_INTR_DW0, BIT(GEN11_GTPM));
-   dw = I915_READ_FW(GEN11_GT_INTR_DW0);
-   }
+   while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
+   ;
  
  	dev_priv->gt_pm.rps.pm_iir = 0;
  
@@ -455,10 +476,12 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
  
  	spin_lock_irq(&dev_priv->irq_lock);

WARN_ON_ONCE(rps->pm_iir);
+
if (INTEL_GEN(dev_priv) >= 11)
-   WARN_ON_ONCE(I915_READ_FW(GEN11_GT_INTR_DW0) & BIT(GEN11_GTPM));
+   WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
else
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_

Re: [Intel-gfx] [PATCH 04/13] drm/amdgpu/dc: Stop updating plane->fb

2018-04-05 Thread Harry Wentland



On 2018-04-05 12:41 PM, Daniel Vetter wrote:
> On Thu, Apr 05, 2018 at 06:13:51PM +0300, Ville Syrjala wrote:
>> From: Ville Syrjälä 
>>
>> We want to get rid of plane->fb on atomic drivers. Stop setting it.
>>
>> Cc: Alex Deucher 
>> Cc: "Christian König" 
>> Cc: "David (ChunMing) Zhou" 
>> Cc: Harry Wentland 
>> Cc: amd-...@lists.freedesktop.org
>> Signed-off-by: Ville Syrjälä 
>> Reviewed-by: Maarten Lankhorst 
>> Reviewed-by: Harry Wentland 
> 
> Under the assumption that all the hits outside of amdgpu/display/ are the
> legacy/non-DC/non-atomic modeset code (which looks to be the case):
> 

Yes, that's the case.

Harry

> Reviewed-by: Daniel Vetter 
> 
>> ---
>>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index e42a28e3adc5..91d048bb5574 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -3943,8 +3943,6 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
>>  
>>  /* Flip */
>>  spin_lock_irqsave(&crtc->dev->event_lock, flags);
>> -/* update crtc fb */
>> -crtc->primary->fb = fb;
>>  
>>  WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
>>  WARN_ON(!acrtc_state->stream);
>> -- 
>> 2.16.1
>>
>> ___
>> dri-devel mailing list
>> dri-de...@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: Use hw engine class, instance to find irq handler

2018-04-05 Thread Michel Thierry


On 4/5/2018 10:10 AM, Daniele Ceraolo Spurio wrote:



On 05/04/18 07:00, Mika Kuoppala wrote:

Interrupt identity register we already read from hardware
contains engine class and instance fields. Leverage
these fields to find correct engine to handle the interrupt.

v3: rebase on top of rps intr
 use correct class / instance limits (Michel)
v4: split engine/other handling

Suggested-by: Daniele Ceraolo Spurio 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Michel Thierry 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_irq.c | 102 
++--

  drivers/gpu/drm/i915/i915_reg.h |   4 +-
  2 files changed, 59 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c 
b/drivers/gpu/drm/i915/i915_irq.c

index 27aee25429b7..f984bf12a0b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2732,47 +2732,9 @@ static void __fini_wedge(struct wedge_me *w)
   (W)->i915;    \
   __fini_wedge((W)))
-static void
-gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
-    const unsigned int bank,
-    const unsigned int engine_n,
-    const u16 iir)
-{
-    struct intel_engine_cs ** const engine = i915->engine;
-
-    switch (bank) {
-    case 0:
-    switch (engine_n) {
-
-    case GEN11_RCS0:
-    return gen8_cs_irq_handler(engine[RCS], iir);
-
-    case GEN11_BCS:
-    return gen8_cs_irq_handler(engine[BCS], iir);
-    }
-    case 1:
-    switch (engine_n) {
-
-    case GEN11_VCS(0):
-    return gen8_cs_irq_handler(engine[_VCS(0)], iir);
-    case GEN11_VCS(1):
-    return gen8_cs_irq_handler(engine[_VCS(1)], iir);
-    case GEN11_VCS(2):
-    return gen8_cs_irq_handler(engine[_VCS(2)], iir);
-    case GEN11_VCS(3):
-    return gen8_cs_irq_handler(engine[_VCS(3)], iir);
-
-    case GEN11_VECS(0):
-    return gen8_cs_irq_handler(engine[_VECS(0)], iir);
-    case GEN11_VECS(1):
-    return gen8_cs_irq_handler(engine[_VECS(1)], iir);
-    }
-    }
-}
-
  static u32
-gen11_gt_engine_intr(struct drm_i915_private * const i915,
- const unsigned int bank, const unsigned int bit)
+gen11_gt_engine_identity(struct drm_i915_private * const i915,
+ const unsigned int bank, const unsigned int bit)
  {
  void __iomem * const regs = i915->regs;
  u32 timeout_ts;
@@ -2799,7 +2761,57 @@ gen11_gt_engine_intr(struct drm_i915_private * 
const i915,

  raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
    GEN11_INTR_DATA_VALID);
-    return ident & GEN11_INTR_ENGINE_MASK;
+    return ident;
+}
+
+static void
+gen11_other_irq_handler(struct drm_i915_private * const i915,
+    const u8 instance, const u16 iir)
+{
+    WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
+  instance, iir);
+}
+
+static void
+gen11_engine_irq_handler(struct drm_i915_private * const i915,
+ const u8 class, const u8 instance, const u16 iir)
+{
+    struct intel_engine_cs *engine;
+
+    if (instance <= MAX_ENGINE_INSTANCE)
+    engine = i915->engine_class[class][instance];
+    else
+    engine = NULL;
+


bikeshed: if we initialize the engine pointer to null above we can skip 
the else case here.



+    if (likely(engine))
+    return gen8_cs_irq_handler(engine, iir);
+
+    WARN_ONCE(1, "unhandled engine interrupt class=0x%x, 
instance=0x%x\n",

+  class, instance);
+}
+
+static void
+gen11_gt_identity_handler(struct drm_i915_private * const i915,
+  const u32 identity)
+{
+    const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
+    const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
+    const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
+
+    if (unlikely(!intr)) {
+    DRM_ERROR("class=0x%x, instance=0x%x, intr expected!\n",
+  class, instance);


This is not an error, it is possible to have an empty iir with double 
buffering. With the log removed:




I agree with Daniele, unlikely but possible.


Reviewed-by: Daniele Ceraolo Spurio 


So with that, also

Reviewed-by: Michel Thierry 


Thanks,
Daniele


+    return;
+    }
+
+    if (class <= COPY_ENGINE_CLASS)
+    return gen11_engine_irq_handler(i915, class, instance, intr);
+
+    if (class == OTHER_CLASS)
+    return gen11_other_irq_handler(i915, instance, intr);
+
+    WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, 
intr=0x%x\n",

+  class, instance, intr);
  }
  static void
@@ -2824,12 +2836,10 @@ gen11_gt_irq_handler(struct drm_i915_private * 
const i915,

  }
  for_each_set_bit(bit, &intr_dw, 32) {
-    const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
-
-    if (unlikely(!iir))
-    continue;
+    const u32 ident = gen11_gt_engine_identity(i9

Re: [Intel-gfx] [PATCH] drm/i915: Fix audio issue on BXT

2018-04-05 Thread Pandiyan, Dhinakaran




On Thu, 2018-04-05 at 22:12 +0530, Gaurav K Singh wrote:
> On Apollolake, with stress test warm reboot, audio card
> was not getting enumerated after reboot. This was a
> spurious issue happening on Apollolake. HW codec and
> HD audio controller link was going out of sync for which
> there was a fix in i915 driver but was not getting invoked
> for BXT. Extending this fix to BXT as well.
> 
> Tested on apollolake chromebook by stress test warm reboot
> with 2500 iterations.
> 
> Bspec: 21829
> 

R-B stands.

Btw, it would be easier to spot this patch and pick this up for merging
if you did not send this as a reply. I guess that's okay this time?
Also, a minor nitpick, "drm/i915/audio" would have been a more
appropriate prefix for the patch subject.



> Signed-off-by: Gaurav K Singh 
> Reviewed-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 709d6ca68074..656f6c931341 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -729,7 +729,7 @@ static void 
> i915_audio_component_codec_wake_override(struct device *kdev,
>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>   u32 tmp;
>  
> - if (!IS_GEN9_BC(dev_priv))
> + if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
>   return;
>  
>   i915_audio_component_get_power(kdev);
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Re: [Intel-gfx] [PATCH] drm/i915/dp: Send DPCD ON for MST before phy_up

2018-04-05 Thread Dhinakaran Pandiyan




On Thu, 2018-04-05 at 19:38 +0300, Ville Syrjälä wrote:
> On Wed, Apr 04, 2018 at 07:27:21PM -0400, Lyude Paul wrote:
> > As it turns out, the aux block being off was not the real problem here,
> > as transition from D3 to D0 is mandated by the DP spec to take a maximum
> > of 1ms, whereas we're allowed a 100ms timeframe to respond to ESI irqs.
> > The real problem here is a bit more subtle.
> > 
> > When doing a modeset where the problem of the sink timing out to our
> > sideband requests when transitioning from D3 to D0 occurs, the timeout
> > is from the aux block not coming on. However, nothing else times out
> > other than the initial phy_up message because the DPCD on call in
> > intel_ddi_enable_dp() ends up waking up the AUX block on the hub, not
> > the phy_up sideband message. 


This is the case only when intel_dp_sink_dpms(DRM_MODE_DPMS_OFF) was the
last action. With power_down_phy in post_disable() and power_up_phy in
pre_enable(), we weren't seeing this issue.




> This means that the real fix we need is to
> > use the DPMS on before sending a phy_up to ensure that the hub is ready
> > to accept sideband messages.
> > 
> > Signed-off-by: Lyude Paul 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Ville Syrjälä 
> > Cc: Laura Abbott 
> > Cc: sta...@vger.kernel.org
> > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> > hub.")
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c| 6 +-
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
> >  2 files changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index a6672a9abd85..9bd675f73f7b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2324,7 +2324,11 @@ static void intel_ddi_pre_enable_dp(struct 
> > intel_encoder *encoder,
> > intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> >  
> > intel_ddi_init_dp_buf_reg(encoder);
> > -   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > +   /* for MST, we do DPMS_ON outside of here so that DPMS_ON can happen
> > +* before drm_dp_send_power_updown_phy()
> > +*/
> > +   if (!intel_dp->is_mst)
> 
> Just 'is_mst' should do here.
> 
> And in general I'd like to see the enable and disable paths remain
> symmetric. Ie. also move out the dpms call in the disable path (or
> maybe move the phy_power_up/down in?).
> 
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index c3de0918ee13..eff9a4eae1f0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -223,6 +223,7 @@ static void intel_mst_pre_enable_dp(struct 
> > intel_encoder *encoder,
> >  
> > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> >  
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
> 
> This could use a comment to remind people that the order does matter.
> 
> > if (intel_dp->active_mst_links == 0)
> > intel_dig_port->base.pre_enable(&intel_dig_port->base,
> > -- 
> > 2.14.3
> 

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc (rev2)

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [01/13] drm/msm: Stop consulting plane->fb/crtc 
(rev2)
URL   : https://patchwork.freedesktop.org/series/41216/
State : success

== Summary ==

Series 41216v2 series starting with [01/13] drm/msm: Stop consulting 
plane->fb/crtc
https://patchwork.freedesktop.org/api/1.0/series/41216/revisions/2/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-cfl-s3) fdo#100368
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-cfl-s3total:285  pass:258  dwarn:0   dfail:0   fail:1   skip:26  
time:552s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:587s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:428s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:663s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:529s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:498s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:584s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  
time:518s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
e1b51ccc69f5 drm: Add local 'plane' variable for tmp->primary
33e599d07f38 drm: Stop updating plane->crtc/fb/old_fb on atomic drivers
57b2eeb3644c drm/omapdrm: Nuke omap_framebuffer_get_next_connector()
5a24279a8f74 drm/atmel-hlcdc: Stop using plane->fb
43630e6c913f drm/vc4: Stop updating plane->fb/crtc
714d9d1b9cb6 drm/virtio: Stop updating plane->crtc
f428f0ac9482 drm/msm: Stop updating plane->fb/crtc
c331a37b19af drm/exynos: Stop updating plane->crtc
67df61edf771 drm/i915: Stop updating plane->fb/crtc
11ba0fc12f00 drm/amdgpu/dc: Stop updating plane->fb
0679b27b65bc drm/atmel-hlcdc: Stop consulting plane->crtc
5c7efe59d8a0 drm/sti: Stop consulting plane->crtc
8862903b5411 drm/msm: Stop consulting plane->fb/crtc

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8602/issues.html
___
Intel-gfx

Re: [Intel-gfx] [PATCH] i915/dp_mst: Keep AUX block running when disabling DPMS

2018-04-05 Thread Sasha Levin

Hi.

[This is an automated email]

This commit has been processed because it contains a "Fixes:" tag.
fixing commit: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable 
MST hub.").

The bot has also determined it's probably a bug fixing patch. (score: 98.3082)

The bot has tested the following trees: v4.15.15, v4.14.32, v4.9.92, v4.4.126, 

v4.15.15: Failed to apply! Possible dependencies:
Unable to calculate.

v4.14.32: Failed to apply! Possible dependencies:
Unable to calculate.

v4.9.92: Failed to apply! Possible dependencies:
Unable to calculate.

v4.4.126: Failed to apply! Possible dependencies:
Unable to calculate.


--
Thanks.
Sasha
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/icl: Add reset control register changes

2018-04-05 Thread Patchwork

== Series Details ==

Series: series starting with [1/5] drm/i915/icl: Add reset control register 
changes
URL   : https://patchwork.freedesktop.org/series/41214/
State : success

== Summary ==

 Possible new issues:

Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
fail   -> PASS   (shard-hsw)

 Known issues:

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-render:
fail   -> PASS   (shard-snb) fdo#103167

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12730s
shard-hswtotal:2680 pass:1786 dwarn:1   dfail:0   fail:1   skip:891 
time:11513s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6931s
Blacklisted hosts:
shard-kbltotal:2622 pass:1887 dwarn:32  dfail:0   fail:7   skip:695 
time:8761s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8597/shards.html
___
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Re: [Intel-gfx] [PATCH 2/7] drm/i915/dp: move link_bw and rate_select debugging where used

2018-04-05 Thread Rodrigo Vivi

On Thu, Apr 05, 2018 at 05:39:00PM +0300, Jani Nikula wrote:
> The debug prints make more sense where the results are actually used,
> and this cleans up extra clutter from the already overcrowded
> intel_dp_compute_config().
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 9 ++---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 5 +
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5f4b30faf6a2..81cf363e71af 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1706,7 +1706,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   int bpp, mode_rate;
>   int link_avail, link_clock;
>   int common_len;
> - uint8_t link_bw, rate_select;
>   bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
>  DP_DPCD_QUIRK_LIMITED_M_N);
>  
> @@ -1852,12 +1851,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   pipe_config->pipe_bpp = bpp;
>   pipe_config->port_clock = intel_dp->common_rates[clock];
>  
> - intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
> -   &link_bw, &rate_select);

the commit message state more about the debug message itself,
but by removing this call here it seems that you change
the behavior of eDP. So I couldn't follow the changes you are
actually aiming to do here.

> -
> - DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d 
> bpp %d\n",
> -   link_bw, rate_select, pipe_config->lane_count,
> -   pipe_config->port_clock, bpp);
> + DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> +   pipe_config->lane_count, pipe_config->port_clock, bpp);
>   DRM_DEBUG_KMS("DP link bw required %i available %i\n",
> mode_rate, link_avail);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index f59b59bb0a21..3fcaa98b9055 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -139,6 +139,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
> *intel_dp)
>   intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> &link_bw, &rate_select);
>  
> + if (link_bw)
> + DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
> + else
> + DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
> +
>   /* Write the link configuration data */
>   link_config[0] = link_bw;
>   link_config[1] = intel_dp->lane_count;
> -- 
> 2.11.0
> 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: i915: Fix audio issue on BXT (rev4)

2018-04-05 Thread Patchwork

== Series Details ==

Series: drm: i915: Fix audio issue on BXT (rev4)
URL   : https://patchwork.freedesktop.org/series/35955/
State : failure

== Summary ==

Series 35955v4 drm: i915: Fix audio issue on BXT
https://patchwork.freedesktop.org/api/1.0/series/35955/revisions/4/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass   -> INCOMPLETE (fi-cnl-y3)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:437s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:386s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:521s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:523s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:229  pass:204  dwarn:0   dfail:0   fail:0   skip:24 
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:662s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:576s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cnl-psr   total:285  pass:255  dwarn:3   dfail:0   fail:1   skip:26  
time:513s

fcaf73c13c14d6bfd64c4f37089bf5437fb32221 drm-tip: 2018y-04m-05d-15h-53m-18s UTC 
integration manifest
2df45b21af1b drm/i915: Fix audio issue on BXT

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8601/issues.html
___
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/dp: remove stale comment about bw constants

2018-04-05 Thread Rodrigo Vivi

On Thu, Apr 05, 2018 at 05:38:59PM +0300, Jani Nikula wrote:
> We haven't used the DP bw constants here for a while. No functional
> changes.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 62f82c4298ac..5f4b30faf6a2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1701,7 +1701,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   int lane_count, clock;
>   int min_lane_count = 1;
>   int max_lane_count = intel_dp_max_lane_count(intel_dp);
> - /* Conveniently, the link BW constants become indices with a shift...*/
>   int min_clock = 0;
>   int max_clock;
>   int bpp, mode_rate;
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: Use hw engine class, instance to find irq handler

2018-04-05 Thread Daniele Ceraolo Spurio




On 05/04/18 07:00, Mika Kuoppala wrote:

Interrupt identity register we already read from hardware
contains engine class and instance fields. Leverage
these fields to find correct engine to handle the interrupt.

v3: rebase on top of rps intr
 use correct class / instance limits (Michel)
v4: split engine/other handling

Suggested-by: Daniele Ceraolo Spurio 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Michel Thierry 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_irq.c | 102 ++--
  drivers/gpu/drm/i915/i915_reg.h |   4 +-
  2 files changed, 59 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27aee25429b7..f984bf12a0b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2732,47 +2732,9 @@ static void __fini_wedge(struct wedge_me *w)
 (W)->i915;  \
 __fini_wedge((W)))
  
-static void

-gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
-   const unsigned int bank,
-   const unsigned int engine_n,
-   const u16 iir)
-{
-   struct intel_engine_cs ** const engine = i915->engine;
-
-   switch (bank) {
-   case 0:
-   switch (engine_n) {
-
-   case GEN11_RCS0:
-   return gen8_cs_irq_handler(engine[RCS], iir);
-
-   case GEN11_BCS:
-   return gen8_cs_irq_handler(engine[BCS], iir);
-   }
-   case 1:
-   switch (engine_n) {
-
-   case GEN11_VCS(0):
-   return gen8_cs_irq_handler(engine[_VCS(0)], iir);
-   case GEN11_VCS(1):
-   return gen8_cs_irq_handler(engine[_VCS(1)], iir);
-   case GEN11_VCS(2):
-   return gen8_cs_irq_handler(engine[_VCS(2)], iir);
-   case GEN11_VCS(3):
-   return gen8_cs_irq_handler(engine[_VCS(3)], iir);
-
-   case GEN11_VECS(0):
-   return gen8_cs_irq_handler(engine[_VECS(0)], iir);
-   case GEN11_VECS(1):
-   return gen8_cs_irq_handler(engine[_VECS(1)], iir);
-   }
-   }
-}
-
  static u32
-gen11_gt_engine_intr(struct drm_i915_private * const i915,
-const unsigned int bank, const unsigned int bit)
+gen11_gt_engine_identity(struct drm_i915_private * const i915,
+const unsigned int bank, const unsigned int bit)
  {
void __iomem * const regs = i915->regs;
u32 timeout_ts;
@@ -2799,7 +2761,57 @@ gen11_gt_engine_intr(struct drm_i915_private * const 
i915,
raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
  GEN11_INTR_DATA_VALID);
  
-	return ident & GEN11_INTR_ENGINE_MASK;

+   return ident;
+}
+
+static void
+gen11_other_irq_handler(struct drm_i915_private * const i915,
+   const u8 instance, const u16 iir)
+{
+   WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
+ instance, iir);
+}
+
+static void
+gen11_engine_irq_handler(struct drm_i915_private * const i915,
+const u8 class, const u8 instance, const u16 iir)
+{
+   struct intel_engine_cs *engine;
+
+   if (instance <= MAX_ENGINE_INSTANCE)
+   engine = i915->engine_class[class][instance];
+   else
+   engine = NULL;
+


bikeshed: if we initialize the engine pointer to null above we can skip 
the else case here.



+   if (likely(engine))
+   return gen8_cs_irq_handler(engine, iir);
+
+   WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
+ class, instance);
+}
+
+static void
+gen11_gt_identity_handler(struct drm_i915_private * const i915,
+ const u32 identity)
+{
+   const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
+   const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
+   const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
+
+   if (unlikely(!intr)) {
+   DRM_ERROR("class=0x%x, instance=0x%x, intr expected!\n",
+ class, instance);


This is not an error, it is possible to have an empty iir with double 
buffering. With the log removed:


Reviewed-by: Daniele Ceraolo Spurio 

Thanks,
Daniele


+   return;
+   }
+
+   if (class <= COPY_ENGINE_CLASS)
+   return gen11_engine_irq_handler(i915, class, instance, intr);
+
+   if (class == OTHER_CLASS)
+   return gen11_other_irq_handler(i915, instance, intr);
+
+   WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
+ class, instance, intr);
  }
  
  static void

@@ -2824,12 +2836,10 @@ gen11_gt_irq_handler(str

1 2 3 >

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