Re: [Intel-gfx] [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.

[Lucas De Marchi]

On Tue, May 22, 2018 at 02:44:43PM +0300, Mika Kahola wrote:
> On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare 
> > 
> > PLLs are the source clocks for the DDIs so in order
> > to determine the ddi clock we need to check the PLL
> > configuration.
> > 
> > This gets a little tricky for ICL since there is
> > no register bit that maps directly to the link clock.
> > So this patch creates a separate function in intel_dpll_mgr.c
> > to obtain the write array PLL Params and compares the set
> > pll_params with the table to get the corresponding link
> > clock.
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Mika Kahola 
> > Cc: Paulo Zanoni 
> > Signed-off-by: Manasi Navare 
> > Signed-off-by: Lucas De Marchi 

Reviewed-by: Lucas De Marchi 

> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   |  3 ++
> >  drivers/gpu/drm/i915/intel_ddi.c  | 26 ++
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> > +++
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 ++
> >  4 files changed, 97 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7f27fe2e38c7..26903cffabf6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> >  #define  DPLL_CFGCR1_QDIV_RATIO_MASK   (0xff << 10)
> >  #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT  (10)
> >  #define  DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> > +#define  DPLL_CFGCR1_QDIV_MODE_SHIFT   (9)
> >  #define  DPLL_CFGCR1_QDIV_MODE(x)  ((x) << 9)
> >  #define  DPLL_CFGCR1_KDIV_MASK (7 << 6)
> > +#define  DPLL_CFGCR1_KDIV_SHIFT(6)
> >  #define  DPLL_CFGCR1_KDIV(x)   ((x) << 6)
> >  #define  DPLL_CFGCR1_KDIV_1(1 << 6)
> >  #define  DPLL_CFGCR1_KDIV_2(2 << 6)
> >  #define  DPLL_CFGCR1_KDIV_4(4 << 6)
> >  #define  DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> > +#define  DPLL_CFGCR1_PDIV_SHIFT(2)
> >  #define  DPLL_CFGCR1_PDIV(x)   ((x) << 2)
> >  #define  DPLL_CFGCR1_PDIV_2(1 << 2)
> >  #define  DPLL_CFGCR1_PDIV_3(2 << 2)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index d8ae82001f83..0d8bed8e2200 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> > intel_crtc_state *pipe_config)
> >     pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> >  }
> >  
> > +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> > +     struct intel_crtc_state *pipe_config)
> > +{
> > +   struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > +   enum port port = encoder->port;
> > +   int link_clock = 0;
> > +   uint32_t pll_id;
> > +
> > +   pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> > >shared_dpll);
> > +   if (port == PORT_A || port == PORT_B) {
> > +   if (encoder->type == INTEL_OUTPUT_HDMI)
> > +   link_clock = cnl_calc_wrpll_link(dev_priv,
> > pll_id);
> > +   else
> > +   link_clock =
> > icl_calc_dp_combo_pll_link(dev_priv,
> > +   pll_
> > id);
> > +   } else {
> > +   /* FIXME - Add for MG PLL */
> > +   WARN(1, "MG PLL clock_get code not implemented
> > yet\n");
> > +   }
> > +
> > +   pipe_config->port_clock = link_clock;
> > +   ddi_dotclock_get(pipe_config);
> > +}
> > +
> >  static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> >       struct intel_crtc_state *pipe_config)
> >  {
> > @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> > intel_encoder *encoder,
> >     bxt_ddi_clock_get(encoder, pipe_config);
> >     else if (IS_CANNONLAKE(dev_priv))
> >     cnl_ddi_clock_get(encoder, pipe_config);
> > +   else if (IS_ICELAKE(dev_priv))
> > +   icl_ddi_clock_get(encoder, pipe_config);
> >  }
> >  
> >  void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> > *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 383fbc15113d..3cc837f74ffb 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state *crtc_state,
> >     return true;
> >  }
> >  
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > +      uint32_t pll_id)
> > +{
> > +   uint32_t cfgcr0, cfgcr1;
> > +   

Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[Nagaraju, Vathsala]

On 5/23/2018 1:28 AM, Dhinakaran Pandiyan wrote:

On Tue, 2018-05-22 at 14:27 +0530, vathsala nagaraju wrote:

From: Vathsala Nagaraju 

Prints live state of psr1.Extending the existing
PSR2 live state function to cover psr1.

Tested on KBL with psr2 and psr1 panel.

v2: rebase
v3: DK
 Rename psr2_live_status to psr_source_status

Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 

Signed-off-by: Vathsala Nagaraju 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 66 +++--

  drivers/gpu/drm/i915/i915_reg.h |  1 +
  2 files changed, 43 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5251544..e4a2f15 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2596,25 +2596,42 @@ static int i915_guc_log_relay_release(struct
inode *inode, struct file *file)
    .release = i915_guc_log_relay_release,
  };
  
-static const char *psr2_live_status(u32 val)

-{
-   static const char * const live_status[] = {
-   "IDLE",
-   "CAPTURE",
-   "CAPTURE_FS",
-   "SLEEP",
-   "BUFON_FW",
-   "ML_UP",
-   "SU_STANDBY",
-   "FAST_SLEEP",
-   "DEEP_SLEEP",
-   "BUF_ON",
-   "TG_ON"
-   };
-
-   val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
EDP_PSR2_STATUS_STATE_SHIFT;
-   if (val < ARRAY_SIZE(live_status))
-   return live_status[val];
+static const char *psr_source_status(u32 val, bool is_psr2_enabled)

Please change this to psr_source_status(drm_i915_private *dev_priv)
to print in format , source psr status %x [%s] , where %x = complete psr 
source register value(0x6f940) , %s = psr_status_bits [31 :28/29].
if we want handle everything as part of psr_source_status() , then we 
need to return register value in some pointer.
if not then we read the  reg and then pass it to psr_source_status which 
returns live status string.

+{
+   if (is_psr2_enabled) {
+   static const char * const live_status[] = {
+   "IDLE",
+   "CAPTURE",
+   "CAPTURE_FS",
+   "SLEEP",
+   "BUFON_FW",
+   "ML_UP",
+   "SU_STANDBY",
+   "FAST_SLEEP",
+   "DEEP_SLEEP",
+   "BUF_ON",
+   "TG_ON"
+   };

With that, you can  
live_status = I915_READ(EDP_PSR2_STATUS);

+   val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
+   EDP_PSR2_STATUS_STATE_SHIFT;
+   if (val < ARRAY_SIZE(live_status))
+   return live_status[val];
+   } else {
+   static const char * const live_status[] = {
+   "IDLE",
+   "SRDONACK",
+   "SRDENT",
+   "BUFOFF",
+   "BUFON",
+   "AUXACK",
+   "SRDOFFACK",
+   "SRDENT_ON",
+   };

live_status = I915_READ(EDP_PSR_STATUS);

+   val = (val & EDP_PSR_STATUS_STATE_MASK) >>
+   EDP_PSR_STATUS_STATE_SHIFT;
+   if (val < ARRAY_SIZE(live_status))
+   return live_status[val];
+   }
  
  	return "unknown";

  }
@@ -2647,6 +2664,7 @@ static int i915_edp_psr_status(struct seq_file
*m, void *data)
    enum pipe pipe;
    bool enabled = false;
    bool sink_support;
+   u32 psr_status;
  
  	if (!HAS_PSR(dev_priv))

    return -ENODEV;
@@ -2714,12 +2732,12 @@ static int i915_edp_psr_status(struct
seq_file *m, void *data)
  
  		seq_printf(m, "Performance_Counter: %u\n", psrperf);

    }
-   if (dev_priv->psr.psr2_enabled) {
-   u32 psr2 = I915_READ(EDP_PSR2_STATUS);
  
-		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",

-      psr2, psr2_live_status(psr2));
-   }
+   psr_status = (dev_priv->psr.psr2_enabled) ?
I915_READ(EDP_PSR2_STATUS) :
+   I915_READ(EDP_PS
R_STATUS);

Please move this inside psr_source_status(), I don't see a point in
checking for psr2_enabled here and again in psr_source_status()




+   seq_printf(m, "SOURCE_PSR_STATUS: %x[%s]\n",

It's easier on the eyes if these strings are consistent, there is no
benefit in writing only this string differently.

Sink status is printed as "Sink PSR status: 0x%x [%s]\n". Please do the
same by writing this as "Source PSR status: 0x%x [%s]\n"
  

+    psr_status,
+    psr_source_status(psr_status, dev_priv-

psr.psr2_enabled));
  
  	if 

Re: [Intel-gfx] [PATCH v4 1/2] vfio/mdev: Check globally for duplicate devices

[Zhenyu Wang]

On 2018.05.22 09:53:37 -0600, Alex Williamson wrote:
> [Cc +GVT-g maintainers/lists]
> 
> On Tue, 22 May 2018 10:13:46 +0200
> Cornelia Huck  wrote:
> 
> > On Fri, 18 May 2018 13:10:25 -0600
> > Alex Williamson  wrote:
> > 
> > > When we create an mdev device, we check for duplicates against the
> > > parent device and return -EEXIST if found, but the mdev device
> > > namespace is global since we'll link all devices from the bus.  We do
> > > catch this later in sysfs_do_create_link_sd() to return -EEXIST, but
> > > with it comes a kernel warning and stack trace for trying to create
> > > duplicate sysfs links, which makes it an undesirable response.
> > > 
> > > Therefore we should really be looking for duplicates across all mdev
> > > parent devices, or as implemented here, against our mdev device list.
> > > Using mdev_list to prevent duplicates means that we can remove
> > > mdev_parent.lock, but in order not to serialize mdev device creation
> > > and removal globally, we add mdev_device.active which allows UUIDs to
> > > be reserved such that we can drop the mdev_list_lock before the mdev
> > > device is fully in place.
> > > 
> > > Two behavioral notes; first, mdev_parent.lock had the side-effect of
> > > serializing mdev create and remove ops per parent device.  This was
> > > an implementation detail, not an intentional guarantee provided to
> > > the mdev vendor drivers.  Vendor drivers can trivially provide this
> > > serialization internally if necessary.  Second, review comments note
> > > the new -EAGAIN behavior when the device, and in particular the remove
> > > attribute, becomes visible in sysfs.  If a remove is triggered prior
> > > to completion of mdev_device_create() the user will see a -EAGAIN
> > > error.  While the errno is different, receiving an error during this
> > > period is not, the previous implementation returned -ENODEV for the
> > > same condition.  Furthermore, the consistency to the user is improved
> > > in the case where mdev_device_remove_ops() returns error.  Previously
> > > concurrent calls to mdev_device_remove() could see the device
> > > disappear with -ENODEV and return in the case of error.  Now a user
> > > would see -EAGAIN while the device is in this transitory state.
> > > 
> > > Signed-off-by: Alex Williamson 
> > > ---
> > >  Documentation/vfio-mediated-device.txt |5 ++
> > >  drivers/vfio/mdev/mdev_core.c  |  102 
> > > +++-
> > >  drivers/vfio/mdev/mdev_private.h   |2 -
> > >  3 files changed, 42 insertions(+), 67 deletions(-)  
> > 
> > Reviewed-by: Cornelia Huck 
> > 
> > I think it is better to deal with any possible vendor driver
> > implications on top of this (I still believe that vfio-ccw is fine).
> 
> Thanks Cornelia.  So if vfio-ccw is fine, presumably NVIDIA is fine,
> then this leaves GVT-g to see if there's any fallout.  Zhenyu & Zhi,
> I've linked the series under discussion here below[1].  The question to
> you is the first of the two behavioral notes listed above, does GVT-g
> have any dependency on the mdev core providing serialization per mdev
> parent device for the create and remove callbacks within the
> mdev_parent_ops?  This was never an intended feature of the
> implementation and as noted it should be trivial for for an mdev vendor
> driver to provide equivalent course grained serialization if
> necessary.  Of course it would be better to implement that sooner
> rather than later if required.
> 
> I see that __intel_gvt_create_vgpu() makes use of gvt->lock, which
> would seem to already provide this level of per-parent locking. The
> remove path makes use of this same lock, so I think we're ok, but
> looking for an explicit ack so there are no surprises.  I'd like
> to queue this series for v4.18.  Thanks,
> 

yeah, we don't expect mdev core for parent serialization for create and
remove of mdev device. Series look good to me.

Acked-by: Zhenyu Wang 


> Alex
> 
> [1] https://lkml.org/lkml/2018/5/18/1035

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: vbt change for psr (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev10)
URL   : https://patchwork.freedesktop.org/series/41289/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4222 -> Patchwork_9090 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9090 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9090, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/10/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9090:

  === IGT changes ===

 Possible regressions 

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   PASS -> FAIL


== Known issues ==

  Here are the changes found in Patchwork_9090 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-skl-6770hq:  FAIL (fdo#103928, fdo#100368) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   DMESG-FAIL (fdo#106103, fdo#102614) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4222 -> Patchwork_9090

  CI_DRM_4222: e783c316409040dab016975896e718fc36cbd8e6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4492: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9090: 46c7737a0d9a5e7256fa23032816fe97c2059da0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4492: 53aa71861efe0095405673c98ff15f6dcf268901 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

46c7737a0d9a drm/i915/psr: vbt change for psr

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9090/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev10)
URL   : https://patchwork.freedesktop.org/series/41289/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
46c7737a0d9a drm/i915/psr: vbt change for psr
-:85: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#85: FILE: drivers/gpu/drm/i915/i915_reg.h:4091:
+#define   EDP_PSR2_TP2_TIME_500us  (0<<8)
  ^

-:86: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#86: FILE: drivers/gpu/drm/i915/i915_reg.h:4092:
+#define   EDP_PSR2_TP2_TIME_100us  (1<<8)
  ^

-:87: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:4093:
+#define   EDP_PSR2_TP2_TIME_2500us (2<<8)
  ^

-:88: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#88: FILE: drivers/gpu/drm/i915/i915_reg.h:4094:
+#define   EDP_PSR2_TP2_TIME_50us   (3<<8)
  ^

-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/intel_bios.c:704:
+   DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside 
range[0-3], defaulting to max value 2500us\n",
+   psr_table->tp1_wakeup_time);

-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/intel_bios.c:723:
+   DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is 
outside range[0-3], defaulting to max value 2500us\n",
+   psr_table->tp2_tp3_wakeup_time);

total: 0 errors, 0 warnings, 6 checks, 135 lines checked

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[Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[vathsala nagaraju]

From: Vathsala Nagaraju 

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
move the 165 version check to intel_bios.c
v3: Jani
Move the abstraction to intel_bios.
v4: Jani
Rename tp*_wakeup_time to have "us" suffix.
For values outside range[0-3],default to max 2500us.
Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
Handle option 2 in default condition.
Print oustide range value.
For negetive values default to 2500us.
v6: Jani
Handle default first and then fall through for case 2.
v7: Rodrigo
Apply this change for IS_GEN9_BC and vbt version > 209
v8: Puthik
Add new function vbt_psr_to_us.
v9: Jani
Change to v7 version as it's more readable.
DK
add comment /*fall through*/ after case2.

Cc: Rodrigo Vivi 
Cc: Puthikorn Voravootivat 
Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Cc: José Roberto de Souza 

Signed-off-by: Maulik V Vaghela 
Signed-off-by: Vathsala Nagaraju 

Reviewed-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++
 drivers/gpu/drm/i915/intel_bios.c | 48 +--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++
 4 files changed, 72 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..dcfa791 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
bool require_aux_wakeup;
int idle_frames;
enum psr_lines_to_wait lines_to_wait;
-   int tp1_wakeup_time;
-   int tp2_tp3_wakeup_time;
+   int tp1_wakeup_time_us;
+   int tp2_tp3_wakeup_time_us;
} psr;
 
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..513b4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE  (1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)   ((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500(0<<8)
-#define   EDP_PSR2_TP2_TIME_100(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500   (2<<8)
-#define   EDP_PSR2_TP2_TIME_50 (3<<8)
+#define   EDP_PSR2_TP2_TIME_500us  (0<<8)
+#define   EDP_PSR2_TP2_TIME_100us  (1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us (2<<8)
+#define   EDP_PSR2_TP2_TIME_50us   (3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK   (3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..417f656 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct 
drm_i915_private *dev_priv,
break;
}
 
-   dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-   dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+   /*
+* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+* Old decimal value is wake up time in multiples of 100 us.
+*/
+   if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+   switch (psr_table->tp1_wakeup_time) {
+   case 0:
+   dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+   break;
+   case 1:
+   dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+   break;
+   case 3:
+   dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+   break;
+   default:
+   DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside 
range[0-3], defaulting to max value 2500us\n",
+   psr_table->tp1_wakeup_time);
+   /* fallthrough */
+   

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: per context slice/subslice powergating (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev5)
URL   : https://patchwork.freedesktop.org/series/42285/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4221_full -> Patchwork_9089_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9089_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9089_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42285/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9089_full:

  === IGT changes ===

 Possible regressions 

igt@gem_ctx_param@invalid-param-get:
  shard-apl:  PASS -> FAIL +1
  shard-glk:  PASS -> FAIL
  shard-snb:  PASS -> FAIL
  shard-hsw:  PASS -> FAIL

igt@gem_ctx_param@invalid-param-set:
  shard-hsw:  PASS -> DMESG-FAIL
  shard-snb:  PASS -> DMESG-FAIL
  shard-glk:  PASS -> DMESG-FAIL
  shard-apl:  PASS -> DMESG-FAIL


 Warnings 

igt@pm_rc6_residency@rc6-accuracy:
  shard-snb:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9089_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_color@pipe-b-ctm-negative:
  shard-apl:  PASS -> DMESG-FAIL (fdo#103558, fdo#105602)

igt@kms_cursor_crc@cursor-256x256-suspend:
  shard-apl:  PASS -> FAIL (fdo#103375)

igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105707) +1


 Possible fixes 

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  FAIL (fdo#106509, fdo#105454) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip@wf_vblank-ts-check-interruptible:
  shard-hsw:  FAIL (fdo#103928) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509


== Participating hosts (9 -> 8) ==

  Missing(1): shard-kbl 


== Build changes ==

* Linux: CI_DRM_4221 -> Patchwork_9089

  CI_DRM_4221: d83aef98e4f2e35440222c69ef80a68daf1abb4e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9089: 92c303df87067fd2ee535cf162ca72ce478d6d55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9089/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Special case kernel_context switch request

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-22 13:49:24)
> From: Mika Kuoppala 
> 
> When checking if engine is idling on a kernel context,
> the last request emitted to it could have been the exact
> request to switch into kernel context.
> 
> Do not bail out early even if engine has requests,
> if the last request was for kernel context.
> 
> Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
> timelines")
> Cc: Chris Wilson 
> Signed-off-by: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index b69b18ef8120..3fe1212b0f7e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -595,7 +595,10 @@ static bool engine_has_idle_kernel_context(struct 
> intel_engine_cs *engine)
> lockdep_assert_held(>i915->drm.struct_mutex);
>  
> list_for_each_entry(ring, active_rings, active_link) {
> -   if (last_request_on_engine(ring->timeline, engine))
> +   struct i915_request *rq =
> +   last_request_on_engine(ring->timeline, engine);
> +
> +   if (rq && rq->gem_context != engine->i915->kernel_context)
> return false;

Ah, this isn't enough yet. The challenge is that we don't want to report
false when there is an active batch followed by the kernel context.

I think we can rely on the kernel request priority being the lowest
here...
-Chris
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Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 15:21 -0700, José Roberto de Souza wrote:
> Sink can be configured to calculate the CRC over the static frame and
> compare with the CRC calculated and transmited in the VSC SDP by
> source, if there is a mismatch sink will do a short pulse in HPD
> and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.
> 
> Also spec recommends to disable MAX_SLEEP as a trigger to exit PSR
> when
> CRC check is enabled to improve power savings.
> 
> Spec: 7723
> 
> v3:
> disabling PSR instead of exiting on error
> 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 29 -
>  2 files changed, 21 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb79272..1add22e664ea 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4020,6 +4020,7 @@ enum {
>  #define   EDP_PSR_SKIP_AUX_EXIT  (1<<12)
>  #define   EDP_PSR_TP1_TP2_SEL(0<<11)
>  #define   EDP_PSR_TP1_TP3_SEL(1<<11)
> +#define   EDP_PSR_CRC_ENABLE (1<<10) /* BDW+
> */
>  #define   EDP_PSR_TP2_TP3_TIME_500us (0<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_100us (1<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_2500us(2<<8)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index f72e3f91809f..2f29dcd6f69e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -363,6 +363,8 @@ static void hsw_psr_enable_sink(struct intel_dp
> *intel_dp)
>   dpcd_val |= DP_PSR_ENABLE_PSR2;
>   if (dev_priv->psr.link_standby)
>   dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>  
>   drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> @@ -418,6 +420,9 @@ static void hsw_activate_psr1(struct intel_dp
> *intel_dp)
>   else
>   val |= EDP_PSR_TP1_TP2_SEL;
>  
> + if (INTEL_GEN(dev_priv) >= 8)
> + val |= EDP_PSR_CRC_ENABLE;
> +
>   val |= I915_READ(EDP_PSR_CTL) &
> EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
>   I915_WRITE(EDP_PSR_CTL, val);
>  }
> @@ -635,11 +640,14 @@ static void hsw_psr_enable_source(struct
> intel_dp *intel_dp,
>    * preventing  other hw tracking issues now we can
> rely
>    * on frontbuffer tracking.
>    */
> - I915_WRITE(EDP_PSR_DEBUG,
> -    EDP_PSR_DEBUG_MASK_MEMUP |
> -    EDP_PSR_DEBUG_MASK_HPD |
> -    EDP_PSR_DEBUG_MASK_LPSP |
> -    EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
> + u32 val = EDP_PSR_DEBUG_MASK_MEMUP |
> +   EDP_PSR_DEBUG_MASK_HPD |
> +   EDP_PSR_DEBUG_MASK_LPSP |
> +   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> +
> + if (INTEL_GEN(dev_priv) >= 8)
> + val |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
Move Patch 7/7 ahead of this one to avoid removing this check again?

> + I915_WRITE(EDP_PSR_DEBUG, val);
>   }
>  }
>  
> @@ -1051,16 +1059,19 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
>   goto exit;
>   }
>  
> - if (val & DP_PSR_RFB_STORAGE_ERROR) {
> - DRM_DEBUG_KMS("PSR RFB storage error, exiting
> PSR\n");
> + if (val & (DP_PSR_RFB_STORAGE_ERROR |
> DP_PSR_LINK_CRC_ERROR)) {
> + if (val & DP_PSR_RFB_STORAGE_ERROR)
> + DRM_DEBUG_KMS("PSR RFB storage error,
> disabling PSR\n");
> + if (val & DP_PSR_LINK_CRC_ERROR)
> + DRM_DEBUG_KMS("PSR Link CRC error, disabling
> PSR\n");
>   psr_disable(intel_dp);
>   }
> - if (val & (DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> DP_PSR_LINK_CRC_ERROR))
> + if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
>   DRM_ERROR("PSR_ERROR_STATUS not handled %x\n", val);
>   /* clear status register */
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS,
> val);
>  
> - /* TODO: handle other PSR/PSR2 errors */
> + /* TODO: handle PSR2 errors */
>  exit:
>   mutex_unlock(>lock);
>  }
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Re: [Intel-gfx] [PATCH v3 4/7] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 15:21 -0700, José Roberto de Souza wrote:
> eDP spec states that sink device will do a short pulse in HPD
> line when there is a PSR/PSR2 error that needs to be handled by
> source, this is handling the first and most simples error:
> DP_PSR_SINK_INTERNAL_ERROR.
> 
> Here taking the safest approach and disabling PSR(at least until
> the next modeset), to avoid multiple rendering issues due to
> bad pannels.
> 
> v3:
> disabling PSR instead of exiting on error
> 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/intel_dp.c  |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 62 +-
> --
>  3 files changed, 52 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index b86da48fd38e..fa2851d4fb36 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4479,6 +4479,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>   if (intel_dp_needs_link_retrain(intel_dp))
>   return false;
>  
> + intel_psr_short_pulse(intel_dp);
> +
>   if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING)
> {
>   DRM_DEBUG_KMS("Link Training Compliance Test
> requested\n");
>   /* Send a Hotplug Uevent to userspace to start
> modeset */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 4508be628450..892da65358e9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1921,6 +1921,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>     struct intel_crtc_state *crtc_state);
>  void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug);
>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> psr_iir);
> +void intel_psr_short_pulse(struct intel_dp *intel_dp);
>  
>  /* intel_runtime_pm.c */
>  int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index d88799482875..60797c8f9f0e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -741,6 +741,23 @@ static void hsw_psr_disable(struct intel_dp
> *intel_dp)
>   psr_aux_io_power_put(intel_dp);
>  }
>  
> +static void psr_disable(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (!dev_priv->psr.enabled)
> + return;
> +
> + dev_priv->psr.disable_source(intel_dp);
> +
> + /* Disable PSR on Sink */
> + drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> + dev_priv->psr.enabled = NULL;
> + cancel_delayed_work_sync(_priv->psr.work);
> +}
> +
>  /**
>   * intel_psr_disable - Disable PSR
>   * @intel_dp: Intel DP
> @@ -762,20 +779,8 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
>   return;
>  
>   mutex_lock(_priv->psr.lock);
> - if (!dev_priv->psr.enabled) {
> - mutex_unlock(_priv->psr.lock);
> - return;
> - }
> -
> - dev_priv->psr.disable_source(intel_dp);
> -
> - /* Disable PSR on Sink */
> - drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> -
> - dev_priv->psr.enabled = NULL;
> + psr_disable(intel_dp);
>   mutex_unlock(_priv->psr.lock);
> -
> - cancel_delayed_work_sync(_priv->psr.work);
>  }
>  
>  static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
> @@ -1014,3 +1019,34 @@ void intel_psr_init(struct drm_i915_private
> *dev_priv)
>   dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
>  
>  }
> +
> +void intel_psr_short_pulse(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct i915_psr *psr = _priv->psr;
> + uint8_t val;
> +
> + if (!HAS_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> + return;
CAN_PSR(dev_priv) should take care of this.

> +
> + mutex_lock(>lock);
Do we really need to acquire the mutex here? How about
> +
> + if (psr->enabled != intel_dp)
not doing this check?

> + goto exit;
> +
> + if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, )
> != 1) {
> + DRM_ERROR("PSR_STATUS dpcd read failed\n");
> + goto exit;
> + }
> +
> + if ((val & DP_PSR_SINK_STATE_MASK) ==
> DP_PSR_SINK_INTERNAL_ERROR) {
> + DRM_DEBUG_KMS("PSR sink internal error, disabling
> PSR\n");
> + psr_disable(intel_dp);
And calling 

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper

[Benson Leung]

On Fri, May 04, 2018 at 03:17:59PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood 
> 
> As more differentation occurs between DP spec. Its useful to have these
> as macros in a drm_dp_helper.
> 
> v2: DPCD_REV_XX to DP_DPCD_REV_XX
> 
> Signed-off-by: Matt Atwood 

Tested-by: Benson Leung  

> ---
>  include/drm/drm_dp_helper.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 91c9bcd4196f..96dcef479ed6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -64,6 +64,11 @@
>  /* AUX CH addresses */
>  /* DPCD */
>  #define DP_DPCD_REV 0x000
> +# define DP_DPCD_REV_10 0x10
> +# define DP_DPCD_REV_11 0x11
> +# define DP_DPCD_REV_12 0x12
> +# define DP_DPCD_REV_13 0x13
> +# define DP_DPCD_REV_14 0x14
>  
>  #define DP_MAX_LINK_RATE0x001
>  
> -- 
> 2.17.0
> 

-- 
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
ble...@google.com
Chromium OS Project
ble...@chromium.org


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Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180517]
[cannot apply to v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180523-031938
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x012-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
from include/drm/drmP.h:73,
from drivers/gpu/drm/i915/intel_dp.c:36:
   drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu/drm/i915/intel_dp.c:5396:13: warning: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t {aka int}' 
>> [-Wformat=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
^
   include/drm/drm_print.h:239:10: note: in definition of macro 'DRM_ERROR'
 drm_err(fmt, ##__VA_ARGS__)
 ^~~

vim +5396 drivers/gpu/drm/i915/intel_dp.c

  5385  
  5386  static inline
  5387  int intel_dp_hdcp2_read_rx_status(struct intel_digital_port 
*intel_dig_port,
  5388uint8_t *rx_status)
  5389  {
  5390  ssize_t ret;
  5391  
  5392  ret = drm_dp_dpcd_read(_dig_port->dp.aux,
  5393 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, 
rx_status,
  5394 HDCP_2_2_DP_RXSTATUS_LEN);
  5395  if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
> 5396  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", 
> ret);
  5397  return ret >= 0 ? -EIO : ret;
  5398  }
  5399  
  5400  return 0;
  5401  }
  5402  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH v3 3/7] drm/i915/psr: Remove intel_crtc_state parameter from disable()

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 15:21 -0700, José Roberto de Souza wrote:
> It was only used in VLV/CHV so after the removal of the PSR support
> for those platforms it is not necessary any more.
Right, Reviewed-by: Dhinakaran Pandiyan 

> 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 3 +--
>  drivers/gpu/drm/i915/intel_psr.c | 5 ++---
>  2 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index c58c5dae4424..34e3449ea182 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -615,8 +615,7 @@ struct i915_psr {
>  
>   void (*enable_source)(struct intel_dp *,
>     const struct intel_crtc_state *);
> - void (*disable_source)(struct intel_dp *,
> -    const struct intel_crtc_state *);
> + void (*disable_source)(struct intel_dp *intel_dp);
>   void (*enable_sink)(struct intel_dp *);
>   void (*activate)(struct intel_dp *);
>   void (*setup_vsc)(struct intel_dp *, const struct
> intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 29443d2c35bb..d88799482875 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -698,8 +698,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>   mutex_unlock(_priv->psr.lock);
>  }
>  
> -static void hsw_psr_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state
> *old_crtc_state)
> +static void hsw_psr_disable(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
>   struct drm_device *dev = intel_dig_port->base.base.dev;
> @@ -768,7 +767,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>   return;
>   }
>  
> - dev_priv->psr.disable_source(intel_dp, old_crtc_state);
> + dev_priv->psr.disable_source(intel_dp);
>  
>   /* Disable PSR on Sink */
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
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Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180517]
[cannot apply to v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180523-031938
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x000-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
from include/drm/drmP.h:73,
from drivers/gpu//drm/i915/intel_dp.c:36:
   drivers/gpu//drm/i915/intel_dp.c: In function 
'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu//drm/i915/intel_dp.c:5396:13: error: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t {aka int}' 
>> [-Werror=format=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
^
   include/drm/drm_print.h:239:10: note: in definition of macro 'DRM_ERROR'
 drm_err(fmt, ##__VA_ARGS__)
 ^~~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_read
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_write
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 3 include/linux/log2.h:is_power_of_2
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
   Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_read
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_set
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_read
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_set
   Cyclomatic Complexity 1 include/asm-generic/atomic-long.h:atomic_long_read
   Cyclomatic Complexity 1 include/linux/lockdep.h:lock_is_held
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 include/linux/mutex.h:__mutex_owner
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/ktime.h:ktime_compare
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_after
   Cyclomatic Complexity 70 include/linux/ktime.h:ktime_divns
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_to_ms
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_ms_delta
   Cyclomatic Complexity 1 include/linux/timekeeping.h:ktime_get_boottime
   Cyclomatic Complexity 2 include/linux/workqueue.h:to_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:queue_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:schedule_delayed_work
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 3 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 1 
include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_max_lane_count
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_enhanced_frame_cap
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_is_branch
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_dpcd_readb
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_dpcd_writeb
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_has_quirk
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_equal
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_valid
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_utils.h:onoff
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_uncore.h:intel_wait_for_register
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/i915_drv.h:msecs_to_jiffies_timeout
   Cyclomatic Complexity 5 

Re: [Intel-gfx] [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2

[Dhinakaran Pandiyan]

On Tue, 2018-05-22 at 07:37 -0700, Tarun Vyas wrote:
> On Fri, May 11, 2018 at 12:51:45PM -0700, Dhinakaran Pandiyan wrote:
> > 
> > While touching the code around this, I noticed that absence of ALPM
> > capability does not stop us from enabling PSR2. But, the spec
> > unambiguously states that ALPM is required for PSR2 and so does
> > this
> > commit that introduced this code
> > 
> > drm/i915/psr: enable ALPM for psr2
> > 
> > As per edp1.4 spec , alpm is required for psr2 operation as
> > it's
> > used for all psr2  main link power down management and alpm
> > enable
> > bit must be set for psr2 operation.
> > 
> Since, the code introduced by "drm/i915/psr: enable ALPM for psr2"
> enables PSR2 even if ALPM isn't supported, can we add the "Fixes" tag
> here ?

I thought about it. I don't think PSR2 was enabled upstream by default,
so we should be good without Fixes. And I didn't investigate if the
original commit missed the ALPM check or if it was mangled later.

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Re: [Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Chris Wilson]

Quoting Lionel Landwerlin (2018-05-22 13:22:32)
> On 22/05/18 13:10, Chris Wilson wrote:
> > nospec quite reasonably asserts that it will never be used with an index
> > larger than unsigned long (that being the largest possibly index into an
> > C array). However, our ubi uses the convention of u64 for any large
> > integer, running afoul of the assertion on 32b. Reduce our index to an
> > unsigned long, checking for type overflow first.
> >
> >drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
> >include/linux/compiler.h:339:38: error: call to 
> > '__compiletime_assert_119' declared with attribute error: BUILD_BUG_ON 
> > failed: sizeof(_s) > sizeof(long)
> >
> > Reported-by: kbuild-...@01.org
> > Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer 
> > lookup")
> > Signed-off-by: Chris Wilson 
> > Cc: Lionel Landwerlin 
> > Cc: Joonas Lahtinen 
> > Cc: Tvrtko Ursulin 
> 
> Reviewed-by: Lionel Landwerlin 

And pushed. Thanks for the review, and sorry for the palaver.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[Dhinakaran Pandiyan]

On Tue, 2018-05-22 at 14:27 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
> 
> Tested on KBL with psr2 and psr1 panel.
> 
> v2: rebase
> v3: DK
> Rename psr2_live_status to psr_source_status
> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 66 +++--
> 
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 43 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5251544..e4a2f15 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2596,25 +2596,42 @@ static int i915_guc_log_relay_release(struct
> inode *inode, struct file *file)
>   .release = i915_guc_log_relay_release,
>  };
>  
> -static const char *psr2_live_status(u32 val)
> -{
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> -
> - val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> EDP_PSR2_STATUS_STATE_SHIFT;
> - if (val < ARRAY_SIZE(live_status))
> - return live_status[val];
> +static const char *psr_source_status(u32 val, bool is_psr2_enabled)
Please change this to psr_source_status(drm_i915_private *dev_priv)

> +{
> + if (is_psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
With that, you can  
live_status = I915_READ(EDP_PSR2_STATUS);
> + val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> + EDP_PSR2_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };

live_status = I915_READ(EDP_PSR_STATUS);
> + val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + }
>  
>   return "unknown";
>  }
> @@ -2647,6 +2664,7 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
>   enum pipe pipe;
>   bool enabled = false;
>   bool sink_support;
> + u32 psr_status;
>  
>   if (!HAS_PSR(dev_priv))
>   return -ENODEV;
> @@ -2714,12 +2732,12 @@ static int i915_edp_psr_status(struct
> seq_file *m, void *data)
>  
>   seq_printf(m, "Performance_Counter: %u\n", psrperf);
>   }
> - if (dev_priv->psr.psr2_enabled) {
> - u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
> - seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> -    psr2, psr2_live_status(psr2));
> - }
> + psr_status = (dev_priv->psr.psr2_enabled) ?
> I915_READ(EDP_PSR2_STATUS) :
> + I915_READ(EDP_PS
> R_STATUS);

Please move this inside psr_source_status(), I don't see a point in
checking for psr2_enabled here and again in psr_source_status()



> + seq_printf(m, "SOURCE_PSR_STATUS: %x[%s]\n",
It's easier on the eyes if these strings are consistent, there is no
benefit in writing only this string differently.

Sink status is printed as "Sink PSR status: 0x%x [%s]\n". Please do the
same by writing this as "Source PSR status: 0x%x [%s]\n"
 
> +  psr_status,
> +  psr_source_status(psr_status, dev_priv-
> >psr.psr2_enabled));
>  
>   if (dev_priv->psr.enabled) {
>   struct drm_dp_aux *aux = _priv->psr.enabled-
> >aux;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 513b4a4..3c42021 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4069,6 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: per context slice/subslice powergating (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev5)
URL   : https://patchwork.freedesktop.org/series/42285/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9089 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9089 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9089, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42285/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9089:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9089 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_flip@basic-flip-vs-dpms:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cfl-s3:  FAIL (fdo#103481) -> PASS


  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4221 -> Patchwork_9089

  CI_DRM_4221: d83aef98e4f2e35440222c69ef80a68daf1abb4e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9089: 92c303df87067fd2ee535cf162ca72ce478d6d55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9089/build_32bit.log

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_query.o
In file included from ./include/asm-generic/barrier.h:20:0,
 from ./arch/x86/include/asm/barrier.h:86,
 from ./include/linux/nospec.h:8,
 from drivers/gpu/drm/i915/i915_query.c:7:
drivers/gpu/drm/i915/i915_query.c: In function ‘i915_query_ioctl’:
./include/linux/compiler.h:339:38: error: call to ‘__compiletime_assert_119’ 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
./include/linux/compiler.h:319:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^~
./include/linux/compiler.h:339:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^~~
./include/linux/build_bug.h:45:37: note: in expansion of macro 
‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^~
./include/linux/build_bug.h:69:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^~~~
./include/linux/nospec.h:53:2: note: in expansion of macro ‘BUILD_BUG_ON’
  BUILD_BUG_ON(sizeof(_i) > sizeof(long));   \
  ^~~~
drivers/gpu/drm/i915/i915_query.c:118:15: note: in expansion of macro 
‘array_index_nospec’
func_idx = array_index_nospec(func_idx,
   ^~
scripts/Makefile.build:312: recipe for target 
'drivers/gpu/drm/i915/i915_query.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_query.o] Error 1
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2


== Linux commits ==

92c303df8706 drm/i915: add a sysfs entry to let users set sseu configs
14eb252b3b42 drm/i915: Expose RPCS (SSEU) configuration to userspace
2bfb63f77f52 drm/i915/perf: lock powergating configuration to default when 
active
59f0b58443a7 drm/i915/perf: reuse intel_lrc ctx regs macro

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: per context slice/subslice powergating (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev5)
URL   : https://patchwork.freedesktop.org/series/42285/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Program RPCS for Broadwell
Okay!

Commit: drm/i915: Record the sseu configuration per-context & engine
Okay!

Commit: drm/i915/perf: simplify configure all context function
Okay!

Commit: drm/i915/perf: reuse intel_lrc ctx regs macro
Okay!

Commit: drm/i915/perf: lock powergating configuration to default when active
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3663:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3679:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3679:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression 
using sizeof(void)

Commit: drm/i915: add a sysfs entry to let users set sseu configs
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3697:16: warning: expression 
using sizeof(void)

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev5)
URL   : https://patchwork.freedesktop.org/series/42285/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
377ebb5122c5 drm/i915: Program RPCS for Broadwell
f8abc1461d28 drm/i915: Record the sseu configuration per-context & engine
-:65: ERROR:TRAILING_WHITESPACE: trailing whitespace
#65: FILE: drivers/gpu/drm/i915/i915_gem_context.h:161:
+^I^I$

total: 1 errors, 0 warnings, 0 checks, 123 lines checked
a6a8c598a410 drm/i915/perf: simplify configure all context function
59f0b58443a7 drm/i915/perf: reuse intel_lrc ctx regs macro
2bfb63f77f52 drm/i915/perf: lock powergating configuration to default when 
active
14eb252b3b42 drm/i915: Expose RPCS (SSEU) configuration to userspace
-:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#40: 
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)

total: 0 errors, 1 warnings, 0 checks, 437 lines checked
92c303df8706 drm/i915: add a sysfs entry to let users set sseu configs

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[Intel-gfx] ✓ Fi.CI.IGT: success for Per-context and per-client engine busyness (rev6)

[Patchwork]

== Series Details ==

Series: Per-context and per-client engine busyness (rev6)
URL   : https://patchwork.freedesktop.org/series/32645/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4220_full -> Patchwork_9081_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9081_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9081_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/32645/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9081_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS

igt@pm_rc6_residency@rc6-accuracy:
  shard-snb:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9081_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#105454, fdo#106509)

igt@kms_flip@2x-plain-flip-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105707)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
  shard-snb:  PASS -> DMESG-WARN (fdo#102365)


 Possible fixes 

igt@kms_cursor_crc@cursor-256x256-suspend:
  shard-apl:  FAIL (fdo#103375) -> PASS

igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS

igt@kms_rotation_crc@sprite-rotation-180:
  shard-snb:  FAIL (fdo#103925, fdo#104724) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4220 -> Patchwork_9081

  CI_DRM_4220: 9d7ce3ad8801a95461ad4fb63bd5374dfc2dff55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9081: 2eefca086175319a176f44264df4751784fdbb3b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9081/shards.html
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[Intel-gfx] [PATCH v6 2/7] drm/i915: Record the sseu configuration per-context & engine

[Lionel Landwerlin]

From: Chris Wilson 

We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.

v2: record sseu configuration per context & engine (Chris)

v3: introduce the i915_gem_context_sseu to store powergating
programming, sseu_dev_info has grown quite a bit (Lionel)

v4: rename i915_gem_sseu into intel_sseu (Chris)
use to_intel_context() (Chris)

Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_gem_context.c |  9 +
 drivers/gpu/drm/i915/i915_gem_context.h | 17 +
 drivers/gpu/drm/i915/i915_request.h | 13 +
 drivers/gpu/drm/i915/intel_lrc.c| 22 +++---
 4 files changed, 50 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..ea9ae1046827 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -260,6 +260,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
 {
struct i915_gem_context *ctx;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
unsigned int n;
int ret;
 
@@ -315,6 +317,13 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 * is no remap info, it will be a NOP. */
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
 
+   /* On all engines, use the whole device by default */
+   for_each_engine(engine, dev_priv, id) {
+   struct intel_context *ce = to_intel_context(ctx, engine);
+
+   ce->sseu = 
intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu);
+   }
+
i915_gem_context_set_bannable(ctx);
ctx->ring_size = 4 * PAGE_SIZE;
ctx->desc_template =
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index c3262b4dd2ee..b18d870c4932 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -30,6 +30,7 @@
 #include 
 
 #include "i915_gem.h"
+#include "intel_device_info.h"
 
 struct pid;
 
@@ -157,6 +158,9 @@ struct i915_gem_context {
int pin_count;
 
const struct intel_context_ops *ops;
+   
+   /** sseu: Control eu/slice partitioning */
+   union intel_sseu sseu;
} __engine[I915_NUM_ENGINES];
 
/** ring_size: size for allocating the per-engine ring buffer */
@@ -335,4 +339,17 @@ static inline void i915_gem_context_put(struct 
i915_gem_context *ctx)
kref_put(>ref, i915_gem_context_release);
 }
 
+static inline union intel_sseu
+intel_sseu_from_device_sseu(const struct sseu_dev_info *sseu)
+{
+   union intel_sseu value = {
+   .slice_mask = sseu->slice_mask,
+   .subslice_mask = sseu->subslice_mask[0],
+   .min_eus_per_subslice = sseu->max_eus_per_subslice,
+   .max_eus_per_subslice = sseu->max_eus_per_subslice,
+   };
+
+   return value;
+}
+
 #endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_request.h 
b/drivers/gpu/drm/i915/i915_request.h
index 17a9fa03..aca60895582b 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -39,6 +39,19 @@ struct drm_i915_gem_object;
 struct i915_request;
 struct i915_timeline;
 
+/*
+ * Powergating configuration for a particular (context,engine).
+ */
+union intel_sseu {
+   struct {
+   u8 slice_mask;
+   u8 subslice_mask;
+   u8 min_eus_per_subslice;
+   u8 max_eus_per_subslice;
+   };
+   u64 value;
+};
+
 struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2500c209c63..f875be03eadb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2481,8 +2481,8 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
return logical_ring_init(engine);
 }
 
-static u32
-make_rpcs(struct drm_i915_private *dev_priv)
+static u32 make_rpcs(const struct sseu_dev_info *sseu,
+union intel_sseu ctx_sseu)
 {
u32 rpcs = 0;
 
@@ -2492,24 +2492,23 @@ make_rpcs(struct drm_i915_private *dev_priv)
 * must make an explicit request through RPCS for full
 * enablement.
*/
-   if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+   if (sseu->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
-   rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
-   GEN8_RPCS_S_CNT_SHIFT;
+ 

[Intel-gfx] [PATCH v6 5/7] drm/i915/perf: lock powergating configuration to default when active

[Lionel Landwerlin]

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.

One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.

Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.

Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active. There is no known issue with this apart from a performance
penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from affecting the
programming so it doesn't sound completely unreasonable to hold on
powergating for the same reason.

v2: Leave RPCS programming in intel_lrc.c (Lionel)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h  | 16 
 drivers/gpu/drm/i915/i915_perf.c | 24 +++-
 drivers/gpu/drm/i915/intel_lrc.c | 11 +++
 drivers/gpu/drm/i915/intel_lrc.h |  3 +++
 4 files changed, 45 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b86ed6401120..21631b51b37b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2743,6 +2743,22 @@ int vlv_force_gfx_clock(struct drm_i915_private 
*dev_priv, bool on);
 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
 int intel_engines_init(struct drm_i915_private *dev_priv);
 
+static inline union intel_sseu
+intel_engine_prepare_sseu(struct intel_engine_cs *engine,
+ union intel_sseu sseu)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+
+   /*
+* If i915/perf is active, we want a stable powergating configuration
+* on the system. The most natural configuration to take in that case
+* is the default (i.e maximum the hardware can do).
+*/
+   return dev_priv->perf.oa.exclusive_stream ?
+   intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu) :
+   sseu;
+}
+
 /* intel_hotplug.c */
 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
   u32 pin_mask, u32 long_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a5d98bda5c2e..7ba8a3ff744c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1574,7 +1574,8 @@ static void hsw_disable_metric_set(struct 
drm_i915_private *dev_priv)
  */
 static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
   u32 *reg_state,
-  const struct i915_oa_config 
*oa_config)
+  const struct i915_oa_config 
*oa_config,
+  union intel_sseu sseu)
 {
struct drm_i915_private *dev_priv = ctx->i915;
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
@@ -1620,6 +1621,9 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
 
CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
+
+   CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+   gen8_make_rpcs(_INFO(dev_priv)->sseu, sseu));
 }
 
 /*
@@ -1751,6 +1755,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
   const struct i915_oa_config *oa_config)
 {
struct intel_engine_cs *engine = dev_priv->engine[RCS];
+   union intel_sseu default_sseu =
+   intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu);
struct i915_gem_context *ctx;
int ret;
unsigned int wait_flags = I915_WAIT_LOCKED;
@@ -1795,7 +1801,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
ce->state->obj->mm.dirty = true;
regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
 
-   gen8_update_reg_state_unlocked(ctx, regs, oa_config);
+   gen8_update_reg_state_unlocked(ctx, regs, 

[Intel-gfx] [PATCH v6 4/7] drm/i915/perf: reuse intel_lrc ctx regs macro

[Lionel Landwerlin]

Abstract the context image access a bit.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 34 +++-
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 805dfc732bba..a5d98bda5c2e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -210,6 +210,7 @@
 #include "i915_oa_cflgt3.h"
 #include "i915_oa_cnl.h"
 #include "i915_oa_icl.h"
+#include "intel_lrc_reg.h"
 
 /* HW requires this to be a power of two, between 128k and 16M, though driver
  * is currently generally designed assuming the largest 16M size is used such
@@ -1579,27 +1580,25 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
/* The MMIO offsets for Flex EU registers aren't contiguous */
-   u32 flex_mmio[] = {
-   i915_mmio_reg_offset(EU_PERF_CNTL0),
-   i915_mmio_reg_offset(EU_PERF_CNTL1),
-   i915_mmio_reg_offset(EU_PERF_CNTL2),
-   i915_mmio_reg_offset(EU_PERF_CNTL3),
-   i915_mmio_reg_offset(EU_PERF_CNTL4),
-   i915_mmio_reg_offset(EU_PERF_CNTL5),
-   i915_mmio_reg_offset(EU_PERF_CNTL6),
+   i915_reg_t flex_regs[] = {
+   EU_PERF_CNTL0,
+   EU_PERF_CNTL1,
+   EU_PERF_CNTL2,
+   EU_PERF_CNTL3,
+   EU_PERF_CNTL4,
+   EU_PERF_CNTL5,
+   EU_PERF_CNTL6,
};
int i;
 
-   reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
-   reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent <<
- GEN8_OA_TIMER_PERIOD_SHIFT) |
-(dev_priv->perf.oa.periodic ?
- GEN8_OA_TIMER_ENABLE : 0) |
-GEN8_OA_COUNTER_RESUME;
+   CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
+   (dev_priv->perf.oa.period_exponent << 
GEN8_OA_TIMER_PERIOD_SHIFT) |
+   (dev_priv->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
+   GEN8_OA_COUNTER_RESUME);
 
-   for (i = 0; i < ARRAY_SIZE(flex_mmio); i++) {
+   for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
u32 state_offset = ctx_flexeu0 + i * 2;
-   u32 mmio = flex_mmio[i];
+   u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
 
/*
 * This arbitrary default will select the 'EU FPU0 Pipeline
@@ -1619,8 +1618,7 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
}
}
 
-   reg_state[state_offset] = mmio;
-   reg_state[state_offset+1] = value;
+   CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
 }
 
-- 
2.17.0

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[Intel-gfx] [PATCH v6 3/7] drm/i915/perf: simplify configure all context function

[Lionel Landwerlin]

We don't need any special treatment on error so just return as soon as
possible.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4f0eb84b3c00..805dfc732bba 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1762,7 +1762,7 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
/* Switch away from any user context. */
ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
if (ret)
-   goto out;
+   return ret;
 
/*
 * The OA register config is setup through the context image. This image
@@ -1779,7 +1779,7 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
 */
ret = i915_gem_wait_for_idle(dev_priv, wait_flags);
if (ret)
-   goto out;
+   return ret;
 
/* Update all contexts now that we've stalled the submission. */
list_for_each_entry(ctx, _priv->contexts.list, link) {
@@ -1791,10 +1791,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
continue;
 
regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
-   if (IS_ERR(regs)) {
-   ret = PTR_ERR(regs);
-   goto out;
-   }
+   if (IS_ERR(regs))
+   return PTR_ERR(regs);
 
ce->state->obj->mm.dirty = true;
regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
@@ -1804,7 +1802,6 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
i915_gem_object_unpin_map(ce->state->obj);
}
 
- out:
return ret;
 }
 
-- 
2.17.0

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[Intel-gfx] [PATCH v6 1/7] drm/i915: Program RPCS for Broadwell

[Lionel Landwerlin]

From: Chris Wilson 

Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may want to
opt out of the "always-enabled" setting.

Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_lrc.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 857ab04452f0..c2500c209c63 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2486,13 +2486,6 @@ make_rpcs(struct drm_i915_private *dev_priv)
 {
u32 rpcs = 0;
 
-   /*
-* No explicit RPCS request is needed to ensure full
-* slice/subslice/EU enablement prior to Gen9.
-   */
-   if (INTEL_GEN(dev_priv) < 9)
-   return 0;
-
/*
 * Starting in Gen9, render power gating can leave
 * slice/subslice/EU in a partially enabled state. We
-- 
2.17.0

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[Intel-gfx] [PATCH v6 0/7] drm/i915: per context slice/subslice powergating

[Lionel Landwerlin]

Hi all,

This iteration adds a couple of things that were missing in v5 :

  - Synchronize requests on the last powergating change request

  - Add a new sysfs entry "gem_allow_sseu" to let normal users set
their sseu configuration. It's disabled by default for normal
users.

Cheers,

Chris Wilson (3):
  drm/i915: Program RPCS for Broadwell
  drm/i915: Record the sseu configuration per-context & engine
  drm/i915: Expose RPCS (SSEU) configuration to userspace

Lionel Landwerlin (4):
  drm/i915/perf: simplify configure all context function
  drm/i915/perf: reuse intel_lrc ctx regs macro
  drm/i915/perf: lock powergating configuration to default when active
  drm/i915: add a sysfs entry to let users set sseu configs

 drivers/gpu/drm/i915/i915_drv.h |  34 
 drivers/gpu/drm/i915/i915_gem.c |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c | 226 
 drivers/gpu/drm/i915/i915_gem_context.h |  17 ++
 drivers/gpu/drm/i915/i915_perf.c|  69 
 drivers/gpu/drm/i915/i915_request.c |  20 +++
 drivers/gpu/drm/i915/i915_request.h |  13 ++
 drivers/gpu/drm/i915/i915_sysfs.c   |  30 
 drivers/gpu/drm/i915/intel_lrc.c| 117 +++-
 drivers/gpu/drm/i915/intel_lrc.h|   3 +
 drivers/gpu/drm/i915/intel_ringbuffer.c |   2 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   4 +
 include/uapi/drm/i915_drm.h |  38 
 13 files changed, 501 insertions(+), 74 deletions(-)

--
2.17.0
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[Intel-gfx] [PATCH v6 7/7] drm/i915: add a sysfs entry to let users set sseu configs

[Lionel Landwerlin]

There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |  5 +++
 drivers/gpu/drm/i915/i915_gem_context.c | 52 -
 drivers/gpu/drm/i915/i915_sysfs.c   | 30 ++
 3 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 09cfcfe1c339..0fccec29fdda 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1843,6 +1843,8 @@ struct drm_i915_private {
struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+
+   bool allow_sseu;
} contexts;
 
u32 fdi_rx_config;
@@ -3274,6 +3276,9 @@ i915_gem_context_lookup(struct drm_i915_file_private 
*file_priv, u32 id)
return ctx;
 }
 
+int i915_gem_contexts_set_allow_sseu(struct drm_i915_private *dev_priv, bool 
allowed);
+bool i915_gem_contexts_get_allow_sseu(struct drm_i915_private *dev_priv);
+
 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file);
 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5c5a12f1c265..815a9d1c29f3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -981,7 +981,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, 
void *data,
break;
}
 
-   if (!capable(CAP_SYS_ADMIN)) {
+   if (!dev_priv->contexts.allow_sseu &&
+   !capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
break;
}
@@ -1058,6 +1059,55 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
return ret;
 }
 
+int i915_gem_contexts_set_allow_sseu(struct drm_i915_private *dev_priv,
+bool allowed)
+{
+   struct intel_engine_cs *engine = dev_priv->engine[RCS];
+   int ret = 0;
+
+   if (!engine->emit_rpcs_config)
+   return -ENODEV;
+
+   mutex_lock(_priv->drm.struct_mutex);
+
+   /*
+* When we allow each context to configure its powergating
+* configuration, there is no need to put the configurations back to
+* the default, it should already be the case.
+*/
+   if (!allowed) {
+   union intel_sseu default_sseu =
+   
intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu);
+   struct i915_gem_context *ctx;
+
+   list_for_each_entry(ctx, _priv->contexts.list, link) {
+   ret = i915_gem_context_reconfigure_sseu(ctx, engine,
+   default_sseu);
+   if (ret)
+   break;
+   }
+   }
+
+   dev_priv->contexts.allow_sseu = allowed;
+
+   mutex_unlock(_priv->drm.struct_mutex);
+   return ret;
+}
+
+bool i915_gem_contexts_get_allow_sseu(struct drm_i915_private *dev_priv)
+{
+   struct intel_engine_cs *engine = dev_priv->engine[RCS];
+   bool ret;
+
+   if (!engine->emit_rpcs_config)
+   return false;
+
+   mutex_lock(_priv->drm.struct_mutex);
+   ret = dev_priv->contexts.allow_sseu;
+   mutex_unlock(_priv->drm.struct_mutex);
+   return ret;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_context.c"
 #include "selftests/i915_gem_context.c"
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6bb2b05..9fd15b138ac9 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -483,6 +483,34 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct 
device_attribute *attr
return snprintf(buf, PAGE_SIZE, "%d\n", val);
 }
 
+static ssize_t gem_allow_sseu_show(struct device *kdev,
+  struct device_attribute *attr, char *buf)
+{
+   struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+   int ret = i915_gem_contexts_get_allow_sseu(dev_priv);
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", ret);
+}
+
+static ssize_t gem_allow_sseu_store(struct device *kdev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+   u32 

[Intel-gfx] [PATCH v6 6/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

[Lionel Landwerlin]

From: Chris Wilson 

We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
first use, the adjustment is for "free"; otherwise if the context is
active we flush the context off the GPU (stalling all users) and forcing
the GPU to save the context to memory where we can modify it and so
ensure that the register is reloaded on next execution.

The overhead of managing additional EU subslices can be significant,
especially in multi-context workloads. Non-GPGPU contexts should
preferably disable the subslices it is not using, and others should
fine-tune the number to match their workload.

We expose complete control over the RPCS register, allowing
configuration of slice/subslice, via masks packed into a u64 for
simplicity. For example,

struct drm_i915_gem_context_param arg;
struct drm_i915_gem_context_param_sseu sseu = { .class = 0,
.instance = 0, };

memset(, 0, sizeof(arg));
arg.ctx_id = ctx;
arg.param = I915_CONTEXT_PARAM_SSEU;
arg.value = (uintptr_t) 
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, ) == 0) {
sseu.packed.subslice_mask = 0;

drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, );
}

could be used to disable all subslices where supported.

v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)

v3: Add ability to program this per engine (Chris)

v4: Move most get_sseu() into i915_gem_context.c (Lionel)

v5: Validate sseu configuration against the device's capabilities (Lionel)

v6: Change context powergating settings through MI_SDM on kernel context (Chris)

v7: Synchronize the requests following a powergating setting change using a 
global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
c: Dmitry Rogozhkin 
CC: Tvrtko Ursulin 
CC: Zhipeng Gong 
CC: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h |  13 ++
 drivers/gpu/drm/i915/i915_gem.c |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c | 167 
 drivers/gpu/drm/i915/i915_request.c |  20 +++
 drivers/gpu/drm/i915/intel_lrc.c| 103 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c |   2 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   4 +
 include/uapi/drm/i915_drm.h |  38 ++
 8 files changed, 314 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21631b51b37b..09cfcfe1c339 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2067,6 +2067,12 @@ struct drm_i915_private {
u32 active_requests;
u32 request_serial;
 
+   /**
+* Global barrier to ensuring ordering of sseu transitions
+* requests.
+*/
+   struct i915_gem_active global_barrier;
+
/**
 * Is the GPU currently considered idle, or busy executing
 * userspace requests? Whilst idle, we allow runtime power
@@ -3227,6 +3233,13 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
return container_of(vm, struct i915_hw_ppgtt, base);
 }
 
+static inline void i915_gem_set_global_barrier(struct drm_i915_private *i915,
+  struct i915_request *rq)
+{
+   lockdep_assert_held(>drm.struct_mutex);
+   i915_gem_active_set(>gt.global_barrier, rq);
+}
+
 /* i915_gem_fence_reg.c */
 struct drm_i915_fence_reg *
 i915_reserve_fence(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03874b50ada9..9c2a0d04bd39 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5548,6 +5548,8 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
if (!dev_priv->priorities)
goto err_dependencies;
 
+   init_request_active(_priv->gt.global_barrier, NULL);
+
INIT_LIST_HEAD(_priv->gt.timelines);
INIT_LIST_HEAD(_priv->gt.active_rings);
INIT_LIST_HEAD(_priv->gt.closed_vma);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index ea9ae1046827..5c5a12f1c265 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/query: nospec expects no more than an unsigned long

[Patchwork]

== Series Details ==

Series: drm/i915/query: nospec expects no more than an unsigned long
URL   : https://patchwork.freedesktop.org/series/43569/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4220_full -> Patchwork_9080_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9080_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9080_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43569/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9080_full:

  === IGT changes ===

 Warnings 

igt@pm_rc6_residency@rc6-accuracy:
  shard-snb:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9080_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)
  shard-glk:  PASS -> INCOMPLETE (fdo#103359, k.org#198133)

igt@drv_selftest@live_hangcheck:
  shard-apl:  NOTRUN -> DMESG-FAIL (fdo#106560)

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  FAIL (fdo#104724) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4220 -> Patchwork_9080

  CI_DRM_4220: 9d7ce3ad8801a95461ad4fb63bd5374dfc2dff55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9080: 524dd95b840b645e0a894ae11afa50de33632e90 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9080/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

Quoting Chris Wilson (2018-05-22 16:49:02)
> In order to prepare the GPU for sleeping, we may want to submit commands
> to it. This is a complicated process that may even require some swapping
> in from shmemfs, if the GPU was in the wrong state. As such, we need to
> do this preparation step synchronously before the rest of the system has
> started to turn off (e.g. swapin fails if scsi is suspended).
> Fortunately, we are provided with a such a hook, pm_ops.prepare().
> 
> v2: Compile cleanup
> v3: Add manual calls to i915_drm_prepare() before i915_drm_suspend().

Revision 2 passed, but revision 3 fails. I don't understand... :(
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Promote .format_mod_supported() to the lead role

[Ville Syrjälä]

On Mon, May 21, 2018 at 12:21:01PM -0700, Eric Anholt wrote:
> Ville Syrjala  writes:
> 
> > From: Ville Syrjälä 
> >
> > Up to now we've used the plane's modifier list as the primary
> > source of information for which modifiers are supported by a
> > given plane. In order to allow auxiliary metadata to be embedded
> > within the bits of the modifier we need to stop doing that.
> >
> > Thus we have to make .format_mod_supported() aware of the plane's
> > capabilities and gracefully deal with any modifier being passed
> > in directly from userspace.
> 
> This seems like it would be a lot shorter if you just had a helper to
> check if your format and modifier was in drm_plane->format_types and
> drm_plane->modifiers, since then you wouldn't be duplicating your tables
> and you wouldn't need has_ccs either.

I suppose. And I guess that's where I started originally :/

But I'm not sure if it's better go that route or the other route of
reducing the arrays to some simple supersets and also utilize
.format_mod_supported() in plane init to filter out the unsupported
formats when populating the plane's format list. Probably best not
dwell on this too much for now so that we can at least make some
progress :)

> 
> However, it's not my driver and it unblocks vc4's patch, so:
> 
> Reviewed-by: Eric Anholt 

Thanks. I'm guessing we should push this into drm-misc-next so
that you can pile your core/sand bits on top?

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Prepare GEM for suspend earlier (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare GEM for suspend earlier (rev3)
URL   : https://patchwork.freedesktop.org/series/43575/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9088 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9088 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9088, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43575/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9088:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-reload-inject:
  {fi-kbl-guc}:   PASS -> FAIL +3

igt@gem_exec_suspend@basic-s4-devices:
  fi-cfl-s3:  PASS -> FAIL
  fi-byt-n2820:   PASS -> FAIL
  fi-cfl-u:   PASS -> FAIL
  fi-snb-2600:PASS -> FAIL
  fi-bxt-j4205:   PASS -> FAIL
  fi-kbl-7567u:   PASS -> FAIL
  fi-hsw-4200u:   PASS -> FAIL
  fi-bdw-gvtdvm:  PASS -> FAIL
  fi-kbl-r:   PASS -> FAIL
  fi-snb-2520m:   PASS -> FAIL
  fi-bxt-dsi: PASS -> FAIL
  fi-ivb-3520m:   PASS -> FAIL
  fi-hsw-4770:PASS -> FAIL
  fi-ilk-650: PASS -> FAIL
  fi-bsw-n3050:   PASS -> FAIL
  fi-ivb-3770:PASS -> FAIL
  fi-hsw-peppy:   PASS -> FAIL
  fi-hsw-4770r:   PASS -> FAIL
  fi-kbl-7500u:   PASS -> FAIL
  fi-bdw-5557u:   PASS -> FAIL
  fi-cfl-8700k:   PASS -> FAIL
  fi-byt-j1900:   PASS -> FAIL
  fi-kbl-7560u:   PASS -> FAIL

igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
  fi-skl-guc: PASS -> FAIL +2
  {fi-cfl-guc}:   PASS -> FAIL +3


 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS

igt@gem_render_tiled_blits@basic:
  {fi-cfl-guc}:   PASS -> SKIP +24

igt@gem_ringfill@basic-default:
  fi-skl-guc: PASS -> SKIP +24

igt@kms_force_connector_basic@force-edid:
  fi-ivb-3520m:   PASS -> SKIP +3

igt@prime_vgem@basic-wait-default:
  {fi-kbl-guc}:   PASS -> SKIP +32


== Known issues ==

  Here are the changes found in Patchwork_9088 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s4-devices:
  fi-skl-6260u:   PASS -> FAIL (fdo#105900)
  fi-skl-6700k2:  PASS -> FAIL (fdo#105900)
  fi-glk-j4005:   PASS -> FAIL (fdo#105900)
  fi-skl-gvtdvm:  PASS -> FAIL (fdo#105900)
  fi-cnl-psr: PASS -> FAIL (fdo#105900)
  fi-skl-guc: PASS -> FAIL (fdo#104699, fdo#105900)
  fi-skl-6770hq:  PASS -> FAIL (fdo#105900)
  fi-skl-6600u:   PASS -> FAIL (fdo#105900)
  fi-cnl-y3:  PASS -> FAIL (fdo#105900)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-cnl-y3:  PASS -> DMESG-FAIL (fdo#103191, fdo#104724)


 Possible fixes 

igt@kms_flip@basic-flip-vs-dpms:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cfl-s3:  FAIL (fdo#103481) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104699 https://bugs.freedesktop.org/show_bug.cgi?id=104699
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4221 -> Patchwork_9088

  CI_DRM_4221: d83aef98e4f2e35440222c69ef80a68daf1abb4e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9088: 9ab7370cff43fb22409904f2bab54ed3f9bc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9088/build_32bit.log

  CHK include/config/kernel.release
  CHK  

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

[Lionel Landwerlin]

On 22/05/18 17:11, Lionel Landwerlin wrote:

On 21/05/18 17:00, Tvrtko Ursulin wrote:


+
+    /* Queue this switch after all other activity */
+    list_for_each_entry(timeline, _priv->gt.timelines, link) {


This can iterate over gt.active_rings for a shorter walk. See current 
state of engine_has_idle_kernel_context.


For some reason, iterating over gt.active_rings will trigger an 
invalid memory access :|


Not sure what's wrong here...


Duh!

Found it :

list_for_each_entry(ring, _priv->gt.active_rings, link) {

Instead of :

list_for_each_entry(ring, _priv->gt.active_rings, active_link) {

-
Lionel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Prepare GEM for suspend earlier

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Prepare GEM for suspend earlier
URL   : https://patchwork.freedesktop.org/series/43578/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9087 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9087 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9087, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43578/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9087:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-no-display:
  fi-elk-e7500:   PASS -> FAIL
  fi-snb-2520m:   PASS -> FAIL
  fi-cfl-8700k:   PASS -> FAIL +1
  fi-ivb-3520m:   PASS -> FAIL
  fi-bdw-gvtdvm:  PASS -> FAIL
  fi-pnv-d510:PASS -> FAIL
  fi-hsw-4200u:   PASS -> FAIL +1
  fi-bwr-2160:PASS -> FAIL
  fi-bdw-5557u:   PASS -> FAIL +1
  fi-skl-6260u:   PASS -> FAIL +1
  fi-snb-2600:PASS -> FAIL
  fi-bsw-n3050:   PASS -> FAIL +1
  fi-ivb-3770:PASS -> FAIL
  {fi-kbl-guc}:   PASS -> FAIL
  fi-kbl-7500u:   PASS -> FAIL +1
  fi-blb-e6850:   PASS -> FAIL
  fi-cfl-u:   PASS -> FAIL +1
  fi-gdg-551: PASS -> FAIL
  fi-skl-gvtdvm:  PASS -> FAIL
  fi-ilk-650: PASS -> FAIL

igt@drv_module_reload@basic-reload:
  fi-skl-guc: PASS -> DMESG-FAIL +1
  fi-bdw-gvtdvm:  PASS -> DMESG-FAIL
  fi-kbl-r:   PASS -> DMESG-FAIL +1
  fi-gdg-551: PASS -> DMESG-FAIL
  fi-cfl-8700k:   PASS -> DMESG-FAIL +1
  fi-snb-2520m:   PASS -> DMESG-FAIL
  fi-bxt-dsi: NOTRUN -> DMESG-FAIL +1
  fi-ivb-3520m:   PASS -> DMESG-FAIL
  fi-hsw-4770:PASS -> DMESG-FAIL +1
  {fi-cfl-guc}:   PASS -> DMESG-FAIL +1
  fi-ilk-650: PASS -> DMESG-FAIL
  fi-bsw-n3050:   PASS -> DMESG-FAIL +1
  fi-ivb-3770:PASS -> DMESG-FAIL
  fi-cnl-y3:  PASS -> DMESG-FAIL +1
  fi-cfl-s3:  PASS -> DMESG-FAIL +1
  fi-hsw-4770r:   PASS -> DMESG-FAIL +1
  fi-cfl-u:   PASS -> DMESG-FAIL +1
  fi-kbl-7500u:   PASS -> DMESG-FAIL +1
  fi-bdw-5557u:   PASS -> DMESG-FAIL +1
  fi-kbl-7567u:   PASS -> DMESG-FAIL +1
  {fi-kbl-guc}:   PASS -> DMESG-FAIL
  fi-hsw-4200u:   PASS -> DMESG-FAIL +1
  fi-blb-e6850:   PASS -> DMESG-FAIL
  fi-pnv-d510:PASS -> DMESG-FAIL
  fi-elk-e7500:   PASS -> DMESG-FAIL
  fi-skl-gvtdvm:  PASS -> DMESG-FAIL
  fi-snb-2600:PASS -> DMESG-FAIL
  fi-bwr-2160:PASS -> DMESG-FAIL

igt@drv_module_reload@basic-reload-inject:
  fi-skl-6260u:   PASS -> INCOMPLETE
  fi-snb-2600:PASS -> INCOMPLETE
  fi-kbl-7560u:   PASS -> INCOMPLETE
  {fi-kbl-guc}:   PASS -> INCOMPLETE
  fi-hsw-4200u:   PASS -> INCOMPLETE
  fi-skl-6770hq:  PASS -> INCOMPLETE
  fi-kbl-r:   PASS -> INCOMPLETE
  fi-cfl-s3:  PASS -> INCOMPLETE
  fi-gdg-551: PASS -> INCOMPLETE
  fi-ilk-650: PASS -> INCOMPLETE
  fi-bsw-n3050:   PASS -> INCOMPLETE
  fi-kbl-7567u:   PASS -> INCOMPLETE
  fi-ivb-3770:PASS -> INCOMPLETE
  fi-kbl-7500u:   PASS -> INCOMPLETE
  fi-ivb-3520m:   PASS -> INCOMPLETE
  fi-hsw-4770:PASS -> INCOMPLETE
  fi-bdw-5557u:   PASS -> INCOMPLETE
  fi-cfl-8700k:   PASS -> INCOMPLETE
  fi-hsw-peppy:   PASS -> INCOMPLETE
  fi-skl-6600u:   PASS -> INCOMPLETE
  fi-pnv-d510:PASS -> INCOMPLETE
  fi-hsw-4770r:   PASS -> INCOMPLETE
  fi-skl-guc: PASS -> INCOMPLETE
  {fi-cfl-guc}:   PASS -> INCOMPLETE
  fi-blb-e6850:   PASS -> INCOMPLETE
  fi-skl-6700k2:  PASS -> INCOMPLETE
  fi-cfl-u:   PASS -> INCOMPLETE

igt@pm_rpm@basic-pci-d3-state:
  fi-skl-6600u:   PASS -> DMESG-FAIL +1
  fi-kbl-7560u:   PASS -> DMESG-FAIL +1
  fi-byt-j1900:   PASS -> DMESG-FAIL +1
  fi-byt-n2820:   PASS -> DMESG-FAIL +1
  fi-skl-6770hq:  PASS -> DMESG-FAIL +1
  fi-skl-6700k2:  PASS -> DMESG-FAIL +1
  fi-cnl-psr: PASS -> DMESG-FAIL
  fi-bxt-j4205:   PASS -> DMESG-FAIL +1
  fi-skl-6260u:   PASS -> DMESG-FAIL +1
  fi-hsw-peppy:   PASS -> DMESG-FAIL +1

igt@pm_rpm@basic-rte:
  {fi-cfl-guc}:   PASS -> FAIL +1
  fi-skl-guc: PASS -> FAIL +1
  fi-kbl-7567u:   PASS -> FAIL +1
  fi-hsw-peppy:   

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

[Lionel Landwerlin]

On 21/05/18 17:00, Tvrtko Ursulin wrote:


+
+    /* Queue this switch after all other activity */
+    list_for_each_entry(timeline, _priv->gt.timelines, link) {


This can iterate over gt.active_rings for a shorter walk. See current 
state of engine_has_idle_kernel_context.


For some reason, iterating over gt.active_rings will trigger an invalid 
memory access :|


Not sure what's wrong here...

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Wait for ELSP submission on restart

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Wait for ELSP submission on restart
URL   : https://patchwork.freedesktop.org/series/43563/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4219_full -> Patchwork_9078_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9078_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9078_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43563/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9078_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-bsd1:
  shard-kbl:  PASS -> SKIP

igt@gem_mocs_settings@mocs-rc6-vebox:
  shard-kbl:  SKIP -> PASS +2


== Known issues ==

  Here are the changes found in Patchwork_9078_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_cursor_crc@cursor-256x256-suspend:
  shard-glk:  PASS -> INCOMPLETE (k.org#198133, fdo#103359)

igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
  shard-glk:  PASS -> FAIL (fdo#104873)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#106509, fdo#105454)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
  shard-glk:  PASS -> DMESG-WARN (fdo#106247) +1

igt@pm_rpm@system-suspend-modeset:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103313)


 Possible fixes 

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#102887, fdo#105363) -> PASS

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-apl:  DMESG-WARN (fdo#103558, fdo#105602) -> PASS +8


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4219 -> Patchwork_9078

  CI_DRM_4219: 510bfdf6beaa5f2409cc638442eced81535e63b4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9078: 78159a7b195f064644a1952c1c892539ae2bf36a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9078/shards.html
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Re: [Intel-gfx] [PATCH v4 1/2] vfio/mdev: Check globally for duplicate devices

[Alex Williamson]

[Cc +GVT-g maintainers/lists]

On Tue, 22 May 2018 10:13:46 +0200
Cornelia Huck  wrote:

> On Fri, 18 May 2018 13:10:25 -0600
> Alex Williamson  wrote:
> 
> > When we create an mdev device, we check for duplicates against the
> > parent device and return -EEXIST if found, but the mdev device
> > namespace is global since we'll link all devices from the bus.  We do
> > catch this later in sysfs_do_create_link_sd() to return -EEXIST, but
> > with it comes a kernel warning and stack trace for trying to create
> > duplicate sysfs links, which makes it an undesirable response.
> > 
> > Therefore we should really be looking for duplicates across all mdev
> > parent devices, or as implemented here, against our mdev device list.
> > Using mdev_list to prevent duplicates means that we can remove
> > mdev_parent.lock, but in order not to serialize mdev device creation
> > and removal globally, we add mdev_device.active which allows UUIDs to
> > be reserved such that we can drop the mdev_list_lock before the mdev
> > device is fully in place.
> > 
> > Two behavioral notes; first, mdev_parent.lock had the side-effect of
> > serializing mdev create and remove ops per parent device.  This was
> > an implementation detail, not an intentional guarantee provided to
> > the mdev vendor drivers.  Vendor drivers can trivially provide this
> > serialization internally if necessary.  Second, review comments note
> > the new -EAGAIN behavior when the device, and in particular the remove
> > attribute, becomes visible in sysfs.  If a remove is triggered prior
> > to completion of mdev_device_create() the user will see a -EAGAIN
> > error.  While the errno is different, receiving an error during this
> > period is not, the previous implementation returned -ENODEV for the
> > same condition.  Furthermore, the consistency to the user is improved
> > in the case where mdev_device_remove_ops() returns error.  Previously
> > concurrent calls to mdev_device_remove() could see the device
> > disappear with -ENODEV and return in the case of error.  Now a user
> > would see -EAGAIN while the device is in this transitory state.
> > 
> > Signed-off-by: Alex Williamson 
> > ---
> >  Documentation/vfio-mediated-device.txt |5 ++
> >  drivers/vfio/mdev/mdev_core.c  |  102 
> > +++-
> >  drivers/vfio/mdev/mdev_private.h   |2 -
> >  3 files changed, 42 insertions(+), 67 deletions(-)  
> 
> Reviewed-by: Cornelia Huck 
> 
> I think it is better to deal with any possible vendor driver
> implications on top of this (I still believe that vfio-ccw is fine).

Thanks Cornelia.  So if vfio-ccw is fine, presumably NVIDIA is fine,
then this leaves GVT-g to see if there's any fallout.  Zhenyu & Zhi,
I've linked the series under discussion here below[1].  The question to
you is the first of the two behavioral notes listed above, does GVT-g
have any dependency on the mdev core providing serialization per mdev
parent device for the create and remove callbacks within the
mdev_parent_ops?  This was never an intended feature of the
implementation and as noted it should be trivial for for an mdev vendor
driver to provide equivalent course grained serialization if
necessary.  Of course it would be better to implement that sooner
rather than later if required.

I see that __intel_gvt_create_vgpu() makes use of gvt->lock, which
would seem to already provide this level of per-parent locking. The
remove path makes use of this same lock, so I think we're ok, but
looking for an explicit ack so there are no surprises.  I'd like
to queue this series for v4.18.  Thanks,

Alex

[1] https://lkml.org/lkml/2018/5/18/1035
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[Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

v2: Compile cleanup
v3: Add manual calls to i915_drm_prepare() before i915_drm_suspend().

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 55 +++--
 1 file changed, 45 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..8642f9a1aff2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,12 +1553,30 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
-   int error;
 
/* ignore lid events during suspend */
mutex_lock(_priv->modeset_restore_lock);
@@ -1575,13 +1593,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -1609,10 +1620,9 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_csr_ucode_suspend(dev_priv);
 
-out:
enable_rpm_wakeref_asserts(dev_priv);
 
-   return error;
+   return 0;
 }
 
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
@@ -1695,6 +1705,10 @@ static int i915_suspend_switcheroo(struct drm_device 
*dev, pm_message_t state)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
 
+   error = i915_drm_prepare(dev);
+   if (error)
+   return error;
+
error = i915_drm_suspend(dev);
if (error)
return error;
@@ -2081,6 +2095,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2153,6 +2183,10 @@ static int i915_pm_freeze(struct device *kdev)
int ret;
 
if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
+   ret = i915_drm_prepare(dev);
+   if (ret)
+   return ret;
+
ret = i915_drm_suspend(dev);
if (ret)
return ret;
@@ -2731,6 +2765,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Prepare GEM for suspend earlier

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Prepare GEM for suspend earlier
URL   : https://patchwork.freedesktop.org/series/43577/
State : failure

== Summary ==

CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/selftests/igt_flush_test.o
drivers/gpu/drm/i915/selftests/igt_flush_test.c: In function ‘igt_flush_test’:
drivers/gpu/drm/i915/selftests/igt_flush_test.c:61:6: error: too few arguments 
to function ‘i915_gem_switch_to_kernel_context’
  i915_gem_switch_to_kernel_context(i915)) {
  ^
In file included from drivers/gpu/drm/i915/selftests/../intel_lrc.h:28:0,
 from drivers/gpu/drm/i915/selftests/../i915_drv.h:63,
 from drivers/gpu/drm/i915/selftests/igt_flush_test.c:7:
drivers/gpu/drm/i915/selftests/../i915_gem_context.h:306:5: note: declared here
 int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
 ^
scripts/Makefile.build:312: recipe for target 
'drivers/gpu/drm/i915/selftests/igt_flush_test.o' failed
make[4]: *** [drivers/gpu/drm/i915/selftests/igt_flush_test.o] Error 1
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Prepare GEM for suspend earlier

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare GEM for suspend earlier
URL   : https://patchwork.freedesktop.org/series/43576/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9085 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9085 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9085, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43576/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9085:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-no-display:
  fi-elk-e7500:   PASS -> FAIL
  fi-cfl-8700k:   PASS -> FAIL +1
  fi-ivb-3520m:   PASS -> FAIL
  fi-bdw-gvtdvm:  PASS -> FAIL
  fi-pnv-d510:PASS -> FAIL
  fi-hsw-4200u:   PASS -> FAIL +1
  fi-bwr-2160:PASS -> FAIL
  fi-bdw-5557u:   PASS -> FAIL +1
  fi-skl-6260u:   PASS -> FAIL +1
  fi-snb-2600:PASS -> FAIL
  fi-bsw-n3050:   PASS -> FAIL +1
  fi-ivb-3770:PASS -> FAIL
  {fi-kbl-guc}:   PASS -> FAIL
  fi-kbl-7500u:   PASS -> FAIL +1
  fi-blb-e6850:   PASS -> FAIL
  fi-cfl-u:   PASS -> FAIL +1
  fi-gdg-551: PASS -> FAIL
  fi-skl-gvtdvm:  PASS -> FAIL
  fi-ilk-650: PASS -> FAIL

igt@drv_module_reload@basic-reload:
  fi-skl-guc: PASS -> DMESG-FAIL +1
  fi-bdw-gvtdvm:  PASS -> DMESG-FAIL
  fi-kbl-r:   PASS -> DMESG-FAIL +1
  fi-gdg-551: PASS -> DMESG-FAIL
  fi-cfl-8700k:   PASS -> DMESG-FAIL +1
  fi-bxt-dsi: NOTRUN -> DMESG-FAIL +1
  fi-ivb-3520m:   PASS -> DMESG-FAIL
  fi-hsw-4770:PASS -> DMESG-FAIL +1
  {fi-cfl-guc}:   PASS -> DMESG-FAIL +1
  fi-ilk-650: PASS -> DMESG-FAIL
  fi-bsw-n3050:   PASS -> DMESG-FAIL +1
  fi-ivb-3770:PASS -> DMESG-FAIL
  fi-cnl-y3:  PASS -> DMESG-FAIL +1
  fi-cfl-s3:  PASS -> DMESG-FAIL +1
  fi-hsw-4770r:   PASS -> DMESG-FAIL +1
  fi-cfl-u:   PASS -> DMESG-FAIL +1
  fi-kbl-7500u:   PASS -> DMESG-FAIL +1
  fi-bdw-5557u:   PASS -> DMESG-FAIL +1
  fi-kbl-7567u:   PASS -> DMESG-FAIL +1
  {fi-kbl-guc}:   PASS -> DMESG-FAIL
  fi-hsw-4200u:   PASS -> DMESG-FAIL +1
  fi-blb-e6850:   PASS -> DMESG-FAIL
  fi-glk-j4005:   PASS -> DMESG-FAIL +1
  fi-pnv-d510:PASS -> DMESG-FAIL
  fi-elk-e7500:   PASS -> DMESG-FAIL
  fi-skl-gvtdvm:  PASS -> DMESG-FAIL
  fi-snb-2600:PASS -> DMESG-FAIL
  fi-bwr-2160:PASS -> DMESG-FAIL

igt@drv_module_reload@basic-reload-inject:
  fi-skl-6260u:   PASS -> INCOMPLETE
  fi-snb-2600:PASS -> INCOMPLETE
  fi-kbl-7560u:   PASS -> INCOMPLETE
  {fi-kbl-guc}:   PASS -> INCOMPLETE
  fi-hsw-4200u:   PASS -> INCOMPLETE
  fi-skl-6770hq:  PASS -> INCOMPLETE
  fi-kbl-r:   PASS -> INCOMPLETE
  fi-cfl-s3:  PASS -> INCOMPLETE
  fi-gdg-551: PASS -> INCOMPLETE
  fi-ilk-650: PASS -> INCOMPLETE
  fi-bsw-n3050:   PASS -> INCOMPLETE
  fi-kbl-7567u:   PASS -> INCOMPLETE
  fi-ivb-3770:PASS -> INCOMPLETE
  fi-kbl-7500u:   PASS -> INCOMPLETE
  fi-ivb-3520m:   PASS -> INCOMPLETE
  fi-hsw-4770:PASS -> INCOMPLETE
  fi-bdw-5557u:   PASS -> INCOMPLETE
  fi-cfl-8700k:   PASS -> INCOMPLETE
  fi-hsw-peppy:   PASS -> INCOMPLETE
  fi-skl-6600u:   PASS -> INCOMPLETE
  fi-pnv-d510:PASS -> INCOMPLETE
  fi-hsw-4770r:   PASS -> INCOMPLETE
  fi-skl-guc: PASS -> INCOMPLETE
  {fi-cfl-guc}:   PASS -> INCOMPLETE
  fi-blb-e6850:   PASS -> INCOMPLETE
  fi-skl-6700k2:  PASS -> INCOMPLETE
  fi-cfl-u:   PASS -> INCOMPLETE

igt@pm_rpm@basic-pci-d3-state:
  fi-skl-6600u:   PASS -> DMESG-FAIL +1
  fi-kbl-7560u:   PASS -> DMESG-FAIL +1
  fi-byt-j1900:   PASS -> DMESG-FAIL +1
  fi-byt-n2820:   PASS -> DMESG-FAIL +1
  fi-skl-6770hq:  PASS -> DMESG-FAIL +1
  fi-skl-6700k2:  PASS -> DMESG-FAIL +1
  fi-cnl-psr: PASS -> DMESG-FAIL
  fi-bxt-j4205:   PASS -> DMESG-FAIL +1
  fi-skl-6260u:   PASS -> DMESG-FAIL +1
  fi-hsw-peppy:   PASS -> DMESG-FAIL +1

igt@pm_rpm@basic-rte:
  fi-glk-j4005:   PASS -> FAIL +1
  {fi-cfl-guc}:   PASS -> FAIL +1
  fi-skl-guc: PASS -> FAIL +1
  fi-kbl-7567u:   PASS -> FAIL +1
  

[Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" after switching to the kernel context

[Chris Wilson]

During suspend we want to flush out all active contexts and their
rendering. To do so we queue a request from the kernel's context, once
we know that request is done, we know the GPU is completely idle. To
speed up that switch bump the GPU clocks.

Switching to the kernel context prior to idling is also used to enforce
a barrier before changing OA properties, and when evicting active
rendering from the global GTT. All cases where we do want to
race-to-idle.

v2: Limit the boosting to only the switch before suspend.
v3: Limit it to the wait-for-idle on suspend.

Signed-off-by: Chris Wilson 
Cc: David Weinehall 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala  #v1
Tested-by: David Weinehall  #v1
---
 drivers/gpu/drm/i915/i915_gem.c | 27 +--
 drivers/gpu/drm/i915/i915_request.h |  1 +
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a81aa124af26..b8945c998759 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3697,7 +3697,29 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
 
 static int wait_for_timeline(struct i915_timeline *tl, unsigned int flags)
 {
-   return i915_gem_active_wait(>last_request, flags);
+   struct i915_request *rq;
+   long ret;
+
+   rq = i915_gem_active_get_unlocked(>last_request);
+   if (!rq)
+   return 0;
+
+   /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+   if (flags & I915_WAIT_FOR_IDLE_BOOST)
+   gen6_rps_boost(rq, NULL);
+
+   ret = i915_request_wait(rq, flags, MAX_SCHEDULE_TIMEOUT);
+   i915_request_put(rq);
+
+   return ret < 0 ? ret : 0;
 }
 
 static int wait_for_engines(struct drm_i915_private *i915)
@@ -4964,7 +4986,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 
ret = i915_gem_wait_for_idle(dev_priv,
 I915_WAIT_INTERRUPTIBLE |
-I915_WAIT_LOCKED);
+I915_WAIT_LOCKED |
+I915_WAIT_FOR_IDLE_BOOST);
if (ret && ret != -EIO)
goto err_unlock;
 
diff --git a/drivers/gpu/drm/i915/i915_request.h 
b/drivers/gpu/drm/i915/i915_request.h
index 17a9fa03..491ff81d0fea 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -267,6 +267,7 @@ long i915_request_wait(struct i915_request *rq,
 #define I915_WAIT_INTERRUPTIBLEBIT(0)
 #define I915_WAIT_LOCKED   BIT(1) /* struct_mutex held, handle GPU reset */
 #define I915_WAIT_ALL  BIT(2) /* used by i915_gem_object_wait() */
+#define I915_WAIT_FOR_IDLE_BOOST BIT(3)
 
 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
 
-- 
2.17.0

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[Intel-gfx] [PATCH 3/4] RFC drm/i915: Switch to kernel context before idling at runtime

[Chris Wilson]

We can reduce our exposure to random neutrinos by resting on the kernel
context having flushed out the user contexts to system memory and
beyond. The corollary is that we then we require two passes through the
idle handler to go to sleep, which on a truly idle system involves an
extra pass through the slow and irregular retire work handler.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03874b50ada9..a81aa124af26 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3504,6 +3504,18 @@ i915_gem_idle_work_handler(struct work_struct *work)
if (!READ_ONCE(dev_priv->gt.awake))
return;
 
+   /*
+* Flush out the last user context, leaving only the pinned
+* kernel context resident. When we are idling on the kernel_context,
+* no more new requests (with a context switch) are emitted and we
+* can finally rest. A consequence is that the idle work handler is
+* always called at least twice before idling (and if the system is
+* idle that implies a round trip through the retire worker).
+*/
+   mutex_lock(_priv->drm.struct_mutex);
+   i915_gem_switch_to_kernel_context(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
/*
 * Wait for last execlists context complete, but bail out in case a
 * new request is submitted. As we don't trust the hardware, we
@@ -4958,7 +4970,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 
assert_kernel_context_is_current(dev_priv);
}
-   i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
intel_uc_suspend(dev_priv);
-- 
2.17.0

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[Intel-gfx] [PATCH 2/4] drm/i915: Special case kernel_context switch request

[Chris Wilson]

From: Mika Kuoppala 

When checking if engine is idling on a kernel context,
the last request emitted to it could have been the exact
request to switch into kernel context.

Do not bail out early even if engine has requests,
if the last request was for kernel context.

Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
timelines")
Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..3fe1212b0f7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -595,7 +595,10 @@ static bool engine_has_idle_kernel_context(struct 
intel_engine_cs *engine)
lockdep_assert_held(>i915->drm.struct_mutex);
 
list_for_each_entry(ring, active_rings, active_link) {
-   if (last_request_on_engine(ring->timeline, engine))
+   struct i915_request *rq =
+   last_request_on_engine(ring->timeline, engine);
+
+   if (rq && rq->gem_context != engine->i915->kernel_context)
return false;
}
 
-- 
2.17.0

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[Intel-gfx] [PATCH 1/4] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

v2: Compile cleanup

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 47 ++---
 1 file changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..a0beabd49f62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,12 +1553,30 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
-   int error;
 
/* ignore lid events during suspend */
mutex_lock(_priv->modeset_restore_lock);
@@ -1575,13 +1593,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -1609,10 +1620,9 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_csr_ucode_suspend(dev_priv);
 
-out:
enable_rpm_wakeref_asserts(dev_priv);
 
-   return error;
+   return 0;
 }
 
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
@@ -2081,6 +2091,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2731,6 +2757,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

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Re: [Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

[Chris Wilson]

Quoting Chris Wilson (2018-05-22 16:08:30)
> During suspend we want to flush out all active contexts and their
> rendering. To do so we queue a request from the kernel's context, once
> we know that request is done, we know the GPU is completely idle. To
> speed up that switch bump the GPU clocks.
> 
> Switching to the kernel context prior to idling is also used to enforce
> a barrier before changing OA properties, and when evicting active
> rendering from the global GTT. All cases where we do want to
> race-to-idle.
> 
> v2: Limit the boosting to only the switch before suspend.
> 
> Signed-off-by: Chris Wilson 
> Cc: David Weinehall 
> Cc: Mika Kuoppala 
> Reviewed-by: Mika Kuoppala  #v1
> Tested-by: David Weinehall  #v1
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 11 ++-
>  drivers/gpu/drm/i915/i915_gem_context.c | 15 ++-
>  drivers/gpu/drm/i915/i915_gem_context.h |  4 +++-
>  drivers/gpu/drm/i915/i915_gem_evict.c   |  2 +-
>  4 files changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a81aa124af26..37a6c9ec5d60 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3513,7 +3513,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
>  * idle that implies a round trip through the retire worker).
>  */
> mutex_lock(_priv->drm.struct_mutex);
> -   i915_gem_switch_to_kernel_context(dev_priv);
> +   i915_gem_switch_to_kernel_context(dev_priv, 0);
> mutex_unlock(_priv->drm.struct_mutex);
>  
> /*
> @@ -4958,7 +4958,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
>  * not rely on its state.
>  */
> if (!i915_terminally_wedged(_priv->gpu_error)) {
> -   ret = i915_gem_switch_to_kernel_context(dev_priv);
> +   ret = i915_gem_switch_to_kernel_context(dev_priv,
> +   I915_SWITCH_BOOST);
> if (ret)
> goto err_unlock;
>  
> @@ -5043,7 +5044,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> intel_uc_resume(i915);
>  
> /* Always reload a context for powersaving. */
> -   if (i915_gem_switch_to_kernel_context(i915))
> +   if (i915_gem_switch_to_kernel_context(i915, 0))
> goto err_wedged;
>  
>  out_unlock:
> @@ -5238,7 +5239,7 @@ static int __intel_engines_record_defaults(struct 
> drm_i915_private *i915)
> goto err_active;
> }
>  
> -   err = i915_gem_switch_to_kernel_context(i915);
> +   err = i915_gem_switch_to_kernel_context(i915, 0);
> if (err)
> goto err_active;
>  
> @@ -5304,7 +5305,7 @@ static int __intel_engines_record_defaults(struct 
> drm_i915_private *i915)
>  * request, ensure we are pointing at the kernel context and
>  * then remove it.
>  */
> -   if (WARN_ON(i915_gem_switch_to_kernel_context(i915)))
> +   if (WARN_ON(i915_gem_switch_to_kernel_context(i915, 0)))
> goto out_ctx;
>  
> if (WARN_ON(i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED)))
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 3fe1212b0f7e..dce1a3d9f5e6 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -605,7 +605,8 @@ static bool engine_has_idle_kernel_context(struct 
> intel_engine_cs *engine)
> return intel_engine_has_kernel_context(engine);
>  }
>  
> -int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915)
> +int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
> + unsigned int flags)
>  {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> @@ -636,6 +637,18 @@ int i915_gem_switch_to_kernel_context(struct 
> drm_i915_private *i915)
>  
> I915_FENCE_GFP);
> }
>  
> +   /*
> +* "Race-to-idle".
> +*
> +* Switching to the kernel context is often used a synchronous
> +* step prior to idling, e.g. in suspend for flushing all
> +* current operations to memory before sleeping. These we
> +* want to complete as quickly as possible to avoid prolonged
> +* stalls, so allow the gpu to boost to maximum clocks.
> +*/
> +   if (flags & I915_SWITCH_BOOST)
> +   gen6_rps_boost(rq, NULL);
> +

Hmm, I thinking that adding this bit to wait_for_idle works better with
the parking to kernel context on idling. As after that patch, we are
less 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prepare GEM for suspend earlier (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare GEM for suspend earlier (rev2)
URL   : https://patchwork.freedesktop.org/series/43575/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9084 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9084 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9084, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43575/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9084:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9084 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
  fi-skl-guc: PASS -> FAIL (fdo#103191, fdo#104724)


 Possible fixes 

igt@kms_flip@basic-flip-vs-dpms:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cfl-s3:  FAIL (fdo#103481) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4221 -> Patchwork_9084

  CI_DRM_4221: d83aef98e4f2e35440222c69ef80a68daf1abb4e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9084: bb7d49da39829da247536185aebd4b47870b68c0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9084/build_32bit.log

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_query.o
In file included from ./include/asm-generic/barrier.h:20:0,
 from ./arch/x86/include/asm/barrier.h:86,
 from ./include/linux/nospec.h:8,
 from drivers/gpu/drm/i915/i915_query.c:7:
drivers/gpu/drm/i915/i915_query.c: In function ‘i915_query_ioctl’:
./include/linux/compiler.h:339:38: error: call to ‘__compiletime_assert_119’ 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
./include/linux/compiler.h:319:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^~
./include/linux/compiler.h:339:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^~~
./include/linux/build_bug.h:45:37: note: in expansion of macro 
‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^~
./include/linux/build_bug.h:69:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^~~~
./include/linux/nospec.h:53:2: note: in expansion of macro ‘BUILD_BUG_ON’
  BUILD_BUG_ON(sizeof(_i) > sizeof(long));   \
  ^~~~
drivers/gpu/drm/i915/i915_query.c:118:15: note: in expansion of macro 
‘array_index_nospec’
func_idx = array_index_nospec(func_idx,
   ^~
scripts/Makefile.build:312: recipe for target 
'drivers/gpu/drm/i915/i915_query.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_query.o] Error 1
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2


== Linux commits ==

bb7d49da3982 

[Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

[Chris Wilson]

During suspend we want to flush out all active contexts and their
rendering. To do so we queue a request from the kernel's context, once
we know that request is done, we know the GPU is completely idle. To
speed up that switch bump the GPU clocks.

Switching to the kernel context prior to idling is also used to enforce
a barrier before changing OA properties, and when evicting active
rendering from the global GTT. All cases where we do want to
race-to-idle.

v2: Limit the boosting to only the switch before suspend.

Signed-off-by: Chris Wilson 
Cc: David Weinehall 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala  #v1
Tested-by: David Weinehall  #v1
---
 drivers/gpu/drm/i915/i915_gem.c | 11 ++-
 drivers/gpu/drm/i915/i915_gem_context.c | 15 ++-
 drivers/gpu/drm/i915/i915_gem_context.h |  4 +++-
 drivers/gpu/drm/i915/i915_gem_evict.c   |  2 +-
 4 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a81aa124af26..37a6c9ec5d60 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3513,7 +3513,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
 * idle that implies a round trip through the retire worker).
 */
mutex_lock(_priv->drm.struct_mutex);
-   i915_gem_switch_to_kernel_context(dev_priv);
+   i915_gem_switch_to_kernel_context(dev_priv, 0);
mutex_unlock(_priv->drm.struct_mutex);
 
/*
@@ -4958,7 +4958,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * not rely on its state.
 */
if (!i915_terminally_wedged(_priv->gpu_error)) {
-   ret = i915_gem_switch_to_kernel_context(dev_priv);
+   ret = i915_gem_switch_to_kernel_context(dev_priv,
+   I915_SWITCH_BOOST);
if (ret)
goto err_unlock;
 
@@ -5043,7 +5044,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
intel_uc_resume(i915);
 
/* Always reload a context for powersaving. */
-   if (i915_gem_switch_to_kernel_context(i915))
+   if (i915_gem_switch_to_kernel_context(i915, 0))
goto err_wedged;
 
 out_unlock:
@@ -5238,7 +5239,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto err_active;
}
 
-   err = i915_gem_switch_to_kernel_context(i915);
+   err = i915_gem_switch_to_kernel_context(i915, 0);
if (err)
goto err_active;
 
@@ -5304,7 +5305,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
 * request, ensure we are pointing at the kernel context and
 * then remove it.
 */
-   if (WARN_ON(i915_gem_switch_to_kernel_context(i915)))
+   if (WARN_ON(i915_gem_switch_to_kernel_context(i915, 0)))
goto out_ctx;
 
if (WARN_ON(i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED)))
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3fe1212b0f7e..dce1a3d9f5e6 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -605,7 +605,8 @@ static bool engine_has_idle_kernel_context(struct 
intel_engine_cs *engine)
return intel_engine_has_kernel_context(engine);
 }
 
-int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915)
+int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
+ unsigned int flags)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -636,6 +637,18 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *i915)
 
I915_FENCE_GFP);
}
 
+   /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+   if (flags & I915_SWITCH_BOOST)
+   gen6_rps_boost(rq, NULL);
+
/*
 * Force a flush after the switch to ensure that all rendering
 * and operations prior to switching to the kernel context hits
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index c3262b4dd2ee..9d9140fa91ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ 

[Intel-gfx] [PATCH 2/4] drm/i915: Special case kernel_context switch request

[Chris Wilson]

From: Mika Kuoppala 

When checking if engine is idling on a kernel context,
the last request emitted to it could have been the exact
request to switch into kernel context.

Do not bail out early even if engine has requests,
if the last request was for kernel context.

Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
timelines")
Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..3fe1212b0f7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -595,7 +595,10 @@ static bool engine_has_idle_kernel_context(struct 
intel_engine_cs *engine)
lockdep_assert_held(>i915->drm.struct_mutex);
 
list_for_each_entry(ring, active_rings, active_link) {
-   if (last_request_on_engine(ring->timeline, engine))
+   struct i915_request *rq =
+   last_request_on_engine(ring->timeline, engine);
+
+   if (rq && rq->gem_context != engine->i915->kernel_context)
return false;
}
 
-- 
2.17.0

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[Intel-gfx] [PATCH 3/4] RFC drm/i915: Switch to kernel context before idling at runtime

[Chris Wilson]

We can reduce our exposure to random neutrinos by resting on the kernel
context having flushed out the user contexts to system memory and
beyond. The corollary is that we then we require two passes through the
idle handler to go to sleep, which on a truly idle system involves an
extra pass through the slow and irregular retire work handler.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03874b50ada9..a81aa124af26 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3504,6 +3504,18 @@ i915_gem_idle_work_handler(struct work_struct *work)
if (!READ_ONCE(dev_priv->gt.awake))
return;
 
+   /*
+* Flush out the last user context, leaving only the pinned
+* kernel context resident. When we are idling on the kernel_context,
+* no more new requests (with a context switch) are emitted and we
+* can finally rest. A consequence is that the idle work handler is
+* always called at least twice before idling (and if the system is
+* idle that implies a round trip through the retire worker).
+*/
+   mutex_lock(_priv->drm.struct_mutex);
+   i915_gem_switch_to_kernel_context(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
/*
 * Wait for last execlists context complete, but bail out in case a
 * new request is submitted. As we don't trust the hardware, we
@@ -4958,7 +4970,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 
assert_kernel_context_is_current(dev_priv);
}
-   i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
intel_uc_suspend(dev_priv);
-- 
2.17.0

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[Intel-gfx] [PATCH 1/4] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

v2: Compile cleanup

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 47 ++---
 1 file changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..a0beabd49f62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,12 +1553,30 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
-   int error;
 
/* ignore lid events during suspend */
mutex_lock(_priv->modeset_restore_lock);
@@ -1575,13 +1593,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -1609,10 +1620,9 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_csr_ucode_suspend(dev_priv);
 
-out:
enable_rpm_wakeref_asserts(dev_priv);
 
-   return error;
+   return 0;
 }
 
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
@@ -2081,6 +2091,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2731,6 +2757,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

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Re: [Intel-gfx] [PATCH v3] drm/i915/gen11: Preempt-to-idle support in execlists.

[Lis, Tomasz]

On 2018-05-22 16:39, Ceraolo Spurio, Daniele wrote:



On 5/21/2018 3:16 AM, Lis, Tomasz wrote:



On 2018-05-18 23:08, Daniele Ceraolo Spurio wrote:



On 11/05/18 08:45, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a 
proper
bit within Execlist Control Register, and receiving preemption 
result from

Context Status Buffer.

Preemption in previous gens required a special batch buffer to be 
executed,
so the Command Streamer never preempted to idle directly. In 
Icelake it is

possible, as there is a hardware mechanism to inform the kernel about
status of the preemption request.

This patch does not cover using the new preemption mechanism when 
GuC is

active.

v2: Added needs_preempt_context() change so that it is not created 
when

 preempt-to-idle is supported. (Chris)
 Updated setting HWACK flag so that it is cleared after
 preempt-to-dle. (Chris, Daniele)
 Updated to use I915_ENGINE_HAS_PREEMPTION flag. (Chris)

v3: Fixed needs_preempt_context() change. (Chris)
 Merged preemption trigger functions to one. (Chris)
 Fixed context state to not assume COMPLETED_MASK after 
preemption,

 since idle-to-idle case will not have it set.

Bspec: 18922
Signed-off-by: Tomasz Lis 
---
  drivers/gpu/drm/i915/i915_drv.h  |   2 +
  drivers/gpu/drm/i915/i915_gem_context.c  |   5 +-
  drivers/gpu/drm/i915/i915_pci.c  |   3 +-
  drivers/gpu/drm/i915/intel_device_info.h |   1 +
  drivers/gpu/drm/i915/intel_lrc.c | 115 
++-

  drivers/gpu/drm/i915/intel_lrc.h |   1 +
  6 files changed, 92 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h

index 57fb3aa..6e9647b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2535,6 +2535,8 @@ intel_info(const struct drm_i915_private 
*dev_priv)

  ((dev_priv)->info.has_logical_ring_elsq)
  #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
  ((dev_priv)->info.has_logical_ring_preemption)
+#define HAS_HW_PREEMPT_TO_IDLE(dev_priv) \
+    ((dev_priv)->info.has_hw_preempt_to_idle)
    #define HAS_EXECLISTS(dev_priv) 
HAS_LOGICAL_RING_CONTEXTS(dev_priv)
  diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c

index 33f8a4b..bdac129 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -454,7 +454,10 @@ destroy_kernel_context(struct i915_gem_context 
**ctxp)

    static bool needs_preempt_context(struct drm_i915_private *i915)
  {
-    return HAS_LOGICAL_RING_PREEMPTION(i915);
+    return HAS_LOGICAL_RING_PREEMPTION(i915) &&
+   (!HAS_HW_PREEMPT_TO_IDLE(i915) ||
+    (HAS_HW_PREEMPT_TO_IDLE(i915) &&
+    !USES_GUC_SUBMISSION(i915)));


Why do we keep the preempt context for !USES_GUC_SUBMISSION(i915) 
even if HAS_HW_PREEMPT_TO_IDLE(i915)? After this patch we shouldn't 
need it anymore, right?
The patch only provides gen11 way for the non-GuC submission. This is 
why the condition is so convoluted - preempt_context is still needed 
if we use GuC.

This will be simplified after GuC paches are added.


mmm I think this check is the other way around because it returns true 
when HAS_HW_PREEMPT_TO_IDLE for !USES_GUC_SUBMISSION, so when GuC is 
not in use.

Yes, agreed. USES_GUC_SUBMISSION should not be negated.
BTW, GuC does not support using the preempt context on platforms that 
have HW supported preempt-to-idle, so there is no need to keep the 
preempt context around for GuC.
Oh, I did not knew that. So the preemption is completely disabled on 
gen11 with GuC then? (because patches for gen11 preempt-to-idle are not 
upstreamed)?



  }
    int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c 
b/drivers/gpu/drm/i915/i915_pci.c

index 4364922..66b6700 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,7 +595,8 @@ static const struct intel_device_info 
intel_cannonlake_info = {

  GEN(11), \
  .ddb_size = 2048, \
  .has_csr = 0, \
-    .has_logical_ring_elsq = 1
+    .has_logical_ring_elsq = 1, \
+    .has_hw_preempt_to_idle = 1
    static const struct intel_device_info intel_icelake_11_info = {
  GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h

index 933e316..4eb97b5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -98,6 +98,7 @@ enum intel_platform {
  func(has_logical_ring_contexts); \
  func(has_logical_ring_elsq); \
  func(has_logical_ring_preemption); \
+    func(has_hw_preempt_to_idle); \
  func(has_overlay); \
  func(has_pooled_eu); \
  func(has_psr); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
b/drivers/gpu/drm/i915/intel_lrc.c

index 29dcf34..8fe6795 100644
--- 

[Intel-gfx] [PATCH 3/3] RFC drm/i915: Switch to kernel context before idling at runtime

[Chris Wilson]

We can reduce our exposure to random neutrinos by resting on the kernel
context having flushed out the user contexts to system memory and
beyond. The corollary is that we then we require two passes through the
idle handler to go to sleep, which on a truly idle system involves an
extra pass through the slow and irregular retire work handler.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03874b50ada9..a81aa124af26 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3504,6 +3504,18 @@ i915_gem_idle_work_handler(struct work_struct *work)
if (!READ_ONCE(dev_priv->gt.awake))
return;
 
+   /*
+* Flush out the last user context, leaving only the pinned
+* kernel context resident. When we are idling on the kernel_context,
+* no more new requests (with a context switch) are emitted and we
+* can finally rest. A consequence is that the idle work handler is
+* always called at least twice before idling (and if the system is
+* idle that implies a round trip through the retire worker).
+*/
+   mutex_lock(_priv->drm.struct_mutex);
+   i915_gem_switch_to_kernel_context(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
/*
 * Wait for last execlists context complete, but bail out in case a
 * new request is submitted. As we don't trust the hardware, we
@@ -4958,7 +4970,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 
assert_kernel_context_is_current(dev_priv);
}
-   i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
intel_uc_suspend(dev_priv);
-- 
2.17.0

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[Intel-gfx] [PATCH 1/3] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

v2: Compile cleanup

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 47 ++---
 1 file changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..a0beabd49f62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,12 +1553,30 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
-   int error;
 
/* ignore lid events during suspend */
mutex_lock(_priv->modeset_restore_lock);
@@ -1575,13 +1593,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -1609,10 +1620,9 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_csr_ucode_suspend(dev_priv);
 
-out:
enable_rpm_wakeref_asserts(dev_priv);
 
-   return error;
+   return 0;
 }
 
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
@@ -2081,6 +2091,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2731,6 +2757,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

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[Intel-gfx] [PATCH 2/3] drm/i915: Special case kernel_context switch request

[Chris Wilson]

From: Mika Kuoppala 

When checking if engine is idling on a kernel context,
the last request emitted to it could have been the exact
request to switch into kernel context.

Do not bail out early even if engine has requests,
if the last request was for kernel context.

Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
timelines")
Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..3fe1212b0f7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -595,7 +595,10 @@ static bool engine_has_idle_kernel_context(struct 
intel_engine_cs *engine)
lockdep_assert_held(>i915->drm.struct_mutex);
 
list_for_each_entry(ring, active_rings, active_link) {
-   if (last_request_on_engine(ring->timeline, engine))
+   struct i915_request *rq =
+   last_request_on_engine(ring->timeline, engine);
+
+   if (rq && rq->gem_context != engine->i915->kernel_context)
return false;
}
 
-- 
2.17.0

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Re: [Intel-gfx] [PATCH v2] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

Quoting Chris Wilson (2018-05-22 15:35:34)
> In order to prepare the GPU for sleeping, we may want to submit commands
> to it. This is a complicated process that may even require some swapping
> in from shmemfs, if the GPU was in the wrong state. As such, we need to
> do this preparation step synchronously before the rest of the system has
> started to turn off (e.g. swapin fails if scsi is suspended).
> Fortunately, we are provided with a such a hook, pm_ops.prepare().

Now, this problem would also be solved by 
RFC drm/i915: Switch to kernel context before idling at runtime
as with that patch, we would be sure to already be on the kernel context
before we unpin the state and so not need to issue the request to
switch.

But I think there is a wider problem this solves for us by making sure
the backing store is still accessible while we finish off user
operations. Otherwise with the async suspend, it does seem like we might
find ourselves unable to flush buffers to disk.
-Chris
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Re: [Intel-gfx] [PATCH v3] drm/i915/gen11: Preempt-to-idle support in execlists.

[Ceraolo Spurio, Daniele]

On 5/21/2018 3:16 AM, Lis, Tomasz wrote:



On 2018-05-18 23:08, Daniele Ceraolo Spurio wrote:



On 11/05/18 08:45, Tomasz Lis wrote:

The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result 
from

Context Status Buffer.

Preemption in previous gens required a special batch buffer to be 
executed,
so the Command Streamer never preempted to idle directly. In Icelake 
it is

possible, as there is a hardware mechanism to inform the kernel about
status of the preemption request.

This patch does not cover using the new preemption mechanism when GuC is
active.

v2: Added needs_preempt_context() change so that it is not created when
 preempt-to-idle is supported. (Chris)
 Updated setting HWACK flag so that it is cleared after
 preempt-to-dle. (Chris, Daniele)
 Updated to use I915_ENGINE_HAS_PREEMPTION flag. (Chris)

v3: Fixed needs_preempt_context() change. (Chris)
 Merged preemption trigger functions to one. (Chris)
 Fixed context state to not assume COMPLETED_MASK after preemption,
 since idle-to-idle case will not have it set.

Bspec: 18922
Signed-off-by: Tomasz Lis 
---
  drivers/gpu/drm/i915/i915_drv.h  |   2 +
  drivers/gpu/drm/i915/i915_gem_context.c  |   5 +-
  drivers/gpu/drm/i915/i915_pci.c  |   3 +-
  drivers/gpu/drm/i915/intel_device_info.h |   1 +
  drivers/gpu/drm/i915/intel_lrc.c | 115 
++-

  drivers/gpu/drm/i915/intel_lrc.h |   1 +
  6 files changed, 92 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h

index 57fb3aa..6e9647b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2535,6 +2535,8 @@ intel_info(const struct drm_i915_private 
*dev_priv)

  ((dev_priv)->info.has_logical_ring_elsq)
  #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
  ((dev_priv)->info.has_logical_ring_preemption)
+#define HAS_HW_PREEMPT_TO_IDLE(dev_priv) \
+    ((dev_priv)->info.has_hw_preempt_to_idle)
    #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
  diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c

index 33f8a4b..bdac129 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -454,7 +454,10 @@ destroy_kernel_context(struct i915_gem_context 
**ctxp)

    static bool needs_preempt_context(struct drm_i915_private *i915)
  {
-    return HAS_LOGICAL_RING_PREEMPTION(i915);
+    return HAS_LOGICAL_RING_PREEMPTION(i915) &&
+   (!HAS_HW_PREEMPT_TO_IDLE(i915) ||
+    (HAS_HW_PREEMPT_TO_IDLE(i915) &&
+    !USES_GUC_SUBMISSION(i915)));


Why do we keep the preempt context for !USES_GUC_SUBMISSION(i915) even 
if HAS_HW_PREEMPT_TO_IDLE(i915)? After this patch we shouldn't need it 
anymore, right?
The patch only provides gen11 way for the non-GuC submission. This is 
why the condition is so convoluted - preempt_context is still needed if 
we use GuC.

This will be simplified after GuC paches are added.


mmm I think this check is the other way around because it returns true 
when HAS_HW_PREEMPT_TO_IDLE for !USES_GUC_SUBMISSION, so when GuC is not 
in use. BTW, GuC does not support using the preempt context on platforms 
that have HW supported preempt-to-idle, so there is no need to keep the 
preempt context around for GuC.





  }
    int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c 
b/drivers/gpu/drm/i915/i915_pci.c

index 4364922..66b6700 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,7 +595,8 @@ static const struct intel_device_info 
intel_cannonlake_info = {

  GEN(11), \
  .ddb_size = 2048, \
  .has_csr = 0, \
-    .has_logical_ring_elsq = 1
+    .has_logical_ring_elsq = 1, \
+    .has_hw_preempt_to_idle = 1
    static const struct intel_device_info intel_icelake_11_info = {
  GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h

index 933e316..4eb97b5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -98,6 +98,7 @@ enum intel_platform {
  func(has_logical_ring_contexts); \
  func(has_logical_ring_elsq); \
  func(has_logical_ring_preemption); \
+    func(has_hw_preempt_to_idle); \
  func(has_overlay); \
  func(has_pooled_eu); \
  func(has_psr); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
b/drivers/gpu/drm/i915/intel_lrc.c

index 29dcf34..8fe6795 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,6 +154,7 @@
  #define GEN8_CTX_STATUS_ACTIVE_IDLE    (1 << 3)
  #define GEN8_CTX_STATUS_COMPLETE    (1 << 4)
  #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
+#define 

Re: [Intel-gfx] [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2

[Tarun Vyas]

On Fri, May 11, 2018 at 12:51:45PM -0700, Dhinakaran Pandiyan wrote:
> While touching the code around this, I noticed that absence of ALPM
> capability does not stop us from enabling PSR2. But, the spec
> unambiguously states that ALPM is required for PSR2 and so does this
> commit that introduced this code
> 
> drm/i915/psr: enable ALPM for psr2
> 
> As per edp1.4 spec , alpm is required for psr2 operation as it's
> used for all psr2  main link power down management and alpm enable
> bit must be set for psr2 operation.
>
Since, the code introduced by "drm/i915/psr: enable ALPM for psr2" enables PSR2 
even if ALPM isn't supported, can we add the "Fixes" tag here ? Rest looks good.

Reviewed-by: Tarun Vyas  
> Cc: Jose Roberto de Souza 
> Cc: Vathsala Nagaraju 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 20 ++--
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index b4a4f5d3a2bb..92abf61e234c 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -254,6 +254,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  
>   if (INTEL_GEN(dev_priv) >= 9 &&
>   (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> + bool y_req = intel_dp->psr_dpcd[1] &
> +  DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + bool alpm = intel_dp_get_alpm_status(intel_dp);
> +
>   /*
>* All panels that supports PSR version 03h (PSR2 +
>* Y-coordinate) can handle Y-coordinates in VSC but we are
> @@ -265,16 +269,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>* Y-coordinate requirement panels we would need to enable
>* GTC first.
>*/
> - dev_priv->psr.sink_psr2_support =
> - intel_dp->psr_dpcd[1] & 
> DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> + dev_priv->psr.sink_psr2_support = y_req && alpm;
>   DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
>  
>   if (dev_priv->psr.sink_psr2_support) {
>   dev_priv->psr.colorimetry_support =
>   intel_dp_get_colorimetry_status(intel_dp);
> - dev_priv->psr.alpm =
> - intel_dp_get_alpm_status(intel_dp);
>   dev_priv->psr.sink_sync_latency =
>   intel_dp_get_sink_sync_latency(intel_dp);
>   }
> @@ -386,13 +387,12 @@ static void hsw_psr_enable_sink(struct intel_dp 
> *intel_dp)
>   u8 dpcd_val = DP_PSR_ENABLE;
>  
>   /* Enable ALPM at sink for psr2 */
> - if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
> - drm_dp_dpcd_writeb(_dp->aux,
> - DP_RECEIVER_ALPM_CONFIG,
> - DP_ALPM_ENABLE);
> -
> - if (dev_priv->psr.psr2_enabled)
> + if (dev_priv->psr.psr2_enabled) {
> + drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> +DP_ALPM_ENABLE);
>   dpcd_val |= DP_PSR_ENABLE_PSR2;
> + }
> +
>   if (dev_priv->psr.link_standby)
>   dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> -- 
> 2.14.1
> 
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[Intel-gfx] [PATCH v2] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

v2: Compile cleanup

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 47 ++---
 1 file changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..a0beabd49f62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,12 +1553,30 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
-   int error;
 
/* ignore lid events during suspend */
mutex_lock(_priv->modeset_restore_lock);
@@ -1575,13 +1593,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -1609,10 +1620,9 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_csr_ucode_suspend(dev_priv);
 
-out:
enable_rpm_wakeref_asserts(dev_priv);
 
-   return error;
+   return 0;
 }
 
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
@@ -2081,6 +2091,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2731,6 +2757,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Prepare GEM for suspend earlier

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare GEM for suspend earlier
URL   : https://patchwork.freedesktop.org/series/43575/
State : failure

== Summary ==

CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_drv.o
drivers/gpu/drm/i915/i915_drv.c: In function ‘i915_drm_suspend’:
drivers/gpu/drm/i915/i915_drv.c:1624:1: error: label ‘out’ defined but not used 
[-Werror=unused-label]
 out:
 ^~~
drivers/gpu/drm/i915/i915_drv.c:1627:9: error: ‘error’ is used uninitialized in 
this function [-Werror=uninitialized]
  return error;
 ^
cc1: all warnings being treated as errors
scripts/Makefile.build:312: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' 
failed
make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

___
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[Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

[Chris Wilson]

In order to prepare the GPU for sleeping, we may want to submit commands
to it. This is a complicated process that may even require some swapping
in from shmemfs, if the GPU was in the wrong state. As such, we need to
do this preparation step synchronously before the rest of the system has
started to turn off (e.g. swapin fails if scsi is suspended).
Fortunately, we are provided with a such a hook, pm_ops.prepare().

Testcase: igt/drv_suspend after igt/gem_tiled_swapping
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 43 +++--
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c449b8d8eab..256642fb8315 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1553,6 +1553,25 @@ static bool suspend_to_idle(struct drm_i915_private 
*dev_priv)
return false;
 }
 
+static int i915_drm_prepare(struct drm_device *dev)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   int err;
+
+   disable_rpm_wakeref_asserts(i915);
+
+   err = i915_gem_suspend(i915);
+   if (err) {
+   dev_err(>drm.pdev->dev,
+   "GEM idle failed, suspend/resume might fail\n");
+   goto out;
+   }
+out:
+   enable_rpm_wakeref_asserts(i915);
+
+   return err;
+}
+
 static int i915_drm_suspend(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1575,13 +1594,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev_priv);
-   if (error) {
-   dev_err(>dev,
-   "GEM idle failed, resume might fail\n");
-   goto out;
-   }
-
intel_display_suspend(dev);
 
intel_dp_mst_suspend(dev);
@@ -2081,6 +2093,22 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
return ret;
 }
 
+static int i915_pm_prepare(struct device *kdev)
+{
+   struct pci_dev *pdev = to_pci_dev(kdev);
+   struct drm_device *dev = pci_get_drvdata(pdev);
+
+   if (!dev) {
+   dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+   return -ENODEV;
+   }
+
+   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+   return 0;
+
+   return i915_drm_prepare(dev);
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
@@ -2731,6 +2759,7 @@ const struct dev_pm_ops i915_pm_ops = {
 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
 * PMSG_RESUME]
 */
+   .prepare = i915_pm_prepare,
.suspend = i915_pm_suspend,
.suspend_late = i915_pm_suspend_late,
.resume_early = i915_pm_resume_early,
-- 
2.17.0

___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: vbt change for psr (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev9)
URL   : https://patchwork.freedesktop.org/series/41289/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4218_full -> Patchwork_9077_full =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/9/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9077_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_eio@in-flight-contexts-1us:
  shard-glk:  PASS -> FAIL (fdo#105954)

igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#106509)

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-apl:  DMESG-FAIL (fdo#106560) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
  shard-hsw:  FAIL (fdo#103928) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#102887) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip@plain-flip-ts-check:
  shard-hsw:  FAIL (fdo#100368) -> PASS
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
  shard-glk:  FAIL (fdo#104724, fdo#103167) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105954 https://bugs.freedesktop.org/show_bug.cgi?id=105954
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560


== Participating hosts (9 -> 8) ==

  Missing(1): shard-kbl 


== Build changes ==

* Linux: CI_DRM_4218 -> Patchwork_9077

  CI_DRM_4218: df2fa6a1766287fc138a6088c48c306191edaf01 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9077: 09cb51f7d1d0561b76e4e5a8decb483b1a364557 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9077/shards.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Special case kernel_context switch request

[Patchwork]

== Series Details ==

Series: drm/i915: Special case kernel_context switch request
URL   : https://patchwork.freedesktop.org/series/43572/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4221 -> Patchwork_9082 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9082 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9082, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43572/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9082:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-reload:
  fi-ilk-650: PASS -> DMESG-WARN


== Known issues ==

  Here are the changes found in Patchwork_9082 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-skl-6770hq:  PASS -> FAIL (fdo#100368, fdo#103928)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-skl-6700k2:  PASS -> FAIL (fdo#104724, fdo#103191)


 Possible fixes 

igt@kms_flip@basic-flip-vs-dpms:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cfl-s3:  FAIL (fdo#103481) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4221 -> Patchwork_9082

  CI_DRM_4221: d83aef98e4f2e35440222c69ef80a68daf1abb4e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9082: 39378c31a4723a75c807c46f5812cf94964daffb @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9082/build_32bit.log

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_query.o
In file included from ./include/asm-generic/barrier.h:20:0,
 from ./arch/x86/include/asm/barrier.h:86,
 from ./include/linux/nospec.h:8,
 from drivers/gpu/drm/i915/i915_query.c:7:
drivers/gpu/drm/i915/i915_query.c: In function ‘i915_query_ioctl’:
./include/linux/compiler.h:339:38: error: call to ‘__compiletime_assert_119’ 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
./include/linux/compiler.h:319:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^~
./include/linux/compiler.h:339:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^~~
./include/linux/build_bug.h:45:37: note: in expansion of macro 
‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^~
./include/linux/build_bug.h:69:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^~~~
./include/linux/nospec.h:53:2: note: in expansion of macro ‘BUILD_BUG_ON’
  BUILD_BUG_ON(sizeof(_i) > sizeof(long));   \
  ^~~~
drivers/gpu/drm/i915/i915_query.c:118:15: note: in expansion of macro 
‘array_index_nospec’
func_idx = array_index_nospec(func_idx,
   ^~
scripts/Makefile.build:312: recipe for target 
'drivers/gpu/drm/i915/i915_query.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_query.o] Error 1
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:559: recipe for target 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr : Add psr1 live status (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/psr : Add psr1 live status (rev3)
URL   : https://patchwork.freedesktop.org/series/42021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4218_full -> Patchwork_9076_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9076_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9076_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42021/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9076_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS

igt@gem_mocs_settings@mocs-rc6-blt:
  shard-kbl:  PASS -> SKIP +1


== Known issues ==

  Here are the changes found in Patchwork_9076_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#106509)

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_vblank@pipe-c-ts-continuation-idle-hang:
  shard-apl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +10


 Possible fixes 

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
  shard-hsw:  FAIL (fdo#103928) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#102887) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip@plain-flip-ts-check:
  shard-hsw:  FAIL (fdo#100368) -> PASS
  shard-glk:  FAIL (fdo#100368) -> PASS +1


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4218 -> Patchwork_9076

  CI_DRM_4218: df2fa6a1766287fc138a6088c48c306191edaf01 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9076: 66eb3f2aeb66300f5586170ae85e2b5d1e46c5ad @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9076/shards.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Per-context and per-client engine busyness (rev6)

[Patchwork]

== Series Details ==

Series: Per-context and per-client engine busyness (rev6)
URL   : https://patchwork.freedesktop.org/series/32645/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4220 -> Patchwork_9081 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/32645/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9081:

  === IGT changes ===

 Possible regressions 

igt@gem_exec_suspend@basic-s3:
  {fi-cfl-guc}:   PASS -> FAIL +1


== Known issues ==

  Here are the changes found in Patchwork_9081 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@gem_mmap_gtt@basic-wc:
  fi-cnl-y3:  INCOMPLETE (fdo#105086) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086


== Participating hosts (44 -> 38) ==

  Missing(6): fi-ilk-m540 fi-bxt-dsi fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4220 -> Patchwork_9081

  CI_DRM_4220: 9d7ce3ad8801a95461ad4fb63bd5374dfc2dff55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9081: 2eefca086175319a176f44264df4751784fdbb3b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9081/build_32bit.log

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_gem_context.o
scripts/Makefile.build:312: recipe for target 
'drivers/gpu/drm/i915/i915_gem_context.o' failed
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed
scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed
scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed
Makefile:1060: recipe for target 'drivers' failed


== Linux commits ==

2eefca086175 drm/i915: Allow clients to query own per-engine busyness
3bcb2a77339a drm/i915: Add sysfs toggle to enable per-client engine stats
8ddf5537f960 drm/i915: Expose per-engine client busyness
5a863a6a533e drm/i915: Update client name on context create
153d8b61ac31 drm/i915: Expose list of clients in sysfs
c51fae7085a5 drm/i915: Track per-context engine busyness
312445e65040 drm/i915: Move intel_engine_context_in/out into intel_lrc.c
89c9c183360d drm/i915: Forward declare struct intel_context
e39413c3a24f drm/i915: Include i915_scheduler.h from i915_gem_context.h
7817526ffcfb drm/i915: Store engine backpointer in the intel_context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9081/issues.html
___
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Re: [Intel-gfx] [RFC 04/10] drm/i915: Move intel_engine_context_in/out into intel_lrc.c

[Tvrtko Ursulin]

On 22/05/2018 13:46, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-22 13:30:14)

From: Tvrtko Ursulin 

Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.

Signed-off-by: Tvrtko Ursulin 


Expectation was that we would be using these in guc. Brief highlight of
how the plan changed?


"Let's postpone the disaster" ? :) I am talking about header file 
ordering disaster, not GuC, so someone doesn't get me wrong.


But in actuality, since we have postponed GuC until Gen11, and there we 
get a different kind of GuC, the kind where will be no way for i915 to 
have visibility on when a context get in and out, and which physical 
engines. So I think we really won't have a need for these hooks in the 
Gen11 GuC code.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Ville Syrjälä]

On Tue, May 22, 2018 at 01:16:59PM +0300, Jani Nikula wrote:
> On Mon, 21 May 2018, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > We already handle the color encoding mode properly. Remove the broken
> > NV12 special case.
> >
> > Cc: Vidya Srinivas 
> > Cc: Maarten Lankhorst 
> > Signed-off-by: Ville Syrjälä 
> 
> For both patches, Fixes: ?
> 
> The deadline for v4.18 just passed, so this won't follow the nv12
> enabling without it.

Yeah, I suppose we want the nv12 fix in asap. The initial phase thing
might event want cc:stable, although no one has actually complained
about the problem afaik.

> 
> BR,
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 7 +--
> >  1 file changed, 1 insertion(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index f5c078c9d0d2..42c1f4a56556 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3643,11 +3643,6 @@ u32 glk_plane_color_ctl(const struct 
> > intel_crtc_state *crtc_state,
> > plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> >  
> > if (intel_format_is_yuv(fb->format->format)) {
> > -   if (fb->format->format == DRM_FORMAT_NV12) {
> > -   plane_color_ctl |=
> > -   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> > -   goto out;
> > -   }
> > if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> > plane_color_ctl |= 
> > PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> > else
> > @@ -3656,7 +3651,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
> > *crtc_state,
> > if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> > plane_color_ctl |= 
> > PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> > }
> > -out:
> > +
> > return plane_color_ctl;
> >  }
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Special case kernel_context switch request

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-22 13:49:24)
> From: Mika Kuoppala 
> 
> When checking if engine is idling on a kernel context,
> the last request emitted to it could have been the exact
> request to switch into kernel context.
> 
> Do not bail out early even if engine has requests,
> if the last request was for kernel context.
> 
> Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
> timelines")
> Cc: Chris Wilson 
> Signed-off-by: Mika Kuoppala 

I feel there's some redundancy here (in the checks at different levels),
but that's my fault.
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per-context and per-client engine busyness (rev6)

[Patchwork]

== Series Details ==

Series: Per-context and per-client engine busyness (rev6)
URL   : https://patchwork.freedesktop.org/series/32645/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Store engine backpointer in the intel_context
Okay!

Commit: drm/i915: Include i915_scheduler.h from i915_gem_context.h
Okay!

Commit: drm/i915: Forward declare struct intel_context
Okay!

Commit: drm/i915: Move intel_engine_context_in/out into intel_lrc.c
Okay!

Commit: drm/i915: Track per-context engine busyness
Okay!

Commit: drm/i915: Expose list of clients in sysfs
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Update client name on context create
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3691:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Expose per-engine client busyness
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3691:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Add sysfs toggle to enable per-client engine stats
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3703:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Allow clients to query own per-engine busyness
+drivers/gpu/drm/i915/i915_gem_context.c:765:14:expected void const 
volatile [noderef] *
+drivers/gpu/drm/i915/i915_gem_context.c:765:14:got unsigned long long 
[unsigned] [usertype] value
+drivers/gpu/drm/i915/i915_gem_context.c:765:14: warning: incorrect type in 
argument 1 (different base types)
+drivers/gpu/drm/i915/i915_gem_context.c:776:34:expected void *to
+drivers/gpu/drm/i915/i915_gem_context.c:776:34:got struct 
drm_i915_context_engine_busy [noderef] *[assigned] busy_user
+drivers/gpu/drm/i915/i915_gem_context.c:776:34: warning: incorrect type in 
argument 1 (different address spaces)
+drivers/gpu/drm/i915/i915_gem_context.c:776:46:expected void const 
[noderef] *from
+drivers/gpu/drm/i915/i915_gem_context.c:776:46:got struct 
drm_i915_context_engine_busy *
+drivers/gpu/drm/i915/i915_gem_context.c:776:46: warning: incorrect type in 
argument 2 (different address spaces)

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per-context and per-client engine busyness (rev6)

[Patchwork]

== Series Details ==

Series: Per-context and per-client engine busyness (rev6)
URL   : https://patchwork.freedesktop.org/series/32645/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7817526ffcfb drm/i915: Store engine backpointer in the intel_context
e39413c3a24f drm/i915: Include i915_scheduler.h from i915_gem_context.h
89c9c183360d drm/i915: Forward declare struct intel_context
312445e65040 drm/i915: Move intel_engine_context_in/out into intel_lrc.c
c51fae7085a5 drm/i915: Track per-context engine busyness
153d8b61ac31 drm/i915: Expose list of clients in sysfs
-:93: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#93: FILE: drivers/gpu/drm/i915/i915_gem.c:5677:
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,

total: 0 errors, 0 warnings, 1 checks, 197 lines checked
5a863a6a533e drm/i915: Update client name on context create
-:24: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:3219:
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,

total: 0 errors, 0 warnings, 1 checks, 66 lines checked
8ddf5537f960 drm/i915: Expose per-engine client busyness
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#22: 
neverball[  6011]:  rcs0:  41.01%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   0.00%

-:148: ERROR:CODE_INDENT: code indent should use tabs where possible
#148: FILE: drivers/gpu/drm/i915/i915_gem.c:5765:
+^I^I^I^I(struct attribute *)attr);$

-:148: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#148: FILE: drivers/gpu/drm/i915/i915_gem.c:5765:
+   ret = sysfs_create_file(file_priv->client.busy_root,
+   (struct attribute *)attr);

total: 1 errors, 1 warnings, 1 checks, 143 lines checked
3bcb2a77339a drm/i915: Add sysfs toggle to enable per-client engine stats
2eefca086175 drm/i915: Allow clients to query own per-engine busyness

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Re: [Intel-gfx] [RFC 02/10] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Mika Kuoppala]

Tvrtko Ursulin  writes:

> From: Tvrtko Ursulin 
>
> struct i915_gem_context embeds structr i915_sched_attr so needs to include
> the respective header.

s/structr/struct
-Mika

>
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_gem_context.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
> b/drivers/gpu/drm/i915/i915_gem_context.h
> index 74512c92a6a0..33933d43c61a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/i915_gem_context.h
> @@ -30,6 +30,7 @@
>  #include 
>  
>  #include "i915_gem.h"
> +#include "i915_scheduler.h"
>  
>  struct pid;
>  
> -- 
> 2.17.0
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/query: nospec expects no more than an unsigned long

[Patchwork]

== Series Details ==

Series: drm/i915/query: nospec expects no more than an unsigned long
URL   : https://patchwork.freedesktop.org/series/43569/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4220 -> Patchwork_9080 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43569/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9080 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cfl-s3:  PASS -> FAIL (fdo#100368)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cfl-s3:  PASS -> FAIL (fdo#103481)


 Possible fixes 

igt@gem_mmap_gtt@basic-wc:
  fi-cnl-y3:  INCOMPLETE (fdo#105086) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4220 -> Patchwork_9080

  CI_DRM_4220: 9d7ce3ad8801a95461ad4fb63bd5374dfc2dff55 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9080: 524dd95b840b645e0a894ae11afa50de33632e90 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

524dd95b840b drm/i915/query: nospec expects no more than an unsigned long

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9080/issues.html
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[Intel-gfx] [PATCH] drm/i915: Special case kernel_context switch request

[Mika Kuoppala]

From: Mika Kuoppala 

When checking if engine is idling on a kernel context,
the last request emitted to it could have been the exact
request to switch into kernel context.

Do not bail out early even if engine has requests,
if the last request was for kernel context.

Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
timelines")
Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..3fe1212b0f7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -595,7 +595,10 @@ static bool engine_has_idle_kernel_context(struct 
intel_engine_cs *engine)
lockdep_assert_held(>i915->drm.struct_mutex);
 
list_for_each_entry(ring, active_rings, active_link) {
-   if (last_request_on_engine(ring->timeline, engine))
+   struct i915_request *rq =
+   last_request_on_engine(ring->timeline, engine);
+
+   if (rq && rq->gem_context != engine->i915->kernel_context)
return false;
}
 
-- 
2.17.0

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Re: [Intel-gfx] [RFC 04/10] drm/i915: Move intel_engine_context_in/out into intel_lrc.c

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-22 13:30:14)
> From: Tvrtko Ursulin 
> 
> Intel_lrc.c is the only caller and so to avoid some header file ordering
> issues in future patches move these two over there.
> 
> Signed-off-by: Tvrtko Ursulin 

Expectation was that we would be using these in guc. Brief highlight of
how the plan changed?
-Chris
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Re: [Intel-gfx] [RFC 02/10] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-22 13:30:12)
> From: Tvrtko Ursulin 
> 
> struct i915_gem_context embeds structr i915_sched_attr so needs to include
> the respective header.
> 
> Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [RFC 03/10] drm/i915: Forward declare struct intel_context

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-22 13:30:13)
> From: Tvrtko Ursulin 
> 
> This is to avoid an error with structure declared in parameter list if the
> include ordering changes.
> 
> Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[Jani Nikula]

On Tue, 22 May 2018, vathsala nagaraju  wrote:
> From: Vathsala Nagaraju 
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
> move the 165 version check to intel_bios.c
> v3: Jani
> Move the abstraction to intel_bios.
> v4: Jani
> Rename tp*_wakeup_time to have "us" suffix.
> For values outside range[0-3],default to max 2500us.
> Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
> Handle option 2 in default condition.
> Print oustide range value.
> For negetive values default to 2500us.
> v6: Jani
> Handle default first and then fall through for case 2.
> v7: Rodrigo
> Apply this change for IS_GEN9_BC and vbt version > 209
> v8: Puthik
> Add new function vbt_psr_to_us.
> v9: Jani
> Change to v7 version as it's more readable.
> DK
> add comment /*fall through*/ after case2.
>
> Cc: Rodrigo Vivi 
> Cc: Puthikorn Voravootivat 
> Cc: Dhinakaran Pandiyan 
> Cc: Jani Nikula 
> Cc: José Roberto de Souza 
>
> Signed-off-by: Maulik V Vaghela 
> Signed-off-by: Vathsala Nagaraju 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++
>  drivers/gpu/drm/i915/intel_bios.c | 48 
> +--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++
>  4 files changed, 72 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e33c380..dcfa791 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>   bool require_aux_wakeup;
>   int idle_frames;
>   enum psr_lines_to_wait lines_to_wait;
> - int tp1_wakeup_time;
> - int tp2_tp3_wakeup_time;
> + int tp1_wakeup_time_us;
> + int tp2_tp3_wakeup_time_us;
>   } psr;
>  
>   struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb..513b4a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4088,10 +4088,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK   (0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500  (0<<8)
> -#define   EDP_PSR2_TP2_TIME_100  (1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500 (2<<8)
> -#define   EDP_PSR2_TP2_TIME_50   (3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us   (2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us (3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK (3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK  (0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bd..417f656 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct 
> drm_i915_private *dev_priv,
>   break;
>   }
>  
> - dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> - dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> + /*
> +  * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +  * Old decimal value is wake up time in multiples of 100 us.
> +  */
> + if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> + switch (psr_table->tp1_wakeup_time) {
> + case 0:
> + dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> + break;
> + case 1:
> + dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> + break;
> + case 3:
> + dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> + break;
> + default:
> + 

Re: [Intel-gfx] [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS

[Nagaraju, Vathsala]

On 5/12/2018 1:21 AM, Dhinakaran Pandiyan wrote:

intel_dp->psr_dpcd already has the required values.

Cc: Jose Roberto de Souza 
Signed-off-by: Dhinakaran Pandiyan 
---
  drivers/gpu/drm/i915/intel_psr.c | 11 +--
  1 file changed, 1 insertion(+), 10 deletions(-)

Reviewed-by: Vathsala Nagaraju 

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 61ade81576f5..381dbdbf30f4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private 
*dev_priv, u32 psr_iir)
}
  }
  
-static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)

-{
-   uint8_t psr_caps = 0;
-
-   if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_CAPS, _caps) != 1)
-   return false;
-   return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
-}
-
  static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
  {
uint8_t dprx = 0;
@@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 * GTC first.
 */
dev_priv->psr.sink_psr2_support =
-   intel_dp_get_y_coord_required(intel_dp);
+   intel_dp->psr_dpcd[1] & 
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
DRM_DEBUG_KMS("PSR2 %ssupported\n",
  dev_priv->psr.sink_psr2_support ? "" : "not ");
  


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[Intel-gfx] [RFC 04/10] drm/i915: Move intel_engine_context_in/out into intel_lrc.c

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c| 57 +
 drivers/gpu/drm/i915/intel_ringbuffer.h | 55 
 2 files changed, 57 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8480c1534c4b..3947bdcd8ea6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -375,6 +375,63 @@ execlists_context_status_change(struct i915_request *rq, 
unsigned long status)
   status, rq);
 }
 
+static inline void
+intel_engine_context_in(struct intel_engine_cs *engine)
+{
+   unsigned long flags;
+
+   if (READ_ONCE(engine->stats.enabled) == 0)
+   return;
+
+   write_seqlock_irqsave(>stats.lock, flags);
+
+   if (engine->stats.enabled > 0) {
+   if (engine->stats.active++ == 0)
+   engine->stats.start = ktime_get();
+   GEM_BUG_ON(engine->stats.active == 0);
+   }
+
+   write_sequnlock_irqrestore(>stats.lock, flags);
+}
+
+static inline void
+intel_engine_context_out(struct intel_engine_cs *engine)
+{
+   unsigned long flags;
+
+   if (READ_ONCE(engine->stats.enabled) == 0)
+   return;
+
+   write_seqlock_irqsave(>stats.lock, flags);
+
+   if (engine->stats.enabled > 0) {
+   ktime_t last;
+
+   if (engine->stats.active && --engine->stats.active == 0) {
+   /*
+* Decrement the active context count and in case GPU
+* is now idle add up to the running total.
+*/
+   last = ktime_sub(ktime_get(), engine->stats.start);
+
+   engine->stats.total = ktime_add(engine->stats.total,
+   last);
+   } else if (engine->stats.active == 0) {
+   /*
+* After turning on engine stats, context out might be
+* the first event in which case we account from the
+* time stats gathering was turned on.
+*/
+   last = ktime_sub(ktime_get(), engine->stats.enabled_at);
+
+   engine->stats.total = ktime_add(engine->stats.total,
+   last);
+   }
+   }
+
+   write_sequnlock_irqrestore(>stats.lock, flags);
+}
+
 inline void
 execlists_user_begin(struct intel_engine_execlists *execlists,
 const struct execlist_port *port)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 7c25db5bcaaa..1bdc42deca3c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -1091,61 +1091,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 struct intel_engine_cs *
 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
 
-static inline void intel_engine_context_in(struct intel_engine_cs *engine)
-{
-   unsigned long flags;
-
-   if (READ_ONCE(engine->stats.enabled) == 0)
-   return;
-
-   write_seqlock_irqsave(>stats.lock, flags);
-
-   if (engine->stats.enabled > 0) {
-   if (engine->stats.active++ == 0)
-   engine->stats.start = ktime_get();
-   GEM_BUG_ON(engine->stats.active == 0);
-   }
-
-   write_sequnlock_irqrestore(>stats.lock, flags);
-}
-
-static inline void intel_engine_context_out(struct intel_engine_cs *engine)
-{
-   unsigned long flags;
-
-   if (READ_ONCE(engine->stats.enabled) == 0)
-   return;
-
-   write_seqlock_irqsave(>stats.lock, flags);
-
-   if (engine->stats.enabled > 0) {
-   ktime_t last;
-
-   if (engine->stats.active && --engine->stats.active == 0) {
-   /*
-* Decrement the active context count and in case GPU
-* is now idle add up to the running total.
-*/
-   last = ktime_sub(ktime_get(), engine->stats.start);
-
-   engine->stats.total = ktime_add(engine->stats.total,
-   last);
-   } else if (engine->stats.active == 0) {
-   /*
-* After turning on engine stats, context out might be
-* the first event in which case we account from the
-* time stats gathering was turned on.
-*/
-   last = 

[Intel-gfx] [RFC 08/10] drm/i915: Expose per-engine client busyness

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Expose per-client and per-engine busyness under the previously added sysfs
client root.

The new files are one per-engine instance and located under the 'busy'
directory.

Each contains a monotonically increasing nano-second resolution times each
client's jobs were executing on the GPU.

$ cat /sys/class/drm/card0/clients/5/busy/rcs0
32516602

This data can serve as an interface to implement a top like utility for
GPU jobs. For instance I have prototyped a tool in IGT which produces
periodic output like:

neverball[  6011]:  rcs0:  41.01%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   0.00%
 Xorg[  5664]:  rcs0:  31.16%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   0.00%
xfwm4[  5727]:  rcs0:   0.00%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   0.00%

This tools can also be extended to use the i915 PMU and show overall engine
busyness, and engine loads using the queue depth metric.

v2: Use intel_context_engine_get_busy_time.
v3: New directory structure.
v4: Rebase.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h |  8 
 drivers/gpu/drm/i915/i915_gem.c | 80 +++--
 2 files changed, 85 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d14798bff230..793565d7bdd0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -318,6 +318,12 @@ struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
 
+struct i915_engine_busy_attribute {
+   struct device_attribute attr;
+   struct drm_i915_file_private *file_priv;
+   struct intel_engine_cs *engine;
+};
+
 struct drm_i915_file_private {
struct drm_i915_private *dev_priv;
struct drm_file *file;
@@ -356,10 +362,12 @@ struct drm_i915_file_private {
char *name;
 
struct kobject *root;
+   struct kobject *busy_root;
 
struct {
struct device_attribute pid;
struct device_attribute name;
+   struct i915_engine_busy_attribute 
busy[I915_NUM_ENGINES];
} attr;
} client;
 };
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cbd5aa818cd4..5b8335871425 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5673,6 +5673,37 @@ show_client_pid(struct device *kdev, struct 
device_attribute *attr, char *buf)
return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
 }
 
+struct busy_ctx {
+   struct intel_engine_cs *engine;
+   u64 total;
+};
+
+static int busy_add(int _id, void *p, void *data)
+{
+   struct busy_ctx *bc = data;
+   struct i915_gem_context *ctx = p;
+   struct intel_context *ce = to_intel_context(ctx, bc->engine);
+
+   bc->total += ktime_to_ns(intel_context_get_busy_time(ce));
+
+   return 0;
+}
+
+static ssize_t
+show_client_busy(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   struct i915_engine_busy_attribute *i915_attr =
+   container_of(attr, typeof(*i915_attr), attr);
+   struct drm_i915_file_private *file_priv = i915_attr->file_priv;
+   struct busy_ctx bc = { .engine = i915_attr->engine };
+
+   rcu_read_lock();
+   idr_for_each(_priv->context_idr, busy_add, );
+   rcu_read_unlock();
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n", bc.total);
+}
+
 int
 i915_gem_add_client(struct drm_i915_private *i915,
struct drm_i915_file_private *file_priv,
@@ -5680,8 +5711,10 @@ i915_gem_add_client(struct drm_i915_private *i915,
unsigned int serial)
 {
int ret = -ENOMEM;
+   struct intel_engine_cs *engine;
struct device_attribute *attr;
-   char id[32];
+   enum intel_engine_id id, id2;
+   char idstr[32];
 
if (!i915->clients.root)
goto err_name;
@@ -5690,8 +5723,8 @@ i915_gem_add_client(struct drm_i915_private *i915,
if (!file_priv->client.name)
goto err_name;
 
-   snprintf(id, sizeof(id), "%u", serial);
-   file_priv->client.root = kobject_create_and_add(id,
+   snprintf(idstr, sizeof(idstr), "%u", serial);
+   file_priv->client.root = kobject_create_and_add(idstr,
i915->clients.root);
if (!file_priv->client.root)
goto err_client;
@@ -5716,10 +5749,41 @@ i915_gem_add_client(struct drm_i915_private *i915,
if (ret)
goto err_attr_pid;
 
+   file_priv->client.busy_root =
+   kobject_create_and_add("busy", file_priv->client.root);
+   if (!file_priv->client.busy_root)
+   goto err_busy_root;
+
+   for_each_engine(engine, i915, id) {
+   file_priv->client.attr.busy[id].file_priv = file_priv;
+   

[Intel-gfx] [RFC 07/10] drm/i915: Update client name on context create

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Some clients have the DRM fd passed to them over a socket by the X server.

Grab the real client and pid when they create their first context and
update the exposed data for more useful enumeration.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h |  8 
 drivers/gpu/drm/i915/i915_gem.c |  4 ++--
 drivers/gpu/drm/i915/i915_gem_context.c | 16 +---
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b25799ca5c5b..d14798bff230 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3213,6 +3213,14 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align);
+
+int
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,
+   struct task_struct *task,
+   unsigned int serial);
+void i915_gem_remove_client(struct drm_i915_file_private *file_priv);
+
 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7be92761fc30..cbd5aa818cd4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5673,7 +5673,7 @@ show_client_pid(struct device *kdev, struct 
device_attribute *attr, char *buf)
return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
 }
 
-static int
+int
 i915_gem_add_client(struct drm_i915_private *i915,
struct drm_i915_file_private *file_priv,
struct task_struct *task,
@@ -5731,7 +5731,7 @@ i915_gem_add_client(struct drm_i915_private *i915,
return ret;
 }
 
-static void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
+void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
 {
sysfs_remove_file(file_priv->client.root,
  (struct attribute *)_priv->client.attr.pid);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 37cace775b31..2fcae26f63bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -656,9 +656,10 @@ static bool client_is_banned(struct drm_i915_file_private 
*file_priv)
 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  struct drm_file *file)
 {
+   struct drm_i915_file_private *file_priv = file->driver_priv;
+   pid_t pid = pid_nr(get_task_pid(current, PIDTYPE_PID));
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_context_create *args = data;
-   struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_gem_context *ctx;
int ret;
 
@@ -670,8 +671,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, 
void *data,
 
if (client_is_banned(file_priv)) {
DRM_DEBUG("client %s[%d] banned from creating ctx\n",
- current->comm,
- pid_nr(get_task_pid(current, PIDTYPE_PID)));
+ current->comm, pid);
 
return -EIO;
}
@@ -680,6 +680,16 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, 
void *data,
if (ret)
return ret;
 
+   if (file_priv->client.pid != pid) {
+   i915_gem_remove_client(file_priv);
+   ret = i915_gem_add_client(dev_priv, file_priv, current,
+ file_priv->client.id);
+   if (ret) {
+   mutex_unlock(>struct_mutex);
+   return ret;
+   }
+   }
+
ctx = i915_gem_create_context(dev_priv, file_priv);
mutex_unlock(>struct_mutex);
if (IS_ERR(ctx))
-- 
2.17.0

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[Intel-gfx] [RFC 09/10] drm/i915: Add sysfs toggle to enable per-client engine stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

By default we are not collecting any per-engine and per-context
statistcs.

Add a new sysfs toggle to enable this facility:

$ echo 1 >/sys/class/drm/card0/clients/enable_stats

v2: Rebase.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++
 drivers/gpu/drm/i915/i915_sysfs.c | 72 +++
 2 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 793565d7bdd0..f0ba8a046bd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2145,6 +2145,10 @@ struct drm_i915_private {
struct i915_drm_clients {
struct kobject *root;
atomic_t serial;
+   struct {
+   bool enabled;
+   struct device_attribute attr;
+   } stats;
} clients;
 
/*
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index d809259456ef..70115072d56f 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -576,9 +576,67 @@ static void i915_setup_error_capture(struct device *kdev) 
{}
 static void i915_teardown_error_capture(struct device *kdev) {}
 #endif
 
+static ssize_t
+show_client_stats(struct device *kdev, struct device_attribute *attr, char 
*buf)
+{
+   struct drm_i915_private *i915 =
+   container_of(attr, struct drm_i915_private, clients.stats.attr);
+
+   return snprintf(buf, PAGE_SIZE, "%u\n", i915->clients.stats.enabled);
+}
+
+static ssize_t
+store_client_stats(struct device *kdev, struct device_attribute *attr,
+  const char *buf, size_t count)
+{
+   struct drm_i915_private *i915 =
+   container_of(attr, struct drm_i915_private, clients.stats.attr);
+   bool disable = false;
+   bool enable = false;
+   bool val = false;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   int ret;
+
+/* Use RCS as proxy for all engines. */
+   if (!intel_engine_supports_stats(i915->engine[RCS]))
+   return -EINVAL;
+
+   ret = kstrtobool(buf, );
+   if (ret)
+   return ret;
+
+   ret = i915_mutex_lock_interruptible(>drm);
+   if (ret)
+   return ret;
+
+   if (val && !i915->clients.stats.enabled)
+   enable = true;
+   else if (!val && i915->clients.stats.enabled)
+   disable = true;
+
+   if (!enable && !disable)
+   goto out;
+
+   for_each_engine(engine, i915, id) {
+   if (enable)
+   WARN_ON_ONCE(intel_enable_engine_stats(engine));
+   else if (disable)
+   intel_disable_engine_stats(engine);
+   }
+
+   i915->clients.stats.enabled = val;
+
+out:
+   mutex_unlock(>drm.struct_mutex);
+
+   return count;
+}
+
 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 {
struct device *kdev = dev_priv->drm.primary->kdev;
+   struct device_attribute *attr;
int ret;
 
dev_priv->clients.root =
@@ -586,6 +644,17 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
if (!dev_priv->clients.root)
DRM_ERROR("Per-client sysfs setup failed\n");
 
+   attr = _priv->clients.stats.attr;
+   attr->attr.name = "enable_stats";
+   attr->attr.mode = 0664;
+   attr->show = show_client_stats;
+   attr->store = store_client_stats;
+
+   ret = sysfs_create_file(dev_priv->clients.root,
+   (struct attribute *)attr);
+   if (ret)
+   DRM_ERROR("Per-client sysfs setup failed! (%d)\n", ret);
+
 #ifdef CONFIG_PM
if (HAS_RC6(dev_priv)) {
ret = sysfs_merge_group(>kobj,
@@ -647,6 +716,9 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
sysfs_unmerge_group(>kobj, _attr_group);
 #endif
 
+   sysfs_remove_file(dev_priv->clients.root,
+ (struct attribute *)_priv->clients.stats.attr);
+
if (dev_priv->clients.root)
kobject_put(dev_priv->clients.root);
 }
-- 
2.17.0

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[Intel-gfx] [RFC 10/10] drm/i915: Allow clients to query own per-engine busyness

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Some customers want to know how much of the GPU time are their clients
using in order to make dynamic load balancing decisions.

With the accounting infrastructure in place in the previous patch, we add
a new context param (I915_CONTEXT_GET_ENGINES_BUSY) which points to struct
drm_i915_context_engines_busy, followed by a variable number of structs
drm_i915_context_engine_busy.

Userspace needs to provide the number of attached structures in the
num_engines fields, as well as set args->size to byte size of the provided
buffer.

Attached drm_i915_context_engine_busy objects need to have the class and
instance of the engine which userspace wants to query busyness of
initialized.

Kernel will then report accumulated engine busyness as monotonically
increasing number of nano-seconds the engine spent executing jobs
belonging to this context.

v2:
 * Use intel_context_engine_get_busy_time.
 * Refactor to only use struct_mutex while initially enabling engine
   stats.

v3:
 * Fix stats enabling.

v4:
 * Change uAPI to enable querying multiple engines at a time.
   (Chris Wilson)

v5:
 * Rebase.

Signed-off-by: Tvrtko Ursulin 
Cc: gordon.ke...@intel.com
---
 drivers/gpu/drm/i915/i915_gem_context.c | 100 ++--
 drivers/gpu/drm/i915/i915_gem_context.h |   1 +
 include/uapi/drm/i915_drm.h |  21 +
 3 files changed, 117 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2fcae26f63bb..7279128becbd 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -117,9 +117,10 @@ static void lut_close(struct i915_gem_context *ctx)
 
 static void i915_gem_context_free(struct i915_gem_context *ctx)
 {
+   struct drm_i915_private *i915 = ctx->i915;
unsigned int n;
 
-   lockdep_assert_held(>i915->drm.struct_mutex);
+   lockdep_assert_held(>drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
 
i915_ppgtt_put(ctx->ppgtt);
@@ -127,6 +128,9 @@ static void i915_gem_context_free(struct i915_gem_context 
*ctx)
for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
struct intel_context *ce = >__engine[n];
 
+   if (i915->engine[n] && ce->stats.enabled)
+   intel_disable_engine_stats(i915->engine[n]);
+
if (ce->ops)
ce->ops->destroy(ce);
}
@@ -136,7 +140,7 @@ static void i915_gem_context_free(struct i915_gem_context 
*ctx)
 
list_del(>link);
 
-   ida_simple_remove(>i915->contexts.hw_ida, ctx->hw_id);
+   ida_simple_remove(>contexts.hw_ida, ctx->hw_id);
kfree_rcu(ctx, rcu);
 }
 
@@ -733,11 +737,93 @@ int i915_gem_context_destroy_ioctl(struct drm_device 
*dev, void *data,
return 0;
 }
 
+static int
+get_engines_busy(struct drm_i915_private *i915,
+struct i915_gem_context *ctx,
+struct drm_i915_gem_context_param *args)
+{
+   struct drm_i915_context_engine_busy __user *busy_user;
+   struct drm_i915_context_engines_busy engines;
+   struct drm_i915_context_engine_busy busy;
+   bool mutex = false;
+   unsigned int i;
+   int ret = 0;
+
+   if (args->size < sizeof(engines))
+   return -EINVAL;
+
+   if (copy_from_user(, u64_to_user_ptr(args->value),
+  sizeof(engines)))
+   return -EFAULT;
+
+   if (engines.pad || engines.mbz)
+   return -EINVAL;
+
+   if (engines.num_engines == 0 || engines.num_engines > I915_NUM_ENGINES)
+   return -EINVAL;
+
+   if (!access_ok(VERIFY_WRITE, args->value,
+  sizeof(engines) + engines.num_engines * sizeof(busy)))
+   return -EFAULT;
+
+   busy_user = (struct drm_i915_context_engine_busy __user *)
+   ((char __user *)args->value + sizeof(engines));
+
+   for (i = 0; i < engines.num_engines; i++, busy_user++) {
+   struct intel_engine_cs *engine;
+   struct intel_context *ce;
+
+   __copy_from_user(busy_user, , sizeof(busy));
+
+   if (busy.mbz || busy.flags || busy.busy) {
+   ret = -EINVAL;
+   goto out;
+   }
+
+   engine = intel_engine_lookup_user(i915,
+ busy.class, busy.instance);
+   if (!engine) {
+   ret = -EINVAL;
+   goto out;
+   }
+
+   /* Enable stats on first query. */
+   ce = to_intel_context(ctx, engine);
+   if (!READ_ONCE(ce->stats.enabled)) {
+   /* Grab mutex if need to enable engine stats. */
+   if (!mutex) {
+   ret = i915_mutex_lock_interruptible(>drm);
+  

[Intel-gfx] [RFC 06/10] drm/i915: Expose list of clients in sysfs

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Expose a list of clients with open file handles in sysfs.

This will be a basis for a top-like utility showing per-client and per-
engine GPU load.

Currently we only expose each client's pid and name under opaque numbered
directories in /sys/class/drm/card0/clients/.

For instance:

/sys/class/drm/card0/clients/3/name: Xorg
/sys/class/drm/card0/clients/3/pid: 5664

v2:
 Chris Wilson:
 * Enclose new members into dedicated structs.
 * Protect against failed sysfs registration.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   |  19 +
 drivers/gpu/drm/i915/i915_gem.c   | 117 --
 drivers/gpu/drm/i915/i915_sysfs.c |   8 ++
 3 files changed, 137 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380b43e3..b25799ca5c5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -348,6 +348,20 @@ struct drm_i915_file_private {
  */
 #define I915_MAX_CLIENT_CONTEXT_BANS 3
atomic_t context_bans;
+
+   struct i915_drm_client {
+   unsigned int id;
+
+   pid_t pid;
+   char *name;
+
+   struct kobject *root;
+
+   struct {
+   struct device_attribute pid;
+   struct device_attribute name;
+   } attr;
+   } client;
 };
 
 /* Interface history:
@@ -2120,6 +2134,11 @@ struct drm_i915_private {
 
struct i915_pmu pmu;
 
+   struct i915_drm_clients {
+   struct kobject *root;
+   atomic_t serial;
+   } clients;
+
/*
 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 * will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ccdfa7250ad3..7be92761fc30 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5653,6 +5653,94 @@ int i915_gem_freeze_late(struct drm_i915_private 
*dev_priv)
return 0;
 }
 
+static ssize_t
+show_client_name(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   struct drm_i915_file_private *file_priv =
+   container_of(attr, struct drm_i915_file_private,
+client.attr.name);
+
+   return snprintf(buf, PAGE_SIZE, "%s", file_priv->client.name);
+}
+
+static ssize_t
+show_client_pid(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   struct drm_i915_file_private *file_priv =
+   container_of(attr, struct drm_i915_file_private,
+client.attr.pid);
+
+   return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
+}
+
+static int
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,
+   struct task_struct *task,
+   unsigned int serial)
+{
+   int ret = -ENOMEM;
+   struct device_attribute *attr;
+   char id[32];
+
+   if (!i915->clients.root)
+   goto err_name;
+
+   file_priv->client.name = kstrdup(task->comm, GFP_KERNEL);
+   if (!file_priv->client.name)
+   goto err_name;
+
+   snprintf(id, sizeof(id), "%u", serial);
+   file_priv->client.root = kobject_create_and_add(id,
+   i915->clients.root);
+   if (!file_priv->client.root)
+   goto err_client;
+
+   attr = _priv->client.attr.name;
+   attr->attr.name = "name";
+   attr->attr.mode = 0444;
+   attr->show = show_client_name;
+
+   ret = sysfs_create_file(file_priv->client.root,
+   (struct attribute *)attr);
+   if (ret)
+   goto err_attr_name;
+
+   attr = _priv->client.attr.pid;
+   attr->attr.name = "pid";
+   attr->attr.mode = 0444;
+   attr->show = show_client_pid;
+
+   ret = sysfs_create_file(file_priv->client.root,
+   (struct attribute *)attr);
+   if (ret)
+   goto err_attr_pid;
+
+   file_priv->client.pid = pid_nr(get_task_pid(task, PIDTYPE_PID));
+
+   return 0;
+
+err_attr_pid:
+   sysfs_remove_file(file_priv->client.root,
+ (struct attribute *)_priv->client.attr.name);
+err_attr_name:
+   kobject_put(file_priv->client.root);
+err_client:
+   kfree(file_priv->client.name);
+err_name:
+   return ret;
+}
+
+static void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
+{
+   sysfs_remove_file(file_priv->client.root,
+ (struct attribute *)_priv->client.attr.pid);
+   sysfs_remove_file(file_priv->client.root,
+ (struct attribute *)_priv->client.attr.name);
+   kobject_put(file_priv->client.root);
+   

[Intel-gfx] [RFC 02/10] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

struct i915_gem_context embeds structr i915_sched_attr so needs to include
the respective header.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_context.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 74512c92a6a0..33933d43c61a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -30,6 +30,7 @@
 #include 
 
 #include "i915_gem.h"
+#include "i915_scheduler.h"
 
 struct pid;
 
-- 
2.17.0

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[Intel-gfx] [RFC 03/10] drm/i915: Forward declare struct intel_context

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

This is to avoid an error with structure declared in parameter list if the
include ordering changes.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_context.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 33933d43c61a..4d6994f311be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -46,6 +46,8 @@ struct intel_ring;
 
 #define DEFAULT_CONTEXT_HANDLE 0
 
+struct intel_context;
+
 struct intel_context_ops {
void (*unpin)(struct intel_context *ce);
void (*destroy)(struct intel_context *ce);
-- 
2.17.0

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[Intel-gfx] [RFC 05/10] drm/i915: Track per-context engine busyness

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Some customers want to know how much of the GPU time are their clients
using in order to make dynamic load balancing decisions.

With the hooks already in place which track the overall engine busyness,
we can extend that slightly to split that time between contexts.

v2: Fix accounting for tail updates.
v3: Rebase.
v4: Mark currently running contexts as active on stats enable.
v5: Include some headers to fix the build.
v6: Added fine grained lock.
v7: Convert to seqlock. (Chris Wilson)
v8: Rebase and tidy with helpers.

Signed-off-by: Tvrtko Ursulin 
Cc: gordon.ke...@intel.com
---
 drivers/gpu/drm/i915/i915_gem_context.c |  1 +
 drivers/gpu/drm/i915/i915_gem_context.h | 17 +++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 27 +++
 drivers/gpu/drm/i915/intel_lrc.c| 62 +
 4 files changed, 97 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index bff3788908e0..37cace775b31 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -283,6 +283,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 
ce->gem_context = ctx;
ce->engine = dev_priv->engine[n];
+   seqlock_init(>stats.lock);
}
 
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4d6994f311be..e3d9948f7186 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "i915_gem.h"
 #include "i915_scheduler.h"
@@ -160,6 +161,13 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
 
+   struct intel_context_stats {
+   seqlock_t lock;
+   bool active;
+   ktime_t start;
+   ktime_t total;
+   } stats;
+
const struct intel_context_ops *ops;
} __engine[I915_NUM_ENGINES];
 
@@ -339,4 +347,13 @@ static inline void i915_gem_context_put(struct 
i915_gem_context *ctx)
kref_put(>ref, i915_gem_context_release);
 }
 
+static inline void
+__intel_context_stats_start(struct intel_context_stats *stats, ktime_t now)
+{
+   stats->start = now;
+   stats->active = true;
+}
+
+ktime_t intel_context_get_busy_time(struct intel_context *ce);
+
 #endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index abfde8968900..020391c8a874 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1580,6 +1580,14 @@ int intel_enable_engine_stats(struct intel_engine_cs 
*engine)
 
engine->stats.enabled_at = ktime_get();
 
+   /* Mark currently running context as active. */
+   if (port_isset(port)) {
+   struct i915_request *rq = port_request(port);
+
+   __intel_context_stats_start(>hw_context->stats,
+   engine->stats.enabled_at);
+   }
+
/* XXX submission method oblivious? */
while (num_ports-- && port_isset(port)) {
engine->stats.active++;
@@ -1653,6 +1661,25 @@ void intel_disable_engine_stats(struct intel_engine_cs 
*engine)
write_sequnlock_irqrestore(>stats.lock, flags);
 }
 
+ktime_t intel_context_get_busy_time(struct intel_context *ce)
+{
+   unsigned int seq;
+   ktime_t total;
+
+   do {
+   seq = read_seqbegin(>stats.lock);
+
+   total = ce->stats.total;
+
+   if (ce->stats.active)
+   total = ktime_add(total,
+ ktime_sub(ktime_get(),
+   ce->stats.start));
+   } while (read_seqretry(>stats.lock, seq));
+
+   return total;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_engine.c"
 #include "selftests/intel_engine_cs.c"
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3947bdcd8ea6..72e2a9065b0f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -376,18 +376,48 @@ execlists_context_status_change(struct i915_request *rq, 
unsigned long status)
 }
 
 static inline void
-intel_engine_context_in(struct intel_engine_cs *engine)
+intel_context_stats_start(struct intel_context_stats *stats, ktime_t now)
 {
+   write_seqlock(>lock);
+   __intel_context_stats_start(stats, now);
+   write_sequnlock(>lock);
+}
+
+static inline void
+intel_context_stats_stop(struct intel_context_stats *stats, ktime_t now)
+{
+   

[Intel-gfx] [RFC 01/10] drm/i915: Store engine backpointer in the intel_context

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

It will become useful in a later patch.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 1 +
 drivers/gpu/drm/i915/i915_gem_context.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..bff3788908e0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -282,6 +282,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct intel_context *ce = >__engine[n];
 
ce->gem_context = ctx;
+   ce->engine = dev_priv->engine[n];
}
 
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index c3262b4dd2ee..74512c92a6a0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -150,6 +150,7 @@ struct i915_gem_context {
/** engine: per-engine logical HW state */
struct intel_context {
struct i915_gem_context *gem_context;
+   struct intel_engine_cs *engine;
struct i915_vma *state;
struct intel_ring *ring;
u32 *lrc_reg_state;
-- 
2.17.0

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[Intel-gfx] [RFC v5 00/10] Per-context and per-client engine busyness

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Another re-post of my earlier, now slightly updated work, to expose a DRM client
hierarchy in sysfs in order to enable a top like tool:

intel-gpu-top - load avg 40.80, 27.11,  1.50;  882/ 950 MHz;0% RC6;  13.26 
Watts;   261903 irqs/s

  IMC reads: 5543 MiB/s
 IMC writes:  236 MiB/s

  ENGINE  BUSYQD MI_SEMA MI_WAIT
 Render/3D/060.47% |███▍   |  28   0   1  0%  0%
   Blitter/092.70% |█▌ |   0   0   1  0%  0%
 Video/0   100.00% |███|  15  37   2  0%  0%
 Video/151.68% |█▊ |   0   0   1  0%  0%
  VideoEnhance/0 0.00% |   |   0   0   0  0%  0%

  PIDNAME   rcs0   bcs0   vcs0   vcs1   vecs0
21664gem_wsim |█▍   || ||█||▋|| |
21662 gem_latency | ||▎|| || || |
21662 gem_latency | || || || || |

Hopefully the screen shot is self-explanatory. It shows overall GPU per-engine
stats, plus per-client and per-engine busyness.

In this version we have a larger rebase on top of the recent code base changes,
some of which made these patches cleaner.

Series now starts with four uninteresting patches, while patches 5 & 10 are what
is asked for by the customer.

Patches 6-9 are the sysfs interface to per-client busyness which enables the
above top like display. I am still sticking with sysfs since theoretically it
could enable easy access control if so would be wanted one day. As discussed
in the past something like this is not possible to expose via PMU.

I think in the future, as compute workloads become more prominent, having the
ability to look at process GPU usage, along the CPU, will become more
interesting.

Final note is that in any case patch 10 is blocked by the lack of open source
userspace.

Tvrtko Ursulin (10):
  drm/i915: Store engine backpointer in the intel_context
  drm/i915: Include i915_scheduler.h from i915_gem_context.h
  drm/i915: Forward declare struct intel_context
  drm/i915: Move intel_engine_context_in/out into intel_lrc.c
  drm/i915: Track per-context engine busyness
  drm/i915: Expose list of clients in sysfs
  drm/i915: Update client name on context create
  drm/i915: Expose per-engine client busyness
  drm/i915: Add sysfs toggle to enable per-client engine stats
  drm/i915: Allow clients to query own per-engine busyness

 drivers/gpu/drm/i915/i915_drv.h |  39 +
 drivers/gpu/drm/i915/i915_gem.c | 191 +++-
 drivers/gpu/drm/i915/i915_gem_context.c | 118 ++-
 drivers/gpu/drm/i915/i915_gem_context.h |  22 +++
 drivers/gpu/drm/i915/i915_sysfs.c   |  80 ++
 drivers/gpu/drm/i915/intel_engine_cs.c  |  27 
 drivers/gpu/drm/i915/intel_lrc.c| 107 -
 drivers/gpu/drm/i915/intel_ringbuffer.h |  55 ---
 include/uapi/drm/i915_drm.h |  21 +++
 9 files changed, 586 insertions(+), 74 deletions(-)

-- 
2.17.0

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Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR

[Nagaraju, Vathsala]

On 5/12/2018 1:21 AM, Dhinakaran Pandiyan wrote:

Ville noticed that we are unncessarily reading DPCD's after knowing
panel did not support PSR. Looks like this check that was present
earlier got removed unintentionally, let's put it back.

While we do this, add the PSR version number in the debug print.

Cc: Ville Syrjälä 
Signed-off-by: Dhinakaran Pandiyan 
---
  drivers/gpu/drm/i915/intel_psr.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

Reviewed-by: Vathsala Nagaraju 


diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1de..8fe6d2f9ab2b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 sizeof(intel_dp->psr_dpcd));
  
-	if (intel_dp->psr_dpcd[0]) {

-   dev_priv->psr.sink_support = true;
-   DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
-   }
+   if (!intel_dp->psr_dpcd[0])
+   return;
+
+   DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
+ intel_dp->psr_dpcd[0]);
+   dev_priv->psr.sink_support = true;
  
  	if (INTEL_GEN(dev_priv) >= 9 &&

(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
@@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 */
dev_priv->psr.sink_psr2_support =
intel_dp_get_y_coord_required(intel_dp);
-   DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
- ? "supported" : "not supported");
+   DRM_DEBUG_KMS("PSR2 %ssupported\n",
+ dev_priv->psr.sink_psr2_support ? "" : "not ");
  
  		if (dev_priv->psr.sink_psr2_support) {

dev_priv->psr.colorimetry_support =


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Re: [Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Lionel Landwerlin]

On 22/05/18 13:10, Chris Wilson wrote:

nospec quite reasonably asserts that it will never be used with an index
larger than unsigned long (that being the largest possibly index into an
C array). However, our ubi uses the convention of u64 for any large
integer, running afoul of the assertion on 32b. Reduce our index to an
unsigned long, checking for type overflow first.

   drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
   include/linux/compiler.h:339:38: error: call to '__compiletime_assert_119' 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)

Reported-by: kbuild-...@01.org
Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer lookup")
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 


Reviewed-by: Lionel Landwerlin 


---
  drivers/gpu/drm/i915/i915_query.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 95f9d179afc4..3f502eef2431 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -102,7 +102,7 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
  
  	for (i = 0; i < args->num_items; i++, user_item_ptr++) {

struct drm_i915_query_item item;
-   u64 func_idx;
+   unsigned long func_idx;
int ret;
  
  		if (copy_from_user(, user_item_ptr, sizeof(item)))

@@ -111,6 +111,9 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
if (item.query_id == 0)
return -EINVAL;
  
+		if (overflows_type(item.query_id - 1, unsigned long))

+   return -EINVAL;
+
func_idx = item.query_id - 1;
  
  		ret = -EINVAL;



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Re: [Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Chris Wilson]

Quoting Chris Wilson (2018-05-22 13:17:06)
> Quoting Lionel Landwerlin (2018-05-22 13:13:03)
> > On 22/05/18 13:10, Chris Wilson wrote:
> > > nospec quite reasonably asserts that it will never be used with an index
> > > larger than unsigned long (that being the largest possibly index into an
> > > C array). However, our ubi uses the convention of u64 for any large
> > > integer, running afoul of the assertion on 32b. Reduce our index to an
> > > unsigned long, checking for type overflow first.
> > >
> > >drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
> > >include/linux/compiler.h:339:38: error: call to 
> > > '__compiletime_assert_119' declared with attribute error: BUILD_BUG_ON 
> > > failed: sizeof(_s) > sizeof(long)
> > >
> > > Reported-by: kbuild-...@01.org
> > > Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer 
> > > lookup")
> > > Signed-off-by: Chris Wilson 
> > > Cc: Lionel Landwerlin 
> > > Cc: Joonas Lahtinen 
> > > Cc: Tvrtko Ursulin 
> > > ---
> > >   drivers/gpu/drm/i915/i915_query.c | 5 -
> > >   1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_query.c 
> > > b/drivers/gpu/drm/i915/i915_query.c
> > > index 95f9d179afc4..3f502eef2431 100644
> > > --- a/drivers/gpu/drm/i915/i915_query.c
> > > +++ b/drivers/gpu/drm/i915/i915_query.c
> > > @@ -102,7 +102,7 @@ int i915_query_ioctl(struct drm_device *dev, void 
> > > *data, struct drm_file *file)
> > >   
> > >   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> > >   struct drm_i915_query_item item;
> > > - u64 func_idx;
> > > + unsigned long func_idx;
> > >   int ret;
> > >   
> > >   if (copy_from_user(, user_item_ptr, sizeof(item)))
> > > @@ -111,6 +111,9 @@ int i915_query_ioctl(struct drm_device *dev, void 
> > > *data, struct drm_file *file)
> > I guess you can get rid of this if (item.query_id == 0) then :
> 
> Hmm, we could indeed. The choice is whether we want to make it clear
> that id=0 is illegal (making it easier to add debug later?)

On second thoughts, I don't think so since u64==unsigned long on 64b, so
(u64)-1 should fit inside unsigned long.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Chris Wilson]

Quoting Lionel Landwerlin (2018-05-22 13:13:03)
> On 22/05/18 13:10, Chris Wilson wrote:
> > nospec quite reasonably asserts that it will never be used with an index
> > larger than unsigned long (that being the largest possibly index into an
> > C array). However, our ubi uses the convention of u64 for any large
> > integer, running afoul of the assertion on 32b. Reduce our index to an
> > unsigned long, checking for type overflow first.
> >
> >drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
> >include/linux/compiler.h:339:38: error: call to 
> > '__compiletime_assert_119' declared with attribute error: BUILD_BUG_ON 
> > failed: sizeof(_s) > sizeof(long)
> >
> > Reported-by: kbuild-...@01.org
> > Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer 
> > lookup")
> > Signed-off-by: Chris Wilson 
> > Cc: Lionel Landwerlin 
> > Cc: Joonas Lahtinen 
> > Cc: Tvrtko Ursulin 
> > ---
> >   drivers/gpu/drm/i915/i915_query.c | 5 -
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_query.c 
> > b/drivers/gpu/drm/i915/i915_query.c
> > index 95f9d179afc4..3f502eef2431 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -102,7 +102,7 @@ int i915_query_ioctl(struct drm_device *dev, void 
> > *data, struct drm_file *file)
> >   
> >   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> >   struct drm_i915_query_item item;
> > - u64 func_idx;
> > + unsigned long func_idx;
> >   int ret;
> >   
> >   if (copy_from_user(, user_item_ptr, sizeof(item)))
> > @@ -111,6 +111,9 @@ int i915_query_ioctl(struct drm_device *dev, void 
> > *data, struct drm_file *file)
> I guess you can get rid of this if (item.query_id == 0) then :

Hmm, we could indeed. The choice is whether we want to make it clear
that id=0 is illegal (making it easier to add debug later?)
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Lionel Landwerlin]

On 22/05/18 13:10, Chris Wilson wrote:

nospec quite reasonably asserts that it will never be used with an index
larger than unsigned long (that being the largest possibly index into an
C array). However, our ubi uses the convention of u64 for any large
integer, running afoul of the assertion on 32b. Reduce our index to an
unsigned long, checking for type overflow first.

   drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
   include/linux/compiler.h:339:38: error: call to '__compiletime_assert_119' 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)

Reported-by: kbuild-...@01.org
Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer lookup")
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_query.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 95f9d179afc4..3f502eef2431 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -102,7 +102,7 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
  
  	for (i = 0; i < args->num_items; i++, user_item_ptr++) {

struct drm_i915_query_item item;
-   u64 func_idx;
+   unsigned long func_idx;
int ret;
  
  		if (copy_from_user(, user_item_ptr, sizeof(item)))

@@ -111,6 +111,9 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)

I guess you can get rid of this if (item.query_id == 0) then :

if (item.query_id == 0)
return -EINVAL;
  
+		if (overflows_type(item.query_id - 1, unsigned long))

+   return -EINVAL;
+
func_idx = item.query_id - 1;
  
  		ret = -EINVAL;



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[Intel-gfx] ✗ Fi.CI.BAT: failure for RFC drm/i915: Switch to kernel context before idling at runtime (rev2)

[Patchwork]

== Series Details ==

Series: RFC drm/i915: Switch to kernel context before idling at runtime (rev2)
URL   : https://patchwork.freedesktop.org/series/42321/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4219 -> Patchwork_9079 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9079 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9079, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42321/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9079:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-no-display:
  fi-elk-e7500:   PASS -> FAIL
  fi-snb-2520m:   PASS -> FAIL
  fi-cfl-8700k:   PASS -> FAIL +1
  fi-ivb-3520m:   PASS -> FAIL
  fi-bdw-gvtdvm:  PASS -> FAIL
  fi-pnv-d510:PASS -> FAIL
  fi-hsw-4200u:   PASS -> FAIL +1
  fi-bwr-2160:PASS -> FAIL
  fi-bdw-5557u:   PASS -> FAIL +1
  fi-skl-6260u:   PASS -> FAIL +1
  fi-snb-2600:PASS -> FAIL
  fi-bsw-n3050:   PASS -> FAIL +1
  fi-ivb-3770:PASS -> FAIL
  {fi-kbl-guc}:   PASS -> FAIL
  fi-kbl-7500u:   PASS -> FAIL +1
  fi-blb-e6850:   PASS -> FAIL
  fi-cfl-u:   PASS -> FAIL +1
  fi-gdg-551: PASS -> FAIL
  fi-skl-gvtdvm:  PASS -> FAIL
  fi-ilk-650: PASS -> FAIL

igt@drv_module_reload@basic-reload:
  fi-skl-guc: PASS -> DMESG-FAIL +1
  fi-bdw-gvtdvm:  PASS -> DMESG-FAIL
  fi-kbl-r:   PASS -> DMESG-FAIL +1
  fi-gdg-551: PASS -> DMESG-FAIL
  fi-cfl-8700k:   PASS -> DMESG-FAIL +1
  fi-snb-2520m:   PASS -> DMESG-FAIL
  fi-bxt-dsi: PASS -> DMESG-FAIL +1
  fi-ivb-3520m:   PASS -> DMESG-FAIL
  fi-hsw-4770:PASS -> DMESG-FAIL +1
  {fi-cfl-guc}:   PASS -> DMESG-FAIL +1
  fi-ilk-650: PASS -> DMESG-FAIL
  fi-bsw-n3050:   PASS -> DMESG-FAIL +1
  fi-ivb-3770:PASS -> DMESG-FAIL
  fi-cnl-y3:  PASS -> DMESG-FAIL +1
  fi-cfl-s3:  PASS -> DMESG-FAIL +1
  fi-hsw-4770r:   PASS -> DMESG-FAIL +1
  fi-cfl-u:   PASS -> DMESG-FAIL +1
  fi-kbl-7500u:   PASS -> DMESG-FAIL +1
  fi-bdw-5557u:   PASS -> DMESG-FAIL +1
  fi-kbl-7567u:   PASS -> DMESG-FAIL +1
  {fi-kbl-guc}:   PASS -> DMESG-FAIL
  fi-hsw-4200u:   PASS -> DMESG-FAIL +1
  fi-blb-e6850:   PASS -> DMESG-FAIL
  fi-glk-j4005:   PASS -> DMESG-FAIL +1
  fi-pnv-d510:PASS -> DMESG-FAIL
  fi-elk-e7500:   PASS -> DMESG-FAIL
  fi-skl-gvtdvm:  PASS -> DMESG-FAIL
  fi-snb-2600:PASS -> DMESG-FAIL
  fi-bwr-2160:PASS -> DMESG-FAIL

igt@drv_module_reload@basic-reload-inject:
  fi-skl-6260u:   PASS -> INCOMPLETE
  fi-snb-2600:PASS -> INCOMPLETE
  fi-kbl-7560u:   PASS -> INCOMPLETE
  {fi-kbl-guc}:   PASS -> INCOMPLETE
  fi-hsw-4200u:   PASS -> INCOMPLETE
  fi-skl-6770hq:  PASS -> INCOMPLETE
  fi-kbl-r:   PASS -> INCOMPLETE
  fi-cfl-s3:  PASS -> INCOMPLETE
  fi-gdg-551: PASS -> INCOMPLETE
  fi-ilk-650: PASS -> INCOMPLETE
  fi-bsw-n3050:   PASS -> INCOMPLETE
  fi-kbl-7567u:   PASS -> INCOMPLETE
  fi-ivb-3770:PASS -> INCOMPLETE
  fi-kbl-7500u:   PASS -> INCOMPLETE
  fi-ivb-3520m:   PASS -> INCOMPLETE
  fi-hsw-4770:PASS -> INCOMPLETE
  fi-bdw-5557u:   PASS -> INCOMPLETE
  fi-cfl-8700k:   PASS -> INCOMPLETE
  fi-hsw-peppy:   PASS -> INCOMPLETE
  fi-skl-6600u:   PASS -> INCOMPLETE
  fi-pnv-d510:PASS -> INCOMPLETE
  fi-hsw-4770r:   PASS -> INCOMPLETE
  fi-skl-guc: PASS -> INCOMPLETE
  {fi-cfl-guc}:   PASS -> INCOMPLETE
  fi-blb-e6850:   PASS -> INCOMPLETE
  fi-skl-6700k2:  PASS -> INCOMPLETE
  fi-cfl-u:   PASS -> INCOMPLETE

igt@pm_rpm@basic-pci-d3-state:
  fi-skl-6600u:   PASS -> DMESG-FAIL +1
  fi-kbl-7560u:   PASS -> DMESG-FAIL +1
  fi-byt-n2820:   PASS -> DMESG-FAIL +1
  fi-skl-6770hq:  PASS -> DMESG-FAIL +1
  fi-skl-6700k2:  PASS -> DMESG-FAIL +1
  fi-cnl-psr: PASS -> DMESG-FAIL
  fi-bxt-j4205:   PASS -> DMESG-FAIL +1
  fi-skl-6260u:   PASS -> DMESG-FAIL +1
  fi-hsw-peppy:   PASS -> DMESG-FAIL +1

igt@pm_rpm@basic-rte:
  fi-glk-j4005:   PASS -> FAIL +1
  {fi-cfl-guc}:   PASS -> FAIL +1
  fi-skl-guc: PASS -> FAIL +1
  fi-kbl-7567u:   

[Intel-gfx] [PATCH] drm/i915/query: nospec expects no more than an unsigned long

[Chris Wilson]

nospec quite reasonably asserts that it will never be used with an index
larger than unsigned long (that being the largest possibly index into an
C array). However, our ubi uses the convention of u64 for any large
integer, running afoul of the assertion on 32b. Reduce our index to an
unsigned long, checking for type overflow first.

  drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
  include/linux/compiler.h:339:38: error: call to '__compiletime_assert_119' 
declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)

Reported-by: kbuild-...@01.org
Fixes: 84b510e22da7 ("drm/i915/query: Protect tainted function pointer lookup")
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_query.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 95f9d179afc4..3f502eef2431 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -102,7 +102,7 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
 
for (i = 0; i < args->num_items; i++, user_item_ptr++) {
struct drm_i915_query_item item;
-   u64 func_idx;
+   unsigned long func_idx;
int ret;
 
if (copy_from_user(, user_item_ptr, sizeof(item)))
@@ -111,6 +111,9 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
if (item.query_id == 0)
return -EINVAL;
 
+   if (overflows_type(item.query_id - 1, unsigned long))
+   return -EINVAL;
+
func_idx = item.query_id - 1;
 
ret = -EINVAL;
-- 
2.17.0

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[Intel-gfx] [drm-intel:drm-intel-next-queued 1/2] include/linux/nospec.h:53:2: note: in expansion of macro 'BUILD_BUG_ON'

[kbuild test robot]

tree:   git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head:   1abb70f5955d1a9021f96359a2c6502ca569b68d
commit: 84b510e22da7926522a257cfe295d3695346a0bd [1/2] drm/i915/query: Protect 
tainted function pointer lookup
config: i386-randconfig-x012-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
git checkout 84b510e22da7926522a257cfe295d3695346a0bd
# save the attached .config to linux build tree
make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from include/asm-generic/barrier.h:20:0,
from arch/x86/include/asm/barrier.h:86,
from include/linux/nospec.h:8,
from drivers/gpu/drm/i915/i915_query.c:7:
   drivers/gpu/drm/i915/i915_query.c: In function 'i915_query_ioctl':
>> include/linux/compiler.h:339:38: error: call to '__compiletime_assert_119' 
>> declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
 _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
 ^
   include/linux/compiler.h:319:4: note: in definition of macro 
'__compiletime_assert'
   prefix ## suffix();\
   ^~
   include/linux/compiler.h:339:2: note: in expansion of macro 
'_compiletime_assert'
 _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
 ^~~
   include/linux/build_bug.h:45:37: note: in expansion of macro 
'compiletime_assert'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~
   include/linux/build_bug.h:69:2: note: in expansion of macro 
'BUILD_BUG_ON_MSG'
 BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
 ^~~~
>> include/linux/nospec.h:53:2: note: in expansion of macro 'BUILD_BUG_ON'
 BUILD_BUG_ON(sizeof(_i) > sizeof(long));   \
 ^~~~
>> drivers/gpu/drm/i915/i915_query.c:118:15: note: in expansion of macro 
>> 'array_index_nospec'
   func_idx = array_index_nospec(func_idx,
  ^~
--
   In file included from include/asm-generic/barrier.h:20:0,
from arch/x86/include/asm/barrier.h:86,
from include/linux/nospec.h:8,
from drivers/gpu//drm/i915/i915_query.c:7:
   drivers/gpu//drm/i915/i915_query.c: In function 'i915_query_ioctl':
>> include/linux/compiler.h:339:38: error: call to '__compiletime_assert_119' 
>> declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
 _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
 ^
   include/linux/compiler.h:319:4: note: in definition of macro 
'__compiletime_assert'
   prefix ## suffix();\
   ^~
   include/linux/compiler.h:339:2: note: in expansion of macro 
'_compiletime_assert'
 _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
 ^~~
   include/linux/build_bug.h:45:37: note: in expansion of macro 
'compiletime_assert'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~
   include/linux/build_bug.h:69:2: note: in expansion of macro 
'BUILD_BUG_ON_MSG'
 BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
 ^~~~
>> include/linux/nospec.h:53:2: note: in expansion of macro 'BUILD_BUG_ON'
 BUILD_BUG_ON(sizeof(_i) > sizeof(long));   \
 ^~~~
   drivers/gpu//drm/i915/i915_query.c:118:15: note: in expansion of macro 
'array_index_nospec'
   func_idx = array_index_nospec(func_idx,
  ^~

vim +/BUILD_BUG_ON +53 include/linux/nospec.h

8fa80c503 Will Deacon  2018-02-05  32  
8fa80c503 Will Deacon  2018-02-05  33  /*
f38042033 Dan Williams 2018-01-29  34   * array_index_nospec - sanitize an 
array index after a bounds check
f38042033 Dan Williams 2018-01-29  35   *
f38042033 Dan Williams 2018-01-29  36   * For a code sequence like:
f38042033 Dan Williams 2018-01-29  37   *
f38042033 Dan Williams 2018-01-29  38   * if (index < size) {
f38042033 Dan Williams 2018-01-29  39   * index = 
array_index_nospec(index, size);
f38042033 Dan Williams 2018-01-29  40   * val = array[index];
f38042033 Dan Williams 2018-01-29  41   * }
f38042033 Dan Williams 2018-01-29  42   *
f38042033 Dan Williams 2018-01-29  43   * ...if the CPU speculates past the 
bounds check then
f38042033 Dan Williams 2018-01-29  44   * array_index_nospec() will clamp the 
index within the range of [0,
f38042033 Dan Williams 2018-01-29  45   * size).
f38042033 Dan Williams 2018-01-29  46   */
f38042033 Dan Williams 2018-01-29  47  #define array_index_nospec(index, size)  
\
f38042033 Dan Williams 2018-01-29  48  ({   
   

Re: [Intel-gfx] [PATCH i-g-t 3/3] benchmarks/gem_syslatency: Specify batch duration

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:

While for stressing the system we want to submit as many batches as we
can as that shows us worst case impact on system latency, it is not a
very realistic case. To introduce a bit more realism allow the batches
run for a user defined duration.
Signed-off-by: Chris Wilson 
---
  benchmarks/gem_syslatency.c | 71 ++---
  1 file changed, 67 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d1056773a..45cabe86c 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -51,6 +51,7 @@ static volatile int done;
  
  struct gem_busyspin {

pthread_t thread;
+   unsigned long sz;
unsigned long count;
bool leak;
bool interrupts;
@@ -96,7 +97,8 @@ static void *gem_busyspin(void *arg)
struct gem_busyspin *bs = arg;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
-   const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
+   const unsigned sz =
+   bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
unsigned engines[16];
unsigned nengine;
unsigned engine;
@@ -112,7 +114,7 @@ static void *gem_busyspin(void *arg)
obj[0].handle = gem_create(fd, 4096);
obj[0].flags = EXEC_OBJECT_WRITE;
obj[1].handle = gem_create(fd, sz);
-   gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
+   gem_write(fd, obj[1].handle, bs->sz, , sizeof(bbe));


Hm what was the point in creating large batches here if bbend was always 
first?


  
  	memset(, 0, sizeof(execbuf));

execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
@@ -125,6 +127,12 @@ static void *gem_busyspin(void *arg)
}
  
  	while (!done) {

+   for (int n = 0; n < nengine; n++) {
+   const int m = rand() % nengine;
+   unsigned int tmp = engines[n];
+   engines[n] = engines[m];
+   engines[m] = tmp;


igt_exchange_int? Problem with frameworks getting more featureful is 
easier to forget what is there. :) Or even igt_permute_array?


But what it has to do with batch duration?


+   }
for (int n = 0; n < nengine; n++) {
execbuf.flags &= ~ENGINE_FLAGS;
execbuf.flags |= engines[n];
@@ -134,7 +142,7 @@ static void *gem_busyspin(void *arg)
if (bs->leak) {
gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
obj[1].handle = gem_create(fd, sz);
-   gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
+   gem_write(fd, obj[1].handle, bs->sz, , sizeof(bbe));
}
}
  
@@ -294,6 +302,50 @@ static void *background_fs(void *path)

return NULL;
  }
  
+static unsigned long calibrate_nop(unsigned int target_us,

+  unsigned int tolerance_pct)
+{
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+   const unsigned int loops = 100;
+   struct drm_i915_gem_exec_object2 obj = {};
+   struct drm_i915_gem_execbuffer2 eb =
+   { .buffer_count = 1, .buffers_ptr = (uintptr_t)};
+   struct timespec t_0, t_end;
+   long sz, prev;
+   int fd;
+
+   fd = drm_open_driver(DRIVER_INTEL);
+
+   clock_gettime(CLOCK_MONOTONIC, _0);
+
+   sz = 256 * 1024;
+   do {
+   struct timespec t_start;
+
+   obj.handle = gem_create(fd, sz + sizeof(bbe));
+   gem_write(fd, obj.handle, sz, , sizeof(bbe));
+   gem_execbuf(fd, );
+   gem_sync(fd, obj.handle);
+
+   clock_gettime(CLOCK_MONOTONIC, _start);
+   for (int loop = 0; loop < loops; loop++)
+   gem_execbuf(fd, );
+   gem_sync(fd, obj.handle);
+   clock_gettime(CLOCK_MONOTONIC, _end);
+
+   gem_close(fd, obj.handle);
+
+   prev = sz;
+   sz = loops * sz / elapsed(_start, _end) * 1e3 * target_us;
+   sz = ALIGN(sz, sizeof(uint32_t));
+   } while (elapsed(_0, _end) < 5 ||
+abs(sz - prev) > (sz * tolerance_pct / 100));
+
+   close(fd);
+
+   return sz;
+}


I presume this is a copy so don't have to look into it in detail.


+
  int main(int argc, char **argv)
  {
struct gem_busyspin *busy;
@@ -309,9 +361,10 @@ int main(int argc, char **argv)
int enable_gem_sysbusy = 1;
bool leak = false;
bool interrupts = false;
+   long batch = 0;
int n, c;
  
-	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {

+   while ((c = getopt(argc, argv, "r:t:f:bmni1")) != -1) {
switch (c) {
case '1':
ncpus = 1;
@@ -328,6 +381,10 @@ int main(int argc, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Wait for ELSP submission on restart

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Wait for ELSP submission on restart
URL   : https://patchwork.freedesktop.org/series/43563/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4219 -> Patchwork_9078 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9078 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9078, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43563/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9078:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9078 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-modeset:
  fi-hsw-4770r:   PASS -> DMESG-WARN (fdo#105602)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-cnl-psr: PASS -> FAIL (fdo#103481)


  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4219 -> Patchwork_9078

  CI_DRM_4219: 510bfdf6beaa5f2409cc638442eced81535e63b4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4490: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9078: 78159a7b195f064644a1952c1c892539ae2bf36a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

78159a7b195f drm/i915/execlists: Wait for ELSP submission on restart


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9078/build_32bit_failure.log

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9078/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.

[Mika Kahola]

On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> From: Manasi Navare 
> 
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
> 
> This gets a little tricky for ICL since there is
> no register bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
> 
> Cc: Rodrigo Vivi 
> Cc: Mika Kahola 
> Cc: Paulo Zanoni 
> Signed-off-by: Manasi Navare 
> Signed-off-by: Lucas De Marchi 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  3 ++
>  drivers/gpu/drm/i915/intel_ddi.c  | 26 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> +++
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 ++
>  4 files changed, 97 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7f27fe2e38c7..26903cffabf6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9182,13 +9182,16 @@ enum skl_power_gate {
>  #define  DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
>  #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT(10)
>  #define  DPLL_CFGCR1_QDIV_RATIO(x)   ((x) << 10)
> +#define  DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
>  #define  DPLL_CFGCR1_QDIV_MODE(x)((x) << 9)
>  #define  DPLL_CFGCR1_KDIV_MASK   (7 << 6)
> +#define  DPLL_CFGCR1_KDIV_SHIFT  (6)
>  #define  DPLL_CFGCR1_KDIV(x) ((x) << 6)
>  #define  DPLL_CFGCR1_KDIV_1  (1 << 6)
>  #define  DPLL_CFGCR1_KDIV_2  (2 << 6)
>  #define  DPLL_CFGCR1_KDIV_4  (4 << 6)
>  #define  DPLL_CFGCR1_PDIV_MASK   (0xf << 2)
> +#define  DPLL_CFGCR1_PDIV_SHIFT  (2)
>  #define  DPLL_CFGCR1_PDIV(x) ((x) << 2)
>  #define  DPLL_CFGCR1_PDIV_2  (1 << 2)
>  #define  DPLL_CFGCR1_PDIV_3  (2 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index d8ae82001f83..0d8bed8e2200 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
>   pipe_config->base.adjusted_mode.crtc_clock = dotclock;
>  }
>  
> +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> +   struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + int link_clock = 0;
> + uint32_t pll_id;
> +
> + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> + if (port == PORT_A || port == PORT_B) {
> + if (encoder->type == INTEL_OUTPUT_HDMI)
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> pll_id);
> + else
> + link_clock =
> icl_calc_dp_combo_pll_link(dev_priv,
> + pll_
> id);
> + } else {
> + /* FIXME - Add for MG PLL */
> + WARN(1, "MG PLL clock_get code not implemented
> yet\n");
> + }
> +
> + pipe_config->port_clock = link_clock;
> + ddi_dotclock_get(pipe_config);
> +}
> +
>  static void cnl_ddi_clock_get(struct intel_encoder *encoder,
>     struct intel_crtc_state *pipe_config)
>  {
> @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> intel_encoder *encoder,
>   bxt_ddi_clock_get(encoder, pipe_config);
>   else if (IS_CANNONLAKE(dev_priv))
>   cnl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_ICELAKE(dev_priv))
> + icl_ddi_clock_get(encoder, pipe_config);
>  }
>  
>  void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 383fbc15113d..3cc837f74ffb 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
>   return true;
>  }
>  
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> +    uint32_t pll_id)
> +{
> + uint32_t cfgcr0, cfgcr1;
> + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> dco_fraction;
> + const struct skl_wrpll_params *params;
> + int index, n_entries, link_clock = 0;
> +
> + /* Read back values from DPLL CFGCR registers */
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> +
> +