[Intel-gfx] [drm-intel:topic/core-for-CI 7/8] backtracetest.c:undefined reference to `save_stack_trace'
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI head: e2ea2db1734a0e38b89e4d706b5f9ad9f73b1543 commit: 72041f9847abb05b9d4d7dea17631b579191ca99 [7/8] RFC: debugobjects: capture stack traces at _init() time config: m68k-allyesconfig (attached as .config) compiler: m68k-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 72041f9847abb05b9d4d7dea17631b579191ca99 # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=m68k All errors (new ones prefixed by >>): kernel/backtracetest.o: In function `backtrace_regression_test': >> backtracetest.c:(.text+0xd8): undefined reference to `save_stack_trace' mm/slub.o: In function `set_track': slub.c:(.text+0x12d2): undefined reference to `save_stack_trace' fs/btrfs/ref-verify.o: In function `btrfs_ref_tree_mod': >> ref-verify.c:(.text+0x92e): undefined reference to `save_stack_trace' lib/debugobjects.o: In function `save_stack.isra.0': debugobjects.c:(.text+0x9f2): undefined reference to `save_stack_trace' --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Wrap around the tail offset before setting ring->tail (rev2)
== Series Details == Series: drm/i915: Wrap around the tail offset before setting ring->tail (rev2) URL : https://patchwork.freedesktop.org/series/44500/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4296_full -> Patchwork_9249_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9249_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9249_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9249_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: SKIP -> PASS +2 igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: shard-snb: SKIP -> PASS igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: shard-snb: PASS -> SKIP +4 == Known issues == Here are the changes found in Patchwork_9249_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) +1 igt@gem_ctx_switch@basic-all-light: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@gem_eio@hibernate: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363, fdo#102887) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) +1 igt@kms_flip_tiling@flip-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_setmode@basic: shard-hsw: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@2x-flip-vs-blocking-wf-vblank: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105189) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4296 -> Patchwork_9249 CI_DRM_4296: 3639b8f5b23b8e777ba46501b4fd257e099bd13c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4513: 7b6838781441cfbc7f6c18f421f127dfb02b44cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9249: f6a0dfb7aab764d47f615642bfd34dd436f85439 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9249/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
== Series Details == Series: drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range URL : https://patchwork.freedesktop.org/series/44501/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9248_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9248_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9248_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9248_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +2 igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9248_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: PASS -> FAIL (fdo#104724, fdo#103925) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: FAIL (fdo#100368) -> PASS +1 shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#104724, fdo#103167) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9248 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9248: 55bc0aa5c748cc7113a250346f86825b6cc629d4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9248/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/perf_pmu: Disable accuracy tests for guc
guc also uses timer-based sampling and cannot reliably hit our accuracy
requirements for the test, so skip.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4570f926d..61e83bf7b 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1507,6 +1507,17 @@ static void __rearm_spin_batch(igt_spin_t *spin)
#define assert_within(x, ref, tolerance) \
__assert_within(x, ref, tolerance, tolerance)
+static bool uses_timer_sampling(int gem_fd)
+{
+ if (!gem_has_execlists(gem_fd))
+ return true;
+
+ if (gem_has_guc_submission(gem_fd))
+ return true;
+
+ return false;
+}
+
static void
accuracy(int gem_fd, const struct intel_execution_engine2 *e,
unsigned long target_busy_pct)
@@ -1524,7 +1535,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2
*e,
int fd;
/* Sampling platforms cannot reach the high accuracy criteria. */
- igt_require(gem_has_execlists(gem_fd));
+ igt_require(!uses_timer_sampling(gem_fd));
while (idle_us < 2500) {
busy_us *= 2;
--
2.17.1
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Re: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R
>Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>
>Use the hardcoded tables provided by our spec.
>
>Signed-off-by: Paulo Zanoni
>---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 -
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>index 72f15e727d07..8a34733de1ea 100644
>--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>icl_dp_combo_pll_19_2MHz_values[] = {
> .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, };
>
>+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>+ .dco_integer = 0x151, .dco_fraction = 0x4000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
>+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
>+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
> static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int
> clock,
> struct skl_wrpll_params *pll_params) { @@ -
>2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private
>*dev_priv, int clock,
> return true;
> }
>
>+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
>+ struct skl_wrpll_params *pll_params) {
>+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
>+ return true;
>+}
>+
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder, int clock,
> struct intel_dpll_hw_state *pll_state) @@ -
>2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> uint32_t cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
>+ bool is_tbt = encoder->port >= PORT_C;
> bool ret;
>
>- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>+ if (is_tbt)
>+ ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
>+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
> else
> ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); @@ -
>2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
>
> cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
>pll_params.dco_integer;
>+ if (is_tbt)
>+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
Paulo,
TBT has some TBT specific CFGCR0 registers which needs to be configured here.
Anusha
> cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>--
>2.14.3
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/gtt: Remove redundant hsw_mm_switch()
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Remove redundant hsw_mm_switch() URL : https://patchwork.freedesktop.org/series/44491/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9245_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9245_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9245_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9245_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +3 igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9245_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763) igt@kms_flip@2x-dpms-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) Possible fixes igt@drv_selftest@live_gtt: shard-apl: FAIL (fdo#105347) -> PASS igt@gem_eio@hibernate: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#106509, fdo#105454) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#104724, fdo#103167) -> PASS Warnings igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> FAIL (fdo#105347) fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9245 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9245: e73d2cb0cd2cfa87fdaa9a854e7a8a30cfaad5a4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9245/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wrap around the tail offset before setting ring->tail (rev2)
== Series Details == Series: drm/i915: Wrap around the tail offset before setting ring->tail (rev2) URL : https://patchwork.freedesktop.org/series/44500/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4296 -> Patchwork_9249 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9249 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9249, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44500/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9249: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9249 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-skl-guc: PASS -> FAIL (fdo#104724, fdo#103191) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 == Participating hosts (41 -> 38) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4296 -> Patchwork_9249 CI_DRM_4296: 3639b8f5b23b8e777ba46501b4fd257e099bd13c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4513: 7b6838781441cfbc7f6c18f421f127dfb02b44cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9249: f6a0dfb7aab764d47f615642bfd34dd436f85439 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f6a0dfb7aab7 drm/i915: Wrap around the tail offset before setting ring->tail == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9249/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH xf86-video-intel] sna/video/sprite: Remove the XV_ALWAYS_ON_TOP restriction for SKL+ scaling
From: Ville Syrjälä
On SKL+ the dst colorkey is enabled on the primary plane instead of the
sprite plane. That means the restriction of scaling vs. keying doesn't
actually apply here as we never scale the primary. So let's remove
the requirement of having XV_ALWAYS_ON_TOP enabled to get hw scaling.
Signed-off-by: Ville Syrjälä
---
src/sna/sna_video_sprite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sna/sna_video_sprite.c b/src/sna/sna_video_sprite.c
index f713abcb9151..8b7ae8ae9e75 100644
--- a/src/sna/sna_video_sprite.c
+++ b/src/sna/sna_video_sprite.c
@@ -49,7 +49,7 @@
#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2
subsampled Cr:Cb plane */
#define has_hw_scaling(sna, video) ((sna)->kgem.gen < 071 || \
- ((sna)->kgem.gen >= 0110 &&
(video)->AlwaysOnTop))
+ (sna)->kgem.gen >= 0110)
#define LOCAL_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct
local_mode_set_plane)
--
2.16.4
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[Intel-gfx] [PATCH i-g-t] igt/gem_mmap_gtt: Checking tiling pattern requires known swizzling
As the swizzling is baked into the tiling pattern, the swizzling has to
be consistent across the entire GTT mmap for our tests to work. However,
under L-shaped memory configurations on older architectures, the
swizzling varied depending on which region the page found itself in --
invalidating our assumptions and ability to predict the tiling pattern.
Reported-by: Adric Blake
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106848
Signed-off-by: Chris Wilson
---
tests/gem_mmap_gtt.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c
index 6a332b254..fd60b8ff8 100644
--- a/tests/gem_mmap_gtt.c
+++ b/tests/gem_mmap_gtt.c
@@ -445,6 +445,24 @@ static int max_tile_width(uint32_t devid, int tiling)
return 8 << 10;
}
+static bool known_swizzling(int fd, uint32_t handle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {
+ .handle = handle,
+ };
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg))
+ return false;
+
+ return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
static void
test_huge_bo(int fd, int huge, int tiling)
{
@@ -488,6 +506,8 @@ test_huge_bo(int fd, int huge, int tiling)
bo = gem_create(fd, PAGE_SIZE);
if (tiling)
igt_require(__gem_set_tiling(fd, bo, tiling, pitch) == 0);
+ igt_require(known_swizzling(fd, bo));
+
linear_pattern = gem_mmap__gtt(fd, bo, PAGE_SIZE,
PROT_READ | PROT_WRITE);
for (i = 0; i < PAGE_SIZE; i++)
--
2.17.1
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[Intel-gfx] [PATCH v2] drm/i915: Wrap around the tail offset before setting ring->tail
The HW only accepts offsets within ring->size, and fails peculiarly if
the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we
set ring->head/ring->tail we want to make sure it is within value (using
intel_ring_wrap()).
v2: Double check execlists as well
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c| 6 --
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 12
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 091e28f0e024..3e008adf5a01 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1413,6 +1413,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
i915_ggtt_offset(ce->ring->vma);
+ GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
ce->state->obj->pin_global++;
@@ -2001,9 +2002,10 @@ static void execlists_reset(struct intel_engine_cs
*engine,
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
- regs[CTX_RING_HEAD + 1] = request->postfix;
- request->ring->head = request->postfix;
+ request->ring->head = intel_ring_wrap(request->ring, request->postfix);
+ regs[CTX_RING_HEAD + 1] = request->ring->head;
+
intel_ring_update_space(request->ring);
/* Reset WaIdleLiteRestore:bdw,skl as well */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6ac3b65373fe..9fac0e0f078e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -496,6 +496,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
DRM_DEBUG_DRIVER("%s initialization failed [head=%08x],
fudging\n",
engine->name, I915_READ_HEAD(engine));
+ /* Check that the ring offsets point within the ring! */
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
+
intel_ring_update_space(ring);
I915_WRITE_HEAD(engine, ring->head);
I915_WRITE_TAIL(engine, ring->tail);
@@ -1064,6 +1068,7 @@ int intel_ring_pin(struct intel_ring *ring,
void intel_ring_reset(struct intel_ring *ring, u32 tail)
{
+ tail = intel_ring_wrap(ring, tail);
ring->tail = tail;
ring->head = tail;
ring->emit = tail;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b44c67849749..1d8140ac2016 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -805,6 +805,18 @@ static inline u32 intel_ring_wrap(const struct intel_ring
*ring, u32 pos)
return pos & (ring->size - 1);
}
+static inline bool
+intel_ring_offset_valid(const struct intel_ring *ring, u32 pos)
+{
+ if (pos & -ring->size) /* must be strictly within the ring */
+ return false;
+
+ if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
+ return false;
+
+ return true;
+}
+
static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
{
/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Add warn about unsupported CDCLK rates (rev3)
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev3) URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9244_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9244_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9244_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9244_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd1: shard-kbl: PASS -> SKIP +1 igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9244_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: PASS -> FAIL (fdo#105189) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105189) igt@kms_flip@plain-flip-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS shard-apl: FAIL (fdo#105347) -> PASS igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: FAIL (fdo#100368) -> PASS +1 shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#103167, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9244 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9244: 38bcd836f3574fc1949555dc0cb11e8a9ad25c82 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9244/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
Quoting Matthew Auld (2018-06-08 18:54:15) > On 8 June 2018 at 18:32, Chris Wilson wrote: > > When we want to unwind an error when allocating the PD for gen6, we call > > gen6_ppgtt_clear_range() telling to clear upto the PD we've previously > > cleared. However, we passed it the incorrect length, passing it the > > endpoint instead. Fortunately, as the start was always 0, this has no > > impact today, but tomorrow we want to start using non-zero origins. > > > > Reported-by: Matthew Auld > > Signed-off-by: Chris Wilson > > Cc: Joonas Lahtinen > > Cc: Mika Kuoppala > > Cc: Matthew Auld > Reviewed-by: Matthew Auld It was a good catch. Pushed with thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Fix sprite destination colorkeying on SKL+
On Tue, Jun 05, 2018 at 08:10:36AM +, Lisovskiy, Stanislav wrote:
> On Tue, 2018-05-29 at 21:28 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On SKL+ the dst colorkey must be configured on the lower
> > plane that contains the colorkey. This is in contrast to
> > most earlier platforms where the dst colorkey is configured
> > on the plane above.
> >
> > The hardware will peform dst keying only between two immediately
> > adjacent (in zorder) planes. Plane 1 will be keyed against plane 0,
> > plane 2 againts plane 1, and so on. There is no way to key arbitrary
> > planes against plane 0. Thus offering dst color keying on plane 2+
> > is pointless. In fact it can be harmful since enabling dst keying on
> > more than one plane on the same pipe leads to only the top-most of
> > the planes performing the keying. For any plane lower in zorder the
> > dst key enable is simply ignored.
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Stanislav Lisovskiy
>
> > ---
> > drivers/gpu/drm/i915/intel_sprite.c | 63
> > +++--
> > 1 file changed, 60 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index ee23613f9fd4..6164c2ca20c3 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1071,6 +1071,36 @@ intel_check_sprite_plane(struct intel_plane
> > *plane,
> > return 0;
> > }
> >
> > +static bool has_dst_key_in_primary_plane(struct drm_i915_private
> > *dev_priv)
> > +{
> > + return INTEL_GEN(dev_priv) >= 9;
> > +}
> > +
> > +static void intel_plane_set_ckey(struct intel_plane_state
> > *plane_state,
> > +const struct
> > drm_intel_sprite_colorkey *set)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >base.plane);
> > + struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > +
> > + *key = *set;
> > +
> > + /*
> > +* We want src key enabled on the
> > +* sprite and not on the primary.
> > +*/
> > + if (plane->id == PLANE_PRIMARY &&
> > + set->flags & I915_SET_COLORKEY_SOURCE)
> > + key->flags = 0;
> > +
> > + /*
> > +* On SKL+ we want dst key enabled on
> > +* the primary and not on the sprite.
> > +*/
> > + if (plane->id != PLANE_PRIMARY &&
The 'INTEL_GEN(dev_priv) >= 9' check that was supposed to be here ended
up in the wrong patch. I moved it over while applying this to avoid
breaking the pre-SKL sprites. Only caught it when glancing at the
resulting code before pushing. Might be time to write some real
colorkeying igts...
Patch pushed to dinq. Thanks for the review.
> > + set->flags & I915_SET_COLORKEY_DESTINATION)
> > + key->flags = 0;
> > +}
> > +
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
== Series Details == Series: drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range URL : https://patchwork.freedesktop.org/series/44501/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9248 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9248 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9248, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44501/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9248: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9248 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-elk-e7500: PASS -> DMESG-WARN (fdo#105225) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-elk-e7500: SKIP -> INCOMPLETE (fdo#103989) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#105225 https://bugs.freedesktop.org/show_bug.cgi?id=105225 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (41 -> 36) == Missing(5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-gvtdvm fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9248 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9248: 55bc0aa5c748cc7113a250346f86825b6cc629d4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 55bc0aa5c748 drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9248/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev3)
== Series Details == Series: series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev3) URL : https://patchwork.freedesktop.org/series/44486/ State : failure == Summary == Applying: drm/i915: Apply batch location restrictions before pinning Applying: drm/i915/ringbuffer: Brute force context restore Applying: drm/i915/ringbuffer: Fix context restore upon reset error: Failed to merge in the changes. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_gtt.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c Patch failed at 0003 drm/i915/ringbuffer: Fix context restore upon reset The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wrap around the tail offset before setting ring->tail
== Series Details == Series: drm/i915: Wrap around the tail offset before setting ring->tail URL : https://patchwork.freedesktop.org/series/44500/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9246 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9246 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9246, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44500/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9246: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9246 that come from known issues: === IGT changes === Issues hit igt@kms_chamelium@hdmi-hpd-fast: fi-kbl-7500u: SKIP -> FAIL (fdo#103841, fdo#102672) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#102614, fdo#106103) fi-hsw-4200u: PASS -> DMESG-FAIL (fdo#102614, fdo#106103) igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: FAIL (fdo#102575) -> PASS igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103 == Participating hosts (41 -> 38) == Additional (1): fi-bxt-dsi Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9246 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9246: ab408babd7e5f765e2d0fe07653bcfdd10f9a859 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ab408babd7e5 drm/i915: Wrap around the tail offset before setting ring->tail == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9246/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
== Series Details == Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h URL : https://patchwork.freedesktop.org/series/44488/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9242_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9242_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9242_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9242_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-vebox: shard-kbl: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_9242_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@gem_exec_suspend@basic-s3: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_cursor_crc@cursor-64x64-random: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +2 igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@prime_vgem@basic-fence-flip: shard-glk: PASS -> FAIL (fdo#104008) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS shard-apl: FAIL (fdo#105347) -> PASS igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560) -> PASS igt@gem_eio@suspend: shard-snb: INCOMPLETE (fdo#105411) -> PASS +1 igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#103167, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9242 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9242: 503bc7e600b180a943cb72eed79622d45fd5f516 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9242/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
On 8 June 2018 at 18:32, Chris Wilson wrote: > When we want to unwind an error when allocating the PD for gen6, we call > gen6_ppgtt_clear_range() telling to clear upto the PD we've previously > cleared. However, we passed it the incorrect length, passing it the > endpoint instead. Fortunately, as the start was always 0, this has no > impact today, but tomorrow we want to start using non-zero origins. > > Reported-by: Matthew Auld > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
When we want to unwind an error when allocating the PD for gen6, we call gen6_ppgtt_clear_range() telling to clear upto the PD we've previously cleared. However, we passed it the incorrect length, passing it the endpoint instead. Fortunately, as the start was always 0, this has no impact today, but tomorrow we want to start using non-zero origins. Reported-by: Matthew Auld Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6ac6520b6e9c..ddd8a16d0246 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1931,7 +1931,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, return 0; unwind_out: - gen6_ppgtt_clear_range(vm, from, start); + gen6_ppgtt_clear_range(vm, from, start - from); return -ENOMEM; } -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/ringbuffer: Fix context restore upon reset
The discovery with trying to enable full-ppgtt was that we were
completely failing to the load both the mm and context following the
reset. Although we were performing mmio to set the PP_DIR (per-process
GTT) and CCID (context), these were taking no effect (the assumption was
that this would trigger reload of the context and restore the page
tables). It was not until we performed the LRI + MI_SET_CONTEXT in a
following context switch would anything occur.
Since we are then required to reset the context image and PP_DIR using
CS commands, we place those commands into every batch. The hardware
should recognise the no-ops and eliminate the expensive context loads,
but we still have to pay the cost of using cross-powerwell register
writes. In practice, this has no effect on actual context switch times,
and only adds a few hundred nanoseconds to no-op switches. We can improve
the latter by eliminating the w/a around known no-op switches, but there
is an ulterior motive to keeping them.
Always emitting the context switch at the beginning of the request (and
relying on HW to skip unneeded switches) does have one key advantage.
Should we implement request reordering on Haswell, we will not know in
advance what the previous executing context was on the GPU and so we
would not be able to elide the MI_SET_CONTEXT commands ourselves and
always have to emit them. Having our hand forced now actually prepares
us for later.
v2: Sandybridge has to agree to use LRI as well.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 45 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 -
drivers/gpu/drm/i915/i915_request.c | 2 +
drivers/gpu/drm/i915/i915_request.h | 3 +
drivers/gpu/drm/i915/i915_trace.h | 33 ---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 124 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 9 --
8 files changed, 64 insertions(+), 157 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ca747a82a00c..6b93bac911b5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1712,45 +1712,6 @@ static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt,
wmb();
}
-static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
-{
- GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
- return ppgtt->pd.base.ggtt_offset << 10;
-}
-
-static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
- struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- u32 *cs;
-
- /* NB: TLBs must be flushed and invalidated before a switch */
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- *cs++ = MI_LOAD_REGISTER_IMM(2);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
- *cs++ = PP_DIR_DCLV_2G;
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
- *cs++ = get_pd_offset(ppgtt);
- *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
-
- return 0;
-}
-
-static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
- struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- struct drm_i915_private *dev_priv = rq->i915;
-
- I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
- I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
- return 0;
-}
-
static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
@@ -2024,12 +1985,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.dma = &i915->drm.pdev->dev;
ppgtt->vm.pte_encode = ggtt->vm.pte_encode;
- if (IS_GEN6(i915))
- ppgtt->switch_mm = gen6_mm_switch;
- else if (IS_GEN7(i915))
- ppgtt->switch_mm = gen7_mm_switch;
- else
- BUG();
err = gen6_ppgtt_alloc(ppgtt);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 16307ba7e303..e70f6abcd0f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -406,8 +406,6 @@ struct i915_hw_ppgtt {
gen6_pte_t __iomem *pd_addr;
- int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
-struct i915_request *rq);
void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
};
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f187250e60c6..9092f5464c24 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -817,6 +817,8 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
/* K
[Intel-gfx] [PATCH] drm/i915: Wrap around the tail offset before setting ring->tail
The HW only accepts offsets within ring->size, and fails peculiarly if
the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we
set ring->head/ring->tail we want to make sure it is within value (using
intel_ring_wrap()).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6ac3b65373fe..9fac0e0f078e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -496,6 +496,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
DRM_DEBUG_DRIVER("%s initialization failed [head=%08x],
fudging\n",
engine->name, I915_READ_HEAD(engine));
+ /* Check that the ring offsets point within the ring! */
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
+
intel_ring_update_space(ring);
I915_WRITE_HEAD(engine, ring->head);
I915_WRITE_TAIL(engine, ring->tail);
@@ -1064,6 +1068,7 @@ int intel_ring_pin(struct intel_ring *ring,
void intel_ring_reset(struct intel_ring *ring, u32 tail)
{
+ tail = intel_ring_wrap(ring, tail);
ring->tail = tail;
ring->head = tail;
ring->emit = tail;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b44c67849749..1d8140ac2016 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -805,6 +805,18 @@ static inline u32 intel_ring_wrap(const struct intel_ring
*ring, u32 pos)
return pos & (ring->size - 1);
}
+static inline bool
+intel_ring_offset_valid(const struct intel_ring *ring, u32 pos)
+{
+ if (pos & -ring->size) /* must be strictly within the ring */
+ return false;
+
+ if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
+ return false;
+
+ return true;
+}
+
static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
{
/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
Quoting Chris Wilson (2018-06-08 17:36:28) > Quoting Patchwork (2018-06-08 17:23:38) > > == Series Details == > > > > Series: series starting with [01/18] drm/i915: Apply batch location > > restrictions before pinning (rev2) > > URL : https://patchwork.freedesktop.org/series/44486/ > > State : failure > > > > == Summary == > > > > = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9241_full = > > > > == Summary - FAILURE == > > > > Serious unknown changes coming with Patchwork_9241_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_9241_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > == Possible new issues == > > > > Here are the unknown changes that may have been introduced in > > Patchwork_9241_full: > > > > === IGT changes === > > > > Possible regressions > > > > igt@drv_selftest@live_hangcheck: > > shard-snb: PASS -> DMESG-FAIL > > shard-hsw: PASS -> DMESG-FAIL > > Darn it! I expected the SNB fail after realising the mistake over its > missing mmio. But Haswell? You were the chosen one! Ok, spotted it; a missing intel_ring_wrap(). Phew. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
Quoting Patchwork (2018-06-08 17:23:38) > == Series Details == > > Series: series starting with [01/18] drm/i915: Apply batch location > restrictions before pinning (rev2) > URL : https://patchwork.freedesktop.org/series/44486/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9241_full = > > == Summary - FAILURE == > > Serious unknown changes coming with Patchwork_9241_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_9241_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_9241_full: > > === IGT changes === > > Possible regressions > > igt@drv_selftest@live_hangcheck: > shard-snb: PASS -> DMESG-FAIL > shard-hsw: PASS -> DMESG-FAIL Darn it! I expected the SNB fail after realising the mistake over its missing mmio. But Haswell? You were the chosen one! Other than that, it looked good and piglit was happy too. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
== Series Details == Series: series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2) URL : https://patchwork.freedesktop.org/series/44486/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9241_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9241_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9241_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9241_full: === IGT changes === Possible regressions igt@drv_selftest@live_hangcheck: shard-snb: PASS -> DMESG-FAIL shard-hsw: PASS -> DMESG-FAIL Warnings igt@gem_mocs_settings@mocs-rc6-render: shard-kbl: PASS -> SKIP +1 igt@gem_ppgtt@flink-and-close-vma-leak: shard-hsw: SKIP -> PASS +2 igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9241_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@dpms-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_gtt: shard-apl: FAIL (fdo#105347) -> PASS igt@gem_eio@suspend: shard-snb: INCOMPLETE (fdo#105411) -> PASS +1 igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS +1 igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#103167, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9241 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9241: bf7d463b083bc7108ce2c73d6669a72d997b5676 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9241/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
On 06/08/2018 06:31 AM, Imre Deak wrote:
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn
off for ~400uS during a normal resolution change. The HDMI retimer on
the GLK NUC appears to require at least a full frame of quiet time
before a new faster clock can be correctly sync'd.
The worst case scenario appears to be 23.98Hz modes which requires a
wait of 41.25ms. Add a quirk to the driver for GLK NUC that waits
42ms.
Just to understand better the failure mode: IIUC without the WA the HDMI
clock line is inactive for ~400us when switching modes (which would
depend on kernel timing) and the retimer chip needs at least 42ms idle
time at least when switching to certain modes.
If switching from 30Hz to 50/60Hz you would only need a delay of 34ms,
but I chose to keep the quirk simple and use the worst case (23.98Hz)
delay of 42ms.
Is there a way to recover the chip from the bad state? By doing a new
off/on modeset with enough idle time, or resetting the chip?
Just an off/on mode set with enough delay will bring the chip out of the
bad state.
-Clint
--Imre
Cc: Imre Deak
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 14 ++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c407366..628491d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -645,6 +645,7 @@ enum intel_sbi_destination {
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
#define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
struct intel_fbdev;
struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b344e0f..61b41c3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1784,6 +1784,9 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
+/* Quirk time computed based on 24fps frame time of 41.25ms */
+#define DDI_DISABLED_QUIRK_TIME 42
+
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder)
{
@@ -1793,6 +1796,11 @@ void intel_ddi_disable_transcoder_func(struct
drm_i915_private *dev_priv,
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+ if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
+ msleep(DDI_DISABLED_QUIRK_TIME);
+ DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+ }
}
int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ed29219..0d07c37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14740,6 +14740,17 @@ static void quirk_increase_t12_delay(struct drm_device
*dev)
DRM_INFO("Applying T12 delay quirk\n");
}
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+ DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14826,6 +14837,9 @@ static int intel_dmi_reverse_brightness(const struct
dmi_system_id *id)
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+ /* GeminiLake NUC */
+ { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
};
static void intel_init_quirks(struct drm_device *dev)
--
1.9.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: fix guest virtual PCH detection on non-PCH systems
== Series Details == Series: series starting with [1/5] drm/i915: fix guest virtual PCH detection on non-PCH systems URL : https://patchwork.freedesktop.org/series/44484/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9239_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9239_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9239_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9239_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-blt: shard-kbl: PASS -> SKIP igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9239_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: shard-hsw: PASS -> FAIL (fdo#104873) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#105189) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS shard-apl: FAIL (fdo#105347) -> PASS igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560) -> PASS igt@gem_eio@hibernate: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-snb: FAIL (fdo#103167, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9239 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9239: 0b3ae319aae1ae31545d9cd3831377a33f3267be @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9239/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gtt: Remove redundant hsw_mm_switch()
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Remove redundant hsw_mm_switch() URL : https://patchwork.freedesktop.org/series/44491/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9245 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44491/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9245 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-wf_vblank: fi-cfl-s3: PASS -> FAIL (fdo#100368) igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) igt@prime_vgem@basic-busy-default: fi-cnl-y3: NOTRUN -> INCOMPLETE (fdo#105086) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 37) == Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9245 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9245: e73d2cb0cd2cfa87fdaa9a854e7a8a30cfaad5a4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e73d2cb0cd2c drm/i915/gtt: Remove vgpu check for gen6 7ef9caf00546 drm/i915/gtt: Remove redundant hsw_mm_switch() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9245/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Add warn about unsupported CDCLK rates (rev3)
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev3) URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9244 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44421/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_9244 that come from known issues: === IGT changes === Issues hit igt@prime_vgem@basic-fence-flip: fi-kbl-7500u: PASS -> FAIL (fdo#104008) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106097, fdo#106000) -> PASS fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 36) == Missing(5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq fi-pnv-d510 == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9244 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9244: 38bcd836f3574fc1949555dc0cb11e8a9ad25c82 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 38bcd836f357 drm/i915/skl: Add warn about unsupported CDCLK rates == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9244/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/gtt: Remove vgpu check for gen6
Since vgpu is not supported on Haswell or any other gen6/7, we do not need to check and act upon it's enablement. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index b4d92d0cdc76..ca747a82a00c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2024,7 +2024,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) ppgtt->vm.dma = &i915->drm.pdev->dev; ppgtt->vm.pte_encode = ggtt->vm.pte_encode; - if (intel_vgpu_active(i915) || IS_GEN6(i915)) + if (IS_GEN6(i915)) ppgtt->switch_mm = gen6_mm_switch; else if (IS_GEN7(i915)) ppgtt->switch_mm = gen7_mm_switch; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/gtt: Remove redundant hsw_mm_switch()
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
1 file changed, 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6ac6520b6e9c..b4d92d0cdc76 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1718,28 +1718,6 @@ static inline u32 get_pd_offset(struct i915_hw_ppgtt
*ppgtt)
return ppgtt->pd.base.ggtt_offset << 10;
}
-static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
-struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- u32 *cs;
-
- /* NB: TLBs must be flushed and invalidated before a switch */
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- *cs++ = MI_LOAD_REGISTER_IMM(2);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
- *cs++ = PP_DIR_DCLV_2G;
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
- *cs++ = get_pd_offset(ppgtt);
- *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
-
- return 0;
-}
-
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
@@ -2048,8 +2026,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.pte_encode = ggtt->vm.pte_encode;
if (intel_vgpu_active(i915) || IS_GEN6(i915))
ppgtt->switch_mm = gen6_mm_switch;
- else if (IS_HASWELL(i915))
- ppgtt->switch_mm = hsw_mm_switch;
else if (IS_GEN7(i915))
ppgtt->switch_mm = gen7_mm_switch;
else
--
2.17.1
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h
On Fri, 08 Jun 2018 15:42:01 +0200, Mika Kuoppala wrote: Carve out chipset definitions into new intel_chipset.h Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 194 + drivers/gpu/drm/i915/intel_chipset.h | 202 +++ 2 files changed, 203 insertions(+), 193 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_chipset.h diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c4073666f1ca..e659c89198d2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -58,6 +58,7 @@ #include "i915_utils.h" #include "intel_bios.h" +#include "intel_chipset.h" #include "intel_device_info.h" #include "intel_display.h" #include "intel_dpll_mgr.h" @@ -2309,199 +2310,6 @@ intel_info(const struct drm_i915_private *dev_priv) #define INTEL_INFO(dev_priv)intel_info((dev_priv)) -#define INTEL_GEN(dev_priv)((dev_priv)->info.gen) -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) - -#define REVID_FOREVER 0xff -#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) - -#define GEN_FOREVER (0) - -#define INTEL_GEN_MASK(s, e) ( \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ - GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ - (s) != GEN_FOREVER ? (s) - 1 : 0) \ -) - -/* - * Returns true if Gen is in inclusive range [Start, End]. - * - * Use GEN_FOREVER for unbound start and or end. - */ -#define IS_GEN(dev_priv, s, e) \ - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e - -/* - * Return true if revision is in range [since,until] inclusive. - * - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. - */ -#define IS_REVID(p, since, until) \ - (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) - -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) - -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001) -#define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ -(dev_priv)->info.gt == 1) -#define IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile) -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ -((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xb ||\ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -/* ULX machines are also considered ULT. */ -#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Add warn about unsupported CDCLK rates (rev2)
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates (rev2) URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9243 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9243 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9243, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44421/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9243: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9243 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-skl-6770hq: PASS -> FAIL (fdo#103481) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 38) == Additional (1): fi-bxt-dsi Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9243 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9243: ba6a0a473aee6cd0a690ba05c03a486148baf2a6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ba6a0a473aee drm/i915/skl: Add warn about unsupported CDCLK rates == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9243/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/18] drm/i915/gtt: Lazily allocate page directories for gen7
Quoting Matthew Auld (2018-06-08 15:37:43) > Ah, in gen6_alloc_va_range() I think we now need: > > unwind_out: > - gen6_ppgtt_clear_range(vm, from, start); > + gen6_ppgtt_clear_range(vm, from, start - from); You are very right. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/skl: Add warn about unsupported CDCLK rates
While checking workarounds related to the CDCLK PLL, I noticed that the DMC firmware bits for WA#1183 are missing for SKL. After that I clarified with HW people that it's not needed on SKL, since it doesn't support eDP1.4 which would be the only thing requiring the problematic CDCLK clock rates. So in theory we shouldn't ever choose these frequencies, but add an assert in any case for catching such cases and for documentation. v2: - Move the check to skl_set_cdclk and warn whenever using the corresponding VCO freq. (Ville) v3: - Actually check for the platform. (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_cdclk.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 704ddb4d3ca7..8ed7bd052e46 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -991,6 +991,16 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, u32 freq_select, cdclk_ctl; int ret; + /* +* Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are +* unsupported on SKL. In theory this should never happen since only +* the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not +* supported on SKL either, see the above WA. WARN whenever trying to +* use the corresponding VCO freq as that always leads to using the +* minimum 308MHz CDCLK. +*/ + WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 864); + mutex_lock(&dev_priv->pcu_lock); ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, -- 2.13.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/18] drm/i915/gtt: Lazily allocate page directories for gen7
On 8 June 2018 at 13:55, Chris Wilson wrote:
> As we were only supporting aliasing_ppgtt on gen7 for some time, we
> saved a few checks by preallocating the page directories on creation.
> However, since we need 2MiB of page directories for each ppgtt, to
> support arbitrary numbers of user contexts, we need to be more prudent
> in our allocations, and defer the page allocation until it is used. We
> don't recover unused pages yet as we found that doing so on the fly
> (i.e. altering TLB entries) would confuse the GPU.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
> Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++--
> 1 file changed, 26 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d5af099939f6..e611884596a6 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -190,11 +190,19 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
> *dev_priv,
> return 1;
> }
>
> -static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
> - enum i915_cache_level cache_level,
> - u32 unused)
> +static int ppgtt_bind_vma(struct i915_vma *vma,
> + enum i915_cache_level cache_level,
> + u32 unused)
> {
> u32 pte_flags;
> + int err;
> +
> + if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
> + err = vma->vm->allocate_va_range(vma->vm,
> +vma->node.start, vma->size);
> + if (err)
> + return err;
> + }
>
> /* Currently applicable only to VLV */
> pte_flags = 0;
> @@ -206,22 +214,6 @@ static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
> return 0;
> }
>
> -static int gen8_ppgtt_bind_vma(struct i915_vma *vma,
> - enum i915_cache_level cache_level,
> - u32 unused)
> -{
> - int ret;
> -
> - if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
> - ret = vma->vm->allocate_va_range(vma->vm,
> -vma->node.start, vma->size);
> - if (ret)
> - return ret;
> - }
> -
> - return gen6_ppgtt_bind_vma(vma, cache_level, unused);
> -}
> -
> static void ppgtt_unbind_vma(struct i915_vma *vma)
> {
> vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
> @@ -1622,7 +1614,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
> drm_i915_private *i915)
> ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
> ppgtt->debug_dump = gen8_dump_ppgtt;
>
> - ppgtt->vm.vma_ops.bind_vma= gen8_ppgtt_bind_vma;
> + ppgtt->vm.vma_ops.bind_vma= ppgtt_bind_vma;
> ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
> ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
> ppgtt->vm.vma_ops.clear_pages = clear_pages;
> @@ -1837,7 +1829,8 @@ static void gen6_ppgtt_clear_range(struct
> i915_address_space *vm,
>
> num_entries -= end - pte;
>
> - /* Note that the hw doesn't support removing PDE on the fly
> + /*
> +* Note that the hw doesn't support removing PDE on the fly
> * (they are cached inside the context with no means to
> * invalidate the cache), so we can only reset the PTE
> * entries back to scratch.
> @@ -2106,12 +2099,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
> drm_i915_private *i915)
>
> ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
>
> + ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
Ah, in gen6_alloc_va_range() I think we now need:
unwind_out:
- gen6_ppgtt_clear_range(vm, from, start);
+ gen6_ppgtt_clear_range(vm, from, start - from);
return -ENOMEM;
}
?
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Re: [Intel-gfx] [PATCH v2] drm/i915/skl: Add warn about unsupported CDCLK rates
On Fri, Jun 08, 2018 at 05:00:02PM +0300, Imre Deak wrote: > While checking workarounds related to the CDCLK PLL, I noticed that the > DMC firmware bits for WA#1183 are missing for SKL. After that I > clarified with HW people that it's not needed on SKL, since it doesn't > support eDP1.4 which would be the only thing requiring the problematic > CDCLK clock rates. So in theory we shouldn't ever choose these > frequencies, but add an assert in any case for catching such cases and > for documentation. > > v2: > - Move the check to skl_set_cdclk and warn whenever using the > corresponding VCO freq. (Ville) > > Cc: Ville Syrjälä > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_cdclk.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > b/drivers/gpu/drm/i915/intel_cdclk.c > index 704ddb4d3ca7..a1e9434698b9 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -991,6 +991,16 @@ static void skl_set_cdclk(struct drm_i915_private > *dev_priv, > u32 freq_select, cdclk_ctl; > int ret; > > + /* > + * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are > + * unsupported on SKL. In theory this should never happen since only > + * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not > + * supported on SKL either, see the above WA. WARN whenever trying to > + * use the corresponding VCO freq as that always leads to using the > + * minimum 308MHz CDCLK. > + */ > + WARN_ON_ONCE(vco == 864); Needs IS_SKYLAKE() with that Reviewed-by: Ville Syrjälä > + > mutex_lock(&dev_priv->pcu_lock); > ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, > SKL_CDCLK_PREPARE_FOR_CHANGE, > -- > 2.13.2 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Store first production revid into device info
Quoting Mika Kuoppala (2018-06-08 14:42:02) > Store first known production revid into the device info. > > This enables us to easily see if we are running on > a preproduction hardware. > > Uninitialized (zero) product revision id means that > there are no known preliminary hardware for this platform, > or that the platform is of gen that we don't care. > This is all pre gen9 platforms. > > Unknown product revision maps to REVID_FOREVER on a > gen9+ platforms on default. When the platform > gets the first production revision and our testing > infra is cleaned from preproduction hardware, we can > set a first production revid. At that point we start > to complain about running driver on preliminary hardware. > > v2: initialize GEN9_FEATURES too (CI) > v3: comment, eyesore fix (Chris), cfl fix, squash > > Suggested-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Chris Wilson > Cc: Tomi Sarvela > Cc: Jani Nikula > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/18] drm/i915/ringbuffer: Fix context restore upon reset
Quoting Chris Wilson (2018-06-08 13:55:47)
> @@ -570,42 +585,10 @@ static void reset_ring(struct intel_engine_cs *engine,
> * the restored context.
> */
> if (request) {
> - struct drm_i915_private *dev_priv = request->i915;
> - struct intel_context *ce = request->hw_context;
> - struct i915_hw_ppgtt *ppgtt;
> -
> - if (ce->state) {
> - I915_WRITE(CCID,
> - i915_ggtt_offset(ce->state) |
> - BIT(8) /* must be set! */ |
> - CCID_EXTENDED_STATE_SAVE |
> - CCID_EXTENDED_STATE_RESTORE |
> - CCID_EN);
> - }
> -
> - ppgtt = request->gem_context->ppgtt ?:
> engine->i915->mm.aliasing_ppgtt;
> - if (ppgtt) {
> - u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
> -
> - I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
> - I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset);
> -
> - /* Wait for the PD reload to complete */
> - if (intel_wait_for_register(dev_priv,
> - RING_PP_DIR_BASE(engine),
> - BIT(0), 0,
> - 10))
> - DRM_ERROR("Wait for reload of ppgtt
> page-directory timed out\n");
> -
> - ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
So I forgot about Sandybridge here. Snb doesn't place an LRI in each
request, and uses mmio instead. Hence has the problem of not setting
PP_DIR after reset until the next request is submitted.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
== Series Details == Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h URL : https://patchwork.freedesktop.org/series/44488/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9242 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9242 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9242, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44488/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9242: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9242 that come from known issues: === IGT changes === Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106097, fdo#106000) -> PASS fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 37) == Additional (1): fi-bxt-dsi Missing(5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-gvtdvm fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9242 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9242: 503bc7e600b180a943cb72eed79622d45fd5f516 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 503bc7e600b1 drm/i915: Warn on obsolete revision checks 941d3c77de1d drm/i915: Remove kbl preproduction workarounds 9ef4f2cb2515 drm/i915: Use unknown production revid as alpha quality flag b8d2b1ec3867 drm/i915: Store first production revid into device info b04c01486105 drm/i915: Move chipset definitions to intel_chipset.h == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9242/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
== Series Details == Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h URL : https://patchwork.freedesktop.org/series/44488/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Move chipset definitions to intel_chipset.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3669:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3477:16: warning: expression using sizeof(void) Commit: drm/i915: Store first production revid into device info Okay! Commit: drm/i915: Use unknown production revid as alpha quality flag Okay! Commit: drm/i915: Remove kbl preproduction workarounds Okay! Commit: drm/i915: Warn on obsolete revision checks Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/18] drm/i915/gtt: Remove vgpu check for gen6
Chris Wilson writes: > Since vgpu is not supported on Haswell or any other gen6/7, we do not > need to check and act upon it's enablement. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 25ad94b1b67e..ca067d9adf54 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2124,7 +2124,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct > drm_i915_private *i915) > ppgtt->base.vm.vma_ops.clear_pages = clear_pages; > > ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; > - if (intel_vgpu_active(i915) || IS_GEN6(i915)) > + if (IS_GEN6(i915)) > ppgtt->switch_mm = gen6_mm_switch; > else if (IS_GEN7(i915)) > ppgtt->switch_mm = gen7_mm_switch; > -- > 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
== Series Details == Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h URL : https://patchwork.freedesktop.org/series/44488/ State : warning == Summary == $ dim checkpatch origin/drm-tip b04c01486105 drm/i915: Move chipset definitions to intel_chipset.h -:225: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #225: new file mode 100644 -:246: CHECK:MACRO_ARG_REUSE: Macro argument reuse 's' - possible side-effects? #246: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:246: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e' - possible side-effects? #246: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:266: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #266: FILE: drivers/gpu/drm/i915/intel_chipset.h:37: +#define IS_REVID(p, since, until) \ + (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -:283: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #283: FILE: drivers/gpu/drm/i915/intel_chipset.h:54: +#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -:290: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #290: FILE: drivers/gpu/drm/i915/intel_chipset.h:61: +#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ +(dev_priv)->info.gt == 1) -:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #304: FILE: drivers/gpu/drm/i915/intel_chipset.h:75: +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -:306: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #306: FILE: drivers/gpu/drm/i915/intel_chipset.h:77: +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ +((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #311: FILE: drivers/gpu/drm/i915/intel_chipset.h:82: +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -:313: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #313: FILE: drivers/gpu/drm/i915/intel_chipset.h:84: +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:315: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #315: FILE: drivers/gpu/drm/i915/intel_chipset.h:86: +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) -:317: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #317: FILE: drivers/gpu/drm/i915/intel_chipset.h:88: +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #320: FILE: drivers/gpu/drm/i915/intel_chipset.h:91: +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ +INTEL_DEVID(dev_priv) == 0x0A1E) -:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #322: FILE: drivers/gpu/drm/i915/intel_chipset.h:93: +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ +INTEL_DEVID(dev_priv) == 0x1913 || \ +INTEL_DEVID(dev_priv) == 0x1916 || \ +INTEL_DEVID(dev_priv) == 0x1921 || \ +INTEL_DEVID(dev_priv) == 0x1926) -:327: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #327: FILE: drivers/gpu/drm/i915/intel_chipset.h:98: +#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ +INTEL_DEVID(dev_priv) == 0x1915 || \ +INTEL_DEVID(dev_priv) == 0x191E) -:330: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #330: FILE: drivers/gpu/drm/i915/intel_chipset.h:10
Re: [Intel-gfx] [PATCH 16/18] drm/i915/gtt: Remove redundant hsw_mm_switch()
Chris Wilson writes:
> hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
> redundant specialism.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 24
> 1 file changed, 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 60a8332a122e..25ad94b1b67e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1697,28 +1697,6 @@ static inline u32 get_pd_offset(struct gen6_hw_ppgtt
> *ppgtt)
> return ppgtt->base.pd.base.ggtt_offset << 10;
> }
>
> -static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt,
> - struct i915_request *rq)
> -{
> - struct intel_engine_cs *engine = rq->engine;
> - u32 *cs;
> -
> - /* NB: TLBs must be flushed and invalidated before a switch */
> - cs = intel_ring_begin(rq, 6);
> - if (IS_ERR(cs))
> - return PTR_ERR(cs);
> -
> - *cs++ = MI_LOAD_REGISTER_IMM(2);
> - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
> - *cs++ = PP_DIR_DCLV_2G;
> - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
> - *cs++ = get_pd_offset(ppgtt);
> - *cs++ = MI_NOOP;
> - intel_ring_advance(rq, cs);
> -
> - return 0;
> -}
> -
> static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt,
> struct i915_request *rq)
> {
> @@ -2148,8 +2126,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
> drm_i915_private *i915)
> ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
> if (intel_vgpu_active(i915) || IS_GEN6(i915))
> ppgtt->switch_mm = gen6_mm_switch;
> - else if (IS_HASWELL(i915))
> - ppgtt->switch_mm = hsw_mm_switch;
> else if (IS_GEN7(i915))
> ppgtt->switch_mm = gen7_mm_switch;
> else
> --
> 2.17.1
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[Intel-gfx] [PATCH v2] drm/i915/skl: Add warn about unsupported CDCLK rates
While checking workarounds related to the CDCLK PLL, I noticed that the DMC firmware bits for WA#1183 are missing for SKL. After that I clarified with HW people that it's not needed on SKL, since it doesn't support eDP1.4 which would be the only thing requiring the problematic CDCLK clock rates. So in theory we shouldn't ever choose these frequencies, but add an assert in any case for catching such cases and for documentation. v2: - Move the check to skl_set_cdclk and warn whenever using the corresponding VCO freq. (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_cdclk.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 704ddb4d3ca7..a1e9434698b9 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -991,6 +991,16 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, u32 freq_select, cdclk_ctl; int ret; + /* +* Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are +* unsupported on SKL. In theory this should never happen since only +* the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not +* supported on SKL either, see the above WA. WARN whenever trying to +* use the corresponding VCO freq as that always leads to using the +* minimum 308MHz CDCLK. +*/ + WARN_ON_ONCE(vco == 864); + mutex_lock(&dev_priv->pcu_lock); ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, -- 2.13.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/18] drm/i915/ringbuffer: Brute force context restore
Quoting Mika Kuoppala (2018-06-08 14:52:13)
> Chris Wilson writes:
>
> > An issue encountered with switching mm on gen7 is that the GPU likes to
> > hang (with the VS unit busy) when told to force restore the current
> > context. We can simply workaround this by substituting the
> > MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
> > forcing the context to be saved and restored; thereby reloading the
> > PP_DIR registers and updating the modified page directory!
> >
> > Signed-off-by: Chris Wilson
> > Cc: Joonas Lahtinen
> > Cc: Mika Kuoppala
> > Cc: Matthew Auld
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++---
> > 1 file changed, 27 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 65811e2fa7da..332d97bc5c27 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1458,6 +1458,7 @@ static inline int mi_set_context(struct i915_request
> > *rq, u32 flags)
> > (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
> > INTEL_INFO(i915)->num_rings - 1 :
> > 0;
> > + bool force_restore = false;
> > int len;
> > u32 *cs;
> >
> > @@ -1471,6 +1472,12 @@ static inline int mi_set_context(struct i915_request
> > *rq, u32 flags)
> > len = 4;
> > if (IS_GEN7(i915))
> > len += 2 + (num_rings ? 4*num_rings + 6 : 0);
> > + if (flags & MI_FORCE_RESTORE) {
> > + GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> > + flags &= ~MI_FORCE_RESTORE;
> > + force_restore = true;
> > + len += 2;
> > + }
> >
> > cs = intel_ring_begin(rq, len);
> > if (IS_ERR(cs))
> > @@ -1496,6 +1503,20 @@ static inline int mi_set_context(struct i915_request
> > *rq, u32 flags)
> > }
> >
> > *cs++ = MI_NOOP;
> > + if (force_restore) {
> > + /*
> > + * The HW doesn't handle being told to restore the current
> > + * context very well. Quite often it likes goes to go off and
> > + * sulk, especially when it is meant to be reloading PP_DIR.
> > + * A very simple fix to force the reload is to simply switch
> > + * away from the current context and back again.
> > + */
> > + *cs++ = MI_SET_CONTEXT;
> > + *cs++ =
> > i915_ggtt_offset(to_intel_context(i915->kernel_context,
> > + engine)->state) |
> > + MI_MM_SPACE_GTT |
> > + MI_RESTORE_INHIBIT;
>
> Why inhibit? You dont really switch to kernel but rather overwrite
> current with kernel ctx.
This is for the switch to kernel context. We don't want to load the
kernel context image, just trigger the load of our own context in the
next MI_SET_CONTEXT.
Ideally, we would tell it not to save the kernel context either. But we
don't have that option in MI_SET_CONTEXT. This does mean that the kernel
context then contains state from current, but we *never* use the kernel
context state.
-Chris
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h
Quoting Mika Kuoppala (2018-06-08 14:42:01) > Carve out chipset definitions into new intel_chipset.h > > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Please check with Jani and Rodrigo that this fits in with our new/old platform strategy. > diff --git a/drivers/gpu/drm/i915/intel_chipset.h > b/drivers/gpu/drm/i915/intel_chipset.h > new file mode 100644 > index ..0e71571fb4c1 > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_chipset.h > @@ -0,0 +1,202 @@ > +/* SPDX-License-Identifier: MIT > + * > + * Copyright © 2018 Intel Corporation > + */ > + > +#ifndef _INTEL_CHIPSET_H_ > +#define _INTEL_CHIPSET_H_ > + > +#define INTEL_GEN(dev_priv)((dev_priv)->info.gen) > +#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) dev_priv. Will make this much harder to become standalone. Oh well. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag
Quoting Mika Kuoppala (2018-06-08 14:42:03) > We don't need to have distinct flag for alpha quality if > we agree that setting the first production revid to be the > epoch for stepping out from alpha quality on that platform. > > v2: rebase, comment beautification > > Cc: Joonas Lahtinen > Cc: Chris Wilson > Cc: Tomi Sarvela > Cc: Jani Nikula > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Though not my domain, so please do get maintainer buy in. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Remove kbl preproduction workarounds
Quoting Mika Kuoppala (2018-06-08 14:42:04) > We don't need kbl preprod workarounds anymore. > > Signed-off-by: Mika Kuoppala As we now consider cnl stable, and icl the new development branch, we can rid ourselves of preproduction w/a for anything older than cnl. (By my understanding of our process rules.) Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/18] drm/i915/ringbuffer: Brute force context restore
Chris Wilson writes:
> An issue encountered with switching mm on gen7 is that the GPU likes to
> hang (with the VS unit busy) when told to force restore the current
> context. We can simply workaround this by substituting the
> MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
> forcing the context to be saved and restored; thereby reloading the
> PP_DIR registers and updating the modified page directory!
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++---
> 1 file changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 65811e2fa7da..332d97bc5c27 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1458,6 +1458,7 @@ static inline int mi_set_context(struct i915_request
> *rq, u32 flags)
> (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
> INTEL_INFO(i915)->num_rings - 1 :
> 0;
> + bool force_restore = false;
> int len;
> u32 *cs;
>
> @@ -1471,6 +1472,12 @@ static inline int mi_set_context(struct i915_request
> *rq, u32 flags)
> len = 4;
> if (IS_GEN7(i915))
> len += 2 + (num_rings ? 4*num_rings + 6 : 0);
> + if (flags & MI_FORCE_RESTORE) {
> + GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> + flags &= ~MI_FORCE_RESTORE;
> + force_restore = true;
> + len += 2;
> + }
>
> cs = intel_ring_begin(rq, len);
> if (IS_ERR(cs))
> @@ -1496,6 +1503,20 @@ static inline int mi_set_context(struct i915_request
> *rq, u32 flags)
> }
>
> *cs++ = MI_NOOP;
> + if (force_restore) {
> + /*
> + * The HW doesn't handle being told to restore the current
> + * context very well. Quite often it likes goes to go off and
> + * sulk, especially when it is meant to be reloading PP_DIR.
> + * A very simple fix to force the reload is to simply switch
> + * away from the current context and back again.
> + */
> + *cs++ = MI_SET_CONTEXT;
> + *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
> + engine)->state) |
> + MI_MM_SPACE_GTT |
> + MI_RESTORE_INHIBIT;
Why inhibit? You dont really switch to kernel but rather overwrite
current with kernel ctx.
-Mika
> + }
> *cs++ = MI_SET_CONTEXT;
> *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
> /*
> @@ -1585,11 +1606,14 @@ static int switch_context(struct i915_request *rq)
>
> to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
> engine->legacy_active_ppgtt = to_mm;
> - hw_flags = MI_FORCE_RESTORE;
> +
> + if (to_ctx == from_ctx) {
> + hw_flags = MI_FORCE_RESTORE;
> + from_ctx = NULL;
> + }
> }
>
> - if (rq->hw_context->state &&
> - (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
> + if (rq->hw_context->state && to_ctx != from_ctx) {
> GEM_BUG_ON(engine->id != RCS);
>
> /*
> --
> 2.17.1
___
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Warn on obsolete revision checks
Quoting Mika Kuoppala (2018-06-08 14:42:05)
> If we are doing revision checks against a preproduction
> range, when there is already a product, it is a sign
> that there is code to be removed.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_chipset.h | 30 +---
> 1 file changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_chipset.h
> b/drivers/gpu/drm/i915/intel_chipset.h
> index 946c889c0118..bc9ff02dc8df 100644
> --- a/drivers/gpu/drm/i915/intel_chipset.h
> +++ b/drivers/gpu/drm/i915/intel_chipset.h
> @@ -131,6 +131,12 @@
> #define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
> FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
> #define IS_PLATFORM_SUPPORT_ALPHA(intel_info)
> (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)
>
> +#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
BUILD_BUG_ON_PREPRODUCTION()
It doesn't look that general, or widely useful to say REVID_LT. Sort of
implies we will have REVID_GTE etc later.
> + BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
> +(revid) < (production_revid)); \
I'd prefer (!BUILD_BUG_ON_ZERO()) (Or push the
!BUILD_BUG_ON_PREPRODUCTION to the caller as that's easier to read).
That avoids the ({block}) making it less likely to cause problems.
-Chris
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[Intel-gfx] [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h
Carve out chipset definitions into new intel_chipset.h Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 194 + drivers/gpu/drm/i915/intel_chipset.h | 202 +++ 2 files changed, 203 insertions(+), 193 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_chipset.h diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c4073666f1ca..e659c89198d2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -58,6 +58,7 @@ #include "i915_utils.h" #include "intel_bios.h" +#include "intel_chipset.h" #include "intel_device_info.h" #include "intel_display.h" #include "intel_dpll_mgr.h" @@ -2309,199 +2310,6 @@ intel_info(const struct drm_i915_private *dev_priv) #define INTEL_INFO(dev_priv) intel_info((dev_priv)) -#define INTEL_GEN(dev_priv)((dev_priv)->info.gen) -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) - -#define REVID_FOREVER 0xff -#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) - -#define GEN_FOREVER (0) - -#define INTEL_GEN_MASK(s, e) ( \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ - GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ - (s) != GEN_FOREVER ? (s) - 1 : 0) \ -) - -/* - * Returns true if Gen is in inclusive range [Start, End]. - * - * Use GEN_FOREVER for unbound start and or end. - */ -#define IS_GEN(dev_priv, s, e) \ - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e - -/* - * Return true if revision is in range [since,until] inclusive. - * - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. - */ -#define IS_REVID(p, since, until) \ - (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) - -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) - -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001) -#define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ -(dev_priv)->info.gt == 1) -#define IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile) -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ -((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -/* ULX machines are also considered ULT. */ -#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ -(dev_priv)->info.gt == 3) -#d
[Intel-gfx] [PATCH 2/5] drm/i915: Store first production revid into device info
Store first known production revid into the device info.
This enables us to easily see if we are running on
a preproduction hardware.
Uninitialized (zero) product revision id means that
there are no known preliminary hardware for this platform,
or that the platform is of gen that we don't care.
This is all pre gen9 platforms.
Unknown product revision maps to REVID_FOREVER on a
gen9+ platforms on default. When the platform
gets the first production revision and our testing
infra is cleaned from preproduction hardware, we can
set a first production revid. At that point we start
to complain about running driver on preliminary hardware.
v2: initialize GEN9_FEATURES too (CI)
v3: comment, eyesore fix (Chris), cfl fix, squash
Suggested-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Tomi Sarvela
Cc: Jani Nikula
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
drivers/gpu/drm/i915/i915_pci.c | 10 --
drivers/gpu/drm/i915/intel_chipset.h | 7 +++
drivers/gpu/drm/i915/intel_device_info.h | 10 ++
4 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index be71fdf8d92e..86725c272251 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -852,13 +852,13 @@ static void i915_workqueues_cleanup(struct
drm_i915_private *dev_priv)
*/
static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
bool pre = false;
pre |= IS_HSW_EARLY_SDV(dev_priv);
- pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
- pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
+ pre |= IS_PREPRODUCTION_HW(dev_priv);
- if (pre) {
+ if (pre && FIRST_PRODUCT_REVID(info) != PRODUCT_REVID_UNKNOWN) {
DRM_ERROR("This is a pre-production stepping. "
"It may not be fully functional.\n");
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97a91e6af7e3..60a02082055c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -461,10 +461,12 @@ static const struct intel_device_info
intel_cherryview_info = {
.has_csr = 1, \
.has_guc = 1, \
.has_ipc = 1, \
+ .first_product_revid = PRODUCT_REVID_UNKNOWN, \
.ddb_size = 896
#define SKL_PLATFORM \
GEN9_FEATURES, \
+ .first_product_revid = SKL_REVID_PRODUCT, \
PLATFORM(INTEL_SKYLAKE)
static const struct intel_device_info intel_skylake_gt1_info = {
@@ -518,6 +520,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_reset_engine = 1, \
.has_snoop = true, \
.has_ipc = 1, \
+ .first_product_revid = PRODUCT_REVID_UNKNOWN, \
GEN9_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS, \
@@ -526,6 +529,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
+ .first_product_revid = BXT_REVID_PRODUCT,
.ddb_size = 512,
};
@@ -538,7 +542,8 @@ static const struct intel_device_info intel_geminilake_info
= {
#define KBL_PLATFORM \
GEN9_FEATURES, \
- PLATFORM(INTEL_KABYLAKE)
+ PLATFORM(INTEL_KABYLAKE), \
+ .first_product_revid = KBL_REVID_PRODUCT
static const struct intel_device_info intel_kabylake_gt1_info = {
KBL_PLATFORM,
@@ -558,7 +563,8 @@ static const struct intel_device_info
intel_kabylake_gt3_info = {
#define CFL_PLATFORM \
GEN9_FEATURES, \
- PLATFORM(INTEL_COFFEELAKE)
+ PLATFORM(INTEL_COFFEELAKE), \
+ .first_product_revid = 0x00 /* cfl doesn't use revids */
static const struct intel_device_info intel_coffeelake_gt1_info = {
CFL_PLATFORM,
diff --git a/drivers/gpu/drm/i915/intel_chipset.h
b/drivers/gpu/drm/i915/intel_chipset.h
index 0e71571fb4c1..a917ab40f857 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -127,6 +127,10 @@
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
+#define PRODUCT_REVID_UNKNOWN REVID_FOREVER
+#define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
+#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
#define SKL_REVID_C0 0x2
@@ -134,6 +138,7 @@
#define SKL_REVID_E0 0x4
#define SKL_REVID_F0 0x5
#define SKL_REVID_G0 0x6
+#define SKL_REVID_PRODUCT SKL_REVID_G0
#define SKL_REVID_H0 0x7
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p)
[Intel-gfx] [PATCH 5/5] drm/i915: Warn on obsolete revision checks
If we are doing revision checks against a preproduction
range, when there is already a product, it is a sign
that there is code to be removed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_chipset.h | 30 +---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_chipset.h
b/drivers/gpu/drm/i915/intel_chipset.h
index 946c889c0118..bc9ff02dc8df 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -131,6 +131,12 @@
#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
#define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info)
== PRODUCT_REVID_UNKNOWN)
+#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
+ BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
+(revid) < (production_revid)); \
+ 1; \
+ })
+
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
#define SKL_REVID_C0 0x2
@@ -141,7 +147,9 @@
#define SKL_REVID_PRODUCT SKL_REVID_G0
#define SKL_REVID_H0 0x7
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
+#define IS_SKL_REVID(p, since, until) \
+ (BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
+IS_SKYLAKE(p) && IS_REVID(p, since, until))
#define BXT_REVID_A0 0x0
#define BXT_REVID_A1 0x1
@@ -151,7 +159,8 @@
#define BXT_REVID_PRODUCT BXT_REVID_C0
#define IS_BXT_REVID(dev_priv, since, until) \
- (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, BXT_REVID_PRODUCT) && \
+IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
@@ -161,29 +170,36 @@
#define KBL_REVID_E0 0x4
#define IS_KBL_REVID(dev_priv, since, until) \
- (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, KBL_REVID_PRODUCT) && \
+IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
#define GLK_REVID_A0 0x0
#define GLK_REVID_A1 0x1
+#define GLK_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
-#define IS_GLK_REVID(dev_priv, since, until) \
- (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+#define IS_GLK_REVID(dev_priv, since, until) \
+ (BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
+IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
#define CNL_REVID_A0 0x0
#define CNL_REVID_B0 0x1
#define CNL_REVID_C0 0x2
+#define CNL_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
#define IS_CNL_REVID(p, since, until) \
- (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, CNL_REVID_PRODUCT) && \
+IS_CANNONLAKE(p) && IS_REVID(p, since, until))
#define ICL_REVID_A0 0x0
#define ICL_REVID_A2 0x1
#define ICL_REVID_B0 0x3
#define ICL_REVID_B2 0x4
#define ICL_REVID_C0 0x5
+#define ICL_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
#define IS_ICL_REVID(p, since, until) \
- (IS_ICELAKE(p) && IS_REVID(p, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, ICL_REVID_PRODUCT) && \
+ IS_ICELAKE(p) && IS_REVID(p, since, until))
/*
* The genX designation typically refers to the render engine, so render
--
2.17.0
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[Intel-gfx] [PATCH 4/5] drm/i915: Remove kbl preproduction workarounds
We don't need kbl preprod workarounds anymore.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 12
drivers/gpu/drm/i915/intel_workarounds.c | 5 -
2 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 091e28f0e024..ffec91cdb1b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1581,18 +1581,6 @@ static u32 *gen9_init_indirectctx_bb(struct
intel_engine_cs *engine, u32 *batch)
GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
*batch++ = MI_NOOP;
- /* WaClearSlmSpaceAtContextSwitch:kbl */
- /* Actual scratch location is at 128 bytes offset */
- if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
- batch = gen8_emit_pipe_control(batch,
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_QW_WRITE,
- i915_ggtt_offset(engine->scratch)
- + 2 * CACHELINE_BYTES);
- }
-
/* WaMediaPoolStateCmdInWABB:bxt,glk */
if (HAS_POOLED_EU(engine->i915)) {
/*
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..cdeb7abc14bf 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -355,11 +355,6 @@ static int kbl_ctx_workarounds_init(struct
drm_i915_private *dev_priv)
if (ret)
return ret;
- /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
- if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FENCE_DEST_SLM_DISABLE);
-
/* WaToEnableHwFixForPushConstHWBug:kbl */
if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
--
2.17.0
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[Intel-gfx] [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag
We don't need to have distinct flag for alpha quality if
we agree that setting the first production revid to be the
epoch for stepping out from alpha quality on that platform.
v2: rebase, comment beautification
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Tomi Sarvela
Cc: Jani Nikula
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +--
drivers/gpu/drm/i915/intel_chipset.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 -
4 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 86725c272251..74d3a905 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -858,7 +858,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_HSW_EARLY_SDV(dev_priv);
pre |= IS_PREPRODUCTION_HW(dev_priv);
- if (pre && FIRST_PRODUCT_REVID(info) != PRODUCT_REVID_UNKNOWN) {
+ if (pre && !IS_PLATFORM_SUPPORT_ALPHA(info)) {
DRM_ERROR("This is a pre-production stepping. "
"It may not be fully functional.\n");
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 60a02082055c..4a5a4f8778ad 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -604,7 +604,6 @@ static const struct intel_device_info intel_cannonlake_info
= {
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
- .is_alpha_support = 1,
.has_resource_streamer = 0,
.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
@@ -689,7 +688,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
(struct intel_device_info *) ent->driver_data;
int err;
- if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
+ if (IS_PLATFORM_SUPPORT_ALPHA(intel_info) &&
!i915_modparams.alpha_support) {
DRM_INFO("The driver support for your hardware in this kernel
version is alpha quality\n"
"See CONFIG_DRM_I915_ALPHA_SUPPORT or
i915.alpha_support module parameter\n"
"to enable support in this kernel version, or check
for kernel updates.\n");
diff --git a/drivers/gpu/drm/i915/intel_chipset.h
b/drivers/gpu/drm/i915/intel_chipset.h
index a917ab40f857..946c889c0118 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -125,11 +125,11 @@
#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x0004) ==
0x0004)
-#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
#define PRODUCT_REVID_UNKNOWN REVID_FOREVER
#define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+#define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info)
== PRODUCT_REVID_UNKNOWN)
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 64ec283003dd..a66837db341b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -77,7 +77,6 @@ enum intel_platform {
#define DEV_INFO_FOR_EACH_FLAG(func) \
func(is_mobile); \
func(is_lp); \
- func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_aliasing_ppgtt); \
--
2.17.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
== Series Details == Series: series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2) URL : https://patchwork.freedesktop.org/series/44486/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9241 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9241 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9241, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44486/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9241: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9241 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: fi-bdw-5557u: PASS -> FAIL (fdo#103481) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: NOTRUN -> INCOMPLETE (fdo#103927) igt@prime_vgem@basic-fence-flip: fi-bdw-5557u: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 == Participating hosts (41 -> 37) == Additional (1): fi-bxt-dsi Missing(5): fi-byt-j1900 fi-byt-squawks fi-ilk-m540 fi-cnl-y3 fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9241 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9241: bf7d463b083bc7108ce2c73d6669a72d997b5676 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bf7d463b083b RFT drm/i915/gtt: Enable full-ppgtt by default everywhere a577338f5224 drm/i915/gtt: Remove vgpu check for gen6 12ad9bea4b2a drm/i915/gtt: Remove redundant hsw_mm_switch() 45557e9cb79b drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt 2943ce67094f drm/i915/gtt: Reduce a pair of runtime asserts b14c6c476216 drm/i915/gtt: Cache the PTE encoding of the scratch page aefdc08285f0 drm/i915/gtt: Skip initializing PT with scratch if full 0d40e5eb8990 drm/i915/gtt: Free unused page tables on unbind the context 75f47fae2367 drm/i915/gtt: Lazily allocate page directories for gen7 66674381f287 drm/i915/gtt: Only keep gen6 page directories pinned while active 69a521d88bfe drm/i915/gtt: Make gen6 page directories evictable 51bf579d69f0 drm/i915/gtt: Reorder aliasing_ppgtt fini f3abd9908e36 drm/i915/gtt: Onionify error handling for gen6_ppgtt_create c048d4432be3 drm/i915/gtt: Subclass gen6_hw_ppgtt 8096c4955335 drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories 276fa4d5d41c drm/i915/ringbuffer: Fix context restore upon reset aa246150d1ae drm/i915/ringbuffer: Brute force context restore c1efb9574092 drm/i915: Apply batch location restrictions before pinning == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9241/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> On GLK NUC platforms the HDMI retiming buffer needs additional disabled
> time to correctly sync to a faster incoming signal.
> When measured on a scope the highspeed lines of the HDMI clock turn
> off for ~400uS during a normal resolution change. The HDMI retimer on
> the GLK NUC appears to require at least a full frame of quiet time
> before a new faster clock can be correctly sync'd.
> The worst case scenario appears to be 23.98Hz modes which requires a
> wait of 41.25ms. Add a quirk to the driver for GLK NUC that waits
> 42ms.
Just to understand better the failure mode: IIUC without the WA the HDMI
clock line is inactive for ~400us when switching modes (which would
depend on kernel timing) and the retimer chip needs at least 42ms idle
time at least when switching to certain modes.
Is there a way to recover the chip from the bad state? By doing a new
off/on modeset with enough idle time, or resetting the chip?
--Imre
>
> Cc: Imre Deak
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 8
> drivers/gpu/drm/i915/intel_display.c | 14 ++
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c407366..628491d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -645,6 +645,7 @@ enum intel_sbi_destination {
> #define QUIRK_BACKLIGHT_PRESENT (1<<3)
> #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
> #define QUIRK_INCREASE_T12_DELAY (1<<6)
> +#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
>
> struct intel_fbdev;
> struct intel_fbc_work;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b344e0f..61b41c3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1784,6 +1784,9 @@ void intel_ddi_enable_transcoder_func(const struct
> intel_crtc_state *crtc_state)
> I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
> +/* Quirk time computed based on 24fps frame time of 41.25ms */
> +#define DDI_DISABLED_QUIRK_TIME 42
> +
> void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> enum transcoder cpu_transcoder)
> {
> @@ -1793,6 +1796,11 @@ void intel_ddi_disable_transcoder_func(struct
> drm_i915_private *dev_priv,
> val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> val |= TRANS_DDI_PORT_NONE;
> I915_WRITE(reg, val);
> +
> + if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
> + msleep(DDI_DISABLED_QUIRK_TIME);
> + DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
> + }
> }
>
> int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ed29219..0d07c37 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14740,6 +14740,17 @@ static void quirk_increase_t12_delay(struct
> drm_device *dev)
> DRM_INFO("Applying T12 delay quirk\n");
> }
>
> +/* GeminiLake NUC HDMI outputs require additional off time
> + * this allows the onboard retimer to correctly sync to signal
> + */
> +static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
> + DRM_INFO("Applying Increase DDI Disabled quirk\n");
> +}
> +
> struct intel_quirk {
> int device;
> int subsystem_vendor;
> @@ -14826,6 +14837,9 @@ static int intel_dmi_reverse_brightness(const struct
> dmi_system_id *id)
>
> /* Toshiba Satellite P50-C-18C */
> { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
> +
> + /* GeminiLake NUC */
> + { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
> };
>
> static void intel_init_quirks(struct drm_device *dev)
> --
> 1.9.1
>
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Re: [Intel-gfx] [bug report] drm/i915/bios: add support for MIPI sequence block v3
On Fri, Jun 08, 2018 at 03:50:47PM +0300, Jani Nikula wrote:
> On Fri, 08 Jun 2018, Dan Carpenter wrote:
> > Hello Jani Nikula,
> >
> > The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
> > block v3" from Jan 11, 2016, leads to the following static checker
> > warning:
> >
> > drivers/gpu/drm/i915/intel_bios.c:926 goto_next_sequence_v3()
> > warn: potentially one past the end of array 'data[index]'
> >
> > drivers/gpu/drm/i915/intel_bios.c
> >897 /* Skip Sequence Byte. */
> >898 index++;
> >899
> >900 /*
> >901 * Size of Sequence. Excludes the Sequence Byte and the
> > size itself,
> >902 * includes MIPI_SEQ_ELEM_END byte, excludes the final
> > MIPI_SEQ_END
> >903 * byte.
> >904 */
> >905 size_of_sequence = *((const uint32_t *)(data + index));
> >906 index += 4;
> >907
> >908 seq_end = index + size_of_sequence;
> >909 if (seq_end > total) {
> >910 DRM_ERROR("Invalid sequence size\n");
> >911 return 0;
> >912 }
> >913
> >914 for (; index < total; index += len) {
>
> The data being parsed here is a sort of TLV coded blob with len here
> referring to the payload length.
>
> It's a sort of TLV coded blob with len here referring to the payload
> length. T being the 1-byte operation_byte, L being the 1-byte len.
>
>
>
>
> >915 u8 operation_byte = *(data + index);
>
> index is now at T, or operation byte.
>
> >916 index++;
> > ^^^
>
> index is now at L, or length.
>
> >917
> >918 if (operation_byte == MIPI_SEQ_ELEM_END) {
>
> it could also be a marker for end of the whole thing, in which case the
> operation_byte is 0.
>
> >919 if (index != seq_end) {
> >920 DRM_ERROR("Invalid element
> > structure\n");
> >921 return 0;
> >922 }
> >923 return index;
> >924 }
> >925
> >926 len = *(data + index);
> > ^
> > This does look to uninitiated eyes as if it might be one past the end?
> >
> >927 index++;
>
> index is now at the payload, which is len bytes.
>
> Makes sense? N.b. I didn't specify the format...
Yeah. That makes sense. It's sort of a common idiom too... I haven't
figured out a way to deal with it from a static analysis perspective...
Anyway, thanks for taking a look.
regards,
dan carpenter
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
== Series Details == Series: series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2) URL : https://patchwork.freedesktop.org/series/44486/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Apply batch location restrictions before pinning Okay! Commit: drm/i915/ringbuffer: Brute force context restore Okay! Commit: drm/i915/ringbuffer: Fix context restore upon reset Okay! Commit: drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories Okay! Commit: drm/i915/gtt: Subclass gen6_hw_ppgtt -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1913:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1913:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1914:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1914:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Onionify error handling for gen6_ppgtt_create Okay! Commit: drm/i915/gtt: Reorder aliasing_ppgtt fini Okay! Commit: drm/i915/gtt: Make gen6 page directories evictable -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2022:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2022:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Only keep gen6 page directories pinned while active Okay! Commit: drm/i915/gtt: Lazily allocate page directories for gen7 Okay! Commit: drm/i915/gtt: Free unused page tables on unbind the context -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1827:36: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1896:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1896:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1827:42: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1906:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1906:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Skip initializing PT with scratch if full Okay! Commit: drm/i915/gtt: Cache the PTE encoding of the scratch page Okay! Commit: drm/i915/gtt: Reduce a pair of runtime asserts Okay! Commit: drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt Okay! Commit: drm/i915/gtt: Remove redundant hsw_mm_switch() Okay! Commit: drm/i915/gtt: Remove vgpu check for gen6 Okay! Commit: RFT drm/i915/gtt: Enable full-ppgtt by default everywhere Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/18] drm/i915: Apply batch location restrictions before pinning (rev2)
== Series Details ==
Series: series starting with [01/18] drm/i915: Apply batch location
restrictions before pinning (rev2)
URL : https://patchwork.freedesktop.org/series/44486/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c1efb9574092 drm/i915: Apply batch location restrictions before pinning
-:30: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#30: FILE: drivers/gpu/drm/i915/i915_gem_execbuffer.c:493:
+ unsigned int i, unsigned batch_idx,
total: 0 errors, 1 warnings, 0 checks, 86 lines checked
aa246150d1ae drm/i915/ringbuffer: Brute force context restore
276fa4d5d41c drm/i915/ringbuffer: Fix context restore upon reset
8096c4955335 drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page
directories
c048d4432be3 drm/i915/gtt: Subclass gen6_hw_ppgtt
-:326: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible
side-effects?
#326: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:419:
+#define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
total: 0 errors, 0 warnings, 1 checks, 330 lines checked
f3abd9908e36 drm/i915/gtt: Onionify error handling for gen6_ppgtt_create
51bf579d69f0 drm/i915/gtt: Reorder aliasing_ppgtt fini
69a521d88bfe drm/i915/gtt: Make gen6 page directories evictable
66674381f287 drm/i915/gtt: Only keep gen6 page directories pinned while active
75f47fae2367 drm/i915/gtt: Lazily allocate page directories for gen7
0d40e5eb8990 drm/i915/gtt: Free unused page tables on unbind the context
aefdc08285f0 drm/i915/gtt: Skip initializing PT with scratch if full
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#9:
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 14826673247e ("drm/i915: Only
initialize partially filled pagetables")'
#9:
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
b14c6c476216 drm/i915/gtt: Cache the PTE encoding of the scratch page
2943ce67094f drm/i915/gtt: Reduce a pair of runtime asserts
-:39: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#39: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:470:
+ GEM_BUG_ON(offset_in_page(addr|length));
^
total: 0 errors, 0 warnings, 1 checks, 18 lines checked
45557e9cb79b drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
12ad9bea4b2a drm/i915/gtt: Remove redundant hsw_mm_switch()
a577338f5224 drm/i915/gtt: Remove vgpu check for gen6
bf7d463b083b RFT drm/i915/gtt: Enable full-ppgtt by default everywhere
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Re: [Intel-gfx] [PATCH i-g-t] igt/drv_suspend: Suspend under memory pressure
Quoting Chris Wilson (2018-06-07 21:50:54) > Recently we discovered that we have a race between swapping and > suspend in our resume path (we might be trying to page in an object > after disabling the block devices). Let's try to exercise that by > exhausting all of system memory before suspend. > > v2: Explicitly share the large memory area on forking to avoid running > out of memory inside the suspend helpers (for they fork!) > > References: https://bugs.freedesktop.org/show_bug.cgi?id=106640 > Signed-off-by: Chris Wilson > Cc: Tomi Sarvela > Reviewed-by: Antonio Argenziano With the more discerning oomkiller, this finally works as intended. Pushed while the iron is hot. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for HACK: drm/i915: see what breaks with display disabled
== Series Details == Series: HACK: drm/i915: see what breaks with display disabled URL : https://patchwork.freedesktop.org/series/44485/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9240 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9240 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9240, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44485/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9240: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-byt-n2820: PASS -> DMESG-FAIL +1 fi-bsw-n3050: PASS -> DMESG-FAIL igt@gem_exec_flush@basic-wb-prw-default: fi-snb-2600:PASS -> INCOMPLETE igt@gem_exec_suspend@basic-s3: fi-bdw-5557u: PASS -> DMESG-WARN fi-bsw-n3050: PASS -> DMESG-WARN fi-hsw-4770:PASS -> DMESG-WARN fi-hsw-4200u: PASS -> DMESG-WARN igt@kms_addfb_basic@addfb25-bad-modifier: fi-gdg-551: PASS -> FAIL +36 igt@kms_addfb_basic@addfb25-modifier-no-flag: fi-cfl-guc: PASS -> FAIL +37 fi-ilk-650: PASS -> FAIL +36 igt@kms_addfb_basic@addfb25-x-tiled-mismatch: fi-kbl-7560u: PASS -> FAIL +36 igt@kms_addfb_basic@addfb25-y-tiled: fi-kbl-r: PASS -> FAIL +36 fi-byt-n2820: PASS -> FAIL +37 igt@kms_addfb_basic@addfb25-y-tiled-small: fi-gdg-551: SKIP -> FAIL fi-bwr-2160:SKIP -> FAIL fi-bdw-5557u: SKIP -> FAIL fi-byt-n2820: SKIP -> FAIL fi-ivb-3520m: SKIP -> FAIL +1 fi-hsw-4200u: SKIP -> FAIL +1 fi-hsw-4770:SKIP -> FAIL fi-ivb-3770:SKIP -> FAIL fi-blb-e6850: SKIP -> FAIL fi-elk-e7500: SKIP -> FAIL fi-ilk-650: SKIP -> FAIL fi-hsw-4770r: SKIP -> FAIL fi-pnv-d510:SKIP -> FAIL igt@kms_addfb_basic@bad-pitch-0: fi-skl-6700k2: PASS -> FAIL +37 igt@kms_addfb_basic@bad-pitch-1024: fi-cfl-u2: PASS -> FAIL +36 fi-bxt-dsi: NOTRUN -> FAIL +37 igt@kms_addfb_basic@bad-pitch-63: fi-kbl-7567u: PASS -> FAIL +37 igt@kms_addfb_basic@bad-pitch-65536: fi-hsw-4200u: PASS -> FAIL +35 igt@kms_addfb_basic@bad-pitch-999: fi-hsw-peppy: PASS -> FAIL +35 igt@kms_addfb_basic@basic: fi-cnl-psr: PASS -> FAIL +36 igt@kms_addfb_basic@basic-x-tiled: fi-ivb-3520m: PASS -> FAIL +35 igt@kms_addfb_basic@clobberred-modifier: fi-skl-6770hq: PASS -> FAIL +37 igt@kms_addfb_basic@framebuffer-vs-set-tiling: fi-cfl-s3: PASS -> FAIL +37 igt@kms_addfb_basic@invalid-get-prop: fi-ivb-3770:PASS -> FAIL +36 igt@kms_addfb_basic@invalid-get-prop-any: fi-skl-6600u: PASS -> FAIL +36 igt@kms_addfb_basic@invalid-set-prop: fi-hsw-4770:PASS -> FAIL +36 fi-pnv-d510:PASS -> FAIL +36 igt@kms_addfb_basic@size-max: fi-snb-2520m: PASS -> FAIL +35 igt@kms_addfb_basic@tile-pitch-mismatch: fi-cfl-8700k: PASS -> FAIL +37 igt@kms_addfb_basic@too-high: fi-bwr-2160:PASS -> FAIL +36 fi-glk-j4005: PASS -> FAIL +37 igt@kms_addfb_basic@unused-handle: fi-elk-e7500: PASS -> FAIL +36 igt@kms_addfb_basic@unused-modifier: fi-bdw-5557u: PASS -> FAIL +36 fi-kbl-guc: PASS -> FAIL +36 igt@kms_addfb_basic@unused-offsets: fi-skl-guc: PASS -> FAIL +37 fi-blb-e6850: PASS -> FAIL +36 igt@kms_addfb_basic@unused-pitches: fi-bxt-j4205: PASS -> FAIL +37 fi-skl-6260u: PASS -> FAIL +37 igt@prime_vgem@basic-fence-flip: fi-hsw-4770r: PASS -> FAIL +36 fi-kbl-7500u: PASS -> FAIL +37 fi-cnl-psr: SKIP -> FAIL fi-hsw-peppy: SKIP -> FAIL +1 fi-kbl-r: SKIP -> FAIL fi-snb-2520m: SKIP -> FAIL +1 fi-skl-6600u: SKIP -> FAIL fi-cfl-u2: SKIP -> FAIL fi-kbl-7560u: SKIP -> FAIL fi-kbl-guc: SKIP -> FAIL Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS igt@kms_busy@basic-flip-a: fi-kbl-7567u: PASS -> SKIP +36 igt@kms_busy@basic-flip-b: fi-skl-6770hq: PASS -> SKIP +36 fi-byt-n2820: PASS -> SKIP +27 igt@kms_chamelium@hdmi-crc-fast: fi-skl-6700k2: PASS -> SKIP +40 igt@kms_cursor_legacy@basic-
[Intel-gfx] [PATCH] drm/i915/gtt: Make gen6 page directories evictable
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the creation of a custom vma to wrap the page
directory as opposed to a GEM object.
In this patch, we leave the page directories pinned upon creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
Put back vma->fence_size = size. I was overeager in trying to remove
unused members.
-Chris
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 257
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 7 +
3 files changed, 155 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd338bccf706..2c739e21c085 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1640,50 +1640,55 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base,
struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_address_space *vm = &base->vm;
- struct i915_page_table *unused;
- gen6_pte_t scratch_pte;
- u32 pd_entry, pte, pde;
-
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
-
- gen6_for_all_pdes(unused, &base->pd, pde) {
- u32 expected;
- gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
- pd_entry = readl(ppgtt->pd_addr + pde);
- expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
-
- if (pd_entry != expected)
- seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
- pde,
- pd_entry,
- expected);
- seq_printf(m, "\tPDE: %x\n", pd_entry);
-
- pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
-
- for (pte = 0; pte < GEN6_PTES; pte+=4) {
- unsigned long va =
- (pde * PAGE_SIZE * GEN6_PTES) +
- (pte * PAGE_SIZE);
+ const gen6_pte_t scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ struct i915_page_table *pt;
+ u32 pte, pde;
+
+ gen6_for_all_pdes(pt, &base->pd, pde) {
+ gen6_pte_t *vaddr;
+
+ if (pt == base->vm.scratch_pt)
+ continue;
+
+ if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
+ u32 expected =
+ GEN6_PDE_ADDR_ENCODE(px_dma(pt)) |
+ GEN6_PDE_VALID;
+ u32 pd_entry = readl(ppgtt->pd_addr + pde);
+
+ if (pd_entry != expected)
+ seq_printf(m,
+ "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
+ pde,
+ pd_entry,
+ expected);
+
+ seq_printf(m, "\tPDE: %x\n", pd_entry);
+ }
+
+ vaddr = kmap_atomic_px(base->pd.page_table[pde]);
+ for (pte = 0; pte < GEN6_PTES; pte += 4) {
int i;
- bool found = false;
+
for (i = 0; i < 4; i++)
- if (pt_vaddr[pte + i] != scratch_pte)
- found = true;
- if (!found)
+ if (vaddr[pte + i] != scratch_pte)
+ break;
+ if (i == 4)
continue;
- seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
+ seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
+ pde, pte,
+ (pde * GEN6_PTES + pte) * PAGE_SIZE);
for (i = 0; i < 4; i++) {
- if (pt_vaddr[pte + i] != scratch_pte)
- seq_printf(m, " %08x", pt_vaddr[pte +
i]);
+ if (vaddr[pte + i] != scratch_pte)
+ seq_printf(m, " %08x", vaddr[pte + i]);
else
- seq_puts(m, " SCRATCH ");
+ seq_puts(m, " SCRATCH");
}
seq_puts(m, "\n");
}
-
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: fix guest virtual PCH detection on non-PCH systems
== Series Details == Series: series starting with [1/5] drm/i915: fix guest virtual PCH detection on non-PCH systems URL : https://patchwork.freedesktop.org/series/44484/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9239 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44484/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9239 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (41 -> 38) == Additional (1): fi-bxt-dsi Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9239 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9239: 0b3ae319aae1ae31545d9cd3831377a33f3267be @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0b3ae319aae1 drm/i915: fix PCH_NOP setting for non-PCH platforms 8a6f31a1e314 drm/i915: be more strict about HAS_PCH_NOP() usage 81187d8bcb43 drm/i915: clean up virtual PCH special case handling e121641fac1b drm/i915: document PCH_NOP eee2855334c4 drm/i915: fix guest virtual PCH detection on non-PCH systems == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9239/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/18] drm/i915/gtt: Subclass gen6_hw_ppgtt
The legacy gen6 ppgtt needs a little more hand holding than gen8+, and
so requires a larger structure. As I intend to make this slightly more
complicated in the future, separate the gen6 from the core gen8 hw
struct by subclassing. This patch moves the gen6 only features out to
gen6_hw_ppgtt and pipes the new type everywhere that needs it.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 106 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 21 +++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 -
4 files changed, 75 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 091251c0e7fc..49e02dee07e0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1636,20 +1636,20 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
return ERR_PTR(err);
}
-static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
+static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
{
- struct i915_address_space *vm = &ppgtt->vm;
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+ struct i915_address_space *vm = &base->vm;
struct i915_page_table *unused;
gen6_pte_t scratch_pte;
u32 pd_entry, pte, pde;
- u32 start = 0, length = ppgtt->vm.total;
scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
- gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
+ gen6_for_all_pdes(unused, &base->pd, pde) {
u32 expected;
gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
+ const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
pd_entry = readl(ppgtt->pd_addr + pde);
expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
@@ -1660,7 +1660,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
expected);
seq_printf(m, "\tPDE: %x\n", pd_entry);
- pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]);
+ pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
for (pte = 0; pte < GEN6_PTES; pte+=4) {
unsigned long va =
@@ -1688,7 +1688,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
}
/* Write pde (index) from the page directory @pd to the page table @pt */
-static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt,
+static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
const unsigned int pde,
const struct i915_page_table *pt)
{
@@ -1699,26 +1699,27 @@ static inline void gen6_write_pde(const struct
i915_hw_ppgtt *ppgtt,
/* Write all the page tables found in the ppgtt structure to incrementing page
* directories. */
-static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
+static void gen6_write_page_range(struct i915_hw_ppgtt *base,
u32 start, u32 length)
{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_page_table *pt;
unsigned int pde;
- gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
+ gen6_for_each_pde(pt, &base->pd, start, length, pde)
gen6_write_pde(ppgtt, pde, pt);
- mark_tlbs_dirty(ppgtt);
- gen6_ggtt_invalidate(ppgtt->vm.i915);
+ mark_tlbs_dirty(base);
+ gen6_ggtt_invalidate(base->vm.i915);
}
-static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
+static inline u32 get_pd_offset(struct gen6_hw_ppgtt *ppgtt)
{
- GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
- return ppgtt->pd.base.ggtt_offset << 10;
+ GEM_BUG_ON(ppgtt->base.pd.base.ggtt_offset & 0x3f);
+ return ppgtt->base.pd.base.ggtt_offset << 10;
}
-static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
struct intel_engine_cs *engine = rq->engine;
@@ -1740,7 +1741,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
return 0;
}
-static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
struct intel_engine_cs *engine = rq->engine;
@@ -1762,7 +1763,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
return 0;
}
-static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int gen6_mm_switch(struct gen6_hw_ppgtt *ppgtt,
st
[Intel-gfx] [PATCH 11/18] drm/i915/gtt: Free unused page tables on unbind the context
As we cannot reliably change used page tables while the context is
active, the earliest opportunity we have to recover excess pages is when
the context becomes idle. So whenever we unbind the context (it must be
idle, and indeed being evicted) free the unused ptes.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 44 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e611884596a6..edb19648a85b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1814,20 +1814,28 @@ static void gen6_ppgtt_enable(struct drm_i915_private
*dev_priv)
static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
u64 start, u64 length)
{
- struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
unsigned int first_entry = start >> PAGE_SHIFT;
unsigned int pde = first_entry / GEN6_PTES;
unsigned int pte = first_entry % GEN6_PTES;
unsigned int num_entries = length >> PAGE_SHIFT;
- gen6_pte_t scratch_pte =
+ const gen6_pte_t scratch_pte =
vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
while (num_entries) {
- struct i915_page_table *pt = ppgtt->pd.page_table[pde++];
- unsigned int end = min(pte + num_entries, GEN6_PTES);
+ struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
+ const unsigned int end = min(pte + num_entries, GEN6_PTES);
+ const unsigned int count = end - pte;
gen6_pte_t *vaddr;
- num_entries -= end - pte;
+ GEM_BUG_ON(pt == vm->scratch_pt);
+
+ num_entries -= count;
+
+ GEM_BUG_ON(count > pt->used_ptes);
+ pt->used_ptes -= count;
+ if (!pt->used_ptes)
+ ppgtt->scan_for_unused_pt = true;
/*
* Note that the hw doesn't support removing PDE on the fly
@@ -1859,6 +1867,8 @@ static void gen6_ppgtt_insert_entries(struct
i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma);
gen6_pte_t *vaddr;
+ GEM_BUG_ON(ppgtt->pd.page_table[act_pt] == vm->scratch_pt);
+
vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
do {
vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
@@ -1894,6 +1904,8 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
bool flush = false;
gen6_for_each_pde(pt, &ppgtt->base.pd, start, length, pde) {
+ const unsigned int count = gen6_pte_count(start, length);
+
if (pt == vm->scratch_pt) {
pt = alloc_pt(vm);
if (IS_ERR(pt))
@@ -1907,7 +1919,11 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
gen6_write_pde(ppgtt, pde, pt);
flush = true;
}
+
+ GEM_BUG_ON(pt->used_ptes);
}
+
+ pt->used_ptes += count;
}
if (flush) {
@@ -2009,6 +2025,24 @@ static int pd_vma_bind(struct i915_vma *vma,
static void pd_vma_unbind(struct i915_vma *vma)
{
+ struct gen6_hw_ppgtt *ppgtt = vma->private;
+ struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt;
+ struct i915_page_table *pt;
+ unsigned int pde;
+
+ if (!ppgtt->scan_for_unused_pt)
+ return;
+
+ /* Free all no longer used page tables */
+ gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) {
+ if (pt->used_ptes || pt == scratch_pt)
+ continue;
+
+ free_pt(&ppgtt->base.vm, pt);
+ ppgtt->base.pd.page_table[pde] = scratch_pt;
+ }
+
+ ppgtt->scan_for_unused_pt = false;
}
static const struct i915_vma_ops pd_vma_ops = {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c20a4f06db37..dc98830fae69 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -414,6 +414,7 @@ struct gen6_hw_ppgtt {
gen6_pte_t __iomem *pd_addr;
unsigned int pin_count;
+ bool scan_for_unused_pt;
int (*switch_mm)(struct gen6_hw_ppgtt *ppgtt, struct i915_request *rq);
};
--
2.17.1
___
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[Intel-gfx] [PATCH 15/18] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
If we know that the user cannot access the GGTT, by virtue of having a segregated memory area, we can skip clearing the unused entries as they cannot be accessed. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0b434954f185..60a8332a122e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3451,7 +3451,9 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->vm.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; - ggtt->vm.clear_range = gen6_ggtt_clear_range; + ggtt->vm.clear_range = nop_clear_range; + if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) + ggtt->vm.clear_range = gen6_ggtt_clear_range; ggtt->vm.insert_page = gen6_ggtt_insert_page; ggtt->vm.insert_entries = gen6_ggtt_insert_entries; ggtt->vm.cleanup = gen6_gmch_remove; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/18] drm/i915/gtt: Remove redundant hsw_mm_switch()
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
1 file changed, 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 60a8332a122e..25ad94b1b67e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1697,28 +1697,6 @@ static inline u32 get_pd_offset(struct gen6_hw_ppgtt
*ppgtt)
return ppgtt->base.pd.base.ggtt_offset << 10;
}
-static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt,
-struct i915_request *rq)
-{
- struct intel_engine_cs *engine = rq->engine;
- u32 *cs;
-
- /* NB: TLBs must be flushed and invalidated before a switch */
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- *cs++ = MI_LOAD_REGISTER_IMM(2);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
- *cs++ = PP_DIR_DCLV_2G;
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
- *cs++ = get_pd_offset(ppgtt);
- *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
-
- return 0;
-}
-
static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
@@ -2148,8 +2126,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
if (intel_vgpu_active(i915) || IS_GEN6(i915))
ppgtt->switch_mm = gen6_mm_switch;
- else if (IS_HASWELL(i915))
- ppgtt->switch_mm = hsw_mm_switch;
else if (IS_GEN7(i915))
ppgtt->switch_mm = gen7_mm_switch;
else
--
2.17.1
___
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[Intel-gfx] [PATCH 04/18] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories
When we update the gen6 ppgtt page directories, we do so by writing the
new address into a reserved slot in the GGTT. It appears that when the
GPU reads that entry from the gsm, it uses its small cache and that we
need to invalidate that cache after writing. We don't see an issue
currently as we prefill the ppgtt page directories on creation; and only
create the single aliasing_ppgtt long before we start using the GGTT
(and so before the cache mayhave a conflicting entry).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6ac6520b6e9c..091251c0e7fc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1693,8 +1693,8 @@ static inline void gen6_write_pde(const struct
i915_hw_ppgtt *ppgtt,
const struct i915_page_table *pt)
{
/* Caller needs to make sure the write completes if necessary */
- writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
- ppgtt->pd_addr + pde);
+ iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
+ ppgtt->pd_addr + pde);
}
/* Write all the page tables found in the ppgtt structure to incrementing page
@@ -1709,7 +1709,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt,
gen6_write_pde(ppgtt, pde, pt);
mark_tlbs_dirty(ppgtt);
- wmb();
+ gen6_ggtt_invalidate(ppgtt->vm.i915);
}
static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1925,7 +1925,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
if (flush) {
mark_tlbs_dirty(ppgtt);
- wmb();
+ gen6_ggtt_invalidate(ppgtt->vm.i915);
}
return 0;
--
2.17.1
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[Intel-gfx] [PATCH 10/18] drm/i915/gtt: Lazily allocate page directories for gen7
As we were only supporting aliasing_ppgtt on gen7 for some time, we
saved a few checks by preallocating the page directories on creation.
However, since we need 2MiB of page directories for each ppgtt, to
support arbitrary numbers of user contexts, we need to be more prudent
in our allocations, and defer the page allocation until it is used. We
don't recover unused pages yet as we found that doing so on the fly
(i.e. altering TLB entries) would confuse the GPU.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++--
1 file changed, 26 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d5af099939f6..e611884596a6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -190,11 +190,19 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
return 1;
}
-static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 unused)
+static int ppgtt_bind_vma(struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 unused)
{
u32 pte_flags;
+ int err;
+
+ if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
+ err = vma->vm->allocate_va_range(vma->vm,
+vma->node.start, vma->size);
+ if (err)
+ return err;
+ }
/* Currently applicable only to VLV */
pte_flags = 0;
@@ -206,22 +214,6 @@ static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
return 0;
}
-static int gen8_ppgtt_bind_vma(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 unused)
-{
- int ret;
-
- if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
- ret = vma->vm->allocate_va_range(vma->vm,
-vma->node.start, vma->size);
- if (ret)
- return ret;
- }
-
- return gen6_ppgtt_bind_vma(vma, cache_level, unused);
-}
-
static void ppgtt_unbind_vma(struct i915_vma *vma)
{
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
@@ -1622,7 +1614,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
ppgtt->debug_dump = gen8_dump_ppgtt;
- ppgtt->vm.vma_ops.bind_vma= gen8_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.bind_vma= ppgtt_bind_vma;
ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->vm.vma_ops.clear_pages = clear_pages;
@@ -1837,7 +1829,8 @@ static void gen6_ppgtt_clear_range(struct
i915_address_space *vm,
num_entries -= end - pte;
- /* Note that the hw doesn't support removing PDE on the fly
+ /*
+* Note that the hw doesn't support removing PDE on the fly
* (they are cached inside the context with no means to
* invalidate the cache), so we can only reset the PTE
* entries back to scratch.
@@ -2106,12 +2099,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+ ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.debug_dump = gen6_dump_ppgtt;
- ppgtt->base.vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->base.vm.vma_ops.bind_vma= ppgtt_bind_vma;
ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
@@ -2136,14 +2130,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
goto err_scratch;
}
- err = gen6_alloc_va_range(&ppgtt->base.vm, 0, ppgtt->base.vm.total);
- if (err)
- goto err_vma;
-
return &ppgtt->base;
-err_vma:
- i915_vma_destroy(ppgtt->vma);
err_scratch:
gen6_ppgtt_free_scratch(&ppgtt->base.vm);
err_free:
@@ -2739,8 +2727,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
if (flags & I915_VMA_LOCAL_BIND) {
struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
- if (!(vma->flags & I915_VMA_LOCAL_BIND) &&
- appgtt->vm.allocate_va_range) {
+ if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
[Intel-gfx] [PATCH 13/18] drm/i915/gtt: Cache the PTE encoding of the scratch page
As the most frequent PTE encoding is for the scratch page, cache it upon
creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 79d63e16c2d4..58fd2ea77d00 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -640,11 +640,10 @@ static void gen8_initialize_pt(struct i915_address_space
*vm,
gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC));
}
-static void gen6_initialize_pt(struct i915_address_space *vm,
+static void gen6_initialize_pt(struct gen6_hw_ppgtt *ppgtt,
struct i915_page_table *pt)
{
- fill32_px(vm, pt,
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
+ fill32_px(&ppgtt->base.vm, pt, ppgtt->scratch_pte);
}
static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
@@ -1631,9 +1630,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
- struct i915_address_space *vm = &base->vm;
- const gen6_pte_t scratch_pte =
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ const gen6_pte_t scratch_pte = ppgtt->scratch_pte;
struct i915_page_table *pt;
u32 pte, pde;
@@ -1819,8 +1816,7 @@ static void gen6_ppgtt_clear_range(struct
i915_address_space *vm,
unsigned int pde = first_entry / GEN6_PTES;
unsigned int pte = first_entry % GEN6_PTES;
unsigned int num_entries = length >> PAGE_SHIFT;
- const gen6_pte_t scratch_pte =
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ const gen6_pte_t scratch_pte = ppgtt->scratch_pte;
while (num_entries) {
struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
@@ -1912,7 +1908,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
goto unwind_out;
if (count < GEN6_PTES)
- gen6_initialize_pt(vm, pt);
+ gen6_initialize_pt(ppgtt, pt);
ppgtt->base.pd.page_table[pde] = pt;
if (i915_vma_is_bound(ppgtt->vma,
@@ -1950,13 +1946,17 @@ static int gen6_ppgtt_init_scratch(struct gen6_hw_ppgtt
*ppgtt)
if (ret)
return ret;
+ ppgtt->scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr,
+ I915_CACHE_NONE, PTE_READ_ONLY);
+
vm->scratch_pt = alloc_pt(vm);
if (IS_ERR(vm->scratch_pt)) {
cleanup_scratch_page(vm);
return PTR_ERR(vm->scratch_pt);
}
- gen6_initialize_pt(vm, vm->scratch_pt);
+ gen6_initialize_pt(ppgtt, vm->scratch_pt);
gen6_for_all_pdes(unused, &ppgtt->base.pd, pde)
ppgtt->base.pd.page_table[pde] = vm->scratch_pt;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index dc98830fae69..c50bbde007f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -412,6 +412,7 @@ struct gen6_hw_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
+ gen6_pte_t scratch_pte;
unsigned int pin_count;
bool scan_for_unused_pt;
--
2.17.1
___
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[Intel-gfx] [PATCH 14/18] drm/i915/gtt: Reduce a pair of runtime asserts
We can stop asserting using WARN_ON as given sufficient CI coverage, we
can rely on using GEM_BUG_ON() to catch problems before merging.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 58fd2ea77d00..0b434954f185 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2861,7 +2861,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915)
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
- if (WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
+ if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
err = -ENODEV;
goto err_ppgtt;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c50bbde007f8..37f565a38d3e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -466,8 +466,8 @@ static inline u32 i915_pte_count(u64 addr, u64 length,
unsigned int pde_shift)
const u64 mask = ~((1ULL << pde_shift) - 1);
u64 end;
- WARN_ON(length == 0);
- WARN_ON(offset_in_page(addr|length));
+ GEM_BUG_ON(length == 0);
+ GEM_BUG_ON(offset_in_page(addr|length));
end = addr + length;
--
2.17.1
___
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[Intel-gfx] [PATCH 06/18] drm/i915/gtt: Onionify error handling for gen6_ppgtt_create
Pull the empty stubs together into the top level gen6_ppgtt_create, and
tear each one down on error in proper onion order (rather than use
Joonas' pet hate of calling the cleanup function in indeterminable
state).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 81 ++---
1 file changed, 39 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 49e02dee07e0..f9f0bffa727e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1936,7 +1936,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
return -ENOMEM;
}
-static int gen6_init_scratch(struct i915_address_space *vm)
+static int gen6_ppgtt_init_scratch(struct i915_address_space *vm)
{
int ret;
@@ -1955,33 +1955,37 @@ static int gen6_init_scratch(struct i915_address_space
*vm)
return 0;
}
-static void gen6_free_scratch(struct i915_address_space *vm)
+static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
{
free_pt(vm, vm->scratch_pt);
cleanup_scratch_page(vm);
}
-static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt)
{
- struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
struct i915_page_table *pt;
u32 pde;
- drm_mm_remove_node(&ppgtt->node);
-
gen6_for_all_pdes(pt, &ppgtt->base.pd, pde)
- if (pt != vm->scratch_pt)
- free_pt(vm, pt);
+ if (pt != ppgtt->base.vm.scratch_pt)
+ free_pt(&ppgtt->base.vm, pt);
+}
- gen6_free_scratch(vm);
+static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
+
+ drm_mm_remove_node(&ppgtt->node);
+
+ gen6_ppgtt_free_pd(ppgtt);
+ gen6_ppgtt_free_scratch(vm);
}
static int gen6_ppgtt_allocate_page_directories(struct gen6_hw_ppgtt *ppgtt)
{
- struct i915_address_space *vm = &ppgtt->base.vm;
struct drm_i915_private *dev_priv = ppgtt->base.vm.i915;
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- int ret;
+ int err;
/* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -1989,17 +1993,13 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
*/
BUG_ON(!drm_mm_initialized(&ggtt->vm.mm));
- ret = gen6_init_scratch(vm);
- if (ret)
- return ret;
-
- ret = i915_gem_gtt_insert(&ggtt->vm, &ppgtt->node,
+ err = i915_gem_gtt_insert(&ggtt->vm, &ppgtt->node,
GEN6_PD_SIZE, GEN6_PD_ALIGN,
I915_COLOR_UNEVICTABLE,
0, ggtt->vm.total,
PIN_HIGH);
- if (ret)
- goto err_out;
+ if (err)
+ return err;
if (ppgtt->node.start < ggtt->mappable_end)
DRM_DEBUG("Forced to use aperture for PDEs\n");
@@ -2011,15 +2011,6 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
ppgtt->base.pd.base.ggtt_offset / sizeof(gen6_pte_t);
return 0;
-
-err_out:
- gen6_free_scratch(vm);
- return ret;
-}
-
-static int gen6_ppgtt_alloc(struct gen6_hw_ppgtt *ppgtt)
-{
- return gen6_ppgtt_allocate_page_directories(ppgtt);
}
static void gen6_scratch_va_range(struct gen6_hw_ppgtt *ppgtt,
@@ -2045,6 +2036,18 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.i915 = i915;
ppgtt->base.vm.dma = &i915->drm.pdev->dev;
+ ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+
+ ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
+ ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
+ ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
+ ppgtt->base.debug_dump = gen6_dump_ppgtt;
+
+ ppgtt->base.vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
+
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
if (intel_vgpu_active(i915) || IS_GEN6(i915))
ppgtt->switch_mm = gen6_mm_switch;
@@ -2055,28 +2058,20 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
else
BUG();
- err = gen6_ppgtt_alloc(ppgtt);
+ err = gen6_ppgtt_init_scratch(&ppgtt->base.vm);
if (err)
goto err_free;
- ppgtt->base.vm.tota
[Intel-gfx] [PATCH 09/18] drm/i915/gtt: Only keep gen6 page directories pinned while active
In order to be able to evict the gen6 ppgtt, we have to unpin it at some
point. We can simply use our context activity tracking to know when the
ppgtt is no longer in use by hardware, and so only keep it pinned while
being used a request.
For the kernel_context (and thus aliasing_ppgtt), it remains pinned at
all times, as the kernel_context itself is pinned at all times.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++
3 files changed, 54 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 96f0638ab0f2..d5af099939f6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1973,7 +1973,6 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
- i915_vma_unpin(ppgtt->vma);
i915_vma_destroy(ppgtt->vma);
gen6_ppgtt_free_pd(ppgtt);
@@ -2058,10 +2057,19 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
return vma;
}
-static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+ /*
+* Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
+* which will be pinned into every active context.
+* (When vma->pin_count becomes atomic, I expect we will naturally
+* need a larger, unpacked, type and kill this redundancy.)
+*/
+ if (ppgtt->pin_count++)
+ return 0;
+
/*
* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -2072,6 +2080,17 @@ static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
PIN_GLOBAL | PIN_HIGH);
}
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+
+ GEM_BUG_ON(!ppgtt->pin_count);
+ if (--ppgtt->pin_count)
+ return;
+
+ i915_vma_unpin(ppgtt->vma);
+}
+
static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
struct i915_ggtt * const ggtt = &i915->ggtt;
@@ -2121,21 +2140,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (err)
goto err_vma;
- err = gen6_ppgtt_pin(&ppgtt->base);
- if (err)
- goto err_pd;
-
- DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
-ppgtt->vma->node.size >> 20,
-ppgtt->vma->node.start / PAGE_SIZE);
-
- DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
-ppgtt->base.pd.base.ggtt_offset << 10);
-
return &ppgtt->base;
-err_pd:
- gen6_ppgtt_free_pd(ppgtt);
err_vma:
i915_vma_destroy(ppgtt->vma);
err_scratch:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c2f270c90bea..c20a4f06db37 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -413,6 +413,8 @@ struct gen6_hw_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
+ unsigned int pin_count;
+
int (*switch_mm)(struct gen6_hw_ppgtt *ppgtt, struct i915_request *rq);
};
@@ -627,6 +629,9 @@ static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt)
kref_put(&ppgtt->ref, i915_ppgtt_release);
}
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
+
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ce07ef9471d2..e89012b66e7e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1178,6 +1178,27 @@ static void intel_ring_context_destroy(struct
intel_context *ce)
__i915_gem_object_release_unless_active(ce->state->obj);
}
+static int __context_pin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+ int err = 0;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+ if (ppgtt)
+ err = gen6_ppgtt_pin(ppgtt);
+
+ return err;
+}
+
+static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm
[Intel-gfx] [PATCH 03/18] drm/i915/ringbuffer: Fix context restore upon reset
The discovery with trying to enable full-ppgtt was that we were
completely failing to the load both the mm and context following the
reset. Although we were performing mmio to set the PP_DIR (per-process
GTT) and CCID (context), these were taking no effect (the assumption was
that this would trigger reload of the context and restore the page
tables). It was not until we performed the LRI + MI_SET_CONTEXT in a
following context switch would anything occur.
Since we are then required to reset the context image and PP_DIR using
CS commands, we place those commands into every batch. The hardware
should recognise the no-ops and eliminate the expensive context loads,
but we still have to pay the cost of using cross-powerwell register
writes. In practice, this has no effect on actual context switch times,
and only adds a few hundred nanoseconds to no-op switches. We can improve
the latter by eliminating the w/a around known no-op switches, but there
is an ulterior motive to keeping them.
Always emitting the context switch at the beginning of the request (and
relying on HW to skip unneeded switches) does have one key advantage.
Should we implement request reordering on Haswell, we will not know in
advance what the previous executing context was on the GPU and so we
would not be able to elide the MI_SET_CONTEXT commands ourselves and
always have to emit them. Having our hand forced now actually prepares
us for later.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 2 +
drivers/gpu/drm/i915/i915_request.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c | 3 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 75 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ---
5 files changed, 28 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f187250e60c6..9092f5464c24 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -817,6 +817,8 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
/* Keep a second pin for the dual retirement along engine and ring */
__intel_context_pin(ce);
+ rq->infix = rq->ring->emit; /* end of header; start of user payload */
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
return rq;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 491ff81d0fea..0e9aba53d0e4 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -134,6 +134,9 @@ struct i915_request {
/** Position in the ring of the start of the request */
u32 head;
+ /** Position in the ring of the start of the user packets */
+ u32 infix;
+
/**
* Position in the ring of the start of the postfix.
* This is required to calculate the maximum available ring space
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2ec2e60dc670..d1cf8b4926ab 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1168,9 +1168,6 @@ void intel_engine_lost_context(struct intel_engine_cs
*engine)
lockdep_assert_held(&engine->i915->drm.struct_mutex);
- engine->legacy_active_context = NULL;
- engine->legacy_active_ppgtt = NULL;
-
ce = fetch_and_zero(&engine->last_retired_context);
if (ce)
intel_context_unpin(ce);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 332d97bc5c27..1b3805adbd57 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -541,6 +541,21 @@ static struct i915_request *reset_prepare(struct
intel_engine_cs *engine)
return i915_gem_find_active_request(engine);
}
+static void skip_request(struct i915_request *request)
+{
+ void *vaddr = request->ring->vaddr;
+ u32 head;
+
+ head = request->infix;
+ if (request->postfix < head) {
+ memset32(vaddr + head, MI_NOOP,
+(request->ring->size - head) / sizeof(u32));
+ head = 0;
+ }
+ memset32(vaddr + head, MI_NOOP,
+(request->postfix - head) / sizeof(u32));
+}
+
static void reset_ring(struct intel_engine_cs *engine,
struct i915_request *request)
{
@@ -570,42 +585,10 @@ static void reset_ring(struct intel_engine_cs *engine,
* the restored context.
*/
if (request) {
- struct drm_i915_private *dev_priv = request->i915;
- struct intel_context *ce = request->hw_context;
- struct i915_hw_ppgtt *ppgtt;
-
- if (ce->state) {
-
[Intel-gfx] Haswell full-ppgtt, no really
The GPU hangs in mesa (piglit at least) were resolved, and GPU reset should now be operational. So as far as CI goes, we should have a clean bill of health. There is still one outstanding issue as Baytail still has the habit of writing to somewhere other than the intended mm. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/18] drm/i915/gtt: Skip initializing PT with scratch if full
If we will completely overwrite the PT with PTEs for the object, we can
forgo filling it with scratch entries.
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index edb19648a85b..79d63e16c2d4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1911,7 +1911,8 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
if (IS_ERR(pt))
goto unwind_out;
- gen6_initialize_pt(vm, pt);
+ if (count < GEN6_PTES)
+ gen6_initialize_pt(vm, pt);
ppgtt->base.pd.page_table[pde] = pt;
if (i915_vma_is_bound(ppgtt->vma,
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/18] RFT drm/i915/gtt: Enable full-ppgtt by default everywhere
Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
let userspace have full control over their own ppgtt, it makes softpinning
far more effective, in turn making GPU dispatch far more efficient and
more secure (due to better mm segregation).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ca067d9adf54..a181fe20964e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
return 0;
}
- if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
- if (has_full_48bit_ppgtt)
- return 3;
+ if (has_full_48bit_ppgtt)
+ return 3;
- if (has_full_ppgtt)
- return 2;
- }
+ if (has_full_ppgtt)
+ return 2;
return 1;
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/18] drm/i915/gtt: Remove vgpu check for gen6
Since vgpu is not supported on Haswell or any other gen6/7, we do not need to check and act upon it's enablement. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 25ad94b1b67e..ca067d9adf54 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2124,7 +2124,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) ppgtt->base.vm.vma_ops.clear_pages = clear_pages; ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; - if (intel_vgpu_active(i915) || IS_GEN6(i915)) + if (IS_GEN6(i915)) ppgtt->switch_mm = gen6_mm_switch; else if (IS_GEN7(i915)) ppgtt->switch_mm = gen7_mm_switch; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/18] drm/i915/gtt: Make gen6 page directories evictable
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the creation of a custom vma to wrap the page
directory as opposed to a GEM object.
In this patch, we leave the page directories pinned upon creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 256
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 7 +
3 files changed, 154 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd338bccf706..96f0638ab0f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1640,50 +1640,55 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base,
struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_address_space *vm = &base->vm;
- struct i915_page_table *unused;
- gen6_pte_t scratch_pte;
- u32 pd_entry, pte, pde;
-
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
-
- gen6_for_all_pdes(unused, &base->pd, pde) {
- u32 expected;
- gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
- pd_entry = readl(ppgtt->pd_addr + pde);
- expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
-
- if (pd_entry != expected)
- seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
- pde,
- pd_entry,
- expected);
- seq_printf(m, "\tPDE: %x\n", pd_entry);
-
- pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
-
- for (pte = 0; pte < GEN6_PTES; pte+=4) {
- unsigned long va =
- (pde * PAGE_SIZE * GEN6_PTES) +
- (pte * PAGE_SIZE);
+ const gen6_pte_t scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ struct i915_page_table *pt;
+ u32 pte, pde;
+
+ gen6_for_all_pdes(pt, &base->pd, pde) {
+ gen6_pte_t *vaddr;
+
+ if (pt == base->vm.scratch_pt)
+ continue;
+
+ if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
+ u32 expected =
+ GEN6_PDE_ADDR_ENCODE(px_dma(pt)) |
+ GEN6_PDE_VALID;
+ u32 pd_entry = readl(ppgtt->pd_addr + pde);
+
+ if (pd_entry != expected)
+ seq_printf(m,
+ "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
+ pde,
+ pd_entry,
+ expected);
+
+ seq_printf(m, "\tPDE: %x\n", pd_entry);
+ }
+
+ vaddr = kmap_atomic_px(base->pd.page_table[pde]);
+ for (pte = 0; pte < GEN6_PTES; pte += 4) {
int i;
- bool found = false;
+
for (i = 0; i < 4; i++)
- if (pt_vaddr[pte + i] != scratch_pte)
- found = true;
- if (!found)
+ if (vaddr[pte + i] != scratch_pte)
+ break;
+ if (i == 4)
continue;
- seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
+ seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
+ pde, pte,
+ (pde * GEN6_PTES + pte) * PAGE_SIZE);
for (i = 0; i < 4; i++) {
- if (pt_vaddr[pte + i] != scratch_pte)
- seq_printf(m, " %08x", pt_vaddr[pte +
i]);
+ if (vaddr[pte + i] != scratch_pte)
+ seq_printf(m, " %08x", vaddr[pte + i]);
else
- seq_puts(m, " SCRATCH ");
+ seq_puts(m, " SCRATCH");
}
seq_puts(m, "\n");
}
- kunmap_atomic(pt_vaddr);
+ kunmap_atomic(vaddr);
}
}
@@ -16
[Intel-gfx] [PATCH 07/18] drm/i915/gtt: Reorder aliasing_ppgtt fini
To allow ourselves to use a first class vma for the aliasing_ppgtt page directory, we have to reorder the shutdown on module unload to remove and unpin the aliasing_ppgtt before complaining about any objects left in the GGTT. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f9f0bffa727e..bd338bccf706 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2891,15 +2891,11 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) ggtt->vm.closed = true; mutex_lock(&dev_priv->drm.struct_mutex); + i915_gem_fini_aliasing_ppgtt(dev_priv); + GEM_BUG_ON(!list_empty(&ggtt->vm.active_list)); list_for_each_entry_safe(vma, vn, &ggtt->vm.inactive_list, vm_link) WARN_ON(i915_vma_unbind(vma)); - mutex_unlock(&dev_priv->drm.struct_mutex); - - i915_gem_cleanup_stolen(&dev_priv->drm); - - mutex_lock(&dev_priv->drm.struct_mutex); - i915_gem_fini_aliasing_ppgtt(dev_priv); if (drm_mm_node_allocated(&ggtt->error_capture)) drm_mm_remove_node(&ggtt->error_capture); @@ -2921,6 +2917,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) arch_phys_wc_del(ggtt->mtrr); io_mapping_fini(&ggtt->iomap); + + i915_gem_cleanup_stolen(&dev_priv->drm); } static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/18] drm/i915: Apply batch location restrictions before pinning
We special case the position of the batch within the GTT to prevent
negative self-relocation deltas from underflowing. However, that
restriction is being applied after a trial pin of the batch in its
current position. Thus we are not rejecting an invalid location if the
batch has been before, leading to an assertion if we happen to need to
rearrange the entire payload. In the worst case, this may cause a GPU
hang on gen7 or perhaps missing state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=105720
Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the
execobjects array")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Martin Peres
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 49 --
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index eefd449502e2..2d2eb3075960 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -489,7 +489,9 @@ eb_validate_vma(struct i915_execbuffer *eb,
}
static int
-eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
+eb_add_vma(struct i915_execbuffer *eb,
+ unsigned int i, unsigned batch_idx,
+ struct i915_vma *vma)
{
struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
int err;
@@ -522,6 +524,24 @@ eb_add_vma(struct i915_execbuffer *eb, unsigned int i,
struct i915_vma *vma)
eb->flags[i] = entry->flags;
vma->exec_flags = &eb->flags[i];
+ /*
+* SNA is doing fancy tricks with compressing batch buffers, which leads
+* to negative relocation deltas. Usually that works out ok since the
+* relocate address is still positive, except when the batch is placed
+* very low in the GTT. Ensure this doesn't happen.
+*
+* Note that actual hangs have only been observed on gen7, but for
+* paranoia do it everywhere.
+*/
+ if (i == batch_idx) {
+ if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
+ eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
+ if (eb->reloc_cache.has_fence)
+ eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
+
+ eb->batch = vma;
+ }
+
err = 0;
if (eb_pin_vma(eb, entry, vma)) {
if (entry->offset != vma->node.start) {
@@ -716,7 +736,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
struct drm_i915_gem_object *obj;
- unsigned int i;
+ unsigned int i, batch;
int err;
if (unlikely(i915_gem_context_is_closed(eb->ctx)))
@@ -728,6 +748,8 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
INIT_LIST_HEAD(&eb->relocs);
INIT_LIST_HEAD(&eb->unbound);
+ batch = eb_batch_index(eb);
+
for (i = 0; i < eb->buffer_count; i++) {
u32 handle = eb->exec[i].handle;
struct i915_lut_handle *lut;
@@ -770,33 +792,16 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
lut->handle = handle;
add_vma:
- err = eb_add_vma(eb, i, vma);
+ err = eb_add_vma(eb, i, batch, vma);
if (unlikely(err))
goto err_vma;
GEM_BUG_ON(vma != eb->vma[i]);
GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
+ GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
+ eb_vma_misplaced(&eb->exec[i], vma, eb->flags[i]));
}
- /* take note of the batch buffer before we might reorder the lists */
- i = eb_batch_index(eb);
- eb->batch = eb->vma[i];
- GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]);
-
- /*
-* SNA is doing fancy tricks with compressing batch buffers, which leads
-* to negative relocation deltas. Usually that works out ok since the
-* relocate address is still positive, except when the batch is placed
-* very low in the GTT. Ensure this doesn't happen.
-*
-* Note that actual hangs have only been observed on gen7, but for
-* paranoia do it everywhere.
-*/
- if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
- eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
- if (eb->reloc_cache.has_fence)
- eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
-
eb->args->flags |= __EXEC_VALIDATED;
return eb_reserve(eb);
--
2.17.1
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[Intel-gfx] [PATCH 02/18] drm/i915/ringbuffer: Brute force context restore
An issue encountered with switching mm on gen7 is that the GPU likes to
hang (with the VS unit busy) when told to force restore the current
context. We can simply workaround this by substituting the
MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
forcing the context to be saved and restored; thereby reloading the
PP_DIR registers and updating the modified page directory!
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 65811e2fa7da..332d97bc5c27 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1458,6 +1458,7 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
INTEL_INFO(i915)->num_rings - 1 :
0;
+ bool force_restore = false;
int len;
u32 *cs;
@@ -1471,6 +1472,12 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+ if (flags & MI_FORCE_RESTORE) {
+ GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
+ flags &= ~MI_FORCE_RESTORE;
+ force_restore = true;
+ len += 2;
+ }
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1496,6 +1503,20 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
}
*cs++ = MI_NOOP;
+ if (force_restore) {
+ /*
+* The HW doesn't handle being told to restore the current
+* context very well. Quite often it likes goes to go off and
+* sulk, especially when it is meant to be reloading PP_DIR.
+* A very simple fix to force the reload is to simply switch
+* away from the current context and back again.
+*/
+ *cs++ = MI_SET_CONTEXT;
+ *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
+ engine)->state) |
+ MI_MM_SPACE_GTT |
+ MI_RESTORE_INHIBIT;
+ }
*cs++ = MI_SET_CONTEXT;
*cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
/*
@@ -1585,11 +1606,14 @@ static int switch_context(struct i915_request *rq)
to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
engine->legacy_active_ppgtt = to_mm;
- hw_flags = MI_FORCE_RESTORE;
+
+ if (to_ctx == from_ctx) {
+ hw_flags = MI_FORCE_RESTORE;
+ from_ctx = NULL;
+ }
}
- if (rq->hw_context->state &&
- (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
+ if (rq->hw_context->state && to_ctx != from_ctx) {
GEM_BUG_ON(engine->id != RCS);
/*
--
2.17.1
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Re: [Intel-gfx] [bug report] drm/i915/bios: add support for MIPI sequence block v3
On Fri, 08 Jun 2018, Dan Carpenter wrote:
> Hello Jani Nikula,
>
> The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
> block v3" from Jan 11, 2016, leads to the following static checker
> warning:
>
> drivers/gpu/drm/i915/intel_bios.c:926 goto_next_sequence_v3()
> warn: potentially one past the end of array 'data[index]'
>
> drivers/gpu/drm/i915/intel_bios.c
>897 /* Skip Sequence Byte. */
>898 index++;
>899
>900 /*
>901 * Size of Sequence. Excludes the Sequence Byte and the size
> itself,
>902 * includes MIPI_SEQ_ELEM_END byte, excludes the final
> MIPI_SEQ_END
>903 * byte.
>904 */
>905 size_of_sequence = *((const uint32_t *)(data + index));
>906 index += 4;
>907
>908 seq_end = index + size_of_sequence;
>909 if (seq_end > total) {
>910 DRM_ERROR("Invalid sequence size\n");
>911 return 0;
>912 }
>913
>914 for (; index < total; index += len) {
The data being parsed here is a sort of TLV coded blob with len here
referring to the payload length.
It's a sort of TLV coded blob with len here referring to the payload
length. T being the 1-byte operation_byte, L being the 1-byte len.
>915 u8 operation_byte = *(data + index);
index is now at T, or operation byte.
>916 index++;
> ^^^
index is now at L, or length.
>917
>918 if (operation_byte == MIPI_SEQ_ELEM_END) {
it could also be a marker for end of the whole thing, in which case the
operation_byte is 0.
>919 if (index != seq_end) {
>920 DRM_ERROR("Invalid element
> structure\n");
>921 return 0;
>922 }
>923 return index;
>924 }
>925
>926 len = *(data + index);
> ^
> This does look to uninitiated eyes as if it might be one past the end?
>
>927 index++;
index is now at the payload, which is len bytes.
Makes sense? N.b. I didn't specify the format...
BR,
Jani.
>928
>929 /*
>930 * FIXME: Would be nice to check elements like for
> v1/v2 in
>931 * goto_next_sequence() above.
>932 */
>933 switch (operation_byte) {
>934 case MIPI_SEQ_ELEM_SEND_PKT:
>935 case MIPI_SEQ_ELEM_DELAY:
>936 case MIPI_SEQ_ELEM_GPIO:
>937 case MIPI_SEQ_ELEM_I2C:
>938 case MIPI_SEQ_ELEM_SPI:
>939 case MIPI_SEQ_ELEM_PMIC:
>940 break;
>941 default:
>
> regards,
> dan carpenter
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [CI HACK PATCH] HACK: drm/i915: see what breaks with display disabled
We don't properly test the i915.disable_display=1 module parameter. We have one display info with .num_pipes = 0, but AFAIK there are others than ivb q. Let's see what CI says of this for platforms with display. *evil grin*. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index aebe0469ddaa..5024461fe965 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -64,7 +64,7 @@ struct drm_printer; param(bool, load_detect_test, false) \ param(bool, force_reset_modeset_test, false) \ param(bool, error_capture, true) \ - param(bool, disable_display, false) \ + param(bool, disable_display, true) \ param(bool, verbose_state_checks, true) \ param(bool, nuclear_pageflip, false) \ param(bool, enable_dp_mst, true) \ -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [bug report] drm/i915/bios: add support for MIPI sequence block v3
Hello Jani Nikula,
The patch 2a33d93486f2: "drm/i915/bios: add support for MIPI sequence
block v3" from Jan 11, 2016, leads to the following static checker
warning:
drivers/gpu/drm/i915/intel_bios.c:926 goto_next_sequence_v3()
warn: potentially one past the end of array 'data[index]'
drivers/gpu/drm/i915/intel_bios.c
897 /* Skip Sequence Byte. */
898 index++;
899
900 /*
901 * Size of Sequence. Excludes the Sequence Byte and the size
itself,
902 * includes MIPI_SEQ_ELEM_END byte, excludes the final
MIPI_SEQ_END
903 * byte.
904 */
905 size_of_sequence = *((const uint32_t *)(data + index));
906 index += 4;
907
908 seq_end = index + size_of_sequence;
909 if (seq_end > total) {
910 DRM_ERROR("Invalid sequence size\n");
911 return 0;
912 }
913
914 for (; index < total; index += len) {
915 u8 operation_byte = *(data + index);
916 index++;
^^^
917
918 if (operation_byte == MIPI_SEQ_ELEM_END) {
919 if (index != seq_end) {
920 DRM_ERROR("Invalid element
structure\n");
921 return 0;
922 }
923 return index;
924 }
925
926 len = *(data + index);
^
This does look to uninitiated eyes as if it might be one past the end?
927 index++;
928
929 /*
930 * FIXME: Would be nice to check elements like for
v1/v2 in
931 * goto_next_sequence() above.
932 */
933 switch (operation_byte) {
934 case MIPI_SEQ_ELEM_SEND_PKT:
935 case MIPI_SEQ_ELEM_DELAY:
936 case MIPI_SEQ_ELEM_GPIO:
937 case MIPI_SEQ_ELEM_I2C:
938 case MIPI_SEQ_ELEM_SPI:
939 case MIPI_SEQ_ELEM_PMIC:
940 break;
941 default:
regards,
dan carpenter
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[Intel-gfx] [PATCH 2/5] drm/i915: document PCH_NOP
From: Lucas De Marchi
There's a difference between PCH_NONE and PCH_NOP: the former means we
don't have a PCH while in the latter we do, but it doesn't have the
south display.
Signed-off-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4073666f1ca..71651ca7a8b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -632,7 +632,7 @@ enum intel_pch {
PCH_KBP,/* Kaby Lake PCH */
PCH_CNP,/* Cannon Lake PCH */
PCH_ICP,/* Ice Lake PCH */
- PCH_NOP,
+ PCH_NOP,/* PCH without south display */
};
enum intel_sbi_destination {
--
2.11.0
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix guest virtual PCH detection on non-PCH systems
On Thu, 31 May 2018, Lucas De Marchi wrote:
> On Thu, May 31, 2018 at 02:56:21PM +0300, Jani Nikula wrote:
>> Virtualized non-PCH systems such as Broxton or Geminilake should use
>> PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
>> specific case to indicate a PCH system without south display.
>
> Then let's go ahead and document it?
Please avoid sending suggestion patches in-reply-to existing
series. This confused patchwork and screwed up CI for the series, which
was already a resend just to get CI. :(
I'm resending the series, with your documentation patch added, but I'm
keeping the extra explanatory text in the last patch. I think it's
warranted.
BR,
Jani.
>
> -
> Subject: [PATCH] drm/i915: document PCH_NOP
>
> There's a difference between PCH_NONE and PCH_NOP: the former means we
> don't have a PCH while in the latter we do, but it doesn't have the
> south display.
>
> Cc: Jani Nikula
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72150f89f200..aa395a898258 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -631,7 +631,7 @@ enum intel_pch {
> PCH_KBP,/* Kaby Lake PCH */
> PCH_CNP,/* Cannon Lake PCH */
> PCH_ICP,/* Ice Lake PCH */
> - PCH_NOP,
> + PCH_NOP,/* PCH without south display */
> };
>
> enum intel_sbi_destination {
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH 5/5] drm/i915: fix PCH_NOP setting for non-PCH platforms
Setting PCH type to PCH_NOP before checking whether we actually have a
PCH ends up returning true for HAS_PCH_SPLIT() on all non-PCH split
platforms. Fix this by using PCH_NOP only for platforms that actually
have a PCH.
Cc: Ville Syrjala
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6b6c9c040617..d76f73e69468 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -248,14 +248,6 @@ static void intel_detect_pch(struct drm_i915_private
*dev_priv)
{
struct pci_dev *pch = NULL;
- /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
-* (which really amounts to a PCH but no South Display).
-*/
- if (INTEL_INFO(dev_priv)->num_pipes == 0) {
- dev_priv->pch_type = PCH_NOP;
- return;
- }
-
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
@@ -295,6 +287,17 @@ static void intel_detect_pch(struct drm_i915_private
*dev_priv)
break;
}
}
+
+ /*
+* Use PCH_NOP (PCH but no South Display) for PCH platforms without
+* display.
+*/
+ if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
+ DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
+ dev_priv->pch_type = PCH_NOP;
+ dev_priv->pch_id = 0;
+ }
+
if (!pch)
DRM_DEBUG_KMS("No PCH found.\n");
--
2.11.0
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[Intel-gfx] [PATCH 3/5] drm/i915: clean up virtual PCH special case handling
Use intel_pch_type() also for mapping the no PCH case (PCH id 0) to
PCH_NONE to simplify code.
Also make sure that intel_pch_type() knows all the PCH ids returned by
intel_virt_detect_pch(). Loudly fail if this isn't the case; this
shouldn't happen anyway.
Cc: Colin Xu
Reviewed-by: Ville Syrjälä
Tested-by: Colin Xu
Reviewed-by: Colin Xu
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dfe6e8f2b52f..6b6c9c040617 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -284,13 +284,12 @@ static void intel_detect_pch(struct drm_i915_private
*dev_priv)
} else if (intel_is_virt_pch(id, pch->subsystem_vendor,
pch->subsystem_device)) {
id = intel_virt_detect_pch(dev_priv);
- if (id) {
- pch_type = intel_pch_type(dev_priv, id);
- if (WARN_ON(pch_type == PCH_NONE))
- pch_type = PCH_NOP;
- } else {
- pch_type = PCH_NONE;
- }
+ pch_type = intel_pch_type(dev_priv, id);
+
+ /* Sanity check virtual PCH id */
+ if (WARN_ON(id && pch_type == PCH_NONE))
+ id = 0;
+
dev_priv->pch_type = pch_type;
dev_priv->pch_id = id;
break;
--
2.11.0
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[Intel-gfx] [PATCH 4/5] drm/i915: be more strict about HAS_PCH_NOP() usage
HAS_PCH_NOP() implies a PCH platform without south display, not generic
disabled display. Prefer num_pipes == 0 for PCH independent checks.
Cc: Ville Syrjala
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 465dff4780fe..18b9e0444116 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1719,7 +1719,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (HAS_PCH_NOP(dev_priv)) {
+ if (INTEL_INFO(dev_priv)->num_pipes == 0) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e6875509bcd9..61729bf84e08 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -771,7 +771,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (HAS_PCH_NOP(dev_priv))
+ if (INTEL_INFO(dev_priv)->num_pipes == 0)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--
2.11.0
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[Intel-gfx] [PATCH 1/5] drm/i915: fix guest virtual PCH detection on non-PCH systems
Virtualized non-PCH systems such as Broxton or Geminilake should use
PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
specific case to indicate a PCH system without south display.
Reported-by: Colin Xu
Cc: Colin Xu
Reviewed-by: Ville Syrjälä
Tested-by: Colin Xu
Reviewed-by: Colin Xu
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index be71fdf8d92e..dfe6e8f2b52f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -289,7 +289,7 @@ static void intel_detect_pch(struct drm_i915_private
*dev_priv)
if (WARN_ON(pch_type == PCH_NONE))
pch_type = PCH_NOP;
} else {
- pch_type = PCH_NOP;
+ pch_type = PCH_NONE;
}
dev_priv->pch_type = pch_type;
dev_priv->pch_id = id;
--
2.11.0
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[Intel-gfx] drm/i915: virtual PCH and PCH_NOP fixes
Just a resend of [1] with Lucas' patch added. BR, Jani. [1] 20180531115624.30269-1-jani.nikula@intel.com">http://mid.mail-archive.com/20180531115624.30269-1-jani.nikula@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next-fixes for drm-next/v4.18
Hi Dave, these missed the main drm-next pull request. drm-intel-next-fixes-2018-06-08-2: First batch of i915 fixes for v4.18: - gvt fixes that missed v4.17, potentially need to be backported - eDP resolution regression revert - remove broken nv12 special casing - remove stale asserts from find active requests BR, Jani. The following changes since commit 315852b422972e6ebb1dfddaadada09e46a2681a: drm: rcar-du: Fix build failure (2018-05-17 15:03:40 +1000) are available in the git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2018-06-08-2 for you to fetch changes up to 807cba6559cf333a74df1fbd74f0597e8e7fa020: Merge tag 'gvt-fixes-2018-04-19' of https://github.com/intel/gvt-linux into drm-intel-next-fixes (2018-06-07 12:06:07 +0300) First batch of i915 fixes for v4.18: - gvt fixes that missed v4.17, potentially need to be backported - eDP resolution regression revert - remove broken nv12 special casing - remove stale asserts from find active requests Changbin Du (2): drm/i915/gvt: Fix the validation on size field of dp aux header drm/i915/kvmgt: Check the pfn got from vfio_pin_pages Chris Wilson (2): drm/i915: Nul-terminate legacy debug string drm/i915: Remove stale asserts from i915_gem_find_active_request() Colin Ian King (1): drm/i915/gvt: fix memory leak of a cmd_entry struct on error exit path Jani Nikula (2): Revert "drm/i915/edp: Allow alternate fixed mode for eDP if available." Merge tag 'gvt-fixes-2018-04-19' of https://github.com/intel/gvt-linux into drm-intel-next-fixes Mahesh Kumar (2): drm/i915/icl: fix icl_unmap/map_plls_to_ports drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw Ville Syrjälä (1): drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup Xiong Zhang (1): drm/i915/gvt: Dereference msi eventfd_ctx when it isn't used anymore Zhenyu Wang (1): Back merge 'drm-intel-fixes' into gvt-fixes drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c| 13 drivers/gpu/drm/i915/gvt/kvmgt.c | 34 +- drivers/gpu/drm/i915/i915_gem.c| 17 +++ drivers/gpu/drm/i915/intel_ddi.c | 6 -- drivers/gpu/drm/i915/intel_display.c | 7 +-- drivers/gpu/drm/i915/intel_dp.c| 38 +- drivers/gpu/drm/i915/intel_drv.h | 2 -- drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 3 +-- drivers/gpu/drm/i915/intel_panel.c | 6 -- drivers/gpu/drm/i915/intel_pm.c| 1 - 15 files changed, 66 insertions(+), 70 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-fixes for 4.17
On Wed, 06 Jun 2018, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2018-06-06 10:49:54) >> On 2018.04.19 15:39:48 +0800, Zhenyu Wang wrote: >> > >> > Hi, >> > >> > Here's current gvt fixes for 4.17 with several kernel warning >> > and other misc fixes as detailed below. >> > >> > p.s: I'll be on vacation from next week till May 2, Zhi will cover for me. >> > >> > Thanks >> > -- >> >> Looks this one got missed for merge...just found when trying to apply new >> change that caused conflict..Pls help to merge and will request a backmerge >> to apply -next change against those. > > As discussed in IRC, the gvt-next PR was as --in-reply-to for this > message, so I indeed confused it for being discussion about the gvt-next > between Jani and Zhi, and missed it :( So this missed v4.17. I've now pulled this into drm-intel-next-fixes, and it'll get merged upstream for v4.18. If you need the commits backported, you'll need to make stable backport requests to the stable team after the commits have been merged to Linus' master. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table
On Thu, 07 Jun 2018, Radhakrishna Sripada
wrote:
> From: "Sripada, Radhakrishna"
>
> Expand the Maud/Naud table according to DP 1.4 spec to include entries for
> 810 MHz clock. This is required for audio to work with HBR3.
>
> Cc: Dhinakaran Pandiyan
> Cc: Jani Nikula
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_audio.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..6d1c33066987 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -59,6 +59,7 @@
> */
>
> /* DP N/M table */
> +#define LC_810M 81
> #define LC_540M 54
> #define LC_270M 27
> #define LC_162M 162000
> @@ -99,6 +100,15 @@ static const struct dp_aud_n_m dp_aud_n_m[] = {
> { 128000, LC_540M, 4096, 33750 },
> { 176400, LC_540M, 3136, 18750 },
> { 192000, LC_540M, 2048, 11250 },
> + { 32000, LC_810M, 1024, 50625 },
> + { 44100, LC_810M, 784, 28125 },
> + { 48000, LC_810M, 512, 16875 },
> + { 64000, LC_810M, 2048, 50625 },
> + { 88200, LC_810M, 1568, 28125 },
> + { 96000, LC_810M, 1024, 16875 },
> + { 128000, LC_810M, 4096, 50625 },
> + { 176400, LC_810M, 3136, 28125 },
> + { 192000, LC_810M, 2048, 16875 },
> };
>
> static const struct dp_aud_n_m *
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Store first production revid into device info (rev2)
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info (rev2) URL : https://patchwork.freedesktop.org/series/44429/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9238 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9238 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9238, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44429/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9238: === IGT changes === Possible regressions igt@drv_module_reload@basic-no-display: fi-cfl-s3: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload: fi-cfl-8700k: PASS -> DMESG-WARN +2 fi-cfl-guc: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload-inject: fi-cfl-u2: PASS -> DMESG-WARN +2 == Known issues == Here are the changes found in Patchwork_9238 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: PASS -> FAIL (fdo#103481) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) Possible fixes igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: DMESG-FAIL (fdo#103841) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000, fdo#106097) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 38) == Additional (1): fi-bxt-dsi Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4294 -> Patchwork_9238 CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9238: 2c53f1798c4f1b1e6269655971119ea450f5f725 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2c53f1798c4f drm/i915: Warn on obsolete revision checks 5eeb7818c8d9 drm/i915: Remove kbl preproduction workarounds 03ad36c85d35 drm/i915: Add a define for first production revid 5c8cb615b9b4 drm/i915: Move chipset definitions to intel_chipset.h 3fb49f40c250 drm/i915: Use unknown production revid as alpha quality flag c1df0dd08b23 drm/i915: Store first production revid into device info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9238/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Store first production revid into device info (rev2)
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info (rev2) URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Store first production revid into device info -drivers/gpu/drm/i915/selftests/../i915_drv.h:3669:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void) Commit: drm/i915: Use unknown production revid as alpha quality flag -drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) Commit: drm/i915: Move chipset definitions to intel_chipset.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3477:16: warning: expression using sizeof(void) Commit: drm/i915: Add a define for first production revid Okay! Commit: drm/i915: Remove kbl preproduction workarounds Okay! Commit: drm/i915: Warn on obsolete revision checks Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Store first production revid into device info (rev2)
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info (rev2) URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim checkpatch origin/drm-tip c1df0dd08b23 drm/i915: Store first production revid into device info -:60: WARNING:LONG_LINE: line over 100 characters #60: FILE: drivers/gpu/drm/i915/i915_drv.h:2435: +#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))) -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/i915_drv.h:2435: +#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))) total: 0 errors, 1 warnings, 1 checks, 99 lines checked 3fb49f40c250 drm/i915: Use unknown production revid as alpha quality flag 5c8cb615b9b4 drm/i915: Move chipset definitions to intel_chipset.h -:231: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #231: new file mode 100644 -:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 's' - possible side-effects? #252: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e' - possible side-effects? #252: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:272: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #272: FILE: drivers/gpu/drm/i915/intel_chipset.h:37: +#define IS_REVID(p, since, until) \ + (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #289: FILE: drivers/gpu/drm/i915/intel_chipset.h:54: +#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -:296: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #296: FILE: drivers/gpu/drm/i915/intel_chipset.h:61: +#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ +(dev_priv)->info.gt == 1) -:310: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #310: FILE: drivers/gpu/drm/i915/intel_chipset.h:75: +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -:312: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #312: FILE: drivers/gpu/drm/i915/intel_chipset.h:77: +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ +((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -:317: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #317: FILE: drivers/gpu/drm/i915/intel_chipset.h:82: +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -:319: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #319: FILE: drivers/gpu/drm/i915/intel_chipset.h:84: +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:321: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #321: FILE: drivers/gpu/drm/i915/intel_chipset.h:86: +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) -:323: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #323: FILE: drivers/gpu/drm/i915/intel_chipset.h:88: +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:326: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #326: FILE: drivers/gpu/drm/i915/intel_chipset.h:91: +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ +INTEL_DEVID(dev_priv) == 0x0A1E) -:328: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #328: FILE: drivers/gpu/drm/i915/intel_chipset.h:93: +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ +INTEL_DEVID(dev_priv) == 0x1913 || \ +
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Store first production revid into device info
Quoting Mika Kuoppala (2018-06-08 09:39:06)
> Store first known production revid into the device info.
>
> This enables us to easily see if we are running on
> a preproduction hardware.
>
> Uninitialized (zero) product revision id means that
> there are no known preliminary hardware for this platform,
> or that the platform is of gen that we don't care.
> This is all pre gen9 platforms.
>
> Unknown product revision maps to REVID_FOREVER on a
> gen9+ platforms on default. When the platform
> gets the first production revision and our testing
> infra is cleaned from preproduction hardware, we can
> set a first production revid. At that point we start
> to complain about running driver on preliminary hardware.
>
> v2: initialize GEN9_FEATURES too (CI)
>
> Suggested-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Tomi Sarvela
> Cc: Jani Nikula
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 +++---
> drivers/gpu/drm/i915/i915_drv.h | 7 +++
> drivers/gpu/drm/i915/i915_pci.c | 10 --
> drivers/gpu/drm/i915/intel_device_info.h | 11 +++
> 4 files changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index be71fdf8d92e..92f244c12f1e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -855,10 +855,10 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
> bool pre = false;
>
> pre |= IS_HSW_EARLY_SDV(dev_priv);
> - pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> - pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> + pre |= IS_PREPRODUCTION_HW(dev_priv);
>
> - if (pre) {
> + if (pre && FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))
> + != PRODUCT_REVID_UNKNOWN) {
> DRM_ERROR("This is a pre-production stepping. "
> "It may not be fully functional.\n");
> add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
I know this is changed later, but this is not very pleasing on the eye.
const struct intel_info *info = INTEL_INFO(dev_priv);
if (IS_PREPRODUCTION_HW(dev_priv) &&
FIRST_PRODUCT_REVID(info) != PRODUCT_REVID_UNKNOWN) {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 933e31669557..9ae9dc553192 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -146,6 +146,17 @@ struct intel_device_info {
> u16 device_id;
> u16 gen_mask;
>
> + u8 first_product_revid;
> + /* Set to corresponding first production hardware revision or:
/*
* Set to
That's the style we're meant to use. It helps when we mix in kerneldoc
comments, e.g.
/**
* Foo:
> +*
> +* 0x00 == uninitialized == no known preliminary hw (legacy gens)
> +* 0xff == PRODUCT_REVID_UNKNOWN == no known production hw yet
> +*
> +* Do not set first product revid unless you are certain
> +* that testing infrastructure is already on top of production
> +* revid machines.
> +*/
Description block before member or short description on the same line.
-Chris
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