[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745 -> Patchwork_10057 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48803/revisions/6/mbox/
== Known issues ==
Here are the changes found in Patchwork_10057 that come from known issues:
=== IGT changes ===
Issues hit
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)
Possible fixes
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362, fdo#103191) -> PASS +1
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107708, fdo#107602) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708
== Participating hosts (54 -> 47) ==
Missing(7): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005
== Build changes ==
* Linux: CI_DRM_4745 -> Patchwork_10057
CI_DRM_4745: 4ddf5e7833fae7268e674ddea403a24b36c8337d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10057: 225ce5d7d0c64e3c963e105a4e8d05d4533539fe @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
225ce5d7d0c6 drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10057/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] [intel-gfx] drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.
This patch resolves the DMC FW loading issue.
Earlier DMC FW package have only one DMC FW for one stepping. But as such
there is no such restriction from Package side.
For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
So while reading the dmc_offset from package header, for 1st stepping
offset used to come 0x0 and was working fine till now.
But for second stepping and other steppings, offset is non zero number
and is in dwords. So we need to convert into bytes to fetch correct DMC
FW from correct place.
v2 : Added check for DMC FW max size for various gen. (Imre Deak)
v3 : Corrected naming convention for various gen. (Imre Deak)
v4 : Initialized max_fw_size to 0
v5 : Corrected DMC FW MAX_SIZE for various gen. (Imre Deak)
v6 : Fixed the typo issues.
Reviewed-by: Imre Deak
Signed-off-by: Jyoti Yadav
---
drivers/gpu/drm/i915/intel_csr.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ec4f09..14cf4c3 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -55,7 +55,9 @@
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
-#define CSR_MAX_FW_SIZE0x2FFF
+#define BXT_CSR_MAX_FW_SIZE0x3000
+#define GLK_CSR_MAX_FW_SIZE0x4000
+#define ICL_CSR_MAX_FW_SIZE0x6000
#define CSR_DEFAULT_FW_OFFSET 0x
struct intel_css_header {
@@ -279,6 +281,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
struct intel_csr *csr = &dev_priv->csr;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
+ uint32_t max_fw_size = 0;
uint32_t i;
uint32_t *dmc_payload;
uint32_t required_version;
@@ -359,6 +362,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
si->stepping);
return NULL;
}
+ /* Convert dmc_offset into number of bytes. By default it is in dwords*/
+ dmc_offset *= 4;
readcount += dmc_offset;
/* Extract dmc_header information. */
@@ -391,8 +396,16 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
nbytes = dmc_header->fw_size * 4;
- if (nbytes > CSR_MAX_FW_SIZE) {
- DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
+ if (INTEL_GEN(dev_priv) >= 11)
+ max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ else if (IS_GEN9(dev_priv))
+ max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ else
+ MISSING_CASE(INTEL_REVID(dev_priv));
+ if (nbytes > max_fw_size) {
+ DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
return NULL;
}
csr->dmc_fw_size = dmc_header->fw_size;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5)
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745 -> Patchwork_10056 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48803/revisions/5/mbox/
== Known issues ==
Here are the changes found in Patchwork_10056 that come from known issues:
=== IGT changes ===
Issues hit
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
Possible fixes
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#103191, fdo#107362) -> PASS +1
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: FAIL (fdo#107336) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4745 -> Patchwork_10056
CI_DRM_4745: 4ddf5e7833fae7268e674ddea403a24b36c8337d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10056: 5e4f9c90b0db307fceeab8c98f860cf4851aa382 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5e4f9c90b0db drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10056/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5)
== Series Details == Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5) URL : https://patchwork.freedesktop.org/series/48803/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5e4f9c90b0db drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: So while reading the dmc_offset from package header, for 1st stepping offset -:18: WARNING:TYPO_SPELLING: 'Initalized' may be misspelled - perhaps 'Initialized'? #18: v4 : Initalized max_fw_size to 0 -:66: ERROR:TRAILING_WHITESPACE: trailing whitespace #66: FILE: drivers/gpu/drm/i915/intel_csr.c:403: +^Ielse if (IS_GEN9(dev_priv)) $ -:74: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Jyoti ' total: 1 errors, 3 warnings, 0 checks, 43 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] [intel-gfx] drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.
From: Jyoti
This patch resolves the DMC FW loading issue.
Earlier DMC FW package have only one DMC FW for one stepping. But as such
there is no such restriction from Package side.
For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
So while reading the dmc_offset from package header, for 1st stepping offset
used to come 0x0 and was working fine till now.
But for second stepping and other steppings, offset is non zero numaber and is
in dwords. So we need to convert into bytes to fetch correct DMC FW from
correct place.
v2 : Added check for DMC FW max size for various gen. (Imre Deak)
v3 : Corrected naming convention for various gen. (Imre Deak)
v4 : Initalized max_fw_size to 0
v5: Corrected DMC FW MAX_SIZE for various gen. (Imre Deak)
Signed-off-by: Jyoti Yadav
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_csr.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ec4f09..dfdcfef 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -55,7 +55,9 @@
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
-#define CSR_MAX_FW_SIZE0x2FFF
+#define BXT_CSR_MAX_FW_SIZE0x3000
+#define GLK_CSR_MAX_FW_SIZE0x4000
+#define ICL_CSR_MAX_FW_SIZE0x6000
#define CSR_DEFAULT_FW_OFFSET 0x
struct intel_css_header {
@@ -279,6 +281,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
struct intel_csr *csr = &dev_priv->csr;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
+ uint32_t max_fw_size = 0;
uint32_t i;
uint32_t *dmc_payload;
uint32_t required_version;
@@ -359,6 +362,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
si->stepping);
return NULL;
}
+ /* Convert dmc_offset into number of bytes. By default it is in dwords*/
+ dmc_offset *= 4;
readcount += dmc_offset;
/* Extract dmc_header information. */
@@ -391,8 +396,16 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
nbytes = dmc_header->fw_size * 4;
- if (nbytes > CSR_MAX_FW_SIZE) {
- DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
+ if (INTEL_GEN(dev_priv) >= 11)
+ max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ else if (IS_GEN9(dev_priv))
+ max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ else
+ MISSING_CASE(INTEL_REVID(dev_priv));
+ if (nbytes > max_fw_size) {
+ DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
return NULL;
}
csr->dmc_fw_size = dmc_header->fw_size;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] [intel-gfx][igt-dev] [PATCH i-g-t] tests/pm_backlight.c : Brightness test with DPMS and System suspend.
From: Jyoti
BIOS programs few of PWM related registers during initial boot.
But during System suspend those registers are cleared.
This test aim to check whether display programs those registers properly after
system resume.
Also checks brightness programming during DPMS ON/OFF cycle to check backlight
programming is done properly from display side.
v2 : Optimize the code to avoid code redundancy. (Rodrigo)
Signed-off-by: Jyoti Yadav
---
tests/pm_backlight.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/tests/pm_backlight.c b/tests/pm_backlight.c
index a695f90..8b5c79d 100644
--- a/tests/pm_backlight.c
+++ b/tests/pm_backlight.c
@@ -47,6 +47,7 @@ struct context {
#define FADESPEED 100 /* milliseconds between steps */
IGT_TEST_DESCRIPTION("Basic backlight sysfs test");
+static int8_t *pm_data = NULL;
static int backlight_read(int *result, const char *fname)
{
@@ -150,19 +151,38 @@ static void test_fade(struct context *context)
nanosleep(&ts, NULL);
}
}
+static void test_fade_with_dpms(struct context *context, igt_output_t *output)
+{
+ bool has_runtime_pm;
+ has_runtime_pm = igt_setup_runtime_pm();
+ igt_info("Runtime PM support: %d\n", has_runtime_pm);
+ igt_assert(has_runtime_pm);
+ kmstest_set_connector_dpms(output->display->drm_fd,
output->config.connector, DRM_MODE_DPMS_OFF);
+ igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED));
+ kmstest_set_connector_dpms(output->display->drm_fd,
output->config.connector, DRM_MODE_DPMS_ON);
+ igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE));
+ test_fade(context);
+}
+static void test_fade_with_suspend(struct context *context, igt_output_t
*output)
+{
+ kmstest_set_connector_dpms(output->display->drm_fd,
output->config.connector, DRM_MODE_DPMS_OFF);
+ igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED));
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
+ test_fade(context);
+}
igt_main
{
struct context context = {0};
int old;
igt_display_t display;
+ igt_output_t *output;
struct igt_fb fb;
igt_skip_on_simulation();
igt_fixture {
enum pipe pipe;
- igt_output_t *output;
bool found = false;
char full_name[32] = {};
char *name;
@@ -187,7 +207,6 @@ igt_main
for_each_pipe_with_valid_output(&display, pipe, output) {
if (strcmp(name + 6, output->name))
continue;
-
found = true;
break;
}
@@ -205,6 +224,7 @@ igt_main
igt_plane_set_fb(primary, &fb);
igt_display_commit2(&display, display.is_atomic ? COMMIT_ATOMIC
: COMMIT_LEGACY);
+ pm_data = igt_pm_enable_sata_link_power_management();
}
igt_subtest("basic-brightness")
@@ -213,6 +233,10 @@ igt_main
test_bad_brightness(&context);
igt_subtest("fade")
test_fade(&context);
+ igt_subtest("fade_with_dpms")
+ test_fade_with_dpms(&context, output);
+ igt_subtest("fade_with_suspend")
+ test_fade_with_suspend(&context, output);
igt_fixture {
/* Restore old brightness */
@@ -220,6 +244,8 @@ igt_main
igt_display_fini(&display);
igt_remove_fb(display.drm_fd, &fb);
+ igt_pm_restore_sata_link_power_management(pm_data);
+ free(pm_data);
close(display.drm_fd);
}
}
--
1.9.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2)
== Series Details == Series: drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2) URL : https://patchwork.freedesktop.org/series/48813/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4741_full -> Patchwork_10055_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10055_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10055_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10055_full: === IGT changes === Warnings igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10055_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) +1 igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) Possible fixes igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: FAIL (fdo#103355) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4741 -> Patchwork_10055 CI_DRM_4741: e987326b55f29482450c9e5f56f170a626030aaf @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10055: bad7437f36fc613791d50213b0864f1f5e9a0fe5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10055/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/21] drm/i915/huc: New HuC status register for Gen11
On Wed, 2018-08-29 at 12:18 -0700, Wajdeczko, Michal wrote:
> Gen11 defines new register for checking HuC authentication status.
> Look into the right register and bit.
>
> BSpec: 19686
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tony Ye
> Cc: Vinay Belgaumkar
> Cc: Michel Thierry
> Cc: John Spotswood
> Cc: Anusha Srivatsa
Reviewed-by: John Spotswood
> ---
> drivers/gpu/drm/i915/intel_guc_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_huc.c | 58
> +++-
> 2 files changed, 53 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
> b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 2149209..de36595 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -79,6 +79,9 @@
> #define HUC_STATUS2 _MMIO(0xD3B0)
> #define HUC_FW_VERIFIED (1<<7)
>
> +#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
> +#define HUC_LOAD_SUCCESSFUL (1 << 0)
> +
> #define GUC_WOPCM_SIZE _MMIO(0xc050)
> #define GUC_WOPCM_SIZE_LOCKED (1<<0)
> #define GUC_WOPCM_SIZE_SHIFT 12
> diff --git a/drivers/gpu/drm/i915/intel_huc.c
> b/drivers/gpu/drm/i915/intel_huc.c
> index 37ef540d..a710c0d 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
> return 0;
> }
>
> +static int gen8_huc_wait_verified(struct intel_huc *huc)
> +{
> + struct drm_i915_private *i915 = huc_to_i915(huc);
> + u32 status;
> + int ret;
> +
> + ret = __intel_wait_for_register(i915,
> + HUC_STATUS2,
> + HUC_FW_VERIFIED,
> + HUC_FW_VERIFIED,
> + 2, 50, &status);
> + if (ret)
> + DRM_ERROR("HuC: status %#x\n", status);
> + return ret;
> +}
> +
> +static int gen11_huc_wait_verified(struct intel_huc *huc)
> +{
> + struct drm_i915_private *i915 = huc_to_i915(huc);
> + int ret;
> +
> + ret = __intel_wait_for_register(i915,
> + GEN11_HUC_KERNEL_LOAD_INFO,
> + HUC_LOAD_SUCCESSFUL,
> + HUC_LOAD_SUCCESSFUL,
> + 2, 50, NULL);
> + return ret;
> +}
> +
> +static int huc_wait_verified(struct intel_huc *huc)
> +{
> + struct drm_i915_private *i915 = huc_to_i915(huc);
> + int ret;
> +
> + if (INTEL_GEN(i915) >= 11)
> + ret = gen11_huc_wait_verified(huc);
> + else
> + ret = gen8_huc_wait_verified(huc);
> + return ret;
> +}
> +
> /**
> * intel_huc_auth() - Authenticate HuC uCode
> * @huc: intel_huc structure
> @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
> struct drm_i915_private *i915 = huc_to_i915(huc);
> struct intel_guc *guc = &i915->guc;
> struct i915_vma *vma;
> - u32 status;
> int ret;
>
> if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
> }
>
> /* Check authentication status, it should be done by now */
> - ret = __intel_wait_for_register(i915,
> - HUC_STATUS2,
> - HUC_FW_VERIFIED,
> - HUC_FW_VERIFIED,
> - 2, 50, &status);
> + ret = huc_wait_verified(huc);
> if (ret) {
> - DRM_ERROR("HuC: Firmware not verified %#x\n",
> status);
> + DRM_ERROR("HuC: Firmware not verified %d\n", ret);
> goto fail_unpin;
> }
>
> @@ -120,7 +156,13 @@ int intel_huc_check_status(struct intel_huc
> *huc)
> return -ENODEV;
>
> intel_runtime_pm_get(dev_priv);
> - status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
> + HUC_LOAD_SUCCESSFUL;
> + else
> + status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> +
> intel_runtime_pm_put(dev_priv);
>
> return status;
___
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Re: [Intel-gfx] [PATCH 03/21] drm/i915/guc: Simplify preparation of GuC parameter block
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Definition of the parameters block passed to GuC is about to change.
> Slightly refactor code now to make upcoming patch smaller.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: John Spotswood
Reviewed-by: John Spotswood
> ---
> drivers/gpu/drm/i915/intel_guc.c | 38 +++---
>
> 1 file changed, 23 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 230aea6..982bcc8 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -320,19 +320,8 @@ static u32 guc_ctl_log_params_flags(struct
> intel_guc *guc)
> return flags;
> }
>
> -/*
> - * Initialise the GuC parameter block before starting the firmware
> - * transfer. These parameters are read by the firmware on startup
> - * and cannot be changed thereafter.
> - */
> -void intel_guc_init_params(struct intel_guc *guc)
> +static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - u32 params[GUC_CTL_MAX_DWORDS];
> - int i;
> -
> - memset(params, 0, sizeof(params));
> -
> /*
> * GuC ARAT increment is 10 ns. GuC default scheduler
> quantum is one
> * second. This ARAR is calculated by:
> @@ -347,9 +336,12 @@ void intel_guc_init_params(struct intel_guc
> *guc)
> params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
> params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
> params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +}
>
> - for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i,
> params[i]);
> +static void guc_write_params(struct intel_guc *guc, const u32
> *params)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + int i;
>
> /*
> * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER
> domain and
> @@ -360,12 +352,28 @@ void intel_guc_init_params(struct intel_guc
> *guc)
>
> I915_WRITE(SOFT_SCRATCH(0), 0);
>
> - for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> + for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) {
> + DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i,
> params[i]);
> I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
> + }
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
> }
>
> +/*
> + * Initialise the GuC parameter block before starting the firmware
> + * transfer. These parameters are read by the firmware on startup
> + * and cannot be changed thereafter.
> + */
> +void intel_guc_init_params(struct intel_guc *guc)
> +{
> + u32 params[GUC_CTL_MAX_DWORDS];
> +
> + memset(params, 0, sizeof(params));
> + guc_prepare_params(guc, params);
> + guc_write_params(guc, params);
> +}
> +
> int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32
> len,
> u32 *response_buf, u32 response_buf_size)
> {
___
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Re: [Intel-gfx] [PATCH 04/21] drm/i915/guc: Support dual Gen9/Gen11 parameters block
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Gen11 GuC boot parameter definitions are different than previously
> used for Gen9. Try to support both definitions until new firmwares
> for pre-Gen11 will be available.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Daniele Ceraolo Spurio
> Cc: Michel Thierry
> Cc: John Spotswood
> Cc: Vinay Belgaumkar
> Cc: Tony Ye
> Cc: Anusha Srivatsa
> Cc: Jeff Mcgee
> Cc: Antonio Argenziano
> Cc: Sujaritha Sundaresan
Reviewed-by: John Spotswood
> ---
> drivers/gpu/drm/i915/intel_guc.c | 76
> +--
> drivers/gpu/drm/i915/intel_guc_fwif.h | 59 +--
>
> 2 files changed, 83 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 982bcc8..a9c2f7b 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -230,14 +230,7 @@ void intel_guc_fini(struct intel_guc *guc)
> static u32 guc_ctl_debug_flags(struct intel_guc *guc)
> {
> u32 level = intel_guc_log_get_level(&guc->log);
> - u32 flags;
> - u32 ads;
> -
> - ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >>
> PAGE_SHIFT;
> - flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
> -
> - if (!GUC_LOG_LEVEL_IS_ENABLED(level))
> - flags |= GUC_LOG_DEFAULT_DISABLED;
> + u32 flags = 0;
>
> if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
> flags |= GUC_LOG_DISABLED;
> @@ -248,20 +241,28 @@ static u32 guc_ctl_debug_flags(struct intel_guc
> *guc)
> return flags;
> }
>
> -static u32 guc_ctl_feature_flags(struct intel_guc *guc)
> +static u32 guc9_ctl_debug_flags(struct intel_guc *guc)
> {
> - u32 flags = 0;
> + u32 level = intel_guc_log_get_level(&guc->log);
> + u32 flags;
> + u32 ads;
>
> - flags |= GUC_CTL_VCS2_ENABLED;
> + ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >>
> PAGE_SHIFT;
> + flags = ads << GUC9_ADS_ADDR_SHIFT | GUC9_ADS_ENABLED;
>
> - if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
> - flags |= GUC_CTL_KERNEL_SUBMISSIONS;
> - else
> - flags |= GUC_CTL_DISABLE_SCHEDULER;
> + if (!GUC_LOG_LEVEL_IS_ENABLED(level))
> + flags |= GUC9_LOG_DEFAULT_DISABLED;
> +
> + flags |= guc_ctl_debug_flags(guc);
>
> return flags;
> }
>
> +static u32 guc9_ctl_feature_flags(struct intel_guc *guc)
> +{
> + return GUC9_CTL_VCS2_ENABLED | GUC9_CTL_DISABLE_SCHEDULER;
> +}
> +
> static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
> {
> u32 flags = 0;
> @@ -279,6 +280,16 @@ static u32 guc_ctl_ctxinfo_flags(struct
> intel_guc *guc)
> return flags;
> }
>
> +static u32 guc_ctl_feature_flags(struct intel_guc *guc)
> +{
> + u32 flags = 0;
> +
> + if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
> + flags |= GUC_CTL_DISABLE_SCHEDULER;
> +
> + return flags;
> +}
> +
> static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
> {
> u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >>
> PAGE_SHIFT;
> @@ -320,22 +331,39 @@ static u32 guc_ctl_log_params_flags(struct
> intel_guc *guc)
> return flags;
> }
>
> -static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> +static void guc9_prepare_params(struct intel_guc *guc, u32 *params)
> {
> /*
> * GuC ARAT increment is 10 ns. GuC default scheduler
> quantum is one
> * second. This ARAR is calculated by:
> * Scheduler-Quantum-in-ns / ARAT-increment-in-ns =
> 10 / 10
> */
> - params[GUC_CTL_ARAT_HIGH] = 0;
> - params[GUC_CTL_ARAT_LOW] = 1;
> + params[GUC9_CTL_ARAT_HIGH] = 0;
> + params[GUC9_CTL_ARAT_LOW] = 1;
> +
> + params[GUC9_CTL_WA] |= GUC9_CTL_WA_UK_BY_DRIVER;
>
> - params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
> + params[GUC9_CTL_FEATURE] = guc9_ctl_feature_flags(guc);
> + params[GUC9_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
> + params[GUC9_CTL_DEBUG] = guc9_ctl_debug_flags(guc);
> + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +}
>
> +static u32 guc_ctl_ads_flags(struct intel_guc *guc)
> +{
> + u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >>
> PAGE_SHIFT;
> + u32 flags = ads << GUC_ADS_ADDR_SHIFT;
> +
> + return flags;
> +}
> +
> +static void guc11_prepare_params(struct intel_guc *guc, u32 *params)
> +{
> + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> + params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
> params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
> - params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
> params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
> - params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> + params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
> }
>
> static void guc_write_params(struct intel_guc *guc, const u32
> *p
Re: [Intel-gfx] [PATCH 02/21] drm/i915/guc: Don't allow GuC submission on pre-Gen11
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Upcoming Gen11 GuC firmware requires new interface that is
> incompatible
> with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11
> will
> arrive later. In the meantime sanitize the enable_guc option so that
> we
> can enable HuC authentication but nothing else on pre-Gen11.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Daniele Ceraolo Spurio
> Cc: Michel Thierry
> Cc: John Spotswood
> Cc: Vinay Belgaumkar
> Cc: Tony Ye
> Cc: Anusha Srivatsa
> Cc: Jeff Mcgee
> Cc: Antonio Argenziano
> Cc: Sujaritha Sundaresan
Reviewed-by: John Spotswood
> ---
> drivers/gpu/drm/i915/intel_uc.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_uc.c
> b/drivers/gpu/drm/i915/intel_uc.c
> index 7a3a4ca..185b29b 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct
> drm_i915_private *i915)
> enable_guc |= ENABLE_GUC_LOAD_HUC;
>
> /* Any platform specific fine-tuning can be done here */
> + if (INTEL_GEN(i915) < 11)
> + enable_guc &= ~ENABLE_GUC_SUBMISSION;
>
> return enable_guc;
> }
> @@ -115,6 +117,13 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> yesno(intel_uc_is_using_guc_submission()),
> yesno(intel_uc_is_using_huc()));
>
> + /* Verify GuC submission support */
> + if (intel_uc_is_using_guc_submission() && INTEL_GEN(i915) <
> 11) {
> + DRM_WARN("Incompatible option detected: %s=%d,
> %s!\n",
> + "enable_guc", i915_modparams.enable_guc,
> + "submission not supported");
> + }
> +
> /* Verify GuC firmware availability */
> if (intel_uc_is_using_guc() &&
> !intel_uc_fw_is_selected(guc_fw)) {
> DRM_WARN("Incompatible option detected: %s=%d,
> %s!\n",
> @@ -292,6 +301,12 @@ int intel_uc_init(struct drm_i915_private *i915)
> return ret;
>
> if (USES_GUC_SUBMISSION(i915)) {
> +
> + if (INTEL_GEN(i915) < 11) {
> + intel_guc_fini(guc);
> + return -EIO;
> + }
> +
> /*
> * This is stuff we need to have available at fw
> load time
> * if we are planning to enable submission later
___
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Re: [Intel-gfx] [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface
On 29/08/18 17:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Lucas De Marchi
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 13 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a34e8f..bc81354 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -85,6 +85,7 @@ struct engine_info {
unsigned int hw_id;
unsigned int uabi_id;
u8 class;
+ u8 guc_class;
u8 instance;
/* mmio bases table *must* be sorted in reverse gen order */
struct engine_mmio_base {
@@ -98,6 +99,7 @@ struct engine_info {
.hw_id = RCS_HW,
.uabi_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
+ .guc_class = GUC_RENDER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 1, .base = RENDER_RING_BASE }
@@ -107,6 +109,7 @@ struct engine_info {
.hw_id = BCS_HW,
.uabi_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
+ .guc_class = GUC_BLITTER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 6, .base = BLT_RING_BASE }
@@ -116,6 +119,7 @@ struct engine_info {
.hw_id = VCS_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD_RING_BASE },
@@ -127,6 +131,7 @@ struct engine_info {
.hw_id = VCS2_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
@@ -137,6 +142,7 @@ struct engine_info {
.hw_id = VCS3_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 2,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
@@ -146,6 +152,7 @@ struct engine_info {
.hw_id = VCS4_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 3,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
@@ -155,6 +162,7 @@ struct engine_info {
.hw_id = VECS_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
@@ -165,6 +173,7 @@ struct engine_info {
.hw_id = VECS2_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
@@ -276,6 +285,9 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
+ if (GEM_WARN_ON(info->guc_class >= GUC_MAX_ENGINE_CLASSES))
+ return -EINVAL;
+
if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
return -EINVAL;
@@ -291,6 +303,7 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
engine->i915 = dev_priv;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
+ engine->guc_class = info->guc_class;
engine->mmio_base = __engine_mmio_base(dev_priv,
info->mmio_bases);
engine->class = info->class;
engine->instance = info->instance;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 963da91..5b7a05b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,13 @@
#define GUC_VIDEO_ENGINE2 4
#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
+#define GUC_RENDER_CLASS 0
+#define GUC_VIDEO_
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/2] drm: Add connector property to limit max bpc
== Series Details == Series: series starting with [v4,1/2] drm: Add connector property to limit max bpc URL : https://patchwork.freedesktop.org/series/48960/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10054_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10054_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10054_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10054_full: === IGT changes === Possible regressions igt@kms_properties@get_properties-sanity-atomic: shard-hsw: PASS -> FAIL +3 igt@kms_properties@get_properties-sanity-non-atomic: shard-snb: PASS -> FAIL +3 Warnings igt@kms_cursor_legacy@flip-vs-cursor-legacy: shard-snb: SKIP -> PASS +2 == Known issues == Here are the changes found in Patchwork_10054_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> INCOMPLETE (fdo#106886, k.org#198133, fdo#103359) igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: PASS -> FAIL (fdo#103375) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@perf_pmu@enable-race-bcs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#106886, fdo#103540) -> PASS igt@gem_exec_await@wide-contexts: shard-kbl: FAIL (fdo#105900) -> PASS igt@gem_render_linear_blits@basic: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-badstride: shard-glk: FAIL (fdo#103167) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4740 -> Patchwork_10054 CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10054: 3555676ce4a1f6a6ddbdc4b5ff425e12826628f6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10054/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add XYUV format support (rev5)
== Series Details == Series: Add XYUV format support (rev5) URL : https://patchwork.freedesktop.org/series/48007/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10053_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10053_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10053_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10053_full: === IGT changes === Possible regressions igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: PASS -> FAIL Warnings igt@kms_cursor_legacy@flip-vs-cursor-legacy: shard-snb: SKIP -> PASS +2 == Known issues == Here are the changes found in Patchwork_10053_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) igt@perf_pmu@enable-race-bcs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#106886, fdo#103540) -> PASS igt@gem_exec_await@wide-contexts: shard-kbl: FAIL (fdo#105900) -> PASS igt@gem_render_linear_blits@basic: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_frontbuffer_tracking@fbc-badstride: shard-glk: FAIL (fdo#103167) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4740 -> Patchwork_10053 CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10053: 7eb5932ca612e002b83fde01dd4f5316ce2e2efe @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10053/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
== Series Details == Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4) URL : https://patchwork.freedesktop.org/series/48906/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10052_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10052_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> INCOMPLETE (fdo#105411, fdo#106886) igt@gem_exec_await@wide-contexts: shard-glk: PASS -> FAIL (fdo#105900) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: PASS -> FAIL (fdo#103375) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@perf_pmu@enable-race-bcs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540, fdo#106886) -> PASS igt@gem_exec_await@wide-contexts: shard-kbl: FAIL (fdo#105900) -> PASS igt@gem_render_linear_blits@basic: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-badstride: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4740 -> Patchwork_10052 CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10052: 41720addaafc699fddfd9771f8825b32c205bef9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10052/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL HDMI clock readout
On Thu, Aug 30, 2018 at 06:48:45PM +0300, Ville Syrjälä wrote:
> On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> > On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > > mgr into the clock readout function as well.
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/intel_ddi.c | 7 +++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index f3b115ce4029..68b301e6f41d 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct
> > > drm_i915_private *dev_priv,
> > >
> > > ref_clock = dev_priv->cdclk.hw.ref;
> >
> > could we move this up to the beginning of the function and
> > then reuse that if (INTEL_GEN(dev_priv) >= 11) { block?
>
> Possible? Sure. Clearer? Not so sure.
yeap... I'm not confident this would be clearer...
>
> Probably the correct answer would be to add some kind of
> cnl_pll_ref_clock() helper that encapsulats the magic exception,
> and then use that from all the places that need it.
hmm... probably
>
> >
> > Anyway, this change is needed and right so however you decide
> > to proceed:
> >
> > Reviewed-by: Rodrigo Vivi
> >
> > >
> > > + /*
> > > + * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > > + * because the DPLL automatically divides that by 2.
> > > + */
> > > + if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
what about to at least make it (INTEL_GEN(dev_priv) >= 11)
to be compatible with above's statement?
> > > + ref_clock = 19200;
> > > +
> > > dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> > >
> > > dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > > --
> > > 2.16.4
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: clear error registers after error capture (rev4)
== Series Details == Series: drm/i915: clear error registers after error capture (rev4) URL : https://patchwork.freedesktop.org/series/48939/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10050_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10050_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) +1 igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763) igt@kms_frontbuffer_tracking@fbc-suspend: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-apl: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: shard-hsw: DMESG-WARN (fdo#102614) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: FAIL (fdo#103375) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4739 -> Patchwork_10050 CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10050: d5b724ce03b4fabe0b79130835f798e28bb4f390 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10050/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 2/2] drm/i915: Adding YUV444 packed format(DRM_FORMAT_XYUV) support.
On Thu, 2018-08-30 at 13:57 +0100, Lisovskiy, Stanislav wrote:
> On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
> >
> > On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy
> > > wrote:
> > > > PLANE_CTL_FORMAT_AYUV is already supported, according to
> > > > hardware
> > > > specification.
> > > >
> > > > v2: Edited commit message, removed redundant whitespaces.
> > > >
> > > > v3: Fixed fallthrough logic for the format switch cases.
> > > >
> > > > v4: Yet again fixed fallthrough logic, to reuse code from other
> > > > case
> > > > labels.
> > > >
> > > > v5: Started to use XYUV instead of AYUV, as we don't use alpha.
Curious what the reason is. Is it because the hardware does not support
alpha with this format?
> > > >
> > > > v6: Removed unneeded initializer for new XYUV format.
> > > >
> > > > v7: Added scaling support for DRM_FORMAT_XYUV
> >
> > I don't see yuv formats in skl_format_to_fourcc(), any idea why?
>
> Good point. I guess would be nice idea to add at least XYUV there
> now.
> I can add rest of the formats with a separate patch afterwards.
Wonder if the expectation is BIOS not use yuv formats. Ville?
>
> >
> > Also, shouldn't plane_color_ctl_alpha() be updated?
>
> I guess not, as we don't support alpha in that case.
Right, the default case should take care of setting
PLANE_CTL_ALPHA_DISABLE. I misread it.
>
> >
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy > > > om
> > > > >
> > > >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 8
> > > > drivers/gpu/drm/i915/intel_sprite.c | 1 +
> > > > 2 files changed, 9 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 30fdfd1a3037..3c96fa3a2b61 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] =
> > > > {
> > > > DRM_FORMAT_YVYU,
> > > > DRM_FORMAT_UYVY,
> > > > DRM_FORMAT_VYUY,
> > > > + DRM_FORMAT_XYUV,
> > > > };
> > > >
> > > > static const uint32_t skl_pri_planar_formats[] = {
> > > > @@ -102,6 +103,7 @@ static const uint32_t
> > > > skl_pri_planar_formats[]
> > > > = {
> > > > DRM_FORMAT_UYVY,
> > > > DRM_FORMAT_VYUY,
> > > > DRM_FORMAT_NV12,
> > > > + DRM_FORMAT_XYUV,
> > >
> > > I would keep the NV12 at the end so that the arrays are easier to
> > > compare visually.
> > >
> > > > };
> > > >
> > > > static const uint64_t skl_format_modifiers_noccs[] = {
> > > > @@ -3501,6 +3503,8 @@ static u32 skl_plane_ctl_format(uint32_t
> > > > pixel_format)
> > > > return PLANE_CTL_FORMAT_XRGB_2101010;
> > > > case DRM_FORMAT_XBGR2101010:
> > > > return PLANE_CTL_ORDER_RGBX |
> > > > PLANE_CTL_FORMAT_XRGB_2101010;
> > > > + case DRM_FORMAT_XYUV:
> > > > + return PLANE_CTL_FORMAT_AYUV;
> > >
> > > We should probably rename that define to XYUV as well since it
> > > doesn't
> > > support per-pixel alpha.
> > >
> > > Since you've only implemented this for skl+ you chould mention
> > > that
> > > in the commit msg. IVB+ support should be equally trivial to
> > > implement (wink wink).
> > >
> > > > case DRM_FORMAT_YUYV:
> > > > return PLANE_CTL_FORMAT_YUV422 |
> > > > PLANE_CTL_YUV422_YUYV;
> > > > case DRM_FORMAT_YVYU:
> > > > @@ -4959,6 +4963,7 @@ static int skl_update_scaler_plane(struct
> > > > intel_crtc_state *crtc_state,
> > > > case DRM_FORMAT_UYVY:
> > > > case DRM_FORMAT_VYUY:
> > > > case DRM_FORMAT_NV12:
> > > > + case DRM_FORMAT_XYUV:
> > > > break;
> > > > default:
> > > > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported
> > > > scaling format 0x%x\n",
> > > > @@ -13399,6 +13404,7 @@ static bool
> > > > skl_plane_format_mod_supported(struct drm_plane *_plane,
> > > > }
> > > >
> > > > switch (format) {
> > > > +
> > >
> > > Bogus whitespace.
> > >
> > > > case DRM_FORMAT_XRGB:
> > > > case DRM_FORMAT_XBGR:
> > > > case DRM_FORMAT_ARGB:
> > > > @@ -13414,6 +13420,7 @@ static bool
> > > > skl_plane_format_mod_supported(struct drm_plane *_plane,
> > > > case DRM_FORMAT_UYVY:
> > > > case DRM_FORMAT_VYUY:
> > > > case DRM_FORMAT_NV12:
> > > > + case DRM_FORMAT_XYUV:
> > > > if (modifier == I915_FORMAT_MOD_Yf_TILED)
> > > > return true;
> > > > /* fall through */
> > > > @@ -14540,6 +14547,7 @@ static int
> > > > intel_framebuffer_init(struct
> > > > intel_framebuffer *intel_fb,
> > > > goto err;
> > > > }
> > > > break;
> > > > + case DRM_FORMAT_XYUV:
> > >
> > > Tha
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
== Series Details == Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc URL : https://patchwork.freedesktop.org/series/48947/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10049_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10049_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) +1 Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: shard-hsw: DMESG-WARN (fdo#102614) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: FAIL (fdo#103375) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4739 -> Patchwork_10049 CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10049: bcd3b9a19948bd0667c4d37e6a31b995f1cad0a1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10049/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2)
== Series Details ==
Series: drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2)
URL : https://patchwork.freedesktop.org/series/48813/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4741 -> Patchwork_10055 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48813/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_10055 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: PASS -> FAIL (fdo#107336)
Possible fixes
igt@drv_module_reload@basic-reload:
fi-glk-j4005: DMESG-WARN (fdo#106725, fdo#106248) -> PASS
igt@drv_selftest@live_coherency:
fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#103191, fdo#107362) -> PASS +1
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (54 -> 48) ==
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4741 -> Patchwork_10055
CI_DRM_4741: e987326b55f29482450c9e5f56f170a626030aaf @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10055: bad7437f36fc613791d50213b0864f1f5e9a0fe5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bad7437f36fc drm/i915/ringbuffer: Delay after invalidating gen6+ xcs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10055/issues.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reduce context HW ID lifetime (rev2)
== Series Details == Series: drm/i915: Reduce context HW ID lifetime (rev2) URL : https://patchwork.freedesktop.org/series/44134/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10046_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10046_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-hsw: PASS -> INCOMPLETE (fdo#106886, fdo#103540) shard-glk: PASS -> FAIL (fdo#106886) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@prime_vgem@basic-sync-default: shard-apl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +1 Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: shard-hsw: DMESG-WARN (fdo#102614) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: FAIL (fdo#103375) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4739 -> Patchwork_10046 CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10046: 30bb0eb3b07e55636c05510321556c28fa14c9fd @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10046/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 2/2] igt/perf_pmu: Improve the presentation of the accuracy calibration
On 08/08/2018 15:59, Chris Wilson wrote:
Normalize the variance to stddev, and remove some redundant steps in
computing the time from itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 5a26d5272..4e8da3d94 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1577,8 +1577,8 @@ accuracy(int gem_fd, const struct intel_execution_engine2
*e,
/* 1st pass is calibration, second pass is the test. */
for (int pass = 0; pass < ARRAY_SIZE(timeout); pass++) {
unsigned int target_idle_us = idle_us;
- uint64_t busy_ns = 0, idle_ns = 0;
struct timespec start = { };
+ uint64_t busy_ns = 0;
unsigned long pass_ns = 0;
double avg = 0.0, var = 0.0;
unsigned int n = 0;
@@ -1589,6 +1589,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2
*e,
unsigned long loop_ns, loop_busy;
struct timespec _ts = { };
double err, tmp;
+ uint64_t now;
/* PWM idle sleep. */
_ts.tv_nsec = target_idle_us * 1000;
@@ -1605,14 +1606,13 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
igt_spin_batch_end(spin);
/* Time accounting. */
- loop_ns = igt_nsec_elapsed(&start);
- loop_busy = loop_ns - loop_busy;
- loop_ns -= pass_ns;
+ now = igt_nsec_elapsed(&start);
+ loop_busy = now - loop_busy;
+ loop_ns = now - pass_ns;
+ pass_ns = now;
busy_ns += loop_busy;
total_busy_ns += loop_busy;
- idle_ns += loop_ns - loop_busy;
- pass_ns += loop_ns;
total_ns += loop_ns;
Looks okay, but ugh... just made me lose ten minutes reconstructing
before and after for no real benefit. :I
/* Re-calibrate. */
@@ -1628,10 +1628,14 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
var += (err - avg) * (err - tmp);
} while (pass_ns < timeout[pass]);
+ pass_ns = igt_nsec_elapsed(&start);
expected = (double)busy_ns / pass_ns;
- igt_info("%u: busy %"PRIu64"us, idle %"PRIu64"us -> %.2f%%
(target: %lu%%; average=%.2f, variance=%f)\n",
-pass, busy_ns / 1000, idle_ns / 1000,
-100 * expected, target_busy_pct, avg, var / n);
+
+ igt_info("%u: busy %"PRIu64"us, idle %"PRIu64"us -> %.2f%%
(target: %lu%%; average=%.2f±%.3f%%)\n",
+pass, busy_ns / 1000, (pass_ns - busy_ns) /
1000,
+100 * expected, target_busy_pct,
+avg, sqrt(var / n));
+
write(link[1], &expected, sizeof(expected));
}
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH i-g-t 1/2] igt/perf_pmu: Aim for a fixed number of iterations for calibrating accuracy
On 08/08/2018 15:59, Chris Wilson wrote:
Our observation is that the systematic error is proportional to the
number of iterations we perform; the suspicion is that it directly
correlates with the number of sleeps. Reduce the number of iterations,
to try and keep the error in check.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 9a20abb6b..5a26d5272 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1521,14 +1521,13 @@ static void __rearm_spin_batch(igt_spin_t *spin)
static void
accuracy(int gem_fd, const struct intel_execution_engine2 *e,
-unsigned long target_busy_pct)
+unsigned long target_busy_pct,
+unsigned long target_iters)
{
- unsigned long busy_us = 1 - 100 * (1 + abs(50 - target_busy_pct));
- unsigned long idle_us = 100 * (busy_us - target_busy_pct *
- busy_us / 100) / target_busy_pct;
const unsigned long min_test_us = 1e6;
- const unsigned long pwm_calibration_us = min_test_us;
- const unsigned long test_us = min_test_us;
+ unsigned long pwm_calibration_us;
+ unsigned long test_us;
+ unsigned long cycle_us, busy_us, idle_us;
double busy_r, expected;
uint64_t val[2];
uint64_t ts[2];
@@ -1538,18 +1537,27 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
/* Sampling platforms cannot reach the high accuracy criteria. */
igt_require(gem_has_execlists(gem_fd));
- while (idle_us < 2500) {
+ /* Aim for approximately 100 iterations for calibration */
+ cycle_us = min_test_us / target_iters;
+ busy_us = cycle_us * target_busy_pct / 100;
+ idle_us = cycle_us - busy_us;
+
+ while (idle_us < 2500 || busy_us < 2500) {
busy_us *= 2;
idle_us *= 2;
}
+ cycle_us = busy_us + idle_us;
+ pwm_calibration_us = target_iters * cycle_us / 2;
I'd be tempted not to halve the calibration phase, just to minimize the
number of changes.
+ test_us = target_iters * cycle_us;
- igt_info("calibration=%lums, test=%lums; ratio=%.2f%% (%luus/%luus)\n",
-pwm_calibration_us / 1000, test_us / 1000,
-(double)busy_us / (busy_us + idle_us) * 100.0,
+ igt_info("calibration=%lums, test=%lums, cycle=%lums; ratio=%.2f%%
(%luus/%luus)\n",
+pwm_calibration_us / 1000, test_us / 1000, cycle_us / 1000,
+(double)busy_us / cycle_us * 100.0,
busy_us, idle_us);
- assert_within_epsilon((double)busy_us / (busy_us + idle_us),
- (double)target_busy_pct / 100.0, tolerance);
+ assert_within_epsilon((double)busy_us / cycle_us,
+ (double)target_busy_pct / 100.0,
+ tolerance);
igt_assert(pipe(link) == 0);
@@ -1796,7 +1804,7 @@ igt_main
for (i = 0; i < ARRAY_SIZE(pct); i++) {
igt_subtest_f("busy-accuracy-%u-%s",
pct[i], e->name)
- accuracy(fd, e, pct[i]);
+ accuracy(fd, e, pct[i], 10);
}
igt_subtest_f("busy-hang-%s", e->name)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context
== Series Details == Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context URL : https://patchwork.freedesktop.org/series/48936/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10045_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10045_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: shard-hsw: DMESG-WARN (fdo#102614) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: FAIL (fdo#103375) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4739 -> Patchwork_10045 CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10045: 64365db50d03ad7dfaa8925030f86221689dcd18 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10045/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reduce context HW ID lifetime
On 30/08/2018 11:24, Chris Wilson wrote:
Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a constant ID).
This means that instead of a max of 2k allocated contexts (worst case
before fun with bit twiddling), we instead have a limit of 2k in flight
contexts (minus a few that have been pinned by the kernel or by perf).
We need a paragraph outlining the implementation.
We cannot reduce the scope of an HW-ID to an engine (allowing the same
gem_context to have different ids on each engine) as in the future we
will need to preassign an id before we know which engine the
context is being executed on.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Oscar Mateo
You can drop Oscar since he left Intel.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem_context.c | 207 +-
drivers/gpu/drm/i915/i915_gem_context.h | 17 ++
drivers/gpu/drm/i915/intel_lrc.c | 8 +
drivers/gpu/drm/i915/selftests/mock_context.c | 11 +-
6 files changed, 181 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a5265c236a33..bf3b6c6db51d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1953,7 +1953,10 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return ret;
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
- seq_printf(m, "HW context %u ", ctx->hw_id);
+ seq_puts(m, "HW context ");
+ if (!list_empty(&ctx->hw_id_link))
+ seq_printf(m, "%x [pin %u]",
+ ctx->hw_id, atomic_read(&ctx->pin_hw_id));
if (ctx->pid) {
struct task_struct *task;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..ca6b55d29d6a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1862,6 +1862,7 @@ struct drm_i915_private {
struct mutex av_mutex;
struct {
+ struct mutex mutex;
struct list_head list;
struct llist_head free_list;
struct work_struct free_work;
@@ -1874,6 +1875,7 @@ struct drm_i915_private {
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+ struct list_head hw_id_list;
} contexts;
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..d3390942f37b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -115,6 +115,85 @@ static void lut_close(struct i915_gem_context *ctx)
rcu_read_unlock();
}
+static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
+{
+ unsigned int max;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ if (INTEL_GEN(i915) >= 11)
+ max = GEN11_MAX_CONTEXT_HW_ID;
+ else if (USES_GUC_SUBMISSION(i915))
+ /*
+* When using GuC in proxy submission, GuC consumes the
+* highest bit in the context id to indicate proxy submission.
+*/
+ max = MAX_GUC_CONTEXT_HW_ID;
+ else
+ max = MAX_CONTEXT_HW_ID;
+
+ return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
+}
+
+static int steal_hw_id(struct drm_i915_private *i915)
+{
+ struct i915_gem_context *ctx, *cn;
+ LIST_HEAD(pinned);
+ int id = -ENOSPC;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ list_for_each_entry_safe(ctx, cn,
+&i915->contexts.hw_id_list, hw_id_link) {
+ if (atomic_read(&ctx->pin_hw_id)) {
+ list_move_tail(&ctx->hw_id_link, &pinned);
+ continue;
+ }
+
+ GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
+ list_del_init(&ctx->hw_id_link);
+ id = ctx->hw_id;
+ break;
+ }
+
+ list_splice_tail(&pinned, &i915->contexts.hw_id_list);
Put a comment what is this code doing please. Trying to create some sort
of LRU order?
+ return id;
+}
+
+static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
+{
+ int ret;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAI
Re: [Intel-gfx] [PATCH v4] drm/i915: clear error registers after error capture
On 30/08/2018 15:11, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-08-30 14:24:24) We need to clear the register in order to get correct value after the next potential hang. v2: Centralize error register clearing in i915_irq.c (Chris) v3: Don't read gen8 register on < gen6 (Chris) v4: Don't swap gen8+ & gen6+ code... (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Lgtm, -Chris Thanks a lot, pushed. - Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm: Add connector property to limit max bpc
== Series Details ==
Series: series starting with [v4,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/48960/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10054 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48960/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10054 that come from known issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
igt@gem_exec_suspend@basic-s3:
{fi-cfl-8109u}: PASS -> INCOMPLETE (fdo#107187)
{fi-kbl-soraka}:NOTRUN -> INCOMPLETE (fdo#107556)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@read-crc-pipe-a:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
Possible fixes
{igt@amdgpu/amd_prime@i915-to-amd}:
fi-bxt-j4205: INCOMPLETE (fdo#103927) -> SKIP
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#107362, fdo#103191) -> PASS
{igt@pm_rpm@module-reload}:
fi-bxt-j4205: DMESG-FAIL (fdo#107712) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107187 https://bugs.freedesktop.org/show_bug.cgi?id=107187
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107712 https://bugs.freedesktop.org/show_bug.cgi?id=107712
== Participating hosts (53 -> 49) ==
Additional (1): fi-kbl-soraka
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4740 -> Patchwork_10054
CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10054: 3555676ce4a1f6a6ddbdc4b5ff425e12826628f6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3555676ce4a1 drm/i915: Allow "max bpc" property to limit pipe_bpp
a2b1ae142db2 drm: Add connector property to limit max bpc
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10054/issues.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/ringbuffer: Delay after invalidating gen6+ xcs
During stress testing of full-ppgtt (on Baytrail at least), we found
that the invalidation around a context/mm switch was insufficient (writes
would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but
it is unclear as to whether this is merely a delaying tactic or if it is
truly serialising with the TLB invalidation. Either way, it is
empirically required.
v2: Avoid the loop for readability;
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107715
References: https://bugs.freedesktop.org/show_bug.cgi?id=107759
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Cc: Tvrtko Ursulin
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 69 -
1 file changed, 34 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d40f55a8dc34..44432677160c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1944,7 +1944,7 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
-static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
+static int emit_mi_flush_dw(struct i915_request *rq, u32 flags)
{
u32 cmd, *cs;
@@ -1954,7 +1954,8 @@ static int gen6_bsd_ring_flush(struct i915_request *rq,
u32 mode)
cmd = MI_FLUSH_DW;
- /* We always require a command barrier so that subsequent
+ /*
+* We always require a command barrier so that subsequent
* commands, such as breadcrumb interrupts, are strictly ordered
* wrt the contents of the write cache being flushed to memory
* (and thus being coherent from the CPU).
@@ -1962,22 +1963,49 @@ static int gen6_bsd_ring_flush(struct i915_request *rq,
u32 mode)
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
/*
-* Bspec vol 1c.5 - video engine command streamer:
+* Bspec vol 1c.3 - blitter engine command streamer:
* "If ENABLED, all TLBs will be invalidated once the flush
* operation is complete. This bit is only valid when the
* Post-Sync Operation field is a value of 1h or 3h."
*/
- if (mode & EMIT_INVALIDATE)
- cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
+ cmd |= flags;
*cs++ = cmd;
*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
*cs++ = 0;
*cs++ = MI_NOOP;
+
intel_ring_advance(rq, cs);
+
return 0;
}
+static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
+{
+ int err;
+
+ /*
+* Not only do we need a full barrier (post-sync write) after
+* invalidating the TLBs, but we need to wait a little bit
+* longer. Whether this is merely delaying us, or the
+* subsequent flush is a key part of serialising with the
+* post-sync op, this extra pass appears vital before a
+* mm switch!
+*/
+ if (mode & EMIT_INVALIDATE) {
+ err = emit_mi_flush_dw(rq, invflags);
+ if (err)
+ return err;
+ }
+
+ return emit_mi_flush_dw(rq, 0);
+}
+
+static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
+{
+ return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
+}
+
static int
hsw_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
@@ -2022,36 +2050,7 @@ gen6_emit_bb_start(struct i915_request *rq,
static int gen6_ring_flush(struct i915_request *rq, u32 mode)
{
- u32 cmd, *cs;
-
- cs = intel_ring_begin(rq, 4);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- cmd = MI_FLUSH_DW;
-
- /* We always require a command barrier so that subsequent
-* commands, such as breadcrumb interrupts, are strictly ordered
-* wrt the contents of the write cache being flushed to memory
-* (and thus being coherent from the CPU).
-*/
- cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
-
- /*
-* Bspec vol 1c.3 - blitter engine command streamer:
-* "If ENABLED, all TLBs will be invalidated once the flush
-* operation is complete. This bit is only valid when the
-* Post-Sync Operation field is a value of 1h or 3h."
-*/
- if (mode & EMIT_INVALIDATE)
- cmd |= MI_INVALIDATE_TLB;
- *cs++ = cmd;
- *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
- *cs++ = 0;
- *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
-
- return 0;
+ return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
}
static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
--
2.19.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.
[Intel-gfx] ✓ Fi.CI.BAT: success for Add XYUV format support (rev5)
== Series Details ==
Series: Add XYUV format support (rev5)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10053 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/5/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10053:
=== IGT changes ===
Warnings
{igt@pm_rpm@module-reload}:
fi-hsw-4770r: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10053 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425)
igt@gem_exec_suspend@basic-s3:
{fi-kbl-soraka}:NOTRUN -> INCOMPLETE (fdo#107556)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-skl-6260u: PASS -> INCOMPLETE (fdo#107556, fdo#104108)
Possible fixes
{igt@amdgpu/amd_prime@i915-to-amd}:
fi-bxt-j4205: INCOMPLETE (fdo#103927) -> SKIP
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#107362, fdo#103191) -> PASS
{igt@pm_rpm@module-reload}:
fi-bxt-j4205: DMESG-FAIL (fdo#107712) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107712 https://bugs.freedesktop.org/show_bug.cgi?id=107712
== Participating hosts (53 -> 49) ==
Additional (1): fi-kbl-soraka
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4740 -> Patchwork_10053
CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10053: 7eb5932ca612e002b83fde01dd4f5316ce2e2efe @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7eb5932ca612 drm/i915: Adding YUV444 packed format support for skl+
48d9e0cf5f5e drm: Introduce new DRM_FORMAT_XYUV
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10053/issues.html
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm: Add connector property to limit max bpc
== Series Details ==
Series: series starting with [v4,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/48960/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2b1ae142db2 drm: Add connector property to limit max bpc
3555676ce4a1 drm/i915: Allow "max bpc" property to limit pipe_bpp
-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#31: FILE: drivers/gpu/drm/i915/intel_display.c:10788:
+connected_sink_max_bpp(struct drm_connector_state *conn_state,
+struct intel_crtc_state *pipe_config)
-:36: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#36: FILE: drivers/gpu/drm/i915/intel_display.c:10793:
+ pipe_config->pipe_bpp = 8*3;
^
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:10797:
+ pipe_config->pipe_bpp = 10*3;
^
-:43: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/intel_display.c:10800:
+ pipe_config->pipe_bpp = 12*3;
^
-:130: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!prop"
#130: FILE: drivers/gpu/drm/i915/intel_modes.c:146:
+ if (prop == NULL) {
-:132: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!prop"
#132: FILE: drivers/gpu/drm/i915/intel_modes.c:148:
+ if (prop == NULL)
total: 0 errors, 0 warnings, 6 checks, 94 lines checked
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL HDMI clock readout
On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > mgr into the clock readout function as well.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 7 +++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3b115ce4029..68b301e6f41d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct
> > drm_i915_private *dev_priv,
> >
> > ref_clock = dev_priv->cdclk.hw.ref;
>
> could we move this up to the beginning of the function and
> then reuse that if (INTEL_GEN(dev_priv) >= 11) { block?
Possible? Sure. Clearer? Not so sure.
Probably the correct answer would be to add some kind of
cnl_pll_ref_clock() helper that encapsulats the magic exception,
and then use that from all the places that need it.
>
> Anyway, this change is needed and right so however you decide
> to proceed:
>
> Reviewed-by: Rodrigo Vivi
>
> >
> > + /*
> > +* For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > +* because the DPLL automatically divides that by 2.
> > +*/
> > + if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> > + ref_clock = 19200;
> > +
> > dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> >
> > dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > --
> > 2.16.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH] drm/i915/ringbuffer: Delay after invalidating gen6+ xcs
On Tue, Aug 28, 2018 at 06:04:29PM +0100, Chris Wilson wrote:
> During stress testing of full-ppgtt (on Baytrail at least), we found
> that the invalidation around a context/mm switch was insufficient (writes
> would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but
> it is unclear as to whether this is merely a delaying tactic or if it is
> truly serialising with the TLB invalidation. Either way, it is
> empirically required.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107715
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 101 +++-
> 1 file changed, 47 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d40f55a8dc34..952b6269bab0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1944,40 +1944,62 @@ static void gen6_bsd_submit_request(struct
> i915_request *request)
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
>
> -static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
> +static int emit_mi_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
> {
> u32 cmd, *cs;
>
> - cs = intel_ring_begin(rq, 4);
> - if (IS_ERR(cs))
> - return PTR_ERR(cs);
> + do {
> + cs = intel_ring_begin(rq, 4);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
>
> - cmd = MI_FLUSH_DW;
> + cmd = MI_FLUSH_DW;
>
> - /* We always require a command barrier so that subsequent
> - * commands, such as breadcrumb interrupts, are strictly ordered
> - * wrt the contents of the write cache being flushed to memory
> - * (and thus being coherent from the CPU).
> - */
> - cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
> + /*
> + * We always require a command barrier so that subsequent
> + * commands, such as breadcrumb interrupts, are strictly ordered
> + * wrt the contents of the write cache being flushed to memory
> + * (and thus being coherent from the CPU).
> + */
> + cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
>
> - /*
> - * Bspec vol 1c.5 - video engine command streamer:
> - * "If ENABLED, all TLBs will be invalidated once the flush
> - * operation is complete. This bit is only valid when the
> - * Post-Sync Operation field is a value of 1h or 3h."
> - */
> - if (mode & EMIT_INVALIDATE)
> - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
> + /*
> + * Bspec vol 1c.3 - blitter engine command streamer:
> + * "If ENABLED, all TLBs will be invalidated once the flush
> + * operation is complete. This bit is only valid when the
> + * Post-Sync Operation field is a value of 1h or 3h."
> + */
> + if (mode & EMIT_INVALIDATE)
> + cmd |= invflags;
> + *cs++ = cmd;
> + *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
> + *cs++ = 0;
> + *cs++ = MI_NOOP;
> + intel_ring_advance(rq, cs);
> +
> + /*
> + * Not only do we need a full barrier (post-sync write) after
> + * invalidating the TLBs, but we need to wait a little bit
> + * longer. Whether this is merely delaying us, or the
> + * subsequent flush is a key part of serialising with the
> + * post-sync op, this extra pass appears vital before a
> + * mm switch!
> + */
> + if (!(mode & EMIT_INVALIDATE))
> + break;
> +
> + mode &= ~EMIT_INVALIDATE;
> + } while (1);
I find the loop thingy somewhat hard to read. I'd probably have
written it as something like
{
if (mode & EMIT_INVALIDATE)
mi_flush(INVALIDATE_TLB);
mi_flush(0);
}
Either way it seems to do what it says so
Reviewed-by: Ville Syrjälä
>
> - *cs++ = cmd;
> - *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
> - *cs++ = 0;
> - *cs++ = MI_NOOP;
> - intel_ring_advance(rq, cs);
> return 0;
> }
>
> +static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
> +{
> + return emit_mi_flush_dw(rq, mode,
> + MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
> +}
> +
> static int
> hsw_emit_bb_start(struct i915_request *rq,
> u64 offset, u32 len,
> @@ -2022,36 +2044,7 @@ gen6_emit_bb_start(struct i915_request *rq,
>
> static int gen6_ring_flush(struct i915_request *rq, u32 mode)
> {
> - u32 cmd, *cs;
> -
> - cs = intel_ring_begin(rq, 4);
> - if (IS_ERR(cs))
> - return
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev5)
== Series Details ==
Series: Add XYUV format support (rev5)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48d9e0cf5f5e drm: Introduce new DRM_FORMAT_XYUV
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:42: WARNING:LONG_LINE_COMMENT: line over 100 characters
#42: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
total: 0 errors, 2 warnings, 0 checks, 14 lines checked
7eb5932ca612 drm/i915: Adding YUV444 packed format support for skl+
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10052 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48906/revisions/4/mbox/
== Known issues ==
Here are the changes found in Patchwork_10052 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: PASS -> INCOMPLETE (fdo#107402)
igt@debugfs_test@read_all_entries:
fi-kbl-7560u: PASS -> INCOMPLETE (fdo#103665)
igt@gem_exec_suspend@basic-s3:
{fi-kbl-soraka}:NOTRUN -> INCOMPLETE (fdo#107556)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362, fdo#103191)
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: PASS -> FAIL (fdo#107336)
Possible fixes
{igt@amdgpu/amd_prime@i915-to-amd}:
fi-bxt-j4205: INCOMPLETE (fdo#103927) -> SKIP
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#107362, fdo#103191) -> PASS
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602, fdo#107708) -> PASS
fi-bxt-j4205: DMESG-FAIL (fdo#107712) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708
fdo#107712 https://bugs.freedesktop.org/show_bug.cgi?id=107712
== Participating hosts (53 -> 49) ==
Additional (1): fi-kbl-soraka
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4740 -> Patchwork_10052
CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10052: 41720addaafc699fddfd9771f8825b32c205bef9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
41720addaafc drm/i915/selftests: Add a simple exerciser for suspend/hibernate
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10052/issues.html
___
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[Intel-gfx] [PULL] drm-misc-next for 4.20
Hi Dave, Here's the first PR for 4.20 (Seth Rogan edition). It's super light compared to most PRs after feature freeze. Perhaps we were all enjoying summer a bit too much! Anyways, nothing controversial, tag description says it all. drm-misc-next-2018-08-30: drm-misc-next for 4.20: UAPI Changes: - Add per-plane blend mode property (Lowry) - Change in drm_fourcc.h is documentation only (Brian) Cross-subsystem Changes: - None Core Changes: - Add get/verify_crc_source for improved crc source selection (Mahesh) - Add __drm_atomic_helper_plane_reset to reduce copypasta (Alexandru) Driver Changes: - various: Replance ref/unref calls with drm_dev_get/put (Thomas) - bridge: Add driver for TI SN65DSI86 chip (Sandeep) - rockchip: Add PX30 support (Sandy) - sun4i: Add support for R40 TCON (Jernej) - vkms: Continued building out vkms, added gem support (Haneen) Cc: Thomas Zimmermann Cc: Sandeep Panda Cc: Sean Paul Cc: Sandy Huang Cc: Lowry Li Cc: Brian Starkey Cc: Jernej Skrabec Cc: Haneen Mohammed Cc: Alexandru Gheorghe Cheers, Sean The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3: Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2018-08-30 for you to fetch changes up to 09c4b49457434fa74749ad6194ef28464d9f5df9: drm/virtio: fix bounds check in virtio_gpu_cmd_get_capset() (2018-08-30 09:41:03 +0200) drm-misc-next for 4.20: UAPI Changes: - Add per-plane blend mode property (Lowry) - Change in drm_fourcc.h is documentation only (Brian) Cross-subsystem Changes: - None Core Changes: - Add get/verify_crc_source for improved crc source selection (Mahesh) - Add __drm_atomic_helper_plane_reset to reduce copypasta (Alexandru) Driver Changes: - various: Replance ref/unref calls with drm_dev_get/put (Thomas) - bridge: Add driver for TI SN65DSI86 chip (Sandeep) - rockchip: Add PX30 support (Sandy) - sun4i: Add support for R40 TCON (Jernej) - vkms: Continued building out vkms, added gem support (Haneen) Cc: Thomas Zimmermann Cc: Sandeep Panda Cc: Sean Paul Cc: Sandy Huang Cc: Lowry Li Cc: Brian Starkey Cc: Jernej Skrabec Cc: Haneen Mohammed Cc: Alexandru Gheorghe Alexandru Gheorghe (8): drm/atomic: Add __drm_atomic_helper_plane_reset drm: mali-dp: Use __drm_atomic_helper_plane_reset instead of copying the logic drm: atmel-hlcdc: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/imx: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/sun4i: Use __drm_atomic_helper_plane_reset instead of copying the logic drm: rcar-du: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/vc4: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/vmwgfx: Use __drm_atomic_helper_plane_reset instead of copying the logic Andrzej Hajda (3): dt-bindings: tc358754: add DT bindings drm/bridge: tc358764: Add DSI to LVDS bridge driver drm/bridge/tc358764: fix drm helper name Anton Vasilyev (2): drm: qxl: Fix error handling at qxl_device_init drm: qxl: Fix NULL pointer dereference at qxl_alloc_client_monitors_config Archit Taneja (2): dt-bindings: mipi-dsi: Add info about peripherals with non-DSI control bus dt-bindings: mipi-dsi: Add dual-channel DSI related info Ayan Kumar Halder (2): drm/sun4i: Use (struct drm_format_info) fields to determine if a format is yuv and multi planar or not. drm: Use horizontal and vertical chroma subsampling factor while calculating offsets in the physical address of framebuffer Brian Starkey (1): drm/fourcc: Add DOC: overview comment Chris Wilson (1): dma-buf: Remove requirement for ops->map() from dma_buf_export Dan Carpenter (1): drm/virtio: fix bounds check in virtio_gpu_cmd_get_capset() Daniel Vetter (5): drm/i915: Remove unecessary dma_fence_ops drm/msm: Remove unecessary dma_fence_ops drm/nouveau: Remove unecessary dma_fence_ops drm/vgem: Remove unecessary dma_fence_ops drm/syncobj: Drop add/remove_callback from driver interface Gerd Hoffmann (1): drm/cirrus: flip default from 24bpp to 16bpp Giulio Benetti (1): drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE checking if panel is used. Guenter Roeck (1): drm/bridge: ti-sn65dsi86: Fix 0-day build error Gustavo A. R. Silva (2): drm/sun4i: tcon-top: Use struct_size() in devm_kzalloc() drm/rockchip: Use struct_size() in devm_kzalloc() Haneen Mohammed (8): drm/vkms: Add functions to map/unmap GEM backing storage drm/vkms: map/unmap buffers in [prepare/cleanup]_fb hooks drm/vkms: Add atomic_helper_check_plane_state drm/vkms: subclass CRTC state drm/vkms: Subclass plane state drm/vkms: Impl
Re: [Intel-gfx] [PATCH v4 1/2] drm: Add connector property to limit max bpc
On Thu, Aug 30, 2018 at 08:06:48AM -0700, Radhakrishna Sripada wrote:
> At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> level shifters etc. To workaround them we may need to drive the output
> at a lower bpc. Currently the user space does not have a way to limit
> the bpc. The default bpc to be programmed is decided by the driver and
> is run against connector limitations.
>
> Creating a new connector property "max bpc" in order to limit the bpc.
> xrandr can make use of this connector property to make sure that bpc does
> not exceed the configured value. This property can be used by userspace to
> set the bpc.
>
> V2: Initialize max_bpc to satisfy kms_properties
> V3: Move the property to drm_connector
> V4: Split drm and i915 components(Ville)
>
> Cc: Ville Syrjälä
> Cc: Kishore Kadiyala
> Cc: Rodrigo Vivi
> Cc: Manasi Navare
> Cc: Stanislav Lisovskiy
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/drm_atomic.c| 4
> drivers/gpu/drm/drm_atomic_helper.c | 4
> include/drm/drm_connector.h | 6 ++
> include/drm/drm_mode_config.h | 5 +
> 4 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index d0478abc01bd..4e352fc1f0a0 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1420,6 +1420,8 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
>
> return set_out_fence_for_connector(state->state, connector,
> fence_ptr);
> + } else if (property == config->max_bpc_property) {
> + state->max_bpc = val;
> } else if (connector->funcs->atomic_set_property) {
> return connector->funcs->atomic_set_property(connector,
> state, property, val);
> @@ -1515,6 +1517,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> *val = 0;
> } else if (property == config->writeback_out_fence_ptr_property) {
> *val = 0;
> + } else if (property == config->max_bpc_property) {
> + *val = state->max_bpc;
> } else if (connector->funcs->atomic_get_property) {
> return connector->funcs->atomic_get_property(connector,
> state, property, val);
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 2c23a48482da..7f763650a623 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -638,6 +638,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
> if (old_connector_state->link_status !=
> new_connector_state->link_status)
> new_crtc_state->connectors_changed = true;
> +
> + if (old_connector_state->max_bpc !=
> + new_connector_state->max_bpc)
> + new_crtc_state->connectors_changed = true;
> }
>
> if (funcs->atomic_check)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 97ea41dc678f..fc11f40aae51 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -460,6 +460,12 @@ struct drm_connector_state {
>* drm_writeback_signal_completion()
>*/
> struct drm_writeback_job *writeback_job;
> +
> + /**
> + * @max_bpc: Connector property to limit the maximum bit depth of
> + * the pixels.
> + */
> + unsigned int max_bpc;
> };
>
> /**
> diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
> index a0b202e1d69a..b9cd7a73b244 100644
> --- a/include/drm/drm_mode_config.h
> +++ b/include/drm/drm_mode_config.h
> @@ -562,6 +562,11 @@ struct drm_mode_config {
>*/
> struct drm_property *link_status_property;
> /**
> + * @max_bpc_property: Default connector property for the max bpc to be
> + * driven out of the connector.
> + */
> + struct drm_property *max_bpc_property;
If we want the exposed limits to be accurate this needs to be
per-connector. The other option of course is to just expose the
global min-max range for the entire device.
The way you wrote the i915 bits suggest you wanted to go for
the per-connector apporach instead.
> + /**
>* @plane_type_property: Default plane property to differentiate
>* CURSOR, PRIMARY and OVERLAY legacy uses of planes.
>*/
> --
> 2.9.3
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
== Series Details == Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4) URL : https://patchwork.freedesktop.org/series/48906/ State : warning == Summary == $ dim checkpatch origin/drm-tip 41720addaafc drm/i915/selftests: Add a simple exerciser for suspend/hibernate -:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 -:39: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #39: FILE: drivers/gpu/drm/i915/selftests/i915_gem.c:1: +/* total: 0 errors, 2 warnings, 0 checks, 233 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Kishore Kadiyala
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 25 +
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c| 7 +++
drivers/gpu/drm/i915/intel_modes.c | 21 +
5 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4bb46f289c0d..216fd4b689b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10783,6 +10783,28 @@ connected_sink_compute_bpp(struct intel_connector
*connector,
}
}
+static void
+connected_sink_max_bpp(struct drm_connector_state *conn_state,
+struct intel_crtc_state *pipe_config)
+{
+ switch (conn_state->max_bpc) {
+ case 8:
+ case 9:
+ pipe_config->pipe_bpp = 8*3;
+ break;
+ case 10:
+ case 11:
+ pipe_config->pipe_bpp = 10*3;
+ break;
+ case 12:
+ pipe_config->pipe_bpp = 12*3;
+ break;
+ default:
+ break;
+ }
+ DRM_DEBUG_KMS("Limiting display bpp to %d\n", pipe_config->pipe_bpp);
+}
+
static int
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
@@ -10811,6 +10833,9 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
if (connector_state->crtc != &crtc->base)
continue;
+ if (connector_state->max_bpc)
+ connected_sink_max_bpp(connector_state, pipe_config);
+
connected_sink_compute_bpp(to_intel_connector(connector),
pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..1c2d38b7f6ab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5719,6 +5719,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_max_bpc_property(connector, 6, 16);
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..b3c703dacc92 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1869,6 +1869,8 @@ int intel_ddc_get_modes(struct drm_connector *c, struct
i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
+void intel_attach_max_bpc_property(struct drm_connector *connector, int min,
int
+ max);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index a2dab0b6bde6..e649bbf07642 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2109,11 +2109,18 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_attach_aspect_ratio_property(connector);
drm_connector_attach_content_type_property(connector);
connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
+ if (HAS_GMCH_DISPLAY(dev_priv))
+ intel_attach_max_bpc_property(connector, 8, 8);
+ else
+ intel_attach_max_bpc_property(connector, 8, 12);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index ca44bf368e24..eb1eaad0115e 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -133,3 +133,24 @@ intel_attach_aspect_ratio_property(struct drm_connector
*connector)
connector->dev->mode_config.aspect_ratio_property,
DRM_MODE_PICTURE_ASPECT_NONE);
}
+
+void
+intel_attach_max_bpc_property(struct drm_connector *connector, int min, int
+ max)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_mode_config *config = &dev->mode_config;
[Intel-gfx] [PATCH v4 1/2] drm: Add connector property to limit max bpc
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against connector limitations.
Creating a new connector property "max bpc" in order to limit the bpc.
xrandr can make use of this connector property to make sure that bpc does
not exceed the configured value. This property can be used by userspace to
set the bpc.
V2: Initialize max_bpc to satisfy kms_properties
V3: Move the property to drm_connector
V4: Split drm and i915 components(Ville)
Cc: Ville Syrjälä
Cc: Kishore Kadiyala
Cc: Rodrigo Vivi
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/drm_atomic.c| 4
drivers/gpu/drm/drm_atomic_helper.c | 4
include/drm/drm_connector.h | 6 ++
include/drm/drm_mode_config.h | 5 +
4 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index d0478abc01bd..4e352fc1f0a0 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1420,6 +1420,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return set_out_fence_for_connector(state->state, connector,
fence_ptr);
+ } else if (property == config->max_bpc_property) {
+ state->max_bpc = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -1515,6 +1517,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = 0;
} else if (property == config->writeback_out_fence_ptr_property) {
*val = 0;
+ } else if (property == config->max_bpc_property) {
+ *val = state->max_bpc;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 2c23a48482da..7f763650a623 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -638,6 +638,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (old_connector_state->link_status !=
new_connector_state->link_status)
new_crtc_state->connectors_changed = true;
+
+ if (old_connector_state->max_bpc !=
+ new_connector_state->max_bpc)
+ new_crtc_state->connectors_changed = true;
}
if (funcs->atomic_check)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 97ea41dc678f..fc11f40aae51 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -460,6 +460,12 @@ struct drm_connector_state {
* drm_writeback_signal_completion()
*/
struct drm_writeback_job *writeback_job;
+
+ /**
+* @max_bpc: Connector property to limit the maximum bit depth of
+* the pixels.
+*/
+ unsigned int max_bpc;
};
/**
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index a0b202e1d69a..b9cd7a73b244 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -562,6 +562,11 @@ struct drm_mode_config {
*/
struct drm_property *link_status_property;
/**
+* @max_bpc_property: Default connector property for the max bpc to be
+* driven out of the connector.
+*/
+ struct drm_property *max_bpc_property;
+ /**
* @plane_type_property: Default plane property to differentiate
* CURSOR, PRIMARY and OVERLAY legacy uses of planes.
*/
--
2.9.3
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[Intel-gfx] ✓ Fi.CI.IGT: success for linux/mei: Header for mei_hdcp driver interface
== Series Details == Series: linux/mei: Header for mei_hdcp driver interface URL : https://patchwork.freedesktop.org/series/48922/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4738_full -> Patchwork_10043_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10043_full that come from known issues: === IGT changes === Issues hit igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@perf_pmu@enable-race-bcs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: FAIL (fdo#103375) -> PASS fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4738 -> Patchwork_10043 CI_DRM_4738: e1ec819ee824a4ed48f168bea66dba4da464e555 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10043: 45780f07f9799a53de8cc28b236cb6bdb8e168e8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10043/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface
On 30/08/2018 14:29, Lis, Tomasz wrote:
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to
have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Lucas De Marchi
Cc: Tomasz Lis
Tested-by: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 13 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a34e8f..bc81354 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -85,6 +85,7 @@ struct engine_info {
unsigned int hw_id;
unsigned int uabi_id;
u8 class;
+ u8 guc_class;
u8 instance;
/* mmio bases table *must* be sorted in reverse gen order */
struct engine_mmio_base {
@@ -98,6 +99,7 @@ struct engine_info {
.hw_id = RCS_HW,
.uabi_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
+ .guc_class = GUC_RENDER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 1, .base = RENDER_RING_BASE }
@@ -107,6 +109,7 @@ struct engine_info {
.hw_id = BCS_HW,
.uabi_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
+ .guc_class = GUC_BLITTER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 6, .base = BLT_RING_BASE }
@@ -116,6 +119,7 @@ struct engine_info {
.hw_id = VCS_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD_RING_BASE },
@@ -127,6 +131,7 @@ struct engine_info {
.hw_id = VCS2_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
@@ -137,6 +142,7 @@ struct engine_info {
.hw_id = VCS3_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 2,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
@@ -146,6 +152,7 @@ struct engine_info {
.hw_id = VCS4_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 3,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
@@ -155,6 +162,7 @@ struct engine_info {
.hw_id = VECS_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
@@ -165,6 +173,7 @@ struct engine_info {
.hw_id = VECS2_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
@@ -276,6 +285,9 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
+ if (GEM_WARN_ON(info->guc_class >= GUC_MAX_ENGINE_CLASSES))
+ return -EINVAL;
+
if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
return -EINVAL;
@@ -291,6 +303,7 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
engine->i915 = dev_priv;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
+ engine->guc_class = info->guc_class;
engine->mmio_base = __engine_mmio_base(dev_priv,
info->mmio_bases);
engine->class = info->class;
engine->instance = info->instance;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 963da91..5b7a05b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,13 @@
#define GUC_VIDEO_ENGINE2 4
#define GUC_MAX_ENGINES_NUM (GUC_V
[Intel-gfx] ✓ Fi.CI.BAT: success for Add XYUV format support (rev4)
== Series Details ==
Series: Add XYUV format support (rev4)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10051 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/4/mbox/
== Known issues ==
Here are the changes found in Patchwork_10051 that come from known issues:
=== IGT changes ===
Issues hit
igt@kms_flip@basic-flip-vs-modeset:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362, fdo#103191)
Possible fixes
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10051
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10051: 739561aa6dabed60e865ba296435c02b0adb0b6c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
739561aa6dab drm/i915: Adding YUV444 packed format support for skl+
e971390c33e8 drm: Introduce new DRM_FORMAT_XYUV
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10051/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: clear error registers after error capture (rev4)
== Series Details == Series: drm/i915: clear error registers after error capture (rev4) URL : https://patchwork.freedesktop.org/series/48939/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10050 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/48939/revisions/4/mbox/ == Known issues == Here are the changes found in Patchwork_10050 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-glk-j4005: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4739 -> Patchwork_10050 CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10050: d5b724ce03b4fabe0b79130835f798e28bb4f390 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d5b724ce03b4 drm/i915: clear error registers after error capture == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10050/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev4)
== Series Details ==
Series: Add XYUV format support (rev4)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e971390c33e8 drm: Introduce new DRM_FORMAT_XYUV
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:40: WARNING:LONG_LINE_COMMENT: line over 100 characters
#40: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
total: 0 errors, 2 warnings, 0 checks, 14 lines checked
739561aa6dab drm/i915: Adding YUV444 packed format support for skl+
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[Intel-gfx] [PATCH v9 0/2] Add XYUV format support
Introduced new XYUV scan-in format for framebuffer and added support for it to i915(SkyLake+). Stanislav Lisovskiy (2): drm: Introduce new DRM_FORMAT_XYUV drm/i915: Adding YUV444 packed format support for skl+ drivers/gpu/drm/drm_fourcc.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 15 +++ drivers/gpu/drm/i915/intel_sprite.c | 1 + include/uapi/drm/drm_fourcc.h| 1 + 5 files changed, 19 insertions(+), 1 deletion(-) -- 2.17.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 15 +++
drivers/gpu/drm/i915/intel_sprite.c | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88a60f6..e0c8480aaa02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6499,7 +6499,7 @@ enum {
#define PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
#define PLANE_CTL_FORMAT_XRGB_ (4 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1a3037..9323708db71f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const uint32_t skl_pri_planar_formats[] = {
@@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_NV12,
};
@@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR2101010:
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_XYUV:
+ if (INTEL_GEN(dev_priv) < 9) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+
drm_get_format_name(mode_cmd->pixel_format, &format_name));
+ goto err;
+ }
+ break;
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda625e4..2ac9471974c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1420,6 +1420,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.17.0
_
[Intel-gfx] [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..2ad09c7ecebc 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9ae16a..5ba5b1473342 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -148,6 +148,7 @@ extern "C" {
#define DRM_FORMAT_VYUYfourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* 2 plane RGB + A
--
2.17.0
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Re: [Intel-gfx] [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface
Uhh, sorry - answered on wrong patch.
Please ignore this one.
-Tomasz
On 2018-08-30 15:29, Lis, Tomasz wrote:
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to
have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Lucas De Marchi
Cc: Tomasz Lis
Tested-by: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 13 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a34e8f..bc81354 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -85,6 +85,7 @@ struct engine_info {
unsigned int hw_id;
unsigned int uabi_id;
u8 class;
+ u8 guc_class;
u8 instance;
/* mmio bases table *must* be sorted in reverse gen order */
struct engine_mmio_base {
@@ -98,6 +99,7 @@ struct engine_info {
.hw_id = RCS_HW,
.uabi_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
+ .guc_class = GUC_RENDER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 1, .base = RENDER_RING_BASE }
@@ -107,6 +109,7 @@ struct engine_info {
.hw_id = BCS_HW,
.uabi_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
+ .guc_class = GUC_BLITTER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 6, .base = BLT_RING_BASE }
@@ -116,6 +119,7 @@ struct engine_info {
.hw_id = VCS_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD_RING_BASE },
@@ -127,6 +131,7 @@ struct engine_info {
.hw_id = VCS2_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
@@ -137,6 +142,7 @@ struct engine_info {
.hw_id = VCS3_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 2,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
@@ -146,6 +152,7 @@ struct engine_info {
.hw_id = VCS4_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 3,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
@@ -155,6 +162,7 @@ struct engine_info {
.hw_id = VECS_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
@@ -165,6 +173,7 @@ struct engine_info {
.hw_id = VECS2_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
@@ -276,6 +285,9 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
+ if (GEM_WARN_ON(info->guc_class >= GUC_MAX_ENGINE_CLASSES))
+ return -EINVAL;
+
if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
return -EINVAL;
@@ -291,6 +303,7 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
engine->i915 = dev_priv;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
+ engine->guc_class = info->guc_class;
engine->mmio_base = __engine_mmio_base(dev_priv,
info->mmio_bases);
engine->class = info->class;
engine->instance = info->instance;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 963da91..5b7a05b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,13 @@
#defi
Re: [Intel-gfx] [PATCH 08/21] drm/i915/guc: Make use of the SW counter field in the context descriptor
On 2018-08-30 02:08, Lionel Landwerlin wrote:
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the maximum number of
concurrent contexts we want to allow, so ideally we want to employ
every possible bit available. Unfortunately, a further limitation in
the interface with the GuC means the combination of SW Context ID +
SW Counter has to be unique within the same engine class (as we use
the SW Context ID to index in the GuC stage descriptor pool, and the
Engine Class + SW Counter to index in the 2-dimensional lrc array).
This essentially means we need to somehow encode the engine instance.
Since the BSpec allows 6 bits for engine instance, we use the whole
SW counter for this task. If the limitation of 2032 maximum simultaneous
contexts is too restrictive, we can always squeeze things a bit more
(3 extras bits for hw_id, 3 bits for instance) and things will still
work (Gen11 does not instance more than 8 engines of any class).
Another alternative would be to generate the hw_id per HW context
instead of per GEM context, but that has other problems (e.g. maximum
number of user-created contexts would be variable, no relationship
between a GuC principal descriptor and the proxy descriptor it uses,
...)
Bspec: 12254
Signed-off-by: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Tested-by: Tomasz Lis
---
drivers/gpu/drm/i915/i915_drv.h | 15 +++
drivers/gpu/drm/i915/i915_gem_context.c | 5 -
drivers/gpu/drm/i915/i915_gem_context.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 12 +---
5 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c..34f5495 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1866,14 +1866,21 @@ struct drm_i915_private {
struct llist_head free_list;
struct work_struct free_work;
- /* The hw wants to have a stable context identifier for the
+ /*
+ * The HW wants to have a stable context identifier for the
* lifetime of the context (for OA, PASID, faults, etc).
* This is limited in execlists to 21 bits.
+ * In enhanced execlist (GEN11+) this is limited to 11 bits
+ * (the SW Context ID field) but GuC limits it a bit further
+ * (11 bits - 16) due to some entries being reserved for future
+ * use (so the firmware only supports a GuC stage descriptor
+ * pool of 2032 entries).
*/
struct ida hw_ida;
-#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
-#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
-#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+#define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */
+#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC (GEN11_MAX_CONTEXT_HW_ID - 16)
} contexts;
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039..e3b500c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -209,7 +209,10 @@ static int assign_hw_id(struct drm_i915_private
*dev_priv, unsigned *out)
unsigned int max;
if (INTEL_GEN(dev_priv) >= 11) {
- max = GEN11_MAX_CONTEXT_HW_ID;
+ if (USES_GUC_SUBMISSION(dev_priv))
+ max = GEN11_MAX_CONTEXT_HW_ID_WITH_GUC;
+ else
+ max = GEN11_MAX_CONTEXT_HW_ID;
} else {
/*
* When using GuC in proxy submission, GuC consumes the
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 851dad6..4b87f5d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -154,6 +154,8 @@ struct i915_gem_context {
struct intel_ring *ring;
u32 *lrc_reg_state;
u64 lrc_desc;
+ u32 sw_context_id;
+ u32 sw_counter;
int pin_count;
const struct intel_context_ops *ops;
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index f232178..ea65d7b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3900,6 +3900,8 @@ enum {
#define GEN8_CTX_ID_WIDTH 21
#define GEN11_SW_CTX_ID_SHIFT 37
#define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_SW_COUNTER_SHIFT 55
+#define GEN11_SW_COUNTER_WIDTH 6
Re: [Intel-gfx] [PATCH v4] drm/i915: clear error registers after error capture
Quoting Lionel Landwerlin (2018-08-30 14:24:24) > We need to clear the register in order to get correct value after the > next potential hang. > > v2: Centralize error register clearing in i915_irq.c (Chris) > > v3: Don't read gen8 register on < gen6 (Chris) > > v4: Don't swap gen8+ & gen6+ code... (Chris) > > Signed-off-by: Lionel Landwerlin > Reviewed-by: Chris Wilson Lgtm, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: clear error registers after error capture (rev4)
== Series Details == Series: drm/i915: clear error registers after error capture (rev4) URL : https://patchwork.freedesktop.org/series/48939/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: clear error registers after error capture -drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3687:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10049 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48947/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10049 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_hangcheck:
fi-skl-guc: PASS -> DMESG-FAIL (fdo#107174, fdo#106685)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
{fi-byt-clapper}: PASS -> FAIL (fdo#103191, fdo#107362)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106685 https://bugs.freedesktop.org/show_bug.cgi?id=106685
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10049
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10049: bcd3b9a19948bd0667c4d37e6a31b995f1cad0a1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bcd3b9a19948 drm/i915: enable P010, P012, P016 formats for primary and sprite
planes
fc793f439251 drm/i915: preparations for enabling P010, P012, P016 formats
c6edb7988b5a drm/i915: Add P010, P012, P016 plane control definitions
c67c3d800643 drm: Add P010, P012, P016 format definitions and fourcc
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10049/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On Thu, Aug 30, 2018 at 03:41:13PM +0300, Juha-Pekka Heikkila wrote:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> (Sharma, Swati2): removed unnecessary checks, changed debug error message
> to be more generic.
>
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 3 +--
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 41
> +--
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 19 +++---
> drivers/gpu/drm/i915/intel_sprite.c | 18 +-
> 6 files changed, 63 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
> /* set scaler mode */
> if ((INTEL_GEN(dev_priv) >= 9) &&
> plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->format ==
> - DRM_FORMAT_NV12) {
> + is_planar_yuv_format(plane_state->base.fb->format->format))
> {
Since there is .is_yuv now it might make sense to stick this into some
common place (drm_fourcc.h perhaps) as something like
'is_yuv && num_planes > 1'
> if (INTEL_GEN(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv) &&
> !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index fa7df5f..d64d993 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> else
> crtc_state->active_planes &= ~BIT(intel_plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
> crtc_state->nv12_planes |= BIT(intel_plane->id);
> else
> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4bb46f2..43efeb4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
> bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_P010:
> + return DRM_FORMAT_P010;
> + case PLANE_CTL_FORMAT_P012:
> + return DRM_FORMAT_P012;
> + case PLANE_CTL_FORMAT_P016:
> + return DRM_FORMAT_P016;
> default:
> case PLANE_CTL_FORMAT_XRGB_:
> if (rgb_order) {
> @@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
>* Handle the AUX surface first since
>* the main surface setup depends on it.
>*/
> - if (fb->format->format == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fb->format->format)) {
> ret = skl_check_nv12_surface(crtc_state, plane_state);
> if (ret)
> return ret;
> @@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_P010:
> + return PLANE_CTL_FORMAT_P010;
> + case DRM_FORMAT_P012:
> + return PLANE_CTL_FORMAT_P012;
> + case DRM_FORMAT_P016:
> + return PLANE_CTL_FORMAT_P016;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> if (plane_scaler_check)
> - if (pixel_format == DRM_FORMAT_NV12)
> - need_scaling = true;
> + need_scaling = is_planar_yuv_format(pixel_format);
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> return 0;
> }
>
> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> -
Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Adding YUV444 packed format support for skl+
On Thu, Aug 30, 2018 at 04:40:27PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic, to reuse code from other case
> labels.
>
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added scaling support for DRM_FORMAT_XYUV
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 9 +
> drivers/gpu/drm/i915/intel_sprite.c | 1 +
> 3 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88a60f6..e0c8480aaa02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6499,7 +6499,7 @@ enum {
> #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> #define PLANE_CTL_FORMAT_XRGB_ (4 << 24)
> #define PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24)
> -#define PLANE_CTL_FORMAT_AYUV (8 << 24)
> +#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1a3037..69ddecbcc224 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV,
> };
>
> static const uint32_t skl_pri_planar_formats[] = {
> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV,
> DRM_FORMAT_NV12,
> };
>
> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order,
> bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XYUV:
> + return DRM_FORMAT_XYUV;
> default:
> case PLANE_CTL_FORMAT_XRGB_:
> if (rgb_order) {
> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR2101010:
> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> + case DRM_FORMAT_XYUV:
> + return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> case DRM_FORMAT_YVYU:
> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
> 0x%x\n",
> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct
> drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14517,6 +14525,7 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> }
> break;
> case DRM_FORMAT_ABGR:
> + case DRM_FORMAT_XYUV:
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
VLV/CHV doesn't have this so this still looks like the wrong place.
> INTEL_GEN(dev_priv) < 9) {
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index c286dda625e4..2ac9471974c2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1420,6 +1420,7 @@ static bool skl_plane_format_mod_supported(struct
> drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> --
> 2.17.0
>
> _
[Intel-gfx] [PATCH v4] drm/i915/selftests: Add a simple exerciser for suspend/hibernate
Although we cannot do a full system-level test of suspend/hibernate from
deep with the kernel selftests, we can exercise the GEM subsystem in
isolation and simulate the external effects (such as losing stolen
contents and trashing the register state).
v2: Don't forget to hold rpm
v3: Suspend the GTT mappings, and more rpm!
Signed-off-by: Chris Wilson
Cc: Jakub Bartmiński
Cc: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/selftests/i915_gem.c | 221 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 223 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0453eb42a1a3..7b7bbfe59697 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -6207,4 +6207,5 @@ int i915_gem_object_attach_phys(struct
drm_i915_gem_object *obj, int align)
#include "selftests/huge_pages.c"
#include "selftests/i915_gem_object.c"
#include "selftests/i915_gem_coherency.c"
+#include "selftests/i915_gem.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
new file mode 100644
index ..e9cfc1fb0c07
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -0,0 +1,221 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+
+#include "../i915_selftest.h"
+
+#include "mock_context.h"
+#include "igt_flush_test.h"
+
+static int switch_to_context(struct drm_i915_private *i915,
+struct i915_gem_context *ctx)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ intel_runtime_pm_get(i915);
+
+ for_each_engine(engine, i915, id) {
+ struct i915_request *rq;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+ }
+
+ intel_runtime_pm_put(i915);
+
+ return err;
+}
+
+static int pm_prepare(struct drm_i915_private *i915)
+{
+ int err = 0;
+
+ if (i915_gem_suspend(i915)) {
+ pr_err("i915_gem_suspend failed\n");
+ err = -EINVAL;
+ }
+
+ return err;
+}
+
+static void trash_stolen(struct drm_i915_private *i915)
+{
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ const u64 slot = ggtt->error_capture.start;
+ const resource_size_t size = resource_size(&i915->dsm);
+ unsigned long page;
+ u32 prng = 0x12345678;
+
+ for (page = 0; page < size; page += PAGE_SIZE) {
+ const dma_addr_t dma = i915->dsm.start + page;
+ u32 __iomem *s;
+ int x;
+
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+
+ s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
+ for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
+ prng = next_pseudo_random32(prng);
+ iowrite32(prng, &s[x]);
+ }
+ io_mapping_unmap_atomic(s);
+ }
+
+ ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
+}
+
+static void simulate_hibernate(struct drm_i915_private *i915)
+{
+ intel_runtime_pm_get(i915);
+
+ /*
+* As a final sting in the tail, invalidate stolen. Under a real S4,
+* stolen is lost and needs to be refilled on resume. However, under
+* CI we merely do S4-device testing (as full S4 is too unreliable
+* for automated testing across a cluster), so to simulate the effect
+* of stolen being trashed across S4, we trash it ourselves.
+*/
+ trash_stolen(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static void pm_resume(struct drm_i915_private *i915)
+{
+ /*
+* Both suspend and hibernate follow the same wakeup path and assume
+* that runtime-pm just works.
+*/
+ intel_runtime_pm_get(i915);
+
+ intel_engines_sanitize(i915);
+ i915_gem_sanitize(i915);
+ i915_gem_resume(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static void pm_suspend(struct drm_i915_private *i915)
+{
+ intel_runtime_pm_get(i915);
+
+ i915_gem_suspend_gtt_mappings(i915);
+ i915_gem_suspend_late(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static int igt_gem_suspend(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ err = -ENOMEM;
+ mutex_lock(&i915->drm.struct_mutex);
+ ctx = live_context(i915, file);
+ if (!IS_ERR(ctx))
+ err = switch_to_context(i915
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
== Series Details == Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc URL : https://patchwork.freedesktop.org/series/48947/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Add P010, P012, P016 format definitions and fourcc Okay! Commit: drm/i915: Add P010, P012, P016 plane control definitions Okay! Commit: drm/i915: preparations for enabling P010, P012, P016 formats -O:drivers/gpu/drm/i915/intel_display.c:13188:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:13188:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13202:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13202:21: warning: expression using sizeof(void) Commit: drm/i915: enable P010, P012, P016 formats for primary and sprite planes Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3)
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10048 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48906/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10048:
=== IGT changes ===
Possible regressions
{igt@drv_selftest@live_gem}:
fi-whl-u: NOTRUN -> DMESG-FAIL
fi-pnv-d510:NOTRUN -> DMESG-FAIL
fi-skl-6600u: NOTRUN -> DMESG-FAIL
fi-kbl-7560u: NOTRUN -> DMESG-FAIL
fi-cfl-s3: NOTRUN -> DMESG-FAIL
{fi-skl-iommu}: NOTRUN -> DMESG-FAIL
fi-hsw-4770r: NOTRUN -> DMESG-FAIL
fi-elk-e7500: NOTRUN -> DMESG-FAIL
fi-skl-6700k2: NOTRUN -> DMESG-FAIL
{fi-bsw-kefka}: NOTRUN -> DMESG-FAIL
fi-skl-6700hq: NOTRUN -> DMESG-FAIL
fi-bdw-5557u: NOTRUN -> DMESG-FAIL
fi-glk-dsi: NOTRUN -> DMESG-FAIL
fi-skl-guc: NOTRUN -> DMESG-FAIL
fi-kbl-guc: NOTRUN -> DMESG-FAIL
{fi-cfl-8109u}: NOTRUN -> DMESG-FAIL
{fi-byt-clapper}: NOTRUN -> DMESG-FAIL
fi-bdw-gvtdvm: NOTRUN -> DMESG-FAIL
fi-kbl-7500u: NOTRUN -> DMESG-FAIL
fi-cfl-8700k: NOTRUN -> DMESG-FAIL
fi-snb-2520m: NOTRUN -> DMESG-FAIL
fi-bxt-dsi: NOTRUN -> DMESG-FAIL
fi-hsw-4770:NOTRUN -> DMESG-FAIL
fi-ivb-3520m: NOTRUN -> DMESG-FAIL
fi-cfl-guc: NOTRUN -> DMESG-FAIL
fi-skl-6770hq: NOTRUN -> DMESG-FAIL
fi-bsw-n3050: NOTRUN -> DMESG-FAIL
fi-ilk-650: NOTRUN -> DMESG-FAIL
fi-ivb-3770:NOTRUN -> DMESG-FAIL
fi-skl-gvtdvm: NOTRUN -> DMESG-FAIL
fi-cnl-psr: NOTRUN -> DMESG-FAIL
fi-hsw-peppy: NOTRUN -> DMESG-FAIL
fi-skl-6260u: NOTRUN -> DMESG-FAIL
fi-bxt-j4205: NOTRUN -> DMESG-FAIL
fi-byt-n2820: NOTRUN -> DMESG-FAIL
fi-kbl-7567u: NOTRUN -> DMESG-FAIL
fi-kbl-x1275: NOTRUN -> DMESG-FAIL
fi-icl-u: NOTRUN -> DMESG-FAIL
fi-snb-2600:NOTRUN -> DMESG-FAIL
fi-bwr-2160:NOTRUN -> DMESG-FAIL
fi-gdg-551: NOTRUN -> DMESG-FAIL
fi-glk-j4005: NOTRUN -> DMESG-FAIL
{fi-kbl-8809g}: NOTRUN -> DMESG-FAIL
{fi-bdw-samus}: NOTRUN -> DMESG-FAIL
fi-blb-e6850: NOTRUN -> DMESG-FAIL
fi-byt-j1900: NOTRUN -> DMESG-FAIL
fi-kbl-r: NOTRUN -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10048 that come from known issues:
=== IGT changes ===
Issues hit
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362) +2
Possible fixes
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10048
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10048: c308e9f7b94b11e482e9f618b9ec44b2de612c25 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c308e9f7b94b drm/i915/selftests: Add a simple exerciser for suspend/hibernate
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10048/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c67c3d800643 drm: Add P010, P012, P016 format definitions and fourcc
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_P010,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_P012,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_P016,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:186:
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
subsampled Cr:Cb plane, 10 bit per channel */
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:187:
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
subsampled Cr:Cb plane, 12 bit per channel */
-:50: WARNING:LONG_LINE_COMMENT: line over 100 characters
#50: FILE: include/uapi/drm/drm_fourcc.h:188:
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
subsampled Cr:Cb plane, 16 bit per channel */
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
c6edb7988b5a drm/i915: Add P010, P012, P016 plane control definitions
fc793f439251 drm/i915: preparations for enabling P010, P012, P016 formats
bcd3b9a19948 drm/i915: enable P010, P012, P016 formats for primary and sprite
planes
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 0/2] Add XYUV format support
Introduced new XYUV scan-in format for framebuffer and added support for it to i915(SkyLake+). Stanislav Lisovskiy (2): drm: Introduce new DRM_FORMAT_XYUV drm/i915: Adding YUV444 packed format support for skl+ drivers/gpu/drm/drm_fourcc.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 9 + drivers/gpu/drm/i915/intel_sprite.c | 1 + include/uapi/drm/drm_fourcc.h| 1 + 5 files changed, 13 insertions(+), 1 deletion(-) -- 2.17.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 2/2] drm/i915: Adding YUV444 packed format support for skl+
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 9 +
drivers/gpu/drm/i915/intel_sprite.c | 1 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88a60f6..e0c8480aaa02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6499,7 +6499,7 @@ enum {
#define PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
#define PLANE_CTL_FORMAT_XRGB_ (4 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1a3037..69ddecbcc224 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const uint32_t skl_pri_planar_formats[] = {
@@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_NV12,
};
@@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR2101010:
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -14517,6 +14525,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
break;
case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XYUV:
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
INTEL_GEN(dev_priv) < 9) {
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda625e4..2ac9471974c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1420,6 +1420,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.17.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 1/2] drm: Introduce new DRM_FORMAT_XYUV
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..2ad09c7ecebc 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9ae16a..5ba5b1473342 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -148,6 +148,7 @@ extern "C" {
#define DRM_FORMAT_VYUYfourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* 2 plane RGB + A
--
2.17.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm: drm/i915: Add connector property to limit max bpc
On Wed, Aug 29, 2018 at 03:57:05PM -0700, Radhakrishna Sripada wrote:
> On Mon, Aug 27, 2018 at 04:31:49PM +0300, Ville Syrjälä wrote:
> > On Fri, Aug 24, 2018 at 06:02:16PM -0700, Radhakrishna Sripada wrote:
> > > At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> > > level shifters etc. To workaround them we may need to drive the output
> > > at a lower bpc. Currently the user space does not have a way to limit
> > > the bpc. The default bpc to be programmed is decided by the driver and
> > > is run against connector limitations.
> > >
> > > Creating a new connector property "max bpc" in order to limit the bpc
> > > with which the pixels are scanned out. xrandr can make use of this
> > > connector property to make sure that bpc does not exceed the configured
> > > value.
> > > This property can be used by userspace to set the bpc.
> > >
> > > V2: Initialize max_bpc to satisfy kms_properties
> > > V3: Move the property to drm_connector
> > >
> > > Cc: Ville Syrjälä
> > > Cc: Kishore Kadiyala
> > > Cc: Rodrigo Vivi
> > > Cc: Manasi Navare
> > > Cc: Stanislav Lisovskiy
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/drm_atomic.c| 4
> > > drivers/gpu/drm/drm_atomic_helper.c | 4
> > > drivers/gpu/drm/i915/intel_drv.h| 2 ++
> > > drivers/gpu/drm/i915/intel_hdmi.c | 11 +++
> > > drivers/gpu/drm/i915/intel_modes.c | 20
> >
> > Pls move all the i915 stuff to the second patch.
> Sure will do it in the next rev.
>
> >
> > > include/drm/drm_connector.h | 6 ++
> > > include/drm/drm_mode_config.h | 5 +
> > > 7 files changed, 52 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > > index 3eb061e11e2e..461dde0c2c10 100644
> > > --- a/drivers/gpu/drm/drm_atomic.c
> > > +++ b/drivers/gpu/drm/drm_atomic.c
> > > @@ -1416,6 +1416,8 @@ static int drm_atomic_connector_set_property(struct
> > > drm_connector *connector,
> > >
> > > return set_out_fence_for_connector(state->state, connector,
> > > fence_ptr);
> > > + } else if (property == config->max_bpc_property) {
> > > + state->max_bpc = val;
> > > } else if (connector->funcs->atomic_set_property) {
> > > return connector->funcs->atomic_set_property(connector,
> > > state, property, val);
> > > @@ -1511,6 +1513,8 @@ drm_atomic_connector_get_property(struct
> > > drm_connector *connector,
> > > *val = 0;
> > > } else if (property == config->writeback_out_fence_ptr_property) {
> > > *val = 0;
> > > + } else if (property == config->max_bpc_property) {
> > > + *val = state->max_bpc;
> > > } else if (connector->funcs->atomic_get_property) {
> > > return connector->funcs->atomic_get_property(connector,
> > > state, property, val);
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c
> > > index 38ce9a375ffb..82caac8d1432 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -638,6 +638,10 @@ drm_atomic_helper_check_modeset(struct drm_device
> > > *dev,
> > > if (old_connector_state->link_status !=
> > > new_connector_state->link_status)
> > > new_crtc_state->connectors_changed = true;
> > > +
> > > + if (old_connector_state->max_bpc !=
> > > + new_connector_state->max_bpc)
> > > + new_crtc_state->connectors_changed = true;
> > > }
> > >
> > > if (funcs->atomic_check)
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 1b78de838c18..209eb1798238 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1862,6 +1862,8 @@ int intel_ddc_get_modes(struct drm_connector *c,
> > > struct i2c_adapter *adapter);
> > > void intel_attach_force_audio_property(struct drm_connector *connector);
> > > void intel_attach_broadcast_rgb_property(struct drm_connector
> > > *connector);
> > > void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> > > +void intel_attach_max_bpc_property(struct drm_connector *connector, int
> > > min, int
> > > +max);
> > >
> > >
> > > /* intel_overlay.c */
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index a1799b5c12bb..82739f342246 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -2097,11 +2097,22 @@ static const struct drm_encoder_funcs
> > > intel_hdmi_enc_funcs = {
> > > static void
> > > intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct
> > > drm_connector *con
Re: [Intel-gfx] [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Lucas De Marchi
Cc: Tomasz Lis
Tested-by: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 13 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
4 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a34e8f..bc81354 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -85,6 +85,7 @@ struct engine_info {
unsigned int hw_id;
unsigned int uabi_id;
u8 class;
+ u8 guc_class;
u8 instance;
/* mmio bases table *must* be sorted in reverse gen order */
struct engine_mmio_base {
@@ -98,6 +99,7 @@ struct engine_info {
.hw_id = RCS_HW,
.uabi_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
+ .guc_class = GUC_RENDER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 1, .base = RENDER_RING_BASE }
@@ -107,6 +109,7 @@ struct engine_info {
.hw_id = BCS_HW,
.uabi_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
+ .guc_class = GUC_BLITTER_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 6, .base = BLT_RING_BASE }
@@ -116,6 +119,7 @@ struct engine_info {
.hw_id = VCS_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD_RING_BASE },
@@ -127,6 +131,7 @@ struct engine_info {
.hw_id = VCS2_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
@@ -137,6 +142,7 @@ struct engine_info {
.hw_id = VCS3_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 2,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
@@ -146,6 +152,7 @@ struct engine_info {
.hw_id = VCS4_HW,
.uabi_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
+ .guc_class = GUC_VIDEO_CLASS,
.instance = 3,
.mmio_bases = {
{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
@@ -155,6 +162,7 @@ struct engine_info {
.hw_id = VECS_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 0,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
@@ -165,6 +173,7 @@ struct engine_info {
.hw_id = VECS2_HW,
.uabi_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
+ .guc_class = GUC_VIDEOENHANCE_CLASS,
.instance = 1,
.mmio_bases = {
{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
@@ -276,6 +285,9 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
+ if (GEM_WARN_ON(info->guc_class >= GUC_MAX_ENGINE_CLASSES))
+ return -EINVAL;
+
if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
return -EINVAL;
@@ -291,6 +303,7 @@ static void __sprint_engine_name(char *name,
const struct engine_info *info)
engine->i915 = dev_priv;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
+ engine->guc_class = info->guc_class;
engine->mmio_base = __engine_mmio_base(dev_priv,
info->mmio_bases);
engine->class = info->class;
engine->instance = info->instance;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 963da91..5b7a05b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,13 @@
#define GUC_VIDEO_ENGINE2 4
#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
+#define GUC_RENDER_CLA
[Intel-gfx] [PATCH v4] drm/i915: clear error registers after error capture
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
v3: Don't read gen8 register on < gen6 (Chris)
v4: Don't swap gen8+ & gen6+ code... (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++
drivers/gpu/drm/i915/i915_irq.c | 18 +-
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 40c93a37e385..34cca15be926 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2817,6 +2817,8 @@ extern void intel_irq_fini(struct drm_i915_private
*dev_priv);
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
+void i915_clear_error_registers(struct drm_i915_private *dev_priv);
+
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..d9d44639ba26 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2337,7 +2337,7 @@ static bool needs_idle_maps(struct drm_i915_private
*dev_priv)
return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
}
-static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_faults(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -2355,15 +2355,11 @@ static void gen6_check_and_clear_faults(struct
drm_i915_private *dev_priv)
fault & RING_FAULT_GTTSEL_MASK ?
"GGTT" : "PPGTT",
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(RING_FAULT_REG(engine),
- fault & ~RING_FAULT_VALID);
}
}
-
- POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
}
-static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen8_check_faults(struct drm_i915_private *dev_priv)
{
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
@@ -2388,22 +2384,20 @@ static void gen8_check_and_clear_faults(struct
drm_i915_private *dev_priv)
GEN8_RING_FAULT_ENGINE_ID(fault),
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(GEN8_RING_FAULT_REG,
- fault & ~RING_FAULT_VALID);
}
-
- POSTING_READ(GEN8_RING_FAULT_REG);
}
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
{
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
if (INTEL_GEN(dev_priv) >= 8)
- gen8_check_and_clear_faults(dev_priv);
+ gen8_check_faults(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
- gen6_check_and_clear_faults(dev_priv);
+ gen6_check_faults(dev_priv);
else
return;
+
+ i915_clear_error_registers(dev_priv);
}
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..e31093ce871c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3215,7 +3215,7 @@ static void i915_reset_device(struct drm_i915_private
*dev_priv,
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
}
-static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
+void i915_clear_error_registers(struct drm_i915_private *dev_priv)
{
u32 eir;
@@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
drm_i915_private *dev_priv)
I915_WRITE(EMR, I915_READ(EMR) | eir);
I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
}
+
+ if (INTEL_GEN(dev_priv) >= 8) {
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
+ POSTING_READ(GEN8_RING_FAULT_REG);
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+ I915_WRITE(RING_FAULT_REG(engine),
+ I915_READ(RING_FAULT_REG(engine)) &
+ ~RING_FAULT_VALID);
+ }
+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+ }
}
/**
--
2.18.0
_
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: clear error registers after error capture (rev3)
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev3)
URL : https://patchwork.freedesktop.org/series/48939/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10047 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48939/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_10047 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
Possible fixes
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602, fdo#107708) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10047
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10047: 08f01e2ac3a1d218de2e842151480d3a7e1126da @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
08f01e2ac3a1 drm/i915: clear error registers after error capture
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10047/issues.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3)
== Series Details == Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3) URL : https://patchwork.freedesktop.org/series/48906/ State : warning == Summary == $ dim checkpatch origin/drm-tip c308e9f7b94b drm/i915/selftests: Add a simple exerciser for suspend/hibernate -:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 -:39: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #39: FILE: drivers/gpu/drm/i915/selftests/i915_gem.c:1: +/* total: 0 errors, 2 warnings, 0 checks, 233 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: clear error registers after error capture (rev3)
== Series Details == Series: drm/i915: clear error registers after error capture (rev3) URL : https://patchwork.freedesktop.org/series/48939/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: clear error registers after error capture -drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3687:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reduce context HW ID lifetime (rev2)
== Series Details ==
Series: drm/i915: Reduce context HW ID lifetime (rev2)
URL : https://patchwork.freedesktop.org/series/44134/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10046 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/44134/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_10046 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: PASS -> INCOMPLETE (fdo#107402)
igt@kms_chamelium@dp-crc-fast:
fi-kbl-7500u: PASS -> DMESG-FAIL (fdo#103841)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)
Possible fixes
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602, fdo#107708) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708
== Participating hosts (54 -> 48) ==
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10046
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10046: 30bb0eb3b07e55636c05510321556c28fa14c9fd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
30bb0eb3b07e drm/i915: Reduce context HW ID lifetime
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10046/issues.html
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Re: [Intel-gfx] [PATCH v3] drm/i915: clear error registers after error capture
On 30/08/2018 13:04, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 12:55:32)
+ if (INTEL_GEN(dev_priv) >= 8) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+ I915_WRITE(RING_FAULT_REG(engine),
+ I915_READ(RING_FAULT_REG(engine)) &
+ ~RING_FAULT_VALID);
+ }
+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
+ POSTING_READ(GEN8_RING_FAULT_REG);
+ }
Reversed! gen8 has the single reg, gen6 has one per engine.
-Chris
Oh... I'm really sorry...
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Re: [Intel-gfx] [PATCH v7 2/2] drm/i915: Adding YUV444 packed format(DRM_FORMAT_XYUV) support.
On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
>
> On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy
> > wrote:
> > > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > > specification.
> > >
> > > v2: Edited commit message, removed redundant whitespaces.
> > >
> > > v3: Fixed fallthrough logic for the format switch cases.
> > >
> > > v4: Yet again fixed fallthrough logic, to reuse code from other
> > > case
> > > labels.
> > >
> > > v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> > >
> > > v6: Removed unneeded initializer for new XYUV format.
> > >
> > > v7: Added scaling support for DRM_FORMAT_XYUV
>
> I don't see yuv formats in skl_format_to_fourcc(), any idea why?
Good point. I guess would be nice idea to add at least XYUV there now.
I can add rest of the formats with a separate patch afterwards.
>
> Also, shouldn't plane_color_ctl_alpha() be updated?
I guess not, as we don't support alpha in that case.
>
> > >
> > > Signed-off-by: Stanislav Lisovskiy > > >
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 8
> > > drivers/gpu/drm/i915/intel_sprite.c | 1 +
> > > 2 files changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 30fdfd1a3037..3c96fa3a2b61 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> > > DRM_FORMAT_YVYU,
> > > DRM_FORMAT_UYVY,
> > > DRM_FORMAT_VYUY,
> > > + DRM_FORMAT_XYUV,
> > > };
> > >
> > > static const uint32_t skl_pri_planar_formats[] = {
> > > @@ -102,6 +103,7 @@ static const uint32_t
> > > skl_pri_planar_formats[]
> > > = {
> > > DRM_FORMAT_UYVY,
> > > DRM_FORMAT_VYUY,
> > > DRM_FORMAT_NV12,
> > > + DRM_FORMAT_XYUV,
> >
> > I would keep the NV12 at the end so that the arrays are easier to
> > compare visually.
> >
> > > };
> > >
> > > static const uint64_t skl_format_modifiers_noccs[] = {
> > > @@ -3501,6 +3503,8 @@ static u32 skl_plane_ctl_format(uint32_t
> > > pixel_format)
> > > return PLANE_CTL_FORMAT_XRGB_2101010;
> > > case DRM_FORMAT_XBGR2101010:
> > > return PLANE_CTL_ORDER_RGBX |
> > > PLANE_CTL_FORMAT_XRGB_2101010;
> > > + case DRM_FORMAT_XYUV:
> > > + return PLANE_CTL_FORMAT_AYUV;
> >
> > We should probably rename that define to XYUV as well since it
> > doesn't
> > support per-pixel alpha.
> >
> > Since you've only implemented this for skl+ you chould mention that
> > in the commit msg. IVB+ support should be equally trivial to
> > implement (wink wink).
> >
> > > case DRM_FORMAT_YUYV:
> > > return PLANE_CTL_FORMAT_YUV422 |
> > > PLANE_CTL_YUV422_YUYV;
> > > case DRM_FORMAT_YVYU:
> > > @@ -4959,6 +4963,7 @@ static int skl_update_scaler_plane(struct
> > > intel_crtc_state *crtc_state,
> > > case DRM_FORMAT_UYVY:
> > > case DRM_FORMAT_VYUY:
> > > case DRM_FORMAT_NV12:
> > > + case DRM_FORMAT_XYUV:
> > > break;
> > > default:
> > > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported
> > > scaling format 0x%x\n",
> > > @@ -13399,6 +13404,7 @@ static bool
> > > skl_plane_format_mod_supported(struct drm_plane *_plane,
> > > }
> > >
> > > switch (format) {
> > > +
> >
> > Bogus whitespace.
> >
> > > case DRM_FORMAT_XRGB:
> > > case DRM_FORMAT_XBGR:
> > > case DRM_FORMAT_ARGB:
> > > @@ -13414,6 +13420,7 @@ static bool
> > > skl_plane_format_mod_supported(struct drm_plane *_plane,
> > > case DRM_FORMAT_UYVY:
> > > case DRM_FORMAT_VYUY:
> > > case DRM_FORMAT_NV12:
> > > + case DRM_FORMAT_XYUV:
> > > if (modifier == I915_FORMAT_MOD_Yf_TILED)
> > > return true;
> > > /* fall through */
> > > @@ -14540,6 +14547,7 @@ static int intel_framebuffer_init(struct
> > > intel_framebuffer *intel_fb,
> > > goto err;
> > > }
> > > break;
> > > + case DRM_FORMAT_XYUV:
> >
> > That's not the right spot if we want the platform checks to match
> > your
> > choice of skl+.
> >
> > > case DRM_FORMAT_YUYV:
> > > case DRM_FORMAT_UYVY:
> > > case DRM_FORMAT_YVYU:
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > index c286dda625e4..2ac9471974c2 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -1420,6 +1420,7 @@ static bool
> > > skl_plane_format_mod_supported(struct drm_plane *_plane,
> > > case DRM_FORMAT_UYVY:
> > > case DRM_FORMAT_VYUY:
> > > case DRM_FORMAT_NV12:
> > > + case DRM_FORMAT_XYUV:
> > > if (modifier == I915_FORMAT_MOD_Yf_TILED)
> > > return true;
> > > /* fall through */
> > > --
> > > 2.17.0
> > >
> > > __
[Intel-gfx] [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
(Sharma, Swati2) Rename glk format table to follow similar style as on skl.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 24 +++-
drivers/gpu/drm/i915/intel_sprite.c | 26 --
2 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 43efeb4..1a67340 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t glk_pri_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ intel_primary_formats = glk_pri_planar_formats;
+ num_formats = ARRAY_SIZE(glk_pri_planar_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY))
{
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 1f1276f..3270fab 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1294,6 +1294,22 @@ static uint32_t skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static uint32_t glk_planar_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1551,8 +1567,14 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
if (skl_plane_has_planar(dev_priv, pipe,
PLANE_SPRITE0 + plane)) {
- plane_formats = skl_planar_formats;
- num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ IS_GEMINILAKE(dev_priv)) {
+ plane_formats = glk_planar_formats;
+ num_plane_formats =
ARRAY_SIZE(glk_planar_formats);
+ } else {
+ plane_formats = skl_planar_formats;
+ num_plane_formats =
ARRAY_SIZE(skl_planar_formats);
+ }
} else {
plane_formats = skl_plane_formats;
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
--
2.7.4
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[Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
(Sharma, Swati2): removed unnecessary checks, changed debug error message
to be more generic.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +--
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 41 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 +++---
drivers/gpu/drm/i915/intel_sprite.c | 18 +-
6 files changed, 63 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b04952b..ab76b72 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+ is_planar_yuv_format(plane_state->base.fb->format->format))
{
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index fa7df5f..d64d993 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible && is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4bb46f2..43efeb4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct intel_crtc_state
*crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
- DRM_DEBUG_KMS("NV12: src dimensions not met\n");
+ DRM_DEBUG_KMS("planar yuv: src dimensions not met\n");
return -EINVAL;
}
@@ -4959,6 +4970,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
[Intel-gfx] [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f232178..2c959c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6497,8 +6497,11 @@ enum {
#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
#define PLANE_CTL_FORMAT_NV12(1 << 24)
#define PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
+#define PLANE_CTL_FORMAT_P010(3 << 24)
#define PLANE_CTL_FORMAT_XRGB_ (4 << 24)
+#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
+#define PLANE_CTL_FORMAT_P016(7 << 24)
#define PLANE_CTL_FORMAT_AYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
--
2.7.4
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[Intel-gfx] [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..32e07a2 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_P010,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..daaabb1 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -178,6 +178,16 @@ extern "C" {
#define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /*
non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
+ * component xxx msb Y [xxx:16-xxx]
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
subsampled Cr:Cb plane, 10 bit per channel */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
subsampled Cr:Cb plane, 12 bit per channel */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
subsampled Cr:Cb plane, 16 bit per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Reduce context HW ID lifetime (rev2)
== Series Details == Series: drm/i915: Reduce context HW ID lifetime (rev2) URL : https://patchwork.freedesktop.org/series/44134/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Reduce context HW ID lifetime -drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3687:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reduce context HW ID lifetime (rev2)
== Series Details == Series: drm/i915: Reduce context HW ID lifetime (rev2) URL : https://patchwork.freedesktop.org/series/44134/ State : warning == Summary == $ dim checkpatch origin/drm-tip 30bb0eb3b07e drm/i915: Reduce context HW ID lifetime -:50: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #50: FILE: drivers/gpu/drm/i915/i915_drv.h:1865: + struct mutex mutex; total: 0 errors, 0 warnings, 1 checks, 408 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10045 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48936/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10045 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s3:
{fi-byt-clapper}: PASS -> INCOMPLETE (fdo#102657)
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
Possible fixes
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4739 -> Patchwork_10045
CI_DRM_4739: f65e436af74d73b095b211d5294f5d7cd5132882 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10045: 64365db50d03ad7dfaa8925030f86221689dcd18 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
64365db50d03 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
a5ee90564358 drm/i915: Remove debugfs/i915_ppgtt_info
bfea670af8a1 drm/i915: Report the number of closed vma held by each context in
debugfs
79dd8ce719df drm/i915/execlists: Onion unwind for logical_ring_init() failure
40a9057253f1 drm/i915/execlists: Use coherent writes into the context image
618cbd719ea0 drm/i915/execlists: Delay updating ring register state after resume
468ebad7aed4 drm/i915/selftests: Basic stress test for rapid context switching
57c9f668fad0 drm/i915: Missed interrupt simulation is no more, tell the world
463c9506f450 drm/i915/execlists: Avoid kicking priority on the current context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10045/issues.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context
== Series Details == Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context URL : https://patchwork.freedesktop.org/series/48936/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/execlists: Avoid kicking priority on the current context Okay! Commit: drm/i915: Missed interrupt simulation is no more, tell the world Okay! Commit: drm/i915/selftests: Basic stress test for rapid context switching +./include/linux/slab.h:631:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:631:13: warning: call with no type! Commit: drm/i915/execlists: Delay updating ring register state after resume Okay! Commit: drm/i915/execlists: Use coherent writes into the context image -drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3691:16: warning: expression using sizeof(void) Commit: drm/i915/execlists: Onion unwind for logical_ring_init() failure Okay! Commit: drm/i915: Report the number of closed vma held by each context in debugfs Okay! Commit: drm/i915: Remove debugfs/i915_ppgtt_info Okay! Commit: drm/i915/execlists: Assert the queue is non-empty on unsubmitting Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/execlists: Avoid kicking priority on the current context
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
463c9506f450 drm/i915/execlists: Avoid kicking priority on the current context
-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:774:
+ if ( __guc_dequeue(engine))
total: 1 errors, 0 warnings, 0 checks, 103 lines checked
57c9f668fad0 drm/i915: Missed interrupt simulation is no more, tell the world
468ebad7aed4 drm/i915/selftests: Basic stress test for rapid context switching
-:120: WARNING:ALLOC_ARRAY_ARGS: kcalloc uses number as first arg, sizeof is
generally wrong
#120: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:127:
+ ctx = kcalloc(sizeof(*ctx), nctx, GFP_KERNEL);
total: 0 errors, 1 warnings, 0 checks, 203 lines checked
618cbd719ea0 drm/i915/execlists: Delay updating ring register state after resume
-:68: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#68: FILE: drivers/gpu/drm/i915/intel_lrc.c:2822:
+ ce->lrc_reg_state[CTX_RING_HEAD+1] = 0;
^
-:69: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#69: FILE: drivers/gpu/drm/i915/intel_lrc.c:2823:
+ ce->lrc_reg_state[CTX_RING_TAIL+1] = 0;
^
total: 0 errors, 0 warnings, 2 checks, 52 lines checked
40a9057253f1 drm/i915/execlists: Use coherent writes into the context image
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/i915_perf.c:1853:
+ regs = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(dev_priv));
total: 0 errors, 0 warnings, 1 checks, 71 lines checked
79dd8ce719df drm/i915/execlists: Onion unwind for logical_ring_init() failure
bfea670af8a1 drm/i915: Report the number of closed vma held by each context in
debugfs
-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/i915/i915_debugfs.c:350:
+ seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \
total: 0 errors, 1 warnings, 0 checks, 169 lines checked
a5ee90564358 drm/i915: Remove debugfs/i915_ppgtt_info
64365db50d03 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#9:
<0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset:
engine_mask=1, ret=0, retry=0
total: 0 errors, 1 warnings, 0 checks, 7 lines checked
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/selftests: Add a simple exerciser for suspend/hibernate
Although we cannot do a full system-level test of suspend/hibernate from
deep with the kernel selftests, we can exercise the GEM subsystem in
isolation and simulate the external effects (such as losing stolen
contents and trashing the register state).
v2: Don't forget to hold rpm
v3: Suspend the GTT mappings, and more rpm!
Signed-off-by: Chris Wilson
Cc: Jakub Bartmiński
Cc: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/selftests/i915_gem.c | 221 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 223 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0453eb42a1a3..7b7bbfe59697 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -6207,4 +6207,5 @@ int i915_gem_object_attach_phys(struct
drm_i915_gem_object *obj, int align)
#include "selftests/huge_pages.c"
#include "selftests/i915_gem_object.c"
#include "selftests/i915_gem_coherency.c"
+#include "selftests/i915_gem.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
new file mode 100644
index ..1dbdc35fdec4
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -0,0 +1,221 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+
+#include "../i915_selftest.h"
+
+#include "mock_context.h"
+#include "igt_flush_test.h"
+
+static int switch_to_context(struct drm_i915_private *i915,
+struct i915_gem_context *ctx)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ intel_runtime_pm_get(i915);
+
+ for_each_engine(engine, i915, id) {
+ struct i915_request *rq;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+ }
+
+ intel_runtime_pm_put(i915);
+
+ return err;
+}
+
+static int pm_prepare(struct drm_i915_private *i915)
+{
+ int err;
+
+ if (i915_gem_suspend(i915)) {
+ pr_err("i915_gem_suspend failed\n");
+ err = -EINVAL;
+ }
+
+ return err;
+}
+
+static void trash_stolen(struct drm_i915_private *i915)
+{
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ const u64 slot = ggtt->error_capture.start;
+ const resource_size_t size = resource_size(&i915->dsm);
+ unsigned long page;
+ u32 prng = 0x12345678;
+
+ for (page = 0; page < size; page += PAGE_SIZE) {
+ const dma_addr_t dma = i915->dsm.start + page;
+ u32 __iomem *s;
+ int x;
+
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+
+ s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
+ for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
+ prng = next_pseudo_random32(prng);
+ iowrite32(prng, &s[x]);
+ }
+ io_mapping_unmap_atomic(s);
+ }
+
+ ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
+}
+
+static void simulate_hibernate(struct drm_i915_private *i915)
+{
+ intel_runtime_pm_get(i915);
+
+ /*
+* As a final sting in the tail, invalidate stolen. Under a real S4,
+* stolen is lost and needs to be refilled on resume. However, under
+* CI we merely do S4-device testing (as full S4 is too unreliable
+* for automated testing across a cluster), so to simulate the effect
+* of stolen being trashed across S4, we trash it ourselves.
+*/
+ trash_stolen(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static void pm_resume(struct drm_i915_private *i915)
+{
+ /*
+* Both suspend and hibernate follow the same wakeup path and assume
+* that runtime-pm just works.
+*/
+ intel_runtime_pm_get(i915);
+
+ intel_engines_sanitize(i915);
+ i915_gem_sanitize(i915);
+ i915_gem_resume(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static void pm_suspend(struct drm_i915_private *i915)
+{
+ intel_runtime_pm_get(i915);
+
+ i915_gem_suspend_gtt_mappings(i915);
+ i915_gem_suspend_late(i915);
+
+ intel_runtime_pm_put(i915);
+}
+
+static int igt_gem_suspend(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ err = -ENOMEM;
+ mutex_lock(&i915->drm.struct_mutex);
+ ctx = live_context(i915, file);
+ if (!IS_ERR(ctx))
+ err = switch_to_context(i915, ct
Re: [Intel-gfx] [PATCH v3] drm/i915: clear error registers after error capture
Quoting Lionel Landwerlin (2018-08-30 12:55:32)
> + if (INTEL_GEN(dev_priv) >= 8) {
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + for_each_engine(engine, dev_priv, id) {
> + I915_WRITE(RING_FAULT_REG(engine),
> + I915_READ(RING_FAULT_REG(engine)) &
> + ~RING_FAULT_VALID);
> + }
> + POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
> + } else if (INTEL_GEN(dev_priv) >= 6) {
> + I915_WRITE(GEN8_RING_FAULT_REG,
> + I915_READ(GEN8_RING_FAULT_REG) &
> ~RING_FAULT_VALID);
> + POSTING_READ(GEN8_RING_FAULT_REG);
> + }
Reversed! gen8 has the single reg, gen6 has one per engine.
-Chris
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: clear error registers after error capture
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
v3: Don't read gen8 register on < gen6 (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++
drivers/gpu/drm/i915/i915_irq.c | 18 +-
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 40c93a37e385..34cca15be926 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2817,6 +2817,8 @@ extern void intel_irq_fini(struct drm_i915_private
*dev_priv);
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
+void i915_clear_error_registers(struct drm_i915_private *dev_priv);
+
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..d9d44639ba26 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2337,7 +2337,7 @@ static bool needs_idle_maps(struct drm_i915_private
*dev_priv)
return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
}
-static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_faults(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -2355,15 +2355,11 @@ static void gen6_check_and_clear_faults(struct
drm_i915_private *dev_priv)
fault & RING_FAULT_GTTSEL_MASK ?
"GGTT" : "PPGTT",
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(RING_FAULT_REG(engine),
- fault & ~RING_FAULT_VALID);
}
}
-
- POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
}
-static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen8_check_faults(struct drm_i915_private *dev_priv)
{
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
@@ -2388,22 +2384,20 @@ static void gen8_check_and_clear_faults(struct
drm_i915_private *dev_priv)
GEN8_RING_FAULT_ENGINE_ID(fault),
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(GEN8_RING_FAULT_REG,
- fault & ~RING_FAULT_VALID);
}
-
- POSTING_READ(GEN8_RING_FAULT_REG);
}
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
{
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
if (INTEL_GEN(dev_priv) >= 8)
- gen8_check_and_clear_faults(dev_priv);
+ gen8_check_faults(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
- gen6_check_and_clear_faults(dev_priv);
+ gen6_check_faults(dev_priv);
else
return;
+
+ i915_clear_error_registers(dev_priv);
}
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..34b8307240df 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3215,7 +3215,7 @@ static void i915_reset_device(struct drm_i915_private
*dev_priv,
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
}
-static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
+void i915_clear_error_registers(struct drm_i915_private *dev_priv)
{
u32 eir;
@@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
drm_i915_private *dev_priv)
I915_WRITE(EMR, I915_READ(EMR) | eir);
I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
}
+
+ if (INTEL_GEN(dev_priv) >= 8) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+ I915_WRITE(RING_FAULT_REG(engine),
+ I915_READ(RING_FAULT_REG(engine)) &
+ ~RING_FAULT_VALID);
+ }
+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
+ POSTING_READ(GEN8_RING_FAULT_REG);
+ }
}
/**
--
2.18.0
___
Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2)
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4738 -> Patchwork_10044 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48906/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10044:
=== IGT changes ===
Possible regressions
{igt@drv_selftest@live_gem}:
fi-whl-u: NOTRUN -> DMESG-WARN
fi-pnv-d510:NOTRUN -> DMESG-WARN
fi-skl-6600u: NOTRUN -> DMESG-WARN
fi-kbl-7560u: NOTRUN -> DMESG-WARN
fi-cfl-s3: NOTRUN -> DMESG-WARN
{fi-skl-iommu}: NOTRUN -> DMESG-WARN
fi-hsw-4770r: NOTRUN -> DMESG-WARN
fi-elk-e7500: NOTRUN -> DMESG-WARN
fi-skl-6700k2: NOTRUN -> DMESG-WARN
{fi-bsw-kefka}: NOTRUN -> DMESG-WARN
fi-skl-6700hq: NOTRUN -> DMESG-WARN
fi-bdw-5557u: NOTRUN -> DMESG-WARN
fi-glk-dsi: NOTRUN -> DMESG-WARN
{fi-cfl-8109u}: NOTRUN -> DMESG-WARN
{fi-byt-clapper}: NOTRUN -> DMESG-WARN
fi-bdw-gvtdvm: NOTRUN -> DMESG-WARN
fi-kbl-7500u: NOTRUN -> DMESG-WARN
fi-cfl-8700k: NOTRUN -> DMESG-WARN
fi-bxt-dsi: NOTRUN -> DMESG-WARN
fi-hsw-4770:NOTRUN -> DMESG-WARN
fi-ivb-3520m: NOTRUN -> DMESG-WARN
fi-skl-6770hq: NOTRUN -> DMESG-WARN
fi-bsw-n3050: NOTRUN -> DMESG-WARN
fi-ilk-650: NOTRUN -> DMESG-WARN
fi-ivb-3770:NOTRUN -> DMESG-WARN
fi-skl-gvtdvm: NOTRUN -> DMESG-WARN
fi-cnl-psr: NOTRUN -> DMESG-WARN
fi-hsw-peppy: NOTRUN -> DMESG-WARN
fi-skl-6260u: NOTRUN -> DMESG-WARN
fi-bxt-j4205: NOTRUN -> DMESG-WARN
fi-byt-n2820: NOTRUN -> DMESG-WARN
fi-kbl-7567u: NOTRUN -> DMESG-WARN
fi-kbl-x1275: NOTRUN -> DMESG-WARN
fi-snb-2600:NOTRUN -> DMESG-WARN
fi-bwr-2160:NOTRUN -> DMESG-WARN
fi-gdg-551: NOTRUN -> DMESG-WARN
fi-glk-j4005: NOTRUN -> DMESG-WARN
{fi-kbl-8809g}: NOTRUN -> DMESG-WARN
{fi-bdw-samus}: NOTRUN -> DMESG-WARN
fi-byt-j1900: NOTRUN -> DMESG-WARN
fi-kbl-r: NOTRUN -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_10044 that come from known issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
{igt@drv_selftest@live_gem}:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#105710, fdo#106679)
fi-kbl-guc: NOTRUN -> DMESG-WARN (fdo#106679)
fi-cfl-guc: NOTRUN -> DMESG-WARN (fdo#106679)
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718)
Possible fixes
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#103191, fdo#107362) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-skl-guc: FAIL (fdo#103191) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
Warnings
{igt@pm_rpm@module-reload}:
fi-bsw-n3050: DMESG-FAIL (fdo#107704) -> DMESG-WARN (fdo#107704)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105710 https://bugs.freedesktop.org/show_bug.cgi?id=105710
fdo#106679 https://bugs.freedesktop.org/show_bug.cgi?id=106679
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107704 https://bugs.freedesktop.org/show_bug.cgi?id=107704
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4738 -> Patchwork_10044
CI_DRM_4738: e1ec819ee824a4ed48f168bea66dba4da464e555 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e
Re: [Intel-gfx] [PATCH v2] drm/i915: clear error registers after error capture
Quoting Lionel Landwerlin (2018-08-30 12:41:42)
> On 30/08/2018 12:23, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2018-08-30 12:15:07)
> >> We need to clear the register in order to get correct value after the
> >> next potential hang.
> >>
> >> v2: Centralize error register clearing in i915_irq.c (Chris)
> >>
> >> Signed-off-by: Lionel Landwerlin
> > Ok, I was thinking of move the code around the files a bit more, but
> > agree with what you've done as being the smallest change possible.
>
>
> If you have a suggestion, I can do a v3.
Basically pulling the fault reg out of i915_gem_gtt.c and everything
into i915_reset.c. And then removing the struct_mutex.
> >> @@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
> >> drm_i915_private *dev_priv)
> >> I915_WRITE(EMR, I915_READ(EMR) | eir);
> >> I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
> >> }
> >> +
> >> + if (INTEL_GEN(dev_priv) < 8) {
> >> + struct intel_engine_cs *engine;
> >> + enum intel_engine_id id;
> >> +
> >> + for_each_engine(engine, dev_priv, id) {
> >> + I915_WRITE(RING_FAULT_REG(engine),
> >> + I915_READ(RING_FAULT_REG(engine)) &
> >> + ~RING_FAULT_VALID);
> >> + }
> >> + POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
> > Memory says this is gen6+, and i915_gpu_error.c has the same opinion.
>
>
> What is? The post read?
The comment below :)
> >> + } else {
> >> + I915_WRITE(GEN8_RING_FAULT_REG,
> >> + I915_READ(GEN8_RING_FAULT_REG) &
> >> ~RING_FAULT_VALID);
> >> + POSTING_READ(GEN8_RING_FAULT_REG);
> >> + }
> > I think you want:
> >
> > if (INTEL_GEN > 8) {
> > ...
> > } else if (INTEL_GEN > 6) {
> > ...
> > } else {
> > /* Are there any fault regs for earlier? */
> > }
> >
> > With that tweak,
>
>
> Thanks, done locally.
Hopefully with >= :)
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: clear error registers after error capture
On 30/08/2018 12:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 12:15:07)
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
Signed-off-by: Lionel Landwerlin
Ok, I was thinking of move the code around the files a bit more, but
agree with what you've done as being the smallest change possible.
If you have a suggestion, I can do a v3.
@@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
drm_i915_private *dev_priv)
I915_WRITE(EMR, I915_READ(EMR) | eir);
I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
}
+
+ if (INTEL_GEN(dev_priv) < 8) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+ I915_WRITE(RING_FAULT_REG(engine),
+ I915_READ(RING_FAULT_REG(engine)) &
+ ~RING_FAULT_VALID);
+ }
+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
Memory says this is gen6+, and i915_gpu_error.c has the same opinion.
What is? The post read?
+ } else {
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
+ POSTING_READ(GEN8_RING_FAULT_REG);
+ }
I think you want:
if (INTEL_GEN > 8) {
...
} else if (INTEL_GEN > 6) {
...
} else {
/* Are there any fault regs for earlier? */
}
With that tweak,
Thanks, done locally.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2)
== Series Details == Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2) URL : https://patchwork.freedesktop.org/series/48906/ State : warning == Summary == $ dim checkpatch origin/drm-tip 87bb0faa6d38 drm/i915/selftests: Add a simple exerciser for suspend/hibernate -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 -:38: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #38: FILE: drivers/gpu/drm/i915/selftests/i915_gem.c:1: +/* total: 0 errors, 2 warnings, 0 checks, 195 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for linux/mei: Header for mei_hdcp driver interface
== Series Details ==
Series: linux/mei: Header for mei_hdcp driver interface
URL : https://patchwork.freedesktop.org/series/48922/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4738 -> Patchwork_10043 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48922/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10043 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128, fdo#107139)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#103191, fdo#107362)
Possible fixes
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#103191, fdo#107362) -> PASS +1
fi-skl-guc: FAIL (fdo#103191) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
Warnings
{igt@pm_rpm@module-reload}:
fi-bsw-n3050: DMESG-FAIL (fdo#107704) -> DMESG-WARN (fdo#107704)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107704 https://bugs.freedesktop.org/show_bug.cgi?id=107704
== Participating hosts (54 -> 48) ==
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-gdg-551
== Build changes ==
* Linux: CI_DRM_4738 -> Patchwork_10043
CI_DRM_4738: e1ec819ee824a4ed48f168bea66dba4da464e555 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10043: 45780f07f9799a53de8cc28b236cb6bdb8e168e8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
45780f07f979 linux/mei: Header for mei_hdcp driver interface
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10043/issues.html
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: clear error registers after error capture
Quoting Lionel Landwerlin (2018-08-30 12:15:07)
> We need to clear the register in order to get correct value after the
> next potential hang.
>
> v2: Centralize error register clearing in i915_irq.c (Chris)
>
> Signed-off-by: Lionel Landwerlin
Ok, I was thinking of move the code around the files a bit more, but
agree with what you've done as being the smallest change possible.
> @@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
> drm_i915_private *dev_priv)
> I915_WRITE(EMR, I915_READ(EMR) | eir);
> I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
> }
> +
> + if (INTEL_GEN(dev_priv) < 8) {
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + for_each_engine(engine, dev_priv, id) {
> + I915_WRITE(RING_FAULT_REG(engine),
> + I915_READ(RING_FAULT_REG(engine)) &
> + ~RING_FAULT_VALID);
> + }
> + POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
Memory says this is gen6+, and i915_gpu_error.c has the same opinion.
> + } else {
> + I915_WRITE(GEN8_RING_FAULT_REG,
> + I915_READ(GEN8_RING_FAULT_REG) &
> ~RING_FAULT_VALID);
> + POSTING_READ(GEN8_RING_FAULT_REG);
> + }
I think you want:
if (INTEL_GEN > 8) {
...
} else if (INTEL_GEN > 6) {
...
} else {
/* Are there any fault regs for earlier? */
}
With that tweak,
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH v2] drm/i915: clear error registers after error capture
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++
drivers/gpu/drm/i915/i915_irq.c | 18 +-
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 40c93a37e385..34cca15be926 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2817,6 +2817,8 @@ extern void intel_irq_fini(struct drm_i915_private
*dev_priv);
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
+void i915_clear_error_registers(struct drm_i915_private *dev_priv);
+
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..d9d44639ba26 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2337,7 +2337,7 @@ static bool needs_idle_maps(struct drm_i915_private
*dev_priv)
return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
}
-static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_faults(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -2355,15 +2355,11 @@ static void gen6_check_and_clear_faults(struct
drm_i915_private *dev_priv)
fault & RING_FAULT_GTTSEL_MASK ?
"GGTT" : "PPGTT",
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(RING_FAULT_REG(engine),
- fault & ~RING_FAULT_VALID);
}
}
-
- POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
}
-static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen8_check_faults(struct drm_i915_private *dev_priv)
{
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
@@ -2388,22 +2384,20 @@ static void gen8_check_and_clear_faults(struct
drm_i915_private *dev_priv)
GEN8_RING_FAULT_ENGINE_ID(fault),
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
- I915_WRITE(GEN8_RING_FAULT_REG,
- fault & ~RING_FAULT_VALID);
}
-
- POSTING_READ(GEN8_RING_FAULT_REG);
}
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
{
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
if (INTEL_GEN(dev_priv) >= 8)
- gen8_check_and_clear_faults(dev_priv);
+ gen8_check_faults(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
- gen6_check_and_clear_faults(dev_priv);
+ gen6_check_faults(dev_priv);
else
return;
+
+ i915_clear_error_registers(dev_priv);
}
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..61a01584eae2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3215,7 +3215,7 @@ static void i915_reset_device(struct drm_i915_private
*dev_priv,
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
}
-static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
+void i915_clear_error_registers(struct drm_i915_private *dev_priv)
{
u32 eir;
@@ -3238,6 +3238,22 @@ static void i915_clear_error_registers(struct
drm_i915_private *dev_priv)
I915_WRITE(EMR, I915_READ(EMR) | eir);
I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
}
+
+ if (INTEL_GEN(dev_priv) < 8) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+ I915_WRITE(RING_FAULT_REG(engine),
+ I915_READ(RING_FAULT_REG(engine)) &
+ ~RING_FAULT_VALID);
+ }
+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+ } else {
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
+ POSTING_READ(GEN8_RING_FAULT_REG);
+ }
}
/**
--
2.18.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for linux/mei: Header for mei_hdcp driver interface
== Series Details == Series: linux/mei: Header for mei_hdcp driver interface URL : https://patchwork.freedesktop.org/series/48922/ State : warning == Summary == $ dim checkpatch origin/drm-tip 45780f07f979 linux/mei: Header for mei_hdcp driver interface -:22: WARNING:TYPO_SPELLING: 'uneeded' may be misspelled - perhaps 'unneeded'? #22: Remove uneeded include to mei_cl_bus.h -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 77 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: clear error registers after error capture
On 30/08/2018 11:55, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-08-30 11:52:28) We need to clear the register in order to get correct value after the next potential hang. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index afd70deae7ef..1cc9cde41328 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1768,6 +1768,8 @@ static int capture(void *data) error->epoch = capture_find_epoch(error); + i915_check_and_clear_faults(error->i915); We already have i915_clear_error_registers() high up in the caller. I'd like to pull i915_check_and_clear_faults() into i915_clear_error_registers, and so also clear the error regs on take over like we do for faults. -Chris Thanks, sure. - Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Add a simple exerciser for suspend/hibernate
Quoting Bartminski, Jakub (2018-08-30 11:47:21)
> On Thu, 2018-08-30 at 10:52 +0100, Chris Wilson wrote:
>
> > +static int igt_gem_suspend(void *arg)
> [...]
> > + if (i915_gem_suspend(i915)) {
> > + pr_err("i915_gem_suspend failed\n");
> > + err = -EINVAL;
> > + goto out;
> > + }
> > +
> > + i915_gem_suspend_late(i915);
>
> Shouldn't we also do i915_gem_suspend_gtt_mappings after
> i915_gem_suspend (usually it's in drm_suspend, which is called by both
> pm_suspend and pm_freeze)? It's later restored in i915_gem_resume.
Possibly, I didn't recall it as being that important. Still, the more
the merrier.
> > +static int igt_gem_hibernate(void *arg)
>
> Most of this function is same as igt_gem_suspend and that is probably
> not going to change since both suspend and hibernation normally go
> through pm_prepare and pm_resume_early/resume, maybe some prepare and
> resume helpers for readability?
You were meant to jump and say, hmm, I'm going to add a few more cases
here with different GPU loads and will need to parameterise the
functions... I was ok with the duplication for now as I expect these to
serve as a base for more tests to come. It was more important for me to
give you a test case that blows up if you remove i915->gt.resume() :)
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: clear error registers after error capture
Quoting Lionel Landwerlin (2018-08-30 11:52:28) > We need to clear the register in order to get correct value after the > next potential hang. > > Signed-off-by: Lionel Landwerlin > --- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > b/drivers/gpu/drm/i915/i915_gpu_error.c > index afd70deae7ef..1cc9cde41328 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1768,6 +1768,8 @@ static int capture(void *data) > > error->epoch = capture_find_epoch(error); > > + i915_check_and_clear_faults(error->i915); We already have i915_clear_error_registers() high up in the caller. I'd like to pull i915_check_and_clear_faults() into i915_clear_error_registers, and so also clear the error regs on take over like we do for faults. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: clear error registers after error capture
We need to clear the register in order to get correct value after the next potential hang. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index afd70deae7ef..1cc9cde41328 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1768,6 +1768,8 @@ static int capture(void *data) error->epoch = capture_find_epoch(error); + i915_check_and_clear_faults(error->i915); + return 0; } -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Add a simple exerciser for suspend/hibernate
On Thu, 2018-08-30 at 10:52 +0100, Chris Wilson wrote:
> +static int igt_gem_suspend(void *arg)
[...]
> + if (i915_gem_suspend(i915)) {
> + pr_err("i915_gem_suspend failed\n");
> + err = -EINVAL;
> + goto out;
> + }
> +
> + i915_gem_suspend_late(i915);
Shouldn't we also do i915_gem_suspend_gtt_mappings after
i915_gem_suspend (usually it's in drm_suspend, which is called by both
pm_suspend and pm_freeze)? It's later restored in i915_gem_resume.
> +static int igt_gem_hibernate(void *arg)
Most of this function is same as igt_gem_suspend and that is probably
not going to change since both suspend and hibernation normally go
through pm_prepare and pm_resume_early/resume, maybe some prepare and
resume helpers for readability?
- Jakub
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Re: [Intel-gfx] [PATCH i-g-t] lib/sysfs: Avoid using FILE* temporary for igt_sysfs_[v]printf
On Thu, Aug 30, 2018 at 09:44:33AM +0100, Chris Wilson wrote:
> Currently we wrap our fd inside a FILE* stream to make use of vfprintf,
> but the man page leaves the question of errno and signal handling in
> doubt. It is documented as returning a negative value and setting
> ferror(), but we have been interpreting errno to handle signal
> restarting. As that is in doubt, reduce it to a sprintf and reuse our
> common interrupt handling write() that already returns -errno.
>
> Signed-off-by: Chris Wilson
> Cc: Katarzyna Dec
> ---
> lib/igt_sysfs.c | 37 ++---
> 1 file changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
> index 8efe889be..b39da4c2a 100644
> --- a/lib/igt_sysfs.c
> +++ b/lib/igt_sysfs.c
> @@ -387,22 +387,37 @@ int igt_sysfs_scanf(int dir, const char *attr, const
> char *fmt, ...)
>
> int igt_sysfs_vprintf(int dir, const char *attr, const char *fmt, va_list ap)
> {
> - FILE *file;
> - int fd;
> - int ret = -1;
> + char stack[128], *buf = stack;
> + va_list tmp;
> + int ret, fd;
>
> fd = openat(dir, attr, O_WRONLY);
> if (fd < 0)
> - return -1;
> + return -errno;
>
> - file = fdopen(fd, "w");
> - if (file) {
> - do {
> - ret = vfprintf(file, fmt, ap);
> - } while (ret == -1 && errno == EINTR);
> - fclose(file);
> + va_copy(tmp, ap);
> + ret = vsnprintf(buf, sizeof(stack), fmt, tmp);
> + va_end(tmp);
> + if (ret < 0)
> + return -EINVAL;
> +
> + if (ret > sizeof(stack)) {
> + int len = ret + 1;
> +
> + buf = malloc(len);
> + if (!buf)
> + return -ENOMEM;
> +
> + ret = vsnprintf(buf, ret, fmt, ap);
> + if (ret > len) {
> + free(buf);
> + return -EINVAL;
> + }
> }
> - close(fd);
> +
> + ret = writeN(fd, buf, ret);
> + if (buf != stack)
> + free(buf);
>
> return ret;
> }
It looks like my issue with returning error from igt_sysfs_printf is solved.
Reviewed-by: Katarzyna Dec
Thanks!
Kasia :)
> --
> 2.19.0.rc1
>
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[Intel-gfx] [PATCH] drm/i915: Reduce context HW ID lifetime
Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a constant ID).
This means that instead of a max of 2k allocated contexts (worst case
before fun with bit twiddling), we instead have a limit of 2k in flight
contexts (minus a few that have been pinned by the kernel or by perf).
We cannot reduce the scope of an HW-ID to an engine (allowing the same
gem_context to have different ids on each engine) as in the future we
will need to preassign an id before we know which engine the
context is being executed on.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem_context.c | 207 +-
drivers/gpu/drm/i915/i915_gem_context.h | 17 ++
drivers/gpu/drm/i915/intel_lrc.c | 8 +
drivers/gpu/drm/i915/selftests/mock_context.c | 11 +-
6 files changed, 181 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a5265c236a33..bf3b6c6db51d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1953,7 +1953,10 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return ret;
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
- seq_printf(m, "HW context %u ", ctx->hw_id);
+ seq_puts(m, "HW context ");
+ if (!list_empty(&ctx->hw_id_link))
+ seq_printf(m, "%x [pin %u]",
+ ctx->hw_id, atomic_read(&ctx->pin_hw_id));
if (ctx->pid) {
struct task_struct *task;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..ca6b55d29d6a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1862,6 +1862,7 @@ struct drm_i915_private {
struct mutex av_mutex;
struct {
+ struct mutex mutex;
struct list_head list;
struct llist_head free_list;
struct work_struct free_work;
@@ -1874,6 +1875,7 @@ struct drm_i915_private {
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+ struct list_head hw_id_list;
} contexts;
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..d3390942f37b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -115,6 +115,85 @@ static void lut_close(struct i915_gem_context *ctx)
rcu_read_unlock();
}
+static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
+{
+ unsigned int max;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ if (INTEL_GEN(i915) >= 11)
+ max = GEN11_MAX_CONTEXT_HW_ID;
+ else if (USES_GUC_SUBMISSION(i915))
+ /*
+* When using GuC in proxy submission, GuC consumes the
+* highest bit in the context id to indicate proxy submission.
+*/
+ max = MAX_GUC_CONTEXT_HW_ID;
+ else
+ max = MAX_CONTEXT_HW_ID;
+
+ return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
+}
+
+static int steal_hw_id(struct drm_i915_private *i915)
+{
+ struct i915_gem_context *ctx, *cn;
+ LIST_HEAD(pinned);
+ int id = -ENOSPC;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ list_for_each_entry_safe(ctx, cn,
+&i915->contexts.hw_id_list, hw_id_link) {
+ if (atomic_read(&ctx->pin_hw_id)) {
+ list_move_tail(&ctx->hw_id_link, &pinned);
+ continue;
+ }
+
+ GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
+ list_del_init(&ctx->hw_id_link);
+ id = ctx->hw_id;
+ break;
+ }
+
+ list_splice_tail(&pinned, &i915->contexts.hw_id_list);
+ return id;
+}
+
+static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
+{
+ int ret;
+
+ lockdep_assert_held(&i915->contexts.mutex);
+
+ ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
+ if (unlikely(ret < 0)) {
+ ret = steal_hw_id(i915);
+ if (ret < 0) /* once again for the correct erro code */
+ ret = new_hw_id(i915, GFP_KERNEL);
+ i
[Intel-gfx] [PATCH 5/9] drm/i915/execlists: Use coherent writes into the context image
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.
v2: With extra enthusiasm.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/i915_perf.c| 3 ++-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c| 8 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
6 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..b6eea715d506 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3070,6 +3070,12 @@ enum i915_map_type {
I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
};
+static inline enum i915_map_type
+i915_coherent_map_type(struct drm_i915_private *i915)
+{
+ return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
+}
+
/**
* i915_gem_object_pin_map - return a contiguous mapping of the entire object
* @obj: the object to map into kernel address space
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0453eb42a1a3..71832e2c85ad 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5404,6 +5404,8 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
for_each_engine(engine, i915, id) {
struct i915_vma *state;
+ GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);
+
state = to_intel_context(ctx, engine)->state;
if (!state)
continue;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0376338d1f8d..d2ba7a641866 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1849,7 +1849,8 @@ static int gen8_configure_all_contexts(struct
drm_i915_private *dev_priv,
if (!ce->state)
continue;
- regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
+ regs = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(dev_priv));
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto out;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a34e8ff82d5..4765c0a69f6a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1157,7 +1157,7 @@ void intel_engines_unpark(struct drm_i915_private *i915)
map = NULL;
if (engine->default_state)
map = i915_gem_object_pin_map(engine->default_state,
- I915_MAP_WB);
+ I915_MAP_FORCE_WB);
if (!IS_ERR_OR_NULL(map))
engine->pinned_default_state = map;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2c37ee7ca276..a617be14f044 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1311,7 +1311,7 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
* on an active context (which by nature is already on the GPU).
*/
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
- err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ err = i915_gem_object_set_to_wc_domain(vma->obj, true);
if (err)
return err;
}
@@ -1339,7 +1339,9 @@ __execlists_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
- vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(ctx->i915) |
+ I915_MAP_OVERRIDE);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
goto unpin_vma;
@@ -2701,7 +2703,7 @@ populate_lr_context(struct i915_gem_context *ctx,
void *defaults;
defaults = i915_gem_object_pin_map(engine->default_state,
- I915_MAP_WB);
+ I915_MAP_FORCE_WB);
if (IS_ERR(defaults)) {
ret = PTR_ERR(defaults);
goto err_unpin_ctx;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d40f55a8dc34..3d82f6b5c229 100644
--- a/drivers/gpu/drm/
[Intel-gfx] [PATCH 8/9] drm/i915: Remove debugfs/i915_ppgtt_info
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 119
1 file changed, 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4a1928a97775..8328165dc095 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2034,124 +2034,6 @@ static int i915_swizzle_info(struct seq_file *m, void
*data)
return 0;
}
-static int per_file_ctx(int id, void *ptr, void *data)
-{
- struct i915_gem_context *ctx = ptr;
- struct seq_file *m = data;
- struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
-
- if (!ppgtt) {
- seq_printf(m, " no ppgtt for context %d\n",
- ctx->user_handle);
- return 0;
- }
-
- if (i915_gem_context_is_default(ctx))
- seq_puts(m, " default context:\n");
- else
- seq_printf(m, " context %d:\n", ctx->user_handle);
- ppgtt->debug_dump(ppgtt, m);
-
- return 0;
-}
-
-static void gen8_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int i;
-
- if (!ppgtt)
- return;
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- for (i = 0; i < 4; i++) {
- u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
- pdp <<= 32;
- pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
- seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
- }
- }
-}
-
-static void gen6_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (IS_GEN6(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- if (IS_GEN7(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n",
- I915_READ(RING_MODE_GEN7(engine)));
- seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE(engine)));
- seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE_READ(engine)));
- seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
- I915_READ(RING_PP_DIR_DCLV(engine)));
- }
- if (dev_priv->mm.aliasing_ppgtt) {
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-
- seq_puts(m, "aliasing PPGTT:\n");
- seq_printf(m, "pd gtt offset: 0x%08x\n",
ppgtt->pd.base.ggtt_offset);
-
- ppgtt->debug_dump(ppgtt, m);
- }
-
- seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
-}
-
-static int i915_ppgtt_info(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = &dev_priv->drm;
- struct drm_file *file;
- int ret;
-
- mutex_lock(&dev->filelist_mutex);
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- goto out_unlock;
-
- intel_runtime_pm_get(dev_priv);
-
- if (INTEL_GEN(dev_priv) >= 8)
- gen8_ppgtt_info(m, dev_priv);
- else if (INTEL_GEN(dev_priv) >= 6)
- gen6_ppgtt_info(m, dev_priv);
-
- list_for_each_entry_reverse(file, &dev->filelist, lhead) {
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct task_struct *task;
-
- task = get_pid_task(file->pid, PIDTYPE_PID);
- if (!task) {
- ret = -ESRCH;
- goto out_rpm;
- }
- seq_printf(m, "\nproc: %s\n", task->comm);
- put_task_struct(task);
- idr_for_each(&file_priv->context_idr, per_file_ctx,
-(void *)(unsigned long)m);
- }
-
-out_rpm:
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev->struct_mutex);
-out_unlock:
- mutex_unlock(&dev->filelist_mutex);
- return ret;
-}
-
static int count_irq_waiters(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
@@ -4720,7 +4602,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_context_status", i915_context_status, 0},
{"
[Intel-gfx] [PATCH 9/9] drm/i915/execlists: Assert the queue is non-empty on unsubmitting
In the sequence <0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset: engine_mask=1, ret=0, retry=0 <0>[ 531.960431] drv_self-48067 527402571us : execlists_reset: rcs0 request global=115de, current=71133 <0>[ 531.960431] drv_self-48067d..1 527402571us : execlists_cancel_port_requests: rcs0:port0 global=71134 (fence 826b:198), (current 71133) <0>[ 531.960431] drv_self-48067d..1 527402572us : execlists_cancel_port_requests: rcs0:port1 global=71135 (fence 826c:53), (current 71133) <0>[ 531.960431] drv_self-48067d..1 527402572us : __i915_request_unsubmit: rcs0 fence 826c:53 <- global=71135, current 71133 <0>[ 531.960431] drv_self-48067d..1 527402579us : __i915_request_unsubmit: rcs0 fence 826b:198 <- global=71134, current 71133 <0>[ 531.960431] drv_self-48067 527402613us : intel_engine_cancel_stop_cs: rcs0 <0>[ 531.960431] drv_self-48067 527402624us : execlists_reset_finish: rcs0 we are missing the execlists_submission_tasklet() invocation before the execlists_reset_fini() implying that either the queue is empty, or we failed to schedule and run the tasklet on finish. Add an assert so we are sure that on unsubmitting the incomplete request after reset, the queue is indeed populated. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3bb871730e26..834520dbe4e8 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -344,6 +344,7 @@ static void __unwind_incomplete_requests(struct intel_engine_cs *engine) last_prio = rq_prio(rq); p = lookup_priolist(engine, last_prio); } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(p->priority != rq_prio(rq)); list_add(&rq->sched.link, &p->requests); -- 2.19.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
