[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/2] drm: Add connector property to limit max bpc
== Series Details == Series: series starting with [v5,1/2] drm: Add connector property to limit max bpc URL : https://patchwork.freedesktop.org/series/49230/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4775_full -> Patchwork_10102_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10102_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> FAIL (fdo#106886) igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) Possible fixes igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4775 -> Patchwork_10102 CI_DRM_4775: 1a2bb6c061217718b972b3f4a74b96b61cf19d0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10102: 44f00038f50883e84572b1f94e54ea272d478557 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10102/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Decode memdev info and bandwidth and implemnt latency WA (rev4)
On Fri, Aug 31, 2018 at 11:22:01AM -, Patchwork wrote: > == Series Details == > > Series: Decode memdev info and bandwidth and implemnt latency WA (rev4) > URL : https://patchwork.freedesktop.org/series/46481/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 441057f30f45 drm/i915/bxt: Decode memory bandwidth and parameters > -:162: CHECK:BOOL_MEMBER: Avoid using bool structure members because of > possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 I'm still asking myself how to proceed with this one here. We clearly have many more cases of bool structure members on i915. > #162: FILE: drivers/gpu/drm/i915/i915_drv.h:1948: > + bool valid; > > total: 0 errors, 0 warnings, 1 checks, 182 lines checked > bc3e164750dd drm/i915/skl+: Decode memory bandwidth and parameters > 08094101d869 drm/i915: Implement 16GB dimm wa for latency level-0 > -:116: CHECK:BOOL_MEMBER: Avoid using bool structure members because of > possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 > #116: FILE: drivers/gpu/drm/i915/i915_drv.h:1949: > + bool valid_dimm; > > -:117: CHECK:BOOL_MEMBER: Avoid using bool structure members because of > possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 > #117: FILE: drivers/gpu/drm/i915/i915_drv.h:1950: > + bool is_16gb_dimm; > > -:125: CHECK:BOOL_MEMBER: Avoid using bool structure members because of > possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 > #125: FILE: drivers/gpu/drm/i915/i915_drv.h:2179: > + bool is_16gb_dimm; > > total: 0 errors, 0 warnings, 3 checks, 107 lines checked > 9968070f860e drm/i915/skl+: don't trust IPC value set by BIOS > 268a50bd35d9 drm/i915/kbl+: Enable IPC only for symmetric memory > configurations > -:82: CHECK:BOOL_MEMBER: Avoid using bool structure members because of > possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 > #82: FILE: drivers/gpu/drm/i915/i915_drv.h:1958: > + bool symmetric_memory; > > total: 0 errors, 0 warnings, 1 checks, 67 lines checked > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/amdgpu: Remove default best_encoder hook from DC (rev2)
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC (rev2) URL : https://patchwork.freedesktop.org/series/49194/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4773_full -> Patchwork_10100_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10100_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10100_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10100_full: === IGT changes === Possible regressions igt@gem_eio@in-flight-1us: shard-glk: PASS -> FAIL == Known issues == Here are the changes found in Patchwork_10100_full that come from known issues: === IGT changes === Issues hit igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_suspend@shrink: shard-glk: FAIL (fdo#106886) -> PASS igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#102887, fdo#105363) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10100 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10100: 8405889a997b3d86b7453a7f4b0c7e2f2813af8b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10100/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/7] drm: Add drm/drm_util.h header file (rev2)
== Series Details == Series: series starting with [1/7] drm: Add drm/drm_util.h header file (rev2) URL : https://patchwork.freedesktop.org/series/49184/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4773_full -> Patchwork_10099_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10099_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_await@wide-contexts: shard-glk: PASS -> FAIL (fdo#105900) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@drv_suspend@shrink: shard-glk: FAIL (fdo#106886) -> PASS igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#102887, fdo#105363) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10099 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10099: 4ec94773c5515f4e52c5b4e584eb05c3bee69df0 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10099/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/intel_csr.c Added ICL Stepping info. (rev2)
== Series Details == Series: drm/i915/intel_csr.c Added ICL Stepping info. (rev2) URL : https://patchwork.freedesktop.org/series/49058/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4773_full -> Patchwork_10098_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10098_full that come from known issues: === IGT changes === Issues hit igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_suspend@shrink: shard-glk: FAIL (fdo#106886) -> PASS igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10098 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10098: 647b1f427344d72cfa29857edb4c3b89842c607d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10098/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/5] lib/igt_fb: Call dumb_destroy ioctl in case of dumb buffers
vmwgfx does not support GEM interface so calling gem_close on vmwgfx
results in error. Call dumb destroy IOCTL in case have dumb buffer.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 5 -
lib/igt_kms.c | 15 +++
lib/igt_kms.h | 1 +
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index ae71d967..ba995a1a 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1920,7 +1920,10 @@ void igt_remove_fb(int fd, struct igt_fb *fb)
cairo_surface_destroy(fb->cairo_surface);
do_or_die(drmModeRmFB(fd, fb->fb_id));
- gem_close(fd, fb->gem_handle);
+ if (fb->is_dumb)
+ kmstest_dumb_destroy(fd, fb->gem_handle);
+ else
+ gem_close(fd, fb->gem_handle);
fb->fb_id = 0;
}
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 62d84684..9e9414cf 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -639,6 +639,21 @@ void *kmstest_dumb_map_buffer(int fd, uint32_t handle,
uint64_t size,
return ptr;
}
+/**
+ * kmstest_dumb_destroy:
+ * @fd: Opened drm file descriptor
+ * @handle: Offset in the file referred to by fd
+ */
+void kmstest_dumb_destroy(int fd, uint32_t handle)
+{
+ struct drm_mode_destroy_dumb arg = {};
+
+ igt_assert_neq(handle, 0);
+
+ arg.handle = handle;
+ do_ioctl(fd, DRM_IOCTL_MODE_DESTROY_DUMB, );
+}
+
/*
* Returns: the previous mode, or KD_GRAPHICS if no /dev/tty0 was
* found and nothing was done.
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 3a12f278..bd0c0f09 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -222,6 +222,7 @@ uint32_t kmstest_dumb_create(int fd, int width, int height,
int bpp,
void *kmstest_dumb_map_buffer(int fd, uint32_t handle, uint64_t size,
unsigned prot);
+void kmstest_dumb_destroy(int fd, uint32_t handle);
void kmstest_wait_for_pageflip(int fd);
unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags);
void igt_assert_plane_visible(int fd, enum pipe pipe, bool visibility);
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 5/5] tests/kms_atomic: Add a new test case for FB_DAMAGE_CLIPS plane property
Some simple test cases to use FB_DAMAGE_CLIPS plane property.
Signed-off-by: Deepak Rawat
Cc: dri-de...@lists.freedesktop.org
Cc: Daniel Vetter
Cc: Lukasz Spintzyk
Cc: Rob Clark
Cc: Daniel Stone
Cc: Noralf Trønnes
Cc: Dave Airlie
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
tests/kms_atomic.c | 260 +
3 files changed, 262 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 9e9414cf..46cd50e1 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -175,6 +175,7 @@ const char * const
igt_plane_prop_names[IGT_NUM_PLANE_PROPS] = {
[IGT_PLANE_IN_FORMATS] = "IN_FORMATS",
[IGT_PLANE_COLOR_ENCODING] = "COLOR_ENCODING",
[IGT_PLANE_COLOR_RANGE] = "COLOR_RANGE",
+ [IGT_PLANE_FB_DAMAGE_CLIPS] = "FB_DAMAGE_CLIPS",
};
const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index bd0c0f09..893b7cf5 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -267,6 +267,7 @@ enum igt_atomic_plane_properties {
IGT_PLANE_IN_FORMATS,
IGT_PLANE_COLOR_ENCODING,
IGT_PLANE_COLOR_RANGE,
+ IGT_PLANE_FB_DAMAGE_CLIPS,
IGT_NUM_PLANE_PROPS
};
diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index 72714e12..4abc0ad5 100644
--- a/tests/kms_atomic.c
+++ b/tests/kms_atomic.c
@@ -56,6 +56,24 @@
IGT_TEST_DESCRIPTION("Test atomic modesetting API");
+/* signed32 drm_mode_rect declared here for use with drm damage for page-flip
*/
+struct damage_rect {
+ int x1;
+ int y1;
+ int x2;
+ int y2;
+};
+
+static inline int damage_rect_width(struct damage_rect *r)
+{
+ return r->x2 - r->x1;
+}
+
+static inline int damage_rect_height(struct damage_rect *r)
+{
+ return r->y2 - r->y1;
+}
+
enum kms_atomic_check_relax {
ATOMIC_RELAX_NONE = 0,
CRTC_RELAX_MODE = (1 << 0),
@@ -840,6 +858,240 @@ static void atomic_invalid_params(igt_pipe_t *pipe,
do_ioctl_err(display->drm_fd, DRM_IOCTL_MODE_ATOMIC, , EFAULT);
}
+static void atomic_plane_damage(igt_pipe_t *pipe, igt_plane_t *plane, struct
igt_fb *fb)
+{
+ struct damage_rect *damage;
+ struct igt_fb fb_1;
+ struct igt_fb fb_2;
+ cairo_t *cr_1;
+ cairo_t *cr_2;
+
+ damage = malloc(sizeof(*damage) * 2);
+ igt_assert(damage);
+
+ /* Color fb with white rect at center */
+ igt_create_color_fb(pipe->display->drm_fd, fb->width, fb->height,
+ fb->drm_format, I915_TILING_NONE, 0.2, 0.2, 0.2,
+ _1);
+ cr_1 = igt_get_cairo_ctx(pipe->display->drm_fd, _1);
+ igt_paint_color(cr_1, fb->width/4, fb->height/4, fb->width/2,
+ fb->height/2, 1.0, 1.0, 1.0);
+ igt_put_cairo_ctx(pipe->display->drm_fd, _1, cr_1);
+
+ /*
+* Flip the primary plane to new color fb using atomic API and check the
+* state.
+*/
+ igt_plane_set_fb(plane, _1);
+ crtc_commit(pipe, plane, COMMIT_ATOMIC, ATOMIC_RELAX_NONE);
+
+ /*
+* Change the color of top left clip from center and issue plane update
+* with damage and verify the state.
+*/
+ damage[0].x1 = 0;
+ damage[0].y1 = 0;
+ damage[0].x2 = fb->width/2;
+ damage[0].y2 = fb->height/2;
+
+ cr_1 = igt_get_cairo_ctx(pipe->display->drm_fd, _1);
+ igt_paint_color(cr_1, damage[0].x1, damage[0].y1,
+ damage_rect_width([0]),
+ damage_rect_height([0]), 1.0, 0, 0);
+ igt_put_cairo_ctx(pipe->display->drm_fd, _1, cr_1);
+
+ igt_plane_set_fb(plane, _1);
+ igt_plane_replace_prop_blob(plane, IGT_PLANE_FB_DAMAGE_CLIPS, damage,
+ sizeof(*damage));
+ crtc_commit(pipe, plane, COMMIT_ATOMIC, ATOMIC_RELAX_NONE);
+
+ /*
+* Change the color of top left and bottom right clip from center and
+* issue plane update with damage and verify the state.
+*/
+ damage[0].x1 = 0;
+ damage[0].y1 = 0;
+ damage[0].x2 = fb->width/2;
+ damage[0].y2 = fb->height/2;
+
+ damage[1].x1 = fb->width/2;
+ damage[1].y1 = fb->height/2;
+ damage[1].x2 = fb->width;
+ damage[1].y2 = fb->height;
+
+ cr_1 = igt_get_cairo_ctx(pipe->display->drm_fd, _1);
+ igt_paint_color(cr_1, damage[0].x1, damage[0].y1,
+ damage_rect_width([0]),
+ damage_rect_height([0]), 1.0, 0, 1.0);
+ igt_paint_color(cr_1, damage[1].x1, damage[1].y1,
+ damage_rect_width([1]),
+ damage_rect_height([1]), 0, 0, 1.0);
+ igt_put_cairo_ctx(pipe->display->drm_fd, _1, cr_1);
+
+ igt_plane_set_fb(plane, _1);
+ igt_plane_replace_prop_blob(plane, IGT_PLANE_FB_DAMAGE_CLIPS, damage,
+ sizeof(*damage) * 2);
+ crtc_commit(pipe, plane, COMMIT_ATOMIC,
[Intel-gfx] [PATCH i-g-t 0/5] vmwgfx as a new driver for igt-gpu-tools
Hi, With this patch series adding vmwgfx as new driver for igt-gpu-tools and some changes to make kms_atomic test case work for vmwgfx. For now the main motivation for this was page-flip with damage test case to test the new plane property FB_DAMAGE_CLIPS. However, will be adding more vmwgfx specific tests in future. Thanks, Deepak Deepak Rawat (5): lib/igt_vmwgfx: Add vmwgfx device lib/igt_fb: Call dumb_destroy ioctl in case of dumb buffers tests/kms: Don't check crtc state for vmwgfx legacy set_crtc lib/igt_fb: Check for stride before creating cairo surface tests/kms_atomic: Add a new test case for FB_DAMAGE_CLIPS plane property lib/drmtest.c | 9 +- lib/drmtest.h | 3 + lib/igt_fb.c | 8 +- lib/igt_kms.c | 16 +++ lib/igt_kms.h | 2 + tests/kms_atomic.c | 267 - 6 files changed, 302 insertions(+), 3 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/5] lib/igt_vmwgfx: Add vmwgfx device
Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
Signed-off-by: Deepak Rawat
---
lib/drmtest.c | 9 -
lib/drmtest.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index bfa2e0f0..563d5b8b 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -105,6 +105,11 @@ bool is_i915_device(int fd)
return __is_device(fd, "i915");
}
+bool is_vmwgfx_device(int fd)
+{
+ return __is_device(fd, "vmwg");
+}
+
static bool has_known_intel_chipset(int fd)
{
struct drm_i915_getparam gp;
@@ -205,7 +210,7 @@ static const struct module {
{ DRIVER_VC4, "vc4" },
{ DRIVER_VGEM, "vgem" },
{ DRIVER_VIRTIO, "virtio-gpu" },
- { DRIVER_VIRTIO, "virtio_gpu" },
+ { DRIVER_VMWGFX, "vmwgfx" },
{}
};
@@ -335,6 +340,8 @@ static const char *chipset_to_str(int chipset)
return "virtio";
case DRIVER_AMDGPU:
return "amdgpu";
+ case DRIVER_VMWGFX:
+ return "vmwgfx";
case DRIVER_ANY:
return "any";
default:
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 949865ee..0213fb51 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -43,6 +43,7 @@
#define DRIVER_VGEM(1 << 2)
#define DRIVER_VIRTIO (1 << 3)
#define DRIVER_AMDGPU (1 << 4)
+#define DRIVER_VMWGFX (1 << 5)
/*
* Exclude DRVER_VGEM from DRIVER_ANY since if you run on a system
* with vgem as well as a supported driver, you can end up with a
@@ -80,6 +81,8 @@ void igt_require_intel(int fd);
bool is_i915_device(int fd);
+bool is_vmwgfx_device(int fd);
+
/**
* do_or_die:
* @x: command
--
2.17.1
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[Intel-gfx] [PATCH i-g-t 3/5] tests/kms: Don't check crtc state for vmwgfx legacy set_crtc
For a Xorg bug vmwgfx has a kernel workaround which reset the value of
mode::type. This will cause crtc state not to match what is expected.
Signed-off-by: Deepak Rawat
---
tests/kms_atomic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index ac02baf0..72714e12 100644
--- a/tests/kms_atomic.c
+++ b/tests/kms_atomic.c
@@ -237,7 +237,12 @@ static void crtc_commit(igt_pipe_t *pipe, igt_plane_t
*plane,
{
igt_display_commit2(pipe->display, s);
- crtc_check_current_state(pipe, pipe->values, plane->values, relax);
+ /*
+* For a vmwgfx xorg driver bug kernel module reset the value of
+* mode::type so crtc state check fails for legacy commit
+*/
+ if (!is_vmwgfx_device(pipe->display->drm_fd) || !(s == COMMIT_LEGACY))
+ crtc_check_current_state(pipe, pipe->values, plane->values,
relax);
plane_check_current_state(plane, plane->values, relax);
}
--
2.17.1
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[Intel-gfx] [PATCH i-g-t 4/5] lib/igt_fb: Check for stride before creating cairo surface
Cairo surface creation will fail if stride of provided buffer is not same as expected by cairo. This fails for vmwgfx odd length framebuffer as in vmwgfx stride is always width * bpp. Signed-off-by: Deepak Rawat --- lib/igt_fb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index ba995a1a..2724e323 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1349,6 +1349,9 @@ static void create_cairo_surface__gtt(int fd, struct igt_fb *fb) ptr = gem_mmap__gtt(fd, fb->gem_handle, fb->size, PROT_READ | PROT_WRITE); + igt_require(fb->stride == cairo_format_stride_for_width( + drm_format_to_cairo(fb->drm_format), fb->width)); + fb->cairo_surface = cairo_image_surface_create_for_data(ptr, drm_format_to_cairo(fb->drm_format), -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Avoid Gen10 watermark workarounds in Gen11
On Wed, Sep 05, 2018 at 02:32:38PM +0530, Karthik B S wrote:
> Display Workarounds #1125 and #1126 are intended for Gen10 and
> below platforms. These workarounds can be avoided in Gen11.
>
> The result blocks for WM1-WM7 should be atleast as high as the level below
> the current level(Part of Display WA #1125). This part is applicable even
> for Gen11, so it is taken out of the condition check.
>
> v2: Improved Commit Message and addresed other review comments(Rodrigo).
>
Cc: José Roberto de Souza
> Signed-off-by: Karthik B S
Reviewed-by: Rodrigo Vivi
(but before pushing I'd like to get an ack from Jose since CI is not
there yet with ICL)
> ---
> drivers/gpu/drm/i915/intel_pm.c | 37 +
> 1 file changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fa..b5db6a3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4677,26 +4677,31 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> res_lines = div_round_up_fixed16(selected_result,
>wp->plane_blocks_per_line);
>
> - /* Display WA #1125: skl,bxt,kbl,glk */
> - if (level == 0 && wp->rc_surface)
> - res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
> -
> - /* Display WA #1126: skl,bxt,kbl,glk */
> - if (level >= 1 && level <= 7) {
> - if (wp->y_tiled) {
> + if (INTEL_GEN(dev_priv) < 11) {
> + /* Display WA #1125: skl,bxt,kbl,glk */
> + if (level == 0 && wp->rc_surface)
> res_blocks += fixed16_to_u32_round_up(
> wp->y_tile_minimum);
> - res_lines += wp->y_min_scanlines;
> - } else {
> - res_blocks++;
> +
> + /* Display WA #1126: skl,bxt,kbl,glk */
> + if (level >= 1 && level <= 7) {
> + if (wp->y_tiled) {
> + res_blocks += fixed16_to_u32_round_up
> + (wp->y_tile_minimum);
> + res_lines += wp->y_min_scanlines;
> + } else {
> + res_blocks++;
> + }
> }
> + }
>
> - /*
> - * Make sure result blocks for higher latency levels are atleast
> - * as high as level below the current level.
> - * Assumption in DDB algorithm optimization for special cases.
> - * Also covers Display WA #1125 for RC.
> - */
> + /*
> + * Make sure result blocks for higher latency levels are atleast
> + * as high as level below the current level.
> + * Assumption in DDB algorithm optimization for special cases.
> + * Also covers Display WA #1125 for RC.
> + */
> + if (level >= 1 && level <= 7) {
> if (result_prev->plane_res_b > res_blocks)
> res_blocks = result_prev->plane_res_b;
> }
> --
> 2.7.4
>
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Update result lines in correspondence with result blocks
The subject here is marked as icl, but the code seems to all platforms
what am I missing?
But also I didn't check spec yet on this particular case
On Wed, Sep 05, 2018 at 02:32:39PM +0530, Karthik B S wrote:
> As the result blocks for WM1-WM7 are always kept higher than the
> level below the present level, make sure result lines are also higher
> than the level below for WM1-WM7.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b5db6a3..cc41009 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4704,6 +4704,8 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> if (level >= 1 && level <= 7) {
> if (result_prev->plane_res_b > res_blocks)
> res_blocks = result_prev->plane_res_b;
> + if (result_prev->plane_res_l > res_lines)
> + res_lines = result_prev->plane_res_l;
> }
>
> if (INTEL_GEN(dev_priv) >= 11) {
> --
> 2.7.4
>
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Re: [Intel-gfx] [PATCH libdrm v3 0/5] intel: rework how we add PCI IDs
On Wed, Sep 05, 2018 at 08:56:44PM +0100, Chris Wilson wrote: > Quoting Lucas De Marchi (2018-09-05 19:31:55) > > Adding PCI IDs to different projects is a boring manual task that > > motivated me to create this series. The idea is to centralize the IDs in > > the kernel header and let other projects copy it. > > > > Initially my plan was to convert all gens, back to gen2, but that proved > > slightly difficult since there are some corner cases to cover and I > > didn't want to block the important part, i.e.: for recent gens, there's > > no risk of missing a PCI ID. > > > > v2: address comments from Chris by pulling it out to a separate .c > > v3: remove/add comments on first patch and rebase the rest > > > > Discussed on v2 but left for later: > > - replace intel_is_genx() with a simple check for bufmgr->gen, > > after making sure said variable is initialized on all code > > paths. > > - treat unknown gen as a future gen > > - convert gen < 9 to use the new header > > > > Lucas De Marchi (5): > > intel: add generic functions to check PCI ID > > intel: make gen11 use generic gen macro > > intel: make gen10 use generic gen macro > > intel: make gen9 use generic gen macro > > intel: get gen once for gen >= 9 > > The opens are fine and I didn't find anything else to question, so the > series is > Reviewed-by: Chris Wilson pushed, thanks for patches and reviews. > -Chris > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] firmware/dmc/icl: Add MODULE_FIRMWARE()
On Wed, Sep 05, 2018 at 12:50:35PM -0700, Anusha Srivatsa wrote: > Add missing MODULE_FIRMWARE while loading DMC on Icelake. > > Rebased on top of https://patchwork.freedesktop.org/patch/246153/ What about a Fixes after the patch gets pushed? so with message removed or replaced by a proper fixes Reviewed-by: Rodrigo Vivi > > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/intel_csr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_csr.c > b/drivers/gpu/drm/i915/intel_csr.c > index 4aa8f3d..d48186e 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -35,6 +35,7 @@ > */ > > #define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin" > +MODULE_FIRMWARE(I915_CSR_ICL); > #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) > > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" > -- > 2.7.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATH i-g-t 2/2] tests: add slice power programming test
Quoting Tvrtko Ursulin (2018-09-05 15:25:44)
> +static bool
> +kernel_has_per_context_sseu_support(int fd)
> +{
> + struct drm_i915_gem_context_param_sseu sseu = { };
> + struct drm_i915_gem_context_param arg =
> + { .param = I915_CONTEXT_PARAM_SSEU,
> + .value = to_user_pointer() };
> +
> + return __gem_context_get_param(fd, ) == 0;
This is meant to just work with
struct drm_i915_gem_context_param arg = {
.param = I915_CONTEXT_PARAM_SSEU
};
return __gem_context_get_param(fd, ) == 0;
-Chris
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] Add support for forcing specific module
Quoting Rodrigo Siqueira (2018-09-05 21:38:27)
> This commit adds a new option for forcing the use of a specific driver
> indicated via an environment variable.
>
> Changes since V1:
> Petri:
> - Use an environment variable instead of command line
> - Refactor the loop in __search_and_open to accept forced module
> - Don't try to load kernel modules
I am still not convinced this is a good solution to the problem of
running tests against all applicable devices, along with generic
filtering of that set (both from the test profile and user config).
Short term wise I'd rather see DRIVER_ANY translated into a known
DRIVER_X selector (so that we have a complete list of drivers for later
exploitation), say
diff --git a/lib/drmtest.c b/lib/drmtest.c
index bfa2e0f..5c96c1d 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -257,11 +257,16 @@ static int __search_and_open(const char *base, int
offset, unsigned int chipset)
return -1;
}
+static unsigned int driver_any_chipset = DRIVER_ANY; // give me a better name
+
static int __open_driver(const char *base, int offset, unsigned int chipset)
{
static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
int fd;
+ if (chipset == DRIVER_ANY)
+ chipset = driver_any_chipset;
+
fd = __search_and_open(base, offset, chipset);
if (fd != -1)
return fd;
@@ -428,3 +433,21 @@ void igt_require_intel(int fd)
{
igt_require(is_i915_device(fd) && has_known_intel_chipset(fd));
}
+
+bool set_driver_any(const char *name)
+{
+ for (int start = 0, end = ARRAY_SIZE(modules) - 1; start < end; ) { //
repetitive much?
+ int mid = start + (end - start) / 2;
+ int ret = strcmp(modules[mid].module, name);
+ if (ret < 0) {
+ start = mid + 1;
+ } else if (ret > 0) {
+ end = mid;
+ } else {
+ driver_any_chipset = modules[mid].bit;
+ return true;
+ }
+ }
+
+ return false;
+}
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Reset CSB pointers on canceling requests (wedging) (rev2)
== Series Details == Series: drm/i915/execlists: Reset CSB pointers on canceling requests (wedging) (rev2) URL : https://patchwork.freedesktop.org/series/49232/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4775 -> Patchwork_10104 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49232/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10104 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@drv_selftest@live_coherency: fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (54 -> 48) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005 == Build changes == * Linux: CI_DRM_4775 -> Patchwork_10104 CI_DRM_4775: 1a2bb6c061217718b972b3f4a74b96b61cf19d0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10104: 5ab9ca3ad2e9d47392ba9ba8704029923b0008c9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5ab9ca3ad2e9 drm/i915/execlists: Reset CSB pointers on canceling requests (wedging) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10104/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev3)
== Series Details == Series: drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev3) URL : https://patchwork.freedesktop.org/series/49150/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772_full -> Patchwork_10097_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10097_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10097_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10097_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10097_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-hsw: PASS -> INCOMPLETE (fdo#103540, fdo#106886) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703, fdo#107409) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@kms_rotation_crc@primary-rotation-180: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 igt@perf_pmu@rc6-runtime-pm: shard-apl: FAIL (fdo#105010) -> PASS fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107409 https://bugs.freedesktop.org/show_bug.cgi?id=107409 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10097 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10097: da090f41880ea903632c27536e87fbf65f5c4360 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10097/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
On Wed, Sep 05, 2018 at 01:12:00PM -0700, Radhakrishna Sripada wrote:
> Use the newly added "max bpc" connector property to limit pipe bpp.
>
> V3: Use drm_connector_state to access the "max bpc" property
> V4: Initialize the drm property, add suuport to DP(Ville)
> V5: Use the property in the connector and fix CI failure(Ville)
>
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Kishore Kadiyala
> Cc: Manasi Navare
> Cc: Stanislav Lisovskiy
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 +++
> drivers/gpu/drm/i915/intel_dp.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_hdmi.c| 7 +++
> drivers/gpu/drm/i915/intel_modes.c | 20
> 5 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1bd14c61dab5..a890aade094c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10787,6 +10787,34 @@ connected_sink_compute_bpp(struct intel_connector
> *connector,
> }
> }
>
> +static void
> +connected_sink_max_bpp(struct drm_connector_state *conn_state,
> + struct intel_crtc_state *pipe_config)
> +{
> + switch (conn_state->max_bpc) {
> + case 8:
> + case 9:
> + pipe_config->pipe_bpp = 8*3;
> + break;
> + case 10:
> + case 11:
> + pipe_config->pipe_bpp = 10*3;
> + break;
> + case 12:
> + case 13:
> + case 14:
> + case 15:
> + pipe_config->pipe_bpp = 12*3;
> + break;
> + case 16:
> + pipe_config->pipe_bpp = 16*3;
> + break;
> + default:
> + break;
> + }
> + DRM_DEBUG_KMS("Limiting display bpp to %d\n", pipe_config->pipe_bpp);
> +}
> +
> static int
> compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> @@ -10815,6 +10843,9 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> if (connector_state->crtc != >base)
> continue;
>
> + if (connector_state->max_bpc)
> + connected_sink_max_bpp(connector_state, pipe_config);
I think this could wold be best put into shared code, computing a max_bpc
that takes connector->display_info and connector_state->max_bpc into
account. So part of the core drm patch. Would need both a ->max_bpc and a
->max_requested_bpc for the property value or something like that.
Besides this small nit I think this looks solid from a high level.
-Daniel
> +
> connected_sink_compute_bpp(to_intel_connector(connector),
> pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 436c22de33b6..3955745a4d9f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5719,6 +5719,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> intel_attach_force_audio_property(connector);
>
> intel_attach_broadcast_rgb_property(connector);
> + intel_attach_max_bpc_property(connector, 8, 16);
>
> if (intel_dp_is_edp(intel_dp)) {
> u32 allowed_scalers;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index f5731215210a..b3c703dacc92 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1869,6 +1869,8 @@ int intel_ddc_get_modes(struct drm_connector *c, struct
> i2c_adapter *adapter);
> void intel_attach_force_audio_property(struct drm_connector *connector);
> void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
> void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> +void intel_attach_max_bpc_property(struct drm_connector *connector, int min,
> int
> +max);
>
>
> /* intel_overlay.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index a2dab0b6bde6..e649bbf07642 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2109,11 +2109,18 @@ static const struct drm_encoder_funcs
> intel_hdmi_enc_funcs = {
> static void
> intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct
> drm_connector *connector)
> {
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
> intel_attach_aspect_ratio_property(connector);
> drm_connector_attach_content_type_property(connector);
> connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> +
> + if (HAS_GMCH_DISPLAY(dev_priv))
> +
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: make field unsigned (rev2)
On Wed, Sep 05, 2018 at 09:05:40PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915: make field unsigned (rev2) > URL : https://patchwork.freedesktop.org/series/48818/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > c39485603dc4 drm/i915: make field unsigned > 6ee99a76cca9 drm/i915: reword documentation of possible pci_device_id struct > -:33: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #33: FILE: include/drm/i915_pciids.h:32: > + * ^I__u32 vendor, device;$ > > -:34: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #34: FILE: include/drm/i915_pciids.h:33: > + * ^I__u32 subvendor, subdevice;$ > > -:35: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #35: FILE: include/drm/i915_pciids.h:34: > + * ^I__u32 class, class_mask;$ > > -:36: WARNING:SPACE_BEFORE_TAB: please, no space before tabs > #36: FILE: include/drm/i915_pciids.h:35: > + * ^Ikernel_ulong_t driver_data;$ Those are in a comment and the spaces are actually correct since it's part of the multline comment style. Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: make field unsigned (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: make field unsigned (rev2) URL : https://patchwork.freedesktop.org/series/48818/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4775 -> Patchwork_10103 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/48818/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10103 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-kbl-7560u: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@basic-flip-vs-wf_vblank: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@drv_selftest@live_coherency: fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4775 -> Patchwork_10103 CI_DRM_4775: 1a2bb6c061217718b972b3f4a74b96b61cf19d0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10103: 6ee99a76cca960284fc550b0d138a353f723f2e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6ee99a76cca9 drm/i915: reword documentation of possible pci_device_id struct c39485603dc4 drm/i915: make field unsigned == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10103/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC
Gaurav,
I needed to make following changes to teh RC parameter values during testing
to get this to work:
On Tue, Jul 31, 2018 at 02:07:12PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This computation of RC params happens in the atomic commit phase
> during compute_config() to validate if display stream compression
> can be enabled for the requested mode.
>
> v5 (From Manasi):
> * Fix dim checkpatch warnings/checks
> v4(From Gaurav):
> * No change.Rebase on drm-tip
>
> v3 (From Gaurav):
> * Rebase on top of Manasi's latest series
> * Return -ve value in case of failure scenarios (Manasi)
>
> Fix review comments from Ville:
> * Remove unnecessary comments
> * Remove unnecessary paranthesis
> * Add comments for few RC params calculations
>
> v2 (From Manasi):
> * Rebase Gaurav's patch from intel-gfx to gfx-internal
> * Use struct drm_dsc_cfg instead of struct intel_dp
> as a parameter
>
> Cc: Manasi Navare
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_vdsc.c | 129
> ++
> 1 file changed, 129 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> b/drivers/gpu/drm/i915/intel_vdsc.c
> index ecd270c..23ba083 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -335,6 +335,132 @@ static int get_column_index_for_rc_params(u8
> bits_per_component)
> }
> }
>
> +static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> +{
> + unsigned long groups_per_line = 0;
> + unsigned long groups_total = 0;
> + unsigned long num_extra_mux_bits = 0;
> + unsigned long slice_bits = 0;
> + unsigned long hrd_delay = 0;
> + unsigned long final_scale = 0;
> + unsigned long rbs_min = 0;
> +
> + /* RC_MODEL_SIZE is a constant across all configurations */
> + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> + /* Number of groups used to code each line of a slice */
> + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +DP_DSC_RC_PIXELS_PER_GROUP);
> +
> + /* chunksize in Bytes */
> + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> + vdsc_cfg->bits_per_pixel, 8);
^^8 *
16
This is what you had in the initial patches and thats the value that works. The
DSC
spec actually has it as just 8, could you tell how you got the 8*16 in your
original
patches?
> +
> + if (vdsc_cfg->convert_rgb)
> + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> + (4 * vdsc_cfg->bits_per_component + 4)
> + - 2);
> + else
> + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> + (4 * vdsc_cfg->bits_per_component + 4) +
> + 2 * (4 * vdsc_cfg->bits_per_component) - 2;
> + /* Number of bits in one Slice */
> + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> +
> + while ((num_extra_mux_bits > 0) &&
> +((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> + num_extra_mux_bits--;
> +
> + if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> + vdsc_cfg->initial_scale_value = groups_per_line + 8;
> +
> + /* scale_decrement_interval calculation according to DSC spec 1.11 */
> + if (vdsc_cfg->initial_scale_value > 8)
> + vdsc_cfg->scale_decrement_interval = groups_per_line /
> + (8 * vdsc_cfg->initial_scale_value - 8);
^^vdsc_cfg->initial_scale_value - 8
This is how it was set in your original patches.
> + else
> + vdsc_cfg->scale_decrement_interval =
> + DP_DSC_SCALE_DECREMENT_INTERVAL_MAX;
> +
> + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> + (vdsc_cfg->initial_xmit_delay *
> + vdsc_cfg->bits_per_pixel) + num_extra_mux_bits;
^vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
Which was in your original patch.
Could you change these back to the original patch values and have a comment
about how they are obtained.
Manasi
> +
> + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> + DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n");
> + return -1;
> + }
> +
> + final_scale = (vdsc_cfg->rc_model_size << 3) /
> + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> + if (vdsc_cfg->slice_height > 1)
> + /*
> + * NflBpgOffset is 16 bit value with 11 fractional bits
> + * hence we multiply by 2^11 for preserving the
> +
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: make field unsigned (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: make field unsigned (rev2) URL : https://patchwork.freedesktop.org/series/48818/ State : warning == Summary == $ dim checkpatch origin/drm-tip c39485603dc4 drm/i915: make field unsigned 6ee99a76cca9 drm/i915: reword documentation of possible pci_device_id struct -:33: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #33: FILE: include/drm/i915_pciids.h:32: + * ^I__u32 vendor, device;$ -:34: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #34: FILE: include/drm/i915_pciids.h:33: + * ^I__u32 subvendor, subdevice;$ -:35: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #35: FILE: include/drm/i915_pciids.h:34: + * ^I__u32 class, class_mask;$ -:36: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #36: FILE: include/drm/i915_pciids.h:35: + * ^Ikernel_ulong_t driver_data;$ total: 0 errors, 4 warnings, 0 checks, 24 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm: Add connector property to limit max bpc
== Series Details == Series: series starting with [v5,1/2] drm: Add connector property to limit max bpc URL : https://patchwork.freedesktop.org/series/49230/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4775 -> Patchwork_10102 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49230/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10102 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@drv_module_reload@basic-reload: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@drv_selftest@live_coherency: fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_psr@primary_page_flip: fi-cnl-psr: FAIL (fdo#107336) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4775 -> Patchwork_10102 CI_DRM_4775: 1a2bb6c061217718b972b3f4a74b96b61cf19d0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10102: 44f00038f50883e84572b1f94e54ea272d478557 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 44f00038f508 drm/i915: Allow "max bpc" property to limit pipe_bpp 2c48291891eb drm: Add connector property to limit max bpc == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10102/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm: Add connector property to limit max bpc
== Series Details ==
Series: series starting with [v5,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/49230/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c48291891eb drm: Add connector property to limit max bpc
44f00038f508 drm/i915: Allow "max bpc" property to limit pipe_bpp
-:32: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#32: FILE: drivers/gpu/drm/i915/intel_display.c:10792:
+connected_sink_max_bpp(struct drm_connector_state *conn_state,
+struct intel_crtc_state *pipe_config)
-:37: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/intel_display.c:10797:
+ pipe_config->pipe_bpp = 8*3;
^
-:41: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#41: FILE: drivers/gpu/drm/i915/intel_display.c:10801:
+ pipe_config->pipe_bpp = 10*3;
^
-:47: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#47: FILE: drivers/gpu/drm/i915/intel_display.c:10807:
+ pipe_config->pipe_bpp = 12*3;
^
-:50: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#50: FILE: drivers/gpu/drm/i915/intel_display.c:10810:
+ pipe_config->pipe_bpp = 16*3;
^
-:136: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!prop"
#136: FILE: drivers/gpu/drm/i915/intel_modes.c:145:
+ if (prop == NULL) {
-:138: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!prop"
#138: FILE: drivers/gpu/drm/i915/intel_modes.c:147:
+ if (prop == NULL)
total: 0 errors, 0 warnings, 7 checks, 99 lines checked
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[Intel-gfx] ✗ Fi.CI.BAT: failure for firmware/dmc/icl: Add MODULE_FIRMWARE()
== Series Details == Series: firmware/dmc/icl: Add MODULE_FIRMWARE() URL : https://patchwork.freedesktop.org/series/49229/ State : failure == Summary == Applying: firmware/dmc/icl: Add MODULE_FIRMWARE() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_csr.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_csr.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_csr.c error: Failed to merge in the changes. Patch failed at 0001 firmware/dmc/icl: Add MODULE_FIRMWARE() Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] Add support for forcing specific module
This commit adds a new option for forcing the use of a specific driver
indicated via an environment variable.
Changes since V1:
Petri:
- Use an environment variable instead of command line
- Refactor the loop in __search_and_open to accept forced module
- Don't try to load kernel modules
Signed-off-by: Rodrigo Siqueira
---
lib/drmtest.c | 44 ++--
lib/drmtest.h | 2 ++
lib/igt_core.c | 5 +
3 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index bfa2e0f0..6e35d1be 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -123,6 +123,36 @@ static bool has_known_intel_chipset(int fd)
return true;
}
+static char _forced_driver[5] = "";
+
+/**
+ * __set_forced_driver:
+ * @name: name of driver to forcibly use
+ *
+ * Set the name of a driver to use when calling #drm_open_driver with
+ * the #DRIVER_ANY flag.
+ */
+void __set_forced_driver(const char *name)
+{
+ if (!strcmp(name, "")) {
+ igt_warn("IGT_FORCE_DRIVER flag specified without a value,"
+"ignoring force option\n");
+ return;
+ }
+
+ igt_info("Attempt to force module %s\n", name);
+
+ strncpy(_forced_driver, name, 4);
+}
+
+static const char *forced_driver(void)
+{
+ if (_forced_driver[0])
+ return _forced_driver;
+
+ return NULL;
+}
+
#define LOCAL_I915_EXEC_VEBOX (4 << 0)
/**
* gem_quiescent_gpu:
@@ -250,8 +280,18 @@ static int __search_and_open(const char *base, int offset,
unsigned int chipset)
sprintf(name, "%s%u", base, i + offset);
fd = open_device(name, chipset);
- if (fd != -1)
- return fd;
+ if (fd == -1)
+ continue;
+
+ // Force module
+ if (chipset == DRIVER_ANY && forced_driver()) {
+ if (__is_device(fd, forced_driver()))
+ return fd;
+ close(fd);
+ continue;
+ }
+
+ return fd;
}
return -1;
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 949865ee..62f53ec3 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -51,6 +51,8 @@
*/
#define DRIVER_ANY ~(DRIVER_VGEM)
+void __set_forced_driver(const char *name);
+
/**
* ARRAY_SIZE:
* @arr: static array
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 23bb858f..8e65b5e3 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -647,6 +647,11 @@ static void common_init_env(void)
igt_frame_dump_path = getenv("IGT_FRAME_DUMP_PATH");
stderr_needs_sentinel = getenv("IGT_SENTINEL_ON_STDERR") != NULL;
+
+ env = getenv("IGT_FORCE_DRIVER");
+ if (env) {
+ __set_forced_driver(env);
+ }
}
static int common_init(int *argc, char **argv,
--
2.18.0
--
Rodrigo Siqueira
http://siqueira.tech
Graduate Student
Department of Computer Science
University of São Paulo
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[Intel-gfx] [PATCH] drm/i915/execlists: Reset CSB pointers on canceling requests (wedging)
The prior assumption was that we did not need to reset the CSB on
wedging when cancelling the outstanding requests as it would be cleaned
up in the subsequent reset prior to restarting the GPU. However, what
was not accounted for was that in performing the reset, we would try to
process the outstanding CSB entries. If the GPU happened to complete a
CS event just as we were performing the cancellation of requests, that
event would be kept in the CSB until the reset -- but our bookkeeping
was cleared, causing confusion when trying to complete the CS event.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b1f0e5211a0..066ab178a8b2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -850,6 +850,7 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
execlists_user_end(execlists);
+ reset_csb_pointers(execlists);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, >timeline.requests, link) {
--
2.19.0.rc2
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Re: [Intel-gfx] [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params
One more fix below which was the cause of all the artifacts
On Wed, Sep 05, 2018 at 01:04:48PM -0700, Manasi Navare wrote:
> Gaurav,
>
> Please find my review comments below. Caught them when I tested
> your patch on DSC sink.
>
> On Tue, Jul 31, 2018 at 02:07:11PM -0700, Manasi Navare wrote:
> > From: Gaurav K Singh
> >
> > This patches does the following:
> >
> > 1. This patch defines all the DSC parameters as per the VESA
> > DSC specification. These are stored in the encoder and used
> > to compute the PPS parameters to be sent to the Sink.
> > 2. Compute all the DSC parameters which are derived from DSC
> > state of intel_crtc_state.
> > 3. Compute all parameters that are VESA DSC specific
> >
> > This computation happens in the atomic check phase during
> > compute_config() to validate if display stream compression
> > can be enabled for the requested mode.
> >
> > v5 (From Manasi):
> > * Add logic to limit the max line buf depth for DSC 1.1 to 13
> > as per DSC 1.1 spec
> > * Fix dim checkpatch warnings/checks
> >
> > v4 (From Gaurav):
> > * Rebase on latest drm tip
> > * rename variable name(Manasi)
> > * Populate linebuf_depth variable(Manasi)
> >
> > v3 (From Gaurav):
> > * Rebase my previous patches on top of Manasi's latest patch
> > series
> > * Using >>n rather than /2^n (Manasi)
> > * Change the commit message to explain what the patch is doing(Gaurav)
> >
> > Fixed review comments from Ville:
> > * Don't use macro TWOS_COMPLEMENT
> > * Mention in comment about the source of RC params
> > * Return directly from case statements
> > * Using single asssignment for assigning rc_range_params
> > * Using < > about the fixed point numbers
> >
> > v2 (From Manasi):
> > * Update logic for minor version to consider the dpcd value
> > and what supported by the HW platform
> > * Use DRM DSC config struct instead of intel_dp struct
> > * Move the DSC constants to DRM DSC header file
> > * Use u16, u8 where bigger data types not needed
> > * * Compute the DSC parameters as part of DSC compute config
> > since the computation can fail (Manasi)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/Makefile | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 7 +
> > drivers/gpu/drm/i915/intel_drv.h | 4 +
> > drivers/gpu/drm/i915/intel_vdsc.c | 455
> > ++
> > include/drm/drm_dp_helper.h | 3 +
> > include/drm/drm_dsc.h | 2 +-
> > 6 files changed, 472 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 5794f10..deaf2d4 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \
> > intel_sdvo.o \
> > intel_tv.o \
> > vlv_dsi.o \
> > - vlv_dsi_pll.o
> > + vlv_dsi_pll.o \
> > + intel_vdsc.o
> >
> > # Post-mortem debug and GPU hang state capture
> > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 7132f52..dc0a3c2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> > }
> > + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
> > + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
> > %d"
> > + "Compressed BPP = %d\n",
> > + pipe_config->pipe_bpp,
> > + pipe_config->dsc_params.compressed_bpp);
> > + return false;
> > + }
> > pipe_config->dsc_params.compression_enable = true;
> > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
> > "Compressed Bpp = %d Slice Count = %d\n",
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index b7c2652..33cc777 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
> > uint8_t lane_count,
> > uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int
> > mode_clock,
> > int mode_hdisplay);
> >
> > +/* intel_vdsc.c */
> > +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *pipe_config);
> > +
> > static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> > {
> > return ~((1 << lane_count) - 1) & 0xf;
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > new
[Intel-gfx] [PATCH] drm/i915/execlists: Reset CSB pointers on canceling requests (wedging)
The prior assumption was that we did not need to reset the CSB on
wedging when cancelling the outstanding requests as it would be cleaned
up in the subsequent reset prior to restarting the GPU. However, what
was not accounted for was that in performing the reset, we would try to
process the outstanding CSB entries. If the GPU happened to complete a
CS event just as we were performing the cancellation of requests, that
event would be kept in the CSB until the reset -- but our bookkeeping
was cleared, causing confusion when trying to complete the CS event.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b1f0e5211a0..daac3e3b8f0e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -850,6 +850,7 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
execlists_user_end(execlists);
+ reset_csb_pointers(>execlists);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, >timeline.requests, link) {
--
2.19.0.rc2
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[Intel-gfx] [PULL] drm-misc-next
Hi Dave, Here's the latest from -misc-next. This PR includes last weeks as well, I've added both summaries below for your convenience. This week was quite busy, guess everyone is back to work now! This pull features a nice mix of new hw support and code cleanup, with the headliner being udmabuf. drm-misc-next-2018-09-05: drm-misc-next for 4.20: UAPI Changes: - Add userspace dma-buf device to turn memfd regions into dma-bufs (Gerd) Cross-subsystem Changes: - None Core Changes: - Remove user logspam and useless lock in vma_offset_mgr destroy (Chris) Driver Changes: - various: fbdev: Wrap remove_conflicting_framebuffers with resource_len accessors to remove a bunch of cargo-cult (Michał) - rockchip: Add rgb output iface support + fixes (Sandy/Heiko) - nouveau/amdgpu: Add cec-over-aux support (Hans) - sun4i: Add support for Allwinner A64 (Jagan) Cc: Gerd Hoffmann Cc: Chris Wilson Cc: Michał Mirosław Cc: Heiko Stuebner Cc: Sandy Huang Cc: Hans Verkuil Cc: Jagan Teki drm-misc-next-2018-08-30: drm-misc-next for 4.20: UAPI Changes: - Add per-plane blend mode property (Lowry) - Change in drm_fourcc.h is documentation only (Brian) Cross-subsystem Changes: - None Core Changes: - Add get/verify_crc_source for improved crc source selection (Mahesh) - Add __drm_atomic_helper_plane_reset to reduce copypasta (Alexandru) Driver Changes: - various: Replance ref/unref calls with drm_dev_get/put (Thomas) - bridge: Add driver for TI SN65DSI86 chip (Sandeep) - rockchip: Add PX30 support (Sandy) - sun4i: Add support for R40 TCON (Jernej) - vkms: Continued building out vkms, added gem support (Haneen) Cc: Thomas Zimmermann Cc: Sandeep Panda Cc: Sean Paul Cc: Sandy Huang Cc: Lowry Li Cc: Brian Starkey Cc: Jernej Skrabec Cc: Haneen Mohammed Cc: Alexandru Gheorghe Cheers, Sean The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3: Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2018-09-05 for you to fetch changes up to 3ee22b769fd761c98eeaceab49153c3eb7612821: drm/rockchip: rgb: add stub functions when rgb encoder is disabled (2018-09-05 15:43:14 -0400) drm-misc-next for 4.20: UAPI Changes: - Add userspace dma-buf device to turn memfd regions into dma-bufs (Gerd) Cross-subsystem Changes: - None Core Changes: - Remove user logspam and useless lock in vma_offset_mgr destroy (Chris) Driver Changes: - various: fbdev: Wrap remove_conflicting_framebuffers with resource_len accessors to remove a bunch of cargo-cult (Michał) - rockchip: Add rgb output iface support + fixes (Sandy/Heiko) - nouveau/amdgpu: Add cec-over-aux support (Hans) - sun4i: Add support for Allwinner A64 (Jagan) Cc: Gerd Hoffmann Cc: Chris Wilson Cc: Michał Mirosław Cc: Heiko Stuebner Cc: Sandy Huang Cc: Hans Verkuil Cc: Jagan Teki Alexandru Gheorghe (8): drm/atomic: Add __drm_atomic_helper_plane_reset drm: mali-dp: Use __drm_atomic_helper_plane_reset instead of copying the logic drm: atmel-hlcdc: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/imx: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/sun4i: Use __drm_atomic_helper_plane_reset instead of copying the logic drm: rcar-du: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/vc4: Use __drm_atomic_helper_plane_reset instead of copying the logic drm/vmwgfx: Use __drm_atomic_helper_plane_reset instead of copying the logic Andrzej Hajda (3): dt-bindings: tc358754: add DT bindings drm/bridge: tc358764: Add DSI to LVDS bridge driver drm/bridge/tc358764: fix drm helper name Anton Vasilyev (2): drm: qxl: Fix error handling at qxl_device_init drm: qxl: Fix NULL pointer dereference at qxl_alloc_client_monitors_config Archit Taneja (2): dt-bindings: mipi-dsi: Add info about peripherals with non-DSI control bus dt-bindings: mipi-dsi: Add dual-channel DSI related info Ayan Kumar Halder (2): drm/sun4i: Use (struct drm_format_info) fields to determine if a format is yuv and multi planar or not. drm: Use horizontal and vertical chroma subsampling factor while calculating offsets in the physical address of framebuffer Brian Starkey (1): drm/fourcc: Add DOC: overview comment Chris Wilson (3): dma-buf: Remove requirement for ops->map() from dma_buf_export drm: Suppress user controlled spam for invalid drm_wait_vblank_ioctl drm: Remove "protection" around drm_vma_offset_manager_destroy() Dan Carpenter (1): drm/virtio: fix bounds check in virtio_gpu_cmd_get_capset() Daniel Vetter (5): drm/i915: Remove unecessary dma_fence_ops drm/msm: Remove unecessary dma_fence_ops
[Intel-gfx] [PATCH v2] drm/i915: reword documentation of possible pci_device_id struct
Document it like a real struct for ease of copy and paste, remove
comment of C99 compatibility and document that in some cases the first 2
fields can be u16.
v2: - remove mention to (non-existent) PCI_DEVICE_ANY and better explain
use of __u16 in first 2 fields
Cc: Chris Wilson
Signed-off-by: Lucas De Marchi
---
include/drm/i915_pciids.h | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 754ce4b10129..0f15d7b2e8ea 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -26,14 +26,17 @@
#define _I915_PCIIDS_H
/*
- * A pci_device_id struct {
- * __u32 vendor, device;
- * __u32 subvendor, subdevice;
- * __u32 class, class_mask;
- * kernel_ulong_t driver_data;
+ * These macros can be used with a struct declared like this:
+ *
+ * struct pci_device_id {
+ * __u32 vendor, device;
+ * __u32 subvendor, subdevice;
+ * __u32 class, class_mask;
+ * kernel_ulong_t driver_data;
* };
- * Don't use C99 here because "class" is reserved and we want to
- * give userspace flexibility.
+ *
+ * This matches the struct used in the kernel. First two fields may be
+ * changed to __u16 if using this header in a userspace program.
*/
#define INTEL_VGA_DEVICE(id, info) { \
0x8086, id, \
--
2.17.1
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[Intel-gfx] [PATCH v5 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
V5: Use the property in the connector and fix CI failure(Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Kishore Kadiyala
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 31 +++
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c| 7 +++
drivers/gpu/drm/i915/intel_modes.c | 20
5 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1bd14c61dab5..a890aade094c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10787,6 +10787,34 @@ connected_sink_compute_bpp(struct intel_connector
*connector,
}
}
+static void
+connected_sink_max_bpp(struct drm_connector_state *conn_state,
+struct intel_crtc_state *pipe_config)
+{
+ switch (conn_state->max_bpc) {
+ case 8:
+ case 9:
+ pipe_config->pipe_bpp = 8*3;
+ break;
+ case 10:
+ case 11:
+ pipe_config->pipe_bpp = 10*3;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ pipe_config->pipe_bpp = 12*3;
+ break;
+ case 16:
+ pipe_config->pipe_bpp = 16*3;
+ break;
+ default:
+ break;
+ }
+ DRM_DEBUG_KMS("Limiting display bpp to %d\n", pipe_config->pipe_bpp);
+}
+
static int
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
@@ -10815,6 +10843,9 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
if (connector_state->crtc != >base)
continue;
+ if (connector_state->max_bpc)
+ connected_sink_max_bpp(connector_state, pipe_config);
+
connected_sink_compute_bpp(to_intel_connector(connector),
pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..3955745a4d9f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5719,6 +5719,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_max_bpc_property(connector, 8, 16);
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..b3c703dacc92 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1869,6 +1869,8 @@ int intel_ddc_get_modes(struct drm_connector *c, struct
i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
+void intel_attach_max_bpc_property(struct drm_connector *connector, int min,
int
+ max);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index a2dab0b6bde6..e649bbf07642 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2109,11 +2109,18 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_attach_aspect_ratio_property(connector);
drm_connector_attach_content_type_property(connector);
connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
+ if (HAS_GMCH_DISPLAY(dev_priv))
+ intel_attach_max_bpc_property(connector, 8, 8);
+ else
+ intel_attach_max_bpc_property(connector, 8, 12);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index ca44bf368e24..12f1238bad8a 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -133,3 +133,23 @@ intel_attach_aspect_ratio_property(struct drm_connector
*connector)
connector->dev->mode_config.aspect_ratio_property,
DRM_MODE_PICTURE_ASPECT_NONE);
}
+
+void
[Intel-gfx] [PATCH v5 1/2] drm: Add connector property to limit max bpc
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against connector limitations.
Creating a new connector property "max bpc" in order to limit the bpc.
xrandr can make use of this connector property to make sure that bpc does
not exceed the configured value. This property can be used by userspace to
set the bpc.
V2: Initialize max_bpc to satisfy kms_properties
V3: Move the property to drm_connector
V4: Split drm and i915 components(Ville)
V5: Make the property per connector(Ville)
Cc: Ville Syrjälä
Cc: Kishore Kadiyala
Cc: Rodrigo Vivi
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/drm_atomic.c| 4
drivers/gpu/drm/drm_atomic_helper.c | 4
include/drm/drm_connector.h | 12
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index d0478abc01bd..6c6f8d5b5214 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1420,6 +1420,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return set_out_fence_for_connector(state->state, connector,
fence_ptr);
+ } else if (property == connector->max_bpc_property) {
+ state->max_bpc = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -1515,6 +1517,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = 0;
} else if (property == config->writeback_out_fence_ptr_property) {
*val = 0;
+ } else if (property == connector->max_bpc_property) {
+ *val = state->max_bpc;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 2c23a48482da..7f763650a623 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -638,6 +638,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (old_connector_state->link_status !=
new_connector_state->link_status)
new_crtc_state->connectors_changed = true;
+
+ if (old_connector_state->max_bpc !=
+ new_connector_state->max_bpc)
+ new_crtc_state->connectors_changed = true;
}
if (funcs->atomic_check)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 97ea41dc678f..9ce961ad28f9 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -460,6 +460,12 @@ struct drm_connector_state {
* drm_writeback_signal_completion()
*/
struct drm_writeback_job *writeback_job;
+
+ /**
+* @max_bpc: Connector property to limit the maximum bit depth of
+* the pixels.
+*/
+ unsigned int max_bpc;
};
/**
@@ -923,6 +929,12 @@ struct drm_connector {
*/
struct drm_property_blob *path_blob_ptr;
+ /**
+* @max_bpc_property: Default connector property for the max bpc to be
+* driven out of the connector.
+*/
+ struct drm_property *max_bpc_property;
+
#define DRM_CONNECTOR_POLL_HPD (1 << 0)
#define DRM_CONNECTOR_POLL_CONNECT (1 << 1)
#define DRM_CONNECTOR_POLL_DISCONNECT (1 << 2)
--
2.9.3
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Re: [Intel-gfx] [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params
Gaurav,
Please find my review comments below. Caught them when I tested
your patch on DSC sink.
On Tue, Jul 31, 2018 at 02:07:11PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This patches does the following:
>
> 1. This patch defines all the DSC parameters as per the VESA
> DSC specification. These are stored in the encoder and used
> to compute the PPS parameters to be sent to the Sink.
> 2. Compute all the DSC parameters which are derived from DSC
> state of intel_crtc_state.
> 3. Compute all parameters that are VESA DSC specific
>
> This computation happens in the atomic check phase during
> compute_config() to validate if display stream compression
> can be enabled for the requested mode.
>
> v5 (From Manasi):
> * Add logic to limit the max line buf depth for DSC 1.1 to 13
> as per DSC 1.1 spec
> * Fix dim checkpatch warnings/checks
>
> v4 (From Gaurav):
> * Rebase on latest drm tip
> * rename variable name(Manasi)
> * Populate linebuf_depth variable(Manasi)
>
> v3 (From Gaurav):
> * Rebase my previous patches on top of Manasi's latest patch
> series
> * Using >>n rather than /2^n (Manasi)
> * Change the commit message to explain what the patch is doing(Gaurav)
>
> Fixed review comments from Ville:
> * Don't use macro TWOS_COMPLEMENT
> * Mention in comment about the source of RC params
> * Return directly from case statements
> * Using single asssignment for assigning rc_range_params
> * Using < about the fixed point numbers
>
> v2 (From Manasi):
> * Update logic for minor version to consider the dpcd value
> and what supported by the HW platform
> * Use DRM DSC config struct instead of intel_dp struct
> * Move the DSC constants to DRM DSC header file
> * Use u16, u8 where bigger data types not needed
> * * Compute the DSC parameters as part of DSC compute config
> since the computation can fail (Manasi)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 7 +
> drivers/gpu/drm/i915/intel_drv.h | 4 +
> drivers/gpu/drm/i915/intel_vdsc.c | 455
> ++
> include/drm/drm_dp_helper.h | 3 +
> include/drm/drm_dsc.h | 2 +-
> 6 files changed, 472 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 5794f10..deaf2d4 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \
> intel_sdvo.o \
> intel_tv.o \
> vlv_dsi.o \
> - vlv_dsi_pll.o
> + vlv_dsi_pll.o \
> + intel_vdsc.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7132f52..dc0a3c2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> return false;
> }
> }
> + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
> + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
> %d"
> + "Compressed BPP = %d\n",
> + pipe_config->pipe_bpp,
> + pipe_config->dsc_params.compressed_bpp);
> + return false;
> + }
> pipe_config->dsc_params.compression_enable = true;
> DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
> "Compressed Bpp = %d Slice Count = %d\n",
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index b7c2652..33cc777 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
> uint8_t lane_count,
> uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int
> mode_clock,
>int mode_hdisplay);
>
> +/* intel_vdsc.c */
> +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config);
> +
> static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> {
> return ~((1 << lane_count) - 1) & 0xf;
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> b/drivers/gpu/drm/i915/intel_vdsc.c
> new file mode 100644
> index 000..ecd270c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -0,0 +1,455 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> +
Re: [Intel-gfx] [PATCH libdrm v3 0/5] intel: rework how we add PCI IDs
Quoting Lucas De Marchi (2018-09-05 19:31:55) > Adding PCI IDs to different projects is a boring manual task that > motivated me to create this series. The idea is to centralize the IDs in > the kernel header and let other projects copy it. > > Initially my plan was to convert all gens, back to gen2, but that proved > slightly difficult since there are some corner cases to cover and I > didn't want to block the important part, i.e.: for recent gens, there's > no risk of missing a PCI ID. > > v2: address comments from Chris by pulling it out to a separate .c > v3: remove/add comments on first patch and rebase the rest > > Discussed on v2 but left for later: > - replace intel_is_genx() with a simple check for bufmgr->gen, > after making sure said variable is initialized on all code > paths. > - treat unknown gen as a future gen > - convert gen < 9 to use the new header > > Lucas De Marchi (5): > intel: add generic functions to check PCI ID > intel: make gen11 use generic gen macro > intel: make gen10 use generic gen macro > intel: make gen9 use generic gen macro > intel: get gen once for gen >= 9 The opens are fine and I didn't find anything else to question, so the series is Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Per context dynamic (sub)slice power-gating (rev2)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev2) URL : https://patchwork.freedesktop.org/series/48194/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4772_full -> Patchwork_10095_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10095_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10095_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10095_full: === IGT changes === Possible regressions igt@gem_ctx_param@invalid-param-get: shard-apl: PASS -> FAIL shard-glk: PASS -> FAIL shard-snb: PASS -> FAIL shard-hsw: PASS -> FAIL shard-kbl: PASS -> FAIL == Known issues == Here are the changes found in Patchwork_10095_full that come from known issues: === IGT changes === Possible fixes igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@kms_rotation_crc@primary-rotation-180: shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +9 shard-apl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +9 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10095 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10095: 8e7f97c0a4d7d79b7f434f2c18a1455fedfcc6a5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10095/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] firmware/dmc/icl: Add MODULE_FIRMWARE()
Add missing MODULE_FIRMWARE while loading DMC on Icelake. Rebased on top of https://patchwork.freedesktop.org/patch/246153/ Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 4aa8f3d..d48186e 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -35,6 +35,7 @@ */ #define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin" +MODULE_FIRMWARE(I915_CSR_ICL); #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm: Drop drmP.h from drm_connector.c
> > > 2) patch revision info belongs outside the changelog part - no? > > If it's information worth writing it's information worth recording. In > drm we're pretty much ok with whatever you feel like, and most people > include the patch revision in the commit message. Too many cases where > critical information was left out and a patch made no sense at all > anymore half a year down the road. Noted, thanks for the explanation. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Wednesday, September 5, 2018 12:31 PM
>To: Srivatsa, Anusha
>Cc: Deak, Imre ; Nikula, Jani ;
>intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
>
>On Wed, Sep 05, 2018 at 11:55:32AM -0700, Srivatsa, Anusha wrote:
>>
>>
>> >-Original Message-
>> >From: Vivi, Rodrigo
>> >Sent: Monday, September 3, 2018 10:27 PM
>> >To: Deak, Imre
>> >Cc: Srivatsa, Anusha ; Nikula, Jani
>> >; intel-gfx@lists.freedesktop.org; Zanoni,
>> >Paulo R
>> >Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on
>> >icelake.
>> >
>> >On Mon, Sep 03, 2018 at 01:00:39PM +0300, Imre Deak wrote:
>> >> On Mon, Aug 27, 2018 at 05:38:44PM -0700, Anusha Srivatsa wrote:
>> >> > Add Support to load DMC on Icelake.
>> >> >
>> >> > While at it, also add support to load the firmware during system
>> >> > resume.
>> >> >
>> >> > v2: load firmware during system resume.(Imre)
>> >> >
>> >> > v3: enable has_csr for icelake.(Jyoti)
>> >> >
>> >> > v4: Only load the firmware in this patch
>> >> >
>> >> > Cc: Jyoti Yadav
>> >> > Cc: Imre Deak
>> >> > Cc: Rodrigo Vivi
>> >> > Cc: Paulo Zanoni
>> >> > Signed-off-by: Anusha Srivatsa
>> >>
>> >> Reviewed-by: Imre Deak
>> >>
>> >> Is it ok to push this already now that the ICL 1.07 firmware is in
>> >> [1] or do we have to wait until it propagates to [2]?
>> >
>> >The main motivation behind having drm-firmware is the
>> >unpredictability of linux- firmware.git pull requests acceptance. It may
>> >take 1
>day or it may take 2 months.
>> >
>> >So on drm-firmware we at least have it public in a way OSVs could
>> >easisly backport. Although hopefully by the end of 4.20 cycle I
>> >believe it will be there on linux-firmware.git already.
>> >
>> >So if fw is already on drm-firmware and passing all tests we should
>> >be able to push the patch to dinq.
>>
>> I will be sending the PR to linux-firmware.git. I think it is safe to push
>> this patch.
>>
>> Regarding MODULE_FIRMWARE, Rodrigo, do you suggest I send that in a
>separate patch? In that case we can merge this patch as it is and have that as
>a
>separate one.
>
>yeap, let's keep a separated patch for now since we are not sure there is an
>rough
>consensus on getting it in one patch.
Sure.
>>
>> In future, maybe better to add MODULE_FIRMWARE in the original patch?
>
>That is my idea.
>Besides those points that I raised on the other branch of this thread I
>remember
>of more two points in favor of having in only one patch:
>
>In case this patch here lands on 4.20, but linux-firmware.git takes
>4 weeks to pull the firmware the 4.20 will have the fw support, but only 4.21
>will
>have it fully supported with initrd installation etc.
>
>So, if in few months from now OSVs decide to free their distro on 4.20 they
>will
>have to remember to backport this patch or force the firmware to their initrd.
>But
>for sure by the time that OSVs get it the image itself will be already on
>linux-
>firmware.git
>
>And in unlikely case that it took months and months and firmware is not there
>yet
>causing the bad messages for OSVs than the issue is easily fixed on linux-
>firmware.git side.
>
>Or they pull from drm-firmware or they help us convincing linux-firmware.git to
>accept the pull.
That makes sense.
Anusha
>>
>> Anusha
>> >Thanks,
>> >Rodrigo.
>> >
>> >>
>> >> [1] https://cgit.freedesktop.org/drm/drm-firmware/
>> >> [2]
>> >> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firm
>> >> war
>> >> e.git
>> >>
>> >> > ---
>> >> > drivers/gpu/drm/i915/intel_csr.c| 7 +++
>> >> > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
>> >> > 2 files changed, 10 insertions(+)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> >> > b/drivers/gpu/drm/i915/intel_csr.c
>> >> > index 1ec4f09c61f6..6d9d47322405 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_csr.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_csr.c
>> >> > @@ -34,6 +34,9 @@
>> >> > * low-power state and comes back to normal.
>> >> > */
>> >> >
>> >> > +#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
>> >> > +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>> >> > +
>> >> > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
>> >> > MODULE_FIRMWARE(I915_CSR_GLK);
>> >> > #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>> >> > @@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct
>> >drm_i915_private *dev_priv,
>> >> > if (csr->fw_path == i915_modparams.dmc_firmware_path) {
>> >> > /* Bypass version check for firmware override. */
>> >> > required_version = csr->version;
>> >> > + } else if (IS_ICELAKE(dev_priv)) {
>> >> > + required_version = ICL_CSR_VERSION_REQUIRED;
>> >> > } else if (IS_CANNONLAKE(dev_priv)) {
>> >> > required_version = CNL_CSR_VERSION_REQUIRED;
>> >> > } else if
Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
On Wed, Sep 05, 2018 at 11:55:32AM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Vivi, Rodrigo
> >Sent: Monday, September 3, 2018 10:27 PM
> >To: Deak, Imre
> >Cc: Srivatsa, Anusha ; Nikula, Jani
> >; intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
> >
> >Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
> >
> >On Mon, Sep 03, 2018 at 01:00:39PM +0300, Imre Deak wrote:
> >> On Mon, Aug 27, 2018 at 05:38:44PM -0700, Anusha Srivatsa wrote:
> >> > Add Support to load DMC on Icelake.
> >> >
> >> > While at it, also add support to load the firmware during system
> >> > resume.
> >> >
> >> > v2: load firmware during system resume.(Imre)
> >> >
> >> > v3: enable has_csr for icelake.(Jyoti)
> >> >
> >> > v4: Only load the firmware in this patch
> >> >
> >> > Cc: Jyoti Yadav
> >> > Cc: Imre Deak
> >> > Cc: Rodrigo Vivi
> >> > Cc: Paulo Zanoni
> >> > Signed-off-by: Anusha Srivatsa
> >>
> >> Reviewed-by: Imre Deak
> >>
> >> Is it ok to push this already now that the ICL 1.07 firmware is in [1]
> >> or do we have to wait until it propagates to [2]?
> >
> >The main motivation behind having drm-firmware is the unpredictability of
> >linux-
> >firmware.git pull requests acceptance. It may take 1 day or it may take 2
> >months.
> >
> >So on drm-firmware we at least have it public in a way OSVs could easisly
> >backport. Although hopefully by the end of 4.20 cycle I believe it will be
> >there on
> >linux-firmware.git already.
> >
> >So if fw is already on drm-firmware and passing all tests we should be able
> >to
> >push the patch to dinq.
>
> I will be sending the PR to linux-firmware.git. I think it is safe to push
> this patch.
>
> Regarding MODULE_FIRMWARE, Rodrigo, do you suggest I send that in a separate
> patch? In that case we can merge this patch as it is and have that as a
> separate one.
yeap, let's keep a separated patch for now since we are not sure
there is an rough consensus on getting it in one patch.
>
> In future, maybe better to add MODULE_FIRMWARE in the original patch?
That is my idea.
Besides those points that I raised on the other branch of this thread
I remember of more two points in favor of having in only one patch:
In case this patch here lands on 4.20, but linux-firmware.git takes
4 weeks to pull the firmware the 4.20 will have the fw support, but
only 4.21 will have it fully supported with initrd installation etc.
So, if in few months from now OSVs decide to free their distro on 4.20
they will have to remember to backport this patch or force the firmware
to their initrd. But for sure by the time that OSVs get it the image
itself will be already on linux-firmware.git
And in unlikely case that it took months and months and firmware is not there
yet causing the bad messages for OSVs than the issue is easily fixed on
linux-firmware.git side.
Or they pull from drm-firmware or they help us convincing linux-firmware.git
to accept the pull.
>
> Anusha
> >Thanks,
> >Rodrigo.
> >
> >>
> >> [1] https://cgit.freedesktop.org/drm/drm-firmware/
> >> [2]
> >> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmwar
> >> e.git
> >>
> >> > ---
> >> > drivers/gpu/drm/i915/intel_csr.c| 7 +++
> >> > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> >> > 2 files changed, 10 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> >> > b/drivers/gpu/drm/i915/intel_csr.c
> >> > index 1ec4f09c61f6..6d9d47322405 100644
> >> > --- a/drivers/gpu/drm/i915/intel_csr.c
> >> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> >> > @@ -34,6 +34,9 @@
> >> > * low-power state and comes back to normal.
> >> > */
> >> >
> >> > +#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
> >> > +#define ICL_CSR_VERSION_REQUIREDCSR_VERSION(1, 7)
> >> > +
> >> > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
> >> > MODULE_FIRMWARE(I915_CSR_GLK);
> >> > #define GLK_CSR_VERSION_REQUIREDCSR_VERSION(1, 4)
> >> > @@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct
> >drm_i915_private *dev_priv,
> >> > if (csr->fw_path == i915_modparams.dmc_firmware_path) {
> >> > /* Bypass version check for firmware override. */
> >> > required_version = csr->version;
> >> > +} else if (IS_ICELAKE(dev_priv)) {
> >> > +required_version = ICL_CSR_VERSION_REQUIRED;
> >> > } else if (IS_CANNONLAKE(dev_priv)) {
> >> > required_version = CNL_CSR_VERSION_REQUIRED;
> >> > } else if (IS_GEMINILAKE(dev_priv)) { @@ -458,6 +463,8 @@ void
> >> > intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> >> >
> >> > if (i915_modparams.dmc_firmware_path)
> >> > csr->fw_path = i915_modparams.dmc_firmware_path;
> >> > +else if (IS_ICELAKE(dev_priv))
> >> > +csr->fw_path = I915_CSR_ICL;
> >> > else if (IS_CANNONLAKE(dev_priv))
> >> > csr->fw_path =
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/amdgpu: Remove default best_encoder hook from DC (rev2)
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC (rev2) URL : https://patchwork.freedesktop.org/series/49194/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4773 -> Patchwork_10100 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49194/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10100 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_psr@primary_page_flip: fi-cnl-psr: PASS -> FAIL (fdo#107336) Possible fixes igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10100 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10100: 8405889a997b3d86b7453a7f4b0c7e2f2813af8b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8405889a997b drm/amdgpu: Remove default best_encoder hook from DC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10100/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation
== Series Details == Series: series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation URL : https://patchwork.freedesktop.org/series/49187/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772_full -> Patchwork_10094_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10094_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10094_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10094_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10094_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_await@wide-contexts: shard-glk: PASS -> FAIL (fdo#105900) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-apl: PASS -> FAIL (fdo#103375) Possible fixes igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454) -> PASS igt@kms_rotation_crc@primary-rotation-180: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 igt@perf_pmu@rc6-runtime-pm: shard-apl: FAIL (fdo#105010) -> PASS fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10094 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10094: 4c81281ccea1630983a24df1e6af060e8d69e2fe @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10094/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/amdgpu: Remove default best_encoder hook from DC (rev2)
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC (rev2) URL : https://patchwork.freedesktop.org/series/49194/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/amdgpu: Remove default best_encoder hook from DC -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3035:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3826:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3826:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3830:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3830:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3937:58: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3012:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3804:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3804:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3808:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3808:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3915:58: warning: Using plain integer as NULL pointer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/amdgpu: Remove default best_encoder hook from DC (rev2)
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC (rev2) URL : https://patchwork.freedesktop.org/series/49194/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8405889a997b drm/amdgpu: Remove default best_encoder hook from DC -:104: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 70 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm: Add drm/drm_util.h header file (rev2)
== Series Details == Series: series starting with [1/7] drm: Add drm/drm_util.h header file (rev2) URL : https://patchwork.freedesktop.org/series/49184/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4773 -> Patchwork_10099 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49184/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10099 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_psr@primary_page_flip: fi-cnl-psr: PASS -> FAIL (fdo#107336) Possible fixes igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10099 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10099: 4ec94773c5515f4e52c5b4e584eb05c3bee69df0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4ec94773c551 drm: extract drm_atomic_uapi.c d4aedeb40f21 drm: Update todo.rst 00332fdfbdca drm/atomic: trim driver interface/docs cc8a1f89a3b1 drm: drop drmP.h include from drm_crtc.c 6d4da8841fd5 drm: drop drmP.h include from drm_plane.c c6a2e00f8ca5 drm: Drop drmP.h from drm_connector.c ef536308c993 drm: Add drm/drm_util.h header file == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10099/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Monday, September 3, 2018 10:27 PM
>To: Deak, Imre
>Cc: Srivatsa, Anusha ; Nikula, Jani
>; intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>
>Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
>
>On Mon, Sep 03, 2018 at 01:00:39PM +0300, Imre Deak wrote:
>> On Mon, Aug 27, 2018 at 05:38:44PM -0700, Anusha Srivatsa wrote:
>> > Add Support to load DMC on Icelake.
>> >
>> > While at it, also add support to load the firmware during system
>> > resume.
>> >
>> > v2: load firmware during system resume.(Imre)
>> >
>> > v3: enable has_csr for icelake.(Jyoti)
>> >
>> > v4: Only load the firmware in this patch
>> >
>> > Cc: Jyoti Yadav
>> > Cc: Imre Deak
>> > Cc: Rodrigo Vivi
>> > Cc: Paulo Zanoni
>> > Signed-off-by: Anusha Srivatsa
>>
>> Reviewed-by: Imre Deak
>>
>> Is it ok to push this already now that the ICL 1.07 firmware is in [1]
>> or do we have to wait until it propagates to [2]?
>
>The main motivation behind having drm-firmware is the unpredictability of
>linux-
>firmware.git pull requests acceptance. It may take 1 day or it may take 2
>months.
>
>So on drm-firmware we at least have it public in a way OSVs could easisly
>backport. Although hopefully by the end of 4.20 cycle I believe it will be
>there on
>linux-firmware.git already.
>
>So if fw is already on drm-firmware and passing all tests we should be able to
>push the patch to dinq.
I will be sending the PR to linux-firmware.git. I think it is safe to push this
patch.
Regarding MODULE_FIRMWARE, Rodrigo, do you suggest I send that in a separate
patch? In that case we can merge this patch as it is and have that as a
separate one.
In future, maybe better to add MODULE_FIRMWARE in the original patch?
Anusha
>Thanks,
>Rodrigo.
>
>>
>> [1] https://cgit.freedesktop.org/drm/drm-firmware/
>> [2]
>> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmwar
>> e.git
>>
>> > ---
>> > drivers/gpu/drm/i915/intel_csr.c| 7 +++
>> > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
>> > 2 files changed, 10 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> > b/drivers/gpu/drm/i915/intel_csr.c
>> > index 1ec4f09c61f6..6d9d47322405 100644
>> > --- a/drivers/gpu/drm/i915/intel_csr.c
>> > +++ b/drivers/gpu/drm/i915/intel_csr.c
>> > @@ -34,6 +34,9 @@
>> > * low-power state and comes back to normal.
>> > */
>> >
>> > +#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
>> > +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>> > +
>> > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
>> > MODULE_FIRMWARE(I915_CSR_GLK);
>> > #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>> > @@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct
>drm_i915_private *dev_priv,
>> >if (csr->fw_path == i915_modparams.dmc_firmware_path) {
>> >/* Bypass version check for firmware override. */
>> >required_version = csr->version;
>> > + } else if (IS_ICELAKE(dev_priv)) {
>> > + required_version = ICL_CSR_VERSION_REQUIRED;
>> >} else if (IS_CANNONLAKE(dev_priv)) {
>> >required_version = CNL_CSR_VERSION_REQUIRED;
>> >} else if (IS_GEMINILAKE(dev_priv)) { @@ -458,6 +463,8 @@ void
>> > intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>> >
>> >if (i915_modparams.dmc_firmware_path)
>> >csr->fw_path = i915_modparams.dmc_firmware_path;
>> > + else if (IS_ICELAKE(dev_priv))
>> > + csr->fw_path = I915_CSR_ICL;
>> >else if (IS_CANNONLAKE(dev_priv))
>> >csr->fw_path = I915_CSR_CNL;
>> >else if (IS_GEMINILAKE(dev_priv))
>> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > index 2852395125cd..bd7da068e813 100644
>> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > @@ -3563,6 +3563,9 @@ static void icl_display_core_init(struct
>> > drm_i915_private *dev_priv,
>> >
>> >/* 7. Setup MBUS. */
>> >icl_mbus_init(dev_priv);
>> > +
>> > + if (resume && dev_priv->csr.dmc_payload)
>> > + intel_csr_load_program(dev_priv);
>> > }
>> >
>> > static void icl_display_core_uninit(struct drm_i915_private
>> > *dev_priv)
>> > --
>> > 2.17.1
>> >
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm: Add drm/drm_util.h header file (rev2)
== Series Details == Series: series starting with [1/7] drm: Add drm/drm_util.h header file (rev2) URL : https://patchwork.freedesktop.org/series/49184/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Add drm/drm_util.h header file -drivers/gpu/drm/i915/selftests/../i915_drv.h:3688:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) Commit: drm: Drop drmP.h from drm_connector.c Okay! Commit: drm: drop drmP.h include from drm_plane.c Okay! Commit: drm: drop drmP.h include from drm_crtc.c Okay! Commit: drm/atomic: trim driver interface/docs Okay! Commit: drm: Update todo.rst Okay! Commit: drm: extract drm_atomic_uapi.c Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm: Add drm/drm_util.h header file (rev2)
== Series Details ==
Series: series starting with [1/7] drm: Add drm/drm_util.h header file (rev2)
URL : https://patchwork.freedesktop.org/series/49184/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef536308c993 drm: Add drm/drm_util.h header file
-:144: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#144:
new file mode 100644
-:149: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#149: FILE: include/drm/drm_util.h:1:
+/*
-:178: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros starting with if should
be enclosed by a do - while loop to avoid possible if/else logic defects
#178: FILE: include/drm/drm_util.h:30:
+#define for_each_if(condition) if (!(condition)) {} else
-:178: WARNING:BRACES: braces {} are not necessary for single statement blocks
#178: FILE: include/drm/drm_util.h:30:
+#define for_each_if(condition) if (!(condition)) {} else
total: 1 errors, 3 warnings, 0 checks, 105 lines checked
c6a2e00f8ca5 drm: Drop drmP.h from drm_connector.c
-:56: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 30 lines checked
6d4da8841fd5 drm: drop drmP.h include from drm_plane.c
-:94: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 55 lines checked
cc8a1f89a3b1 drm: drop drmP.h include from drm_crtc.c
-:35: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
00332fdfbdca drm/atomic: trim driver interface/docs
-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/drm_atomic.c:501:
+static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state, struct drm_property *property,
-:202: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#202: FILE: drivers/gpu/drm/drm_atomic.c:1253:
+static int drm_atomic_set_writeback_fb_for_connector(
-:342: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 2 checks, 301 lines checked
d4aedeb40f21 drm: Update todo.rst
4ec94773c551 drm: extract drm_atomic_uapi.c
-:1515: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#1515:
new file mode 100644
-:1520: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#1520: FILE: drivers/gpu/drm/drm_atomic_uapi.c:1:
+/*
-:1569: WARNING:TYPO_SPELLING: 'similiar' may be misspelled - perhaps 'similar'?
#1569: FILE: drivers/gpu/drm/drm_atomic_uapi.c:50:
+ * for load detect or similiar.
-:1600: ERROR:CODE_INDENT: code indent should use tabs where possible
#1600: FILE: drivers/gpu/drm/drm_atomic_uapi.c:81:
+^I^I sizeof(umode),$
-:1600: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1600: FILE: drivers/gpu/drm/drm_atomic_uapi.c:81:
+ drm_property_create_blob(state->crtc->dev,
+sizeof(umode),
-:1601: ERROR:CODE_INDENT: code indent should use tabs where possible
#1601: FILE: drivers/gpu/drm/drm_atomic_uapi.c:82:
+^I^I );$
-:1634: ERROR:CODE_INDENT: code indent should use tabs where possible
#1634: FILE: drivers/gpu/drm/drm_atomic_uapi.c:115:
+ struct drm_property_blob *blob)$
-:1634: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#1634: FILE: drivers/gpu/drm/drm_atomic_uapi.c:115:
+ struct drm_property_blob *blob)$
-:1877: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1877: FILE: drivers/gpu/drm/drm_atomic_uapi.c:358:
+static int set_out_fence_for_connector(struct drm_atomic_state *state,
+ struct drm_connector *connector,
-:1917: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"!new_blob"
#1917: FILE: drivers/gpu/drm/drm_atomic_uapi.c:398:
+ if (new_blob == NULL)
-:1939: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1939: FILE: drivers/gpu/drm/drm_atomic_uapi.c:420:
+static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *state, struct drm_property *property,
-:1947: CHECK:BRACES: braces {} should be used on all arms of this statement
#1947: FILE: drivers/gpu/drm/drm_atomic_uapi.c:428:
+ if (property == config->prop_active)
[...]
+ else if (property == config->prop_mode_id) {
[...]
+ } else if (property == config->degamma_lut_property) {
[...]
+ } else if (property == config->ctm_property) {
[...]
+ } else if (property == config->gamma_lut_property) {
[...]
+ } else if
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/intel_csr.c Added ICL Stepping info. (rev2)
== Series Details == Series: drm/i915/intel_csr.c Added ICL Stepping info. (rev2) URL : https://patchwork.freedesktop.org/series/49058/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4773 -> Patchwork_10098 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49058/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10098 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-byt-clapper: PASS -> INCOMPLETE (fdo#102657) igt@kms_psr@primary_page_flip: fi-cnl-psr: PASS -> FAIL (fdo#107336) Possible fixes igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4773 -> Patchwork_10098 CI_DRM_4773: fb94a684a02a423798c1c773cf2ca9d5a7a94fb7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4630: 86686c6e2f7c6f0944bced11550e06d20bc6957f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10098: 647b1f427344d72cfa29857edb4c3b89842c607d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 647b1f427344 drm/i915/intel_csr.c Added ICL Stepping info. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10098/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move final cleanup of drm_i915_private to i915_driver_destroy
On Wed, 05 Sep 2018 16:09:21 +0200, Chris Wilson wrote: Introduce a complementary function to i915_driver_create() to undo all that is created. Suggested-by: Michal Wajdeczko Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko ~Michal ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH libdrm v3 1/5] intel: add generic functions to check PCI ID
This will allow platforms to reuse kernel IDs instead of manually
keeping them in sync. In most of the cases we only need to extend
IS_9XX(). Current platforms that fit this requirement can be ported
over to use this macro. Right now it's a nop since it doesn't have any
PCI ID added.
The i915_pciids.h header is in sync with kernel tree on
drm-tip 2018y-08m-20d-21h-41m-11s.
v2: - move to a separate .c so we can have the array in a single
compilation unit
- use a single array for all gens
- add real functions to get or check gen by pciid
- define our own pci device struct rather than inherit the one
kernel uses: we can throw away most of the fields
v3: - add comment to keep ids sorted by gen
- remove misleading comment about all gens
Cc: Chris Wilson
Signed-off-by: Lucas De Marchi
---
intel/Makefile.sources | 1 +
intel/i915_pciids.h| 461 +
intel/intel_chipset.c | 78 +++
intel/intel_chipset.h | 9 +-
intel/meson.build | 2 +-
5 files changed, 549 insertions(+), 2 deletions(-)
create mode 100644 intel/i915_pciids.h
create mode 100644 intel/intel_chipset.c
diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 6947ab74..61f43aeb 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -5,6 +5,7 @@ LIBDRM_INTEL_FILES := \
intel_bufmgr_gem.c \
intel_decode.c \
intel_chipset.h \
+ intel_chipset.c \
mm.c \
mm.h \
uthash.h
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
new file mode 100644
index ..fd965ffb
--- /dev/null
+++ b/intel/i915_pciids.h
@@ -0,0 +1,461 @@
+/*
+ * Copyright 2013 Intel Corporation
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _I915_PCIIDS_H
+#define _I915_PCIIDS_H
+
+/*
+ * A pci_device_id struct {
+ * __u32 vendor, device;
+ * __u32 subvendor, subdevice;
+ * __u32 class, class_mask;
+ * kernel_ulong_t driver_data;
+ * };
+ * Don't use C99 here because "class" is reserved and we want to
+ * give userspace flexibility.
+ */
+#define INTEL_VGA_DEVICE(id, info) { \
+ 0x8086, id, \
+ ~0, ~0, \
+ 0x03, 0xff, \
+ (unsigned long) info }
+
+#define INTEL_QUANTA_VGA_DEVICE(info) {\
+ 0x8086, 0x16a, \
+ 0x152d, 0x8990, \
+ 0x03, 0xff, \
+ (unsigned long) info }
+
+#define INTEL_I810_IDS(info) \
+ INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
+ INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */\
+ INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
+
+#define INTEL_I815_IDS(info) \
+ INTEL_VGA_DEVICE(0x1132, info) /* I815*/
+
+#define INTEL_I830_IDS(info) \
+ INTEL_VGA_DEVICE(0x3577, info)
+
+#define INTEL_I845G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2562, info)
+
+#define INTEL_I85X_IDS(info) \
+ INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
+ INTEL_VGA_DEVICE(0x358e, info)
+
+#define INTEL_I865G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
+
+#define INTEL_I915G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
+ INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
+
+#define INTEL_I915GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
+
+#define INTEL_I945G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
+
+#define INTEL_I945GM_IDS(info) \
+
[Intel-gfx] [PATCH libdrm v3 5/5] intel: get gen once for gen >= 9
We don't need to call IS_GEN() for each gen >= 9: we can rather use the
new intel_is_genx() helper to iterate the pciids array once.
Signed-off-by: Lucas De Marchi
---
intel/intel_bufmgr_gem.c | 8 +---
intel/intel_decode.c | 8 ++--
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 8c3a4b20..d6587b76 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3656,13 +3656,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->gen = 7;
else if (IS_GEN8(bufmgr_gem->pci_device))
bufmgr_gem->gen = 8;
- else if (IS_GEN9(bufmgr_gem->pci_device))
- bufmgr_gem->gen = 9;
- else if (IS_GEN10(bufmgr_gem->pci_device))
- bufmgr_gem->gen = 10;
- else if (IS_GEN11(bufmgr_gem->pci_device))
- bufmgr_gem->gen = 11;
- else {
+ else if (!intel_get_genx(bufmgr_gem->pci_device, _gem->gen)) {
free(bufmgr_gem);
bufmgr_gem = NULL;
goto exit;
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index b24861b1..0ff095bc 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3823,12 +3823,8 @@ drm_intel_decode_context_alloc(uint32_t devid)
ctx->devid = devid;
ctx->out = stdout;
- if (IS_GEN11(devid))
- ctx->gen = 11;
- else if (IS_GEN10(devid))
- ctx->gen = 10;
- else if (IS_GEN9(devid))
- ctx->gen = 9;
+ if (intel_get_genx(devid, >gen))
+ ;
else if (IS_GEN8(devid))
ctx->gen = 8;
else if (IS_GEN7(devid))
--
2.17.1
___
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[Intel-gfx] [PATCH libdrm v3 3/5] intel: make gen10 use generic gen macro
Signed-off-by: Lucas De Marchi
---
intel/intel_chipset.c | 1 +
intel/intel_chipset.h | 34 +-
2 files changed, 2 insertions(+), 33 deletions(-)
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
index a960b756..a627928e 100644
--- a/intel/intel_chipset.c
+++ b/intel/intel_chipset.c
@@ -36,6 +36,7 @@ static const struct pci_device {
} pciids[] = {
/* Keep ids sorted by gen; latest gen first */
INTEL_ICL_11_IDS(11),
+ INTEL_CNL_IDS(10),
};
bool intel_is_genx(unsigned int devid, int gen)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index db9b53b2..7179b623 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -246,21 +246,6 @@
#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
-#define PCI_CHIP_CANNONLAKE_0 0x5A51
-#define PCI_CHIP_CANNONLAKE_1 0x5A59
-#define PCI_CHIP_CANNONLAKE_2 0x5A41
-#define PCI_CHIP_CANNONLAKE_3 0x5A49
-#define PCI_CHIP_CANNONLAKE_4 0x5A52
-#define PCI_CHIP_CANNONLAKE_5 0x5A5A
-#define PCI_CHIP_CANNONLAKE_6 0x5A42
-#define PCI_CHIP_CANNONLAKE_7 0x5A4A
-#define PCI_CHIP_CANNONLAKE_8 0x5A50
-#define PCI_CHIP_CANNONLAKE_9 0x5A40
-#define PCI_CHIP_CANNONLAKE_10 0x5A54
-#define PCI_CHIP_CANNONLAKE_11 0x5A5C
-#define PCI_CHIP_CANNONLAKE_12 0x5A44
-#define PCI_CHIP_CANNONLAKE_13 0x5A4C
-
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@@ -527,29 +512,13 @@
IS_GEMINILAKE(devid) || \
IS_COFFEELAKE(devid))
-#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \
-(devid) == PCI_CHIP_CANNONLAKE_1 || \
-(devid) == PCI_CHIP_CANNONLAKE_2 || \
-(devid) == PCI_CHIP_CANNONLAKE_3 || \
-(devid) == PCI_CHIP_CANNONLAKE_4 || \
-(devid) == PCI_CHIP_CANNONLAKE_5 || \
-(devid) == PCI_CHIP_CANNONLAKE_6 || \
-(devid) == PCI_CHIP_CANNONLAKE_7 || \
-(devid) == PCI_CHIP_CANNONLAKE_8 || \
-(devid) == PCI_CHIP_CANNONLAKE_9 || \
-(devid) == PCI_CHIP_CANNONLAKE_10 || \
-(devid) == PCI_CHIP_CANNONLAKE_11 || \
-(devid) == PCI_CHIP_CANNONLAKE_12 || \
-(devid) == PCI_CHIP_CANNONLAKE_13)
-
-#define IS_GEN10(devid)(IS_CANNONLAKE(devid))
-
/* New platforms use kernel pci ids */
#include
bool intel_is_genx(unsigned int devid, int gen);
bool intel_get_genx(unsigned int devid, int *gen);
+#define IS_GEN10(devid) intel_is_genx(devid, 10)
#define IS_GEN11(devid) intel_is_genx(devid, 11)
#define IS_9XX(dev)(IS_GEN3(dev) || \
@@ -559,7 +528,6 @@ bool intel_get_genx(unsigned int devid, int *gen);
IS_GEN7(dev) || \
IS_GEN8(dev) || \
IS_GEN9(dev) || \
-IS_GEN10(dev) || \
intel_get_genx(dev, NULL))
#endif /* _INTEL_CHIPSET_H */
--
2.17.1
___
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[Intel-gfx] [PATCH libdrm v3 2/5] intel: make gen11 use generic gen macro
Signed-off-by: Lucas De Marchi
---
intel/intel_chipset.c | 1 +
intel/intel_chipset.h | 27 ++-
2 files changed, 3 insertions(+), 25 deletions(-)
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
index 545819ae..a960b756 100644
--- a/intel/intel_chipset.c
+++ b/intel/intel_chipset.c
@@ -35,6 +35,7 @@ static const struct pci_device {
uint16_t gen;
} pciids[] = {
/* Keep ids sorted by gen; latest gen first */
+ INTEL_ICL_11_IDS(11),
};
bool intel_is_genx(unsigned int devid, int gen)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e4783d4e..db9b53b2 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -261,16 +261,6 @@
#define PCI_CHIP_CANNONLAKE_12 0x5A44
#define PCI_CHIP_CANNONLAKE_13 0x5A4C
-#define PCI_CHIP_ICELAKE_11_0 0x8A50
-#define PCI_CHIP_ICELAKE_11_1 0x8A51
-#define PCI_CHIP_ICELAKE_11_2 0x8A5C
-#define PCI_CHIP_ICELAKE_11_3 0x8A5D
-#define PCI_CHIP_ICELAKE_11_4 0x8A52
-#define PCI_CHIP_ICELAKE_11_5 0x8A5A
-#define PCI_CHIP_ICELAKE_11_6 0x8A5B
-#define PCI_CHIP_ICELAKE_11_7 0x8A71
-#define PCI_CHIP_ICELAKE_11_8 0x8A70
-
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@@ -554,26 +544,14 @@
#define IS_GEN10(devid)(IS_CANNONLAKE(devid))
-#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \
-(devid) == PCI_CHIP_ICELAKE_11_1 || \
-(devid) == PCI_CHIP_ICELAKE_11_2 || \
-(devid) == PCI_CHIP_ICELAKE_11_3 || \
-(devid) == PCI_CHIP_ICELAKE_11_4 || \
-(devid) == PCI_CHIP_ICELAKE_11_5 || \
-(devid) == PCI_CHIP_ICELAKE_11_6 || \
-(devid) == PCI_CHIP_ICELAKE_11_7 || \
-(devid) == PCI_CHIP_ICELAKE_11_8)
-
-#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid))
-
-#define IS_GEN11(devid)(IS_ICELAKE_11(devid))
-
/* New platforms use kernel pci ids */
#include
bool intel_is_genx(unsigned int devid, int gen);
bool intel_get_genx(unsigned int devid, int *gen);
+#define IS_GEN11(devid) intel_is_genx(devid, 11)
+
#define IS_9XX(dev)(IS_GEN3(dev) || \
IS_GEN4(dev) || \
IS_GEN5(dev) || \
@@ -582,7 +560,6 @@ bool intel_get_genx(unsigned int devid, int *gen);
IS_GEN8(dev) || \
IS_GEN9(dev) || \
IS_GEN10(dev) || \
-IS_GEN11(dev) || \
intel_get_genx(dev, NULL))
#endif /* _INTEL_CHIPSET_H */
--
2.17.1
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[Intel-gfx] [PATCH libdrm v3 0/5] intel: rework how we add PCI IDs
Adding PCI IDs to different projects is a boring manual task that motivated me to create this series. The idea is to centralize the IDs in the kernel header and let other projects copy it. Initially my plan was to convert all gens, back to gen2, but that proved slightly difficult since there are some corner cases to cover and I didn't want to block the important part, i.e.: for recent gens, there's no risk of missing a PCI ID. v2: address comments from Chris by pulling it out to a separate .c v3: remove/add comments on first patch and rebase the rest Discussed on v2 but left for later: - replace intel_is_genx() with a simple check for bufmgr->gen, after making sure said variable is initialized on all code paths. - treat unknown gen as a future gen - convert gen < 9 to use the new header Lucas De Marchi (5): intel: add generic functions to check PCI ID intel: make gen11 use generic gen macro intel: make gen10 use generic gen macro intel: make gen9 use generic gen macro intel: get gen once for gen >= 9 intel/Makefile.sources | 1 + intel/i915_pciids.h | 461 +++ intel/intel_bufmgr_gem.c | 8 +- intel/intel_chipset.c| 85 intel/intel_chipset.h| 253 + intel/intel_decode.c | 8 +- intel/meson.build| 2 +- 7 files changed, 561 insertions(+), 257 deletions(-) create mode 100644 intel/i915_pciids.h create mode 100644 intel/intel_chipset.c -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH libdrm v3 4/5] intel: make gen9 use generic gen macro
The 2 PCI IDs that are used for the command line overrid mechanism
were left defined. The rest can be gone and then we just use the kernel
defines.
Signed-off-by: Lucas De Marchi
---
intel/intel_chipset.c | 5 ++
intel/intel_chipset.h | 187 +-
2 files changed, 6 insertions(+), 186 deletions(-)
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
index a627928e..d5c33cc5 100644
--- a/intel/intel_chipset.c
+++ b/intel/intel_chipset.c
@@ -37,6 +37,11 @@ static const struct pci_device {
/* Keep ids sorted by gen; latest gen first */
INTEL_ICL_11_IDS(11),
INTEL_CNL_IDS(10),
+ INTEL_CFL_IDS(9),
+ INTEL_GLK_IDS(9),
+ INTEL_KBL_IDS(9),
+ INTEL_BXT_IDS(9),
+ INTEL_SKL_IDS(9),
};
bool intel_is_genx(unsigned int devid, int gen)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 7179b623..9b1e64f1 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -165,86 +165,8 @@
#define PCI_CHIP_CHERRYVIEW_2 0x22b2
#define PCI_CHIP_CHERRYVIEW_3 0x22b3
-#define PCI_CHIP_SKYLAKE_DT_GT10x1902
-#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
-#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
-#define PCI_CHIP_SKYLAKE_H_GT1 0x190B
-#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
#define PCI_CHIP_SKYLAKE_DT_GT20x1912
-#define PCI_CHIP_SKYLAKE_FUSED0_GT20x1913 /* Reserved */
-#define PCI_CHIP_SKYLAKE_FUSED1_GT20x1915 /* Reserved */
-#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
-#define PCI_CHIP_SKYLAKE_FUSED2_GT20x1917 /* Reserved */
-#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */
-#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
-#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
-#define PCI_CHIP_SKYLAKE_MOBILE_GT20x1921 /* Reserved */
-#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923
-#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926
-#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927
-#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
-#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
-#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D
-#define PCI_CHIP_SKYLAKE_DT_GT40x1932
-#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
-#define PCI_CHIP_SKYLAKE_H_GT4 0x193B
-#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
-
-#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
-#define PCI_CHIP_KABYLAKE_ULT_GT1_50x5913
-#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
-#define PCI_CHIP_KABYLAKE_ULT_GT3_00x5923
-#define PCI_CHIP_KABYLAKE_ULT_GT3_10x5926
-#define PCI_CHIP_KABYLAKE_ULT_GT3_20x5927
-#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
-#define PCI_CHIP_KABYLAKE_ULX_GT1_50x5915
-#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
-#define PCI_CHIP_KABYLAKE_ULX_GT2_00x591E
#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
-#define PCI_CHIP_KABYLAKE_M_GT20x5917
-#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
-#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
-#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
-#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908
-#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B
-#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
-#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
-#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
-
-#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C
-#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0
-
-#define PCI_CHIP_BROXTON_0 0x0A84
-#define PCI_CHIP_BROXTON_1 0x1A84
-#define PCI_CHIP_BROXTON_2 0x5A84
-#define PCI_CHIP_BROXTON_3 0x1A85
-#define PCI_CHIP_BROXTON_4 0x5A85
-
-#define PCI_CHIP_GLK 0x3184
-#define PCI_CHIP_GLK_2X6 0x3185
-
-#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
-#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
-#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
-#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
-#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
-#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
-#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E98
-#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E9A
-#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
-#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
-#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9
-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
-
-#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1
-#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0
-#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2
-#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
-#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -405,119 +327,13 @@
#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Here goes drm-intel-fixes-2018-09-05: The critical fix here on display side is the DP MST regression one. But this pull also include fixes for DP SST, small VDSC register fix and GVT's bucked with "BXT fixes, two guest warning fixes, dmabuf format mod fix and one for recent multiple VM timeout failure." Thanks, Rodrigo. The following changes since commit 57361846b52bc686112da6ca5368d11210796804: Linux 4.19-rc2 (2018-09-02 14:37:30 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-09-05 for you to fetch changes up to 2b82435cb90bed2c5f8398730d964dd11602217c: drm/i915/dp_mst: Fix enabling pipe clock for all streams (2018-09-03 21:34:36 -0700) The critical fix here on display side is the DP MST regression one. But this pull also include fixes for DP SST, small VDSC register fix and GVT's bucked with "BXT fixes, two guest warning fixes, dmabuf format mod fix and one for recent multiple VM timeout failure." Colin Xu (2): drm/i915/gvt: Make correct handling to vreg BXT_PHY_CTL_FAMILY drm/i915/gvt: Handle GEN9_WM_CHICKEN3 with F_CMD_ACCESS. Hang Yuan (1): drm/i915/gvt: move intel_runtime_pm_get out of spin_lock in stop_schedule Imre Deak (1): drm/i915/dp_mst: Fix enabling pipe clock for all streams Jan-Marek Glogowski (1): drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse" Manasi Navare (1): drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Rodrigo Vivi (1): Merge tag 'gvt-fixes-2018-09-04' of https://github.com/intel/gvt-linux into drm-intel-fixes Xiaolin Zhang (1): drm/i915/gvt: emulate gen9 dbuf ctl register access Zhenyu Wang (2): drm/i915/gvt: Fix drm_format_mod value for vGPU plane drm/i915/gvt: Give new born vGPU higher scheduling chance drivers/gpu/drm/i915/gvt/dmabuf.c | 33 ++--- drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 ++--- drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 33 +++-- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 -- drivers/gpu/drm/i915/gvt/sched_policy.c | 37 ++--- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- drivers/gpu/drm/i915/intel_ddi.c| 17 --- drivers/gpu/drm/i915/intel_dp.c | 33 - drivers/gpu/drm/i915/intel_dp_mst.c | 4 10 files changed, 120 insertions(+), 50 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/7] drm: Add drm/drm_util.h header file
== Series Details == Series: series starting with [1/7] drm: Add drm/drm_util.h header file URL : https://patchwork.freedesktop.org/series/49184/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772_full -> Patchwork_10093_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10093_full that come from known issues: === IGT changes === Issues hit igt@kms_flip@flip-vs-expired-vblank: shard-kbl: PASS -> FAIL (fdo#102887, fdo#105363) Possible fixes igt@kms_rotation_crc@primary-rotation-180: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9 igt@perf_pmu@rc6-runtime-pm: shard-apl: FAIL (fdo#105010) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10093 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10093: df2c2eecc6bfd175617f735143a2d876e3122acc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10093/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/amdgpu: Remove default best_encoder hook from DC
For atomic driver this is the default, no need to reimplement it. We
still need to keep the copypasta for not-atomic drivers though, since
no one polished the legacy crtc helpers as much as the atomic ones.
v2: amdgpu uses ->best_encoder internally, give it a local copy. It
might be a good idea to merge the connector and encoder into one
amdgpu_dm_sink structure, that might match DC internals better. At
least for non-DPMST outputs. Kudos to Ville for spotting this.
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Andrey Grodzovsky
Cc: Tony Cheng
Cc: "Leo (Sunpeng) Li"
Cc: Shirish S
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 ---
1 file changed, 7 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index af6adffba788..cbc84b7469eb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2794,28 +2794,6 @@ static const struct drm_connector_funcs
amdgpu_dm_connector_funcs = {
.atomic_get_property = amdgpu_dm_connector_atomic_get_property
};
-static struct drm_encoder *best_encoder(struct drm_connector *connector)
-{
- int enc_id = connector->encoder_ids[0];
- struct drm_mode_object *obj;
- struct drm_encoder *encoder;
-
- DRM_DEBUG_DRIVER("Finding the best encoder\n");
-
- /* pick the encoder ids */
- if (enc_id) {
- obj = drm_mode_object_find(connector->dev, NULL, enc_id,
DRM_MODE_OBJECT_ENCODER);
- if (!obj) {
- DRM_ERROR("Couldn't find a matching encoder for our
connector\n");
- return NULL;
- }
- encoder = obj_to_encoder(obj);
- return encoder;
- }
- DRM_ERROR("No encoder id\n");
- return NULL;
-}
-
static int get_modes(struct drm_connector *connector)
{
return amdgpu_dm_connector_get_modes(connector);
@@ -2934,7 +2912,6 @@ amdgpu_dm_connector_helper_funcs = {
*/
.get_modes = get_modes,
.mode_valid = amdgpu_dm_connector_mode_valid,
- .best_encoder = best_encoder
};
static void dm_crtc_helper_disable(struct drm_crtc *crtc)
@@ -3332,14 +3309,17 @@ static int to_drm_connector_type(enum signal_type st)
}
}
+static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector
*connector)
+{
+ return drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[0]);
+}
+
static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
{
- const struct drm_connector_helper_funcs *helper =
- connector->helper_private;
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
- encoder = helper->best_encoder(connector);
+ encoder = amdgpu_dm_connector_to_encoder(connector);
if (encoder == NULL)
return;
@@ -3466,14 +3446,12 @@ static void amdgpu_dm_connector_ddc_get_modes(struct
drm_connector *connector,
static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
{
- const struct drm_connector_helper_funcs *helper =
- connector->helper_private;
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
struct drm_encoder *encoder;
struct edid *edid = amdgpu_dm_connector->edid;
- encoder = helper->best_encoder(connector);
+ encoder = amdgpu_dm_connector_to_encoder(connector);
if (!edid || !drm_edid_is_valid(edid)) {
drm_add_modes_noedid(connector, 640, 480);
--
2.19.0.rc1
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[Intel-gfx] [PATCH] drm: Update todo.rst
- drmP.h is now fully split up. - vkms is happening (and will gain its own todo and docs under a new vkms.rst file real soon) - legacy cruft is completely hidden now, drm_vblank.c is split out from drm_irq.c now. I've decided to drop the task to split out drm_legacy.ko, partially because Dave already rejected a patch to hide the old dri1 drivers better. Current state feels good enough to me. - best_encoder atomic cleanup is done (it's now the default, not even exported anymore) - bunch of smaller things v2: - Explain why the drm_legacy.ko task is dropped (Emil). - typos (Sam). v3: Fix typo (Ilia) Cc: Ilia Mirkin Cc: Sam Ravnborg Cc: Emil Velikov Signed-off-by: Daniel Vetter Cc: Gustavo Padovan Cc: Maarten Lankhorst Cc: Sean Paul Cc: David Airlie --- Documentation/gpu/todo.rst | 68 ++ 1 file changed, 10 insertions(+), 58 deletions(-) diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index a7c150d6b63f..4c7c3ab60089 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -127,7 +127,8 @@ interfaces to fix these issues: the acquire context explicitly on stack and then also pass it down into drivers explicitly so that the legacy-on-atomic functions can use them. - Except for some driver code this is done. + Except for some driver code this is done. This task should be finished by + adding WARN_ON(!drm_drv_uses_atomic_modeset) in drm_modeset_lock_all(). * A bunch of the vtable hooks are now in the wrong place: DRM has a split between core vfunc tables (named ``drm_foo_funcs``), which are used to @@ -137,13 +138,6 @@ interfaces to fix these issues: ``_helper_funcs`` since they are not part of the core ABI. There's a ``FIXME`` comment in the kerneldoc for each such case in ``drm_crtc.h``. -* There's a new helper ``drm_atomic_helper_best_encoder()`` which could be - used by all atomic drivers which don't select the encoder for a given - connector at runtime. That's almost all of them, and would allow us to get - rid of a lot of ``best_encoder`` boilerplate in drivers. - - This was almost done, but new drivers added a few more cases again. - Contact: Daniel Vetter Get rid of dev->struct_mutex from GEM drivers @@ -164,9 +158,8 @@ private lock. The tricky part is the BO free functions, since those can't reliably take that lock any more. Instead state needs to be protected with suitable subordinate locks or some cleanup work pushed to a worker thread. For performance-critical drivers it might also be better to go with a more -fine-grained per-buffer object and per-context lockings scheme. Currently the -following drivers still use ``struct_mutex``: ``msm``, ``omapdrm`` and -``udl``. +fine-grained per-buffer object and per-context lockings scheme. Currently only the +``msm`` driver still use ``struct_mutex``. Contact: Daniel Vetter, respective driver maintainers @@ -190,7 +183,8 @@ Convert drivers to use simple modeset suspend/resume Most drivers (except i915 and nouveau) that use drm_atomic_helper_suspend/resume() can probably be converted to use -drm_mode_config_helper_suspend/resume(). +drm_mode_config_helper_suspend/resume(). Also there's still open-coded version +of the atomic suspend/resume code in older atomic modeset drivers. Contact: Maintainer of the driver you plan to convert @@ -246,20 +240,10 @@ Core refactorings Clean up the DRM header mess -Currently the DRM subsystem has only one global header, ``drmP.h``. This is -used both for functions exported to helper libraries and drivers and functions -only used internally in the ``drm.ko`` module. The goal would be to move all -header declarations not needed outside of ``drm.ko`` into -``drivers/gpu/drm/drm_*_internal.h`` header files. ``EXPORT_SYMBOL`` also -needs to be dropped for these functions. - -This would nicely tie in with the below task to create kerneldoc after the API -is cleaned up. Or with the "hide legacy cruft better" task. - -Note that this is well in progress, but ``drmP.h`` is still huge. The updated -plan is to switch to per-file driver API headers, which will also structure -the kerneldoc better. This should also allow more fine-grained ``#include`` -directives. +The DRM subsystem originally had only one huge global header, ``drmP.h``. This +is now split up, but many source files still include it. The remaining part of +the cleanup work here is to replace any ``#include `` by only the +headers needed (and fixing up any missing pre-declarations in the headers). In the end no .c file should need to include ``drmP.h`` anymore. @@ -278,26 +262,6 @@ See https://dri.freedesktop.org/docs/drm/ for what's there already. Contact: Daniel Vetter -Hide legacy cruft better - - -Way back DRM supported only drivers which shadow-attached to PCI devices with -userspace or fbdev drivers setting up outputs. Modern DRM drivers take charge -of
Re: [Intel-gfx] [PATCH libdrm v2 5/5] intel: get gen once for gen >= 9
On Wed, Aug 29, 2018 at 03:31:11PM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-29 01:35:32)
> > We don't need to call IS_GEN() for each gen >= 9: we can rather use the
> > new intel_is_genx() helper to iterate the pciids array once.
> >
> > Signed-off-by: Lucas De Marchi
> > ---
> > intel/intel_bufmgr_gem.c | 8 +---
> > intel/intel_decode.c | 8 ++--
> > 2 files changed, 3 insertions(+), 13 deletions(-)
> >
> > diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> > index 8c3a4b20..d6587b76 100644
> > --- a/intel/intel_bufmgr_gem.c
> > +++ b/intel/intel_bufmgr_gem.c
> > @@ -3656,13 +3656,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
> > bufmgr_gem->gen = 7;
> > else if (IS_GEN8(bufmgr_gem->pci_device))
> > bufmgr_gem->gen = 8;
> > - else if (IS_GEN9(bufmgr_gem->pci_device))
> > - bufmgr_gem->gen = 9;
> > - else if (IS_GEN10(bufmgr_gem->pci_device))
> > - bufmgr_gem->gen = 10;
> > - else if (IS_GEN11(bufmgr_gem->pci_device))
> > - bufmgr_gem->gen = 11;
> > - else {
> > + else if (!intel_get_genx(bufmgr_gem->pci_device, _gem->gen))
> > {
> > free(bufmgr_gem);
> > bufmgr_gem = NULL;
> > goto exit;
>
> And while you are here, don't exit for an unknown gen, just pretend it's
> a future one. i915_pciids.h should contain *all* ids, even reserved, for
> exactly this reason. (The same behaviour is relied on elsewhere so that
> we don't get caught out by some one retrospectively introducing a new
> chip. Don't even get started on the abuse of pci-id for sub-gen
> encoding...)
This can be done as a separate series, otherwise we will just start
shoving a lot of things on top of this series and never get it merged.
Lucas De Marchi
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[Intel-gfx] [PATCH] [intel-gfx] drm/i915/intel_csr.c Added ICL Stepping info.
As DMC Package contain DMC FW for multiple steppings including default
stepping. This patch will help to load FW for that particular stepping,
if FW for that stepping is available, instead of loading default FW.
v2 : Fix formatting issue.
Signed-off-by: Jyoti Yadav
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_csr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ec4f09..5c467f2 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -184,6 +184,12 @@ struct stepping_info {
{'B', '0'}, {'B', '1'}, {'B', '2'}
};
+static const struct stepping_info icl_stepping_info[] = {
+ {'A', '0'}, {'A', '1'}, {'A', '2'},
+ {'B', '0'}, {'B', '2'},
+ {'C', '0'}
+};
+
static const struct stepping_info no_stepping_info = { '*', '*' };
static const struct stepping_info *
@@ -192,7 +198,10 @@ struct stepping_info {
const struct stepping_info *si;
unsigned int size;
- if (IS_SKYLAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ size = ARRAY_SIZE(icl_stepping_info);
+ si = icl_stepping_info;
+ } else if (IS_SKYLAKE(dev_priv)) {
size = ARRAY_SIZE(skl_stepping_info);
si = skl_stepping_info;
} else if (IS_BROXTON(dev_priv)) {
--
1.9.1
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bdw: Increase IPS disable timeout to 100ms
On Wed, Sep 05, 2018 at 12:44:37PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/bdw: Increase IPS disable timeout to 100ms > URL : https://patchwork.freedesktop.org/series/49175/ > State : success Pushed, thanks for the review. > > == Summary == > > = CI Bug Log - changes from CI_DRM_4770_full -> Patchwork_10091_full = > > == Summary - SUCCESS == > > No regressions found. > > > > == Known issues == > > Here are the changes found in Patchwork_10091_full that come from known > issues: > > === IGT changes === > > Issues hit > > igt@gem_exec_big: > shard-hsw: PASS -> INCOMPLETE (fdo#103540) > > igt@kms_cursor_legacy@cursor-vs-flip-toggle: > shard-hsw: PASS -> FAIL (fdo#103355) > > igt@kms_flip@2x-flip-vs-expired-vblank: > shard-glk: PASS -> FAIL (fdo#105363) > > igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt: > shard-glk: PASS -> FAIL (fdo#103167) > > igt@perf@blocking: > shard-hsw: PASS -> FAIL (fdo#102252) > > > Possible fixes > > igt@drv_suspend@shrink: > shard-snb: FAIL (fdo#106886) -> PASS > > igt@kms_busy@extended-modeset-hang-newfb-render-b: > shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS > > igt@kms_flip@flip-vs-expired-vblank: > shard-glk: FAIL (fdo#105363) -> PASS > > > fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 > fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 > fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 > fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 > fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 > fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 > fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 > k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > == Participating hosts (5 -> 5) == > > No changes in participating hosts > > > == Build changes == > > * Linux: CI_DRM_4770 -> Patchwork_10091 > > CI_DRM_4770: 0c3535cf60140d017a5df73d84d06e8b1a5b5d3b @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_4627: e0c3033a57d85c0d2eb33af0451afa16edc79f10 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_10091: 6745896fef66c4282e347efd2270d6c0d5739ed3 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10091/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm: Drop drmP.h from drm_connector.c
On Wed, Sep 5, 2018 at 7:12 PM, Sam Ravnborg wrote: > On Wed, Sep 05, 2018 at 03:57:06PM +0200, Daniel Vetter wrote: >> Only needed minimal changes in drm_internal.h (for the drm_ioctl_t >> type and a few forward declarations), plus a few missing includes in >> drm_connector.c. >> >> Yay, the last stage of the drm header cleanup can finally commence! >> >> v2: Compiles now, with drm/kernel.h extracted. > 1) It is now named drm_util.h (the drm_util name makes more sense to me) Ah right, I'll fix up when applying or respinning, whichever comes first. > 2) patch revision info belongs outside the changelog part - no? If it's information worth writing it's information worth recording. In drm we're pretty much ok with whatever you feel like, and most people include the patch revision in the commit message. Too many cases where critical information was left out and a patch made no sense at all anymore half a year down the road. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm: Drop drmP.h from drm_connector.c
On Wed, Sep 05, 2018 at 03:57:06PM +0200, Daniel Vetter wrote: > Only needed minimal changes in drm_internal.h (for the drm_ioctl_t > type and a few forward declarations), plus a few missing includes in > drm_connector.c. > > Yay, the last stage of the drm header cleanup can finally commence! > > v2: Compiles now, with drm/kernel.h extracted. 1) It is now named drm_util.h (the drm_util name makes more sense to me) 2) patch revision info belongs outside the changelog part - no? Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against
On Wed, 2018-09-05 at 12:51 +0200, Maarten Lankhorst wrote:
> Op 05-09-18 om 12:22 schreef Ville Syrjälä:
> > On Tue, Sep 04, 2018 at 08:54:03PM +, Pandiyan, Dhinakaran
> > wrote:
> > > On Tue, 2018-09-04 at 19:12 +0100, Chris Wilson wrote:
> > > > Quoting Ville Syrjälä (2018-09-04 19:06:29)
> > > > > On Tue, Sep 04, 2018 at 08:59:32PM +0300, Ville Syrjälä
> > > > > wrote:
> > > > > > On Tue, Sep 04, 2018 at 06:44:14PM +0100, Chris Wilson
> > > > > > wrote:
> > > > > > > Quoting Ville Syrjälä (2018-09-04 18:39:53)
> > > > > > > > On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson
> > > > > > > > wrote:
> > > > > > > > > If the previous modeset commit has completed and is
> > > > > > > > > no
> > > > > > > > > longer part of
> > > > > > > > > the crtc state, skip waiting for it.
> > > > > > > > >
> > > > > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?i
> > > > > > > > > d=1077
> > > > > > > > > 92
> > > > > > > > > Fixes: c44301fce614 ("drm/i915: Allow control of PSR
> > > > > > > > > at
> > > > > > > > > runtime through debugfs, v6")
> > > > > > > > > Signed-off-by: Chris Wilson > > > > > > > > >
> > > > > > > > > Cc: Maarten Lankhorst > > > > > > > > com>
> > > > > > > > > Cc: Rodrigo Vivi
> > > > > > > > > Cc: Dhinakaran Pandiyan > > > > > > > > m>
> > > > > > > > > ---
> > > > > > > > > drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> > > > > > > > >
> > > > > > > > > 1 file changed, 10 insertions(+), 6 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > > > > index 21984d4c08ed..bddc9c7c681e 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > > > > @@ -834,6 +834,7 @@ int
> > > > > > > > > intel_psr_set_debugfs_mode(struct
> > > > > > > > > drm_i915_private *dev_priv,
> > > > > > > > > struct drm_device *dev = _priv->drm;
> > > > > > > > > struct drm_connector_state *conn_state;
> > > > > > > > > struct intel_crtc_state *crtc_state = NULL;
> > > > > > > > > + struct drm_crtc_commit *commit = NULL;
> > > > > > > > > struct drm_crtc *crtc;
> > > > > > > > > struct intel_dp *dp;
> > > > > > > > > int ret;
> > > > > > > > > @@ -860,12 +861,15 @@ int
> > > > > > > > > intel_psr_set_debugfs_mode(struct
> > > > > > > > > drm_i915_private *dev_priv,
> > > > > > > > > return ret;
> > > > > > > > >
> > > > > > > > > crtc_state = to_intel_crtc_state(crtc-
> > > > > > > > > > state);
> > > > > > > > >
> > > > > > > > > - ret =
> > > > > > > > > wait_for_completion_interruptible(_state-
> > > > > > > > > >base.commit-
> > > > > > > > > > hw_done);
> > > > > > > > >
> > > > > > > > > - } else
> > > > > > > > > - ret =
> > > > > > > > > wait_for_completion_interruptible(_state-
> > > > > > > > > >commit-
> > > > > > > > > > hw_done);
> > > > > > > > >
> > > > > > > > > -
> > > > > > > > > - if (ret)
> > > > > > > > > - return ret;
> > > > > > > > > + commit = crtc_state->base.commit;
> > > > > > > > > + } else {
> > > > > > > > > + commit = conn_state->commit;
> > > > > > > >
> > > > > > > > I can't even find where we clear state->commit after
> > > > > > > > its
> > > > > > > > done.
> > > > > > > > Do we just leave it pointing at freed memory or
> > > > > > > > something?
> > > > > > > > Also I
> > > > > > > > can't figure out why drm_atomic_helper_commit_hw_done()
> > > > > > > > copies
> > > > > > > > the commit also to the old state.
> > > > > > >
> > > > > > > Let me be the messenger then ;) commit is NULL at this
> > > > > > > point, I
> > > > > > > just
> > > > > > > presumed it was intentional.
> > > > > >
> > > > > > My expectation would be that it gets cleared somewhere, but
> > > > > > I
> > > > > > simply
> > > > > > can't find any such code.
> > > > >
> > > > > Actually it looks like there is no such code. The event based
> > > > > release_crtc_commit() thing gets its own reference so
> > > > > presumably
> > > > > the
> > > > > original reference stays with the state until the state
> > > > > itself gets
> > > > > destroyed.
> > > >
> > > > Happy with the it never had a commit theory, or is this a
> > > > deeper
> > > > problem
> > > > that needs root causing?
> > >
> > > Just so that I understand this correctly, even if there was a
> > > prior
> > > commit, state->commit would have been freed when completion was
> > > signaled. Is that right?
> >
> > Nah, looks like it's going to hang on to the commit as long as the
> > state exists. At least that's my reading of the atomic helper.
> > Or maybe I'm missing something clever? Daniel/Maarten?
> >
>
> The commit is refcounted, and the original state has a reference. As
> long as that's not freed, the commit will hang around. So that can't
> cause a hang..
>
Okay, the
Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams
On Wed, Sep 05, 2018 at 01:01:58PM +0300, Jani Nikula wrote: 1;5202;0c> On Tue, 04 Sep 2018, Dhinakaran Pandiyan wrote: > > On Tue, 2018-09-04 at 16:19 -0700, Rodrigo Vivi wrote: > >> On Tue, Sep 04, 2018 at 03:53:51PM -0700, Dhinakaran Pandiyan wrote: > >> > Is it possible to have another external display connected to one of > >> > these? > >> > >> or to both of them?! > >> > > :) Not sure why I wanted only one of them. > > Heh, well, we did have a bug in the past where we failed if the device > was booted with no displays. Diversify, don't maximize. ;) hehe :) yeap, makes sense! > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
On Wed, Sep 05, 2018 at 12:07:43PM +0300, Joonas Lahtinen wrote:
> Quoting Rodrigo Vivi (2018-09-04 08:27:14)
> > On Mon, Sep 03, 2018 at 01:00:39PM +0300, Imre Deak wrote:
> > > On Mon, Aug 27, 2018 at 05:38:44PM -0700, Anusha Srivatsa wrote:
> > > > Add Support to load DMC on Icelake.
> > > >
> > > > While at it, also add support to load the firmware
> > > > during system resume.
> > > >
> > > > v2: load firmware during system resume.(Imre)
> > > >
> > > > v3: enable has_csr for icelake.(Jyoti)
> > > >
> > > > v4: Only load the firmware in this patch
> > > >
> > > > Cc: Jyoti Yadav
> > > > Cc: Imre Deak
> > > > Cc: Rodrigo Vivi
> > > > Cc: Paulo Zanoni
> > > > Signed-off-by: Anusha Srivatsa
> > >
> > > Reviewed-by: Imre Deak
> > >
> > > Is it ok to push this already now that the ICL 1.07 firmware is in [1]
> > > or do we have to wait until it propagates to [2]?
> >
> > The main motivation behind having drm-firmware is the unpredictability
> > of linux-firmware.git pull requests acceptance. It may take 1 day or it
> > may take 2 months.
> >
> > So on drm-firmware we at least have it public in a way OSVs
> > could easisly backport. Although hopefully by the end of 4.20
> > cycle I believe it will be there on linux-firmware.git already.
> >
> > So if fw is already on drm-firmware and passing all tests
> > we should be able to push the patch to dinq.
>
> Was not the decision that we only gate the MODULE_FIRMWARE line until
> the firmware is in linux-firmware.git?
>
> So it should be no harm to support loading firmwares that are available
> from drm-firmware.git as long as we don't add the MODULE_FIRMWARE which
> would trigger false positives for distro packagers.
As far as I can remember we had agreed on changing this and adding
MODULE_FIRMWARE from the beginning.
1. the process gets complex
2. we forgot many times to add it afterwards
3. module_firmware changes nothing... only the fact that initrd generation
wont complain if firmware is not there yet.
4. The old issue was that patches were merged without the pull request
being sent... We fixed that by only accepting patches after pull request
is sent.
5. By the time that all lands to distros linux-firmware.git will have
the firmware because of 4.
6. We have now drm-firmware to mirror what official linux-firmware.git will
be in few weeks from now.
So I don't see a reason anymore why to keep with complicated process with
split MODULE_FIRMWARE.
Thanks,
Rodrigo.
>
> Regards, Joonas
>
> >
> > Thanks,
> > Rodrigo.
> >
> > >
> > > [1] https://cgit.freedesktop.org/drm/drm-firmware/
> > > [2]
> > > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_csr.c| 7 +++
> > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> > > > 2 files changed, 10 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > > > b/drivers/gpu/drm/i915/intel_csr.c
> > > > index 1ec4f09c61f6..6d9d47322405 100644
> > > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > > @@ -34,6 +34,9 @@
> > > > * low-power state and comes back to normal.
> > > > */
> > > >
> > > > +#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
> > > > +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> > > > +
> > > > #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
> > > > MODULE_FIRMWARE(I915_CSR_GLK);
> > > > #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
> > > > @@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct
> > > > drm_i915_private *dev_priv,
> > > > if (csr->fw_path == i915_modparams.dmc_firmware_path) {
> > > > /* Bypass version check for firmware override. */
> > > > required_version = csr->version;
> > > > + } else if (IS_ICELAKE(dev_priv)) {
> > > > + required_version = ICL_CSR_VERSION_REQUIRED;
> > > > } else if (IS_CANNONLAKE(dev_priv)) {
> > > > required_version = CNL_CSR_VERSION_REQUIRED;
> > > > } else if (IS_GEMINILAKE(dev_priv)) {
> > > > @@ -458,6 +463,8 @@ void intel_csr_ucode_init(struct drm_i915_private
> > > > *dev_priv)
> > > >
> > > > if (i915_modparams.dmc_firmware_path)
> > > > csr->fw_path = i915_modparams.dmc_firmware_path;
> > > > + else if (IS_ICELAKE(dev_priv))
> > > > + csr->fw_path = I915_CSR_ICL;
> > > > else if (IS_CANNONLAKE(dev_priv))
> > > > csr->fw_path = I915_CSR_CNL;
> > > > else if (IS_GEMINILAKE(dev_priv))
> > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > index 2852395125cd..bd7da068e813 100644
> > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > @@ -3563,6 +3563,9 @@ static void icl_display_core_init(struct
> > > > drm_i915_private *dev_priv,
> > > >
> > > > /* 7. Setup MBUS. */
> > > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev3)
== Series Details == Series: drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev3) URL : https://patchwork.freedesktop.org/series/49150/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772 -> Patchwork_10097 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49150/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_10097 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@userptr: fi-kbl-8809g: PASS -> INCOMPLETE (fdo#107402) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#107139, fdo#105128) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402 == Participating hosts (54 -> 49) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10097 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10097: da090f41880ea903632c27536e87fbf65f5c4360 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == da090f41880e drm: Reject unknown legacy bpp and depth for drm_mode_addfb ioctl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10097/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dp: optimize eDP 1.4+ link config fast and narrow
On Wed, Sep 05, 2018 at 12:53:21PM +0300, Jani Nikula wrote:
> We've opted to use the maximum link rate and lane count for eDP panels,
> because typically the maximum supported configuration reported by the
> panel has matched the native resolution requirements of the panel, and
> optimizing the link has lead to problems.
>
> With eDP 1.4 rate select method and DSC features, this is decreasingly
> the case. There's a need to optimize the link parameters. Moreover,
> already eDP 1.3 states fast link with fewer lanes is preferred over the
> wide and slow. (Wide and slow should still be more reliable for longer
> cable lengths.)
>
> Additionally, there have been reports of panels failing on arbitrary
> link configurations, although arguably all configurations they claim to
> support should work.
>
> Optimize eDP 1.4+ link config fast and narrow.
>
> Side note: The implementation has a near duplicate of the link config
> function, with just the two inner for loops turned inside out. Perhaps
> there'd be a way to make this, say, more table driven to reduce the
> duplication, but seems like that would lead to duplication in the table
> generation. We'll also have to see how the link config optimization for
> DSC turns out.
In case of DSC, currently we only compute DSC params and enable DSC if
intel_dp_compute_link_config() returns a false. So since the fast_narrow
link calculation is embedded within the intel_dp_compute_link_config(),
DSC can still be enabled if link config returns false with either fast_narrow
or wide approach.
However ideally, for power savings for eDP we could eventually enable DSC first
if supported by the panel, find the mode rate with compressed bpp and then
optimize the link config with that compressed bpp. So reverse the order
of dsc_compute_config and intel_dp_compute_link_config()
Everything else in the patch looks good to me.
Acked-by: Manasi Navare
Manasi
>
> Cc: Ville Syrjälä
> Cc: Manasi Navare
> Cc: Rodrigo Vivi
> Cc: Matt Atwood
> Cc: "Lee, Shawn C"
> Acked-by: Rodrigo Vivi
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105267
> Signed-off-by: Jani Nikula
>
> ---
>
> v2 of
> http://patchwork.freedesktop.org/patch/msgid/20180509071321.28563-1-jani.nik...@intel.com
>
> Untested. It's possible this helps the referenced bug. The downside is
> that this patch has a bunch of dependencies that are too much to
> backport to stable kernels. If the patch works, we may need to consider
> hacking together an uglier backport.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 73
> ++---
> 1 file changed, 62 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 436c22de33b6..bf7b91832c8a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1921,6 +1921,42 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> return false;
> }
>
> +/* Optimize link config in order: max bpp, min lanes, min clock */
> +static bool
> +intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config,
> + const struct link_config_limits *limits)
> +{
> + struct drm_display_mode *adjusted_mode =
> _config->base.adjusted_mode;
> + int bpp, clock, lane_count;
> + int mode_rate, link_clock, link_avail;
> +
> + for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> + mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> +bpp);
> +
> + for (lane_count = limits->min_lane_count;
> + lane_count <= limits->max_lane_count;
> + lane_count <<= 1) {
> + for (clock = limits->min_clock; clock <=
> limits->max_clock; clock++) {
> + link_clock = intel_dp->common_rates[clock];
> + link_avail = intel_dp_max_data_rate(link_clock,
> + lane_count);
> +
> + if (mode_rate <= link_avail) {
> + pipe_config->lane_count = lane_count;
> + pipe_config->pipe_bpp = bpp;
> + pipe_config->port_clock = link_clock;
> +
> + return true;
> + }
> + }
> + }
> + }
> +
> + return false;
> +}
> +
> static bool
> intel_dp_compute_link_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
> @@ -1945,13 +1981,15 @@ intel_dp_compute_link_config(struct intel_encoder
> *encoder,
> limits.min_bpp = 6 * 3;
> limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>
> - if
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/amdgpu: Remove default best_encoder hook from DC
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC URL : https://patchwork.freedesktop.org/series/49194/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4772 -> Patchwork_10096 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10096 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10096, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/49194/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10096: === IGT changes === Possible regressions igt@core_auth@basic-auth: fi-kbl-8809g: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10096 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128, fdo#107139) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (54 -> 48) == Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10096 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10096: 0e61c0665c5237599b0b1ee41b0ff6a54033c2ec @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0e61c0665c52 drm/amdgpu: Remove default best_encoder hook from DC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10096/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm: Reject unknown legacy bpp and depth for drm_mode_addfb ioctl
Since this is handling user provided bpp and depth, we need to sanity
check and propagate the EINVAL back rather than assume what the insane
client intended and fill the logs with DRM_ERROR.
v2: Check both bpp and depth match the builtin pixel format, and
introduce a canonical DRM_FORMAT_INVALID to reserve 0 against any future
fourcc.
v3: Mark up DRM_FORMAT_C8 as being {bpp:8, depth:8}
Testcase: igt/kms_addfb_basic/legacy-format
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Michel Dänzer
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_fourcc.c | 37 ++-
drivers/gpu/drm/drm_framebuffer.c | 7 +-
include/uapi/drm/drm_fourcc.h | 3 +++
3 files changed, 36 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..be1d6aaef651 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -45,32 +45,49 @@ static char printable_char(int c)
*/
uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
{
- uint32_t fmt;
+ uint32_t fmt = DRM_FORMAT_INVALID;
switch (bpp) {
case 8:
- fmt = DRM_FORMAT_C8;
+ if (depth == 8)
+ fmt = DRM_FORMAT_C8;
break;
+
case 16:
- if (depth == 15)
+ switch (depth) {
+ case 15:
fmt = DRM_FORMAT_XRGB1555;
- else
+ break;
+ case 16:
fmt = DRM_FORMAT_RGB565;
+ break;
+ default:
+ break;
+ }
break;
+
case 24:
- fmt = DRM_FORMAT_RGB888;
+ if (depth == 24)
+ fmt = DRM_FORMAT_RGB888;
break;
+
case 32:
- if (depth == 24)
+ switch (depth) {
+ case 24:
fmt = DRM_FORMAT_XRGB;
- else if (depth == 30)
+ break;
+ case 30:
fmt = DRM_FORMAT_XRGB2101010;
- else
+ break;
+ case 32:
fmt = DRM_FORMAT_ARGB;
+ break;
+ default:
+ break;
+ }
break;
+
default:
- DRM_ERROR("bad bpp, assuming x8r8g8b8 pixel format\n");
- fmt = DRM_FORMAT_XRGB;
break;
}
diff --git a/drivers/gpu/drm/drm_framebuffer.c
b/drivers/gpu/drm/drm_framebuffer.c
index 781af1d42d76..636f626c5828 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -112,12 +112,17 @@ int drm_mode_addfb(struct drm_device *dev, struct
drm_mode_fb_cmd *or,
struct drm_mode_fb_cmd2 r = {};
int ret;
+ r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
+ if (r.pixel_format == DRM_FORMAT_INVALID) {
+ DRM_DEBUG("bad (bpp:%d, depth:%d)\n", or->bpp, or->depth);
+ return -EINVAL;
+ }
+
/* convert to new format and call new ioctl */
r.fb_id = or->fb_id;
r.width = or->width;
r.height = or->height;
r.pitches[0] = or->pitch;
- r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
r.handles[0] = or->handle;
if (r.pixel_format == DRM_FORMAT_XRGB2101010 &&
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9ae16a..139632b87181 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -71,6 +71,9 @@ extern "C" {
#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of
little endian */
+/* Reserve 0 for the invalid format specifier */
+#define DRM_FORMAT_INVALID 0
+
/* color index */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
--
2.19.0.rc2
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Re: [Intel-gfx] [PATCH 6/7] drm/i915: Expose RPCS (SSEU) configuration to userspace
Quoting Tvrtko Ursulin (2018-09-05 15:22:21)
> From: Chris Wilson
Now this looks nothing like my first suggestion!
I think Tvrtko should stand ad the author of the final mechanism, I
think it is substantially different from the submission method first
done by Lionel.
> We want to allow userspace to reconfigure the subslice configuration for
> its own use case. To do so, we expose a context parameter to allow
> adjustment of the RPCS register stored within the context image (and
> currently not accessible via LRI). If the context is adjusted before
> first use, the adjustment is for "free"; otherwise if the context is
> active we flush the context off the GPU (stalling all users) and forcing
> the GPU to save the context to memory where we can modify it and so
> ensure that the register is reloaded on next execution.
>
> The overhead of managing additional EU subslices can be significant,
> especially in multi-context workloads. Non-GPGPU contexts should
> preferably disable the subslices it is not using, and others should
> fine-tune the number to match their workload.
>
> We expose complete control over the RPCS register, allowing
> configuration of slice/subslice, via masks packed into a u64 for
> simplicity. For example,
>
> struct drm_i915_gem_context_param arg;
> struct drm_i915_gem_context_param_sseu sseu = { .class = 0,
> .instance = 0, };
>
> memset(, 0, sizeof(arg));
> arg.ctx_id = ctx;
> arg.param = I915_CONTEXT_PARAM_SSEU;
> arg.value = (uintptr_t)
> if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, ) == 0) {
> sseu.packed.subslice_mask = 0;
>
> drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, );
> }
>
> could be used to disable all subslices where supported.
>
> v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
>
> v3: Add ability to program this per engine (Chris)
>
> v4: Move most get_sseu() into i915_gem_context.c (Lionel)
>
> v5: Validate sseu configuration against the device's capabilities (Lionel)
>
> v6: Change context powergating settings through MI_SDM on kernel context
> (Chris)
>
> v7: Synchronize the requests following a powergating setting change using a
> global
> dependency (Chris)
> Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
> Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
>
> v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
> s/dev_priv/i915/ (Tvrtko)
> Change uapi class/instance fields to u16 (Tvrtko)
> Bump mask fields to 64bits (Lionel)
> Don't return EPERM when dynamic sseu is disabled (Tvrtko)
>
> v9: Import context image into kernel context's ppgtt only when
> reconfiguring powergated slice/subslices (Chris)
> Use aliasing ppgtt when needed (Michel)
>
> Tvrtko Ursulin:
>
> v10:
> * Update for upstream changes.
> * Request submit needs a RPM reference.
> * Reject on !FULL_PPGTT for simplicity.
> * Pull out get/set param to helpers for readability and less indent.
> * Use i915_request_await_dma_fence in add_global_barrier to skip waits
>on the same timeline and avoid GEM_BUG_ON.
> * No need to explicitly assign a NULL pointer to engine in legacy mode.
> * No need to move gen8_make_rpcs up.
> * Factored out global barrier as prep patch.
> * Allow to only CAP_SYS_ADMIN if !Gen11.
>
> v11:
> * Remove engine vfunc in favour of local helper. (Chris Wilson)
> * Stop retiring requests before updates since it is not needed
>(Chris Wilson)
> * Implement direct CPU update path for idle contexts. (Chris Wilson)
> * Left side dependency needs only be on the same context timeline.
>(Chris Wilson)
> * It is sufficient to order the timeline. (Chris Wilson)
> * Reject !RCS configuration attempts with -ENODEV for now.
>
> v12:
> * Rebase for make_rpcs.
>
> v13:
> * Centralize SSEU normalization to make_rpcs.
> * Type width checking (uAPI <-> implementation).
> * Gen11 restrictions uAPI checks.
> * Gen11 subslice count differences handling.
> Chris Wilson:
> * args->size handling fixes.
> * Update context image from GGTT.
> * Postpone context image update to pinning.
> * Use i915_gem_active_raw instead of last_request_on_engine.
>
> v14:
> * Add activity tracker on intel_context to fix the lifetime issues
>and simplify the code. (Chris Wilson)
>
> v15:
> * Fix context pin leak if no space in ring by simplifying the
>context pinning sequence.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
> Issue: https://github.com/intel/media-driver/issues/267
> Signed-off-by: Chris Wilson
> Signed-off-by: Lionel Landwerlin
> Cc: Dmitry Rogozhkin
> Cc: Tvrtko Ursulin
> Cc: Zhipeng Gong
> Cc: Joonas Lahtinen
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 303 +++-
>
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/amdgpu: Remove default best_encoder hook from DC
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC URL : https://patchwork.freedesktop.org/series/49194/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/amdgpu: Remove default best_encoder hook from DC -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3035:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3826:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3826:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3830:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3830:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3937:58: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3012:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3803:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3803:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3807:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3807:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3914:58: warning: Using plain integer as NULL pointer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/amdgpu: Remove default best_encoder hook from DC
== Series Details == Series: drm/amdgpu: Remove default best_encoder hook from DC URL : https://patchwork.freedesktop.org/series/49194/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0e61c0665c52 drm/amdgpu: Remove default best_encoder hook from DC -:58: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 35 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/7] drm/i915: Add timeline barrier support
Quoting Tvrtko Ursulin (2018-09-05 15:22:20) > From: Tvrtko Ursulin > > Timeline barrier allows serialization between different timelines. > > After calling i915_timeline_set_barrier with a request, all following > submissions on this timeline will be set up as depending on this request, > or barrier. Once the barrier has been completed it automatically gets > cleared and things continue as normal. > > This facility will be used by the upcoming context SSEU code. > > v2: > * Assert barrier has been retired on timeline_fini. (Chris Wilson) > * Fix mock_timeline. > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Chris Wilson > Cc: Chris Wilson Reviewed-by: Chris Wilson I really should follow through on my threat to move switch_to_kernel_context over to a similar scheme. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/amdgpu: Remove default best_encoder hook from DC
For atomic driver this is the default, no need to reimplement it. We
still need to keep the copypasta for not-atomic drivers though, since
no one polished the legacy crtc helpers as much as the atomic ones.
Signed-off-by: Daniel Vetter
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Andrey Grodzovsky
Cc: Tony Cheng
Cc: "Leo (Sunpeng) Li"
Cc: Shirish S
---
Stand-alone submission because our CI says this kills kbl-g somewhere in
the amdgpu.ko load path, and I just don't see why.
-Daniel
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index af6adffba788..333f9904f135 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2794,28 +2794,6 @@ static const struct drm_connector_funcs
amdgpu_dm_connector_funcs = {
.atomic_get_property = amdgpu_dm_connector_atomic_get_property
};
-static struct drm_encoder *best_encoder(struct drm_connector *connector)
-{
- int enc_id = connector->encoder_ids[0];
- struct drm_mode_object *obj;
- struct drm_encoder *encoder;
-
- DRM_DEBUG_DRIVER("Finding the best encoder\n");
-
- /* pick the encoder ids */
- if (enc_id) {
- obj = drm_mode_object_find(connector->dev, NULL, enc_id,
DRM_MODE_OBJECT_ENCODER);
- if (!obj) {
- DRM_ERROR("Couldn't find a matching encoder for our
connector\n");
- return NULL;
- }
- encoder = obj_to_encoder(obj);
- return encoder;
- }
- DRM_ERROR("No encoder id\n");
- return NULL;
-}
-
static int get_modes(struct drm_connector *connector)
{
return amdgpu_dm_connector_get_modes(connector);
@@ -2934,7 +2912,6 @@ amdgpu_dm_connector_helper_funcs = {
*/
.get_modes = get_modes,
.mode_valid = amdgpu_dm_connector_mode_valid,
- .best_encoder = best_encoder
};
static void dm_crtc_helper_disable(struct drm_crtc *crtc)
--
2.19.0.rc1
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Re: [Intel-gfx] [PATCH 4/7] drm/i915/perf: lock powergating configuration to default when active
Quoting Tvrtko Ursulin (2018-09-05 15:22:19)
> -static u32 make_rpcs(struct drm_i915_private *dev_priv,
> -struct intel_sseu *ctx_sseu)
> +u32 gen8_make_rpcs(struct drm_i915_private *dev_priv,
> + struct intel_sseu *req_sseu)
Should we retrospectively make this const?
(And anychance for a s/dev_priv/i915?)
> {
> const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
> bool subslice_pg = sseu->has_subslice_pg;
> - u8 slices = hweight8(ctx_sseu->slice_mask);
> - u8 subslices = hweight8(ctx_sseu->subslice_mask);
> + struct intel_sseu ctx_sseu;
> + u8 slices, subslices;
> u32 rpcs = 0;
>
> + /*
> +* If i915/perf is active, we want a stable powergating configuration
> +* on the system. The most natural configuration to take in that case
> +* is the default (i.e maximum the hardware can do).
> +*/
> + if (unlikely(dev_priv->perf.oa.exclusive_stream))
> + ctx_sseu = intel_device_default_sseu(dev_priv);
> + else
> + ctx_sseu = *req_sseu;
:(
I'm not sure if I can suggest anything better, but this does feel like a
layering violation.
It makes sense which makes it only feel worse.
-Chris
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Record the sseu configuration per-context & engine
Quoting Tvrtko Ursulin (2018-09-05 15:22:18)
> From: Chris Wilson
>
> We want to expose the ability to reconfigure the slices, subslice and
> eu per context and per engine. To facilitate that, store the current
> configuration on the context for each engine, which is initially set
> to the device default upon creation.
>
> v2: record sseu configuration per context & engine (Chris)
>
> v3: introduce the i915_gem_context_sseu to store powergating
> programming, sseu_dev_info has grown quite a bit (Lionel)
>
> v4: rename i915_gem_sseu into intel_sseu (Chris)
> use to_intel_context() (Chris)
>
> v5: More to_intel_context() (Tvrtko)
> Switch intel_sseu from union to struct (Tvrtko)
> Move context default sseu in existing loop (Chris)
>
> v6: s/intel_sseu_from_device_sseu/intel_device_default_sseu/ (Tvrtko)
>
> Tvrtko Ursulin:
>
> v7:
> * Pass intel_sseu by pointer instead of value to make_rpcs.
> * Rebase for make_rpcs changes.
>
> v8:
> * Rebase for RPCS edit on pin.
>
> v9:
> * Rebase for context image setup changes.
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Lionel Landwerlin
> Signed-off-by: Tvrtko Ursulin
I feel this is substantially different (since I just outlined a v1!) to
merit a
Reviewed-by: Chris Wilson
and probably deserves a different author. I think Lionel is still the
principle author here, but Tvrtko has done a lot of refactoring and
integrating in the new scheme.
> -static u32 make_rpcs(struct drm_i915_private *dev_priv);
> +static u32 make_rpcs(struct drm_i915_private *dev_priv,
> +struct intel_sseu *ctx_sseu);
>
> static struct intel_context *
> __execlists_context_pin(struct intel_engine_cs *engine,
> @@ -1349,7 +1350,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
> /* RPCS */
> if (engine->class == RENDER_CLASS) {
> ce->lrc_reg_state[CTX_R_PWR_CLK_STATE + 1] =
> - make_rpcs(engine->i915);
> + make_rpcs(engine->i915, >sseu);
We have different habits here; my vim config just gives this a single
tab indent beyond the incomplete line. (Was going to say it earlier ;)
-Chris
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin
Quoting Tvrtko Ursulin (2018-09-05 15:22:16) > From: Tvrtko Ursulin > > Configuring RPCS in context image just before pin is sufficient and will > come extra handy in one of the following patches. > > v2: > * Split image setup a bit differently. (Chris Wilson) > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Chris Wilson > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev2)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev2) URL : https://patchwork.freedesktop.org/series/48194/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772 -> Patchwork_10095 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/48194/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10095 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128, fdo#107139) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (54 -> 48) == Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10095 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10095: 8e7f97c0a4d7d79b7f434f2c18a1455fedfcc6a5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8e7f97c0a4d7 drm/i915/icl: Support co-existance between per-context SSEU and OA 8a0c3e82be78 drm/i915: Expose RPCS (SSEU) configuration to userspace 51555815cbdc drm/i915: Add timeline barrier support 3a30bf8ddfa7 drm/i915/perf: lock powergating configuration to default when active 377a656e5c19 drm/i915: Record the sseu configuration per-context & engine ecdf22ac2704 drm/i915: Program RPCS for Broadwell ed66235dc3a5 drm/i915/execlists: Move RPCS setup to context pin == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10095/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards.
On Mon, Aug 27, 2018 at 03:37:53PM +0300, Juha-Pekka Heikkila wrote:
> From gen11 onwards RGB565 90/270 plane rotation is supported on hardware.
>
> IGT: https://patchwork.freedesktop.org/series/48756/
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 344a16b..c245906 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -123,14 +123,17 @@ static bool intel_plane_valid_rotation(const struct
> drm_plane_state *plane_state
> }
>
> /*
> - * 90/270 is not allowed with RGB64 16:16:16:16,
> - * RGB 16-bit 5:6:5, and Indexed 8-bit.
> + * 90/270 is not allowed with RGB64 16:16:16:16 and
> + * Indexed 8-bit. RGB 16-bit. 5:6:5 is allowed gen11 onwards.
^
Extra period there
Otherwise lgtm
Reviewed-by: Ville Syrjälä
>* TBD: Add RGB64 case once its added in supported format
>* list.
>*/
> switch (plane_state->fb->format->format) {
> - case DRM_FORMAT_C8:
> case DRM_FORMAT_RGB565:
> + if (INTEL_GEN(dev_priv) >= 11)
> + break;
> + /* fall through */
> + case DRM_FORMAT_C8:
> DRM_DEBUG_KMS("Unsupported pixel format %s for
> 90/270!\n",
>
> drm_get_format_name(plane_state->fb->format->format,
> _name));
> --
> 2.7.4
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev2)
== Series Details == Series: drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl (rev2) URL : https://patchwork.freedesktop.org/series/49150/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772_full -> Patchwork_10092_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10092_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@kms_rotation_crc@primary-rotation-180: shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +9 igt@perf_pmu@rc6-runtime-pm: shard-apl: FAIL (fdo#105010) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10092 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10092: a45f2f453a4c5c43baad34e27142bd73f27063dd @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10092/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per context dynamic (sub)slice power-gating (rev2)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev2) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/execlists: Move RPCS setup to context pin Okay! Commit: drm/i915: Program RPCS for Broadwell Okay! Commit: drm/i915: Record the sseu configuration per-context & engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3688:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3702:16: warning: expression using sizeof(void) Commit: drm/i915/perf: lock powergating configuration to default when active Okay! Commit: drm/i915: Add timeline barrier support Okay! Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace +drivers/gpu/drm/i915/intel_lrc.c:2543:25: warning: expression using sizeof(void) Commit: drm/i915/icl: Support co-existance between per-context SSEU and OA Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev2)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev2) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim checkpatch origin/drm-tip ed66235dc3a5 drm/i915/execlists: Move RPCS setup to context pin ecdf22ac2704 drm/i915: Program RPCS for Broadwell 377a656e5c19 drm/i915: Record the sseu configuration per-context & engine 3a30bf8ddfa7 drm/i915/perf: lock powergating configuration to default when active 51555815cbdc drm/i915: Add timeline barrier support 8a0c3e82be78 drm/i915: Expose RPCS (SSEU) configuration to userspace -:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #40: v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) total: 0 errors, 1 warnings, 0 checks, 441 lines checked 8e7f97c0a4d7 drm/i915/icl: Support co-existance between per-context SSEU and OA -:4: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'? #4: Subject: [PATCH] drm/i915/icl: Support co-existance between per-context SSEU total: 0 errors, 1 warnings, 0 checks, 33 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation
== Series Details == Series: series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation URL : https://patchwork.freedesktop.org/series/49187/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4772 -> Patchwork_10094 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49187/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10094 that come from known issues: === IGT changes === Issues hit igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: PASS -> FAIL (fdo#103841) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#107139, fdo#105128) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_psr@primary_page_flip: fi-cnl-psr: FAIL (fdo#107336) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (54 -> 48) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u == Build changes == * Linux: CI_DRM_4772 -> Patchwork_10094 CI_DRM_4772: 1351ee8f3aacdb8f4a71cd17a7035556065c59a9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4629: c3b6d69aa3dd2d1a6c1f2e787670a0aef78f2ea5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10094: 4c81281ccea1630983a24df1e6af060e8d69e2fe @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4c81281ccea1 drm/i915: Move final cleanup of drm_i915_private to i915_driver_destroy 418a878462ee drm/i915: Attach the pci match data to the device upon creation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10094/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Reject unknown legacy bpp and depth for drm_mode_addfb ioctl
On Wed, Sep 05, 2018 at 11:22:05AM +0100, Chris Wilson wrote:
> Since this is handling user provided bpp and depth, we need to sanity
> check and propagate the EINVAL back rather than assume what the insane
> client intended and fill the logs with DRM_ERROR.
>
> v2: Check both bpp and depth match the builtin pixel format, and
> introduce a canonical DRM_FORMAT_INVALID to reserve 0 against any future
> fourcc.
>
> Testcase: igt/kms_addfb_basic/legacy-format
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
I checked a bunch of randomly selected userspace pieces, and if there's
hairy stuff going on then it's mis-selected bpp.
> ---
> drivers/gpu/drm/drm_fourcc.c | 33 +--
> drivers/gpu/drm/drm_framebuffer.c | 7 ++-
> include/uapi/drm/drm_fourcc.h | 3 +++
> 3 files changed, 32 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 35c1e2742c27..d9dadbc43327 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -45,32 +45,45 @@ static char printable_char(int c)
> */
> uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
> {
> - uint32_t fmt;
> + uint32_t fmt = DRM_FORMAT_INVALID;
>
> switch (bpp) {
> case 8:
> - fmt = DRM_FORMAT_C8;
> + if (depth == 0)
> + fmt = DRM_FORMAT_C8;
Michel Dänzer thinks this should be depth == 8 here. I grepped around in
-modesetting, seems outright not supported. Apparently amd drivers do
support it, and set 8/8. With that addressed:
Reviewed-by: Daniel Vetter
> break;
> case 16:
> - if (depth == 15)
> + switch (depth) {
> + case 15:
> fmt = DRM_FORMAT_XRGB1555;
> - else
> + break;
> + case 16:
> fmt = DRM_FORMAT_RGB565;
> + break;
> + default:
> + break;
> + }
> break;
> case 24:
> - fmt = DRM_FORMAT_RGB888;
> + if (depth == 24)
> + fmt = DRM_FORMAT_RGB888;
> break;
> case 32:
> - if (depth == 24)
> + switch (depth) {
> + case 24:
> fmt = DRM_FORMAT_XRGB;
> - else if (depth == 30)
> + break;
> + case 30:
> fmt = DRM_FORMAT_XRGB2101010;
> - else
> + break;
> + case 32:
> fmt = DRM_FORMAT_ARGB;
> + break;
> + default:
> + break;
> + }
> break;
> default:
> - DRM_ERROR("bad bpp, assuming x8r8g8b8 pixel format\n");
> - fmt = DRM_FORMAT_XRGB;
> break;
> }
>
> diff --git a/drivers/gpu/drm/drm_framebuffer.c
> b/drivers/gpu/drm/drm_framebuffer.c
> index 781af1d42d76..636f626c5828 100644
> --- a/drivers/gpu/drm/drm_framebuffer.c
> +++ b/drivers/gpu/drm/drm_framebuffer.c
> @@ -112,12 +112,17 @@ int drm_mode_addfb(struct drm_device *dev, struct
> drm_mode_fb_cmd *or,
> struct drm_mode_fb_cmd2 r = {};
> int ret;
>
> + r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
> + if (r.pixel_format == DRM_FORMAT_INVALID) {
> + DRM_DEBUG("bad (bpp:%d, depth:%d)\n", or->bpp, or->depth);
> + return -EINVAL;
> + }
> +
> /* convert to new format and call new ioctl */
> r.fb_id = or->fb_id;
> r.width = or->width;
> r.height = or->height;
> r.pitches[0] = or->pitch;
> - r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
> r.handles[0] = or->handle;
>
> if (r.pixel_format == DRM_FORMAT_XRGB2101010 &&
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 2ed46e9ae16a..139632b87181 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -71,6 +71,9 @@ extern "C" {
>
> #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of
> little endian */
>
> +/* Reserve 0 for the invalid format specifier */
> +#define DRM_FORMAT_INVALID 0
> +
> /* color index */
> #define DRM_FORMAT_C8fourcc_code('C', '8', ' ', ' ') /*
> [7:0] C */
>
> --
> 2.19.0.rc1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [PATH i-g-t 1/2] headers: bump
From: Lionel Landwerlin
---
include/drm-uapi/amdgpu_drm.h | 23 ++
include/drm-uapi/drm.h | 7 +
include/drm-uapi/drm_mode.h| 22 +-
include/drm-uapi/etnaviv_drm.h | 6 +
include/drm-uapi/exynos_drm.h | 240
include/drm-uapi/i915_drm.h| 43 +++
include/drm-uapi/msm_drm.h | 2 +
include/drm-uapi/tegra_drm.h | 492 -
include/drm-uapi/vc4_drm.h | 13 +-
include/drm-uapi/virtgpu_drm.h | 1 +
10 files changed, 833 insertions(+), 16 deletions(-)
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 1816bd8200d1..78b4dd89fcb4 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -78,6 +78,12 @@ extern "C" {
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
+#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
+AMDGPU_GEM_DOMAIN_GTT | \
+AMDGPU_GEM_DOMAIN_VRAM | \
+AMDGPU_GEM_DOMAIN_GDS | \
+AMDGPU_GEM_DOMAIN_GWS | \
+AMDGPU_GEM_DOMAIN_OA)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -95,6 +101,10 @@ extern "C" {
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
/* Flag that BO sharing will be explicitly synchronized */
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC(1 << 7)
+/* Flag that indicates allocating MQD gart on GFX9, where the mtype
+ * for the second page onward should be set to NC.
+ */
+#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -520,6 +530,10 @@ union drm_amdgpu_cs {
/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
+/* The IB fence should do the L2 writeback but not invalidate any shader
+ * caches (L2/vL1/sL1/I$). */
+#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -618,6 +632,14 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_SOS 0x0c
/* Subquery id: Query PSP ASD firmware version */
#define AMDGPU_INFO_FW_ASD 0x0d
+ /* Subquery id: Query VCN firmware version */
+ #define AMDGPU_INFO_FW_VCN 0x0e
+ /* Subquery id: Query GFX RLC SRLC firmware version */
+ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
+ /* Subquery id: Query GFX RLC SRLG firmware version */
+ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
+ /* Subquery id: Query GFX RLC SRLS firmware version */
+ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
/* the used VRAM size */
@@ -806,6 +828,7 @@ struct drm_amdgpu_info_firmware {
#define AMDGPU_VRAM_TYPE_GDDR5 5
#define AMDGPU_VRAM_TYPE_HBM 6
#define AMDGPU_VRAM_TYPE_DDR3 7
+#define AMDGPU_VRAM_TYPE_DDR4 8
struct drm_amdgpu_info_device {
/** PCI Device ID */
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index f0bd91de0cf9..778a97fcfe63 100644
--- a/include/drm-uapi/drm.h
+++ b/include/drm-uapi/drm.h
@@ -674,6 +674,13 @@ struct drm_get_cap {
*/
#define DRM_CLIENT_CAP_ATOMIC 3
+/**
+ * DRM_CLIENT_CAP_ASPECT_RATIO
+ *
+ * If set to 1, the DRM core will provide aspect ratio information in modes.
+ */
+#define DRM_CLIENT_CAP_ASPECT_RATIO4
+
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 2c575794fb52..971c016b368c 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -93,6 +93,15 @@ extern "C" {
#define DRM_MODE_PICTURE_ASPECT_NONE 0
#define DRM_MODE_PICTURE_ASPECT_4_31
#define DRM_MODE_PICTURE_ASPECT_16_9 2
+#define DRM_MODE_PICTURE_ASPECT_64_27 3
+#define DRM_MODE_PICTURE_ASPECT_256_1354
+
+/* Content type options */
+#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
+#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
+#define DRM_MODE_CONTENT_TYPE_PHOTO2
+#define DRM_MODE_CONTENT_TYPE_CINEMA 3
+#define DRM_MODE_CONTENT_TYPE_GAME 4
/* Aspect ratio flag bitmask (4 bits 22:19) */
#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
@@ -102,6 +111,10 @@ extern "C" {
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
#define DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
+#define DRM_MODE_FLAG_PIC_AR_64_27 \
+
[Intel-gfx] [PATH i-g-t 2/2] tests: add slice power programming test
From: Lionel Landwerlin
Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
before Cannonlake.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
v3: Rename to gem_ctx_rpcs (Lionel)
v4: Update kernel API (Lionel)
Add 0 value test (Lionel)
Exercise invalid values (Lionel)
v5: Add perf tests (Lionel)
v6: Add new sysfs entry tests (Lionel)
v7: Test rsvd fields
Update for kernel series changes
v8: Drop test_no_sseu_support() test (Kelvin)
Drop drm_intel_*() apis (Chris)
v9: by Chris:
Drop all do_ioctl/do_ioctl_err()
Use gem_context_[gs]et_param()
Use gem_read() instead of mapping memory
by Lionel:
Test dynamic sseu on/off more
Tvrtko Ursulin:
v10:
* Various style tweaks and refactorings.
* New test coverage.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
---
tests/Makefile.am |1 +
tests/Makefile.sources |1 +
tests/gem_ctx_param.c |4 +-
tests/gem_ctx_sseu.c | 1040
tests/meson.build |7 +
5 files changed, 1052 insertions(+), 1 deletion(-)
create mode 100644 tests/gem_ctx_sseu.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index ee5a7c5e83b8..6b67bd2cc17a 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -107,6 +107,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index c84933f1d971..f8f2c8d67d72 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -56,6 +56,7 @@ TESTS_progs = \
gem_ctx_exec \
gem_ctx_isolation \
gem_ctx_param \
+ gem_ctx_sseu \
gem_ctx_switch \
gem_ctx_thrash \
gem_double_irq_loop \
diff --git a/tests/gem_ctx_param.c b/tests/gem_ctx_param.c
index c46fd709b0d7..af1afeaa2f2f 100644
--- a/tests/gem_ctx_param.c
+++ b/tests/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
set_priority(fd);
}
+ /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first.
*/
- arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+ arg.param = I915_CONTEXT_PARAM_SSEU + 1;
igt_subtest("invalid-param-get") {
arg.ctx_id = ctx;
diff --git a/tests/gem_ctx_sseu.c b/tests/gem_ctx_sseu.c
new file mode 100644
index ..1f816818e3de
--- /dev/null
+++ b/tests/gem_ctx_sseu.c
@@ -0,0 +1,1040 @@
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Lionel Landwerlin
+ *
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt_dummyload.h"
+#include "igt_perf.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test context render powergating programming.");
+
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+
+#define MI_SET_PREDICATE (0x1 << 23)
+#define MI_SET_PREDICATE_NOOP_NEVER (0)
+#define MI_SET_PREDICATE_NOOP_RESULT2_CLEAR (1)
+#define MI_SET_PREDICATE_NOOP_RESULT2_SET (2)
+#define MI_SET_PREDICATE_NOOP_RESULT_CLEAR (3)
+#define MI_SET_PREDICATE_NOOP_RESULT_SET(4)
+#define
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation
== Series Details == Series: series starting with [1/2] drm/i915: Attach the pci match data to the device upon creation URL : https://patchwork.freedesktop.org/series/49187/ State : warning == Summary == $ dim checkpatch origin/drm-tip 418a878462ee drm/i915: Attach the pci match data to the device upon creation -:84: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #84: FILE: drivers/gpu/drm/i915/i915_drv.c:1353: + BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); total: 0 errors, 1 warnings, 0 checks, 107 lines checked 4c81281ccea1 drm/i915: Move final cleanup of drm_i915_private to i915_driver_destroy ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATH i-g-t 0/2] Per context dynamic (sub)slice power-gating
From: Tvrtko Ursulin Some tests for the corresponding i915 series. I dropped the benchmark for now but plan to bring it back later. Lionel Landwerlin (2): headers: bump tests: add slice power programming test include/drm-uapi/amdgpu_drm.h | 23 + include/drm-uapi/drm.h |7 + include/drm-uapi/drm_mode.h| 22 +- include/drm-uapi/etnaviv_drm.h |6 + include/drm-uapi/exynos_drm.h | 240 include/drm-uapi/i915_drm.h| 43 ++ include/drm-uapi/msm_drm.h |2 + include/drm-uapi/tegra_drm.h | 492 ++- include/drm-uapi/vc4_drm.h | 13 +- include/drm-uapi/virtgpu_drm.h |1 + tests/Makefile.am |1 + tests/Makefile.sources |1 + tests/gem_ctx_param.c |4 +- tests/gem_ctx_sseu.c | 1040 tests/meson.build |7 + 15 files changed, 1885 insertions(+), 17 deletions(-) create mode 100644 tests/gem_ctx_sseu.c -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915: Expose RPCS (SSEU) configuration to userspace
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
first use, the adjustment is for "free"; otherwise if the context is
active we flush the context off the GPU (stalling all users) and forcing
the GPU to save the context to memory where we can modify it and so
ensure that the register is reloaded on next execution.
The overhead of managing additional EU subslices can be significant,
especially in multi-context workloads. Non-GPGPU contexts should
preferably disable the subslices it is not using, and others should
fine-tune the number to match their workload.
We expose complete control over the RPCS register, allowing
configuration of slice/subslice, via masks packed into a u64 for
simplicity. For example,
struct drm_i915_gem_context_param arg;
struct drm_i915_gem_context_param_sseu sseu = { .class = 0,
.instance = 0, };
memset(, 0, sizeof(arg));
arg.ctx_id = ctx;
arg.param = I915_CONTEXT_PARAM_SSEU;
arg.value = (uintptr_t)
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, ) == 0) {
sseu.packed.subslice_mask = 0;
drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, );
}
could be used to disable all subslices where supported.
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
v3: Add ability to program this per engine (Chris)
v4: Move most get_sseu() into i915_gem_context.c (Lionel)
v5: Validate sseu configuration against the device's capabilities (Lionel)
v6: Change context powergating settings through MI_SDM on kernel context (Chris)
v7: Synchronize the requests following a powergating setting change using a
global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
s/dev_priv/i915/ (Tvrtko)
Change uapi class/instance fields to u16 (Tvrtko)
Bump mask fields to 64bits (Lionel)
Don't return EPERM when dynamic sseu is disabled (Tvrtko)
v9: Import context image into kernel context's ppgtt only when
reconfiguring powergated slice/subslices (Chris)
Use aliasing ppgtt when needed (Michel)
Tvrtko Ursulin:
v10:
* Update for upstream changes.
* Request submit needs a RPM reference.
* Reject on !FULL_PPGTT for simplicity.
* Pull out get/set param to helpers for readability and less indent.
* Use i915_request_await_dma_fence in add_global_barrier to skip waits
on the same timeline and avoid GEM_BUG_ON.
* No need to explicitly assign a NULL pointer to engine in legacy mode.
* No need to move gen8_make_rpcs up.
* Factored out global barrier as prep patch.
* Allow to only CAP_SYS_ADMIN if !Gen11.
v11:
* Remove engine vfunc in favour of local helper. (Chris Wilson)
* Stop retiring requests before updates since it is not needed
(Chris Wilson)
* Implement direct CPU update path for idle contexts. (Chris Wilson)
* Left side dependency needs only be on the same context timeline.
(Chris Wilson)
* It is sufficient to order the timeline. (Chris Wilson)
* Reject !RCS configuration attempts with -ENODEV for now.
v12:
* Rebase for make_rpcs.
v13:
* Centralize SSEU normalization to make_rpcs.
* Type width checking (uAPI <-> implementation).
* Gen11 restrictions uAPI checks.
* Gen11 subslice count differences handling.
Chris Wilson:
* args->size handling fixes.
* Update context image from GGTT.
* Postpone context image update to pinning.
* Use i915_gem_active_raw instead of last_request_on_engine.
v14:
* Add activity tracker on intel_context to fix the lifetime issues
and simplify the code. (Chris Wilson)
v15:
* Fix context pin leak if no space in ring by simplifying the
context pinning sequence.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Issue: https://github.com/intel/media-driver/issues/267
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Cc: Dmitry Rogozhkin
Cc: Tvrtko Ursulin
Cc: Zhipeng Gong
Cc: Joonas Lahtinen
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 303 +++-
drivers/gpu/drm/i915/i915_gem_context.h | 6 +
drivers/gpu/drm/i915/intel_lrc.c| 4 +-
include/uapi/drm/i915_drm.h | 43
4 files changed, 353 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ca2c8fcd1090..aa1f34e63080 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
#include
#include "i915_drv.h"
#include "i915_trace.h"
[Intel-gfx] [PATCH 3/7] drm/i915: Record the sseu configuration per-context & engine
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration per context & engine (Chris)
v3: introduce the i915_gem_context_sseu to store powergating
programming, sseu_dev_info has grown quite a bit (Lionel)
v4: rename i915_gem_sseu into intel_sseu (Chris)
use to_intel_context() (Chris)
v5: More to_intel_context() (Tvrtko)
Switch intel_sseu from union to struct (Tvrtko)
Move context default sseu in existing loop (Chris)
v6: s/intel_sseu_from_device_sseu/intel_device_default_sseu/ (Tvrtko)
Tvrtko Ursulin:
v7:
* Pass intel_sseu by pointer instead of value to make_rpcs.
* Rebase for make_rpcs changes.
v8:
* Rebase for RPCS edit on pin.
v9:
* Rebase for context image setup changes.
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 14 +
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
drivers/gpu/drm/i915/i915_gem_context.h | 4
drivers/gpu/drm/i915/i915_request.h | 10 ++
drivers/gpu/drm/i915/intel_lrc.c| 26 -
5 files changed, 43 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 767615ecdea5..e4682fc572e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3449,6 +3449,20 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)_priv->info;
}
+static inline struct intel_sseu
+intel_device_default_sseu(struct drm_i915_private *i915)
+{
+ const struct sseu_dev_info *sseu = _INFO(i915)->sseu;
+ struct intel_sseu value = {
+ .slice_mask = sseu->slice_mask,
+ .subslice_mask = sseu->subslice_mask[0],
+ .min_eus_per_subslice = sseu->max_eus_per_subslice,
+ .max_eus_per_subslice = sseu->max_eus_per_subslice,
+ };
+
+ return value;
+}
+
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 747b8170a15a..ca2c8fcd1090 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -343,6 +343,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct intel_context *ce = >__engine[n];
ce->gem_context = ctx;
+ /* Use the whole device by default */
+ ce->sseu = intel_device_default_sseu(dev_priv);
}
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index e09673ca731d..79d2e8f62ad1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -31,6 +31,7 @@
#include "i915_gem.h"
#include "i915_scheduler.h"
+#include "intel_device_info.h"
struct pid;
@@ -165,6 +166,9 @@ struct i915_gem_context {
int pin_count;
const struct intel_context_ops *ops;
+
+ /** sseu: Control eu/slice partitioning */
+ struct intel_sseu sseu;
} __engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 9898301ab7ef..eb6f8cce16c4 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -39,6 +39,16 @@ struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+/*
+ * Powergating configuration for a particular (context,engine).
+ */
+struct intel_sseu {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 min_eus_per_subslice;
+ u8 max_eus_per_subslice;
+};
+
struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3bdc1ac3e926..8a477e43dbca 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1305,7 +1305,8 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32 make_rpcs(struct drm_i915_private *dev_priv);
+static u32 make_rpcs(struct drm_i915_private *dev_priv,
+struct intel_sseu *ctx_sseu);
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
@@ -1349,7 +1350,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
/* RPCS */
if (engine->class == RENDER_CLASS) {
[Intel-gfx] [PATCH 7/7] drm/i915/icl: Support co-existance between per-context SSEU and OA
From: Tvrtko Ursulin
When OA is active we want to lock the powergating configuration, but on
Icelake users like media stack will have issues if we lock to the full
device configuration.
Instead lock to a subset of (sub)slices which are currently a known
working configuration for all users.
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3c85392a3109..19c9c46308e5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2502,13 +2502,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *dev_priv,
/*
* If i915/perf is active, we want a stable powergating configuration
-* on the system. The most natural configuration to take in that case
-* is the default (i.e maximum the hardware can do).
+* on the system.
+*
+* We could choose full enablement, but on ICL we know there are use
+* cases which disable slices for functional, apart for performance
+* reasons. So in this case we select a known stable subset.
*/
- if (unlikely(dev_priv->perf.oa.exclusive_stream))
- ctx_sseu = intel_device_default_sseu(dev_priv);
- else
+ if (!dev_priv->perf.oa.exclusive_stream) {
ctx_sseu = *req_sseu;
+ } else {
+ ctx_sseu = intel_device_default_sseu(dev_priv);
+
+ if (IS_GEN11(dev_priv)) {
+ /*
+* We only need subslice count so it doesn't matter
+* which ones we select - just turn of low bits in the
+* amount of half of all available subslices per slice.
+*/
+ ctx_sseu.subslice_mask =
+ ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
+ ctx_sseu.slice_mask = 0x1;
+ }
+ }
slices = hweight8(ctx_sseu.slice_mask);
subslices = hweight8(ctx_sseu.subslice_mask);
--
2.17.1
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[Intel-gfx] [PATCH 2/7] drm/i915: Program RPCS for Broadwell
From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the configuration to userspace and may want to opt out of the "always-enabled" setting. Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 358fad63564c..3bdc1ac3e926 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2501,13 +2501,6 @@ make_rpcs(struct drm_i915_private *dev_priv) u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); u32 rpcs = 0; - /* -* No explicit RPCS request is needed to ensure full -* slice/subslice/EU enablement prior to Gen9. - */ - if (INTEL_GEN(dev_priv) < 9) - return 0; - /* * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits * wide and Icelake has up to eight subslices, specfial programming is -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11 0/7] Per context dynamic (sub)slice power-gating
From: Tvrtko Ursulin Updated series after continuing Lionel's work. Userspace for the feature is the media-driver project on GitHub. Please see https://github.com/intel/media-driver/pull/271/commits. No headline changes this time. Some review feedback, some refactoring, some patches got merged and two new appeared to help with the simplified implementation and also lock SSEU config to a workable set on Icelake. IGT to be sent separately. Chris Wilson (3): drm/i915: Program RPCS for Broadwell drm/i915: Record the sseu configuration per-context & engine drm/i915: Expose RPCS (SSEU) configuration to userspace Lionel Landwerlin (1): drm/i915/perf: lock powergating configuration to default when active Tvrtko Ursulin (3): drm/i915/execlists: Move RPCS setup to context pin drm/i915: Add timeline barrier support drm/i915/icl: Support co-existance between per-context SSEU and OA drivers/gpu/drm/i915/i915_drv.h | 14 + drivers/gpu/drm/i915/i915_gem_context.c | 305 +- drivers/gpu/drm/i915/i915_gem_context.h | 10 + drivers/gpu/drm/i915/i915_perf.c | 5 + drivers/gpu/drm/i915/i915_request.c | 13 + drivers/gpu/drm/i915/i915_request.h | 10 + drivers/gpu/drm/i915/i915_timeline.c | 3 + drivers/gpu/drm/i915/i915_timeline.h | 27 ++ drivers/gpu/drm/i915/intel_lrc.c | 65 ++-- drivers/gpu/drm/i915/intel_lrc.h | 3 + .../gpu/drm/i915/selftests/mock_timeline.c| 2 + include/uapi/drm/i915_drm.h | 43 +++ 12 files changed, 479 insertions(+), 21 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin
From: Tvrtko Ursulin
Configuring RPCS in context image just before pin is sufficient and will
come extra handy in one of the following patches.
v2:
* Split image setup a bit differently. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b1f0e5211a0..358fad63564c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1305,6 +1305,8 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
+static u32 make_rpcs(struct drm_i915_private *dev_priv);
+
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
@@ -1344,6 +1346,12 @@ __execlists_context_pin(struct intel_engine_cs *engine,
GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
+ /* RPCS */
+ if (engine->class == RENDER_CLASS) {
+ ce->lrc_reg_state[CTX_R_PWR_CLK_STATE + 1] =
+ make_rpcs(engine->i915);
+ }
+
ce->state->obj->pin_global++;
i915_gem_context_get(ctx);
return ce;
@@ -2706,8 +2714,7 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
- CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev_priv));
+ CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
i915_oa_init_reg_state(engine, ctx, regs);
}
--
2.17.1
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[Intel-gfx] [PATCH 4/7] drm/i915/perf: lock powergating configuration to default when active
From: Lionel Landwerlin
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.
Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.
Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active. There is no known issue with this apart from a performance
penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from affecting the
programming so it doesn't sound completely unreasonable to hold on
powergating for the same reason.
v2: Leave RPCS programming in intel_lrc.c (Lionel)
v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
More to_intel_context() (Tvrtko)
s/dev_priv/i915/ (Tvrtko)
Tvrtko Ursulin:
v4:
* Rebase for make_rpcs changes.
v5:
* Apply OA restriction from make_rpcs directly.
v6:
* Rebase for context image setup changes.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 30 --
drivers/gpu/drm/i915/intel_lrc.h | 3 +++
3 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ccb20230df2c..dd65b72bddd4 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1677,6 +1677,11 @@ static void gen8_update_reg_state_unlocked(struct
i915_gem_context *ctx,
CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
+
+ CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+ gen8_make_rpcs(dev_priv,
+ _intel_context(ctx,
+dev_priv->engine[RCS])->sseu));
}
/*
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8a477e43dbca..9709c1fbe836 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1305,9 +1305,6 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32 make_rpcs(struct drm_i915_private *dev_priv,
-struct intel_sseu *ctx_sseu);
-
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
@@ -1350,7 +1347,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
/* RPCS */
if (engine->class == RENDER_CLASS) {
ce->lrc_reg_state[CTX_R_PWR_CLK_STATE + 1] =
- make_rpcs(engine->i915, >sseu);
+ gen8_make_rpcs(engine->i915, >sseu);
}
ce->state->obj->pin_global++;
@@ -2494,15 +2491,28 @@ int logical_xcs_ring_init(struct intel_engine_cs
*engine)
return logical_ring_init(engine);
}
-static u32 make_rpcs(struct drm_i915_private *dev_priv,
-struct intel_sseu *ctx_sseu)
+u32 gen8_make_rpcs(struct drm_i915_private *dev_priv,
+ struct intel_sseu *req_sseu)
{
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
bool subslice_pg = sseu->has_subslice_pg;
- u8 slices = hweight8(ctx_sseu->slice_mask);
- u8 subslices = hweight8(ctx_sseu->subslice_mask);
+ struct intel_sseu ctx_sseu;
+ u8 slices, subslices;
u32 rpcs = 0;
+ /*
+* If i915/perf is active, we want a stable powergating configuration
+* on the system. The most natural configuration to take in that case
+* is the default (i.e maximum the hardware can do).
+*/
+ if (unlikely(dev_priv->perf.oa.exclusive_stream))
+ ctx_sseu = intel_device_default_sseu(dev_priv);
+ else
+ ctx_sseu = *req_sseu;
+
+ slices = hweight8(ctx_sseu.slice_mask);
+ subslices =
