Re: [Intel-gfx] [PATCH 5/7] drm/i915/gen11: Program the chroma upsampler for HDR planes.
Op 21-09-18 om 20:53 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 07:39:43PM +0200, Maarten Lankhorst wrote:
>> We configure the chroma upsampler with the same chroma siting as
>> used by the scaler for consistency, the chroma upsampler is used
>> instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 22 ++
>> drivers/gpu/drm/i915/intel_sprite.c | 22 ++
>> 2 files changed, 44 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 1b59d15aaf59..b614a06b66c4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6560,6 +6560,19 @@ enum {
>> #define _PLANE_AUX_DIST_2_A 0x702c0
>> #define _PLANE_AUX_OFFSET_1_A 0x701c4
>> #define _PLANE_AUX_OFFSET_2_A 0x702c4
>> +#define _PLANE_CUS_CTL_1_A 0x701c8
>> +#define _PLANE_CUS_CTL_2_A 0x702c8
>> +#define PLANE_CUS_ENABLE (1 << 31)
>> +#define PLANE_CUS_PLANE_6 (0 << 30)
>> +#define PLANE_CUS_PLANE_7 (1 << 30)
>> +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
>> +#define PLANE_CUS_HPHASE_0 (0 << 16)
>> +#define PLANE_CUS_HPHASE_0_25 (1 << 16)
>> +#define PLANE_CUS_HPHASE_0_5 (2 << 16)
>> +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
>> +#define PLANE_CUS_VPHASE_0 (0 << 12)
>> +#define PLANE_CUS_VPHASE_0_25 (1 << 12)
>> +#define PLANE_CUS_VPHASE_0_5 (2 << 12)
>> #define _PLANE_COLOR_CTL_1_A0x701CC /* GLK+ */
>> #define _PLANE_COLOR_CTL_2_A0x702CC /* GLK+ */
>> #define _PLANE_COLOR_CTL_3_A0x703CC /* GLK+ */
>> @@ -6697,6 +6710,15 @@ enum {
>> #define PLANE_AUX_OFFSET(pipe, plane) \
>> _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
>>
>> +#define _PLANE_CUS_CTL_1_B 0x711c8
>> +#define _PLANE_CUS_CTL_2_B 0x712c8
>> +#define _PLANE_CUS_CTL_1(pipe) \
>> +_PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
>> +#define _PLANE_CUS_CTL_2(pipe) \
>> +_PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
>> +#define PLANE_CUS_CTL(pipe, plane) \
>> +_MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
>> +
>> #define _PLANE_COLOR_CTL_1_B0x711CC
>> #define _PLANE_COLOR_CTL_2_B0x712CC
>> #define _PLANE_COLOR_CTL_3_B0x713CC
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 111d72a5d5a0..c4e05b0b60bf 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -358,6 +358,7 @@ skl_update_plane(struct intel_plane *plane,
>> uint32_t y = plane_state->color_plane[0].y;
>> uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>> uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
>> +struct intel_plane *linked = plane_state->linked_plane;
>> unsigned long irqflags;
>>
>> /* Sizes are 0 based */
>> @@ -385,6 +386,27 @@ skl_update_plane(struct intel_plane *plane,
>>(plane_state->color_plane[1].y << 16) |
>>plane_state->color_plane[1].x);
>>
>> +if (icl_is_hdr_plane(plane)) {
>> +u32 cus_ctl = 0;
>> +
>> +if (linked) {
>> +/* Enable and use MPEG-2 chroma siting */
>> +cus_ctl = PLANE_CUS_ENABLE |
>> +PLANE_CUS_HPHASE_0 |
>> +PLANE_CUS_VPHASE_SIGN_NEGATIVE |
>> +PLANE_CUS_VPHASE_0_25;
> Or vphase=-0.5 and hphase=-0.25 maybe? That would be consistent
> with the phase we program into the normal scaler. But maybe the
> cus considers works differently?
Just following what the documentation says in PLANE_CUS_CTL..
YUV 420 Chroma Siting
Left (MPEG-2): Hphase: 0, Vphase: -0.25
>> +
>> +if (linked->id == PLANE_SPRITE5)
>> +cus_ctl |= PLANE_CUS_PLANE_7;
>> +else if (linked->id == PLANE_SPRITE4)
>> +cus_ctl |= PLANE_CUS_PLANE_6;
> PLANE_CUS_SOMETHING(plane) ?
Considered it, but the field is a bool. So it doesn't work like that.
I rather explicitly add the MISSING_CASE() and not hide the fact you can't use
an arbitrary plane in there.
>> +else
>> +MISSING_CASE(linked->id);
>> +}
>> +
>> +I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
>> +}
>> +
>> /* program plane scaler */
>> if (plane_state-
Re: [Intel-gfx] [PATCH 4/7] drm/i915/gen11: Program the scalers correctly for planar formats.
Op 21-09-18 om 20:45 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
>> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
>> upsampler to upscale YUV420 to YUV444 and the scaler should only be
>> used for upscaling. Because of this we shouldn't program the scalers
>> in planar mode if NV12 and the chroma upsampler are used. Instead
>> program the scalers like on normal planes.
>>
>> Sprite 2 and 3 have no dedicated scaler, and need to program the
>> selected Y plane in the scaler mode.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_atomic.c | 6 +-
>> drivers/gpu/drm/i915/intel_display.c | 30
>> drivers/gpu/drm/i915/intel_drv.h | 8
>> drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
>> 5 files changed, 34 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index e7e6ca7f9665..1b59d15aaf59 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6872,6 +6872,8 @@ enum {
>> #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
>> #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
>> #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
>> +#define PS_PLANE_Y_SEL_MASK (7 << 5)
>> +#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
>>
>> #define _PS_PWR_GATE_1A 0x68160
>> #define _PS_PWR_GATE_2A 0x68260
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
>> b/drivers/gpu/drm/i915/intel_atomic.c
>> index 20bfc89c652c..3c240ad0a8d3 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -235,9 +235,13 @@ static void intel_atomic_setup_scaler(struct
>> intel_crtc_scaler_state *scaler_sta
>> if (INTEL_GEN(dev_priv) == 9 &&
>> !IS_GEMINILAKE(dev_priv))
>> mode = SKL_PS_SCALER_MODE_NV12;
>> -else
>> +else if
>> (!icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
>> mode = PS_SCALER_MODE_PLANAR;
>>
>> +if (plane_state->linked_plane)
>> +mode |=
>> PS_PLANE_Y_SEL(plane_state->linked_plane->id);
>> +} else
>> +mode = PS_SCALER_MODE_PACKED;
>> } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
>> mode = PS_SCALER_MODE_PACKED;
>> } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 19cd6bbb43c4..cea91235d498 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4833,8 +4833,7 @@ static int
>> skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>>unsigned int scaler_user, int *scaler_id,
>>int src_w, int src_h, int dst_w, int dst_h,
>> - bool plane_scaler_check,
>> - uint32_t pixel_format)
>> + const struct drm_format_info *format, bool need_scaling)
>> {
>> struct intel_crtc_scaler_state *scaler_state =
>> &crtc_state->scaler_state;
>> @@ -4843,18 +4842,14 @@ skl_update_scaler(struct intel_crtc_state
>> *crtc_state, bool force_detach,
>> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>> const struct drm_display_mode *adjusted_mode =
>> &crtc_state->base.adjusted_mode;
>> -int need_scaling;
>>
>> /*
>> * Src coordinates are already rotated by 270 degrees for
>> * the 90/270 degree plane rotation cases (to match the
>> * GTT mapping), hence no need to account for rotation here.
>> */
>> -need_scaling = src_w != dst_w || src_h != dst_h;
>> -
>> -if (plane_scaler_check)
>> -if (pixel_format == DRM_FORMAT_NV12)
>> -need_scaling = true;
>> +if (src_w != dst_w || src_h != dst_h)
>> +need_scaling = true;
>>
>> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>> need_scaling = true;
>> @@ -4895,7 +4890,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
>> bool force_detach,
>> return 0;
>> }
>>
>> -if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
>> +if (format && format->format == DRM_FORMAT_NV12 &&
>> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
>> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>> return -EINVAL;
>> @@ -4943,7 +4938,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state
>> *state)
>> &state->scaler_state.scaler_id,
>> state->pipe_src_w, state->pipe_src_h,
>> adjusted_mode->crtc_hdisplay,
>> -
Re: [Intel-gfx] [PATCH 12/40] drm/i915/execlists: Assert the queue is non-empty on unsubmitting
On 19/09/2018 20:55, Chris Wilson wrote: In the sequence <0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset: engine_mask=1, ret=0, retry=0 <0>[ 531.960431] drv_self-48067 527402571us : execlists_reset: rcs0 request global=115de, current=71133 How such a unbelievably huge delta between the guilty request and hws? <0>[ 531.960431] drv_self-48067d..1 527402571us : execlists_cancel_port_requests: rcs0:port0 global=71134 (fence 826b:198), (current 71133) <0>[ 531.960431] drv_self-48067d..1 527402572us : execlists_cancel_port_requests: rcs0:port1 global=71135 (fence 826c:53), (current 71133) <0>[ 531.960431] drv_self-48067d..1 527402572us : __i915_request_unsubmit: rcs0 fence 826c:53 <- global=71135, current 71133 <0>[ 531.960431] drv_self-48067d..1 527402579us : __i915_request_unsubmit: rcs0 fence 826b:198 <- global=71134, current 71133 <0>[ 531.960431] drv_self-48067 527402613us : intel_engine_cancel_stop_cs: rcs0 <0>[ 531.960431] drv_self-48067 527402624us : execlists_reset_finish: rcs0 we are missing the execlists_submission_tasklet() invocation before the execlists_reset_fini() implying that either the queue is empty, or we failed to schedule and run the tasklet on finish. Add an assert so we are sure that on unsubmitting the incomplete request after reset, the queue is indeed populated. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3edb417caa7b..e8de250c3413 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -344,6 +344,7 @@ static void __unwind_incomplete_requests(struct intel_engine_cs *engine) last_prio = rq_prio(rq); p = lookup_priolist(engine, last_prio); } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(p->priority != rq_prio(rq)); list_add(&rq->sched.link, &p->requests); Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/40] drm/i915: Reserve some priority bits for internal use
On 19/09/2018 20:55, Chris Wilson wrote:
In the next few patches, we will want to give a small priority boost to
some requests/queues but not so much that we perturb the user controlled
order. As such we shift the user priority bits higher leaving ourselves
Prepare for shifting actually.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
a few low priority bits for our bumping.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem_context.c| 9 +
drivers/gpu/drm/i915/i915_scheduler.h | 6 ++
drivers/gpu/drm/i915/selftests/intel_lrc.c | 8 +---
4 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d4daa7412f1..b902bb96e0be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3230,7 +3230,7 @@ int i915_gem_object_wait(struct drm_i915_gem_object *obj,
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
const struct i915_sched_attr *attr);
-#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
+#define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
int __must_check
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f772593b99ab..150d7a6b2bd3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -337,7 +337,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
kref_init(&ctx->ref);
list_add_tail(&ctx->link, &dev_priv->contexts.list);
ctx->i915 = dev_priv;
- ctx->sched.priority = I915_PRIORITY_NORMAL;
+ ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
struct intel_context *ce = &ctx->__engine[n];
@@ -504,7 +504,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
}
i915_gem_context_clear_bannable(ctx);
- ctx->sched.priority = prio;
+ ctx->sched.priority = I915_USER_PRIORITY(prio);
ctx->ring_size = PAGE_SIZE;
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
@@ -879,7 +879,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev,
void *data,
args->value = i915_gem_context_is_bannable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
- args->value = ctx->sched.priority;
+ args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
break;
default:
ret = -EINVAL;
@@ -948,7 +948,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev,
void *data,
!capable(CAP_SYS_NICE))
ret = -EPERM;
else
- ctx->sched.priority = priority;
+ ctx->sched.priority =
+ I915_USER_PRIORITY(priority);
}
break;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 70a42220358d..7edfad0abfd7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -19,6 +19,12 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
+#define I915_USER_PRIORITY_SHIFT 0
+#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
+
+#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
+#define I915_PRIORITY_MASK (-I915_PRIORITY_COUNT)
+
struct i915_sched_attr {
/**
* @priority: execution and service priority
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c
b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index 1aea7a8f2224..94ceb5f6c507 100644
--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
@@ -291,12 +291,14 @@ static int live_preempt(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, i915, id) {
struct i915_request *rq;
@@ -417,7 +419,7 @@ static int live_late_preempt(void *arg)
goto err_wedged;
}
- attr.priority = I915_PRIORITY_MAX;
+ attr.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
Re: [Intel-gfx] [RFC] drm/i915: GEM_WARN_ON considered harmful
On Thu, 20 Sep 2018, Tvrtko Ursulin wrote:
> Ping!
>
> Any comments here?
>
> Main goal was to allow GEM_WARN_ON as a statement, plus also protect
> uses in if statements, which there are some who I think don't expect the
> branch to completely disappear.
I've said before I don't like the conditional early returns vanishing
depending on config options, but I've been shot down. I think this patch
is an improvement.
BR,
Jani.
>
> Regards,
>
> Tvrtko
>
> On 07/09/2018 12:53, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin
>>
>> GEM_WARN_ON currently has dangerous semantics where it is completely
>> compiled out on !GEM_DEBUG builds. This can leave users who expect it to
>> be more like a WARN_ON, just without a warning in non-debug builds, in
>> complete ignorance.
>>
>> Another gotcha with it is that it cannot be used as a statement. Which is
>> again different from a standard kernel WARN_ON.
>>
>> This patch fixes both problems by making it behave as one would expect.
>>
>> It can now be used both as an expression and as statement, and also the
>> condition evaluates properly in all builds - code under the conditional
>> will therefore not unexpectedly disappear.
>>
>> To satisfy call sites which really want the code under the conditional to
>> completely disappear, we add GEM_DEBUG_WARN_ON and convert some of the
>> callers to it. This one can also be used as both expression and statement.
>>
>> From the above it follows GEM_DEBUG_WARN_ON should be used in situations
>> where we are certain the condition will be hit during development, but at
>> a place in code where error can be handled to the benefit of not crashing
>> the machine.
>>
>> GEM_WARN_ON on the other hand should be used where condition may happen in
>> production and we just want to distinguish the level of debugging output
>> emitted between the production and debug build.
>>
>> Signed-off-by: Tvrtko Ursulin
>> Cc: Chris Wilson
>> Cc: Joonas Lahtinen
>> Cc: Matthew Auld
>> Cc: Mika Kuoppala
>> ---
>> Quickly put together and compile tested only!
>> ---
>> drivers/gpu/drm/i915/i915_gem.h | 4 +++-
>> drivers/gpu/drm/i915/i915_vma.c | 8
>> drivers/gpu/drm/i915/intel_engine_cs.c | 8
>> drivers/gpu/drm/i915/intel_lrc.c | 8
>> drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
>> 5 files changed, 16 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem.h
>> b/drivers/gpu/drm/i915/i915_gem.h
>> index 599c4f6eb1ea..b0e4b976880c 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.h
>> +++ b/drivers/gpu/drm/i915/i915_gem.h
>> @@ -47,17 +47,19 @@ struct drm_i915_private;
>> #define GEM_DEBUG_DECL(var) var
>> #define GEM_DEBUG_EXEC(expr) expr
>> #define GEM_DEBUG_BUG_ON(expr) GEM_BUG_ON(expr)
>> +#define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
>>
>> #else
>>
>> #define GEM_SHOW_DEBUG() (0)
>>
>> #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
>> -#define GEM_WARN_ON(expr) (BUILD_BUG_ON_INVALID(expr), 0)
>> +#define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
>>
>> #define GEM_DEBUG_DECL(var)
>> #define GEM_DEBUG_EXEC(expr) do { } while (0)
>> #define GEM_DEBUG_BUG_ON(expr)
>> +#define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
>> #endif
>>
>> #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
>> diff --git a/drivers/gpu/drm/i915/i915_vma.c
>> b/drivers/gpu/drm/i915/i915_vma.c
>> index 31efc971a3a8..82652c3d1bed 100644
>> --- a/drivers/gpu/drm/i915/i915_vma.c
>> +++ b/drivers/gpu/drm/i915/i915_vma.c
>> @@ -305,12 +305,12 @@ int i915_vma_bind(struct i915_vma *vma, enum
>> i915_cache_level cache_level,
>> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
>> GEM_BUG_ON(vma->size > vma->node.size);
>>
>> -if (GEM_WARN_ON(range_overflows(vma->node.start,
>> -vma->node.size,
>> -vma->vm->total)))
>> +if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
>> + vma->node.size,
>> + vma->vm->total)))
>> return -ENODEV;
>>
>> -if (GEM_WARN_ON(!flags))
>> +if (GEM_DEBUG_WARN_ON(!flags))
>> return -EINVAL;
>>
>> bind_flags = 0;
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 10cd051ba29e..8dbdb18b2668 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -273,13 +273,13 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
>> BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
>> BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
>>
>> -if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
>> +if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
>> return -EINVAL;
>>
>> -if (GEM_WARN_ON(info->instance > MAX_
Re: [Intel-gfx] [PATCH 14/40] drm/i915: Combine multiple internal plists into the same i915_priolist bucket
On 19/09/2018 20:55, Chris Wilson wrote:
As we are about to allow ourselves to slightly bump the user priority
into a few different sublevels, packthose internal priority lists
into the same i915_priolist to keep the rbtree compact and avoid having
to allocate the default user priority even after the internal bumping.
The downside to having an requests[] rather than a node per active list,
is that we then have to walk over the empty higher priority lists. To
compensate, we track the active buckets and use a small bitmap to skip
over any inactive ones.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 12 ++-
drivers/gpu/drm/i915/intel_lrc.c| 87 ++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 13 ++-
4 files changed, 80 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 217ed3ee1cab..83f2f7774c1f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1534,10 +1534,10 @@ void intel_engine_dump(struct intel_engine_cs *engine,
count = 0;
drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority);
for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
- struct i915_priolist *p =
- rb_entry(rb, typeof(*p), node);
+ struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
+ int i;
- list_for_each_entry(rq, &p->requests, sched.link) {
+ priolist_for_each_request(rq, p, i) {
if (count++ < MAX_REQUESTS_TO_SHOW - 1)
print_request(m, rq, "\t\tQ ");
else
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 6f693ef62c64..8531bd917ec3 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -726,30 +726,28 @@ static bool __guc_dequeue(struct intel_engine_cs *engine)
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
struct i915_request *rq, *rn;
+ int i;
- list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
+ priolist_for_each_request_consume(rq, rn, p, i) {
Hm consumed clears the bitmask every time, but we are not certain yet we
will consume the request.
if (last && rq->hw_context != last->hw_context) {
- if (port == last_port) {
- __list_del_many(&p->requests,
- &rq->sched.link);
+ if (port == last_port)
goto done;
- }
if (submit)
port_assign(port, last);
port++;
}
- INIT_LIST_HEAD(&rq->sched.link);
+ list_del_init(&rq->sched.link);
__i915_request_submit(rq);
trace_i915_request_in(rq, port_index(port, execlists));
+
last = rq;
submit = true;
}
rb_erase_cached(&p->node, &execlists->queue);
- INIT_LIST_HEAD(&p->requests);
if (p->priority != I915_PRIORITY_NORMAL)
kmem_cache_free(engine->i915->priorities, p);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e8de250c3413..aeae82b5223c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -259,14 +259,49 @@ intel_lr_context_descriptor_update(struct
i915_gem_context *ctx,
ce->lrc_desc = desc;
}
-static struct i915_priolist *
+static void assert_priolists(struct intel_engine_execlists * const execlists,
+int queue_priority)
+{
+ struct rb_node *rb;
+ int last_prio, i;
+
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ GEM_BUG_ON(rb_first_cached(&execlists->queue) !=
+ rb_first(&execlists->queue.rb_root));
+
+ last_prio = (queue_priority >> I915_USER_PRIORITY_SHIFT) + 1;
>
+ for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
+ struct i915_priolist *p = to_priolist(rb);
+
+ GEM_BUG_ON(p->priority >= last_prio);
+ last_prio = p->priority;
+
+ GEM_BUG_ON(!p->used);
+ for (i = 0; i < ARRAY_SIZE(p->requests); i++) {
+ if (list_empty(&p->requests[i]))
+ continue;
Asserting that bitmask slot is not set if list is empty is
Re: [Intel-gfx] [PATCH 15/40] drm/i915: Priority boost for new clients
On 19/09/2018 20:55, Chris Wilson wrote:
Taken from an idea used for FQ_CODEL, we give the first request of a
new request flows a small priority boost. These flows are likely to
correspond with short, interactive tasks and so be more latency sensitive
than the longer free running queues. As soon as the client has more than
one request in the queue, further requests are not boosted and it settles
down into ordinary steady state behaviour. Such small kicks dramatically
help combat the starvation issue, by allowing each client the opportunity
to run even when the system is under heavy throughput load (within the
constraints of the user selected priority).
v2: Mark the preempted request as the start of a new flow, to prevent a
single client being continually gazumped by its peers.
Testcase: igt/benchmarks/rrul
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_request.c | 16 ++--
drivers/gpu/drm/i915/i915_scheduler.h | 4 +++-
drivers/gpu/drm/i915/intel_lrc.c | 25 +++--
3 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a492385b2089..56140ca054e8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1127,8 +1127,20 @@ void i915_request_add(struct i915_request *request)
*/
local_bh_disable();
rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(request, &request->gem_context->sched);
+ if (engine->schedule) {
+ struct i915_sched_attr attr = request->gem_context->sched;
+
+ /*
+* Boost priorities to new clients (new request flows).
+*
+* Allow interactive/synchronous clients to jump ahead of
+* the bulk clients. (FQ_CODEL)
+*/
+ if (!prev || i915_request_completed(prev))
+ attr.priority |= I915_PRIORITY_NEWCLIENT;
+
+ engine->schedule(request, &attr);
+ }
rcu_read_unlock();
i915_sw_fence_commit(&request->submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7edfad0abfd7..93e43e263d8c 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -19,12 +19,14 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 0
+#define I915_USER_PRIORITY_SHIFT 1
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (-I915_PRIORITY_COUNT)
+#define I915_PRIORITY_NEWCLIENT ((u8)BIT(0))
Is the cast important and why?
+
struct i915_sched_attr {
/**
* @priority: execution and service priority
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index aeae82b5223c..ee9a656e549c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -363,9 +363,9 @@ static void unwind_wa_tail(struct i915_request *rq)
static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
{
- struct i915_request *rq, *rn;
+ struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int last_prio = I915_PRIORITY_INVALID;
+ int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
lockdep_assert_held(&engine->timeline.lock);
@@ -373,19 +373,32 @@ static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
&engine->timeline.requests,
link) {
if (i915_request_completed(rq))
- return;
+ break;
__i915_request_unsubmit(rq);
unwind_wa_tail(rq);
GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != last_prio) {
- last_prio = rq_prio(rq);
- pl = lookup_priolist(engine, last_prio);
+ if (rq_prio(rq) != prio) {
+ prio = rq_prio(rq);
+ pl = lookup_priolist(engine, prio);
}
GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
list_add(&rq->sched.link, pl);
+
+ active = rq;
+ }
+
+ /*
+* The active request is now effectively the start of a new client
+* stream, so give it the equivalent small priority bump to prevent
+* it being gazumped a second time by another peer.
+*/
+ if (!(prio & I915_PRIORITY_NEWCLIENT)) {
+ prio |= I915_PRIORITY_NEWC
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2)
== Series Details ==
Series: drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2)
URL : https://patchwork.freedesktop.org/series/42923/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4867 -> Patchwork_10261 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/42923/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_10261 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s3:
fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
{fi-skl-caroline}: PASS -> INCOMPLETE (fdo#107556, fdo#104108)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
== Participating hosts (46 -> 42) ==
Additional (1): fi-kbl-soraka
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4867 -> Patchwork_10261
CI_DRM_4867: d3bc4f8ea48e074e21aac5dbd0805630ecea9b65 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10261: c3f83dcadc38bd1212e596388aa861326f843d14 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c3f83dcadc38 drm/i915/dp: optimize eDP 1.4+ link config fast and narrow
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10261/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Match code to comment and enforce ppgtt for execlists
Quoting Chris Wilson (2018-09-22 17:18:03) > Our execlist dispatch code requires a ppGTT so make sure we enforce that > option in intel_sanitize_enable_ppgtt(). The comment already tries to > explain that execlists requires ppgtt, but was written when gen8 may > have also taken the legacy path; so rewrite the code to match the > comment by using HAS_EXECLISTS() feature instead of the gen. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/40] drm/i915: Pull scheduling under standalone lock
On 19/09/2018 20:55, Chris Wilson wrote:
Currently, the backend scheduling code abuses struct_mutex into order to
have a global lock to manipulate a temporary list (without widespread
allocation) and to protect against list modifications. This is an
extraneous coupling to struct_mutex and further can not extend beyond
the local device.
Pull all the code that needs to be under the one true lock into
i915_scheduler.c, and make it so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_request.c | 85 --
drivers/gpu/drm/i915/i915_request.h | 8 -
drivers/gpu/drm/i915/i915_scheduler.c | 377
drivers/gpu/drm/i915/i915_scheduler.h | 25 ++
drivers/gpu/drm/i915/intel_display.c| 3 +-
drivers/gpu/drm/i915/intel_lrc.c| 268 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +-
8 files changed, 411 insertions(+), 361 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5794f102f9b8..ef1480c14e4e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -75,6 +75,7 @@ i915-y += i915_cmd_parser.o \
i915_gemfs.o \
i915_query.o \
i915_request.o \
+ i915_scheduler.o \
i915_timeline.o \
i915_trace_points.o \
i915_vma.o \
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 56140ca054e8..d73ad490a261 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -111,91 +111,6 @@ i915_request_remove_from_client(struct i915_request
*request)
spin_unlock(&file_priv->mm.lock);
}
-static struct i915_dependency *
-i915_dependency_alloc(struct drm_i915_private *i915)
-{
- return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
-}
-
-static void
-i915_dependency_free(struct drm_i915_private *i915,
-struct i915_dependency *dep)
-{
- kmem_cache_free(i915->dependencies, dep);
-}
-
-static void
-__i915_sched_node_add_dependency(struct i915_sched_node *node,
-struct i915_sched_node *signal,
-struct i915_dependency *dep,
-unsigned long flags)
-{
- INIT_LIST_HEAD(&dep->dfs_link);
- list_add(&dep->wait_link, &signal->waiters_list);
- list_add(&dep->signal_link, &node->signalers_list);
- dep->signaler = signal;
- dep->flags = flags;
-}
-
-static int
-i915_sched_node_add_dependency(struct drm_i915_private *i915,
- struct i915_sched_node *node,
- struct i915_sched_node *signal)
-{
- struct i915_dependency *dep;
-
- dep = i915_dependency_alloc(i915);
- if (!dep)
- return -ENOMEM;
-
- __i915_sched_node_add_dependency(node, signal, dep,
-I915_DEPENDENCY_ALLOC);
- return 0;
-}
-
-static void
-i915_sched_node_fini(struct drm_i915_private *i915,
-struct i915_sched_node *node)
-{
- struct i915_dependency *dep, *tmp;
-
- GEM_BUG_ON(!list_empty(&node->link));
-
- /*
-* Everyone we depended upon (the fences we wait to be signaled)
-* should retire before us and remove themselves from our list.
-* However, retirement is run independently on each timeline and
-* so we may be called out-of-order.
-*/
- list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) {
- GEM_BUG_ON(!i915_sched_node_signaled(dep->signaler));
- GEM_BUG_ON(!list_empty(&dep->dfs_link));
-
- list_del(&dep->wait_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(i915, dep);
- }
-
- /* Remove ourselves from everyone who depends upon us */
- list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) {
- GEM_BUG_ON(dep->signaler != node);
- GEM_BUG_ON(!list_empty(&dep->dfs_link));
-
- list_del(&dep->signal_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(i915, dep);
- }
-}
-
-static void
-i915_sched_node_init(struct i915_sched_node *node)
-{
- INIT_LIST_HEAD(&node->signalers_list);
- INIT_LIST_HEAD(&node->waiters_list);
- INIT_LIST_HEAD(&node->link);
- node->attr.priority = I915_PRIORITY_INVALID;
-}
-
static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
{
struct intel_engine_cs *engine;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 7fa94b024968..5f7361e0fca6 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
Re: [Intel-gfx] [PATCH 17/40] drm/i915: Priority boost for waiting clients
On 19/09/2018 20:55, Chris Wilson wrote:
Latency is in the eye of the beholder. In the case where a client stops
and waits for the gpu, give that request chain a small priority boost
(not so that it overtakes higher priority clients, to preserve the
external ordering) so that ideally the wait completes earlier.
Testcase: igt/gem_sync/switch-default
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Dmitry Rogozhkin
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++-
drivers/gpu/drm/i915/i915_request.c | 2 ++
drivers/gpu/drm/i915/i915_request.h | 5 ++--
drivers/gpu/drm/i915/i915_scheduler.c | 34 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 5 +++-
5 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6b347ffb996b..2fa75f2a1980 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1748,6 +1748,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
*/
err = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_PRIORITY |
(write_domain ? I915_WAIT_ALL : 0),
MAX_SCHEDULE_TIMEOUT,
to_rps_client(file));
@@ -3749,7 +3750,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
start = ktime_get();
ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_PRIORITY |
+ I915_WAIT_ALL,
to_wait_timeout(args->timeout_ns),
to_rps_client(file));
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index d73ad490a261..abd4dacbab8e 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1237,6 +1237,8 @@ long i915_request_wait(struct i915_request *rq,
add_wait_queue(errq, &reset);
intel_wait_init(&wait);
+ if (flags & I915_WAIT_PRIORITY)
+ i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
restart:
do {
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 5f7361e0fca6..90e9d170a0cd 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -277,8 +277,9 @@ long i915_request_wait(struct i915_request *rq,
__attribute__((nonnull(1)));
#define I915_WAIT_INTERRUPTIBLE BIT(0)
#define I915_WAIT_LOCKED BIT(1) /* struct_mutex held, handle GPU reset */
-#define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */
-#define I915_WAIT_FOR_IDLE_BOOST BIT(3)
+#define I915_WAIT_PRIORITY BIT(2) /* small priority bump for the request */
+#define I915_WAIT_ALL BIT(3) /* used by i915_gem_object_wait() */
+#define I915_WAIT_FOR_IDLE_BOOST BIT(4)
static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
u32 seqno);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 910ac7089596..1423088dceff 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -239,7 +239,8 @@ sched_lock_engine(struct i915_sched_node *node, struct
intel_engine_cs *locked)
return engine;
}
-void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr)
+static void __i915_schedule(struct i915_request *rq,
+ const struct i915_sched_attr *attr)
{
struct list_head *uninitialized_var(pl);
struct intel_engine_cs *engine, *last;
@@ -248,6 +249,8 @@ void i915_schedule(struct i915_request *rq, const struct
i915_sched_attr *attr)
const int prio = attr->priority;
LIST_HEAD(dfs);
+ /* Needed in order to use the temporary link inside i915_dependency */
+ lockdep_assert_held(&schedule_lock);
GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
if (i915_request_completed(rq))
@@ -256,9 +259,6 @@ void i915_schedule(struct i915_request *rq, const struct
i915_sched_attr *attr)
if (prio <= READ_ONCE(rq->sched.attr.priority))
return;
- /* Needed in order to use the temporary link inside i915_dependency */
- spin_lock(&schedule_lock);
-
stack.signaler = &rq->sched;
list_add(&stack.dfs_link, &dfs);
@@ -312,7 +312,7 @@ void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr)
rq->sched.attr = *attr;
if (stack.dfs_link.next == stack.dfs_link.prev)
- goto out_unlock;
+
[Intel-gfx] [PATCH 1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9
Requirement to clear forcewake bits is for all gen9. Update
the wa comment to reflect that.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 3ad302c66254..9f11c51baae8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1403,7 +1403,7 @@ static void intel_uncore_fw_domains_init(struct
drm_i915_private *dev_priv)
dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
dev_priv->uncore.fw_clear = 0;
} else {
- /* WaRsClearFWBitsAtReset:bdw,skl */
+ /* WaRsClearFWBitsAtFLR:bdw,skl,bxt,kbl,glk,cfl */
dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0x);
dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
dev_priv->uncore.fw_clear =
_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
--
2.17.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915/gen9: WaRsDoubleRc6WrlWithCoarsePowerGating is for all gen9
We used to enable this for skl only, but it is for all gen9.
Cc: Tom O'Rourke
Cc: Akash Goel
Cc: Sagar Arun Kamble
Cc: Alex Dai
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db9b8328275..330bbd41eff1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6899,10 +6899,10 @@ static void gen9_enable_rc6(struct drm_i915_private
*dev_priv)
if (INTEL_GEN(dev_priv) >= 10) {
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
- } else if (IS_SKYLAKE(dev_priv)) {
+ } else if (IS_GEN9(dev_priv)) {
/*
-* WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
-* when CPG is enabled
+* WaRsDoubleRc6WrlWithCoarsePowerGating:skl,bxt,kbl,glk,cfl
+* Doubling WRL only when CPG is enabled
*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
} else {
--
2.17.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2)
== Series Details == Series: drm/i915/dp: optimize eDP 1.4+ link config fast and narrow (rev2) URL : https://patchwork.freedesktop.org/series/42923/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4867_full -> Patchwork_10261_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10261_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10261_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10261_full: === IGT changes === Warnings igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: shard-apl: PASS -> SKIP +13 igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS igt@pm_rc6_residency@rc6-accuracy: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10261_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106886) igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) +3 igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +13 igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-glk: NOTRUN -> DMESG-WARN (fdo#107956) +7 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +2 shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: NOTRUN -> FAIL (fdo#105454, fdo#106509) igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: NOTRUN -> DMESG-WARN (fdo#105763, fdo#106538) igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: PASS -> DMESG-WARN (fdo#103558) igt@kms_setmode@basic: shard-glk: NOTRUN -> FAIL (fdo#99912) shard-snb: NOTRUN -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-kbl: NOTRUN -> FAIL (fdo#100047) Possible fixes igt@gem_exec_big: shard-hsw: TIMEOUT (fdo#107937) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4867 -> Patchwork_10261 CI_DRM_4867: d3bc4f8ea48e074e21aac5dbd0805630ecea9b65 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10261: c3f83dcadc38bd1212e596388aa861326f843d14 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10261/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/40] drm/i915: Report the number of closed vma held by each context in debugfs
On 19/09/2018 20:55, Chris Wilson wrote:
Include the total size of closed vma when reporting the per_ctx_stats of
debugfs/i915_gem_objects.
Why do we need/want this?
Whilst adjusting the context tracking, note that we can simply use our
list of contexts in i915->contexts rather than circumlocute via
dev->filelist and the per-file context idr.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 113 +++-
1 file changed, 42 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ac75bc10afa..6b5cc30f3e09 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -302,6 +302,7 @@ struct file_stats {
u64 total, unbound;
u64 global, shared;
u64 active, inactive;
+ u64 closed;
};
static int per_file_stats(int id, void *ptr, void *data)
@@ -336,6 +337,9 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->active += vma->node.size;
else
stats->inactive += vma->node.size;
+
+ if (i915_vma_is_closed(vma))
+ stats->closed += vma->node.size;
We can have closed and active?
}
return 0;
@@ -343,7 +347,7 @@ static int per_file_stats(int id, void *ptr, void *data)
#define print_file_stats(m, name, stats) do { \
if (stats.count) \
- seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound)\n", \
+ seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \
name, \
stats.count, \
stats.total, \
@@ -351,7 +355,8 @@ static int per_file_stats(int id, void *ptr, void *data)
stats.inactive, \
stats.global, \
stats.shared, \
- stats.unbound); \
+ stats.unbound, \
+ stats.closed); \
} while (0)
static void print_batch_pool_stats(struct seq_file *m,
@@ -377,44 +382,44 @@ static void print_batch_pool_stats(struct seq_file *m,
print_file_stats(m, "[k]batch pool", stats);
}
-static int per_file_ctx_stats(int idx, void *ptr, void *data)
+static void print_context_stats(struct seq_file *m,
+ struct drm_i915_private *i915)
{
- struct i915_gem_context *ctx = ptr;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- for_each_engine(engine, ctx->i915, id) {
- struct intel_context *ce = to_intel_context(ctx, engine);
+ struct file_stats kstats = {};
+ struct i915_gem_context *ctx;
- if (ce->state)
- per_file_stats(0, ce->state->obj, data);
- if (ce->ring)
- per_file_stats(0, ce->ring->vma->obj, data);
- }
+ list_for_each_entry(ctx, &i915->contexts.list, link) {
+ struct file_stats stats = { .file_priv = ctx->file_priv };
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
- return 0;
-}
+ for_each_engine(engine, i915, id) {
+ struct intel_context *ce = to_intel_context(ctx,
engine);
-static void print_context_stats(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = &dev_priv->drm;
- struct file_stats stats;
- struct drm_file *file;
+ if (ce->state)
+ per_file_stats(0, ce->state->obj, &kstats);
+ if (ce->ring)
+ per_file_stats(0, ce->ring->vma->obj, &kstats);
+ }
- memset(&stats, 0, sizeof(stats));
+ if (!IS_ERR_OR_NULL(stats.file_priv)) {
+ struct drm_file *file = stats.file_priv->file;
+ struct task_struct *task;
- mutex_lock(&dev->struct_mutex);
- if (dev_priv->kernel_context)
- per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
+ spin_lock(&file->table_lock);
+ idr_for_each(&file->object_idr, per_file_stats, &stats);
Headache inducing diff.. however, doesn't this over-account objects on
the account of walking the same file from multiple-contexts?
+ spin_unlock(&file->table_lock);
- list_for_each_entry(file, &dev->filelist, lhead) {
- struct drm_i915_file_private *fpriv = file->driver_priv;
- idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
+ rcu_read_lock();
+ task = pid_task(ctx->pid ?:
Re: [Intel-gfx] [PATCH 19/40] drm/i915: Remove debugfs/i915_ppgtt_info
On 19/09/2018 20:55, Chris Wilson wrote:
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 119
1 file changed, 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6b5cc30f3e09..39f319c49def 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2035,124 +2035,6 @@ static int i915_swizzle_info(struct seq_file *m, void
*data)
return 0;
}
-static int per_file_ctx(int id, void *ptr, void *data)
-{
- struct i915_gem_context *ctx = ptr;
- struct seq_file *m = data;
- struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
-
- if (!ppgtt) {
- seq_printf(m, " no ppgtt for context %d\n",
- ctx->user_handle);
- return 0;
- }
-
- if (i915_gem_context_is_default(ctx))
- seq_puts(m, " default context:\n");
- else
- seq_printf(m, " context %d:\n", ctx->user_handle);
- ppgtt->debug_dump(ppgtt, m);
-
- return 0;
-}
-
-static void gen8_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int i;
-
- if (!ppgtt)
- return;
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- for (i = 0; i < 4; i++) {
- u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
- pdp <<= 32;
- pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
- seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
- }
- }
-}
-
-static void gen6_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (IS_GEN6(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- if (IS_GEN7(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n",
- I915_READ(RING_MODE_GEN7(engine)));
- seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE(engine)));
- seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE_READ(engine)));
- seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
- I915_READ(RING_PP_DIR_DCLV(engine)));
- }
- if (dev_priv->mm.aliasing_ppgtt) {
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-
- seq_puts(m, "aliasing PPGTT:\n");
- seq_printf(m, "pd gtt offset: 0x%08x\n",
ppgtt->pd.base.ggtt_offset);
-
- ppgtt->debug_dump(ppgtt, m);
- }
-
- seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
-}
-
-static int i915_ppgtt_info(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = &dev_priv->drm;
- struct drm_file *file;
- int ret;
-
- mutex_lock(&dev->filelist_mutex);
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- goto out_unlock;
-
- intel_runtime_pm_get(dev_priv);
-
- if (INTEL_GEN(dev_priv) >= 8)
- gen8_ppgtt_info(m, dev_priv);
- else if (INTEL_GEN(dev_priv) >= 6)
- gen6_ppgtt_info(m, dev_priv);
-
- list_for_each_entry_reverse(file, &dev->filelist, lhead) {
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct task_struct *task;
-
- task = get_pid_task(file->pid, PIDTYPE_PID);
- if (!task) {
- ret = -ESRCH;
- goto out_rpm;
- }
- seq_printf(m, "\nproc: %s\n", task->comm);
- put_task_struct(task);
- idr_for_each(&file_priv->context_idr, per_file_ctx,
-(void *)(unsigned long)m);
- }
-
-out_rpm:
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev->struct_mutex);
-out_unlock:
- mutex_unlock(&dev->filelist_mutex);
- return ret;
-}
-
static int count_irq_waiters(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
@@ -4741,7 +4623,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_c
Re: [Intel-gfx] [PATCH 22/40] drm/i915: Syntatic sugar for using intel_runtime_pm
On 19/09/2018 20:55, Chris Wilson wrote:
Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.
Interesting and tempting but I cannot shake the feeling it is maybe
going a bit too far. We could add with_lock, with_mutex,
with_runtime_pm_and_lock and where does it end? :) Don't know.. ping
some more people on this one I guess.
Regards,
Tvrtko
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 163 --
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 44 ++---
drivers/gpu/drm/i915/i915_pmu.c | 7 +-
drivers/gpu/drm/i915/i915_sysfs.c | 7 +-
drivers/gpu/drm/i915/intel_drv.h | 8 +
drivers/gpu/drm/i915/intel_guc_log.c | 26 ++-
drivers/gpu/drm/i915/intel_huc.c | 7 +-
drivers/gpu/drm/i915/intel_panel.c| 18 +-
drivers/gpu/drm/i915/intel_uncore.c | 30 ++--
drivers/gpu/drm/i915/selftests/i915_gem.c | 34 ++--
.../gpu/drm/i915/selftests/i915_gem_context.c | 12 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 11 +-
.../drm/i915/selftests/intel_workarounds.c| 12 +-
15 files changed, 193 insertions(+), 219 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index dbfe4e456d97..98fa216d19bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -952,9 +952,9 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
struct i915_gpu_state *gpu;
intel_wakeref_t wakeref;
- wakeref = intel_runtime_pm_get(i915);
- gpu = i915_capture_gpu_state(i915);
- intel_runtime_pm_put(i915, wakeref);
+ gpu = NULL;
+ with_intel_runtime_pm(i915, wakeref)
+ gpu = i915_capture_gpu_state(i915);
if (!gpu)
return -ENOMEM;
@@ -1015,9 +1015,8 @@ i915_next_seqno_set(void *data, u64 val)
if (ret)
return ret;
- wakeref = intel_runtime_pm_get(dev_priv);
- ret = i915_gem_set_global_seqno(dev, val);
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref)
+ ret = i915_gem_set_global_seqno(dev, val);
mutex_unlock(&dev->struct_mutex);
@@ -1305,17 +1304,15 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
return 0;
}
- wakeref = intel_runtime_pm_get(dev_priv);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ for_each_engine(engine, dev_priv, id) {
+ acthd[id] = intel_engine_get_active_head(engine);
+ seqno[id] = intel_engine_get_seqno(engine);
+ }
- for_each_engine(engine, dev_priv, id) {
- acthd[id] = intel_engine_get_active_head(engine);
- seqno[id] = intel_engine_get_seqno(engine);
+ intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
}
- intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
-
- intel_runtime_pm_put(dev_priv, wakeref);
-
if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
seq_printf(m, "Hangcheck active, timer fires in %dms\n",
jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
@@ -1591,18 +1588,16 @@ static int i915_drpc_info(struct seq_file *m, void
*unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
- int err;
-
- wakeref = intel_runtime_pm_get(dev_priv);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- err = vlv_drpc_info(m);
- else if (INTEL_GEN(dev_priv) >= 6)
- err = gen6_drpc_info(m);
- else
- err = ironlake_drpc_info(m);
+ int err = -ENODEV;
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ err = vlv_drpc_info(m);
+ else if (INTEL_GEN(dev_priv) >= 6)
+ err = gen6_drpc_info(m);
+ else
+ err = ironlake_drpc_info(m);
+ }
return err;
}
@@ -2167,9 +2162,8 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
p = drm_seq_file_printer(m);
intel_uc_fw_dump(&dev_priv->huc.fw, &p);
- wakeref = intel_runtime_pm_get(dev_priv);
- seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9
== Series Details == Series: series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9 URL : https://patchwork.freedesktop.org/series/50088/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4867 -> Patchwork_10262 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50088/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10262 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774) igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 == Participating hosts (46 -> 41) == Additional (1): fi-kbl-soraka Missing(6): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4867 -> Patchwork_10262 CI_DRM_4867: d3bc4f8ea48e074e21aac5dbd0805630ecea9b65 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10262: 07abc7fb1bc3ff392c2c5822e4699c8ce7bfc7f2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 07abc7fb1bc3 drm/i915/gen9: WaRsDoubleRc6WrlWithCoarsePowerGating is for all gen9 229b324ef4ed drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10262/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Remove i915.enable_ppgtt override
Quoting Chris Wilson (2018-09-22 17:18:04) > Now that we are confident in providing full-ppgtt where supported, > remove the ability to override the context isolation. > > v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Matthew Auld > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 8624b4bdc242..28f77810bc47 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2593,9 +2593,13 @@ intel_info(const struct drm_i915_private *dev_priv) > > #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) > > -#define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) > -#define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) > -#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt > == 3) Maybe INTEL_PPGTT(dev_priv) accessor for consistency. Also, after this a mechanical patch for s/USES_PPGTT/HAS_PPGTT/ might be in place as HAS means USES, too. Looks good otherwise, but this removes the condition that GVT-g doesn't support 32-bit ppGTT. So that needs a respin. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v3.
Op 21-09-18 om 21:31 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 09:35:52PM +0300, Ville Syrjälä wrote:
>> On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
>>> To make NV12 working on icl, we need to update 2 planes simultaneously.
>>> I've chosen to do this in the CRTC step after plane validation is done,
>>> so we know what planes are (in)visible. The linked Y plane will get
>>> updated in intel_plane_update_planes_on_crtc(), by the call to
>>> update_slave, which gets the master's plane_state as argument.
>>>
>>> The link requires both planes for atomic_update to work,
>>> so make sure skl_ddb_add_affected_planes() adds both states.
>>>
>>> Changes since v1:
>>> - Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers.
>>> - Put all the state updating login in intel_plane_atomic_check_with_state().
>>> - Clean up changes in intel_plane_atomic_check().
>>> Changes since v2:
>>> - Fix intel_atomic_get_old_plane_state() to actually return old state.
>>> - Move visibility changes to preparation patch.
>>> - Only try to find a Y plane on gen11, earlier platforms only require a
>>> single plane.
>>>
>>> Signed-off-by: Maarten Lankhorst
>>>
>>> fixup Y/UV Linkage
>>>
>>> Signed-off-by: Maarten Lankhorst
>>> ---
>>> drivers/gpu/drm/i915/intel_atomic_plane.c | 106 ++
>>> drivers/gpu/drm/i915/intel_display.c | 57
>>> drivers/gpu/drm/i915/intel_drv.h | 53 +++
>>> drivers/gpu/drm/i915/intel_pm.c | 12 ++-
>>> 4 files changed, 210 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
>>> b/drivers/gpu/drm/i915/intel_atomic_plane.c
>>> index 984bc1f26625..522699085a59 100644
>>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>>> @@ -121,7 +121,11 @@ int intel_plane_atomic_check_with_state(const struct
>>> intel_crtc_state *old_crtc_
>>> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>>> intel_state->base.visible = false;
>>>
>>> - /* If this is a cursor plane, no further checks are needed. */
>>> + /* Destroy the link */
>>> + intel_state->linked_plane = NULL;
>>> + intel_state->slave = false;
>>> +
>>> + /* If this is a cursor or Y plane, no further checks are needed. */
>>> if (!intel_state->base.crtc && !old_plane_state->base.crtc)
>>> return 0;
>>>
>>> @@ -142,27 +146,76 @@ int intel_plane_atomic_check_with_state(const struct
>>> intel_crtc_state *old_crtc_
>>>state);
>>> }
>>>
>>> -static int intel_plane_atomic_check(struct drm_plane *plane,
>>> - struct drm_plane_state *new_plane_state)
>>> +static int intel_plane_atomic_check(struct drm_plane *drm_plane,
>>> + struct drm_plane_state *new_drm_plane_state)
>>> {
>>> - struct drm_atomic_state *state = new_plane_state->state;
>>> - const struct drm_plane_state *old_plane_state =
>>> - drm_atomic_get_old_plane_state(state, plane);
>>> - struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
>>> - const struct drm_crtc_state *old_crtc_state;
>>> - struct drm_crtc_state *new_crtc_state;
>>> -
>>> - new_plane_state->visible = false;
>>> + struct intel_atomic_state *state =
>>> + to_intel_atomic_state(new_drm_plane_state->state);
>>> + struct intel_plane *plane = to_intel_plane(drm_plane);
>>> + const struct intel_plane_state *old_plane_state =
>>> + intel_atomic_get_old_plane_state(state, plane);
>>> + struct intel_plane_state *new_plane_state =
>>> + to_intel_plane_state(new_drm_plane_state);
>>> + struct intel_crtc *crtc = to_intel_crtc(
>>> + new_plane_state->base.crtc ?:
>>> + old_plane_state->base.crtc);
>>> + const struct intel_crtc_state *old_crtc_state;
>>> + struct intel_crtc_state *new_crtc_state;
>>> + struct intel_plane *linked = old_plane_state->linked_plane;
>>> + int ret;
>>> + const struct intel_plane_state *old_linked_state;
>>> + struct intel_plane_state *new_linked_state = NULL;
>>> +
>>> + if (linked) {
>>> + /*
>>> + * Make sure a previously linked plane (and implicitly, the CRTC)
>>> + * is part of the atomic commit.
>>> + */
>>> + if (!intel_atomic_get_new_plane_state(state, linked)) {
>>> + new_linked_state = intel_atomic_get_plane_state(state,
>>> linked);
>>> + if (IS_ERR(new_linked_state))
>>> + return PTR_ERR(new_linked_state);
>>> + }
>>> +
>>> + old_linked_state =
>>> + intel_atomic_get_old_plane_state(state, linked);
>>> +
>>> + /*
>>> +* This will happen when we're the Y plane. In which case
>>> +* old/new_state->crtc are both NULL. We still need to perform
>>> +* updates on the li
Re: [Intel-gfx] [PATCH 4/7] drm/i915/gen11: Program the scalers correctly for planar formats.
On Mon, Sep 24, 2018 at 10:39:54AM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 20:45 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
> >> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> >> upsampler to upscale YUV420 to YUV444 and the scaler should only be
> >> used for upscaling. Because of this we shouldn't program the scalers
> >> in planar mode if NV12 and the chroma upsampler are used. Instead
> >> program the scalers like on normal planes.
> >>
> >> Sprite 2 and 3 have no dedicated scaler, and need to program the
> >> selected Y plane in the scaler mode.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >> drivers/gpu/drm/i915/intel_atomic.c | 6 +-
> >> drivers/gpu/drm/i915/intel_display.c | 30
> >> drivers/gpu/drm/i915/intel_drv.h | 8
> >> drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
> >> 5 files changed, 34 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h
> >> index e7e6ca7f9665..1b59d15aaf59 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -6872,6 +6872,8 @@ enum {
> >> #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
> >> #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
> >> #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
> >> +#define PS_PLANE_Y_SEL_MASK (7 << 5)
> >> +#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
> >>
> >> #define _PS_PWR_GATE_1A 0x68160
> >> #define _PS_PWR_GATE_2A 0x68260
> >> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> >> b/drivers/gpu/drm/i915/intel_atomic.c
> >> index 20bfc89c652c..3c240ad0a8d3 100644
> >> --- a/drivers/gpu/drm/i915/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> >> @@ -235,9 +235,13 @@ static void intel_atomic_setup_scaler(struct
> >> intel_crtc_scaler_state *scaler_sta
> >>if (INTEL_GEN(dev_priv) == 9 &&
> >>!IS_GEMINILAKE(dev_priv))
> >>mode = SKL_PS_SCALER_MODE_NV12;
> >> - else
> >> + else if
> >> (!icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
> >>mode = PS_SCALER_MODE_PLANAR;
> >>
> >> + if (plane_state->linked_plane)
> >> + mode |=
> >> PS_PLANE_Y_SEL(plane_state->linked_plane->id);
> >> + } else
> >> + mode = PS_SCALER_MODE_PACKED;
> >>} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
> >>mode = PS_SCALER_MODE_PACKED;
> >>} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 19cd6bbb43c4..cea91235d498 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -4833,8 +4833,7 @@ static int
> >> skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> >> unsigned int scaler_user, int *scaler_id,
> >> int src_w, int src_h, int dst_w, int dst_h,
> >> -bool plane_scaler_check,
> >> -uint32_t pixel_format)
> >> +const struct drm_format_info *format, bool need_scaling)
> >> {
> >>struct intel_crtc_scaler_state *scaler_state =
> >>&crtc_state->scaler_state;
> >> @@ -4843,18 +4842,14 @@ skl_update_scaler(struct intel_crtc_state
> >> *crtc_state, bool force_detach,
> >>struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> >>const struct drm_display_mode *adjusted_mode =
> >>&crtc_state->base.adjusted_mode;
> >> - int need_scaling;
> >>
> >>/*
> >> * Src coordinates are already rotated by 270 degrees for
> >> * the 90/270 degree plane rotation cases (to match the
> >> * GTT mapping), hence no need to account for rotation here.
> >> */
> >> - need_scaling = src_w != dst_w || src_h != dst_h;
> >> -
> >> - if (plane_scaler_check)
> >> - if (pixel_format == DRM_FORMAT_NV12)
> >> - need_scaling = true;
> >> + if (src_w != dst_w || src_h != dst_h)
> >> + need_scaling = true;
> >>
> >>if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> >>need_scaling = true;
> >> @@ -4895,7 +4890,7 @@ skl_update_scaler(struct intel_crtc_state
> >> *crtc_state, bool force_detach,
> >>return 0;
> >>}
> >>
> >> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> >> + if (format && format->format == DRM_FORMAT_NV12 &&
> >>(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> >>DRM_DEBUG_KMS("NV12: src dimensions not met\n");
> >>return -EINVAL;
> >> @@ -4943,7 +4938,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state
> >> *state)
> >> &st
Re: [Intel-gfx] [PATCH 29/40] drm/i915: Differentiate between ggtt->mutex and ppgtt->mutex
On 19/09/2018 20:55, Chris Wilson wrote:
We have two classes of VM, global GTT and per-process GTT. In order to
allow ourselves the freedom to mix both along call chains, distinguish
the two classes with regards to their mutex and lockdep maps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 6 +++---
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ef38d09b6ce0..719e1ac212c1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -523,8 +523,7 @@ static void vm_free_page(struct i915_address_space *vm,
struct page *page)
spin_unlock(&vm->free_pages.lock);
}
-static void i915_address_space_init(struct i915_address_space *vm,
- struct drm_i915_private *dev_priv)
+static void i915_address_space_init(struct i915_address_space *vm, int
subclass)
{
/*
* The vm->mutex must be reclaim safe (for use in the shrinker).
@@ -532,6 +531,7 @@ static void i915_address_space_init(struct
i915_address_space *vm,
* attempt holding the lock is immediately reported by lockdep.
*/
mutex_init(&vm->mutex);
+ lockdep_set_subclass(&vm->mutex, subclass);
i915_gem_shrinker_taints_mutex(&vm->mutex);
GEM_BUG_ON(!vm->total);
@@ -1658,7 +1658,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
*/
ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
- i915_address_space_init(&ppgtt->vm, i915);
+ i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
@@ -2165,7 +2165,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
- i915_address_space_init(&ppgtt->base.vm, i915);
+ i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
@@ -3607,7 +3607,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
* and beyond the end of the GTT if we do not provide a guard.
*/
mutex_lock(&dev_priv->drm.struct_mutex);
- i915_address_space_init(&ggtt->vm, dev_priv);
+ i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
ggtt->vm.is_ggtt = true;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..849a1f67b037 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -286,6 +286,8 @@ struct i915_address_space {
bool closed;
struct mutex mutex; /* protects vma and our lists */
+#define VM_CLASS_GGTT 0
+#define VM_CLASS_PPGTT 1
struct i915_page_dma scratch_page;
struct i915_page_table *scratch_pt;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index 6ae418c76015..976c862b3842 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -70,7 +70,7 @@ mock_ppgtt(struct drm_i915_private *i915,
ppgtt->vm.total = round_down(U64_MAX, PAGE_SIZE);
ppgtt->vm.file = ERR_PTR(-ENODEV);
- i915_address_space_init(&ppgtt->vm, i915);
+ i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
ppgtt->vm.clear_range = nop_clear_range;
ppgtt->vm.insert_page = mock_insert_page;
@@ -102,6 +102,7 @@ void mock_init_ggtt(struct drm_i915_private *i915)
struct i915_ggtt *ggtt = &i915->ggtt;
ggtt->vm.i915 = i915;
+ ggtt->vm.is_ggtt = true;
ggtt->gmadr = (struct resource) DEFINE_RES_MEM(0, 2048 * PAGE_SIZE);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
@@ -117,9 +118,8 @@ void mock_init_ggtt(struct drm_i915_private *i915)
ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
ggtt->vm.vma_ops.clear_pages = clear_pages;
- i915_address_space_init(&ggtt->vm, i915);
- ggtt->vm.is_ggtt = true;
+ i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
}
void mock_fini_ggtt(struct drm_i915_private *i915)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH 5/7] drm/i915/gen11: Program the chroma upsampler for HDR planes.
On Mon, Sep 24, 2018 at 10:38:17AM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 20:53 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 07:39:43PM +0200, Maarten Lankhorst wrote:
> >> We configure the chroma upsampler with the same chroma siting as
> >> used by the scaler for consistency, the chroma upsampler is used
> >> instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 22 ++
> >> drivers/gpu/drm/i915/intel_sprite.c | 22 ++
> >> 2 files changed, 44 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h
> >> index 1b59d15aaf59..b614a06b66c4 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -6560,6 +6560,19 @@ enum {
> >> #define _PLANE_AUX_DIST_2_A 0x702c0
> >> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> >> #define _PLANE_AUX_OFFSET_2_A 0x702c4
> >> +#define _PLANE_CUS_CTL_1_A0x701c8
> >> +#define _PLANE_CUS_CTL_2_A0x702c8
> >> +#define PLANE_CUS_ENABLE (1 << 31)
> >> +#define PLANE_CUS_PLANE_6(0 << 30)
> >> +#define PLANE_CUS_PLANE_7(1 << 30)
> >> +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> >> +#define PLANE_CUS_HPHASE_0 (0 << 16)
> >> +#define PLANE_CUS_HPHASE_0_25(1 << 16)
> >> +#define PLANE_CUS_HPHASE_0_5 (2 << 16)
> >> +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
> >> +#define PLANE_CUS_VPHASE_0 (0 << 12)
> >> +#define PLANE_CUS_VPHASE_0_25(1 << 12)
> >> +#define PLANE_CUS_VPHASE_0_5 (2 << 12)
> >> #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> >> #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> >> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> >> @@ -6697,6 +6710,15 @@ enum {
> >> #define PLANE_AUX_OFFSET(pipe, plane) \
> >>_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> >>
> >> +#define _PLANE_CUS_CTL_1_B0x711c8
> >> +#define _PLANE_CUS_CTL_2_B0x712c8
> >> +#define _PLANE_CUS_CTL_1(pipe) \
> >> + _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> >> +#define _PLANE_CUS_CTL_2(pipe) \
> >> + _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> >> +#define PLANE_CUS_CTL(pipe, plane) \
> >> + _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> >> +
> >> #define _PLANE_COLOR_CTL_1_B 0x711CC
> >> #define _PLANE_COLOR_CTL_2_B 0x712CC
> >> #define _PLANE_COLOR_CTL_3_B 0x713CC
> >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >> b/drivers/gpu/drm/i915/intel_sprite.c
> >> index 111d72a5d5a0..c4e05b0b60bf 100644
> >> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >> @@ -358,6 +358,7 @@ skl_update_plane(struct intel_plane *plane,
> >>uint32_t y = plane_state->color_plane[0].y;
> >>uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >>uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >> + struct intel_plane *linked = plane_state->linked_plane;
> >>unsigned long irqflags;
> >>
> >>/* Sizes are 0 based */
> >> @@ -385,6 +386,27 @@ skl_update_plane(struct intel_plane *plane,
> >> (plane_state->color_plane[1].y << 16) |
> >> plane_state->color_plane[1].x);
> >>
> >> + if (icl_is_hdr_plane(plane)) {
> >> + u32 cus_ctl = 0;
> >> +
> >> + if (linked) {
> >> + /* Enable and use MPEG-2 chroma siting */
> >> + cus_ctl = PLANE_CUS_ENABLE |
> >> + PLANE_CUS_HPHASE_0 |
> >> + PLANE_CUS_VPHASE_SIGN_NEGATIVE |
> >> + PLANE_CUS_VPHASE_0_25;
> > Or vphase=-0.5 and hphase=-0.25 maybe? That would be consistent
> > with the phase we program into the normal scaler. But maybe the
> > cus considers works differently?
>
> Just following what the documentation says in PLANE_CUS_CTL..
I wouldn't trust the docs. They were nonsese for the normal
plane scaler too. Better verify visually.
IIRC I used a hacked version of this for the skl+ stuff:
git://github.com/vsyrjala/intel-gpu-tools.git plane_scaling_basic
>
> YUV 420 Chroma Siting
> Left (MPEG-2): Hphase: 0, Vphase: -0.25
>
> >> +
> >> + if (linked->id == PLANE_SPRITE5)
> >> + cus_ctl |= PLANE_CUS_PLANE_7;
> >> + else if (linked->id == PLANE_SPRITE4)
> >> + cus_ctl |= PLANE_CUS_PLANE_6;
> > PLAN
Re: [Intel-gfx] [PATCH 2/7] drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v3.
On Mon, Sep 24, 2018 at 02:35:13PM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 21:31 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 09:35:52PM +0300, Ville Syrjälä wrote:
> >> On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
> >>> To make NV12 working on icl, we need to update 2 planes simultaneously.
> >>> I've chosen to do this in the CRTC step after plane validation is done,
> >>> so we know what planes are (in)visible. The linked Y plane will get
> >>> updated in intel_plane_update_planes_on_crtc(), by the call to
> >>> update_slave, which gets the master's plane_state as argument.
> >>>
> >>> The link requires both planes for atomic_update to work,
> >>> so make sure skl_ddb_add_affected_planes() adds both states.
> >>>
> >>> Changes since v1:
> >>> - Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers.
> >>> - Put all the state updating login in
> >>> intel_plane_atomic_check_with_state().
> >>> - Clean up changes in intel_plane_atomic_check().
> >>> Changes since v2:
> >>> - Fix intel_atomic_get_old_plane_state() to actually return old state.
> >>> - Move visibility changes to preparation patch.
> >>> - Only try to find a Y plane on gen11, earlier platforms only require a
> >>> single plane.
> >>>
> >>> Signed-off-by: Maarten Lankhorst
> >>>
> >>> fixup Y/UV Linkage
> >>>
> >>> Signed-off-by: Maarten Lankhorst
> >>> ---
> >>> drivers/gpu/drm/i915/intel_atomic_plane.c | 106 ++
> >>> drivers/gpu/drm/i915/intel_display.c | 57
> >>> drivers/gpu/drm/i915/intel_drv.h | 53 +++
> >>> drivers/gpu/drm/i915/intel_pm.c | 12 ++-
> >>> 4 files changed, 210 insertions(+), 18 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> >>> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> >>> index 984bc1f26625..522699085a59 100644
> >>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> >>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> >>> @@ -121,7 +121,11 @@ int intel_plane_atomic_check_with_state(const struct
> >>> intel_crtc_state *old_crtc_
> >>> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> >>> intel_state->base.visible = false;
> >>>
> >>> - /* If this is a cursor plane, no further checks are needed. */
> >>> + /* Destroy the link */
> >>> + intel_state->linked_plane = NULL;
> >>> + intel_state->slave = false;
> >>> +
> >>> + /* If this is a cursor or Y plane, no further checks are needed. */
> >>> if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> >>> return 0;
> >>>
> >>> @@ -142,27 +146,76 @@ int intel_plane_atomic_check_with_state(const
> >>> struct intel_crtc_state *old_crtc_
> >>> state);
> >>> }
> >>>
> >>> -static int intel_plane_atomic_check(struct drm_plane *plane,
> >>> - struct drm_plane_state *new_plane_state)
> >>> +static int intel_plane_atomic_check(struct drm_plane *drm_plane,
> >>> + struct drm_plane_state *new_drm_plane_state)
> >>> {
> >>> - struct drm_atomic_state *state = new_plane_state->state;
> >>> - const struct drm_plane_state *old_plane_state =
> >>> - drm_atomic_get_old_plane_state(state, plane);
> >>> - struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
> >>> - const struct drm_crtc_state *old_crtc_state;
> >>> - struct drm_crtc_state *new_crtc_state;
> >>> -
> >>> - new_plane_state->visible = false;
> >>> + struct intel_atomic_state *state =
> >>> + to_intel_atomic_state(new_drm_plane_state->state);
> >>> + struct intel_plane *plane = to_intel_plane(drm_plane);
> >>> + const struct intel_plane_state *old_plane_state =
> >>> + intel_atomic_get_old_plane_state(state, plane);
> >>> + struct intel_plane_state *new_plane_state =
> >>> + to_intel_plane_state(new_drm_plane_state);
> >>> + struct intel_crtc *crtc = to_intel_crtc(
> >>> + new_plane_state->base.crtc ?:
> >>> + old_plane_state->base.crtc);
> >>> + const struct intel_crtc_state *old_crtc_state;
> >>> + struct intel_crtc_state *new_crtc_state;
> >>> + struct intel_plane *linked = old_plane_state->linked_plane;
> >>> + int ret;
> >>> + const struct intel_plane_state *old_linked_state;
> >>> + struct intel_plane_state *new_linked_state = NULL;
> >>> +
> >>> + if (linked) {
> >>> + /*
> >>> + * Make sure a previously linked plane (and implicitly, the CRTC)
> >>> + * is part of the atomic commit.
> >>> + */
> >>> + if (!intel_atomic_get_new_plane_state(state, linked)) {
> >>> + new_linked_state = intel_atomic_get_plane_state(state,
> >>> linked);
> >>> + if (IS_ERR(new_linked_state))
> >>> + return PTR_ERR(new_linked_state);
> >>> + }
> >>> +
> >>> + old_linked_state =
> >>> + intel_atomic_get_old_plane_state(state, linked);
> >>> +
> >>> + /*
> >
Re: [Intel-gfx] [PATCH 32/40] drm/i915: Introduce the i915_user_extension_method
On 19/09/2018 20:55, Chris Wilson wrote:
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked into the ioctl data only when required by the
user. The key advantage being able to ignore large control structs for
optional interfaces/extensions, while being able to process them in a
consistent manner.
In comparison to other extensible ioctls, the key difference is the
use of a linked chain of extension structs vs an array of tagged
pointers. For example,
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
__u32 length_dw;
__u64 chunk_data;
};
struct drm_amdgpu_cs_in {
__u32 ctx_id;
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u64 chunks;
};
Since verbose example of what this is better from, or at least different
than, I think an example of itself in the commit message would be preferred.
allows userspace to pass in array of pointers to extension structs, but
must therefore keep constructing that array along side the command stream.
In dynamic situations like that, a linked list is preferred and does not
similar from extra cache line misses as the extension structs themselves
s/similar/suffer/ ?
must still be loaded separate to the chunks array.
v2: Apply the tail call optimisation directly to nip the worry of stack
overflow in the bud.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_user_extensions.c | 37 +
drivers/gpu/drm/i915/i915_user_extensions.h | 20 +++
include/uapi/drm/i915_drm.h | 20 +++
4 files changed, 78 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.c
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4654ef481b45..6ffeb60392f5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -45,6 +45,7 @@ i915-y := i915_drv.o \
i915_syncmap.o \
i915_sw_fence.o \
i915_sysfs.o \
+ i915_user_extensions.o \
intel_csr.o \
intel_device_info.o \
intel_pm.o \
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c
b/drivers/gpu/drm/i915/i915_user_extensions.c
new file mode 100644
index ..00622f8ac468
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+#include
+
+#include "i915_user_extensions.h"
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data)
Should data be called base or something like that? To signify it is not
per-extension but points back to the base ioctl?
+{
+ while (ext) {
+ int err;
+ u64 x;
s/x/name/ or id?
+
+ if (get_user(x, &ext->name))
+ return -EFAULT;
+
+ err = -EINVAL;
+ if (x < count && tbl[x])
+ err = tbl[x](ext, data);
+ if (err)
+ return err;
Stopping on unknown extension or error, hm.. probably makes sense given
the context of extension use cases. Which is not like for instance the
list of query ioctls, but something really specific to each individual
base ioctl.
+
+ if (get_user(x, &ext->next_extension))
+ return -EFAULT;
+
+ ext = u64_to_user_ptr(x);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.h
b/drivers/gpu/drm/i915/i915_user_extensions.h
new file mode 100644
index ..313a510b068a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef I915_USER_EXTENSIONS_H
+#define I915_USER_EXTENSIONS_H
+
+struct i915_user_extension;
+
+typedef int (*i915_user_extension_fn)(struct i915_user_extension __user *ext,
+ void *data);
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data);
+
+#endif /* I915_USER_EXTENSIONS_H */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a4446f452040..4fa7e54501cc 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/inc
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9
== Series Details == Series: series starting with [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9 URL : https://patchwork.freedesktop.org/series/50088/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4867_full -> Patchwork_10262_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10262_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10262_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10262_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10262_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) +3 igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-glk: NOTRUN -> DMESG-WARN (fdo#107956) +7 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +2 shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: NOTRUN -> FAIL (fdo#106509, fdo#105454) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: NOTRUN -> FAIL (fdo#105363) igt@kms_setmode@basic: shard-glk: NOTRUN -> FAIL (fdo#99912) shard-kbl: PASS -> FAIL (fdo#99912) shard-snb: NOTRUN -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-kbl: NOTRUN -> FAIL (fdo#100047) Possible fixes igt@gem_exec_big: shard-hsw: TIMEOUT (fdo#107937) -> PASS igt@kms_busy@extended-pageflip-hang-newfb-render-a: shard-apl: DMESG-WARN (fdo#107956) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4867 -> Patchwork_10262 CI_DRM_4867: d3bc4f8ea48e074e21aac5dbd0805630ecea9b65 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10262: 07abc7fb1bc3ff392c2c5822e4699c8ce7bfc7f2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10262/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Check fb stride against plane max stride
On Fri, Sep 21, 2018 at 03:17:45PM -0700, Dhinakaran Pandiyan wrote:
> On Tuesday, September 18, 2018 7:02:43 AM PDT Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > commit 4e0b83a567e2 ("drm/i915: Extract per-platform plane->check()
> > functions") removed the plane max stride check for sprite planes.
> > I was going to add it back when introducing GTT remapping for the
> > display, but after further thought it seems better to re-introduce
> > it separately.
> >
> > So let's add the max stride check back. And let's do it in a nicer
> > form than what we had before and do it for all plane types (easy
> > now that we have the ->max_stride() plane vfunc).
> >
> > Only sprite planes really need this for now since primary planes
> > are capable of scanning out the current max fb size we allow, and
> > cursors have more stringent stride checks elsewhere.
> >
> > Cc: José Roberto de Souza
> > Fixes: 4e0b83a567e2 ("drm/i915: Extract per-platform plane->check()
> > functions") Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 14 ++
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_sprite.c | 22 ++
> > 3 files changed, 37 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c index eb25037d7b38..1eb99d5ec221
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3151,6 +3151,10 @@ int skl_check_plane_surface(struct intel_plane_state
> > *plane_state) plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> > rotation); plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> > rotation);
> >
> > + ret = intel_plane_check_stride(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -3286,10 +3290,15 @@ int i9xx_check_plane_surface(struct
> > intel_plane_state *plane_state) int src_x = plane_state->base.src.x1 >> 16;
> > int src_y = plane_state->base.src.y1 >> 16;
> > u32 offset;
> > + int ret;
> >
> > intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> >
> Is there a good reason to not inline the code ?
> if (color_plane[0].stride > plane->max_stride())
> return -EINVAL;
Consistency. Easier to just call a single function that does things in a
consistent fashion rather than duplicating the same check everywhere.
Also keeps the debug print consistent.
>
>
> > + ret = intel_plane_check_stride(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> >
> > if (INTEL_GEN(dev_priv) >= 4)
> > @@ -9685,10 +9694,15 @@ static int intel_cursor_check_surface(struct
> > intel_plane_state *plane_state) unsigned int rotation =
> > plane_state->base.rotation;
> > int src_x, src_y;
> > u32 offset;
> > + int ret;
> >
> > intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> >
> > + ret = intel_plane_check_stride(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > src_x = plane_state->base.src_x >> 16;
> > src_y = plane_state->base.src_y >> 16;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h index bf1c38728a59..a34c2f1f9159 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -2140,6 +2140,7 @@ unsigned int skl_plane_max_stride(struct intel_plane
> > *plane, unsigned int rotation);
> > int skl_plane_check(struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state);
> > +int intel_plane_check_stride(const struct intel_plane_state *plane_state);
> > int intel_plane_check_src_coordinates(struct intel_plane_state
> > *plane_state); int chv_plane_check_rotation(const struct intel_plane_state
> > *plane_state);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c index d4c8e10fc90b..5fd2f7bf3927
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -230,6 +230,28 @@ void intel_pipe_update_end(struct intel_crtc_state
> > *new_crtc_state) #endif
> > }
> >
> > +int intel_plane_check_stride(const struct intel_plane_state *plane_state)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + unsigned int rotation = plane_state->base.rotation;
> > + u32 stride, max_stride;
> > +
> > + /* FIXME other color planes? */
> Doesn't the color plane 0 have the max stride always?
Each color plane could have a different maximum. Depends on the hw.
Not that it's actually docu
Re: [Intel-gfx] [PATCH 11/18] drm/i915: Return the mask of enabled infoframes from ->inforame_enabled()
On Thu, Sep 20, 2018 at 09:51:38PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We want to start tracking which infoframes are enabled, so let's replace
> the boolean flag with a bitmask.
>
> We'll abstract the bitmask so that it's not platform dependent. That
> will allow us to examine the bitmask later in platform independent code.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 87
> ---
> 3 files changed, 68 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 086e3f940586..098a0e4edf2a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3390,7 +3390,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> pipe_config->has_hdmi_sink = true;
> intel_dig_port = enc_to_dig_port(&encoder->base);
>
> - if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
> + if (intel_hdmi_infoframes_enabled(encoder, pipe_config))
> pipe_config->has_infoframe = true;
>
> if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e0f3a79fc75e..6815c69aac2f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1181,7 +1181,7 @@ struct intel_digital_port {
> bool enable,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> - bool (*infoframe_enabled)(struct intel_encoder *encoder,
> + u32 (*infoframes_enabled)(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config);
> };
>
> @@ -1856,6 +1856,8 @@ bool intel_hdmi_handle_sink_scrambling(struct
> intel_encoder *encoder,
> bool scrambling);
> void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool
> enable);
> void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
> +u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
>
> /* intel_lvds.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index c3c2a638d062..a8fcddb199ae 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -100,10 +100,14 @@ static u32 g4x_infoframe_index(unsigned int type)
> static u32 g4x_infoframe_enable(unsigned int type)
> {
> switch (type) {
> + case HDMI_PACKET_TYPE_NULL:
> + return VIDEO_DIP_ENABLE; /* slight lie */
Not exactly sure why we're tracking this one here, but not for hsw.
Shouldn't we include that one if the DDI port is in hdmi mode? Would be
more consistent I think.
Aside from that lgtm, has my
Reviewed-by: Daniel Vetter
once we figured the TYPE_NULL thing out.
-Daniel
> case HDMI_PACKET_TYPE_GENERAL_CONTROL:
> return VIDEO_DIP_ENABLE_GCP;
> case HDMI_PACKET_TYPE_GAMUT_METADATA:
> return VIDEO_DIP_ENABLE_GAMUT;
> + case DP_SDP_VSC:
> + return 0;
> case HDMI_INFOFRAME_TYPE_AVI:
> return VIDEO_DIP_ENABLE_AVI;
> case HDMI_INFOFRAME_TYPE_SPD:
> @@ -119,6 +123,8 @@ static u32 g4x_infoframe_enable(unsigned int type)
> static u32 hsw_infoframe_enable(unsigned int type)
> {
> switch (type) {
> + case HDMI_PACKET_TYPE_NULL:
> + return 0;
> case HDMI_PACKET_TYPE_GENERAL_CONTROL:
> return VIDEO_DIP_ENABLE_GCP_HSW;
> case HDMI_PACKET_TYPE_GAMUT_METADATA:
> @@ -197,19 +203,19 @@ static void g4x_write_infoframe(struct intel_encoder
> *encoder,
> POSTING_READ(VIDEO_DIP_CTL);
> }
>
> -static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
> +static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 val = I915_READ(VIDEO_DIP_CTL);
>
> if ((val & VIDEO_DIP_ENABLE) == 0)
> - return false;
> + return 0;
>
> if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
> - return false;
> + return 0;
>
> - return val & (VIDEO_DIP_ENABLE_AVI |
> + return val & (VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
> VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
> }
>
> @@ -252,7 +258,7 @@ static void ibx_write_infoframe(struct intel_encoder
> *encoder,
> POSTING_READ(reg);
> }
>
> -static bool ibx_infoframe_enabled(struc
Re: [Intel-gfx] [PATCH 12/18] drm/i915: Store mask of enabled infoframes in the crtc state
On Thu, Sep 20, 2018 at 09:51:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Store the mask of enabled infoframes in the crtc state. We'll start
> with just the readout for HDMI encoder, and we'll expand this
> to compute the bitmask in .compute_config() later. SDVO will also
> follow later.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 -
> drivers/gpu/drm/i915/intel_drv.h | 4
> drivers/gpu/drm/i915/intel_hdmi.c | 5 -
> 3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 098a0e4edf2a..19fef88e680e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3390,7 +3390,10 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> pipe_config->has_hdmi_sink = true;
> intel_dig_port = enc_to_dig_port(&encoder->base);
>
> - if (intel_hdmi_infoframes_enabled(encoder, pipe_config))
> + pipe_config->infoframes.enable |=
> + intel_hdmi_infoframes_enabled(encoder, pipe_config);
> +
> + if (pipe_config->infoframes.enable)
> pipe_config->has_infoframe = true;
>
> if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 6815c69aac2f..50c0c049ee15 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -893,6 +893,10 @@ struct intel_crtc_state {
> u8 active_planes;
> u8 nv12_planes;
>
> + struct {
> + u32 enable;
> + } infoframes;
> +
> /* HDMI scrambling status */
> bool hdmi_scrambling;
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index a8fcddb199ae..98a44084324c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1264,7 +1264,10 @@ static void intel_hdmi_get_config(struct intel_encoder
> *encoder,
> if (tmp & HDMI_MODE_SELECT_HDMI)
> pipe_config->has_hdmi_sink = true;
>
> - if (intel_hdmi_infoframes_enabled(encoder, pipe_config))
> + pipe_config->infoframes.enable |=
> + intel_hdmi_infoframes_enabled(encoder, pipe_config);
> +
> + if (pipe_config->infoframes.enable)
> pipe_config->has_infoframe = true;
>
> if (tmp & SDVO_AUDIO_ENABLE)
> --
> 2.16.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/18] drm/i915: Precompute HDMI infoframes
On Thu, Sep 20, 2018 at 09:51:40PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Store the infoframes in the crtc state and precompute them in
> .compute_config(). While precomputing we'll also fill out the
> inforames.enable bitmask appropriately.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 5 +
> drivers/gpu/drm/i915/intel_hdmi.c | 249
> +++---
> 3 files changed, 187 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 19fef88e680e..5f3bd536d261 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3391,6 +3391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_dig_port = enc_to_dig_port(&encoder->base);
>
> pipe_config->infoframes.enable |=
> + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_NULL) |
Misplaced hunk? Assuming I'm reading this correctly, this will give you a
0. Not exactly sure what's going on here ... I guess I'm not following why
we care about TYPE_NULL, and why we have to reconstruct it here?
I thought TYPE_NULL is equivalent to state->has_hdmi_sink? Comment
(unfortunately not yet kerneldoc) even explains that ...
Maybe just nuke all the TYPE_NULL tracking here, perhaps with the g4x
(except for g4x itself, because it's shared there) decoder to also take
DIP_ENABLE into account for has_hdmi_sink.
Or update the comment in intel_crtc_state.
Otherwise lgtm, thought admittedly I did clean over the details a bit,
trusting CI and gcc to catch the small stuff :-)
Reviewed-by: Daniel Vetter with the TYPE_NULL
story somehow figured out.
-Daniel
> intel_hdmi_infoframes_enabled(encoder, pipe_config);
>
> if (pipe_config->infoframes.enable)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 50c0c049ee15..357624a6bfe2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -895,6 +895,10 @@ struct intel_crtc_state {
>
> struct {
> u32 enable;
> + u32 gcp;
> + union hdmi_infoframe avi;
> + union hdmi_infoframe spd;
> + union hdmi_infoframe hdmi;
> } infoframes;
>
> /* HDMI scrambling status */
> @@ -1862,6 +1866,7 @@ void intel_dp_dual_mode_set_tmds_output(struct
> intel_hdmi *hdmi, bool enable);
> void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
> u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> +u32 intel_hdmi_infoframe_enable(unsigned int type);
>
>
> /* intel_lvds.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 98a44084324c..491001fc0fad 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -446,6 +446,18 @@ static const u8 infoframe_type_to_idx[] = {
> HDMI_INFOFRAME_TYPE_VENDOR,
> };
>
> +u32 intel_hdmi_infoframe_enable(unsigned int type)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
> + if (infoframe_type_to_idx[i] == type)
> + return BIT(i);
> + }
> +
> + return 0;
> +}
> +
> u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -491,15 +503,23 @@ u32 intel_hdmi_infoframes_enabled(struct intel_encoder
> *encoder,
> */
> static void intel_write_infoframe(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> - union hdmi_infoframe *frame)
> + enum hdmi_infoframe_type type,
> + const union hdmi_infoframe *frame)
> {
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(&encoder->base);
> u8 buffer[VIDEO_DIP_DATA_SIZE];
> ssize_t len;
>
> + if ((crtc_state->infoframes.enable &
> + intel_hdmi_infoframe_enable(type)) == 0)
> + return;
> +
> + if (WARN_ON(frame->any.type != type))
> + return;
> +
> /* see comment above for the reason for this offset */
> - len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
> - if (len < 0)
> + len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
> + if (WARN_ON(len < 0))
> return;
>
> /* Insert the 'hole' (see big comment above) at position 3 */
> @@ -507,85 +527,111 @@ static void intel_write_infoframe(struct intel_encoder
> *encoder,
> buffer[3] = 0;
> len++;
>
> - intel_dig_port->write_infoframe(encoder,
> -
Re: [Intel-gfx] [PATCH 14/18] drm/i915: Read out HDMI infoframes
On Thu, Sep 20, 2018 at 09:51:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add code to read the infoframes from the video DIP and unpack them into
> the crtc state.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 17
> drivers/gpu/drm/i915/intel_drv.h | 10 ++
> drivers/gpu/drm/i915/intel_hdmi.c | 203
> ++
> 3 files changed, 230 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 5f3bd536d261..a56289f78326 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3459,6 +3459,23 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
>
> intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
> +
> + intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
> +
> + if (!intel_read_infoframe(encoder, pipe_config,
> + HDMI_INFOFRAME_TYPE_AVI,
> + &pipe_config->infoframes.avi))
> + DRM_ERROR("failed to read AVI infoframe\n");
> +
> + if (!intel_read_infoframe(encoder, pipe_config,
> + HDMI_INFOFRAME_TYPE_SPD,
> + &pipe_config->infoframes.spd))
> + DRM_ERROR("failed to read SPD infoframe:\n");
> +
> + if (!intel_read_infoframe(encoder, pipe_config,
> + HDMI_INFOFRAME_TYPE_VENDOR,
> + &pipe_config->infoframes.hdmi))
> + DRM_ERROR("failed to read HDMI infoframe\n");
> }
>
> static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 357624a6bfe2..75ec99b85232 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1185,6 +1185,10 @@ struct intel_digital_port {
> const struct intel_crtc_state *crtc_state,
> unsigned int type,
> const void *frame, ssize_t len);
> + ssize_t (*read_infoframe)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + void *frame, ssize_t len);
> void (*set_infoframes)(struct intel_encoder *encoder,
> bool enable,
> const struct intel_crtc_state *crtc_state,
> @@ -1867,6 +1871,12 @@ void intel_infoframe_init(struct intel_digital_port
> *intel_dig_port);
> u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> u32 intel_hdmi_infoframe_enable(unsigned int type);
> +void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
> +struct intel_crtc_state *crtc_state);
> +bool intel_read_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + enum hdmi_infoframe_type type,
> + union hdmi_infoframe *frame);
>
>
> /* intel_lvds.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 491001fc0fad..27cb6ec32e94 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -203,6 +203,31 @@ static void g4x_write_infoframe(struct intel_encoder
> *encoder,
> POSTING_READ(VIDEO_DIP_CTL);
> }
>
> +static ssize_t g4x_read_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + void *frame, ssize_t len)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + u32 val, *data = frame;
> + int i;
> +
> + val = I915_READ(VIDEO_DIP_CTL);
> +
> + if ((val & g4x_infoframe_enable(type)) == 0)
> + return 0;
> +
> + val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
> + val |= g4x_infoframe_index(type);
> +
> + I915_WRITE(VIDEO_DIP_CTL, val);
> +
> + for (i = 0; i < len; i += 4)
> + *data++ = I915_READ(VIDEO_DIP_DATA);
> +
> + return len;
> +}
> +
> static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> @@ -258,6 +283,32 @@ static void ibx_write_infoframe(struct intel_encoder
> *encoder,
> POSTING_READ(reg);
> }
>
> +static ssize_t ibx_read_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + void *frame
Re: [Intel-gfx] [PATCH 16/18] drm/i915/sdvo: Read out HDMI infoframes
On Thu, Sep 20, 2018 at 09:51:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Read the HDMI infoframes from the hbuf and unpack them into
> the crtc state.
>
> Well, actually just AVI infoframe for now but let's write the
> infoframe readout code in a more generic fashion in case we
> expand this later.
>
> Signed-off-by: Ville Syrjälä
Hm, caring about sdvo seems a bit overkill. And afaik we don't have any
sdvo (much less hdmi) in CI. I'm leaning towards just adding a
PIPE_CONFIG_QUIRK_INFOFRAMES for sdvo, and short-circuiting the checks if
that's set. Except if you can somehow convince CI folks to add an sdvo
hdmi card to CI :-)
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 92
> +--
> 1 file changed, 89 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> b/drivers/gpu/drm/i915/intel_sdvo.c
> index d8c78aebaf01..4d787c86df6d 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -981,6 +981,58 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo
> *intel_sdvo,
> &tx_rate, 1);
> }
>
> +static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
> + unsigned int if_index,
> + u8 *data, unsigned int length)
> +{
> + u8 set_buf_index[2] = { if_index, 0 };
> + u8 hbuf_size, tx_rate, av_split;
> + int i;
> +
> + if (!intel_sdvo_get_value(intel_sdvo,
> + SDVO_CMD_GET_HBUF_AV_SPLIT,
> + &av_split, 1))
> + return -ENXIO;
> +
> + if (av_split < if_index)
> + return 0;
> +
> + if (!intel_sdvo_get_value(intel_sdvo,
> + SDVO_CMD_GET_HBUF_TXRATE,
> + &tx_rate, 1))
> + return -ENXIO;
> +
> + if (tx_rate == SDVO_HBUF_TX_DISABLED)
> + return 0;
> +
> + if (!intel_sdvo_set_value(intel_sdvo,
> + SDVO_CMD_SET_HBUF_INDEX,
> + set_buf_index, 2))
> + return -ENXIO;
> +
> + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
> + &hbuf_size, 1))
> + return -ENXIO;
> +
> + /* Buffer size is 0 based, hooray! */
> + hbuf_size++;
> +
> + DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
> + if_index, length, hbuf_size);
> +
> + hbuf_size = min_t(unsigned int, length, hbuf_size);
> +
> + for (i = 0; i < hbuf_size; i += 8) {
> + if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA,
> NULL, 0))
> + return -ENXIO;
> + if (!intel_sdvo_read_response(intel_sdvo, &data[i],
> + min_t(unsigned int, 8, hbuf_size
> - i)))
> + return -ENXIO;
> + }
> +
> + return hbuf_size;
> +}
> +
> static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
>struct intel_crtc_state
> *crtc_state,
>struct drm_connector_state
> *conn_state)
> @@ -1039,6 +1091,37 @@ static bool intel_sdvo_set_avi_infoframe(struct
> intel_sdvo *intel_sdvo,
> sdvo_data, sizeof(sdvo_data));
> }
>
> +static bool intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
> + struct intel_crtc_state *crtc_state)
> +{
> + u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
> + union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
> + ssize_t len;
> + int ret;
> +
> + if (!crtc_state->has_hdmi_sink)
> + return true;
> +
> + len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
> + sdvo_data, sizeof(sdvo_data));
> + if (len < 0)
> + return false;
> + else if (len == 0)
> + return true;
> +
> + crtc_state->infoframes.enable |=
> + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
> +
> + ret = hdmi_infoframe_unpack(frame, sdvo_data, sizeof(sdvo_data));
> + if (ret)
> + return false;
> +
> + if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
> + return false;
> +
> + return true;
> +}
> +
> static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
>const struct drm_connector_state
> *conn_state)
> {
> @@ -1535,6 +1618,10 @@ static void intel_sdvo_get_config(struct intel_encoder
> *encoder,
> }
> }
>
> + WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
> + "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> + pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> +
>
Re: [Intel-gfx] [PATCH 17/18] drm/i915: Check infoframe state in intel_pipe_config_compare()
On Thu, Sep 20, 2018 at 09:51:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Check the infoframes and infoframe enable state when comparing two
> crtc states.
>
> We'll use the infoframe logging functions from video/hdmi.c to
> show the infoframes as part of the state dump.
>
> TODO: Try to better integrate the infoframe dumps with
> drm state dumps
>
> v2: drm_printk() is no more
>
> Signed-off-by: Ville Syrjälä
> ---
Might need adapting to PIPE_CONFIG_QUIRK_INFOFRAME, but aside from that
Reviewed-by: Daniel Vetter
> drivers/gpu/drm/i915/intel_display.c | 49
> +++-
> 1 file changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index fbcc56caffb6..3dce49e36a05 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11380,6 +11380,37 @@ intel_compare_link_m_n(const struct intel_link_m_n
> *m_n,
> return false;
> }
>
> +static bool
> +intel_compare_infoframe(const union hdmi_infoframe *a,
> + const union hdmi_infoframe *b)
> +{
> + return memcmp(a, b, sizeof(*a)) == 0;
> +}
> +
> +static void
> +pipe_config_infoframe_err(struct drm_i915_private *dev_priv,
> + bool adjust, const char *name,
> + const union hdmi_infoframe *a,
> + const union hdmi_infoframe *b)
> +{
> + if (adjust) {
> + if ((drm_debug & DRM_UT_KMS) == 0)
> + return;
> +
> + drm_dbg(DRM_UT_KMS, "mismatch in %s infoframe", name);
> + drm_dbg(DRM_UT_KMS, "expected:");
> + hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
> + drm_dbg(DRM_UT_KMS, "found");
> + hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
> + } else {
> + drm_err("mismatch in %s infoframe", name);
> + drm_err("expected:");
> + hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
> + drm_err("found");
> + hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
> + }
Mildly concerned about padding fields (since these are the not-compatified
structs). Maybe dump the mismatching byte too, plus byte offset? Or maybe
I'm just too paranoid.
> +}
> +
> static void __printf(3, 4)
> pipe_config_err(bool adjust, const char *name, const char *format, ...)
> {
> @@ -11541,7 +11572,17 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
> } \
> } while (0)
>
> -#define PIPE_CONF_QUIRK(quirk) \
> +#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
> + if (!intel_compare_infoframe(¤t_config->infoframes.name, \
> + &pipe_config->infoframes.name)) { \
> + pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
> + ¤t_config->infoframes.name, \
> + &pipe_config->infoframes.name); \
> + ret = false; \
> + } \
> +} while (0)
> +
> +#define PIPE_CONF_QUIRK(quirk) \
> ((current_config->quirks | pipe_config->quirks) & (quirk))
>
> PIPE_CONF_CHECK_I(cpu_transcoder);
> @@ -11670,6 +11711,12 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
>
> PIPE_CONF_CHECK_I(min_voltage_level);
>
> + PIPE_CONF_CHECK_X(infoframes.enable);
> + PIPE_CONF_CHECK_X(infoframes.gcp);
> + PIPE_CONF_CHECK_INFOFRAME(avi);
> + PIPE_CONF_CHECK_INFOFRAME(spd);
> + PIPE_CONF_CHECK_INFOFRAME(hdmi);
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_BOOL
> --
> 2.16.4
>
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Re: [Intel-gfx] [PATCH 18/18] drm/i915: Include infoframes in the crtc state dump
On Thu, Sep 20, 2018 at 09:51:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dump out the infoframes in the normal crtc state dump.
>
> TODO: Try to better integrate the infoframe dumps with
> drm state dumps
>
> Signed-off-by: Ville Syrjälä
Going to make dmesg with state debugging enabled even more noisier, but
hey, whatever gives us more data to drown in :-)
More seriously, maybe eventually someone ports drm debug over to one of
the more scalable logging thingies.
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3dce49e36a05..27ac33a2a4d3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10924,6 +10924,16 @@ intel_dump_m_n_config(struct intel_crtc_state
> *pipe_config, char *id,
> m_n->link_m, m_n->link_n, m_n->tu);
> }
>
> +static void
> +intel_dump_infoframe(struct drm_i915_private *dev_priv,
> + const union hdmi_infoframe *frame)
> +{
> + if ((drm_debug & DRM_UT_KMS) == 0)
> + return;
> +
> + hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
> +}
> +
> #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
>
> static const char * const output_type_str[] = {
> @@ -11013,6 +11023,22 @@ static void intel_dump_pipe_config(struct intel_crtc
> *crtc,
> DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
> pipe_config->has_audio, pipe_config->has_infoframe);
>
> + DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
> + pipe_config->infoframes.enable);
> +
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
> + DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
> + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
> + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
> + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> +
> DRM_DEBUG_KMS("requested mode:\n");
> drm_mode_debug_printmodeline(&pipe_config->base.mode);
> DRM_DEBUG_KMS("adjusted mode:\n");
> --
> 2.16.4
>
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Re: [Intel-gfx] [PATCH 11/18] drm/i915: Return the mask of enabled infoframes from ->inforame_enabled()
On Mon, Sep 24, 2018 at 05:51:16PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:38PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We want to start tracking which infoframes are enabled, so let's replace
> > the boolean flag with a bitmask.
> >
> > We'll abstract the bitmask so that it's not platform dependent. That
> > will allow us to examine the bitmask later in platform independent code.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> > drivers/gpu/drm/i915/intel_drv.h | 4 +-
> > drivers/gpu/drm/i915/intel_hdmi.c | 87
> > ---
> > 3 files changed, 68 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 086e3f940586..098a0e4edf2a 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3390,7 +3390,7 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > pipe_config->has_hdmi_sink = true;
> > intel_dig_port = enc_to_dig_port(&encoder->base);
> >
> > - if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
> > + if (intel_hdmi_infoframes_enabled(encoder, pipe_config))
> > pipe_config->has_infoframe = true;
> >
> > if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index e0f3a79fc75e..6815c69aac2f 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1181,7 +1181,7 @@ struct intel_digital_port {
> >bool enable,
> >const struct intel_crtc_state *crtc_state,
> >const struct drm_connector_state *conn_state);
> > - bool (*infoframe_enabled)(struct intel_encoder *encoder,
> > + u32 (*infoframes_enabled)(struct intel_encoder *encoder,
> > const struct intel_crtc_state *pipe_config);
> > };
> >
> > @@ -1856,6 +1856,8 @@ bool intel_hdmi_handle_sink_scrambling(struct
> > intel_encoder *encoder,
> >bool scrambling);
> > void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool
> > enable);
> > void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
> > +u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> >
> >
> > /* intel_lvds.c */
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index c3c2a638d062..a8fcddb199ae 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -100,10 +100,14 @@ static u32 g4x_infoframe_index(unsigned int type)
> > static u32 g4x_infoframe_enable(unsigned int type)
> > {
> > switch (type) {
> > + case HDMI_PACKET_TYPE_NULL:
> > + return VIDEO_DIP_ENABLE; /* slight lie */
>
> Not exactly sure why we're tracking this one here, but not for hsw.
HSW+ doesn't have a DIP enable bit like this. It only has the
bits to enable specific infoframes.
> Shouldn't we include that one if the DDI port is in hdmi mode? Would be
> more consistent I think.
Yes that would seem like the more correct thing. I think the reason
I did this here was so that I could map the DIP_ENABLE bit to
something unique. Would allow us to differentiate between the
"DIP enabled with no infoframes enabled" vs. "DIP enabled with
some infoframes enabled" cases. But seeing as we always enable some
infoframes I guess this doesn't really provide us with anything
particularly useful.
That said, I'm actually not sure whether the hw will send the null
packets if we don't enable the DIP. Would require a HDMI analyzer
to confirm.
Hmm. Actually gen4 bspec tells me:
"If DIP is enabled but DIP types are all disabled, no DIP is sent.
However, a single Null DIP will be sent at the same point in the
stream that DIP packets would have been sent. This is done to
keep the port in HDMI mode, otherwise it would revert to DVI mode.
The "Null packets enabled during vsync" mode (bit #9 of port
control register) overrides this behavior."
So I guess mapping the null packet to the DIP enable bit is more or
less correct. Although the spec doesn't quite say whether the null
packet is also sent when some DIP types are also enabled, or if it
is only send when no DIP types are enabled.
So to match the hw I guess the readout should really do something
like:
if (hdmi & HDMI_MODE || dip_ctl & DIP_ENABLE)
infoframes |= TYPE_NULL;
but that would again mean that we can't tell the two cases
apart.
>
> Aside from that lgtm, has my
>
> Reviewed-by: Daniel Vetter
>
> once we figured the TYPE_NULL thing out.
> -Daniel
>
> > case HDMI_PACKET_TYPE_GENERAL_CONTROL:
> >
Re: [Intel-gfx] [PATCH 13/18] drm/i915: Precompute HDMI infoframes
On Mon, Sep 24, 2018 at 05:58:25PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:40PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Store the infoframes in the crtc state and precompute them in
> > .compute_config(). While precomputing we'll also fill out the
> > inforames.enable bitmask appropriately.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 1 +
> > drivers/gpu/drm/i915/intel_drv.h | 5 +
> > drivers/gpu/drm/i915/intel_hdmi.c | 249
> > +++---
> > 3 files changed, 187 insertions(+), 68 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 19fef88e680e..5f3bd536d261 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3391,6 +3391,7 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > intel_dig_port = enc_to_dig_port(&encoder->base);
> >
> > pipe_config->infoframes.enable |=
> > + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_NULL) |
>
> Misplaced hunk? Assuming I'm reading this correctly, this will give you a
> 0. Not exactly sure what's going on here ... I guess I'm not following why
> we care about TYPE_NULL, and why we have to reconstruct it here?
I rather wanted the infoframes bitmask to be truthful about which
packets we're sending out. But not quite sure why I included it in
this particular patch.
>
> I thought TYPE_NULL is equivalent to state->has_hdmi_sink? Comment
> (unfortunately not yet kerneldoc) even explains that ...
Yeah it's the same thing (apart from the g4x DIP enable thing). Maybe
I should remove has_hdmi_sink entirely and just rely on the null packet
bit instead...
>
> Maybe just nuke all the TYPE_NULL tracking here, perhaps with the g4x
> (except for g4x itself, because it's shared there) decoder to also take
> DIP_ENABLE into account for has_hdmi_sink.
That would the other option I suppose. Though I might like the idea
of dropping the bool for the bitmask a bit more perhaps.
>
> Or update the comment in intel_crtc_state.
>
> Otherwise lgtm, thought admittedly I did clean over the details a bit,
> trusting CI and gcc to catch the small stuff :-)
>
> Reviewed-by: Daniel Vetter with the TYPE_NULL
> story somehow figured out.
> -Daniel
>
>
> > intel_hdmi_infoframes_enabled(encoder, pipe_config);
> >
> > if (pipe_config->infoframes.enable)
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 50c0c049ee15..357624a6bfe2 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -895,6 +895,10 @@ struct intel_crtc_state {
> >
> > struct {
> > u32 enable;
> > + u32 gcp;
> > + union hdmi_infoframe avi;
> > + union hdmi_infoframe spd;
> > + union hdmi_infoframe hdmi;
> > } infoframes;
> >
> > /* HDMI scrambling status */
> > @@ -1862,6 +1866,7 @@ void intel_dp_dual_mode_set_tmds_output(struct
> > intel_hdmi *hdmi, bool enable);
> > void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
> > u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > +u32 intel_hdmi_infoframe_enable(unsigned int type);
> >
> >
> > /* intel_lvds.c */
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 98a44084324c..491001fc0fad 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -446,6 +446,18 @@ static const u8 infoframe_type_to_idx[] = {
> > HDMI_INFOFRAME_TYPE_VENDOR,
> > };
> >
> > +u32 intel_hdmi_infoframe_enable(unsigned int type)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
> > + if (infoframe_type_to_idx[i] == type)
> > + return BIT(i);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > @@ -491,15 +503,23 @@ u32 intel_hdmi_infoframes_enabled(struct
> > intel_encoder *encoder,
> > */
> > static void intel_write_infoframe(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > - union hdmi_infoframe *frame)
> > + enum hdmi_infoframe_type type,
> > + const union hdmi_infoframe *frame)
> > {
> > struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(&encoder->base);
> > u8 buffer[VIDEO_DIP_DATA_SIZE];
> > ssize_t len;
> >
> > + if ((crtc_state->infoframes.enable &
> > +intel_hdmi_infoframe_enable(type)) == 0)
> >
[Intel-gfx] [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, of ICL it only applies
to combo phy and not to eDP. This means we need to apply the WA only on
Aux B.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7e6ca7f9665..1e92112d23de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8928,6 +8928,10 @@ enum skl_power_gate {
#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
+#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
+#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
+#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
+
/* HDCP Key Registers */
#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGERBIT(31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0fdabce647ab..a97d2f762b77 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
hsw_wait_for_power_well_enable(dev_priv, power_well);
+
+ /* Display WA #1178: icl */
+ if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
+ val = I915_READ(ICL_AUX_ANAOVRD1_B);
+ val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
+ I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
+ }
}
static void
--
2.17.1
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Re: [Intel-gfx] [PATCH 14/18] drm/i915: Read out HDMI infoframes
On Mon, Sep 24, 2018 at 06:08:09PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:41PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add code to read the infoframes from the video DIP and unpack them into
> > the crtc state.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 17
> > drivers/gpu/drm/i915/intel_drv.h | 10 ++
> > drivers/gpu/drm/i915/intel_hdmi.c | 203
> > ++
> > 3 files changed, 230 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 5f3bd536d261..a56289f78326 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3459,6 +3459,23 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
> >
> > intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
> > +
> > + intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
> > +
> > + if (!intel_read_infoframe(encoder, pipe_config,
> > + HDMI_INFOFRAME_TYPE_AVI,
> > + &pipe_config->infoframes.avi))
> > + DRM_ERROR("failed to read AVI infoframe\n");
> > +
> > + if (!intel_read_infoframe(encoder, pipe_config,
> > + HDMI_INFOFRAME_TYPE_SPD,
> > + &pipe_config->infoframes.spd))
> > + DRM_ERROR("failed to read SPD infoframe:\n");
> > +
> > + if (!intel_read_infoframe(encoder, pipe_config,
> > + HDMI_INFOFRAME_TYPE_VENDOR,
> > + &pipe_config->infoframes.hdmi))
> > + DRM_ERROR("failed to read HDMI infoframe\n");
> > }
> >
> > static enum intel_output_type
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 357624a6bfe2..75ec99b85232 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1185,6 +1185,10 @@ struct intel_digital_port {
> > const struct intel_crtc_state *crtc_state,
> > unsigned int type,
> > const void *frame, ssize_t len);
> > + ssize_t (*read_infoframe)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len);
> > void (*set_infoframes)(struct intel_encoder *encoder,
> >bool enable,
> >const struct intel_crtc_state *crtc_state,
> > @@ -1867,6 +1871,12 @@ void intel_infoframe_init(struct intel_digital_port
> > *intel_dig_port);
> > u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > u32 intel_hdmi_infoframe_enable(unsigned int type);
> > +void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> > +bool intel_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + enum hdmi_infoframe_type type,
> > + union hdmi_infoframe *frame);
> >
> >
> > /* intel_lvds.c */
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 491001fc0fad..27cb6ec32e94 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -203,6 +203,31 @@ static void g4x_write_infoframe(struct intel_encoder
> > *encoder,
> > POSTING_READ(VIDEO_DIP_CTL);
> > }
> >
> > +static ssize_t g4x_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + u32 val, *data = frame;
> > + int i;
> > +
> > + val = I915_READ(VIDEO_DIP_CTL);
> > +
> > + if ((val & g4x_infoframe_enable(type)) == 0)
> > + return 0;
> > +
> > + val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
> > + val |= g4x_infoframe_index(type);
> > +
> > + I915_WRITE(VIDEO_DIP_CTL, val);
> > +
> > + for (i = 0; i < len; i += 4)
> > + *data++ = I915_READ(VIDEO_DIP_DATA);
> > +
> > + return len;
> > +}
> > +
> > static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *pipe_config)
> > {
> > @@ -258,6 +283,32 @@ static void ibx_write_infoframe(struct intel_encoder
> > *encoder,
> > POSTING_READ(reg);
> > }
> >
> > +static ssize_t ibx_read_infoframe(str
Re: [Intel-gfx] [PATCH 16/18] drm/i915/sdvo: Read out HDMI infoframes
On Mon, Sep 24, 2018 at 06:10:14PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Read the HDMI infoframes from the hbuf and unpack them into
> > the crtc state.
> >
> > Well, actually just AVI infoframe for now but let's write the
> > infoframe readout code in a more generic fashion in case we
> > expand this later.
> >
> > Signed-off-by: Ville Syrjälä
>
> Hm, caring about sdvo seems a bit overkill. And afaik we don't have any
> sdvo (much less hdmi) in CI. I'm leaning towards just adding a
> PIPE_CONFIG_QUIRK_INFOFRAMES for sdvo, and short-circuiting the checks if
> that's set. Except if you can somehow convince CI folks to add an sdvo
> hdmi card to CI :-)
Unfortunately I only have one SDVO HDMI device and it has the chip
straight on the motherboard. I can't give mine up for ci :) I guess
we could try to find another one of those as that model doesn't
even seem super rare. Just the annoying usual problem of getting
one from somewhere approved.
I think having to maintain a quirk is ~500% more annoying than
adding the readout code.
>
> > ---
> > drivers/gpu/drm/i915/intel_sdvo.c | 92
> > +--
> > 1 file changed, 89 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> > b/drivers/gpu/drm/i915/intel_sdvo.c
> > index d8c78aebaf01..4d787c86df6d 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -981,6 +981,58 @@ static bool intel_sdvo_write_infoframe(struct
> > intel_sdvo *intel_sdvo,
> > &tx_rate, 1);
> > }
> >
> > +static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
> > +unsigned int if_index,
> > +u8 *data, unsigned int length)
> > +{
> > + u8 set_buf_index[2] = { if_index, 0 };
> > + u8 hbuf_size, tx_rate, av_split;
> > + int i;
> > +
> > + if (!intel_sdvo_get_value(intel_sdvo,
> > + SDVO_CMD_GET_HBUF_AV_SPLIT,
> > + &av_split, 1))
> > + return -ENXIO;
> > +
> > + if (av_split < if_index)
> > + return 0;
> > +
> > + if (!intel_sdvo_get_value(intel_sdvo,
> > + SDVO_CMD_GET_HBUF_TXRATE,
> > + &tx_rate, 1))
> > + return -ENXIO;
> > +
> > + if (tx_rate == SDVO_HBUF_TX_DISABLED)
> > + return 0;
> > +
> > + if (!intel_sdvo_set_value(intel_sdvo,
> > + SDVO_CMD_SET_HBUF_INDEX,
> > + set_buf_index, 2))
> > + return -ENXIO;
> > +
> > + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
> > + &hbuf_size, 1))
> > + return -ENXIO;
> > +
> > + /* Buffer size is 0 based, hooray! */
> > + hbuf_size++;
> > +
> > + DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
> > + if_index, length, hbuf_size);
> > +
> > + hbuf_size = min_t(unsigned int, length, hbuf_size);
> > +
> > + for (i = 0; i < hbuf_size; i += 8) {
> > + if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA,
> > NULL, 0))
> > + return -ENXIO;
> > + if (!intel_sdvo_read_response(intel_sdvo, &data[i],
> > + min_t(unsigned int, 8, hbuf_size
> > - i)))
> > + return -ENXIO;
> > + }
> > +
> > + return hbuf_size;
> > +}
> > +
> > static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
> > struct intel_crtc_state
> > *crtc_state,
> > struct drm_connector_state
> > *conn_state)
> > @@ -1039,6 +1091,37 @@ static bool intel_sdvo_set_avi_infoframe(struct
> > intel_sdvo *intel_sdvo,
> > sdvo_data, sizeof(sdvo_data));
> > }
> >
> > +static bool intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
> > +struct intel_crtc_state *crtc_state)
> > +{
> > + u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
> > + union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
> > + ssize_t len;
> > + int ret;
> > +
> > + if (!crtc_state->has_hdmi_sink)
> > + return true;
> > +
> > + len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
> > + sdvo_data, sizeof(sdvo_data));
> > + if (len < 0)
> > + return false;
> > + else if (len == 0)
> > + return true;
> > +
> > + crtc_state->infoframes.enable |=
> > + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
> > +
> > + ret = hdmi_infoframe_unpack(frame, sdvo_data, sizeof(sdvo_data));
> > + if (ret)
> > + return false;
> > +
> > + if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
Re: [Intel-gfx] [PATCH 33/40] drm/i915: Extend CREATE_CONTEXT to allow inheritance ala clone()
On 19/09/2018 20:55, Chris Wilson wrote:
A context encompasses the driver's view of process related state, and
encapsulates the logical GPU state where available. Each context is
currently equivalent to a process in CPU terms. Like with processes,
sometimes the user wants a lighter encapsulation that shares some state
with the parent process, for example two threads have unique register
state but share the virtual memory mappings. We can support exactly the
same principle using contexts where we may share the GTT but keep the
logical GPU state distinct. This allows quicker switching between those
contexts, and for userspace to allocate a single offset in the GTT and
use it across multiple contexts. Like with clone(), in the future we may
wish to allow userspace to select more features to copy across from the
parent, but for now we only allow sharing of the GTT.
Note that if full per-process GTT is not supported on the harder, the
s/harder/hardware/
GTT are already implicitly shared between contexts, and this request
to create contexts with shared GTT fails. With full ppGTT, every fd
(i.e. every process) is allocated a unique GTT so this request cannot be
used to share GTT between processes/fds, it can only share GTT belonging
to this fd.
Testcase: igt/gem_ctx_shared
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_context.c | 62 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 1 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 252 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +
include/uapi/drm/i915_drm.h | 11 +-
9 files changed, 279 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 150d7a6b2bd3..da2ac10f8e8a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -110,6 +110,8 @@ static void lut_close(struct i915_gem_context *ctx)
struct i915_vma *vma = rcu_dereference_raw(*slot);
radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
+
+ vma->open_count--;
__i915_gem_object_release_unless_active(vma->obj);
}
rcu_read_unlock();
@@ -292,7 +294,7 @@ static void context_close(struct i915_gem_context *ctx)
*/
lut_close(ctx);
if (ctx->ppgtt)
- i915_ppgtt_close(&ctx->ppgtt->vm);
+ i915_ppgtt_close(ctx->ppgtt);
ctx->file_priv = ERR_PTR(-EBADF);
i915_gem_context_put(ctx);
@@ -399,9 +401,12 @@ static void __destroy_hw_context(struct i915_gem_context
*ctx,
context_close(ctx);
}
+#define CREATE_VM BIT(0)
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+ struct drm_i915_file_private *file_priv,
+ unsigned int flags)
{
struct i915_gem_context *ctx;
@@ -414,7 +419,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
if (IS_ERR(ctx))
return ctx;
- if (USES_FULL_PPGTT(dev_priv)) {
+ if (flags & CREATE_VM && USES_FULL_PPGTT(dev_priv)) {
struct i915_hw_ppgtt *ppgtt;
ppgtt = i915_ppgtt_create(dev_priv, file_priv);
@@ -493,7 +498,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
struct i915_gem_context *ctx;
int err;
- ctx = i915_gem_create_context(i915, NULL);
+ ctx = i915_gem_create_context(i915, NULL, CREATE_VM);
if (IS_ERR(ctx))
return ctx;
@@ -620,7 +625,7 @@ int i915_gem_context_open(struct drm_i915_private *i915,
idr_init(&file_priv->context_idr);
mutex_lock(&i915->drm.struct_mutex);
- ctx = i915_gem_create_context(i915, file_priv);
+ ctx = i915_gem_create_context(i915, file_priv, CREATE_VM);
mutex_unlock(&i915->drm.struct_mutex);
if (IS_ERR(ctx)) {
idr_destroy(&file_priv->context_idr);
@@ -778,10 +783,12 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_context_create *args = data;
+ struct drm_i915_gem_context_create_v2 *args = data;
struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct i915_gem_context *share = NULL;
struct i915_gem_context *ctx;
- int ret;
+ unsigned int flags = CREATE_VM;
+ int err;
if (!DRIVER_CAPS(dev_priv)->ha
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: apply Display WA #1178 to fix type C dongles
== Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles URL : https://patchwork.freedesktop.org/series/50102/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10263 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10263 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10263, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50102/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10263: === IGT changes === Possible regressions igt@core_prop_blob@basic: fi-kbl-7560u: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10263 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: fi-skl-guc: PASS -> DMESG-FAIL (fdo#106685) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_psr@primary_page_flip: fi-kbl-r: PASS -> FAIL (fdo#107336) Possible fixes igt@gem_exec_suspend@basic-s3: fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106685 https://bugs.freedesktop.org/show_bug.cgi?id=106685 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 == Participating hosts (46 -> 41) == Additional (1): fi-hsw-4770r Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4868 -> Patchwork_10263 CI_DRM_4868: dd42062d73b630f0ef0e8891bcc6438c14dae9dc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10263: f1c0d6306647d46d6aaf9b5d3247b19a5f9927e2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f1c0d6306647 drm/i915/icl: apply Display WA #1178 to fix type C dongles == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10263/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Check fb stride against plane max stride
On Monday, September 24, 2018 6:31:56 AM PDT Ville Syrjälä wrote:
> On Fri, Sep 21, 2018 at 03:17:45PM -0700, Dhinakaran Pandiyan wrote:
> > On Tuesday, September 18, 2018 7:02:43 AM PDT Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > commit 4e0b83a567e2 ("drm/i915: Extract per-platform plane->check()
> > > functions") removed the plane max stride check for sprite planes.
> > > I was going to add it back when introducing GTT remapping for the
> > > display, but after further thought it seems better to re-introduce
> > > it separately.
> > >
> > > So let's add the max stride check back. And let's do it in a nicer
> > > form than what we had before and do it for all plane types (easy
> > > now that we have the ->max_stride() plane vfunc).
> > >
> > > Only sprite planes really need this for now since primary planes
> > > are capable of scanning out the current max fb size we allow, and
> > > cursors have more stringent stride checks elsewhere.
> > >
Reviewed-by: Dhinakaran Pandiyan
> > > Cc: José Roberto de Souza
> > > Fixes: 4e0b83a567e2 ("drm/i915: Extract per-platform plane->check()
> > > functions") Signed-off-by: Ville Syrjälä
> > > ---
> > >
> > > drivers/gpu/drm/i915/intel_display.c | 14 ++
> > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > drivers/gpu/drm/i915/intel_sprite.c | 22 ++
> > > 3 files changed, 37 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c index eb25037d7b38..1eb99d5ec221
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3151,6 +3151,10 @@ int skl_check_plane_surface(struct
> > > intel_plane_state
> > > *plane_state) plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> > > rotation); plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> > > rotation);
> > >
> > > + ret = intel_plane_check_stride(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > >
> > > if (!plane_state->base.visible)
> > >
> > > return 0;
> > >
> > > @@ -3286,10 +3290,15 @@ int i9xx_check_plane_surface(struct
> > > intel_plane_state *plane_state) int src_x = plane_state->base.src.x1 >>
> > > 16;
> > >
> > > int src_y = plane_state->base.src.y1 >> 16;
> > > u32 offset;
> > >
> > > + int ret;
> > >
> > > intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> >
> > Is there a good reason to not inline the code ?
> >
> > if (color_plane[0].stride > plane->max_stride())
> >
> > return -EINVAL;
>
> Consistency. Easier to just call a single function that does things in a
> consistent fashion rather than duplicating the same check everywhere.
> Also keeps the debug print consistent.
>
> > > + ret = intel_plane_check_stride(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > >
> > > intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> > >
> > > if (INTEL_GEN(dev_priv) >= 4)
> > >
> > > @@ -9685,10 +9694,15 @@ static int intel_cursor_check_surface(struct
> > > intel_plane_state *plane_state) unsigned int rotation =
> > > plane_state->base.rotation;
> > >
> > > int src_x, src_y;
> > > u32 offset;
> > >
> > > + int ret;
> > >
> > > intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > >
> > > + ret = intel_plane_check_stride(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > >
> > > src_x = plane_state->base.src_x >> 16;
> > > src_y = plane_state->base.src_y >> 16;
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h index bf1c38728a59..a34c2f1f9159
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -2140,6 +2140,7 @@ unsigned int skl_plane_max_stride(struct
> > > intel_plane
> > > *plane, unsigned int rotation);
> > >
> > > int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >
> > > struct intel_plane_state *plane_state);
> > >
> > > +int intel_plane_check_stride(const struct intel_plane_state
> > > *plane_state);
> > >
> > > int intel_plane_check_src_coordinates(struct intel_plane_state
> > >
> > > *plane_state); int chv_plane_check_rotation(const struct
> > > intel_plane_state
> > > *plane_state);
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > b/drivers/gpu/drm/i915/intel_sprite.c index d4c8e10fc90b..5fd2f7bf3927
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -230,6 +230,28 @@ void intel_pipe_update_end(struct intel_crtc_state
> > > *new_crtc_state) #endif
> > >
> > > }
> > >
> > > +int intel_plane_check_stride(const struct intel_plane_state
> > > *plane_state)
> > > +{
> >
[Intel-gfx] [PATCH v10 1/2] drm: Add connector property to limit max bpc
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against connector limitations.
Creating a new connector property "max bpc" in order to limit the bpc.
xrandr can make use of this connector property to make sure that bpc does
not exceed the configured value. This property can be used by userspace to
set the bpc.
V2: Initialize max_bpc to satisfy kms_properties
V3: Move the property to drm_connector
V4: Split drm and i915 components(Ville)
V5: Make the property per connector(Ville)
V6: Compare the requested bpc to connector bpc(Daniel)
Move the attach_property function to core(Ville)
V7: Fix checkpatch warnings
V8: Simplify the connector check code(Ville)
V9: Const display_info(Ville)
V10: Fix CI issues.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Kishore Kadiyala
Cc: Rodrigo Vivi
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Cc: Sunpeng Li
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/drm_atomic.c| 5 +
drivers/gpu/drm/drm_atomic_helper.c | 4
drivers/gpu/drm/drm_atomic_uapi.c | 4
drivers/gpu/drm/drm_connector.c | 33 +
include/drm/drm_connector.h | 20
5 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 2870ae205237..f328bcca84a8 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -390,6 +390,7 @@ static int drm_atomic_connector_check(struct drm_connector
*connector,
{
struct drm_crtc_state *crtc_state;
struct drm_writeback_job *writeback_job = state->writeback_job;
+ const struct drm_display_info *info = &connector->display_info;
if ((connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) ||
!writeback_job)
return 0;
@@ -417,6 +418,10 @@ static int drm_atomic_connector_check(struct drm_connector
*connector,
return -EINVAL;
}
+ state->max_bpc = info->bpc ? info->bpc : 8;
+ if (connector->max_bpc_property)
+ state->max_bpc = min(state->max_bpc, state->max_requested_bpc);
+
return 0;
}
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index e49b22381048..75aeca35f6d9 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -639,6 +639,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (old_connector_state->link_status !=
new_connector_state->link_status)
new_crtc_state->connectors_changed = true;
+
+ if (old_connector_state->max_requested_bpc !=
+ new_connector_state->max_requested_bpc)
+ new_crtc_state->connectors_changed = true;
}
if (funcs->atomic_check)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index d5b7f315098c..86ac33922b09 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -740,6 +740,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return set_out_fence_for_connector(state->state, connector,
fence_ptr);
+ } else if (property == connector->max_bpc_property) {
+ state->max_requested_bpc = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -804,6 +806,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = 0;
} else if (property == config->writeback_out_fence_ptr_property) {
*val = 0;
+ } else if (property == connector->max_bpc_property) {
+ *val = state->max_requested_bpc;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 1e40e5decbe9..65e22c1b37a5 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1583,6 +1583,39 @@ void drm_connector_set_link_status_property(struct
drm_connector *connector,
EXPORT_SYMBOL(drm_connector_set_link_status_property);
/**
+ * drm_connector_attach_max_bpc_property - attach "max bpc" property
+ * @connector: connector to attach max bpc property on.
+ * @min: The minimum bit depth supported by the connector.
+ * @max: The maximum bit depth supported by the connector.
+
[Intel-gfx] [PATCH v10 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
V5: Use the property in the connector and fix CI failure(Ville)
V6: Use the core function to attach max_bpc property, remove the redundant
clamping of pipe bpp based on connector info
V7: Fix Checkpatch warnings
V9: Cleanup connected_sink_max_bpp and fix initial value in DP(Ville)
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Kishore Kadiyala
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 48 +---
drivers/gpu/drm/i915/intel_dp.c | 4 +++
drivers/gpu/drm/i915/intel_hdmi.c| 5
3 files changed, 37 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 931898013506..057abfd77cc3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10839,30 +10839,38 @@ static void
intel_modeset_update_connector_atomic_state(struct drm_device *dev)
drm_connector_list_iter_end(&conn_iter);
}
-static void
-connected_sink_compute_bpp(struct intel_connector *connector,
- struct intel_crtc_state *pipe_config)
+static int
+connected_sink_max_bpp(const struct drm_connector_state *conn_state,
+ struct intel_crtc_state *pipe_config)
{
- const struct drm_display_info *info = &connector->base.display_info;
- int bpp = pipe_config->pipe_bpp;
+ int bpp;
+ struct drm_display_info *info = &conn_state->connector->display_info;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
- connector->base.base.id,
- connector->base.name);
+ bpp = min(pipe_config->pipe_bpp, conn_state->max_bpc * 3);
- /* Don't use an invalid EDID bpc value */
- if (info->bpc != 0 && info->bpc * 3 < bpp) {
- DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported
max of %d\n",
- bpp, info->bpc * 3);
- pipe_config->pipe_bpp = info->bpc * 3;
+ switch (conn_state->max_bpc) {
+ case 6 ... 7:
+ pipe_config->pipe_bpp = 6 * 3;
+ case 8 ... 9:
+ pipe_config->pipe_bpp = 8 * 3;
+ break;
+ case 10 ... 11:
+ pipe_config->pipe_bpp = 10 * 3;
+ break;
+ case 12:
+ pipe_config->pipe_bpp = 12 * 3;
+ break;
+ default:
+ return -EINVAL;
}
- /* Clamp bpp to 8 on screens without EDID 1.4 */
- if (info->bpc == 0 && bpp > 24) {
- DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit
of 24\n",
- bpp);
- pipe_config->pipe_bpp = 24;
+ if (bpp != pipe_config->pipe_bpp) {
+ DRM_DEBUG_KMS("Limiting display bpp to %d instead of requested "
+ "bpp %d, Edid bpp %d\n", bpp, 3 * info->bpc,
+ 3 * conn_state->max_requested_bpc);
+ pipe_config->pipe_bpp = bpp;
}
+ return 0;
}
static int
@@ -10893,8 +10901,8 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
if (connector_state->crtc != &crtc->base)
continue;
- connected_sink_compute_bpp(to_intel_connector(connector),
- pipe_config);
+ if (connected_sink_max_bpp(connector_state, pipe_config) < 0)
+ return -EINVAL;
}
return bpp;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b4c19123f2a..d8e128e771a1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5719,6 +5719,10 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ if (HAS_GMCH_DISPLAY(dev_priv))
+ drm_connector_attach_max_bpc_property(connector, 6, 10);
+ else if (INTEL_GEN(dev_priv) >= 5)
+ drm_connector_attach_max_bpc_property(connector, 6, 12);
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index a2dab0b6bde6..2b432c7e4f8a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2109,11 +2109,16 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,1/2] drm: Add connector property to limit max bpc
== Series Details == Series: series starting with [v10,1/2] drm: Add connector property to limit max bpc URL : https://patchwork.freedesktop.org/series/50110/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Add connector property to limit max bpc +drivers/gpu/drm/drm_atomic.c:423:34: warning: expression using sizeof(void) +drivers/gpu/drm/drm_atomic.c:423:34: warning: expression using sizeof(void) Commit: drm/i915: Allow "max bpc" property to limit pipe_bpp +drivers/gpu/drm/i915/intel_display.c:10849:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:10849:15: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v10,1/2] drm: Add connector property to limit max bpc
== Series Details == Series: series starting with [v10,1/2] drm: Add connector property to limit max bpc URL : https://patchwork.freedesktop.org/series/50110/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10264 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10264 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10264, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50110/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10264: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-skl-iommu: PASS -> FAIL +34 fi-bdw-samus: PASS -> FAIL fi-blb-e6850: PASS -> FAIL fi-kbl-soraka: PASS -> FAIL igt@drv_hangman@error-state-basic: fi-pnv-d510:PASS -> DMESG-WARN fi-blb-e6850: PASS -> DMESG-WARN fi-bwr-2160:PASS -> DMESG-WARN igt@gem_exec_suspend@basic-s3: fi-kbl-r: PASS -> DMESG-WARN fi-skl-6770hq: PASS -> DMESG-WARN fi-byt-n2820: PASS -> DMESG-WARN fi-cfl-8109u: PASS -> DMESG-WARN fi-cfl-s3: PASS -> DMESG-WARN fi-snb-2600:PASS -> DMESG-WARN fi-whl-u: PASS -> DMESG-WARN fi-skl-caroline:PASS -> DMESG-WARN fi-elk-e7500: PASS -> DMESG-WARN fi-cfl-guc: PASS -> DMESG-WARN fi-skl-iommu: PASS -> DMESG-WARN fi-kbl-7567u: PASS -> DMESG-WARN fi-skl-guc: PASS -> DMESG-WARN fi-glk-j4005: PASS -> DMESG-WARN fi-glk-dsi: PASS -> DMESG-WARN fi-snb-2520m: PASS -> DMESG-WARN +1 fi-cfl-8700k: PASS -> DMESG-WARN fi-bsw-kefka: PASS -> DMESG-WARN fi-bxt-dsi: PASS -> DMESG-WARN fi-byt-clapper: PASS -> DMESG-WARN fi-bsw-n3050: PASS -> DMESG-WARN fi-hsw-4770:PASS -> DMESG-WARN fi-kbl-7560u: PASS -> DMESG-WARN fi-bxt-j4205: PASS -> DMESG-WARN fi-skl-6700hq: PASS -> DMESG-WARN fi-cnl-u: PASS -> DMESG-WARN fi-ivb-3770:PASS -> DMESG-WARN fi-skl-6700k2: PASS -> DMESG-WARN fi-hsw-4770r: NOTRUN -> DMESG-WARN fi-skl-6600u: PASS -> DMESG-WARN fi-hsw-peppy: PASS -> DMESG-WARN igt@kms_busy@basic-flip-a: fi-kbl-7567u: PASS -> FAIL +34 fi-whl-u: PASS -> FAIL +39 igt@kms_chamelium@hdmi-crc-fast: fi-skl-6700k2: PASS -> FAIL +35 igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: fi-glk-j4005: PASS -> FAIL +34 igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: fi-hsw-4770r: NOTRUN -> FAIL +34 fi-pnv-d510:PASS -> FAIL +20 fi-skl-6600u: PASS -> FAIL +39 fi-cfl-8700k: PASS -> FAIL +34 igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: fi-skl-guc: PASS -> FAIL +34 fi-snb-2600:PASS -> FAIL +24 igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: fi-snb-2520m: PASS -> FAIL +25 igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: fi-skl-caroline:PASS -> FAIL +39 igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: fi-bsw-n3050: PASS -> FAIL +20 fi-hsw-4770:PASS -> FAIL +35 igt@kms_flip@basic-flip-vs-dpms: fi-skl-6770hq: PASS -> FAIL +34 igt@kms_flip@basic-flip-vs-modeset: fi-cnl-u: PASS -> FAIL +38 igt@kms_flip@basic-flip-vs-wf_vblank: fi-hsw-peppy: PASS -> FAIL +34 igt@kms_frontbuffer_tracking@basic: fi-elk-e7500: SKIP -> FAIL igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-ivb-3770:PASS -> FAIL +35 igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-bxt-j4205: PASS -> FAIL +34 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-elk-e7500: PASS -> FAIL +20 fi-byt-n2820: PASS -> FAIL +23 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-bsw-kefka: PASS -> FAIL +24 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-bdw-gvtdvm: PASS -> FAIL +34 fi-gdg-551: PASS -> FAIL +12 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c: fi-skl-gvtdvm: PASS -> FAIL +34 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: fi-glk-dsi: PASS -> FAIL +35 igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-bwr-2160:PASS -> FAIL +20 igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequen
[Intel-gfx] [PATCH 1/3] drm/i915/icl: Add WaEnable32PlaneMode
From: "Sripada, Radhakrishna"
Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Use the wa name.(Oscar)
v3: rebase
v4: rebase
Cc: Oscar Mateo Lozano
Cc: Michel Thierry
Cc: James Ausmus
Cc: Anusha Srivatsa
Acked-by: Michel Thierry
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7e6ca7f9665..82f246ad87a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2573,6 +2573,7 @@ enum i915_power_well_id {
/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
/* WaClearTdlStateAckDirtyBits */
#define GEN8_STATE_ACK _MMIO(0x20F0)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 4bcdeaf8d98f..ba4009b4ad2c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -905,6 +905,10 @@ static void icl_gt_workarounds_apply(struct
drm_i915_private *dev_priv)
I915_WRITE(GAMT_CHKN_BIT_REG,
I915_READ(GAMT_CHKN_BIT_REG) |
GAMT_CHKN_DISABLE_L3_COH_PIPE);
+
+ /* WaEnable32PlaneMode:icl */
+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
+ _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
2.9.3
___
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[Intel-gfx] [PATCH 2/3] drm/i915/icl: apply Display WA #1178 to fix type C dongles
From: Lucas De Marchi
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, of ICL it only applies
to combo phy and not to eDP. This means we need to apply the WA only on
Aux B.
v2: simplify macro with w/a register (Paulo)
v3: Rebase on drm-tip. (Imre)
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f246ad87a8..d61bfb305e93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8929,6 +8929,10 @@ enum skl_power_gate {
#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
+#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
+#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
+#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
+
/* HDCP Key Registers */
#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGERBIT(31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0fdabce647ab..a97d2f762b77 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
hsw_wait_for_power_well_enable(dev_priv, power_well);
+
+ /* Display WA #1178: icl */
+ if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
+ val = I915_READ(ICL_AUX_ANAOVRD1_B);
+ val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
+ I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
+ }
}
static void
--
2.9.3
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[Intel-gfx] [PATCH 3/3] drm/i915/icl: Implement Display WA 1148
From: "Sripada, Radhakrishna" Display WA #1148 asks to not enable YUV 420 HDMI 10bpc when horizontal blank size mod 8 reminder is 2. v2: rebase V3: Implement in hdmi_deep_color_possible function v4: Take care of line length wrapping (James) v5: Move the WA outside the connector loop (Ville) v6: Add icl in the comment (Ville) Cc: James Ausmus Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_hdmi.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index a2dab0b6bde6..853c5b51b0be 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1597,6 +1597,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, struct drm_atomic_state *state = crtc_state->base.state; struct drm_connector_state *connector_state; struct drm_connector *connector; + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; int i; if (HAS_GMCH_DISPLAY(dev_priv)) @@ -1645,7 +1647,13 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, /* Display WA #1139: glk */ if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && - crtc_state->base.adjusted_mode.htotal > 5460) + adjusted_mode->htotal > 5460) + return false; + + /* Display Wa #1148:icl */ + if (crtc_state->ycbcr420 && bpc == 10 && IS_ICELAKE(dev_priv) && + (adjusted_mode->crtc_hblank_end - +adjusted_mode->crtc_hblank_start) % 8 == 2) return false; return true; -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
== Series Details == Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode URL : https://patchwork.freedesktop.org/series/50112/ State : warning == Summary == $ dim checkpatch origin/drm-tip 163418d50d03 drm/i915/icl: Add WaEnable32PlaneMode -:46: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Sripada, Radhakrishna ' total: 0 errors, 1 warnings, 0 checks, 17 lines checked be5ae329cca4 drm/i915/icl: apply Display WA #1178 to fix type C dongles 7539ac16c554 drm/i915/icl: Implement Display WA 1148 -:51: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Sripada, Radhakrishna ' total: 0 errors, 1 warnings, 0 checks, 22 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: apply Display WA #1178 to fix type C dongles
On Mon, Sep 24, 2018 at 2:55 PM Radhakrishna Sripada
wrote:
>
> From: Lucas De Marchi
>
> Display WA #1178 is meant to fix Aux channel voltage swing too low with
> some type C dongles. Although it is for type C, of ICL it only applies
> to combo phy and not to eDP. This means we need to apply the WA only on
> Aux B.
>
> v2: simplify macro with w/a register (Paulo)
> v3: Rebase on drm-tip. (Imre)
There's no v2, v3 of this patch. There's v1 that has been sent to the
mailing list earlier today. Please stick with
that version and provide any review there.
thanks
Lucas De Marchi
>
> Cc: Rodrigo Vivi
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f246ad87a8..d61bfb305e93 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8929,6 +8929,10 @@ enum skl_power_gate {
> #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
> #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
>
> +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
> +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
> +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
> +
> /* HDCP Key Registers */
> #define HDCP_KEY_CONF _MMIO(0x66c00)
> #define HDCP_AKSV_SEND_TRIGGERBIT(31)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0fdabce647ab..a97d2f762b77 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
> +
> + /* Display WA #1178: icl */
> + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
> + val = I915_READ(ICL_AUX_ANAOVRD1_B);
> + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> + I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
> + }
> }
>
> static void
> --
> 2.9.3
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
== Series Details == Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode URL : https://patchwork.freedesktop.org/series/50112/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10265 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50112/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10265 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_psr@primary_page_flip: fi-kbl-r: PASS -> FAIL (fdo#107336) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_psr@primary_page_flip: fi-cnl-u: FAIL (fdo#107336) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (46 -> 42) == Additional (1): fi-hsw-4770r Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4868 -> Patchwork_10265 CI_DRM_4868: dd42062d73b630f0ef0e8891bcc6438c14dae9dc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10265: 7539ac16c554041a5014aac119e367932727cad3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7539ac16c554 drm/i915/icl: Implement Display WA 1148 be5ae329cca4 drm/i915/icl: apply Display WA #1178 to fix type C dongles 163418d50d03 drm/i915/icl: Add WaEnable32PlaneMode == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10265/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/6] drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect()
A crtc modeset lock was added for link retraining but
intel_dp_retrain_link() knows to take the necessary locks since
commit c85d200e8321 ("drm/i915: Move SST DP link retraining into the
->post_hotplug() hook")
Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
->post_hotplug() hook")
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 09229fc66dec..87a631098a6d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5079,8 +5079,13 @@ intel_dp_long_pulse(struct intel_connector *connector,
* Some external monitors do not signal loss of link synchronization
* with an IRQ_HPD, so force a link status check.
*/
- if (!intel_dp_is_edp(intel_dp))
- intel_dp_retrain_link(encoder, ctx);
+ if (!intel_dp_is_edp(intel_dp)) {
+ int ret;
+
+ ret = intel_dp_retrain_link(encoder, ctx);
+ if (ret)
+ return ret;
+ }
/*
* Clearing NACK and defer counts to get their exact values
@@ -5130,19 +5135,8 @@ intel_dp_detect(struct drm_connector *connector,
connector->base.id, connector->name);
/* If full detect is not performed yet, do a full detect */
- if (!intel_dp->detect_done) {
- struct drm_crtc *crtc;
- int ret;
-
- crtc = connector->state->crtc;
- if (crtc) {
- ret = drm_modeset_lock(&crtc->mutex, ctx);
- if (ret)
- return ret;
- }
-
+ if (!intel_dp->detect_done)
status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
- }
intel_dp->detect_done = false;
--
2.17.1
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[Intel-gfx] [PATCH v2 3/6] drm/i915/dp: Use a local variable for intel_encoder *
We have two cases of intel_dp to intel_encoder conversions, use a
local variable to store the conversion.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6130d05d8b88..09229fc66dec 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5017,6 +5017,7 @@ intel_dp_long_pulse(struct intel_connector *connector,
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
enum drm_connector_status status;
u8 sink_irq_vector = 0;
@@ -5027,7 +5028,7 @@ intel_dp_long_pulse(struct intel_connector *connector,
/* Can't disconnect eDP */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
- else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
+ else if (intel_digital_port_connected(encoder))
status = intel_dp_detect_dpcd(intel_dp);
else
status = connector_status_disconnected;
@@ -5078,11 +5079,8 @@ intel_dp_long_pulse(struct intel_connector *connector,
* Some external monitors do not signal loss of link synchronization
* with an IRQ_HPD, so force a link status check.
*/
- if (!intel_dp_is_edp(intel_dp)) {
- struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-
+ if (!intel_dp_is_edp(intel_dp))
intel_dp_retrain_link(encoder, ctx);
- }
/*
* Clearing NACK and defer counts to get their exact values
--
2.17.1
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[Intel-gfx] [PATCH v2 5/6] drm/i915/dp: Kill intel_dp->detect_done flag
The intel_dp->detect_done flag is no more useful. Pull
intel_dp_long_pulse() into the lone caller,
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 43
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 11 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 87a631098a6d..d6ea93e453a2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5012,15 +5012,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
}
static int
-intel_dp_long_pulse(struct intel_connector *connector,
- struct drm_modeset_acquire_ctx *ctx)
+intel_dp_detect(struct drm_connector *connector,
+ struct drm_modeset_acquire_ctx *ctx,
+ bool force)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- enum drm_connector_status status;
+ int status;
u8 sink_irq_vector = 0;
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
@@ -5096,9 +5099,9 @@ intel_dp_long_pulse(struct intel_connector *connector,
intel_dp->aux.i2c_defer_count = 0;
intel_dp_set_edid(intel_dp);
- if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
+ if (intel_dp_is_edp(intel_dp) ||
+ to_intel_connector(connector)->detect_edid)
status = connector_status_connected;
- intel_dp->detect_done = true;
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
@@ -5123,26 +5126,6 @@ intel_dp_long_pulse(struct intel_connector *connector,
return status;
}
-static int
-intel_dp_detect(struct drm_connector *connector,
- struct drm_modeset_acquire_ctx *ctx,
- bool force)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- int status = connector->status;
-
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
-
- /* If full detect is not performed yet, do a full detect */
- if (!intel_dp->detect_done)
- status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
-
- intel_dp->detect_done = false;
-
- return status;
-}
-
static void
intel_dp_force(struct drm_connector *connector)
{
@@ -5635,7 +5618,6 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
if (long_hpd) {
intel_dp->reset_link_params = true;
- intel_dp->detect_done = false;
return IRQ_NONE;
}
@@ -5652,7 +5634,6 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
intel_dp->is_mst = false;
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
intel_dp->is_mst);
- intel_dp->detect_done = false;
goto put_power;
}
}
@@ -5665,10 +5646,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
/* Short pulse can signify loss of hdcp authentication */
intel_hdcp_check_link(intel_dp->attached_connector);
- if (!handled) {
- intel_dp->detect_done = false;
+ if (!handled)
goto put_power;
- }
}
ret = IRQ_HANDLED;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8073a85d7178..a7c151c40e7d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1070,7 +1070,6 @@ struct intel_dp {
bool link_mst;
bool link_trained;
bool has_audio;
- bool detect_done;
bool reset_link_params;
enum aux_ch aux_ch;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
--
2.17.1
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[Intel-gfx] [PATCH v2 6/6] drm/i915/dp: Fix duplication of DEVICE_SERVICE_IRQ handling
There are two copies of the same code called from long and short
pulse handlers.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 59 -
1 file changed, 22 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d6ea93e453a2..64c6158feb0b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4038,13 +4038,6 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
intel_dp->is_mst);
}
-static bool
-intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
-{
- return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
-sink_irq_vector) == 1;
-}
-
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
@@ -4432,6 +4425,26 @@ static bool intel_dp_hotplug(struct intel_encoder
*encoder,
return changed;
}
+static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
+{
+ u8 val;
+
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
+ return;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
+ return;
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
+
+ if (val & DP_AUTOMATED_TEST_REQUEST)
+ intel_dp_handle_test_request(intel_dp);
+
+ if (val & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
+ DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+}
+
/*
* According to DP spec
* 5.1.2:
@@ -4449,7 +4462,6 @@ static bool
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u8 sink_irq_vector = 0;
u8 old_sink_count = intel_dp->sink_count;
bool ret;
@@ -4472,20 +4484,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
return false;
}
- /* Try to read the source of the interrupt */
- if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
- intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
- sink_irq_vector != 0) {
- /* Clear interrupt source */
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_DEVICE_SERVICE_IRQ_VECTOR,
- sink_irq_vector);
-
- if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
- intel_dp_handle_test_request(intel_dp);
- if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
- DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
- }
+ intel_dp_check_service_irq(intel_dp);
/* Handle CEC interrupts, if any */
drm_dp_cec_irq(&intel_dp->aux);
@@ -5020,7 +5019,6 @@ intel_dp_detect(struct drm_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int status;
- u8 sink_irq_vector = 0;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
connector->base.id, connector->name);
@@ -5103,20 +5101,7 @@ intel_dp_detect(struct drm_connector *connector,
to_intel_connector(connector)->detect_edid)
status = connector_status_connected;
- /* Try to read the source of the interrupt */
- if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
- intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
- sink_irq_vector != 0) {
- /* Clear interrupt source */
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_DEVICE_SERVICE_IRQ_VECTOR,
- sink_irq_vector);
-
- if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
- intel_dp_handle_test_request(intel_dp);
- if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
- DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
- }
+ intel_dp_check_service_irq(intel_dp);
out:
if (status != connector_status_connected && !intel_dp->is_mst)
--
2.17.1
___
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[Intel-gfx] [PATCH v2 2/6] drm/i915/dp: Restrict link retrain workaround to external monitors
Commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")' applies a work around for sinks
that don't signal link loss. The work around does not need to have to be
that broad as the issue was seen with only one particular monitor; limit
this only for external displays as eDP features like PSR turn off the link
and the driver ends up retraining the link seeeing that link is not
synchronized.
Cc: Lyude Paul
Cc: Jan-Marek Glogowski
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 34c561011e7a..6130d05d8b88 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5072,12 +5072,13 @@ intel_dp_long_pulse(struct intel_connector *connector,
*/
status = connector_status_disconnected;
goto out;
- } else {
- /*
-* Some external monitors do not signal loss of link
-* synchronization with an IRQ_HPD, so force a link status
-* check.
-*/
+ }
+
+ /*
+* Some external monitors do not signal loss of link synchronization
+* with an IRQ_HPD, so force a link status check.
+*/
+ if (!intel_dp_is_edp(intel_dp)) {
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
intel_dp_retrain_link(encoder, ctx);
--
2.17.1
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[Intel-gfx] [PATCH v2 1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
Comment claims link needs to be retrained because the connected sink raised
a long pulse to indicate link loss. If the sink did so,
intel_dp_hotplug() would have handled link retraining. Looking at the
logs in Bugzilla referenced in commit '3cf71bc9904d ("drm/i915: Re-apply
Perform link quality check, unconditionally during long pulse"")', the
issue is that the sink does not trigger an interrupt. What we want is
->detect() from user space to check link status and retrain. Ville's
review for the original patch also indicates the same root cause. So,
rewrite the comment.
v2: Patch split and rewrote comment.
Cc: Lyude Paul
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jan-Marek Glogowski
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b4c19123f2a..34c561011e7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5074,16 +5074,9 @@ intel_dp_long_pulse(struct intel_connector *connector,
goto out;
} else {
/*
-* If display is now connected check links status,
-* there has been known issues of link loss triggering
-* long pulse.
-*
-* Some sinks (eg. ASUS PB287Q) seem to perform some
-* weird HPD ping pong during modesets. So we can apparently
-* end up with HPD going low during a modeset, and then
-* going back up soon after. And once that happens we must
-* retrain the link to get a picture. That's in case no
-* userspace component reacted to intermittent HPD dip.
+* Some external monitors do not signal loss of link
+* synchronization with an IRQ_HPD, so force a link status
+* check.
*/
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode
== Series Details == Series: series starting with [1/3] drm/i915/icl: Add WaEnable32PlaneMode URL : https://patchwork.freedesktop.org/series/50112/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4868_full -> Patchwork_10265_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10265_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10265_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10265_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS igt@pm_rc6_residency@rc6-accuracy: shard-snb: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10265_full that come from known issues: === IGT changes === Issues hit igt@gem_userptr_blits@readonly-unsync: shard-apl: PASS -> INCOMPLETE (fdo#103927) +1 igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-glk: NOTRUN -> DMESG-WARN (fdo#107956) igt@perf@enable-disable: shard-kbl: NOTRUN -> INCOMPLETE (fdo#103665) Possible fixes igt@drv_suspend@shrink: shard-kbl: INCOMPLETE (fdo#106886, fdo#103665) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4868 -> Patchwork_10265 CI_DRM_4868: dd42062d73b630f0ef0e8891bcc6438c14dae9dc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10265: 7539ac16c554041a5014aac119e367932727cad3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10265/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Redefine some Whiskey Lake SKUs
commit 'b9be78531d27 ("drm/i915/whl: Introducing
Whiskey Lake platform")' introduced WHL by moving some
of CFL IDs here and using the Spec information of "U43" for
most of IDs what appeared to be GT3.
However when propagating the change to Mesa, Lionel noticed
that based on number of execution unities the classification
here seems at least strange.
So, let's move for now with the information we trust more:
the number of EUs. So we are able to propagate this change
across the stack without getting stuck forever.
Reference: https://patchwork.freedesktop.org/patch/246695/
Fixes: b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
Cc: Lionel Landwerlin
Cc: José Roberto de Souza
Cc: David Airlie
Signed-off-by: Rodrigo Vivi
---
include/drm/i915_pciids.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index fd965ffbb92e..c8d3d541ad01 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -407,17 +407,17 @@
/* WHL/CFL U GT1 */
#define INTEL_WHL_U_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA1, info)
+ INTEL_VGA_DEVICE(0x3EA1, info), \
+ INTEL_VGA_DEVICE(0x3EA4, info)
/* WHL/CFL U GT2 */
#define INTEL_WHL_U_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA0, info)
+ INTEL_VGA_DEVICE(0x3EA0, info), \
+ INTEL_VGA_DEVICE(0x3EA3, info)
/* WHL/CFL U GT3 */
#define INTEL_WHL_U_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA2, info), \
- INTEL_VGA_DEVICE(0x3EA3, info), \
- INTEL_VGA_DEVICE(0x3EA4, info)
+ INTEL_VGA_DEVICE(0x3EA2, info)
#define INTEL_CFL_IDS(info) \
INTEL_CFL_S_GT1_IDS(info), \
--
2.17.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment
in intel_dp_long_pulse()
URL : https://patchwork.freedesktop.org/series/50113/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
017be37fce85 drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#27:
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
-:27: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3cf71bc9904d ("drm/i915:
Re-apply "Perform link quality check, unconditionally during long pulse"")'
#27:
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
total: 1 errors, 1 warnings, 0 checks, 19 lines checked
0973c8f3f60e drm/i915/dp: Restrict link retrain workaround to external monitors
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#22:
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3cf71bc9904d ("drm/i915:
Re-apply "Perform link quality check, unconditionally during long pulse"")'
#22:
References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")
total: 1 errors, 1 warnings, 0 checks, 19 lines checked
3b988cab2936 drm/i915/dp: Use a local variable for intel_encoder *
9cdccd0a7cfb drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect()
3a2b516cb993 drm/i915/dp: Kill intel_dp->detect_done flag
59778a072668 drm/i915/dp: Fix duplication of DEVICE_SERVICE_IRQ handling
___
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/psr: Share PSR and PSR2 exit mask
On Thursday, September 20, 2018 1:43:20 PM PDT José Roberto de Souza wrote:
> Now both PSR and PSR2 have the same exit mask, so let's share then
> instead of have the same code 2 times.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 34
> 1 file changed, 13 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index b6838b525502..358bbcd3b5f3 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -575,28 +575,20 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp, else
> chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
> I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> -
> - I915_WRITE(EDP_PSR_DEBUG,
> -EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP |
> -EDP_PSR_DEBUG_MASK_MAX_SLEEP |
> -EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
> - } else {
> - /*
> - * Per Spec: Avoid continuous PSR exit by masking MEMUP
> - * and HPD. also mask LPSP to avoid dependency on other
> - * drivers that might block runtime_pm besides
> - * preventing other hw tracking issues now we can rely
> - * on frontbuffer tracking.
> - */
> - I915_WRITE(EDP_PSR_DEBUG,
> -EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP |
> -EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> -EDP_PSR_DEBUG_MASK_MAX_SLEEP);
> }
> +
> + /*
> + * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
> + * mask LPSP to avoid dependency on other drivers that might block
> + * runtime_pm besides preventing other hw tracking issues now we
> + * can rely on frontbuffer tracking.
> + */
Hmm.. I don't think I understand this comment completely and we should update
it. This patch however looks correct,
Reviewed-by: Dhinakaran Pandiyan
> + I915_WRITE(EDP_PSR_DEBUG,
> +EDP_PSR_DEBUG_MASK_MEMUP |
> +EDP_PSR_DEBUG_MASK_HPD |
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> +EDP_PSR_DEBUG_MASK_MAX_SLEEP);
> }
>
> static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
== Series Details == Series: series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse() URL : https://patchwork.freedesktop.org/series/50113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10266 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10266 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10266, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50113/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10266: === IGT changes === Possible regressions igt@drv_module_reload@basic-reload: fi-skl-guc: NOTRUN -> DMESG-WARN +1 fi-skl-6770hq: PASS -> DMESG-WARN fi-skl-6700k2: PASS -> DMESG-WARN fi-bxt-j4205: PASS -> DMESG-WARN igt@drv_module_reload@basic-reload-inject: fi-kbl-7567u: PASS -> DMESG-WARN +1 igt@pm_rpm@basic-rte: fi-skl-guc: NOTRUN -> FAIL fi-kbl-7567u: PASS -> FAIL fi-skl-6770hq: PASS -> FAIL fi-skl-6700k2: PASS -> FAIL fi-bxt-j4205: PASS -> FAIL Warnings igt@pm_rpm@basic-pci-d3-state: fi-skl-6770hq: PASS -> SKIP +1 fi-skl-6700k2: PASS -> SKIP +1 igt@pm_rpm@module-reload: fi-bxt-j4205: PASS -> SKIP fi-kbl-7567u: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_10266 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-cfl-8109u: PASS -> INCOMPLETE (fdo#107187) fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@pm_rpm@module-reload: fi-skl-caroline:INCOMPLETE (fdo#107807) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107187 https://bugs.freedesktop.org/show_bug.cgi?id=107187 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 == Participating hosts (46 -> 41) == Additional (1): fi-skl-guc Missing(6): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10266 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10266: 59778a0726687dd01f1a9876199985052781f7b4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 59778a072668 drm/i915/dp: Fix duplication of DEVICE_SERVICE_IRQ handling 3a2b516cb993 drm/i915/dp: Kill intel_dp->detect_done flag 9cdccd0a7cfb drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect() 3b988cab2936 drm/i915/dp: Use a local variable for intel_encoder * 0973c8f3f60e drm/i915/dp: Restrict link retrain workaround to external monitors 017be37fce85 drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10266/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/8] drm/i915/psr: Do not set MASK_DISP_REG_WRITE in ICL
On Thursday, September 20, 2018 1:43:21 PM PDT José Roberto de Souza wrote:
> ICL spec states that this bit is now reserved.
It reads better if you state the bit name and register in the commit message.
With this nit addressed,
Reviewed-by: Dhinakaran Pandiyan
>
> Spec: 7722
Change this to Bspec: 7722 to be clear? But, I don't know if there is a tag
that we consistently use for citing bspec.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_psr.c | 17 +++--
> 2 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 4948b352bf4c..4dd5290a3b95 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4195,7 +4195,7 @@ enum {
> #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
> #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
> #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
> -#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16)
> +#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16) /* Reserved in
> ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
>
> #define EDP_PSR2_CTL _MMIO(0x6f900)
> @@ -4232,7 +4232,7 @@ enum {
> #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
> #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
> #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
> -#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
> +#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
> #define PSR_EVENT_HDCP_ENABLE (1 << 4)
> #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
> #define PSR_EVENT_VBI_ENABLE(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 358bbcd3b5f3..6f3c6f0c539f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -558,6 +558,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp, {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 mask;
>
> /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
>* use hardcoded values PSR AUX transactions
> @@ -583,12 +584,16 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp, * runtime_pm besides preventing other hw tracking issues now we
> * can rely on frontbuffer tracking.
>*/
> - I915_WRITE(EDP_PSR_DEBUG,
> -EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP |
> -EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> -EDP_PSR_DEBUG_MASK_MAX_SLEEP);
> + mask = EDP_PSR_DEBUG_MASK_MEMUP |
> +EDP_PSR_DEBUG_MASK_HPD |
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> +EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + mask &= ~EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> +
> + I915_WRITE(EDP_PSR_DEBUG, mask);
> }
>
> static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
___
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[Intel-gfx] [PATCH 2/3] drm/i915: make the primary plane func structs const
Because we can, the places where we use them already expect const
structs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fdff1779f778..a21ec8ae46f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13467,7 +13467,7 @@ static bool intel_cursor_format_mod_supported(struct
drm_plane *_plane,
format == DRM_FORMAT_ARGB;
}
-static struct drm_plane_funcs skl_plane_funcs = {
+static const struct drm_plane_funcs skl_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = intel_plane_destroy,
@@ -13478,7 +13478,7 @@ static struct drm_plane_funcs skl_plane_funcs = {
.format_mod_supported = skl_plane_format_mod_supported,
};
-static struct drm_plane_funcs i965_plane_funcs = {
+static const struct drm_plane_funcs i965_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = intel_plane_destroy,
@@ -13489,7 +13489,7 @@ static struct drm_plane_funcs i965_plane_funcs = {
.format_mod_supported = i965_plane_format_mod_supported,
};
-static struct drm_plane_funcs i8xx_plane_funcs = {
+static const struct drm_plane_funcs i8xx_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = intel_plane_destroy,
--
2.14.4
___
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[Intel-gfx] [PATCH 3/3] drm/i915: remove a copy of skl_plane_format_mod_supported()
A little git-blame'ing suggests that both functions were added by
commit 714244e280de ("drm/i915: Add format modifiers for Intel"), as
skl_mod_supported() on intel_display.c and
skl_plane_format_mod_supported() on intel_sprite.c. At that time they
were different, but right now they are exactly the same, name and tabs
included. Remove one of the copies and make the other non-static.
Given how our hardware has evolved it is unlikely that future
platforms will require a different format_mod_supported() function for
the primary plane vs the sprite plane, and we can always bring back
the additional copy if we need.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 50
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_sprite.c | 4 +--
3 files changed, 4 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a21ec8ae46f6..b9a0183dc580 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13410,56 +13410,6 @@ static bool i965_plane_format_mod_supported(struct
drm_plane *_plane,
}
}
-static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
- u32 format, u64 modifier)
-{
- struct intel_plane *plane = to_intel_plane(_plane);
-
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Yf_TILED:
- break;
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (!plane->has_ccs)
- return false;
- break;
- default:
- return false;
- }
-
- switch (format) {
- case DRM_FORMAT_XRGB:
- case DRM_FORMAT_XBGR:
- case DRM_FORMAT_ARGB:
- case DRM_FORMAT_ABGR:
- if (is_ccs_modifier(modifier))
- return true;
- /* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
- case DRM_FORMAT_YUYV:
- case DRM_FORMAT_YVYU:
- case DRM_FORMAT_UYVY:
- case DRM_FORMAT_VYUY:
- case DRM_FORMAT_NV12:
- if (modifier == I915_FORMAT_MOD_Yf_TILED)
- return true;
- /* fall through */
- case DRM_FORMAT_C8:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
- return true;
- /* fall through */
- default:
- return false;
- }
-}
-
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf1c38728a59..313337f03da8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2140,6 +2140,8 @@ unsigned int skl_plane_max_stride(struct intel_plane
*plane,
unsigned int rotation);
int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
+bool skl_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier);
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8821e59b70ea..db297d257e1e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1609,8 +1609,8 @@ static bool vlv_sprite_format_mod_supported(struct
drm_plane *_plane,
}
}
-static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
- u32 format, u64 modifier)
+bool skl_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
{
struct intel_plane *plane = to_intel_plane(_plane);
--
2.14.4
___
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[Intel-gfx] [PATCH 1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling
Function intel_framebuffer_init() checks for the possibilities during
framebuffer creation (addfb ioctl time). It is missing the fact that
the indexed format is not supported with Yf tiling.
It is worth noticing that skl_plane_format_mod_supported() correctly
handles for the C8/Yf combination, but this function runs during
modeset time, so we only reject the combination later.
Ville recently proposed a new IGT test that only uses addfb to assert
supported formats, so that IGT was failing. Add the check so we get
green squares right from the start after Ville merges his test.
Also drive-by fix the missing /* fall through */ in the chunk we
modified by just turning it into a "break;" since IMHO breaks are
easier to read than fall-throughs.
BSpec: 18565
Testcase: igt/kms_addfb_basic/expected-formats (not merged yet)
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index eb25037d7b38..fdff1779f778 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14473,13 +14473,19 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
/* fall through */
- case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ if (mode_cmd->pixel_format == DRM_FORMAT_C8) {
+ DRM_DEBUG_KMS("Indexed format does not support Yf
tiling\n");
+ goto err;
+ }
+ /* fall through */
+ case I915_FORMAT_MOD_Y_TILED:
if (INTEL_GEN(dev_priv) < 9) {
DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
mode_cmd->modifier[0]);
goto err;
}
+ break;
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
break;
--
2.14.4
___
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Re: [Intel-gfx] [PATCH 3/8] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6f3c6f0c539f..b4edbbda8d71 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -340,7 +340,7 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> if (dev_priv->psr.psr2_enabled) {
> drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> - dpcd_val |= DP_PSR_ENABLE_PSR2;
> + dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> }
} else if (INTEL_GEN(dev_priv) >=8) {
dpcd_val |= DP_PSR_CRC_VERIFICATION;
}
How about doing this for clarity?
>
> if (dev_priv->psr.link_standby)
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Redefine some Whiskey Lake SKUs
== Series Details == Series: drm/i915: Redefine some Whiskey Lake SKUs URL : https://patchwork.freedesktop.org/series/50114/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10267 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50114/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10267 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@gem_exec_suspend@basic-s4-devices: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) igt@kms_psr@primary_page_flip: fi-cfl-s3: PASS -> FAIL (fdo#107336) Possible fixes igt@drv_selftest@live_hangcheck: fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@pm_rpm@module-reload: fi-skl-caroline:INCOMPLETE (fdo#107807) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 == Participating hosts (46 -> 42) == Additional (1): fi-skl-guc Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10267 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10267: 94a4f7e2f915707ce5042bc82a3eb2bb1f47e091 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 94a4f7e2f915 drm/i915: Redefine some Whiskey Lake SKUs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10267/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling
== Series Details == Series: series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling URL : https://patchwork.freedesktop.org/series/50115/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10268 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50115/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10268 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@drv_selftest@live_hangcheck: fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@pm_rpm@module-reload: fi-skl-caroline:INCOMPLETE (fdo#107807) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 == Participating hosts (46 -> 42) == Additional (1): fi-skl-guc Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10268 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10268: 7ea4513bb3c512c1045ed3e253166d213f2172db @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7ea4513bb3c5 drm/i915: remove a copy of skl_plane_format_mod_supported() 03ad98ef111e drm/i915: make the primary plane func structs const f1df62edc741 drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10268/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Do not get aux power for disconnected DP ports
For ICL type-c ports there is a aux power restriction, it can only be
enabled while there is sink connected.
BSpec: 21750
Cc: Maarten Lankhorst
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b4c19123f2a..48fd38cd4ba4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5019,19 +5019,27 @@ intel_dp_long_pulse(struct intel_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
enum drm_connector_status status;
u8 sink_irq_vector = 0;
+ bool got_aux_power;
WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
+ /* Can't disconnect eDP */
+ if (!intel_dp_is_edp(intel_dp) &&
+ !intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
+ status = connector_status_disconnected;
+ got_aux_power = false;
+ goto port_disconnected;
+ }
+
intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
+ got_aux_power = true;
- /* Can't disconnect eDP */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
- else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
- status = intel_dp_detect_dpcd(intel_dp);
else
- status = connector_status_disconnected;
+ status = intel_dp_detect_dpcd(intel_dp);
+port_disconnected:
if (status == connector_status_disconnected) {
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
@@ -5122,7 +5130,8 @@ intel_dp_long_pulse(struct intel_connector *connector,
if (status != connector_status_connected && !intel_dp->is_mst)
intel_dp_unset_edid(intel_dp);
- intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
+ if (got_aux_power)
+ intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
return status;
}
--
2.19.0
___
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[Intel-gfx] [PATCH 1/2] drm: Do not call drm_dp_cec_set_edid() while registering DP connectors
drm_dp_cec_register_connector() is called when registering each DP connector in DRM, while sounds a good idea register CEC adapters as earlier as possible, it causes some driver initialization delay trying to do DPCD transactions in disconnected connectors. This change will cause no regressions as drm_dp_cec_set_edid() will still be called in further detection of connected connectors with a valid edid parameter. This change reduced the module load of i915 by average 0.5sec in a machine with just one DP port disconnected while reducing more than 3sec in a machine with 4 DP ports disconnected. Cc: Hans Verkuil Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/drm_dp_cec.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_cec.c b/drivers/gpu/drm/drm_dp_cec.c index 8a718f85079a..b15cee85b702 100644 --- a/drivers/gpu/drm/drm_dp_cec.c +++ b/drivers/gpu/drm/drm_dp_cec.c @@ -424,8 +424,6 @@ void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name, aux->cec.parent = parent; INIT_DELAYED_WORK(&aux->cec.unregister_work, drm_dp_cec_unregister_work); - - drm_dp_cec_set_edid(aux, NULL); } EXPORT_SYMBOL(drm_dp_cec_register_connector); -- 2.19.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Redefine some Whiskey Lake SKUs
== Series Details == Series: drm/i915: Redefine some Whiskey Lake SKUs URL : https://patchwork.freedesktop.org/series/50114/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4869_full -> Patchwork_10267_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10267_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10267_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10267_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-256x256-random: shard-snb: PASS -> SKIP igt@pm_rc6_residency@rc6-accuracy: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_10267_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_await@wide-contexts: shard-kbl: PASS -> FAIL (fdo#106680) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_setmode@basic: shard-snb: NOTRUN -> FAIL (fdo#99912) Possible fixes igt@gem_exec_schedule@smoketest-render: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +12 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10267 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10267: 94a4f7e2f915707ce5042bc82a3eb2bb1f47e091 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10267/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm: Do not call drm_dp_cec_set_edid() while registering DP connectors
== Series Details == Series: series starting with [1/2] drm: Do not call drm_dp_cec_set_edid() while registering DP connectors URL : https://patchwork.freedesktop.org/series/50116/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10269 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10269 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10269, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50116/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10269: === IGT changes === Possible regressions igt@drv_module_reload@basic-reload: fi-skl-guc: NOTRUN -> DMESG-WARN +3 fi-kbl-x1275: PASS -> DMESG-WARN +2 fi-bdw-gvtdvm: PASS -> DMESG-WARN +1 fi-cfl-8700k: PASS -> DMESG-WARN +3 fi-snb-2520m: PASS -> DMESG-WARN +2 fi-bxt-dsi: PASS -> DMESG-WARN +2 fi-hsw-4770:PASS -> DMESG-WARN +2 fi-bsw-n3050: PASS -> DMESG-WARN +3 fi-ivb-3770:PASS -> DMESG-WARN +2 fi-hsw-4770r: PASS -> DMESG-WARN +1 fi-skl-6700k2: PASS -> DMESG-WARN +2 fi-elk-e7500: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload-inject: fi-snb-2600:PASS -> DMESG-WARN +2 fi-kbl-guc: PASS -> DMESG-WARN +2 fi-skl-6770hq: PASS -> DMESG-WARN +4 fi-skl-gvtdvm: PASS -> DMESG-WARN +1 igt@kms_flip@basic-flip-vs-dpms: fi-byt-clapper: PASS -> DMESG-WARN fi-bsw-kefka: PASS -> DMESG-WARN igt@pm_rpm@basic-rte: fi-skl-iommu: PASS -> DMESG-WARN +3 fi-cfl-guc: PASS -> DMESG-WARN +3 fi-kbl-7567u: PASS -> DMESG-WARN +4 igt@pm_rpm@module-reload: fi-glk-dsi: PASS -> DMESG-WARN +3 fi-cfl-8109u: PASS -> DMESG-WARN +3 fi-bxt-j4205: PASS -> DMESG-WARN +2 fi-byt-n2820: PASS -> DMESG-WARN +1 == Known issues == Here are the changes found in Patchwork_10269 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-bxt-j4205: PASS -> DMESG-WARN (fdo#107821) fi-bxt-dsi: PASS -> DMESG-WARN (fdo#107821) fi-hsw-4770:PASS -> DMESG-WARN (fdo#107924) fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107924) igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@drv_selftest@live_hangcheck: fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@pm_rpm@module-reload: fi-skl-caroline:INCOMPLETE (fdo#107807) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107821 https://bugs.freedesktop.org/show_bug.cgi?id=107821 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 == Participating hosts (46 -> 42) == Additional (1): fi-skl-guc Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10269 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10269: 6e2ae7daa56eb0614e38fb0a7ea1412dd7504583 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6e2ae7daa56e drm/i915: Do not get aux power for disconnected DP ports b5ee32da469c drm: Do not call drm_dp_cec_set_edid() while registering DP connectors == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10269/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling
== Series Details == Series: series starting with [1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling URL : https://patchwork.freedesktop.org/series/50115/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4869_full -> Patchwork_10268_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10268_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10268_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10268_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-kbl: SKIP -> PASS shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10268_full that come from known issues: === IGT changes === Issues hit igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_setmode@basic: shard-snb: NOTRUN -> FAIL (fdo#99912) Possible fixes igt@gem_exec_schedule@smoketest-render: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +12 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10268 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10268: 7ea4513bb3c512c1045ed3e253166d213f2172db @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10268/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
On Tue, 2018-09-25 at 00:28 +, Pandiyan, Dhinakaran wrote:
> On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> > eDP spec states 2 different bits to enable sink to trigger a
> > interruption when there is a CRC mismatch.
> > DP_PSR_CRC_VERIFICATION is for PSR only and
> > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
Do you have a system that triggers a short pulse for this? If yes, do
we end up calling the PSR error interrupt handler at all?
intel_dp_short_pulse()
...
if intel_dp_needs_link_retrain()
return
intel_psr_short_pulse()
> >
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 6f3c6f0c539f..b4edbbda8d71 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -340,7 +340,7 @@ static void intel_psr_enable_sink(struct
> > intel_dp
> > *intel_dp)
> > if (dev_priv->psr.psr2_enabled) {
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> >DP_ALPM_ENABLE);
> > - dpcd_val |= DP_PSR_ENABLE_PSR2;
> > + dpcd_val |= DP_PSR_ENABLE_PSR2 |
> > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> > }
>
> } else if (INTEL_GEN(dev_priv) >=8) {
>
> dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> How about doing this for clarity?
>
>
>
> >
> > if (dev_priv->psr.link_standby)
>
>
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/psr: Use WA to force HW tracking to exit PSR2
On Thu, 2018-09-20 at 23:01 +, Souza, Jose wrote:
> On Thu, 2018-09-20 at 15:54 -0700, Rodrigo Vivi wrote:
> > On Thu, Sep 20, 2018 at 01:43:25PM -0700, José Roberto de Souza
> > wrote:
> > > This WA also works fine for PSR2, triggering a selective update
> > > when
> > > possible.
> >
> > Oh! really?! It didn't work when I chacked on my CNL,
> > but we probably had other bugs back there...
>
> Tested in WHL and ICL, I will give a try in CNL.
>
> >
> > Thanks for finding this
> >
> >
> > Reviewed-by: Rodrigo Vivi
I haven't checked myself but from what I understand it should work
Acked-by: Dhinakaran Pandiyan
> >
> >
> >
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/intel_psr.c | 24 ++--
> > > 1 file changed, 10 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 84b512426514..cf9d6e965697 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -1026,20 +1026,16 @@ void intel_psr_flush(struct
> > > drm_i915_private *dev_priv,
> > >
> > > /* By definition flush = invalidate + flush */
> > > if (frontbuffer_bits) {
> > > - if (dev_priv->psr.psr2_enabled) {
> > > - intel_psr_exit(dev_priv);
> > > - } else {
> > > - /*
> > > - * Display WA #0884: all
> > > - * This documented WA for bxt can be
> > > safely
> > > applied
> > > - * broadly so we can force HW tracking
> > > to exit
> > > PSR
> > > - * instead of disabling and re-enabling.
> > > - * Workaround tells us to write 0 to
> > > CUR_SURFLIVE_A,
> > > - * but it makes more sense write to the
> > > current
> > > active
> > > - * pipe.
> > > - */
> > > - I915_WRITE(CURSURFLIVE(pipe), 0);
> > > - }
> > > + /*
> > > + * Display WA #0884: all
> > > + * This documented WA for bxt can be safely
> > > applied
> > > + * broadly so we can force HW tracking to exit
> > > PSR
> > > + * instead of disabling and re-enabling.
> > > + * Workaround tells us to write 0 to
> > > CUR_SURFLIVE_A,
> > > + * but it makes more sense write to the current
> > > active
> > > + * pipe.
> > > + */
> > > + I915_WRITE(CURSURFLIVE(pipe), 0);
> > > }
> > >
> > > if (!dev_priv->psr.active && !dev_priv-
> > > > psr.busy_frontbuffer_bits)
> > >
> > > --
> > > 2.19.0
> > >
>
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/psr: Don't tell sink that main link will be active in PSR2
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> For PSR2 we don't have the option to keep main link enabled while
> PSR2 is active, so don't configure sink DPCD with a wrong value.
Is this what the DP spec says or an Intel HW restriction?
-DK
>
> Cc: Dhinakaran Pandiyan s
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index cf9d6e965697..60cf6fd251d0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -344,12 +344,13 @@ static void intel_psr_enable_sink(struct
> intel_dp *intel_dp)
> drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> + } else {
> + if (dev_priv->psr.link_standby)
> + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + if (INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> - if (dev_priv->psr.link_standby)
> - dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/psr: Remove alpm from i915_psr
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> ALPM is a requirement and we don't need to keep it's cached, what
> were done in commit 97c9de66ca80
> ("drm/i915/psr: Fix ALPM cap check for PSR2") but the alpm was not
> removed from i915_psr.:
You're right.
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 41f1082da122..4ed129cf4d12 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -630,7 +630,6 @@ struct i915_psr {
We should rename this intel_psr and move it to the same file where
struct intel_dp lives.
> bool sink_psr2_support;
> bool link_standby;
> bool colorimetry_support;
> - bool alpm;
> bool psr2_enabled;
And rename this too? The bool is set to enable_psr2 and does not mean
PSR2 is enabled.
> u8 sink_sync_latency;
> ktime_t last_entry_attempt;
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Predictive governor to control eu/slice/subslice based on workload
Hi Tvrtko,
Thank you for your valuable comments. We have gone through it.
I'll be submitting revised patch-sets after incorporating all your review
comments.
> On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
> > From: Praveen Diwakar
> >
> > High resoluton timer is used for this purpose.
> >
> > Debugfs is provided to enable/disable/update timer configuration
> >
> > Change-Id: I35d692c5afe962fcad4573185bc6f744487711d0
> > Signed-off-by: Praveen Diwakar
> > Signed-off-by: Yogesh Marathe
> > Signed-off-by: Aravindan Muthukumar
> > Signed-off-by: Kedar J Karanje
> > Signed-off-by: Ankit Navik > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 94
> -
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > 2 files changed, 94 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index f9ce35d..81ba509 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4740,6 +4740,97 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
> > {"i915_drrs_status", i915_drrs_status, 0},
> > {"i915_rps_boost_info", i915_rps_boost_info, 0},
> > };
> > +
> > +#define POLL_PERIOD_MS (1000 * 1000)
> > +#define PENDING_REQ_0 0 /* No active request pending*/
> > +#define PENDING_REQ_3 3 /* Threshold value of 3 active request
> pending*/
> > + /* Anything above this is considered as HIGH load
> > + * context
> > + */
> > + /* And less is considered as LOW load*/
> > + /* And equal is considered as mediaum load */
>
> Wonky comments and some typos up to here.
>
> > +
> > +static int predictive_load_enable;
> > +static int predictive_load_timer_init;
> > +
> > +static enum hrtimer_restart predictive_load_cb(struct hrtimer
> > +*hrtimer) {
> > + struct drm_i915_private *dev_priv =
> > + container_of(hrtimer, typeof(*dev_priv),
> > + pred_timer);
> > + enum intel_engine_id id;
> > + struct intel_engine_cs *engine;
>
> Some unused's.
>
> > + struct i915_gem_context *ctx;
> > + u64 req_pending;
>
> unsigned long, and also please try to order declaration so the right edge of
> text
> is moving in one direction only.
>
> > +
> > + list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
> > +
> > + if (!ctx->name)
> > + continue;
>
> What is this?
>
> > +
> > + mutex_lock(&dev_priv->pred_mutex);
>
> Here the mutex bites you since you cannot sleep in the timer callback.
> atomic_t would solve it. Or would a native unsigned int/long since lock to
> read a
> native word on x86 is not needed.
>
> > + req_pending = ctx->req_cnt;
> > + mutex_unlock(&dev_priv->pred_mutex);
> > +
> > + if (req_pending == PENDING_REQ_0)
> > + continue;
> > +
> > + if (req_pending > PENDING_REQ_3)
> > + ctx->load_type = LOAD_TYPE_HIGH;
> > + else if (req_pending == PENDING_REQ_3)
> > + ctx->load_type = LOAD_TYPE_MEDIUM;
> > + else if (req_pending < PENDING_REQ_3)
>
> Must be smaller if not greater or equal, but maybe the compiler does that for
> you.
>
> > + ctx->load_type = LOAD_TYPE_LOW;
> > +
> > + i915_set_optimum_config(ctx->load_type, ctx,
> KABYLAKE_GT3);
>
> Only KBL? Idea to put the table in dev_priv FTW! :)
>
> ctx->load_type used only as a temporary uncovered here? :)
>
> > + }
> > +
> > + hrtimer_forward_now(hrtimer,
> > +
> ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS));
>
> Or HRTIMER_NORESTART if disabled? Hard to call it, details..
>
> > +
> > + return HRTIMER_RESTART;
> > +}
> > +
> > +static int
> > +i915_predictive_load_get(void *data, u64 *val) {
> > + struct drm_i915_private *dev_priv = data;
> > +
> > + *val = predictive_load_enable;
> > + return 0;
> > +}
> > +
> > +static int
> > +i915_predictive_load_set(void *data, u64 val) {
> > + struct drm_i915_private *dev_priv = data;
> > + struct intel_device_info *info;
> > +
> > + info = mkwrite_device_info(dev_priv);
>
> Unused, why?
>
> > +
> > + predictive_load_enable = val;
> > +
> > + if (predictive_load_enable) {
> > + if (!predictive_load_timer_init) {
> > + hrtimer_init(&dev_priv->pred_timer,
> CLOCK_MONOTONIC,
> > + HRTIMER_MODE_REL);
> > + dev_priv->pred_timer.function = predictive_load_cb;
> > + predictive_load_timer_init = 1;
>
> Move timer init to dev_priv setup.
>
> > + }
> > + hrtimer_start(&dev_priv->pred_timer,
> > +
> ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS),
> > + HRTIMER_MODE_REL_PINNED);
>
> Two threads can race to here.
>
> Also you can gi
Re: [Intel-gfx] [PATCH 5/8] drm/i915/psr: Do not enable PSR2 if sink requires selective update X granularity
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> According to eDP spec, sink could required a granularity in the
> start of x coordinate or in the width of the selective update region.
> As it is not supported by hardware,
I think this warrants an explanation, what is not supported in
hardware? A certain granularity that a specific sink expects?
Even if the sink does not require a specific granularity, the source
has to support the standard granularity values (x%16 = w%4 = y%1 = 0).
Another sink can have these standard values, supported by hardware, as
a requirement and your patch will disable PSR2 on it.
-DK
> lets not enable PSR2 in sinks
> that requires it.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0dd4211cb293..84b512426514 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -243,6 +243,8 @@ void intel_psr_init_dpcd(struct intel_dp
> *intel_dp)
> bool y_req = intel_dp->psr_dpcd[1] &
>DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> bool alpm = intel_dp_get_alpm_status(intel_dp);
> + bool granularity_req = (intel_dp->psr_dpcd[1] &
> + DP_PSR2_SU_GRANULARITY_REQUI
> RED);
>
> /*
>* All panels that supports PSR version 03h (PSR2 +
> @@ -255,7 +257,8 @@ void intel_psr_init_dpcd(struct intel_dp
> *intel_dp)
>* Y-coordinate requirement panels we would need to
> enable
>* GTC first.
>*/
> - dev_priv->psr.sink_psr2_support = y_req && alpm;
> + dev_priv->psr.sink_psr2_support = y_req && alpm &&
> + !granularity_req;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" :
> "not ");
>
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Re: [Intel-gfx] [PATCH 4/8] drm/i915/psr: Remove PSR2 TODO error handling
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote: > We are already handling all PSR2 errors, so we can drop this TODO. Yes, we can remove it to thanks to all the work you have been doing. Reviewed-by: Dhinakaran Pandiyan > > Cc: Dhinakaran Pandiyan > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/intel_psr.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index b4edbbda8d71..0dd4211cb293 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -1127,8 +1127,6 @@ void intel_psr_short_pulse(struct intel_dp > *intel_dp) > intel_psr_disable_locked(intel_dp); > /* clear status register */ > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, > val); > - > - /* TODO: handle PSR2 errors */ > exit: > mutex_unlock(&psr->lock); > } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
== Series Details == Series: series starting with [v2,1/6] drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse() URL : https://patchwork.freedesktop.org/series/50113/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4869 -> Patchwork_10270 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10270 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10270, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50113/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10270: === IGT changes === Possible regressions igt@drv_module_reload@basic-reload: fi-skl-guc: NOTRUN -> DMESG-WARN fi-hsw-4770r: PASS -> DMESG-WARN +1 fi-cfl-8109u: PASS -> DMESG-WARN fi-skl-6770hq: PASS -> DMESG-WARN fi-skl-6700k2: PASS -> DMESG-WARN +1 fi-bxt-j4205: PASS -> DMESG-WARN igt@drv_module_reload@basic-reload-inject: fi-kbl-7567u: PASS -> DMESG-WARN +1 igt@pm_rpm@basic-rte: fi-skl-guc: NOTRUN -> FAIL fi-kbl-7567u: PASS -> FAIL fi-hsw-4770r: PASS -> FAIL fi-cfl-8109u: PASS -> FAIL fi-skl-6770hq: PASS -> FAIL fi-skl-6700k2: PASS -> FAIL fi-bxt-j4205: PASS -> FAIL Warnings igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-j4205: PASS -> SKIP +4 igt@pm_rpm@basic-pci-d3-state: fi-skl-6770hq: PASS -> SKIP +1 fi-skl-6700k2: PASS -> SKIP +1 fi-hsw-4770r: PASS -> SKIP +1 igt@pm_rpm@module-reload: fi-cfl-8109u: PASS -> SKIP +1 fi-kbl-7567u: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_10270 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107924) igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bxt-j4205: PASS -> DMESG-FAIL (fdo#105602) Possible fixes igt@drv_selftest@live_hangcheck: fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@pm_rpm@module-reload: fi-skl-caroline:INCOMPLETE (fdo#107807) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 == Participating hosts (46 -> 40) == Additional (1): fi-skl-guc Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4869 -> Patchwork_10270 CI_DRM_4869: 9a74a6db272a007c3db063ae3375fbee60a7bd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10270: d7e77e6ab2178dbcbe5d0d85a639e1fbc44292b7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d7e77e6ab217 drm/i915/dp: Fix duplication of DEVICE_SERVICE_IRQ handling ae605a974179 drm/i915/dp: Kill intel_dp->detect_done flag 760475370a38 drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect() 5c0f60e4a08d drm/i915/dp: Use a local variable for intel_encoder * b3430681eebd drm/i915/dp: Restrict link retrain workaround to external monitors af60bb3d378c drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10270/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove a copy of skl_plane_format_mod_supported()
On Mon, 2018-09-24 at 17:19 -0700, Paulo Zanoni wrote:
> A little git-blame'ing suggests that both functions were added by
> commit 714244e280de ("drm/i915: Add format modifiers for Intel"), as
> skl_mod_supported() on intel_display.c and
> skl_plane_format_mod_supported() on intel_sprite.c. At that time they
> were different, but right now they are exactly the same, name and
> tabs
> included. Remove one of the copies and make the other non-static.
>
> Given how our hardware has evolved it is unlikely that future
> platforms will require a different format_mod_supported() function
> for
> the primary plane vs the sprite plane, and we can always bring
> back
> the additional copy if we need.
Quick review since I knew the function had a duplicate.
Reviewed-by: Dhinakaran Pandiyan
Also noticed that the modifier arrays are exact copies but the pixel
format arrays look different.
>
> Cc: Ville Syrjälä
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_display.c | 50 --
> --
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_sprite.c | 4 +--
> 3 files changed, 4 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a21ec8ae46f6..b9a0183dc580 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13410,56 +13410,6 @@ static bool
> i965_plane_format_mod_supported(struct drm_plane *_plane,
> }
> }
>
> -static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> -u32 format, u64 modifier)
> -{
> - struct intel_plane *plane = to_intel_plane(_plane);
> -
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - case I915_FORMAT_MOD_Y_TILED:
> - case I915_FORMAT_MOD_Yf_TILED:
> - break;
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (!plane->has_ccs)
> - return false;
> - break;
> - default:
> - return false;
> - }
> -
> - switch (format) {
> - case DRM_FORMAT_XRGB:
> - case DRM_FORMAT_XBGR:
> - case DRM_FORMAT_ARGB:
> - case DRM_FORMAT_ABGR:
> - if (is_ccs_modifier(modifier))
> - return true;
> - /* fall through */
> - case DRM_FORMAT_RGB565:
> - case DRM_FORMAT_XRGB2101010:
> - case DRM_FORMAT_XBGR2101010:
> - case DRM_FORMAT_YUYV:
> - case DRM_FORMAT_YVYU:
> - case DRM_FORMAT_UYVY:
> - case DRM_FORMAT_VYUY:
> - case DRM_FORMAT_NV12:
> - if (modifier == I915_FORMAT_MOD_Yf_TILED)
> - return true;
> - /* fall through */
> - case DRM_FORMAT_C8:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> - return true;
> - /* fall through */
> - default:
> - return false;
> - }
> -}
> -
> static bool intel_cursor_format_mod_supported(struct drm_plane
> *_plane,
> u32 format, u64
> modifier)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index bf1c38728a59..313337f03da8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2140,6 +2140,8 @@ unsigned int skl_plane_max_stride(struct
> intel_plane *plane,
> unsigned int rotation);
> int skl_plane_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> +bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> + u32 format, u64 modifier);
> int intel_plane_check_src_coordinates(struct intel_plane_state
> *plane_state);
> int chv_plane_check_rotation(const struct intel_plane_state
> *plane_state);
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 8821e59b70ea..db297d257e1e 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1609,8 +1609,8 @@ static bool
> vlv_sprite_format_mod_supported(struct drm_plane *_plane,
> }
> }
>
> -static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> -u32 format, u64 modifier)
> +bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> + u32 format, u64 modifier)
> {
> struct intel_plane *plane = to_intel_plane(_plane);
>
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