Re: [Intel-gfx] [PATCH v7 01/23] drm/i915: make encoder enable and disable hooks optional
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Encoders are not alike, make enable and disable hooks optional like
other hooks. Utilize this in DSI code, and remove the silly nop hook.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/vlv_dsi.c | 16
2 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 41abd03ce6a6..32ea71bac663 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5461,7 +5461,8 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
if (conn_state->crtc != crtc)
continue;
- encoder->enable(encoder, crtc_state, conn_state);
+ if (encoder->enable)
+ encoder->enable(encoder, crtc_state, conn_state);
intel_opregion_notify_encoder(encoder, true);
}
}
@@ -5482,7 +5483,8 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
continue;
intel_opregion_notify_encoder(encoder, false);
- encoder->disable(encoder, old_crtc_state, old_conn_state);
+ if (encoder->disable)
+ encoder->disable(encoder, old_crtc_state,
old_conn_state);
}
encoder->disable() gets called directly inside intel_sanitize_encoder()
without
intel_encoders_disable().I think, we need to put the check there as well.
With that fix,
Reviewed-by: Madhav Chauhan
Regards,
Madhav
}
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bafeb2a19b90..dbca30460a6b 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -794,6 +794,10 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi,
int msec)
* - wait t4 - wait t4
*/
+/*
+ * DSI port enable has to be done before pipe and plane enable, so we do it in
+ * the pre_enable hook instead of the enable hook.
+ */
static void intel_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
@@ -896,17 +900,6 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder,
}
/*
- * DSI port enable has to be done before pipe and plane enable, so we do it in
- * the pre_enable hook.
- */
-static void intel_dsi_enable_nop(struct intel_encoder *encoder,
-const struct intel_crtc_state *pipe_config,
-const struct drm_connector_state *conn_state)
-{
- DRM_DEBUG_KMS("\n");
-}
-
-/*
* DSI port disable has to be done after pipe and plane disable, so we do it
in
* the post_disable hook.
*/
@@ -1764,7 +1757,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
intel_encoder->compute_config = intel_dsi_compute_config;
intel_encoder->pre_enable = intel_dsi_pre_enable;
- intel_encoder->enable = intel_dsi_enable_nop;
intel_encoder->disable = intel_dsi_disable;
intel_encoder->post_disable = intel_dsi_post_disable;
intel_encoder->get_hw_state = intel_dsi_get_hw_state;
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports (rev5)
== Series Details == Series: Refactor and Add helper function for combophy/tc ports (rev5) URL : https://patchwork.freedesktop.org/series/50484/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4984_full -> Patchwork_10467_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10467_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10467_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10467_full: === IGT changes === Warnings igt@drm_read@empty-nonblock: shard-snb: PASS -> SKIP +3 == Known issues == Here are the changes found in Patchwork_10467_full that come from known issues: === IGT changes === Issues hit igt@gem_cpu_reloc@full: shard-skl: NOTRUN -> INCOMPLETE (fdo#108073) igt@gem_exec_schedule@pi-ringfull-vebox: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@gem_wait@busy-default: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-skl: NOTRUN -> FAIL (fdo#105458) igt@kms_cursor_crc@cursor-256x256-random: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_draw_crc@fill-fb: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_flip@flip-vs-expired-vblank: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: shard-apl: SKIP -> INCOMPLETE (fdo#103927) igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-apl: PASS -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +2 igt@kms_plane_lowres@pipe-c-tiling-x: shard-kbl: PASS -> DMESG-WARN (fdo#105345) igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_psr@suspend: shard-skl: PASS -> INCOMPLETE (fdo#107773) igt@kms_rotation_crc@exhaust-fences: shard-skl: NOTRUN -> DMESG-WARN (fdo#105748) Possible fixes igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip_tiling@flip-yf-tiled: shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: DMESG-FAIL (fdo#103167, fdo#103558, fdo#105602) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_lowres@pipe-a-tiling-yf: shard-kbl: DMESG-WARN (fdo#105345) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +2 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#10
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports (rev5)
== Series Details == Series: Refactor and Add helper function for combophy/tc ports (rev5) URL : https://patchwork.freedesktop.org/series/50484/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10467 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/5/mbox/ == Known issues == Here are the changes found in Patchwork_10467 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (53 -> 46) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 == Build changes == * Linux: CI_DRM_4984 -> Patchwork_10467 CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10467: 3cc221173ac3118a71378cf5e0ad68c12af019f2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3cc221173ac3 drm/i915/icl: Fix DDI/TC port clk_off bits 76fe790f6910 drm/i915/icl: Introduce new macros to get combophy registers fe97027237f6 drm/i915/icl: Combine all port/combophy macros at one place d44e98562823 drm/i915/icl: Refactor icl pll functions 7e97618174e4 drm/i915/icl: Use helper functions to classify the ports 1d213780b313 drm/i915/icl: Refactor get_ddi_pll using helper func 99f69dd6d4e8 drm/i915/icl: use combophy/TC helper functions during display detection 7a0475e44ad4 drm/i915/icl: create function to identify combophy port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10467/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/atomic_helper: Stop modesets on unregistered connectors harder
== Series Details ==
Series: drm/atomic_helper: Stop modesets on unregistered connectors harder
URL : https://patchwork.freedesktop.org/series/51041/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10466 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10466 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10466, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/51041/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10466:
=== IGT changes ===
Possible regressions
igt@drv_module_reload@basic-reload:
fi-kbl-8809g: PASS -> DMESG-WARN +3
igt@drv_module_reload@basic-reload-inject:
fi-skl-6260u: PASS -> DMESG-WARN
fi-snb-2600:PASS -> DMESG-WARN
fi-kbl-7560u: PASS -> DMESG-WARN
fi-kbl-guc: PASS -> DMESG-WARN
fi-skl-6770hq: PASS -> DMESG-WARN
fi-bwr-2160:PASS -> DMESG-WARN
fi-kbl-r: PASS -> DMESG-WARN
fi-cfl-s3: PASS -> DMESG-WARN
fi-byt-clapper: PASS -> DMESG-WARN
fi-gdg-551: PASS -> DMESG-WARN
fi-icl-u2: PASS -> DMESG-WARN
fi-bsw-kefka: PASS -> DMESG-WARN
fi-bdw-gvtdvm: PASS -> DMESG-WARN
fi-ilk-650: PASS -> DMESG-WARN
fi-bsw-n3050: PASS -> DMESG-WARN
fi-cnl-u: PASS -> DMESG-WARN
fi-kbl-7567u: PASS -> DMESG-WARN +2
fi-glk-j4005: PASS -> DMESG-WARN
fi-skl-iommu: PASS -> DMESG-WARN
fi-ivb-3770:PASS -> DMESG-WARN
fi-skl-gvtdvm: PASS -> DMESG-WARN
fi-whl-u: PASS -> DMESG-WARN
fi-skl-6700hq: PASS -> DMESG-WARN
fi-ivb-3520m: PASS -> DMESG-WARN
fi-glk-dsi: PASS -> DMESG-WARN
fi-bdw-5557u: PASS -> DMESG-WARN
{fi-apl-guc}: PASS -> DMESG-WARN
fi-cfl-8700k: PASS -> DMESG-WARN
fi-icl-u: NOTRUN -> DMESG-WARN
fi-kbl-x1275: PASS -> DMESG-WARN
fi-skl-6600u: PASS -> DMESG-WARN
fi-pnv-d510:PASS -> DMESG-WARN
fi-skl-guc: PASS -> DMESG-WARN
fi-cfl-guc: PASS -> DMESG-WARN
fi-skl-6700k2: PASS -> DMESG-WARN
fi-elk-e7500: PASS -> DMESG-WARN
igt@pm_rpm@module-reload:
fi-cfl-8109u: PASS -> DMESG-WARN +2
fi-kbl-7500u: PASS -> DMESG-WARN +2
== Known issues ==
Here are the changes found in Patchwork_10466 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_getparams_basic@basic-subslice-total:
fi-snb-2520m: PASS -> DMESG-WARN (fdo#103713) +10
igt@drv_module_reload@basic-reload-inject:
fi-bxt-j4205: PASS -> DMESG-WARN (fdo#107821)
fi-bxt-dsi: PASS -> DMESG-WARN (fdo#107821)
fi-hsw-4770:PASS -> DMESG-WARN (fdo#107924)
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#107924)
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107924)
igt@drv_selftest@live_hangcheck:
fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108315)
igt@kms_flip@basic-flip-vs-modeset:
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) +1
Possible fixes
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#107821 https://bugs.freedesktop.org/show_bug.cgi?id=107821
fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
== Participating hosts (53 -> 47) ==
Additional (1): fi-icl-u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820
== Build changes ==
* Linux: CI_DRM_4984 -> Patchwork_10466
CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10466: 26909bc1ea409e674f04fca95b55bed4c69caa9c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
26909bc1ea40 drm/atomic_helper: Stop modesets on unregistered connectors harder
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10466/issues.html
___
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Fix power domain reference balance when DMC firmware is not present
== Series Details == Series: series starting with [1/2] drm/i915: Fix power domain reference balance when DMC firmware is not present URL : https://patchwork.freedesktop.org/series/51039/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4984_full -> Patchwork_10465_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10465_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10465_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10465_full: === IGT changes === Warnings igt@drm_read@empty-nonblock: shard-snb: PASS -> SKIP +3 == Known issues == Here are the changes found in Patchwork_10465_full that come from known issues: === IGT changes === Issues hit igt@gem_cpu_reloc@full: shard-skl: NOTRUN -> INCOMPLETE (fdo#108073) igt@gem_ctx_isolation@vcs0-s3: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) igt@gem_exec_schedule@pi-ringfull-vebox: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_wait@busy-default: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-skl: NOTRUN -> FAIL (fdo#105458) igt@kms_cursor_crc@cursor-256x85-sliding: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_draw_crc@fill-fb: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_panel_fitting@legacy: shard-skl: NOTRUN -> FAIL (fdo#105456) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: shard-skl: PASS -> FAIL (fdo#103191, fdo#107362) igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-apl: PASS -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +3 igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_rotation_crc@exhaust-fences: shard-skl: NOTRUN -> DMESG-WARN (fdo#105748) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) Possible fixes igt@kms_cursor_crc@cursor-64x64-dpms: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_flip_tiling@flip-yf-tiled: shard-apl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: DMESG-FAIL (fdo#105602, fdo#103558, fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_lowres@pipe-a-tiling-yf: shard-kbl: DMESG-WARN (fdo#105345) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?i
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports (rev5)
== Series Details == Series: Refactor and Add helper function for combophy/tc ports (rev5) URL : https://patchwork.freedesktop.org/series/50484/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7a0475e44ad4 drm/i915/icl: create function to identify combophy port 99f69dd6d4e8 drm/i915/icl: use combophy/TC helper functions during display detection 1d213780b313 drm/i915/icl: Refactor get_ddi_pll using helper func 7e97618174e4 drm/i915/icl: Use helper functions to classify the ports d44e98562823 drm/i915/icl: Refactor icl pll functions fe97027237f6 drm/i915/icl: Combine all port/combophy macros at one place 76fe790f6910 drm/i915/icl: Introduce new macros to get combophy registers 3cc221173ac3 drm/i915/icl: Fix DDI/TC port clk_off bits -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9314: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ + 21 : (tc_port) + 12)) total: 0 errors, 0 warnings, 1 checks, 54 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/lspcon: Fix Parade LSPCON scrambling fail
Regards
Shashank
On 10/13/2018 12:58 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 10:17:57PM +0300, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 10/13/2018 12:08 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate when switching from a mode that needs them to a mode that does
not. This manifests as a "no signal" on my TV when I try to go from
4k to 1080p for example. Resetting the SCDC register bits with
i2cset is sufficient to restore the picture to the screen.
Here's the OUI/fw revision for the LSPCON chip in question:
DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32 quirks 0x
Asking users to poke at SCDC with i2cset is a bit much, so
let's work around this in the driver. We don't need to go all
out here and compute whether scrambling is needed or not as
LSPCON will do that itself. If scrambling is actually
required LSPCON does not forget to enable it.
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 52 ---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 5 ++-
3 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 47960c92cbbf..ef502fc9add1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2984,6 +2984,23 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
}
+static void intel_ddi_pre_enable_lspcon(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ intel_ddi_pre_enable(encoder, crtc_state, conn_state);
+
+ /*
+* Parade LSPCON forgets to turn off scrambling/bit clock rate
+* when switching from a mode that needs them to a mode that
+* does not.
+*/
+ intel_hdmi_handle_sink_scrambling(encoder, conn_state->connector,
+ &intel_dp->aux.ddc, false, false);
+}
+
static void intel_disable_ddi_buf(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3086,6 +3103,23 @@ static void intel_ddi_post_disable(struct intel_encoder
*encoder,
old_crtc_state, old_conn_state);
}
+static void intel_ddi_post_disable_lspcon(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ /*
+* Parade LSPCON forgets to turn off scrambling/bit clock rate
+* when switching from a mode that needs them to a mode that
+* does not.
+*/
+ intel_hdmi_handle_sink_scrambling(encoder, old_conn_state->connector,
+ &intel_dp->aux.ddc, false, false);
+
+ intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
+}
Few thoughts:
- Would it make more sense to move these 2 functions to intel_lspcon.c ?
Would require more non-statics. But I guess it might be nice to attempt
isolating it as much as possible.
- And then add a lspcon->vendor == VENDOR_PARADE check, so that we will
run the code only when needed.
Maybe. The ->vendor thing isn't in yet, and we'd have to backport it
as well. Is it big?
Also at this time I have no idea whether Megachips LSPCON is similarly
bugged. Would need to find one and test it.
Oh, and another open question is what happens if one of these chips is
in a DP->HDMI 2.0 dongle. In that case we might end up needing the same
workaround in the normal DP codepath as well :(
You are right, that would be a LSPCON in a dongle configuration (this
one is motherboard down configuration), which we are not officially
supporting yet.
That might come with its own complexity. I think we already have a BZ
for such a Parade dongle adapter.
- Shashank
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Re: [Intel-gfx] [PATCH] drm/i915/lspcon: Fix Parade LSPCON scrambling fail
Regards
Shashank
On 10/13/2018 12:47 AM, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:26:57AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 10/13/2018 12:08 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The Parade LSPCON on KBL NUCs forgets to turn off scrambling/bit clock
rate when switching from a mode that needs them to a mode that does
not. This manifests as a "no signal" on my TV when I try to go from
4k to 1080p for example. Resetting the SCDC register bits with
i2cset is sufficient to restore the picture to the screen.
Here's the OUI/fw revision for the LSPCON chip in question:
DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32 quirks 0x
Asking users to poke at SCDC with i2cset is a bit much, so
let's work around this in the driver. We don't need to go all
out here and compute whether scrambling is needed or not as
LSPCON will do that itself. If scrambling is actually
required LSPCON does not forget to enable it.
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 52 ---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 5 ++-
3 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 47960c92cbbf..ef502fc9add1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2984,6 +2984,23 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
}
+static void intel_ddi_pre_enable_lspcon(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ intel_ddi_pre_enable(encoder, crtc_state, conn_state);
+
+ /*
+* Parade LSPCON forgets to turn off scrambling/bit clock rate
+* when switching from a mode that needs them to a mode that
+* does not.
+*/
+ intel_hdmi_handle_sink_scrambling(encoder, conn_state->connector,
+ &intel_dp->aux.ddc, false, false);
+}
+
static void intel_disable_ddi_buf(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3086,6 +3103,23 @@ static void intel_ddi_post_disable(struct intel_encoder
*encoder,
old_crtc_state, old_conn_state);
}
+static void intel_ddi_post_disable_lspcon(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ /*
+* Parade LSPCON forgets to turn off scrambling/bit clock rate
+* when switching from a mode that needs them to a mode that
+* does not.
+*/
+ intel_hdmi_handle_sink_scrambling(encoder, old_conn_state->connector,
+ &intel_dp->aux.ddc, false, false);
+
+ intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
+}
Few thoughts:
- Would it make more sense to move these 2 functions to intel_lspcon.c ?
Would require more non-statics. But I guess it might be nice to attempt
isolating it as much as possible.
- And then add a lspcon->vendor == VENDOR_PARADE check, so that we will
run the code only when needed.
Maybe. The ->vendor thing isn't in yet, and we'd have to backport it
as well. Is it big?
The LSPCON patches are merged now, we can directly use the vendor check
now.
Also at this time I have no idea whether Megachips LSPCON is similarly
bugged. Would need to find one and test it.
That would be best, we will have to do that anyways for compliance
issues sooner or later :-)
- Also, we should check if scrambling is enabled, there might be a case
where we are driving a HDMI 2.0 display (scrambling->supported = 1) but
current mode is 1080 P.
As explained in the commit message this is not needed. And currently we
have no idea whether LSPCON will enable scrambling or not. Adding code
to determine that would mean second guessing what LSPCON will do. I
don't see any benefit in doing that.
Humm, I guess this can be determined with few checks, and HDMI spec
mendates:
- clock above 340Mhz ? LSPCON must enable scrambling
- clock below 340Mhz && monitor supports scrambling below 340Mhz ?
LSPCON should enable scrambling : LSPCON mustn't enable scrambling.
This will make sure that we are doing what's recommended by spec.
- Shashank
- Shashank
+
void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
const struct intel_crtc_state *old
[Intel-gfx] [PATCH v2] drm/i915/icl: Fix DDI/TC port clk_off bits
From: Mahesh Kumar
DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.
v2: Add fixes tag (Lucas)
Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
Signed-off-by: Mahesh Kumar
Signed-off-by: Vandita Kulkarni
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ddi.c | 21 ++---
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 590574e1ffa7..2366b95f5965 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9310,6 +9310,9 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 :
\
(port) + 10))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+ 21 : (tc_port) + 12))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e0a91b6080d..6b9742baa5f2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2740,6 +2740,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
}
+static inline
+uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (intel_port_is_combophy(dev_priv, port)) {
+ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ } else if (intel_port_is_tc(dev_priv, port)) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+ return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
+ }
+
+ return 0;
+}
+
void icl_map_plls_to_ports(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct drm_atomic_state *old_state)
@@ -2763,7 +2778,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
+ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
if (intel_port_is_combophy(dev_priv, port)) {
val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
@@ -2772,7 +2787,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
POSTING_READ(DPCLKA_CFGCR0_ICL);
}
- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@@ -2800,7 +2815,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
mutex_lock(&dev_priv->dpll_lock);
I915_WRITE(DPCLKA_CFGCR0_ICL,
I915_READ(DPCLKA_CFGCR0_ICL) |
- DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+ icl_dpclka_cfgcr0_clk_off(dev_priv, port));
mutex_unlock(&dev_priv->dpll_lock);
}
}
--
2.19.1.1.g8c3cf03f71
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[Intel-gfx] [PATCH v2] drm/i915/icl: Introduce new macros to get combophy registers
combo-phy register instances are at same offset from base for each
combo-phy port, i.e.
Port A base offset: 0x16200
Port B base offset: 0x6C000
All the other addresses for both ports can be derived by calculating
offset to these base addresses.
PORT_CL_DW_OFFSET 0x0
PORT_CL_DW 0 + x * 4
PORT_COMP_OFFSET0x100
PORT_COMP_DW 0x100 + x * 4
PORT_PCS_AUX_OFFSET 0x300
PORT_PCS_GRP_OFFSET 0x600
PORT_PCS_LN_OFFSET 0x800 + y * 0x100
PORT_TX_AUX_OFFSET 0x380
PORT_TX_GRP_OFFSET 0x680
PORT_TX_LN_OFFSET0x880 + y * 0x100
And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
Based on original patch by Mahesh Kumar .
v2: make port, dw and ln arguments follow the order in
register's name
Signed-off-by: Lucas De Marchi
Signed-off-by: Mahesh Kumar
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 163
1 file changed, 59 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fe81dd76734..590574e1ffa7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,20 +1658,21 @@ enum i915_power_well_id {
/*
* CNL/ICL Port/COMBO-PHY Registers
*/
+#define _ICL_COMBOPHY_A0x162000
+#define _ICL_COMBOPHY_B0x6C000
+#define _ICL_COMBOPHY(port)_PICK(port, _ICL_COMBOPHY_A, \
+ _ICL_COMBOPHY_B)
+
/* CNL/ICL Port CL_DW registers */
-#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
-#define _ICL_PORT_CL_DW5_A 0x162014
-#define _ICL_PORT_CL_DW5_B 0x6C014
-#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
-_ICL_PORT_CL_DW5_B)
+#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
+4 * (dw))
+
+#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
+#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
#define CL_POWER_DOWN_ENABLE (1 << 4)
#define SUS_CLOCK_CONFIG (3 << 0)
-#define _CNL_PORT_CL_DW10_A0x162028
-#define _ICL_PORT_CL_DW10_B0x6c028
-#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port,\
- _CNL_PORT_CL_DW10_A, \
- _ICL_PORT_CL_DW10_B)
+#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
#define PG_SEQ_DELAY_OVERRIDE_MASK(3 << 25)
#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
@@ -1687,31 +1688,23 @@ enum i915_power_well_id {
#define PWR_DOWN_LN_MASK (0xf << 4)
#define PWR_DOWN_LN_SHIFT 4
-#define _ICL_PORT_CL_DW12_A0x162030
-#define _ICL_PORT_CL_DW12_B0x6C030
+#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
#define ICL_LANE_ENABLE_AUX (1 << 0)
-#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
- _ICL_PORT_CL_DW12_A, \
- _ICL_PORT_CL_DW12_B)
/* CNL/ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP 0x100
+#define _ICL_PORT_COMP_DW(dw, port)(_ICL_COMBOPHY(port) + \
+_ICL_PORT_COMP + 4 * (dw))
+
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
-#define _ICL_PORT_COMP_DW0_A 0x162100
-#define _ICL_PORT_COMP_DW0_B 0x6C100
-#define ICL_PORT_COMP_DW0(port)_MMIO_PORT(port,
_ICL_PORT_COMP_DW0_A, \
-_ICL_PORT_COMP_DW0_B)
+#define ICL_PORT_COMP_DW0(port)_MMIO(_ICL_PORT_COMP_DW(0,
port))
#define COMP_INIT(1 << 31)
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
-#define _ICL_PORT_COMP_DW1_A 0x162104
-#define _ICL_PORT_COMP_DW1_B 0x6C104
-#define ICL_PORT_COMP_DW1(port)_MMIO_PORT(port,
_ICL_PORT_COMP_DW1_A, \
-_ICL_PORT_COMP_DW1_B)
+#define ICL_PORT_COMP_DW1(port)_MMIO(_ICL_PORT_COMP_DW(1,
port))
+
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
-#define _ICL_PORT_COMP_DW3_A 0x16210C
-#define _ICL_PORT_COMP_DW3_B 0x6C10C
-#define ICL_PORT_COMP_DW3(port)_MMIO_PORT(port,
_ICL_PORT_COMP_DW3_A, \
-_ICL_PORT_COMP_DW3_B)
+#define ICL_PORT_COMP_DW3(port)_MMIO(_ICL_PORT_COMP_DW(3,
port))
#define PROCESS_INFO_DOT_0 (0 << 26)
#define PROCESS_INFO_DOT_1 (1 << 26)
#define PROCESS_INFO_DOT_4 (2 << 26)
@@ -1724,17 +1717,10 @@ enum i915_power_well_id {
#define VOLTAGE_INFO_SH
[Intel-gfx] [PATCH] drm/atomic_helper: Stop modesets on unregistered connectors harder
Unfortunately, it appears our fix in:
commit b5d29843d8ef ("drm/atomic_helper: Allow DPMS On<->Off changes
for unregistered connectors")
Which attempted to work around the problems introduced by:
commit 4d80273976bf ("drm/atomic_helper: Disallow new modesets on
unregistered connectors")
Is still not the right solution, as modesets can still be triggered
outside of drm_atomic_set_crtc_for_connector().
So in order to fix this, while still being careful that we don't break
modesets that a driver may perform before being registered with
userspace, we replace connector->registered with a tristate member,
connector->registration_state. This allows us to keep track of whether
or not a connector is still initializing and hasn't been exposed to
userspace, is currently registered and exposed to userspace, or has been
legitimately removed from the system after having once been present.
Using this info, we can prevent userspace from performing new modesets
on unregistered connectors while still allowing the driver to perform
modesets on unregistered connectors before the driver has finished being
registered.
Fixes: b5d29843d8ef ("drm/atomic_helper: Allow DPMS On<->Off changes for
unregistered connectors")
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org
Cc: David Airlie
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_atomic_helper.c | 60 +
drivers/gpu/drm/drm_atomic_uapi.c | 21 -
drivers/gpu/drm/drm_connector.c | 10 ++---
drivers/gpu/drm/i915/intel_dp_mst.c | 8 ++--
include/drm/drm_connector.h | 68 -
5 files changed, 127 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 6f66777dca4b..6cadeaf28ae4 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -529,6 +529,35 @@ mode_valid(struct drm_atomic_state *state)
return 0;
}
+static int
+unregistered_connector_check(struct drm_atomic_state *state,
+struct drm_connector *connector,
+struct drm_connector_state *old_conn_state,
+struct drm_connector_state *new_conn_state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+
+ if (!drm_connector_unregistered(connector))
+ return 0;
+
+ crtc = new_conn_state->crtc;
+ if (!crtc)
+ return 0;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ if (!crtc_state || !drm_atomic_crtc_needs_modeset(crtc_state))
+ return 0;
+
+ if (crtc_state->mode_changed) {
+ DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] can't change mode on
unregistered connector\n",
+connector->base.id, connector->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/**
* drm_atomic_helper_check_modeset - validate state object for modeset changes
* @dev: DRM device
@@ -684,18 +713,33 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
return ret;
}
- /*
-* Iterate over all connectors again, to make sure atomic_check()
-* has been called on them when a modeset is forced.
-*/
for_each_oldnew_connector_in_state(state, connector,
old_connector_state, new_connector_state, i) {
const struct drm_connector_helper_funcs *funcs =
connector->helper_private;
- if (connectors_mask & BIT(i))
- continue;
+ /* Make sure atomic_check() is called on any unchecked
+* connectors when a modeset has been forced
+*/
+ if (connectors_mask & BIT(i) && funcs->atomic_check) {
+ ret = funcs->atomic_check(connector,
+ new_connector_state);
+ if (ret)
+ return ret;
+ }
- if (funcs->atomic_check)
- ret = funcs->atomic_check(connector,
new_connector_state);
+ /*
+* Prevent userspace from turning on new displays or setting
+* new modes using connectors which have been removed from
+* userspace. This is racy since an unplug could happen at any
+* time including after this check, but that's OK: we only
+* care about preventing userspace from trying to set invalid
+* state using destroyed connectors that it's been notified
+* about. No one can save us after the atomic check completes
+* but ourselves.
+*/
+ ret = unregistered_connector_check(state,
+ connector,
+ old_co
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix power domain reference balance when DMC firmware is not present
== Series Details == Series: series starting with [1/2] drm/i915: Fix power domain reference balance when DMC firmware is not present URL : https://patchwork.freedesktop.org/series/51039/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10465 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51039/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10465 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: PASS -> FAIL (fdo#103167) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (53 -> 47) == Additional (1): fi-icl-u Missing(7): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 == Build changes == * Linux: CI_DRM_4984 -> Patchwork_10465 CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10465: be186bd6a687fce3e74f76640daf026f1d09cb90 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == be186bd6a687 drm/i915: Do not print DC off mismatch state when DMC firmware in not loaded 39f4c897f58b drm/i915: Fix power domain reference balance when DMC firmware is not present == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10465/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/16] drm/i915: Do not print DC off mismatch state when DMC firmware in not loaded
On Mon, 2018-10-15 at 13:58 +0300, Imre Deak wrote:
> On Fri, Oct 12, 2018 at 02:52:15PM -0700, José Roberto de Souza
> wrote:
> > When DMC firmware is not loaded, it return earlier in
> > gen9_dc_off_power_well_disable() as it will have no effect without
> > DMC firmware loaded. But it will cause a mismatch state error when
> > running intel_power_domains_verify_state(), so skipping this error
> > in this case.
>
> DC states are disabled when DMC is not loaded and we won't ever
> enable
> them, as runtime PM as a whole is disabled. So not sure why you get a
> mismatch error, but ignoring that by special casing it doesn't seem
> correct.
I just found out a bug that was hidden this bug from drm-tip, I just
sent a separated PR(https://patchwork.freedesktop.org/series/51039/)
with this patch and the fix please take a look.
But it was hidden because at every call to
intel_power_domains_verify_state() something was holding a reference to
one of DC_OFF domains, keeping it in the on state that means DC is
disabaled.
If you run drm-tip with the fix without any output all references to
DC_OFF domain will be release but as DMC firmware was not loaded DC is
not actualy enabled causing the state mismatch.
A easy way to reproduce is just run drm-tip with disable_display=1 and
check the error message in dmesg.
Although I'm not 100% happy with the way that I'm identifying DC_OFF
power well, do you have suggestion?
>
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 -
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 8b1c4d0db0af..629091ad8337 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -4014,11 +4014,22 @@ static void
> > intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
> > enabled = power_well->desc->ops->is_enabled(dev_priv,
> > power_well)
> > ;
> > if ((power_well->count || power_well->desc->always_on)
> > !=
> > - enabled)
> > + enabled) {
> > + /* If DMC firmware is not loaded it could cause
> > a
> > +* mismatch state as we can't disable DC off,
> > so let's
> > +* do not print any errors in this scenario.
> > +*/
> > +
> > + if (!strcmp("DC off", power_well->desc->name)
> > &&
> > + !dev_priv->csr.dmc_payload)
> > + goto skip_state_mismatch_error;
> > +
> > DRM_ERROR("power well %s state mismatch
> > (refcount %d/enabled %d)",
> > power_well->desc->name,
> > power_well->count, enabled);
> > + }
> >
> > +skip_state_mismatch_error:
> > domains_count = 0;
> > for_each_power_domain(domain, power_well->desc-
> > >domains)
> > domains_count += power_domains-
> > >domain_use_count[domain];
> > --
> > 2.19.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Do not print DC off mismatch state when DMC firmware in not loaded
When DMC firmware is not loaded, it return earlier in
gen9_dc_off_power_well_disable() as it will have no effect without
DMC firmware loaded. But it will cause a mismatch state error when
running intel_power_domains_verify_state(), so skipping this error
in this case.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3cf8533e0834..99edfcafc106 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3980,11 +3980,22 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *dev_priv)
enabled = power_well->desc->ops->is_enabled(dev_priv,
power_well);
if ((power_well->count || power_well->desc->always_on) !=
- enabled)
+ enabled) {
+ /* If DMC firmware is not loaded it could cause a
+* mismatch state as we can't disable DC off, so let's
+* do not print any errors in this scenario.
+*/
+
+ if (!strcmp("DC off", power_well->desc->name) &&
+ !dev_priv->csr.dmc_payload)
+ goto skip_state_mismatch_error;
+
DRM_ERROR("power well %s state mismatch (refcount
%d/enabled %d)",
power_well->desc->name,
power_well->count, enabled);
+ }
+skip_state_mismatch_error:
domains_count = 0;
for_each_power_domain(domain, power_well->desc->domains)
domains_count +=
power_domains->domain_use_count[domain];
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Fix power domain reference balance when DMC firmware is not present
intel_csr_ucode_init() gets a POWER_DOMAIN_INIT reference but it is
only released in csr_load_work_fn() if DMC firmware is present in
filesystem, keeping a reference to POWER_DOMAIN_INIT and every power
well enabled all the times.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index fc7bd21fa586..7c91a56869e9 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -423,8 +423,6 @@ static void csr_load_work_fn(struct work_struct *work)
if (dev_priv->csr.dmc_payload) {
intel_csr_load_program(dev_priv);
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
-
DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
dev_priv->csr.fw_path,
CSR_VERSION_MAJOR(csr->version),
@@ -439,6 +437,8 @@ static void csr_load_work_fn(struct work_struct *work)
}
release_firmware(fw);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
}
/**
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 16/28] drm/i915/dsc: Define & Compute VESA DSC params
Ville/Jani,
Could you please look at the logistics of the patch and ACK this?
This has been validated and tested on the DSC panel.
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:54PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This patches does the following:
>
> 1. This patch defines all the DSC parameters as per the VESA
> DSC specification. These are stored in the encoder and used
> to compute the PPS parameters to be sent to the Sink.
> 2. Compute all the DSC parameters which are derived from DSC
> state of intel_crtc_state.
> 3. Compute all parameters that are VESA DSC specific
>
> This computation happens in the atomic check phase during
> compute_config() to validate if display stream compression
> can be enabled for the requested mode.
>
> v7: (From Manasi)
> * Dont use signed int for rc_range_params (Manasi)
> * Mask the range_bpg_offset to use only 6 bits
> * Add SPDX identifier (Chris Wilson)
> v6 (From Manasi):
> * Add a check for line_buf_depth return value (Anusha)
> * Remove DRM DSC constants to different patch (Manasi)
> v5 (From Manasi):
> * Add logic to limit the max line buf depth for DSC 1.1 to 13
> as per DSC 1.1 spec
> * Fix dim checkpatch warnings/checks
>
> v4 (From Gaurav):
> * Rebase on latest drm tip
> * rename variable name(Manasi)
> * Populate linebuf_depth variable(Manasi)
>
> v3 (From Gaurav):
> * Rebase my previous patches on top of Manasi's latest patch
> series
> * Using >>n rather than /2^n (Manasi)
> * Change the commit message to explain what the patch is doing(Gaurav)
>
> Fixed review comments from Ville:
> * Don't use macro TWOS_COMPLEMENT
> * Mention in comment about the source of RC params
> * Return directly from case statements
> * Using single asssignment for assigning rc_range_params
> * Using < about the fixed point numbers
>
> v2 (From Manasi):
> * Update logic for minor version to consider the dpcd value
> and what supported by the HW platform
> * Use DRM DSC config struct instead of intel_dp struct
> * Move the DSC constants to DRM DSC header file
> * Use u16, u8 where bigger data types not needed
> * * Compute the DSC parameters as part of DSC compute config
> since the computation can fail (Manasi)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Co-developed-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 7 +
> drivers/gpu/drm/i915/intel_drv.h | 4 +
> drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
> include/drm/drm_dp_helper.h | 3 +
> 5 files changed, 471 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ef1480c14e4e..127efb2948a7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -154,7 +154,8 @@ i915-y += dvo_ch7017.o \
> intel_sdvo.o \
> intel_tv.o \
> vlv_dsi.o \
> - vlv_dsi_pll.o
> + vlv_dsi_pll.o \
> + intel_vdsc.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 05300d82b202..89990a96263b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2073,6 +2073,13 @@ static bool intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> return false;
> }
> }
> + if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
> + DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
> %d"
> + "Compressed BPP = %d\n",
> + pipe_config->pipe_bpp,
> + pipe_config->dsc_params.compressed_bpp);
> + return false;
> + }
> pipe_config->dsc_params.compression_enable = true;
> DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
> "Compressed Bpp = %d Slice Count = %d\n",
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 443afe97423a..36089c77e493 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1760,6 +1760,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
> uint8_t lane_count,
> uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int
> mode_clock,
>int mode_hdisplay);
>
> +/* intel_vdsc.c */
> +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config);
> +
> static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> {
> return ~((1 << lane_count) - 1) & 0xf;
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> b/drivers/gpu/drm/i915/inte
Re: [Intel-gfx] [PATCH v5 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
Hi Jani,
This patch has a verbal ACK from you when we went over the patch together,
This is rebased on top of edp fast/narrow optimized config like we discussed.
could you please review this?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:51PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice ocunt and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++-
> drivers/gpu/drm/i915/intel_display.h | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 4 files changed, 155 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 36434c5359b1..4ebf7c83085c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6532,7 +6532,7 @@ static int ironlake_fdi_compute_config(struct
> intel_crtc *intel_crtc,
>
> pipe_config->fdi_lanes = lane;
>
> - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> link_bw, &pipe_config->fdi_m_n, false);
>
> ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6767,17 +6767,25 @@ static void compute_m_n(unsigned int m, unsigned int
> n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> {
> m_n->tu = 64;
>
> - compute_m_n(bits_per_pixel * pixel_clock,
> - link_clock * nlanes * 8,
> - &m_n->gmch_m, &m_n->gmch_n,
> - constant_n);
> + /* For DSC, Data M/N calculation uses compressed BPP */
> + if (compressed_bpp)
> + compute_m_n(compressed_bpp * pixel_clock,
> + link_clock * nlanes * 8,
> + &m_n->gmch_m, &m_n->gmch_n,
> + constant_n);
> + else
> + compute_m_n(bits_per_pixel * pixel_clock,
> + link_clock * nlanes * 8,
> + &m_n->gmch_m, &m_n->gmch_n,
> + constant_n);
>
> compute_m_n(pixel_clock, link_clock,
> &m_n->link_m, &m_n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 9fac67e31205..9eaba1bccae8 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -402,7 +402,8 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> + int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8e6891356d5b..05300d82b202 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
> @@ -1894,6 +1896,16 @@ static int intel_dp_compute_bpp(struct intel_dp
> *intel_dp,
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Silence build error with UBSAN
== Series Details == Series: drm/i915: Silence build error with UBSAN URL : https://patchwork.freedesktop.org/series/51025/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4983_full -> Patchwork_10462_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10462_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10462_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10462_full: === IGT changes === Warnings igt@kms_plane@plane-position-covered-pipe-b-planes: shard-snb: PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_10462_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@forcewake: shard-snb: PASS -> DMESG-WARN (fdo#102365) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_pwrite_pread@uncached-pwrite-blt-gtt_mmap-performance: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_render_tiled_blits@basic: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_color@pipe-a-legacy-gamma: shard-skl: NOTRUN -> FAIL (fdo#104782, fdo#108145) igt@kms_cursor_crc@cursor-128x128-dpms: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x64-sliding: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: PASS -> FAIL (fdo#103167, fdo#105682) shard-apl: PASS -> FAIL (fdo#103167, fdo#105682) igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: shard-skl: NOTRUN -> FAIL (fdo#107362, fdo#103191) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145) +2 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) +2 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_suspend@debugfs-reader: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@gem_wait@busy-default: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +2 fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4983 -> Patchwork_10462 CI_DRM_4983: dc8a59f4b22474cdc1ba4745d6ceadddbdff376e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/
Re: [Intel-gfx] [PATCH v5 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes
Hi Jani,
This patch adds the cpu_to_be16 macro and removes the bitfields and
uses macros instead for packing the infoframe as per your feedback
on the previous version of the patch.
Could you please review this patch?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:49PM -0700, Manasi Navare wrote:
> According to Display Stream compression spec 1.2, the picture
> parameter set metadata is sent from source to sink device
> using the DP Secondary data packet. An infoframe is formed
> for the PPS SDP header and PPS SDP payload bytes.
> This patch adds helpers to fill the PPS SDP header
> and PPS SDP payload according to the DSC 1.2 specification.
>
> v6:
> * Use proper sequence points for breaking down the
> assignments (Chris Wilson)
> * Use SPDX identifier
> v5:
> Do not use bitfields for DRM structs (Jani N)
> v4:
> * Use DSC constants for params that dont change across
> configurations
> v3:
> * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
> (Daniel Vetter)
>
> v2:
> * Add EXPORT_SYMBOL for the drm functions (Manasi)
>
> Cc: dri-de...@lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Harry Wentland
> Signed-off-by: Manasi Navare
> Acked-by: Harry Wentland
> ---
> Documentation/gpu/drm-kms-helpers.rst | 12 ++
> drivers/gpu/drm/Makefile | 2 +-
> drivers/gpu/drm/drm_dsc.c | 223 ++
> include/drm/drm_dsc.h | 22 +++
> 4 files changed, 258 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/drm_dsc.c
>
> diff --git a/Documentation/gpu/drm-kms-helpers.rst
> b/Documentation/gpu/drm-kms-helpers.rst
> index f9cfcdcdf024..50bb71712f82 100644
> --- a/Documentation/gpu/drm-kms-helpers.rst
> +++ b/Documentation/gpu/drm-kms-helpers.rst
> @@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
> .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
> :export:
>
> +Display Stream Compression Helper Functions Reference
> +=
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> + :doc: dsc helpers
> +
> +.. kernel-doc:: include/drm/drm_dsc.h
> + :internal:
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> + :export:
> +
> Output Probing Helper Functions Reference
> =
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index bc6a16a3c36e..8e310fadb95d 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
> drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
> drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
>
> -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
> +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
> drm_probe_helper.o \
> drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
> drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
> drm_simple_kms_helper.o drm_modeset_helper.o \
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> new file mode 100644
> index ..21ae8d015afd
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2018 Intel Corp
> + *
> + * Author:
> + * Manasi Navare
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/**
> + * DOC: dsc helpers
> + *
> + * These functions contain some common logic and helpers to deal with VESA
> + * Display Stream Compression standard required for DSC on Display Port/eDP
> or
> + * MIPI display interfaces.
> + */
> +
> +/**
> + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
> + * for DisplayPort as per the DP 1.4 spec.
> + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
> + */
> +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
> +{
> + memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
> +
> + pps_sdp->pps_header.HB1 = DP_SDP_PPS;
> + pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
> +}
> +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
> +
> +/**
> + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> + * using the DSC configuration parameters in the order expected
> + * by the DSC Display Sink device. For the DSC, the sink device
> + * expects the PPS payload in the big endian format for the fields
> + * that span more than 1 byte.
> + *
> + * @pps_sdp:
> + * Secondary data packet for DSC Picture Parameter Set
> + * @dsc_cfg:
> + * DSC Configuration data filled by driver
> + */
> +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> + struct drm_dsc_config *dsc_cfg)
> +{
> + u8 i = 0;
> +
> + memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> +
> + /* PPS 0 */
> + pps_sd
Re: [Intel-gfx] [PATCH v5 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
Hi Ville,
This adds a helper function to get the power well as per
the transcoder as per your suggestion.
Could you please review this one?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:23:04PM -0700, Manasi Navare wrote:
> A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> whereas all other transcoders use the power wells associated with the
> transcoders for VDSC.
> This patch adds a helper to obtain correct power domain depending on
> transcoder being used and enables/disables the power wells during
> VDSC enabling/disabling.
>
> Suggested-by: Ville Syrjala
> Cc: Ville Syrjala
> Cc: Imre Deak
> Cc: Rodrigo Vivi
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_vdsc.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> b/drivers/gpu/drm/i915/intel_vdsc.c
> index 4963e80a87f0..d2b4601459c3 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -581,6 +581,23 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
> return 0;
> }
>
> +static enum intel_display_power_domain
> +intel_dsc_get_power_domains(struct intel_crtc_state *crtc_state)
> +{
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + /*
> + * On ICL+ PW2/ POWER_DOMAIN_VDSC_PIPE_A is required for
> + * VDSC/joining for eDP transcoder.
> + * For any other transcoder, VDSC/joining uses the power well
> associated
> + * with the pipe/transcoder in use.
> + */
> + if (cpu_transcoder == TRANSCODER_EDP)
> + return POWER_DOMAIN_VDSC_PIPE_A;
> + else
> + return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> +}
> +
> static void intel_configure_pps_for_dsc_encoder(struct intel_encoder
> *encoder,
> struct intel_crtc_state
> *crtc_state)
> {
> @@ -1019,6 +1036,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> if (!crtc_state->dsc_params.compression_enable)
> return;
>
> + /* Enable Power wells for VDSC/joining */
> + intel_display_power_get(dev_priv,
> + intel_dsc_get_power_domains(crtc_state));
> +
> intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
>
> intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> @@ -1073,4 +1094,8 @@ void intel_dsc_disable(struct intel_encoder *encoder,
> RIGHT_BRANCH_VDSC_ENABLE);
> I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
>
> + /* Disable Power wells for VDSC/joining */
> + intel_display_power_put(dev_priv,
> + intel_dsc_get_power_domains(old_crtc_state));
> +
> }
> --
> 2.18.0
>
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Re: [Intel-gfx] [PATCH v5 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Hi Imre/Ville,
This patch adds the power domain as per our discussion and feedback
on previous patch set.
Could you please take a look at this?
Manasi
On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> On Icelake, a separate power well PG2 is created for
> VDSC engine used for eDP/MIPI DSI. This patch adds a new
> display power domain for Power well 2.
>
> v2:
> * Fix the power well mismatch CI error (Ville)
> * Rename as VDSC_PIPE_A (Imre)
> * Fix a whitespace (Anusha)
> * Fix Comments (Imre)
>
> Cc: Ville Syrjala
> Cc: Rodrigo Vivi
> Cc: Imre Deak
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_display.h| 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 9eaba1bccae8..4c513169960c 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -256,6 +256,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> POWER_DOMAIN_INIT,
> + POWER_DOMAIN_VDSC_PIPE_A,
>
> POWER_DOMAIN_NUM,
> };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3cf8533e0834..3ed0a3a1015a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -146,6 +146,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "MODESET";
> case POWER_DOMAIN_GT_IRQ:
> return "GT_IRQ";
> + case POWER_DOMAIN_VDSC_PIPE_A:
> + return "VDSC_PIPE_A";
> default:
> MISSING_CASE(domain);
> return "?";
> @@ -1971,9 +1973,9 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
>*/
> #define ICL_PW_2_POWER_DOMAINS ( \
> ICL_PW_3_POWER_DOMAINS |\
> + BIT_ULL(POWER_DOMAIN_VDSC_PIPE_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
> - * - eDP/DSI VDSC
>* - KVMR (HW control)
>*/
> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> --
> 2.18.0
>
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Re: [Intel-gfx] [PATCH 15/16] drm/i915: Power down any power well left on by BIOS
On Mon, 2018-10-15 at 14:06 +0300, Imre Deak wrote:
> On Fri, Oct 12, 2018 at 02:52:17PM -0700, José Roberto de Souza
> wrote:
> > Just not enable power wells is not enough as BIOS/firmware can turn
> > on some power wells during boot, so is needed disable those to save
> > power and to avoid mismatch state errors in
> > intel_power_domains_verify_state().
> > So here disabling every non-real power well first as it could have
> > some dependency in a real power well and then disabling all power
> > wells in reverse(power well 2 depends on power well 1 and so on)
> > other as required by spec.
>
> You can't disable a power well while the function depending on it is
> still on, that would lead to a hang. Also some power wells can only
> be
> enabled/disabled at a specific place in the modeset sequence, so
> disabling them here would lead to timeouts. The correct way to get
> power
> wells disbled is to disable the corresponding functions by doing a
> modeset disabling any active outputs.
Do a modeset disabling would require initialize some display stuff and
that is what this PR is avoiding when display is disabled by parameter.
Also I did not reproduced any hang and CI did not too as somes IGT
tests load i915 with display off.
>
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 59
> > +
> > 1 file changed, 59 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 56c65d921acd..0f5016b74228 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3785,6 +3785,61 @@ static void vlv_cmnlane_wa(struct
> > drm_i915_private *dev_priv)
> >
> > static void intel_power_domains_verify_state(struct
> > drm_i915_private *dev_priv);
> >
> > +static void
> > +intel_power_domains_disable_leftovers(struct drm_i915_private
> > *dev_priv)
> > +{
> > + struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > + struct i915_power_well *power_well;
> > + int i;
> > +
> > + mutex_lock(&power_domains->lock);
> > +
> > + /* Disable everything that is enabled and is not a HW
> > power_well */
> > + for_each_power_well(dev_priv, power_well) {
> > + WARN_ON(power_well->count);
> > +
> > + /*
> > +* Power wells not belonging to any domain (like the
> > MISC_IO
> > +* and PW1 power wells) are under FW control, so ignore
> > them,
> > +* since their state can change asynchronously.
> > +*/
> > + if (!power_well->desc->domains || power_well->desc-
> > >always_on)
> > + continue;
> > +
> > + if (power_well->desc->id != DISP_PW_ID_NONE)
> > + continue;
> > +
> > + if (!power_well->hw_enabled)
> > + continue;
> > +
> > + intel_power_well_disable(dev_priv, power_well);
> > + }
> > +
> > + /* Disabled HW power wells in reverse order, so power well 2 is
> > +* disabled before power well 1 and so on as required by spec.
> > +*/
> > + for (i = power_domains->power_well_count - 1; i >= 0; i--) {
> > + power_well = &power_domains->power_wells[i];
> > +
> > + WARN_ON(power_well->count);
> > +
> > + if (!power_well->desc->domains || power_well->desc-
> > >always_on)
> > + continue;
> > +
> > + if (power_well->desc->id == DISP_PW_ID_NONE)
> > + continue;
> > +
> > + if (!power_well->hw_enabled)
> > + continue;
> > +
> > + intel_power_well_disable(dev_priv, power_well);
> > + }
> > +
> > + mutex_unlock(&power_domains->lock);
> > +
> > + intel_power_domains_verify_state(dev_priv);
> > +}
> > +
> > /**
> > * intel_power_domains_init_hw - initialize hardware power domain
> > state
> > * @dev_priv: i915 device instance
> > @@ -3838,6 +3893,10 @@ void intel_power_domains_init_hw(struct
> > drm_i915_private *dev_priv, bool resume)
> > intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> > intel_power_domains_sync_hw(dev_priv);
> >
> > + /* Disable everything left enabled by BIOS/firmware */
> > + if (!INTEL_INFO(dev_priv)->num_pipes)
> > + intel_power_domains_disable_leftovers(dev_priv);
> > +
> > power_domains->initializing = false;
> > }
> >
> > --
> > 2.19.1
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
== Series Details == Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7) URL : https://patchwork.freedesktop.org/series/40747/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4982_full -> Patchwork_10461_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10461_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10461_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10461_full: === IGT changes === Possible regressions igt@kms_atomic_transition@1x-modeset-transitions: shard-skl: NOTRUN -> FAIL Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10461_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@sysfs-reader: shard-snb: PASS -> DMESG-WARN (fdo#102365) igt@gem_exec_schedule@pi-ringfull-render: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +4 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-skl: NOTRUN -> FAIL (fdo#105458) igt@kms_ccs@pipe-b-crc-sprite-planes-basic: shard-skl: NOTRUN -> FAIL (fdo#107725, fdo#108145) igt@kms_color@pipe-a-legacy-gamma: shard-skl: NOTRUN -> FAIL (fdo#104782, fdo#108145) igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: NOTRUN -> FAIL (fdo#103191, fdo#103232) igt@kms_cursor_crc@cursor-256x85-offscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_draw_crc@fill-fb: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: PASS -> FAIL (fdo#103167, fdo#105682) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: PASS -> FAIL (fdo#103167) +4 igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: shard-skl: NOTRUN -> FAIL (fdo#103191, fdo#107362) igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) +1 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145) +5 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-apl: PASS -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_rotation_crc@exhaust-fences: shard-skl: NOTRUN -> DMESG-WARN (fdo#105748) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) Possible fixes igt@gem_wait@busy-default: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: FAIL (fdo#103167, fdo#105682) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freede
Re: [Intel-gfx] [PATCH 02/16] drm/i915: Move out non-display related calls from display/modeset init/cleanup
On Mon, 2018-10-15 at 12:14 +0100, Chris Wilson wrote: > Quoting José Roberto de Souza (2018-10-12 22:52:04) > > i915_load_modeset_init() and intel_modeset_cleanup() was > > initializing > > and cleaning up things that is not related to display or modeset. > > This changes will make easy initialize driver without display > > block. > > Still broken, as the display must reserve it's portion of the GTT > before > i915_gem_init. Hi Chris I did not found any calls to this functions: i915_gem_info_add_obj() i915_gem_object_create() i915_gem_gtt_reserve() i915_gem_gtt_insert() i915_vma_insert() before the i915_gem_init() call, I even added dump_stack() in those functions but still did got any call before i915_gem_init(), could explain more? All of this running with drm-tip with display enabled. Thanks > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
On 15/10/18 15:47, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51033/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10464 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10464 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10464, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/51033/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10464:
=== IGT changes ===
Possible regressions
igt@drv_selftest@live_execlists:
fi-skl-6700hq: PASS -> INCOMPLETE
Log seem to be cut for this one. Since it is stopping inside
live_preempt_smoke it is probably a known issue that Chris mentioned.
Can't reproduce on my skylake even with the test in a loop.
igt@drv_selftest@live_guc:
fi-kbl-7567u: PASS -> DMESG-WARN
fi-skl-6600u: PASS -> DMESG-WARN
fi-skl-gvtdvm: PASS -> DMESG-WARN
fi-skl-iommu: PASS -> DMESG-WARN
fi-skl-6260u: PASS -> DMESG-WARN
fi-bxt-dsi: PASS -> DMESG-WARN
fi-skl-6700k2: PASS -> DMESG-WARN
fi-whl-u: PASS -> DMESG-WARN
fi-skl-6770hq: PASS -> DMESG-WARN
fi-kbl-7560u: PASS -> DMESG-WARN
fi-kbl-8809g: PASS -> DMESG-WARN
fi-kbl-r: PASS -> DMESG-WARN
fi-kbl-x1275: PASS -> DMESG-WARN
fi-bxt-j4205: PASS -> DMESG-WARN
fi-cfl-s3: PASS -> DMESG-WARN
fi-cfl-8109u: PASS -> DMESG-WARN
fi-kbl-7500u: PASS -> DMESG-WARN
fi-cfl-8700k: PASS -> DMESG-WARN
These are all:
[drm:intel_guc_send_mmio [i915]] *ERROR* MMIO: GuC action 0x10 failed
with error -5 0xf000f000
Which is not a real failure since the test is triggering it on purpose
igt@drv_selftest@live_hangcheck:
fi-skl-gvtdvm: PASS -> DMESG-FAIL
<7> [464.966238] [drm:guc_fw_xfer [i915]] GuC status 0x20
<3> [464.966361] [drm:guc_fw_xfer [i915]] *ERROR* GuC firmware xfer
error -110
This looks like GuC is stuck very early in the boot flow (even before
the RSA check). On SKL there are known issues that could cause this and
we should reset GuC and retry, but we aren't. Looks like we indirectly
stopped applying WaEnableuKernelHeaderValidFix and
WaEnableGuCBootHashCheckNotSet by not returning -EAGAIN from
intel_guc_fw_upload in any case. Michal?
Thanks,
Daniele
== Known issues ==
Here are the changes found in Patchwork_10464 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
{fi-apl-guc}: NOTRUN -> DMESG-WARN (fdo#107258)
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> DMESG-FAIL (fdo#103713)
igt@kms_setmode@basic-clone-single-crtc:
fi-snb-2520m: PASS -> DMESG-WARN (fdo#103713)
igt@pm_backlight@basic-brightness:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
Possible fixes
igt@drv_selftest@live_gem:
{fi-apl-guc}: INCOMPLETE (fdo#106693) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (53 -> 47) ==
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4984 -> Patchwork_10464
CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10464: c88fb110ee8261c636d63f4f6d9fa9440891b3a6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c88fb110ee82 HAX enable GuC for CI
4454d4d05ce3 drm/i915/guc: fix GuC suspend/resume
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10464/issues.html
__
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
== Series Details == Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3) URL : https://patchwork.freedesktop.org/series/50810/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4982_full -> Patchwork_10460_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10460_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> INCOMPLETE (fdo#105411, fdo#106886) shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133, fdo#106886) igt@gem_exec_schedule@pi-ringfull-render: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-skl: NOTRUN -> FAIL (fdo#105458) igt@kms_color@pipe-a-legacy-gamma: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#104782) igt@kms_cursor_crc@cursor-128x128-dpms: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: NOTRUN -> FAIL (fdo#103232, fdo#103191) igt@kms_cursor_crc@cursor-64x64-sliding: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145) +4 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-apl: PASS -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-glk: PASS -> FAIL (fdo#103166) shard-apl: PASS -> FAIL (fdo#103166) Possible fixes igt@gem_wait@busy-default: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: FAIL (fdo#103167, fdo#105682) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@pm_rpm@modeset-pc8-residency-stress: shard-skl: INCOMPLETE (fdo#107807) -> SKIP fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105458 https://bugs.freedesktop.org/show_bug.cgi?id=105458 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51033/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10464 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10464 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10464, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/51033/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10464:
=== IGT changes ===
Possible regressions
igt@drv_selftest@live_execlists:
fi-skl-6700hq: PASS -> INCOMPLETE
igt@drv_selftest@live_guc:
fi-kbl-7567u: PASS -> DMESG-WARN
fi-skl-6600u: PASS -> DMESG-WARN
fi-skl-gvtdvm: PASS -> DMESG-WARN
fi-skl-iommu: PASS -> DMESG-WARN
fi-skl-6260u: PASS -> DMESG-WARN
fi-bxt-dsi: PASS -> DMESG-WARN
fi-skl-6700k2: PASS -> DMESG-WARN
fi-whl-u: PASS -> DMESG-WARN
fi-skl-6770hq: PASS -> DMESG-WARN
fi-kbl-7560u: PASS -> DMESG-WARN
fi-kbl-8809g: PASS -> DMESG-WARN
fi-kbl-r: PASS -> DMESG-WARN
fi-kbl-x1275: PASS -> DMESG-WARN
fi-bxt-j4205: PASS -> DMESG-WARN
fi-cfl-s3: PASS -> DMESG-WARN
fi-cfl-8109u: PASS -> DMESG-WARN
fi-kbl-7500u: PASS -> DMESG-WARN
fi-cfl-8700k: PASS -> DMESG-WARN
igt@drv_selftest@live_hangcheck:
fi-skl-gvtdvm: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10464 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
{fi-apl-guc}: NOTRUN -> DMESG-WARN (fdo#107258)
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> DMESG-FAIL (fdo#103713)
igt@kms_setmode@basic-clone-single-crtc:
fi-snb-2520m: PASS -> DMESG-WARN (fdo#103713)
igt@pm_backlight@basic-brightness:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
Possible fixes
igt@drv_selftest@live_gem:
{fi-apl-guc}: INCOMPLETE (fdo#106693) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (53 -> 47) ==
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4984 -> Patchwork_10464
CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10464: c88fb110ee8261c636d63f4f6d9fa9440891b3a6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c88fb110ee82 HAX enable GuC for CI
4454d4d05ce3 drm/i915/guc: fix GuC suspend/resume
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10464/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: fix GuC suspend/resume
== Series Details == Series: series starting with [1/2] drm/i915/guc: fix GuC suspend/resume URL : https://patchwork.freedesktop.org/series/51033/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4454d4d05ce3 drm/i915/guc: fix GuC suspend/resume c88fb110ee82 HAX enable GuC for CI -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Forward Error Correction (rev2)
== Series Details == Series: Forward Error Correction (rev2) URL : https://patchwork.freedesktop.org/series/47848/ State : failure == Summary == Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c). error: could not build fake ancestor Patch failed at 0001 i915/dp/fec: Cache the FEC_CAPABLE DPCD register Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc: fix GuC suspend/resume
The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
FW and then return, so waiting on the H2H is not enough to guarantee
GuC is done.
When all the processing is done, GuC writes 0 to scratch register 14,
so we can poll on that. Note that GuC does not ensure that the value
in the register is different from 0 while the action is in progress
so we need to take care of that ourselves as well.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc.c | 28 +--
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 230aea69385d..f238cd7a9dcf 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -521,6 +521,30 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32
rsa_offset)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+/*
+ * The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC FW
and
+ * then return, so waiting on the H2H is not enough to guarantee GuC is done.
+ * When all the processing is done, GuC writes 0 to scratch register 14, so we
+ * can poll on that. Note that GuC does not ensure that the value in the
+ * register is different from 0 while the action is in progress so we need to
+ * take care of that ourselves as well.
+ */
+static int guc_sleep_state_action(struct intel_guc *guc,
+ const u32 *action, u32 len)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+
+ I915_WRITE(SOFT_SCRATCH(14), ~0x0);
+
+ ret = intel_guc_send(guc, action, len);
+ if (ret)
+ return ret;
+
+ return intel_wait_for_register(dev_priv, SOFT_SCRATCH(14), ~0x0,
+ INTEL_GUC_SLEEP_STATE_SUCCESS, 10);
+}
+
/**
* intel_guc_suspend() - notify GuC entering suspend state
* @guc: the guc
@@ -533,7 +557,7 @@ int intel_guc_suspend(struct intel_guc *guc)
intel_guc_ggtt_offset(guc, guc->shared_data)
};
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
+ return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
}
/**
@@ -571,7 +595,7 @@ int intel_guc_resume(struct intel_guc *guc)
intel_guc_ggtt_offset(guc, guc->shared_data)
};
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
+ return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..b0eb5aabe0a7 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -687,6 +687,12 @@ enum intel_guc_report_status {
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
};
+enum intel_guc_sleep_state_status {
+ INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
+ INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
+ INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+};
+
#define GUC_LOG_CONTROL_LOGGING_ENABLED(1 << 0)
#define GUC_LOG_CONTROL_VERBOSITY_SHIFT4
#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
--
2.19.0
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[Intel-gfx] [PATCH 2/2] HAX enable GuC for CI
From: Michal Wajdeczko Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 7e56c516c815..c681537bcb92 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -45,7 +45,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.19.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 1/6] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
On Mon, Oct 15, 2018 at 02:50:32PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> Suggested-by: Jani Nikula
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dcc5a207fcbd..8a0e0a0b26f6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4163,8 +4163,10 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
> *intel_dp)
> /*
>*Clear the cached register set to avoid using stale values
>* for the sinks that do not support DSC.
> + * Similarly, clear the cached FEC register.
>*/
> memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
> + memset(intel_dp->fec_dpcd, 0, sizeof(intel_dp->fec_dpcd));
Memset is an expensive opertaion for just a single value,
just set that to 0
>
> /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
> @@ -4179,6 +4181,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
> *intel_dp)
> (int)sizeof(intel_dp->dsc_dpcd),
> intel_dp->dsc_dpcd);
> }
> + /* FEC is supported only on DP 1.4 */
> + if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
> + intel_dp->fec_dpcd) < 0)
> + DRM_ERROR("Failed to read FEC DPCD register\n");
> + }
> }
>
> static bool
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 7b4af8cba279..b87ea052c9ca 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1086,6 +1086,7 @@ struct intel_dp {
> uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> + u8 fec_dpcd[1];
Why create an array for just 1 value, I think just a u8 fec_capable field
will suffice
Manasi
> /* source rates */
> int num_source_rates;
> const int *source_rates;
> --
> 2.17.1
>
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[Intel-gfx] [v2 5/6] i915/dp/fec: Configure the Forward Error Correction bits.
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 27 +++
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
4 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcde78bc0027..c8d7fdcd7823 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9093,6 +9093,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9111,6 +9112,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f531900165bf..67c013ea4d39 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2911,6 +2911,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
DP_DECOMPRESSION_EN);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
intel_dp_start_link_train(intel_dp);
+ intel_dp_enable_fec_state(intel_dp, crtc_state);
+
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b4e8af3142a2..b9f85502d9ff 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3017,6 +3017,33 @@ void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
}
+void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ enum port port = intel_dig_port->base.port;
+ u32 val;
+
+ /* FEC support exists for DP 1.4 only */
+ if (intel_dp_is_edp(intel_dp))
+ return;
+
+ /* If Display Compression is not enabled, FEC need not be configured */
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fbc9fa06e8be..e51d612a9f42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1532,7 +1532,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder);
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
-
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@@ -1712,6 +1711,8 @@ void intel_dp_sink_set_decompressio
[Intel-gfx] [v2 6/6] drm/i915/fec: Disable FEC state.
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 18 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 67c013ea4d39..fefa92070b2d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3245,6 +3245,8 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
/* Disable the decompression in DP Sink */
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
~DP_DECOMPRESSION_EN);
+ /* Disable FEC in DP Sink */
+ intel_dp_disable_fec_state(intel_dp, old_crtc_state);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b9f85502d9ff..1db1a738c85f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3044,6 +3044,24 @@ void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ enum port port = intel_dig_port->base.port;
+ u32 val;
+
+ if (crtc_state->dsc_params.compression_enable)
+ DRM_DEBUG_KMS("Compression still enabled\n");
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e51d612a9f42..0c2429f7cc35 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1713,6 +1713,8 @@ void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
int state);
void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.17.1
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[Intel-gfx] [v2 0/6] Forward Error Correction
With Display Compression, the bit error in the pixel stream can turn into a significant corruption on the screen. The DP1.4 adds FEC - Forward Error Correction scheme which uses Reed-Solomon parity/correction check generated by the source and used by the sink to detect and correct small numbers of bit errors in the compressed stream. v2: Avoid doing aux channel read eberytime we check for FEC support. Instead cache the value of the DPCD registers, similar to the DSC implementaion (Jani) This is rebased on top of Manasi's End-to-end DSC Implementation: https://patchwork.freedesktop.org/series/47514/ Tested on Odelia Board after applying the FEC workaround. Anusha Srivatsa (6): i915/dp/fec: Cache the FEC_CAPABLE DPCD register i915/dp/fec: Check for FEC Support drm/dp/fec: DRM helper for Forward Error Correction drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/intel_dp.c | 82 +++- drivers/gpu/drm/i915/intel_drv.h | 9 +++- include/drm/drm_dp_helper.h | 7 +++ 5 files changed, 102 insertions(+), 3 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 3/6] i915/dp/fec: Check for FEC Support
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Check if the sink supports FEC using the helper.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check even if FEC is not supported. (manasi)
v3: Do not perform any dpcd writes in the atomic
check phase. (DK, Manasi)
v4: Use debug level logging for scenario where sink does
not support a feature. (DK)
v5: Correct commit message. rebase.
Cc: Gaurav K Singh
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Cc: Dhinakaran Pandiyan
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a0e0a0b26f6..318494afd14a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -650,7 +650,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_dpcd)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -660,7 +660,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
mode->hdisplay);
- }
+ } else
+ DRM_DEBUG_KMS("Sink device does not Support FEC\n");
}
if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
@@ -2033,6 +2034,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp))
return false;
+ /* DSC not supported if external DP sink does not support FEC */
+ if (!intel_dp_is_edp(intel_dp) &&
+ !drm_dp_sink_supports_fec(intel_dp->fec_dpcd)) {
+ DRM_DEBUG_KMS("Sink does not support Forward Error Correction,
disabling Display Compression\n");
+ return false;
+ }
+
/* DSC not supported for DSC sink BPC < 8 */
if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
--
2.17.1
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[Intel-gfx] [v2 2/6] drm/dp/fec: DRM helper for Forward Error Correction
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style changes (Gaurav)
- Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani)
v4:
- Avoid aux reads everytime, instead read cached
values of dpcd register (jani)
- Move helper to drm_dp_helper.h like other dsc
helpers.(Anusha)
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 33cb78925094..82bbccc69acf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1099,6 +1099,13 @@ drm_dp_dsc_sink_max_slice_width(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
DP_DSC_SLICE_WIDTH_MULTIPLIER;
}
+/* Forward Error Correction Support on DP 1.4*/
+static inline bool
+drm_dp_sink_supports_fec(const u8 fec_dpcd[])
+{
+ return fec_dpcd[0] & DP_FEC_CAPABLE;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.17.1
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[Intel-gfx] [v2 4/6] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2db6284d3a96..f531900165bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2909,6 +2909,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
DP_DECOMPRESSION_EN);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 318494afd14a..b4e8af3142a2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3000,6 +3000,23 @@ void intel_dp_sink_set_decompression_state(struct
intel_dp *intel_dp,
state == DP_DECOMPRESSION_EN ? "enable" :
"disable");
}
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state,
+int state)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (intel_dp_is_edp(intel_dp))
+ return;
+
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b87ea052c9ca..fbc9fa06e8be 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1709,6 +1709,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int
mode);
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
int state);
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state,
+int state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.17.1
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[Intel-gfx] [v2 1/6] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 8
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dcc5a207fcbd..8a0e0a0b26f6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4163,8 +4163,10 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp)
/*
*Clear the cached register set to avoid using stale values
* for the sinks that do not support DSC.
+* Similarly, clear the cached FEC register.
*/
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ memset(intel_dp->fec_dpcd, 0, sizeof(intel_dp->fec_dpcd));
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
@@ -4179,6 +4181,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp)
(int)sizeof(intel_dp->dsc_dpcd),
intel_dp->dsc_dpcd);
}
+ /* FEC is supported only on DP 1.4 */
+ if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+ intel_dp->fec_dpcd) < 0)
+ DRM_ERROR("Failed to read FEC DPCD register\n");
+ }
}
static bool
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b4af8cba279..b87ea052c9ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1086,6 +1086,7 @@ struct intel_dp {
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+ u8 fec_dpcd[1];
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.17.1
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: create function to identify combophy port
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
>
> Signed-off-by: Mahesh Kumar
> Cc: Madhav Chauhan
> Cc: Manasi Navare
Looks good to me.
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 15 ---
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port,
> INTEL_OUTPUT_HDMI, &n_entries);
> else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder
> *encoder,
> uint32_t pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
> *encoder)
> int n_entries;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> &n_entries);
> else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> u32 level,
> enum intel_output_type type)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
>
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> mutex_lock(&dev_priv->dpll_lock);
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_pll_sel(encoder, pll));
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
> *encoder)
> enum port port = encoder->port;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
> *dev_priv, enum port port)
> return port - PORT_C;
> }
>
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port
> port)
> +{
> + if (port == PORT_NONE)
> + return false;
> +
> + if (IS_ICELAKE(dev_priv))
> + return (port <= PORT_B);
> +
> + return false;
> +}
> +
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> {
> switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d
Re: [Intel-gfx] [PATCH i-g-t] igt/pm_rpm: Ignore modesets for basic tests with no KMS
On Fri, 2018-10-05 at 09:05 +0100, Chris Wilson wrote:
> If KMS is not available, we cannot simply turn on an output and
> expect
> that to wake the device up. As such we have to ignore that part of
> the
> basic subtest and simply proclaim victory if the device is able to
> sleep!
We could replace the 'turn on a screen' to submit some job batch to one
of the engines, this way we could test the waking path too when KMS is
disabled but for now it is better than skip the tests at all as you
said.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Chris Wilson
> ---
> tests/pm_rpm.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index 7488efd7..731c9cf6 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -777,7 +777,8 @@ static void basic_subtest(void)
> {
> disable_all_screens_and_wait(&ms_data);
>
> - enable_one_screen_and_wait(&ms_data);
> + if (ms_data.res)
> + enable_one_screen_and_wait(&ms_data);
> }
>
> static void pc8_residency_subtest(void)
> @@ -1405,8 +1406,10 @@ static void pci_d3_state_subtest(void)
> disable_all_screens_and_wait(&ms_data);
> igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
>
> - enable_one_screen_and_wait(&ms_data);
> - igt_assert(!device_in_pci_d3());
> + if (ms_data.res) {
> + enable_one_screen_and_wait(&ms_data);
> + igt_assert(!device_in_pci_d3());
> + }
> }
>
> static void __attribute__((noreturn)) stay_subtest(void)
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: sleep on enable
On 15/10/18 12:23, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-10-15 19:33:26) On 14/10/18 10:02, Chris Wilson wrote: Seems like there's a missing ack before the guc is ready for commands. I'm assuming you're running without HuC since the HuC auth H2G comes before this one. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4981/fi-apl-guc/boot0.log i915.enable_guc=3 <7>[6.877175] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch i915/bxt_guc_ver9_29.bin <7>[6.877268] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch PENDING <7>[6.879780] [drm:intel_uc_fw_fetch [i915]] GuC fw size 146432 ptr 3fdb20d0 <7>[6.879869] [drm:intel_uc_fw_fetch [i915]] GuC fw version 9.29 (wanted 9.29) <7>[6.880425] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch SUCCESS <7>[6.880723] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch i915/bxt_huc_ver01_07_1398.bin <7>[6.880807] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch PENDING <7>[6.882529] [drm:intel_uc_fw_fetch [i915]] HuC fw size 154432 ptr 0aad61c4 <7>[6.882621] [drm:intel_uc_fw_fetch [i915]] HuC fw version 1.7 (wanted 1.7) <7>[6.883098] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch SUCCESS What we're polling to indicate load completion (GS_UKERNEL_READY) is definitely what the firmware uses to signal readiness. The other check we do (GS_MIA_CORE_STATE) should only apply for rc6 scenarios. From what I can see from the firmware code, all the initialization steps are done before GS_UKERNEL_READY is written to the status register so there shouldn't be any missing acks in principle. Is the GuC returning anything in the scratch 0 register? It should be printed out by the H2G error message. The value of the status register (0xc000) could also provide interesting debug info. When do you want to know? As you are probably aware, our first indication of failure is from wait_for_guc_preempt_report() and the wait there on report->report_return_status timing out. Michel asked what was the value when it timed out, but alas apl-guc was not available for comment. -Chris I think found the root cause of the issue (with the help of one of the GuC devs). The guc suspend/resume protocol requires us to do an extra couple of steps to make sure GuC is done managing its state, waiting on the H2G return is not enough; since we're not correctly doing those GuC is still in the middle of the resume process when the preemption request arrives, thus causing the failure. Patch to fix this incoming. Note that since we ensure the HW is idle before suspend we could theoretically skip the guc_resume step as there is nothing to restore, but this is untested from the GuC side so not recommended yet. We still need to do guc_suspend since that step ensures that all guc timers are correctly disabled. I think you mentioned you were also seeing issues even outside of the suspend/resume path, so we probably have a different issue as well :( Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm-intel-fixes CI issues
On Mon, 2018-10-15 at 14:20 -0700, Rodrigo Vivi wrote:
> On Mon, Oct 15, 2018 at 03:59:36PM -0400, Lyude Paul wrote:
> > Poke: still wondering what we should do about the patch in these fixes
> > that
> > came up a little later which got Cc'd to stable, despite it apparently not
> > being a patch we want in stable (mentioned this over IRC):
> >
> > https://patchwork.freedesktop.org/patch/255428/ and
> > https://patchwork.freedesktop.org/series/50770/
>
> Thanks for bringing this up.
>
> So, These 2 patches are merged on the tree, but we don't want
> them propagated to stable tree anymore? Do we have a fix for those?
> Or are we reverting them?
I am in the process of making a fix and am just about finished; just had to
clear some corner cases up with danvet. I think we should be fine if we do
either one of two things:
* Just cc the third patch (once I've got it on the ML today) to stable, since
I did want the problem these were intended to fix to also be fixed
downstream, and while messy it should take care of fixing the problems that
were introduced.
* Don't cc the two patches to stable, and I can just handle backporting the
third and final fix to stable
This is a new situation for me, so I'm honestly not sure which of those two
would be the best approach.
[more below]
>
> We probably want to raise this up to Greg so he doesn't pick
> them when running his stable scripts.
>
> But also I was wondering another aspect of these patches I had here
> on this dropped list.
>
> In the end most of patches that was here will be picked by Greg's
> stable scripts anyways.
>
> Also other patches with cc:stable that were on that round
> but got removed:
>
> commit 1e712535c51a ("drm/i915/dp: Link train Fallback on eDP only if
> fallback link BW can fit panel's native mode")
According to Manasi earlier in the thread:
"I am okay with that w.r.t my patch ("drm/i915/dp: Link train Fallback on eDP
only if fallback link BW can fit panel's native mode")"
So I think waiting until v4.19 on that one should be fine.
> commit 62358aa4ee86 ("drm/i915: Use the correct crtc when sanitizing plane
> mapping")
> commit 68bc30deac62 ("drm/i915: Restore vblank interrupts earlier")
>
Can't speak for these two though
> Should I add back at least these patches this week?
> Or we should really wait for 4.19 to be released?
>
> Thanks,
> Rodrigo.
>
> >
> > On Thu, 2018-10-11 at 09:17 +1000, David Airlie wrote:
> > > On Thu, Oct 11, 2018 at 8:53 AM Rodrigo Vivi
> > > wrote:
> > > >
> > > > Hi all,
> > > >
> > > > I need your help to decide what to do with this round of fixes.
> > > >
> > > > I have collected these patches this week:
> > > >
> > > > commit b43e8916172a ("drm/i915/dp: Link train Fallback on eDP only if
> > > > fallback link BW can fit panel's native mode")
> > > > commit 5abb01e541ed ("drm/i915: Fix intel_dp_mst_best_encoder()")
> > > > commit 02713246296d ("drm/i915: Skip vcpi allocation for MSTB ports
> > > > that
> > > > are gone")
> > > > commit cc6e027f5f50 ("drm/i915: Don't unset intel_connector-
> > > > >mst_port")
> > > > commit f5aec50ba21e ("drm/i915: Use the correct crtc when sanitizing
> > > > plane
> > > > mapping")
> > > > commit 6547684bf50a ("drm/i915: Restore vblank interrupts earlier")
> > > >
> > > > CI_DIF_309 represents Greg's v4.19-rc7 and it is clean.
> > > >
> > > > However 2 following CI runs are kind of strange.
> > > >
> > > > There's few underruns here and there, but those looks flip-flops.
> > > >
> > > > My biggest concern is specially around:
> > > >
> > > > igt@kms_plane@pixel-format-pipe-a-planes:
> > > > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
> > > >
> > > >
> >
> >
https://intel-gfx-ci.01.org/tree/drm-intel-fixes/CI_DIF_311/shard-glk8/igt@kms_pl...@pixel-format-pipe-c-planes.html
> > > >
> > > > Thoughts?
> > > >
> > > > I'm holding the pull request for now and will try to do some local
> > > > tests
> > > > here
> > > > to see if I can identify a culprit.
> > >
> > > At this late in the game for rc8, unless these fix a major regression
> > > in the current tree, I'd say drop them until -next.
> > >
> > > Dave.
> >
> > --
> > Cheers,
> > Lyude Paul
> >
--
Cheers,
Lyude Paul
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Re: [Intel-gfx] drm-intel-fixes CI issues
On Mon, Oct 15, 2018 at 03:59:36PM -0400, Lyude Paul wrote:
> Poke: still wondering what we should do about the patch in these fixes that
> came up a little later which got Cc'd to stable, despite it apparently not
> being a patch we want in stable (mentioned this over IRC):
>
> https://patchwork.freedesktop.org/patch/255428/ and
> https://patchwork.freedesktop.org/series/50770/
Thanks for bringing this up.
So, These 2 patches are merged on the tree, but we don't want
them propagated to stable tree anymore? Do we have a fix for those?
Or are we reverting them?
We probably want to raise this up to Greg so he doesn't pick
them when running his stable scripts.
But also I was wondering another aspect of these patches I had here
on this dropped list.
In the end most of patches that was here will be picked by Greg's
stable scripts anyways.
Also other patches with cc:stable that were on that round
but got removed:
commit 1e712535c51a ("drm/i915/dp: Link train Fallback on eDP only if fallback
link BW can fit panel's native mode")
commit 62358aa4ee86 ("drm/i915: Use the correct crtc when sanitizing plane
mapping")
commit 68bc30deac62 ("drm/i915: Restore vblank interrupts earlier")
Should I add back at least these patches this week?
Or we should really wait for 4.19 to be released?
Thanks,
Rodrigo.
>
> On Thu, 2018-10-11 at 09:17 +1000, David Airlie wrote:
> > On Thu, Oct 11, 2018 at 8:53 AM Rodrigo Vivi wrote:
> > >
> > > Hi all,
> > >
> > > I need your help to decide what to do with this round of fixes.
> > >
> > > I have collected these patches this week:
> > >
> > > commit b43e8916172a ("drm/i915/dp: Link train Fallback on eDP only if
> > > fallback link BW can fit panel's native mode")
> > > commit 5abb01e541ed ("drm/i915: Fix intel_dp_mst_best_encoder()")
> > > commit 02713246296d ("drm/i915: Skip vcpi allocation for MSTB ports that
> > > are gone")
> > > commit cc6e027f5f50 ("drm/i915: Don't unset intel_connector->mst_port")
> > > commit f5aec50ba21e ("drm/i915: Use the correct crtc when sanitizing plane
> > > mapping")
> > > commit 6547684bf50a ("drm/i915: Restore vblank interrupts earlier")
> > >
> > > CI_DIF_309 represents Greg's v4.19-rc7 and it is clean.
> > >
> > > However 2 following CI runs are kind of strange.
> > >
> > > There's few underruns here and there, but those looks flip-flops.
> > >
> > > My biggest concern is specially around:
> > >
> > > igt@kms_plane@pixel-format-pipe-a-planes:
> > > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
> > >
> > >
> https://intel-gfx-ci.01.org/tree/drm-intel-fixes/CI_DIF_311/shard-glk8/igt@kms_pl...@pixel-format-pipe-c-planes.html
> > >
> > > Thoughts?
> > >
> > > I'm holding the pull request for now and will try to do some local tests
> > > here
> > > to see if I can identify a culprit.
> >
> > At this late in the game for rc8, unless these fix a major regression
> > in the current tree, I'd say drop them until -next.
> >
> > Dave.
> --
> Cheers,
> Lyude Paul
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Silence build error with UBSAN
== Series Details == Series: drm/i915: Silence build error with UBSAN URL : https://patchwork.freedesktop.org/series/51025/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4983 -> Patchwork_10462 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51025/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10462 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@prime_vgem@basic-fence-flip: fi-byt-n2820: PASS -> FAIL (fdo#104008) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (52 -> 47) == Additional (1): fi-kbl-r Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4983 -> Patchwork_10462 CI_DRM_4983: dc8a59f4b22474cdc1ba4745d6ceadddbdff376e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10462: 95b8c305ff231405ace85692d0caf12f15c5206b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 95b8c305ff23 drm/i915: Silence build error with UBSAN == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10462/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Silence build error with UBSAN
When I enable UBSAN and compile this driver with clang I get the following build error: drivers/gpu/drm/i915/intel_engine_cs.o: In function `intel_engine_init_execlist': drivers/gpu/drm/i915/intel_engine_cs.c:411: undefined reference to `__compiletime_assert_411' from what I can figure out, the compiler can't optimize execlists_num_ports() sufficiently enough at compile time to figure out that the 'execlists->port_mask = 1' assignment one line above the BUILD_BUG_ON_NOT_POWER_OF_2 check will make execlists_num_ports() return 2. Most likely that's because UBSAN is going to check the load inside execlists_num_ports() and that check isn't omitted so the optimizer can't optimize away the whole function. So let's just change this check to cause a build error when the maximum number of ports isn't a power of two. It looks like this is similar to what's being checked here so this might work well enough. Cc: Masahiro Yamada Cc: Michal Marek Cc: Andrey Ryabinin Signed-off-by: Stephen Boyd --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 217ed3ee1cab..bdf75628ed83 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -463,7 +463,7 @@ static void intel_engine_init_execlist(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; execlists->port_mask = 1; - BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists)); + BUILD_BUG_ON_NOT_POWER_OF_2(EXECLIST_MAX_PORTS); GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); execlists->queue_priority = INT_MIN; -- Sent by a computer through tubes ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm-intel-fixes CI issues
Poke: still wondering what we should do about the patch in these fixes that
came up a little later which got Cc'd to stable, despite it apparently not
being a patch we want in stable (mentioned this over IRC):
https://patchwork.freedesktop.org/patch/255428/ and
https://patchwork.freedesktop.org/series/50770/
On Thu, 2018-10-11 at 09:17 +1000, David Airlie wrote:
> On Thu, Oct 11, 2018 at 8:53 AM Rodrigo Vivi wrote:
> >
> > Hi all,
> >
> > I need your help to decide what to do with this round of fixes.
> >
> > I have collected these patches this week:
> >
> > commit b43e8916172a ("drm/i915/dp: Link train Fallback on eDP only if
> > fallback link BW can fit panel's native mode")
> > commit 5abb01e541ed ("drm/i915: Fix intel_dp_mst_best_encoder()")
> > commit 02713246296d ("drm/i915: Skip vcpi allocation for MSTB ports that
> > are gone")
> > commit cc6e027f5f50 ("drm/i915: Don't unset intel_connector->mst_port")
> > commit f5aec50ba21e ("drm/i915: Use the correct crtc when sanitizing plane
> > mapping")
> > commit 6547684bf50a ("drm/i915: Restore vblank interrupts earlier")
> >
> > CI_DIF_309 represents Greg's v4.19-rc7 and it is clean.
> >
> > However 2 following CI runs are kind of strange.
> >
> > There's few underruns here and there, but those looks flip-flops.
> >
> > My biggest concern is specially around:
> >
> > igt@kms_plane@pixel-format-pipe-a-planes:
> > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
> >
> >
https://intel-gfx-ci.01.org/tree/drm-intel-fixes/CI_DIF_311/shard-glk8/igt@kms_pl...@pixel-format-pipe-c-planes.html
> >
> > Thoughts?
> >
> > I'm holding the pull request for now and will try to do some local tests
> > here
> > to see if I can identify a culprit.
>
> At this late in the game for rc8, unless these fix a major regression
> in the current tree, I'd say drop them until -next.
>
> Dave.
--
Cheers,
Lyude Paul
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: sleep on enable
Quoting Daniele Ceraolo Spurio (2018-10-15 19:33:26) > > > On 14/10/18 10:02, Chris Wilson wrote: > > Seems like there's a missing ack before the guc is ready for commands. > > > > I'm assuming you're running without HuC since the HuC auth H2G comes > before this one. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4981/fi-apl-guc/boot0.log i915.enable_guc=3 <7>[6.877175] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch i915/bxt_guc_ver9_29.bin <7>[6.877268] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch PENDING <7>[6.879780] [drm:intel_uc_fw_fetch [i915]] GuC fw size 146432 ptr 3fdb20d0 <7>[6.879869] [drm:intel_uc_fw_fetch [i915]] GuC fw version 9.29 (wanted 9.29) <7>[6.880425] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch SUCCESS <7>[6.880723] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch i915/bxt_huc_ver01_07_1398.bin <7>[6.880807] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch PENDING <7>[6.882529] [drm:intel_uc_fw_fetch [i915]] HuC fw size 154432 ptr 0aad61c4 <7>[6.882621] [drm:intel_uc_fw_fetch [i915]] HuC fw version 1.7 (wanted 1.7) <7>[6.883098] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch SUCCESS > What we're polling to indicate load completion (GS_UKERNEL_READY) is > definitely what the firmware uses to signal readiness. The other check > we do (GS_MIA_CORE_STATE) should only apply for rc6 scenarios. From what > I can see from the firmware code, all the initialization steps are done > before GS_UKERNEL_READY is written to the status register so there > shouldn't be any missing acks in principle. > Is the GuC returning anything in the scratch 0 register? It should be > printed out by the H2G error message. The value of the status register > (0xc000) could also provide interesting debug info. When do you want to know? As you are probably aware, our first indication of failure is from wait_for_guc_preempt_report() and the wait there on report->report_return_status timing out. Michel asked what was the value when it timed out, but alas apl-guc was not available for comment. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Always read out M2_N2 in intel_cpu_transcoder_get_m_n, v2.
On Mon, Oct 15, 2018 at 11:40:23AM +0200, Maarten Lankhorst wrote:
> has_drrs is a flag we can't read out. We set it when seamless DRRS is
> enabled in pipe_config, so intel_dump_pipe_config() and
> intel_pipe_config_compare() will continue to do the right thing when
> has_drrs is set on the real state.
>
> This removes one more dereference of crtc->config.
> While at it, fixup the comment and also read out M2_N2 for CHV, since
> we program it in the set_m_n function.
>
> Changes since v1:
> - Only read out M2/N2 on platforms that support DRRS.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 ++--
> 1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 64c1c6f8e0f4..1ca93cb89842 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6769,6 +6769,19 @@ static void intel_pch_transcoder_set_m_n(const struct
> intel_crtc_state *crtc_sta
> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
> }
>
> +static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
> + enum transcoder transcoder)
> +{
> + if (IS_HASWELL(dev_priv))
> + return transcoder == TRANSCODER_EDP;
> +
> + /*
> + * Strictly speaking some registers are available before
> + * gen7, but we only support DRRS on gen7+
> + */
> + return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv);
> +}
> +
> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
> *crtc_state,
>const struct intel_link_m_n *m_n,
>const struct intel_link_m_n *m2_n2)
> @@ -6783,12 +6796,12 @@ static void intel_cpu_transcoder_set_m_n(const struct
> intel_crtc_state *crtc_sta
> I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
> I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
> I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
> - /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
> - * for gen < 8) and if DRRS is supported (to make sure the
> - * registers are not unnecessarily accessed).
> + /*
> + * M2_N2 registers are set only if DRRS is supported
> + * (to make sure the registers are not unnecessarily accessed).
>*/
> - if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
> - INTEL_GEN(dev_priv) < 8) && crtc_state->has_drrs) {
> + if (m2_n2 && crtc_state->has_drrs &&
> + transcoder_has_m2_n2(dev_priv, transcoder)) {
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -8637,12 +8650,8 @@ static void intel_cpu_transcoder_get_m_n(struct
> intel_crtc *crtc,
> m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
> m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
> & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> - /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
> - * gen < 8) and if DRRS is supported (to make sure the
> - * registers are not unnecessarily read).
> - */
> - if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
> - crtc->config->has_drrs) {
> +
> + if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
> m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
> m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
> m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
> --
> 2.19.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/perf: remove redundant oa buffer initialization
On Mon, Oct 15, 2018 at 04:59:57PM +0100, Lionel Landwerlin wrote:
> We initialize the OA buffer everytime we enable the OA unit (first call in
> gen[78]_oa_enable), so we don't need to initialize when preparing the metric
> set.
>
> Signed-off-by: Lionel Landwerlin
> Reviewed-by: Matthew Auld
Reviewed-by: Lucas De Marchi
thanks
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 17 -
> drivers/gpu/drm/i915/i915_perf.c | 6 +-
> 2 files changed, 1 insertion(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 63ce0da4e723..eef7c811bd8f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1529,23 +1529,6 @@ struct i915_oa_ops {
>*/
> bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
>
> - /**
> - * @init_oa_buffer: Resets the head and tail pointers of the
> - * circular buffer for periodic OA reports.
> - *
> - * Called when first opening a stream for OA metrics, but also may be
> - * called in response to an OA buffer overflow or other error
> - * condition.
> - *
> - * Note it may be necessary to clear the full OA buffer here as part of
> - * maintaining the invariable that new reports must be written to
> - * zeroed memory for us to be able to reliable detect if an expected
> - * report has not yet landed in memory. (At least on Haswell the OA
> - * buffer tail pointer is not synchronized with reports being visible
> - * to the CPU)
> - */
> - void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
> -
> /**
>* @enable_metric_set: Selects and applies any MUX configuration to set
>* up the Boolean and Custom (B/C) counters that are part of the
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 30911efd2cf7..14f7d03aabcf 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1530,8 +1530,6 @@ static int alloc_oa_buffer(struct drm_i915_private
> *dev_priv)
> goto err_unpin;
> }
>
> - dev_priv->perf.oa.ops.init_oa_buffer(dev_priv);
> -
> DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr =
> %p\n",
>i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma),
>dev_priv->perf.oa.oa_buffer.vaddr);
> @@ -2000,7 +1998,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
> *stream,
> return -EINVAL;
> }
>
> - if (!dev_priv->perf.oa.ops.init_oa_buffer) {
> + if (!dev_priv->perf.oa.ops.enable_metric_set) {
> DRM_DEBUG("OA unit not supported\n");
> return -ENODEV;
> }
> @@ -3389,7 +3387,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> dev_priv->perf.oa.ops.is_valid_mux_reg =
> hsw_is_valid_mux_addr;
> dev_priv->perf.oa.ops.is_valid_flex_reg = NULL;
> - dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer;
> dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set;
> dev_priv->perf.oa.ops.disable_metric_set =
> hsw_disable_metric_set;
> dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable;
> @@ -3408,7 +3405,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>*/
> dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
>
> - dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
> dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
> dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
> dev_priv->perf.oa.ops.read = gen8_oa_read;
> --
> 2.19.1
>
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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/perf: update generated files headers
On Mon, Oct 15, 2018 at 04:59:56PM +0100, Lionel Landwerlin wrote: > Lucas submitted a patch to generator script, so just reflecting the > change here. > > Signed-off-by: Lionel Landwerlin Reviewed-by: Lucas De Marchi thanks Lucas De Marchi > --- > drivers/gpu/drm/i915/i915_oa_bdw.c| 27 --- > drivers/gpu/drm/i915/i915_oa_bdw.h| 27 --- > drivers/gpu/drm/i915/i915_oa_bxt.c| 27 --- > drivers/gpu/drm/i915/i915_oa_bxt.h| 27 --- > drivers/gpu/drm/i915/i915_oa_cflgt2.c | 27 --- > drivers/gpu/drm/i915/i915_oa_cflgt2.h | 27 --- > drivers/gpu/drm/i915/i915_oa_cflgt3.c | 27 --- > drivers/gpu/drm/i915/i915_oa_cflgt3.h | 27 --- > drivers/gpu/drm/i915/i915_oa_chv.c| 27 --- > drivers/gpu/drm/i915/i915_oa_chv.h| 27 --- > drivers/gpu/drm/i915/i915_oa_cnl.c| 27 --- > drivers/gpu/drm/i915/i915_oa_cnl.h| 27 --- > drivers/gpu/drm/i915/i915_oa_glk.c| 27 --- > drivers/gpu/drm/i915/i915_oa_glk.h| 27 --- > drivers/gpu/drm/i915/i915_oa_hsw.c| 27 --- > drivers/gpu/drm/i915/i915_oa_hsw.h| 27 --- > drivers/gpu/drm/i915/i915_oa_icl.c| 27 --- > drivers/gpu/drm/i915/i915_oa_icl.h| 27 --- > drivers/gpu/drm/i915/i915_oa_kblgt2.c | 27 --- > drivers/gpu/drm/i915/i915_oa_kblgt2.h | 27 --- > drivers/gpu/drm/i915/i915_oa_kblgt3.c | 27 --- > drivers/gpu/drm/i915/i915_oa_kblgt3.h | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt2.c | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt2.h | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt3.c | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt3.h | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt4.c | 27 --- > drivers/gpu/drm/i915/i915_oa_sklgt4.h | 27 --- > 28 files changed, 112 insertions(+), 644 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c > b/drivers/gpu/drm/i915/i915_oa_bdw.c > index 4abd2e8b5083..4acdb94555b7 100644 > --- a/drivers/gpu/drm/i915/i915_oa_bdw.c > +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c > @@ -1,29 +1,10 @@ > /* > - * Autogenerated file by GPU Top : https://github.com/rib/gputop > - * DO NOT EDIT manually! > - * > - * > - * Copyright (c) 2015 Intel Corporation > + * SPDX-License-Identifier: MIT > * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > - * The above copyright notice and this permission notice (including the next > - * paragraph) shall be included in all copies or substantial portions of the > - * Software. > - * > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > DEALINGS > - * IN THE SOFTWARE. > + * Copyright © 2018 Intel Corporation > * > + * Autogenerated file by GPU Top : https://github.com/rib/gputop > + * DO NOT EDIT manually! > */ > > #include > diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h > b/drivers/gpu/drm/i915/i915_oa_bdw.h > index b812d16162ac..0e667f1a8aa1 100644 > --- a/drivers/gpu/drm/i915/i915_oa_bdw.h > +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h > @@ -1,29 +1,10 @@ > /* > - * Autogenerated file by GPU Top : https://github.com/rib/gputop > - * DO NOT EDIT manually! > - * > - * > - * Copyright (c) 2015 Intel Corporation > + * SPDX-License-Identifier: MIT > * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is
Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: sleep on enable
On 14/10/18 10:02, Chris Wilson wrote: Seems like there's a missing ack before the guc is ready for commands. I'm assuming you're running without HuC since the HuC auth H2G comes before this one. What we're polling to indicate load completion (GS_UKERNEL_READY) is definitely what the firmware uses to signal readiness. The other check we do (GS_MIA_CORE_STATE) should only apply for rc6 scenarios. From what I can see from the firmware code, all the initialization steps are done before GS_UKERNEL_READY is written to the status register so there shouldn't be any missing acks in principle. Is the GuC returning anything in the scratch 0 register? It should be printed out by the H2G error message. The value of the status register (0xc000) could also provide interesting debug info. Thanks, Daniele Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index fb0499f80b62..b7fd3422cb28 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1307,6 +1307,8 @@ int intel_guc_submission_enable(struct intel_guc *guc) GEM_BUG_ON(!guc->execbuf_client); + usleep_range(1000, 1); + err = intel_guc_sample_forcewake(guc); if (err) return err; ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
== Series Details == Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7) URL : https://patchwork.freedesktop.org/series/40747/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4982 -> Patchwork_10461 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/40747/revisions/7/mbox/ == Known issues == Here are the changes found in Patchwork_10461 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774, fdo#107859) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@drv_getparams_basic@basic-subslice-total: fi-snb-2520m: DMESG-WARN (fdo#103713) -> PASS +10 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fi-icl-u2: INCOMPLETE (fdo#107713) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 == Participating hosts (52 -> 47) == Additional (2): fi-kbl-soraka fi-skl-guc Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-kbl-7560u == Build changes == * Linux: CI_DRM_4982 -> Patchwork_10461 CI_DRM_4982: 6222b112cd485ea16d06c120531becf97ee57bc7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10461: 40f273c57c71aeb1957dd683859fdee8baffd13a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 40f273c57c71 drm/i915/icl: Preempt-to-idle support in execlists. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10461/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gen8: Disable master intr before reading
== Series Details == Series: series starting with [1/3] drm/i915/gen8: Disable master intr before reading URL : https://patchwork.freedesktop.org/series/51009/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4981_full -> Patchwork_10458_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10458_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10458_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10458_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10458_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-hsw: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-a-ctm-max: shard-apl: PASS -> FAIL (fdo#108147) igt@kms_cursor_crc@cursor-256x256-random: shard-glk: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_crc@cursor-256x256-sliding: shard-skl: NOTRUN -> FAIL (fdo#103232) +1 igt@kms_cursor_crc@cursor-64x64-dpms: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt: shard-skl: NOTRUN -> FAIL (fdo#103167) +4 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145) +3 igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: shard-glk: NOTRUN -> FAIL (fdo#108145) Possible fixes igt@kms_color@pipe-a-ctm-negative: shard-skl: FAIL -> PASS igt@kms_cursor_crc@cursor-128x42-sliding: shard-glk: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: FAIL (fdo#103167) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS +4 igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: shard-skl: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: shard-skl: FAIL (fdo#108145) -> PASS igt@kms_plane_alpha_blend@pipe-b-constant-alpha-mid: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-kbl: DMESG-WARN (fdo#105345) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4981 -> Patchwork_10458 CI_DRM_4981: 79887268bfe4128788d7cfcf38b62308346fd7f1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4677: 68ff28a022dbaa26a20c8a3c0212011a006614b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Pa
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
== Series Details == Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7) URL : https://patchwork.freedesktop.org/series/40747/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Preempt-to-idle support in execlists. -drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3727:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev7)
URL : https://patchwork.freedesktop.org/series/40747/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40f273c57c71 drm/i915/icl: Preempt-to-idle support in execlists.
-:129: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"!execlists->ctrl_reg"
#129: FILE: drivers/gpu/drm/i915/intel_lrc.c:502:
+ GEM_BUG_ON(execlists->ctrl_reg == NULL);
-:205: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#205: FILE: drivers/gpu/drm/i915/intel_lrc.c:940:
+ if ((status & GEN8_CTX_STATUS_IDLE_ACTIVE) &&
+(status & GEN11_CTX_STATUS_PREEMPT_IDLE)) {
-:239: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/intel_lrc.c:970:
+ buf[2*head + 1] == execlists->preempt_complete_status)) {
^
total: 0 errors, 0 warnings, 3 checks, 187 lines checked
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Disable master intr before reading
On 15/10/18 07:14, Mika Kuoppala wrote: Disable master interrupt before reading level indications. This will close a race where we get a level indication between reading and disabling, generating an extra interrupt where we could have avoided one. Further, as the reading acts also as a post, replace the write/post on the irq reset with the helper. On enabling side, posting doesn't serve any purpose so it can also be replaced with helper. Cc: Chris Wilson Cc: Ville Syrjälä Cc: Daniele Ceraolo Spurio Signed-off-by: Mika Kuoppala Acked-by: Chris Wilson --- Reviewed-by: Daniele Ceraolo Spurio Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
== Series Details == Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3) URL : https://patchwork.freedesktop.org/series/50810/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4982 -> Patchwork_10460 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50810/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_10460 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@drv_selftest@live_hangcheck: fi-icl-u: PASS -> INCOMPLETE (fdo#108315) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107859, fdo#107556) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@pm_rpm@module-reload: fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@drv_getparams_basic@basic-subslice-total: fi-snb-2520m: DMESG-WARN (fdo#103713) -> PASS +10 igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fi-icl-u2: INCOMPLETE (fdo#107713) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 == Participating hosts (52 -> 49) == Additional (2): fi-kbl-soraka fi-skl-guc Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4982 -> Patchwork_10460 CI_DRM_4982: 6222b112cd485ea16d06c120531becf97ee57bc7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10460: 3b0d6f948ca201a0a7433e6b58260a3b2bdc399f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3b0d6f948ca2 drm/i915/perf: add a parameter to control the size of OA buffer 9a97a3a627b0 drm/i915/perf: pass stream to vfuncs when possible 88da93631a80 drm/i915/perf: remove redundant oa buffer initialization 766560106b0d drm/i915/perf: update generated files headers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10460/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915/icl: Preempt-to-idle support in execlists.
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a special batch buffer to be executed,
so the Command Streamer never preempted to idle directly. In Icelake it is
possible, as there is a hardware mechanism to inform the kernel about
status of the preemption request.
This patch does not cover using the new preemption mechanism when GuC is
active.
v2: Added needs_preempt_context() change so that it is not created when
preempt-to-idle is supported. (Chris)
Updated setting HWACK flag so that it is cleared after
preempt-to-dle. (Chris, Daniele)
Updated to use I915_ENGINE_HAS_PREEMPTION flag. (Chris)
v3: Fixed needs_preempt_context() change. (Chris)
Merged preemption trigger functions to one. (Chris)
Fixed conyext state tonot assume COMPLETED_MASK after preemption,
since idle-to-idle case will not have it set.
v4: Simplified needs_preempt_context() change. (Daniele)
Removed clearing HWACK flag in idle-to-idle preempt. (Daniele)
v5: Renamed inject_preempt_context(). (Daniele)
Removed duplicated GEM_BUG_ON() on HWACK (Daniele)
Bspec: 18922
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michal Winiarski
Cc: Mika Kuoppala
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Tomasz Lis
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem_context.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 109 +--
drivers/gpu/drm/i915/intel_lrc.h | 1 +
6 files changed, 84 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef0..4817438 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2597,6 +2597,8 @@ intel_info(const struct drm_i915_private *dev_priv)
((dev_priv)->info.has_logical_ring_elsq)
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
((dev_priv)->info.has_logical_ring_preemption)
+#define HAS_HW_PREEMPT_TO_IDLE(dev_priv) \
+ ((dev_priv)->info.has_hw_preempt_to_idle)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8cbe580..98ca20e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -529,7 +529,8 @@ static void init_contexts(struct drm_i915_private *i915)
static bool needs_preempt_context(struct drm_i915_private *i915)
{
- return HAS_LOGICAL_RING_PREEMPTION(i915);
+ return HAS_LOGICAL_RING_PREEMPTION(i915) &&
+ !HAS_HW_PREEMPT_TO_IDLE(i915);
}
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a05cc7..f708d97 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -597,7 +597,8 @@ static const struct intel_device_info intel_cannonlake_info
= {
GEN10_FEATURES, \
GEN(11), \
.ddb_size = 2048, \
- .has_logical_ring_elsq = 1
+ .has_logical_ring_elsq = 1, \
+ .has_hw_preempt_to_idle = 1
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index af70026..7dcf0fd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -104,6 +104,7 @@ enum intel_ppgtt {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_hw_preempt_to_idle); \
func(has_overlay); \
func(has_pooled_eu); \
func(has_psr); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ff0e2b3..4c2bfed 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -155,6 +155,7 @@
#define GEN8_CTX_STATUS_ACTIVE_IDLE(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
+#define GEN11_CTX_STATUS_PREEMPT_IDLE (1 << 29)
#define GEN8_CTX_STATUS_COMPLETED_MASK \
(GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
@@ -488,29 +489,49 @@ static void port_assign(struct execlist_port *port,
struct i915_request *rq)
port_set(port, port_pack(i915_request_get(rq), port_count(port)));
}
-static void inject_preempt_context(struct intel_engine_cs *engine)
+static void execlist_send_preempt_to_idle(struct intel_engine_cs *engine)
{
struct intel_engine_execlists *execlists = &engine->execlists;
- struct intel_context *ce =
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
== Series Details == Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3) URL : https://patchwork.freedesktop.org/series/50810/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/perf: update generated files headers Okay! Commit: drm/i915/perf: remove redundant oa buffer initialization -drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) Commit: drm/i915/perf: pass stream to vfuncs when possible -drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void) Commit: drm/i915/perf: add a parameter to control the size of OA buffer -O:drivers/gpu/drm/i915/i915_perf.c:1422:15: warning: memset with byte count of 16777216 -O:drivers/gpu/drm/i915/i915_perf.c:1480:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_perf.c:2669:17: warning: ex
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Add OA buffer size uAPI parameter (rev3)
== Series Details == Series: drm/i915/perf: Add OA buffer size uAPI parameter (rev3) URL : https://patchwork.freedesktop.org/series/50810/ State : warning == Summary == $ dim checkpatch origin/drm-tip 766560106b0d drm/i915/perf: update generated files headers 88da93631a80 drm/i915/perf: remove redundant oa buffer initialization -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: gen[78]_oa_enable), so we don't need to initialize when preparing the metric total: 0 errors, 1 warnings, 0 checks, 53 lines checked 9a97a3a627b0 drm/i915/perf: pass stream to vfuncs when possible 3b0d6f948ca2 drm/i915/perf: add a parameter to control the size of OA buffer -:48: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'tail' may be better as '(tail)' to avoid precedence issues #48: FILE: drivers/gpu/drm/i915/i915_perf.c:215: +#define OA_TAKEN(tail, head) ((tail - head) & (dev_priv->perf.oa.oa_buffer.vma->size - 1)) -:48: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'head' may be better as '(head)' to avoid precedence issues #48: FILE: drivers/gpu/drm/i915/i915_perf.c:215: +#define OA_TAKEN(tail, head) ((tail - head) & (dev_priv->perf.oa.oa_buffer.vma->size - 1)) total: 0 errors, 0 warnings, 2 checks, 259 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Hold rpm wakeref for debugfs/i915_drop_caches_set
== Series Details == Series: drm/i915: Hold rpm wakeref for debugfs/i915_drop_caches_set URL : https://patchwork.freedesktop.org/series/51001/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4980_full -> Patchwork_10457_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10457_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10457_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10457_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-128x128-rapid-movement: shard-snb: PASS -> SKIP igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10457_full that come from known issues: === IGT changes === Issues hit igt@gem_render_linear_blits@basic: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_softpin@noreloc-s3: shard-snb: PASS -> DMESG-WARN (fdo#102365) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-apl: PASS -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-skl: PASS -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-256x256-random: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render: shard-glk: PASS -> DMESG-FAIL (fdo#106538, fdo#103167) igt@kms_frontbuffer_tracking@fbc-badstride: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +1 igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@pm_rpm@dpms-lpsp: shard-skl: PASS -> INCOMPLETE (fdo#107807) +1 Possible fixes igt@drv_suspend@shrink: shard-snb: INCOMPLETE (fdo#105411, fdo#106886) -> PASS igt@gem_exec_await@wide-contexts: shard-kbl: FAIL (fdo#106680) -> PASS igt@kms_busy@extended-pageflip-hang-newfb-render-c: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: shard-skl: FAIL (fdo#103184) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: FAIL (fdo#105682) -> PASS +1 igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu: shard-skl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@pm_rpm@gem-execbuf-stress-extra-wait: shard-skl: INCOMPLETE (fdo#107807, fdo#107803) -> PASS Warnings igt@kms_cursor_crc@cursor-256x85-onscreen: shard-glk: FAIL (fdo#103232) -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> DMESG-FAIL (fdo#106538, fdo#103167) fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107803 https://bugs.freedesktop.o
Re: [Intel-gfx] [PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers
On Fri, Oct 12, 2018 at 03:58:52PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 12, 2018 at 03:25:37PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> > > From: Lucas De Marchi
> > >
> > > combo-phy register instances are at same offset from base for each
> > > combo-phy port, i.e.
> > >
> > > Port A base offset: 0x16200
> > > Port B base offset: 0x6C000
> > >
> > > All the other addresses for both ports can be derived by calculating
> > > offset to these base addresses.
> > >
> > > PORT_CL_DW_OFFSET 0x0
> > > PORT_CL_DW 0 + x * 4
> > >
> > > PORT_COMP_OFFSET 0x100
> > > PORT_COMP_DW 0x100 + x * 4
> > >
> > > PORT_PCS_AUX_OFFSET 0x300
> > > PORT_PCS_GRP_OFFSET 0x600
> > > PORT_PCS_LN_OFFSET 0x800 + y * 0x100
> > >
> > > PORT_TX_AUX_OFFSET 0x380
> > > PORT_TX_GRP_OFFSET 0x680
> > > PORT_TX_LN_OFFSET0x880 + y * 0x100
> >
> > well, in the past I was in favor of trying to find
> > logic and simplify as much as possible the register offsets and bits.
> >
> > However nowadays I'm more inclined to keep them explicit for some
> > reasons.
> >
> > 1. Another developer when adding some workaround later might
> > search the code for the reg offset, not finding and adding it again.
> > In this case the risk is minimal because it is only a risk of
> > duplicating the offset definition.
> >
> > 2. HW Architects when planing to remove some bits consult us
> > to see the impact and I always get myself searching for the offsets.
> > In this case the risk is higher because if we can't find the hidden
> > offset we might underestimate the impact on a future hw generation.
> >
> > 3. I'm checking to see if there are better ways to get
> > spec changes to notify us that we have to change something.
> > It would be harder to parse, but I know it is possible.
> >
> > Well, maybe a tool for 3 could already answer the item above
> > in a automated and more reliable way... But while we don't have
> > such tool maybe it is better to keep explicit.
> >
> > But I'm not blocking or anything like that. I'm just brainstorming
> > some points here from my view on this.
>
>
> I agree with the reasonings, but in this particular case I think it's simpler
> since
> the spec itself is now modular wrt combophy instance. See 29482, although it
> continues
> to define the individual values, this is not always the case.
hmm... makes sense...
>
>
> >
> > another detail below:
> >
> > >
> > > And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
> > >
> > > Based on original patch by Mahesh Kumar .
> > >
> > > Signed-off-by: Lucas De Marchi
> > > Signed-off-by: Mahesh Kumar
> > > Cc: Rodrigo Vivi
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 154
> > > ++--
> > > 1 file changed, 54 insertions(+), 100 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index e3ac65f5aa81..eaf3e0d529d3 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1658,21 +1658,21 @@ enum i915_power_well_id {
> > > /*
> > > * CNL/ICL Port/COMBO-PHY Registers
> > > */
> > > +#define _ICL_COMBOPHY_A 0x162000
> > > +#define _ICL_COMBOPHY_B 0x6C000
> > > +#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
> > > + _ICL_COMBOPHY_B)
> > > +
> > > /* CNL/ICL Port CL_DW registers */
> > > -#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> > > +#define _ICL_PORT_CL_DW(port, dw)(_ICL_COMBOPHY(port) + \
> > > + 4 * (dw))
> >
> > probably better if inverted DW(dw, port)
> > because reg definition is DW#dw_#port and I got
> > confused when reviewing items below...
>
> ok
thanks, with this changed feel free to already add
Reviewed-by: Rodrigo Vivi
>
> thanks
> Lucas De Marchi
>
> >
> > >
> > > -#define _ICL_PORT_CL_DW5_A 0x162014
> > > -#define _ICL_PORT_CL_DW5_B 0x6C014
> > > -#define ICL_PORT_CL_DW5(port)_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> > > - _ICL_PORT_CL_DW5_B)
> > > +#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> > > +#define ICL_PORT_CL_DW5(port)_MMIO(_ICL_PORT_CL_DW(port, 5))
> > > #define CL_POWER_DOWN_ENABLE (1 << 4)
> > > #define SUS_CLOCK_CONFIG (3 << 0)
> > >
> > > -#define _CNL_PORT_CL_DW10_A 0x162028
> > > -#define _ICL_PORT_CL_DW10_B 0x6c028
> > > -#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port,\
> > > -_CNL_PORT_CL_DW10_A, \
> > > -_ICL_PORT_CL_DW10_B)
> > > +#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(port, 10))
> > > #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> > > #define
Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Initialize SCDC registers according to spec
On 10/15/2018 06:41 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 01:14:45PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement features that require polling of the status update bits. Once
FRL, DSC, or Source Test is enabled in the driver the status flags will
need to be read by the source according to specification.
Cc: Ville Syrjälä
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_hdmi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2c53efc..ab3eac5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1910,6 +1910,8 @@ bool intel_hdmi_compute_config(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
+ struct i2c_adapter *adapter =
+ intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
connector->base.id, connector->name);
@@ -1925,6 +1927,16 @@ bool intel_hdmi_compute_config(struct intel_encoder
*encoder,
if (intel_hdmi_set_edid(connector))
status = connector_status_connected;
+ if (connector->display_info.hdmi.scdc.supported) {
+ /* SCDC source version HDMI 2.1 Sec. 10.4.1.2 */
+ if (drm_scdc_writeb(adapter, SCDC_SOURCE_VERSION, 0x01) < 0)
+ DRM_DEBUG_KMS("Unable to set SCDC Source Version
register\n");
+
+ /* Clear SCDC CONFIG_0 HDMI 2.1 Sec. 10.4.1.6 - RR_Enable
Polling Only */
+ if (drm_scdc_writeb(adapter, SCDC_CONFIG_0, 0x00) < 0)
+ DRM_DEBUG_KMS("Unable to set SCDC CONFIG_0 register\n");
+ }
I'd probably put this into intel_hdmi_set_edid() so that we'll do it for
the ->force() path as well. Or maybe a separate function called from
both places.
intel_hdmi_set_edid() doesn't actually decode the edid block that it
reads. This means
display_info.hdmi.scdc.supported isn't from the new EDID block. I have a
patch in my sandbox to send the new EDID block to DRM to be decoded.
-Clint
+
out:
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel] sna/uxa: Fix colormap handling at screen depth 30. (v2)
On Tue, Jun 12, 2018 at 06:20:35PM +0200, Mario Kleiner wrote:
> The various clut handling functions like a setup
> consistent with the x-screen color depth. Otherwise
> we observe improper sampling in the gamma tables
> at depth 30.
>
> Therefore replace hard-coded bitsPerRGB = 8 by actual
> bits per channel scrn->rgbBits. Also use this for call
> to xf86HandleColormaps().
>
> Tested for uxa and sna at depths 8, 16, 24 and 30 on
> IvyBridge, and tested at depth 24 and 30 that xgamma
> and gamma table animations work, and with measurement
> equipment to make sure identity gamma ramps actually
> are identity mappings at the output.
>
> v2: Also deal with X-Server 1.19 and earlier, which as of
> v1.19.6 lack a fix to color palette handling and can
> not deal with depths/bpc > 24/8 bpc. On < 1.20 we skip
> xf86HandleColormaps() setup at > 8 bpc. This disables
> color palette handling on such servers at > 8 bpc, but
> still keeps RandR gamma table handling intact.
>
> Tested on 1.19.6 and 1.20.0 to do the right thing.
>
> Signed-off-by: Mario Kleiner
Forgot this didn't get applied. It did make sense to me at the
time when I was looking at the explosions with depth 30.
Still seems to do the trick on 1.19, and redshit still works
so
Reviewed-by: Ville Syrjälä
> ---
> src/sna/sna_driver.c | 9 ++---
> src/uxa/intel_driver.c | 6 +-
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/src/sna/sna_driver.c b/src/sna/sna_driver.c
> index 2007e354..8c79d43b 100644
> --- a/src/sna/sna_driver.c
> +++ b/src/sna/sna_driver.c
> @@ -1152,7 +1152,7 @@ sna_screen_init(SCREEN_INIT_ARGS_DECL)
> if (!miInitVisuals(&visuals, &depths, &nvisuals, &ndepths, &rootdepth,
> &defaultVisual,
> ((unsigned long)1 << (scrn->bitsPerPixel - 1)),
> -8, -1))
> +scrn->rgbBits, -1))
> return FALSE;
>
> if (!miScreenInit(screen, NULL,
> @@ -1223,8 +1223,11 @@ sna_screen_init(SCREEN_INIT_ARGS_DECL)
> if (!miCreateDefColormap(screen))
> return FALSE;
>
> - if (sna->mode.num_real_crtc &&
> - !xf86HandleColormaps(screen, 256, 8, sna_load_palette, NULL,
> + /* X-Server < 1.20 mishandles > 256 slots / > 8 bpc color maps. */
> + if (sna->mode.num_real_crtc && (scrn->rgbBits <= 8 ||
> + XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,20,0,0,0)) &&
> + !xf86HandleColormaps(screen, 1 << scrn->rgbBits, scrn->rgbBits,
> + sna_load_palette, NULL,
>CMAP_RELOAD_ON_MODE_SWITCH |
>CMAP_PALETTED_TRUECOLOR))
> return FALSE;
> diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
> index 3703c412..77c0dc00 100644
> --- a/src/uxa/intel_driver.c
> +++ b/src/uxa/intel_driver.c
> @@ -991,7 +991,11 @@ I830ScreenInit(SCREEN_INIT_ARGS_DECL)
> if (!miCreateDefColormap(screen))
> return FALSE;
>
> - if (!xf86HandleColormaps(screen, 256, 8, I830LoadPalette, NULL,
> + /* X-Server < 1.20 mishandles > 256 slots / > 8 bpc color maps. */
> + if ((scrn->rgbBits <= 8 ||
> + XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,20,0,0,0)) &&
> + !xf86HandleColormaps(screen, 1 << scrn->rgbBits, scrn->rgbBits,
> + I830LoadPalette, NULL,
>CMAP_RELOAD_ON_MODE_SWITCH |
>CMAP_PALETTED_TRUECOLOR)) {
> return FALSE;
> --
> 2.17.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 04/18] drm/selftest: Add drm damage helper selftest
> On Wed, Oct 10, 2018 at 05:16:43PM -0700, Deepak Rawat wrote:
> > Selftest for drm damage helper iterator functions.
> >
> > Cc: ville.syrj...@linux.intel.com
> > Cc: Daniel Vetter
> > Cc: Pekka Paalanen
> > Cc: Daniel Stone
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: igt-...@lists.freedesktop.org
> > Cc: petri.latv...@intel.com
> > Cc: ch...@chris-wilson.co.uk
> > Signed-off-by: Deepak Rawat
> > ---
> > drivers/gpu/drm/selftests/Makefile| 3 +-
> > .../selftests/drm_damage_helper_selftests.h | 22 +
> > .../drm/selftests/test-drm_damage_helper.c| 844
> ++
> > 3 files changed, 868 insertions(+), 1 deletion(-)
> > create mode 100644
> drivers/gpu/drm/selftests/drm_damage_helper_selftests.h
> > create mode 100644 drivers/gpu/drm/selftests/test-
> drm_damage_helper.c
> >
> > diff --git a/drivers/gpu/drm/selftests/Makefile
> b/drivers/gpu/drm/selftests/Makefile
> > index 9fc349fa18e9..88ac216f5962 100644
> > --- a/drivers/gpu/drm/selftests/Makefile
> > +++ b/drivers/gpu/drm/selftests/Makefile
> > @@ -1 +1,2 @@
> > -obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm-
> helper.o
> > +obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm-
> helper.o \
> > + test-drm_damage_helper.o
>
> With the testcase intagrated into the test-drm-helper.ko module, for
> patches 1-4 in this series:
>
> Reviewed-by: Daniel Vetter
>
> Obviously needs some adjusting on the igt side too, since we seem to be
> missing the igt scaffolding for tests-drm-helper.ko.
> -Daniel
Hi Daniel,
Thanks for the review. I am a little confused here. Should we have single
kernel module for drm plane helper selftest and damage helper selftest?
Also shall I rename the kernel selfttest to kms_*?
For user-space igt test it should be it makes sense to rename to kms_selftets?
>
> > diff --git a/drivers/gpu/drm/selftests/drm_damage_helper_selftests.h
> b/drivers/gpu/drm/selftests/drm_damage_helper_selftests.h
> > new file mode 100644
> > index ..3a1cbe05bef0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/selftests/drm_damage_helper_selftests.h
> > @@ -0,0 +1,22 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +selftest(damage_iter_no_damage, igt_damage_iter_no_damage)
> > +selftest(damage_iter_no_damage_fractional_src,
> igt_damage_iter_no_damage_fractional_src)
> > +selftest(damage_iter_no_damage_src_moved,
> igt_damage_iter_no_damage_src_moved)
> > +selftest(damage_iter_no_damage_fractional_src_moved,
> igt_damage_iter_no_damage_fractional_src_moved)
> > +selftest(damage_iter_no_damage_not_visible,
> igt_damage_iter_no_damage_not_visible)
> > +selftest(damage_iter_no_damage_no_crtc,
> igt_damage_iter_no_damage_no_crtc)
> > +selftest(damage_iter_no_damage_no_fb,
> igt_damage_iter_no_damage_no_fb)
> > +selftest(damage_iter_simple_damage,
> igt_damage_iter_simple_damage)
> > +selftest(damage_iter_single_damage, igt_damage_iter_single_damage)
> > +selftest(damage_iter_single_damage_intersect_src,
> igt_damage_iter_single_damage_intersect_src)
> > +selftest(damage_iter_single_damage_outside_src,
> igt_damage_iter_single_damage_outside_src)
> > +selftest(damage_iter_single_damage_fractional_src,
> igt_damage_iter_single_damage_fractional_src)
> > +selftest(damage_iter_single_damage_intersect_fractional_src,
> igt_damage_iter_single_damage_intersect_fractional_src)
> > +selftest(damage_iter_single_damage_outside_fractional_src,
> igt_damage_iter_single_damage_outside_fractional_src)
> > +selftest(damage_iter_single_damage_src_moved,
> igt_damage_iter_single_damage_src_moved)
> > +selftest(damage_iter_single_damage_fractional_src_moved,
> igt_damage_iter_single_damage_fractional_src_moved)
> > +selftest(damage_iter_damage, igt_damage_iter_damage)
> > +selftest(damage_iter_damage_one_intersect,
> igt_damage_iter_damage_one_intersect)
> > +selftest(damage_iter_damage_one_outside,
> igt_damage_iter_damage_one_outside)
> > +selftest(damage_iter_damage_src_moved,
> igt_damage_iter_damage_src_moved)
> > +selftest(damage_iter_damage_not_visible,
> igt_damage_iter_damage_not_visible)
> > diff --git a/drivers/gpu/drm/selftests/test-drm_damage_helper.c
> b/drivers/gpu/drm/selftests/test-drm_damage_helper.c
> > new file mode 100644
> > index ..17754734c47a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/selftests/test-drm_damage_helper.c
> > @@ -0,0 +1,844 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Test case for drm_damage_helper functions
> > + */
> > +
> > +#define pr_fmt(fmt) "drm_damage_helper: " fmt
> > +
> > +#include
> > +#include
> > +
> > +#define TESTS "drm_damage_helper_selftests.h"
> > +#include "drm_selftest.h"
> > +
> > +#define FAIL(test, msg, ...) \
> > + do { \
> > + if (test) { \
> > + pr_err("%s/%u: " msg, __FUNCTION__, __LINE__,
> ##__VA_ARGS__); \
> > + return -EINVAL; \
> > + } \
> > + } while (0)
> > +
> > +#define FAIL_ON(x) FAIL((x), "%s", "FAIL_ON(
[Intel-gfx] [PATCH v3 1/4] drm/i915/perf: update generated files headers
Lucas submitted a patch to generator script, so just reflecting the change here. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_oa_bdw.c| 27 --- drivers/gpu/drm/i915/i915_oa_bdw.h| 27 --- drivers/gpu/drm/i915/i915_oa_bxt.c| 27 --- drivers/gpu/drm/i915/i915_oa_bxt.h| 27 --- drivers/gpu/drm/i915/i915_oa_cflgt2.c | 27 --- drivers/gpu/drm/i915/i915_oa_cflgt2.h | 27 --- drivers/gpu/drm/i915/i915_oa_cflgt3.c | 27 --- drivers/gpu/drm/i915/i915_oa_cflgt3.h | 27 --- drivers/gpu/drm/i915/i915_oa_chv.c| 27 --- drivers/gpu/drm/i915/i915_oa_chv.h| 27 --- drivers/gpu/drm/i915/i915_oa_cnl.c| 27 --- drivers/gpu/drm/i915/i915_oa_cnl.h| 27 --- drivers/gpu/drm/i915/i915_oa_glk.c| 27 --- drivers/gpu/drm/i915/i915_oa_glk.h| 27 --- drivers/gpu/drm/i915/i915_oa_hsw.c| 27 --- drivers/gpu/drm/i915/i915_oa_hsw.h| 27 --- drivers/gpu/drm/i915/i915_oa_icl.c| 27 --- drivers/gpu/drm/i915/i915_oa_icl.h| 27 --- drivers/gpu/drm/i915/i915_oa_kblgt2.c | 27 --- drivers/gpu/drm/i915/i915_oa_kblgt2.h | 27 --- drivers/gpu/drm/i915/i915_oa_kblgt3.c | 27 --- drivers/gpu/drm/i915/i915_oa_kblgt3.h | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt2.c | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt2.h | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt3.c | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt3.h | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt4.c | 27 --- drivers/gpu/drm/i915/i915_oa_sklgt4.h | 27 --- 28 files changed, 112 insertions(+), 644 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index 4abd2e8b5083..4acdb94555b7 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -1,29 +1,10 @@ /* - * Autogenerated file by GPU Top : https://github.com/rib/gputop - * DO NOT EDIT manually! - * - * - * Copyright (c) 2015 Intel Corporation + * SPDX-License-Identifier: MIT * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. + * Copyright © 2018 Intel Corporation * + * Autogenerated file by GPU Top : https://github.com/rib/gputop + * DO NOT EDIT manually! */ #include diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h index b812d16162ac..0e667f1a8aa1 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.h +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h @@ -1,29 +1,10 @@ /* - * Autogenerated file by GPU Top : https://github.com/rib/gputop - * DO NOT EDIT manually! - * - * - * Copyright (c) 2015 Intel Corporation + * SPDX-License-Identifier: MIT * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
[Intel-gfx] [PATCH v3 2/4] drm/i915/perf: remove redundant oa buffer initialization
We initialize the OA buffer everytime we enable the OA unit (first call in
gen[78]_oa_enable), so we don't need to initialize when preparing the metric
set.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm/i915/i915_perf.c | 6 +-
2 files changed, 1 insertion(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63ce0da4e723..eef7c811bd8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1529,23 +1529,6 @@ struct i915_oa_ops {
*/
bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
- /**
-* @init_oa_buffer: Resets the head and tail pointers of the
-* circular buffer for periodic OA reports.
-*
-* Called when first opening a stream for OA metrics, but also may be
-* called in response to an OA buffer overflow or other error
-* condition.
-*
-* Note it may be necessary to clear the full OA buffer here as part of
-* maintaining the invariable that new reports must be written to
-* zeroed memory for us to be able to reliable detect if an expected
-* report has not yet landed in memory. (At least on Haswell the OA
-* buffer tail pointer is not synchronized with reports being visible
-* to the CPU)
-*/
- void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
-
/**
* @enable_metric_set: Selects and applies any MUX configuration to set
* up the Boolean and Custom (B/C) counters that are part of the
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 30911efd2cf7..14f7d03aabcf 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1530,8 +1530,6 @@ static int alloc_oa_buffer(struct drm_i915_private
*dev_priv)
goto err_unpin;
}
- dev_priv->perf.oa.ops.init_oa_buffer(dev_priv);
-
DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr =
%p\n",
i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma),
dev_priv->perf.oa.oa_buffer.vaddr);
@@ -2000,7 +1998,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -EINVAL;
}
- if (!dev_priv->perf.oa.ops.init_oa_buffer) {
+ if (!dev_priv->perf.oa.ops.enable_metric_set) {
DRM_DEBUG("OA unit not supported\n");
return -ENODEV;
}
@@ -3389,7 +3387,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.ops.is_valid_mux_reg =
hsw_is_valid_mux_addr;
dev_priv->perf.oa.ops.is_valid_flex_reg = NULL;
- dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer;
dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set;
dev_priv->perf.oa.ops.disable_metric_set =
hsw_disable_metric_set;
dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable;
@@ -3408,7 +3405,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
*/
dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
- dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.oa.ops.read = gen8_oa_read;
--
2.19.1
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[Intel-gfx] [PATCH v3 4/4] drm/i915/perf: add a parameter to control the size of OA buffer
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA reports to be available
through the i915 perf stream, we can set the OA buffer to the minimum
size to avoid consuming memory which won't be used by the driver.
v2: Simplify oa buffer size exponent selection (Chris)
Reuse vma size field (Lionel)
v3: Restrict size opening parameter to values supported by HW (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 92 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +
include/uapi/drm/i915_drm.h | 7 +++
4 files changed, 74 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65eaac2d7e3c..f12770bd4858 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2053,6 +2053,7 @@ struct drm_i915_private {
u32 last_ctx_id;
int format;
int format_size;
+ int size_exponent;
/**
* Locks reads and writes to all head/tail state
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 88f3f9b6a353..ff90ccebe1c1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -212,13 +212,7 @@
#include "i915_oa_icl.h"
#include "intel_lrc_reg.h"
-/* HW requires this to be a power of two, between 128k and 16M, though driver
- * is currently generally designed assuming the largest 16M size is used such
- * that the overflow cases are unlikely in normal operation.
- */
-#define OA_BUFFER_SIZE SZ_16M
-
-#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
+#define OA_TAKEN(tail, head) ((tail - head) &
(dev_priv->perf.oa.oa_buffer.vma->size - 1))
/**
* DOC: OA Tail Pointer Race
@@ -361,6 +355,7 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+ u32 oa_buffer_size_exponent;
};
static void free_oa_config(struct drm_i915_private *dev_priv,
@@ -523,7 +518,7 @@ static bool oa_buffer_check_unlocked(struct
drm_i915_private *dev_priv)
* could put the tail out of bounds...
*/
if (hw_tail >= gtt_offset &&
- hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
+ hw_tail < (gtt_offset +
dev_priv->perf.oa.oa_buffer.vma->size)) {
dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset =
aging_tail = hw_tail;
dev_priv->perf.oa.oa_buffer.aging_timestamp = now;
@@ -652,7 +647,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
int report_size = dev_priv->perf.oa.oa_buffer.format_size;
u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
+ u32 mask = (dev_priv->perf.oa.oa_buffer.vma->size - 1);
size_t start_offset = *offset;
unsigned long flags;
unsigned int aged_tail_idx;
@@ -692,8 +687,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ if (WARN_ONCE(head > dev_priv->perf.oa.oa_buffer.vma->size || head %
report_size ||
+ tail > dev_priv->perf.oa.oa_buffer.vma->size || tail %
report_size,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -716,7 +711,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* here would imply a driver bug that would result
* in an overrun.
*/
- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
+ if (WARN_ON((dev_priv->perf.oa.oa_buffer.vma->size - head) <
report_size)) {
DRM_ERROR("Spurious OA head ptr: non-integral report
offset\n");
break;
}
@@ -941,7 +936,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream
*stream,
int report_size = dev_priv->perf.oa.oa_buffer.format_size;
u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
+ u32 mask = (dev_priv->perf.oa.oa_buffer.vma->size - 1);
size_t start_
[Intel-gfx] [PATCH v3 3/4] drm/i915/perf: pass stream to vfuncs when possible
We want to use some of the properties of the perf stream to program
the hardware in a later commit.
v2: Pass only perf stream as argument (Matthew)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++---
drivers/gpu/drm/i915/i915_perf.c | 43 +++-
2 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eef7c811bd8f..65eaac2d7e3c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1535,8 +1535,7 @@ struct i915_oa_ops {
* counter reports being sampled. May apply system constraints such as
* disabling EU clock gating as required.
*/
- int (*enable_metric_set)(struct drm_i915_private *dev_priv,
-const struct i915_oa_config *oa_config);
+ int (*enable_metric_set)(struct i915_perf_stream *stream);
/**
* @disable_metric_set: Remove system constraints associated with using
@@ -1547,12 +1546,12 @@ struct i915_oa_ops {
/**
* @oa_enable: Enable periodic sampling
*/
- void (*oa_enable)(struct drm_i915_private *dev_priv);
+ void (*oa_enable)(struct i915_perf_stream *stream);
/**
* @oa_disable: Disable periodic sampling
*/
- void (*oa_disable)(struct drm_i915_private *dev_priv);
+ void (*oa_disable)(struct i915_perf_stream *stream);
/**
* @read: Copy data from the circular OA buffer into a given userspace
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 14f7d03aabcf..88f3f9b6a353 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -890,8 +890,8 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
dev_priv->perf.oa.period_exponent);
- dev_priv->perf.oa.ops.oa_disable(dev_priv);
- dev_priv->perf.oa.ops.oa_enable(dev_priv);
+ dev_priv->perf.oa.ops.oa_disable(stream);
+ dev_priv->perf.oa.ops.oa_enable(stream);
/*
* Note: .oa_enable() is expected to re-init the oabuffer and
@@ -1114,8 +1114,8 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
dev_priv->perf.oa.period_exponent);
- dev_priv->perf.oa.ops.oa_disable(dev_priv);
- dev_priv->perf.oa.ops.oa_enable(dev_priv);
+ dev_priv->perf.oa.ops.oa_disable(stream);
+ dev_priv->perf.oa.ops.oa_enable(stream);
oastatus1 = I915_READ(GEN7_OASTATUS1);
}
@@ -1563,9 +1563,11 @@ static void config_oa_regs(struct drm_i915_private
*dev_priv,
}
}
-static int hsw_enable_metric_set(struct drm_i915_private *dev_priv,
-const struct i915_oa_config *oa_config)
+static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ const struct i915_oa_config *oa_config = stream->oa_config;
+
/* PRM:
*
* OA unit is using “crclk” for its functionality. When trunk
@@ -1767,9 +1769,10 @@ static int gen8_configure_all_contexts(struct
drm_i915_private *dev_priv,
return 0;
}
-static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
- const struct i915_oa_config *oa_config)
+static int gen8_enable_metric_set(struct i915_perf_stream *stream)
{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ const struct i915_oa_config *oa_config = stream->oa_config;
int ret;
/*
@@ -1837,10 +1840,10 @@ static void gen10_disable_metric_set(struct
drm_i915_private *dev_priv)
I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
}
-static void gen7_oa_enable(struct drm_i915_private *dev_priv)
+static void gen7_oa_enable(struct i915_perf_stream *stream)
{
- struct i915_gem_context *ctx =
- dev_priv->perf.oa.exclusive_stream->ctx;
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct i915_gem_context *ctx = stream->ctx;
u32 ctx_id = dev_priv->perf.oa.specific_ctx_id;
bool periodic = dev_priv->perf.oa.periodic;
u32 period_exponent = dev_priv->perf.oa.period_exponent;
@@ -1867,8 +1870,9 @@ static void gen7_oa_enable(struct drm_i915_private
*dev_priv)
GEN7_OACONTROL_ENABLE);
}
-static void gen8_oa_enable(struct drm_i915_private *dev_priv)
+static void gen8_oa_enable(struct i915_perf_stream *stream)
{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
u32 report_format = dev_priv->perf.oa.oa_buffer.format;
[Intel-gfx] [PATCH v3 0/4] drm/i915/perf: Add OA buffer size uAPI parameter
Hi all, Chris recommended we stick on what the HW can do with regard to the buffer size parameter. This is reflected in the update of patch 4. Added patch 1 which was requested for newer test config files by Lucas. I figured we could update the existing files too. Cheers, Lionel Landwerlin (4): drm/i915/perf: update generated files headers drm/i915/perf: remove redundant oa buffer initialization drm/i915/perf: pass stream to vfuncs when possible drm/i915/perf: add a parameter to control the size of OA buffer drivers/gpu/drm/i915/i915_drv.h | 25 + drivers/gpu/drm/i915/i915_oa_bdw.c| 27 + drivers/gpu/drm/i915/i915_oa_bdw.h| 27 + drivers/gpu/drm/i915/i915_oa_bxt.c| 27 + drivers/gpu/drm/i915/i915_oa_bxt.h| 27 + drivers/gpu/drm/i915/i915_oa_cflgt2.c | 27 + drivers/gpu/drm/i915/i915_oa_cflgt2.h | 27 + drivers/gpu/drm/i915/i915_oa_cflgt3.c | 27 + drivers/gpu/drm/i915/i915_oa_cflgt3.h | 27 + drivers/gpu/drm/i915/i915_oa_chv.c| 27 + drivers/gpu/drm/i915/i915_oa_chv.h| 27 + drivers/gpu/drm/i915/i915_oa_cnl.c| 27 + drivers/gpu/drm/i915/i915_oa_cnl.h| 27 + drivers/gpu/drm/i915/i915_oa_glk.c| 27 + drivers/gpu/drm/i915/i915_oa_glk.h| 27 + drivers/gpu/drm/i915/i915_oa_hsw.c| 27 + drivers/gpu/drm/i915/i915_oa_hsw.h| 27 + drivers/gpu/drm/i915/i915_oa_icl.c| 27 + drivers/gpu/drm/i915/i915_oa_icl.h| 27 + drivers/gpu/drm/i915/i915_oa_kblgt2.c | 27 + drivers/gpu/drm/i915/i915_oa_kblgt2.h | 27 + drivers/gpu/drm/i915/i915_oa_kblgt3.c | 27 + drivers/gpu/drm/i915/i915_oa_kblgt3.h | 27 + drivers/gpu/drm/i915/i915_oa_sklgt2.c | 27 + drivers/gpu/drm/i915/i915_oa_sklgt2.h | 27 + drivers/gpu/drm/i915/i915_oa_sklgt3.c | 27 + drivers/gpu/drm/i915/i915_oa_sklgt3.h | 27 + drivers/gpu/drm/i915/i915_oa_sklgt4.c | 27 + drivers/gpu/drm/i915/i915_oa_sklgt4.h | 27 + drivers/gpu/drm/i915/i915_perf.c | 141 -- drivers/gpu/drm/i915/i915_reg.h | 2 + include/uapi/drm/i915_drm.h | 7 ++ 32 files changed, 215 insertions(+), 716 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling
== Series Details ==
Series: drm/i915/icl: dsi enabling
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4981 -> Patchwork_10459 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10459 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10459, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10459:
=== IGT changes ===
Possible regressions
igt@kms_busy@basic-flip-a:
fi-icl-u2: PASS -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_10459 that come from known issues:
=== IGT changes ===
Issues hit
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) +1
Possible fixes
igt@gem_exec_suspend@basic-s3:
fi-icl-u: INCOMPLETE (fdo#107713) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@pm_rpm@module-reload:
{fi-apl-guc}: DMESG-WARN (fdo#106685) -> PASS
fi-skl-6600u: INCOMPLETE (fdo#107807) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
fdo#106685 https://bugs.freedesktop.org/show_bug.cgi?id=106685
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
== Participating hosts (54 -> 48) ==
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-snb-2520m fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4981 -> Patchwork_10459
CI_DRM_4981: 79887268bfe4128788d7cfcf38b62308346fd7f1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4677: 68ff28a022dbaa26a20c8a3c0212011a006614b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10459: 40cd071d495aebb20871cb992c8b7163d6bd89f8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
40cd071d495a drm/i915/icl: Turn ON panel backlight
f24121c2b8aa drm/i915/icl: Ensure all cmd/data disptached to panel
2ded53515fac drm/i915/icl: Wait for header/payload credits release
b4f147d6e59a drm/i915/icl: Power on DSI panel
8fbeffd78efd drm/i915/icl: Set max return packet size for DSI panel
b4e25fc83b04 drm/i915/icl: Define DSI panel programming registers
45434712c8ed drm/i915/icl: Enable DSI transcoders
2798285cb709 drm/i915/icl: Define TRANS_CONF register for DSI
f40776f438c5 drm/i915/icl: Configure DSI transcoder timings
16b3a933fd57 drm/i915/icl: Define DSI transcoder timing registers
c4b1dbebffe2 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
fa60d3c6232b drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
8fedd977c309 drm/i915/icl: Configure DSI transcoders
5dcfc9bcf556 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
f214bf74072b drm/i915/icl: Add macros for MMIO of DSI transcoder registers
0e2b629b050f drm/i915/icl: Get DSI transcoder for a given port
51bb6f5afbd6 drm/i915/icl: Program TA_TIMING_PARAM registers
1766764bfdc9 drm/i915/icl: Program DSI clock and data lane timing params
f5d8752673e3 drm/i915/icl: Make common DSI functions available
f747b1606322 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
b14852354e52 drm/i915/dsi: abstract dphy parameter init
1a879a6d5120 drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
b12abf6e31c4 drm/i915: make encoder enable and disable hooks optional
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10459/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling
== Series Details == Series: drm/i915/icl: dsi enabling URL : https://patchwork.freedesktop.org/series/51011/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: make encoder enable and disable hooks optional Okay! Commit: drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init() +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsi: abstract dphy parameter init Okay! Commit: drm/i915/dsi: abstract intel_dsi_tlpx_ns() Okay! Commit: drm/i915/icl: Make common DSI functions available Okay! Commit: drm/i915/icl: Program DSI clock and data lane timing params +drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:534:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:535:26: warning: expression using sizeof(void) Commit: drm/i915/icl: Program TA_TIMING_PARAM registers Okay! Commit: drm/i915/icl: Get DSI transcoder for a given port Okay! Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers Okay! Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Okay! Commit: drm/i915/icl: Configure DSI transcoders Okay! Commit: drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers Okay! Commit: drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers Okay! Commit: drm/i915/icl: Define DSI transcoder timing registers Okay! Commit: drm/i915/icl: Configure DSI transcoder timings Okay! Commit: drm/i915/icl: Define TRANS_CONF register for DSI Okay! Commit: drm/i915/icl: Enable DSI transcoders Okay! Commit: drm/i915/icl: Define DSI panel programming registers Okay! Commit: drm/i915/icl: Set max return packet size for DSI panel Okay! Commit: drm/i915/icl: Power on DSI panel Okay! Commit: drm/i915/icl: Wait for header/payload credits release Okay! Commit: drm/i915/icl: Ensure all cmd/data disptached to panel Okay! Commit: drm/i915/icl: Turn ON panel backlight Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling
== Series Details ==
Series: drm/i915/icl: dsi enabling
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b12abf6e31c4 drm/i915: make encoder enable and disable hooks optional
1a879a6d5120 drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#29:
new file mode 100644
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:552:
+ intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal *
intel_dsi->pixel_overlap * 60, 1000);
total: 0 errors, 2 warnings, 0 checks, 118 lines checked
b14852354e52 drm/i915/dsi: abstract dphy parameter init
-:129: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#129: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:691:
+ pixel_format_from_register_bits(
-:155: WARNING:BRACES: braces {} are not necessary for single statement blocks
#155: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:717:
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+ intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal *
intel_dsi->pixel_overlap * 60, 1000);
+ }
-:156: WARNING:LONG_LINE: line over 100 characters
#156: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:718:
+ intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal *
intel_dsi->pixel_overlap * 60, 1000);
-:164: CHECK:BRACES: braces {} should be used on all arms of this statement
#164: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:726:
+ if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
[...]
+ } else
[...]
-:173: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#173: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:735:
+ burst_mode_ratio = DIV_ROUND_UP(
-:182: CHECK:BRACES: Unbalanced braces around else statement
#182: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:744:
+ } else
total: 0 errors, 2 warnings, 4 checks, 169 lines checked
f747b1606322 drm/i915/dsi: abstract intel_dsi_tlpx_ns()
f5d8752673e3 drm/i915/icl: Make common DSI functions available
1766764bfdc9 drm/i915/icl: Program DSI clock and data lane timing params
51bb6f5afbd6 drm/i915/icl: Program TA_TIMING_PARAM registers
0e2b629b050f drm/i915/icl: Get DSI transcoder for a given port
f214bf74072b drm/i915/icl: Add macros for MMIO of DSI transcoder registers
5dcfc9bcf556 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
8fedd977c309 drm/i915/icl: Configure DSI transcoders
-:146: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#146: FILE: drivers/gpu/drm/i915/intel_dsi.h:85:
+ bool bgr_enabled;
total: 0 errors, 0 warnings, 1 checks, 121 lines checked
fa60d3c6232b drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
c4b1dbebffe2 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
16b3a933fd57 drm/i915/icl: Define DSI transcoder timing registers
f40776f438c5 drm/i915/icl: Configure DSI transcoder timings
2798285cb709 drm/i915/icl: Define TRANS_CONF register for DSI
45434712c8ed drm/i915/icl: Enable DSI transcoders
b4e25fc83b04 drm/i915/icl: Define DSI panel programming registers
8fbeffd78efd drm/i915/icl: Set max return packet size for DSI panel
b4f147d6e59a drm/i915/icl: Power on DSI panel
2ded53515fac drm/i915/icl: Wait for header/payload credits release
-:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#22: FILE: drivers/gpu/drm/i915/icl_dsi.c:31:
+static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
-:34: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#34: FILE: drivers/gpu/drm/i915/icl_dsi.c:43:
+static void __attribute__((unused)) wait_for_dsi_payload_credit_release(
total: 0 errors, 0 warnings, 2 checks, 30 lines checked
f24121c2b8aa drm/i915/icl: Ensure all cmd/data disptached to panel
40cd071d495a drm/i915/icl: Turn ON panel backlight
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gen8: Disable master intr before reading
== Series Details == Series: series starting with [1/3] drm/i915/gen8: Disable master intr before reading URL : https://patchwork.freedesktop.org/series/51009/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4981 -> Patchwork_10458 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51009/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10458 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@drv_selftest@live_hangcheck: fi-icl-u2: INCOMPLETE (fdo#108315) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@pm_rpm@module-reload: fi-skl-6600u: INCOMPLETE (fdo#107807) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 == Participating hosts (54 -> 46) == Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-gdg-551 fi-pnv-d510 == Build changes == * Linux: CI_DRM_4981 -> Patchwork_10458 CI_DRM_4981: 79887268bfe4128788d7cfcf38b62308346fd7f1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4677: 68ff28a022dbaa26a20c8a3c0212011a006614b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10458: 584e9458bfbd1176f076e88bc556c5b9dded2923 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 584e9458bfbd drm/i915/icl: Disable master intr before reading d6f38f088417 drm/i915/icl: No need to ack intr through master control 156a3aff56b5 drm/i915/gen8: Disable master intr before reading == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10458/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/edid: VSDB yCBCr420 Deep Color mode bit definitions
Regards
Shashank
On 10/15/2018 4:39 PM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI Forum VSDB YCBCR420 deep color capability bits are 2:0. Correct
definitions in the header for the mask to work correctly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107893
Signed-off-by: Clint Taylor
When posting fixes like this, please do git blame on the stuff you're
fixing, and add Fixes: tag and a bunch of Cc's. It'll help us propagate
the fix to stable kernels and get feedback from the authors and
reviewers. 'dim fixes' will help you with this:
$ dim fixes e6a9a2c3dc437
Fixes: e6a9a2c3dc43 ("drm/edid: parse ycbcr 420 deep color information")
Cc: Ville Syrjälä
Cc: Jose Abreu
Cc: Shashank Sharma
Cc: Gustavo Padovan
Cc: Maarten Lankhorst
Cc: Sean Paul
Cc: David Airlie
Cc: dri-de...@lists.freedesktop.org
Cc: # v4.14+
Anyway this looks sane to me,
Reviewed-by: Jani Nikula
but I'm wondering if there was some deeper meaning to the original |= in
there.
Honestly, I was considering new blocks in HDMI 2.1 spec for dc, and
parsing of those before this block, keeping |= required.
But we can always do other way around, or will take care of it when we
add code for it.
Just cross checked with the spec too,
Reviewed-by: Shashank Sharma
- Shashank
PS. It'll be useful to repost this Cc: intel-gfx just to get the CI as
we seem to be the only consumer of the stuff being fixed.
BR,
Jani.
---
drivers/gpu/drm/drm_edid.c | 2 +-
include/drm/drm_edid.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1e2b940..ff0bfc6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4282,7 +4282,7 @@ static void drm_parse_ycbcr420_deep_color_info(struct
drm_connector *connector,
struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
- hdmi->y420_dc_modes |= dc_mask;
+ hdmi->y420_dc_modes = dc_mask;
}
static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b25d12e..e3c4048 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -214,9 +214,9 @@ struct detailed_timing {
#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
/* YCBCR 420 deep color modes */
-#define DRM_EDID_YCBCR420_DC_48 (1 << 6)
-#define DRM_EDID_YCBCR420_DC_36 (1 << 5)
-#define DRM_EDID_YCBCR420_DC_30 (1 << 4)
+#define DRM_EDID_YCBCR420_DC_48 (1 << 2)
+#define DRM_EDID_YCBCR420_DC_36 (1 << 1)
+#define DRM_EDID_YCBCR420_DC_30 (1 << 0)
#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
DRM_EDID_YCBCR420_DC_36 | \
DRM_EDID_YCBCR420_DC_30)
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[Intel-gfx] [PATCH v7 20/23] drm/i915/icl: Power on DSI panel
From: Madhav Chauhan
This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5ede055b263e..0393fed98a6f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -659,6 +659,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
if (ret < 0)
DRM_ERROR("error setting max return pkt size%d\n", tmp);
}
+
+ /* panel power on related mipi dsi vbt sequences */
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+ intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
}
static void __attribute__((unused))
--
2.11.0
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[Intel-gfx] [PATCH v7 18/23] drm/i915/icl: Define DSI panel programming registers
From: Madhav Chauhan
This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
bitfields, masks and macros used for configuring DSI panel.
v2: Define remaining bitfields
v3 by Jani:
- Alignment fix
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 839e681bd3a4..fe6b42037ded 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10463,6 +10463,44 @@ enum skl_power_gate {
#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
#define EOTP_DISABLED (1 << 0)
+#define _DSI_CMD_RXCTL_0 0x6b0d4
+#define _DSI_CMD_RXCTL_1 0x6b8d4
+#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_RXCTL_0,\
+ _DSI_CMD_RXCTL_1)
+#define READ_UNLOADS_DW (1 << 16)
+#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
+#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
+#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
+#define RECEIVED_RESET_TRIGGER(1 << 12)
+#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
+#define RECEIVED_CRC_WAS_LOST (1 << 10)
+#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
+#define NUMBER_RX_PLOAD_DW_SHIFT 0
+
+#define _DSI_CMD_TXCTL_0 0x6b0d0
+#define _DSI_CMD_TXCTL_1 0x6b8d0
+#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXCTL_0,\
+ _DSI_CMD_TXCTL_1)
+#define KEEP_LINK_IN_HS (1 << 24)
+#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
+#define FREE_HEADER_CREDIT_SHIFT 0x8
+#define FREE_PLOAD_CREDIT_MASK(0xff << 0)
+#define FREE_PLOAD_CREDIT_SHIFT 0
+#define MAX_HEADER_CREDIT 0x10
+#define MAX_PLOAD_CREDIT 0x40
+
+#define _DSI_LP_MSG_0 0x6b0d8
+#define _DSI_LP_MSG_1 0x6b8d8
+#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
+ _DSI_LP_MSG_0,\
+ _DSI_LP_MSG_1)
+#define LPTX_IN_PROGRESS (1 << 17)
+#define LINK_IN_ULPS (1 << 16)
+#define LINK_ULPS_TYPE_LP11 (1 << 8)
+#define LINK_ENTER_ULPS (1 << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.11.0
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[Intel-gfx] [PATCH v7 21/23] drm/i915/icl: Wait for header/payload credits release
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0393fed98a6f..5fe024dfbdb0 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,6 +28,30 @@
#include
#include "intel_dsi.h"
+static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
+ struct intel_dsi *intel_dsi,
+ enum transcoder dsi_trans)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+ if (wait_for_us(((I915_READ(DSI_CMD_TXCTL(dsi_trans)) &
+ FREE_HEADER_CREDIT_MASK) >> FREE_HEADER_CREDIT_SHIFT)
+ == MAX_HEADER_CREDIT, 100))
+ DRM_ERROR("DSI header credits not released\n");
+}
+
+static void __attribute__((unused)) wait_for_dsi_payload_credit_release(
+ struct intel_dsi *intel_dsi,
+ enum transcoder dsi_trans)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+ if (wait_for_us((I915_READ(DSI_CMD_TXCTL(dsi_trans)) &
+ FREE_PLOAD_CREDIT_MASK) == MAX_PLOAD_CREDIT,
+ 100))
+ DRM_ERROR("DSI payload credits not released\n");
+}
+
static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
--
2.11.0
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[Intel-gfx] [PATCH v7 22/23] drm/i915/icl: Ensure all cmd/data disptached to panel
From: Madhav Chauhan
As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 53 ++
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5fe024dfbdb0..90188ba8a4dc 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,9 +28,8 @@
#include
#include "intel_dsi.h"
-static void __attribute__((unused)) wait_for_dsi_hdr_credit_release(
- struct intel_dsi *intel_dsi,
- enum transcoder dsi_trans)
+static void wait_for_dsi_hdr_credit_release(struct intel_dsi *intel_dsi,
+ enum transcoder dsi_trans)
{
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
@@ -40,8 +39,7 @@ static void __attribute__((unused))
wait_for_dsi_hdr_credit_release(
DRM_ERROR("DSI header credits not released\n");
}
-static void __attribute__((unused)) wait_for_dsi_payload_credit_release(
- struct intel_dsi *intel_dsi,
+static void wait_for_dsi_payload_credit_release(struct intel_dsi *intel_dsi,
enum transcoder dsi_trans)
{
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
@@ -60,6 +58,48 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
return TRANSCODER_DSI_1;
}
+static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ int ret;
+
+ /* wait for header/payload credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_dsi_hdr_credit_release(intel_dsi, dsi_trans);
+ wait_for_dsi_payload_credit_release(intel_dsi, dsi_trans);
+ }
+
+ /* send nop DCS command */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+ dsi->channel = 0;
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0)
+ DRM_ERROR("error sending DCS NOP command\n");
+ }
+
+ /* wait for header credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_dsi_hdr_credit_release(intel_dsi, dsi_trans);
+ }
+
+ /* wait for LP TX in progress bit to be cleared */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LPTX_IN_PROGRESS),
+ 20))
+ DRM_ERROR("LPTX bit not cleared\n");
+ }
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -690,6 +730,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+
+ /* ensure all panel commands dispatched before enabling transcoder */
+ wait_for_cmds_dispatched_to_panel(encoder);
}
static void __attribute__((unused))
--
2.11.0
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[Intel-gfx] [PATCH v7 23/23] drm/i915/icl: Turn ON panel backlight
From: Madhav Chauhan
This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 90188ba8a4dc..7ea6741e37ac 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -740,6 +740,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
@@ -757,4 +759,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
+
+ /* step7: enable backlight */
+ intel_panel_enable_backlight(pipe_config, conn_state);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
--
2.11.0
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[Intel-gfx] [PATCH v7 19/23] drm/i915/icl: Set max return packet size for DSI panel
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
FIXME: Looks like this is storing sw state in registers.
---
drivers/gpu/drm/i915/icl_dsi.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a1753d246..5ede055b263e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
* Jani Nikula
*/
+#include
#include "intel_dsi.h"
static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -636,6 +637,30 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder,
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+ int ret;
+
+ /* set maximum return packet size */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+ tmp &= NUMBER_RX_PLOAD_DW_MASK;
+ /* multiply "Number Rx Payload DW" by 4 to get max value */
+ tmp = tmp * 4;
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+ if (ret < 0)
+ DRM_ERROR("error setting max return pkt size%d\n", tmp);
+ }
+}
+
static void __attribute__((unused))
gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -650,6 +675,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+ /* step5: program and powerup panel */
+ gen11_dsi_powerup_panel(encoder);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
--
2.11.0
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[Intel-gfx] [PATCH v7 17/23] drm/i915/icl: Enable DSI transcoders
From: Madhav Chauhan
This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.
v2 by Jani:
- Rebase
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f6ed57b28676..216a1753d246 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -591,6 +591,28 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
}
}
+static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ tmp |= PIPECONF_ENABLE;
+ I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+ /* wait for transcoder to be enabled */
+ if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE,
+ I965_PIPECONF_ACTIVE, 10))
+ DRM_ERROR("DSI transcoder not enabled\n");
+ }
+}
+
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
@@ -630,4 +652,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
+
+ /* step6d: enable dsi transcoder */
+ gen11_dsi_enable_transcoder(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v7 16/23] drm/i915/icl: Define TRANS_CONF register for DSI
From: Madhav Chauhan
This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.
v2: Add blank line before comment
v3 by Jani:
- Move DSI specific .pipe_offsets to GEN11_FEATURES
- Macro placement and comment juggling
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_pci.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b86b735a8634..44e745921ac1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info
= {
#define GEN11_FEATURES \
GEN10_FEATURES, \
+ .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
+ PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
+ PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4270ca26a11..839e681bd3a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5652,6 +5652,10 @@ enum {
*/
#define PIPE_EDP_OFFSET0x7f000
+/* ICL DSI 0 and 1 */
+#define PIPE_DSI0_OFFSET 0x7b000
+#define PIPE_DSI1_OFFSET 0x7b800
+
#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
dev_priv->info.display_mmio_offset)
@@ -6240,6 +6244,10 @@ enum {
#define _DSPBOFFSET(dev_priv->info.display_mmio_offset + 0x711A4)
#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
+/* ICL DSI 0 and 1 */
+#define _PIPEDSI0CONF 0x7b008
+#define _PIPEDSI1CONF 0x7b808
+
/* Sprite A control */
#define _DVSACNTR 0x72180
#define DVS_ENABLE (1 << 31)
--
2.11.0
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[Intel-gfx] [PATCH v7 13/23] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
From: Madhav Chauhan
This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.
v2 by Jani:
- Use MISSING_CASE with fallthrough instead of DRM_ERROR
- minor stylistic changes
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 64 +++---
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 756c75d0c86c..87d5e6435791 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -340,10 +340,14 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
}
}
-static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+static void
+gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ enum pipe pipe = intel_crtc->pipe;
u32 tmp;
enum port port;
enum transcoder dsi_trans;
@@ -420,9 +424,61 @@ static void gen11_dsi_configure_transcoder(struct
intel_encoder *encoder)
I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
}
+
+ /* enable port sync mode if dual link */
+ if (intel_dsi->dual_link) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
+ tmp |= PORT_SYNC_MODE_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
+ }
+
+ //TODO: configure DSS_CTL1
+ }
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* select data lane width */
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ tmp &= ~DDI_PORT_WIDTH_MASK;
+ tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+
+ /* select input pipe */
+ tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
+ switch (pipe) {
+ default:
+ MISSING_CASE(pipe);
+ /* fallthrough */
+ case PIPE_A:
+ tmp |= TRANS_DDI_EDP_INPUT_A_ON;
+ break;
+ case PIPE_B:
+ tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+ break;
+ case PIPE_C:
+ tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+ break;
+ }
+
+ /* enable DDI buffer */
+ tmp |= TRANS_DDI_FUNC_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+ }
+
+ /* wait for link ready */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
+ LINK_READY), 2500))
+ DRM_ERROR("DSI link not ready\n");
+ }
}
-static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
+static void
+gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
{
/* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder);
@@ -440,7 +496,7 @@ static void gen11_dsi_enable_port_and_phy(struct
intel_encoder *encoder)
gen11_dsi_setup_dphy_timings(encoder);
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
- gen11_dsi_configure_transcoder(encoder);
+ gen11_dsi_configure_transcoder(encoder, pipe_config);
}
static void __attribute__((unused))
@@ -455,5 +511,5 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
gen11_dsi_program_esc_clk_div(encoder);
/* step4: enable DSI port and DPHY */
- gen11_dsi_enable_port_and_phy(encoder);
+ gen11_dsi_enable_port_and_phy(encoder, pipe_config);
}
--
2.11.0
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[Intel-gfx] [PATCH v7 15/23] drm/i915/icl: Configure DSI transcoder timings
From: Madhav Chauhan
As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.
v2: Remove TRANS_TIMING_SHIFT usage
v3 by Jani:
- Rebase
- Reduce temp variable use
- Checkpatch fix
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 118 +
1 file changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 87d5e6435791..f6ed57b28676 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -477,6 +477,121 @@ gen11_dsi_configure_transcoder(struct intel_encoder
*encoder,
}
static void
+gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
+const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+ enum port port;
+ enum transcoder dsi_trans;
+ /* horizontal timings */
+ u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
+ u16 hfront_porch, hback_porch;
+ /* vertical timings */
+ u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+
+ hactive = adjusted_mode->crtc_hdisplay;
+ htotal = adjusted_mode->crtc_htotal;
+ hsync_start = adjusted_mode->crtc_hsync_start;
+ hsync_end = adjusted_mode->crtc_hsync_end;
+ hsync_size = hsync_end - hsync_start;
+ hfront_porch = (adjusted_mode->crtc_hsync_start -
+ adjusted_mode->crtc_hdisplay);
+ hback_porch = (adjusted_mode->crtc_htotal -
+ adjusted_mode->crtc_hsync_end);
+ vactive = adjusted_mode->crtc_vdisplay;
+ vtotal = adjusted_mode->crtc_vtotal;
+ vsync_start = adjusted_mode->crtc_vsync_start;
+ vsync_end = adjusted_mode->crtc_vsync_end;
+ vsync_shift = hsync_start - htotal / 2;
+
+ if (intel_dsi->dual_link) {
+ hactive /= 2;
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+ hactive += intel_dsi->pixel_overlap;
+ htotal /= 2;
+ }
+
+ /* minimum hactive as per bspec: 256 pixels */
+ if (adjusted_mode->crtc_hdisplay < 256)
+ DRM_ERROR("hactive is less then 256 pixels\n");
+
+ /* if RGB666 format, then hactive must be multiple of 4 pixels */
+ if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
+ DRM_ERROR("hactive pixels are not multiple of 4\n");
+
+ /* program TRANS_HTOTAL register */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ I915_WRITE(HTOTAL(dsi_trans),
+ (hactive - 1) | ((htotal - 1) << 16));
+ }
+
+ /* TRANS_HSYNC register to be programmed only for video mode */
+ if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+ if (intel_dsi->video_mode_format ==
+ VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+ /* BSPEC: hsync size should be atleast 16 pixels */
+ if (hsync_size < 16)
+ DRM_ERROR("hsync size < 16 pixels\n");
+ }
+
+ if (hback_porch < 16)
+ DRM_ERROR("hback porch < 16 pixels\n");
+
+ if (intel_dsi->dual_link) {
+ hsync_start /= 2;
+ hsync_end /= 2;
+ }
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ I915_WRITE(HSYNC(dsi_trans),
+ (hsync_start - 1) | ((hsync_end - 1) << 16));
+ }
+ }
+
+ /* program TRANS_VTOTAL register */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ /*
+* FIXME: Programing this by assuming progressive mode, since
+* non-interlaced info from VBT is not saved inside
+* struct drm_display_mode.
+* For interlace mode: program required pixel minus 2
+*/
+ I915_WRITE(VTOTAL(dsi_trans),
+ (vactive - 1) | ((vtotal - 1) << 16));
+ }
+
+ if (vsync_end < vsync_start || vsync_end > vtotal)
+ DRM_ERROR("Invalid vsync_end value\n");
+
+ if (vsync_start < vactive)
+ DRM_ERROR("vsync_start less than vactive\n");
+
+ /* program TRANS_VSYNC register */
+
[Intel-gfx] [PATCH v7 14/23] drm/i915/icl: Define DSI transcoder timing registers
From: Madhav Chauhan
This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.
v2: Remove TRANS_TIMING_SHIFT definition
v3 by Jani:
- Group macros by transcoder
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79e633c1e9ad..c4270ca26a11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4061,6 +4061,20 @@ enum {
#define _VSYNCSHIFT_B 0x61028
#define _PIPE_MULT_B 0x6102c
+/* DSI 0 timing regs */
+#define _HTOTAL_DSI0 0x6b000
+#define _HSYNC_DSI00x6b008
+#define _VTOTAL_DSI0 0x6b00c
+#define _VSYNC_DSI00x6b014
+#define _VSYNCSHIFT_DSI0 0x6b028
+
+/* DSI 1 timing regs */
+#define _HTOTAL_DSI1 0x6b800
+#define _HSYNC_DSI10x6b808
+#define _VTOTAL_DSI1 0x6b80c
+#define _VSYNC_DSI10x6b814
+#define _VSYNCSHIFT_DSI1 0x6b828
+
#define TRANSCODER_A_OFFSET 0x6
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
--
2.11.0
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[Intel-gfx] [PATCH v7 12/23] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
From: Madhav Chauhan
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes:
- Remove redundant extra line
- Correct some of bitfield definition
v3 by Jani:
- Move DSI transcoder offsets to GEN11_FEATURES
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_pci.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a05cc7ace14..b86b735a8634 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info
= {
#define GEN11_FEATURES \
GEN10_FEATURES, \
+ .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
+ TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
+ TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b065e4ca0b45..79e633c1e9ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4066,6 +4066,8 @@ enum {
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET 0x6b000
+#define TRANSCODER_DSI1_OFFSET 0x6b800
#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
@@ -9021,6 +9023,8 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL_B 0x61400
#define _TRANS_DDI_FUNC_CTL_C 0x62400
#define _TRANS_DDI_FUNC_CTL_EDP0x6F400
+#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
+#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
#define TRANS_DDI_FUNC_ENABLE (1 << 31)
@@ -9058,6 +9062,19 @@ enum skl_power_gate {
| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
| TRANS_DDI_HDMI_SCRAMBLING)
+#define _TRANS_DDI_FUNC_CTL2_A 0x60404
+#define _TRANS_DDI_FUNC_CTL2_B 0x61404
+#define _TRANS_DDI_FUNC_CTL2_C 0x62404
+#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
+#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
+#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
+#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
+_TRANS_DDI_FUNC_CTL2_A)
+#define PORT_SYNC_MODE_ENABLE (1 << 4)
+#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
+#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
+#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT0
+
/* DisplayPort Transport Control */
#define _DP_TP_CTL_A 0x64040
#define _DP_TP_CTL_B 0x64140
--
2.11.0
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Re: [Intel-gfx] [PATCH v12 8/8] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
Regards
Shashank
On 10/15/2018 6:42 PM, Jani Nikula wrote:
On Fri, 12 Oct 2018, Ville Syrjälä wrote:
On Sat, Oct 13, 2018 at 12:02:25AM +0530, Sharma, Shashank wrote:
+void lspcon_ycbcr420_config(struct drm_connector *connector,
+ struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_info *info = &connector->display_info;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+
+ if (drm_mode_is_420_only(info, adjusted_mode) &&
+ connector->ycbcr_420_allowed) {
+ crtc_state->port_clock /= 2;
This looks bogus. We're talking about DP here so we should not be
frobbing port_clock. And since we output 4:4:4 from the port
anyway we don't even have to take 4:2:0 into consideration
when calculating port_clock.
I agree on this.
Ah, this guy is called before we even calculate port_clock.
That explains why this didn't cause any problems. So this is
just dead code here.
And looks like the port_clock adjustment in intel_hdmi_ycbcr420_config()
also dead code since the caller overwrites it there as well.
I am not sure if that's the case for Native HDMI 2.0.
In intel_hdmi_420_config we are updating the config->port_clock, which
is the same thing being updated for 8/12/16 BPC deep color too, just
after this function.
I have tested the output with HDMI 2.0 analyzer, which reported right
pixel clock (297Mhz). Now, as any of the port clock calculations do not
get information
about HDMI output type, there is no other way they will calculate the
right pixel clock (594/2) for 4:2:0 outputs. So I believe that code is
active.
It effectively does this:
1. port_clock = who knows
2. port_clock /= 2;
Here, in intel_hdmi_compute_ycbcr_config() function, we are additionally
doing this also:
clock_8bpc /= 2;
clock_10bpc /= 2;
clock_12bpc /= 2;
3. if (12bpc)
port_clock = clock_12bpc;
else if (10bpc)
port_clock = clock_10bpc;
else
port_clock = clock_8bpc;
This means effectively the selected clock is /2, so the code is not dead
(thankfully :-))
Only the port_clock/=2 part. I never claimed the rest was dead.
The whole series pushed to dinq, dismissing this last part with Ville's
approval, to get some closure here. Thanks for the patches and
review. Further patches to clean up the existing and new dead code will
be appreciated.
Thanks Jani, I will have a look at the series post merge, and send any
follow up / cleanup patches if required.
- Shashank
BR,
Jani.
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[Intel-gfx] [PATCH v7 10/23] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
From: Madhav Chauhan
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
v2: Changes (Jani N)
- Define _SHIFT and _MASK for bitfields
- Define values for fields already shifted in place
v3 by Jani:
- Fix _SHIFT fields copy-pasted from _MASK
- Indentation fixes
- Reduce S3D orientation to single macro
- Wrap a macro parameter in parens
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 436ff68b6b18..b065e4ca0b45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10379,6 +10379,51 @@ enum skl_power_gate {
#define TA_GET_MASK (0xf << 0)
#define TA_GET_SHIFT 0
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0 0x6b030
+#define _DSI_TRANS_FUNC_CONF_1 0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)_MMIO_DSI(tc, \
+ _DSI_TRANS_FUNC_CONF_0,\
+ _DSI_TRANS_FUNC_CONF_1)
+#define OP_MODE_MASK (0x3 << 28)
+#define OP_MODE_SHIFT 28
+#define CMD_MODE_NO_GATE (0x0 << 28)
+#define CMD_MODE_TE_GATE (0x1 << 28)
+#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
+#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
+#define LINK_READY(1 << 20)
+#define PIX_FMT_MASK (0x3 << 16)
+#define PIX_FMT_SHIFT 16
+#define PIX_FMT_RGB565(0x0 << 16)
+#define PIX_FMT_RGB666_PACKED (0x1 << 16)
+#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
+#define PIX_FMT_RGB888(0x3 << 16)
+#define PIX_FMT_RGB101010 (0x4 << 16)
+#define PIX_FMT_RGB121212 (0x5 << 16)
+#define PIX_FMT_COMPRESSED(0x6 << 16)
+#define BGR_TRANSMISSION (1 << 15)
+#define PIX_VIRT_CHAN(x) ((x) << 12)
+#define PIX_VIRT_CHAN_MASK(0x3 << 12)
+#define PIX_VIRT_CHAN_SHIFT 12
+#define PIX_BUF_THRESHOLD_MASK(0x3 << 10)
+#define PIX_BUF_THRESHOLD_SHIFT 10
+#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
+#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
+#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
+#define PIX_BUF_THRESHOLD_FULL(0x3 << 10)
+#define CONTINUOUS_CLK_MASK (0x3 << 8)
+#define CONTINUOUS_CLK_SHIFT 8
+#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
+#define CLK_HS_OR_LP (0x2 << 8)
+#define CLK_HS_CONTINUOUS (0x3 << 8)
+#define LINK_CALIBRATION_MASK (0x3 << 4)
+#define LINK_CALIBRATION_SHIFT4
+#define CALIBRATION_DISABLED (0x0 << 4)
+#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
+#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
+#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
+#define EOTP_DISABLED (1 << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.11.0
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[Intel-gfx] [PATCH v7 11/23] drm/i915/icl: Configure DSI transcoders
From: Madhav Chauhan
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
v3: Use newly defined bitfields.
v4 by Jani:
- Use intel_dsi_bitrate()
- Make bgr_enabled bool
- Use 0 instead of 0x0
- Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode
- Use is_vid_mode()
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 87 +++-
drivers/gpu/drm/i915/intel_dsi.h | 3 ++
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 407c3065d08d..756c75d0c86c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,7 +27,7 @@
#include "intel_dsi.h"
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum
port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
return TRANSCODER_DSI_0;
@@ -340,6 +340,88 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+ if (intel_dsi->eotp_pkt)
+ tmp &= ~EOTP_DISABLED;
+ else
+ tmp |= EOTP_DISABLED;
+
+ /* enable link calibration if freq > 1.5Gbps */
+ if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+ tmp &= ~LINK_CALIBRATION_MASK;
+ tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
+ }
+
+ /* configure continuous clock */
+ tmp &= ~CONTINUOUS_CLK_MASK;
+ if (intel_dsi->clock_stop)
+ tmp |= CLK_ENTER_LP_AFTER_DATA;
+ else
+ tmp |= CLK_HS_CONTINUOUS;
+
+ /* configure buffer threshold limit to minimum */
+ tmp &= ~PIX_BUF_THRESHOLD_MASK;
+ tmp |= PIX_BUF_THRESHOLD_1_4;
+
+ /* set virtual channel to '0' */
+ tmp &= ~PIX_VIRT_CHAN_MASK;
+ tmp |= PIX_VIRT_CHAN(0);
+
+ /* program BGR transmission */
+ if (intel_dsi->bgr_enabled)
+ tmp |= BGR_TRANSMISSION;
+
+ /* select pixel format */
+ tmp &= ~PIX_FMT_MASK;
+ switch (intel_dsi->pixel_format) {
+ default:
+ MISSING_CASE(intel_dsi->pixel_format);
+ /* fallthrough */
+ case MIPI_DSI_FMT_RGB565:
+ tmp |= PIX_FMT_RGB565;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ tmp |= PIX_FMT_RGB666_PACKED;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ tmp |= PIX_FMT_RGB666_LOOSE;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ tmp |= PIX_FMT_RGB888;
+ break;
+ }
+
+ /* program DSI operation mode */
+ if (is_vid_mode(intel_dsi)) {
+ tmp &= ~OP_MODE_MASK;
+ switch (intel_dsi->video_mode_format) {
+ default:
+ MISSING_CASE(intel_dsi->video_mode_format);
+ /* fallthrough */
+ case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
+ tmp |= VIDEO_MODE_SYNC_EVENT;
+ break;
+ case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
+ tmp |= VIDEO_MODE_SYNC_PULSE;
+ break;
+ }
+ }
+
+ I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+ }
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
{
/* step 4a: power up all lanes of the DDI used by DSI */
@@ -356,6 +438,9 @@ static void gen11_dsi_enable_port_and_phy(struct
intel_encoder *encoder)
/* setup D-PHY timings */
gen11_dsi_setup_dphy_timings(encoder);
+
+ /* Step (4h, 4i, 4j, 4k): Configure transcoder */
+ gen11_dsi_configure_transcoder(encoder)
[Intel-gfx] [PATCH v7 09/23] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
From: Madhav Chauhan
This patch adds _MMIO_DSI macros for accessing DSI
transcoder registers.
v2: Use _MMIO_TRANS() (Ville)
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e13e51fee47..436ff68b6b18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9795,6 +9795,10 @@ enum skl_power_gate {
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/* ports A and
C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
+/* Gen11 DSI */
+#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
+ dsi0, dsi1)
+
#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
--
2.11.0
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[Intel-gfx] [PATCH v7 08/23] drm/i915/icl: Get DSI transcoder for a given port
From: Madhav Chauhan
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
drivers/gpu/drm/i915/intel_display.h | 6 --
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f9df3a7fa66b..407c3065d08d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,14 @@
#include "intel_dsi.h"
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum
port port)
+{
+ if (port == PORT_A)
+ return TRANSCODER_DSI_0;
+ else
+ return TRANSCODER_DSI_1;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 9fac67e31205..54087130f67e 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -61,8 +61,10 @@ enum transcoder {
TRANSCODER_B,
TRANSCODER_C,
TRANSCODER_EDP,
- TRANSCODER_DSI_A,
- TRANSCODER_DSI_C,
+ TRANSCODER_DSI_0,
+ TRANSCODER_DSI_1,
+ TRANSCODER_DSI_A = TRANSCODER_DSI_0,/* legacy DSI */
+ TRANSCODER_DSI_C = TRANSCODER_DSI_1,/* legacy DSI */
I915_MAX_TRANSCODERS
};
--
2.11.0
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[Intel-gfx] [PATCH v7 03/23] drm/i915/dsi: abstract dphy parameter init
intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
modified due to ICL DSI. Abstract out the VLV specific dphy param
init. No functional changes. Intentionally no stylistic changes during
code movement.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 147 +++
1 file changed, 78 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 6c4cc92f5947..fdeba8386d53 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -499,13 +499,11 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
return 1;
}
-bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
+static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
- struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
- struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
u32 tlpx_ns, extra_byte_count, tlpx_ui;
u32 ui_num, ui_den;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
@@ -513,72 +511,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
u32 tclk_prepare_clkzero, ths_prepare_hszero;
u32 lp_to_hs_switch, hs_to_lp_switch;
u32 mul;
- u16 burst_mode_ratio;
- enum port port;
-
- DRM_DEBUG_KMS("\n");
-
- intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
- intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
- intel_dsi->lane_count = mipi_config->lane_cnt + 1;
- intel_dsi->pixel_format =
- pixel_format_from_register_bits(
- mipi_config->videomode_color_format << 7);
-
- intel_dsi->dual_link = mipi_config->dual_link;
- intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
- intel_dsi->operation_mode = mipi_config->is_cmd_mode;
- intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
- intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
- intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
- intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
- intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
- intel_dsi->init_count = mipi_config->master_init_timer;
- intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
- intel_dsi->video_frmt_cfg_bits =
- mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
-
- /* Starting point, adjusted depending on dual link and burst mode */
- intel_dsi->pclk = mode->clock;
-
- /* In dual link mode each port needs half of pixel clock */
- if (intel_dsi->dual_link) {
- intel_dsi->pclk /= 2;
-
- /* we can enable pixel_overlap if needed by panel. In this
-* case we need to increase the pixelclock for extra pixels
-*/
- if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
- intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal *
intel_dsi->pixel_overlap * 60, 1000);
- }
- }
-
- /* Burst Mode Ratio
-* Target ddr frequency from VBT / non burst ddr freq
-* multiply by 100 to preserve remainder
-*/
- if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
- if (mipi_config->target_burst_mode_freq) {
- u32 bitrate = intel_dsi_bitrate(intel_dsi);
-
- if (mipi_config->target_burst_mode_freq < bitrate) {
- DRM_ERROR("Burst mode freq is less than
computed\n");
- return false;
- }
-
- burst_mode_ratio = DIV_ROUND_UP(
- mipi_config->target_burst_mode_freq * 100,
- bitrate);
-
- intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk *
burst_mode_ratio, 100);
- } else {
- DRM_ERROR("Burst mode target is not set\n");
- return false;
- }
- } else
- burst_mode_ratio = 100;
-
- intel_dsi->burst_mode_ratio = burst_mode_ratio;
switch (intel_dsi->escape_clk_div) {
case 0:
@@ -738,6 +670,83 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
8);
intel_dsi->clk_hs_to_lp_count += extra_byte_count;
+}
+
+bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
[Intel-gfx] [PATCH v7 07/23] drm/i915/icl: Program TA_TIMING_PARAM registers
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
v2: Changes
- Don't use KHz() macro (Ville/Jani N)
- Use newly defined bitfields
v3 by Jani:
- Use intel_dsi_bitrate() in favor of a new field
- Remove redundant parens
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9602b6532028..f9df3a7fa66b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -309,6 +309,27 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
I915_WRITE(DSI_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
}
+
+ /*
+* If DSI link operating at or below an 800 MHz,
+* TA_SURE should be override and programmed to
+* a value '0' inside TA_PARAM_REGISTERS otherwise
+* leave all fields at HW default values.
+*/
+ if (intel_dsi_bitrate(intel_dsi) <= 80) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+ tmp &= ~TA_SURE_MASK;
+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+ I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+ /* shadow register inside display core */
+ tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+ tmp &= ~TA_SURE_MASK;
+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+ I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+ }
+ }
}
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
--
2.11.0
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[Intel-gfx] [PATCH v7 05/23] drm/i915/icl: Make common DSI functions available
From: Madhav Chauhan
This patch moves couple of legacy DSI functions to header and common DSI
files so that they can be re-used by Gen11 DSI. No functional change.
v2 by Jani:
- Move intel_dsi_msleep() to intel_dsi_vbt.c
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.h | 11 +++
drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++
drivers/gpu/drm/i915/vlv_dsi.c | 21 -
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0d911a4adfaa..d7c0c599b52d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -129,6 +129,16 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
+static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
+}
+
+static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
+}
+
/* intel_dsi.c */
int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
@@ -162,5 +172,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id);
int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
enum mipi_seq seq_id);
+void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index b0d8548f0462..5e16b4c5f531 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -481,6 +481,17 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi
*intel_dsi,
}
}
+void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+ /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
+ if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
+ return;
+
+ msleep(msec);
+}
+
int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
{
struct intel_connector *connector = intel_dsi->attached_connector;
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index dbca30460a6b..ee0cd5d0bf91 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -290,16 +290,6 @@ static void band_gap_reset(struct drm_i915_private
*dev_priv)
mutex_unlock(&dev_priv->sb_lock);
}
-static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
-{
- return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
-}
-
-static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
-{
- return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
-}
-
static bool intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -746,17 +736,6 @@ static void intel_dsi_prepare(struct intel_encoder
*intel_encoder,
const struct intel_crtc_state *pipe_config);
static void intel_dsi_unprepare(struct intel_encoder *encoder);
-static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
-{
- struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
-
- /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
- if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
- return;
-
- msleep(msec);
-}
-
/*
* Panel enable/disable sequences from the VBT spec.
*
--
2.11.0
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[Intel-gfx] [PATCH v7 02/23] drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()
Abstract bitrate calculation to a newly resurrected intel_dsi.c file
that will contain common code for VLV and ICL DSI.
No functional changes.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/intel_dsi.c | 17 +
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/intel_dsi_vbt.c | 28 ++--
4 files changed, 31 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 48cae0eae3f9..22cbf9c3bb0c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -143,6 +143,7 @@ i915-y += dvo_ch7017.o \
intel_dp_link_training.o \
intel_dp_mst.o \
intel_dp.o \
+ intel_dsi.o \
intel_dsi_dcs_backlight.o \
intel_dsi_vbt.o \
intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
new file mode 100644
index ..4daa1da94047
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+#include "intel_dsi.h"
+
+int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
+{
+ int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+ if (WARN_ON(bpp < 0))
+ bpp = 16;
+
+ return intel_dsi->pclk * bpp / intel_dsi->lane_count;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ad7c1cb32983..68f14d8f1e18 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -129,6 +129,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
+/* intel_dsi.c */
+int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
+
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index ac83d6b89ae0..6c4cc92f5947 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -506,14 +506,12 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
- u32 bpp;
- u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
+ u32 tlpx_ns, extra_byte_count, tlpx_ui;
u32 ui_num, ui_den;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
u32 ths_prepare_ns, tclk_trail_ns;
u32 tclk_prepare_clkzero, ths_prepare_hszero;
u32 lp_to_hs_switch, hs_to_lp_switch;
- u32 pclk, computed_ddr;
u32 mul;
u16 burst_mode_ratio;
enum port port;
@@ -526,7 +524,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->pixel_format =
pixel_format_from_register_bits(
mipi_config->videomode_color_format << 7);
- bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
intel_dsi->dual_link = mipi_config->dual_link;
intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
@@ -541,19 +538,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->video_frmt_cfg_bits =
mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
- pclk = mode->clock;
+ /* Starting point, adjusted depending on dual link and burst mode */
+ intel_dsi->pclk = mode->clock;
/* In dual link mode each port needs half of pixel clock */
if (intel_dsi->dual_link) {
- pclk = pclk / 2;
+ intel_dsi->pclk /= 2;
/* we can enable pixel_overlap if needed by panel. In this
* case we need to increase the pixelclock for extra pixels
*/
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
- pclk += DIV_ROUND_UP(mode->vtotal *
- intel_dsi->pixel_overlap *
- 60, 1000);
+ intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal *
intel_dsi->pixel_overlap * 60, 1000);
}
}
@@ -563,19 +559,18 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
*/
if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
if (mipi_config->target_burst_mode_freq) {
- computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
+
[Intel-gfx] [PATCH v7 00/23] drm/i915/icl: dsi enabling
The v7 is a bit misleading, but it's essentially the next version of [1], embedding my review into the commits directly. This is the first batch from me, and there's more to come. The new patches that I've added naturally need review. The patches I've changed need approval from Madhav. I think two sets of eyballs should be enough, and an additional independent review is redundant (though of course appreciated). The patches I've not changed I think can be pushed as-is, as long as the dependencies have been merged appropriately. BR, Jani. [1] 1537095223-5184-1-git-send-email-madhav.chauhan@intel.com">http://mid.mail-archive.com/1537095223-5184-1-git-send-email-madhav.chauhan@intel.com Jani Nikula (4): drm/i915: make encoder enable and disable hooks optional drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init() drm/i915/dsi: abstract dphy parameter init drm/i915/dsi: abstract intel_dsi_tlpx_ns() Madhav Chauhan (19): drm/i915/icl: Make common DSI functions available drm/i915/icl: Program DSI clock and data lane timing params drm/i915/icl: Program TA_TIMING_PARAM registers drm/i915/icl: Get DSI transcoder for a given port drm/i915/icl: Add macros for MMIO of DSI transcoder registers drm/i915/icl: Define TRANS_DSI_FUNC_CONF register drm/i915/icl: Configure DSI transcoders drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers drm/i915/icl: Define DSI transcoder timing registers drm/i915/icl: Configure DSI transcoder timings drm/i915/icl: Define TRANS_CONF register for DSI drm/i915/icl: Enable DSI transcoders drm/i915/icl: Define DSI panel programming registers drm/i915/icl: Set max return packet size for DSI panel drm/i915/icl: Power on DSI panel drm/i915/icl: Wait for header/payload credits release drm/i915/icl: Ensure all cmd/data disptached to panel drm/i915/icl: Turn ON panel backlight drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_pci.c | 6 + drivers/gpu/drm/i915/i915_reg.h | 126 ++ drivers/gpu/drm/i915/icl_dsi.c | 443 ++- drivers/gpu/drm/i915/intel_display.c | 6 +- drivers/gpu/drm/i915/intel_display.h | 6 +- drivers/gpu/drm/i915/intel_dsi.c | 30 +++ drivers/gpu/drm/i915/intel_dsi.h | 21 ++ drivers/gpu/drm/i915/intel_dsi_vbt.c | 279 +++--- drivers/gpu/drm/i915/vlv_dsi.c | 37 +-- 10 files changed, 830 insertions(+), 125 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_dsi.c -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 06/23] drm/i915/icl: Program DSI clock and data lane timing params
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
v2: Use newly defined bitfields for data and clock lane
v3 by Jani:
- Rebase on dphy abstraction
- Reduce local variables
- Remove unrelated comment changes (Ville)
- Use the same style for range checks as VLV (Ville)
- Assign, don't OR dphy_reg contents
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 18 ++
drivers/gpu/drm/i915/intel_dsi.h | 3 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 110 ++-
3 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ff5b285ca495..9602b6532028 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
tmp |= intel_dsi->init_count;
I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
}
+
+ /* Program DPHY clock lanes timings */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+ /* shadow register inside display core */
+ I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+ }
+
+ /* Program DPHY data lanes timings */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+ intel_dsi->dphy_data_lane_reg);
+
+ /* shadow register inside display core */
+ I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+ intel_dsi->dphy_data_lane_reg);
+ }
}
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index d7c0c599b52d..12b758ebefce 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
u32 port_bits;
u32 bw_timer;
u32 dphy_reg;
+
+ /* data lanes dphy timing */
+ u32 dphy_data_lane_reg;
u32 video_frmt_cfg_bits;
u16 lp_byte_clk;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 5e16b4c5f531..3035422aa0d6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -510,6 +510,111 @@ int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
return 1;
}
+#define ICL_PREPARE_CNT_MAX0x7
+#define ICL_CLK_ZERO_CNT_MAX 0xf
+#define ICL_TRAIL_CNT_MAX 0x7
+#define ICL_TCLK_PRE_CNT_MAX 0x3
+#define ICL_TCLK_POST_CNT_MAX 0x7
+#define ICL_HS_ZERO_CNT_MAX0xf
+#define ICL_EXIT_ZERO_CNT_MAX 0x7
+
+static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ u32 tlpx_ns;
+ u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+ u32 ths_prepare_ns, tclk_trail_ns;
+ u32 hs_zero_cnt;
+ u32 tclk_pre_cnt, tclk_post_cnt;
+
+ tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
+
+ tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+ ths_prepare_ns = max(mipi_config->ths_prepare,
+mipi_config->tclk_prepare);
+
+ /*
+* prepare cnt in escape clocks
+* this field represents a hexadecimal value with a precision
+* of 1.2 – i.e. the most significant bit is the integer
+* and the least significant 2 bits are fraction bits.
+* so, the field can represent a range of 0.25 to 1.75
+*/
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+ if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
+ DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
+ prepare_cnt = ICL_PREPARE_CNT_MAX;
+ }
+
+ /* clk zero count in escape clocks */
+ clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
+ ths_prepare_ns, tlpx_ns);
+ if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
+ DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
+ clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
+ }
+
+ /* trail cnt in escape clocks*/
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+ if (trail_cnt > ICL_TRAIL_CNT_MAX) {
+ DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
+ trail_cnt = ICL_TRAIL_CNT_MAX;
+ }
+
+ /* tclk pre count in
[Intel-gfx] [PATCH v7 04/23] drm/i915/dsi: abstract intel_dsi_tlpx_ns()
Will be needed in the future. No functional changes.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 13 +
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 16 +---
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4daa1da94047..a32cc1f4b384 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -15,3 +15,16 @@ int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
return intel_dsi->pclk * bpp / intel_dsi->lane_count;
}
+
+int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
+{
+ switch (intel_dsi->escape_clk_div) {
+ default:
+ case 0:
+ return 50;
+ case 1:
+ return 100;
+ case 2:
+ return 200;
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 68f14d8f1e18..0d911a4adfaa 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -131,6 +131,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
drm_encoder *encoder)
/* intel_dsi.c */
int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
+int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index fdeba8386d53..b0d8548f0462 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -512,21 +512,7 @@ static void vlv_dphy_param_init(struct intel_dsi
*intel_dsi)
u32 lp_to_hs_switch, hs_to_lp_switch;
u32 mul;
- switch (intel_dsi->escape_clk_div) {
- case 0:
- tlpx_ns = 50;
- break;
- case 1:
- tlpx_ns = 100;
- break;
-
- case 2:
- tlpx_ns = 200;
- break;
- default:
- tlpx_ns = 50;
- break;
- }
+ tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
switch (intel_dsi->lane_count) {
case 1:
--
2.11.0
___
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