Re: [Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info.
On Tue, 30 Oct 2018, Lucas De Marchi wrote: > On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote: >> On Mon, 29 Oct 2018, Rodrigo Vivi wrote: >> > +#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(2))) >> > +#define IS_DISPLAY_GEN3(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(3))) >> > +#define IS_DISPLAY_GEN4(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(4))) >> > +#define IS_DISPLAY_GEN5(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(5))) >> > +#define IS_DISPLAY_GEN6(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(6))) >> > +#define IS_DISPLAY_GEN7(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(7))) >> > +#define IS_DISPLAY_GEN8(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(8))) >> > +#define IS_DISPLAY_GEN9(dev_priv) (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(9))) >> > +#define IS_DISPLAY_GEN10(dev_priv) >> > (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(10))) >> > +#define IS_DISPLAY_GEN11(dev_priv) >> > (!!((dev_priv)->info.display_gen_mask \ >> > + & BIT(11))) >> >> I know this is the same pattern as in IS_GEN above, but shouldn't the >> compiler end up with the same result if these were simply: >> >> #define IS_DISPLAY_GEN2(dev_priv) IS_DISPLAY_GEN(dev_priv, 2, 2) > > > humn... maybe this is too magic, but it works for me and I didn't add any > additional > macro to the kernel to implement it :) > > [CI, DON'T TEST THIS] diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > [CI, DON'T TEST THIS] index 554627dc623c..02a8b51fd733 100644 > [CI, DON'T TEST THIS] --- a/drivers/gpu/drm/i915/i915_drv.h > [CI, DON'T TEST THIS] +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2385,9 +2385,15 @@ intel_info(const struct drm_i915_private *dev_priv) > GENMASK((e) - 1, (s) - 1)) > > /* Returns true if Gen is in inclusive range [Start, End] */ > -#define IS_GEN(dev_priv, s, e) \ > +#define _IS_GEN_ARG2(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e > > +#define _IS_GEN_ARG1(dev_priv, g) \ > + (!!((dev_priv)->info.gen_mask & BIT((g) - 1))) > + > +#define IS_GEN(dev_priv, ...) \ > + CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), > ##__VA_ARGS__) > + > /* > * Return true if revision is in range [since,until] inclusive. > * > > > So we could use IS_GEN(dev_priv, 2) as well as IS_GEN(dev_priv, 2, 4), which > IMO is very clear. > The same would apply for IS_DISPLAY_GEN() version. And if they generate the > same code, we could > just change the expansion to repeat the argument. I like this stuff. So I'd prefer IS_GEN(dev_priv, 2) in favor of IS_GEN2(dev_priv) throughout. As long as it doesn't increase the code size too much, but this being macro magic I don't think it should. Care to cook up a patch against current tip to make IS_GEN() take 1 or 2 args? If I read the above right, you'll get a build error for using IS_GEN(dev_priv, 1, 2, 3), is that correct? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] mm, drm/i915: mark pinned shmemfs pages as unevictable
The i915 driver uses shmemfs to allocate backing storage for gem
objects. These shmemfs pages can be pinned (increased ref count) by
shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan
wastes a lot of time scanning these pinned pages. In some extreme case,
all pages in the inactive anon lru are pinned, and only the inactive
anon lru is scanned due to inactive_ratio, the system cannot swap and
invokes the oom-killer. Mark these pinned pages as unevictable to speed
up vmscan.
Add check_move_lru_page() to move page to appropriate lru list.
This patch was inspired by Chris Wilson's change [1].
[1]: https://patchwork.kernel.org/patch/9768741/
Cc: Chris Wilson
Cc: Michal Hocko
Cc: Joonas Lahtinen
Cc: Peter Zijlstra
Cc: Andrew Morton
Cc: Dave Hansen
Signed-off-by: Kuo-Hsin Yang
---
The previous mapping_set_unevictable patch is worse on gem_syslatency
because it defers to vmscan to move these pages to the unevictable list
and the test measures latency to allocate 2MiB pages. This performance
impact can be solved by explicit moving pages to the unevictable list in
the i915 function.
Chris, can you help to run the "igt/benchmarks/gem_syslatency -t 120 -b -m"
test with this patch on your testing machine? I tried to run the test on
a Celeron N4000, 4GB Ram machine. The mean value with this patch is
similar to that with the mlock patch.
x tip-mean.txt # current stock i915
+ lock_vma-mean.txt # the old mlock patch
* mapping-mean.txt # this patch
NMinMax MedianAvg Stddev
x 60548.898 2563.653 2149.573 1999.273480.837
+ 60479.049 2119.902 1964.399 1893.226314.736
* 60455.358 3212.368 1991.308 1903.686411.448
Changes for v3:
Use check_move_lru_page instead of shmem_unlock_mapping to move pages
to appropriate lru lists.
Changes for v2:
Squashed the two patches.
Documentation/vm/unevictable-lru.rst | 4 +++-
drivers/gpu/drm/i915/i915_gem.c | 20 +++-
include/linux/swap.h | 1 +
mm/vmscan.c | 20 +---
4 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/Documentation/vm/unevictable-lru.rst
b/Documentation/vm/unevictable-lru.rst
index fdd84cb8d511..a812fb55136d 100644
--- a/Documentation/vm/unevictable-lru.rst
+++ b/Documentation/vm/unevictable-lru.rst
@@ -143,7 +143,7 @@ using a number of wrapper functions:
Query the address space, and return true if it is completely
unevictable.
-These are currently used in two places in the kernel:
+These are currently used in three places in the kernel:
(1) By ramfs to mark the address spaces of its inodes when they are created,
and this mark remains for the life of the inode.
@@ -154,6 +154,8 @@ These are currently used in two places in the kernel:
swapped out; the application must touch the pages manually if it wants to
ensure they're in memory.
+ (3) By the i915 driver to mark pinned address space until it's unpinned.
+
Detecting Unevictable Pages
---
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0c8aa57ce83b..6dc3ecef67e4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2387,6 +2387,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj,
{
struct sgt_iter sgt_iter;
struct page *page;
+ struct address_space *mapping;
__i915_gem_object_release_shmem(obj, pages, true);
@@ -2395,6 +2396,9 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj,
if (i915_gem_object_needs_bit17_swizzle(obj))
i915_gem_object_save_bit_17_swizzle(obj, pages);
+ mapping = file_inode(obj->base.filp)->i_mapping;
+ mapping_clear_unevictable(mapping);
+
for_each_sgt_page(page, sgt_iter, pages) {
if (obj->mm.dirty)
set_page_dirty(page);
@@ -2402,6 +2406,10 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj,
if (obj->mm.madv == I915_MADV_WILLNEED)
mark_page_accessed(page);
+ lock_page(page);
+ check_move_lru_page(page);
+ unlock_page(page);
+
put_page(page);
}
obj->mm.dirty = false;
@@ -2559,6 +2567,7 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
* Fail silently without starting the shrinker
*/
mapping = obj->base.filp->f_mapping;
+ mapping_set_unevictable(mapping);
noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
@@ -2630,6 +2639,10 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
}
last_pfn = page_to_pfn(page);
+ lock_page(page);
+ check_move_lru_page(page);
+ u
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Revert "Disable read-only support under GVT"
Quoting Zhenyu Wang (2018-10-31 05:17:48) > On 2018.10.30 15:08:01 +0800, intel-gfx-boun...@lists.freedesktop.org wrote: > > From: Hang Yuan > > > > This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd. > > > > Checked GVT codes that guest PPGTT PTE flag bits are propagated > > to shadow PTE. Read/write bit is not changed. Further tested by > > i915 self-test case "igt_ctx_readonly". No error or GPU hang was > > detected. So enable read-only support under GVT. > > > > Signed-off-by: Hang Yuan > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-- > > 1 file changed, 2 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 19b2d99..bdf9f9f 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -1602,12 +1602,8 @@ static struct i915_hw_ppgtt > > *gen8_ppgtt_create(struct drm_i915_private *i915) > > 1ULL << 48 : > > 1ULL << 32; > > > > - /* > > - * From bdw, there is support for read-only pages in the PPGTT. > > - * > > - * XXX GVT is not honouring the lack of RW in the PTE bits. > > - */ > > - ppgtt->vm.has_read_only = !intel_vgpu_active(i915); > > + /* From bdw, there is support for read-only pages in the PPGTT. */ > > + ppgtt->vm.has_read_only = true; > > > > i915_address_space_init(&ppgtt->vm, i915); > > > > In consider we have that shadow logic from initial of gvt support, > this is ok. > > Acked-by: Zhenyu Wang Thanks for the patch and confirmation, pushed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info.
On 31/10/2018 08:13, Jani Nikula wrote: On Tue, 30 Oct 2018, Lucas De Marchi wrote: On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote: On Mon, 29 Oct 2018, Rodrigo Vivi wrote: +#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(2))) +#define IS_DISPLAY_GEN3(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(3))) +#define IS_DISPLAY_GEN4(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(4))) +#define IS_DISPLAY_GEN5(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(5))) +#define IS_DISPLAY_GEN6(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(6))) +#define IS_DISPLAY_GEN7(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(7))) +#define IS_DISPLAY_GEN8(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(8))) +#define IS_DISPLAY_GEN9(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(9))) +#define IS_DISPLAY_GEN10(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(10))) +#define IS_DISPLAY_GEN11(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(11))) I know this is the same pattern as in IS_GEN above, but shouldn't the compiler end up with the same result if these were simply: #define IS_DISPLAY_GEN2(dev_priv) IS_DISPLAY_GEN(dev_priv, 2, 2) humn... maybe this is too magic, but it works for me and I didn't add any additional macro to the kernel to implement it :) [CI, DON'T TEST THIS] diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h [CI, DON'T TEST THIS] index 554627dc623c..02a8b51fd733 100644 [CI, DON'T TEST THIS] --- a/drivers/gpu/drm/i915/i915_drv.h [CI, DON'T TEST THIS] +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2385,9 +2385,15 @@ intel_info(const struct drm_i915_private *dev_priv) GENMASK((e) - 1, (s) - 1)) /* Returns true if Gen is in inclusive range [Start, End] */ -#define IS_GEN(dev_priv, s, e) \ +#define _IS_GEN_ARG2(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e +#define _IS_GEN_ARG1(dev_priv, g) \ + (!!((dev_priv)->info.gen_mask & BIT((g) - 1))) + +#define IS_GEN(dev_priv, ...) \ + CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), ##__VA_ARGS__) + /* * Return true if revision is in range [since,until] inclusive. * So we could use IS_GEN(dev_priv, 2) as well as IS_GEN(dev_priv, 2, 4), which IMO is very clear. The same would apply for IS_DISPLAY_GEN() version. And if they generate the same code, we could just change the expansion to repeat the argument. I like this stuff. So I'd prefer IS_GEN(dev_priv, 2) in favor of IS_GEN2(dev_priv) throughout. As long as it doesn't increase the code size too much, but this being macro magic I don't think it should. Care to cook up a patch against current tip to make IS_GEN() take 1 or 2 args? If I read the above right, you'll get a build error for using IS_GEN(dev_priv, 1, 2, 3), is that correct? I saw some mention somewhere on IS_GEN_RANGE, which looked clearer than IS_GEN(dev_priv, s, e). Presumably that did not go anywhere since now the proposal is the above? I have to say I am not sure it reads completely intuitive when seen near in code: IS_GEN(dev_priv, 9) IS_GEN(dev_priv, 8, 9) Looks like a variable arg list and the difference in semantics does not come through. As such I am leaning towards thinking it is too much churn for unclear benefit. Or in other words I thought IS_GEN_RANGE was a better direction. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest: test aligned offsets for 64K
Quoting Patchwork (2018-10-29 23:07:25) > == Series Details == > > Series: drm/i915/selftest: test aligned offsets for 64K > URL : https://patchwork.freedesktop.org/series/51707/ > State : success > > == Summary == > > = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10636 = > > == Summary - SUCCESS == > > No regressions found. I've picked this up for pushing shortly. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info.
On Wed, 31 Oct 2018, Tvrtko Ursulin wrote: > I saw some mention somewhere on IS_GEN_RANGE, which looked clearer than > IS_GEN(dev_priv, s, e). Presumably that did not go anywhere since now > the proposal is the above? I have to say I am not sure it reads > completely intuitive when seen near in code: > > IS_GEN(dev_priv, 9) > IS_GEN(dev_priv, 8, 9) > > Looks like a variable arg list and the difference in semantics does not > come through. As such I am leaning towards thinking it is too much churn > for unclear benefit. Or in other words I thought IS_GEN_RANGE was a > better direction. Okay, thanks for the feedback. I'm not locked into any resolution yet, apart from not churning anything until we have a better picture where we're going. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] RFT drm/i915/execlists: Flush memory before signaling ELSQ
We observe that the ordering of writes for a CS event is not as strong
from the GPU as we would like, and that on occasions we see the
ringbuffer tail updated before the event is written into the ringbuffer,
leading us to reuse the stale data.
Through around a big hammer to try and batter ELSQ into submission with
the presumption that perhaps the UC mmio write is not flushing our
writes into the context images.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..ba61849fbb9b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,8 +454,10 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
}
/* we need to manually load the submit queue */
- if (execlists->ctrl_reg)
+ if (execlists->ctrl_reg) {
+ wmb(); /* XXX Big hammer or paper? XXX */
writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+ }
execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
}
--
2.19.1
___
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[Intel-gfx] [PATCH 16/20] drm/i915: Mark up Ironlake ips with rpm wakerefs
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As this involved adding a potentially sleeping rpm_get, we have to
rearrange the spinlocks slightly and so switch to acquiring a device-ref
under the spinlock rather than hold the spinlock for the whole
operation. To be consistent, we make the change in pattern common to the
intel_ips interface even though this adds a few more atomic operations
than necessary in a few cases.
v2: Sagar noted the mb around setting mch_dev were overkill as we only
need ordering there, and that i915_emon_status was still using
struct_mutex for no reason, but lacked rpm.
Signed-off-by: Chris Wilson
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 29 +++--
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/intel_pm.c | 172 ++--
3 files changed, 103 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0b9b70caa98e..e2330ff46fa5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1757,27 +1757,24 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
static int i915_emon_status(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = &dev_priv->drm;
- unsigned long temp, chipset, gfx;
- int ret;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ intel_wakeref_t wakeref;
- if (!IS_GEN5(dev_priv))
+ if (!IS_GEN5(i915))
return -ENODEV;
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- return ret;
+ with_intel_runtime_pm(i915, wakeref) {
+ unsigned long temp, chipset, gfx;
- temp = i915_mch_val(dev_priv);
- chipset = i915_chipset_val(dev_priv);
- gfx = i915_gfx_val(dev_priv);
- mutex_unlock(&dev->struct_mutex);
+ temp = i915_mch_val(i915);
+ chipset = i915_chipset_val(i915);
+ gfx = i915_gfx_val(i915);
- seq_printf(m, "GMCH temp: %ld\n", temp);
- seq_printf(m, "Chipset power: %ld\n", chipset);
- seq_printf(m, "GFX power: %ld\n", gfx);
- seq_printf(m, "Total power: %ld\n", chipset + gfx);
+ seq_printf(m, "GMCH temp: %ld\n", temp);
+ seq_printf(m, "Chipset power: %ld\n", chipset);
+ seq_printf(m, "GFX power: %ld\n", gfx);
+ seq_printf(m, "Total power: %ld\n", chipset + gfx);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6df349cd56f9..1dd875559aee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1763,6 +1763,9 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
+ /* Flush any external code that still may be under the RCU lock */
+ synchronize_rcu();
+
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 233c161fc515..b95eed1c82dc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6283,10 +6283,6 @@ void intel_init_ipc(struct drm_i915_private *dev_priv)
*/
DEFINE_SPINLOCK(mchdev_lock);
-/* Global for IPS driver to get at the current i915 device. Protected by
- * mchdev_lock. */
-static struct drm_i915_private *i915_mch_dev;
-
bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
{
u16 rgvswctl;
@@ -7929,16 +7925,17 @@ static unsigned long __i915_chipset_val(struct
drm_i915_private *dev_priv)
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
- unsigned long val;
+ intel_wakeref_t wakeref;
+ unsigned long val = 0;
if (!IS_GEN5(dev_priv))
return 0;
- spin_lock_irq(&mchdev_lock);
-
- val = __i915_chipset_val(dev_priv);
-
- spin_unlock_irq(&mchdev_lock);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ spin_lock_irq(&mchdev_lock);
+ val = __i915_chipset_val(dev_priv);
+ spin_unlock_irq(&mchdev_lock);
+ }
return val;
}
@@ -8015,14 +8012,16 @@ static void __i915_update_gfx_val(struct
drm_i915_private *dev_priv)
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
+ intel_wakeref_t wakeref;
+
if (!IS_GEN5(dev_priv))
return;
- spin_lock_irq(&mchdev_lock);
-
- __i915_update_gfx_val(dev_priv);
-
- spin_unlock_irq(&mchdev_lock);
+ with_intel_runtime_pm(dev_priv, w
[Intel-gfx] [PATCH 20/20] drm/i915: Make all GPU resets atomic
In preparation for the next few commits, make resetting the GPU atomic.
Currently, we have prepared gen6+ for atomic resetting of individual
engines, but now there is a requirement to perform the whole device
level reset (just the register poking) from inside an atomic context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 50 +--
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 78801c59ea31..f8196f13643d 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -144,14 +144,14 @@ static int i915_do_reset(struct drm_i915_private *i915,
/* Assert reset for at least 20 usec, and wait for acknowledgement. */
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- usleep_range(50, 200);
- err = wait_for(i915_in_reset(pdev), 500);
+ udelay(50);
+ err = wait_for_atomic(i915_in_reset(pdev), 50);
/* Clear the reset request. */
pci_write_config_byte(pdev, I915_GDRST, 0);
- usleep_range(50, 200);
+ udelay(50);
if (!err)
- err = wait_for(!i915_in_reset(pdev), 500);
+ err = wait_for_atomic(!i915_in_reset(pdev), 50);
return err;
}
@@ -171,7 +171,7 @@ static int g33_do_reset(struct drm_i915_private *i915,
struct pci_dev *pdev = i915->drm.pdev;
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- return wait_for(g4x_reset_complete(pdev), 500);
+ return wait_for_atomic(g4x_reset_complete(pdev), 50);
}
static int g4x_do_reset(struct drm_i915_private *dev_priv,
@@ -182,13 +182,13 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
int ret;
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
@@ -196,7 +196,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
@@ -205,9 +205,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
out:
pci_write_config_byte(pdev, I915_GDRST, 0);
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
return ret;
}
@@ -218,27 +218,29 @@ static int ironlake_do_reset(struct drm_i915_private
*dev_priv,
{
int ret;
- I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
- I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
}
out:
- I915_WRITE(ILK_GDSR, 0);
- POSTING_READ(ILK_GDSR);
+ I915_WRITE_FW(ILK_GDSR, 0);
+ POS
[Intel-gfx] [PATCH 01/20] RFT drm/i915/execlists: Flush memory before signaling ELSQ
We observe that the ordering of writes for a CS event is not as strong
from the GPU as we would like, and that on occasions we see the
ringbuffer tail updated before the event is written into the ringbuffer,
leading us to reuse the stale data.
Through around a big hammer to try and batter ELSQ into submission with
the presumption that perhaps the UC mmio write is not flushing our
writes into the context images.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..ba61849fbb9b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,8 +454,10 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
}
/* we need to manually load the submit queue */
- if (execlists->ctrl_reg)
+ if (execlists->ctrl_reg) {
+ wmb(); /* XXX Big hammer or paper? XXX */
writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+ }
execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
}
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/20] drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start
Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
notifiers") we have been able to report failure from
mmu_invalidate_range_start which allows us to use a trylock on the
struct_mutex to avoid potential recursion and report -EBUSY instead.
Furthermore, this allows us to pull the work into the main callback and
avoid the sleight-of-hand in using a workqueue to avoid lockdep.
However, not all paths to mmu_invalidate_range_start are prepared to
handle failure, so instead of reporting the recursion, deal with it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108375
References: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
notifiers")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 18 +-
drivers/gpu/drm/i915/i915_gem_object.h | 7 +
drivers/gpu/drm/i915/i915_gem_userptr.c | 217 +++-
4 files changed, 120 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9e5bab6861b..96d7a08e6e68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3068,8 +3068,8 @@ enum i915_mm_subclass { /* lockdep subclass for
obj->mm.lock */
I915_MM_SHRINKER
};
-void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
-enum i915_mm_subclass subclass);
+int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
+ enum i915_mm_subclass subclass);
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
enum i915_map_type {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 93d09282710d..9a8af9454a53 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2429,8 +2429,8 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
struct sg_table *pages;
pages = fetch_and_zero(&obj->mm.pages);
- if (!pages)
- return NULL;
+ if (IS_ERR_OR_NULL(pages))
+ return pages;
spin_lock(&i915->mm.obj_lock);
list_del(&obj->mm.link);
@@ -2454,17 +2454,16 @@ __i915_gem_object_unset_pages(struct
drm_i915_gem_object *obj)
return pages;
}
-void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
-enum i915_mm_subclass subclass)
+int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
+ enum i915_mm_subclass subclass)
{
struct sg_table *pages;
+ int ret = -EBUSY;
if (i915_gem_object_has_pinned_pages(obj))
- return;
+ return -EBUSY;
GEM_BUG_ON(obj->bind_count);
- if (!i915_gem_object_has_pages(obj))
- return;
/* May be called by shrinker from within get_pages() (on another bo) */
mutex_lock_nested(&obj->mm.lock, subclass);
@@ -2477,11 +2476,16 @@ void __i915_gem_object_put_pages(struct
drm_i915_gem_object *obj,
* lists early.
*/
pages = __i915_gem_object_unset_pages(obj);
+ if (!pages && !i915_gem_object_needs_async_cancel(obj))
+ pages = ERR_PTR(-EINVAL);
if (!IS_ERR(pages))
obj->ops->put_pages(obj, pages);
+ ret = 0;
unlock:
mutex_unlock(&obj->mm.lock);
+
+ return ret;
}
bool i915_sg_trim(struct sg_table *orig_st)
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index a6dd7c46de0d..49ce797173b5 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -56,6 +56,7 @@ struct drm_i915_gem_object_ops {
#define I915_GEM_OBJECT_HAS_STRUCT_PAGEBIT(0)
#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
#define I915_GEM_OBJECT_IS_PROXY BIT(2)
+#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
@@ -386,6 +387,12 @@ i915_gem_object_is_proxy(const struct drm_i915_gem_object
*obj)
return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
}
+static inline bool
+i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
+{
+ return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
+}
+
static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 2c9b284036d1..ab5ae426e27b 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -50,79 +50,84 @@ struct i915_mmu_notifier {
struct hlist_node node;
struct mmu_notifier mn;
struct rb_root_cached objects;
- struct workqueue_struct *wq;
+ struct i915_mm_struct *mm;
};
struct i915_mmu_o
[Intel-gfx] [PATCH 14/20] drm/i915/dp: Markup pps lock power well
Track where and when we acquire and release the power well for pps
access along the dp aux link, with a view to detecting if we leak any
wakerefs.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_dp.c | 226 +---
1 file changed, 118 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4c4b414d3813..346344fc2074 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -682,28 +682,36 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
static void
intel_dp_pps_init(struct intel_dp *intel_dp);
-static void pps_lock(struct intel_dp *intel_dp)
+static intel_wakeref_t
+pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
/*
* See intel_power_sequencer_reset() why we need
* a power domain reference here.
*/
- intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
-
+ wakeref = intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
mutex_lock(&dev_priv->pps_mutex);
+
+ return wakeref;
}
-static void pps_unlock(struct intel_dp *intel_dp)
+static intel_wakeref_t
+pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
mutex_unlock(&dev_priv->pps_mutex);
+ intel_display_power_put(dev_priv, intel_dp->aux_power_domain, wakeref);
- intel_display_power_put_unchecked(dev_priv, intel_dp->aux_power_domain);
+ return 0;
}
+#define with_pps_lock(dp, wf) \
+ for (wf = pps_lock(dp); wf; wf = pps_unlock(dp, wf))
+
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
@@ -1052,30 +1060,30 @@ static int edp_notify_handler(struct notifier_block
*this, unsigned long code,
struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
edp_notifier);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
return 0;
- pps_lock(intel_dp);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
- i915_reg_t pp_ctrl_reg, pp_div_reg;
- u32 pp_div;
-
- pp_ctrl_reg = PP_CONTROL(pipe);
- pp_div_reg = PP_DIVISOR(pipe);
- pp_div = I915_READ(pp_div_reg);
- pp_div &= PP_REFERENCE_DIVIDER_MASK;
-
- /* 0x1F write to PP_DIV_REG sets max cycle delay */
- I915_WRITE(pp_div_reg, pp_div | 0x1F);
- I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- msleep(intel_dp->panel_power_cycle_delay);
+ with_pps_lock(intel_dp, wakeref) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+ i915_reg_t pp_ctrl_reg, pp_div_reg;
+ u32 pp_div;
+
+ pp_ctrl_reg = PP_CONTROL(pipe);
+ pp_div_reg = PP_DIVISOR(pipe);
+ pp_div = I915_READ(pp_div_reg);
+ pp_div &= PP_REFERENCE_DIVIDER_MASK;
+
+ /* 0x1F write to PP_DIV_REG sets max cycle delay */
+ I915_WRITE(pp_div_reg, pp_div | 0x1F);
+ I915_WRITE(pp_ctrl_reg,
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ msleep(intel_dp->panel_power_cycle_delay);
+ }
}
- pps_unlock(intel_dp);
-
return 0;
}
@@ -1261,16 +1269,17 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
to_i915(intel_dig_port->base.base.dev);
i915_reg_t ch_ctl, ch_data[5];
uint32_t aux_clock_divider;
+ intel_wakeref_t wakeref;
int i, ret, recv_bytes;
- uint32_t status;
int try, clock = 0;
+ uint32_t status;
bool vdd;
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
for (i = 0; i < ARRAY_SIZE(ch_data); i++)
ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
- pps_lock(intel_dp);
+ wakeref = pps_lock(intel_dp);
/*
* We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1414,7 +1423,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
- pps_unlock(intel_dp);
+ pps_unlock(intel_dp, wakeref);
return ret;
}
@@ -2433,15 +2442,15 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
*/
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
+ intel_wa
[Intel-gfx] [PATCH 11/20] drm/i915: Markup paired operations on display power domains
The majority of runtime-pm operations are bounded and scoped within a
function; these are easy to verify that the wakeref are handled
correctly. We can employ the compiler to help us, and reduce the number
of wakerefs tracked when debugging, by passing around cookies provided
by the various rpm_get functions to their rpm_put counterpart. This
makes the pairing explicit, and given the required wakeref cookie the
compiler can verify that we pass an initialised value to the rpm_put
(quite handy for double checking error paths).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 35 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/intel_audio.c | 3 +-
drivers/gpu/drm/i915/intel_cdclk.c | 10 ++--
drivers/gpu/drm/i915/intel_crt.c| 25 +
drivers/gpu/drm/i915/intel_csr.c| 25 +++--
drivers/gpu/drm/i915/intel_ddi.c| 36 -
drivers/gpu/drm/i915/intel_display.c| 68 ++-
drivers/gpu/drm/i915/intel_dp.c | 32 ++-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 66 +++
drivers/gpu/drm/i915/intel_drv.h| 17 --
drivers/gpu/drm/i915/intel_hdmi.c | 18 ---
drivers/gpu/drm/i915/intel_i2c.c| 20 +++
drivers/gpu/drm/i915/intel_lvds.c | 8 +--
drivers/gpu/drm/i915/intel_pipe_crc.c | 6 ++-
drivers/gpu/drm/i915/intel_pm.c | 7 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 71 -
drivers/gpu/drm/i915/intel_sprite.c | 24 ++---
drivers/gpu/drm/i915/vlv_dsi.c | 8 +--
20 files changed, 314 insertions(+), 171 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b95aa2bef8c8..925f73085d4f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -626,10 +626,12 @@ static void gen8_display_interrupt_info(struct seq_file
*m)
for_each_pipe(dev_priv, pipe) {
enum intel_display_power_domain power_domain;
+ intel_wakeref_t wakeref;
power_domain = POWER_DOMAIN_PIPE(pipe);
- if (!intel_display_power_get_if_enabled(dev_priv,
- power_domain)) {
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+power_domain);
+ if (!wakeref) {
seq_printf(m, "Pipe %c power disabled\n",
pipe_name(pipe));
continue;
@@ -644,7 +646,7 @@ static void gen8_display_interrupt_info(struct seq_file *m)
pipe_name(pipe),
I915_READ(GEN8_DE_PIPE_IER(pipe)));
- intel_display_power_put(dev_priv, power_domain);
+ intel_display_power_put(dev_priv, power_domain, wakeref);
}
seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
@@ -680,6 +682,8 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
wakeref = intel_runtime_pm_get(dev_priv);
if (IS_CHERRYVIEW(dev_priv)) {
+ intel_wakeref_t pref;
+
seq_printf(m, "Master Interrupt Control:\t%08x\n",
I915_READ(GEN8_MASTER_IRQ));
@@ -695,8 +699,9 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
enum intel_display_power_domain power_domain;
power_domain = POWER_DOMAIN_PIPE(pipe);
- if (!intel_display_power_get_if_enabled(dev_priv,
- power_domain)) {
+ pref = intel_display_power_get_if_enabled(dev_priv,
+ power_domain);
+ if (!pref) {
seq_printf(m, "Pipe %c power disabled\n",
pipe_name(pipe));
continue;
@@ -706,17 +711,17 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
pipe_name(pipe),
I915_READ(PIPESTAT(pipe)));
- intel_display_power_put(dev_priv, power_domain);
+ intel_display_power_put(dev_priv, power_domain, pref);
}
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
seq_printf(m, "Port hotplug:\t%08x\n",
I915_READ(PORT_HOTPLUG_EN));
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
I915_READ(VLV_DPFLIPSTAT));
seq_printf(m, "DPINVGTT:\t%08x\n",
[Intel-gfx] [PATCH 06/20] drm/i915: Report the number of closed vma held by each context in debugfs
Include the total size of closed vma when reporting the per_ctx_stats of
debugfs/i915_gem_objects.
Whilst adjusting the context tracking, note that we can simply use our
list of contexts in i915->contexts rather than circumlocute via
dev->filelist and the per-file context idr, with the result that we can
show objects allocated to different vm (i.e. contexts within a file).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 124 +++-
1 file changed, 47 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 17616458eb70..62a716d03a69 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -297,11 +297,12 @@ static int i915_gem_stolen_list_info(struct seq_file *m,
void *data)
}
struct file_stats {
- struct drm_i915_file_private *file_priv;
+ struct i915_address_space *vm;
unsigned long count;
u64 total, unbound;
u64 global, shared;
u64 active, inactive;
+ u64 closed;
};
static int per_file_stats(int id, void *ptr, void *data)
@@ -326,9 +327,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (i915_vma_is_ggtt(vma)) {
stats->global += vma->node.size;
} else {
- struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
-
- if (ppgtt->vm.file != stats->file_priv)
+ if (vma->vm != stats->vm)
continue;
}
@@ -336,6 +335,9 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->active += vma->node.size;
else
stats->inactive += vma->node.size;
+
+ if (i915_vma_is_closed(vma))
+ stats->closed += vma->node.size;
}
return 0;
@@ -343,7 +345,7 @@ static int per_file_stats(int id, void *ptr, void *data)
#define print_file_stats(m, name, stats) do { \
if (stats.count) \
- seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound)\n", \
+ seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \
name, \
stats.count, \
stats.total, \
@@ -351,20 +353,19 @@ static int per_file_stats(int id, void *ptr, void *data)
stats.inactive, \
stats.global, \
stats.shared, \
- stats.unbound); \
+ stats.unbound, \
+ stats.closed); \
} while (0)
static void print_batch_pool_stats(struct seq_file *m,
struct drm_i915_private *dev_priv)
{
struct drm_i915_gem_object *obj;
- struct file_stats stats;
struct intel_engine_cs *engine;
+ struct file_stats stats = {};
enum intel_engine_id id;
int j;
- memset(&stats, 0, sizeof(stats));
-
for_each_engine(engine, dev_priv, id) {
for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++)
{
list_for_each_entry(obj,
@@ -377,44 +378,47 @@ static void print_batch_pool_stats(struct seq_file *m,
print_file_stats(m, "[k]batch pool", stats);
}
-static int per_file_ctx_stats(int idx, void *ptr, void *data)
+static void print_context_stats(struct seq_file *m,
+ struct drm_i915_private *i915)
{
- struct i915_gem_context *ctx = ptr;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
+ struct file_stats kstats = {};
+ struct i915_gem_context *ctx;
- for_each_engine(engine, ctx->i915, id) {
- struct intel_context *ce = to_intel_context(ctx, engine);
+ list_for_each_entry(ctx, &i915->contexts.list, link) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
- if (ce->state)
- per_file_stats(0, ce->state->obj, data);
- if (ce->ring)
- per_file_stats(0, ce->ring->vma->obj, data);
- }
+ for_each_engine(engine, i915, id) {
+ struct intel_context *ce = to_intel_context(ctx,
engine);
- return 0;
-}
+ if (ce->state)
+ per_file_stats(0, ce->state->obj, &kstats);
+ if (ce->ring)
+ per_file_stats(0, ce->ring->vma->obj, &kstats);
+ }
-static void print_context_stats(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = &dev
[Intel-gfx] [PATCH 04/20] drm/i915: Always try to reset the GPU on takeover
When we first introduced the reset to sanitize the GPU on taking over
from the BIOS and before returning control to third parties (the BIOS!),
we restricted it to only systems utilizing HW contexts as we were
uncertain of how stable our reset mechanism truly was. We now have
reasonable coverage across all machines that expose a GPU reset method,
and so we should be safe to sanitize the GPU state everywhere.
v2: We _have_ to skip the reset if it would clobber the display.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 11 ++-
drivers/gpu/drm/i915/i915_pci.c | 5 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_engine_cs.c| 14 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +-
8 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 198d625f2871..fea3d471fa4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2163,7 +2163,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
- intel_engines_sanitize(dev_priv);
+ intel_engines_sanitize(dev_priv, true);
enable_rpm_wakeref_asserts(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9a8af9454a53..8ea253dcfcf2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3437,8 +3437,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
- if (!intel_gpu_reset(i915, ALL_ENGINES))
- intel_engines_sanitize(i915);
+ intel_engines_sanitize(i915, false);
/*
* Undo nop_submit_request. We prevent all new i915 requests from
@@ -5030,8 +5029,6 @@ void __i915_gem_object_release_unless_active(struct
drm_i915_gem_object *obj)
void i915_gem_sanitize(struct drm_i915_private *i915)
{
- int err;
-
GEM_TRACE("\n");
mutex_lock(&i915->drm.struct_mutex);
@@ -5056,11 +5053,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
* it may impact the display and we are uncertain about the stability
* of the reset, so this could be applied to even earlier gen.
*/
- err = -ENODEV;
- if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
- err = WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
- if (!err)
- intel_engines_sanitize(i915);
+ intel_engines_sanitize(i915, false);
intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
intel_runtime_pm_put(i915);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..e43449efbb31 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -69,6 +69,7 @@
GEN(2), \
.num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
+ .gpu_reset_clobbers_display = true, \
.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
@@ -109,6 +110,7 @@ static const struct intel_device_info intel_i865g_info = {
GEN(3), \
.num_pipes = 2, \
.has_gmch_display = 1, \
+ .gpu_reset_clobbers_display = true, \
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -179,6 +181,7 @@ static const struct intel_device_info intel_pineview_info =
{
.num_pipes = 2, \
.has_hotplug = 1, \
.has_gmch_display = 1, \
+ .gpu_reset_clobbers_display = true, \
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -208,6 +211,7 @@ static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
.ring_mask = RENDER_RING | BSD_RING,
+ .gpu_reset_clobbers_display = false,
};
static const struct intel_device_info intel_gm45_info = {
@@ -216,6 +220,7 @@ static const struct intel_device_info intel_gm45_info = {
.is_mobile = 1, .has_fbc = 1,
.supports_tv = 1,
.ring_mask = RENDER_RING | BSD_RING,
+ .gpu_reset_clobbers_display = false,
};
#define GEN5_FEATURES \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4eae78b..d49c7e8613d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -92,6 +92,7 @@ enum intel_ppgtt {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_fbc); \
func(has_
[Intel-gfx] [PATCH 10/20] drm/i915: Syntatic sugar for using intel_runtime_pm
Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 167 --
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 44 ++---
drivers/gpu/drm/i915/i915_pmu.c | 7 +-
drivers/gpu/drm/i915/i915_sysfs.c | 7 +-
drivers/gpu/drm/i915/intel_drv.h | 8 +
drivers/gpu/drm/i915/intel_guc_log.c | 26 ++-
drivers/gpu/drm/i915/intel_huc.c | 7 +-
drivers/gpu/drm/i915/intel_panel.c| 18 +-
drivers/gpu/drm/i915/intel_uncore.c | 30 ++--
drivers/gpu/drm/i915/selftests/i915_gem.c | 34 ++--
.../gpu/drm/i915/selftests/i915_gem_context.c | 12 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 11 +-
.../drm/i915/selftests/intel_workarounds.c| 12 +-
15 files changed, 194 insertions(+), 222 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4bca4a41a545..b95aa2bef8c8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -951,9 +951,9 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
struct i915_gpu_state *gpu;
intel_wakeref_t wakeref;
- wakeref = intel_runtime_pm_get(i915);
- gpu = i915_capture_gpu_state(i915);
- intel_runtime_pm_put(i915, wakeref);
+ gpu = NULL;
+ with_intel_runtime_pm(i915, wakeref)
+ gpu = i915_capture_gpu_state(i915);
if (!gpu)
return -ENOMEM;
@@ -1014,9 +1014,8 @@ i915_next_seqno_set(void *data, u64 val)
if (ret)
return ret;
- wakeref = intel_runtime_pm_get(dev_priv);
- ret = i915_gem_set_global_seqno(dev, val);
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref)
+ ret = i915_gem_set_global_seqno(dev, val);
mutex_unlock(&dev->struct_mutex);
@@ -1304,17 +1303,15 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
return 0;
}
- wakeref = intel_runtime_pm_get(dev_priv);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ for_each_engine(engine, dev_priv, id) {
+ acthd[id] = intel_engine_get_active_head(engine);
+ seqno[id] = intel_engine_get_seqno(engine);
+ }
- for_each_engine(engine, dev_priv, id) {
- acthd[id] = intel_engine_get_active_head(engine);
- seqno[id] = intel_engine_get_seqno(engine);
+ intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
}
- intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
-
- intel_runtime_pm_put(dev_priv, wakeref);
-
if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
seq_printf(m, "Hangcheck active, timer fires in %dms\n",
jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
@@ -1590,18 +1587,16 @@ static int i915_drpc_info(struct seq_file *m, void
*unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
- int err;
-
- wakeref = intel_runtime_pm_get(dev_priv);
+ int err = -ENODEV;
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- err = vlv_drpc_info(m);
- else if (INTEL_GEN(dev_priv) >= 6)
- err = gen6_drpc_info(m);
- else
- err = ironlake_drpc_info(m);
-
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ err = vlv_drpc_info(m);
+ else if (INTEL_GEN(dev_priv) >= 6)
+ err = gen6_drpc_info(m);
+ else
+ err = ironlake_drpc_info(m);
+ }
return err;
}
@@ -2080,8 +2075,7 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
intel_wakeref_t wakeref;
struct drm_file *file;
- wakeref = intel_runtime_pm_get_if_in_use(dev_priv);
- if (wakeref) {
+ with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&dev_priv->pcu_lock);
act_freq = vlv_punit_read(dev_priv,
@@ -2092,7 +2086,6 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
act_freq = intel_get_cagf(dev_priv,
[Intel-gfx] [PATCH 03/20] drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture
Since capturing the error state requires fiddling around with the GGTT
to read arbitrary buffers and is itself run under stop_machine(), it
deadlocks the machine (effectively a hard hang) when run in conjunction
with Broxton's VTd workaround to serialize GGTT access.
v2: Store the ERR_PTR in first_error so that the error can be reported
to the user via sysfs.
Fixes: 0ef34ad6222a ("drm/i915: Serialize GTT/Aperture accesses on BXT")
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: John Harrison
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 15 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 8 +++-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a98c29147d5e..b7120bf03c31 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3360,6 +3360,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
if (ggtt->vm.clear_range != nop_clear_range)
ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
+
+ /* Prevent recursively calling stop_machine() and deadlocks. */
+ i915_disable_error_state(dev_priv, -ENODEV);
}
ggtt->invalidate = gen6_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c8d8f79688a8..21b5c8765015 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -648,6 +648,9 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
return 0;
}
+ if (IS_ERR(error))
+ return PTR_ERR(error);
+
if (*error->error_msg)
err_printf(m, "%s\n", error->error_msg);
err_printf(m, "Kernel: " UTS_RELEASE "\n");
@@ -1867,6 +1870,7 @@ void i915_capture_error_state(struct drm_i915_private
*i915,
error = i915_capture_gpu_state(i915);
if (!error) {
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
+ i915_disable_error_state(i915, -ENOMEM);
return;
}
@@ -1922,5 +1926,14 @@ void i915_reset_error_state(struct drm_i915_private
*i915)
i915->gpu_error.first_error = NULL;
spin_unlock_irq(&i915->gpu_error.lock);
- i915_gpu_state_put(error);
+ if (!IS_ERR(error))
+ i915_gpu_state_put(error);
+}
+
+void i915_disable_error_state(struct drm_i915_private *i915, int err)
+{
+ spin_lock_irq(&i915->gpu_error.lock);
+ if (!i915->gpu_error.first_error)
+ i915->gpu_error.first_error = ERR_PTR(err);
+ spin_unlock_irq(&i915->gpu_error.lock);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 8710fb18ed74..3ec89a504de5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -343,6 +343,7 @@ static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu)
struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
+void i915_disable_error_state(struct drm_i915_private *i915, int err);
#else
@@ -355,13 +356,18 @@ static inline void i915_capture_error_state(struct
drm_i915_private *dev_priv,
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
- return NULL;
+ return ERR_PTR(-ENODEV);
}
static inline void i915_reset_error_state(struct drm_i915_private *i915)
{
}
+static inline void i915_disable_error_state(struct drm_i915_private *i915,
+ int err)
+{
+}
+
#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
#endif /* _I915_GPU_ERROR_H_ */
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/20] drm/i915: Pull all the reset functionality together into i915_reset.c
Currently the code to reset the GPU and our state is spread widely
across a few files. Pull the logic together into a common file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_debugfs.c |2 +
drivers/gpu/drm/i915/i915_drv.c | 205 +--
drivers/gpu/drm/i915/i915_drv.h | 33 +-
drivers/gpu/drm/i915/i915_gem.c | 484 +-
drivers/gpu/drm/i915/i915_gem_gtt.c |1 +
drivers/gpu/drm/i915/i915_irq.c | 238 ---
drivers/gpu/drm/i915/i915_request.c |1 +
drivers/gpu/drm/i915/i915_reset.c | 1331 +
drivers/gpu/drm/i915/i915_reset.h | 39 +
drivers/gpu/drm/i915/intel_display.c | 15 +-
drivers/gpu/drm/i915/intel_engine_cs.c|1 +
drivers/gpu/drm/i915/intel_guc.h |3 +
drivers/gpu/drm/i915/intel_hangcheck.c|1 +
drivers/gpu/drm/i915/intel_uc.c |1 +
drivers/gpu/drm/i915/intel_uncore.c | 451 --
drivers/gpu/drm/i915/selftests/intel_lrc.c|2 +
.../drm/i915/selftests/intel_workarounds.c|1 +
18 files changed, 1408 insertions(+), 1404 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_reset.c
create mode 100644 drivers/gpu/drm/i915/i915_reset.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 28c7d7884e88..0a5707326af6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -40,7 +40,8 @@ i915-y := i915_drv.o \
i915_mm.o \
i915_params.o \
i915_pci.o \
- i915_suspend.o \
+ i915_reset.o \
+ i915_suspend.o \
i915_syncmap.o \
i915_sw_fence.o \
i915_sysfs.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e2330ff46fa5..bb726e677981 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -32,6 +32,8 @@
#include "intel_drv.h"
#include "intel_guc_submission.h"
+#include "i915_reset.h"
+
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
return to_i915(node->minor->dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1dd875559aee..84fa9a9fc585 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_pmu.h"
+#include "i915_reset.h"
#include "i915_query.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
@@ -2189,210 +2190,6 @@ static int i915_resume_switcheroo(struct drm_device
*dev)
return i915_drm_resume(dev);
}
-/**
- * i915_reset - reset chip after a hang
- * @i915: #drm_i915_private to reset
- * @stalled_mask: mask of the stalled engines with the guilty requests
- * @reason: user error message for why we are resetting
- *
- * Reset the chip. Useful if a hang is detected. Marks the device as wedged
- * on failure.
- *
- * Caller must hold the struct_mutex.
- *
- * Procedure is fairly simple:
- * - reset the chip using the reset reg
- * - re-init context state
- * - re-init hardware status page
- * - re-init ring buffer
- * - re-init interrupt state
- * - re-init display
- */
-void i915_reset(struct drm_i915_private *i915,
- unsigned int stalled_mask,
- const char *reason)
-{
- struct i915_gpu_error *error = &i915->gpu_error;
- int ret;
- int i;
-
- GEM_TRACE("flags=%lx\n", error->flags);
-
- might_sleep();
- lockdep_assert_held(&i915->drm.struct_mutex);
- GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
-
- if (!test_bit(I915_RESET_HANDOFF, &error->flags))
- return;
-
- /* Clear any previous failed attempts at recovery. Time to try again. */
- if (!i915_gem_unset_wedged(i915))
- goto wakeup;
-
- if (reason)
- dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
- error->reset_count++;
-
- ret = i915_gem_reset_prepare(i915);
- if (ret) {
- dev_err(i915->drm.dev, "GPU recovery failed\n");
- goto taint;
- }
-
- if (!intel_has_gpu_reset(i915)) {
- if (i915_modparams.reset)
- dev_err(i915->drm.dev, "GPU reset not supported\n");
- else
- DRM_DEBUG_DRIVER("GPU reset disabled\n");
- goto error;
- }
-
- for (i = 0; i < 3; i++) {
- ret = intel_gpu_reset(i915, ALL_ENGINES);
- if (ret == 0)
- break;
-
- msleep(100);
- }
- if (ret) {
- dev_err(i915->drm.dev, "Failed to reset chip\n");
- goto taint;
- }
-
- /* Ok, now get things going again... */
-
- /*
-
[Intel-gfx] [PATCH 18/20] drm/i915: Differentiate between ggtt->mutex and ppgtt->mutex
We have two classes of VM, global GTT and per-process GTT. In order to
allow ourselves the freedom to mix both along call chains, distinguish
the two classes with regards to their mutex and lockdep maps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 6 +++---
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 45d982af52a9..e05b8b04b55a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -474,8 +474,7 @@ static void vm_free_page(struct i915_address_space *vm,
struct page *page)
spin_unlock(&vm->free_pages.lock);
}
-static void i915_address_space_init(struct i915_address_space *vm,
- struct drm_i915_private *dev_priv)
+static void i915_address_space_init(struct i915_address_space *vm, int
subclass)
{
/*
* The vm->mutex must be reclaim safe (for use in the shrinker).
@@ -483,6 +482,7 @@ static void i915_address_space_init(struct
i915_address_space *vm,
* attempt holding the lock is immediately reported by lockdep.
*/
mutex_init(&vm->mutex);
+ lockdep_set_subclass(&vm->mutex, subclass);
i915_gem_shrinker_taints_mutex(&vm->mutex);
GEM_BUG_ON(!vm->total);
@@ -1550,7 +1550,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
/* From bdw, there is support for read-only pages in the PPGTT. */
ppgtt->vm.has_read_only = true;
- i915_address_space_init(&ppgtt->vm, i915);
+ i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
@@ -1990,7 +1990,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
- i915_address_space_init(&ppgtt->base.vm, i915);
+ i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
@@ -3425,7 +3425,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
* and beyond the end of the GTT if we do not provide a guard.
*/
mutex_lock(&dev_priv->drm.struct_mutex);
- i915_address_space_init(&ggtt->vm, dev_priv);
+ i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
ggtt->vm.is_ggtt = true;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index db1fa5452a61..65786716af5c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -288,6 +288,8 @@ struct i915_address_space {
bool closed;
struct mutex mutex; /* protects vma and our lists */
+#define VM_CLASS_GGTT 0
+#define VM_CLASS_PPGTT 1
u64 scratch_pte;
struct i915_page_dma scratch_page;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index 6ae418c76015..976c862b3842 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -70,7 +70,7 @@ mock_ppgtt(struct drm_i915_private *i915,
ppgtt->vm.total = round_down(U64_MAX, PAGE_SIZE);
ppgtt->vm.file = ERR_PTR(-ENODEV);
- i915_address_space_init(&ppgtt->vm, i915);
+ i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
ppgtt->vm.clear_range = nop_clear_range;
ppgtt->vm.insert_page = mock_insert_page;
@@ -102,6 +102,7 @@ void mock_init_ggtt(struct drm_i915_private *i915)
struct i915_ggtt *ggtt = &i915->ggtt;
ggtt->vm.i915 = i915;
+ ggtt->vm.is_ggtt = true;
ggtt->gmadr = (struct resource) DEFINE_RES_MEM(0, 2048 * PAGE_SIZE);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
@@ -117,9 +118,8 @@ void mock_init_ggtt(struct drm_i915_private *i915)
ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
ggtt->vm.vma_ops.clear_pages = clear_pages;
- i915_address_space_init(&ggtt->vm, i915);
- ggtt->vm.is_ggtt = true;
+ i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
}
void mock_fini_ggtt(struct drm_i915_private *i915)
--
2.19.1
___
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[Intel-gfx] [PATCH 15/20] drm/i915: Complain if hsw_get_pipe_config acquires the same power well twice
As we only release each power well once, we assume that each transcoder
maps to a different domain. Complain if this is not so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 117f487765c8..ca21af88cb9f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9412,6 +9412,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc
*crtc,
power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false;
+
+ WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
*power_domain_mask |= BIT_ULL(power_domain);
tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
@@ -9439,6 +9441,8 @@ static bool bxt_get_dsi_transcoder_state(struct
intel_crtc *crtc,
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
+
+ WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
*power_domain_mask |= BIT_ULL(power_domain);
/*
@@ -9554,7 +9558,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
+ WARN_ON(power_domain_mask & BIT_ULL(power_domain));
power_domain_mask |= BIT_ULL(power_domain);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_get_pfit_config(crtc, pipe_config);
else
--
2.19.1
___
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[Intel-gfx] [PATCH 09/20] drm/i915: Markup paired operations on wakerefs
The majority of runtime-pm operations are bounded and scoped within a function; these are easy to verify that the wakeref are handled correctly. We can employ the compiler to help us, and reduce the number of wakerefs tracked when debugging, by passing around cookies provided by the various rpm_get functions to their rpm_put counterpart. This makes the pairing explicit, and given the required wakeref cookie the compiler can verify that we pass an initialised value to the rpm_put (quite handy for double checking error paths). For regular builds, the compiler should be able to eliminate the unused local variables and the program growth should be minimal. Fwiw, it came out as a net improvement as gcc was able to refactor rpm_get and rpm_get_if_in_use together, add/remove: 1/1 grow/shrink: 20/9 up/down: 191/-268 (-77) Function old new delta intel_runtime_pm_put_unchecked - 136+136 i915_gem_unpark 396 406 +10 intel_runtime_pm_get 135 141 +6 intel_runtime_pm_get_noresume136 141 +5 i915_perf_open_ioctl43754379 +4 i915_gpu_busy 72 76 +4 i915_gem_idle_work_handler 954 958 +4 capture 68146818 +4 mock_gem_device 14331436 +3 __execlists_submission_tasklet 25732576 +3 i915_sample 756 758 +2 intel_guc_submission_disable 364 365 +1 igt_mmap_offset_exhaustion 10351036 +1 i915_runtime_pm_status 257 258 +1 i915_rps_boost_info 13581359 +1 i915_hangcheck_info 12291230 +1 i915_gem_switch_to_kernel_context682 683 +1 i915_gem_suspend 410 411 +1 i915_gem_resume 254 255 +1 i915_gem_park190 191 +1 i915_engine_info 279 280 +1 intel_rps_mark_interactive 194 193 -1 i915_hangcheck_elapsed 15261525 -1 i915_gem_wait_for_idle 298 297 -1 i915_drop_caches_set 555 554 -1 execlists_submission_tasklet 126 125 -1 aliasing_gtt_bind_vma235 234 -1 i915_gem_retire_work_handler 144 142 -2 igt_evict_contexts.part 916 910 -6 intel_runtime_pm_get_if_in_use 141 23-118 intel_runtime_pm_put 136 --136 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Kconfig.debug| 1 + drivers/gpu/drm/i915/gvt/aperture_gm.c| 8 +- drivers/gpu/drm/i915/gvt/gvt.h| 2 +- drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 4 +- drivers/gpu/drm/i915/i915_debugfs.c | 133 +++--- drivers/gpu/drm/i915/i915_drv.h | 6 +- drivers/gpu/drm/i915/i915_gem.c | 58 +--- drivers/gpu/drm/i915/i915_gem_execbuffer.c| 5 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +-- drivers/gpu/drm/i915/i915_gem_shrinker.c | 27 ++-- drivers/gpu/drm/i915/i915_irq.c | 5 +- drivers/gpu/drm/i915/i915_perf.c | 10 +- drivers/gpu/drm/i915/i915_pmu.c | 26 ++-- drivers/gpu/drm/i915/i915_sysfs.c | 24 ++-- drivers/gpu/drm/i915/intel_display.c | 5 +- drivers/gpu/drm/i915/intel_drv.h | 15 +- drivers/gpu/drm/i915/intel_engine_cs.c| 12 +- drivers/gpu/drm/i915/intel_fbdev.c| 9 +- drivers/gpu/drm/i915/intel_guc_log.c | 15 +- drivers/gpu/drm/i915/intel_hotplug.c | 5 +- drivers/gpu/drm/i915/intel_huc.c | 5 +- drivers/gpu/drm/i915/intel_panel.c| 5 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 89 +--- drivers/gpu/drm/i915/intel_uncore.c | 5 +- drivers/gpu/drm/i915/selftests/huge_pages.c | 5 +- drivers/gpu/drm/i915/selftests/i915_gem.c | 29 ++-- .../drm/i915/selftests/i915_gem_coherency.c | 5 +- .../gpu/drm/i915/selftests/i915_gem_context.c | 27 ++-- .../gpu/drm/i915/selftests/i915_gem_evict.c | 11 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 10 +- .../gpu/drm/i915/selftests/i915_gem_object.c | 18 ++- drivers/gpu/drm/i915/selftests/i915_request.c | 22 +-- drivers/gpu/drm/i915/selftests/intel_guc.c| 10 +- .../gpu/drm/i915/selftests/intel_hangcheck.c | 5
[Intel-gfx] [PATCH 17/20] drm/i915: Serialise concurrent calls to i915_gem_set_wedged()
Make i915_gem_set_wedged() and i915_gem_unset_wedged() behaviour more
consistently if called concurrently.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 32 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 4 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28a5eb8c713d..3a80ebeda9a0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3319,10 +3319,15 @@ static void nop_complete_submit_request(struct
i915_request *request)
void i915_gem_set_wedged(struct drm_i915_private *i915)
{
+ struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- GEM_TRACE("start\n");
+ mutex_lock(&error->wedge_mutex);
+ if (test_bit(I915_WEDGED, &error->flags)) {
+ mutex_unlock(&error->wedge_mutex);
+ return;
+ }
if (GEM_SHOW_DEBUG()) {
struct drm_printer p = drm_debug_printer(__func__);
@@ -3331,8 +3336,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
intel_engine_dump(engine, &p, "%s\n", engine->name);
}
- if (test_and_set_bit(I915_WEDGED, &i915->gpu_error.flags))
- goto out;
+ GEM_TRACE("start\n");
/*
* First, stop submission to hw, but do not yet complete requests by
@@ -3392,20 +3396,28 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
i915_gem_reset_finish_engine(engine);
}
-out:
+ smp_mb__before_atomic();
+ set_bit(I915_WEDGED, &error->flags);
+
GEM_TRACE("end\n");
+ mutex_unlock(&error->wedge_mutex);
- wake_up_all(&i915->gpu_error.reset_queue);
+ wake_up_all(&error->reset_queue);
}
bool i915_gem_unset_wedged(struct drm_i915_private *i915)
{
+ struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
+ bool ret = false;
lockdep_assert_held(&i915->drm.struct_mutex);
- if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
+
+ if (!test_bit(I915_WEDGED, &error->flags))
return true;
+ mutex_lock(&error->wedge_mutex);
+
GEM_TRACE("start\n");
/*
@@ -3439,7 +3451,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
*/
if (dma_fence_default_wait(&rq->fence, true,
MAX_SCHEDULE_TIMEOUT) < 0)
- return false;
+ goto unlock;
}
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
@@ -3462,8 +3474,11 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
+ ret = true;
+unlock:
+ mutex_unlock(&i915->gpu_error.wedge_mutex);
- return true;
+ return ret;
}
static void
@@ -5794,6 +5809,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
i915_gem_idle_work_handler);
init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
+ mutex_init(&dev_priv->gpu_error.wedge_mutex);
atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index ff2652bbb0b0..9b61037baa43 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -270,8 +270,8 @@ struct i915_gpu_error {
#define I915_RESET_BACKOFF 0
#define I915_RESET_HANDOFF 1
#define I915_RESET_MODESET 2
+#define I915_RESET_ENGINE 3
#define I915_WEDGED(BITS_PER_LONG - 1)
-#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
/** Number of times an engine has been reset */
u32 reset_engine_count[I915_NUM_ENGINES];
@@ -282,6 +282,8 @@ struct i915_gpu_error {
/** Reason for the current *global* reset */
const char *reason;
+ struct mutex wedge_mutex; /* serialises wedging/unwedging */
+
/**
* Waitqueue to signal when a hang is detected. Used to for waiters
* to release the struct_mutex for the reset to procede.
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index aa4ddae94aca..4a25d2a344f2 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -189,6 +189,7 @@ struct drm_i915_private *mock_gem_device(void)
init_waitqueue_head(&i915->gpu_error.wait_queue);
init_waitqueue_head(&i915->gpu_error.reset_qu
[Intel-gfx] [PATCH 13/20] drm/i915: Combined gt.awake/gt.power wakerefs
As the GT_IRQ power domain implies a wakeref, we can use it inplace of
our existing redundant rpm grab.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 +
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dbb424044e8a..339d8e644535 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2122,7 +2122,6 @@ struct drm_i915_private {
* is a slight delay before we do so.
*/
intel_wakeref_t awake;
- intel_wakeref_t power;
/**
* The number of times we have woken up.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5e70c5b511c6..28a5eb8c713d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -177,9 +177,7 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
if (INTEL_GEN(i915) >= 6)
gen6_rps_idle(i915);
- intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, i915->gt.power);
-
- intel_runtime_pm_put(i915, wakeref);
+ intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref);
return i915->gt.epoch;
}
@@ -204,13 +202,11 @@ void i915_gem_unpark(struct drm_i915_private *i915)
lockdep_assert_held(&i915->drm.struct_mutex);
GEM_BUG_ON(!i915->gt.active_requests);
+ assert_rpm_wakelock_held(i915);
if (i915->gt.awake)
return;
- i915->gt.awake = intel_runtime_pm_get_noresume(i915);
- GEM_BUG_ON(!i915->gt.awake);
-
/*
* It seems that the DMC likes to transition between the DC states a lot
* when there are no connected displays (no active power domains) during
@@ -222,7 +218,8 @@ void i915_gem_unpark(struct drm_i915_private *i915)
* Work around it by grabbing a GT IRQ power domain whilst there is any
* GT activity, preventing any DC state transitions.
*/
- i915->gt.power = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
+ i915->gt.awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
+ GEM_BUG_ON(!i915->gt.awake);
if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
i915->gt.epoch = 1;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0eb283e7fc96..aa4ddae94aca 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -164,6 +164,7 @@ struct drm_i915_private *mock_gem_device(void)
pm_runtime_dont_use_autosuspend(&pdev->dev);
if (pm_runtime_enabled(&pdev->dev))
WARN_ON(pm_runtime_get_sync(&pdev->dev));
+ disable_rpm_wakeref_asserts(i915);
err = drm_dev_init(&i915->drm, &mock_driver, &pdev->dev);
if (err) {
--
2.19.1
___
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[Intel-gfx] [PATCH 07/20] drm/i915: Remove debugfs/i915_ppgtt_info
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 119
drivers/gpu/drm/i915/i915_gem_gtt.c | 134
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 -
3 files changed, 255 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 62a716d03a69..7c218614e322 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2034,124 +2034,6 @@ static int i915_swizzle_info(struct seq_file *m, void
*data)
return 0;
}
-static int per_file_ctx(int id, void *ptr, void *data)
-{
- struct i915_gem_context *ctx = ptr;
- struct seq_file *m = data;
- struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
-
- if (!ppgtt) {
- seq_printf(m, " no ppgtt for context %d\n",
- ctx->user_handle);
- return 0;
- }
-
- if (i915_gem_context_is_default(ctx))
- seq_puts(m, " default context:\n");
- else
- seq_printf(m, " context %d:\n", ctx->user_handle);
- ppgtt->debug_dump(ppgtt, m);
-
- return 0;
-}
-
-static void gen8_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int i;
-
- if (!ppgtt)
- return;
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- for (i = 0; i < 4; i++) {
- u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
- pdp <<= 32;
- pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
- seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
- }
- }
-}
-
-static void gen6_ppgtt_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (IS_GEN6(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
-
- for_each_engine(engine, dev_priv, id) {
- seq_printf(m, "%s\n", engine->name);
- if (IS_GEN7(dev_priv))
- seq_printf(m, "GFX_MODE: 0x%08x\n",
- I915_READ(RING_MODE_GEN7(engine)));
- seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE(engine)));
- seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE_READ(engine)));
- seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
- I915_READ(RING_PP_DIR_DCLV(engine)));
- }
- if (dev_priv->mm.aliasing_ppgtt) {
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-
- seq_puts(m, "aliasing PPGTT:\n");
- seq_printf(m, "pd gtt offset: 0x%08x\n",
ppgtt->pd.base.ggtt_offset);
-
- ppgtt->debug_dump(ppgtt, m);
- }
-
- seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
-}
-
-static int i915_ppgtt_info(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = &dev_priv->drm;
- struct drm_file *file;
- int ret;
-
- mutex_lock(&dev->filelist_mutex);
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- goto out_unlock;
-
- intel_runtime_pm_get(dev_priv);
-
- if (INTEL_GEN(dev_priv) >= 8)
- gen8_ppgtt_info(m, dev_priv);
- else if (INTEL_GEN(dev_priv) >= 6)
- gen6_ppgtt_info(m, dev_priv);
-
- list_for_each_entry_reverse(file, &dev->filelist, lhead) {
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct task_struct *task;
-
- task = get_pid_task(file->pid, PIDTYPE_PID);
- if (!task) {
- ret = -ESRCH;
- goto out_rpm;
- }
- seq_printf(m, "\nproc: %s\n", task->comm);
- put_task_struct(task);
- idr_for_each(&file_priv->context_idr, per_file_ctx,
-(void *)(unsigned long)m);
- }
-
-out_rpm:
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev->struct_mutex);
-out_unlock:
- mutex_unlock(&dev->filelist_mutex);
- return ret;
-}
-
static int count_irq_waiters(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
@@ -4786,7 +4668,6 @@ static cons
[Intel-gfx] [PATCH 12/20] drm/i915: Track the wakeref used to initialise display power domains
On module load and unload, we grab the POWER_DOMAIN_INIT powerwells and
transfer them to the runtime-pm code. We can use our wakeref tracking to
verify that the wakeref is indeed passed from init to enable, and
disable to fini; and across suspend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 151 +---
3 files changed, 88 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 925f73085d4f..0b9b70caa98e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2710,6 +2710,9 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
if (!HAS_RUNTIME_PM(dev_priv))
seq_puts(m, "Runtime power management not supported\n");
+ seq_printf(m, "Runtime power management: %s\n",
+ enableddisabled(!dev_priv->power_domains.wakeref));
+
seq_printf(m, "GPU idle: %s (epoch %u)\n",
yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
seq_printf(m, "IRQs disabled: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d13ffe24c5ee..dbb424044e8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -947,6 +947,8 @@ struct i915_power_domains {
bool display_core_suspended;
int power_well_count;
+ intel_wakeref_t wakeref;
+
struct mutex lock;
int domain_use_count[POWER_DOMAIN_NUM];
struct i915_power_well *power_wells;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6d32cd2b9763..d5c16252063c 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -4011,7 +4011,7 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *dev_priv);
/**
* intel_power_domains_init_hw - initialize hardware power domain state
- * @dev_priv: i915 device instance
+ * @i915: i915 device instance
* @resume: Called from resume code paths or not
*
* This function initializes the hardware power domain state and enables all
@@ -4025,30 +4025,31 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *dev_priv);
* intel_power_domains_enable()) and must be paired with
* intel_power_domains_fini_hw().
*/
-void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
resume)
+void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &i915->power_domains;
power_domains->initializing = true;
- if (IS_ICELAKE(dev_priv)) {
- icl_display_core_init(dev_priv, resume);
- } else if (IS_CANNONLAKE(dev_priv)) {
- cnl_display_core_init(dev_priv, resume);
- } else if (IS_GEN9_BC(dev_priv)) {
- skl_display_core_init(dev_priv, resume);
- } else if (IS_GEN9_LP(dev_priv)) {
- bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ if (IS_ICELAKE(i915)) {
+ icl_display_core_init(i915, resume);
+ } else if (IS_CANNONLAKE(i915)) {
+ cnl_display_core_init(i915, resume);
+ } else if (IS_GEN9_BC(i915)) {
+ skl_display_core_init(i915, resume);
+ } else if (IS_GEN9_LP(i915)) {
+ bxt_display_core_init(i915, resume);
+ } else if (IS_CHERRYVIEW(i915)) {
mutex_lock(&power_domains->lock);
- chv_phy_control_init(dev_priv);
+ chv_phy_control_init(i915);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(i915)) {
mutex_lock(&power_domains->lock);
- vlv_cmnlane_wa(dev_priv);
+ vlv_cmnlane_wa(i915);
mutex_unlock(&power_domains->lock);
- } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ } else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) {
+ intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
+ }
/*
* Keep all power wells enabled for any dependent HW access during
@@ -4056,18 +4057,20 @@ void intel_power_domains_init_hw(struct
drm_i915_private *dev_priv, bool resume)
* resources powered until display HW readout is complete. We drop
* this reference in intel_power_domains_enable().
*/
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ power_domains->wakeref =
+ intel_display_power_get(i915, POWER_DOMAIN_INIT);
+
/* Disable power support
[Intel-gfx] [PATCH 08/20] drm/i915: Track all held rpm wakerefs
Everytime we take a wakeref, record the stack trace of where it was
taken; clearing the set if we ever drop back to no owners. For debugging
a rpm leak, we can look at all the current wakerefs and check if they
have a matching rpm_put.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug| 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/intel_drv.h | 44 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 267 --
.../gpu/drm/i915/selftests/mock_gem_device.c | 8 +-
7 files changed, 292 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 9e36ffb5eb7c..a97929c47466 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -21,11 +21,11 @@ config DRM_I915_DEBUG
select DEBUG_FS
select PREEMPT_COUNT
select I2C_CHARDEV
+select STACKDEPOT
select DRM_DP_AUX_CHARDEV
select X86_MSR # used by igt/pm_rpm
select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
select DRM_DEBUG_MM if DRM=y
-select STACKDEPOT if DRM=y # for DRM_DEBUG_MM
select DRM_DEBUG_SELFTEST
select SW_SYNC # signaling validation framework (igt/syncobj*)
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7c218614e322..7bc69a4da120 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2714,6 +2714,12 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
pci_power_name(pdev->current_state),
pdev->current_state);
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
+ struct drm_printer p = drm_seq_file_printer(m);
+
+ print_intel_runtime_pm_wakeref(dev_priv, &p);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fea3d471fa4f..6df349cd56f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -895,6 +895,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->pps_mutex);
i915_memcpy_init_early(dev_priv);
+ intel_runtime_pm_init_early(dev_priv);
ret = i915_workqueues_init(dev_priv);
if (ret < 0)
@@ -1791,8 +1792,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_cleanup_mmio(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
-
- WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
+ intel_runtime_pm_cleanup(dev_priv);
}
static void i915_driver_release(struct drm_device *dev)
@@ -1994,6 +1994,8 @@ static int i915_drm_suspend_late(struct drm_device *dev,
bool hibernation)
out:
enable_rpm_wakeref_asserts(dev_priv);
+ if (!dev_priv->uncore.user_forcewake.count)
+ intel_runtime_pm_cleanup(dev_priv);
return ret;
}
@@ -2948,7 +2950,7 @@ static int intel_runtime_suspend(struct device *kdev)
}
enable_rpm_wakeref_asserts(dev_priv);
- WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
+ intel_runtime_pm_cleanup(dev_priv);
if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96d7a08e6e68..d7f94fc92439 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -45,6 +45,7 @@
#include
#include
#include
+#include
#include
#include
@@ -1291,6 +1292,12 @@ struct i915_runtime_pm {
atomic_t wakeref_count;
bool suspended;
bool irqs_enabled;
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+ spinlock_t debug_lock;
+ depot_stack_handle_t *debug_owners;
+ unsigned long debug_count;
+#endif
};
enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e4eaa40bd5f1..6c2a6c795287 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -41,6 +41,8 @@
#include
#include
+struct drm_printer;
+
/**
* __wait_for - magic wait macro
*
@@ -2042,6 +2044,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state
*new_crtc_state,
void intel_init_quirks(struct drm_i915_private *dev_priv);
/* intel_runtime_pm.c */
+void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
int intel_power_domains_init(struct drm_i915_private *);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
[Intel-gfx] [PATCH 05/20] drm/i915: Cache the error string
Currently, we convert the error state into a string every time we read
from sysfs (and sysfs reads in page size (4KiB) chunks). We do try to
window the string and only capture the portion that is being read, but
that means that we must always convert up to the window to find the
start. For a very large error state bordering on EXEC_OBJECT_CAPTURE
abuse, this is noticeable as it degrades to O(N^2)!
As we do not have a convenient hook for sysfs open(), and we would like
to keep the lazy conversion into a string, do the conversion of the
whole string on the first read and keep the string until the error state
is freed.
v2: Don't double advance simple_read_from_buffer
v3: Due to extreme pain of lack of vrealloc, use a scatterlist
v4: Keep the forward iterator loosely cached
Reported-by: Jason Ekstrand
Testcase: igt/gem_exec_capture/many*
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Jason Ekstrand
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 402 +++---
drivers/gpu/drm/i915/i915_gpu_error.h | 28 +-
drivers/gpu/drm/i915/i915_sysfs.c | 27 +-
4 files changed, 273 insertions(+), 216 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 041319d48ca3..17616458eb70 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -943,30 +943,28 @@ static int i915_gem_fence_regs_info(struct seq_file *m,
void *data)
static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
size_t count, loff_t *pos)
{
- struct i915_gpu_state *error = file->private_data;
- struct drm_i915_error_state_buf str;
+ struct i915_gpu_state *error;
ssize_t ret;
- loff_t tmp;
+ void *buf;
+ error = file->private_data;
if (!error)
return 0;
- ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
- if (ret)
- return ret;
-
- ret = i915_error_state_to_str(&str, error);
- if (ret)
- goto out;
+ /* Bounce buffer required because of kernfs __user API convenience. */
+ buf = kmalloc(count, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
- tmp = 0;
- ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
- if (ret < 0)
- goto out;
+ ret = i915_gpu_state_copy_to_buffer(error, buf, *pos, count);
+ if (ret > 0) {
+ if (!copy_to_user(ubuf, buf, ret))
+ *pos += ret;
+ else
+ ret = -EFAULT;
+ }
- *pos = str.start + ret;
-out:
- i915_error_state_buf_release(&str);
+ kfree(buf);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 21b5c8765015..94c56c9fa66d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -28,6 +28,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -77,112 +79,110 @@ static const char *purgeable_flag(int purgeable)
return purgeable ? " purgeable" : "";
}
-static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
+static void __sg_set_buf(struct scatterlist *sg,
+void *addr, unsigned int len, loff_t it)
{
-
- if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
- e->err = -ENOSPC;
- return false;
- }
-
- if (e->bytes == e->size - 1 || e->err)
- return false;
-
- return true;
+ sg->page_link = (unsigned long)virt_to_page(addr);
+ sg->offset = offset_in_page(addr);
+ sg->length = len;
+ sg->dma_address = it;
}
-static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
- unsigned len)
+static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
{
- if (e->pos + len <= e->start) {
- e->pos += len;
+ if (!len)
return false;
- }
- /* First vsnprintf needs to fit in its entirety for memmove */
- if (len >= e->size) {
- e->err = -EIO;
- return false;
- }
+ if (e->bytes + len + 1 > e->size) {
+ if (e->bytes) {
+ __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
+ e->iter += e->bytes;
+ e->buf = NULL;
+ e->bytes = 0;
+ }
- return true;
-}
+ if (e->cur == e->end) {
+ struct scatterlist *sgl;
-static void __i915_error_advance(struct drm_i915_error_state_buf *e,
-unsigned len)
-{
- /* If this is first printf in this window, adjust it so that
-* start position matches start of the buffer
-
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: context submission pvmmio optimization
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He, Min ;
Jiang; Jiang, Fei ; Gong; Gong, Zhipeng
; Yuan; Yuan, Hang ; Lv, Zhiyuan
Subject: [PATCH v2 3/5] drm/i915: context submission pvmmio optimization
It is performance optimization to reduce mmio trap numbers from 4 to
1 durning ELSP porting writing (context submission).
When context subission, to cache elsp_data[4] values in the shared page, the
last elsp_data[0] port writing will be trapped to gvt for real context
submission.
Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.
v0: RFC
v1: rebase
v2: added pv ops for pv context submission. to maximize code resuse, introduced
2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of submit_ports and
preempt_context implemented.
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: He, Min
Cc: Jiang, Fei
Cc: Gong, Zhipeng
Cc: Yuan, Hang
Cc: Zhiyuan Lv
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_vgpu.c| 2 +
drivers/gpu/drm/i915/intel_lrc.c| 88 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++
3 files changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index cb409d5..9870ea6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,6 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
+ dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+
magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
if (magic != VGT_MAGIC)
return;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8..9e6ccf9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -460,6 +460,60 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); }
+static void execlists_submit_ports_pv(struct intel_engine_cs *engine) {
+ struct intel_engine_execlists *execlists = &engine->execlists;
+ struct execlist_port *port = execlists->port;
+ u32 __iomem *elsp =
+ engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+ u32 *elsp_data;
+ unsigned int n;
+ u32 descs[4];
+ int i = 0;
+
+ /*
+* ELSQ note: the submit queue is not cleared after being submitted
+* to the HW so we need to make sure we always clean it up. This is
+* currently ensured by the fact that we always write the same number
+* of elsq entries, keep this in mind before changing the loop below.
+*/
+ for (n = execlists_num_ports(execlists); n--; ) {
+ struct i915_request *rq;
+ unsigned int count;
+ u64 desc;
+
+ rq = port_unpack(&port[n], &count);
+ if (rq) {
+ GEM_BUG_ON(count > !n);
+ if (!count++)
+ execlists_context_schedule_in(rq);
+ port_set(&port[n], port_pack(rq, count));
+ desc = execlists_update_context(rq);
+ } else {
+ GEM_BUG_ON(!n);
+ desc = 0;
+ }
+ GEM_BUG_ON(i >= 4);
+ descs[i] = upper_32_bits(desc);
+ descs[i + 1] = lower_32_bits(desc);
+ i += 2;
+ }
+
+ spin_lock(&engine->i915->vgpu.shared_page_lock);
+ elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+ *elsp_data = descs[0];
+ *(elsp_data + 1) = descs[1];
+ *(elsp_data + 2) = descs[2];
+ writel(descs[3], elsp);
+ spin_unlock(&engine->i915->vgpu.shared_page_lock);
+
+ /* we need to manually load the submit queue */
+ if (execlists->ctrl_reg)
+ writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+
+ execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); }
+
static bool ctx_single_port_submission(const struct intel_context *ce) {
return (IS_ENABLED(CONFIG_DRM_I915_GVT) && @@ -497,7 +551,6 @@ static
void inject_preempt_context(struct intel_engine_cs *engine)
GEM_BUG_ON(execlists->preempt_complete_status !=
upper_32_bits(ce->lrc_desc));
-
/*
* Switch to our empty preempt context so
* the state of the GPU is known (idle).
@@ -516,6 +569,27 @@ static void inject_preempt_context(struct intel_engine_cs
*engine)
execlists_set_active(execlists, EXECLISTS_
Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu
Ping review. Thanks very much.
BRs
Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He, Min ;
Jiang; Jiang, Fei ; Gong; Gong, Zhipeng
; Yuan; Yuan, Hang ; Lv, Zhiyuan
Subject: [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu
This u32 pv_caps field is used to control the different level pvmmio feature
for MMIO emulation in GVT.
This field is default zero, no pvmmio feature enabled.
it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg can support
PV feature or not.
v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter by pv
capability check.
v2: rebase
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: He, Min
Cc: Jiang, Fei
Cc: Gong, Zhipeng
Cc: Yuan, Hang
Cc: Zhiyuan Lv
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.h| 11 +++
drivers/gpu/drm/i915/i915_pvinfo.h | 17 -
drivers/gpu/drm/i915/i915_vgpu.c | 19 +--
3 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef0..7b2d7cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
#include "i915_params.h"
#include "i915_reg.h"
+#include "i915_pvinfo.h"
#include "i915_utils.h"
#include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds { struct i915_virtual_gpu {
bool active;
u32 caps;
+ u32 pv_caps;
};
/* used in computing the new watermarks state */ @@ -2853,6 +2855,11 @@ static
inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.active;
}
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private
+*dev_priv) {
+ return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO; }
+
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
enum pipe pipe);
void
@@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct
drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level) \
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..26709e8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,12 +49,26 @@ enum vgt_g2v_type {
VGT_G2V_MAX,
};
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
/*
* VGT capabilities type
*/
#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
#define VGT_CAPS_HWSP_EMULATIONBIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
+#define VGT_CAPS_PVMMIOBIT(5)
+
+/*
+ * define different levels of PVMMIO optimization */ enum
+pvmmio_levels {
+ PVMMIO_ELSP_SUBMIT = 0x1,
+ PVMMIO_PLANE_UPDATE = 0x2,
+ PVMMIO_PLANE_WM_UPDATE = 0x4,
+ PVMMIO_MASTER_IRQ = 0x8,
+ PVMMIO_PPGTT_UPDATE = 0x10,
+};
struct vgt_if {
u64 magic; /* VGT_MAGIC */
@@ -106,8 +120,9 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
+ u32 enable_pvmmio;
- u32 rsv7[0x200 - 24];/* pad to one page */
+ u32 rsv7[0x200 - 25];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..907bbd2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -76,9 +76,24 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
}
dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
dev_priv->vgpu.active = true;
- DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+ if (!intel_vgpu_has_pvmmio(dev_priv)) {
+ DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+ return;
+ }
+
+ /* If guest wants to enable pvmmio, it needs to enable it explicitly
+* through vgt_if interface, and then read back the enable state from
+* gvt layer.
+*/
+ __raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+ dev_priv->vgpu.pv_caps);
+ dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+ vgtif_reg(enable_pvmmio));
+
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+ dev_priv->vgpu.pv_caps);
}
bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
--
2.7.4
___
Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He, Min ;
Jiang; Jiang, Fei ; Gong; Gong, Zhipeng
; Yuan; Yuan, Hang ; Lv, Zhiyuan
Subject: [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio
To enable pvmmio feature, we need to prepare one 4K shared page which will be
accessed by both guest and backend i915 driver.
guest i915 allocate one page memory and then the guest physical address is
passed to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page without hypeviser trap cost for shared data
exchagne via hyperviser read_gpa functionality.
v0: RFC
v1: addressed RFC comment to move both shared_page_lock and shared_page to
i915_virtual_gpu structure
v2: packed i915_virtual_gpu structure
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: He, Min
Cc: Jiang, Fei
Cc: Gong, Zhipeng
Cc: Yuan, Hang
Cc: Zhiyuan Lv
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.c| 2 ++
drivers/gpu/drm/i915/i915_drv.h| 4 +++-
drivers/gpu/drm/i915/i915_pvinfo.h | 24 +++-
drivers/gpu/drm/i915/i915_vgpu.c | 24 +++-
4 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f..557ab67 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -987,6 +987,8 @@ static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv)
intel_teardown_mchbar(dev_priv);
pci_iounmap(pdev, dev_priv->regs);
+ if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b2d7cb..d7a972f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1345,7 +1345,9 @@ struct i915_virtual_gpu {
bool active;
u32 caps;
u32 pv_caps;
-};
+ spinlock_t shared_page_lock;
+ struct gvt_shared_page *shared_page;
+} __packed;
/* used in computing the new watermarks state */ struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 26709e8..179d558 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,6 +49,24 @@ enum vgt_g2v_type {
VGT_G2V_MAX,
};
+struct pv_ppgtt_update {
+ u64 pdp;
+ u64 start;
+ u64 length;
+ u32 cache_level;
+};
+
+/*
+ * shared page(4KB) between gvt and VM, could be allocated by guest
+driver
+ * or a fixed location in PCI bar 0 region */ struct gvt_shared_page {
+ u32 elsp_data[4];
+ u32 reg_addr;
+ u32 disable_irq;
+ struct pv_ppgtt_update pv_ppgtt;
+};
+
#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
/*
@@ -121,8 +139,12 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
u32 enable_pvmmio;
+ struct {
+ u32 lo;
+ u32 hi;
+ } shared_page_gpa;
- u32 rsv7[0x200 - 25];/* pad to one page */
+ u32 rsv7[0x200 - 27];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 907bbd2..cb409d5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -62,6 +62,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv) {
u64 magic;
u16 version_major;
+ u64 gpa;
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
@@ -91,7 +92,28 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
dev_priv->vgpu.pv_caps);
dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
vgtif_reg(enable_pvmmio));
-
+ if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.pv_caps) {
+ dev_priv->vgpu.shared_page = (struct gvt_shared_page *)
+ get_zeroed_page(GFP_KERNEL);
+ if (!dev_priv->vgpu.shared_page) {
+ DRM_ERROR("out of memory for shared page memory\n");
+ return;
+ }
+ gpa = __pa(dev_priv->vgpu.shared_page);
+ __raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+ lower_32_bits(gpa));
+ __raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+ upper_32_bits(gpa));
+ if (gpa != __raw_i915_read64(dev_priv,
+ vgtif_r
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: master irq pvmmio optimization
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He, Min ;
Jiang; Jiang, Fei ; Gong; Gong, Zhipeng
; Yuan; Yuan, Hang ; Lv, Zhiyuan
Subject: [PATCH v2 4/5] drm/i915: master irq pvmmio optimization
Master irq register is accessed twice every irq handling, then trapped to SOS
very frequently. Optimize it by moving master irq register to share page,
writing don't need be trapped.
When need enable irq to let SOS inject irq timely, use another pvmmio register
to achieve this purpose. So avoid one trap when we disable master irq.
Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization.
v0: RFC
v1: rebase
v2: added pv version callbacks for irq_{irq_handler, irq_preinstall,
irq_postinstall}
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: He, Min
Cc: Jiang, Fei
Cc: Gong, Zhipeng
Cc: Yuan, Hang
Cc: Zhiyuan Lv
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_irq.c| 82 --
drivers/gpu/drm/i915/i915_pvinfo.h | 3 +-
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
3 files changed, 81 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d1f537..95ed2e7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2938,6 +2938,40 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
+static irqreturn_t gen8_irq_handler_pv(int irq, void *arg) {
+ struct drm_i915_private *dev_priv = to_i915(arg);
+ u32 master_ctl;
+ u32 gt_iir[4];
+
+ if (!intel_irqs_enabled(dev_priv))
+ return IRQ_NONE;
+
+ master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+ master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
+ if (!master_ctl)
+ return IRQ_NONE;
+
+ dev_priv->vgpu.shared_page->disable_irq = 1;
+
+ /* Find, clear, then process each source of interrupt */
+ gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
+
+ /* IRQs are synced during runtime_suspend, we don't require a wakeref */
+ if (master_ctl & ~GEN8_GT_IRQS) {
+ disable_rpm_wakeref_asserts(dev_priv);
+ gen8_de_irq_handler(dev_priv, master_ctl);
+ enable_rpm_wakeref_asserts(dev_priv);
+ }
+
+ dev_priv->vgpu.shared_page->disable_irq = 0;
+ __raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+ gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
+
+ return IRQ_HANDLED;
+}
+
struct wedge_me {
struct delayed_work work;
struct drm_i915_private *i915;
@@ -3626,13 +3660,11 @@ static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv)
GEN8_IRQ_RESET_NDX(GT, 3);
}
-static void gen8_irq_reset(struct drm_device *dev)
+static void gen8_irq_reset_common(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
int pipe;
- gen8_master_intr_disable(dev_priv->regs);
-
gen8_gt_irq_reset(dev_priv);
I915_WRITE(EDP_PSR_IMR, 0x);
@@ -3651,6 +3683,22 @@ static void gen8_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev_priv);
}
+static void gen8_irq_reset(struct drm_device *dev) {
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ gen8_master_intr_disable(dev_priv->regs);
+ gen8_irq_reset_common(dev);
+}
+
+static void gen8_irq_reset_pv(struct drm_device *dev) {
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->vgpu.shared_page->disable_irq = 1;
+ gen8_irq_reset_common(dev);
+}
+
static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) {
/* Disable RCS, BCS, VCS and VECS class engines. */ @@ -4262,7 +4310,7
@@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
-static int gen8_irq_postinstall(struct drm_device *dev)
+static int gen8_irq_postinstall_common(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4275,11 +4323,32 @@ static int gen8_irq_postinstall(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev);
+ return 0;
+}
+
+static int gen8_irq_postinstall(struct drm_device *dev) {
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ gen8_irq_postinstall_common(dev);
+
gen8_master_intr_enable(dev_priv->regs);
return 0;
}
+static int gen8_irq_postinstall_pv(struct drm_device *dev) {
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ gen8_irq_postinstall_common(dev);
+
+ dev_priv->vgpu.shared_page->disable_irq = 0;
+ __raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51785/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Okay! Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 02/38] drm/i915/dsi: move connector mode functions to common file
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Patch 1 & 2 v2 changes, i.e. code movement to intel_dsi.c
looks fine to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 47 +++
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/vlv_dsi.c | 48
3 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 97e04c272612..b9d5ef79015e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -29,6 +29,53 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
}
}
+int intel_dsi_get_modes(struct drm_connector *connector)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_display_mode *mode;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (!intel_connector->panel.fixed_mode) {
+ DRM_DEBUG_KMS("no fixed mode\n");
+ return 0;
+ }
+
+ mode = drm_mode_duplicate(connector->dev,
+ intel_connector->panel.fixed_mode);
+ if (!mode) {
+ DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
+ return 0;
+ }
+
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
+ int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (fixed_mode) {
+ if (mode->hdisplay > fixed_mode->hdisplay)
+ return MODE_PANEL;
+ if (mode->vdisplay > fixed_mode->vdisplay)
+ return MODE_PANEL;
+ if (fixed_mode->clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+ }
+
+ return MODE_OK;
+}
+
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops
*funcs,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 09f0fa9ccc7d..10fd1582a8e2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+int intel_dsi_get_modes(struct drm_connector *connector);
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode);
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops
*funcs,
enum port port);
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index cbb935a9acf3..bab87b62bc2d 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1212,31 +1212,6 @@ static void intel_dsi_get_config(struct intel_encoder
*encoder,
}
}
-static enum drm_mode_status
-intel_dsi_mode_valid(struct drm_connector *connector,
-struct drm_display_mode *mode)
-{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
-
- DRM_DEBUG_KMS("\n");
-
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
- return MODE_NO_DBLESCAN;
-
- if (fixed_mode) {
- if (mode->hdisplay > fixed_mode->hdisplay)
- return MODE_PANEL;
- if (mode->vdisplay > fixed_mode->vdisplay)
- return MODE_PANEL;
- if (fixed_mode->clock > max_dotclk)
- return MODE_CLOCK_HIGH;
- }
-
- return MODE_OK;
-}
-
/* return txclkesc cycles in terms of divider and duration in us */
static u16 txclkesc(u32 divider, unsigned int us)
{
@@ -1559,29 +1534,6 @@ static void intel_dsi_unprepare(struct intel_encoder
*encoder)
}
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He, Min ;
Jiang; Jiang, Fei ; Gong; Gong, Zhipeng
; Yuan; Yuan, Hang ; Lv, Zhiyuan
Subject: [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization
This patch extends g2v notification to notify host GVT-g of ppgtt update from
guest, including alloc_4lvl, clear_4lv4 and insert_4lvl. It uses shared page to
pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.
Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.
v0: RFC
v1: rebase
v2: added pv callbacks for vm.{allocate_va_range, insert_entries, clear_range}
within ppgtt.
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: He, Min
Cc: Jiang, Fei
Cc: Gong, Zhipeng
Cc: Yuan, Hang
Cc: Zhiyuan Lv
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +
drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++
drivers/gpu/drm/i915/i915_vgpu.c| 3 +-
3 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1e..b529f53 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -956,6 +956,25 @@ static void gen8_ppgtt_clear_4lvl(struct
i915_address_space *vm,
}
}
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+ u64 start, u64 length)
+{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct i915_pml4 *pml4 = &ppgtt->pml4;
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->vgpu.shared_page->pv_ppgtt;
+ u64 orig_start = start;
+ u64 orig_length = length;
+
+ gen8_ppgtt_clear_4lvl(vm, start, length);
+
+ pv_ppgtt->pdp = px_dma(pml4);
+ pv_ppgtt->start = orig_start;
+ pv_ppgtt->length = orig_length;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR); }
+
static inline struct sgt_dma {
struct scatterlist *sg;
dma_addr_t dma, max;
@@ -1197,6 +1216,25 @@ static void gen8_ppgtt_insert_4lvl(struct
i915_address_space *vm,
}
}
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 flags)
+{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->vgpu.shared_page->pv_ppgtt;
+
+ gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
+
+ pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+ pv_ppgtt->start = vma->node.start;
+ pv_ppgtt->length = vma->node.size;
+ pv_ppgtt->cache_level = cache_level;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT); }
+
static void gen8_free_page_tables(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
@@ -1466,6 +1504,30 @@ static int gen8_ppgtt_alloc_4lvl(struct
i915_address_space *vm,
return -ENOMEM;
}
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+u64 start, u64 length)
+{
+ struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct i915_pml4 *pml4 = &ppgtt->pml4;
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->vgpu.shared_page->pv_ppgtt;
+ int ret;
+ u64 orig_start = start;
+ u64 orig_length = length;
+
+ ret = gen8_ppgtt_alloc_4lvl(vm, start, length);
+ if (ret)
+ return ret;
+
+ pv_ppgtt->pdp = px_dma(pml4);
+ pv_ppgtt->start = orig_start;
+ pv_ppgtt->length = orig_length;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+
+ return 0;
+}
+
static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
struct i915_page_directory_pointer *pdp,
u64 start, u64 length,
@@ -1631,6 +1693,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+ if (PVMMIO_LEVEL_ENABLE(i915, PVMMIO_PPGTT_UPDATE)) {
+ ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv;
+ ppgtt->vm.insert_entries = gen8_p
Re: [Intel-gfx] [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Looks OK to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a1753d246..9c424adc8b75 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
* Jani Nikula
*/
+#include
#include "intel_dsi.h"
static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder,
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+ int ret;
+
+ /* set maximum return packet size */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /*
+* FIXME: This uses the number of DW's currently in the payload
+* receive queue. This is probably not what we want here.
+*/
+ tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+ tmp &= NUMBER_RX_PLOAD_DW_MASK;
+ /* multiply "Number Rx Payload DW" by 4 to get max value */
+ tmp = tmp * 4;
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+ if (ret < 0)
+ DRM_ERROR("error setting max return pkt size%d\n", tmp);
+ }
+}
+
static void __attribute__((unused))
gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+ /* step5: program and powerup panel */
+ gen11_dsi_powerup_panel(encoder);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
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Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
On Tue, 30 Oct 2018, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula
> wrote:
>>
>> On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
>> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
>> > from the base - which is the FLexi IO Adaptor. Lets follow the
>> > offset calculation while accessing these registers.
>>
>> Why?
>>
>> If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
>> I'm looking for.
>>
>> We generally don't follow this type of definitions for registers. We may
>> have some, but those are exceptions.
>
> Because spec 29550 treats those registers as a base + offset to be more
> future proof regarding a change of the base. And yes, I think something
> like that needs to be stated in the commit message. Is this enough?
Fair enough. Please also see comments in-line.
>
> Lucas De Marchi
>
>>
>> Please don't do this without some pretty good rationale written in the
>> commit message.
>>
>> BR,
>> Jani.
>>
>> >
>> > v2:
>> > - Follow spec for numbering - s/0/1(Lucas)
>> > - s/FIA_1/FIA1_BASE (Anusha)
>> >
>> > Cc: Lucas De Marchi
>> > Signed-off-by: Anusha Srivatsa
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 15 +++
>> > 1 file changed, 11 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index bcee91bcfba6..dd74bc01c64e 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
>> > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy),
>> > _PORT_CL2CM_DW6_BC)
>> > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>> >
>> > +/* FIA Offsets */
>> > +#define FIA1_BASE0x163000
Ok.
>> > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
>> > +#define PORT_TX_DFLEXDPPMS_OFFSET0x00890
>> > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
>> > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
These should not be grouped here, instead please add above each macro
below or just leave out, see below.
>> > +
>> > /* ICL PHY DFLEX registers */
>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
>> > PORT_TX_DFLEXDPMLE1_OFFSET)
IMO either:
#define _PORT_TX_DFLEXDPMLE10x008C0
#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + _PORT_TX_DFLEXDPMLE1)
or just:
#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
BR,
Jani.
>> > #define DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
>> > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>> >
>> > @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>> >
>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> >
>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>> >
>> > -#define PORT_TX_DFLEXDPSP_MMIO(0x1638A0)
>> > +#define PORT_TX_DFLEXDPSP_MMIO(FIA1_BASE +
>> > PORT_TX_DFLEXDPSP_OFFSET)
>> > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
>> > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
>> > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>> > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>> > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>> >
>> > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
>> > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
>> > PORT_TX_DFLEXDPPMS_OFFSET)
>> > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 <<
>> > (tc_port))
>> >
>> > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
>> > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE +
>> > PORT_TX_DFLEXDPCSSS_OFFSET)
>> > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 <<
>> > (tc_port))
>> >
>> > #endif /* _I915_REG_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51785/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5059 -> Patchwork_10656 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51785/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10656 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1 Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (48 -> 43) == Additional (1): fi-pnv-d510 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005 == Build changes == * Linux: CI_DRM_5059 -> Patchwork_10656 CI_DRM_5059: ca3747e473d592e64dab2e82e33a874015179ce5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4701: 3aedf1b000e27abfa1bf179205a81efe2b76a508 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10656: b8dd8c515719b26d330775671a302380e9bd1ffb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b8dd8c515719 drm/dp: Define payload size for DP SDP PPS packet 07201a0a9252 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported a4f0f127a021 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC a97d52d54ad6 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 5c906a6b94e5 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 1b63c518d4b6 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 433daab7b536 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10656/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
On Wed, 31 Oct 2018, Madhav Chauhan wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> This patch programs maximum size of the payload transmitted
>> from peripheral back to the host processor using short packet
>> as a part of panel programming.
>>
>> v2: Rebase
>>
>> v3 by Jani:
>> - Add FIXME note.
>
> Looks OK to me.
Thanks, pushed patches 1-3 to dinq.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 33 +
>> 1 file changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index 216a1753d246..9c424adc8b75 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -25,6 +25,7 @@
>>* Jani Nikula
>>*/
>>
>> +#include
>> #include "intel_dsi.h"
>>
>> static enum transcoder dsi_port_to_transcoder(enum port port)
>> @@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
>> *encoder,
>> gen11_dsi_configure_transcoder(encoder, pipe_config);
>> }
>>
>> +static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>> +{
>> +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +struct mipi_dsi_device *dsi;
>> +enum port port;
>> +enum transcoder dsi_trans;
>> +u32 tmp;
>> +int ret;
>> +
>> +/* set maximum return packet size */
>> +for_each_dsi_port(port, intel_dsi->ports) {
>> +dsi_trans = dsi_port_to_transcoder(port);
>> +
>> +/*
>> + * FIXME: This uses the number of DW's currently in the payload
>> + * receive queue. This is probably not what we want here.
>> + */
>> +tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
>> +tmp &= NUMBER_RX_PLOAD_DW_MASK;
>> +/* multiply "Number Rx Payload DW" by 4 to get max value */
>> +tmp = tmp * 4;
>> +dsi = intel_dsi->dsi_hosts[port]->device;
>> +ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
>> +if (ret < 0)
>> +DRM_ERROR("error setting max return pkt size%d\n", tmp);
>> +}
>> +}
>> +
>> static void __attribute__((unused))
>> gen11_dsi_pre_enable(struct intel_encoder *encoder,
>> const struct intel_crtc_state *pipe_config,
>> @@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
>> /* step4: enable DSI port and DPHY */
>> gen11_dsi_enable_port_and_phy(encoder, pipe_config);
>>
>> +/* step5: program and powerup panel */
>> +gen11_dsi_powerup_panel(encoder);
>> +
>> /* step6c: configure transcoder timings */
>> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>>
>
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v8 04/38] drm/i915/icl: Power on DSI panel
On Tue, 30 Oct 2018, Jani Nikula wrote:
> From: Madhav Chauhan
>
> This patch execute poweron, deassert reset, display on
> VBT sequences and send TURN_ON DSI command to panel for
> powering it up.
>
> Signed-off-by: Madhav Chauhan
> Reviewed-by: Jani Nikula
> Signed-off-by: Jani Nikula
Pushed to dinq.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9c424adc8b75..d9c91001f107 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -664,6 +664,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
> *encoder)
> if (ret < 0)
> DRM_ERROR("error setting max return pkt size%d\n", tmp);
> }
> +
> + /* panel power on related mipi dsi vbt sequences */
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
> + intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> }
>
> static void __attribute__((unused))
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v3] mm, drm/i915: mark pinned shmemfs pages as unevictable
Quoting Kuo-Hsin Yang (2018-10-31 08:19:45) > The i915 driver uses shmemfs to allocate backing storage for gem > objects. These shmemfs pages can be pinned (increased ref count) by > shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan > wastes a lot of time scanning these pinned pages. In some extreme case, > all pages in the inactive anon lru are pinned, and only the inactive > anon lru is scanned due to inactive_ratio, the system cannot swap and > invokes the oom-killer. Mark these pinned pages as unevictable to speed > up vmscan. > > Add check_move_lru_page() to move page to appropriate lru list. > > This patch was inspired by Chris Wilson's change [1]. > > [1]: https://patchwork.kernel.org/patch/9768741/ > > Cc: Chris Wilson > Cc: Michal Hocko > Cc: Joonas Lahtinen > Cc: Peter Zijlstra > Cc: Andrew Morton > Cc: Dave Hansen > Signed-off-by: Kuo-Hsin Yang > --- > The previous mapping_set_unevictable patch is worse on gem_syslatency > because it defers to vmscan to move these pages to the unevictable list > and the test measures latency to allocate 2MiB pages. This performance > impact can be solved by explicit moving pages to the unevictable list in > the i915 function. > > Chris, can you help to run the "igt/benchmarks/gem_syslatency -t 120 -b -m" > test with this patch on your testing machine? I tried to run the test on > a Celeron N4000, 4GB Ram machine. The mean value with this patch is > similar to that with the mlock patch. Will do. As you are confident, I'll try a few different machines. :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] sysfs: constify sysfs create/remove files harder
On Tue, 16 Oct 2018, Greg Kroah-Hartman wrote: > On Tue, Oct 16, 2018 at 03:10:24PM +0300, Jani Nikula wrote: >> On Tue, 16 Oct 2018, Greg Kroah-Hartman wrote: >> > On Tue, Oct 16, 2018 at 02:38:53PM +0300, Jani Nikula wrote: >> >> On Tue, 16 Oct 2018, Greg Kroah-Hartman >> >> wrote: >> >> > On Thu, Oct 04, 2018 at 05:37:49PM +0300, Jani Nikula wrote: >> >> >> Let the passed in array be const (and thus placed in rodata) instead of >> >> >> a mutable array of const pointers. >> >> >> >> >> >> Cc: Greg Kroah-Hartman >> >> >> Cc: "Rafael J. Wysocki" >> >> >> Signed-off-by: Jani Nikula >> >> >> --- >> >> >> fs/sysfs/file.c | 4 ++-- >> >> >> include/linux/sysfs.h | 8 >> >> >> 2 files changed, 6 insertions(+), 6 deletions(-) >> >> > >> >> > Reviewed-by: Greg Kroah-Hartman >> >> >> >> Thanks; who should pick them up? >> > >> > I could pick the first one up, but as you need this for a drm patch, >> > both should probably go through that tree, right? >> >> I can pick them both if it doesn't bother you that the sysfs parts will >> be merged in the merge window for v4.21 i.e. the change would be in drm >> trees for an entire release cycle. We've been done for v4.20 merge >> window for a while now. > > No objection from me. Argh, I dropped the ball a bit. May I take that as an ack to merge via drm-intel? I try to be careful not to assume acks and reviews. Thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.
v2 by Jani:
- squash the credit wait helpers patch with the first user
- pass dev_priv to the credit wait helpers
- bikeshed credit helper names
- wait for *at least* the current maximum number of credits
- indentation fix
- add helpers for credits available
This is good optimization, thanks. Looks good.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d9c91001f107..0f0447b6b1be 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,6 +28,36 @@
#include
#include "intel_dsi.h"
+static inline int header_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ >> FREE_HEADER_CREDIT_SHIFT;
+}
+
+static inline int payload_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ >> FREE_PLOAD_CREDIT_SHIFT;
+}
+
+static void wait_for_header_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
+ MAX_HEADER_CREDIT, 100))
+ DRM_ERROR("DSI header credits not released\n");
+}
+
+static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
+enum transcoder dsi_trans)
+{
+ if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
+ MAX_PLOAD_CREDIT, 100))
+ DRM_ERROR("DSI payload credits not released\n");
+}
+
static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
@@ -36,6 +66,47 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
return TRANSCODER_DSI_1;
}
+static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ int ret;
+
+ /* wait for header/payload credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ wait_for_payload_credits(dev_priv, dsi_trans);
+ }
+
+ /* send nop DCS command */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+ dsi->channel = 0;
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0)
+ DRM_ERROR("error sending DCS NOP command\n");
+ }
+
+ /* wait for header credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ }
+
+ /* wait for LP TX in progress bit to be cleared */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LPTX_IN_PROGRESS), 20))
+ DRM_ERROR("LPTX bit not cleared\n");
+ }
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -671,6 +742,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+
+ /* ensure all panel commands dispatched before enabling transcoder */
+ wait_for_cmds_dispatched_to_panel(encoder);
}
static
Re: [Intel-gfx] [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Thanks for catching this, it has to be low.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f7f48ff147d0..644ad7475920 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -777,6 +777,29 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
+static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* disable transcoder */
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ tmp &= ~PIPECONF_ENABLE;
+ I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+ /* wait for transcoder to be disabled */
+ if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE, 0, 50))
+ DRM_ERROR("DSI trancoder not disabled\n");
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -787,4 +810,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step1: turn off backlight */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_panel_disable_backlight(old_conn_state);
+
+ /* step2d,e: disable transcoder and wait */
+ gen11_dsi_disable_transcoder(encoder);
}
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Re: [Intel-gfx] [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit definitions
Ok. I was little confused with BSPEC description "HW will set this bit,
SW must clear it with a write of 1b"
meaning timeout will happen (reverse behavior) when bit is '0' :).
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..8d089ef848b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10533,6 +10533,49 @@ enum skl_power_gate {
#define LINK_ULPS_TYPE_LP11 (1 << 8)
#define LINK_ENTER_ULPS (1 << 0)
+/* DSI timeout registers */
+#define _DSI_HSTX_TO_0 0x6b044
+#define _DSI_HSTX_TO_1 0x6b844
+#define DSI_HSTX_TO(tc)_MMIO_DSI(tc, \
+ _DSI_HSTX_TO_0,\
+ _DSI_HSTX_TO_1)
+#define HSTX_TIMEOUT_VALUE_MASK (0x << 16)
+#define HSTX_TIMEOUT_VALUE_SHIFT 16
+#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
+#define HSTX_TIMED_OUT(1 << 0)
+
+#define _DSI_LPRX_HOST_TO_00x6b048
+#define _DSI_LPRX_HOST_TO_10x6b848
+#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
+ _DSI_LPRX_HOST_TO_0,\
+ _DSI_LPRX_HOST_TO_1)
+#define LPRX_TIMED_OUT(1 << 16)
+#define LPRX_TIMEOUT_VALUE_MASK (0x << 0)
+#define LPRX_TIMEOUT_VALUE_SHIFT 0
+#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
+
+#define _DSI_PWAIT_TO_00x6b040
+#define _DSI_PWAIT_TO_10x6b840
+#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
+ _DSI_PWAIT_TO_0,\
+ _DSI_PWAIT_TO_1)
+#define PRESET_TIMEOUT_VALUE_MASK (0x << 16)
+#define PRESET_TIMEOUT_VALUE_SHIFT16
+#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
+#define PRESPONSE_TIMEOUT_VALUE_MASK (0x << 0)
+#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
+#define PRESPONSE_TIMEOUT_VALUE(x)((x) << 0)
+
+#define _DSI_TA_TO_0 0x6b04c
+#define _DSI_TA_TO_1 0x6b84c
+#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
+ _DSI_TA_TO_0,\
+ _DSI_TA_TO_1)
+#define TA_TIMED_OUT (1 << 16)
+#define TA_TIMEOUT_VALUE_MASK (0x << 0)
+#define TA_TIMEOUT_VALUE_SHIFT0
+#define TA_TIMEOUT_VALUE(x) ((x) << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL(dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL(dev_priv->mipi_mmio_base + 0xb884)
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Re: [Intel-gfx] [PATCH v3] mm, drm/i915: mark pinned shmemfs pages as unevictable
On Wed, Oct 31, 2018 at 5:42 PM Chris Wilson wrote: > Will do. As you are confident, I'll try a few different machines. :) > -Chris Great! Thanks for your help. :) Vovo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Forward Error Correction (rev4)
== Series Details == Series: Forward Error Correction (rev4) URL : https://patchwork.freedesktop.org/series/47848/ State : failure == Summary == Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c). error: could not build fake ancestor Patch failed at 0001 i915/dp/fec: Cache the FEC_CAPABLE DPCD register Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and allow the link to enter into LP state.
LP RX: Monitor the length of LP receptions from Peripheral. If timeout
happens then host will drive the stop state onto all data lanes (only
Data Lane 0 should be receiving anything from the Peripheral). This
effectively takes back ownership of the bus transmit in the HS state.
TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
BTA sequence should complete within a bounded amount of time, with
peripheral acknowledging BTA by driving the stop state.
v2 by Jani:
- Rebase
- Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
- Squash HX TX, LP RX and TA timeout into one patch
- Fix bspec mode set sequence reference
- Add FIXME about two timeouts
Looks fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 52
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ac22c74ae146..fd82f349ced9 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
+
+ /*
+* escape clock count calculation:
+* BYTE_CLK_COUNT = TIME_NS/(8 * UI)
+* UI (nsec) = (10^6)/Bitrate
+* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
+* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
+*/
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) *
1000;
+ mul = 8 * 100;
+ hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
+divisor);
+ lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
+ ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* program hst_tx_timeout */
+ tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
+ tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
+ tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
+ I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_CALIB_TO */
+
+ /* program lp_rx_host timeout */
+ tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
+ tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
+ tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
+ I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_PWAIT_TO */
+
+ /* program turn around timeout */
+ tmp = I915_READ(DSI_TA_TO(dsi_trans));
+ tmp &= ~TA_TIMEOUT_VALUE_MASK;
+ tmp |= TA_TIMEOUT_VALUE(ta_timeout);
+ I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
+ }
+}
+
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
@@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* setup D-PHY timings */
gen11_dsi_setup_dphy_timings(encoder);
+ /* step 4h: setup DSI protocol timeouts */
+ gen11_dsi_setup_timeouts(encoder);
+
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 10fd1582a8e2..f2a3ddedcc5d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -95,6 +95,7 @@ struct intel_dsi {
u16 lp_byte_clk;
/* timeouts in byte clocks */
+ u16 hs_tx_timeout;
u16 lp_rx_timeout;
u16 turn_arnd_val;
u16 rst_timer_val;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index cca071406c25..80bd56e96143 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -799,6 +799,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
intel_dsi->escape_clk_div
[Intel-gfx] [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
The device info offset arrays for unevenly spaced register offsets is great for widely used registers. However, the palette registers are only used in one function, i9xx_load_luts_internal(), and only for GMCH platforms, wasting device info. Replace palette_offsets with _PICK() in palette register definition. While the use of _PICK() does not check for pipe C existence, neither does the current offset array usage, and leads to bogus address when pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads to a sensible register offset, just non-existing on non-CHV. Either way, this shouldn't happen anyway. Remove unused old palette macros while at it. Bloat-o-meter results below for completeness. add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184) Function old new delta i9xx_load_luts_internal 394 483 +89 i915_driver_load51035107 +4 g4x_pre_enable_dp378 379 +1 intel_engines_init_mmio 11171116 -1 intel_engine_lookup_user 47 46 -1 hdmi_port_clock_valid310 309 -1 gen11_irq_handler707 706 -1 intel_device_info_dump_runtime 329 311 -18 intel_device_info_runtime_init 51664910-256 Total: Before=918650, After=918466, chg -0.02% add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576) Data old new delta intel_valleyview_info200 188 -12 intel_skylake_gt4_info 200 188 -12 intel_skylake_gt3_info 200 188 -12 intel_skylake_gt2_info 200 188 -12 intel_skylake_gt1_info 200 188 -12 intel_sandybridge_m_gt2_info 200 188 -12 intel_sandybridge_m_gt1_info 200 188 -12 intel_sandybridge_d_gt2_info 200 188 -12 intel_sandybridge_d_gt1_info 200 188 -12 intel_pineview_info 200 188 -12 intel_kabylake_gt3_info 200 188 -12 intel_kabylake_gt2_info 200 188 -12 intel_kabylake_gt1_info 200 188 -12 intel_ivybridge_q_info 200 188 -12 intel_ivybridge_m_gt2_info 200 188 -12 intel_ivybridge_m_gt1_info 200 188 -12 intel_ivybridge_d_gt2_info 200 188 -12 intel_ivybridge_d_gt1_info 200 188 -12 intel_ironlake_m_info200 188 -12 intel_ironlake_d_info200 188 -12 intel_icelake_11_info200 188 -12 intel_i965gm_info200 188 -12 intel_i965g_info 200 188 -12 intel_i945gm_info200 188 -12 intel_i945g_info 200 188 -12 intel_i915gm_info200 188 -12 intel_i915g_info 200 188 -12 intel_i865g_info 200 188 -12 intel_i85x_info 200 188 -12 intel_i845g_info 200 188 -12 intel_i830_info 200 188 -12 intel_haswell_gt3_info 200 188 -12 intel_haswell_gt2_info 200 188 -12 intel_haswell_gt1_info 200 188 -12 intel_gm45_info 200 188 -12 intel_geminilake_info200 188 -12 intel_g45_info 200 188 -12 intel_g33_info 200 188 -12 intel_coffeelake_gt3_info200 188 -12 intel_coffeelake_gt2_info200 188 -12 intel_coffeelake_gt1_info200 188 -12 intel_cherryview_info200 188 -12 intel_cannonlake_info200 188 -12 intel_broxton_info 200 188 -12 intel_broadwell_rsvd_info200 188 -12 intel_broadwell_gt3_info 200 188 -12 intel_broadwell_gt2_info 200 188 -12 intel_broadwell_gt1_info 200 188 -12 Total: Before=195529, After=194953, chg -0.29% Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_pci.c | 7 ++- drivers/gpu/drm/i915/i915_reg.h | 16 +++- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files change
[Intel-gfx] [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers
Try to make it slightly less of an eye sore. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d0145967482..22db12b070af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -157,20 +157,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
-#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
-#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
-#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
-#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
-#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
-#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
-#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
-#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
-#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
-#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
-#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
-#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
-#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
+#define _PLANE(plane, a, b)_PICK_EVEN(plane, a, b)
+#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
+#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
+#define _PLL(pll, a, b)_PICK_EVEN(pll, a, b)
+
+#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
+#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
+#define _MMIO_TRANS(tran, a, b)_MMIO(_TRANS(tran, a, b))
+#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
+#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+
+#define _PHY3(phy, ...)_PICK(phy, __VA_ARGS__)
+
+#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
--
2.11.0
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[Intel-gfx] [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
Minor semantic nit, no functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d97cf98e3edf..0d0145967482 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -160,7 +160,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) -#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) #define _PORT(port, a, b) _PICK_EVEN(port, a, b) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: also group device info array helper macros with others
Keep the register choosing macros together. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 22db12b070af..6327a5f02da5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -175,6 +175,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+/*
+ * Device info offset array based helpers for groups of registers with unevenly
+ * spaced base offsets.
+ */
+#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe]
- \
+
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
+
dev_priv->info.display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg)
_MMIO(dev_priv->info.trans_offsets[(pipe)] - \
+
dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
+
dev_priv->info.display_mmio_offset)
+#define _CURSOR2(pipe, reg)
_MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
+
dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
+
dev_priv->info.display_mmio_offset)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask))\
@@ -4052,10 +4066,6 @@ enum {
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
-#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
- dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
@@ -5624,10 +5634,6 @@ enum {
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
-#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
- dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe)_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -6075,10 +6081,6 @@ enum {
#define _CURBBASE_IVB 0x71084
#define _CURBPOS_IVB 0x71088
-#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
- dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
--
2.11.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2)
== Series Details == Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2) URL : https://patchwork.freedesktop.org/series/25337/ State : warning == Summary == $ dim checkpatch origin/drm-tip c5bc6a6a53e8 mm, drm/i915: mark pinned shmemfs pages as unevictable -:126: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #126: FILE: include/linux/swap.h:377: +extern void check_move_lru_page(struct page *page); total: 0 errors, 0 warnings, 1 checks, 112 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51785/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5059_full -> Patchwork_10656_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10656_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@rcs0-none: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) +1 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) +2 igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x64-sliding: shard-glk: PASS -> FAIL (fdo#103232) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: PASS -> FAIL (fdo#103167) +5 igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_panel_fitting@legacy: shard-skl: NOTRUN -> FAIL (fdo#105456) igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +3 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) igt@pm_rpm@pc8-residency: shard-skl: SKIP -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106887, fdo#103665, fdo#106023) -> PASS igt@gem_workarounds@suspend-resume: shard-kbl: DMESG-WARN (fdo#108566) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_chv_cursor_fail@pipe-a-128x128-left-edge: shard-skl: FAIL (fdo#104671) -> PASS igt@kms_cursor_crc@cursor-128x42-onscreen: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled: shard-skl: FAIL (fdo#103184) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: shard-apl: INCOMPLETE (fdo#103927) -> SKIP igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +2 igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456 fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108566 https://bugs.freedesktop.org/show_bug.cgi?id=108566 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5059 -> Patchwork_10656
Re: [Intel-gfx] [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
On Wed, 31 Oct 2018, Madhav Chauhan wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> Program the timeout values (in escape clock) for HS TX, LP RX and TA
>> timeout.
>>
>> HX TX: Ensure that host does not continuously transmit in the HS
>> state. If this timer expires, then host will gracefully end its HS
>> transmission and allow the link to enter into LP state.
>>
>> LP RX: Monitor the length of LP receptions from Peripheral. If timeout
>> happens then host will drive the stop state onto all data lanes (only
>> Data Lane 0 should be receiving anything from the Peripheral). This
>> effectively takes back ownership of the bus transmit in the HS state.
>>
>> TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
>> BTA sequence should complete within a bounded amount of time, with
>> peripheral acknowledging BTA by driving the stop state.
>>
>> v2 by Jani:
>> - Rebase
>> - Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
>> - Squash HX TX, LP RX and TA timeout into one patch
>> - Fix bspec mode set sequence reference
>> - Add FIXME about two timeouts
>
> Looks fine.
Thanks, pushed up to and including this patch.
BR,
Jani.
>
> Regards,
> Madhav
>
>> Signed-off-by: Madhav Chauhan
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 52
>>
>> drivers/gpu/drm/i915/intel_dsi.h | 1 +
>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
>> 3 files changed, 54 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index ac22c74ae146..fd82f349ced9 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct
>> intel_encoder *encoder)
>> }
>> }
>>
>> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>> +{
>> +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +enum port port;
>> +enum transcoder dsi_trans;
>> +u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
>> +
>> +/*
>> + * escape clock count calculation:
>> + * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
>> + * UI (nsec) = (10^6)/Bitrate
>> + * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>> + * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
>> + */
>> +divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) *
>> 1000;
>> +mul = 8 * 100;
>> +hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>> + divisor);
>> +lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
>> +ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
>> +
>> +for_each_dsi_port(port, intel_dsi->ports) {
>> +dsi_trans = dsi_port_to_transcoder(port);
>> +
>> +/* program hst_tx_timeout */
>> +tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
>> +tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
>> +tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
>> +I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
>> +
>> +/* FIXME: DSI_CALIB_TO */
>> +
>> +/* program lp_rx_host timeout */
>> +tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
>> +tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
>> +tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
>> +I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
>> +
>> +/* FIXME: DSI_PWAIT_TO */
>> +
>> +/* program turn around timeout */
>> +tmp = I915_READ(DSI_TA_TO(dsi_trans));
>> +tmp &= ~TA_TIMEOUT_VALUE_MASK;
>> +tmp |= TA_TIMEOUT_VALUE(ta_timeout);
>> +I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
>> +}
>> +}
>> +
>> static void
>> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>>const struct intel_crtc_state *pipe_config)
>> @@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
>> *encoder,
>> /* setup D-PHY timings */
>> gen11_dsi_setup_dphy_timings(encoder);
>>
>> +/* step 4h: setup DSI protocol timeouts */
>> +gen11_dsi_setup_timeouts(encoder);
>> +
>> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> gen11_dsi_configure_transcoder(encoder, pipe_config);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>> b/drivers/gpu/drm/i915/intel_dsi.h
>> index 10fd1582a8e2..f2a3ddedcc5d 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -95,6 +95,7 @@ struct intel_dsi {
>> u16 lp_byte_clk;
>>
>> /* timeouts in byte clocks */
>> +u16 hs_tx_timeout;
>> u16 lp_rx_timeout;
>> u16 turn_arnd_val;
>> u16 rst_timer_val;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> b/drivers/gpu/drm/i915/intel_dsi_vbt.
Re: [Intel-gfx] [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
- s/intel_gen11_dsi_init/icl_dsi_init/g
Changes looks fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
drivers/gpu/drm/i915/intel_bios.c| 12 ++--
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index fd82f349ced9..01f422df8c23 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step4: disable IO power */
gen11_dsi_disable_io_power(encoder);
}
+
+void icl_dsi_init(struct drm_i915_private *dev_priv)
+{
+ enum port port;
+
+ if (!intel_bios_is_dsi_present(dev_priv, &port))
+ return;
+}
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..5fa2133f801d 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv,
dvo_port = child->dvo_port;
- switch (dvo_port) {
- case DVO_PORT_MIPIA:
- case DVO_PORT_MIPIC:
+ if (dvo_port == DVO_PORT_MIPIA ||
+ (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
+ (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
if (port)
*port = dvo_port - DVO_PORT_MIPIA;
return true;
- case DVO_PORT_MIPIB:
- case DVO_PORT_MIPID:
+ } else if (dvo_port == DVO_PORT_MIPIB ||
+ dvo_port == DVO_PORT_MIPIC ||
+ dvo_port == DVO_PORT_MIPID) {
DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
port_name(dvo_port - DVO_PORT_MIPIA));
- break;
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3cadc09f859..1d46f06ede37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_D);
intel_ddi_init(dev_priv, PORT_E);
intel_ddi_init(dev_priv, PORT_F);
+ icl_dsi_init(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 268afb6d2746..3081cca1a151 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct
intel_digital_port *intel_dig_port);
/* vlv_dsi.c */
void vlv_dsi_init(struct drm_i915_private *dev_priv);
+/* icl_dsi.c */
+void icl_dsi_init(struct drm_i915_private *dev_priv);
+
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector);
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2)
== Series Details == Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2) URL : https://patchwork.freedesktop.org/series/25337/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5061 -> Patchwork_10658 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10658 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10658, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/25337/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10658: === IGT changes === Warnings igt@drv_selftest@live_execlists: fi-icl-u2: PASS -> SKIP +2 igt@drv_selftest@live_guc: fi-icl-u: PASS -> SKIP +2 igt@pm_rpm@module-reload: fi-hsw-4770r: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10658 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425, fdo#107924) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS Warnings igt@drv_selftest@live_contexts: fi-icl-u2: DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108315) fi-icl-u: DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108315) fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5061 -> Patchwork_10658 CI_DRM_5061: 70b3439196839087be83ffe4b6f43ff5b1218668 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10658: c5bc6a6a53e843350fd800e575deb171344853d3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c5bc6a6a53e8 mm, drm/i915: mark pinned shmemfs pages as unevictable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10658/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.
v2 by Jani:
- Drop GEN11 prefix from encoder name
- Drop extra parenthesis
- Drop extra local variable
- Squash encoder power domain here
Looks good to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 96 ++
1 file changed, 88 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 01f422df8c23..a117ecc6c5a3 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -799,10 +799,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
wait_for_cmds_dispatched_to_panel(encoder);
}
-static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
-const struct intel_crtc_state *pipe_config,
-const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *pipe_config,
+const struct drm_connector_state *conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -945,10 +944,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
}
}
-static void __attribute__((unused)) gen11_dsi_disable(
- struct intel_encoder *encoder,
- const struct intel_crtc_state *old_crtc_state,
- const struct drm_connector_state *old_conn_state)
+static void gen11_dsi_disable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -972,10 +970,92 @@ static void __attribute__((unused)) gen11_dsi_disable(
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ intel_encoder_destroy(encoder);
+}
+
+static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
+ .destroy = gen11_dsi_encoder_destroy,
+};
+
+static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = &dev_priv->drm;
+ struct intel_dsi *intel_dsi;
+ struct intel_encoder *encoder;
+ struct intel_connector *intel_connector;
+ struct drm_connector *connector;
+ struct drm_display_mode *scan, *fixed_mode = NULL;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, &port))
return;
+
+ intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+ if (!intel_dsi)
+ return;
+
+ intel_connector = intel_connector_alloc();
+ if (!intel_connector) {
+ kfree(intel_dsi);
+ return;
+ }
+
+ encoder = &intel_dsi->base;
+ intel_dsi->attached_connector = intel_connector;
+ connector = &intel_connector->base;
+
+ /* register DSI encoder with DRM subsystem */
+ drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
+DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
+
+ encoder->pre_enable = gen11_dsi_pre_enable;
+ encoder->disable = gen11_dsi_disable;
+ encoder->port = port;
+ encoder->type = INTEL_OUTPUT_DSI;
+ encoder->cloneable = 0;
+ encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+
+ /* register DSI connector with DRM subsystem */
+ drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ /* attach connector to encoder */
+ intel_connector_attach_encoder(intel_connector, encoder);
+
+ /* fill mode info from VBT */
+ mutex_lock(&dev->mode_config.mutex);
+ intel_dsi_vbt_get_modes(intel_dsi);
+ list_for_each_entry(scan, &connector->probed_modes, head) {
+ if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+ fixed_mode = drm_mode_duplicate(dev, scan);
+ break;
+ }
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+
+ if (!fixed_mode) {
+ DRM_ERROR("DSI fixed mode info missing\n")
Re: [Intel-gfx] [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch allocates DSI host structure for each
DSI port available on gen11 and register them with
DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this. This patch also fills
MIPI config block info from VBT to local structure.
v2 by Jani:
- indentation
Looks fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a117ecc6c5a3..d0c60d402dfe 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -982,6 +982,23 @@ static const struct drm_encoder_funcs
gen11_dsi_encoder_funcs = {
static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
};
+static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
+struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
+struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
+ .attach = gen11_dsi_host_attach,
+ .detach = gen11_dsi_host_detach,
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
@@ -1052,6 +1069,21 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ struct intel_dsi_host *host;
+
+ host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops,
port);
+ if (!host)
+ goto err;
+
+ intel_dsi->dsi_hosts[port] = host;
+ }
+
+ if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
+ DRM_DEBUG_KMS("no device found\n");
+ goto err;
+ }
+
return;
err:
___
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Re: [Intel-gfx] [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
v2 change are fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef848b2..639667d0fb00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10523,6 +10523,28 @@ enum skl_power_gate {
#define MAX_HEADER_CREDIT0x10
#define MAX_PLOAD_CREDIT 0x40
+#define _DSI_CMD_TXHDR_0 0x6b100
+#define _DSI_CMD_TXHDR_1 0x6b900
+#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXHDR_0,\
+ _DSI_CMD_TXHDR_1)
+#define PAYLOAD_PRESENT (1 << 31)
+#define LP_DATA_TRANSFER (1 << 30)
+#define VBLANK_FENCE (1 << 29)
+#define PARAM_WC_MASK (0x << 8)
+#define PARAM_WC_LOWER_SHIFT 8
+#define PARAM_WC_UPPER_SHIFT 16
+#define VC_MASK (0x3 << 6)
+#define VC_SHIFT 6
+#define DT_MASK (0x3f << 0)
+#define DT_SHIFT 0
+
+#define _DSI_CMD_TXPYLD_0 0x6b104
+#define _DSI_CMD_TXPYLD_1 0x6b904
+#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXPYLD_0,\
+ _DSI_CMD_TXPYLD_1)
+
#define _DSI_LP_MSG_0 0x6b0d8
#define _DSI_LP_MSG_1 0x6b8d8
#define DSI_LP_MSG(tc)_MMIO_DSI(tc, \
___
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Re: [Intel-gfx] [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit available helper
- Use int for free_credits
Changes looks fine, this also has squashing of some of the patches
for sending packet header. That info can be added in "v2 details"
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d0c60d402dfe..c7b77cd81e45 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,44 @@ static void wait_for_cmds_dispatched_to_panel(struct
intel_encoder *encoder)
}
}
+static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt, bool enable_lpdt)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ u32 tmp;
+ int free_credits;
+
+ /* check if header credit available */
+ free_credits = header_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("send pkt header failed, not enough hdr credits\n");
+ return -1;
+ }
+
+ tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+
+ if (pkt.payload)
+ tmp |= PAYLOAD_PRESENT;
+ else
+ tmp &= ~PAYLOAD_PRESENT;
+
+ tmp &= ~VBLANK_FENCE;
+
+ if (enable_lpdt)
+ tmp |= LP_DATA_TRANSFER;
+
+ tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
+ tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
+ tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
+ tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
+ tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
+ I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -994,9 +1032,33 @@ static int gen11_dsi_host_detach(struct mipi_dsi_host
*host,
return 0;
}
+static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
+ const struct mipi_dsi_msg *msg)
+{
+ struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+ struct mipi_dsi_packet dsi_pkt;
+ ssize_t ret;
+ bool enable_lpdt = false;
+
+ ret = mipi_dsi_create_packet(&dsi_pkt, msg);
+ if (ret < 0)
+ return ret;
+
+ if (msg->flags & MIPI_DSI_MSG_USE_LPM)
+ enable_lpdt = true;
+
+ /* send packet header */
+ ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
.attach = gen11_dsi_host_attach,
.detach = gen11_dsi_host_detach,
+ .transfer = gen11_dsi_host_transfer,
};
void icl_dsi_init(struct drm_i915_private *dev_priv)
___
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[Intel-gfx] [v2 1/2] drm: Add colorspace property
This patch adds a colorspace property enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace enum to incorporate both HDMI and DP supported
colorspaces. Also, added a default option for colorspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_uapi.c | 4
drivers/gpu/drm/drm_connector.c | 44 +++
include/drm/drm_connector.h | 7 +++
include/drm/drm_mode_config.h | 6 ++
include/uapi/drm/drm_mode.h | 24 +
5 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index d5b7f31..9e1d46b 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -721,6 +721,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
state->content_type = val;
+ } else if (property == config->colorspace_property) {
+ state->colorspace = val;
} else if (property == connector->scaling_mode_property) {
state->scaling_mode = val;
} else if (property == connector->content_protection_property) {
@@ -795,6 +797,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->picture_aspect_ratio;
} else if (property == config->content_type_property) {
*val = state->content_type;
+ } else if (property == config->colorspace_property) {
+ *val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index aa18b1d..5ad52a0 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -826,6 +826,38 @@ int drm_display_info_set_bus_formats(struct
drm_display_info *info,
};
DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
+static const struct drm_prop_enum_list colorspace[] = {
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "601" },
+ { COLORIMETRY_ITU_709, "709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { COLORIMETRY_S_YCC_601, "s601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { COLORIMETRY_ADOBE_YCC_601, "adobe601" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_ADOBE_RGB, "adobe_rgb" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_RGB, "BT2020_rgb" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_YCC, "BT2020_ycc" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_CYCC, "BT2020_cycc" },
+ /* DP MSA Colorimetry */
+ { COLORIMETRY_Y_CBCR_ITU_601, "YCBCR_ITU_601" },
+ { COLORIMETRY_Y_CBCR_ITU_709, "YCBCR_ITU_709" },
+ { COLORIMETRY_SRGB, "SRGB" },
+ { COLORIMETRY_RGB_WIDE_GAMUT, "RGB Wide Gamut" },
+ { COLORIMETRY_SCRGB, "SCRGB" },
+ { COLORIMETRY_DCI_P3, "DCIP3" },
+ { COLORIMETRY_CUSTOM_COLOR_PROFILE, "Custom Proflie" },
+ /* FOR HD 720p+, Default Colorimetry is based on ITU-R BT.709 */
+ { COLORIMETRY_DEFAULT, "Default: ITU_709" },
+};
+
/**
* DOC: standard connector properties
*
@@ -972,6 +1004,12 @@ int drm_display_info_set_bus_formats(struct
drm_display_info *info,
* can also expose this property to external outputs, in which case they
* must support "None", which should be the default (since external screens
* have a built-in scaler).
+ *
+ * colorspace:
+ * This property helps select a suitable colorspace based on the sink
+ * capability. Modern sink devices support wider gamut like BT2020.
+ * This helps switch to BT2020 mode if the BT2020 encoded video stream
+ * is being played by the user, same for any other colorspace.
*/
int drm_connector_create_standard_properties(struct drm_device *dev)
@@ -1020,6 +1058,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace",
+ colorspace, ARRAY_SIZE(colorspace));
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_co
[Intel-gfx] [v2 2/2] drm/i915: Attach colorspace property and enable modeset
This patch attaches the colorspace connector property to the hdmi connector. Based on colorspace change, modeset will be triggered to switch to new colorspace. Based on colorspace property value create an infoframe with appropriate colorspace. This can be used to send an infoframe packet with proper colorspace value set which will help to enable wider color gamut like BT2020 on sink. v2: Merged the changes of creating infoframe as well to this patch as per Maarten's suggestion. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_atomic.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 5 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index a5a2c8f..35ef70a 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -125,6 +125,7 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn, */ if (new_conn_state->force_audio != old_conn_state->force_audio || new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb || + new_state->colorspace != old_state->colorspace || new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || new_conn_state->base.content_type != old_conn_state->base.content_type || new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 129b880..8a41fb3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -486,6 +486,8 @@ static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder, else frame.avi.colorspace = HDMI_COLORSPACE_RGB; + frame.avi.extended_colorimetry = conn_state->colorspace; + drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : @@ -2125,6 +2127,9 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_attach_broadcast_rgb_property(connector); intel_attach_aspect_ratio_property(connector); drm_connector_attach_content_type_property(connector); + drm_object_attach_property(&connector->base, + connector->dev->mode_config.colorspace_property, + COLORIMETRY_ITU_709); connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; } -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 0/2] Add Colorspace connector property interface
This patch series creates a new connector property to program colorspace to sink devices. Modern sink devices support more than 1 type of colorspace like 601, 709, BT2020 etc. This helps to switch based on content type which is to be displayed. The decision lies with compositors as to in which scenarios, a particular colorspace will be picked. This will be helpful mostly to switch to higher gamut colorspaces like BT2020 when the media content is encoded as BT2020. Thereby giving a good visual experience to users. The expectation from userspace is that it should parse the EDID and get supported colorspaces. Use this property and switch to the one supported. Kernel will not give the supported colorspaces since this is panel dependent and our curremt property infrastructure is not supporting it. Have tested this using xrandr by using below command: xrandr --output HDMI2 --set "Colorspace" "BT2020_rgb" v2: Addressed Ville and Maarten's review comments. Merged the 2nd and 3rd patch into one common logical patch. Uma Shankar (2): drm: Add colorspace property drm/i915: Attach colorspace property and enable modeset drivers/gpu/drm/drm_atomic_uapi.c | 4 drivers/gpu/drm/drm_connector.c | 44 + drivers/gpu/drm/i915/intel_atomic.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 5 + include/drm/drm_connector.h | 7 ++ include/drm/drm_mode_config.h | 6 + include/uapi/drm/drm_mode.h | 24 7 files changed, 91 insertions(+) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch adds DSI packet payload to command payload
queue using credit based mechanism for *long* packets.
v2 by Jani:
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j
v2 changes are fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c7b77cd81e45..58774a1ac84b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,33 @@ static void wait_for_cmds_dispatched_to_panel(struct
intel_encoder *encoder)
}
}
+static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
+ u32 len)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ int free_credits;
+ int i, j;
+
+ for (i = 0; i < len; i += 4) {
+ u32 tmp = 0;
+
+ free_credits = payload_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("Payload credit not available\n");
+ return false;
+ }
+
+ for (j = 0; j < min_t(u32, len - i, 4); j++)
+ tmp |= *data++ << 8 * j;
+
+ I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+ }
+
+ return true;
+}
+
static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
struct mipi_dsi_packet pkt, bool enable_lpdt)
{
@@ -145,6 +172,25 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
return 0;
}
+static int dsi_send_pkt_payld(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt)
+{
+ /* payload queue can accept *256 bytes*, check limit */
+ if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
+ DRM_ERROR("payload size exceeds max queue limit\n");
+ return -1;
+ }
+
+ /* load data into command payload queue */
+ if (!add_payld_to_queue(host, pkt.payload,
+ pkt.payload_length)) {
+ DRM_ERROR("adding payload to queue failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1052,6 +1098,17 @@ static ssize_t gen11_dsi_host_transfer(struct
mipi_dsi_host *host,
if (ret < 0)
return ret;
+ /* only long packet contains payload */
+ if (mipi_dsi_packet_format_is_long(msg->type)) {
+ ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
+ if (ret < 0)
+ return ret;
+ }
+
+ //TODO: add payload receive code if needed
+
+ ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
+
return ret;
}
___
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Re: [Intel-gfx] [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Looks fine to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 83612c444eab..0c1f84cca16e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1067,6 +1067,46 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock = pixel_clk;
}
+static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
+ enum pipe *pipe)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+ bool ret = false;
+
+ if (!intel_display_power_get_if_enabled(dev_priv,
+ encoder->power_domain))
+ return false;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ *pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ *pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ *pipe = PIPE_C;
+ break;
+ default:
+ DRM_ERROR("Invalid PIPE input\n");
+ goto out;
+ }
+
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ ret = tmp & PIPECONF_ENABLE;
+ }
+out:
+ intel_display_power_put(dev_priv, encoder->power_domain);
+ return ret;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1166,6 +1206,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
@@ -1177,6 +1218,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
+ intel_connector->get_hw_state = intel_connector_get_hw_state;
/* attach connector to encoder */
intel_connector_attach_encoder(intel_connector, encoder);
___
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[Intel-gfx] [PATCH] drm/syncobj: Mark local add/remove callback functions as static
drivers/gpu/drm/drm_syncobj.c:181:6: warning: no previous prototype for
‘drm_syncobj_add_callback’ [-Wmissing-prototypes]
drivers/gpu/drm/drm_syncobj.c:190:6: warning: no previous prototype for
‘drm_syncobj_remove_callback’ [-Wmissing-prototypes]
Fixing that leads to
drivers/gpu/drm/drm_syncobj.c:181:13: warning: ‘drm_syncobj_add_callback’
defined but not used [-Wunused-function]
so remove the unused drm_syncobj_add_callback() entirely.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_syncobj.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index d3e2335b88f9..4dca5f7e8c4b 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -123,9 +123,9 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file
*file_private,
}
EXPORT_SYMBOL(drm_syncobj_find);
-static struct dma_fence
-*drm_syncobj_find_signal_pt_for_point(struct drm_syncobj *syncobj,
- uint64_t point)
+static struct dma_fence *
+drm_syncobj_find_signal_pt_for_point(struct drm_syncobj *syncobj,
+uint64_t point)
{
struct drm_syncobj_signal_pt *signal_pt;
@@ -178,17 +178,8 @@ static void drm_syncobj_fence_get_or_add_callback(struct
drm_syncobj *syncobj,
mutex_unlock(&syncobj->cb_mutex);
}
-void drm_syncobj_add_callback(struct drm_syncobj *syncobj,
- struct drm_syncobj_cb *cb,
- drm_syncobj_func_t func)
-{
- mutex_lock(&syncobj->cb_mutex);
- drm_syncobj_add_callback_locked(syncobj, cb, func);
- mutex_unlock(&syncobj->cb_mutex);
-}
-
-void drm_syncobj_remove_callback(struct drm_syncobj *syncobj,
-struct drm_syncobj_cb *cb)
+static void drm_syncobj_remove_callback(struct drm_syncobj *syncobj,
+ struct drm_syncobj_cb *cb)
{
mutex_lock(&syncobj->cb_mutex);
list_del_init(&cb->node);
--
2.19.1
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/20] RFT drm/i915/execlists: Flush memory before signaling ELSQ
== Series Details == Series: series starting with [01/20] RFT drm/i915/execlists: Flush memory before signaling ELSQ URL : https://patchwork.freedesktop.org/series/51797/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/icl_dsi.o drivers/gpu/drm/i915/icl_dsi.c: In function ‘gen11_dsi_disable_io_power’: drivers/gpu/drm/i915/icl_dsi.c:935:2: error: too few arguments to function ‘intel_display_power_put’ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_A_IO); ^~~ In file included from drivers/gpu/drm/i915/intel_dsi.h:30:0, from drivers/gpu/drm/i915/icl_dsi.c:29: drivers/gpu/drm/i915/intel_drv.h:2087:6: note: declared here void intel_display_power_put(struct drm_i915_private *dev_priv, ^~~ drivers/gpu/drm/i915/icl_dsi.c:938:3: error: too few arguments to function ‘intel_display_power_put’ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO); ^~~ In file included from drivers/gpu/drm/i915/intel_dsi.h:30:0, from drivers/gpu/drm/i915/icl_dsi.c:29: drivers/gpu/drm/i915/intel_drv.h:2087:6: note: declared here void intel_display_power_put(struct drm_i915_private *dev_priv, ^~~ scripts/Makefile.build:305: recipe for target 'drivers/gpu/drm/i915/icl_dsi.o' failed make[4]: *** [drivers/gpu/drm/i915/icl_dsi.o] Error 1 scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:546: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1052: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915 pvmmio to improve GVTg performance (rev6)
== Series Details == Series: i915 pvmmio to improve GVTg performance (rev6) URL : https://patchwork.freedesktop.org/series/51235/ State : failure == Summary == Applying: drm/i915: introduced pv capability for vgpu error: patch fragment without header at line 38: @@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) error: could not build fake ancestor Patch failed at 0001 drm/i915: introduced pv capability for vgpu Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for RFT drm/i915/execlists: Flush memory before signaling ELSQ
== Series Details == Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ URL : https://patchwork.freedesktop.org/series/51796/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10659 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10659 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10659, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51796/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10659: === IGT changes === Warnings igt@drv_selftest@live_guc: fi-skl-iommu: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_10659 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: fi-skl-iommu: PASS -> INCOMPLETE (fdo#108602) Possible fixes igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: INCOMPLETE (k.org#199541, fdo#105524, fdo#104108) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108602 https://bugs.freedesktop.org/show_bug.cgi?id=108602 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (49 -> 43) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10659 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10659: 354fbf13beadd4b8e6ed3b7fe6fc3d044b4e5739 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 354fbf13bead RFT drm/i915/execlists: Flush memory before signaling ELSQ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10659/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
>-Original Message-
>From: Roper, Matthew D
>Sent: Tuesday, October 30, 2018 4:59 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV
>to
>RGB Conversion
>
>On Fri, Oct 26, 2018 at 03:31:57PM +0530, Uma Shankar wrote:
>> Plane input CSC needs to be enabled to convert frambuffers from YUV to
>> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>> have hardcoded conversion and taken care by the legacy code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> Note: This is currently untested and floated to get an early feedback
>> on the design and implementation for this feature. In parallel, I will
>> test this on actual ICL hardware and confirm with planar formats.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift issue
>> with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> v5: Fixed Matt and Maarten's review comments.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 79
>
>> drivers/gpu/drm/i915/intel_display.c | 23 ---
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 3 files changed, 98 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..681cd13 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
>CSC_RGB_TO_YUV_BV
>> 0x1e08
>>
>> +#define ROFF(x) (((x) & 0x) << 16)
>> +#define GOFF(x) (((x) & 0x) << 0)
>> +#define BOFF(x) (((x) & 0x) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI0x1800
>> +#define PREOFF_YUV_TO_RGB_ME0x1F00
>> +#define PREOFF_YUV_TO_RGB_LO0x1800
>> +
>> /*
>> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>> * format). This macro takes the coefficient we want transformed and
>> the @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
>> return -EINVAL;
>> }
>>
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state) {
>> +struct drm_i915_private *dev_priv =
>> +to_i915(plane_state->base.plane->dev);
>> +struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +enum pipe pipe = crtc->pipe;
>> +struct intel_plane *intel_plane =
>> +to_intel_plane(plane_state->base.plane);
>> +enum plane_id plane = intel_plane->id;
>> +
>> +static const u16 input_csc_matrix[][9] = {
>
>Can you add comments to these indicating the human-readable values they
>translate to?
Sure Matt, will add that.
>> +/* BT.601 full range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT601] = {
>> +0x7AF8, 0x7800, 0x0,
>> +0x8B28, 0x7800, 0x9AC0,
>> +0x0, 0x7800, 0x7DD8,
>> +},
>> +/* BT.709 full range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT709] = {
>> +0x7C98, 0x7800, 0x0,
>> +0x9EF8, 0x7800, 0xABF8,
>> +0x0, 0x7800, 0x7ED8,
>> +},
>> +};
>> +
>> +/* Matrix for Limited Range to Full Range Conversion */
>> +static const u16 input_csc_matrix_lr[][9] = {
>> +/* BT.601 Limted range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT601] = {
>> +0x7CC8, 0x7950, 0x0,
>> +0x8CB8, 0x7918, 0x9C40,
>> +0x0, 0x7918, 0x7FC8,
>
>Are these obtained by scaling the first row (Y-based) by 256/219 and the other
>two rows (Cb and Cr) by 256/224? If so, it looks like you've always rounded
>down, whereas in some cases rounding up gives you a closer value (and matches
>how the bspec seems to have chosen the full range encodings for their example).
Yes, this is how it's done. But the only reason of delta is that you have taken
8 bit max
value as 256, but I am taking it as 255. I feel it should be (1 << bpc ie 8) -
1. If you put that,
the values which you got will match to what I have here. Please let me know if
that's ok.
And thanks for detailed review and useful pointers.
Regards,
Uma Shankar
>[ 0x7CD0, 0x7958,0x0 ]
>[ 0x8CC0, 0x7928, 0x9C4
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Colorspace connector property interface (rev2)
== Series Details == Series: Add Colorspace connector property interface (rev2) URL : https://patchwork.freedesktop.org/series/47132/ State : warning == Summary == $ dim checkpatch origin/drm-tip b716d24947ce drm: Add colorspace property 33d07ea8810b drm/i915: Attach colorspace property and enable modeset -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/intel_hdmi.c:2131: + drm_object_attach_property(&connector->base, + connector->dev->mode_config.colorspace_property, total: 0 errors, 0 warnings, 1 checks, 24 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Colorspace connector property interface (rev2)
== Series Details == Series: Add Colorspace connector property interface (rev2) URL : https://patchwork.freedesktop.org/series/47132/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: Add colorspace property Okay! Commit: drm/i915: Attach colorspace property and enable modeset +drivers/gpu/drm/i915/intel_hdmi.c:489:52: int enum encoder_colorimetry versus +drivers/gpu/drm/i915/intel_hdmi.c:489:52: int enum hdmi_extended_colorimetry +drivers/gpu/drm/i915/intel_hdmi.c:489:52: warning: mixing different enum types ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Tuesday, October 30, 2018 4:25 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV
>to
>RGB Conversion
>
>Op 26-10-18 om 12:01 schreef Uma Shankar:
>> Plane input CSC needs to be enabled to convert frambuffers from YUV to
>> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>> have hardcoded conversion and taken care by the legacy code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> Note: This is currently untested and floated to get an early feedback
>> on the design and implementation for this feature. In parallel, I will
>> test this on actual ICL hardware and confirm with planar formats.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift issue
>> with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> v5: Fixed Matt and Maarten's review comments.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 79
>
>> drivers/gpu/drm/i915/intel_display.c | 23 ---
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 3 files changed, 98 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..681cd13 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
>CSC_RGB_TO_YUV_BV
>> 0x1e08
>>
>> +#define ROFF(x) (((x) & 0x) << 16)
>> +#define GOFF(x) (((x) & 0x) << 0)
>> +#define BOFF(x) (((x) & 0x) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI0x1800
>> +#define PREOFF_YUV_TO_RGB_ME0x1F00
>> +#define PREOFF_YUV_TO_RGB_LO0x1800
>> +
>> /*
>> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>> * format). This macro takes the coefficient we want transformed and
>> the @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
>> return -EINVAL;
>> }
>>
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state) {
>> +struct drm_i915_private *dev_priv =
>> +to_i915(plane_state->base.plane->dev);
>> +struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +enum pipe pipe = crtc->pipe;
>> +struct intel_plane *intel_plane =
>> +to_intel_plane(plane_state->base.plane);
>> +enum plane_id plane = intel_plane->id;
>> +
>> +static const u16 input_csc_matrix[][9] = {
>> +/* BT.601 full range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT601] = {
>> +0x7AF8, 0x7800, 0x0,
>> +0x8B28, 0x7800, 0x9AC0,
>> +0x0, 0x7800, 0x7DD8,
>> +},
>> +/* BT.709 full range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT709] = {
>> +0x7C98, 0x7800, 0x0,
>> +0x9EF8, 0x7800, 0xABF8,
>> +0x0, 0x7800, 0x7ED8,
>> +},
>> +};
>> +
>> +/* Matrix for Limited Range to Full Range Conversion */
>> +static const u16 input_csc_matrix_lr[][9] = {
>> +/* BT.601 Limted range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT601] = {
>> +0x7CC8, 0x7950, 0x0,
>> +0x8CB8, 0x7918, 0x9C40,
>> +0x0, 0x7918, 0x7FC8,
>> +},
>> +/* BT.709 Limited range YCbCr -> full range RGB */
>> +[DRM_COLOR_YCBCR_BT709] = {
>> +0x7EA8, 0x7950, 0x0,
>> +0x, 0x7918, 0xADA8,
>> +0x0, 0x7918, 0x6870,
>> +},
>> +};
>> +const u16 *csc;
>> +
>> +if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> +csc = input_csc_matrix[plane_state->base.color_encoding];
>> +else
>> +csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>> +
>> +I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
>> + GOFF(csc[1]));
>> +I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
>> +I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
>> +
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
== Series Details == Series: series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() URL : https://patchwork.freedesktop.org/series/51802/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10662 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51802/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10662 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_frontbuffer_tracking@basic: fi-icl-u: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: INCOMPLETE (fdo#104108, fdo#105524, k.org#199541) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (49 -> 42) == Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-pnv-d510 == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10662 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10662: f586520210ac6732cba884a5be3da74227fe53e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f586520210ac drm/i915: also group device info array helper macros with others feaa6abaf111 drm/i915: reorder and reindent the register choosing helper wrappers 900ed489f2c9 drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() ab0e5d165ab8 drm/i915: remove palette_offsets from device info in favor of _PICK() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10662/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add Colorspace connector property interface (rev2)
== Series Details == Series: Add Colorspace connector property interface (rev2) URL : https://patchwork.freedesktop.org/series/47132/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10663 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10663 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10663, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/47132/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10663: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-skl-iommu: PASS -> INCOMPLETE fi-ivb-3770:PASS -> INCOMPLETE fi-cfl-s3: PASS -> INCOMPLETE fi-hsw-peppy: PASS -> INCOMPLETE fi-skl-6260u: PASS -> INCOMPLETE fi-icl-u: PASS -> INCOMPLETE fi-snb-2600:PASS -> INCOMPLETE fi-hsw-4770r: PASS -> INCOMPLETE fi-kbl-guc: PASS -> FAIL fi-bsw-kefka: PASS -> INCOMPLETE fi-skl-6700hq: PASS -> INCOMPLETE fi-kbl-x1275: PASS -> FAIL fi-kbl-7500u: PASS -> INCOMPLETE fi-blb-e6850: PASS -> INCOMPLETE fi-bwr-2160:PASS -> INCOMPLETE fi-bdw-5557u: PASS -> INCOMPLETE fi-kbl-r: PASS -> INCOMPLETE fi-kbl-7567u: PASS -> INCOMPLETE fi-cnl-u: PASS -> INCOMPLETE fi-gdg-551: PASS -> INCOMPLETE fi-cfl-8109u: PASS -> INCOMPLETE fi-skl-6600u: PASS -> INCOMPLETE fi-cfl-8700k: PASS -> INCOMPLETE fi-whl-u: PASS -> INCOMPLETE fi-pnv-d510:PASS -> INCOMPLETE fi-ivb-3520m: PASS -> INCOMPLETE fi-bsw-n3050: PASS -> INCOMPLETE fi-skl-6700k2: PASS -> INCOMPLETE fi-hsw-4770:PASS -> INCOMPLETE fi-kbl-soraka: PASS -> INCOMPLETE fi-skl-6770hq: PASS -> INCOMPLETE igt@gem_exec_suspend@basic-s3: fi-kbl-x1275: PASS -> INCOMPLETE Warnings igt@debugfs_test@read_all_entries: fi-icl-u2: DMESG-WARN (fdo#108070) -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10663 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-glk-dsi: PASS -> INCOMPLETE (fdo#103359, k.org#198133) fi-skl-gvtdvm: PASS -> INCOMPLETE (fdo#105600) fi-bdw-gvtdvm: PASS -> INCOMPLETE (fdo#105600) fi-bxt-j4205: PASS -> INCOMPLETE (fdo#103927) fi-skl-guc: PASS -> INCOMPLETE (fdo#106693) fi-apl-guc: PASS -> INCOMPLETE (fdo#106693) fi-glk-j4005: PASS -> INCOMPLETE (fdo#103359, k.org#198133) fi-byt-clapper: PASS -> INCOMPLETE (fdo#102657) fi-byt-j1900: PASS -> INCOMPLETE (fdo#102657) fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) fi-kbl-7560u: PASS -> INCOMPLETE (fdo#103665) fi-cfl-guc: PASS -> INCOMPLETE (fdo#106693) igt@gem_exec_suspend@basic-s3: fi-kbl-guc: PASS -> INCOMPLETE (fdo#106693) fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10663 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10663: 33d07ea8810b104ee7f473d476386f8d662b3305 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 33d07ea8810b drm/i915: Attach colorspace property and enable modeset b716d24947ce drm: Add colorspace property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10663/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
On Wed, Oct 31, 2018 at 01:04:50PM +0200, Jani Nikula wrote: > The device info offset arrays for unevenly spaced register offsets is > great for widely used registers. However, the palette registers are only > used in one function, i9xx_load_luts_internal(), and only for GMCH > platforms, wasting device info. Replace palette_offsets with _PICK() in > palette register definition. > > While the use of _PICK() does not check for pipe C existence, neither > does the current offset array usage, and leads to bogus address when > pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads > to a sensible register offset, just non-existing on non-CHV. Either way, > this shouldn't happen anyway. > > Remove unused old palette macros while at it. > > Bloat-o-meter results below for completeness. > > add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184) > Function old new delta > i9xx_load_luts_internal 394 483 +89 > i915_driver_load51035107 +4 > g4x_pre_enable_dp378 379 +1 > intel_engines_init_mmio 11171116 -1 > intel_engine_lookup_user 47 46 -1 > hdmi_port_clock_valid310 309 -1 > gen11_irq_handler707 706 -1 > intel_device_info_dump_runtime 329 311 -18 > intel_device_info_runtime_init 51664910-256 > Total: Before=918650, After=918466, chg -0.02% > > add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576) > Data old new delta > intel_valleyview_info200 188 -12 > intel_skylake_gt4_info 200 188 -12 > intel_skylake_gt3_info 200 188 -12 > intel_skylake_gt2_info 200 188 -12 > intel_skylake_gt1_info 200 188 -12 > intel_sandybridge_m_gt2_info 200 188 -12 > intel_sandybridge_m_gt1_info 200 188 -12 > intel_sandybridge_d_gt2_info 200 188 -12 > intel_sandybridge_d_gt1_info 200 188 -12 > intel_pineview_info 200 188 -12 > intel_kabylake_gt3_info 200 188 -12 > intel_kabylake_gt2_info 200 188 -12 > intel_kabylake_gt1_info 200 188 -12 > intel_ivybridge_q_info 200 188 -12 > intel_ivybridge_m_gt2_info 200 188 -12 > intel_ivybridge_m_gt1_info 200 188 -12 > intel_ivybridge_d_gt2_info 200 188 -12 > intel_ivybridge_d_gt1_info 200 188 -12 > intel_ironlake_m_info200 188 -12 > intel_ironlake_d_info200 188 -12 > intel_icelake_11_info200 188 -12 > intel_i965gm_info200 188 -12 > intel_i965g_info 200 188 -12 > intel_i945gm_info200 188 -12 > intel_i945g_info 200 188 -12 > intel_i915gm_info200 188 -12 > intel_i915g_info 200 188 -12 > intel_i865g_info 200 188 -12 > intel_i85x_info 200 188 -12 > intel_i845g_info 200 188 -12 > intel_i830_info 200 188 -12 > intel_haswell_gt3_info 200 188 -12 > intel_haswell_gt2_info 200 188 -12 > intel_haswell_gt1_info 200 188 -12 > intel_gm45_info 200 188 -12 > intel_geminilake_info200 188 -12 > intel_g45_info 200 188 -12 > intel_g33_info 200 188 -12 > intel_coffeelake_gt3_info200 188 -12 > intel_coffeelake_gt2_info200 188 -12 > intel_coffeelake_gt1_info200 188 -12 > intel_cherryview_info200 188 -12 > intel_cannonlake_info200 188 -12 > intel_broxton_info 200 188 -12 > intel_broadwell_rsvd_info200 188 -12 > intel_broadwell_gt3_info 200 188 -12 > intel_broadwell_gt2_info 200 188 -12 > intel_broadwell_gt1_info 200 188 -12 > Total: Before=195529, After=194953, chg -0.29% > > Cc: Ville
Re: [Intel-gfx] [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
On Wed, Oct 31, 2018 at 01:04:51PM +0200, Jani Nikula wrote: > Minor semantic nit, no functional changes. > > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d97cf98e3edf..0d0145967482 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -160,7 +160,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) > #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) > #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) > -#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) > +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) > #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) > #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) > #define _PORT(port, a, b) _PICK_EVEN(port, a, b) > -- > 2.11.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers
On Wed, Oct 31, 2018 at 01:04:52PM +0200, Jani Nikula wrote:
> Try to make it slightly less of an eye sore. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 31 +--
> 1 file changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0d0145967482..22db12b070af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -157,20 +157,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> /*
> * Named helper wrappers around _PICK_EVEN() and _PICK().
> */
> -#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
> -#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> -#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
> -#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> -#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> -#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> -#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
> -#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
> -#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> -#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
> -#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
> -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
> +#define _PIPE(pipe, a, b)_PICK_EVEN(pipe, a, b)
> +#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
> +#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> +#define _PORT(port, a, b)_PICK_EVEN(port, a, b)
> +#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
> +
> +#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> +#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> +#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
> +#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> +
> +#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
Hmm. Not sure why this is a vararg macro.
Anyways, patch seesm fine
Reviewed-by: Ville Syrjälä
> +
> +#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({
>\
> --
> 2.11.0
>
> ___
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: also group device info array helper macros with others
On Wed, Oct 31, 2018 at 01:04:53PM +0200, Jani Nikula wrote:
> Keep the register choosing macros together. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 22db12b070af..6327a5f02da5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -175,6 +175,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>
> +/*
> + * Device info offset array based helpers for groups of registers with
> unevenly
> + * spaced base offsets.
> + */
> +#define _MMIO_PIPE2(pipe, reg)
> _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> +
> dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> +
> dev_priv->info.display_mmio_offset)
> +#define _MMIO_TRANS2(pipe, reg)
> _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
> +
> dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> +
> dev_priv->info.display_mmio_offset)
> +#define _CURSOR2(pipe, reg)
> _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> +
> dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> +
> dev_priv->info.display_mmio_offset)
I guess this guy could should be called _MMIO_CURSOR2(). But that's
material for another patch.
This one is
Reviewed-by: Ville Syrjälä
> +
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({
>\
> if (__builtin_constant_p(mask))\
> @@ -4052,10 +4066,6 @@ enum {
> #define TRANSCODER_DSI0_OFFSET 0x6b000
> #define TRANSCODER_DSI1_OFFSET 0x6b800
>
> -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] -
> \
> - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define HTOTAL(trans)_MMIO_TRANS2(trans, _HTOTAL_A)
> #define HBLANK(trans)_MMIO_TRANS2(trans, _HBLANK_A)
> #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
> @@ -5624,10 +5634,6 @@ enum {
> #define PIPE_DSI0_OFFSET 0x7b000
> #define PIPE_DSI1_OFFSET 0x7b800
>
> -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
> #define PIPEDSL(pipe)_MMIO_PIPE2(pipe, _PIPEADSL)
> #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> @@ -6075,10 +6081,6 @@ enum {
> #define _CURBBASE_IVB0x71084
> #define _CURBPOS_IVB 0x71088
>
> -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
> #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
> #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
> --
> 2.11.0
>
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/syncobj: Mark local add/remove callback functions as static
== Series Details == Series: drm/syncobj: Mark local add/remove callback functions as static URL : https://patchwork.freedesktop.org/series/51809/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/syncobj: Mark local add/remove callback functions as static -O:drivers/gpu/drm/drm_syncobj.c:181:6: warning: symbol 'drm_syncobj_add_callback' was not declared. Should it be static? -O:drivers/gpu/drm/drm_syncobj.c:190:6: warning: symbol 'drm_syncobj_remove_callback' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Define WA 0870 and kill dead code.
On Tue, Oct 30, 2018 at 03:15:55PM -0700, Rodrigo Vivi wrote:
> Let's introduce the WA number that is the
> cause of having NV12 disabled on both SLK and BXT.
>
> According to Spec:
>
> WA 0870: "Display flickers with NV12 video playback in
> Y tiling mode.
> WA: Use YUV422 surface format instead of NV12."
>
> v2: remove the useless dead code and consequently
> avoiding device info flag. (Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 --
> drivers/gpu/drm/i915/intel_sprite.c | 1 +
> 2 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ce60aefc14d7..360d248a59b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -458,9 +458,6 @@ static const struct intel_limit intel_limits_bxt = {
> static void
> skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
> {
> - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> - return;
> -
> if (enable)
> I915_WRITE(CLKGATE_DIS_PSL(pipe),
> DUPS1_GATING_DIS | DUPS2_GATING_DIS);
> @@ -5227,9 +5224,6 @@ static bool needs_nv12_wa(struct drm_i915_private
> *dev_priv,
> if (!crtc_state->nv12_planes)
> return false;
>
> - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> - return false;
> -
> if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> IS_CANNONLAKE(dev_priv))
> return true;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index e7c95ec879cc..370c827294d8 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1868,6 +1868,7 @@ static bool skl_plane_has_planar(struct
> drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) >= 11)
> return plane_id <= PLANE_SPRITE3;
>
> + /* Display WA #0870: skl, bxt */
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> --
> 2.19.1
--
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Re: [Intel-gfx] [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
On Tue, Oct 30, 2018 at 04:45:35PM -0700, Manasi Navare wrote:
> On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > > DSC PPS secondary data packet infoframes are filled with
> > > DSC picure parameter set metadata according to the DSC standard.
> > > These infoframes are sent to the sink device and used during DSC
> > > decoding.
> > >
> > > v2:
> > > * Rebase ond drm-tip
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/intel_vdsc.c | 21 +
> > > 1 file changed, 21 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > > b/drivers/gpu/drm/i915/intel_vdsc.c
> > > index b0fc716bbbfd..4b4b812d68f3 100644
> > > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > > @@ -988,6 +988,25 @@ static void
> > > intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> > > }
> > > }
> > >
> > > +static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *crtc_state)
> >
> > const crtc_state
>
> Changing this to const crtc_state started giving me an error when I get the
> struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
const struct drm_dsc_config ...
>
> So this is making me think that since dp_dsc_cfg is written during
> compute_config,
> and there on we just read it, we dont need to pass *vdsc_cfg , we can
> just pass the struct directly right?
Not sure what you're asking here.
>
> Manasi
>
> >
> > s/send/write/ ?
> >
> > > +{
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> > > + struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
> > > +
> > > + /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
> > > + drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
> > > +
> > > + /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
> > > + drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
> > > +
> > > + intel_dig_port->write_infoframe(encoder, crtc_state,
> > > + DP_SDP_PPS, &dp_dsc_pps_sdp,
> > > + sizeof(dp_dsc_pps_sdp));
> > > +}
> > > +
> > > void intel_dsc_enable(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> > >
> > > intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> > >
> > > + intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> > > +
> > > return;
> > > }
> > > --
> > > 2.18.0
> >
> > --
> > Ville Syrjälä
> > Intel
> > ___
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Re: [Intel-gfx] [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
On Tue, Oct 30, 2018 at 04:53:49PM -0700, Manasi Navare wrote:
> On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> > Basic DSC parameters and DSC configuration data needs to be computed
> > for each of the requested mode during atomic check. This is
> > required since for certain modes, valid DSC parameters and config
> > data might not be computed in which case compression cannot be
> > enabled for that mode.
> > For that reason we need to add these params and config structure
> > to the intel_crtc_state so that if valid this state information
> > can directly be used while enabling DSC in atomic commit.
> >
> > v2:
> > * Rebase on drm-tip (Manasi)
> >
> > Cc: Gaurav K Singh
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_drv.h | 9 +
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 2d7761b8ac07..45fd7894722b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -53,6 +53,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "i915_params.h"
> > #include "i915_reg.h"
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 62c051098859..27d47950f438 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -931,6 +931,15 @@ struct intel_crtc_state {
> >
> > /* Output down scaling is done in LSPCON device */
> > bool lspcon_downsampling;
> > +
> > + /* Display Stream compression state */
> > + struct {
> > + bool compression_enable;
> > + bool dsc_split;
> > + u16 compressed_bpp;
> > + u8 slice_count;
> > + } dsc_params;
> > + struct drm_dsc_config dp_dsc_cfg;
>
> Ville, Jani should this be defined as a pointer to struct drm_dsc_config?
> struct drm_dsc_config *dp_dsc_cfg
> since we populate this in intel_dp_compute_config and then on only read during
> commit.
Pointer to where exactly? You need the memory for it somewhere.
>
> Manasi
>
> > };
> >
> > struct intel_crtc {
> > --
> > 2.18.0
> >
--
Ville Syrjälä
Intel
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[Intel-gfx] [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
v5: Renamed the register Macro as per Matt's suggestion.
v6: No Change
Signed-off-by: Uma Shankar
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 50 +
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..87c275c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)
@@ -6585,6 +6586,55 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A0x70278
#define _PLANE_NV12_BUF_CFG_2_A0x70378
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+_PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+_PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)\
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
--
1.9.1
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[Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.
This has been verified and tested by Maarten and the change is working
as expected.
v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.
v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.
v4: Added support for Limited Range Color Handling
v5: Fixed Matt and Maarten's review comments.
v6: Added human readable matrix values for YUV to RGB Conversion along
with just the bspec register values, as per Matt's suggestion.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 103 +++
drivers/gpu/drm/i915/intel_display.c | 23 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 122 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..6dc9075 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
#define CSC_RGB_TO_YUV_BV 0x1e08
+#define ROFF(x) (((x) & 0x) << 16)
+#define GOFF(x) (((x) & 0x) << 0)
+#define BOFF(x) (((x) & 0x) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI 0x1800
+#define PREOFF_YUV_TO_RGB_ME 0x1F00
+#define PREOFF_YUV_TO_RGB_LO 0x1800
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
return -EINVAL;
}
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ struct intel_plane *intel_plane =
+ to_intel_plane(plane_state->base.plane);
+ enum plane_id plane = intel_plane->id;
+
+ static const u16 input_csc_matrix[][9] = {
+ /*
+* BT.601 full range YCbCr -> full range RGB
+* The matrix required is :
+* [1.000, 0.000, 1.371,
+* 1.000, -0.336, -0.698,
+* 1.000, 1.732, 0.]
+*/
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7AF8, 0x7800, 0x0,
+ 0x8B28, 0x7800, 0x9AC0,
+ 0x0, 0x7800, 0x7DD8,
+ },
+ /*
+* BT.709 full range YCbCr -> full range RGB
+* The matrix required is :
+* [1.000, 0.000, 1.574,
+* 1.000, -0.187, -0.468,
+* 1.000, 1.855, 0.]
+*/
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7C98, 0x7800, 0x0,
+ 0x9EF8, 0x7800, 0xABF8,
+ 0x0, 0x7800, 0x7ED8,
+ },
+ };
+
+ /* Matrix for Limited Range to Full Range Conversion */
+ static const u16 input_csc_matrix_lr[][9] = {
+ /*
+* BT.601 Limted range YCbCr -> full range RGB
+* The matrix required is :
+* [1.164384, 0.000, 1.596370,
+* 1.138393, -0.382500, -0.794598,
+* 1.138393, 1.971696, 0.]
+*/
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7CC8, 0x7950, 0x0,
+ 0x8CB8, 0x7918, 0x9C40,
+ 0x0, 0x7918, 0x7FC8,
+ },
+ /*
+* BT.709 Limited range YCbCr -> full range RGB
+* The matrix required is :
+* [1.164, 0.000, 1.833671,
+* 1.138393, -0.213249, -0.532909,
+* 1.138393, 2.112402, 0.]
+*/
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7EA8, 0x7950, 0x0,
+ 0x, 0x7918, 0xADA8,
+ 0x0, 0x7918, 0x6870,
+ },
+ };
+ const u16 *csc;
+
+ if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ csc = input_csc_matrix[plane_state->base.color_encoding];
+ else
+ csc = input_csc_ma
[Intel-gfx] [v6 0/2] Enable Plane Input CSC for ICL
This patch series enables plane input csc feature for ICL. This is needed for YUV to RGB conversion on bottom 3 planes on ICL, other planes are handled in the legacy way using fixed function hardware. This series enables color conversion for Full Range YUV data, limited range handling will be done as a separate patch. v2: Separated the patch into 2 parts as per Maarten's comments. Addressed Ville and Maarten's review comment. v3: Redesigned the register macro definition as per Matt's comment. Addressed Maarten's review comment. v4: Added support for Limited Range Color Handling. v5: Fixed Matt and Maarten's review comments. v6: Added human readable matrix values for YUV to RGB Conversion along with just the bspec register values, as per Matt's suggestion. This has been verified and tested by Maarten and the change is working as expected. Uma Shankar (2): drm/i915/icl: Define Plane Input CSC Coefficient Registers drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion drivers/gpu/drm/i915/i915_reg.h | 50 + drivers/gpu/drm/i915/intel_color.c | 103 +++ drivers/gpu/drm/i915/intel_display.c | 23 ++-- drivers/gpu/drm/i915/intel_drv.h | 2 + 4 files changed, 172 insertions(+), 6 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/syncobj: Mark local add/remove callback functions as static
== Series Details == Series: drm/syncobj: Mark local add/remove callback functions as static URL : https://patchwork.freedesktop.org/series/51809/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10664 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10664 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10664, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51809/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10664: === IGT changes === Warnings igt@drv_selftest@live_guc: fi-skl-iommu: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_10664 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@drv_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@drv_selftest@live_hangcheck: fi-skl-iommu: PASS -> INCOMPLETE (fdo#108602) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: INCOMPLETE (fdo#105524, fdo#104108, k.org#199541) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108602 https://bugs.freedesktop.org/show_bug.cgi?id=108602 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10664 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10664: 9e64fd6e0e4794b5c2b36485a479c56c69f4ba58 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9e64fd6e0e47 drm/syncobj: Mark local add/remove callback functions as static == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10664/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain
On Tue, Oct 30, 2018 at 02:57:51PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 05:40:50PM +0200, Imre Deak wrote:
> > Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> > parameters. As opposed to this the flag specifying the thunderbolt vs.
> > non-thunderbolt mode of the port is not related to AUX transfers at all
> > (rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
> > The programming has to be done before enabling the corresponding AUX
> > power well, so make it part of the power well code.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 69
> > +
> > 2 files changed, 62 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index c57b701f72a7..dbf894835cb2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -921,6 +921,7 @@ struct i915_power_well_desc {
> > /* The pw is backing the VGA functionality */
> > bool has_vga:1;
> > bool has_fuses:1;
> > + bool is_tc_tbt;
>
> what's up with the bitfield just above? Eitehr make this a bitfield or turn
> the others into
> !bitfield ?
Yes, typoed it, thanks for catching it. It should remain a bitfield.
>
> We also may want to do:
>
> struct {
> struct _hsw;
> bool is_tc_tbt;
> } icl;
>
> to clarify this is icl+...
Not sure, since we'd still use power_well->desc->hsw if calling a helper
like hsw_wait_for_power_well_enable(). I can add a comment that the
field is for ICL TC PHYs.
>
> ugh, but that needs a "subdir-ccflags-y += -fms-extensions" :(.
>
>
> Lucas De Marchi
>
> > } hsw;
> > };
> > const struct i915_power_well_ops *ops;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 5f5416eb9644..eed17440a4a7 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -465,6 +465,44 @@ icl_combo_phy_aux_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > hsw_wait_for_power_well_disable(dev_priv, power_well);
> > }
> >
> > +#define ICL_AUX_PW_TO_CH(pw_idx) \
> > + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> > +
> > +static void
> > +icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> > +struct i915_power_well *power_well)
> > +{
> > + const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > + int pw_idx = power_well->desc->hsw.idx;
> > + enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(pw_idx);
> > + u32 val;
> > +
> > + val = I915_READ(DP_AUX_CH_CTL(aux_ch));
> > + val &= ~DP_AUX_CH_CTL_TBT_IO;
> > + if (power_well->desc->hsw.is_tc_tbt)
> > + val |= DP_AUX_CH_CTL_TBT_IO;
> > + I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
> > +
> > + val = I915_READ(regs->driver);
> > + I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> > +
> > + hsw_wait_for_power_well_enable(dev_priv, power_well);
> > +}
> > +
> > +static void
> > +icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > + int pw_idx = power_well->desc->hsw.idx;
> > + u32 val;
> > +
> > + val = I915_READ(regs->driver);
> > + I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> > +
> > + hsw_wait_for_power_well_disable(dev_priv, power_well);
> > +}
> > +
> > /*
> > * We should only use the power well if we explicitly asked the hardware to
> > * enable it, so check if it's enabled and also check if we've requested
> > it to
> > @@ -2725,6 +2763,13 @@ static const struct i915_power_well_ops
> > icl_combo_phy_aux_power_well_ops = {
> > .is_enabled = hsw_power_well_enabled,
> > };
> >
> > +static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
> > + .sync_hw = hsw_power_well_sync_hw,
> > + .enable = icl_tc_phy_aux_power_well_enable,
> > + .disable = icl_tc_phy_aux_power_well_disable,
> > + .is_enabled = hsw_power_well_enabled,
> > +};
> > +
> > static const struct i915_power_well_regs icl_aux_power_well_regs = {
> > .bios = ICL_PWR_WELL_CTL_AUX1,
> > .driver = ICL_PWR_WELL_CTL_AUX2,
> > @@ -2870,81 +2915,89 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > {
> > .name = "AUX C",
> > .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> > - .ops = &hsw_power_well_ops,
> > + .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
>
Re: [Intel-gfx] [PATCH 7/8] drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain
On Wed, Oct 31, 2018 at 01:28:07AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> > parameters. As opposed to this the flag specifying the thunderbolt
> > vs.
> > non-thunderbolt mode of the port is not related to AUX transfers at
> > all
> > (rather it's repurposed to enable either TBT or non-TBT PHY HW
> > blocks).
> > The programming has to be done before enabling the corresponding AUX
> > power well, so make it part of the power well code.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
>
> Reviewed-by: José Roberto de Souza
>
> If respinning this patch please consider the comments bellow but nice
> catch.
>
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 69
> > +
> > 2 files changed, 62 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index c57b701f72a7..dbf894835cb2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -921,6 +921,7 @@ struct i915_power_well_desc {
> > /* The pw is backing the VGA functionality */
> > bool has_vga:1;
> > bool has_fuses:1;
> > + bool is_tc_tbt;
> > } hsw;
> > };
> > const struct i915_power_well_ops *ops;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 5f5416eb9644..eed17440a4a7 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -465,6 +465,44 @@ icl_combo_phy_aux_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > hsw_wait_for_power_well_disable(dev_priv, power_well);
> > }
> >
> > +#define ICL_AUX_PW_TO_CH(pw_idx) \
> > + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> > +
> > +static void
> > +icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> > +struct i915_power_well *power_well)
> > +{
> > + const struct i915_power_well_regs *regs = power_well->desc-
> > >hsw.regs;
> > + int pw_idx = power_well->desc->hsw.idx;
> > + enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(pw_idx);
> > + u32 val;
> > +
> > + val = I915_READ(DP_AUX_CH_CTL(aux_ch));
> > + val &= ~DP_AUX_CH_CTL_TBT_IO;
> > + if (power_well->desc->hsw.is_tc_tbt)
> > + val |= DP_AUX_CH_CTL_TBT_IO;
> > + I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
> > +
> > + val = I915_READ(regs->driver);
> > + I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> > +
> > + hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> Minor but you could call hsw_power_well_enable() after write to
> DP_AUX_CH_CTL instead of duplicate code.
>
> > +}
> > +
> > +static void
> > +icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + const struct i915_power_well_regs *regs = power_well->desc-
> > >hsw.regs;
> > + int pw_idx = power_well->desc->hsw.idx;
> > + u32 val;
> > +
> > + val = I915_READ(regs->driver);
> > + I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> > +
> > + hsw_wait_for_power_well_disable(dev_priv, power_well);
> > +}
>
> Minor too you could use the hsw_power_well_disable() instead of
> duplicate code.
Ok, will change these.
>
> > +
> > /*
> > * We should only use the power well if we explicitly asked the
> > hardware to
> > * enable it, so check if it's enabled and also check if we've
> > requested it to
> > @@ -2725,6 +2763,13 @@ static const struct i915_power_well_ops
> > icl_combo_phy_aux_power_well_ops = {
> > .is_enabled = hsw_power_well_enabled,
> > };
> >
> > +static const struct i915_power_well_ops
> > icl_tc_phy_aux_power_well_ops = {
> > + .sync_hw = hsw_power_well_sync_hw,
> > + .enable = icl_tc_phy_aux_power_well_enable,
> > + .disable = icl_tc_phy_aux_power_well_disable,
> > + .is_enabled = hsw_power_well_enabled,
> > +};
> > +
> > static const struct i915_power_well_regs icl_aux_power_well_regs = {
> > .bios = ICL_PWR_WELL_CTL_AUX1,
> > .driver = ICL_PWR_WELL_CTL_AUX2,
> > @@ -2870,81 +2915,89 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > {
> > .name = "AUX C",
> > .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> > - .ops = &hsw_power_well_ops,
> > + .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = &icl_aux_power_well_regs,
> > .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> > + .hsw.is_tc_tbt = false,
> > },
> > },
> > {
> >
Re: [Intel-gfx] [PATCH 2/8] drm/i915: Move aux_ch to intel_digital_port
On Wed, Oct 31, 2018 at 12:36:00AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > From ICL onwards all DDI/TypeC ports - even working in HDMI mode -
> > need
> > to know their corresponding AUX CH, so move the field to a common
> > struct.
> >
> > No functional change.
> >
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
> > drivers/gpu/drm/i915/intel_dp.c | 35 +++---
> > -
> > drivers/gpu/drm/i915/intel_drv.h | 2 +-
> > 3 files changed, 27 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index e40a8c97d34b..32a080265d03 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2084,6 +2084,8 @@ bool intel_ddi_get_hw_state(struct
> > intel_encoder *encoder,
> > static inline enum intel_display_power_domain
> > intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
> > {
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +
> > /* CNL+ HW requires corresponding AUX IOs to be powered up for
> > PSR with
> > * DC states enabled at the same time, while for driver
> > initiated AUX
> > * transfers we need the same AUX IOs to be powered but with DC
> > states
> > @@ -2096,7 +2098,7 @@ intel_ddi_main_link_aux_domain(struct intel_dp
> > *intel_dp)
> > * Note that PSR is enabled only on Port A even though this
> > function
> > * returns the correct domain for other ports too.
> > */
> > - return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
> > + return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
> > intel_dp-
> > >aux_power_domain;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 2445897b8f6c..5530c604c694 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1156,6 +1156,7 @@ static uint32_t
> > g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> > static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp,
> > int index)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >
> > if (index)
> > return 0;
> > @@ -1165,7 +1166,7 @@ static uint32_t
> > ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> > * like to run at 2MHz. So, take the cdclk or PCH rawclk value
> > and
> > * divide by 2000 and use that
> > */
> > - if (intel_dp->aux_ch == AUX_CH_A)
> > + if (dig_port->aux_ch == AUX_CH_A)
> > return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk,
> > 2000);
> > else
> > return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
> > @@ -1174,8 +1175,9 @@ static uint32_t
> > ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> > static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp,
> > int index)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >
> > - if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
> > + if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
> > /* Workaround for non-ULT HSW */
> > switch (index) {
> > case 0: return 63;
> > @@ -1506,7 +1508,9 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux,
> > struct drm_dp_aux_msg *msg)
> > static enum intel_display_power_domain
> > intel_aux_power_domain(struct intel_dp *intel_dp)
> > {
> > - switch (intel_dp->aux_ch) {
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +
> > + switch (dig_port->aux_ch) {
> > case AUX_CH_A:
> > return POWER_DOMAIN_AUX_A;
> > case AUX_CH_B:
> > @@ -1520,7 +1524,7 @@ intel_aux_power_domain(struct intel_dp
> > *intel_dp)
> > case AUX_CH_F:
> > return POWER_DOMAIN_AUX_F;
> > default:
> > - MISSING_CASE(intel_dp->aux_ch);
> > + MISSING_CASE(dig_port->aux_ch);
> > return POWER_DOMAIN_AUX_A;
> > }
> > }
> > @@ -1528,7 +1532,8 @@ intel_aux_power_domain(struct intel_dp
> > *intel_dp)
> > static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - enum aux_ch aux_ch = intel_dp->aux_ch;
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > + enum aux_ch aux_ch = dig_port->aux_ch;
> >
> > switch (aux_ch) {
> > case AUX_CH_B:
> > @@ -1544,7 +1549,8 @@ static i915_reg_t g4x_aux_ctl_reg(struct
> > intel_dp *intel_dp)
> > static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int
> > index)
> > {
> > struct drm_i915_private *dev_priv
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev5)
== Series Details == Series: Enable Plane Input CSC for ICL (rev5) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0788076afc3f drm/i915/icl: Define Plane Input CSC Coefficient Registers -:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #58: FILE: drivers/gpu/drm/i915/i915_reg.h:6602: +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #58: FILE: drivers/gpu/drm/i915/i915_reg.h:6602: +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #74: FILE: drivers/gpu/drm/i915/i915_reg.h:6618: +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #74: FILE: drivers/gpu/drm/i915/i915_reg.h:6618: +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/i915_reg.h:6634: +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/i915_reg.h:6634: +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) total: 0 errors, 0 warnings, 6 checks, 62 lines checked d14aa7612d93 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev5)
== Series Details == Series: Enable Plane Input CSC for ICL (rev5) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers Okay! Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> This has been verified and tested by Maarten and the change is working
> as expected.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> v6: Added human readable matrix values for YUV to RGB Conversion along
> with just the bspec register values, as per Matt's suggestion.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 103
> +++
> drivers/gpu/drm/i915/intel_display.c | 23 ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 122 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..6dc9075 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e08
>
> +#define ROFF(x) (((x) & 0x) << 16)
> +#define GOFF(x) (((x) & 0x) << 0)
> +#define BOFF(x) (((x) & 0x) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /*
> + * BT.601 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.371,
> + * 1.000, -0.336, -0.698,
> + * 1.000, 1.732, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /*
> + * BT.709 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.574,
> + * 1.000, -0.187, -0.468,
> + * 1.000, 1.855, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /*
> + * BT.601 Limted range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164384, 0.000, 1.596370,
> + * 1.138393, -0.382500, -0.794598,
> + * 1.138393, 1.971696, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /*
> + * BT.709 Limited range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164, 0.000, 1.833671,
> + * 1.138393, -0.213249, -0.532909,
> + * 1.138393, 2.112402, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (
[Intel-gfx] ✓ Fi.CI.BAT: success for RFT drm/i915/execlists: Flush memory before signaling ELSQ
== Series Details == Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ URL : https://patchwork.freedesktop.org/series/51796/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10665 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51796/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10665 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) fi-skl-6600u: PASS -> INCOMPLETE (fdo#104108) Possible fixes igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: INCOMPLETE (k.org#199541, fdo#104108, fdo#105524) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10665 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10665: 78b9296dc448e92f3dc469631381a721ee2c5997 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 78b9296dc448 RFT drm/i915/execlists: Flush memory before signaling ELSQ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10665/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> This has been verified and tested by Maarten and the change is working
> as expected.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> v6: Added human readable matrix values for YUV to RGB Conversion along
> with just the bspec register values, as per Matt's suggestion.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 103
> +++
> drivers/gpu/drm/i915/intel_display.c | 23 ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 122 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..6dc9075 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e08
>
> +#define ROFF(x) (((x) & 0x) << 16)
> +#define GOFF(x) (((x) & 0x) << 0)
> +#define BOFF(x) (((x) & 0x) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /*
> + * BT.601 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.371,
> + * 1.000, -0.336, -0.698,
> + * 1.000, 1.732, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /*
> + * BT.709 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.574,
> + * 1.000, -0.187, -0.468,
> + * 1.000, 1.855, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /*
> + * BT.601 Limted range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164384, 0.000, 1.596370,
> + * 1.138393, -0.382500, -0.794598,
> + * 1.138393, 1.971696, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /*
> + * BT.709 Limited range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164, 0.000, 1.833671,
> + * 1.138393, -0.213249, -0.532909,
> + * 1.138393, 2.112402, 0.]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev5)
== Series Details == Series: Enable Plane Input CSC for ICL (rev5) URL : https://patchwork.freedesktop.org/series/51463/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10666 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/5/mbox/ == Known issues == Here are the changes found in Patchwork_10666 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) Possible fixes igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: INCOMPLETE (fdo#105524, fdo#104108, k.org#199541) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (49 -> 43) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5062 -> Patchwork_10666 CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10666: d14aa7612d93371216d77ae2dc684afd4550047b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d14aa7612d93 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion 0788076afc3f drm/i915/icl: Define Plane Input CSC Coefficient Registers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10666/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] mm, drm/i915: mark pinned shmemfs pages as unevictable
On 10/31/18 1:19 AM, owner-linux...@kvack.org wrote: > -These are currently used in two places in the kernel: > +These are currently used in three places in the kernel: > > (1) By ramfs to mark the address spaces of its inodes when they are created, > and this mark remains for the life of the inode. > @@ -154,6 +154,8 @@ These are currently used in two places in the kernel: > swapped out; the application must touch the pages manually if it wants > to > ensure they're in memory. > > + (3) By the i915 driver to mark pinned address space until it's unpinned. mlock() and ramfs usage are pretty easy to track down. /proc/$pid/smaps or /proc/meminfo can show us mlock() and good ol' 'df' and friends can show us ramfs the extent of pinned memory. With these, if we see "Unevictable" in meminfo bump up, we at least have a starting point to find the cause. Do we have an equivalent for i915? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 1/2] drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines
From: Oscar Mateo
SFC (Scaler & Format Converter) units are shared between VD and VEBoxes.
They also happen to have separate reset bits. So, whenever we want to reset
one or more of the media engines, we have to make sure the SFCs do not
change owner in the process and, if this owner happens to be one of the
engines being reset, we need to reset the SFC as well.
This happens in 4 steps:
1) Tell the engine that a software reset is going to happen. The engine
will then try to force lock the SFC (if currently locked, it will
remain so; if currently unlocked, it will ignore this and all new lock
requests).
2) Poll the ack bit to make sure the hardware has received the forced
lock from the driver. Once this bit is set, it indicates SFC status
(lock or unlock) will not change anymore (until we tell the engine it
is safe to unlock again).
3) Check the usage bit to see if the SFC has ended up being locked to
the engine we want to reset. If this is the case, we have to reset
the SFC as well.
4) Unlock all the SFCs once the reset sequence is completed.
Obviously, if we are resetting the whole GPU, we don't have to worry
about all of this.
BSpec: 10989
BSpec: 10990
BSpec: 10954
BSpec: 10955
BSpec: 10956
BSpec: 19212
Signed-off-by: Tomasz Lis
Signed-off-by: Oscar Mateo
Signed-off-by: Michel Thierry
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++
drivers/gpu/drm/i915/intel_uncore.c | 105 ++--
2 files changed, 119 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef..7b4dffa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -330,6 +330,24 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GRDOM_MEDIA4(1 << 8)
#define GEN11_GRDOM_VECS (1 << 13)
#define GEN11_GRDOM_VECS2 (1 << 14)
+#define GEN11_GRDOM_SFC0 (1 << 17)
+#define GEN11_GRDOM_SFC1 (1 << 18)
+
+#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 <<
((instance) >> 1))
+#define GEN11_VECS_SFC_RESET_BIT(instance)(GEN11_GRDOM_SFC0 << (instance))
+
+#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base +
0x88C)
+#define GEN11_VCS_SFC_FORCED_LOCK_BIT(1 << 0)
+#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base +
0x890)
+#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
+#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
+
+#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base +
0x201C)
+#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
+#define GEN11_VECS_SFC_LOCK_ACK(engine)
_MMIO((engine)->mmio_base + 0x2018)
+#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
+#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base +
0x2014)
+#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9289515..481e70e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1931,6 +1931,95 @@ static int gen6_reset_engines(struct drm_i915_private
*dev_priv,
return gen6_hw_domain_reset(dev_priv, hw_mask);
}
+static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,
+ struct intel_engine_cs *engine)
+{
+ u8 vdbox_sfc_access = INTEL_INFO(dev_priv)->vdbox_sfc_access;
+ i915_reg_t sfc_forced_lock;
+ u32 sfc_forced_lock_bit;
+ i915_reg_t sfc_forced_lock_ack;
+ u32 sfc_forced_lock_ack_bit;
+ i915_reg_t sfc_usage;
+ u32 sfc_usage_bit;
+ u32 sfc_reset_bit;
+
+ switch (engine->class) {
+ case VIDEO_DECODE_CLASS:
+ if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
+ return 0;
+ sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
+ sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
+ sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
+ sfc_forced_lock_ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
+ sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
+ sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
+ sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
+ break;
+ case VIDEO_ENHANCEMENT_CLASS:
+ sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
+ sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
+ sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
+ sfc_forced_lock_ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
+ s
[Intel-gfx] [PATCH v1 2/2] drm/i915/icl: Record the valid VDBoxes with SFC capability
From: Oscar Mateo
In Gen11, only even numbered "logical" VDBoxes are hooked up to an SFC
(Scaler & Format Converter) unit. We will use this information to decide
when the SFC units need to be reset.
BSpec: 20189
Signed-off-by: Tomasz Lis
Signed-off-by: Oscar Mateo
Signed-off-by: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_device_info.c | 9 +
drivers/gpu/drm/i915/intel_device_info.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 89ed3a8..e2454a7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -881,6 +881,7 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
u32 media_fuse;
+ uint logical_vdbox = 0;
unsigned int i;
if (INTEL_GEN(dev_priv) < 11)
@@ -900,7 +901,15 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
if (!(BIT(i) & info->vdbox_enable)) {
info->ring_mask &= ~ENGINE_MASK(_VCS(i));
DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
+ continue;
}
+
+ /*
+* In Gen11, only even numbered logical VDBOXes are
+* hooked up to an SFC (Scaler & Format Converter) unit.
+*/
+ if (logical_vdbox++ % 2 == 0)
+ info->vdbox_sfc_access |= BIT(i);
}
DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4e..1eda80f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,6 +189,9 @@ struct intel_device_info {
u8 vdbox_enable;
u8 vebox_enable;
+ /* Media engine access to SFC per instance */
+ u8 vdbox_sfc_access;
+
struct color_luts {
u16 degamma_lut_size;
u16 gamma_lut_size;
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] mm, drm/i915: mark pinned shmemfs pages as unevictable
On Wed 31-10-18 16:19:45, Kuo-Hsin Yang wrote: [...] > The previous mapping_set_unevictable patch is worse on gem_syslatency > because it defers to vmscan to move these pages to the unevictable list > and the test measures latency to allocate 2MiB pages. This performance > impact can be solved by explicit moving pages to the unevictable list in > the i915 function. As I've mentioned in the previous version and testing results. Are you sure that the lazy unevictable pages collecting is the real problem here? The test case was generating a lot of page cache and we simply do not reclaim anon LRUs at all. Maybe I have misunderstood the test though. I am also wondering whether unevictable pages culling can be really visible when we do the anon LRU reclaim because the swap path is quite expensinve on its own. -- Michal Hocko SUSE Labs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
