date:20181128

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync 
registers on ring init
URL   : https://patchwork.freedesktop.org/series/53185/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5216_full -> Patchwork_10936_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_10936_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_import_export@import-close-race-flink:
- shard-skl:  PASS -> TIMEOUT [fdo#108667]

  * igt@gem_exec_whisper@normal:
- shard-skl:  PASS -> TIMEOUT [fdo#108592]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl:  PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +3

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-glk:  PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_flip_tiling@flip-to-y-tiled:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl:  PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk:  PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- {shard-iclb}:   PASS -> FAIL [fdo#105683]

  * igt@kms_panel_fitting@legacy:
- shard-skl:  NOTRUN -> FAIL [fdo#105456]

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk:  PASS -> FAIL [fdo#108145]

  * igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-apl:  PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +6

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl:  PASS -> FAIL [fdo#103166] +2

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk:  PASS -> FAIL [fdo#103166] +1
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103166] +1

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107724]

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- {shard-iclb}:   PASS -> FAIL [fdo#103925]

  * igt@kms_setmode@basic:
- shard-apl:  PASS -> FAIL [fdo#99912]
- shard-skl:  NOTRUN -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] +3

  * igt@pm_backlight@fade_with_suspend:
- shard-skl:  NOTRUN -> FAIL [fdo#107847]

  * igt@pm_rpm@legacy-planes:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#108654]

  * igt@pm_rpm@system-suspend-execbuf:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]

  * igt@pm_rps@min-max-config-loaded:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#102250]

  * {igt@runner@aborted}:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#108756]

  
 Possible fixes 

  * igt@gem_eio@in-flight-1us:
- shard-glk:  INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_color@pipe-c-ctm-0-5:
- shard-skl:  FAIL [fdo#108682] -> PASS

  * igt@kms_cursor_crc@cursor-128x42-random:
- shard-glk:  FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-random:
- shard-skl:  FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk:  FAIL [fdo#104873] -> PASS

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk:  FAIL [fdo#105363] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank:
- shard-glk:  FAIL [fdo#102887] / [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-glk:  FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-apl:  FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}:   FAIL [fdo#103167] -> PASS +1

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

2018-11-28 Thread Saarinen, Jani

Hi, 

> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Rodrigo Vivi
> Sent: torstai 29. marraskuuta 2018 8.18
> To: Souza, Jose 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id
> following atomic guidelines (rev2)
> 
> On Wed, Nov 28, 2018 at 02:13:12PM -0800, Souza, Jose wrote:
> > On Wed, 2018-11-28 at 21:02 +, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
> > > URL   : https://patchwork.freedesktop.org/series/53132/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934
> > > 
> > >
> > > Summary
> > > ---
> > >
> > >   **FAILURE**
> > >
> > >   Serious unknown changes coming with Patchwork_10934 absolutely
> > > need to be
> > >   verified manually.
> > >
> > >   If you think the reported changes have nothing to do with the
> > > changes
> > >   introduced in Patchwork_10934, please notify your bug team to
> > > allow them
> > >   to document this new failure mode, which will reduce false
> > > positives in CI.
> > >
> > >   External URL:
> > > https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/m
> > > box/
> > >
> > > Possible new issues
> > > ---
> > >
> > >   Here are the unknown changes that may have been introduced in
> > > Patchwork_10934:
> > >
> > > ### IGT changes ###
> > >
> > >  Possible regressions 
> > >
> > >   * igt@i915_selftest@live_sanitycheck:
> > > - fi-apl-guc: PASS -> DMESG-WARN
> > >
> > >   * {igt@runner@aborted}:
> > > - fi-apl-guc: NOTRUN -> FAIL
> >
> > Both are pretty much non related with display, what do you think
> > Rodrigo? It is a merge blocker?
> 
> I got addicted to see all green on CI. So I always prefer to trigger a 
> retest. So
> anyone following the link that is merged with the patch doens't have to
> understand and analyze why it was merged with BAT failure.
> 
> I just triggered the re-test for this patch.
Martin, Arek, fyi, not preferred? 
> 
> Thanks,
> Rodrigo.
> 
> >
> > >
> > >
> > > Known issues
> > > 
> > >
> > >   Here are the changes found in Patchwork_10934 that come from known
> > > issues:
> > >
> > > ### IGT changes ###
> > >
> > >  Issues hit 
> > >
> > >   * igt@i915_selftest@live_hangcheck:
> > > - fi-kbl-7560u:   PASS -> INCOMPLETE [fdo#108044]
> > >
> > >   * igt@kms_pipe_crc_basic@read-crc-pipe-a:
> > > - fi-byt-clapper: PASS -> FAIL [fdo#107362]
> > >
> > >
> > >   {name}: This element is suppressed. This means it is ignored when
> > > computing
> > >   the status of the difference (SUCCESS, WARNING, or
> > > FAILURE).
> > >
> > >   [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
> > >   [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
> > >
> > >
> > > Participating hosts (50 -> 44)
> > > --
> > >
> > >   Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> > > squawks fi-bsw-cyan fi-ctg-p8600
> > >
> > >
> > > Build changes
> > > -
> > >
> > > * Linux: CI_DRM_5216 -> Patchwork_10934
> > >
> > >   CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @
> > > git://anongit.freedesktop.org/gfx-ci/linux
> > >   IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @
> > > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> > >   Patchwork_10934: 2ebde49b2d0906d8106b020a2b0480bc5f552a01 @
> > > git://anongit.freedesktop.org/gfx-ci/linux
> > >
> > >
> > > == Linux commits ==
> > >
> > > 2ebde49b2d09 drm/i915/psr: Get pipe id following atomic guidelines
> > >
> > > == Logs ==
> > >
> > > For more details see:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10934/
> 
> 
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Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

2018-11-28 Thread Lisovskiy, Stanislav

On Wed, 2018-11-28 at 22:21 +0100, Daniel Vetter wrote:
> On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote:
> > On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy
> > wrote:
> > > Currently kernel might allocate different connector ids
> > > for the same outputs in case of DP MST, which seems to
> > > confuse userspace. There are can be different connector
> > > ids in the list, which could be assigned to the same
> > > output, while being in different states.
> > > This results in issues, like external displays staying
> > > blank after quick unplugging and plugging back(bug #106250).
> > > Returning only active DP connectors fixes the issue.
> > > 
> > > v2: Removed caps from the title
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106250
> > > Signed-off-by: Stanislav Lisovskiy  > > >
> > > ---
> > >  drivers/gpu/drm/drm_mode_config.c | 16 +++-
> > >  1 file changed, 11 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_mode_config.c
> > > b/drivers/gpu/drm/drm_mode_config.c
> > > index ee80788f2c40..ec5b2b08a45e 100644
> > > --- a/drivers/gpu/drm/drm_mode_config.c
> > > +++ b/drivers/gpu/drm/drm_mode_config.c
> > > @@ -143,6 +143,7 @@ int drm_mode_getresources(struct drm_device
> > > *dev, void *data,
> > >   drm_connector_list_iter_begin(dev, _iter);
> > >   count = 0;
> > >   connector_id = u64_to_user_ptr(card_res-
> > > >connector_id_ptr);
> > > + DRM_DEBUG_KMS("GetResources: writing connectors start");
> > >   drm_for_each_connector_iter(connector, _iter) {
> > >   /* only expose writeback connectors if userspace
> > > understands them */
> > >   if (!file_priv->writeback_connectors &&
> > > @@ -150,15 +151,20 @@ int drm_mode_getresources(struct drm_device
> > > *dev, void *data,
> > >   continue;
> > >  
> > >   if (drm_lease_held(file_priv, connector-
> > > >base.id)) {
> > > - if (count < card_res->count_connectors
> > > &&
> > > - put_user(connector->base.id,
> > > connector_id + count)) {
> > > - drm_connector_list_iter_end(
> > > n_iter);
> > > - return -EFAULT;
> > > + if (connector->connector_type !=
> > > DRM_MODE_CONNECTOR_DisplayPort ||
> > > + connector->status !=
> > > connector_status_disconnected) {
> > > + if (count < card_res-
> > > >count_connectors &&
> > > + put_user(connector->base.id, 
> > > connector_id + count)) {
> > > + drm_connector_list_iter_
> > > end(_iter);
> > > + return -EFAULT;
> > > + }
> > > + DRM_DEBUG_KMS("GetResources:
> > > connector %s", connector->name);
> > > + count++;
> > 
> > I tried to read the bug and I have no idea what's going on here.
> > Userspace
> > is supposed to shut off outputs that are disconnected, whether
> > that's DP,
> > DP MST or something else shouldn't matter. New connectors can
> > come as
> > they see fit. Also not really something special.
> > 
> > Why do we need to dynamically hide an output here? Note that this
> > also
> > affects normal DP ports, which I have no idea is actually what you
> > want to
> > do or not.

This bug is real and easily reproducible with recent drm-tip.
Unplugging and then quickly plugging back periodically leaves both my
external displays connected to the docking station blank, there are
also many duplicate bugs for this, which I simply didn't track. This
patch at least fixes that annoying thing. 
The userspace seems to get confused when we are returning two different
connector ids, one in disconnected state and another in connected state
for the same output. This results in userspace believing that nothing
had changed and drm_mode_setcrtc call is not required( I have done
traces confirming that theory). 

This could be also fixed in userspace by checking connectors more
carefully - that fix I've also implemented for Intel DDX and attached
to the bug, however seems that this happens also for Wayland.

> 
> For entertainment and other reasons, testing the below diff would be
> interesting.
> 
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 4de247ddf05f..e1b66396c83b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -499,6 +499,8 @@ static void
> intel_dp_register_mst_connector(struct drm_connector *connector)
>   drm_fb_helper_add_one_connector(_priv->fbdev-
> >helper,
>   connector);
>  
> + list_move(>head, >dev-
> >mode_config.connector_list);
> +
>   drm_connector_register(connector);
>  }
>  
-- 
Best Regards,

Lisovskiy Stanislav
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Support 64 bpp half float formats

2018-11-28 Thread Patchwork

== Series Details ==

Series: Support 64 bpp half float formats
URL   : https://patchwork.freedesktop.org/series/53212/
State : failure

== Summary ==

Applying: drm/fourcc: Add 64 bpp half float formats
Applying: drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane
Applying: drm/i915: Implement half float formats and pixel normalize property
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_drv.h
M   drivers/gpu/drm/i915/intel_sprite.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_sprite.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_sprite.c
Auto-merging drivers/gpu/drm/i915/intel_drv.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
error: Failed to merge in the changes.
Patch failed at 0003 drm/i915: Implement half float formats and pixel normalize 
property
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH 1/3] drm/fourcc: Add 64 bpp half float formats

2018-11-28 Thread Kevin Strasser

Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.

An 'is_fp' attribute is added to drm_format_info so that drivers can easily
distinguish these formats from those that might contain uint pixel data.

This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
  https://patchwork.kernel.org/patch/10072545/

Signed-off-by: Kevin Strasser 
Cc: Tina Zhang 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Ville Syrjälä 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_fourcc.c  | 4 
 include/drm/drm_fourcc.h  | 3 +++
 include/uapi/drm/drm_fourcc.h | 6 ++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index f523948..a7b969a 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ABGR,.depth = 32, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGBA,.depth = 32, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGRA,.depth = 32, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_XRGB16161616H,   .depth = 48, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true },
+   { .format = DRM_FORMAT_XBGR16161616H,   .depth = 48, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true },
+   { .format = DRM_FORMAT_ARGB16161616H,   .depth = 64, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, 
.is_fp = true },
+   { .format = DRM_FORMAT_ABGR16161616H,   .depth = 64, 
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, 
.is_fp = true },
{ .format = DRM_FORMAT_RGB888_A8,   .depth = 32, 
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8,   .depth = 32, 
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB_A8, .depth = 32, 
.num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index bcb389f..2c5aa19 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -133,6 +133,9 @@ struct drm_format_info {
 
/** @is_yuv: Is it a YUV format? */
bool is_yuv;
+
+   /** @is_fp: Is it a floating point format? */
+   bool is_fp;
 };
 
 /**
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e7e48f1f..530bce4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,12 @@ extern "C" {
 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] 
R:G:B:A 10:10:10:2 little endian */
 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] 
B:G:R:A 10:10:10:2 little endian */
 
+/* 64 bpp RGB IEEE-754 half-precision float (binary16) */
+#define DRM_FORMAT_XBGR16161616H fourcc_code('X', 'B', '4', 'H') /* [63:0] 
x:B:G:R 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616H fourcc_code('A', 'B', '4', 'H') /* [63:0] 
A:B:G:R 16:16:16:16 little endian */
+#define DRM_FORMAT_XRGB16161616H fourcc_code('X', 'R', '4', 'H') /* [63:0] 
x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ARGB16161616H fourcc_code('A', 'R', '4', 'H') /* [63:0] 
A:R:G:B 16:16:16:16 little endian */
+
 /* packed YCbCr */
 #define DRM_FORMAT_YUYVfourcc_code('Y', 'U', 'Y', 'V') /* 
[31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
 #define DRM_FORMAT_YVYUfourcc_code('Y', 'V', 'Y', 'U') /* 
[31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
-- 
2.7.4

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[Intel-gfx] [PATCH 2/3] drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane

2018-11-28 Thread Kevin Strasser

Add an optional property to allow applications to indicate what range their
floating point pixel data is normalized to. Drivers are free to choose what
ranges they want to support and can attach this property to each plane that
actually supports floating point formats

Signed-off-by: Kevin Strasser 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Ville Syrjälä 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_atomic.c|  2 ++
 drivers/gpu/drm/drm_atomic_uapi.c   |  4 +++
 drivers/gpu/drm/drm_color_mgmt.c| 68 +
 drivers/gpu/drm/drm_crtc_internal.h |  1 +
 include/drm/drm_color_mgmt.h|  9 +
 include/drm/drm_plane.h | 14 
 6 files changed, 98 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 1706ed1..1f520ef 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -624,6 +624,8 @@ static void drm_atomic_plane_print_state(struct drm_printer 
*p,
   drm_get_color_encoding_name(state->color_encoding));
drm_printf(p, "\tcolor-range=%s\n",
   drm_get_color_range_name(state->color_range));
+   drm_printf(p, "\tpixel-normalize-range=%s\n",
+  
drm_get_pixel_normalize_range_name(state->pixel_normalize_range));
 
if (plane->funcs->atomic_print_state)
plane->funcs->atomic_print_state(p, state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
b/drivers/gpu/drm/drm_atomic_uapi.c
index 86ac339..e79a23cd 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -566,6 +566,8 @@ static int drm_atomic_plane_set_property(struct drm_plane 
*plane,
state->color_encoding = val;
} else if (property == plane->color_range_property) {
state->color_range = val;
+   } else if (property == plane->pixel_normalize_range_property) {
+   state->pixel_normalize_range = val;
} else if (plane->funcs->atomic_set_property) {
return plane->funcs->atomic_set_property(plane, state,
property, val);
@@ -621,6 +623,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->color_encoding;
} else if (property == plane->color_range_property) {
*val = state->color_range;
+   } else if (property == plane->pixel_normalize_range_property) {
+   *val = state->pixel_normalize_range;
} else if (plane->funcs->atomic_get_property) {
return plane->funcs->atomic_get_property(plane, state, 
property, val);
} else {
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 581cc37..b1e2a0a 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -472,3 +472,71 @@ int drm_plane_create_color_properties(struct drm_plane 
*plane,
return 0;
 }
 EXPORT_SYMBOL(drm_plane_create_color_properties);
+
+static const char * const pixel_normalize_range_name[] = {
+   [DRM_PIXEL_NORMALIZE_RANGE_0_1] = "0.0 - 1.0",
+   [DRM_PIXEL_NORMALIZE_RANGE_0_255] = "0.0 - 255.0",
+};
+
+/**
+ * drm_get_pixel_normalize_range_name - return a string for pixel normalize
+ * range
+ * @range: pixel normalize range to compute name of
+ *
+ * In contrast to the other drm_get_*_name functions this one here returns a
+ * const pointer and hence is threadsafe.
+ */
+const char *drm_get_pixel_normalize_range_name(enum drm_pixel_normalize_range 
range)
+{
+   if (WARN_ON(range >= ARRAY_SIZE(pixel_normalize_range_name)))
+   return "unknown";
+
+   return pixel_normalize_range_name[range];
+}
+
+/**
+ * drm_plane_create_pixel_normalize_range_property - pixel normalize range
+ * property
+ * @plane: plane object
+ * @supported_ranges: bitfield indicating supported normalize ranges
+ * @default_range: default normalize range
+ *
+ * Create and attach plane specific PIXEL_NORMALIZE_RANGE property to @plane.
+ * The supported ranges should be provided in supported_ranges bitmask. Eeach
+ * bit set in the bitmask indicates that its number as enum value is supported.
+ */
+int drm_plane_create_pixel_normalize_range_property(struct drm_plane *plane,
+   u32 supported_ranges, enum drm_pixel_normalize_range default_range)
+{
+   struct drm_property *prop;
+   struct drm_prop_enum_list enum_list[DRM_PIXEL_NORMALIZE_RANGE_MAX];
+   int i, len = 0;
+
+   if (WARN_ON(supported_ranges == 0 ||
+   (supported_ranges & -BIT(DRM_PIXEL_NORMALIZE_RANGE_MAX)) != 
0 ||
+   (supported_ranges & BIT(default_range)) == 0))
+   return -EINVAL;
+
+   for (i = 0; i < DRM_PIXEL_NORMALIZE_RANGE_MAX; i++) {
+   if ((supported_ranges & BIT(i)) == 0)
+   continue;
+
+   enum_list[len].type = i;
+

[Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats

2018-11-28 Thread Kevin Strasser

This series defines new formats and adds a plane property to be used for
floating point framebuffer content. Implementation is then added to i915.

I have shared an IGT branch which adds test coverage for the new formats:
  https://github.com/strassek/xorg-intel-gpu-tools/tree/fp16

Kevin Strasser (3):
  drm/fourcc: Add 64 bpp half float formats
  drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane
  drm/i915: Implement half float formats and pixel normalize property

 drivers/gpu/drm/drm_atomic.c |  2 +
 drivers/gpu/drm/drm_atomic_uapi.c|  4 ++
 drivers/gpu/drm/drm_color_mgmt.c | 67 +++
 drivers/gpu/drm/drm_crtc_internal.h  |  1 +
 drivers/gpu/drm/drm_fourcc.c |  4 ++
 drivers/gpu/drm/i915/i915_reg.h  | 15 -
 drivers/gpu/drm/i915/intel_display.c | 47 
 drivers/gpu/drm/i915/intel_drv.h |  5 ++
 drivers/gpu/drm/i915/intel_sprite.c  | 82 ++--
 include/drm/drm_color_mgmt.h |  9 +++
 include/drm/drm_fourcc.h |  3 +
 include/drm/drm_plane.h  | 14 +
 include/uapi/drm/drm_fourcc.h|  6 ++
 13 files changed, 252 insertions(+), 7 deletions(-)

-- 
2.17.1

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[Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

2018-11-28 Thread Kevin Strasser

64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
  * 90/270 rotation not supported
  * Yf Tiling not supported
  * Frame Buffer Compression not supported
  * Color Keying not supported

The behavior of pixel normalize with non-float formats is currently
undefined. As such, the pixel normalize register is enabled iff the
framebuffer contains floating point pixel data.

Signed-off-by: Kevin Strasser 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Ville Syrjälä 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/i915_reg.h  | 15 ++-
 drivers/gpu/drm/i915/intel_display.c | 48 +
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 82 +---
 4 files changed, 143 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe..871d293 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6563,6 +6563,10 @@ enum {
 #define _PLANE_KEYMAX_1_A  0x701a0
 #define _PLANE_KEYMAX_2_A  0x702a0
 #define  PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_PIXEL_NORMALIZE_1_A 0x701a8
+#define _PLANE_PIXEL_NORMALIZE_2_A 0x702a8
+#define   PLANE_PIXEL_NORMALIZE_ENABLE (1 << 31)
+#define   PLANE_PIXEL_NORMALIZE_FACTOR_MASK0x
 #define _PLANE_AUX_DIST_1_A0x701c0
 #define _PLANE_AUX_DIST_2_A0x702c0
 #define _PLANE_AUX_OFFSET_1_A  0x701c4
@@ -6786,7 +6790,16 @@ enum {
 #define PLANE_COLOR_CTL(pipe, plane)   \
_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
 
-#/* SKL new cursor registers */
+#define _PLANE_PIXEL_NORMALIZE_1_B 0x711a8
+#define _PLANE_PIXEL_NORMALIZE_2_B 0x712a8
+#define _PLANE_PIXEL_NORMALIZE_1(pipe) \
+   _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B)
+#define _PLANE_PIXEL_NORMALIZE_2(pipe) \
+   _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
+#define PLANE_PIXEL_NORMALIZE(pipe, plane) \
+   _MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), 
_PLANE_PIXEL_NORMALIZE_2(pipe))
+
+/* SKL new cursor registers */
 #define _CUR_BUF_CFG_A 0x7017c
 #define _CUR_BUF_CFG_B 0x7117c
 #define CUR_BUF_CFG(pipe)  _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22..cbacb4b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+   case PLANE_CTL_FORMAT_XRGB_16161616F:
+   if (rgb_order) {
+   if (alpha)
+   return DRM_FORMAT_ABGR16161616H;
+   else
+   return DRM_FORMAT_XBGR16161616H;
+   } else {
+   if (alpha)
+   return DRM_FORMAT_ARGB16161616H;
+   else
+   return DRM_FORMAT_XRGB16161616H;
+   }
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+   case DRM_FORMAT_XBGR16161616H:
+   case DRM_FORMAT_ABGR16161616H:
+   return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+   case DRM_FORMAT_XRGB16161616H:
+   case DRM_FORMAT_ARGB16161616H:
+   return PLANE_CTL_FORMAT_XRGB_16161616F;
default:
MISSING_CASE(pixel_format);
}
@@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_color_ctl;
 }
 
+u32 icl_plane_pixel_normalize(uint32_t pixel_format,
+ enum drm_pixel_normalize_range range)
+{
+   /* 1.0 in half float */
+   u16 half_float_1 = 0x3c00;
+   /* 3.92E-3 in half float */
+   u16 half_float_255 = 0x1c04;
+
+   switch (pixel_format) {
+   case DRM_FORMAT_XRGB16161616H:
+   case DRM_FORMAT_XBGR16161616H:
+   case DRM_FORMAT_ARGB16161616H:
+   case DRM_FORMAT_ABGR16161616H:
+   switch (range) {
+   case DRM_PIXEL_NORMALIZE_RANGE_0_1:
+   return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_1;
+   case DRM_PIXEL_NORMALIZE_RANGE_0_255:
+   return

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev3)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915/psr: Get pipe id following atomic guidelines (rev3)
URL   : https://patchwork.freedesktop.org/series/53132/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10945


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_10945 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10945, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/3/mbox/

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_10945:

### IGT changes ###

 Possible regressions 

  * igt@gem_close_race@basic-threads:
- fi-bsw-kefka:   PASS -> INCOMPLETE

  
Known issues


  Here are the changes found in Patchwork_10945 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy:   PASS -> DMESG-WARN [fdo#102614]

  
 Possible fixes 

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362


Participating hosts (49 -> 44)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5220 -> Patchwork_10945

  CI_DRM_5220: b3a448de6828d0bd0397318d15ec143a3dfb553a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10945: 6f9263b860081021f1915f2a547d3cf9b3e0bcd7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6f9263b86008 drm/i915/psr: Get pipe id following atomic guidelines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10945/
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

2018-11-28 Thread Rodrigo Vivi

On Wed, Nov 28, 2018 at 02:13:12PM -0800, Souza, Jose wrote:
> On Wed, 2018-11-28 at 21:02 +, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
> > URL   : https://patchwork.freedesktop.org/series/53132/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934
> > 
> > 
> > Summary
> > ---
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_10934 absolutely need
> > to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the
> > changes
> >   introduced in Patchwork_10934, please notify your bug team to allow
> > them
> >   to document this new failure mode, which will reduce false
> > positives in CI.
> > 
> >   External URL: 
> > https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/mbox/
> > 
> > Possible new issues
> > ---
> > 
> >   Here are the unknown changes that may have been introduced in
> > Patchwork_10934:
> > 
> > ### IGT changes ###
> > 
> >  Possible regressions 
> > 
> >   * igt@i915_selftest@live_sanitycheck:
> > - fi-apl-guc: PASS -> DMESG-WARN
> > 
> >   * {igt@runner@aborted}:
> > - fi-apl-guc: NOTRUN -> FAIL
> 
> Both are pretty much non related with display, what do you think
> Rodrigo? It is a merge blocker?

I got addicted to see all green on CI. So I always prefer to
trigger a retest. So anyone following the link that is merged with
the patch doens't have to understand and analyze why it was merged
with BAT failure.

I just triggered the re-test for this patch.

Thanks,
Rodrigo.

> 
> > 
> >   
> > Known issues
> > 
> > 
> >   Here are the changes found in Patchwork_10934 that come from known
> > issues:
> > 
> > ### IGT changes ###
> > 
> >  Issues hit 
> > 
> >   * igt@i915_selftest@live_hangcheck:
> > - fi-kbl-7560u:   PASS -> INCOMPLETE [fdo#108044]
> > 
> >   * igt@kms_pipe_crc_basic@read-crc-pipe-a:
> > - fi-byt-clapper: PASS -> FAIL [fdo#107362]
> > 
> >   
> >   {name}: This element is suppressed. This means it is ignored when
> > computing
> >   the status of the difference (SUCCESS, WARNING, or
> > FAILURE).
> > 
> >   [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
> >   [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
> > 
> > 
> > Participating hosts (50 -> 44)
> > --
> > 
> >   Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> > squawks fi-bsw-cyan fi-ctg-p8600 
> > 
> > 
> > Build changes
> > -
> > 
> > * Linux: CI_DRM_5216 -> Patchwork_10934
> > 
> >   CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @
> > git://anongit.freedesktop.org/gfx-ci/linux
> >   IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @
> > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >   Patchwork_10934: 2ebde49b2d0906d8106b020a2b0480bc5f552a01 @
> > git://anongit.freedesktop.org/gfx-ci/linux
> > 
> > 
> > == Linux commits ==
> > 
> > 2ebde49b2d09 drm/i915/psr: Get pipe id following atomic guidelines
> > 
> > == Logs ==
> > 
> > For more details see: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10934/


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Get pipe id following atomic guidelines (rev3)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915/psr: Get pipe id following atomic guidelines (rev3)
URL   : https://patchwork.freedesktop.org/series/53132/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Get pipe id following atomic guidelines
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression 
using sizeof(void)

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915/cnl: Fix the formulae for register offsets (rev2)
URL   : https://patchwork.freedesktop.org/series/52960/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10944


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/52960/revisions/2/mbox/

Known issues


  Here are the changes found in Patchwork_10944 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u3}:PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850:   PASS -> INCOMPLETE [fdo#107718]

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m:   FAIL [fdo#108880] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: FAIL [fdo#108769] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108769]: https://bugs.freedesktop.org/show_bug.cgi?id=108769
  [fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880


Participating hosts (49 -> 43)
--

  Additional (1): fi-byt-j1900 
  Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 


Build changes
-

* Linux: CI_DRM_5220 -> Patchwork_10944

  CI_DRM_5220: b3a448de6828d0bd0397318d15ec143a3dfb553a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10944: 70af57c2affce2b9eaa8dfbd777a6d4395d2ce79 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

70af57c2affc drm/i915/cnl: Fix the formulae for register offsets

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10944/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the HDMI hot plug disconnection failure (rev4)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915: Fix the HDMI hot plug disconnection failure (rev4)
URL   : https://patchwork.freedesktop.org/series/50477/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10943


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/50477/revisions/4/mbox/

Known issues


  Here are the changes found in Patchwork_10943 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850:   PASS -> INCOMPLETE [fdo#107718]

  
 Possible fixes 

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718


Participating hosts (49 -> 44)
--

  Additional (1): fi-byt-j1900 
  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5220 -> Patchwork_10943

  CI_DRM_5220: b3a448de6828d0bd0397318d15ec143a3dfb553a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10943: 74baf446cd7cf1e0493a37fa34381575e7b79f94 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

74baf446cd7c drm/i915: Fix the HDMI hot plug disconnection failure (v4)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10943/
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[Intel-gfx] [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets

2018-11-28 Thread Radhakrishna Sripada

For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well
for higher slices.

v2: Use _PICK instead of formulae(Jani)

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Cc: Lucs De Marchi 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/i915_reg.h | 54 -
 1 file changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..3b8ee7dd9b62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8662,18 +8662,60 @@ enum {
 #define   CHV_EU311_PG_ENABLE  (1 << 1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice) * 0x4)
-#define GEN10_SLICE_PGCTL_ACK(slice)   _MMIO(0x804c + ((slice) / 3) * 0x34 + \
- ((slice) % 3) * 0x4)
+
+#define _CNL_SLICE0_PGCTL_ACK  0x804c
+#define _CNL_SLICE1_PGCTL_ACK  0x8050
+#define _CNL_SLICE2_PGCTL_ACK  0x8054
+#define _CNL_SLICE3_PGCTL_ACK  0x8080
+#define _CNL_SLICE4_PGCTL_ACK  0x8084
+#define _CNL_SLICE5_PGCTL_ACK  0x8088
+
+#define GEN10_SLICE_PGCTL_ACK(slice)   _MMIO(_PICK(slice, \
+   _CNL_SLICE0_PGCTL_ACK, \
+   _CNL_SLICE1_PGCTL_ACK, \
+   _CNL_SLICE2_PGCTL_ACK, \
+   _CNL_SLICE3_PGCTL_ACK, \
+   _CNL_SLICE4_PGCTL_ACK, \
+   _CNL_SLICE5_PGCTL_ACK))
+
 #define   GEN9_PGCTL_SLICE_ACK (1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)  (1 << (2 + (subslice) * 2))
 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice)  _MMIO(0x805c + (slice) * 0x8)
-#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
- ((slice) % 3) * 0x8)
+
+#define _CNL_SLICE0_SS01_EU_PGCTL_ACK  0x805c
+#define _CNL_SLICE1_SS01_EU_PGCTL_ACK  0x8064
+#define _CNL_SLICE2_SS01_EU_PGCTL_ACK  0x806c
+#define _CNL_SLICE3_SS01_EU_PGCTL_ACK  0x808c
+#define _CNL_SLICE4_SS01_EU_PGCTL_ACK  0x8094
+#define _CNL_SLICE5_SS01_EU_PGCTL_ACK  0x809c
+
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
+   
_CNL_SLICE0_SS01_EU_PGCTL_ACK, \
+   
_CNL_SLICE1_SS01_EU_PGCTL_ACK, \
+   
_CNL_SLICE2_SS01_EU_PGCTL_ACK, \
+   
_CNL_SLICE3_SS01_EU_PGCTL_ACK, \
+   
_CNL_SLICE4_SS01_EU_PGCTL_ACK, \
+   
_CNL_SLICE5_SS01_EU_PGCTL_ACK))
+
 #define GEN9_SS23_EU_PGCTL_ACK(slice)  _MMIO(0x8060 + (slice) * 0x8)
-#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
- ((slice) % 3) * 0x8)
+
+#define _CNL_SLICE0_SS23_EU_PGCTL_ACK  0x8060
+#define _CNL_SLICE1_SS23_EU_PGCTL_ACK  0x8068
+#define _CNL_SLICE2_SS23_EU_PGCTL_ACK  0x8070
+#define _CNL_SLICE3_SS23_EU_PGCTL_ACK  0x8090
+#define _CNL_SLICE4_SS23_EU_PGCTL_ACK  0x8098
+#define _CNL_SLICE5_SS23_EU_PGCTL_ACK  0x80a0
+
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
+   
_CNL_SLICE0_SS23_EU_PGCTL_ACK, \
+   
_CNL_SLICE1_SS23_EU_PGCTL_ACK, \
+   
_CNL_SLICE2_SS23_EU_PGCTL_ACK, \
+   
_CNL_SLICE3_SS23_EU_PGCTL_ACK, \
+   
_CNL_SLICE4_SS23_EU_PGCTL_ACK, \
+   
_CNL_SLICE5_SS23_EU_PGCTL_ACK))
+
 #define   GEN9_PGCTL_SSA_EU08_ACK  (1 << 0)
 #define   GEN9_PGCTL_SSA_EU19_ACK  (1 << 2)
 #define   GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
-- 
2.9.3

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[Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v4)

2018-11-28 Thread Guang Bai

On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes
the kernel to believe the HDMI display is still connected. This is because
the HDMI DDC lines are disconnected a little bit later after the hot-plug
interrupt triggered thus an immediate edid fetch can be made. This problem
has been identified by more than one customer recently. Use digital
port live states to authorize the edid read at HDMI detection point will
ensure most of the display related software states updated and rest of them
will be renewed accordingly when the port is connected.

v2: Fix the formatting issue
v3: Use digital port states to authorize the edid read
v4: Add comments on issue histories and rationale of the fix (Chris W)

Cc: Jani Nikula 
Cc: Chris Chiu 
Cc: Chris Wilson 
Signed-off-by: Guang Bai 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index e2c6a2b..8cf7c78 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1929,7 +1929,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool 
force)
 
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 
-   if (IS_ICELAKE(dev_priv) &&
+   if ((IS_ICELAKE(dev_priv) || IS_GEN9_BC(dev_priv)) &&
!intel_digital_port_connected(encoder))
goto out;
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations

2018-11-28 Thread Lyude Paul


On Wed, 2018-11-28 at 09:17 +0100, Daniel Vetter wrote:
> On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote:
> > On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote:
> > 
> > We could do this the other way around so it looks like this maybe
> > 
> > struct kref; /* manages kfree() */
> > struct topology_kref; /* corresonds to lifetime in topology */
> > 
> > Then only expose functions for the normal kref to drivers, so that any
> > possible confusion is still limited to drm_dp_mst_topology.c
> 
> I like this bikeshed a lot. Since we need a bunch of the plain
> kref_get/put internally, probably still good to have a wrapper. For that
> the port_malloc_get/put() still sounds good to me - port_kfree_get/put
> sounds confusing, since it's not the kfree we're refcounting, but the
> memory allocation.
> 
> Another option would be to add _topology to the public get/put functions,
> but that makes for a fairly long function name :-/

bleh. Looked at not using a malloc() prefix in the naming but it's
definitely still more confusing without one.

I really do question if we really want the canonical naming prefix for the MST
helpers to be drm_dp_mst_topology. It would be very nice to have this freed so
we could do something like this:

drm_dp_mst_topology_get_mstb() /* _kref */
drm_dp_mst_topology_put_mstb() /* _kref */
drm_dp_mst_get_mstb_malloc()   /*  */
drm_dp_mst_put_mstb_malloc()   /*  */

drm_dp_mst_topology_get_port() /* _kref */
drm_dp_mst_topology_put_port() /* _kref */
drm_dp_mst_get_port_malloc()   /*  */
drm_dp_mst_put_port_malloc()   /*  */

Additionally, I had an epiphany and figured out a seriously dead-simple
rule that answers "what ref to use where" in the MST helper code:

Let's start with a topology like this:

  |- mst_primary
 |- port #1
 |- port #2
 |- port #3
|- mstb #1
   |- port #4
  |- mstb #2
   |- port #5
   |- port #6
  |- mstb #3
 |- port #7
|- mstb #4
 |- port #8
 |- port #9

If mstb #1 was removed from the topology, ports 4-9 and mstbs 2-4 must
lose their topology references. Simply put: each port holds a topology
reference to it's mstb (if there is one), and each mstb holds a topology
reference to it's ports.

Now, let's allocate some payloads on the topology:

  |- mst_primary
 |- port #1
 |- port #2
 |- port #3
|- mstb #1
   |- port #4
  |- mstb #2 (has payload)
   |- port #5
   |- port #6
  |- mstb #3
 |- port #7
|- mstb #4 (has payload)
 |- port #8
 |- port #9

So, now if we remove mstb #1 any payloads under it need to be freed.
Since mstb #4's and #2's parents no longer exist in the topology
however, we must go back up the tree to find our last living relative.

So:

mstb #4 → port #7 → mstb #3 → port #6 → mstb #1 → port #3   for payload 1
mstb #4 → port #4 → mstb #1 → port #3   for payload 2

Going off this we can come up with the rule for malloc refs: each port
holds a malloc ref to it's parent mstb, and each mstb holds a malloc ref
to it's parent port (if there is one). So, it's just the reverse of the
topology ref rule. Now just add refs for payloads and other stuff, and
we're good.

Hooray! Now I can also use this in any docs I write too :)

> -Daniel
> 
> > > > > -Daniel
> > > > > 
> > > > > > Piles of comments below.
> > > > > > 
> > > > > > Cheers, Daniel
> > > > > > 
> > > > > > >  - Use the small changes to drm_dp_put_port() to add even more
> > > > > > > error
> > > > > > >checking to make misusage of the helpers more obvious. I
> > > > > > > added
> > > > > > > this
> > > > > > >after having to chase down various use-after-free conditions
> > > > > > > that
> > > > > > >started popping up from the new helpers so no one else has to
> > > > > > >troubleshoot that.
> > > > > > >  - Move some accidental DRM_DEBUG_KMS() calls to
> > > > > > > DRM_DEBUG_ATOMIC()
> > > > > > >  - Update documentation again, note that find/release() should
> > > > > > > both
> > > > > > > not
> > > > > > > be
> > > > > > >called on the same port in a single atomic check phase (but
> > > > > > > multiple
> > > > > > >calls to one or the other is OK)
> > > > > > > 
> > > > > > > Changes since v4:
> > > > > > >  - Don't skip the atomic checks for VCPI allocations if no new
> > > > > > > VCPI
> > > > > > >allocations happen in a state. This makes the next change I'm
> > > > > > > about
> > > > > > >to list here a lot easier to implement.
> > > > > > >  - Don't ignore VCPI allocations on destroyed ports, instead
> > > > > > > ensure
> > > > > > > that
> > > > > > >when ports are destroyed and still have VCPI allocations in
> > > > > > > the
> > > > > > >topology state, the only state changes allowed are releasing
> > > > > > > said
> > > > > > >ports'

[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev9)

2018-11-28 Thread Patchwork

== Series Details ==

Series: HDCP1.4 fixes (rev9)
URL   : https://patchwork.freedesktop.org/series/38978/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10932_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10932_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10932_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10932_full:

### IGT changes ###

 Warnings 

  * igt@pm_rc6_residency@rc6-accuracy:
- shard-snb:  SKIP -> PASS

  
Known issues


  Here are the changes found in Patchwork_10932_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#106887]

  * igt@gem_softpin@noreloc-s3:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@i915_suspend@shrink:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#108784]

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb:  NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_color@pipe-a-legacy-gamma:
- shard-apl:  PASS -> FAIL [fdo#104782] / [fdo#108145]

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +3

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl:  NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x21-random:
- shard-skl:  PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_flip@flip-vs-fences:
- shard-kbl:  PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +22

  * igt@kms_flip_tiling@flip-to-y-tiled:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-apl:  PASS -> INCOMPLETE [fdo#103927]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-hsw:  PASS -> DMESG-WARN [fdo#102614] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk:  PASS -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-skl:  NOTRUN -> FAIL [fdo#105682] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-skl:  PASS -> FAIL [fdo#105682]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +3

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
- {shard-iclb}:   PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk:  PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl:  PASS -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl:  PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-kbl:  NOTRUN -> FAIL [fdo#103166]
- shard-skl:  NOTRUN -> FAIL [fdo#103166] / [fdo#107815]

  * igt@kms_rotation_crc@primary-rotation-180:
- shard-snb:  NOTRUN -> FAIL [fdo#103925]

  * igt@kms_setmode@basic:
- shard-hsw:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp-mst-helper: Remove hotplug callback

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/dp-mst-helper: Remove hotplug callback
URL   : https://patchwork.freedesktop.org/series/53192/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10942


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53192/revisions/1/mbox/

Known issues


  Here are the changes found in Patchwork_10942 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic-files:
- fi-bsw-n3050:   PASS -> FAIL [fdo#108656]

  * igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m:   PASS -> FAIL [fdo#108880]

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]

  
 Possible fixes 

  * igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: FAIL [fdo#108769] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
  [fdo#108769]: https://bugs.freedesktop.org/show_bug.cgi?id=108769
  [fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880


Participating hosts (49 -> 44)
--

  Additional (1): fi-pnv-d510 
  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5217 -> Patchwork_10942

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10942: 0825ba70571a92893a699ac3762b1b1aaa240ac3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0825ba70571a drm/dp-mst-helper: Remove hotplug callback

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10942/
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp-mst-helper: Remove hotplug callback

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/dp-mst-helper: Remove hotplug callback
URL   : https://patchwork.freedesktop.org/series/53192/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0825ba70571a drm/dp-mst-helper: Remove hotplug callback
-:167: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch 
author 'Daniel Vetter '

total: 0 errors, 1 warnings, 0 checks, 119 lines checked

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[Intel-gfx] ✗ Fi.CI.BAT: failure for HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)
URL   : https://patchwork.freedesktop.org/series/53191/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10940


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_10940 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10940, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53191/revisions/2/mbox/

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_10940:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live_guc:
- fi-bdw-gvtdvm:  PASS -> FAIL +15

  
 Warnings 

  * igt@kms_addfb_basic@addfb25-bad-modifier:
- fi-bdw-gvtdvm:  PASS -> SKIP +229

  


Participating hosts (49 -> 23)
--

  Missing(26): fi-kbl-soraka fi-cnl-u fi-icl-u2 fi-snb-2520m fi-icl-u3 
fi-blb-e6850 fi-byt-n2820 fi-hsw-4770r fi-bdw-5557u fi-bsw-n3050 fi-byt-j1900 
fi-bwr-2160 fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-gdg-551 fi-ivb-3770 
fi-elk-e7500 fi-ivb-3520m fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks 
fi-bsw-cyan fi-bsw-kefka fi-byt-clapper 


Build changes
-

* Linux: CI_DRM_5217 -> Patchwork_10940

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10940: 1a987393fb1ba3fb72a8d3202f57a3776c067a68 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1a987393fb1b HAX enable HuC for CI
4fdcb5ba00ae firmware/guc/glk: Load GuC v11.98 for Geminilake.
afc0b5259f0b firmware/huc/GLK: Load HuC for GLK
a6b97b520d1d firmware/huc/KBL: Update HuC for KBL
495993ba9aed firmware/huc/SKL: Update HuC versiom for SKL
2f174cb3de1c firmware/huc/BXT: Update the HuC version

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10940/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/icl: Release TC ports when unloading or suspending driver (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/icl: Release TC ports when 
unloading or suspending driver (rev2)
URL   : https://patchwork.freedesktop.org/series/52195/
State : failure

== Summary ==

Applying: drm/i915/icl: Release TC ports when unloading or suspending driver
error: corrupt patch at line 8
error: could not build fake ancestor
Patch failed at 0001 drm/i915/icl: Release TC ports when unloading or 
suspending driver
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK] (rev2)
URL   : https://patchwork.freedesktop.org/series/53191/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2f174cb3de1c firmware/huc/BXT: Update the HuC version
495993ba9aed firmware/huc/SKL: Update HuC versiom for SKL
a6b97b520d1d firmware/huc/KBL: Update HuC for KBL
afc0b5259f0b firmware/huc/GLK: Load HuC for GLK
4fdcb5ba00ae firmware/guc/glk: Load GuC v11.98 for Geminilake.
1a987393fb1b HAX enable HuC for CI
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 8 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC 
config to intel_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/53184/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10939


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53184/revisions/2/mbox/

Known issues


  Here are the changes found in Patchwork_10939 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_contexts:
- fi-bsw-kefka:   PASS -> DMESG-FAIL [fdo#108626] / [fdo#108656]

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108626]: https://bugs.freedesktop.org/show_bug.cgi?id=108626
  [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656


Participating hosts (49 -> 42)
--

  Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5217 -> Patchwork_10939

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10939: c878df13f9c00451f7281d105e0f2246cd65748c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c878df13f9c0 drm/i915/fec: Disable FEC state.
303f000edcd4 i915/dp/fec: Configure the Forward Error Correction bits.
2cb9fde528c3 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
9211bdb6b64b i915/dp/fec: Add fec_enable to the crtc state.
2f4fb87c9b59 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
1cfac339f7ea drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
ca153c0dbe0a drm/i915/dp: Configure Display stream splitter registers during 
DSC enable
ad3fbff47ade drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
909a40d71447 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
f078f264482d drm/i915/dp: Configure i915 Picture parameter Set registers during 
DSC enabling
0541a790e095 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
5a207b28b067 drm/i915/dp: Enable/Disable DSC in DP Sink
f0efd1a5bded drm/i915/dsc: Compute Rate Control parameters for DSC
682f70ba2e90 drm/i915/dsc: Define & Compute VESA DSC params
7e99dcca72b9 drm/i915/dp: Do not enable PSR2 if DSC is enabled
3251c57ea8f7 drm/i915/dp: Compute DSC pipe config in atomic check
6cc046b0e53f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10939/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Return only active connectors for get_resources ioctl

2018-11-28 Thread Patchwork

== Series Details ==

Series: Return only active connectors for get_resources ioctl
URL   : https://patchwork.freedesktop.org/series/53163/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10931_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_10931_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10931_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10931_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled:
- shard-skl:  NOTRUN -> FAIL

  
 Warnings 

  * igt@kms_lease@lease_unleased_connector:
- shard-apl:  PASS -> SKIP

  * igt@perf_pmu@rc6:
- shard-kbl:  PASS -> SKIP

  * igt@tools_test@tools_test:
- shard-snb:  PASS -> SKIP

  
Known issues


  Here are the changes found in Patchwork_10931_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#106887]

  * igt@gem_softpin@softpin:
- shard-apl:  PASS -> INCOMPLETE [fdo#103927]

  * igt@i915_suspend@shrink:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#108784]

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] +16

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb:  NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-glk:  PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] +2

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl:  NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x21-random:
- shard-skl:  PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-xtiled:
- {shard-iclb}:   PASS -> WARN [fdo#108336]

  * igt@kms_flip@flip-vs-expired-vblank:
- shard-skl:  NOTRUN -> FAIL [fdo#105363]

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk:  PASS -> FAIL [fdo#105363]

  * igt@kms_flip_tiling@flip-to-y-tiled:
- shard-skl:  PASS -> FAIL [fdo#107931]

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724] +3

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-skl:  NOTRUN -> FAIL [fdo#105682] +2

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk:  PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-skl:  PASS -> FAIL [fdo#105682]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +5

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- {shard-iclb}:   PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] / 
[fdo#107773]

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl:  PASS -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-glk:  PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl:

Re: [Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v2)

2018-11-28 Thread Guang Bai

On Tue, 13 Nov 2018 13:07:46 +0200
Jani Nikula  wrote:

> On Mon, 12 Nov 2018, Guang Bai  wrote:
> > Actually I'm still working on it right now with
> > DRM_MODE_CONNECTOR_HDMIA/HDMIB, recommended by James, I'm able to
> > differentiate the HDMI or DP even the encoder type is the
> > "INTEL_OUTPUT_DDI", I still have the "trybot" intermittent test
> > failures with new DRM connector types. Even worse, there is phantom
> > "intel_encoder_hotplug()" call following the correct one:
> > When connecting both DP and HDMI on the platform, unplug the DP, the
> > "i915_hotplug_work_func()" first calls the "intel_encoder_hotplug()"
> > with DP encoder, then calls again with HDMI encoder.
> > I haven't identified if the work function get queued twice or itself
> > is incorrectly identifying wrong encoder hotplut status. Will try to
> > get everything cleaned up ASAP.  
> 
> Frankly I liked the simplicity of [1] over the patch in this thread.
> It fixed the real-world use case Chris Chiu has, but I understand
> that it still failed the slow unplug HDMI test case you have. The
> problem is, we have zero visibility to the test case you have. Is it
> automated or manual? Can we see the specs or source code for the test
> case?
> 
> If we have to consider the live status unreliable, it's possible to
> devise a pathological test case that will always fail, regardless of
> what we do in the driver. Does the test case reflect real world usage?
> 
> Also Cc: Ville for input.
> 
> BR,
> Jani.
> 
Hi Jani, Ville & Chris (Chiu):
Sorry for the late reply as I have beening bumping around different
projects and also spent sometime to investigate [v2] failures with
testing the codes on trybot
1. My testcase: I have one+ customer KBL laptop and uBuntu16.04
running, slowly unplug the HDMI cable (wiggling), the issue can be
reproduced very easily - Just check kernel HDMI-A-1 connecting states
2. I belive Chris is using roughly the same test case?
3. I don't like the [v2] solution either since it's *not* clean and
have intermittent trybot/patchwork failures
4. with latest drm-tip codes, I'm able to workout a very clean solution
[v3] today and it passes the patchwork tests - Would you like to try it
out and also review the change?
Thanks,
Guang
> 
> 
> [1]
> http://patchwork.freedesktop.org/patch/msgid/20180925071836.24711-1-jani.nik...@intel.com
> 
> 

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC 
config to intel_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/53184/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression 
using sizeof(void)

Commit: drm/i915/dp: Compute DSC pipe config in atomic check
+drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)

Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled
Okay!

Commit: drm/i915/dsc: Define & Compute VESA DSC params
+drivers/gpu/drm/i915/intel_vdsc.c:352:17: warning: expression using 
sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from 
constant value (8000 becomes 0)

Commit: drm/i915/dsc: Compute Rate Control parameters for DSC
Okay!

Commit: drm/i915/dp: Enable/Disable DSC in DP Sink
Okay!

Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Okay!

Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC 
enabling
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression 
using sizeof(void)

Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Okay!

Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
Okay!

Commit: drm/i915/dp: Configure Display stream splitter registers during DSC 
enable
Okay!

Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression 
using sizeof(void)

Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC
Okay!

Commit: i915/dp/fec: Add fec_enable to the crtc state.
Okay!

Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Okay!

Commit: i915/dp/fec: Configure the Forward Error Correction bits.
Okay!

Commit: drm/i915/fec: Disable FEC state.
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC 
config to intel_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/53184/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6cc046b0e53f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible 
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:948:
+   bool compression_enable;

-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible 
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:949:
+   bool dsc_split;

total: 0 errors, 0 warnings, 2 checks, 22 lines checked
3251c57ea8f7 drm/i915/dp: Compute DSC pipe config in atomic check
7e99dcca72b9 drm/i915/dp: Do not enable PSR2 if DSC is enabled
682f70ba2e90 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68: 
Co-developed-by: Manasi Navare 

-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#119: 
new file mode 100644

total: 0 errors, 2 warnings, 0 checks, 497 lines checked
f0efd1a5bded drm/i915/dsc: Compute Rate Control parameters for DSC
5a207b28b067 drm/i915/dp: Enable/Disable DSC in DP Sink
0541a790e095 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
f078f264482d drm/i915/dp: Configure i915 Picture parameter Set registers during 
DSC enabling
-:391: WARNING:LONG_LINE: line over 100 characters
#391: FILE: drivers/gpu/drm/i915/intel_vdsc.c:897:
+   rc_range_params_dword[i / 2] |= 
(u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

total: 0 errors, 1 warnings, 0 checks, 426 lines checked
909a40d71447 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
ad3fbff47ade drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
ca153c0dbe0a drm/i915/dp: Configure Display stream splitter registers during 
DSC enable
1cfac339f7ea drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
2f4fb87c9b59 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
9211bdb6b64b i915/dp/fec: Add fec_enable to the crtc state.
-:126: CHECK:BOOL_MEMBER: Avoid using bool structure members because of 
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#126: FILE: drivers/gpu/drm/i915/intel_drv.h:956:
+   bool fec_enable;

total: 0 errors, 0 warnings, 1 checks, 65 lines checked
2cb9fde528c3 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
303f000edcd4 i915/dp/fec: Configure the Forward Error Correction bits.
c878df13f9c0 drm/i915/fec: Disable FEC state.

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the HDMI hot plug disconnection failure (rev3)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915: Fix the HDMI hot plug disconnection failure (rev3)
URL   : https://patchwork.freedesktop.org/series/50477/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10938


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/50477/revisions/3/mbox/

Known issues


  Here are the changes found in Patchwork_10938 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic-files:
- fi-bsw-n3050:   PASS -> FAIL [fdo#108656]

  * igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy:   PASS -> DMESG-WARN [fdo#102614]
- fi-byt-clapper: PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]

  
 Possible fixes 

  * igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: FAIL [fdo#108769] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
  [fdo#108769]: https://bugs.freedesktop.org/show_bug.cgi?id=108769


Participating hosts (49 -> 44)
--

  Additional (1): fi-pnv-d510 
  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5217 -> Patchwork_10938

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10938: 365b3fb384daa0f192de6e2414182d323e8422a4 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

365b3fb384da drm/i915: Fix the HDMI hot plug disconnection failure (v3)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10938/
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[Intel-gfx] ✓ Fi.CI.BAT: success for Return only active connectors for get_resources ioctl (rev3)

2018-11-28 Thread Patchwork

== Series Details ==

Series: Return only active connectors for get_resources ioctl (rev3)
URL   : https://patchwork.freedesktop.org/series/53163/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10937


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53163/revisions/3/mbox/

Known issues


  Here are the changes found in Patchwork_10937 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic-files:
- fi-bsw-kefka:   PASS -> FAIL [fdo#108656]

  * igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m:   PASS -> FAIL [fdo#108880]

  * igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-cfl-8109u:   PASS -> INCOMPLETE [fdo#106070] / [fdo#108126]

  * {igt@runner@aborted}:
- {fi-icl-u3}:NOTRUN -> FAIL [fdo#108315]

  
 Possible fixes 

  * igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: FAIL [fdo#108769] -> PASS

  
 Warnings 

  * igt@i915_selftest@live_contexts:
- {fi-icl-u3}:DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
  [fdo#108126]: https://bugs.freedesktop.org/show_bug.cgi?id=108126
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
  [fdo#108769]: https://bugs.freedesktop.org/show_bug.cgi?id=108769
  [fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880


Participating hosts (49 -> 44)
--

  Additional (1): fi-pnv-d510 
  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5217 -> Patchwork_10937

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10937: 14116c78b12f59eb6e2b7de6f07730fa261360d6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

14116c78b12f Return only active connectors for get_resources ioctl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10937/
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

2018-11-28 Thread Souza, Jose

On Wed, 2018-11-28 at 21:02 +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
> URL   : https://patchwork.freedesktop.org/series/53132/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_10934 absolutely need
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the
> changes
>   introduced in Patchwork_10934, please notify your bug team to allow
> them
>   to document this new failure mode, which will reduce false
> positives in CI.
> 
>   External URL: 
> https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/mbox/
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in
> Patchwork_10934:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live_sanitycheck:
> - fi-apl-guc: PASS -> DMESG-WARN
> 
>   * {igt@runner@aborted}:
> - fi-apl-guc: NOTRUN -> FAIL

Both are pretty much non related with display, what do you think
Rodrigo? It is a merge blocker?

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_10934 that come from known
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@i915_selftest@live_hangcheck:
> - fi-kbl-7560u:   PASS -> INCOMPLETE [fdo#108044]
> 
>   * igt@kms_pipe_crc_basic@read-crc-pipe-a:
> - fi-byt-clapper: PASS -> FAIL [fdo#107362]
> 
>   
>   {name}: This element is suppressed. This means it is ignored when
> computing
>   the status of the difference (SUCCESS, WARNING, or
> FAILURE).
> 
>   [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
>   [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
> 
> 
> Participating hosts (50 -> 44)
> --
> 
>   Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> squawks fi-bsw-cyan fi-ctg-p8600 
> 
> 
> Build changes
> -
> 
> * Linux: CI_DRM_5216 -> Patchwork_10934
> 
>   CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_10934: 2ebde49b2d0906d8106b020a2b0480bc5f552a01 @
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 2ebde49b2d09 drm/i915/psr: Get pipe id following atomic guidelines
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10934/


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[Intel-gfx] [PATCH] drm/dp-mst-helper: Remove hotplug callback

2018-11-28 Thread Daniel Vetter

When everyone implements it exactly the same way, among all 4
implementations, there's not really a need to overwrite this at all.

Aside: drm_kms_helper_hotplug_event is pretty much core functionality
at this point. Probably should move it there.

Signed-off-by: Daniel Vetter 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c|  9 -
 drivers/gpu/drm/drm_dp_mst_topology.c  |  7 ---
 drivers/gpu/drm/i915/intel_dp_mst.c| 10 --
 drivers/gpu/drm/nouveau/dispnv50/disp.c|  8 
 drivers/gpu/drm/radeon/radeon_dp_mst.c |  9 -
 include/drm/drm_dp_mst_helper.h|  2 --
 6 files changed, 4 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d02c32a1039c..9fdeca096407 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -396,14 +396,6 @@ static void dm_dp_destroy_mst_connector(struct 
drm_dp_mst_topology_mgr *mgr,
drm_connector_put(connector);
 }
 
-static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-{
-   struct amdgpu_dm_connector *master = container_of(mgr, struct 
amdgpu_dm_connector, mst_mgr);
-   struct drm_device *dev = master->base.dev;
-
-   drm_kms_helper_hotplug_event(dev);
-}
-
 static void dm_dp_mst_register_connector(struct drm_connector *connector)
 {
struct drm_device *dev = connector->dev;
@@ -420,7 +412,6 @@ static void dm_dp_mst_register_connector(struct 
drm_connector *connector)
 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
.add_connector = dm_dp_add_mst_connector,
.destroy_connector = dm_dp_destroy_mst_connector,
-   .hotplug = dm_dp_mst_hotplug,
.register_connector = dm_dp_mst_register_connector
 };
 
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 08978ad72f33..639552918b44 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /**
  * DOC: dp mst helper
@@ -1650,7 +1651,7 @@ static void drm_dp_send_link_address(struct 
drm_dp_mst_topology_mgr *mgr,
for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) {
drm_dp_add_port(mstb, mgr->dev, 
>reply.u.link_addr.ports[i]);
}
-   (*mgr->cbs->hotplug)(mgr);
+   drm_kms_helper_hotplug_event(mgr->dev);
}
} else {
mstb->link_address_sent = false;
@@ -2423,7 +2424,7 @@ static int drm_dp_mst_handle_up_req(struct 
drm_dp_mst_topology_mgr *mgr)
drm_dp_update_port(mstb, _stat);
 
DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d 
ip: %d pdt: %d\n", msg.u.conn_stat.port_number, 
msg.u.conn_stat.legacy_device_plug_status, 
msg.u.conn_stat.displayport_device_plug_status, 
msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, 
msg.u.conn_stat.peer_device_type);
-   (*mgr->cbs->hotplug)(mgr);
+   drm_kms_helper_hotplug_event(mgr->dev);
 
} else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, 
msg.req_type, seqno, false);
@@ -3120,7 +3121,7 @@ static void drm_dp_destroy_connector_work(struct 
work_struct *work)
send_hotplug = true;
}
if (send_hotplug)
-   (*mgr->cbs->hotplug)(mgr);
+   drm_kms_helper_hotplug_event(mgr->dev);
 }
 
 static struct drm_private_state *
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 4de247ddf05f..f05427b74e34 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -517,20 +517,10 @@ static void intel_dp_destroy_mst_connector(struct 
drm_dp_mst_topology_mgr *mgr,
drm_connector_put(connector);
 }
 
-static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-{
-   struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
-   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-   struct drm_device *dev = intel_dig_port->base.base.dev;
-
-   drm_kms_helper_hotplug_event(dev);
-}
-
 static const struct drm_dp_mst_topology_cbs mst_cbs = {
.add_connector = intel_dp_add_mst_connector,
.register_connector = intel_dp_register_mst_connector,
.destroy_connector = intel_dp_destroy_mst_connector,
-   .hotplug = intel_dp_mst_hotplug,
 };
 
 static struct intel_dp_mst_encoder *
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Add kbl A0 to preproduction detection list

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915: Add kbl A0 to preproduction 
detection list
URL   : https://patchwork.freedesktop.org/series/53162/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10930_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10930_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10930_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10930_full:

### IGT changes ###

 Warnings 

  * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
- shard-snb:  PASS -> SKIP +1

  * igt@pm_rc6_residency@rc6-accuracy:
- shard-snb:  SKIP -> PASS

  
Known issues


  Here are the changes found in Patchwork_10930_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_softpin@noreloc-s3:
- {shard-iclb}:   NOTRUN -> INCOMPLETE [fdo#107713]
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_color@pipe-b-legacy-gamma:
- shard-apl:  PASS -> FAIL [fdo#104782]

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +2

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl:  NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_flip_tiling@flip-to-y-tiled:
- shard-skl:  PASS -> FAIL [fdo#107931]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl:  PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk:  PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +2

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl:  PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
- {shard-iclb}:   PASS -> FAIL [fdo#103166]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-glk:  PASS -> FAIL [fdo#103166]

  * igt@kms_rotation_crc@primary-rotation-180:
- shard-snb:  NOTRUN -> FAIL [fdo#103925]

  * igt@kms_setmode@basic:
- shard-hsw:  PASS -> FAIL [fdo#99912]

  * igt@pm_rpm@system-suspend-modeset:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]

  
 Possible fixes 

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing:
- shard-apl:  INCOMPLETE [fdo#103927] -> PASS +1

  * igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl:  FAIL [fdo#107725] -> PASS

  * igt@kms_color@pipe-a-ctm-max:
- shard-apl:  FAIL [fdo#108147] -> PASS

  * igt@kms_color@pipe-b-degamma:
- shard-apl:  FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl:  FAIL [fdo#103191] / [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk:  FAIL [fdo#103232] -> PASS +2

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl:  FAIL [fdo#103232] -> PASS +2

  * igt@kms_draw_crc@draw-method-xrgb-pwrite-untiled:
- shard-skl:  FAIL [fdo#108472] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl:  FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl:  FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- {shard-iclb}:   FAIL [fdo#103167] -> PASS +3

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk:  FAIL [fdo#103167] -> PASS

  *

Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: Release TC ports when unloading or suspending driver

2018-11-28 Thread Souza, Jose

On Wed, 2018-11-28 at 13:34 +0200, Imre Deak wrote:
> On Wed, Nov 07, 2018 at 04:05:52PM -0800, José Roberto de Souza
> wrote:
> > When suspending or unloading the driver, it needs to release the
> > TC ports so HW can change it state without wait for driver
> > handshake.
> 
> According to 
> https://bugs.freedesktop.org/show_bug.cgi?id=108070#c26
> 
> this patch should fix the bug reported at
> https://bugs.freedesktop.org/show_bug.cgi?id=108070#c17
> 
> but, I can't see how the change here would fix the corresponding
> problem
> described in
> https://bugs.freedesktop.org/show_bug.cgi?id=108070#c18
> 
> Would you explain?
> 
> I think there are more fundamental problems in TypeC HPD handling as
> we
> discussed earlier here on the list, which should be fixed first:
> 
> - Switching to/from type C mode from the interrupt handler without
>   considering if we have an active mode or an ongoing AUX transfer.

Yes that is still missing, I plan to work on that after I deliver a few
tasks. Also I read the emails in discussion that you started about
that.

> 
> - Not having any way for handling the case where we'd do a modeset
> after
>   an HPD disconnect interrupt, like in the case of
>   common-hpd-after-suspend in the bug report.

For what I understood about this test it will suspend, disconnect
chamelium board from source, wakeup and check if connector state match,
as we did not marked port as safe before suspending we are left in a
invalid state where PD firmware do not trigger a interruption after
wakeup.

> 
> More comments below:
> 
> > Cc: Imre Deak 
> > Cc: Ville Syrjälä 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c  |  1 +
> >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
> >  drivers/gpu/drm/i915/i915_irq.c  |  1 +
> >  drivers/gpu/drm/i915/intel_dp.c  | 19 +++
> >  drivers/gpu/drm/i915/intel_drv.h |  1 +
> >  drivers/gpu/drm/i915/intel_hotplug.c |  9 +
> >  6 files changed, 32 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index acb516308262..14331c396278 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1911,6 +1911,7 @@ static int i915_drm_suspend(struct drm_device
> > *dev)
> >  
> > intel_runtime_pm_disable_interrupts(dev_priv);
> > intel_hpd_cancel_work(dev_priv);
> > +   intel_hpd_suspend(dev_priv);
> 
> What about runtime suspend? We won't receive HPD interrupts after
> that
> either, so we'd need to disconnect in that case too according to the
> spec.

Oh my bad I was thinking that the regular suspend would handle this too
but I was wrong.

So I will add a intel_hpd_suspend() call to intel_runtime_suspend()
leaving the i915_drv.c changes as this.

diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index b1d23c73c147..948914a79c67 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1905,6 +1905,7 @@ static int i915_drm_suspend(struct drm_device
*dev)

intel_runtime_pm_disable_interrupts(dev_priv);
intel_hpd_cancel_work(dev_priv);
+   intel_hpd_suspend(dev_priv);

intel_suspend_encoders(dev_priv);

@@ -2909,6 +2910,7 @@ static int intel_runtime_suspend(struct device
*kdev)
intel_uc_suspend(dev_priv);

intel_runtime_pm_disable_interrupts(dev_priv);
+   intel_hpd_suspend(dev_priv);

intel_uncore_suspend(dev_priv);

Also I will drop the next patch as we don't call
intel_hpd_cancel_work() in intel_runtime_suspend() path.


> 
> And how are we handling resume then where we'll be in a disconnected
> state due to the change in this patch and would continue to do a
> modeset (to restore the mode we had before suspend).

The drm_kms_helper_poll_enable() calls will trigger the call to the
detection function of the connectors that will call
intel_digital_port_connected() thal will call ICL TC functions that
will take care of update everything.

> 
> >  
> > intel_suspend_encoders(dev_priv);
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 0c8438de3c1b..96d5ddc36f4e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2792,6 +2792,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> > drm_i915_private *dev_priv,
> >enum port port);
> >  bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum
> > hpd_pin pin);
> >  void intel_hpd_enable(struct drm_i915_private *dev_priv, enum
> > hpd_pin pin);
> > +void intel_hpd_suspend(struct drm_i915_private *dev_priv);
> >  
> >  /* i915_irq.c */
> >  static inline void i915_queue_hangcheck(struct drm_i915_private
> > *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index d7e47d6082de..23084d227e2a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++

Re: [Intel-gfx] [PATCH v5 4/5] drm: Add library for shmem backed GEM objects

2018-11-28 Thread Eric Anholt

Daniel Vetter  writes:

> On Tue, Nov 27, 2018 at 12:38:44PM -0800, Eric Anholt wrote:
>> Daniel Vetter  writes:
>> 
>> > On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote:
>> >> Noralf Trønnes  writes:
>> >> > +static void drm_gem_shmem_vm_close(struct vm_area_struct *vma)
>> >> > +{
>> >> > +   struct drm_gem_object *obj = vma->vm_private_data;
>> >> > +   struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
>> >> > +
>> >> > +   drm_gem_shmem_put_pages(shmem);
>> >> > +   drm_gem_vm_close(vma);
>> >> > +}
>> >> > +
>> >> > +const struct vm_operations_struct drm_gem_shmem_vm_ops = {
>> >> > +   .fault = drm_gem_shmem_fault,
>> >> > +   .open = drm_gem_vm_open,
>> >> > +   .close = drm_gem_shmem_vm_close,
>> >> > +};
>> >> > +EXPORT_SYMBOL_GPL(drm_gem_shmem_vm_ops);
>> >> 
>> >> I just saw a warning from drm_gem_shmem_put_pages() for
>> >> !shmem->pages_use_count -- I think drm_gem_vm_open() needs to
>> >> drm_gem_shmem_get_pages().
>> >
>> > Yeah we need a drm_gem_shmem_vm_open here.
>> 
>> Adding one of those fixed my refcounting issues, so I've sent out a v6
>> with it.
>
> Just realized that I've reviewed this patch already, spotted that vma
> management issue there too. Plus a pile of other things. From reading that
> other thread discussion with Noralf concluded with "not yet ready for
> prime time" unfortunately :-/

I saw stuff about how it wasn't usable for SPI because SPI does weird
things with DMA mapping.  Was there something else?


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Return only active connectors for get_resources ioctl (rev3)

2018-11-28 Thread Patchwork

== Series Details ==

Series: Return only active connectors for get_resources ioctl (rev3)
URL   : https://patchwork.freedesktop.org/series/53163/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
14116c78b12f Return only active connectors for get_resources ioctl
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#26: 
> > > diff --git a/drivers/gpu/drm/drm_mode_config.c 
> > > b/drivers/gpu/drm/drm_mode_config.c

-:90: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 16 lines checked

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[Intel-gfx] [PATCH 5/6] firmware/guc/glk: Load GuC v11.98 for Geminilake.

2018-11-28 Thread Anusha

From: John Spotswood 

load the v11.98 guC on geminilake.

v2: rebased.

v3: Change subject prefix. (Anusha)

Cc: Tomi Sarvela 
Cc: Jani Saarinen 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: John Spotswood 
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a67144ee5ceb..55900937882a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
 #define KBL_FW_MAJOR 9
 #define KBL_FW_MINOR 39
 
+#define GLK_FW_MAJOR 11
+#define GLK_FW_MINOR 98
+
 #define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" 
__stringify(minor) ".bin"
 
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
+#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
+MODULE_FIRMWARE(I915_GLK_GUC_UCODE);
+
 static void guc_fw_select(struct intel_uc_fw *guc_fw)
 {
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+   } else if (IS_GEMINILAKE(dev_priv)) {
+   guc_fw->path = I915_GLK_GUC_UCODE;
+   guc_fw->major_ver_wanted = GLK_FW_MAJOR;
+   guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
dev_info(dev_priv->drm.dev,
 "%s: No firmware known for this platform!\n",
-- 
2.19.1

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[Intel-gfx] [PATCH 6/6] HAX enable HuC for CI

2018-11-28 Thread Anusha

From: Anusha Srivatsa 

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..fa65edeb0202 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.19.1

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[Intel-gfx] [PATCH 3/6] firmware/huc/KBL: Update HuC for KBL

2018-11-28 Thread Anusha

From: Anusha Srivatsa 

We have an update of HuC for KBL.
Load the latest version.

cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c 
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 4c4f21731d36..1fa10e327a2d 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -30,9 +30,9 @@
 #define SKL_HUC_FW_MINOR 8
 #define SKL_BLD_NUM 2893
 
-#define KBL_HUC_FW_MAJOR 02
-#define KBL_HUC_FW_MINOR 00
-#define KBL_BLD_NUM 1810
+#define KBL_HUC_FW_MAJOR 03
+#define KBL_HUC_FW_MINOR 01
+#define KBL_BLD_NUM 2893
 
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
-- 
2.19.1

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[Intel-gfx] [PATCH 4/6] firmware/huc/GLK: Load HuC for GLK

2018-11-28 Thread Anusha

From: Anusha Srivatsa 

Load Huc for GLK.

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_huc_fw.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c 
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 1fa10e327a2d..634bafb77d79 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
 #define KBL_HUC_FW_MINOR 01
 #define KBL_BLD_NUM 2893
 
+#define GLK_HUC_FW_MAJOR 03
+#define GLK_HUC_FW_MINOR 01
+#define GLK_BLD_NUM 2893
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
 
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+   GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
 static void huc_fw_select(struct intel_uc_fw *huc_fw)
 {
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+   } else if (IS_GEMINILAKE(dev_priv)) {
+   huc_fw->path = I915_GLK_HUC_UCODE;
+   huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
 intel_uc_fw_type_repr(huc_fw->type));
-- 
2.19.1

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[Intel-gfx] [PATCH 2/6] firmware/huc/SKL: Update HuC versiom for SKL

2018-11-28 Thread Anusha

From: Anusha Srivatsa 

We have an update of huC for SKL.
Load the latest verion.

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c 
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 9612227b3c44..4c4f21731d36 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -27,8 +27,8 @@
 #define BXT_BLD_NUM 2893
 
 #define SKL_HUC_FW_MAJOR 01
-#define SKL_HUC_FW_MINOR 07
-#define SKL_BLD_NUM 1398
+#define SKL_HUC_FW_MINOR 8
+#define SKL_BLD_NUM 2893
 
 #define KBL_HUC_FW_MAJOR 02
 #define KBL_HUC_FW_MINOR 00
-- 
2.19.1

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[Intel-gfx] [PATCH 1/6] firmware/huc/BXT: Update the HuC version

2018-11-28 Thread Anusha

From: Anusha Srivatsa 

We have an update for HuC for BXT.
Load the latest version.

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c 
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d2384d482..9612227b3c44 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -23,8 +23,8 @@
  */
 
 #define BXT_HUC_FW_MAJOR 01
-#define BXT_HUC_FW_MINOR 07
-#define BXT_BLD_NUM 1398
+#define BXT_HUC_FW_MINOR 8
+#define BXT_BLD_NUM 2893
 
 #define SKL_HUC_FW_MAJOR 01
 #define SKL_HUC_FW_MINOR 07
-- 
2.19.1

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[Intel-gfx] [PATCH 0/6] HuC Updates [BXT,SKL,KBL,GLK] GuC [GLK]

2018-11-28 Thread Anusha

Adding PR -
The following changes since commit 1baa34868b2c0a004dc595b20678145e3fff83e7:

Merge branch 'nxp_mc' of https://github.com/NXP/linux-firmware (2018-10-26 
08:13:19 -0400)

are available in the Git repository at:

git://anongit.freedesktop.org/drm/drm-firmware firmware_updates

for you to fetch changes up to 908244c9c196116069fc6ba43573192ad08ea3af:

  firmware/guc/GLK: Add GuC Support for GLK (2018-11-28 10:40:38 -0800)

Anusha Srivatsa (5):
  firmware/huc/BXT: Update the HuC version
  firmware/huc/SKL: Update HuC versiom for SKL
  firmware/huc/KBL: Update HuC for KBL
  firmware/huc/GLK: Load HuC for GLK
  HAX enable HuC for CI

John Spotswood (1):
  firmware/guc/glk: Load GuC v11.98 for Geminilake.

 drivers/gpu/drm/i915/i915_params.h  |  2 +-
 drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
 drivers/gpu/drm/i915/intel_huc_fw.c | 26 +++---
 3 files changed, 30 insertions(+), 8 deletions(-)

-- 
2.19.1

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Re: [Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v3)

2018-11-28 Thread Chris Wilson

Quoting Guang Bai (2018-11-28 21:18:13)
> On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes
> the kernel to believe the HDMI display is still connected. This is because
> the HDMI DDC lines are disconnected a little bit later after the hot-plug
> interrupt triggered thus an immediate edid fetch can be made. Use digital
> port live states to authorize the edid read.

You should at least comment upon why we don't historically do this and
why you now believe that it is safe.
-Chris
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[Intel-gfx] [PATCH v14 02/17] drm/i915/dp: Compute DSC pipe config in atomic check

2018-11-28 Thread Manasi Navare

DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.

v15:
* Rebase over drm-tip
v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)

v7:
* Fix indentation in compute_m_n (Manasi)

v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)

v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)

v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)

v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)

v2:
* Add if-else for eDP/DP (Gaurav)

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Cc: Gaurav K Singh 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
Reviewed-by: Ville Syrjala 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_display.c |   2 +-
 drivers/gpu/drm/i915/intel_display.h |   3 +-
 drivers/gpu/drm/i915/intel_dp.c  | 192 ---
 3 files changed, 172 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d07fa4456150..18ab713f9a6b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6736,7 +6736,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
 }
 
 void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
   struct intel_link_m_n *m_n,
   bool constant_n)
diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index a7ceb8f904f7..3ec704c93d6e 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -440,10 +440,9 @@ struct intel_link_m_n {
 (__i)++) \
for_each_if(crtc)
 
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
-
 bool is_ccs_modifier(u64 modifier);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 70ae3d57316b..a2780733768a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
 
 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC   8
+#define DP_DSC_MAX_SUPPORTED_BPC   10
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
 };
 
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state 
*pipe_config)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+   /* FIXME: FEC needed for external DP until then reject DSC on DP */
+   if (!intel_dp_is_edp(intel_dp))
+   return false;
+
+   return INTEL_GEN(dev_priv) >= 10 &&
+   pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+   return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+   drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+}
+
 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
 {
@@ -1842,14 +1864,115 @@ intel_dp_compute_link_config_fast(struct intel_dp 
*intel_dp,
return false;
 }
 
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+{
+   int i, num_bpc;
+   u8 dsc_bpc[3] = {0};
+
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+

[Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v3)

2018-11-28 Thread Guang Bai

On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable makes
the kernel to believe the HDMI display is still connected. This is because
the HDMI DDC lines are disconnected a little bit later after the hot-plug
interrupt triggered thus an immediate edid fetch can be made. Use digital
port live states to authorize the edid read.

v2: Fix the formatting issue
v3: Use digital port states to authorize the edid read

Cc: Jani Nikula 
Cc: Chris Chiu 
Signed-off-by: Guang Bai 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index e2c6a2b3e8f2..8cf7c78b8cdd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1929,7 +1929,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool 
force)
 
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 
-   if (IS_ICELAKE(dev_priv) &&
+   if ((IS_ICELAKE(dev_priv) || IS_GEN9_BC(dev_priv)) &&
!intel_digital_port_connected(encoder))
goto out;
 
-- 
2.17.1

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[Intel-gfx] [PULL v2] drm-misc-fixes

2018-11-28 Thread Sean Paul


Hi Dave,
Here's the updated PR with the mst destroy patch reverted.

drm-misc-fixes-2018-11-28-1:
- mst: Don't try to validate ports while destroying them (Lyude)
- Revert: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Sergio)
- meson: Do vblank_on/off on enable/disable (Neil)
- meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
- meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)

Cc: Lyude Paul 
Cc: Sergio Correia 
Cc: Neil Armstrong 

Cheers, Sean

For completeness, here's my summary from the v1:
---
Hi Dave,
Happy meson week! A bunch of stellar fixes coming in this week from Lyude, and a
couple others plugging holes in meson and core.


drm-misc-fixes-2018-11-28:
- mst: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Sergio)
- meson: Do vblank_on/off on enable/disable (Neil)
- meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
- meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)

Cc: Lyude Paul 
Cc: Sergio Correia 
Cc: Neil Armstrong 

Cheers, Sean
---


The following changes since commit 2e6e902d185027f8e3cb8b7305238f7e35d6a436:

  Linux 4.20-rc4 (2018-11-25 14:19:31 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2018-11-28-1

for you to fetch changes up to 9765635b30756eb74e05e260ac812659c296cd28:

  Revert "drm/dp_mst: Skip validating ports during destruction, just ref" 
(2018-11-28 16:22:17 -0500)


- mst: Don't try to validate ports while destroying them (Lyude)
- Revert: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Sergio)
- meson: Do vblank_on/off on enable/disable (Neil)
- meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
- meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)

Cc: Lyude Paul 
Cc: Sergio Correia 
Cc: Neil Armstrong 


Christian Hewitt (1):
  drm/meson: add support for 1080p25 mode

Lyude Paul (4):
  drm/dp_mst: Skip validating ports during destruction, just ref
  drm/meson: Enable fast_io in meson_dw_hdmi_regmap_config
  drm/meson: Fix OOB memory accesses in meson_viu_set_osd_lut()
  Revert "drm/dp_mst: Skip validating ports during destruction, just ref"

Neil Armstrong (1):
  drm/meson: Fixes for drm_crtc_vblank_on/off support

Sergio Correia (1):
  drm: set is_master to 0 upon drm_new_set_master() failure

 drivers/gpu/drm/drm_auth.c|  2 ++
 drivers/gpu/drm/meson/meson_crtc.c| 27 +--
 drivers/gpu/drm/meson/meson_dw_hdmi.c |  1 +
 drivers/gpu/drm/meson/meson_venc.c|  4 
 drivers/gpu/drm/meson/meson_viu.c | 12 ++--
 5 files changed, 38 insertions(+), 8 deletions(-)

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync 
registers on ring init
URL   : https://patchwork.freedesktop.org/series/53185/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10936


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53185/revisions/1/mbox/

Known issues


  Here are the changes found in Patchwork_10936 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s4-devices:
- {fi-kbl-7500u}: PASS -> DMESG-WARN [fdo#105128] / [fdo#107139]

  * {igt@runner@aborted}:
- {fi-icl-u3}:NOTRUN -> FAIL [fdo#108866 ]

  
 Warnings 

  * igt@i915_selftest@live_contexts:
- {fi-icl-u3}:DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108866 ]: https://bugs.freedesktop.org/show_bug.cgi?id=108866 


Participating hosts (50 -> 43)
--

  Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 


Build changes
-

* Linux: CI_DRM_5216 -> Patchwork_10936

  CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10936: ae4f82c5d364231a64f059987ea6cc7ffe0a01b7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ae4f82c5d364 drm/i915: Pipeline PDP updates for Braswell
08ed6c2f4294 drm/i915/selftests: Reorder request allocation vs vma pinning
89921a7696e3 drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
7046de4f256b drm/i915: Allocate a common scratch page
0b963406d978 drm/i915/ringbuffer: Clear semaphore sync registers on ring init

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10936/
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Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

2018-11-28 Thread Ville Syrjälä

On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza wrote:
> As stated in struct drm_encoder, crtc field should only be used
> by non-atomic drivers.
> 
> So here caching the pipe id in intel_psr_enable() what is way more
> simple and efficient than at every call to
> intel_psr_flush()/invalidate() get the
> drm.mode_config.connection_mutex lock to safely be able to get the
> pipe id by reading drm_connector_state.crtc.
> 
> This should fix the null pointer dereference crash below as the
> previous way to get the pipe id was prone to race conditions.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 19 ---
>  2 files changed, 5 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f763b30f98d9..9ea39b82836f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -494,6 +494,7 @@ struct i915_psr {
>   bool sink_support;
>   bool prepared, enabled;
>   struct intel_dp *dp;
> + enum pipe pipe;
>   bool active;
>   struct work_struct work;
>   unsigned busy_frontbuffer_bits;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 572e626eadff..11a520074f06 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -705,6 +705,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>   dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
>   dev_priv->psr.busy_frontbuffer_bits = 0;
>   dev_priv->psr.prepared = true;
> + dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;

A step in the right direction. And would be nice if someone could
eventually move the psr state to be a per-crtc thing rather than
a global thing.

>  
>   if (psr_global_enabled(dev_priv->psr.debug))
>   intel_psr_enable_locked(dev_priv, crtc_state);
> @@ -1012,9 +1013,6 @@ static void intel_psr_work(struct work_struct *work)
>  void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits, enum fb_op_origin origin)
>  {
> - struct drm_crtc *crtc;
> - enum pipe pipe;
> -
>   if (!CAN_PSR(dev_priv))
>   return;
>  
> @@ -1027,10 +1025,7 @@ void intel_psr_invalidate(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>  
> - crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> - pipe = to_intel_crtc(crtc)->pipe;
> -
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
>   dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
>  
>   if (frontbuffer_bits)
> @@ -1055,9 +1050,6 @@ void intel_psr_invalidate(struct drm_i915_private 
> *dev_priv,
>  void intel_psr_flush(struct drm_i915_private *dev_priv,
>unsigned frontbuffer_bits, enum fb_op_origin origin)
>  {
> - struct drm_crtc *crtc;
> - enum pipe pipe;
> -
>   if (!CAN_PSR(dev_priv))
>   return;
>  
> @@ -1070,10 +1062,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>   return;
>   }
>  
> - crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> - pipe = to_intel_crtc(crtc)->pipe;
> -
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
>   dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
>  
>   /* By definition flush = invalidate + flush */
> @@ -1087,7 +1076,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>* but it makes more sense write to the current active
>* pipe.
>*/
> - I915_WRITE(CURSURFLIVE(pipe), 0);
> + I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
>   }
>  
>   if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> -- 
> 2.19.2
> 
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-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

2018-11-28 Thread Daniel Vetter

On Wed, Nov 28, 2018 at 10:21:33PM +0100, Daniel Vetter wrote:
> On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote:
> > On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote:
> > > Currently kernel might allocate different connector ids
> > > for the same outputs in case of DP MST, which seems to
> > > confuse userspace. There are can be different connector
> > > ids in the list, which could be assigned to the same
> > > output, while being in different states.
> > > This results in issues, like external displays staying
> > > blank after quick unplugging and plugging back(bug #106250).
> > > Returning only active DP connectors fixes the issue.
> > > 
> > > v2: Removed caps from the title
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106250
> > > Signed-off-by: Stanislav Lisovskiy 
> > > ---
> > >  drivers/gpu/drm/drm_mode_config.c | 16 +++-
> > >  1 file changed, 11 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_mode_config.c 
> > > b/drivers/gpu/drm/drm_mode_config.c
> > > index ee80788f2c40..ec5b2b08a45e 100644
> > > --- a/drivers/gpu/drm/drm_mode_config.c
> > > +++ b/drivers/gpu/drm/drm_mode_config.c
> > > @@ -143,6 +143,7 @@ int drm_mode_getresources(struct drm_device *dev, 
> > > void *data,
> > >   drm_connector_list_iter_begin(dev, _iter);
> > >   count = 0;
> > >   connector_id = u64_to_user_ptr(card_res->connector_id_ptr);
> > > + DRM_DEBUG_KMS("GetResources: writing connectors start");
> > >   drm_for_each_connector_iter(connector, _iter) {
> > >   /* only expose writeback connectors if userspace understands 
> > > them */
> > >   if (!file_priv->writeback_connectors &&
> > > @@ -150,15 +151,20 @@ int drm_mode_getresources(struct drm_device *dev, 
> > > void *data,
> > >   continue;
> > >  
> > >   if (drm_lease_held(file_priv, connector->base.id)) {
> > > - if (count < card_res->count_connectors &&
> > > - put_user(connector->base.id, connector_id + count)) 
> > > {
> > > - drm_connector_list_iter_end(_iter);
> > > - return -EFAULT;
> > > + if (connector->connector_type != 
> > > DRM_MODE_CONNECTOR_DisplayPort ||
> > > + connector->status != 
> > > connector_status_disconnected) {
> > > + if (count < card_res->count_connectors &&
> > > + put_user(connector->base.id, connector_id + 
> > > count)) {
> > > + drm_connector_list_iter_end(_iter);
> > > + return -EFAULT;
> > > + }
> > > + DRM_DEBUG_KMS("GetResources: connector %s", 
> > > connector->name);
> > > + count++;
> > 
> > I tried to read the bug and I have no idea what's going on here. Userspace
> > is supposed to shut off outputs that are disconnected, whether that's DP,
> > DP MST or something else shouldn't matter. New connectors can come as
> > they see fit. Also not really something special.
> > 
> > Why do we need to dynamically hide an output here? Note that this also
> > affects normal DP ports, which I have no idea is actually what you want to
> > do or not.
> 
> For entertainment and other reasons, testing the below diff would be
> interesting.

Now also with real locking:

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 4de247ddf05f..1b83567aa922 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -494,11 +494,16 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
 static void intel_dp_register_mst_connector(struct drm_connector *connector)
 {
struct drm_i915_private *dev_priv = to_i915(connector->dev);
+   struct drm_mode_config *config = >dev->mode_config;
 
if (dev_priv->fbdev)
drm_fb_helper_add_one_connector(_priv->fbdev->helper,
connector);
 
+   spin_lock_irq(>connector_list_lock);
+   list_move(>head, >connector_list);
+   spin_unlock_irq(>connector_list_lock);
+
drm_connector_register(connector);
 }
 
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

2018-11-28 Thread Daniel Vetter

On Wed, Nov 28, 2018 at 09:51:13PM +0100, Daniel Vetter wrote:
> On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote:
> > Currently kernel might allocate different connector ids
> > for the same outputs in case of DP MST, which seems to
> > confuse userspace. There are can be different connector
> > ids in the list, which could be assigned to the same
> > output, while being in different states.
> > This results in issues, like external displays staying
> > blank after quick unplugging and plugging back(bug #106250).
> > Returning only active DP connectors fixes the issue.
> > 
> > v2: Removed caps from the title
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106250
> > Signed-off-by: Stanislav Lisovskiy 
> > ---
> >  drivers/gpu/drm/drm_mode_config.c | 16 +++-
> >  1 file changed, 11 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_mode_config.c 
> > b/drivers/gpu/drm/drm_mode_config.c
> > index ee80788f2c40..ec5b2b08a45e 100644
> > --- a/drivers/gpu/drm/drm_mode_config.c
> > +++ b/drivers/gpu/drm/drm_mode_config.c
> > @@ -143,6 +143,7 @@ int drm_mode_getresources(struct drm_device *dev, void 
> > *data,
> > drm_connector_list_iter_begin(dev, _iter);
> > count = 0;
> > connector_id = u64_to_user_ptr(card_res->connector_id_ptr);
> > +   DRM_DEBUG_KMS("GetResources: writing connectors start");
> > drm_for_each_connector_iter(connector, _iter) {
> > /* only expose writeback connectors if userspace understands 
> > them */
> > if (!file_priv->writeback_connectors &&
> > @@ -150,15 +151,20 @@ int drm_mode_getresources(struct drm_device *dev, 
> > void *data,
> > continue;
> >  
> > if (drm_lease_held(file_priv, connector->base.id)) {
> > -   if (count < card_res->count_connectors &&
> > -   put_user(connector->base.id, connector_id + count)) 
> > {
> > -   drm_connector_list_iter_end(_iter);
> > -   return -EFAULT;
> > +   if (connector->connector_type != 
> > DRM_MODE_CONNECTOR_DisplayPort ||
> > +   connector->status != 
> > connector_status_disconnected) {
> > +   if (count < card_res->count_connectors &&
> > +   put_user(connector->base.id, connector_id + 
> > count)) {
> > +   drm_connector_list_iter_end(_iter);
> > +   return -EFAULT;
> > +   }
> > +   DRM_DEBUG_KMS("GetResources: connector %s", 
> > connector->name);
> > +   count++;
> 
> I tried to read the bug and I have no idea what's going on here. Userspace
> is supposed to shut off outputs that are disconnected, whether that's DP,
> DP MST or something else shouldn't matter. New connectors can come as
> they see fit. Also not really something special.
> 
> Why do we need to dynamically hide an output here? Note that this also
> affects normal DP ports, which I have no idea is actually what you want to
> do or not.

For entertainment and other reasons, testing the below diff would be
interesting.


diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 4de247ddf05f..e1b66396c83b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -499,6 +499,8 @@ static void intel_dp_register_mst_connector(struct 
drm_connector *connector)
drm_fb_helper_add_one_connector(_priv->fbdev->helper,
connector);
 
+   list_move(>head, 
>dev->mode_config.connector_list);
+
drm_connector_register(connector);
 }
 
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark up early pre-production Kabylakes

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915: Mark up early pre-production Kabylakes
URL   : https://patchwork.freedesktop.org/series/53161/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10929_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10929_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10929_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10929_full:

### IGT changes ###

 Warnings 

  * igt@perf_pmu@rc6:
- shard-kbl:  PASS -> SKIP

  
Known issues


  Here are the changes found in Patchwork_10929_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@gem_render_tiled_blits@basic:
- shard-apl:  PASS -> INCOMPLETE [fdo#103927]

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +4

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl:  NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-glk:  PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk:  PASS -> FAIL [fdo#104873]

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl:  PASS -> FAIL [fdo#102670] / [fdo#106081]

  * igt@kms_flip@flip-vs-expired-vblank:
- shard-kbl:  PASS -> FAIL [fdo#102887] / [fdo#105363]

  * igt@kms_flip_tiling@flip-to-y-tiled:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-apl:  PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-glk:  PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk:  PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +2

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-skl:  PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl:  PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl:  PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- {shard-iclb}:   PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107724]

  * igt@kms_setmode@basic:
- shard-hsw:  PASS -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] +4

  * igt@pm_rpm@dpms-mode-unset-non-lpsp:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#107807]

  * igt@pm_rpm@system-suspend-execbuf:
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]

  * igt@pm_rpm@universal-planes:
- shard-skl:  PASS -> INCOMPLETE [fdo#107807] +2

  
 Possible fixes 

  * igt@drm_import_export@import-close-race-flink:
- shard-skl:  TIMEOUT [fdo#108667] -> PASS

  *

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/5] drm/i915/ringbuffer: Clear semaphore sync 
registers on ring init
URL   : https://patchwork.freedesktop.org/series/53185/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/ringbuffer: Clear semaphore sync registers on ring init
Okay!

Commit: drm/i915: Allocate a common scratch page
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3568:16: warning: expression 
using sizeof(void)

Commit: drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
Okay!

Commit: drm/i915/selftests: Reorder request allocation vs vma pinning
Okay!

Commit: drm/i915: Pipeline PDP updates for Braswell
Okay!

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
URL   : https://patchwork.freedesktop.org/series/53132/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_10934 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10934, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/mbox/

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_10934:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live_sanitycheck:
- fi-apl-guc: PASS -> DMESG-WARN

  * {igt@runner@aborted}:
- fi-apl-guc: NOTRUN -> FAIL

  
Known issues


  Here are the changes found in Patchwork_10934 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-7560u:   PASS -> INCOMPLETE [fdo#108044]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044


Participating hosts (50 -> 44)
--

  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


Build changes
-

* Linux: CI_DRM_5216 -> Patchwork_10934

  CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10934: 2ebde49b2d0906d8106b020a2b0480bc5f552a01 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2ebde49b2d09 drm/i915/psr: Get pipe id following atomic guidelines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10934/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC 
config to intel_crtc_state
URL   : https://patchwork.freedesktop.org/series/53184/
State : failure

== Summary ==

Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Applying: drm/i915/dp: Compute DSC pipe config in atomic check
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_display.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_display.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
error: Failed to merge in the changes.
Patch failed at 0002 drm/i915/dp: Compute DSC pipe config in atomic check
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH v2] Return only active connectors for get_resources ioctl

2018-11-28 Thread Daniel Vetter

On Wed, Nov 28, 2018 at 03:55:58PM +0200, Stanislav Lisovskiy wrote:
> Currently kernel might allocate different connector ids
> for the same outputs in case of DP MST, which seems to
> confuse userspace. There are can be different connector
> ids in the list, which could be assigned to the same
> output, while being in different states.
> This results in issues, like external displays staying
> blank after quick unplugging and plugging back(bug #106250).
> Returning only active DP connectors fixes the issue.
> 
> v2: Removed caps from the title
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106250
> Signed-off-by: Stanislav Lisovskiy 
> ---
>  drivers/gpu/drm/drm_mode_config.c | 16 +++-
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_mode_config.c 
> b/drivers/gpu/drm/drm_mode_config.c
> index ee80788f2c40..ec5b2b08a45e 100644
> --- a/drivers/gpu/drm/drm_mode_config.c
> +++ b/drivers/gpu/drm/drm_mode_config.c
> @@ -143,6 +143,7 @@ int drm_mode_getresources(struct drm_device *dev, void 
> *data,
>   drm_connector_list_iter_begin(dev, _iter);
>   count = 0;
>   connector_id = u64_to_user_ptr(card_res->connector_id_ptr);
> + DRM_DEBUG_KMS("GetResources: writing connectors start");
>   drm_for_each_connector_iter(connector, _iter) {
>   /* only expose writeback connectors if userspace understands 
> them */
>   if (!file_priv->writeback_connectors &&
> @@ -150,15 +151,20 @@ int drm_mode_getresources(struct drm_device *dev, void 
> *data,
>   continue;
>  
>   if (drm_lease_held(file_priv, connector->base.id)) {
> - if (count < card_res->count_connectors &&
> - put_user(connector->base.id, connector_id + count)) 
> {
> - drm_connector_list_iter_end(_iter);
> - return -EFAULT;
> + if (connector->connector_type != 
> DRM_MODE_CONNECTOR_DisplayPort ||
> + connector->status != 
> connector_status_disconnected) {
> + if (count < card_res->count_connectors &&
> + put_user(connector->base.id, connector_id + 
> count)) {
> + drm_connector_list_iter_end(_iter);
> + return -EFAULT;
> + }
> + DRM_DEBUG_KMS("GetResources: connector %s", 
> connector->name);
> + count++;

I tried to read the bug and I have no idea what's going on here. Userspace
is supposed to shut off outputs that are disconnected, whether that's DP,
DP MST or something else shouldn't matter. New connectors can come as
they see fit. Also not really something special.

Why do we need to dynamically hide an output here? Note that this also
affects normal DP ports, which I have no idea is actually what you want to
do or not.
-Daniel

>   }
> - count++;
>   }
>   }
>   card_res->count_connectors = count;
> + DRM_DEBUG_KMS("GetResources: writing connectors end - count %d", count);
>   drm_connector_list_iter_end(_iter);
>  
>   return ret;
> -- 
> 2.17.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [v4 3/3] drm/i915: Attach colorspace property and enable modeset

2018-11-28 Thread kbuild test robot

Hi Uma,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20181128]
[cannot apply to v4.20-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Uma-Shankar/Add-Colorspace-connector-property-interface/20181128-083317
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/intel_hdmi.c:493:51: warning: mixing different enum 
>> types
   drivers/gpu/drm/i915/intel_hdmi.c:493:51: unsigned int enum 
absolute_colorimetry_list  versus
   drivers/gpu/drm/i915/intel_hdmi.c:493:51: unsigned int enum 
hdmi_colorimetry 
   include/linux/slab.h:332:43: warning: dubious: x & !y
   include/linux/slab.h:332:43: warning: dubious: x & !y

vim +493 drivers/gpu/drm/i915/intel_hdmi.c

   460  
   461  static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
   462   const struct intel_crtc_state 
*crtc_state,
   463   const struct 
drm_connector_state *conn_state)
   464  {
   465  struct intel_hdmi *intel_hdmi = 
enc_to_intel_hdmi(>base);
   466  const struct drm_display_mode *adjusted_mode =
   467  _state->base.adjusted_mode;
   468  struct drm_connector *connector = 
_hdmi->attached_connector->base;
   469  bool is_hdmi2_sink = 
connector->display_info.hdmi.scdc.supported ||
   470 connector->display_info.color_formats & 
DRM_COLOR_FORMAT_YCRCB420;
   471  union hdmi_infoframe frame;
   472  int ret;
   473  
   474  ret = drm_hdmi_avi_infoframe_from_display_mode(,
   475 adjusted_mode,
   476 is_hdmi2_sink);
   477  if (ret < 0) {
   478  DRM_ERROR("couldn't fill AVI infoframe\n");
   479  return;
   480  }
   481  
   482  if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
   483  frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
   484  else if (crtc_state->output_format == 
INTEL_OUTPUT_FORMAT_YCBCR444)
   485  frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
   486  else
   487  frame.avi.colorspace = HDMI_COLORSPACE_RGB;
   488  
   489  if (conn_state->colorspace == COLORIMETRY_DEFAULT) {
   490  /* Set ITU 709 as default for HDMI */
   491  frame.avi.colorimetry = COLORIMETRY_ITU_709;
   492  } else if (conn_state->colorspace < COLORIMETRY_XV_YCC_601) {
 > 493  frame.avi.colorimetry = conn_state->colorspace;
   494  } else {
   495  frame.avi.colorimetry = HDMI_COLORIMETRY_EXTENDED;
   496  /*
   497   * Starting from extended list where 
COLORIMETRY_XV_YCC_601
   498   * is the first extended mode and its value is 0 as per 
HDMI
   499   * specification.
   500   */
   501  frame.avi.extended_colorimetry = conn_state->colorspace 
-
   502  
COLORIMETRY_XV_YCC_601;
   503  }
   504  
   505  drm_hdmi_avi_infoframe_quant_range(, adjusted_mode,
   506 
crtc_state->limited_color_range ?
   507 
HDMI_QUANTIZATION_RANGE_LIMITED :
   508 HDMI_QUANTIZATION_RANGE_FULL,
   509 
intel_hdmi->rgb_quant_range_selectable,
   510 is_hdmi2_sink);
   511  
   512  drm_hdmi_avi_infoframe_content_type(,
   513  conn_state);
   514  
   515  /* TODO: handle pixel repetition for YCBCR420 outputs */
   516  intel_write_infoframe(encoder, crtc_state,
   517);
   518  }
   519  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
URL   : https://patchwork.freedesktop.org/series/53132/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Get pipe id following atomic guidelines
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression 
using sizeof(void)

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Re: [Intel-gfx] [PATCH 4/4] drm/edid: Add display_info.rgb_quant_range_selectable

2018-11-28 Thread Alex Deucher

On Wed, Nov 28, 2018 at 12:19 PM Eric Anholt  wrote:
>
> Ville Syrjala  writes:
>
> > From: Ville Syrjälä 
> >
> > Move the CEA-861 QS bit handling entirely into the edid code. No
> > need to bother the drivers with this.
> >
> > Cc: Alex Deucher 
> > Cc: "Christian König" 
> > Cc: "David (ChunMing) Zhou" 
> > Cc: amd-...@lists.freedesktop.org
> > Cc: Eric Anholt  (supporter:DRM DRIVERS FOR VC4)
> > Signed-off-by: Ville Syrjälä 
>
> For vc4,
> Acked-by: Eric Anholt 
>
> Looks like a nice cleanup!

for radeon:
Acked-by: Alex Deucher 
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Re: [Intel-gfx] [PULL] drm-misc-fixes

2018-11-28 Thread Sean Paul

On Wed, Nov 28, 2018 at 3:04 PM Sean Paul  wrote:
>
>
> Hi Dave,
> Happy meson week! A bunch of stellar fixes coming in this week from Lyude, 
> and a
> couple others plugging holes in meson and core.
>
>
> drm-misc-fixes-2018-11-28:
> - mst: Don't try to validate ports while destroying them (Lyude)

ICYMIRC, Lyude noticed a new issue with this patch, so we're going to
revert and re-send.

Please drop for now,

Sean

> - core: Don't set device to master unless set_master succeeds (Sergio)
> - meson: Do vblank_on/off on enable/disable (Neil)
> - meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
> - meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)
>
> Cc: Lyude Paul 
> Cc: Sergio Correia 
> Cc: Neil Armstrong 
>
> Cheers, Sean
>
>
> The following changes since commit 2e6e902d185027f8e3cb8b7305238f7e35d6a436:
>
>   Linux 4.20-rc4 (2018-11-25 14:19:31 -0800)
>
> are available in the Git repository at:
>
>   git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2018-11-28
>
> for you to fetch changes up to 31e1ab494559fb46de304cc6c2aed1528f94b298:
>
>   drm/meson: add support for 1080p25 mode (2018-11-26 16:14:28 -0500)
>
> 
> - mst: Don't try to validate ports while destroying them (Lyude)
> - core: Don't set device to master unless set_master succeeds (Sergio)
> - meson: Do vblank_on/off on enable/disable (Neil)
> - meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
> - meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)
>
> Cc: Lyude Paul 
> Cc: Sergio Correia 
> Cc: Neil Armstrong 
>
> 
> Christian Hewitt (1):
>   drm/meson: add support for 1080p25 mode
>
> Lyude Paul (3):
>   drm/dp_mst: Skip validating ports during destruction, just ref
>   drm/meson: Enable fast_io in meson_dw_hdmi_regmap_config
>   drm/meson: Fix OOB memory accesses in meson_viu_set_osd_lut()
>
> Neil Armstrong (1):
>   drm/meson: Fixes for drm_crtc_vblank_on/off support
>
> Sergio Correia (1):
>   drm: set is_master to 0 upon drm_new_set_master() failure
>
>  drivers/gpu/drm/drm_auth.c|  2 ++
>  drivers/gpu/drm/drm_dp_mst_topology.c | 15 +--
>  drivers/gpu/drm/meson/meson_crtc.c| 27 +--
>  drivers/gpu/drm/meson/meson_dw_hdmi.c |  1 +
>  drivers/gpu/drm/meson/meson_venc.c|  4 
>  drivers/gpu/drm/meson/meson_viu.c | 12 ++--
>  6 files changed, 51 insertions(+), 10 deletions(-)
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH 4/5] drm/i915/selftests: Reorder request allocation vs vma pinning

2018-11-28 Thread Chris Wilson

Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  31 +++--
 .../gpu/drm/i915/selftests/intel_hangcheck.c  | 123 +-
 drivers/gpu/drm/i915/selftests/intel_lrc.c|  86 ++--
 3 files changed, 119 insertions(+), 121 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..a0c7cbc212ba 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -972,7 +972,6 @@ static int gpu_write(struct i915_vma *vma,
 {
struct i915_request *rq;
struct i915_vma *batch;
-   int flags = 0;
int err;
 
GEM_BUG_ON(!intel_engine_can_store_dword(engine));
@@ -981,14 +980,14 @@ static int gpu_write(struct i915_vma *vma,
if (err)
return err;
 
-   rq = i915_request_alloc(engine, ctx);
-   if (IS_ERR(rq))
-   return PTR_ERR(rq);
-
batch = gpu_write_dw(vma, dword * sizeof(u32), value);
-   if (IS_ERR(batch)) {
-   err = PTR_ERR(batch);
-   goto err_request;
+   if (IS_ERR(batch))
+   return PTR_ERR(batch);
+
+   rq = i915_request_alloc(engine, ctx);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   goto err_batch;
}
 
err = i915_vma_move_to_active(batch, rq, 0);
@@ -996,21 +995,21 @@ static int gpu_write(struct i915_vma *vma,
goto err_request;
 
i915_gem_object_set_active_reference(batch->obj);
-   i915_vma_unpin(batch);
-   i915_vma_close(batch);
 
-   err = engine->emit_bb_start(rq,
-   batch->node.start, batch->node.size,
-   flags);
+   err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
if (err)
goto err_request;
 
-   err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+   err = engine->emit_bb_start(rq,
+   batch->node.start, batch->node.size,
+   0);
+err_request:
if (err)
i915_request_skip(rq, err);
-
-err_request:
i915_request_add(rq);
+err_batch:
+   i915_vma_unpin(batch);
+   i915_vma_close(batch);
 
return err;
 }
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index a48fbe2557ea..b767fab9ce1f 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -102,52 +102,87 @@ static u64 hws_address(const struct i915_vma *hws,
return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
 }
 
-static int emit_recurse_batch(struct hang *h,
- struct i915_request *rq)
+static int move_to_active(struct i915_vma *vma,
+ struct i915_request *rq,
+ unsigned int flags)
+{
+   int err;
+
+   err = i915_vma_move_to_active(vma, rq, 0);
+   if (err)
+   return err;
+
+   if (!i915_gem_object_has_active_reference(vma->obj)) {
+   i915_gem_object_get(vma->obj);
+   i915_gem_object_set_active_reference(vma->obj);
+   }
+
+   return 0;
+}
+
+static struct i915_request *
+hang_create_request(struct hang *h, struct intel_engine_cs *engine)
 {
struct drm_i915_private *i915 = h->i915;
struct i915_address_space *vm =
-   rq->gem_context->ppgtt ?
-   >gem_context->ppgtt->vm :
-   >ggtt.vm;
+   h->ctx->ppgtt ? >ctx->ppgtt->vm : >ggtt.vm;
+   struct i915_request *rq = NULL;
struct i915_vma *hws, *vma;
unsigned int flags;
u32 *batch;
int err;
 
+   if (i915_gem_object_is_active(h->obj)) {
+   struct drm_i915_gem_object *obj;
+   void *vaddr;
+
+   obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
+   if (IS_ERR(obj))
+   return ERR_CAST(obj);
+
+   vaddr = i915_gem_object_pin_map(obj,
+   
i915_coherent_map_type(h->i915));
+   if (IS_ERR(vaddr)) {
+   i915_gem_object_put(obj);
+   return ERR_CAST(vaddr);
+   }
+
+   i915_gem_object_unpin_map(h->obj);
+   i915_gem_object_put(h->obj);
+
+   h->obj = obj;
+   h->batch = vaddr;
+   }
+
vma = i915_vma_instance(h->obj, vm, NULL);
if (IS_ERR(vma))
-   return PTR_ERR(vma);
+   return ERR_CAST(vma);
 
hws = i915_vma_instance(h->hws,

[Intel-gfx] [PATCH 5/5] drm/i915: Pipeline PDP updates for Braswell

2018-11-28 Thread Chris Wilson

Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as it is unserialised with any access (read or write)
the GPU is doing. By asserting that Braswell is not used with vGPU
(currently an unsupported platform) we can eliminate the dangerous
direct write into the context image and solely use the pipelined update.

However, the LRI of the PDP fouls up the GPU, causing it to freeze and
take out the machine with "forcewake ack timeouts". This seems possible
to workaround by preventing the GPU from sleeping (via means of
disabling the power-state management interface, i.e. forcing each ring
to remain awake) around the update.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656
References: https://bugs.freedesktop.org/show_bug.cgi?id=108714
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 143 ---
 1 file changed, 76 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c60a1c2233e0..071022acbb4d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -363,31 +363,12 @@ execlists_context_schedule_out(struct i915_request *rq, 
unsigned long status)
trace_i915_request_out(rq);
 }
 
-static void
-execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
-{
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
-}
-
 static u64 execlists_update_context(struct i915_request *rq)
 {
-   struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
struct intel_context *ce = rq->hw_context;
-   u32 *reg_state = ce->lrc_reg_state;
-
-   reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
 
-   /*
-* True 32b PPGTT with dynamic page allocation: update PDP
-* registers and point the unallocated PDPs to scratch page.
-* PML4 is allocated during ppgtt init, so this is not needed
-* in 48-bit mode.
-*/
-   if (!i915_vm_is_48bit(>vm))
-   execlists_update_context_pdps(ppgtt, reg_state);
+   ce->lrc_reg_state[CTX_RING_TAIL + 1] =
+   intel_ring_set_tail(rq->ring, rq->tail);
 
/*
 * Make sure the context image is complete before we submit it to HW.
@@ -1233,6 +1214,64 @@ execlists_context_pin(struct intel_engine_cs *engine,
return __execlists_context_pin(engine, ctx, ce);
 }
 
+static int emit_pdps(struct i915_request *rq)
+{
+   const struct intel_engine_cs * const engine = rq->engine;
+   struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt;
+   const unsigned int num_rings = INTEL_INFO(rq->i915)->num_rings;
+   struct intel_engine_cs *other;
+   enum intel_engine_id id;
+   u32 *cs;
+   int i;
+
+   if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine)))
+   return 0;
+
+   cs = intel_ring_begin(rq, 4 * (GEN8_3LVL_PDPES + num_rings) + 8);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   /*
+* Force the GPU (not just the local engine/powerwell!) to remain awake,
+* or else we may kill the machine with "timed out waiting for
+* forcewake ack request".
+*/
+
+   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
+   for_each_engine(other, rq->i915, id) {
+   *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base));
+   *cs++ = _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
+   }
+
+   *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
+   for (i = GEN8_3LVL_PDPES; i--; ) {
+   const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
+
+   *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
+   *cs++ = upper_32_bits(pd_daddr);
+   *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
+   *cs++ = lower_32_bits(pd_daddr);
+   }
+   *cs++ = MI_NOOP;
+
+   /* Posting read to flush the mmio before letting the GPU sleep again */
+   *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
+   *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0));
+   *cs++ = i915_ggtt_offset(engine->i915->gt.scratch);
+   *cs++ = 0;
+
+   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
+   for_each_engine(other, rq->i915, id) {
+   *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base));
+   *cs++ = _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
+   }
+
+   intel_ring_advance(rq, cs);
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   return 0;

[Intel-gfx] [PATCH 1/5] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

2018-11-28 Thread Chris Wilson

Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e18a64d41843..82c844488755 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
 
intel_engine_reset_breadcrumbs(engine);
 
+   if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+   I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+   I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+   if (HAS_VEBOX(dev_priv))
+   I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+   }
+
/* Enforce ordering by reading HEAD register back */
I915_READ_HEAD(engine);
 
-- 
2.20.0.rc1

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[Intel-gfx] [PATCH 2/5] drm/i915: Allocate a common scratch page

2018-11-28 Thread Chris Wilson

Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications by not assuming per-engine isolation.

For later use, it simplifies engine initialisation (by removing the
allocation that required struct_mutex!) and means that we can always rely
on there being a scratch page.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h |  7 
 drivers/gpu/drm/i915/i915_gem.c | 50 -
 drivers/gpu/drm/i915/i915_gpu_error.c   |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c  | 42 -
 drivers/gpu/drm/i915/intel_lrc.c| 17 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 33 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 ---
 7 files changed, 71 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 645c2bbdcdfa..b1203a0eaa5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1994,6 +1994,8 @@ struct drm_i915_private {
struct delayed_work idle_work;
 
ktime_t last_init_time;
+
+   struct i915_vma *scratch;
} gt;
 
/* perform PHY state sanity checks? */
@@ -3719,4 +3721,9 @@ static inline int intel_hws_csb_write_index(struct 
drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
 }
 
+static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
+{
+   return i915_ggtt_offset(i915->gt.scratch);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..417c265fd93c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5529,6 +5529,44 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
 }
 
+static int
+i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
+{
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *vma;
+   int ret;
+
+   obj = i915_gem_object_create_stolen(i915, size);
+   if (!obj)
+   obj = i915_gem_object_create_internal(i915, size);
+   if (IS_ERR(obj)) {
+   DRM_ERROR("Failed to allocate scratch page\n");
+   return PTR_ERR(obj);
+   }
+
+   vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+   if (IS_ERR(vma)) {
+   ret = PTR_ERR(vma);
+   goto err_unref;
+   }
+
+   ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+   if (ret)
+   goto err_unref;
+
+   i915->gt.scratch = vma;
+   return 0;
+
+err_unref:
+   i915_gem_object_put(obj);
+   return ret;
+}
+
+static void i915_gem_fini_scratch(struct drm_i915_private *i915)
+{
+   i915_vma_unpin_and_release(>gt.scratch, 0);
+}
+
 int i915_gem_init(struct drm_i915_private *dev_priv)
 {
int ret;
@@ -5575,12 +5613,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_unlock;
}
 
-   ret = i915_gem_contexts_init(dev_priv);
+   ret = i915_gem_init_scratch(dev_priv,
+   IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE);
if (ret) {
GEM_BUG_ON(ret == -EIO);
goto err_ggtt;
}
 
+   ret = i915_gem_contexts_init(dev_priv);
+   if (ret) {
+   GEM_BUG_ON(ret == -EIO);
+   goto err_scratch;
+   }
+
ret = intel_engines_init(dev_priv);
if (ret) {
GEM_BUG_ON(ret == -EIO);
@@ -5653,6 +5698,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 err_context:
if (ret != -EIO)
i915_gem_contexts_fini(dev_priv);
+err_scratch:
+   i915_gem_fini_scratch(dev_priv);
 err_ggtt:
 err_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -5704,6 +5751,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
+   i915_gem_fini_scratch(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
 
intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index a6885a59568b..07465123c166 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1571,7 +1571,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
if (HAS_BROKEN_CS_TLB(i915))
ee->wa_batchbuffer =
i915_error_object_create(i915,
-
engine->scratch);
+

[Intel-gfx] [PATCH 3/5] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly

2018-11-28 Thread Chris Wilson

If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index defe671130ab..a48fbe2557ea 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -308,6 +308,7 @@ static int igt_hang_sanitycheck(void *arg)
goto unlock;
 
for_each_engine(engine, i915, id) {
+   struct igt_wedge_me w;
long timeout;
 
if (!intel_engine_can_store_dword(engine))
@@ -328,9 +329,14 @@ static int igt_hang_sanitycheck(void *arg)
 
i915_request_add(rq);
 
-   timeout = i915_request_wait(rq,
-   I915_WAIT_LOCKED,
-   MAX_SCHEDULE_TIMEOUT);
+   timeout = 0;
+   igt_wedge_on_timeout(, i915, HZ / 10 /* 100ms timeout*/)
+   timeout = i915_request_wait(rq,
+   I915_WAIT_LOCKED,
+   MAX_SCHEDULE_TIMEOUT);
+   if (i915_terminally_wedged(>gpu_error))
+   timeout = -EIO;
+
i915_request_put(rq);
 
if (timeout < 0) {
-- 
2.20.0.rc1

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[Intel-gfx] ✓ Fi.CI.IGT: success for Return only active connectors for GET_RESOURCES

2018-11-28 Thread Patchwork

== Series Details ==

Series: Return only active connectors for GET_RESOURCES
URL   : https://patchwork.freedesktop.org/series/53159/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10928_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10928_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10928_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10928_full:

### IGT changes ###

 Warnings 

  * igt@kms_lease@lease_unleased_connector:
- shard-apl:  PASS -> SKIP

  
Known issues


  Here are the changes found in Patchwork_10928_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries_display_off:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#104108]

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@gem_linear_blits@interruptible:
- shard-glk:  PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#106887]

  * igt@gem_softpin@noreloc-s3:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1

  * igt@i915_suspend@shrink:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#108784]

  * igt@i915_suspend@sysfs-reader:
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713] +1

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] +4

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_color@pipe-b-legacy-gamma:
- shard-apl:  PASS -> FAIL [fdo#104782]

  * igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-glk:  PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] +2

  * igt@kms_cursor_crc@cursor-256x256-offscreen:
- shard-skl:  PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-glk:  PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl:  PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw:  PASS -> FAIL [fdo#105767]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl:  PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-glk:  PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] / 
[fdo#107773]

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-skl:  PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl:  PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl:  PASS -> FAIL [fdo#103166] +1
- {shard-iclb}:   PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk:  PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-skl:  NOTRUN -> FAIL [fdo#103166] / [fdo#107815]

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- {shard-iclb}:   NOTRUN ->

[Intel-gfx] [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits.

2018-11-28 Thread Manasi Navare

From: Anusha Srivatsa 

If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.

The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.

v2:
- Change commit message. Configure fec state after
  link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)

v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)

v4: rebased.

v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.

v6: Pass intel_encoder, instead of intel_dp. (Ville)

v7: Remove unwanted comments (Manasi)

Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Manasi Navare 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Manasi Navare 
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 23 +++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eadd880b0ef6..d3ef97915455 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9198,6 +9198,7 @@ enum skl_power_gate {
 #define _DP_TP_CTL_B   0x64140
 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
 #define  DP_TP_CTL_ENABLE  (1 << 31)
+#define  DP_TP_CTL_FEC_ENABLE  (1 << 30)
 #define  DP_TP_CTL_MODE_SST(0 << 27)
 #define  DP_TP_CTL_MODE_MST(1 << 27)
 #define  DP_TP_CTL_FORCE_ACT   (1 << 25)
@@ -9216,6 +9217,7 @@ enum skl_power_gate {
 #define _DP_TP_STATUS_A0x64044
 #define _DP_TP_STATUS_B0x64144
 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define  DP_TP_STATUS_FEC_ENABLE_LIVE  (1 << 28)
 #define  DP_TP_STATUS_IDLE_DONE(1 << 25)
 #define  DP_TP_STATUS_ACT_SENT (1 << 24)
 #define  DP_TP_STATUS_MODE_STATUS_MST  (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4c74bbe1cf73..12acdb08a750 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp 
*intel_dp,
DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
 }
 
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   u32 val;
+
+   if (!crtc_state->fec_enable)
+   return;
+
+   val = I915_READ(DP_TP_CTL(port));
+   val |= DP_TP_CTL_FEC_ENABLE;
+   I915_WRITE(DP_TP_CTL(port), val);
+
+   if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+   DP_TP_STATUS_FEC_ENABLE_LIVE,
+   DP_TP_STATUS_FEC_ENABLE_LIVE,
+   1))
+   DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state 
*conn_state)
@@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
 
+   intel_ddi_enable_fec(encoder, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
 
if (!is_mst)
-- 
2.19.1

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[Intel-gfx] [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION

2018-11-28 Thread Manasi Navare

From: Anusha Srivatsa 

If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.

This has to happen before link training.

v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
   - change commit message. (Gaurav)

v3: rebased. (r-b Manasi)

v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)

v5: Move to intel_ddi.c
- Make the function static (Anusha)

v6: Dont pass state as a separate argument (Ville)

v7: (From Manasi)
* Correct the debug print (Ville)

Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Manasi Navare 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_ddi.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6533624226a7..4c74bbe1cf73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct 
intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
 }
 
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+   const struct intel_crtc_state 
*crtc_state)
+{
+   if (!crtc_state->fec_enable)
+   return;
+
+   if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION, 
DP_FEC_READY) <= 0)
+   DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state 
*conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
  true);
+   intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
-- 
2.19.1

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[Intel-gfx] [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits

2018-11-28 Thread Manasi Navare

1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg

v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Signed-off-by: Gaurav K Singh 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_vdsc.c| 31 
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9dc8731907af..5fe5d8f2d061 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3345,6 +3345,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private 
*dev_priv,
  bool enable);
 void intel_dsc_enable(struct intel_encoder *encoder,
  const struct intel_crtc_state *crtc_state);
+void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 69bb0b75a806..7a221fb9ca66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5889,6 +5889,8 @@ static void haswell_crtc_disable(struct intel_crtc_state 
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
 
+   intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index 38f391329b8c..f1892f690220 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1027,3 +1027,34 @@ void intel_dsc_enable(struct intel_encoder *encoder,
I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 }
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe;
+   i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+   u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+   if (!old_crtc_state->dsc_params.compression_enable)
+   return;
+
+   if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+   dss_ctl1_reg = DSS_CTL1;
+   dss_ctl2_reg = DSS_CTL2;
+   } else {
+   dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+   dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+   }
+   dss_ctl1_val = I915_READ(dss_ctl1_reg);
+   if (dss_ctl1_val & JOINER_ENABLE)
+   dss_ctl1_val &= ~JOINER_ENABLE;
+   I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+   dss_ctl2_val = I915_READ(dss_ctl2_reg);
+   if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+   dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+   dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+   I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+}
-- 
2.19.1

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[Intel-gfx] [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

2018-11-28 Thread Manasi Navare

A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.

v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)

Suggested-by: Ville Syrjala 
Cc: Ville Syrjala 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Manasi Navare 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c  |  6 ++
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_vdsc.c | 26 ++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 339be10986d7..6533624226a7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct 
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
 
+   /*
+* VDSC power is needed when DSC is enabled
+*/
+   if (crtc_state->dsc_params.compression_enable)
+   domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa452fbb16c6..b5693cac26d7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1858,6 +1858,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp 
*intel_dp, int mode_clock,
 /* intel_vdsc.c */
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index f1892f690220..0696deaf75cb 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
 }
 
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+   /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+   if (cpu_transcoder == TRANSCODER_EDP)
+   return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+   else
+   return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state 
*crtc_state)
 {
@@ -1008,6 +1026,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
 
+   /* Enable Power wells for VDSC/joining */
+   intel_display_power_get(dev_priv,
+   intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1057,4 +1079,8 @@ void intel_dsc_disable(const struct intel_crtc_state 
*old_crtc_state)
dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
  RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+   /* Disable Power wells for VDSC/joining */
+   intel_display_power_put(dev_priv,
+   intel_dsc_power_domain(old_crtc_state));
 }
-- 
2.19.1

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[Intel-gfx] [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params

2018-11-28 Thread Manasi Navare

From: Gaurav K Singh 

This patches does the following:

1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific

This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.

v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks

v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)

v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)

Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Cc: Gaurav K Singh 
Signed-off-by: Gaurav K Singh 
Signed-off-by: Manasi Navare 
Co-developed-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/Makefile |   3 +-
 drivers/gpu/drm/i915/intel_dp.c   |   7 +
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_vdsc.c | 456 ++
 include/drm/drm_dp_helper.h   |   3 +
 5 files changed, 472 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..8370b9de6e4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -157,7 +157,8 @@ i915-y += dvo_ch7017.o \
  intel_sdvo.o \
  intel_tv.o \
  vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
 
 # Post-mortem debug and GPU hang state capture
 i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2780733768a..3b612eb134e7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1953,6 +1953,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
return false;
}
}
+   if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+   DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input 
Bpp = %d "
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+   return false;
+   }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
  "Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 270212fa43a0..316ec1e107bf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1852,6 +1852,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, 
uint8_t lane_count,
 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
 int mode_hdisplay);
 
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+   struct intel_crtc_state *pipe_config);
+
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..4ce6f0c453bb
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh 
+ * Manasi Navare 
+ */
+
+#include 
+#include 
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+   ROW_INDEX_6BPP = 0,
+   ROW_INDEX_8BPP,
+   ROW_INDEX_10BPP,
+   ROW_INDEX_12BPP,
+   ROW_INDEX_15BPP,
+   MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+   COLUMN_INDEX_8BPC = 0,
+   COLUMN_INDEX_10BPC,
+   COLUMN_INDEX_12BPC,
+   COLUMN_INDEX_14BPC,
+   COLUMN_INDEX_16BPC,
+

[Intel-gfx] [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI

2018-11-28 Thread Manasi Navare

On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.

v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)

v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)

Cc: Ville Syrjala 
Cc: Rodrigo Vivi 
Cc: Imre Deak 
Signed-off-by: Manasi Navare 
Reviewed-by: Ville Syrjala 
---
 drivers/gpu/drm/i915/intel_display.h| 1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index 5e253f741d29..b41b06dc8347 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -242,6 +242,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+   POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1c2de9b69a19..4350a5270423 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+   case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+   return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2028,9 +2030,9 @@ void intel_display_power_put(struct drm_i915_private 
*dev_priv,
 */
 #define ICL_PW_2_POWER_DOMAINS (   \
ICL_PW_3_POWER_DOMAINS |\
+   BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
 * - KVMR (HW control)
 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
-- 
2.19.1

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[Intel-gfx] [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

2018-11-28 Thread Manasi Navare

Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.

v2:
* Rebase on drm-tip (Manasi)

Cc: Gaurav K Singh 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_drv.h | 9 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..183aae996305 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "i915_fixed.h"
 #include "i915_params.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a62d77b76291..270212fa43a0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -937,6 +937,15 @@ struct intel_crtc_state {
 
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+   /* Display Stream compression state */
+   struct {
+   bool compression_enable;
+   bool dsc_split;
+   u16 compressed_bpp;
+   u8 slice_count;
+   } dsc_params;
+   struct drm_dsc_config dp_dsc_cfg;
 };
 
 struct intel_crtc {
-- 
2.19.1

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[Intel-gfx] [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink

2018-11-28 Thread Manasi Navare

From: Gaurav K Singh 

This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.

v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Cc: Gaurav K Singh 
Signed-off-by: Gaurav K Singh 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_ddi.c |  5 +
 drivers/gpu/drm/i915/intel_dp.c  | 16 
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 3 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad11540ac436..fa5ad62cd0db 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3491,6 +3493,9 @@ static void intel_disable_ddi_dp(struct intel_encoder 
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+   /* Disable the decompression in DP Sink */
+   intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3b612eb134e7..4e65dd1a6c07 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2857,6 +2857,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp 
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
 }
 
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+  const struct intel_crtc_state 
*crtc_state,
+  bool enable)
+{
+   int ret;
+
+   if (!crtc_state->dsc_params.compression_enable)
+   return;
+
+   ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+   if (ret < 0)
+   DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
 /* If the sink supports it, try to set the power state appropriately */
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 316ec1e107bf..fa452fbb16c6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1797,6 +1797,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
  struct drm_modeset_acquire_ctx *ctx);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+  const struct intel_crtc_state 
*crtc_state,
+  bool enable);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
-- 
2.19.1

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[Intel-gfx] [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC

2018-11-28 Thread Manasi Navare

From: Gaurav K Singh 

This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.

v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)

v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip

v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)

Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations

v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter

Cc: Manasi Navare 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Signed-off-by: Gaurav K Singh 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_vdsc.c | 125 +-
 1 file changed, 124 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index 4ce6f0c453bb..39baff618ed8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -318,6 +318,129 @@ static int get_column_index_for_rc_params(u8 
bits_per_component)
}
 }
 
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+   unsigned long groups_per_line = 0;
+   unsigned long groups_total = 0;
+   unsigned long num_extra_mux_bits = 0;
+   unsigned long slice_bits = 0;
+   unsigned long hrd_delay = 0;
+   unsigned long final_scale = 0;
+   unsigned long rbs_min = 0;
+
+   /* Number of groups used to code each line of a slice */
+   groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+  DSC_RC_PIXELS_PER_GROUP);
+
+   /* chunksize in Bytes */
+   vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+   if (vdsc_cfg->convert_rgb)
+   num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+   else
+   num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+   (4 * vdsc_cfg->bits_per_component + 4) +
+   2 * (4 * vdsc_cfg->bits_per_component) - 2;
+   /* Number of bits in one Slice */
+   slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+   while ((num_extra_mux_bits > 0) &&
+  ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+   num_extra_mux_bits--;
+
+   if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+   vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+   /* scale_decrement_interval calculation according to DSC spec 1.11 */
+   if (vdsc_cfg->initial_scale_value > 8)
+   vdsc_cfg->scale_decrement_interval = groups_per_line /
+   (vdsc_cfg->initial_scale_value - 8);
+   else
+   vdsc_cfg->scale_decrement_interval = 
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+   vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+   (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+   if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+   DRM_DEBUG_KMS("FinalOfs < RcModelSze for this 
InitialXmitDelay\n");
+   return -ERANGE;
+   }
+
+   final_scale = (vdsc_cfg->rc_model_size * 8) /
+   (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+   if (vdsc_cfg->slice_height > 1)
+   /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+   vdsc_cfg->nfl_bpg_offset = 
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+   (vdsc_cfg->slice_height 
- 1));
+   else
+   vdsc_cfg->nfl_bpg_offset = 0;
+
+   /* 2^16 - 1 */
+   if (vdsc_cfg->nfl_bpg_offset > 65535) {
+   DRM_DEBUG_KMS("NflBpgOffset is too large for this slice 
height\n");
+   return -ERANGE;
+   }
+
+   /* Number of groups used to code the entire slice */
+   groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+   /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+   vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+

[Intel-gfx] [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable

2018-11-28 Thread Manasi Navare

Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.

v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_vdsc.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index 56290093d43f..38f391329b8c 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -998,10 +998,32 @@ static void intel_dp_write_dsc_pps_sdp(struct 
intel_encoder *encoder,
 void intel_dsc_enable(struct intel_encoder *encoder,
  const struct intel_crtc_state *crtc_state)
 {
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum pipe pipe = crtc->pipe;
+   i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+   u32 dss_ctl1_val = 0;
+   u32 dss_ctl2_val = 0;
+
if (!crtc_state->dsc_params.compression_enable)
return;
 
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
+   if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+   dss_ctl1_reg = DSS_CTL1;
+   dss_ctl2_reg = DSS_CTL2;
+   } else {
+   dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+   dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+   }
+   dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+   if (crtc_state->dsc_params.dsc_split) {
+   dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+   dss_ctl1_val |= JOINER_ENABLE;
+   }
+   I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+   I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 }
-- 
2.19.1

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[Intel-gfx] [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs

2018-11-28 Thread Manasi Navare

Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.

v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_reg.h   |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..eadd880b0ef6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4570,6 +4570,7 @@ enum {
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE  32
 #define   VIDEO_DIP_VSC_DATA_SIZE  36
+#define   VIDEO_DIP_PPS_DATA_SIZE  132
 #define VIDEO_DIP_CTL  _MMIO(0x61170)
 /* Pre HSW: */
 #define   VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index e2c6a2b3e8f2..07e803a604bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+   case DP_SDP_PPS:
+   return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+   case DP_SDP_PPS:
+   return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
 }
 
+static int hsw_dip_data_size(unsigned int type)
+{
+   switch (type) {
+   case DP_SDP_VSC:
+   return VIDEO_DIP_VSC_DATA_SIZE;
+   case DP_SDP_PPS:
+   return VIDEO_DIP_PPS_DATA_SIZE;
+   default:
+   return VIDEO_DIP_DATA_SIZE;
+   }
+}
+
 static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
-   int data_size = type == DP_SDP_VSC ?
-   VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+   int data_size;
int i;
u32 val = I915_READ(ctl_reg);
 
+   data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
 
-- 
2.19.1

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[Intel-gfx] [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state.

2018-11-28 Thread Manasi Navare

From: Anusha Srivatsa 

For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.

Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.

v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)

- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)

v3: Check for FEC support along with setting crtc state.

v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)

v5: Move fec check to intel_dp_supports_dsc(Ville)

v6: Remove warning. rebase.

v7: change crtc state to include DP sink and fec capability
of source.(Manasi)

v8: Set fec_enable in crtc in intel_dp_compute_config().

v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly

v10 (From Manasi):
* Rebase

Suggested-by: Ville Syrjala 
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Manasi Navare 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_dp.c  | 28 +++-
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4e65dd1a6c07..38a6e82153fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =

drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
-   } else {
+   } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -1710,14 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
 };
 
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 const struct intel_crtc_state 
*pipe_config)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-   /* FIXME: FEC needed for external DP until then reject DSC on DP */
-   if (!intel_dp_is_edp(intel_dp))
-   return false;
+   return INTEL_GEN(dev_priv) >= 11 &&
+   pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+   return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+   drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state 
*pipe_config)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
return INTEL_GEN(dev_priv) >= 10 &&
pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1738,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp 
*intel_dp,
 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
  const struct intel_crtc_state *pipe_config)
 {
+   if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+   return false;
+
return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 }
@@ -2129,6 +2144,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
 
+   pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
return false;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b5693cac26d7..8c582d53c00a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+   /* Forward Error correction State */
+   bool fec_enable;
 };
 
 struct intel_crtc {
-- 
2.19.1

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[Intel-gfx] [CI v13 17/17] drm/i915/fec: Disable FEC state.

2018-11-28 Thread Manasi Navare

From: Anusha Srivatsa 

Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.

v2:
- rebased.
- Add additional check for compression state. (Gaurav)

v3: rebased.

v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)

v5: Remove unnecessary checks (Ville)

v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)

Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Manasi Navare 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_ddi.c | 28 
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 12acdb08a750..61d7145f93bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder 
*encoder,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
 }
 
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+   const struct intel_crtc_state 
*crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   u32 val;
+
+   if (!crtc_state->fec_enable)
+   return;
+
+   val = I915_READ(DP_TP_CTL(port));
+   val &= ~DP_TP_CTL_FEC_ENABLE;
+   I915_WRITE(DP_TP_CTL(port), val);
+   POSTING_READ(DP_TP_CTL(port));
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state 
*conn_state)
@@ -3272,7 +3288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*encoder,
}
 }
 
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -3291,6 +3308,9 @@ static void intel_disable_ddi_buf(struct intel_encoder 
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
 
+   /* Disable FEC in DP Sink */
+   intel_ddi_disable_fec_state(encoder, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
 }
@@ -3314,7 +3334,7 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
 
-   intel_disable_ddi_buf(encoder);
+   intel_disable_ddi_buf(encoder, old_crtc_state);
 
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
@@ -3337,7 +3357,7 @@ static void intel_ddi_post_disable_hdmi(struct 
intel_encoder *encoder,
 
intel_ddi_disable_pipe_clock(old_crtc_state);
 
-   intel_disable_ddi_buf(encoder);
+   intel_disable_ddi_buf(encoder, old_crtc_state);
 
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
 
@@ -3388,7 +3408,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder 
*encoder,
val &= ~FDI_RX_ENABLE;
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 
-   intel_disable_ddi_buf(encoder);
+   intel_disable_ddi_buf(encoder, old_crtc_state);
intel_ddi_clk_disable(encoder);
 
val = I915_READ(FDI_RX_MISC(PIPE_A));
-- 
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[Intel-gfx] [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check

2018-11-28 Thread Manasi Navare

DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.

v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)

v7:
* Fix indentation in compute_m_n (Manasi)

v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)

v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)

v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)

v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)

v2:
* Add if-else for eDP/DP (Gaurav)

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Cc: Gaurav K Singh 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
Reviewed-by: Ville Syrjala 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_display.c |   2 +-
 drivers/gpu/drm/i915/intel_display.h |   2 +-
 drivers/gpu/drm/i915/intel_dp.c  | 192 ---
 3 files changed, 172 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22b2a4e..69bb0b75a806 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6724,7 +6724,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
 }
 
 void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
   struct intel_link_m_n *m_n,
   bool constant_n)
diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index 5f2955b944da..5e253f741d29 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -423,7 +423,7 @@ struct intel_link_m_n {
 (__i)++) \
for_each_if(plane)
 
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 70ae3d57316b..a2780733768a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
 
 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC   8
+#define DP_DSC_MAX_SUPPORTED_BPC   10
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
 };
 
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state 
*pipe_config)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+   /* FIXME: FEC needed for external DP until then reject DSC on DP */
+   if (!intel_dp_is_edp(intel_dp))
+   return false;
+
+   return INTEL_GEN(dev_priv) >= 10 &&
+   pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+   return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+   drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+}
+
 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
 {
@@ -1842,14 +1864,115 @@ intel_dp_compute_link_config_fast(struct intel_dp 
*intel_dp,
return false;
 }
 
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+{
+   int i, num_bpc;
+   u8 dsc_bpc[3] = {0};
+
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+  dsc_bpc);
+   for (i = 0; i < num_bpc;

[Intel-gfx] [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes

2018-11-28 Thread Manasi Navare

DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.

v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_vdsc.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index a76e77a3231b..56290093d43f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -976,6 +976,25 @@ static void intel_configure_pps_for_dsc_encoder(struct 
intel_encoder *encoder,
}
 }
 
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+  const struct intel_crtc_state 
*crtc_state)
+{
+   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+   struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+   /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+   drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+   /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+   drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+   intel_dig_port->write_infoframe(encoder, crtc_state,
+   DP_SDP_PPS, _dsc_pps_sdp,
+   sizeof(dp_dsc_pps_sdp));
+}
+
 void intel_dsc_enable(struct intel_encoder *encoder,
  const struct intel_crtc_state *crtc_state)
 {
@@ -983,4 +1002,6 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
 
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+
+   intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
 }
-- 
2.19.1

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[Intel-gfx] [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled

2018-11-28 Thread Manasi Navare

If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.

v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Signed-off-by: Manasi Navare 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626eadff..2084784f320d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private 
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
 
+   /* Cannot enable DSC and PSR2 simultaneously */
+   WARN_ON(crtc_state->dsc_params.compression_enable &&
+   crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -502,6 +506,16 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
 
+   /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+   if (crtc_state->dsc_params.compression_enable) {
+   DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+   return false;
+   }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
-- 
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[Intel-gfx] [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

2018-11-28 Thread Manasi Navare

After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.

v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)

v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)

v2:
* Enable PG2 power well for VDSC on eDP

Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/intel_ddi.c  |   2 +
 drivers/gpu/drm/i915/intel_vdsc.c | 407 ++
 3 files changed, 411 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 183aae996305..9dc8731907af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3343,6 +3343,8 @@ extern void intel_rps_mark_interactive(struct 
drm_i915_private *i915,
   bool interactive);
 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  bool enable);
+void intel_dsc_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
 
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fa5ad62cd0db..339be10986d7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3144,6 +3144,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
 
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+   intel_dsc_enable(encoder, crtc_state);
 }
 
 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c 
b/drivers/gpu/drm/i915/intel_vdsc.c
index 39baff618ed8..a76e77a3231b 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -577,3 +577,410 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 
return intel_compute_rc_parameters(vdsc_cfg);
 }
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+   const struct intel_crtc_state 
*crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+   enum pipe pipe = crtc->pipe;
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+   u32 pps_val = 0;
+   u32 rc_buf_thresh_dword[4];
+   u32 rc_range_params_dword[8];
+   u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+   int i = 0;
+
+   /* Populate PICTURE_PARAMETER_SET_0 registers */
+   pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+   DSC_VER_MIN_SHIFT |
+   vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+   vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+   if (vdsc_cfg->block_pred_enable)
+   pps_val |= DSC_BLOCK_PREDICTION;
+   if (vdsc_cfg->convert_rgb)
+   pps_val |= DSC_COLOR_SPACE_CONVERSION;
+   if (vdsc_cfg->enable422)
+   pps_val |= DSC_422_ENABLE;
+   if (vdsc_cfg->vbr_enable)
+   pps_val |= DSC_VBR_ENABLE;
+   DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+   if (cpu_transcoder == TRANSCODER_EDP) {
+   I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+   /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+   if (crtc_state->dsc_params.dsc_split)
+   I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+   } else {
+   I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+   if (crtc_state->dsc_params.dsc_split)
+   I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+  pps_val);
+   }
+
+   /* Populate PICTURE_PARAMETER_SET_1 registers */
+   pps_val = 0;
+   pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+   DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+   if (cpu_transcoder == TRANSCODER_EDP) {
+

Re: [Intel-gfx] [PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully

2018-11-28 Thread Ville Syrjälä

On Wed, Nov 14, 2018 at 11:07:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Here's the remainder of the skl+ ddb/wm programming series. I tried to
> split up the ugly monster patch into a few chunks, and I tossed in
> a few extra nuggets on top. I also tried to improve the commit
> messages a bit based on the previous review feedback.
> 
> Entire series available here:
> git://github.com/vsyrjala/linux.git skl_plane_ddb_wm_update_3
> 
> Ville Syrjälä (13):
>   drm/i915: Reorganize plane register writes to make them more atomic
>   drm/i915: Move single buffered plane register writes to the end
>   drm/i915: Introduce crtc_state->update_planes bitmask
>   drm/i915: Pass the new crtc_state to ->disable_plane()
>   drm/i915: Fix latency==0 handling for level 0 watermark on skl+
>   drm/i915: Remove some useless zeroing on skl+ wm calculations
>   drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
>   drm/i915: Clean up skl+ vs. icl+ watermark computation
>   drm/i915: Don't pass dev_priv around so much
>   drm/i915: Move ddb/wm programming into plane update/disable hooks on
> skl+
>   drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
>   drm/i915: Rename the confusing 'plane_id' to 'color_plane'
>   drm/i915: Pass the plane to icl_program_input_csc_coeff()

Entire series pushed to dinq. Thanks for the reviews everyone.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/9] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

2018-11-28 Thread Souza, Jose

On Wed, 2018-11-28 at 11:02 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza
> wrote:
> > For PSR2 there is no register to tell HW to keep main link enabled
> > while PSR2 is active, so don't configure sink DPCD with a
> > misleading value.
> > 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 10 ++
> >  1 file changed, 6 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index f5d27a02eb28..888e348cc1b4 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -391,12 +391,14 @@ static void intel_psr_enable_sink(struct
> > intel_dp *intel_dp)
> > drm_dp_dpcd_writeb(_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> >DP_ALPM_ENABLE);
> > dpcd_val |= DP_PSR_ENABLE_PSR2;
> > +   } else {
> > +   if (dev_priv->psr.link_standby)
> > +   dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> > +
> > +   if (INTEL_GEN(dev_priv) >= 8)
> > +   dpcd_val |= DP_PSR_CRC_VERIFICATION;
> 
> commit message only mention the link stand-by...
> could you please do this in a separated patch?

We were already doing it for PSR1, I just grouped all the PSR1 checks
inside of this else block, so there is no functional change in CRC
verification but I can move it to a separated patch if you want.


> 
> > }
> >  
> > -   if (dev_priv->psr.link_standby)
> > -   dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> > -   if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> > -   dpcd_val |= DP_PSR_CRC_VERIFICATION;
> > drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> >  
> > drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > -- 
> > 2.19.2
> > 


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[Intel-gfx] [PULL] drm-misc-fixes

2018-11-28 Thread Sean Paul


Hi Dave,
Happy meson week! A bunch of stellar fixes coming in this week from Lyude, and a
couple others plugging holes in meson and core.


drm-misc-fixes-2018-11-28:
- mst: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Sergio)
- meson: Do vblank_on/off on enable/disable (Neil)
- meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
- meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)

Cc: Lyude Paul 
Cc: Sergio Correia 
Cc: Neil Armstrong 

Cheers, Sean


The following changes since commit 2e6e902d185027f8e3cb8b7305238f7e35d6a436:

  Linux 4.20-rc4 (2018-11-25 14:19:31 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2018-11-28

for you to fetch changes up to 31e1ab494559fb46de304cc6c2aed1528f94b298:

  drm/meson: add support for 1080p25 mode (2018-11-26 16:14:28 -0500)


- mst: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Sergio)
- meson: Do vblank_on/off on enable/disable (Neil)
- meson: Use fast_io regmap option to avoid sleeping in irq ctx (Lyude)
- meson: Don't walk off the end of the OSD EOTF LUTs (Lyude)

Cc: Lyude Paul 
Cc: Sergio Correia 
Cc: Neil Armstrong 


Christian Hewitt (1):
  drm/meson: add support for 1080p25 mode

Lyude Paul (3):
  drm/dp_mst: Skip validating ports during destruction, just ref
  drm/meson: Enable fast_io in meson_dw_hdmi_regmap_config
  drm/meson: Fix OOB memory accesses in meson_viu_set_osd_lut()

Neil Armstrong (1):
  drm/meson: Fixes for drm_crtc_vblank_on/off support

Sergio Correia (1):
  drm: set is_master to 0 upon drm_new_set_master() failure

 drivers/gpu/drm/drm_auth.c|  2 ++
 drivers/gpu/drm/drm_dp_mst_topology.c | 15 +--
 drivers/gpu/drm/meson/meson_crtc.c| 27 +--
 drivers/gpu/drm/meson/meson_dw_hdmi.c |  1 +
 drivers/gpu/drm/meson/meson_venc.c|  4 
 drivers/gpu/drm/meson/meson_viu.c | 12 ++--
 6 files changed, 51 insertions(+), 10 deletions(-)

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume

2018-11-28 Thread Daniele Ceraolo Spurio




On 27/11/2018 11:34, Daniele Ceraolo Spurio wrote:



On 26/11/2018 06:51, Michal Wajdeczko wrote:
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio 
 wrote:


/snip/

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h

index 8382d591c784..1a853cc627e3 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -687,6 +687,13 @@ enum intel_guc_report_status {
 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
 };
+enum intel_guc_sleep_state_status {
+    INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
+    INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
+    INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+};


btw, it used to be 0,1,2 but from some time fw defines above as:

 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3,

Michal


Yeah, I think I had already mentioned in some reply that the newer 
firmware does suspend/resume differently, but I haven't looked at the 
details. I'm not even sure if polling the register will still be required.


Daniele


I've confirmed with the GuC team that the differences are mostly 
internal to GuC and the only change from the kernel perspective is that 
the enum values have changed. We still need to do the polling, but I 
guess we'll be able to init the register to zero since all the return 
values are > 0.


Daniele


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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2)

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync 
registers on ring init (rev2)
URL   : https://patchwork.freedesktop.org/series/53154/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10927_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10927_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10927_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10927_full:

### IGT changes ###

 Warnings 

  * igt@pm_rc6_residency@rc6-accuracy:
- shard-snb:  SKIP -> PASS

  
Known issues


  Here are the changes found in Patchwork_10927_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +3

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-glk:  PASS -> FAIL [fdo#103232] +2

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl:  NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_flip@plain-flip-fb-recreate:
- shard-skl:  PASS -> FAIL [fdo#100368]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk:  PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +5

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl:  PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
- {shard-iclb}:   PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl:  NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107724]

  * igt@kms_rmfb@close-fd:
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] +1

  * igt@kms_setmode@basic:
- shard-hsw:  PASS -> FAIL [fdo#99912]

  * igt@pm_rpm@dpms-mode-unset-non-lpsp:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#107807]

  * igt@pm_rpm@gem-pread:
- {shard-iclb}:   PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]

  * igt@pm_rpm@legacy-planes-dpms:
- shard-skl:  PASS -> INCOMPLETE [fdo#105959] / [fdo#107807]

  
 Possible fixes 

  * igt@drm_import_export@import-close-race-flink:
- shard-skl:  TIMEOUT [fdo#108667] -> PASS

  * igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl:  FAIL [fdo#107725] -> PASS

  * igt@kms_color@pipe-a-ctm-max:
- shard-apl:  FAIL [fdo#108147] -> PASS

  * igt@kms_color@pipe-b-degamma:
- shard-apl:  FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl:  FAIL [fdo#103191] / [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk:  FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl:  FAIL [fdo#103232] -> PASS +2

  * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-xtiled:
- shard-skl:  FAIL [fdo#107791] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl:  FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl:  FAIL

Re: [Intel-gfx] [PATCH v7] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

2018-11-28 Thread Manasi Navare

On Wed, Nov 28, 2018 at 11:09:46AM +0200, Jani Nikula wrote:
> On Tue, 27 Nov 2018, Manasi Navare  wrote:
> > From: Matt Atwood 
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability. These
> > values will match 0h through Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> >
> > Read from DPCD once for all 3 values as this is an expensive operation.
> > Spec mentions that all of address space 02200h through 0220Fh should
> > contain the right information however currently only 3 values can
> > differ.
> >
> > There is no address space in the intel_dp->dpcd struct for addresses
> > 02200h through 0220Fh, and since so much of the data is a identical,
> > simply overwrite the values stored in 0h through Fh with the
> > values that can be overwritten from addresses 02200h through 0220Fh.
> >
> > This patch helps with backward compatibility for devices pre DP1.3.
> >
> > v2: read only dpcd values which can be affected, remove incorrect check,
> > split into drm include changes into separate patch, commit message,
> > verbose debugging statements during overwrite.
> > v3: white space fixes
> > v4: make path dependent on DPCD revision > 1.2
> > v5: split into function, removed DPCD rev check
> > v6: add debugging prints for early exit conditions
> > v7 (From Manasi):
> > * Memcpy, memcmp and debig logging based on sizeof(dpcd_ext) (Jani N)
> > * Exit early (Jani N)
> >
> > Cc: Jani Nikula 
> > Cc: Ville Syrjala 
> > Signed-off-by: Matt Atwood 
> > Tested-by: Manasi Navare 
> > Acked-by: Manasi Navare 
> > Reviewed-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 41 +
> >  1 file changed, 41 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 70ae3d57316b..a9eb14a4ab27 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3802,6 +3802,45 @@ intel_dp_link_down(struct intel_encoder *encoder,
> > }
> >  }
> >  
> > +static void
> > +intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
> > +{
> > +   u8 dpcd_ext[6];
> > +
> > +   /*
> > +* Prior to DP1.3 the bit represented by
> > +* DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
> > +* if it is set DP_DPCD_REV at h could be at a value less than
> > +* the true capability of the panel. The only way to check is to
> > +* then compare h and 2200h.
> > +*/
> > +   if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
> > +   return;
> > +
> > +   DRM_DEBUG_KMS("DPCD: Reading extended receiver capabilities\n");
> 
> Superfluous debug logging.

Will get rid of this

> 
> > +
> > +   if (drm_dp_dpcd_read(_dp->aux, DP_DP13_DPCD_REV,
> > +_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
> > +   DRM_ERROR("DPCD failed read at extended capabilities\n");
> 
> Most of our dpcd failures are logged using DRM_DEBUG_KMS. The ones that
> log DRM_ERROR seem to be very recent additions deviating from the debug
> loggin practice. There isn't much the user can do, really.

Here this change from DEBUG_KMS to DRM_ERROR was as per Rodrigo's comment
on the initial patch. (https://patchwork.freedesktop.org/patch/240452/) 
Also IMO it should be an error since it will give unexpected results as we were
unable to get the true extended capabilities.

> 
> > +   return;
> > +   }
> > +   if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
> > +   DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD 
> > rev\n");
> 
> Okay, seems like a rare event.

Again this check and logging comes from Rodrigo's review comments on the 
initial patch.

https://patchwork.freedesktop.org/patch/240452/

> 
> > +   return;
> > +   }
> > +   if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) {
> > +   DRM_DEBUG_KMS("Extended Receiver Cap DPCD match the base 
> > DPCD\n");
> 
> I don't think this debug logging is needed.

Sure will get rid of this.

> 
> > +   return;
> > +   }
> > +
> > +   DRM_DEBUG_KMS("Base DPCD: %*ph\n", (int)sizeof(dpcd_ext), 
> > intel_dp->dpcd);
> 
> Using sizeof(dpcd_ext) when printing something else is a red flag. You
> could log the whole dpcd here.
> 
>   DRM_DEBUG_KMS("DPCD: %*ph (base)\n", (int) sizeof(intel_dp->dpcd), 
> intel_dp->dpcd);

Yes will do this.

> 
> > +   DRM_DEBUG_KMS("Extended Receiver Cap DPCD: %*ph\n",
> > + (int)sizeof(dpcd_ext), dpcd_ext);
> 
> The caller will log the *updated* DPCD right after this returns, you
> don't need to log dpcd_ext.

Okay agreed, I will get rid of this debug print since the caller already prints 
it.


> 
> > +   memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
> > +}
> > +
> > +
> 
>

Re: [Intel-gfx] [PATCH 2/9] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

2018-11-28 Thread Rodrigo Vivi

On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
> while PSR2 is active, so don't configure sink DPCD with a
> misleading value.
> 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index f5d27a02eb28..888e348cc1b4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -391,12 +391,14 @@ static void intel_psr_enable_sink(struct intel_dp 
> *intel_dp)
>   drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
>  DP_ALPM_ENABLE);
>   dpcd_val |= DP_PSR_ENABLE_PSR2;
> + } else {
> + if (dev_priv->psr.link_standby)
> + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> +
> + if (INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;

commit message only mention the link stand-by...
could you please do this in a separated patch?

>   }
>  
> - if (dev_priv->psr.link_standby)
> - dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>  
>   drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> -- 
> 2.19.2
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params (fwd)

2018-11-28 Thread Julia Lawall



On Wed, 28 Nov 2018, Manasi Navare wrote:

> On Wed, Nov 28, 2018 at 11:46:26AM +, Julia Lawall wrote:
> > Hello,
> >
> > row_index and column_index are unsigned, so in the last line shown
> > they will not be less than 0.
> >
>
> Row_index and column_index are assigned to 0 at the beginning of the function 
> and so
> if thre is no valid index found the get_column_index /row_index will return 
> -EINVAL
> and hence they can have values < 0.

Since they have an unsigned type, the negative values will be considered
to be really big positive numbers.

julia

>
> Does this make sense?
>
> Manasi
>
> > julia
> >
> > -- Forwarded message --
> > Date: Wed, 28 Nov 2018 19:43:30 +0800
> > From: kbuild test robot 
> > To: kbu...@01.org
> > Cc: Julia Lawall 
> > Subject: Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA 
> > DSC
> > params
> >
> > CC: kbuild-...@01.org
> > In-Reply-To: <20181127214125.17658-10-manasi.d.nav...@intel.com>
> > References: <20181127214125.17658-10-manasi.d.nav...@intel.com>
> > TO: Manasi Navare 
> > CC: intel-gfx@lists.freedesktop.org
> > CC:
> >
> > Hi Gaurav,
> >
> > Thank you for the patch! Perhaps something to improve:
> >
> > [auto build test WARNING on drm-intel/for-linux-next]
> > [also build test WARNING on next-20181127]
> > [cannot apply to v4.20-rc4]
> > [if your patch is applied to the wrong git tree, please drop us a note to 
> > help improve the system]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095026
> > base:   git://anongit.freedesktop.org/drm-intel for-linux-next
> > :: branch date: 10 hours ago
> > :: commit date: 10 hours ago
> >
> > >> drivers/gpu/drm/i915/intel_vdsc.c:404:22-34: WARNING: Unsigned 
> > >> expression compared with zero: column_index < 0
> > >> drivers/gpu/drm/i915/intel_vdsc.c:404:5-14: WARNING: Unsigned expression 
> > >> compared with zero: row_index < 0
> >
> > # 
> > https://github.com/0day-ci/linux/commit/5b6895999d5a84b154fcd49dc3a91d71897d03ec
> > git remote add linux-review https://github.com/0day-ci/linux
> > git remote update linux-review
> > git checkout 5b6895999d5a84b154fcd49dc3a91d71897d03ec
> > vim +404 drivers/gpu/drm/i915/intel_vdsc.c
> >
> > 5b689599 Gaurav K Singh 2018-11-27  319
> > 5b689599 Gaurav K Singh 2018-11-27  320  int 
> > intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> > 5b689599 Gaurav K Singh 2018-11-27  321 struct 
> > intel_crtc_state *pipe_config)
> > 5b689599 Gaurav K Singh 2018-11-27  322  {
> > 5b689599 Gaurav K Singh 2018-11-27  323 struct drm_dsc_config *vdsc_cfg 
> > = _config->dp_dsc_cfg;
> > 5b689599 Gaurav K Singh 2018-11-27  324 u16 compressed_bpp = 
> > pipe_config->dsc_params.compressed_bpp;
> > 5b689599 Gaurav K Singh 2018-11-27  325 u8 i = 0;
> > 5b689599 Gaurav K Singh 2018-11-27  326 u8 row_index = 0;
> > 5b689599 Gaurav K Singh 2018-11-27  327 u8 column_index = 0;
> > 5b689599 Gaurav K Singh 2018-11-27  328 u8 line_buf_depth = 0;
> > 5b689599 Gaurav K Singh 2018-11-27  329
> > 5b689599 Gaurav K Singh 2018-11-27  330 vdsc_cfg->pic_width = 
> > pipe_config->base.adjusted_mode.crtc_hdisplay;
> > 5b689599 Gaurav K Singh 2018-11-27  331 vdsc_cfg->pic_height = 
> > pipe_config->base.adjusted_mode.crtc_vdisplay;
> > 5b689599 Gaurav K Singh 2018-11-27  332 vdsc_cfg->slice_width = 
> > DIV_ROUND_UP(vdsc_cfg->pic_width,
> > 5b689599 Gaurav K Singh 2018-11-27  333 
> >  pipe_config->dsc_params.slice_count);
> > 5b689599 Gaurav K Singh 2018-11-27  334 /*
> > 5b689599 Gaurav K Singh 2018-11-27  335  * Slice Height of 8 works for 
> > all currently available panels. So start
> > 5b689599 Gaurav K Singh 2018-11-27  336  * with that if pic_height is 
> > an integral multiple of 8.
> > 5b689599 Gaurav K Singh 2018-11-27  337  * Eventually add logic to try 
> > multiple slice heights.
> > 5b689599 Gaurav K Singh 2018-11-27  338  */
> > 5b689599 Gaurav K Singh 2018-11-27  339 if (vdsc_cfg->pic_height % 8 == 
> > 0)
> > 5b689599 Gaurav K Singh 2018-11-27  340 vdsc_cfg->slice_height 
> > = 8;
> > 5b689599 Gaurav K Singh 2018-11-27  341 else if (vdsc_cfg->pic_height %

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

2018-11-28 Thread Patchwork

== Series Details ==

Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync 
registers on ring init
URL   : https://patchwork.freedesktop.org/series/53154/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10926_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_10926_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10926_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10926_full:

### IGT changes ###

 Warnings 

  * igt@pm_rc6_residency@rc6-accuracy:
- shard-snb:  SKIP -> PASS

  
Known issues


  Here are the changes found in Patchwork_10926_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-glk:  PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] +2

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-glk:  PASS -> FAIL [fdo#103232] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl:  PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-glk:  PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk:  PASS -> FAIL [fdo#103167] +3

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl:  PASS -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl:  PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-kbl:  NOTRUN -> FAIL [fdo#103166]

  * igt@kms_setmode@basic:
- shard-hsw:  PASS -> FAIL [fdo#99912]

  * {igt@runner@aborted}:
- shard-hsw:  NOTRUN -> FAIL [fdo#108770]

  
 Possible fixes 

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing:
- shard-apl:  INCOMPLETE [fdo#103927] -> PASS +1

  * igt@kms_color@pipe-a-ctm-max:
- shard-apl:  FAIL [fdo#108147] -> PASS

  * igt@kms_color@pipe-b-degamma:
- shard-apl:  FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-apl:  FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl:  FAIL [fdo#103191] / [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk:  FAIL [fdo#103232] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl:  FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl:  FAIL [fdo#103167] / [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk:  FAIL [fdo#103167] -> PASS +2

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-apl:  DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +27

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk:  FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-apl:  FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-kbl:  DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +13

  * igt@kms_setmode@basic:
- shard-apl:  FAIL [fdo#99912] -> PASS

  * igt@perf@blocking:
- shard-hsw:  FAIL [fdo#102252] -> PASS

  
 Warnings 

  * igt@i915_suspend@shrink:
- shard-kbl:  INCOMPLETE [fdo#103665] / [fdo#106886] -> DMESG-WARN 
[fdo#108784]

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]:

Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations

2018-11-28 Thread Lyude Paul

On Wed, 2018-11-28 at 09:17 +0100, Daniel Vetter wrote:
> On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote:
> > On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote:
> > > On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote:
> > > > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote:
> > > > > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Daniel Vetter wrote:
> > > > > > On Thu, Nov 15, 2018 at 07:50:05PM -0500, Lyude Paul wrote:
> > > > > > > There has been a TODO waiting for quite a long time in
> > > > > > > drm_dp_mst_topology.c:
> > > > > > > 
> > > > > > >   /* We cannot rely on port->vcpi.num_slots to update
> > > > > > >* topology_state->avail_slots as the port may not exist if
> > > > > > > the parent
> > > > > > >* branch device was unplugged. This should be fixed by
> > > > > > > tracking
> > > > > > >* per-port slot allocation in drm_dp_mst_topology_state
> > > > > > > instead of
> > > > > > >* depending on the caller to tell us how many slots to
> > > > > > > release.
> > > > > > >*/
> > > > > > > 
> > > > > > > That's not the only reason we should fix this: forcing the
> > > > > > > driver to
> > > > > > > track the VCPI allocations throughout a state's atomic check is
> > > > > > > error prone, because it means that extra care has to be taken
> > > > > > > with
> > > > > > > the
> > > > > > > order that drm_dp_atomic_find_vcpi_slots() and
> > > > > > > drm_dp_atomic_release_vcpi_slots() are called in in order to
> > > > > > > ensure
> > > > > > > idempotency. Currently the only driver actually using these
> > > > > > > helpers,
> > > > > > > i915, doesn't even do this correctly: multiple ->best_encoder()
> > > > > > > checks
> > > > > > > with i915's current implementation would not be idempotent and
> > > > > > > would
> > > > > > > over-allocate VCPI slots, something I learned trying to
> > > > > > > implement
> > > > > > > fallback retraining in MST.
> > > > > > > 
> > > > > > > So: simplify this whole mess, and teach
> > > > > > > drm_dp_atomic_find_vcpi_slots()
> > > > > > > and drm_dp_atomic_release_vcpi_slots() to track the VCPI
> > > > > > > allocations
> > > > > > > for
> > > > > > > each port. This allows us to ensure idempotency without having
> > > > > > > to
> > > > > > > rely
> > > > > > > on the driver as much. Additionally: the driver doesn't need to
> > > > > > > do
> > > > > > > any
> > > > > > > kind of VCPI slot tracking anymore if it doesn't need it for
> > > > > > > it's
> > > > > > > own
> > > > > > > internal state.
> > > > > > > 
> > > > > > > Additionally; this adds a new drm_dp_mst_atomic_check() helper
> > > > > > > which
> > > > > > > must be used by atomic drivers to perform validity checks for
> > > > > > > the
> > > > > > > new
> > > > > > > VCPI allocations incurred by a state.
> > > > > > > 
> > > > > > > Also: update the documentation and make it more obvious that
> > > > > > > these
> > > > > > > /must/ be called by /all/ atomic drivers supporting MST.
> > > > > > > 
> > > > > > > Changes since v6:
> > > > > > >  - Keep a kref to all of the ports we have allocations on. This
> > > > > > > required
> > > > > > >a good bit of changing to when we call
> > > > > > > drm_dp_find_vcpi_slots(),
> > > > > > >mainly that we need to ensure that we only redo VCPI
> > > > > > > allocations
> > > > > > > on
> > > > > > >actual mode or CRTC changes, not crtc_state->active changes.
> > > > > > >Additionally, we no longer take the registration of the DRM
> > > > > > > connector
> > > > > > >for each port into account because so long as we have a kref
> > > > > > > to
> > > > > > > the
> > > > > > >port in the new or previous atomic state, the connector will
> > > > > > > stay
> > > > > > >registered.
> > > > > > 
> > > > > > I write an entire pile of small nitpits (still included most of
> > > > > > them
> > > > > > below), until I realized this here wont work. Delaying the call to
> > > > > > destroy
> > > > > > the connector (well, unregister it really) wreaks the design we've
> > > > > > come up
> > > > > > with thus far, resulting in most of my comments here.
> > > > > > 
> > > > > > Instead, all we need to do is delay the kfree(port) at the bottom
> > > > > > of
> > > > > > drm_dp_destroy_port(). The vcpi allocation structure _only_ needs
> > > > > > the
> > > > > > pointer value to stay valid, as a lookup key. It doesn't care at
> > > > > > all
> > > > > > about
> > > > > > anything actually stored in there. So the only thing we need to
> > > > > > delay
> > > > > > is
> > > > > > the kfree. I think the simplest way to achieve this is to add a
> > > > > > 2nd
> > > > > > kref
> > > > > > (port->kfree_ref or something like that), with on reference held
> > > > > > by
> > > > > > the
> > > > > > port itself (released in drm_dp_destroy_port), and the other one
> > > > > > held
> > > > > > as-needed by the vcpi allocation lists.
> > > > > > 
> > > > > > I think if we go with this design instead of

Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params (fwd)

2018-11-28 Thread Manasi Navare

On Wed, Nov 28, 2018 at 11:46:26AM +, Julia Lawall wrote:
> Hello,
> 
> row_index and column_index are unsigned, so in the last line shown
> they will not be less than 0.
>

Row_index and column_index are assigned to 0 at the beginning of the function 
and so
if thre is no valid index found the get_column_index /row_index will return 
-EINVAL
and hence they can have values < 0.

Does this make sense?

Manasi
 
> julia
> 
> -- Forwarded message --
> Date: Wed, 28 Nov 2018 19:43:30 +0800
> From: kbuild test robot 
> To: kbu...@01.org
> Cc: Julia Lawall 
> Subject: Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA 
> DSC
> params
> 
> CC: kbuild-...@01.org
> In-Reply-To: <20181127214125.17658-10-manasi.d.nav...@intel.com>
> References: <20181127214125.17658-10-manasi.d.nav...@intel.com>
> TO: Manasi Navare 
> CC: intel-gfx@lists.freedesktop.org
> CC:
> 
> Hi Gaurav,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm-intel/for-linux-next]
> [also build test WARNING on next-20181127]
> [cannot apply to v4.20-rc4]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095026
> base:   git://anongit.freedesktop.org/drm-intel for-linux-next
> :: branch date: 10 hours ago
> :: commit date: 10 hours ago
> 
> >> drivers/gpu/drm/i915/intel_vdsc.c:404:22-34: WARNING: Unsigned expression 
> >> compared with zero: column_index < 0
> >> drivers/gpu/drm/i915/intel_vdsc.c:404:5-14: WARNING: Unsigned expression 
> >> compared with zero: row_index < 0
> 
> # 
> https://github.com/0day-ci/linux/commit/5b6895999d5a84b154fcd49dc3a91d71897d03ec
> git remote add linux-review https://github.com/0day-ci/linux
> git remote update linux-review
> git checkout 5b6895999d5a84b154fcd49dc3a91d71897d03ec
> vim +404 drivers/gpu/drm/i915/intel_vdsc.c
> 
> 5b689599 Gaurav K Singh 2018-11-27  319
> 5b689599 Gaurav K Singh 2018-11-27  320  int 
> intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> 5b689599 Gaurav K Singh 2018-11-27  321   struct 
> intel_crtc_state *pipe_config)
> 5b689599 Gaurav K Singh 2018-11-27  322  {
> 5b689599 Gaurav K Singh 2018-11-27  323   struct drm_dsc_config *vdsc_cfg 
> = _config->dp_dsc_cfg;
> 5b689599 Gaurav K Singh 2018-11-27  324   u16 compressed_bpp = 
> pipe_config->dsc_params.compressed_bpp;
> 5b689599 Gaurav K Singh 2018-11-27  325   u8 i = 0;
> 5b689599 Gaurav K Singh 2018-11-27  326   u8 row_index = 0;
> 5b689599 Gaurav K Singh 2018-11-27  327   u8 column_index = 0;
> 5b689599 Gaurav K Singh 2018-11-27  328   u8 line_buf_depth = 0;
> 5b689599 Gaurav K Singh 2018-11-27  329
> 5b689599 Gaurav K Singh 2018-11-27  330   vdsc_cfg->pic_width = 
> pipe_config->base.adjusted_mode.crtc_hdisplay;
> 5b689599 Gaurav K Singh 2018-11-27  331   vdsc_cfg->pic_height = 
> pipe_config->base.adjusted_mode.crtc_vdisplay;
> 5b689599 Gaurav K Singh 2018-11-27  332   vdsc_cfg->slice_width = 
> DIV_ROUND_UP(vdsc_cfg->pic_width,
> 5b689599 Gaurav K Singh 2018-11-27  333   
>  pipe_config->dsc_params.slice_count);
> 5b689599 Gaurav K Singh 2018-11-27  334   /*
> 5b689599 Gaurav K Singh 2018-11-27  335* Slice Height of 8 works for 
> all currently available panels. So start
> 5b689599 Gaurav K Singh 2018-11-27  336* with that if pic_height is 
> an integral multiple of 8.
> 5b689599 Gaurav K Singh 2018-11-27  337* Eventually add logic to try 
> multiple slice heights.
> 5b689599 Gaurav K Singh 2018-11-27  338*/
> 5b689599 Gaurav K Singh 2018-11-27  339   if (vdsc_cfg->pic_height % 8 == 
> 0)
> 5b689599 Gaurav K Singh 2018-11-27  340   vdsc_cfg->slice_height 
> = 8;
> 5b689599 Gaurav K Singh 2018-11-27  341   else if (vdsc_cfg->pic_height % 
> 4 == 0)
> 5b689599 Gaurav K Singh 2018-11-27  342   vdsc_cfg->slice_height 
> = 4;
> 5b689599 Gaurav K Singh 2018-11-27  343   else
> 5b689599 Gaurav K Singh 2018-11-27  344   vdsc_cfg->slice_height 
> = 2;
> 5b689599 Gaurav K Singh 2018-11-27  345
> 5b689599 Gaurav K Singh 2018-11-27  346   /* Values filled from DSC Sink 
> DPCD */
> 5b689599 Gaurav K Singh 2018-11-27  347   vdsc_cfg->dsc_version_major =
> 5b689599 Gaurav K Singh 2018-11-27  348   
> (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &a

Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

2018-11-28 Thread Rodrigo Vivi

On Wed, Nov 28, 2018 at 10:21:05AM -0800, Souza, Jose wrote:
> On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote:
> > On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza
> > wrote:
> > > As stated in struct drm_encoder, crtc field should only be used
> > > by non-atomic drivers.
> > > 
> > > So here caching the pipe id in intel_psr_enable() what is way more
> > > simple and efficient than at every call to
> > > intel_psr_flush()/invalidate() get the
> > > drm.mode_config.connection_mutex lock to safely be able to get the
> > > pipe id by reading drm_connector_state.crtc.
> > > 
> > > This should fix the null pointer dereference crash below as the
> > > previous way to get the pipe id was prone to race conditions.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959
> > > Cc: Dhinakaran Pandiyan 
> > > Cc: Rodrigo Vivi 
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
> > >  drivers/gpu/drm/i915/intel_psr.c | 19 ---
> > >  2 files changed, 5 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index f763b30f98d9..9ea39b82836f 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -494,6 +494,7 @@ struct i915_psr {
> > >   bool sink_support;
> > >   bool prepared, enabled;
> > >   struct intel_dp *dp;
> > > + enum pipe pipe;
> > >   bool active;
> > >   struct work_struct work;
> > >   unsigned busy_frontbuffer_bits;
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 572e626eadff..11a520074f06 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -705,6 +705,7 @@ void intel_psr_enable(struct intel_dp
> > > *intel_dp,
> > >   dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv,
> > > crtc_state);
> > >   dev_priv->psr.busy_frontbuffer_bits = 0;
> > >   dev_priv->psr.prepared = true;
> > > + dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)-
> > > >pipe;
> > >  
> > >   if (psr_global_enabled(dev_priv->psr.debug))
> > >   intel_psr_enable_locked(dev_priv, crtc_state);
> > > @@ -1012,9 +1013,6 @@ static void intel_psr_work(struct work_struct
> > > *work)
> > >  void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> > > unsigned frontbuffer_bits, enum fb_op_origin
> > > origin)
> > >  {
> > > - struct drm_crtc *crtc;
> > > - enum pipe pipe;
> > > -
> > >   if (!CAN_PSR(dev_priv))
> > >   return;
> > >  
> > > @@ -1027,10 +1025,7 @@ void intel_psr_invalidate(struct
> > > drm_i915_private *dev_priv,
> > >   return;
> > >   }
> > >  
> > > - crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> > > - pipe = to_intel_crtc(crtc)->pipe;
> > > -
> > > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > > + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > > >psr.pipe);
> > >   dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
> > >  
> > >   if (frontbuffer_bits)
> > > @@ -1055,9 +1050,6 @@ void intel_psr_invalidate(struct
> > > drm_i915_private *dev_priv,
> > >  void intel_psr_flush(struct drm_i915_private *dev_priv,
> > >unsigned frontbuffer_bits, enum fb_op_origin
> > > origin)
> > >  {
> > > - struct drm_crtc *crtc;
> > > - enum pipe pipe;
> > > -
> > >   if (!CAN_PSR(dev_priv))
> > >   return;
> > >  
> > > @@ -1070,10 +1062,7 @@ void intel_psr_flush(struct drm_i915_private
> > > *dev_priv,
> > >   return;
> > >   }
> > >  
> > > - crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> > > - pipe = to_intel_crtc(crtc)->pipe;
> > > -
> > > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > > + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > > >psr.pipe);
> > 
> > This approach will introduce another bug.
> > 
> > Any frontbuffer tracking from any connector on another pipe will
> > trigger
> > psr actions on eDP.
> 
> Why that would happen? dev_priv->psr.pipe will be set with the pipe id
> that is used by the eDP panel so INTEL_FRONTBUFFER_ALL_MASK() will
> return only the frontbuffer bits of that pipe.

Oh... nevermind... and I saw that we were already getting from psr.dp
anyway...


Reviewed-by: Rodrigo Vivi 



> 
> > 
> > >   dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> > >  
> > >   /* By definition flush = invalidate + flush */
> > > @@ -1087,7 +1076,7 @@ void intel_psr_flush(struct drm_i915_private
> > > *dev_priv,
> > >* but it makes more sense write to the current active
> > >* pipe.
> > >*/
> > > - I915_WRITE(CURSURFLIVE(pipe), 0);
> > > + I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
> > >   }
> > >  
> > >   if (!dev_priv->psr.active && !dev_priv-
> > > >psr.busy_frontbuffer_bits)
> > > -- 
> > > 2.19.2
> > > 
> > >

Re: [Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines

2018-11-28 Thread Souza, Jose

On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote:
> On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza
> wrote:
> > As stated in struct drm_encoder, crtc field should only be used
> > by non-atomic drivers.
> > 
> > So here caching the pipe id in intel_psr_enable() what is way more
> > simple and efficient than at every call to
> > intel_psr_flush()/invalidate() get the
> > drm.mode_config.connection_mutex lock to safely be able to get the
> > pipe id by reading drm_connector_state.crtc.
> > 
> > This should fix the null pointer dereference crash below as the
> > previous way to get the pipe id was prone to race conditions.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959
> > Cc: Dhinakaran Pandiyan 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
> >  drivers/gpu/drm/i915/intel_psr.c | 19 ---
> >  2 files changed, 5 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index f763b30f98d9..9ea39b82836f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -494,6 +494,7 @@ struct i915_psr {
> > bool sink_support;
> > bool prepared, enabled;
> > struct intel_dp *dp;
> > +   enum pipe pipe;
> > bool active;
> > struct work_struct work;
> > unsigned busy_frontbuffer_bits;
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 572e626eadff..11a520074f06 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -705,6 +705,7 @@ void intel_psr_enable(struct intel_dp
> > *intel_dp,
> > dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv,
> > crtc_state);
> > dev_priv->psr.busy_frontbuffer_bits = 0;
> > dev_priv->psr.prepared = true;
> > +   dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)-
> > >pipe;
> >  
> > if (psr_global_enabled(dev_priv->psr.debug))
> > intel_psr_enable_locked(dev_priv, crtc_state);
> > @@ -1012,9 +1013,6 @@ static void intel_psr_work(struct work_struct
> > *work)
> >  void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> >   unsigned frontbuffer_bits, enum fb_op_origin
> > origin)
> >  {
> > -   struct drm_crtc *crtc;
> > -   enum pipe pipe;
> > -
> > if (!CAN_PSR(dev_priv))
> > return;
> >  
> > @@ -1027,10 +1025,7 @@ void intel_psr_invalidate(struct
> > drm_i915_private *dev_priv,
> > return;
> > }
> >  
> > -   crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> > -   pipe = to_intel_crtc(crtc)->pipe;
> > -
> > -   frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > +   frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > >psr.pipe);
> > dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
> >  
> > if (frontbuffer_bits)
> > @@ -1055,9 +1050,6 @@ void intel_psr_invalidate(struct
> > drm_i915_private *dev_priv,
> >  void intel_psr_flush(struct drm_i915_private *dev_priv,
> >  unsigned frontbuffer_bits, enum fb_op_origin
> > origin)
> >  {
> > -   struct drm_crtc *crtc;
> > -   enum pipe pipe;
> > -
> > if (!CAN_PSR(dev_priv))
> > return;
> >  
> > @@ -1070,10 +1062,7 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > return;
> > }
> >  
> > -   crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
> > -   pipe = to_intel_crtc(crtc)->pipe;
> > -
> > -   frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > +   frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > >psr.pipe);
> 
> This approach will introduce another bug.
> 
> Any frontbuffer tracking from any connector on another pipe will
> trigger
> psr actions on eDP.

Why that would happen? dev_priv->psr.pipe will be set with the pipe id
that is used by the eDP panel so INTEL_FRONTBUFFER_ALL_MASK() will
return only the frontbuffer bits of that pipe.

> 
> > dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> >  
> > /* By definition flush = invalidate + flush */
> > @@ -1087,7 +1076,7 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> >  * but it makes more sense write to the current active
> >  * pipe.
> >  */
> > -   I915_WRITE(CURSURFLIVE(pipe), 0);
> > +   I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
> > }
> >  
> > if (!dev_priv->psr.active && !dev_priv-
> > >psr.busy_frontbuffer_bits)
> > -- 
> > 2.19.2
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx


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[Intel-gfx] [PULL] drm-intel-fixes

2018-11-28 Thread Joonas Lahtinen

Hi Dave,

Been a steady week, and no fixes apart from GVT, so quoting Zhenyu:

"One to correct MOCS registers load on engine list, one for rpm lock
warning fix, and another for use-after-free fix for partial ggtt
list destroy. "

Next week, Thursday is a national holiday in Finland, so I'll send
the PR by Wed if there is something urgent surfacing, but doesn't
look like that for now.

Regards, Joonas

***

drm-intel-fixes-2018-11-28:

Just gvt-fixes-2018-11-26

The following changes since commit 2e6e902d185027f8e3cb8b7305238f7e35d6a436:

  Linux 4.20-rc4 (2018-11-25 14:19:31 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-11-28

for you to fetch changes up to 2455facbb700e3c3ca26b9255956d6ed45cb6217:

  Merge tag 'gvt-fixes-2018-11-26' of https://github.com/intel/gvt-linux into 
drm-intel-fixes (2018-11-26 11:19:48 +0200)


Just gvt-fixes-2018-11-26


Chris Wilson (1):
  drm/i915/gvt: Avoid use-after-free iterating the gtt list

Hang Yuan (1):
  drm/i915/gvt: ensure gpu is powered before do i915_gem_gtt_insert

Joonas Lahtinen (1):
  Merge tag 'gvt-fixes-2018-11-26' of https://github.com/intel/gvt-linux 
into drm-intel-fixes

Xinyun Liu (1):
  drm/i915/gvt: not to touch undefined MOCS registers

 drivers/gpu/drm/i915/gvt/aperture_gm.c  | 2 ++
 drivers/gpu/drm/i915/gvt/gtt.c  | 7 ---
 drivers/gpu/drm/i915/gvt/mmio_context.c | 2 ++
 3 files changed, 8 insertions(+), 3 deletions(-)
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Fix up drm_atomic_state_helper.[hc] extraction

2018-11-28 Thread Patchwork

== Series Details ==

Series: drm: Fix up drm_atomic_state_helper.[hc] extraction
URL   : https://patchwork.freedesktop.org/series/53148/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10925_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_10925_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10925_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_10925_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_userptr_blits@readonly-unsync:
- shard-glk:  PASS -> TIMEOUT

  
Known issues


  Here are the changes found in Patchwork_10925_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-1us:
- shard-glk:  PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl:  NOTRUN -> FAIL [fdo#103158]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl:  NOTRUN -> INCOMPLETE [fdo#106887]

  * igt@i915_suspend@shrink:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#108784]

  * igt@kms_available_modes_crc@available_mode_test_crc:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb:  NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#107725]

  * igt@kms_color@pipe-a-gamma:
- shard-skl:  NOTRUN -> FAIL [fdo#104782]

  * igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-glk:  PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] +2

  * igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl:  PASS -> FAIL [fdo#103232] +4

  * igt@kms_cursor_crc@cursor-256x256-offscreen:
- shard-skl:  PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-glk:  PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-dpms:
- {shard-iclb}:   NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-snb:  NOTRUN -> INCOMPLETE [fdo#105411]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl:  PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk:  PASS -> FAIL [fdo#104873]

  * igt@kms_flip@busy-flip-interruptible:
- shard-skl:  PASS -> FAIL [fdo#103257]

  * igt@kms_flip_tiling@flip-to-y-tiled:
- shard-skl:  PASS -> FAIL [fdo#107931]
- {shard-iclb}:   PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}:   PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk:  PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-skl:  NOTRUN -> FAIL [fdo#105682] +2

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- {shard-iclb}:   PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl:  NOTRUN -> FAIL [fdo#103167] +3

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-skl:  PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl:  NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk:  PASS -> FAIL [fdo#103166]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl:  NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl:  PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl:  PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- {shard-iclb}:   PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-kbl:  NOTRUN -> FAIL [fdo#103166]
- shard-skl:  NOTRUN -> FAIL [fdo#103166] / [fdo#107815]

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- {shard-iclb}:   NOTRUN -> DMESG-WARN [fdo#107724]

  * igt@kms_rotation_crc@primary-rotation-180:
- shard-snb:  NOTRUN -> FAIL [fdo#103925]

  *

Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE

2018-11-28 Thread Lucas De Marchi

On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote:
> On Tue, 06 Nov 2018, Lucas De Marchi  wrote:
> > From: Rodrigo Vivi 
> >
> > RANGE makes it longer, but clear. We are also going to add a check for
> > the display part, so make rename to GT.
> 
> I also still have my doubts about this patch I'm afraid. I've expressed
> the concern before, but here goes again.
> 
> How much is the split of gen to GT gen and display gen going to help us
> in the long run? The only current platform that would benefit from this
> is GLK. However, not all IS_GEMINILAKE() can be replaced with
> IS_DISPLAY_GEN() >= 10 or similar. We also have VLV/CHV display that is
> better represented by HAS_GMCH_DISPLAY() and AFAICT can't usefully be
> replaced by a display gen check.
> 
> My main fear is that the split adds a lot of confusion. (Where should I
> use GT gen, where should I use display gen, patches to change between
> one and the other. It's not 100% clear cut.)
> 
> Here too I wonder if we're better off adding more has_feature flags that
> describe what gt or display features a platform has.

It will never be a clear cut. Adding more flags make perfect sense when
there is such a feature to check for. Sometimes registers just change
location based on what is the display gen. Having the display gen serves
to group small differences together into a "single flag" if you will.
And today what we do is to actually check for gen rather than display
gen. Or a mix of platform names.

Lucas De Marchi
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Re: [Intel-gfx] [PATCH v2 0/7] Make GEN macros more similar

2018-11-28 Thread Lucas De Marchi

On Tue, Nov 27, 2018 at 04:19:23PM -0800, Rodrigo Vivi wrote:
> > Then on the question of IS_ prefix or not, I don't feel very strongly about
> > it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it
> > doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote
> > ends up being.
> 
> okay, the HAS_ parallel is a good point...
> 
> but still in that case my brain prefers
> 
> if HAS_FEATURE
> than
> if FEATURE
> 
> because "FEATURE what?" Like if feature was more "transitive" requiring 
> something else.
> 
> while for "is" my brain prefers
> 
> if PLATFORM
> than
> if IS_PLATFORM
> 
> because here it seems more "intransitive"...
> like... self contained meaning where "is" can be implicit.

for me both IS_PLATFORM and PLATFORM make sense. IS_ prefix is used in
several other places for things like that. I just don't like the outcome
of having it: gigantic horrendous macros like IS_GT_GEN_RANGE().

Lucas De Marchi
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Re: [Intel-gfx] [PATCH 4/4] drm/edid: Add display_info.rgb_quant_range_selectable

2018-11-28 Thread Eric Anholt

Ville Syrjala  writes:

> From: Ville Syrjälä 
>
> Move the CEA-861 QS bit handling entirely into the edid code. No
> need to bother the drivers with this.
>
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: "David (ChunMing) Zhou" 
> Cc: amd-...@lists.freedesktop.org
> Cc: Eric Anholt  (supporter:DRM DRIVERS FOR VC4)
> Signed-off-by: Ville Syrjälä 

For vc4,
Acked-by: Eric Anholt 

Looks like a nice cleanup!


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