Re: [Intel-gfx] [PATCH] drm/i915/breadcrumbs: Drop assertion that we've already enabled irqs
On 17/01/2019 23:31, Chris Wilson wrote:
The motivation for introducing the check that we only enable breadcrumb
irqs if the device's irq was installed was once upon a time we waited
during suspend after disabling interrupts (which was quite slow until
the bug was discovered). Since then we have the notion of pinning the
breadcrumb irq, broadening it from the sole purpose of user interrupt
notification and waiting, and more importantly decoupling it from a very
defined time period during which enabling the irq was expected. So stop
insisting the irq is installed before we setup our IMR masks, if the IER
isn't yet enabled, nothing will happen and we will timeout instead,
revealing the lack of irq in the hang debug messages.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 28 ++--
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ed7105d7ff5..bfbff04c16aa 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -158,30 +158,24 @@ static void intel_breadcrumbs_fake_irq(struct timer_list
*t)
static void irq_enable(struct intel_engine_cs *engine)
{
- /*
-* FIXME: Ideally we want this on the API boundary, but for the
-* sake of testing with mock breadcrumbs (no HW so unable to
-* enable irqs) we place it deep within the bowels, at the point
-* of no return.
-*/
- GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
+ if (!engine->irq_enable)
+ return;
/* Caller disables interrupts */
- if (engine->irq_enable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_enable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_enable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
static void irq_disable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_disable)
+ return;
+
/* Caller disables interrupts */
- if (engine->irq_disable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_disable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_disable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Split out drm_probe_helper.h (rev4)
== Series Details == Series: drm: Split out drm_probe_helper.h (rev4) URL : https://patchwork.freedesktop.org/series/55232/ State : success == Summary == CI Bug Log - changes from CI_DRM_5441_full -> Patchwork_11974_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11974_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - shard-skl: NOTRUN -> INCOMPLETE [fdo#108901] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +7 * igt@kms_atomic_transition@plane-all-transition: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#109225] * igt@kms_color@pipe-c-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_crc@cursor-128x128-dpms: - shard-apl: PASS -> FAIL [fdo#103232] +2 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-size-change: - shard-glk: PASS -> FAIL [fdo#103232] * igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +5 * igt@kms_fbcon_fbt@psr: - shard-iclb: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-glk: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-iclb: NOTRUN -> FAIL [fdo#108948] * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-x: - shard-iclb: PASS -> FAIL [fdo#103166] +2 * igt@kms_setmode@basic: - shard-hsw: PASS -> FAIL [fdo#99912] - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] * igt@pm_rps@min-max-config-loaded: - shard-iclb: NOTRUN -> FAIL [fdo#102250] Possible fixes * igt@i915_suspend@fence-restore-untiled: - shard-iclb: INCOMPLETE [fdo#107713] -> PASS * igt@kms_atomic_transition@plane-all-transition-nonblocking: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#109225] -> PASS * igt@kms_cursor_crc@cursor-128x128-onscreen: - shard-glk: FAIL [fdo#103232] -> PASS +1 * igt@kms_cursor_crc@cursor-256x256-random: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-iclb: WARN [fdo#108336] -> PASS +1 * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: DMESG-FAIL [fdo#105681] / [fdo#107724] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS +3 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: DMESG-FAIL [fdo#107724] -> PASS +5 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-iclb: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +2 * igt@kms_plane@pixel-format-pipe-a-planes: - shard-glk: FAIL [fdo#103166] -> PASS * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-apl: FAIL [fdo#108948] -> PASS * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS * igt@kms_universal_plane@universal-plane-pipe-c-functional: - shard-apl: FAIL [fdo#103166] -> PASS * igt@kms_vblank@pipe-b-query-idle-hang: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +15 * igt@pm_rpm@dpms-lpsp: - shard-iclb: INCOMPLETE [fdo#108840] -> PASS +1 Warnings * igt@
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Adding few more device IDs for Ice Lake
== Series Details ==
Series: drm/i915/icl: Adding few more device IDs for Ice Lake
URL : https://patchwork.freedesktop.org/series/55393/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5444 -> Patchwork_11978
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55393/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11978 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: PASS -> DMESG-WARN [fdo#105541]
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182]
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-icl-u2: DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (48 -> 44)
--
Additional (1): fi-kbl-7560u
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5444 -> Patchwork_11978
CI_DRM_5444: d940d4523445e27e553d1f66da0cef2954f23418 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11978: e1ff6a31726cf09202bf7bba91333deabaf2e638 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e1ff6a31726c drm/i915/icl: Adding few more device IDs for Ice Lake
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11978/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for icl: Misc PLL patches
== Series Details == Series: icl: Misc PLL patches URL : https://patchwork.freedesktop.org/series/55378/ State : success == Summary == CI Bug Log - changes from CI_DRM_5440_full -> Patchwork_11972_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11972_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@i915_suspend@shrink: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_cursor_crc@cursor-64x21-sliding: - shard-apl: PASS -> FAIL [fdo#103232] +6 * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-glk: PASS -> FAIL [fdo#104873] * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-iclb: PASS -> FAIL [fdo#103355] * igt@kms_draw_crc@draw-method-xrgb-blt-untiled: - shard-skl: PASS -> FAIL [fdo#103232] / [fdo#108472] * igt@kms_draw_crc@draw-method-xrgb-pwrite-ytiled: - shard-skl: PASS -> FAIL [fdo#108222] * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move: - shard-glk: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#105682] +3 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-skl: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-a-planes: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes: - shard-skl: NOTRUN -> FAIL [fdo#103166] * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - shard-iclb: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] * igt@kms_setmode@basic: - shard-kbl: PASS -> FAIL [fdo#99912] * igt@pm_rpm@dpms-lpsp: - shard-skl: PASS -> INCOMPLETE [fdo#107807] Possible fixes * igt@debugfs_test@read_all_entries_display_off: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +2 * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-iclb: DMESG-WARN [fdo#107956] -> PASS * igt@kms_color@pipe-a-gamma: - shard-skl: FAIL [fdo#104782] -> PASS * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x42-sliding: - shard-glk: FAIL [fdo#103232] -> PASS +2 * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +2 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: FAIL [fdo#105767] -> PASS * igt@kms_flip_event_leak: - shard-kbl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +4 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS - shard-apl: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - shard-glk: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-2p-rte: - sh
[Intel-gfx] [PATCH] drm/i915/icl: Adding few more device IDs for Ice Lake
We just got aware that there was more IDs available at spec, so let's add them already. Cc: James Ausmus Cc: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 4 1 file changed, 4 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 192667144693..df72be7e8b88 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -457,9 +457,13 @@ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5C, info), \ INTEL_VGA_DEVICE(0x8A5D, info), \ + INTEL_VGA_DEVICE(0x8A59, info), \ + INTEL_VGA_DEVICE(0x8A58, info), \ INTEL_VGA_DEVICE(0x8A52, info), \ INTEL_VGA_DEVICE(0x8A5A, info), \ INTEL_VGA_DEVICE(0x8A5B, info), \ + INTEL_VGA_DEVICE(0x8A57, info), \ + INTEL_VGA_DEVICE(0x8A56, info), \ INTEL_VGA_DEVICE(0x8A71, info), \ INTEL_VGA_DEVICE(0x8A70, info) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user
== Series Details == Series: drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user URL : https://patchwork.freedesktop.org/series/55366/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5440_full -> Patchwork_11971_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_11971_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11971_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11971_full: ### IGT changes ### Possible regressions * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> DMESG-FAIL Known issues Here are the changes found in Patchwork_11971_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@i915_suspend@shrink: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_ccs@pipe-a-crc-primary-basic: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_color@pipe-c-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] * igt@kms_cursor_crc@cursor-128x42-sliding: - shard-apl: PASS -> FAIL [fdo#103232] +6 * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-iclb: PASS -> FAIL [fdo#103355] * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled: - shard-iclb: PASS -> WARN [fdo#108336] +2 * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-skl: PASS -> FAIL [fdo#103184] +1 * igt@kms_draw_crc@draw-method-xrgb-blt-untiled: - shard-skl: PASS -> FAIL [fdo#103232] / [fdo#108472] * igt@kms_draw_crc@draw-method-xrgb-pwrite-ytiled: - shard-skl: PASS -> FAIL [fdo#108222] * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: PASS -> FAIL [fdo#105683] / [fdo#108040] - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-skl: PASS -> FAIL [fdo#105682] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#105682] +2 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_rmfb@close-fd: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-apl: PASS -> DMESG-FAIL [fdo#108950] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] * igt@pm_rpm@universal-planes: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] Possible fixes * igt@debugfs_test@read_all_entries_display_off: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +1 * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS * igt@kms_cursor_
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/breadcrumbs: Drop assertion that we've already enabled irqs
== Series Details ==
Series: drm/i915/breadcrumbs: Drop assertion that we've already enabled irqs
URL : https://patchwork.freedesktop.org/series/55388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5443 -> Patchwork_11977
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55388/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11977 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6700k2: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#108767]
Possible fixes
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (48 -> 44)
--
Additional (1): fi-pnv-d510
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5443 -> Patchwork_11977
CI_DRM_5443: 62c660c0385bee9e07ef59265f95e66fb536753e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11977: 5cc8b2907dce7e07ef6d6dc7692e1953ca4f244d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5cc8b2907dce drm/i915/breadcrumbs: Drop assertion that we've already enabled
irqs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11977/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_mmap_gtt: Reset faster and longer to catch fencing errors
Performing a GPU reset clobbers the fence registers, affecting which
addresses the tiled GTT mmap access. If the driver does not take
precautions across a GPU reset, a client may read the wrong values (but
only within their own buffer as the fence will only be degraded to
I915_TILING_NONE, reducing the access area). However, as this requires
performing a read using the indirect GTT at exactly the same time as the
reset occurs, it can be quite difficult to catch, so repeat the test
many times and across all cores simultaneously.
Signed-off-by: Chris Wilson
---
tests/i915/gem_mmap_gtt.c | 99 +++
1 file changed, 68 insertions(+), 31 deletions(-)
diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
index f63535556..21880d31d 100644
--- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.c
@@ -38,6 +38,7 @@
#include "drm.h"
#include "igt.h"
+#include "igt_sysfs.h"
#include "igt_x86.h"
#ifndef PAGE_SIZE
@@ -375,50 +376,86 @@ test_clflush(int fd)
static void
test_hang(int fd)
{
- igt_hang_t hang;
- uint32_t patterns[] = {
+ const uint32_t patterns[] = {
0, 0x, 0x, 0x,
};
- uint32_t *gtt[3];
- int last_pattern = 0;
- int next_pattern = 1;
- int i;
+ const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+ struct {
+ bool done;
+ bool error;
+ } *control;
+ unsigned long count;
+ igt_hang_t hang;
+ int dir;
- for (i = I915_TILING_NONE; i <= I915_TILING_Y; i++) {
- uint32_t handle;
+ hang = igt_allow_hang(fd, 0, 0);
+ igt_sysfs_set_parameter(fd, "reset", "1"); /* global resets */
- handle = gem_create(fd, OBJECT_SIZE);
- gem_set_tiling(fd, handle, i, 2048);
+ control = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(control != MAP_FAILED);
- gtt[i] = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_WRITE);
- set_domain_gtt(fd, handle);
- gem_close(fd, handle);
- }
+ igt_fork(child, ncpus) {
+ int last_pattern = 0;
+ int next_pattern = 1;
+ uint32_t *gtt[2];
- hang = igt_hang_ring(fd, I915_EXEC_RENDER);
+ for (int i = 0; i < ARRAY_SIZE(gtt); i++) {
+ uint32_t handle;
- do {
- for (i = 0; i < OBJECT_SIZE / 64; i++) {
- int x = 16*i + (i%16);
+ handle = gem_create(fd, OBJECT_SIZE);
+ gem_set_tiling(fd, handle, I915_TILING_X + i, 2048);
- igt_assert(gtt[0][x] == patterns[last_pattern]);
- igt_assert(gtt[1][x] == patterns[last_pattern]);
- igt_assert(gtt[2][x] == patterns[last_pattern]);
+ gtt[i] = gem_mmap__gtt(fd, handle, OBJECT_SIZE,
PROT_WRITE);
+ set_domain_gtt(fd, handle);
+ gem_close(fd, handle);
+ }
- gtt[0][x] = patterns[next_pattern];
- gtt[1][x] = patterns[next_pattern];
- gtt[2][x] = patterns[next_pattern];
+ while (!READ_ONCE(control->done)) {
+ for (int i = 0; i < OBJECT_SIZE / 64; i++) {
+ uint32_t expected = patterns[last_pattern];
+ uint32_t found[2];
+ int x = 16*i + (i%16);
+
+ found[0] = READ_ONCE(gtt[0][x]);
+ found[1] = READ_ONCE(gtt[1][x]);
+
+ if (found[0] != expected ||
+ found[1] != expected) {
+ igt_warn("child[%d] found (%x, %x),
expecting %x\n",
+child,
+found[0], found[1],
+expected);
+ control->error = true;
+ exit(0);
+ }
+
+ gtt[0][x] = patterns[next_pattern];
+ gtt[1][x] = patterns[next_pattern];
+ }
+
+ last_pattern = next_pattern;
+ next_pattern = (next_pattern + 1) %
ARRAY_SIZE(patterns);
}
+ }
- last_pattern = next_pattern;
- next_pattern = (next_pattern + 1) % ARRAY_SIZE(patterns);
- } while (gem_bo_busy(fd, hang.spin->handle));
+ count = 0;
+ dir = igt_debugfs_dir(fd);
+ igt_until_timeout(5) {
+ igt_sysfs_set(dir, "i915_wedged", "-1");
+ if (READ_ONCE(control->error))
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Query the vm under test for hugepage support (rev2)
== Series Details ==
Series: drm/i915/selftests: Query the vm under test for hugepage support (rev2)
URL : https://patchwork.freedesktop.org/series/55386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5442 -> Patchwork_11976
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55386/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_11976 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#107341]
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (48 -> 44)
--
Additional (1): fi-skl-6770hq
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5442 -> Patchwork_11976
CI_DRM_5442: e61d473e10b8b46fd205b388ec39b6c431b5ba8f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11976: a5987d3cf56d1900b5c4c7e44c8839cd6a632fb2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a5987d3cf56d drm/i915/selftests: Query the vm under test for hugepage support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11976/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/23] drm/i915: Make all GPU resets atomic
Quoting Patchwork (2019-01-17 23:36:23) > Possible regressions > > * igt@gem_mmap_gtt@hang: > - shard-snb: PASS -> FAIL The only thing unexpected here is that they all didn't fail. (Dropping this protection of disabling memory access while the fence registers are being reset is a shortcoming of not being able to take a common mutex in i915_gem_fault and reset due to the memory allocations required to setup the CPU PTEs.) I guess I should ensure that this test always fails so we don't get annoying flip-flops. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/23] drm/i915: Make all GPU resets atomic
== Series Details == Series: series starting with [01/23] drm/i915: Make all GPU resets atomic URL : https://patchwork.freedesktop.org/series/55365/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5440_full -> Patchwork_11970_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_11970_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11970_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11970_full: ### IGT changes ### Possible regressions * igt@gem_mmap_gtt@hang: - shard-snb: PASS -> FAIL Known issues Here are the changes found in Patchwork_11970_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@i915_suspend@shrink: - shard-skl: NOTRUN -> INCOMPLETE [fdo#106886] - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_ccs@pipe-a-crc-primary-basic: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_color@pipe-a-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_color@pipe-a-degamma: - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_color@pipe-b-legacy-gamma: - shard-apl: PASS -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-64x21-sliding: - shard-apl: PASS -> FAIL [fdo#103232] +6 * igt@kms_cursor_crc@cursor-size-change: - shard-glk: PASS -> FAIL [fdo#103232] +2 * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: PASS -> FAIL [fdo#103060] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-apl: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: - shard-glk: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#103167] +5 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-apl: PASS -> FAIL [fdo#108948] * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes: - shard-skl: NOTRUN -> FAIL [fdo#103166] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] - shard-glk: PASS -> FAIL [fdo#103166] - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-apl: PASS -> DMESG-FAIL [fdo#108950] * igt@kms_rotation_crc@primary-rotation-180: - shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] * igt@pm_rpm@system-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807] * igt@pm_rpm@universal-planes-dpms: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] Possible fixes * igt@debugfs_test@read_all_entries_display_off: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +2 * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: FAIL [fdo#103232] -> PASS +2 - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +3 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: FAIL [
[Intel-gfx] [PATCH] drm/i915/breadcrumbs: Drop assertion that we've already enabled irqs
The motivation for introducing the check that we only enable breadcrumb
irqs if the device's irq was installed was once upon a time we waited
during suspend after disabling interrupts (which was quite slow until
the bug was discovered). Since then we have the notion of pinning the
breadcrumb irq, broadening it from the sole purpose of user interrupt
notification and waiting, and more importantly decoupling it from a very
defined time period during which enabling the irq was expected. So stop
insisting the irq is installed before we setup our IMR masks, if the IER
isn't yet enabled, nothing will happen and we will timeout instead,
revealing the lack of irq in the hang debug messages.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 28 ++--
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ed7105d7ff5..bfbff04c16aa 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -158,30 +158,24 @@ static void intel_breadcrumbs_fake_irq(struct timer_list
*t)
static void irq_enable(struct intel_engine_cs *engine)
{
- /*
-* FIXME: Ideally we want this on the API boundary, but for the
-* sake of testing with mock breadcrumbs (no HW so unable to
-* enable irqs) we place it deep within the bowels, at the point
-* of no return.
-*/
- GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
+ if (!engine->irq_enable)
+ return;
/* Caller disables interrupts */
- if (engine->irq_enable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_enable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_enable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
static void irq_disable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_disable)
+ return;
+
/* Caller disables interrupts */
- if (engine->irq_disable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_disable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_disable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 32/46] drm/i915: Pull VM lists under the VM mutex.
Quoting Tvrtko Ursulin (2019-01-17 16:23:48)
>
> On 16/01/2019 17:01, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-01-16 16:47:43)
> >>
> >> On 07/01/2019 11:54, Chris Wilson wrote:
> >>> @@ -1530,20 +1531,21 @@ i915_gem_pwrite_ioctl(struct drm_device *dev,
> >>> void *data,
> >>>
> >>>static void i915_gem_object_bump_inactive_ggtt(struct
> >>> drm_i915_gem_object *obj)
> >>>{
> >>> - struct drm_i915_private *i915;
> >>> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> >>>struct list_head *list;
> >>>struct i915_vma *vma;
> >>>
> >>>GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
> >>>
> >>> + mutex_lock(&i915->ggtt.vm.mutex);
> >>>for_each_ggtt_vma(vma, obj) {
> >>>if (!drm_mm_node_allocated(&vma->node))
> >>>continue;
> >>>
> >>>list_move_tail(&vma->vm_link, &vma->vm->bound_list);
> >>>}
> >>> + mutex_unlock(&i915->ggtt.vm.mutex);
> >>
> >> This is now struct_mutex -> vm->mutex nesting, which we would preferably
> >> want to avoid? There only two callers for the function.
> >>
> >> It looks we could remove nesting from i915_gem_set_domain_ioctl by just
> >> moving the call to after mutex unlock.
> >>
> >> i915_gem_object_unpin_from_display_plane callers are not as easy so
> >> maybe at least do the one above?
> >
> > unpin_from_display_plane is the goal here tbh.
> >
> >>> - i915 = to_i915(obj->base.dev);
> >>>spin_lock(&i915->mm.obj_lock);
> >>>list = obj->bind_count ? &i915->mm.bound_list :
> >>> &i915->mm.unbound_list;
> >>>list_move_tail(&obj->mm.link, list);
> >>> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
> >>> b/drivers/gpu/drm/i915/i915_gem_evict.c
> >>> index a76f65fe86be..4a0c6830659d 100644
> >>> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> >>> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> >>> @@ -433,6 +433,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
> >>>}
> >>>
> >>>INIT_LIST_HEAD(&eviction_list);
> >>> + mutex_lock(&vm->mutex);
> >>>list_for_each_entry(vma, &vm->bound_list, vm_link) {
> >>>if (i915_vma_is_pinned(vma))
> >>>continue;
> >>> @@ -440,6 +441,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
> >>>__i915_vma_pin(vma);
> >>>list_add(&vma->evict_link, &eviction_list);
> >>>}
> >>> + mutex_unlock(&vm->mutex);
> >>
> >> This is another nesting so I suppose you leave all this fun for later?
Yes, I remember some more of the fun that made me defer this task -- and
that was the random waits we could hit, requiring the GPU reset dilemma
be resolved (i.e. reworking reset to avoid taking any these resets,
which also prevents us from hitting these from the shrinker).
> > Yes, the intent was to put the locks in place (gradually) then peel back
> > struct_mutex (gradually).
> >
> >>> @@ -689,8 +694,10 @@ i915_vma_remove(struct i915_vma *vma)
> >>>
> >>>vma->ops->clear_pages(vma);
> >>>
> >>> + mutex_lock(&vma->vm->mutex);
> >>>drm_mm_remove_node(&vma->node);
> >>
> >> This is by design also protected by the vm->mutex? But insertion is not
> >> AFAICT.
> >
> > Not yet. Can you guess which bit proved tricky? ;) Getting the right
> > point to lock for execbuf, and eviction. At the same time over there is
> > the fuss with ww_mutex, as well as contexts et al, and it all gets
> > confusing quickly.
> >
> > ...(tries to remember why this patch is actually here; this set was
> > picked so that I could do obj->vma_list without struct_mutex (which
> > was used for timeline allocation) and I pulled in anything required to
> > resolve conflicts, but why this one)...
>
> Have you figured it out in the meantime?
The patch does at it says and protects the vma->vm_link/vm->*_list. You
start to look at trying to decide if i915_vma_pin() does atomic magic or
if it should require the caller lock(vm->mutex), and I quickly descend
into wanting to do the domain+fence management of
ww_mutex_lock(obj->resv.lock) instead.
Bah, make the caller take vm->mutex and then we can see if that is
better than atomic magic later.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/selftests: Query the vm under test for hugepage support
Since we have the ppgtt we want to test, we can ask it directly if it is
suitable for the hugepage test we intend to undertake.
v2: Not everyone has full-ppgtt
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index a52450111802..a9a2fa35876f 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1449,7 +1449,7 @@ static int igt_ppgtt_pin_update(void *arg)
* huge-gtt-pages.
*/
- if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
+ if (!ppgtt || !i915_vm_is_48bit(&ppgtt->vm)) {
pr_info("48b PPGTT not supported, skipping\n");
return 0;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Query the vm under test for hugepage support
== Series Details ==
Series: drm/i915/selftests: Query the vm under test for hugepage support
URL : https://patchwork.freedesktop.org/series/55386/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5441 -> Patchwork_11975
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_11975 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11975, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55386/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11975:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hugepages:
- fi-snb-2520m: PASS -> INCOMPLETE
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- fi-snb-2520m: NOTRUN -> FAIL
- fi-snb-2600:NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_11975 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hugepages:
- fi-snb-2600:PASS -> INCOMPLETE [fdo#105411]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
Possible fixes
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (47 -> 42)
--
Additional (2): fi-ivb-3520m fi-skl-guc
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-skl-6260u fi-icl-y fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5441 -> Patchwork_11975
CI_DRM_5441: 11e23757a15c3aaf01a06a0e63a7d2d0d7f9d76d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11975: fde77805efeaab8da03da64c4d181244df9f440b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fde77805efea drm/i915/selftests: Query the vm under test for hugepage support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11975/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Query the vm under test for hugepage support
Since we have the ppgtt we want to test, we can ask it directly if it is
suitable for the hugepage test we intend to undertake.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index a52450111802..e724819e458d 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1449,7 +1449,7 @@ static int igt_ppgtt_pin_update(void *arg)
* huge-gtt-pages.
*/
- if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
+ if (!i915_vm_is_48bit(&ppgtt->vm)) {
pr_info("48b PPGTT not supported, skipping\n");
return 0;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 3/3] PM/runtime:Replace jiffies based accounting with ktime based accounting
On Fri, Dec 21, 2018 at 11:33:56AM +0100, Vincent Guittot wrote:
> From: Thara Gopinath
>
> This patch replaces jiffies based accounting for runtime_active_time
> and runtime_suspended_time with ktime base accounting. This makes the
> runtime debug counters inline with genpd and other pm subsytems which
> uses ktime based accounting.
>
> timekeeping is initialized before pm_runtime_init() so ktime_get() will
> be ready before first call. In fact, timekeeping_init() is called early
> in start_kernel() which is way before driver_init() (and that's when
> devices can start to be initialized) called from rest_init() via
> kernel_init_freeable() and do_basic_setup().
>
This is not (always) correct. My qemu "collie" boot test fails with this
patch applied. Reverting the patch fixes the problem. Bisect log attached.
With some added debugging:
...
IRQS: 16, nr_irqs: 65, preallocated irqs: 65
irq: Cannot allocate irq_descs @ IRQ1, assuming pre-allocated
gpio gpiochip0: ### pm_runtime_init()
irq: Cannot allocate irq_descs @ IRQ33, assuming pre-allocated
## timekeeping_init()
sched_clock: 32 bits at 3686kHz, resolution 271ns, wraps every 58254200ns^M
...
This is with:
void pm_runtime_init(struct device *dev)
{
+ dev_info(dev, "### pm_runtime_init() \n");
+
...
@@ -1526,6 +1526,8 @@ void __init timekeeping_init(void)
struct clocksource *clock;
unsigned long flags;
+ pr_info("## timekeeping_init() \n");
+
Guenter
---
# bad: [a37d50ca3b837c19a297f349365d11a20c1087d0] Add linux-next specific files
for 20190117
# good: [1c7fc5cbc33980acd13d668f1c8f0313d6ae9fd8] Linux 5.0-rc2
git bisect start 'HEAD' 'v5.0-rc2'
# bad: [4edb817d29fdf19fb5d52784bb3c29c40e00f586] Merge remote-tracking branch
'pm/linux-next'
git bisect bad 4edb817d29fdf19fb5d52784bb3c29c40e00f586
# good: [6d95886720d306a1914a7c9a8aeb0bcbc7aef018] Merge remote-tracking branch
'omap/for-next'
git bisect good 6d95886720d306a1914a7c9a8aeb0bcbc7aef018
# good: [975b5cdd74430bc8a04f832d65a47cdb95b73fec] Merge remote-tracking branch
'fuse/for-next'
git bisect good 975b5cdd74430bc8a04f832d65a47cdb95b73fec
# good: [112386d2189fc54b979c3a8bf64b2908df91e123] Merge remote-tracking branch
'i2c/i2c/for-next'
git bisect good 112386d2189fc54b979c3a8bf64b2908df91e123
# good: [3943f059823b6e15884387f31618b84826e924b3] media: coda: Add control for
h.264 chroma qp index offset
git bisect good 3943f059823b6e15884387f31618b84826e924b3
# good: [44970b5079ee100875b06e45db5d6e91a16e] Merge remote-tracking branch
'v4l-dvb/master'
git bisect good 44970b5079ee100875b06e45db5d6e91a16e
# bad: [599170c2b860aca3364574f833bb9cc801c9668d] Merge branch 'pm-core' into
linux-next
git bisect bad 599170c2b860aca3364574f833bb9cc801c9668d
# good: [347d570919ca9a3a3653ce9cbb7399c7c0ba8248] Merge branch 'acpi-pci' into
linux-next
git bisect good 347d570919ca9a3a3653ce9cbb7399c7c0ba8248
# good: [e0a9fde86ba1bc26dd754c733b32e70cd8f1c187] Merge branches 'acpi-tables'
and 'acpi-apei' into linux-next
git bisect good e0a9fde86ba1bc26dd754c733b32e70cd8f1c187
# good: [3b4ed2e2eb5583774a1ed4aa4596a5a3c55f2567] drm/i915: Move on the new pm
runtime interface
git bisect good 3b4ed2e2eb5583774a1ed4aa4596a5a3c55f2567
# bad: [c75c303933a68c547f3352d1d708843f9449d3f4] PM: clock_ops: fix missing
clk_prepare() return value check
git bisect bad c75c303933a68c547f3352d1d708843f9449d3f4
# bad: [3982ab9ce433efc72ca31eb9ddc85d9355966444] PM-runtime: Replace jiffies
based accounting with ktime-based accounting
git bisect bad 3982ab9ce433efc72ca31eb9ddc85d9355966444
# first bad commit: [3982ab9ce433efc72ca31eb9ddc85d9355966444] PM-runtime:
Replace jiffies based accounting with ktime-based accounting
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Split out drm_probe_helper.h (rev4)
== Series Details ==
Series: drm: Split out drm_probe_helper.h (rev4)
URL : https://patchwork.freedesktop.org/series/55232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5441 -> Patchwork_11974
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55232/revisions/4/mbox/
Known issues
Here are the changes found in Patchwork_11974 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
Possible fixes
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (47 -> 42)
--
Additional (2): fi-ivb-3520m fi-skl-guc
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-whl-u
fi-gdg-551 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5441 -> Patchwork_11974
CI_DRM_5441: 11e23757a15c3aaf01a06a0e63a7d2d0d7f9d76d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11974: 6b67170fc38297157f1ba3be2c69f7bb76b1f1f1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6b67170fc382 drm: Split out drm_probe_helper.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11974/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: allow shared plls to be non-consecutive
On Thu, Jan 17, 2019 at 12:21 PM Lucas De Marchi
wrote:
>
> Right now when searching for shared plls we mandate that they have
> consecutive IDs since we just pass the min and max id and loop over the
> range. However the IDs can't be arbitrarily defined since they are used
> as index to the MMIO address, hence dependent on what the hardware
> implements.
>
> This allows us to use PLLs that are not consecutive (although we don't
> currently have any case) while clarifying the code paths in which only
> one PLL is supposed to be used.
Other possible approach for if/when we need this would be to use a different
macro that doesn't use the id as the index for the registers... Not
sure which one is better.
Lucas De Marchi
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 41 ---
> 1 file changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 8f70838ac7d8..103e42cfa2e3 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -243,8 +243,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> static struct intel_shared_dpll *
> intel_find_shared_dpll(struct intel_crtc *crtc,
>struct intel_crtc_state *crtc_state,
> - enum intel_dpll_id range_min,
> - enum intel_dpll_id range_max)
> + unsigned long pll_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll, *unused_pll = NULL;
> @@ -253,7 +252,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
>
> shared_dpll =
> intel_atomic_get_shared_dpll_state(crtc_state->base.state);
>
> - for (i = range_min; i <= range_max; i++) {
> + for_each_set_bit(i, &pll_mask, I915_NUM_PLLS) {
> pll = &dev_priv->shared_dplls[i];
>
> /* Only want to check enabled timings first */
> @@ -436,8 +435,8 @@ ibx_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> pll->info->name);
> } else {
> pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_PCH_PLL_A,
> -DPLL_ID_PCH_PLL_B);
> +GENMASK(DPLL_ID_PCH_PLL_B,
> +DPLL_ID_PCH_PLL_A));
> }
>
> if (!pll)
> @@ -780,7 +779,7 @@ static struct intel_shared_dpll
> *hsw_ddi_hdmi_get_dpll(int clock,
> crtc_state->dpll_hw_state.wrpll = val;
>
> pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
> +GENMASK(DPLL_ID_WRPLL2, DPLL_ID_WRPLL1));
>
> if (!pll)
> return NULL;
> @@ -840,7 +839,7 @@ hsw_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
> SPLL_PLL_SSC;
>
> pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_SPLL, DPLL_ID_SPLL);
> +BIT(DPLL_ID_SPLL));
> } else {
> return NULL;
> }
> @@ -1389,6 +1388,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> int clock = crtc_state->port_clock;
> bool bret;
> struct intel_dpll_hw_state dpll_hw_state;
> + unsigned long pll_mask;
>
> memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
>
> @@ -1410,13 +1410,11 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> }
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_SKL_DPLL0,
> -DPLL_ID_SKL_DPLL0);
> + pll_mask = BIT(DPLL_ID_SKL_DPLL0);
> else
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_SKL_DPLL1,
> -DPLL_ID_SKL_DPLL3);
> + pll_mask = GENMASK(DPLL_ID_SKL_DPLL3, DPLL_ID_SKL_DPLL1);
> +
> + pll = intel_find_shared_dpll(crtc, crtc_state, pll_mask);
> if (!pll)
> return NULL;
>
> @@ -2390,8 +2388,8 @@ cnl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> }
>
> pll = intel_find_shared_dpll(crtc, crtc_state,
> -DPLL_ID_SKL_DPLL0,
> -DPLL_ID_SKL_DPLL2);
> +GENMASK(DPLL_ID_SKL_DP
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Split out drm_probe_helper.h (rev4)
== Series Details == Series: drm: Split out drm_probe_helper.h (rev4) URL : https://patchwork.freedesktop.org/series/55232/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6b67170fc382 drm: Split out drm_probe_helper.h -:686: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus_drv.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:689: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus_drv.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:698: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus_mode.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:701: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus_mode.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:3405: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #3405: new file mode 100644 -:3410: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #3410: FILE: include/drm/drm_probe_helper.h:1: +// SPDX-License-Identifier: GPL-2.0 OR MIT -:3436: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 7 warnings, 0 checks, 2226 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: introduce macros to define register contents (rev2)
== Series Details == Series: drm/i915: introduce macros to define register contents (rev2) URL : https://patchwork.freedesktop.org/series/50513/ State : success == Summary == CI Bug Log - changes from CI_DRM_5440_full -> Patchwork_11969_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_11969_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11969_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11969_full: ### IGT changes ### Warnings * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> FAIL Known issues Here are the changes found in Patchwork_11969_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@i915_suspend@shrink: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244] - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107886] / [fdo#109244] * igt@kms_addfb_basic@too-wide: - shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +16 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_ccs@pipe-a-crc-primary-basic: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_color@pipe-c-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] +4 * igt@kms_cursor_crc@cursor-64x64-sliding: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: NOTRUN -> FAIL [fdo#105682] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +6 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - shard-iclb: PASS -> FAIL [fdo#103166] +3 * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-glk: PASS -> FAIL [fdo#103166] +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-apl: PASS -> DMESG-FAIL [fdo#108950] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] * igt@pm_rpm@modeset-lpsp-stress-no-wait: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] * igt@sw_sync@sync_busy_fork: - shard-skl: NOTRUN -> INCOMPLETE [fdo#108889] Possible fixes * igt@debugfs_test@read_all_entries_display_off: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_color@pipe-a-gamma: - shard-skl: FAIL [fdo#104782] -> PASS * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x42-sliding: - shard-glk: FAIL [fdo#103232] -> PASS +2 * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +1 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: FAIL [fdo#105767] -> PASS * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled: - shard-skl: FAIL [fdo#103184] -> PASS * igt@kms_flip_event_leak:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v4,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/psr: Allow PSR2 to be enabled
when debugfs asks
URL : https://patchwork.freedesktop.org/series/55379/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5440 -> Patchwork_11973
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_11973 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11973, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55379/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11973:
### IGT changes ###
Possible regressions
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: NOTRUN -> WARN
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@cursor_plane_move:
- fi-icl-u2: PASS -> {SKIP} +3
- fi-icl-u3: PASS -> {SKIP} +3
Known issues
Here are the changes found in Patchwork_11973 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (45 -> 44)
--
Additional (3): fi-kbl-7567u fi-glk-j4005 fi-byt-clapper
Missing(4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5440 -> Patchwork_11973
CI_DRM_5440: b36a89b5ab74fd49a4369e6df0d2c02bc464a474 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11973: 5e13a560ff7c0f00642245c6d992313900372420 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5e13a560ff7c drm/i915/debugfs: Print PSR selective update status register values
4636e2528cf3 drm/i915: Add PSR2 selective update status registers and bits
definitions
24183bf35613 drm/i915: Refactor PSR status debugfs
5e4082ef6525 drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11973/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Series Details == Series: series starting with [v4,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks URL : https://patchwork.freedesktop.org/series/55379/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5e4082ef6525 drm/i915/psr: Allow PSR2 to be enabled when debugfs asks 24183bf35613 drm/i915: Refactor PSR status debugfs -:22: WARNING:BAD_SIGN_OFF: Use a single space after To: #22: To: -:22: ERROR:BAD_SIGN_OFF: Unrecognized email address: '' #22: To: total: 1 errors, 1 warnings, 0 checks, 146 lines checked 4636e2528cf3 drm/i915: Add PSR2 selective update status registers and bits definitions -:33: WARNING:LONG_LINE: line over 100 characters #33: FILE: drivers/gpu/drm/i915/i915_reg.h:4278: +#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) total: 0 errors, 1 warnings, 0 checks, 15 lines checked 5e13a560ff7c drm/i915/debugfs: Print PSR selective update status register values ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for icl: Misc PLL patches
== Series Details ==
Series: icl: Misc PLL patches
URL : https://patchwork.freedesktop.org/series/55378/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5440 -> Patchwork_11972
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55378/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11972 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-skl-gvtdvm: PASS -> INCOMPLETE [fdo#105600] / [fdo#108744]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105600]: https://bugs.freedesktop.org/show_bug.cgi?id=105600
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (45 -> 42)
--
Additional (3): fi-kbl-7567u fi-glk-j4005 fi-byt-clapper
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-icl-y
Build changes
-
* Linux: CI_DRM_5440 -> Patchwork_11972
CI_DRM_5440: b36a89b5ab74fd49a4369e6df0d2c02bc464a474 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11972: 12401b81e6c363f85249d4e0d0060d94a27106f6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
12401b81e6c3 drm/i915: allow shared plls to be non-consecutive
27401a448f20 drm/i915/icl: keep track of unused pll while looping
29f565fdc104 drm/i915/icl: remove dpll from clk_sel
6246a3763ba7 drm/i915: always return something
bc90321eb832 drm/i915/icl: use tc_port in MG_PLL macros
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11972/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/4] drm/i915/debugfs: Print PSR selective update status register values
The value of this registers will be used to test if PSR2 is doing
selective update and if the number of blocks match with the expected.
v2:
- Using new macros
- Changed the string output
v3:
- reading PSR2_SU_STATUS registers together(Dhinakaran)
- printing SU blocks of frames with 0 updates(Dhinakaran)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index aa9b54c89634..b15093d20e33 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2608,6 +2608,29 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
}
+ if (psr->psr2_enabled) {
+ u32 su_frames_val[3];
+ int frame;
+
+ /*
+* Reading all 3 registers before hand to minimize crossing a
+* frame boundary between register reads
+*/
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3)
+ su_frames_val[frame / 3] =
I915_READ(PSR2_SU_STATUS(frame));
+
+ seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
+
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
+ u32 su_blocks;
+
+ su_blocks = su_frames_val[frame / 3] &
+ PSR2_SU_STATUS_MASK(frame);
+ su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
+ seq_printf(m, "%d\t%d\n", frame, su_blocks);
+ }
+ }
+
unlock:
mutex_unlock(&psr->lock);
intel_runtime_pm_put(dev_priv, wakeref);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/4] drm/i915: Refactor PSR status debugfs
The old debugfs fields was not following a naming partern and it was
a bit confusing.
So it went from:
~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
Sink_Support: yes
PSR mode: PSR1
Enabled: yes
Busy frontbuffer bits: 0x000
Main link in standby mode: no
HW Enabled & Active bit: yes
Source PSR status: 0x24050006 [SRDONACK]
To:
~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
Sink support: yes [0x03]
PSR mode: PSR1 enabled
Source PSR ctl: enabled [0x81f00e26]
Source PSR status: IDLE [0x04010006]
Busy frontbuffer bits: 0x
The 'Main link in standby mode' was removed as it is not useful but
if needed by someone the information is still in the register value
of 'Source PSR ctl' inside of the brackets, PSR mode and Enabled was
squashed into PSR mode, some renames and reorders and we have this
cleaner version. This will also make easy to parse debugfs for IGT
tests.
v2: Printing sink PSR version with only 2 hex digits as it is a byte
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Suggested-by: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Acked-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 98 +++--
1 file changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 86152503331b..aa9b54c89634 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2506,7 +2506,8 @@ DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
{
- u32 val, psr_status;
+ u32 val, status_val;
+ const char *status = "unknown";
if (dev_priv->psr.psr2_enabled) {
static const char * const live_status[] = {
@@ -2522,14 +2523,11 @@ psr_source_status(struct drm_i915_private *dev_priv,
struct seq_file *m)
"BUF_ON",
"TG_ON"
};
- psr_status = I915_READ(EDP_PSR2_STATUS);
- val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
- EDP_PSR2_STATUS_STATE_SHIFT;
- if (val < ARRAY_SIZE(live_status)) {
- seq_printf(m, "Source PSR status: 0x%x [%s]\n",
- psr_status, live_status[val]);
- return;
- }
+ val = I915_READ(EDP_PSR2_STATUS);
+ status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
+ EDP_PSR2_STATUS_STATE_SHIFT;
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
} else {
static const char * const live_status[] = {
"IDLE",
@@ -2541,75 +2539,79 @@ psr_source_status(struct drm_i915_private *dev_priv,
struct seq_file *m)
"SRDOFFACK",
"SRDENT_ON",
};
- psr_status = I915_READ(EDP_PSR_STATUS);
- val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
- EDP_PSR_STATUS_STATE_SHIFT;
- if (val < ARRAY_SIZE(live_status)) {
- seq_printf(m, "Source PSR status: 0x%x [%s]\n",
- psr_status, live_status[val]);
- return;
- }
+ val = I915_READ(EDP_PSR_STATUS);
+ status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
+ EDP_PSR_STATUS_STATE_SHIFT;
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
}
- seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");
+ seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
}
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct i915_psr *psr = &dev_priv->psr;
intel_wakeref_t wakeref;
- u32 psrperf = 0;
- bool enabled = false;
- bool sink_support;
+ const char *status;
+ bool enabled;
+ u32 val;
if (!HAS_PSR(dev_priv))
return -ENODEV;
- sink_support = dev_priv->psr.sink_support;
- seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
- if (!sink_support)
+ seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
+ if (psr->dp)
+ seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]);
+ seq_puts(m, "\n");
+
+ if (!psr->sink_support)
return 0;
wakeref = intel_runtime_pm_get(dev_priv);
+ mutex_lock(&psr->lock);
- mutex_lock(&dev_priv->psr.lock);
- seq_printf(m, "PSR mode: %s\n",
- dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1");
- seq_printf(m, "Enabled: %s
[Intel-gfx] [PATCH v4 3/4] drm/i915: Add PSR2 selective update status registers and bits definitions
This register contains how many blocks was sent in the past selective
updates.
Those registers are not kept set all the times but polling it after flip
can show the values corresponding to the last 8 frames.
v2: Improved macros(Dhinakaran)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a1340cfda6c..a78789cc0e8f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4272,6 +4272,15 @@ enum {
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT28
+#define _PSR2_SU_STATUS_0 0x6F914
+#define _PSR2_SU_STATUS_1 0x6F918
+#define _PSR2_SU_STATUS_2 0x6F91C
+#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index),
_PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
+#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
+#define PSR2_SU_STATUS_SHIFT(frame)(((frame) % 3) * 10)
+#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
+#define PSR2_SU_STATUS_FRAMES 8
+
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA_MMIO(0xe1100)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
For now PSR2 is still disabled by default for all platforms but is
our intention to let debugfs to enable it for debug and tests
proporses, so intel_psr2_enabled() that is also used by debugfs to
decide if PSR2 is going to be enabled needs to take in consideration
the debug field.
v2: Using the switch/case that intel_psr2_enabled() already had to
handle this(DK)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8dbf26c212cc..84a0fb981561 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -70,17 +70,17 @@ static bool psr_global_enabled(u32 debug)
static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
- /* Disable PSR2 by default for all platforms */
- if (i915_modparams.enable_psr == -1)
- return false;
-
/* Cannot enable DSC and PSR2 simultaneously */
WARN_ON(crtc_state->dsc_params.compression_enable &&
crtc_state->has_psr2);
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
+ case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
+ case I915_PSR_DEBUG_DEFAULT:
+ if (i915_modparams.enable_psr <= 0)
+ return false;
default:
return crtc_state->has_psr2;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/debugfs: Print PSR selective update status register values
On Wed, 2019-01-16 at 14:37 -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2019-01-11 at 12:44 -0800, José Roberto de Souza wrote:
> > The value of this registers will be used to test if PSR2 is doing
> > selective update and if the number of blocks match with the
> > expected.
> >
> > v2:
> > - Using new macros
> > - Changed the string output
> >
> > v3:
> > - reading PSR2_SU_STATUS registers together(Dhinakaran)
> > - printing SU blocks of frames with 0 updates(Dhinakaran)
> >
> > Cc: Rodrigo Vivi
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index f8668cb05d64..5817ae0fb5f8 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2600,6 +2600,29 @@ static int i915_edp_psr_status(struct
> > seq_file
> > *m, void *data)
> > seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
> > }
> >
> > + if (psr->psr2_enabled) {
> > + u32 su_frames_val[3];
> > + u8 frame;
> 'int' seems like a more appropriate choice here. With that changed,
> Reviewed-by: Dhinakaran Pandiyan
Done and sending rebased version to mail list.
Thanks for the reviews.
>
> Also, patch 2/4 needs rebase.
>
> -DK
>
> > +
> > + /*
> > +* Reading all 3 registers before hand to minimize
> > crossing a
> > +* frame boundary between register reads
> > +*/
> > + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame +=
> > 3)
> > + su_frames_val[frame / 3] =
> > I915_READ(PSR2_SU_STATUS(frame));
> > +
> > + seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
> > +
> > + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++)
> > {
> > + u32 su_blocks;
> > +
> > + su_blocks = su_frames_val[frame / 3] &
> > + PSR2_SU_STATUS_MASK(frame);
> > + su_blocks = su_blocks >>
> > PSR2_SU_STATUS_SHIFT(frame);
> > + seq_printf(m, "%d\t%d\n", frame, su_blocks);
> > + }
> > + }
> > +
> > unlock:
> > mutex_unlock(&psr->lock);
> > intel_runtime_pm_put(dev_priv);
signature.asc
Description: This is a digitally signed message part
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [alsa-devel] Timing issues between ALSA and i915 drivers
I tried to narrow down the issue further and my current understanding is that the Skylake driver performs link reset operations without the display power turned on - which does not look like a very smart thing to do in hindsight. In other words, it's not really when snd_hdac_i915_init() is called that matters as I assumed initially, but more when snd_hdac_display_power() is invoked. There are two cases where this happens, and for each of them turning the display power on results in HDMI detection. The attached diffs split the initialization from the power on, which provides a better understanding of the issue. OK, this makes some sense, and that's the very reason we have HDA_CODEC_IDX_CONTROLLER for snd_hdac_display_power(). IIRC, we needed to power on the display for probing of the legacy HDA, too. Once after that, for the normal operation, the display power is needed only when you output the HDMI stream. What would be really useful at this point is a confirmation that snd_hdac_i915_init() cannot be called in the initial probe but does need to be executed in a work queue. That would really impact the way the initialization sequence is reworked on the Skylake side as well as modify the way the SOF driver deals with i915 initialization. It's needed to be called in a work queue, yes. Basically you shouldn't call request_module() in the driver's probe callback. When the probe callback is called from the module loading, it blocks the module loading itself, hence loading yet another module can't work. A situation might be easier than the past (which deadlocked), but still it's advised to use either the request_module_nowait() with the callback or call request_module() asynchronously from probe. Thanks Takashi, this is very useful. I guess that will require a complete rework of the Skylake initialization sequence then, my simple code translation isn't enough indeed and the current partition between probe/work queue can't comply with both requirements (request module asynchronously from probe, display turned on before mucking with links). We also need this changed for SOF, the i915_init is done in the probe. -Pierre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for icl: Misc PLL patches
== Series Details == Series: icl: Misc PLL patches URL : https://patchwork.freedesktop.org/series/55378/ State : warning == Summary == $ dim checkpatch origin/drm-tip bc90321eb832 drm/i915/icl: use tc_port in MG_PLL macros -:183: WARNING:LINE_SPACING: Missing a blank line after declarations #183: FILE: drivers/gpu/drm/i915/intel_display.c:9419: + enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + id = icl_tc_port_to_pll_id(tc_port); total: 0 errors, 1 warnings, 0 checks, 314 lines checked 6246a3763ba7 drm/i915: always return something 29f565fdc104 drm/i915/icl: remove dpll from clk_sel 27401a448f20 drm/i915/icl: keep track of unused pll while looping 12401b81e6c3 drm/i915: allow shared plls to be non-consecutive ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [alsa-devel] Timing issues between ALSA and i915 drivers
On Thu, 17 Jan 2019 20:53:06 +0100,
Pierre-Louis Bossart wrote:
>
>
> > I could use some feedback on HDMI audio issues exposed during the
> > 4.21 merge window. By accident (misleading documentation) we ended
> > up enabling the Skylake driver instead of the HDaudio legacy, and
> > broke audio on a number of Skylake and ApolloLake devices where the
> > HDMI/iDISP codec was not detected (bit 2 not set in the
> > codec_mask). Linus' Dell XPS13 9350 was the first to be impacted of
> > course...
> >
> > After debugging a bit, this issue can be resolved by either
> >
> > a) compiling both SOUND and DRM as built-ins (y instead of m)
> >
> > b) moving the calls snd_hdac_i915_init() to the probe function
> > instead of the worker queue (code at
> > https://github.com/plbossart/sound/commits/fix/skl-hdmi)
> >
> > Both solutions point to timing issues.
> >
> > During internal reviews I was alerted to the fact that the suggested
> > fix essentially reverts patch ab1b732d53c18 ('ASoC: Intel: Skylake:
> > Move i915 registration to worker thread') which was introduced to
> > solve DRM lockup issues.
>
> I tried to narrow down the issue further and my current understanding
> is that the Skylake driver performs link reset operations without the
> display power turned on - which does not look like a very smart thing
> to do in hindsight.
>
> In other words, it's not really when snd_hdac_i915_init() is called
> that matters as I assumed initially, but more when
> snd_hdac_display_power() is invoked. There are two cases where this
> happens, and for each of them turning the display power on results in
> HDMI detection. The attached diffs split the initialization from the
> power on, which provides a better understanding of the issue.
OK, this makes some sense, and that's the very reason we have
HDA_CODEC_IDX_CONTROLLER for snd_hdac_display_power(). IIRC, we
needed to power on the display for probing of the legacy HDA, too.
Once after that, for the normal operation, the display power is needed
only when you output the HDMI stream.
> What would be really useful at this point is a confirmation that
> snd_hdac_i915_init() cannot be called in the initial probe but does
> need to be executed in a work queue. That would really impact the way
> the initialization sequence is reworked on the Skylake side as well as
> modify the way the SOF driver deals with i915 initialization.
It's needed to be called in a work queue, yes.
Basically you shouldn't call request_module() in the driver's probe
callback. When the probe callback is called from the module loading,
it blocks the module loading itself, hence loading yet another module
can't work. A situation might be easier than the past (which
deadlocked), but still it's advised to use either the
request_module_nowait() with the callback or call request_module()
asynchronously from probe.
thanks,
Takashi
>
> Thanks
>
> -Pierre
>
> diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
> index 60c94836bf5b..56556d06a17f 100644
> --- a/sound/soc/intel/skylake/skl.c
> +++ b/sound/soc/intel/skylake/skl.c
> @@ -767,23 +767,6 @@ static const struct hdac_bus_ops bus_core_ops = {
> .get_response = snd_hdac_bus_get_response,
> };
>
> -static int skl_i915_init(struct hdac_bus *bus)
> -{
> - int err;
> -
> - /*
> - * The HDMI codec is in GPU so we need to ensure that it is powered
> - * up and ready for probe
> - */
> - err = snd_hdac_i915_init(bus);
> - if (err < 0)
> - return err;
> -
> - snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
> -
> - return 0;
> -}
> -
> static void skl_probe_work(struct work_struct *work)
> {
> struct skl *skl = container_of(work, struct skl, probe_work);
> @@ -791,12 +774,6 @@ static void skl_probe_work(struct work_struct *work)
> struct hdac_ext_link *hlink = NULL;
> int err;
>
> - if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
> - err = skl_i915_init(bus);
> - if (err < 0)
> - return;
> - }
> -
> err = skl_init_chip(bus, true);
> if (err < 0) {
> dev_err(bus->dev, "Init chip failed with err: %d\n", err);
> @@ -899,6 +876,11 @@ static int skl_first_init(struct hdac_bus *bus)
> unsigned short gcap;
> int cp_streams, pb_streams, start_idx;
>
> + err = snd_hdac_i915_init(bus);
> + if (err < 0)
> + return err;
> +
> +
> err = pci_request_regions(pci, "Skylake HD audio");
> if (err < 0)
> return err;
> @@ -910,7 +892,10 @@ static int skl_first_init(struct hdac_bus *bus)
> return -ENXIO;
> }
>
> - snd_hdac_bus_reset_link(bus, true);
> + /* this bus_reset_link is unnecessary, and without the display
> + * power turned on prevents HDMI from being detected
> + */
> + //snd_hdac_bus_reset_link(bus, true);
>
> snd_hdac_bus_parse_capabilities(bus);
>
> @@ -962,7 +
[Intel-gfx] [PATCH 5/5] drm/i915: allow shared plls to be non-consecutive
Right now when searching for shared plls we mandate that they have
consecutive IDs since we just pass the min and max id and loop over the
range. However the IDs can't be arbitrarily defined since they are used
as index to the MMIO address, hence dependent on what the hardware
implements.
This allows us to use PLLs that are not consecutive (although we don't
currently have any case) while clarifying the code paths in which only
one PLL is supposed to be used.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 41 ---
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8f70838ac7d8..103e42cfa2e3 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -243,8 +243,7 @@ void intel_disable_shared_dpll(const struct
intel_crtc_state *crtc_state)
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- enum intel_dpll_id range_min,
- enum intel_dpll_id range_max)
+ unsigned long pll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll, *unused_pll = NULL;
@@ -253,7 +252,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
shared_dpll =
intel_atomic_get_shared_dpll_state(crtc_state->base.state);
- for (i = range_min; i <= range_max; i++) {
+ for_each_set_bit(i, &pll_mask, I915_NUM_PLLS) {
pll = &dev_priv->shared_dplls[i];
/* Only want to check enabled timings first */
@@ -436,8 +435,8 @@ ibx_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
pll->info->name);
} else {
pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_PCH_PLL_A,
-DPLL_ID_PCH_PLL_B);
+GENMASK(DPLL_ID_PCH_PLL_B,
+DPLL_ID_PCH_PLL_A));
}
if (!pll)
@@ -780,7 +779,7 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int
clock,
crtc_state->dpll_hw_state.wrpll = val;
pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+GENMASK(DPLL_ID_WRPLL2, DPLL_ID_WRPLL1));
if (!pll)
return NULL;
@@ -840,7 +839,7 @@ hsw_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_SPLL, DPLL_ID_SPLL);
+BIT(DPLL_ID_SPLL));
} else {
return NULL;
}
@@ -1389,6 +1388,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
int clock = crtc_state->port_clock;
bool bret;
struct intel_dpll_hw_state dpll_hw_state;
+ unsigned long pll_mask;
memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
@@ -1410,13 +1410,11 @@ skl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
}
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL0);
+ pll_mask = BIT(DPLL_ID_SKL_DPLL0);
else
- pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_SKL_DPLL1,
-DPLL_ID_SKL_DPLL3);
+ pll_mask = GENMASK(DPLL_ID_SKL_DPLL3, DPLL_ID_SKL_DPLL1);
+
+ pll = intel_find_shared_dpll(crtc, crtc_state, pll_mask);
if (!pll)
return NULL;
@@ -2390,8 +2388,8 @@ cnl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
}
pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL2);
+GENMASK(DPLL_ID_SKL_DPLL2,
+DPLL_ID_SKL_DPLL0));
if (!pll) {
DRM_DEBUG_KMS("No PLL selected\n");
return NULL;
@@ -2899,13 +2897,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll;
struct intel_dpll_hw_state pll_state = {};
enum port port = encoder->port;
- enum intel_dpll_id min, max;
+
[Intel-gfx] [PATCH 3/5] drm/i915/icl: remove dpll from clk_sel
We should not pass DPLL_ID_ICL_DPLL0 or DPLL_ID_ICL_DPLL1 to this
function because the path is only taken for non-combophy ports. Let the
warning trigger if improper value is given.
While at it, rename the function to match the register name we are
trying to program.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4dc03e8c6c10..94d0fdc14b42 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -995,7 +995,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct
intel_shared_dpll *pll)
}
}
-static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
+static uint32_t icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -1004,10 +1004,11 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct
intel_encoder *encoder,
switch (id) {
default:
+ /*
+* DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be use
+* here, so do warn if this get passed in
+*/
MISSING_CASE(id);
- /* fall through */
- case DPLL_ID_ICL_DPLL0:
- case DPLL_ID_ICL_DPLL1:
return DDI_CLK_SEL_NONE;
case DPLL_ID_ICL_TBTPLL:
switch (clock) {
@@ -2869,7 +2870,7 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
if (IS_ICELAKE(dev_priv)) {
if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port),
- icl_pll_to_ddi_pll_sel(encoder, crtc_state));
+ icl_pll_to_ddi_clk_sel(encoder, crtc_state));
} else if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
--
2.20.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] icl: Misc PLL patches
Some PLL reworks on ICL. Patches are more or less independent of each other, but touch the same part of the code. Lucas De Marchi (5): drm/i915/icl: use tc_port in MG_PLL macros drm/i915: always return something drm/i915/icl: remove dpll from clk_sel drm/i915/icl: keep track of unused pll while looping drm/i915: allow shared plls to be non-consecutive drivers/gpu/drm/i915/i915_reg.h | 52 +- drivers/gpu/drm/i915/intel_ddi.c | 20 ++-- drivers/gpu/drm/i915/intel_display.c | 3 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 137 -- drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +- 5 files changed, 105 insertions(+), 109 deletions(-) -- 2.20.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/icl: keep track of unused pll while looping
Instead of looping again on the range of plls, just keep track of one
unused one and use it later.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 211b3ffa5bed..8f70838ac7d8 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -247,7 +247,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
enum intel_dpll_id range_max)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_shared_dpll *pll;
+ struct intel_shared_dpll *pll, *unused_pll = NULL;
struct intel_shared_dpll_state *shared_dpll;
enum intel_dpll_id i;
@@ -257,8 +257,10 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
pll = &dev_priv->shared_dplls[i];
/* Only want to check enabled timings first */
- if (shared_dpll[i].crtc_mask == 0)
+ if (shared_dpll[i].crtc_mask == 0) {
+ unused_pll = pll;
continue;
+ }
if (memcmp(&crtc_state->dpll_hw_state,
&shared_dpll[i].hw_state,
@@ -273,14 +275,11 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
}
/* Ok no matching timings, maybe there's a free one? */
- for (i = range_min; i <= range_max; i++) {
- pll = &dev_priv->shared_dplls[i];
- if (shared_dpll[i].crtc_mask == 0) {
- DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
- crtc->base.base.id, crtc->base.name,
- pll->info->name);
- return pll;
- }
+ if (unused_pll) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
+ crtc->base.base.id, crtc->base.name,
+ unused_pll->info->name);
+ return unused_pll;
}
return NULL;
--
2.20.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: always return something
Even if we don't have the correct clock and get a warning, we should not
skip the return.
Fixes: 1fa11ee2d9d0 ("drm/i915/icl: start adding the TBT pll")
Cc: Paulo Zanoni
Cc: # v4.19+
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8dbf6c9e22fb..4dc03e8c6c10 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1021,7 +1021,7 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct
intel_encoder *encoder,
return DDI_CLK_SEL_TBT_810;
default:
MISSING_CASE(clock);
- break;
+ return DDI_CLK_SEL_NONE;
}
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
--
2.20.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915/icl: use tc_port in MG_PLL macros
Fix the TODO leftover in the code by changing the argument in MG_PLL
macros. The MG_PLL ids used to access the register values can be
converted from tc_port rather than port.
The helper functions were also renamed to use "tc" as prefix to make
them more generic.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 52 +-
drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +--
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
5 files changed, 72 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a1340cfda6c..de209e0fdc01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9545,7 +9545,7 @@ enum skl_power_gate {
#define _MG_PLL3_ENABLE0x46038
#define _MG_PLL4_ENABLE0x4603C
/* Bits are the same as DPLL0_ENABLE */
-#define MG_PLL_ENABLE(port)_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
+#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
@@ -9554,9 +9554,9 @@ enum skl_power_gate {
#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
#define MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8)
-#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
-_MG_REFCLKIN_CTL_PORT1, \
-_MG_REFCLKIN_CTL_PORT2)
+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_REFCLKIN_CTL_PORT1, \
+ _MG_REFCLKIN_CTL_PORT2)
#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
@@ -9566,9 +9566,9 @@ enum skl_power_gate {
#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
-#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
- _MG_CLKTOP2_CORECLKCTL1_PORT1, \
- _MG_CLKTOP2_CORECLKCTL1_PORT2)
+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
+
_MG_CLKTOP2_CORECLKCTL1_PORT1, \
+
_MG_CLKTOP2_CORECLKCTL1_PORT2)
#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
@@ -9586,9 +9586,9 @@ enum skl_power_gate {
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT8
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
-#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
-_MG_CLKTOP2_HSCLKCTL_PORT1, \
-_MG_CLKTOP2_HSCLKCTL_PORT2)
+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
+ _MG_CLKTOP2_HSCLKCTL_PORT2)
#define _MG_PLL_DIV0_PORT1 0x168A00
#define _MG_PLL_DIV0_PORT2 0x169A00
@@ -9600,8 +9600,8 @@ enum skl_power_gate {
#define MG_PLL_DIV0_FBDIV_FRAC(x)((x) << 8)
#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
-#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
-_MG_PLL_DIV0_PORT2)
+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
+ _MG_PLL_DIV0_PORT2)
#define _MG_PLL_DIV1_PORT1 0x168A04
#define _MG_PLL_DIV1_PORT2 0x169A04
@@ -9615,8 +9615,8 @@ enum skl_power_gate {
#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
#define MG_PLL_DIV1_FBPREDIV_MASK(0xf << 0)
#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
-#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
-_MG_PLL_DIV1_PORT2)
+#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
+ _MG_PLL_DIV1_PORT2)
#define _MG_PLL_LF_PORT1 0x168A08
#define _MG_PLL_LF_PORT2 0x169A08
@@ -
Re: [Intel-gfx] [alsa-devel] Timing issues between ALSA and i915 drivers
I could use some feedback on HDMI audio issues exposed during the 4.21
merge window. By accident (misleading documentation) we ended up
enabling the Skylake driver instead of the HDaudio legacy, and broke
audio on a number of Skylake and ApolloLake devices where the
HDMI/iDISP codec was not detected (bit 2 not set in the codec_mask).
Linus' Dell XPS13 9350 was the first to be impacted of course...
After debugging a bit, this issue can be resolved by either
a) compiling both SOUND and DRM as built-ins (y instead of m)
b) moving the calls snd_hdac_i915_init() to the probe function instead
of the worker queue (code at
https://github.com/plbossart/sound/commits/fix/skl-hdmi)
Both solutions point to timing issues.
During internal reviews I was alerted to the fact that the suggested
fix essentially reverts patch ab1b732d53c18 ('ASoC: Intel: Skylake:
Move i915 registration to worker thread') which was introduced to
solve DRM lockup issues.
I tried to narrow down the issue further and my current understanding is
that the Skylake driver performs link reset operations without the
display power turned on - which does not look like a very smart thing to
do in hindsight.
In other words, it's not really when snd_hdac_i915_init() is called that
matters as I assumed initially, but more when snd_hdac_display_power()
is invoked. There are two cases where this happens, and for each of them
turning the display power on results in HDMI detection. The attached
diffs split the initialization from the power on, which provides a
better understanding of the issue.
What would be really useful at this point is a confirmation that
snd_hdac_i915_init() cannot be called in the initial probe but does need
to be executed in a work queue. That would really impact the way the
initialization sequence is reworked on the Skylake side as well as
modify the way the SOF driver deals with i915 initialization.
Thanks
-Pierre
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index 60c94836bf5b..56556d06a17f 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -767,23 +767,6 @@ static const struct hdac_bus_ops bus_core_ops = {
.get_response = snd_hdac_bus_get_response,
};
-static int skl_i915_init(struct hdac_bus *bus)
-{
- int err;
-
- /*
- * The HDMI codec is in GPU so we need to ensure that it is powered
- * up and ready for probe
- */
- err = snd_hdac_i915_init(bus);
- if (err < 0)
- return err;
-
- snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
-
- return 0;
-}
-
static void skl_probe_work(struct work_struct *work)
{
struct skl *skl = container_of(work, struct skl, probe_work);
@@ -791,12 +774,6 @@ static void skl_probe_work(struct work_struct *work)
struct hdac_ext_link *hlink = NULL;
int err;
- if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
- err = skl_i915_init(bus);
- if (err < 0)
- return;
- }
-
err = skl_init_chip(bus, true);
if (err < 0) {
dev_err(bus->dev, "Init chip failed with err: %d\n", err);
@@ -899,6 +876,11 @@ static int skl_first_init(struct hdac_bus *bus)
unsigned short gcap;
int cp_streams, pb_streams, start_idx;
+ err = snd_hdac_i915_init(bus);
+ if (err < 0)
+ return err;
+
+
err = pci_request_regions(pci, "Skylake HD audio");
if (err < 0)
return err;
@@ -910,7 +892,10 @@ static int skl_first_init(struct hdac_bus *bus)
return -ENXIO;
}
- snd_hdac_bus_reset_link(bus, true);
+ /* this bus_reset_link is unnecessary, and without the display
+ * power turned on prevents HDMI from being detected
+ */
+ //snd_hdac_bus_reset_link(bus, true);
snd_hdac_bus_parse_capabilities(bus);
@@ -962,7 +947,14 @@ static int skl_first_init(struct hdac_bus *bus)
/* initialize chip */
skl_init_pci(skl);
- return skl_init_chip(bus, true);
+ /* turning the display power here works */
+ snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
+
+ err = skl_init_chip(bus, true);
+
+ /* turning the display power here does not work, HDMI not detected */
+
+ return err;
}
static int skl_probe(struct pci_dev *pci,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
On Thu, Jan 17, 2019 at 11:13:58AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:23PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Planes scanning out C8 will want to use the legacy lut as
> > their palette. That means the LUT content are unikely to
> > be useful for gamma correction on other planes. Thus we
> > should disable pipe gamma for all the other planes. And
> > we should reject any non legacy LUT configurations when
> > C8 planes are present.
> >
> > Fixes the appearance of the hw cursor when running
> > X -depth 8.
> >
> > Note that CHV with it's independent CGM degamma/gamma LUTs
> > could probably use the CGM for gamma correction even when
> > the legacy LUT is used for C8. But that would require a
> > new uapi for configuring the legacy LUT and CGM LUTs at
> > the same time. Totally not worth it.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +
> > drivers/gpu/drm/i915/intel_color.c| 8 +++-
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 3 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index 50be2c5dd76e..f311763867c4 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct
> > intel_crtc_state *old_crtc_
> >
> > new_crtc_state->active_planes &= ~BIT(plane->id);
> > new_crtc_state->nv12_planes &= ~BIT(plane->id);
> > + new_crtc_state->c8_planes &= ~BIT(plane->id);
> > new_plane_state->base.visible = false;
> >
> > if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> > @@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct
> > intel_crtc_state *old_crtc_
> > new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> > new_crtc_state->nv12_planes |= BIT(plane->id);
> >
> > + if (new_plane_state->base.visible &&
> > + new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
> > + new_crtc_state->c8_planes |= BIT(plane->id);
> > +
> > if (new_plane_state->base.visible || old_plane_state->base.visible)
> > new_crtc_state->update_planes |= BIT(plane->id);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index 789b04bb51d2..c8d12653d77f 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >
> > - crtc_state->gamma_enable = gamma_lut || degamma_lut;
> > + /* C8 needs the legacy LUT all to itself */
> > + if (crtc_state->c8_planes &&
> > + !crtc_state_is_legacy_gamma(crtc_state))
> > + return -EINVAL;
> > +
> > + crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > + !crtc_state->c8_planes;
>
> It's not really clear to me from the bspec...the legacy gamma will still
> get used as the c8 palette even when the pipe gamma enable bit is off
> for the plane?
Yes. At least it did on all the platforms I tried, which IIRC
were quite a few.
> If so,
>
> Reviewed-by: Matt Roper
>
> >
> > if (INTEL_GEN(dev_priv) >= 9 ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index a4496f799af3..4d9ea05a6825 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -930,6 +930,7 @@ struct intel_crtc_state {
> > /* bitmask of visible planes (enum plane_id) */
> > u8 active_planes;
> > u8 nv12_planes;
> > + u8 c8_planes;
> >
> > /* bitmask of planes that will be updated during the commit */
> > u8 update_planes;
> > --
> > 2.19.2
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
On Fri, Jan 11, 2019 at 07:08:23PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Planes scanning out C8 will want to use the legacy lut as
> their palette. That means the LUT content are unikely to
> be useful for gamma correction on other planes. Thus we
> should disable pipe gamma for all the other planes. And
> we should reject any non legacy LUT configurations when
> C8 planes are present.
>
> Fixes the appearance of the hw cursor when running
> X -depth 8.
>
> Note that CHV with it's independent CGM degamma/gamma LUTs
> could probably use the CGM for gamma correction even when
> the legacy LUT is used for C8. But that would require a
> new uapi for configuring the legacy LUT and CGM LUTs at
> the same time. Totally not worth it.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +
> drivers/gpu/drm/i915/intel_color.c| 8 +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 50be2c5dd76e..f311763867c4 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
>
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> + new_crtc_state->c8_planes &= ~BIT(plane->id);
> new_plane_state->base.visible = false;
>
> if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> @@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> new_crtc_state->nv12_planes |= BIT(plane->id);
>
> + if (new_plane_state->base.visible &&
> + new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
> + new_crtc_state->c8_planes |= BIT(plane->id);
> +
> if (new_plane_state->base.visible || old_plane_state->base.visible)
> new_crtc_state->update_planes |= BIT(plane->id);
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 789b04bb51d2..c8d12653d77f 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state
> *crtc_state)
> degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
> - crtc_state->gamma_enable = gamma_lut || degamma_lut;
> + /* C8 needs the legacy LUT all to itself */
> + if (crtc_state->c8_planes &&
> + !crtc_state_is_legacy_gamma(crtc_state))
> + return -EINVAL;
> +
> + crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> + !crtc_state->c8_planes;
It's not really clear to me from the bspec...the legacy gamma will still
get used as the c8 palette even when the pipe gamma enable bit is off
for the plane? If so,
Reviewed-by: Matt Roper
>
> if (INTEL_GEN(dev_priv) >= 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a4496f799af3..4d9ea05a6825 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -930,6 +930,7 @@ struct intel_crtc_state {
> /* bitmask of visible planes (enum plane_id) */
> u8 active_planes;
> u8 nv12_planes;
> + u8 c8_planes;
>
> /* bitmask of planes that will be updated during the commit */
> u8 update_planes;
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
On Fri, Jan 11, 2019 at 07:08:22PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> As with pipe gamma we can avoid the potential precision loss from
> the pipe csc unit when there is no need to use it. And again
> we need the same logic for updating the planes.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_color.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index a8b7428a64bf..789b04bb51d2 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -659,7 +659,8 @@ intel_color_add_affected_planes(struct intel_crtc_state
> *new_crtc_state)
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_plane *plane;
>
> - if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> + if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> + new_crtc_state->csc_enable == old_crtc_state->csc_enable)
> return 0;
>
> for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> @@ -684,6 +685,7 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> const struct drm_property_blob *degamma_lut =
> crtc_state->base.degamma_lut;
> size_t gamma_length, degamma_length;
> + bool limited_color_range = false;
> int ret;
>
> degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -693,7 +695,11 @@ int intel_color_check(struct intel_crtc_state
> *crtc_state)
>
> if (INTEL_GEN(dev_priv) >= 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> - crtc_state->csc_enable = true;
> + limited_color_range = crtc_state->limited_color_range;
> +
> + crtc_state->csc_enable =
> + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> + crtc_state->base.ctm || limited_color_range;
>
> ret = intel_color_add_affected_planes(crtc_state);
> if (ret)
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
On Thu, Jan 17, 2019 at 10:40:23AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:21PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The pipe internal precision is higher than what we currently program to
> > the degamma/gamma LUTs. We can get a higher quality image by bypassing
> > the LUTs when they're not needed. Let's do that.
> >
> > Each plane has its own control bit for this, so we have to update
> > all active planes. The way we've done this we don't actually have
> > to run through the whole .check_plane() thing. And we actually
> > do the .color_check() after .check_plane() so we couldn't even do
> > that without shuffling the code around.
> >
> > Additionally on pre-skl we have to update the primary plane regardless
> > of whether it's active or not on account of the primayr plane gamma
>
> s/primayr/primary/
>
> > enable bit also affecting the pipe bottom color.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_color.c | 55 --
> > 1 file changed, 53 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index 8d7ea902a34b..a8b7428a64bf 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state
> > *crtc_state)
> > dev_priv->display.color_commit(crtc_state);
> > }
> >
> > +static bool need_plane_update(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
> > + /*
> > +* On pre-SKL the pipe gamma enable and pipe csc enable for
> > +* the pipe bottom color are configured via the primary plane.
> > +* We have to reconfigure that even if the plane is inactive.
> > +*/
> > + return crtc_state->active_planes & BIT(plane->id) ||
> > + (INTEL_GEN(dev_priv) < 9 &&
> > +plane->id == PLANE_PRIMARY);
> > +}
> > +
> > +static int
> > +intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + struct intel_atomic_state *state =
> > + to_intel_atomic_state(new_crtc_state->base.state);
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> > + struct intel_plane *plane;
> > +
> > + if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> > + return 0;
> > +
> > + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> > + struct intel_plane_state *plane_state;
> > +
> > + if (!need_plane_update(plane, new_crtc_state))
> > + continue;
> > +
> > + plane_state = intel_atomic_get_plane_state(state, plane);
> > + if (IS_ERR(plane_state))
> > + return PTR_ERR(plane_state);
> > +
> > + new_crtc_state->update_planes |= BIT(plane->id);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > int intel_color_check(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > size_t gamma_length, degamma_length;
> > + int ret;
> >
> > degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >
> > - crtc_state->gamma_enable = true;
> > + crtc_state->gamma_enable = gamma_lut || degamma_lut;
> >
> > if (INTEL_GEN(dev_priv) >= 9 ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > crtc_state->csc_enable = true;
> >
> > + ret = intel_color_add_affected_planes(crtc_state);
> > + if (ret)
> > + return ret;
> > +
> > /*
> > * We also allow no degamma lut/ctm and a gamma lut at the legacy
> > * size (256 entries).
> > */
> > - if (crtc_state_is_legacy_gamma(crtc_state)) {
> > + if (!crtc_state->gamma_enable ||
> > + crtc_state_is_legacy_gamma(crtc_state)) {
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>
> If none of our planes are actually using the gamma, what does switching
> back to 8bit mode do for us?
Hopefilly nothing. Just a matter of selecting something for
consistency.
>
> Regardless,
>
> Reviewed-by: Matt Roper
>
>
> > return 0;
> > }
> > --
> > 2.19.2
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
___
Intel-gfx mailin
Re: [Intel-gfx] [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
On Fri, Jan 11, 2019 at 07:08:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The pipe internal precision is higher than what we currently program to
> the degamma/gamma LUTs. We can get a higher quality image by bypassing
> the LUTs when they're not needed. Let's do that.
>
> Each plane has its own control bit for this, so we have to update
> all active planes. The way we've done this we don't actually have
> to run through the whole .check_plane() thing. And we actually
> do the .color_check() after .check_plane() so we couldn't even do
> that without shuffling the code around.
>
> Additionally on pre-skl we have to update the primary plane regardless
> of whether it's active or not on account of the primayr plane gamma
s/primayr/primary/
> enable bit also affecting the pipe bottom color.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_color.c | 55 --
> 1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 8d7ea902a34b..a8b7428a64bf 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state
> *crtc_state)
> dev_priv->display.color_commit(crtc_state);
> }
>
> +static bool need_plane_update(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> + /*
> + * On pre-SKL the pipe gamma enable and pipe csc enable for
> + * the pipe bottom color are configured via the primary plane.
> + * We have to reconfigure that even if the plane is inactive.
> + */
> + return crtc_state->active_planes & BIT(plane->id) ||
> + (INTEL_GEN(dev_priv) < 9 &&
> + plane->id == PLANE_PRIMARY);
> +}
> +
> +static int
> +intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(new_crtc_state->base.state);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + struct intel_plane *plane;
> +
> + if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> + return 0;
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + struct intel_plane_state *plane_state;
> +
> + if (!need_plane_update(plane, new_crtc_state))
> + continue;
> +
> + plane_state = intel_atomic_get_plane_state(state, plane);
> + if (IS_ERR(plane_state))
> + return PTR_ERR(plane_state);
> +
> + new_crtc_state->update_planes |= BIT(plane->id);
> + }
> +
> + return 0;
> +}
> +
> int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> const struct drm_property_blob *degamma_lut =
> crtc_state->base.degamma_lut;
> size_t gamma_length, degamma_length;
> + int ret;
>
> degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
> - crtc_state->gamma_enable = true;
> + crtc_state->gamma_enable = gamma_lut || degamma_lut;
>
> if (INTEL_GEN(dev_priv) >= 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> crtc_state->csc_enable = true;
>
> + ret = intel_color_add_affected_planes(crtc_state);
> + if (ret)
> + return ret;
> +
> /*
>* We also allow no degamma lut/ctm and a gamma lut at the legacy
>* size (256 entries).
>*/
> - if (crtc_state_is_legacy_gamma(crtc_state)) {
> + if (!crtc_state->gamma_enable ||
> + crtc_state_is_legacy_gamma(crtc_state)) {
> crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
If none of our planes are actually using the gamma, what does switching
back to 8bit mode do for us?
Regardless,
Reviewed-by: Matt Roper
> return 0;
> }
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Disable global reset
On 01/17/2019 06:24 AM, Mika Kuoppala wrote:
Chris Wilson writes:
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here is verboten (as we must be able to reset from underneath any
of our mutexes). That makes recovering the guc unviable without, for
example, reserving contiguous vma space and pages for it to use.
Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
We do want ack from Daniele as well.
As long as no one opposes the temporary arrangement we discussed to
re-enable the reset with guc (perma-pinning the firmware in the GuC
unaccessible range of the GGTT),
Acked-by: Daniele Ceraolo Spurio
Daniele
-Mika
---
drivers/gpu/drm/i915/i915_reset.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index f9512e07646d..c9a844d2626f 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -590,6 +590,9 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned
int engine_mask)
bool intel_has_gpu_reset(struct drm_i915_private *i915)
{
+ if (USES_GUC(i915))
+ return false;
+
return intel_get_gpu_reset(i915);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support
On Wed, Jan 16, 2019 at 03:43:20PM -0800, José Roberto de Souza wrote:
> If the sink and source supports HBR3, TP4 should be used as link
> training pattern.
> For PSR2 there is no register to set and enable TP4 but according to
> eDP spec TP3 is still a training pattern acceptable for HBR3 panels.
>
The spec refers to training pattern 4 as TPS4, 3 as TPS3 etc so its better
to stick with the same abbreviations in this patch commit message and comments
as well since the spec uses TP2/TP3 etc for test point 2/3.
> Cc: Manasi Navare
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
>
> Still trying to understand how PSR1 was working on ICL while sending
> TP4 to a panel that only supports HBR2.
>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp_link_training.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 24 ++-
> 4 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5faca634ee70..1e792309a79e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4162,6 +4162,7 @@ enum {
> #define EDP_PSR_TP1_TP3_SEL(1 << 11)
> #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
> #define EDP_PSR_TP2_TP3_TIME_SHIFT (8)
> +#define EDP_PSR_TP4_TIME_SHIFT (6) /* ICL+ */
> #define EDP_PSR_TP1_TIME_SHIFT (4)
> #define EDP_PSR_IDLE_FRAME_SHIFT 0
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 30be0e39bd5f..3e9798a5498c 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -238,7 +238,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp)
> * or for 1.4 devices that support it, training Pattern 3 for HBR2
> * or 1.2 devices that support it, Training Pattern 2 otherwise.
> */
> -static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> +u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> {
> bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e5a436c33307..fc3e6ae92276 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1807,6 +1807,7 @@ int intel_dp_get_link_train_fallback_values(struct
> intel_dp *intel_dp,
> int link_rate, uint8_t lane_count);
> void intel_dp_start_link_train(struct intel_dp *intel_dp);
> void intel_dp_stop_link_train(struct intel_dp *intel_dp);
> +u32 intel_dp_training_pattern(struct intel_dp *intel_dp);
> int intel_dp_retrain_link(struct intel_encoder *encoder,
> struct drm_modeset_acquire_ctx *ctx);
> void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2fc537fb6e78..b0525940e5e9 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -440,6 +440,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 max_sleep_time = 0x1f;
> u32 val = EDP_PSR_ENABLE;
> + u32 tp;
I would prefer calling this tps like the intel_dp_training_pattern function
calls it source_tps sink_tps.
Apart from that looks good. So with these changes
Reviewed-by: Manasi Navare
Manasi
>
> /* Let's use 6 as the minimum to cover all known cases including the
>* off-by-one issue that HW has in some cases.
> @@ -460,13 +461,24 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> val |= EDP_PSR_LINK_STANDBY;
>
> val |= dev_priv->vbt.psr.tp1_wakeup_time << EDP_PSR_TP1_TIME_SHIFT;
> - val |= dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time <<
> EDP_PSR_TP2_TP3_TIME_SHIFT;
>
> - if (intel_dp_source_supports_hbr2(intel_dp) &&
> - drm_dp_tps3_supported(intel_dp->dpcd))
> - val |= EDP_PSR_TP1_TP3_SEL;
> - else
> - val |= EDP_PSR_TP1_TP2_SEL;
> + tp = intel_dp_training_pattern(intel_dp);
> + if (tp == DP_TRAINING_PATTERN_4) {
> + /*
> + * TP4 is selected by setting EDP_PSR_TP4_TIME with other value
> + * than PSR_TP_WAKEUP_TIME_NONE
> + */
> + val |= dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time <<
> EDP_PSR_TP4_TIME_SHIFT;
> + } else {
> + if (INTEL_GEN(dev_priv) >= 11)
> + val |= PSR_TP_WAKEUP_TIME_NONE <<
> EDP_PSR_TP4_TIME_SHIFT;
> +
> + val |= dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time <<
> EDP_PSR_TP2_TP3_TIME_SHIFT;
> + if (tp == DP_TRAINI
Re: [Intel-gfx] [PATCH 09/23] drm/i915: Use b->irq_enable() as predicate for mock engine
On 17/01/2019 16:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-01-17 16:44:54)
On 17/01/2019 14:34, Chris Wilson wrote:
Since commit d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
we have required a mechanism to avoid touching the interrupt hardware
for breadcrumbs, superseding our mock interface for selftests.
References: d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 39
drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 -
4 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ed7105d7ff5..7b517bf83507 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -158,6 +158,9 @@ static void intel_breadcrumbs_fake_irq(struct timer_list *t)
static void irq_enable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_enable)
+ return;
+
/*
* FIXME: Ideally we want this on the API boundary, but for the
* sake of testing with mock breadcrumbs (no HW so unable to
Okay I think I misunderstood this patch in the last round. So you want
to avoid the GEM_BUG_ON below _and_ a dedicated boolean only for the
mock engine.
I only wonder on the remaining merit of this comment and actually a
GEM_BUG_ON, which will be hit and miss depending on the platform now.
Gut feeling says something is still not ideal here. Selftests variable
does actually feel better in this sense.
mock_engine seems only used from mock_gem_device, so could an
alternative be to set i915->runtime_pm.irqs_enabled there and keep the
GEM_BUG_ON in irq_enable above the !engine->irq_enable early return?
That would still provide the unconditional assert on the state of the
driver outside selftests.
I'm just going to kill the mention of irqs enabled here, eventually. It
was interesting once because we messed up suspend a decade ago and had to
handle the case of waiting after we had already uninstalled the irq
handler.
This is nothing to do with irqs_enabled; the selftest variable was all
because the mock engine had no engine->irq_enable() callback, and now it
is not the only engine so the assumption that we must always have
engine->irq_enable() is invalid.
Okay, my complaint was minimal anyway:
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/23] drm/i915: Move list of timelines under its own lock
On 17/01/2019 14:34, Chris Wilson wrote:
Currently, the list of timelines is serialised by the struct_mutex, but
to alleviate difficulties with using that mutex in future, move the
list management under its own dedicated mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem.c | 89 +--
drivers/gpu/drm/i915/i915_reset.c | 8 +-
drivers/gpu/drm/i915/i915_timeline.c | 38 ++--
drivers/gpu/drm/i915/i915_timeline.h | 3 +
drivers/gpu/drm/i915/i915_vma.c | 6 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 7 +-
.../gpu/drm/i915/selftests/mock_timeline.c| 3 +-
8 files changed, 101 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 94680b15bed0..3913900600b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1975,7 +1975,10 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
- struct list_head timelines;
+ struct i915_gt_timelines {
+ struct mutex mutex; /* protects list, tainted by GPU */
What does it mean "tainted by GPU"?
+ struct list_head list;
+ } timelines;
struct list_head active_rings;
struct list_head closed_vma;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 15acd052da46..3c6091021290 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3222,33 +3222,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
}
-static long wait_for_timeline(struct i915_timeline *tl,
- unsigned int flags, long timeout)
-{
- struct i915_request *rq;
-
- rq = i915_gem_active_get_unlocked(&tl->last_request);
- if (!rq)
- return timeout;
-
- /*
-* "Race-to-idle".
-*
-* Switching to the kernel context is often used a synchronous
-* step prior to idling, e.g. in suspend for flushing all
-* current operations to memory before sleeping. These we
-* want to complete as quickly as possible to avoid prolonged
-* stalls, so allow the gpu to boost to maximum clocks.
-*/
- if (flags & I915_WAIT_FOR_IDLE_BOOST)
- gen6_rps_boost(rq, NULL);
-
- timeout = i915_request_wait(rq, flags, timeout);
- i915_request_put(rq);
-
- return timeout;
-}
-
static int wait_for_engines(struct drm_i915_private *i915)
{
if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
@@ -3265,6 +3238,8 @@ static int wait_for_engines(struct drm_i915_private *i915)
int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
+ struct i915_timeline *tl;
+
GEM_TRACE("flags=%x (%s), timeout=%ld%s\n",
flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked",
timeout, timeout == MAX_SCHEDULE_TIMEOUT ? " (forever)" : "");
@@ -3273,17 +3248,45 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915,
if (!READ_ONCE(i915->gt.awake))
return 0;
+ mutex_lock(&i915->gt.timelines.mutex);
+ list_for_each_entry(tl, &i915->gt.timelines.list, link) {
+ struct i915_request *rq;
+
+ rq = i915_gem_active_get_unlocked(&tl->last_request);
+ if (!rq)
+ continue;
+
+ mutex_unlock(&i915->gt.timelines.mutex);
+
+ /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+ if (flags & I915_WAIT_FOR_IDLE_BOOST)
+ gen6_rps_boost(rq, NULL);
+
+ timeout = i915_request_wait(rq, flags, timeout);
+ i915_request_put(rq);
+ if (timeout < 0)
+ return timeout;
+
+ mutex_lock(&i915->gt.timelines.mutex);
+
+ /* restart after dropping the lock */
+ tl = list_entry(&i915->gt.timelines.list, typeof(*tl), link);
+ }
+ mutex_unlock(&i915->gt.timelines.mutex);
Hm, since the loop above bothers restarting after dropping the lock,
that implies when we drop the lock here we may not be idle any longer.
Or we actually still depend on struct
Re: [Intel-gfx] [PATCH] drm: Split out drm_probe_helper.h
On Thu, Jan 17, 2019 at 05:45:41PM +0100, Daniel Vetter wrote: > On Wed, Jan 16, 2019 at 07:10:18PM +0100, Sam Ravnborg wrote: > > Hi Daniel. > > > > > v5: Actually try to sort them, and while at it, sort all the ones I > > > touch. > > > > Applied this variant on top of drm-misc and did a build test. > > Looked good for ia64, x86 and alpha. > > > > Took a closer look at the changes to atmel_hlcd - and they looked OK. > > > > But I noticed that atmel_hlcdc uses only drm_kms_helper_poll_init() and > > drm_kms_helper_poll_fini(). > > But there are no hits on DRM_CONNECTOR_POLL - so I think we maybe > > have a driver here where we have plugged the drm_poll infrastructure, > > but it is not in use. > > > > > include/drm/drm_crtc_helper.h | 16 --- > > > > The list of include files in this file could be dropped and replaced by: > > struct drm_connector; > > struct drm_device; > > struct drm_display_mode; > > struct drm_encoder; > > struct drm_framebuffer; > > struct drm_mode_set; > > struct drm_modeset_acquire_ctx; > > > > I tried to do so on top of your patch. > > But there were too many build errros and I somehow lost the motivation. > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy > kms drivers. Just removing it from all the atomic drivers caused lots of > fallout, I expect even more if you entirely remove the includes it has. > Maybe a todo, care to pls create that patch since it's your idea? The main reason I bailed out initially was that this would create small changes to several otherwise seldomly touched files. And then we would later come and remove drmP.h - so lots of small but incremental changes to the same otherwise seldomly edited files. And the job was only partially done. I will try to experiment with an approach where I clean up the include/drm/*.h files a little (like suggested above, +delete drmP.h and maybe a bit more). Then to try on a driver by driver basis to make it build with a cleaned set of include files. I hope that the cleaned up driver can still build without the cleaned header files so the changes can be submitted piecemal. Will do so with an eye on the lesser maintained drivers to try it out to avoid creating too much chrunch for others. And if it works out I expect the active drivers to follow the example. todo.rst item will wait until I run out of energy. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/23] drm/i915/selftests: Make evict tolerant of foreign objects
On 17/01/2019 14:34, Chris Wilson wrote:
The evict selftests presumed that all objects in use had been allocated
by itself. This is a dubious claim and so instead of asserting complete
control over the object lists, take (temporary) ownership of them
instead.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_evict.c | 64 +++
1 file changed, 53 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index fb7df895afeb..c8deb961a020 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -31,30 +31,63 @@
static int populate_ggtt(struct drm_i915_private *i915)
{
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj, *on;
+ unsigned long expected_unbound, expected_bound;
+ unsigned long unbound, bound, count;
Minor/optional comment - longs seem like overkill for either filling
ggtt with page size objects or for initial state. :)
u64 size;
+ int err;
+
+ expected_unbound = 0;
+ list_for_each_entry(obj, &i915->mm.unbound_list, mm.link) {
+ i915_gem_object_get(obj);
+ expected_unbound++;
+ }
+
+ expected_bound = 0;
+ list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
+ i915_gem_object_get(obj);
+ expected_bound++;
+ }
+ count = 0;
for (size = 0;
size + I915_GTT_PAGE_SIZE <= i915->ggtt.vm.total;
size += I915_GTT_PAGE_SIZE) {
struct i915_vma *vma;
obj = i915_gem_object_create_internal(i915, I915_GTT_PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto cleanup;
+ }
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto cleanup;
+ }
+
+ count++;
}
- if (!list_empty(&i915->mm.unbound_list)) {
- size = 0;
- list_for_each_entry(obj, &i915->mm.unbound_list, mm.link)
- size++;
+ unbound = 0;
+ list_for_each_entry(obj, &i915->mm.unbound_list, mm.link)
+ unbound++;
+ if (unbound != expected_unbound) {
+ pr_err("%s: Found %lu objects unbound, expected %lu!\n",
+ __func__, unbound, expected_unbound);
+ err = -EINVAL;
+ goto cleanup;
+ }
- pr_err("Found %lld objects unbound!\n", size);
- return -EINVAL;
+ bound = 0;
+ list_for_each_entry(obj, &i915->mm.bound_list, mm.link)
+ bound++;
+ if (bound != expected_bound + count) {
+ pr_err("%s: Found %lu objects bound, expected %lu!\n",
+ __func__, bound, expected_bound + count);
+ err = -EINVAL;
+ goto cleanup;
}
if (list_empty(&i915->ggtt.vm.bound_list)) {
@@ -63,6 +96,15 @@ static int populate_ggtt(struct drm_i915_private *i915)
}
return 0;
+
+cleanup:
+ list_for_each_entry_safe(obj, on, &i915->mm.unbound_list, mm.link)
+ i915_gem_object_put(obj);
+
+ list_for_each_entry_safe(obj, on, &i915->mm.bound_list, mm.link)
+ i915_gem_object_put(obj);
+
+ return err;
}
static void unpin_ggtt(struct drm_i915_private *i915)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user
== Series Details ==
Series: drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user
URL : https://patchwork.freedesktop.org/series/55366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5440 -> Patchwork_11971
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55366/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11971 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: NOTRUN -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: NOTRUN -> DMESG-FAIL [fdo#105079]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
* igt@pm_rpm@module-reload:
- fi-kbl-7567u: NOTRUN -> DMESG-WARN [fdo#108529]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (45 -> 43)
--
Additional (3): fi-kbl-7567u fi-glk-j4005 fi-byt-clapper
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-pnv-d510
Build changes
-
* Linux: CI_DRM_5440 -> Patchwork_11971
CI_DRM_5440: b36a89b5ab74fd49a4369e6df0d2c02bc464a474 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11971: c42d476cf09ca69bc81c10839b86460cda833b4f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c42d476cf09c drm/i915: Fix wakeref cookie handling in
debugfs/i915_forcewake_user
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11971/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/23] drm/i915: Use b->irq_enable() as predicate for mock engine
Quoting Tvrtko Ursulin (2019-01-17 16:44:54)
>
> On 17/01/2019 14:34, Chris Wilson wrote:
> > Since commit d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
> > we have required a mechanism to avoid touching the interrupt hardware
> > for breadcrumbs, superseding our mock interface for selftests.
> >
> > References: d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/intel_breadcrumbs.c | 39
> > drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
> > drivers/gpu/drm/i915/selftests/mock_engine.c | 1 -
> > 4 files changed, 20 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> > b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> > index 4ed7105d7ff5..7b517bf83507 100644
> > --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> > +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> > @@ -158,6 +158,9 @@ static void intel_breadcrumbs_fake_irq(struct
> > timer_list *t)
> >
> > static void irq_enable(struct intel_engine_cs *engine)
> > {
> > + if (!engine->irq_enable)
> > + return;
> > +
> > /*
> >* FIXME: Ideally we want this on the API boundary, but for the
> >* sake of testing with mock breadcrumbs (no HW so unable to
>
> Okay I think I misunderstood this patch in the last round. So you want
> to avoid the GEM_BUG_ON below _and_ a dedicated boolean only for the
> mock engine.
>
> I only wonder on the remaining merit of this comment and actually a
> GEM_BUG_ON, which will be hit and miss depending on the platform now.
> Gut feeling says something is still not ideal here. Selftests variable
> does actually feel better in this sense.
>
> mock_engine seems only used from mock_gem_device, so could an
> alternative be to set i915->runtime_pm.irqs_enabled there and keep the
> GEM_BUG_ON in irq_enable above the !engine->irq_enable early return?
> That would still provide the unconditional assert on the state of the
> driver outside selftests.
I'm just going to kill the mention of irqs enabled here, eventually. It
was interesting once because we messed up suspend a decade ago and had to
handle the case of waiting after we had already uninstalled the irq
handler.
This is nothing to do with irqs_enabled; the selftest variable was all
because the mock engine had no engine->irq_enable() callback, and now it
is not the only engine so the assumption that we must always have
engine->irq_enable() is invalid.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
On 17/01/2019 16:36, Chris Wilson wrote: Quoting Chris Wilson (2019-01-17 16:31:27) Quoting Tvrtko Ursulin (2019-01-17 16:27:04) On 17/01/2019 14:34, Chris Wilson wrote: Remove the struct_mutex requirement for looking up the vma for an object. Another patch with missing change log. There was no functional change. I see that you at least fixed the tree typo since the round I last reviewed. But I also had some other questions which I did not see you commented on. I answer those questions. in 154644420773.27300.5770992084643848631@skylake-alporthouse-com ? Hm.. no hits for me anywhere. Can you see it in the archives? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Split out drm_probe_helper.h
On Wed, Jan 16, 2019 at 07:10:18PM +0100, Sam Ravnborg wrote: > Hi Daniel. > > > v5: Actually try to sort them, and while at it, sort all the ones I > > touch. > > Applied this variant on top of drm-misc and did a build test. > Looked good for ia64, x86 and alpha. > > Took a closer look at the changes to atmel_hlcd - and they looked OK. > > But I noticed that atmel_hlcdc uses only drm_kms_helper_poll_init() and > drm_kms_helper_poll_fini(). > But there are no hits on DRM_CONNECTOR_POLL - so I think we maybe > have a driver here where we have plugged the drm_poll infrastructure, > but it is not in use. > > > include/drm/drm_crtc_helper.h | 16 --- > > The list of include files in this file could be dropped and replaced by: > struct drm_connector; > struct drm_device; > struct drm_display_mode; > struct drm_encoder; > struct drm_framebuffer; > struct drm_mode_set; > struct drm_modeset_acquire_ctx; > > I tried to do so on top of your patch. > But there were too many build errros and I somehow lost the motivation. Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy kms drivers. Just removing it from all the atomic drivers caused lots of fallout, I expect even more if you entirely remove the includes it has. Maybe a todo, care to pls create that patch since it's your idea? -Daniel > > > > include/drm/drm_probe_helper.h| 27 +++ > This on the other hand is fine - as expected as this is a new file. > > But the above is just some random comments so: > > Acked-by: Sam Ravnborg -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
Quoting Tvrtko Ursulin (2019-01-17 16:27:04)
>
> On 17/01/2019 14:34, Chris Wilson wrote:
> > Remove the struct_mutex requirement for looking up the vma for an
> > object.
>
> Another patch with missing change log.
>
> I see that you at least fixed the tree typo since the round I last
> reviewed. But I also had some other questions which I did not see you
> commented on.
>
> Anyways, it is very hard to review without change logs.. I am not sure
> why is this series particularly bad in this respect.
The short explanation, as given on the next patch,
rb = *p;
pos = rb_entry(rb, struct i915_vma, obj_node);
+ /*
+* If the view already exists in the tree, another thread
+* already created a matching vma, so return the older instance
+* and dispose of ours.
+*/
cmp = i915_vma_compare(pos, vm, view);
if (cmp == 0) {
spin_unlock(&obj->vma.lock);
@@ -294,6 +299,7 @@ i915_vma_instance(struct drm_i915_gem_object *obj,
vma = vma_lookup(obj, vm, view);
spin_unlock(&obj->vma.lock);
+ /* vma_create() will resolve the race if another creates the vma */
if (unlikely(!vma))
vma = vma_create(obj, vm, view);
which should explain why the whitespace is peculiar and the early return
returns pos not vma.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/23] drm/i915: Use b->irq_enable() as predicate for mock engine
On 17/01/2019 14:34, Chris Wilson wrote:
Since commit d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
we have required a mechanism to avoid touching the interrupt hardware
for breadcrumbs, superseding our mock interface for selftests.
References: d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 39
drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 -
4 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ed7105d7ff5..7b517bf83507 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -158,6 +158,9 @@ static void intel_breadcrumbs_fake_irq(struct timer_list *t)
static void irq_enable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_enable)
+ return;
+
/*
* FIXME: Ideally we want this on the API boundary, but for the
* sake of testing with mock breadcrumbs (no HW so unable to
Okay I think I misunderstood this patch in the last round. So you want
to avoid the GEM_BUG_ON below _and_ a dedicated boolean only for the
mock engine.
I only wonder on the remaining merit of this comment and actually a
GEM_BUG_ON, which will be hit and miss depending on the platform now.
Gut feeling says something is still not ideal here. Selftests variable
does actually feel better in this sense.
mock_engine seems only used from mock_gem_device, so could an
alternative be to set i915->runtime_pm.irqs_enabled there and keep the
GEM_BUG_ON in irq_enable above the !engine->irq_enable early return?
That would still provide the unconditional assert on the state of the
driver outside selftests.
Regards,
Tvrtko
@@ -167,21 +170,20 @@ static void irq_enable(struct intel_engine_cs *engine)
GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
/* Caller disables interrupts */
- if (engine->irq_enable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_enable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_enable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
static void irq_disable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_disable)
+ return;
+
/* Caller disables interrupts */
- if (engine->irq_disable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_disable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_disable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
@@ -293,25 +295,16 @@ static bool __intel_breadcrumbs_enable_irq(struct
intel_breadcrumbs *b)
if (b->irq_armed)
return false;
- /* The breadcrumb irq will be disarmed on the interrupt after the
+ /*
+* The breadcrumb irq will be disarmed on the interrupt after the
* waiters are signaled. This gives us a single interrupt window in
* which we can add a new waiter and avoid the cost of re-enabling
* the irq.
*/
b->irq_armed = true;
- if (I915_SELFTEST_ONLY(b->mock)) {
- /* For our mock objects we want to avoid interaction
-* with the real hardware (which is not set up). So
-* we simply pretend we have enabled the powerwell
-* and the irq, and leave it up to the mock
-* implementation to call intel_engine_wakeup()
-* itself when it wants to simulate a user interrupt,
-*/
- return true;
- }
-
- /* Since we are waiting on a request, the GPU should be busy
+ /*
+* Since we are waiting on a request, the GPU should be busy
* and should have its own rpm reference. This is tracked
* by i915->gt.awake, we can forgo holding our own wakref
* for the interrupt as before i915->gt.awake is released (when
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e2f65c59d6e8..fc52737751e7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -917,6 +917,9 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
intel_wakeref_t wakeref;
bool idle = true;
+ if (I915_SELFTEST_ONLY(!engine->mmio_base))
+ return true;
+
/* If the whole device is asleep, the engine must be idle */
wakeref = intel_runtime_pm_get_if_in_use(dev_priv);
if
Re: [Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
Quoting Chris Wilson (2019-01-17 16:31:27) > Quoting Tvrtko Ursulin (2019-01-17 16:27:04) > > > > On 17/01/2019 14:34, Chris Wilson wrote: > > > Remove the struct_mutex requirement for looking up the vma for an > > > object. > > > > Another patch with missing change log. > > There was no functional change. > > > I see that you at least fixed the tree typo since the round I last > > reviewed. But I also had some other questions which I did not see you > > commented on. > > I answer those questions. in 154644420773.27300.5770992084643848631@skylake-alporthouse-com ? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
On Wed, Jan 16, 2019 at 05:11:26PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > >Ville Syrjälä > >Sent: Tuesday, January 15, 2019 12:42 AM > >To: Roper, Matthew D > >Cc: intel-gfx@lists.freedesktop.org > >Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable > >bits > >from the plane_ctl() function > > > >On Mon, Jan 14, 2019 at 07:11:10PM +0200, Ville Syrjälä wrote: > >> On Fri, Jan 11, 2019 at 04:41:37PM -0800, Matt Roper wrote: > >> > On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote: > >> > > From: Ville Syrjälä > >> > > > >> > > On g4x+ the pipe gamma enable bit for the primary plane affects > >> > > the pipe bottom color as well. The same for the pipe csc enable > >> > > bit on ilk+. Thus we must configure those bits correctly even when > >> > > the primary plane is disabled. > >> > > >> > This is only true for >> > dedicated bits that control this, so I don't think the primay > >> > plane's settings should have any impact when disabled. I.e., we > >> > also need the bits set in this patch: > >> > > >> > https://patchwork.freedesktop.org/patch/271109/ > >> > >> Yes. I had the same bits (or something similar in a later patch in the > >> series). But we should probably just land your stuff first. > >> > >> > > >> > > To make the feasible let's split those settings from the > >> > > plane_ctl() function into a seprate funciton that we can call from > > Typo here. > > >> > > the ->disable_plane() hook as well. > >> > > >> > Is calling it from ->disable_plane() enough? If we just disable the > >> > primary plane, then those bits will remain set while the crtc > >> > remains active. But if you then disable the whole crtc and > >> > re-enable it again later, won't we have lost the bits at that point? > > Just curious, once crtc is re-enabled plane enable will eventually happen > where this can again be enabled. So is this the corner case where crtc gets > enabled and primary plane is not enabled and it works with just overlays ? Yes. > > If this is the case, why not just explicitly enable these separately in crtc > enable > sequence and not rely on primary plane enabling path to set this for us. What > could be the potential problem if we do this ? We have to configure them whenever gamma_enable/csc_enable change. Not just crtc_enable. So we'd have to duplicate the DSPCNTR reg writes in color_commit()/something which would also mean doing an ugly RMW since we wouldn't have the plane state around. Much cleaner to just add the plane to the state and let the normal codepath handle it. > > >> > >> Hmm. Yes, probably. > >> > >> Just adding a needs_modeset() check into > >> intel_color_add_affected_planes() (introduced in a later patch) could > >> be one way. But that means the plane control reg won't be updated > >> before the pipe is already active. So we might need a special case for > >> that too. > >> > >> That said, I kinda hate the pipe enable special cases for the color > >> management stuff. So I'm wondering if we could eliminate it all and > >> just rely on the normal pipe+plane update to do things correctly. But > >> to make that consistent we might have to have another special case to > >> disable gamma/etc. prior to enabling the pipe so that it can all be > >> enabled atomically later. Hmm. I suppose that could be achieved by > >> clearing all relevant control bits in disable_plane() (or in > >> crtc_disable() for skl+) if the crtc is no longer active. > >> > >> And I guess we could still keep the .load_luts() special case since > >> guaranteeing the atomicity for that isn't as easy. > >> > >> It would mean the pipe alwasy comes up with gamma and csc disabled. > >> But since it's all some shade of black anyway I guess it shouldn't be > >> a big deal. > > > >Bah. That won't actually work without more hacks for the case where the crtc > >was enabled already. I guess I'll just have to stick an explicit primary- > >>disable_plane() call into the crtc_enable() path :( > > >> > >> > > >> > > >> > Matt > >> > > >> > > > >> > > For consistency we'll do that on all the plane types. While that > >> > > has no real benefits at this time, it'll become useful when we > >> > > start to control the pipe gamma/csc enable bits dynamically when > >> > > we overhaul the color management code. > >> > > > >> > > On pre-g4x there doesn't appear to be any way to gamma correct the > >> > > pipe bottom color, but sticking to the same pattern doesn't hurt. > >> > > And it'll still help us to do crtc state readout correctly for the > >> > > pipe gamma enable bit for the color management overhaul. > >> > > > >> > > An alternative apporach would be to still precompute these bits > > Typo in approach. > > >> > > into plane_state->ctl, but that would require that we run through > >> > > the plane check even when the plane isn't logically enabled on any > >> > > crtc. Cu
Re: [Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
Quoting Tvrtko Ursulin (2019-01-17 16:27:04) > > On 17/01/2019 14:34, Chris Wilson wrote: > > Remove the struct_mutex requirement for looking up the vma for an > > object. > > Another patch with missing change log. There was no functional change. > I see that you at least fixed the tree typo since the round I last > reviewed. But I also had some other questions which I did not see you > commented on. I answer those questions. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 516a49cc1946 drm/i915: Fix assert_plane() warning on bootup with
external display.
The bot has tested the following trees: v4.20.2.
v4.20.2: Failed to apply! Possible dependencies:
c84c6fe30302 ("drm/i915: make encoder enable and disable hooks optional")
How should we proceed with this patch?
--
Thanks,
Sasha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 516a49cc1946 drm/i915: Fix assert_plane() warning on bootup with
external display.
The bot has tested the following trees: v4.20.2.
v4.20.2: Failed to apply! Possible dependencies:
c84c6fe30302 ("drm/i915: make encoder enable and disable hooks optional")
How should we proceed with this patch?
--
Thanks,
Sasha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
On 17/01/2019 14:34, Chris Wilson wrote:
Remove the struct_mutex requirement for looking up the vma for an
object.
Another patch with missing change log.
I see that you at least fixed the tree typo since the round I last
reviewed. But I also had some other questions which I did not see you
commented on.
Anyways, it is very hard to review without change logs.. I am not sure
why is this series particularly bad in this respect.
Regards,
Tvrtko
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_gem.c | 33 +++--
drivers/gpu/drm/i915/i915_gem_object.h| 45 ++---
drivers/gpu/drm/i915/i915_vma.c | 60 +++
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 4 +-
6 files changed, 92 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ba7f05b493ed..d052329c2319 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -159,14 +159,14 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (i915_vma_is_pinned(vma))
pin_count++;
}
seq_printf(m, " (pinned x %d)", pin_count);
if (obj->pin_global)
seq_printf(m, " (global)");
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -322,7 +322,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 538fa5404603..15acd052da46 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -437,15 +437,19 @@ int i915_gem_object_unbind(struct drm_i915_gem_object
*obj)
if (ret)
return ret;
- while ((vma = list_first_entry_or_null(&obj->vma_list,
- struct i915_vma,
- obj_link))) {
+ spin_lock(&obj->vma.lock);
+ while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
+ struct i915_vma,
+ obj_link))) {
list_move_tail(&vma->obj_link, &still_in_list);
+ spin_unlock(&obj->vma.lock);
+
ret = i915_vma_unbind(vma);
- if (ret)
- break;
+
+ spin_lock(&obj->vma.lock);
}
- list_splice(&still_in_list, &obj->vma_list);
+ list_splice(&still_in_list, &obj->vma.list);
+ spin_unlock(&obj->vma.lock);
return ret;
}
@@ -3489,7 +3493,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
* reading an invalid PTE on older architectures.
*/
restart:
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3567,7 +3571,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
*/
}
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3577,7 +3581,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
}
}
- list_for_each_entry(vma, &obj->vma_list, obj_link)
+ list_for_each_entry(vma, &obj->vma.list, obj_link)
vma->node.color = cache_level;
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true; /* Always invalidate stale cachelines */
@@ -4153,7 +4157,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
{
mutex_init(&obj->mm.lock);
- INIT_LIST_HEAD(&obj->vma_list);
+ spin_lock_init(&obj->vma.lock);
+ INIT_LIST_HEAD(&obj->vma.list);
+
INIT_LIST_HEAD(&obj->lut_list);
INIT_LIST_HEAD(&obj-
Re: [Intel-gfx] [PATCH 32/46] drm/i915: Pull VM lists under the VM mutex.
On 16/01/2019 17:01, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-01-16 16:47:43)
On 07/01/2019 11:54, Chris Wilson wrote:
@@ -1530,20 +1531,21 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void
*data,
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct list_head *list;
struct i915_vma *vma;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ mutex_lock(&i915->ggtt.vm.mutex);
for_each_ggtt_vma(vma, obj) {
if (!drm_mm_node_allocated(&vma->node))
continue;
list_move_tail(&vma->vm_link, &vma->vm->bound_list);
}
+ mutex_unlock(&i915->ggtt.vm.mutex);
This is now struct_mutex -> vm->mutex nesting, which we would preferably
want to avoid? There only two callers for the function.
It looks we could remove nesting from i915_gem_set_domain_ioctl by just
moving the call to after mutex unlock.
i915_gem_object_unpin_from_display_plane callers are not as easy so
maybe at least do the one above?
unpin_from_display_plane is the goal here tbh.
- i915 = to_i915(obj->base.dev);
spin_lock(&i915->mm.obj_lock);
list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
list_move_tail(&obj->mm.link, list);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index a76f65fe86be..4a0c6830659d 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -433,6 +433,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
}
INIT_LIST_HEAD(&eviction_list);
+ mutex_lock(&vm->mutex);
list_for_each_entry(vma, &vm->bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
@@ -440,6 +441,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
__i915_vma_pin(vma);
list_add(&vma->evict_link, &eviction_list);
}
+ mutex_unlock(&vm->mutex);
This is another nesting so I suppose you leave all this fun for later?
Yes, the intent was to put the locks in place (gradually) then peel back
struct_mutex (gradually).
@@ -689,8 +694,10 @@ i915_vma_remove(struct i915_vma *vma)
vma->ops->clear_pages(vma);
+ mutex_lock(&vma->vm->mutex);
drm_mm_remove_node(&vma->node);
This is by design also protected by the vm->mutex? But insertion is not
AFAICT.
Not yet. Can you guess which bit proved tricky? ;) Getting the right
point to lock for execbuf, and eviction. At the same time over there is
the fuss with ww_mutex, as well as contexts et al, and it all gets
confusing quickly.
...(tries to remember why this patch is actually here; this set was
picked so that I could do obj->vma_list without struct_mutex (which
was used for timeline allocation) and I pulled in anything required to
resolve conflicts, but why this one)...
Have you figured it out in the meantime?
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915/vbt: Add 'tp4' to varibles holding TP2/3/4 PSR wakeup time
== Series Details == Series: series starting with [1/4] drm/i915/vbt: Add 'tp4' to varibles holding TP2/3/4 PSR wakeup time URL : https://patchwork.freedesktop.org/series/55340/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5439_full -> Patchwork_11968_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_11968_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11968_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11968_full: ### IGT changes ### Possible regressions * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-iclb: PASS -> FAIL Known issues Here are the changes found in Patchwork_11968_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_ccs@pipe-b-crc-primary-basic: - shard-iclb: NOTRUN -> FAIL [fdo#107725] +2 * igt@kms_color@pipe-a-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_color@pipe-a-degamma: - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: PASS -> FAIL [fdo#103232] - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] * igt@kms_cursor_crc@cursor-256x256-random: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +3 - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@2x-busy-flip-interruptible: - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_hdmi_inject@inject-audio: - shard-iclb: NOTRUN -> FAIL [fdo#102370] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +2 - shard-skl: PASS -> FAIL [fdo#103166] * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +3 * igt@kms_plane_multiple@atomic-pipe-a-tiling-none: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] * igt@kms_setmode@basic: - shard-kbl: PASS -> FAIL [fdo#99912] * igt@pm_rpm@fences-dpms: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] * igt@pm_rpm@gem-idle: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +2 * igt@pm_rpm@universal-planes: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@pm_rpm@universal-planes-dpms: - shard-iclb: PASS -> DMESG-WARN [fdo#108654] Possible fixes * igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS * igt@kms_color@pipe-c-ctm-max: - shard-apl: FAIL [fdo#108147] -> PASS * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-apl: FAIL [fdo#103232] -> PASS +3 * igt@kms_cursor_crc@cursor-256x256-sliding: - shard-glk: FAIL [fdo#103232] -> PASS +2 * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-skl: FAIL [fdo#103184] -> PASS * igt@kms_draw_crc@draw-method-xrgb-blt-untiled: - shard-skl: FAIL [fdo#103232] / [fdo#108472] ->
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/icl: Work around broken VBTs for port F detection
Hi, On Wed, Jan 16, 2019 at 05:33:19PM -0800, Dhinakaran Pandiyan wrote: > On Thu, 2018-12-20 at 17:52 +0200, Imre Deak wrote: > > VBT may include incorrect information about the presence of port F. > > Work > > around this on SKUs where we know the port is not present. > > If we cannot trust the data in VBT, can we not test for the absence of > port-F by enabling the powerwell and checking for a timeout? Or at > least mark up a non-existent port after the first timeout so that we > don't keep probing it. Yes, thought about it too, but I'm not sure if it's a good idea. Enabling power wells has unexpected (at least to me) side effects on ICL, so I'd rather avoid using that as a detection method. OTOH the PCI ID list with fused-off ports must be well-defined and known, there just seems to be a difficulty to get at that list internally. So instead I'd suggest pushing for getting that list added to BSpec. I opened already a change request in BSpec for that, but more poking would be good. > > This patch is an improvement over checking the VBT for all ports, so > Reviewed-by: Dhinakaran Pandiyan Thanks for the review. > > > > > v2: > > - Fix IS_ICL_WITH_PORT_F, so it's useable from any context. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108915 > > Cc: Mika Kahola > > Cc: Jani Nikula > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/intel_display.c | 4 +++- > > 2 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h > > index 815db160b966..e45cda9d9555 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2317,6 +2317,8 @@ intel_info(const struct drm_i915_private > > *dev_priv) > > (dev_priv)->info.gt == 3) > > #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ > > (INTEL_DEVID(dev_priv) & > > 0x0004) == 0x0004) > > +#define IS_ICL_WITH_PORT_F(dev_priv) (IS_ICELAKE(dev_priv) && \ > > + INTEL_DEVID(dev_priv) != > > 0x8A51) > > > > #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)- > > >is_alpha_support) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2b81da068010..bd7fdaf7e093 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -14276,8 +14276,10 @@ static void intel_setup_outputs(struct > > drm_i915_private *dev_priv) > > /* > > * On some ICL SKUs port F is not present. No strap > > bits for > > * this, so rely on VBT. > > +* Work around broken VBTs on SKUs known to have no > > port F. > > */ > > - if (intel_bios_is_port_present(dev_priv, PORT_F)) > > + if (IS_ICL_WITH_PORT_F(dev_priv) && > > + intel_bios_is_port_present(dev_priv, PORT_F)) > > intel_ddi_init(dev_priv, PORT_F); > > > > icl_dsi_init(dev_priv); > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/23] drm/i915: Make all GPU resets atomic
== Series Details ==
Series: series starting with [01/23] drm/i915: Make all GPU resets atomic
URL : https://patchwork.freedesktop.org/series/55365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5440 -> Patchwork_11970
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55365/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11970 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (45 -> 39)
--
Additional (3): fi-kbl-7567u fi-glk-j4005 fi-byt-clapper
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-kbl-7500u fi-gdg-551 fi-pnv-d510 fi-icl-y fi-snb-2600
Build changes
-
* Linux: CI_DRM_5440 -> Patchwork_11970
CI_DRM_5440: b36a89b5ab74fd49a4369e6df0d2c02bc464a474 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4777: 8614d5eb114a660c3bd7ff77eab8bed53424cd30 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11970: f7e648e4bba87e1ddbeb45b377ec4470562fb286 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f7e648e4bba8 drm/i915: Drop fake breadcrumb irq
2c07c68932af drm/i915: Replace global breadcrumbs with per-context interrupt
tracking
f4d10d8a497c drm/i915: Remove the intel_engine_notify tracepoint
22e584a722b8 drm/i915: Identify active requests
97e2101df0fe drm/i915: Track the context's seqno in its own timeline HWSP
590309e71727 drm/i915: Keep all partially allocated HWSP on a freelist
9a2c0d841b87 drm/i915: Share per-timeline HWSP using a slab suballocator
90c17ef7381e drm/i915: Allocate a status page for each timeline
722338216230 drm/i915: Enlarge vma->pin_count
fb705705e39d drm/i915: Introduce concept of per-timeline (context) HWSP
4faf68c5 drm/i915: Move list of timelines under its own lock
a9fb042af3e7 drm/i915: Always allocate an object/vma for the HWSP
e64538758ef8 drm/i915/selftests: Make evict tolerant of foreign objects
a6cd7e980da3 drm/i915/selftests: Allocate mock ring/timeline per context
178df8680efe drm/i915: Use b->irq_enable() as predicate for mock engine
1b8241711cd3 drm/i915: Move vma lookup to its own lock
b590cd93b877 drm/i915: Pull VM lists under the VM mutex.
941079fbcd79 drm/i915: Stop tracking MRU activity on VMA
9c242ce79a77 drm/i915: Issue engine resets onto idle engines
b126705eb583 drm/i915/selftests: Trim struct_mutex duration for set-wedged
selftest
13c95ff25011 drm/i915: Remove GPU reset dependence on struct_mutex
84c5d840f63e drm/i915/guc: Disable global reset
cc34d0c113bf drm/i915: Make all GPU resets atomic
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11970/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Limit the for_each_set_bit() to the valid range
Quoting Ville Syrjälä (2019-01-17 15:07:53)
> On Wed, Jan 16, 2019 at 03:54:21PM +, Chris Wilson wrote:
> > Let static analyzers (smatch) know that we are not going to wander off
> > the end of the array by providing a tight upper bound:
> >
> > drivers/gpu/drm/i915/intel_display.c:9532 hsw_get_transcoder_state() error:
> > buffer overflow 'dev_priv->__info.trans_offsets' 6 <= 31
> >
> > References: 0716931a82b4 ("drm/i915/icl: fix transcoder state readout")
> > Signed-off-by: Chris Wilson
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Imre Deak
> > Cc: Madhav Chauhan
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 62d61fcad89c..b087ed285cc1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9526,7 +9526,9 @@ static bool hsw_get_transcoder_state(struct
> > intel_crtc *crtc,
> >* XXX: Do intel_display_power_get_if_enabled before reading this (for
> >* consistency and less surprising code; it's in always on power).
> >*/
> > - for_each_set_bit(panel_transcoder, &panel_transcoder_mask, 32) {
> > + for_each_set_bit(panel_transcoder,
> > + &panel_transcoder_mask,
> > + ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
>
> Or just I915_MAX_TRANSCODERS maybe? Doesn't really matter I suppose.
I don't know which would be better long term either.
trans_offset[] to match the TRANS_DDI_FUNC_CTL() closely,
or MAX_TRANSCODERS to match the panel bits closely.
I suppose MAX_TRANSCODERS here would at least cause smatch to complain
if MAX_TRANSCODERS was greater than trans_offset[] which might be
useful. (But I also think it will always remain trans_offsets[MAX_TRANSCODERS]).
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Limit the for_each_set_bit() to the valid range
On Wed, Jan 16, 2019 at 03:54:21PM +, Chris Wilson wrote:
> Let static analyzers (smatch) know that we are not going to wander off
> the end of the array by providing a tight upper bound:
>
> drivers/gpu/drm/i915/intel_display.c:9532 hsw_get_transcoder_state() error:
> buffer overflow 'dev_priv->__info.trans_offsets' 6 <= 31
>
> References: 0716931a82b4 ("drm/i915/icl: fix transcoder state readout")
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Imre Deak
> Cc: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 62d61fcad89c..b087ed285cc1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9526,7 +9526,9 @@ static bool hsw_get_transcoder_state(struct intel_crtc
> *crtc,
>* XXX: Do intel_display_power_get_if_enabled before reading this (for
>* consistency and less surprising code; it's in always on power).
>*/
> - for_each_set_bit(panel_transcoder, &panel_transcoder_mask, 32) {
> + for_each_set_bit(panel_transcoder,
> + &panel_transcoder_mask,
> + ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
Or just I915_MAX_TRANSCODERS maybe? Doesn't really matter I suppose.
Reviewed-by: Ville Syrjälä
> enum pipe trans_pipe;
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
> --
> 2.20.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/23] drm/i915: Make all GPU resets atomic
== Series Details == Series: series starting with [01/23] drm/i915: Make all GPU resets atomic URL : https://patchwork.freedesktop.org/series/55365/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Make all GPU resets atomic Okay! Commit: drm/i915/guc: Disable global reset Okay! Commit: drm/i915: Remove GPU reset dependence on struct_mutex -drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest Okay! Commit: drm/i915: Issue engine resets onto idle engines Okay! Commit: drm/i915: Stop tracking MRU activity on VMA Okay! Commit: drm/i915: Pull VM lists under the VM mutex. Okay! Commit: drm/i915: Move vma lookup to its own lock Okay! Commit: drm/i915: Use b->irq_enable() as predicate for mock engine Okay! Commit: drm/i915/selftests: Allocate mock ring/timeline per context Okay! Commit: drm/i915/selftests: Make evict tolerant of foreign objects Okay! Commit: drm/i915: Always allocate an object/vma for the HWSP Okay! Commit: drm/i915: Move list of timelines under its own lock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) Commit: drm/i915: Introduce concept of per-timeline (context) HWSP Okay! Commit: drm/i915: Enlarge vma->pin_count Okay! Commit: drm/i915: Allocate a status page for each timeline +./include/linux/mm.h:619:13: error: not a function +./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/mm.h:619:13: warning: call with no type! Commit: drm/i915: Share per-timeline HWSP using a slab suballocator -drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) Commit: drm/i915: Keep all partially allocated HWSP on a freelist -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) Commit: drm/i915: Track the context's seqno in its own timeline HWSP Okay! Commit: drm/i915: Identify active requests Okay! Commit: drm/i915: Remove the intel_engine_notify tracepoint Okay! Commit: drm/i915: Replace global breadcrumbs with per-context interrupt tracking +drivers/gpu/drm/i915/selftests/i915_request.c:283:40: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_request.c:283:40: warning: expression using sizeof(void) -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' -./include/linux/mm.h:619:13: warning: call with no type! +./include/linux/slab.h:664:13: error: not a function +./include/linux/slab.h:664:13: error: not a function Commit: drm/i915: Drop fake breadcrumb irq Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
On Wed, Jan 16, 2019 at 09:38:59AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:17PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The LUTs are single buffered so we should program them after
> > the double buffered pipe updates have been latched by the
> > hardware.
> >
> > We'll also fix up the IPS vs. split gamma w/a to do the IPS
> > disable like everyone else. Note that this is currently dead
> > code as we don't use the split gamma mode on HSW, but that
> > will be fixed up shortly.
>
> I don't think this is quite dead code...we don't use split gamma
> ourselves, but we could potentially inherit that setup from the BIOS
> (which will stick around until it eventually gets clobbered by the first
> modeset/fastset).
>
> Uma's series added some logic to sanitize the LUT's immediately on boot,
> but that hasn't landed yet.
With the gamma_enable/csc_enable flags properly tracked we shouldn't
need anything like that. Or am I missing something?
>
>
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_color.c | 25 +--
> > drivers/gpu/drm/i915/intel_display.c | 47
> > 2 files changed, 42 insertions(+), 30 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index f9e0855162f3..0c0da7ed0fd7 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -361,29 +361,6 @@ static void hsw_color_commit(const struct
> > intel_crtc_state *crtc_state)
> > ilk_load_csc_matrix(crtc_state);
> > }
> >
> > -/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> > -static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - bool reenable_ips = false;
> > -
> > - /*
> > -* Workaround : Do not read or write the pipe palette/gamma data while
> > -* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > -*/
> > - if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
> > - (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> > - hsw_disable_ips(crtc_state);
> > - reenable_ips = true;
> > - }
> > -
> > - i9xx_load_luts(crtc_state);
> > -
> > - if (reenable_ips)
> > - hsw_enable_ips(crtc_state);
> > -}
> > -
> > static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > @@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
> > if (IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.load_luts = cherryview_load_luts;
> > } else if (IS_HASWELL(dev_priv)) {
> > - dev_priv->display.load_luts = haswell_load_luts;
> > + dev_priv->display.load_luts = i9xx_load_luts;
> > dev_priv->display.color_commit = hsw_color_commit;
> > } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> >IS_BROXTON(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 96c78566b8e6..1caee4128974 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc
> > *crtc)
> > static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
> > *old_crtc_state,
> >const struct intel_crtc_state
> > *new_crtc_state)
> > {
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> > if (!old_crtc_state->ips_enabled)
> > return false;
> >
> > if (needs_modeset(&new_crtc_state->base))
> > return true;
> >
> > + /*
> > +* Workaround : Do not read or write the pipe palette/gamma data while
> > +* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > +*
> > +* Disable IPS before we program the LUT.
> > +*/
> > + if (IS_HASWELL(dev_priv) &&
> > + (new_crtc_state->base.color_mgmt_changed ||
> > +new_crtc_state->update_pipe) &&
> > + new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>
> Wouldn't we want old_crtc_state for the gamma_mode test? We need to
> disable IPS if we're already in split gamma mode (inherited from BIOS),
> regardless of whether we're moving to non-split gamma.
>
>
> Matt
>
> > + return true;
> > +
> > return !new_crtc_state->ips_enabled;
> > }
> >
> > static bool hsw_post_update_enable_ips(const struct intel_crtc_state
> > *old_crtc_state,
> >const struct intel_crtc_state
> > *new_crtc_state)
> > {
> > + struct intel_cr
Re: [Intel-gfx] [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
On Thu, Jan 17, 2019 at 05:14:06AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Roper, Matthew D
> >Sent: Thursday, January 17, 2019 1:07 AM
> >To: Ville Syrjala
> >Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> >Subject: Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc
> >state
> >
> >On Fri, Jan 11, 2019 at 07:08:19PM +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Track whether pipe gamma is enabled or disabled. For now we stick to
> >> the current behaviour of always enabling gamma. But we do get working
> >> state readout for this now. On SKL+ we use the pipe bottom color as
> >> our hardware state. On pre-SKL we read the state back from the primary
> >> plane control register.
> >> That only really correct for g4x+, as older platforms never gamma
> >> correct pipe bottom color. But doing the readout the same way on all
> >> platforms is fine, and there is no other way to do it really.
> >>
> >> Signed-off-by: Ville Syrjälä
> >
> >Reviewed-by: Matt Roper
> >
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 8
> >> drivers/gpu/drm/i915/intel_color.c | 24 +++-
> >> drivers/gpu/drm/i915/intel_display.c | 56 ++--
> >> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> >> drivers/gpu/drm/i915/intel_sprite.c | 17 +++--
> >> 5 files changed, 92 insertions(+), 16 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 9d17ba199be4..7f0913bc1b47
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -5707,6 +5707,14 @@ enum {
> >> #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
> >> #define PIPEMISC(pipe)_MMIO_PIPE2(pipe,
> >_PIPE_MISC_A)
> >>
> >> +/* SKL+ pipe bottom color */
> >> +#define _PIPE_BOTTOM_COLOR_A 0x70034
> >> +#define _PIPE_BOTTOM_COLOR_B 0x71034
> >> +#define PIPE_BOTTOM_GAMMA_ENABLE(1 << 31)
> >> +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
> >> +#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
> >> +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe,
> >_PIPE_BOTTOM_COLOR_A)
> >> +
> >> #define VLV_DPFLIPSTAT
> > _MMIO(VLV_DISPLAY_BASE + 0x70028)
> >> #define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
> >> #define PIPEB_HLINE_INT_EN (1 << 28)
> >> diff --git a/drivers/gpu/drm/i915/intel_color.c
> >> b/drivers/gpu/drm/i915/intel_color.c
> >> index 6fdbfa8c4008..313b281204fa 100644
> >> --- a/drivers/gpu/drm/i915/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/intel_color.c
> >> @@ -387,6 +387,24 @@ static void hsw_color_commit(const struct
> >intel_crtc_state *crtc_state)
> >>ilk_load_csc_matrix(crtc_state);
> >> }
> >>
> >> +static void skl_color_commit(const struct intel_crtc_state
> >> +*crtc_state) {
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> + enum pipe pipe = crtc->pipe;
> >> + u32 val;
> >> +
> >> + val = 0;
>
> We can initialize this above itself.
Ack.
>
> >> + if (crtc_state->gamma_enable)
> >> + val |= PIPE_BOTTOM_GAMMA_ENABLE;
> >> + val |= PIPE_BOTTOM_CSC_ENABLE;
> >> + I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
> >> +
> >> + I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> >> +
> >> + ilk_load_csc_matrix(crtc_state);
> >> +}
> >> +
> >> static void bdw_load_degamma_lut(const struct intel_crtc_state
> >> *crtc_state) {
> >>struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> @@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state
> >*crtc_state)
> >>degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >>gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >>
> >> + crtc_state->gamma_enable = true;
> >> +
> >>/*
> >> * We also allow no degamma lut/ctm and a gamma lut at the legacy
> >> * size (256 entries).
> >> @@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
> >>else
> >>dev_priv->display.load_luts = i9xx_load_luts;
> >>
> >> - if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> >> + if (INTEL_GEN(dev_priv) >= 9)
> >> + dev_priv->display.color_commit = skl_color_commit;
> >> + else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> >>dev_priv->display.color_commit = hsw_color_commit;
> >>else
> >>dev_priv->display.color_commit = ilk_color_commit; diff
> >--git
> >> a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 90afcae91b30..896ce95790cb 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct
> >intel_crtc_state *crtc_state)
> >>struct d
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] drm/i915: Make all GPU resets atomic
== Series Details ==
Series: series starting with [01/23] drm/i915: Make all GPU resets atomic
URL : https://patchwork.freedesktop.org/series/55365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cc34d0c113bf drm/i915: Make all GPU resets atomic
-:23: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#23: FILE: drivers/gpu/drm/i915/i915_reset.c:147:
+ udelay(50);
-:29: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#29: FILE: drivers/gpu/drm/i915/i915_reset.c:152:
+ udelay(50);
total: 0 errors, 0 warnings, 2 checks, 121 lines checked
84c5d840f63e drm/i915/guc: Disable global reset
13c95ff25011 drm/i915: Remove GPU reset dependence on struct_mutex
-:616: WARNING:MEMORY_BARRIER: memory barrier without comment
#616: FILE: drivers/gpu/drm/i915/i915_reset.c:692:
+ smp_store_mb(i915->gpu_error.restart, NULL);
-:769: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its
#endif
#769: FILE: drivers/gpu/drm/i915/i915_reset.c:920:
+#if 0
total: 0 errors, 2 warnings, 0 checks, 1395 lines checked
b126705eb583 drm/i915/selftests: Trim struct_mutex duration for set-wedged
selftest
9c242ce79a77 drm/i915: Issue engine resets onto idle engines
941079fbcd79 drm/i915: Stop tracking MRU activity on VMA
b590cd93b877 drm/i915: Pull VM lists under the VM mutex.
1b8241711cd3 drm/i915: Move vma lookup to its own lock
-:157: WARNING:USE_SPINLOCK_T: struct spinlock should be spinlock_t
#157: FILE: drivers/gpu/drm/i915/i915_gem_object.h:94:
+ struct spinlock lock;
total: 0 errors, 1 warnings, 0 checks, 284 lines checked
178df8680efe drm/i915: Use b->irq_enable() as predicate for mock engine
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit d4ccceb05591 ("drm/i915/icl:
Ringbuffer interrupt handling")'
#6:
Since commit d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit d4ccceb05591 ("drm/i915/icl:
Ringbuffer interrupt handling")'
#10:
References: d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
total: 2 errors, 0 warnings, 0 checks, 111 lines checked
a6cd7e980da3 drm/i915/selftests: Allocate mock ring/timeline per context
e64538758ef8 drm/i915/selftests: Make evict tolerant of foreign objects
a9fb042af3e7 drm/i915: Always allocate an object/vma for the HWSP
4faf68c5 drm/i915: Move list of timelines under its own lock
fb705705e39d drm/i915: Introduce concept of per-timeline (context) HWSP
722338216230 drm/i915: Enlarge vma->pin_count
90c17ef7381e drm/i915: Allocate a status page for each timeline
9a2c0d841b87 drm/i915: Share per-timeline HWSP using a slab suballocator
590309e71727 drm/i915: Keep all partially allocated HWSP on a freelist
97e2101df0fe drm/i915: Track the context's seqno in its own timeline HWSP
-:170: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#170: FILE: drivers/gpu/drm/i915/intel_lrc.c:2042:
}
+static const int gen8_emit_breadcrumb_sz = 10 + WA_TAIL_DWORDS;
-:201: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#201: FILE: drivers/gpu/drm/i915/intel_lrc.c:2068:
}
+static const int gen8_emit_breadcrumb_rcs_sz = 14 + WA_TAIL_DWORDS;
-:227: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#227: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:343:
}
+static const int gen6_rcs_emit_breadcrumb_sz = 18;
-:250: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#250: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:450:
}
+static const int gen7_rcs_emit_breadcrumb_sz = 10;
-:271: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#271: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:468:
}
+static const int gen6_xcs_emit_breadcrumb_sz = 8;
-:299: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#299: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:498:
}
+static const int gen7_xcs_emit_breadcrumb_sz = 10 + GEN7_XCS_WA * 3;
-:351: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#351: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:944:
}
+static const int i9xx_emit_breadcrumb_sz = 8;
-:379: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#379: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:972:
}
+static const int gen5_emit_breadcrumb_sz = GEN5_WA_STORES * 3 + 6;
total: 0 errors, 0 warnings, 8 checks, 397 lines checked
22e584a722b8 drm/i915: Identify active requests
f4d10d8a497c drm/i915: Remove the intel_engine_notify tracepoint
2c07c68932af drm/i915: Replace global breadcrumbs with per-context inte
Re: [Intel-gfx] [PATCH] drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user
Quoting Tvrtko Ursulin (2019-01-17 14:48:31) > From: Tvrtko Ursulin > > To avoid a false positive of a leaked wakeref, we can store the cookie > in file->private_data and use it in intel_runtime_pm_put. > > Signed-off-by: Tvrtko Ursulin > Cc: Chris Wilson > --- > drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index 64d805d9ae59..487b6eeba031 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4408,7 +4408,7 @@ static int i915_forcewake_open(struct inode *inode, > struct file *file) > if (INTEL_GEN(i915) < 6) > return 0; > > - intel_runtime_pm_get(i915); > + file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915); > intel_uncore_forcewake_user_get(i915); > > return 0; > @@ -4422,7 +4422,8 @@ static int i915_forcewake_release(struct inode *inode, > struct file *file) > return 0; > > intel_uncore_forcewake_user_put(i915); > - intel_runtime_pm_put_unchecked(i915); > + intel_runtime_pm_put(i915, > +(intel_wakeref_t)(uintptr_t)file->private_data); We definitely don't need to cast between integer types after uintptr, but I can see the desire for symmetry. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix wakeref cookie handling in debugfs/i915_forcewake_user
From: Tvrtko Ursulin To avoid a false positive of a leaked wakeref, we can store the cookie in file->private_data and use it in intel_runtime_pm_put. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 64d805d9ae59..487b6eeba031 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4408,7 +4408,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) if (INTEL_GEN(i915) < 6) return 0; - intel_runtime_pm_get(i915); + file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915); intel_uncore_forcewake_user_get(i915); return 0; @@ -4422,7 +4422,8 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) return 0; intel_uncore_forcewake_user_put(i915); - intel_runtime_pm_put_unchecked(i915); + intel_runtime_pm_put(i915, +(intel_wakeref_t)(uintptr_t)file->private_data); return 0; } -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Swapping a single global interrupt handler for a herd
I wrote something here like... Just the early part of the series with the HWSP allocation changes suggested by John. Tvrtko I haven't applied your mutex feedback yet. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/23] drm/i915: Move vma lookup to its own lock
Remove the struct_mutex requirement for looking up the vma for an
object.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_gem.c | 33 +++--
drivers/gpu/drm/i915/i915_gem_object.h| 45 ++---
drivers/gpu/drm/i915/i915_vma.c | 60 +++
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 4 +-
6 files changed, 92 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ba7f05b493ed..d052329c2319 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -159,14 +159,14 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (i915_vma_is_pinned(vma))
pin_count++;
}
seq_printf(m, " (pinned x %d)", pin_count);
if (obj->pin_global)
seq_printf(m, " (global)");
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -322,7 +322,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 538fa5404603..15acd052da46 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -437,15 +437,19 @@ int i915_gem_object_unbind(struct drm_i915_gem_object
*obj)
if (ret)
return ret;
- while ((vma = list_first_entry_or_null(&obj->vma_list,
- struct i915_vma,
- obj_link))) {
+ spin_lock(&obj->vma.lock);
+ while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
+ struct i915_vma,
+ obj_link))) {
list_move_tail(&vma->obj_link, &still_in_list);
+ spin_unlock(&obj->vma.lock);
+
ret = i915_vma_unbind(vma);
- if (ret)
- break;
+
+ spin_lock(&obj->vma.lock);
}
- list_splice(&still_in_list, &obj->vma_list);
+ list_splice(&still_in_list, &obj->vma.list);
+ spin_unlock(&obj->vma.lock);
return ret;
}
@@ -3489,7 +3493,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
* reading an invalid PTE on older architectures.
*/
restart:
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3567,7 +3571,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
*/
}
- list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ list_for_each_entry(vma, &obj->vma.list, obj_link) {
if (!drm_mm_node_allocated(&vma->node))
continue;
@@ -3577,7 +3581,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
}
}
- list_for_each_entry(vma, &obj->vma_list, obj_link)
+ list_for_each_entry(vma, &obj->vma.list, obj_link)
vma->node.color = cache_level;
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true; /* Always invalidate stale cachelines */
@@ -4153,7 +4157,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
{
mutex_init(&obj->mm.lock);
- INIT_LIST_HEAD(&obj->vma_list);
+ spin_lock_init(&obj->vma.lock);
+ INIT_LIST_HEAD(&obj->vma.list);
+
INIT_LIST_HEAD(&obj->lut_list);
INIT_LIST_HEAD(&obj->batch_pool_link);
@@ -4319,14 +4325,13 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
mutex_lock(&i915->drm.struct_mutex);
GEM_BUG_ON(i915_gem_object_is_active(obj));
- list_for_each_entry_safe(vma, vn,
-&obj->vma_list, obj_link) {
+ list_for_
[Intel-gfx] [PATCH 01/23] drm/i915: Make all GPU resets atomic
In preparation for the next few commits, make resetting the GPU atomic.
Currently, we have prepared gen6+ for atomic resetting of individual
engines, but now there is a requirement to perform the whole device
level reset (just the register poking) from inside an atomic context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 50 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 +-
2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 342d9ee42601..b9d0ea70361c 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -144,14 +144,14 @@ static int i915_do_reset(struct drm_i915_private *i915,
/* Assert reset for at least 20 usec, and wait for acknowledgement. */
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- usleep_range(50, 200);
- err = wait_for(i915_in_reset(pdev), 500);
+ udelay(50);
+ err = wait_for_atomic(i915_in_reset(pdev), 50);
/* Clear the reset request. */
pci_write_config_byte(pdev, I915_GDRST, 0);
- usleep_range(50, 200);
+ udelay(50);
if (!err)
- err = wait_for(!i915_in_reset(pdev), 500);
+ err = wait_for_atomic(!i915_in_reset(pdev), 50);
return err;
}
@@ -171,7 +171,7 @@ static int g33_do_reset(struct drm_i915_private *i915,
struct pci_dev *pdev = i915->drm.pdev;
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- return wait_for(g4x_reset_complete(pdev), 500);
+ return wait_for_atomic(g4x_reset_complete(pdev), 50);
}
static int g4x_do_reset(struct drm_i915_private *dev_priv,
@@ -182,13 +182,13 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
int ret;
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
@@ -196,7 +196,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
@@ -205,9 +205,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
out:
pci_write_config_byte(pdev, I915_GDRST, 0);
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
return ret;
}
@@ -218,27 +218,29 @@ static int ironlake_do_reset(struct drm_i915_private
*dev_priv,
{
int ret;
- I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
- I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
}
out:
- I915_WRITE(ILK_GDSR, 0);
- POSTING_READ(IL
[Intel-gfx] [PATCH 16/23] drm/i915: Allocate a status page for each timeline
Allocate a page for use as a status page by a group of timelines, as we
only need a dword of storage for each (rounded up to the cacheline for
safety) we can pack multiple timelines into the same page. Each timeline
will then be able to track its own HW seqno.
v2: Reuse the common per-engine HWSP for the solitary ringbuffer
timeline, so that we do not have to emit (using per-gen specialised
vfuncs) the breadcrumb into the distinct timeline HWSP and instead can
keep on using the common MI_STORE_DWORD_INDEX. However, to maintain the
sleight-of-hand for the global/per-context seqno switchover, we will
store both temporarily (and so use a custom offset for the shared timeline
HWSP until the switch over).
v3: Keep things simple and allocate a page for each timeline, page
sharing comes next.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_timeline.c | 106 -
drivers/gpu/drm/i915/i915_timeline.h | 21 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 64 +--
drivers/gpu/drm/i915/intel_lrc.c | 22 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_mock_selftests.h | 2 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 373 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 17 +-
10 files changed, 571 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 84550f17d3df..380f4d25fb89 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,11 +9,38 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
-void i915_timeline_init(struct drm_i915_private *i915,
- struct i915_timeline *timeline,
- const char *name)
+static int hwsp_alloc(struct i915_timeline *timeline)
+{
+ struct drm_i915_private *i915 = timeline->i915;
+ struct drm_i915_gem_object *bo;
+ struct i915_vma *vma;
+
+ bo = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ i915_gem_object_set_cache_level(bo, I915_CACHE_LLC);
+
+ vma = i915_vma_instance(bo, &i915->ggtt.vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(bo);
+ return PTR_ERR(vma);
+ }
+
+ timeline->hwsp_ggtt = vma;
+ timeline->hwsp_offset = 0;
+
+ return 0;
+}
+
+int i915_timeline_init(struct drm_i915_private *i915,
+ struct i915_timeline *timeline,
+ const char *name,
+ struct i915_vma *global_hwsp)
{
struct i915_gt_timelines *gt = &i915->gt.timelines;
+ void *vaddr;
+ int err;
/*
* Ideally we want a set of engines on a single leaf as we expect
@@ -25,10 +52,27 @@ void i915_timeline_init(struct drm_i915_private *i915,
timeline->i915 = i915;
timeline->name = name;
+ timeline->pin_count = 0;
+
+ if (global_hwsp) {
+ timeline->hwsp_ggtt = i915_vma_get(global_hwsp);
+ timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
+ } else {
+ err = hwsp_alloc(timeline);
+ if (err)
+ return err;
+ }
- mutex_lock(>->mutex);
- list_add(&timeline->link, >->list);
- mutex_unlock(>->mutex);
+ vaddr = i915_gem_object_pin_map(timeline->hwsp_ggtt->obj, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ i915_vma_put(timeline->hwsp_ggtt);
+ return PTR_ERR(vaddr);
+ }
+
+ timeline->hwsp_seqno =
+ memset(vaddr + timeline->hwsp_offset,
+ 0,
+ sizeof(*timeline->hwsp_seqno));
/* Called during early_init before we know how many engines there are */
@@ -40,6 +84,12 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(&timeline->requests);
i915_syncmap_init(&timeline->sync);
+
+ mutex_lock(>->mutex);
+ list_add(&timeline->link, >->list);
+ mutex_unlock(>->mutex);
+
+ return 0;
}
void i915_timelines_init(struct drm_i915_private *i915)
@@ -85,6 +135,7 @@ void i915_timeline_fini(struct i915_timeline *timeline)
{
struct i915_gt_timelines *gt = &timeline->i915->gt.timelines;
+ GEM_BUG_ON(timeline->pin_count);
GEM_BUG_ON(!list_empty(&timeline->requests));
i915_syncmap_free(&timeline->sync);
@@ -92,23 +143,62 @@ void i915_timeline_fini(struct i915_timeline *timeline)
mutex_lock(>->mutex);
list_del(&timeline->link);
mutex_unlock(>->mutex);
+
+ i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
+ i915_vma_put(timeline->hwsp_ggtt);
}
struct i915_timeline *
-i915_timeline_create(struct drm_i915_private *i915, const cha
[Intel-gfx] [PATCH 13/23] drm/i915: Move list of timelines under its own lock
Currently, the list of timelines is serialised by the struct_mutex, but
to alleviate difficulties with using that mutex in future, move the
list management under its own dedicated mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem.c | 89 +--
drivers/gpu/drm/i915/i915_reset.c | 8 +-
drivers/gpu/drm/i915/i915_timeline.c | 38 ++--
drivers/gpu/drm/i915/i915_timeline.h | 3 +
drivers/gpu/drm/i915/i915_vma.c | 6 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 7 +-
.../gpu/drm/i915/selftests/mock_timeline.c| 3 +-
8 files changed, 101 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 94680b15bed0..3913900600b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1975,7 +1975,10 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
- struct list_head timelines;
+ struct i915_gt_timelines {
+ struct mutex mutex; /* protects list, tainted by GPU */
+ struct list_head list;
+ } timelines;
struct list_head active_rings;
struct list_head closed_vma;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 15acd052da46..3c6091021290 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3222,33 +3222,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
}
-static long wait_for_timeline(struct i915_timeline *tl,
- unsigned int flags, long timeout)
-{
- struct i915_request *rq;
-
- rq = i915_gem_active_get_unlocked(&tl->last_request);
- if (!rq)
- return timeout;
-
- /*
-* "Race-to-idle".
-*
-* Switching to the kernel context is often used a synchronous
-* step prior to idling, e.g. in suspend for flushing all
-* current operations to memory before sleeping. These we
-* want to complete as quickly as possible to avoid prolonged
-* stalls, so allow the gpu to boost to maximum clocks.
-*/
- if (flags & I915_WAIT_FOR_IDLE_BOOST)
- gen6_rps_boost(rq, NULL);
-
- timeout = i915_request_wait(rq, flags, timeout);
- i915_request_put(rq);
-
- return timeout;
-}
-
static int wait_for_engines(struct drm_i915_private *i915)
{
if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
@@ -3265,6 +3238,8 @@ static int wait_for_engines(struct drm_i915_private *i915)
int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
+ struct i915_timeline *tl;
+
GEM_TRACE("flags=%x (%s), timeout=%ld%s\n",
flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked",
timeout, timeout == MAX_SCHEDULE_TIMEOUT ? " (forever)" : "");
@@ -3273,17 +3248,45 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915,
if (!READ_ONCE(i915->gt.awake))
return 0;
+ mutex_lock(&i915->gt.timelines.mutex);
+ list_for_each_entry(tl, &i915->gt.timelines.list, link) {
+ struct i915_request *rq;
+
+ rq = i915_gem_active_get_unlocked(&tl->last_request);
+ if (!rq)
+ continue;
+
+ mutex_unlock(&i915->gt.timelines.mutex);
+
+ /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+ if (flags & I915_WAIT_FOR_IDLE_BOOST)
+ gen6_rps_boost(rq, NULL);
+
+ timeout = i915_request_wait(rq, flags, timeout);
+ i915_request_put(rq);
+ if (timeout < 0)
+ return timeout;
+
+ mutex_lock(&i915->gt.timelines.mutex);
+
+ /* restart after dropping the lock */
+ tl = list_entry(&i915->gt.timelines.list, typeof(*tl), link);
+ }
+ mutex_unlock(&i915->gt.timelines.mutex);
+
if (flags & I915_WAIT_LOCKED) {
- struct i915_timeline *tl;
int err;
lockdep_assert_held(&i915->drm.struct_mutex);
- list_for_each_entry(tl, &i915->gt.timelines, link) {
-
[Intel-gfx] [PATCH 03/23] drm/i915: Remove GPU reset dependence on struct_mutex
Now that the submission backends are controlled via their own spinlocks,
with a wave of a magic wand we can lift the struct_mutex requirement
around GPU reset. That is we allow the submission frontend (userspace)
to keep on submitting while we process the GPU reset as we can suspend
the backend independently.
The major change is around the backoff/handoff strategy for performing
the reset. With no mutex deadlock, we no longer have to coordinate with
any waiter, and just perform the reset immediately.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/i915_gem.c | 18 +-
drivers/gpu/drm/i915/i915_gem_fence_reg.h | 1 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.h | 24 +-
drivers/gpu/drm/i915/i915_request.c | 47 ---
drivers/gpu/drm/i915/i915_reset.c | 397 --
drivers/gpu/drm/i915/i915_reset.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 5 +-
drivers/gpu/drm/i915/intel_lrc.c | 92 ++--
drivers/gpu/drm/i915/intel_overlay.c | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 91 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 13 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 57 +--
.../drm/i915/selftests/intel_workarounds.c| 3 -
17 files changed, 317 insertions(+), 462 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 86152503331b..ba7f05b493ed 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1284,8 +1284,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_puts(m, "Wedged\n");
if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
seq_puts(m, "Reset in progress: struct_mutex backoff\n");
- if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
- seq_puts(m, "Reset in progress: reset handoff to waiter\n");
if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
seq_puts(m, "Waiter holding struct mutex\n");
if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
@@ -3907,11 +3905,6 @@ i915_wedged_set(void *data, u64 val)
i915_handle_error(i915, val, I915_ERROR_CAPTURE,
"Manually set wedged engine mask = %llx", val);
-
- wait_on_bit(&i915->gpu_error.flags,
- I915_RESET_HANDOFF,
- TASK_UNINTERRUPTIBLE);
-
return 0;
}
@@ -4066,13 +4059,8 @@ i915_drop_caches_set(void *data, u64 val)
mutex_unlock(&i915->drm.struct_mutex);
}
- if (val & DROP_RESET_ACTIVE &&
- i915_terminally_wedged(&i915->gpu_error)) {
+ if (val & DROP_RESET_ACTIVE && i915_terminally_wedged(&i915->gpu_error))
i915_handle_error(i915, ALL_ENGINES, 0, NULL);
- wait_on_bit(&i915->gpu_error.flags,
- I915_RESET_HANDOFF,
- TASK_UNINTERRUPTIBLE);
- }
fs_reclaim_acquire(GFP_KERNEL);
if (val & DROP_BOUND)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 310d9e1e1620..94680b15bed0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3001,11 +3001,6 @@ static inline bool i915_reset_backoff(struct
i915_gpu_error *error)
return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}
-static inline bool i915_reset_handoff(struct i915_gpu_error *error)
-{
- return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
-}
-
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
return unlikely(test_bit(I915_WEDGED, &error->flags));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b359390ba22c..d20b42386c3c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -657,11 +657,6 @@ i915_gem_object_wait(struct drm_i915_gem_object *obj,
struct intel_rps_client *rps_client)
{
might_sleep();
-#if IS_ENABLED(CONFIG_LOCKDEP)
- GEM_BUG_ON(debug_locks &&
- !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
- !!(flags & I915_WAIT_LOCKED));
-#endif
GEM_BUG_ON(timeout < 0);
timeout = i915_gem_object_wait_reservation(obj->resv,
@@ -4493,8 +4488,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
GEM_TRACE("\n");
- mutex_lock(&i915->drm.struct_mutex);
-
wakeref = intel_runtime_pm_get(i915);
intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
@@ -4520,6 +4513,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
intel_uncore_forcewake_put(i
[Intel-gfx] [PATCH 02/23] drm/i915/guc: Disable global reset
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here is verboten (as we must be able to reset from underneath any
of our mutexes). That makes recovering the guc unviable without, for
example, reserving contiguous vma space and pages for it to use.
The plan to re-enable global reset for the GuC centers around reusing the
WOPM reserved space at the top of the aperture (that we know we can
populate a contiguous range large enough to dma xfer the fw image).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index b9d0ea70361c..2961c21d9420 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -590,6 +590,9 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned
int engine_mask)
bool intel_has_gpu_reset(struct drm_i915_private *i915)
{
+ if (USES_GUC(i915))
+ return false;
+
return intel_get_gpu_reset(i915);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/23] drm/i915: Enlarge vma->pin_count
Previously we only accommodated having a vma pinned by a small number of
users, with the maximum being pinned for use by the display engine. As
such, we used a small bitfield only large enough to allow the vma to
be pinned twice (for back/front buffers) in each scanout plane. Keeping
the maximum permissible pin_count small allows us to quickly catch a
potential leak. However, as we want to split a 4096B page into 64
different cachelines and pin each cacheline for use by a different
timeline, we will exceed the current maximum permissible vma->pin_count
and so time has come to enlarge it.
Whilst we are here, try to pull together the similar bits:
Address/layout specification:
- bias, mappable, zone_4g: address limit specifiers
- fixed: address override, limits still apply though
- high: not strictly an address limit, but an address direction to search
Search controls:
- nonblock, nonfault, noevict
v2: Rewrite the guideline comment on bit consumption.
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 -
drivers/gpu/drm/i915/i915_vma.h | 45 +++--
2 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index bd679c8c56dd..03ade71b8d9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -642,19 +642,19 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
/* Flags used by pin/bind&friends. */
#define PIN_NONBLOCK BIT_ULL(0)
-#define PIN_MAPPABLE BIT_ULL(1)
-#define PIN_ZONE_4GBIT_ULL(2)
-#define PIN_NONFAULT BIT_ULL(3)
-#define PIN_NOEVICTBIT_ULL(4)
-
-#define PIN_MBZBIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
-#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
-#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
-#define PIN_UPDATE BIT_ULL(8)
-
-#define PIN_HIGH BIT_ULL(9)
-#define PIN_OFFSET_BIASBIT_ULL(10)
-#define PIN_OFFSET_FIXED BIT_ULL(11)
+#define PIN_NONFAULT BIT_ULL(1)
+#define PIN_NOEVICTBIT_ULL(2)
+#define PIN_MAPPABLE BIT_ULL(3)
+#define PIN_ZONE_4GBIT_ULL(4)
+#define PIN_HIGH BIT_ULL(5)
+#define PIN_OFFSET_BIASBIT_ULL(6)
+#define PIN_OFFSET_FIXED BIT_ULL(7)
+
+#define PIN_MBZBIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
+#define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
+#define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
+#define PIN_UPDATE BIT_ULL(11)
+
#define PIN_OFFSET_MASK(-I915_GTT_PAGE_SIZE)
#endif
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 7252abc73d3e..5793abe509a2 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -71,29 +71,42 @@ struct i915_vma {
unsigned int open_count;
unsigned long flags;
/**
-* How many users have pinned this object in GTT space. The following
-* users can each hold at most one reference: pwrite/pread, execbuffer
-* (objects are not allowed multiple times for the same batchbuffer),
-* and the framebuffer code. When switching/pageflipping, the
-* framebuffer code has at most two buffers pinned per crtc.
+* How many users have pinned this object in GTT space.
*
-* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
-* bits with absolutely no headroom. So use 4 bits.
+* This is a tightly bound, fairly small number of users, so we
+* stuff inside the flags field so that we can both check for overflow
+* and detect a no-op i915_vma_pin() in a single check, while also
+* pinning the vma.
+*
+* The worst case display setup would have the same vma pinned for
+* use on each plane on each crtc, while also building the next atomic
+* state and holding a pin for the length of the cleanup queue. In the
+* future, the flip queue may be increased from 1.
+* Estimated worst case: 3 [qlen] * 4 [max crtcs] * 7 [max planes] = 84
+*
+* For GEM, the number of concurrent users for pwrite/pread is
+* unbounded. For execbuffer, it is currently one but will in future
+* be extended to allow multiple clients to pin vma concurrently.
+*
+* We also use suballocated pages, with each suballocation claiming
+* its own pin on the shared vma. At present, this is limited to
+* exclusive cachelines of a single page, so a maximum of 64 possible
+* users.
*/
-#define I915_VMA_PIN_MASK 0xf
-#define I915_VMA_PIN_OVERFLOW BIT(5)
+#define I915_VMA_PIN_MASK 0xff
+#define I915_VMA_PIN_OVERFLOW BIT(8)
[Intel-gfx] [PATCH 07/23] drm/i915: Pull VM lists under the VM mutex.
A starting point to counter the pervasive struct_mutex. For the goal of
avoiding (or at least blocking under them!) global locks during user
request submission, a simple but important step is being able to manage
each clients GTT separately. For which, we want to replace using the
struct_mutex as the guard for all things GTT/VM and switch instead to a
specific mutex inside i915_address_space.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 14 --
drivers/gpu/drm/i915/i915_gem_evict.c | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c| 4
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 ++
drivers/gpu/drm/i915/i915_vma.c | 11 +++
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
8 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f45186ddb236..538fa5404603 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -245,18 +245,19 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
+ mutex_lock(&ggtt->vm.mutex);
+
pinned = ggtt->vm.reserved;
- mutex_lock(&dev->struct_mutex);
list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
- mutex_unlock(&dev->struct_mutex);
+
+ mutex_unlock(&ggtt->vm.mutex);
args->aper_size = ggtt->vm.total;
args->aper_available_size = args->aper_size - pinned;
@@ -1529,20 +1530,21 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void
*data,
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct list_head *list;
struct i915_vma *vma;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ mutex_lock(&i915->ggtt.vm.mutex);
for_each_ggtt_vma(vma, obj) {
if (!drm_mm_node_allocated(&vma->node))
continue;
list_move_tail(&vma->vm_link, &vma->vm->bound_list);
}
+ mutex_unlock(&i915->ggtt.vm.mutex);
- i915 = to_i915(obj->base.dev);
spin_lock(&i915->mm.obj_lock);
list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
list_move_tail(&obj->mm.link, list);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 5cfe4b75e7d6..dc137701acb8 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -432,6 +432,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
}
INIT_LIST_HEAD(&eviction_list);
+ mutex_lock(&vm->mutex);
list_for_each_entry(vma, &vm->bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
@@ -439,6 +440,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
__i915_vma_pin(vma);
list_add(&vma->evict_link, &eviction_list);
}
+ mutex_unlock(&vm->mutex);
ret = 0;
list_for_each_entry_safe(vma, next, &eviction_list, evict_link) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2ad9070a54c1..49b00996a15e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1931,7 +1931,10 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
INIT_LIST_HEAD(&vma->obj_link);
+
+ mutex_lock(&vma->vm->mutex);
list_add(&vma->vm_link, &vma->vm->unbound_list);
+ mutex_unlock(&vma->vm->mutex);
return vma;
}
@@ -3504,9 +3507,10 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
i915_check_and_clear_faults(dev_priv);
+ mutex_lock(&ggtt->vm.mutex);
+
/* First fill our portion of the GTT with scratch pages */
ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
-
ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */
/* clflush objects bound into the GGTT and rebind them. */
@@ -3516,19 +3520,26 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
if (!(vma->flags & I915_VMA_GLOBAL_BIND))
continue
[Intel-gfx] [PATCH 05/23] drm/i915: Issue engine resets onto idle engines
Always perform the requested reset, even if we believe the engine is
idle. Presumably there was a reason the caller wanted the reset, and in
the near future we lose the easy tracking for whether the engine is
idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 4
.../gpu/drm/i915/selftests/intel_hangcheck.c | 22 +--
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 064fc6da1512..d44b095e2860 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -1063,10 +1063,6 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
- if (i915_seqno_passed(intel_engine_get_seqno(engine),
- intel_engine_last_submit(engine)))
- return 0;
-
reset_prepare_engine(engine);
if (msg)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 28144fd72550..9d0cc9d63a1e 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -449,8 +449,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
-
if (active) {
struct i915_request *rq;
@@ -479,8 +477,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
i915_request_put(rq);
}
@@ -496,11 +492,10 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- reset_engine_count += active;
if (i915_reset_engine_count(&i915->gpu_error, engine) !=
- reset_engine_count) {
- pr_err("%s engine reset %srecorded!\n",
- engine->name, active ? "not " : "");
+ ++reset_engine_count) {
+ pr_err("%s engine reset not recorded!\n",
+ engine->name);
err = -EINVAL;
break;
}
@@ -728,7 +723,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
struct i915_request *rq = NULL;
if (flags & TEST_ACTIVE) {
@@ -756,9 +750,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
err = -EIO;
break;
}
-
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
}
err = i915_reset_engine(engine, NULL);
@@ -795,10 +786,9 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
reported = i915_reset_engine_count(&i915->gpu_error, engine);
reported -= threads[engine->id].resets;
- if (reported != (flags & TEST_ACTIVE ? count : 0)) {
- pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu, expected %lu reported\n",
- engine->name, test_name, count, reported,
- (flags & TEST_ACTIVE ? count : 0));
+ if (reported != count) {
+ pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu\n",
+ engine->name, test_name, count, reported);
if (!err)
err = -EINVAL;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/23] drm/i915/selftests: Make evict tolerant of foreign objects
The evict selftests presumed that all objects in use had been allocated
by itself. This is a dubious claim and so instead of asserting complete
control over the object lists, take (temporary) ownership of them
instead.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_evict.c | 64 +++
1 file changed, 53 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index fb7df895afeb..c8deb961a020 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -31,30 +31,63 @@
static int populate_ggtt(struct drm_i915_private *i915)
{
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj, *on;
+ unsigned long expected_unbound, expected_bound;
+ unsigned long unbound, bound, count;
u64 size;
+ int err;
+
+ expected_unbound = 0;
+ list_for_each_entry(obj, &i915->mm.unbound_list, mm.link) {
+ i915_gem_object_get(obj);
+ expected_unbound++;
+ }
+
+ expected_bound = 0;
+ list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
+ i915_gem_object_get(obj);
+ expected_bound++;
+ }
+ count = 0;
for (size = 0;
size + I915_GTT_PAGE_SIZE <= i915->ggtt.vm.total;
size += I915_GTT_PAGE_SIZE) {
struct i915_vma *vma;
obj = i915_gem_object_create_internal(i915, I915_GTT_PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto cleanup;
+ }
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto cleanup;
+ }
+
+ count++;
}
- if (!list_empty(&i915->mm.unbound_list)) {
- size = 0;
- list_for_each_entry(obj, &i915->mm.unbound_list, mm.link)
- size++;
+ unbound = 0;
+ list_for_each_entry(obj, &i915->mm.unbound_list, mm.link)
+ unbound++;
+ if (unbound != expected_unbound) {
+ pr_err("%s: Found %lu objects unbound, expected %lu!\n",
+ __func__, unbound, expected_unbound);
+ err = -EINVAL;
+ goto cleanup;
+ }
- pr_err("Found %lld objects unbound!\n", size);
- return -EINVAL;
+ bound = 0;
+ list_for_each_entry(obj, &i915->mm.bound_list, mm.link)
+ bound++;
+ if (bound != expected_bound + count) {
+ pr_err("%s: Found %lu objects bound, expected %lu!\n",
+ __func__, bound, expected_bound + count);
+ err = -EINVAL;
+ goto cleanup;
}
if (list_empty(&i915->ggtt.vm.bound_list)) {
@@ -63,6 +96,15 @@ static int populate_ggtt(struct drm_i915_private *i915)
}
return 0;
+
+cleanup:
+ list_for_each_entry_safe(obj, on, &i915->mm.unbound_list, mm.link)
+ i915_gem_object_put(obj);
+
+ list_for_each_entry_safe(obj, on, &i915->mm.bound_list, mm.link)
+ i915_gem_object_put(obj);
+
+ return err;
}
static void unpin_ggtt(struct drm_i915_private *i915)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/23] drm/i915: Use b->irq_enable() as predicate for mock engine
Since commit d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
we have required a mechanism to avoid touching the interrupt hardware
for breadcrumbs, superseding our mock interface for selftests.
References: d4ccceb05591 ("drm/i915/icl: Ringbuffer interrupt handling")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 39
drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 -
4 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4ed7105d7ff5..7b517bf83507 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -158,6 +158,9 @@ static void intel_breadcrumbs_fake_irq(struct timer_list *t)
static void irq_enable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_enable)
+ return;
+
/*
* FIXME: Ideally we want this on the API boundary, but for the
* sake of testing with mock breadcrumbs (no HW so unable to
@@ -167,21 +170,20 @@ static void irq_enable(struct intel_engine_cs *engine)
GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
/* Caller disables interrupts */
- if (engine->irq_enable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_enable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_enable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
static void irq_disable(struct intel_engine_cs *engine)
{
+ if (!engine->irq_disable)
+ return;
+
/* Caller disables interrupts */
- if (engine->irq_disable) {
- spin_lock(&engine->i915->irq_lock);
- engine->irq_disable(engine);
- spin_unlock(&engine->i915->irq_lock);
- }
+ spin_lock(&engine->i915->irq_lock);
+ engine->irq_disable(engine);
+ spin_unlock(&engine->i915->irq_lock);
}
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
@@ -293,25 +295,16 @@ static bool __intel_breadcrumbs_enable_irq(struct
intel_breadcrumbs *b)
if (b->irq_armed)
return false;
- /* The breadcrumb irq will be disarmed on the interrupt after the
+ /*
+* The breadcrumb irq will be disarmed on the interrupt after the
* waiters are signaled. This gives us a single interrupt window in
* which we can add a new waiter and avoid the cost of re-enabling
* the irq.
*/
b->irq_armed = true;
- if (I915_SELFTEST_ONLY(b->mock)) {
- /* For our mock objects we want to avoid interaction
-* with the real hardware (which is not set up). So
-* we simply pretend we have enabled the powerwell
-* and the irq, and leave it up to the mock
-* implementation to call intel_engine_wakeup()
-* itself when it wants to simulate a user interrupt,
-*/
- return true;
- }
-
- /* Since we are waiting on a request, the GPU should be busy
+ /*
+* Since we are waiting on a request, the GPU should be busy
* and should have its own rpm reference. This is tracked
* by i915->gt.awake, we can forgo holding our own wakref
* for the interrupt as before i915->gt.awake is released (when
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e2f65c59d6e8..fc52737751e7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -917,6 +917,9 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
intel_wakeref_t wakeref;
bool idle = true;
+ if (I915_SELFTEST_ONLY(!engine->mmio_base))
+ return true;
+
/* If the whole device is asleep, the engine must be idle */
wakeref = intel_runtime_pm_get_if_in_use(dev_priv);
if (!wakeref)
@@ -955,9 +958,6 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
if (!intel_engine_signaled(engine, intel_engine_last_submit(engine)))
return false;
- if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
- return true;
-
/* Waiting to drain ELSP? */
if (READ_ONCE(engine->execlists.active)) {
struct tasklet_struct *t = &engine->execlists.tasklet;
@@ -983,10 +983,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
return false;
/* Ring stopped? */
- if (!ring_is_idle(engine))
- return false;
-
- return true;
+ return ring_is_idle(engine);
}
bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
dif
[Intel-gfx] [PATCH 06/23] drm/i915: Stop tracking MRU activity on VMA
Our goal is to remove struct_mutex and replace it with fine grained
locking. One of the thorny issues is our eviction logic for reclaiming
space for an execbuffer (or GTT mmaping, among a few other examples).
While eviction itself is easy to move under a per-VM mutex, performing
the activity tracking is less agreeable. One solution is not to do any
MRU tracking and do a simple coarse evaluation during eviction of
active/inactive, with a loose temporal ordering of last
insertion/evaluation. That keeps all the locking constrained to when we
are manipulating the VM itself, neatly avoiding the tricky handling of
possible recursive locking during execbuf and elsewhere.
Note that discarding the MRU is unlikely to impact upon our efficiency
to reclaim VM space (where we think a LRU model is best) as our
current strategy is to use random idle replacement first before doing
a search, and over time the use of softpinned 48b per-ppGTT is growing
(thereby eliminating any need to perform any eviction searches, in
theory at least).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 10 +--
drivers/gpu/drm/i915/i915_gem_evict.c | 71 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 ++-
drivers/gpu/drm/i915/i915_gem_stolen.c| 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +--
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
10 files changed, 84 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d20b42386c3c..f45186ddb236 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -253,10 +253,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void
*data,
pinned = ggtt->vm.reserved;
mutex_lock(&dev->struct_mutex);
- list_for_each_entry(vma, &ggtt->vm.active_list, vm_link)
- if (i915_vma_is_pinned(vma))
- pinned += vma->node.size;
- list_for_each_entry(vma, &ggtt->vm.inactive_list, vm_link)
+ list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
mutex_unlock(&dev->struct_mutex);
@@ -1539,13 +1536,10 @@ static void i915_gem_object_bump_inactive_ggtt(struct
drm_i915_gem_object *obj)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
for_each_ggtt_vma(vma, obj) {
- if (i915_vma_is_active(vma))
- continue;
-
if (!drm_mm_node_allocated(&vma->node))
continue;
- list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
+ list_move_tail(&vma->vm_link, &vma->vm->bound_list);
}
i915 = to_i915(obj->base.dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index f6855401f247..5cfe4b75e7d6 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -126,14 +126,10 @@ i915_gem_evict_something(struct i915_address_space *vm,
struct drm_i915_private *dev_priv = vm->i915;
struct drm_mm_scan scan;
struct list_head eviction_list;
- struct list_head *phases[] = {
- &vm->inactive_list,
- &vm->active_list,
- NULL,
- }, **phase;
struct i915_vma *vma, *next;
struct drm_mm_node *node;
enum drm_mm_insert_mode mode;
+ struct i915_vma *active;
int ret;
lockdep_assert_held(&vm->i915->drm.struct_mutex);
@@ -169,17 +165,46 @@ i915_gem_evict_something(struct i915_address_space *vm,
*/
if (!(flags & PIN_NONBLOCK))
i915_retire_requests(dev_priv);
- else
- phases[1] = NULL;
search_again:
+ active = NULL;
INIT_LIST_HEAD(&eviction_list);
- phase = phases;
- do {
- list_for_each_entry(vma, *phase, vm_link)
- if (mark_free(&scan, vma, flags, &eviction_list))
- goto found;
- } while (*++phase);
+ list_for_each_entry_safe(vma, next, &vm->bound_list, vm_link) {
+ /*
+* We keep this list in a rough least-recently scanned order
+* of active elements (inactive elements are cheap to reap).
+* New entries are added to the end, and we move anything we
+* scan to the end. The assumption is that the working set
+* of applications is either steady state (and thanks to the
+* userspace bo cache it almost always is) or volatile and
+* frequently replaced after a
[Intel-gfx] [PATCH 04/23] drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest
Trim the struct_mutex hold and exclude the call to i915_gem_set_wedged() as a reminder that it must be callable without struct_mutex held. Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Cc: Mika Kuoppala --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 67431355cd6e..28144fd72550 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -389,16 +389,16 @@ static int igt_wedged_reset(void *arg) /* Check that we can recover a wedged device with a GPU reset */ igt_global_reset_lock(i915); - mutex_lock(&i915->drm.struct_mutex); wakeref = intel_runtime_pm_get(i915); i915_gem_set_wedged(i915); - GEM_BUG_ON(!i915_terminally_wedged(&i915->gpu_error)); + mutex_lock(&i915->drm.struct_mutex); + GEM_BUG_ON(!i915_terminally_wedged(&i915->gpu_error)); i915_reset(i915, ALL_ENGINES, NULL); + mutex_unlock(&i915->drm.struct_mutex); intel_runtime_pm_put(i915, wakeref); - mutex_unlock(&i915->drm.struct_mutex); igt_global_reset_unlock(i915); return i915_terminally_wedged(&i915->gpu_error) ? -EIO : 0; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/23] drm/i915/selftests: Allocate mock ring/timeline per context
To correctly simulate preemption between contexts, we need independent
timelines along each context. Make it so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/mock_engine.c | 90 ++--
1 file changed, 47 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c
b/drivers/gpu/drm/i915/selftests/mock_engine.c
index 9fe5b2c8f8d4..8b8d51af7d6a 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -30,6 +30,36 @@ struct mock_ring {
struct i915_timeline timeline;
};
+static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
+{
+ const unsigned long sz = PAGE_SIZE / 2;
+ struct mock_ring *ring;
+
+ ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL);
+ if (!ring)
+ return NULL;
+
+ i915_timeline_init(engine->i915, &ring->timeline, engine->name);
+
+ ring->base.size = sz;
+ ring->base.effective_size = sz;
+ ring->base.vaddr = (void *)(ring + 1);
+ ring->base.timeline = &ring->timeline;
+
+ INIT_LIST_HEAD(&ring->base.request_list);
+ intel_ring_update_space(&ring->base);
+
+ return &ring->base;
+}
+
+static void mock_ring_free(struct intel_ring *base)
+{
+ struct mock_ring *ring = container_of(base, typeof(*ring), base);
+
+ i915_timeline_fini(&ring->timeline);
+ kfree(ring);
+}
+
static struct mock_request *first_request(struct mock_engine *engine)
{
return list_first_entry_or_null(&engine->hw_queue,
@@ -80,6 +110,9 @@ static void mock_context_unpin(struct intel_context *ce)
static void mock_context_destroy(struct intel_context *ce)
{
GEM_BUG_ON(ce->pin_count);
+
+ if (ce->ring)
+ mock_ring_free(ce->ring);
}
static const struct intel_context_ops mock_context_ops = {
@@ -93,13 +126,22 @@ mock_context_pin(struct intel_engine_cs *engine,
{
struct intel_context *ce = to_intel_context(ctx, engine);
- if (!ce->pin_count++) {
- i915_gem_context_get(ctx);
- ce->ring = engine->buffer;
- ce->ops = &mock_context_ops;
+ if (ce->pin_count++)
+ return ce;
+
+ if (!ce->ring) {
+ ce->ring = mock_ring(engine);
+ if (!ce->ring)
+ goto err;
}
+ ce->ops = &mock_context_ops;
+ i915_gem_context_get(ctx);
return ce;
+
+err:
+ ce->pin_count = 0;
+ return ERR_PTR(-ENOMEM);
}
static int mock_request_alloc(struct i915_request *request)
@@ -143,36 +185,6 @@ static void mock_submit_request(struct i915_request
*request)
spin_unlock_irq(&engine->hw_lock);
}
-static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
-{
- const unsigned long sz = PAGE_SIZE / 2;
- struct mock_ring *ring;
-
- ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL);
- if (!ring)
- return NULL;
-
- i915_timeline_init(engine->i915, &ring->timeline, engine->name);
-
- ring->base.size = sz;
- ring->base.effective_size = sz;
- ring->base.vaddr = (void *)(ring + 1);
- ring->base.timeline = &ring->timeline;
-
- INIT_LIST_HEAD(&ring->base.request_list);
- intel_ring_update_space(&ring->base);
-
- return &ring->base;
-}
-
-static void mock_ring_free(struct intel_ring *base)
-{
- struct mock_ring *ring = container_of(base, typeof(*ring), base);
-
- i915_timeline_fini(&ring->timeline);
- kfree(ring);
-}
-
struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
const char *name,
int id)
@@ -207,17 +219,11 @@ struct intel_engine_cs *mock_engine(struct
drm_i915_private *i915,
timer_setup(&engine->hw_delay, hw_delay_complete, 0);
INIT_LIST_HEAD(&engine->hw_queue);
- engine->base.buffer = mock_ring(&engine->base);
- if (!engine->base.buffer)
- goto err_breadcrumbs;
-
if (IS_ERR(intel_context_pin(i915->kernel_context, &engine->base)))
- goto err_ring;
+ goto err_breadcrumbs;
return &engine->base;
-err_ring:
- mock_ring_free(engine->base.buffer);
err_breadcrumbs:
intel_engine_fini_breadcrumbs(&engine->base);
i915_timeline_fini(&engine->base.timeline);
@@ -260,8 +266,6 @@ void mock_engine_free(struct intel_engine_cs *engine)
__intel_context_unpin(engine->i915->kernel_context, engine);
- mock_ring_free(engine->buffer);
-
intel_engine_fini_breadcrumbs(engine);
i915_timeline_fini(&engine->timeline);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/23] drm/i915: Keep all partially allocated HWSP on a freelist
Keep track of partially allocated pages for use in allocating future
timeline HWSP. This is still without migration, so it is possible for
the system to end up with each timeline in its own page, but we ensure
that no new allocation would needless allocate a fresh page!
Signed-off-by: Chris Wilson
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_timeline.c | 81 +---
2 files changed, 50 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d59228dabb6e..0bebef428f1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1981,8 +1981,7 @@ struct drm_i915_private {
/* Pack multiple timelines' seqnos into the same page */
spinlock_t hwsp_lock;
- struct i915_vma *hwsp;
- u64 bitmap;
+ struct list_head hwsp;
} timelines;
struct list_head active_rings;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index e939a9e1a4ab..64bb1ce24318 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,74 +9,94 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
+struct i915_timeline_hwsp {
+ struct list_head link;
+ struct i915_vma *vma;
+ u64 bitmap;
+};
+
static int hwsp_alloc(struct i915_timeline *timeline)
{
-#define NBITS BITS_PER_TYPE(typeof(gt->bitmap))
struct drm_i915_private *i915 = timeline->i915;
struct i915_gt_timelines *gt = &i915->gt.timelines;
- struct i915_vma *vma;
+ struct i915_timeline_hwsp *hwsp;
int offset;
spin_lock(>->hwsp_lock);
-restart:
- offset = find_first_bit((unsigned long *)>->bitmap, NBITS);
- if (offset == NBITS && gt->hwsp) {
- i915_vma_put(gt->hwsp);
- gt->hwsp = NULL;
- }
-
- vma = gt->hwsp;
- if (!vma) {
+ hwsp = list_first_entry_or_null(>->hwsp, typeof(*hwsp), link);
+ if (!hwsp) {
struct drm_i915_gem_object *bo;
+ struct i915_vma *vma;
spin_unlock(>->hwsp_lock);
- BUILD_BUG_ON(NBITS * CACHELINE_BYTES > PAGE_SIZE);
+ hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
+ if (!hwsp)
+ return -ENOMEM;
+
+ BUILD_BUG_ON(BITS_PER_TYPE(hwsp->bitmap) * CACHELINE_BYTES >
PAGE_SIZE);
bo = i915_gem_object_create_internal(i915, PAGE_SIZE);
- if (IS_ERR(bo))
+ if (IS_ERR(bo)) {
+ kfree(hwsp);
return PTR_ERR(bo);
+ }
i915_gem_object_set_cache_level(bo, I915_CACHE_LLC);
vma = i915_vma_instance(bo, &i915->ggtt.vm, NULL);
if (IS_ERR(vma)) {
i915_gem_object_put(bo);
+ kfree(hwsp);
return PTR_ERR(vma);
}
- spin_lock(>->hwsp_lock);
- if (gt->hwsp) {
- i915_gem_object_put(bo);
- goto restart;
- }
+ vma->private = hwsp;
+ hwsp->vma = vma;
+ hwsp->bitmap = ~0ull;
- gt->hwsp = vma;
- gt->bitmap = ~0ull;
- offset = 0;
+ spin_lock(>->hwsp_lock);
+ list_add(&hwsp->link, >->hwsp);
}
- gt->bitmap &= ~BIT_ULL(offset);
+ GEM_BUG_ON(!hwsp->bitmap);
+ offset = __ffs64(hwsp->bitmap);
+ hwsp->bitmap &= ~BIT_ULL(offset);
+ if (!hwsp->bitmap)
+ list_del(&hwsp->link);
spin_unlock(>->hwsp_lock);
- timeline->hwsp_ggtt = i915_vma_get(vma);
+ timeline->hwsp_ggtt = i915_vma_get(hwsp->vma);
timeline->hwsp_offset = offset * CACHELINE_BYTES;
+ GEM_BUG_ON(timeline->hwsp_ggtt->private != hwsp);
+
return 0;
-#undef NBITS
}
static void hwsp_free(struct i915_timeline *timeline)
{
struct i915_gt_timelines *gt = &timeline->i915->gt.timelines;
+ struct i915_timeline_hwsp *hwsp;
- if (timeline->hwsp_ggtt != gt->hwsp)
+ hwsp = timeline->hwsp_ggtt->private;
+ if (!hwsp)
return;
spin_lock(>->hwsp_lock);
- if (timeline->hwsp_ggtt == gt->hwsp)
- gt->bitmap |= BIT_ULL(timeline->hwsp_offset / CACHELINE_BYTES);
+
+ if (!hwsp->bitmap)
+ list_add_tail(&hwsp->link, >->hwsp);
+
+ hwsp->bitmap |= BIT_ULL(timeline->hwsp_offset / CACHELINE_BYTES);
+
+ if (hwsp->bitmap == ~0ull) {
+ i915_vma_put(hwsp->vma);
+ list_del(&hwsp->link);
+ kfree(hwsp);
+ }
+
spin_unlock(>->hwsp_lock);
}
@@ -148,6 +168
[Intel-gfx] [PATCH 12/23] drm/i915: Always allocate an object/vma for the HWSP
Currently we only allocate an object and vma if we are using a GGTT
virtual HWSP, and a plain struct page for a physical HWSP. For
convenience later on with global timelines, it will be useful to always
have the status page being tracked by a struct i915_vma. Make it so.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_engine_cs.c | 109 ++-
drivers/gpu/drm/i915/intel_guc_submission.c | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 11 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +---
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
6 files changed, 90 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index fc52737751e7..4b4b7358c482 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -506,27 +506,61 @@ void intel_engine_setup_common(struct intel_engine_cs
*engine)
static void cleanup_status_page(struct intel_engine_cs *engine)
{
+ struct i915_vma *vma;
+
/* Prevent writes into HWSP after returning the page to the system */
intel_engine_set_hwsp_writemask(engine, ~0u);
- if (HWS_NEEDS_PHYSICAL(engine->i915)) {
- void *addr = fetch_and_zero(&engine->status_page.page_addr);
+ vma = fetch_and_zero(&engine->status_page.vma);
+ if (!vma)
+ return;
- __free_page(virt_to_page(addr));
- }
+ if (!HWS_NEEDS_PHYSICAL(engine->i915))
+ i915_vma_unpin(vma);
+
+ i915_gem_object_unpin_map(vma->obj);
+ __i915_gem_object_release_unless_active(vma->obj);
+}
+
+static int pin_ggtt_status_page(struct intel_engine_cs *engine,
+ struct i915_vma *vma)
+{
+ unsigned int flags;
+
+ flags = PIN_GLOBAL;
+ if (!HAS_LLC(engine->i915))
+ /*
+* On g33, we cannot place HWS above 256MiB, so
+* restrict its pinning to the low mappable arena.
+* Though this restriction is not documented for
+* gen4, gen5, or byt, they also behave similarly
+* and hang if the HWS is placed at the top of the
+* GTT. To generalise, it appears that all !llc
+* platforms have issues with us placing the HWS
+* above the mappable region (even though we never
+* actually map it).
+*/
+ flags |= PIN_MAPPABLE;
+ else
+ flags |= PIN_HIGH;
- i915_vma_unpin_and_release(&engine->status_page.vma,
- I915_VMA_RELEASE_MAP);
+ return i915_vma_pin(vma, 0, 0, flags);
}
static int init_status_page(struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- unsigned int flags;
void *vaddr;
int ret;
+ /*
+* Though the HWS register does support 36bit addresses, historically
+* we have had hangs and corruption reported due to wild writes if
+* the HWS is placed above 4G. We only allow objects to be allocated
+* in GFP_DMA32 for i965, and no earlier physical address users had
+* access to more than 4G.
+*/
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate status page\n");
@@ -543,61 +577,30 @@ static int init_status_page(struct intel_engine_cs
*engine)
goto err;
}
- flags = PIN_GLOBAL;
- if (!HAS_LLC(engine->i915))
- /* On g33, we cannot place HWS above 256MiB, so
-* restrict its pinning to the low mappable arena.
-* Though this restriction is not documented for
-* gen4, gen5, or byt, they also behave similarly
-* and hang if the HWS is placed at the top of the
-* GTT. To generalise, it appears that all !llc
-* platforms have issues with us placing the HWS
-* above the mappable region (even though we never
-* actually map it).
-*/
- flags |= PIN_MAPPABLE;
- else
- flags |= PIN_HIGH;
- ret = i915_vma_pin(vma, 0, 0, flags);
- if (ret)
- goto err;
-
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- goto err_unpin;
+ goto err;
}
+ engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine->status_page.vma = vma;
- engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
- engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
+
+ if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
+
[Intel-gfx] [PATCH 22/23] drm/i915: Replace global breadcrumbs with per-context interrupt tracking
A few years ago, see commit 688e6c725816 ("drm/i915: Slaughter the
thundering i915_wait_request herd"), the issue of handling multiple
clients waiting in parallel was brought to our attention. The
requirement was that every client should be woken immediately upon its
request being signaled, without incurring any cpu overhead.
To handle certain fragility of our hw meant that we could not do a
simple check inside the irq handler (some generations required almost
unbounded delays before we could be sure of seqno coherency) and so
request completion checking required delegation.
Before commit 688e6c725816, the solution was simple. Every client waking
on a request would be woken on every interrupt and each would do a
heavyweight check to see if their request was complete. Commit
688e6c725816 introduced an rbtree so that only the earliest waiter on
the global timeline would woken, and would wake the next and so on.
(Along with various complications to handle requests being reordered
along the global timeline, and also a requirement for kthread to provide
a delegate for fence signaling that had no process context.)
The global rbtree depends on knowing the execution timeline (and global
seqno). Without knowing that order, we must instead check all contexts
queued to the HW to see which may have advanced. We trim that list by
only checking queued contexts that are being waited on, but still we
keep a list of all active contexts and their active signalers that we
inspect from inside the irq handler. By moving the waiters onto the fence
signal list, we can combine the client wakeup with the dma_fence
signaling (a dramatic reduction in complexity, but does require the HW
being coherent, the seqno must be visible from the cpu before the
interrupt is raised - we keep a timer backup just in case).
Having previously fixed all the issues with irq-seqno serialisation (by
inserting delays onto the GPU after each request instead of random delays
on the CPU after each interrupt), we can rely on the seqno state to
perfom direct wakeups from the interrupt handler. This allows us to
preserve our single context switch behaviour of the current routine,
with the only downside that we lose the RT priority sorting of wakeups.
In general, direct wakeup latency of multiple clients is about the same
(about 10% better in most cases) with a reduction in total CPU time spent
in the waiter (about 20-50% depending on gen). Average herd behaviour is
improved, but at the cost of not delegating wakeups on task_prio.
References: 688e6c725816 ("drm/i915: Slaughter the thundering i915_wait_request
herd")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/i915_gem_context.h | 2 +
drivers/gpu/drm/i915/i915_gpu_error.c | 73 --
drivers/gpu/drm/i915/i915_gpu_error.h | 8 -
drivers/gpu/drm/i915/i915_irq.c | 88 +-
drivers/gpu/drm/i915/i915_request.c | 128 +--
drivers/gpu/drm/i915/i915_request.h | 22 +-
drivers/gpu/drm/i915/i915_reset.c | 13 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 809 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 34 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 95 +-
.../drm/i915/selftests/i915_mock_selftests.h | 1 -
drivers/gpu/drm/i915/selftests/i915_request.c | 398 +
drivers/gpu/drm/i915/selftests/igt_spinner.c | 5 -
.../drm/i915/selftests/intel_breadcrumbs.c| 470 --
.../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/selftests/lib_sw_fence.c | 54 ++
drivers/gpu/drm/i915/selftests/lib_sw_fence.h | 3 +
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +
drivers/gpu/drm/i915/selftests/mock_engine.c | 26 +-
drivers/gpu/drm/i915/selftests/mock_engine.h | 6 -
23 files changed, 782 insertions(+), 1493 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d052329c2319..a8830d7d1617 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1315,29 +1315,16 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
for_each_engine(engine, dev_priv, id) {
- struct intel_breadcrumbs *b = &engine->breadcrumbs;
- struct rb_node *rb;
-
seq_printf(m, "%s:\n", engine->name);
seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
engine->hangcheck.seqno, seqno[id],
intel_engine_last_submit(engine));
- seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s,
wedged? %s\n",
- yesno(intel_
[Intel-gfx] [PATCH 23/23] drm/i915: Drop fake breadcrumb irq
Missed breadcrumb detection is defunct due to the tight coupling with
dma_fence signaling and the myriad ways we may signal fences from
everywhere but from an interrupt, i.e. we frequently signal a fence
before we even see its interrupt. This means that even if we miss an
interrupt for a fence, it still is signaled before our breadcrumb
hangcheck fires, so simplify the breadcrumb hangchecking by moving it
into the GPU hangcheck and forgo fake interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 94 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 2 -
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
drivers/gpu/drm/i915/intel_breadcrumbs.c | 147 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 7 -
drivers/gpu/drm/i915/selftests/i915_request.c | 7 -
8 files changed, 6 insertions(+), 263 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a8830d7d1617..3c89ab5ea480 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1319,9 +1319,7 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
engine->hangcheck.seqno, seqno[id],
intel_engine_last_submit(engine));
- seq_printf(m, "\tfake irq active? %s, stalled? %s, wedged?
%s\n",
- yesno(test_bit(engine->id,
-
&dev_priv->gpu_error.missed_irq_rings)),
+ seq_printf(m, "\tstalled? %s, wedged? %s\n",
yesno(engine->hangcheck.stalled),
yesno(engine->hangcheck.wedged));
@@ -3886,94 +3884,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
-static int
-fault_irq_set(struct drm_i915_private *i915,
- unsigned long *irq,
- unsigned long val)
-{
- int err;
-
- err = mutex_lock_interruptible(&i915->drm.struct_mutex);
- if (err)
- return err;
-
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED |
-I915_WAIT_INTERRUPTIBLE,
-MAX_SCHEDULE_TIMEOUT);
- if (err)
- goto err_unlock;
-
- *irq = val;
- mutex_unlock(&i915->drm.struct_mutex);
-
- /* Flush idle worker to disarm irq */
- drain_delayed_work(&i915->gt.idle_work);
-
- return 0;
-
-err_unlock:
- mutex_unlock(&i915->drm.struct_mutex);
- return err;
-}
-
-static int
-i915_ring_missed_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.missed_irq_rings;
- return 0;
-}
-
-static int
-i915_ring_missed_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
- i915_ring_missed_irq_get, i915_ring_missed_irq_set,
- "0x%08llx\n");
-
-static int
-i915_ring_test_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.test_irq_rings;
-
- return 0;
-}
-
-static int
-i915_ring_test_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* GuC keeps the user interrupt permanently enabled for submission */
- if (USES_GUC_SUBMISSION(i915))
- return -ENODEV;
-
- /*
-* From icl, we can no longer individually mask interrupt generation
-* from each engine.
-*/
- if (INTEL_GEN(i915) >= 11)
- return -ENODEV;
-
- val &= INTEL_INFO(i915)->ring_mask;
- DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
-
- return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
- i915_ring_test_irq_get, i915_ring_test_irq_set,
- "0x%08llx\n");
-
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4735,8 +4645,6 @@ static const struct i915_debugfs_files {
} i915_debugfs_files[] = {
{"i915_wedged", &i915_wedged_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
- {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
- {"i915_ring_test_irq", &i915_ring_test_irq_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
{"i915_error_state", &i915_error_state_fops},
[Intel-gfx] [PATCH 20/23] drm/i915: Identify active requests
To allow requests to forgo a common execution timeline, one question we
need to be able to answer is "is this request running?". To track
whether a request has started on HW, we can emit a breadcrumb at the
beginning of the request and check its timeline's HWSP to see if the
breadcrumb has advanced past the start of this request. (This is in
contrast to the global timeline where we need only ask if we are on the
global timeline and if the timeline has advanced past the end of the
previous request.)
There is still confusion from a preempted request, which has already
started but relinquished the HW to a high priority request. For the
common case, this discrepancy should be negligible. However, for
identification of hung requests, knowing which one was running at the
time of the hang will be much more important.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_timeline.c| 1 +
drivers/gpu/drm/i915/i915_timeline.h| 2 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +++-
drivers/gpu/drm/i915/intel_lrc.c| 23 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
7 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 0d7b71aff28f..f61cc5c1bf08 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -332,6 +332,7 @@ void i915_request_retire_upto(struct i915_request *rq)
static u32 timeline_get_seqno(struct i915_timeline *tl)
{
+ tl->seqno += tl->has_initial_breadcrumb;
return ++tl->seqno;
}
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index a16a3b7f7d92..83ce982dcbd9 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -324,6 +324,7 @@ static inline u32 hwsp_seqno(const struct i915_request *rq)
*/
static inline bool i915_request_started(const struct i915_request *rq)
{
+ /* Remember: started but may have since been preempted! */
return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
}
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 64bb1ce24318..e4c78ea8c73c 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -120,6 +120,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->i915 = i915;
timeline->name = name;
timeline->pin_count = 0;
+ timeline->has_initial_breadcrumb = !global_hwsp;
if (global_hwsp) {
timeline->hwsp_ggtt = i915_vma_get(global_hwsp);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 0c3739d53d79..421eb34568de 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -47,6 +47,8 @@ struct i915_timeline {
struct i915_vma *hwsp_ggtt;
u32 hwsp_offset;
+ bool has_initial_breadcrumb;
+
/**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index c850d131d8c3..ae455b874c9f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1239,7 +1239,9 @@ static void print_request(struct drm_printer *m,
drm_printf(m, "%s%x%s [%llx:%llx]%s @ %dms: %s\n",
prefix,
rq->global_seqno,
- i915_request_completed(rq) ? "!" : "",
+ i915_request_completed(rq) ? "!" :
+ i915_request_started(rq) ? "*" :
+ "",
rq->fence.context, rq->fence.seqno,
buf,
jiffies_to_msecs(jiffies - rq->emitted_jiffies),
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 593928dd6bbe..87b334a29836 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1263,6 +1263,25 @@ execlists_context_pin(struct intel_engine_cs *engine,
return __execlists_context_pin(engine, ctx, ce);
}
+static int emit_initial_breadcrumb(struct i915_request *rq)
+{
+ u32 *cs;
+
+ GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb);
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = i915_timeline_seqno_address(rq->timeline);
+ *cs++ = 0;
+ *cs++ = rq->fence.seqno - 1;
+
+ intel_ring_advance(rq, cs);
+ return 0;
+}
+
static int emit_pdps(struct i915_request *rq)
{
const struct intel_engine_cs * const engine = rq->engine;
@@ -1337,6 +1356,10 @@ static int execlists_request_alloc(struct i915_request
*request)
*
[Intel-gfx] [PATCH 21/23] drm/i915: Remove the intel_engine_notify tracepoint
The global seqno is defunct and so we have no meaningful indicator of
forward progress for an engine. You need to listen to the request
signaling tracepoints instead.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 2 --
drivers/gpu/drm/i915/i915_trace.h | 25 -
2 files changed, 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1abfc3fa76ad..8da5816e2854 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1210,8 +1210,6 @@ static void notify_ring(struct intel_engine_cs *engine)
wake_up_process(tsk);
rcu_read_unlock();
-
- trace_intel_engine_notify(engine, wait);
}
static void vlv_c0_read(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 33d90eca9cdd..cb5bc65d575d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -750,31 +750,6 @@ trace_i915_request_out(struct i915_request *rq)
#endif
#endif
-TRACE_EVENT(intel_engine_notify,
- TP_PROTO(struct intel_engine_cs *engine, bool waiters),
- TP_ARGS(engine, waiters),
-
- TP_STRUCT__entry(
-__field(u32, dev)
-__field(u16, class)
-__field(u16, instance)
-__field(u32, seqno)
-__field(bool, waiters)
-),
-
- TP_fast_assign(
- __entry->dev = engine->i915->drm.primary->index;
- __entry->class = engine->uabi_class;
- __entry->instance = engine->instance;
- __entry->seqno = intel_engine_get_seqno(engine);
- __entry->waiters = waiters;
- ),
-
- TP_printk("dev=%u, engine=%u:%u, seqno=%u, waiters=%u",
- __entry->dev, __entry->class, __entry->instance,
- __entry->seqno, __entry->waiters)
-);
-
DEFINE_EVENT(i915_request, i915_request_retire,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Swapping a single global interrupt handler for a herd
___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/23] drm/i915: Introduce concept of per-timeline (context) HWSP
Supplement the per-engine HWSP with a per-timeline HWSP. That is a
per-request pointer through which we can check a local seqno,
abstracting away the presumption of a global seqno. In this first step,
we point each request back into the engine's HWSP so everything
continues to work with the global timeline.
v2: s/i915_request_hwsp/hwsp_seqno/ to emphasis that this is the current
HW value and that we are accessing it via i915_request merely as a
convenience.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 16 +-
drivers/gpu/drm/i915/i915_request.h | 34 +++--
drivers/gpu/drm/i915/intel_lrc.c| 9 +---
3 files changed, 44 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index fb723ed2f574..7d068c406a49 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -182,10 +182,11 @@ static void free_capture_list(struct i915_request
*request)
static void __retire_engine_request(struct intel_engine_cs *engine,
struct i915_request *rq)
{
- GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d:%d\n",
__func__, engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!i915_request_completed(rq));
@@ -244,10 +245,11 @@ static void i915_request_retire(struct i915_request
*request)
{
struct i915_gem_active *active, *next;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
request->engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(request->engine));
lockdep_assert_held(&request->i915->drm.struct_mutex);
@@ -307,10 +309,11 @@ void i915_request_retire_upto(struct i915_request *rq)
struct intel_ring *ring = rq->ring;
struct i915_request *tmp;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
rq->engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(rq->engine));
lockdep_assert_held(&rq->i915->drm.struct_mutex);
@@ -348,10 +351,11 @@ void __i915_request_submit(struct i915_request *request)
struct intel_engine_cs *engine = request->engine;
u32 seqno;
- GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
engine->timeline.seqno + 1,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -398,10 +402,11 @@ void __i915_request_unsubmit(struct i915_request *request)
{
struct intel_engine_cs *engine = request->engine;
- GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -609,6 +614,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == &engine->timeline);
+ rq->hwsp_seqno = &engine->status_page.addr[I915_GEM_HWS_INDEX];
spin_lock_init(&rq->lock);
dma_fence_init(&rq->fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index d014b0605445..4dd22dadf5ce 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -130,6 +130,13 @@ struct i915_request {
struct i915_sched_node sched;
struct i915_dependency dep;
+ /*
+* A convenience pointer to the current breadcrumb value stored in
+* the HW status page (or our timeline's local equivalent). The full
+* path would be rq->hw_context->ring->timeline->hwsp_seqno.
+*/
+ const u32 *hwsp_seqno;
+
/**
* GEM sequence number associated with this request on the
* global execution timeline. It is zero when the request is not
@@ -280,11 +287,6 @@ long i915_request_
[Intel-gfx] [PATCH 17/23] drm/i915: Share per-timeline HWSP using a slab suballocator
If we restrict ourselves to only using a cacheline for each timeline's
HWSP (we could go smaller, but want to avoid needless polluting
cachelines on different engines between different contexts), then we can
suballocate a single 4k page into 64 different timeline HWSP. By
treating each fresh allocation as a slab of 64 entries, we can keep it
around for the next 64 allocation attempts until we need to refresh the
slab cache.
John Harrison noted the issue of fragmentation leading to the same worst
case performance of one page per timeline as before, which can be
mitigated by adopting a freelist.
Signed-off-by: Chris Wilson
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_timeline.c | 80
2 files changed, 74 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3913900600b7..d59228dabb6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1978,6 +1978,11 @@ struct drm_i915_private {
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head list;
+
+ /* Pack multiple timelines' seqnos into the same page */
+ spinlock_t hwsp_lock;
+ struct i915_vma *hwsp;
+ u64 bitmap;
} timelines;
struct list_head active_rings;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 380f4d25fb89..e939a9e1a4ab 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -11,26 +11,73 @@
static int hwsp_alloc(struct i915_timeline *timeline)
{
+#define NBITS BITS_PER_TYPE(typeof(gt->bitmap))
struct drm_i915_private *i915 = timeline->i915;
- struct drm_i915_gem_object *bo;
+ struct i915_gt_timelines *gt = &i915->gt.timelines;
struct i915_vma *vma;
+ int offset;
+
+ spin_lock(>->hwsp_lock);
+
+restart:
+ offset = find_first_bit((unsigned long *)>->bitmap, NBITS);
+ if (offset == NBITS && gt->hwsp) {
+ i915_vma_put(gt->hwsp);
+ gt->hwsp = NULL;
+ }
+
+ vma = gt->hwsp;
+ if (!vma) {
+ struct drm_i915_gem_object *bo;
+
+ spin_unlock(>->hwsp_lock);
- bo = i915_gem_object_create_internal(i915, PAGE_SIZE);
- if (IS_ERR(bo))
- return PTR_ERR(bo);
+ BUILD_BUG_ON(NBITS * CACHELINE_BYTES > PAGE_SIZE);
+ bo = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
- i915_gem_object_set_cache_level(bo, I915_CACHE_LLC);
+ i915_gem_object_set_cache_level(bo, I915_CACHE_LLC);
- vma = i915_vma_instance(bo, &i915->ggtt.vm, NULL);
- if (IS_ERR(vma)) {
- i915_gem_object_put(bo);
- return PTR_ERR(vma);
+ vma = i915_vma_instance(bo, &i915->ggtt.vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(bo);
+ return PTR_ERR(vma);
+ }
+
+ spin_lock(>->hwsp_lock);
+ if (gt->hwsp) {
+ i915_gem_object_put(bo);
+ goto restart;
+ }
+
+ gt->hwsp = vma;
+ gt->bitmap = ~0ull;
+ offset = 0;
}
- timeline->hwsp_ggtt = vma;
- timeline->hwsp_offset = 0;
+ gt->bitmap &= ~BIT_ULL(offset);
+
+ spin_unlock(>->hwsp_lock);
+
+ timeline->hwsp_ggtt = i915_vma_get(vma);
+ timeline->hwsp_offset = offset * CACHELINE_BYTES;
return 0;
+#undef NBITS
+}
+
+static void hwsp_free(struct i915_timeline *timeline)
+{
+ struct i915_gt_timelines *gt = &timeline->i915->gt.timelines;
+
+ if (timeline->hwsp_ggtt != gt->hwsp)
+ return;
+
+ spin_lock(>->hwsp_lock);
+ if (timeline->hwsp_ggtt == gt->hwsp)
+ gt->bitmap |= BIT_ULL(timeline->hwsp_offset / CACHELINE_BYTES);
+ spin_unlock(>->hwsp_lock);
}
int i915_timeline_init(struct drm_i915_private *i915,
@@ -65,6 +112,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
vaddr = i915_gem_object_pin_map(timeline->hwsp_ggtt->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
+ hwsp_free(timeline);
i915_vma_put(timeline->hwsp_ggtt);
return PTR_ERR(vaddr);
}
@@ -99,6 +147,8 @@ void i915_timelines_init(struct drm_i915_private *i915)
mutex_init(>->mutex);
INIT_LIST_HEAD(>->list);
+ spin_lock_init(>->hwsp_lock);
+
/* via i915_gem_wait_for_idle() */
i915_gem_shrinker_taints_mutex(i915, >->mutex);
}
@@ -144,6 +194,9 @@ void i915_timeline_fini(s
[Intel-gfx] [PATCH 19/23] drm/i915: Track the context's seqno in its own timeline HWSP
Now that we have allocated ourselves a cacheline to store a breadcrumb,
we can emit a write from the GPU into the timeline's HWSP of the
per-context seqno as we complete each request. This drops the mirroring
of the per-engine HWSP and allows each context to operate independently.
We do not need to unwind the per-context timeline, and so requests are
always consistent with the timeline breadcrumb, greatly simplifying the
completion checks as we no longer need to be concerned about the
global_seqno changing mid check.
At this point, we are emitting both per-context and global seqno and
still using the single per-engine execution timeline for resolving
interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_request.h | 27 ++
drivers/gpu/drm/i915/i915_reset.c| 1 +
drivers/gpu/drm/i915/i915_vma.h | 7 ++
drivers/gpu/drm/i915/intel_lrc.c | 32 ---
drivers/gpu/drm/i915/intel_ringbuffer.c | 91 ++--
drivers/gpu/drm/i915/selftests/mock_engine.c | 8 +-
8 files changed, 109 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3c6091021290..a5bd51987c0d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2890,7 +2890,7 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
*/
spin_lock_irqsave(&engine->timeline.lock, flags);
list_for_each_entry(request, &engine->timeline.requests, link) {
- if (__i915_request_completed(request, request->global_seqno))
+ if (i915_request_completed(request))
continue;
active = request;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 7d068c406a49..0d7b71aff28f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -614,7 +614,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == &engine->timeline);
- rq->hwsp_seqno = &engine->status_page.addr[I915_GEM_HWS_INDEX];
+ rq->hwsp_seqno = rq->timeline->hwsp_seqno;
spin_lock_init(&rq->lock);
dma_fence_init(&rq->fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 4dd22dadf5ce..a16a3b7f7d92 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -324,32 +324,21 @@ static inline u32 hwsp_seqno(const struct i915_request
*rq)
*/
static inline bool i915_request_started(const struct i915_request *rq)
{
- u32 seqno;
-
- seqno = i915_request_global_seqno(rq);
- if (!seqno) /* not yet submitted to HW */
- return false;
-
- return i915_seqno_passed(hwsp_seqno(rq), seqno - 1);
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
}
-static inline bool
-__i915_request_completed(const struct i915_request *rq, u32 seqno)
+static inline bool i915_request_completed(const struct i915_request *rq)
{
- GEM_BUG_ON(!seqno);
- return i915_seqno_passed(hwsp_seqno(rq), seqno) &&
- seqno == i915_request_global_seqno(rq);
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno);
}
-static inline bool i915_request_completed(const struct i915_request *rq)
+static inline void i915_request_fake_complete(const struct i915_request *rq)
{
- u32 seqno;
-
- seqno = i915_request_global_seqno(rq);
- if (!seqno)
- return false;
+ /* Don't allow ourselves to accidentally go backwards. */
+ if (i915_request_completed(rq))
+ return;
- return __i915_request_completed(rq, seqno);
+ WRITE_ONCE(*(u32 *)rq->hwsp_seqno, rq->fence.seqno);
}
void i915_retire_requests(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 12e5a2bc825c..eff76558b958 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -756,6 +756,7 @@ static void nop_submit_request(struct i915_request *request)
spin_lock_irqsave(&request->engine->timeline.lock, flags);
__i915_request_submit(request);
+ i915_request_fake_complete(request);
intel_engine_write_global_seqno(request->engine, request->global_seqno);
spin_unlock_irqrestore(&request->engine->timeline.lock, flags);
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 5793abe509a2..18be786a970d 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -221,6 +221,13 @@ static inline u32 i915_ggtt_offset(const struct i915_vma
*vma)
return lower_32
Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Disable global reset
Chris Wilson writes:
> The guc (and huc) currently inexcruitably depend on struct_mutex for
> device reinitialisation from inside the reset, and indeed taking any
> mutex here is verboten (as we must be able to reset from underneath any
> of our mutexes). That makes recovering the guc unviable without, for
> example, reserving contiguous vma space and pages for it to use.
>
> Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
We do want ack from Daniele as well.
-Mika
> ---
> drivers/gpu/drm/i915/i915_reset.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c
> b/drivers/gpu/drm/i915/i915_reset.c
> index f9512e07646d..c9a844d2626f 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -590,6 +590,9 @@ int intel_gpu_reset(struct drm_i915_private *i915,
> unsigned int engine_mask)
>
> bool intel_has_gpu_reset(struct drm_i915_private *i915)
> {
> + if (USES_GUC(i915))
> + return false;
> +
> return intel_get_gpu_reset(i915);
> }
>
> --
> 2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
